3 Broadcom B43 wireless driver
5 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
6 Copyright (c) 2005 Stefano Brivio <stefano.brivio@polimi.it>
7 Copyright (c) 2005-2009 Michael Buesch <mb@bu3sch.de>
8 Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
9 Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
11 Some parts of the code in this file are derived from the ipw2200
12 driver Copyright(c) 2003 - 2004 Intel Corporation.
14 This program is free software; you can redistribute it and/or modify
15 it under the terms of the GNU General Public License as published by
16 the Free Software Foundation; either version 2 of the License, or
17 (at your option) any later version.
19 This program is distributed in the hope that it will be useful,
20 but WITHOUT ANY WARRANTY; without even the implied warranty of
21 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 GNU General Public License for more details.
24 You should have received a copy of the GNU General Public License
25 along with this program; see the file COPYING. If not, write to
26 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
27 Boston, MA 02110-1301, USA.
31 #include <linux/delay.h>
32 #include <linux/init.h>
33 #include <linux/moduleparam.h>
34 #include <linux/if_arp.h>
35 #include <linux/etherdevice.h>
36 #include <linux/firmware.h>
37 #include <linux/wireless.h>
38 #include <linux/workqueue.h>
39 #include <linux/skbuff.h>
41 #include <linux/dma-mapping.h>
42 #include <asm/unaligned.h>
47 #include "phy_common.h"
57 MODULE_DESCRIPTION("Broadcom B43 wireless driver");
58 MODULE_AUTHOR("Martin Langer");
59 MODULE_AUTHOR("Stefano Brivio");
60 MODULE_AUTHOR("Michael Buesch");
61 MODULE_LICENSE("GPL");
63 MODULE_FIRMWARE(B43_SUPPORTED_FIRMWARE_ID);
66 static int modparam_bad_frames_preempt;
67 module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
68 MODULE_PARM_DESC(bad_frames_preempt,
69 "enable(1) / disable(0) Bad Frames Preemption");
71 static char modparam_fwpostfix[16];
72 module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444);
73 MODULE_PARM_DESC(fwpostfix, "Postfix for the .fw files to load.");
75 static int modparam_hwpctl;
76 module_param_named(hwpctl, modparam_hwpctl, int, 0444);
77 MODULE_PARM_DESC(hwpctl, "Enable hardware-side power control (default off)");
79 static int modparam_nohwcrypt;
80 module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
81 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
83 static int modparam_qos = 1;
84 module_param_named(qos, modparam_qos, int, 0444);
85 MODULE_PARM_DESC(qos, "Enable QOS support (default on)");
87 static int modparam_btcoex = 1;
88 module_param_named(btcoex, modparam_btcoex, int, 0444);
89 MODULE_PARM_DESC(btcoex, "Enable Bluetooth coexistance (default on)");
91 int b43_modparam_verbose = B43_VERBOSITY_DEFAULT;
92 module_param_named(verbose, b43_modparam_verbose, int, 0644);
93 MODULE_PARM_DESC(verbose, "Log message verbosity: 0=error, 1=warn, 2=info(default), 3=debug");
96 static const struct ssb_device_id b43_ssb_tbl[] = {
97 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 5),
98 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 6),
99 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 7),
100 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 9),
101 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 10),
102 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 11),
103 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 13),
104 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 15),
105 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 16),
109 MODULE_DEVICE_TABLE(ssb, b43_ssb_tbl);
111 /* Channel and ratetables are shared for all devices.
112 * They can't be const, because ieee80211 puts some precalculated
113 * data in there. This data is the same for all devices, so we don't
114 * get concurrency issues */
115 #define RATETAB_ENT(_rateid, _flags) \
117 .bitrate = B43_RATE_TO_BASE100KBPS(_rateid), \
118 .hw_value = (_rateid), \
123 * NOTE: When changing this, sync with xmit.c's
124 * b43_plcp_get_bitrate_idx_* functions!
126 static struct ieee80211_rate __b43_ratetable[] = {
127 RATETAB_ENT(B43_CCK_RATE_1MB, 0),
128 RATETAB_ENT(B43_CCK_RATE_2MB, IEEE80211_RATE_SHORT_PREAMBLE),
129 RATETAB_ENT(B43_CCK_RATE_5MB, IEEE80211_RATE_SHORT_PREAMBLE),
130 RATETAB_ENT(B43_CCK_RATE_11MB, IEEE80211_RATE_SHORT_PREAMBLE),
131 RATETAB_ENT(B43_OFDM_RATE_6MB, 0),
132 RATETAB_ENT(B43_OFDM_RATE_9MB, 0),
133 RATETAB_ENT(B43_OFDM_RATE_12MB, 0),
134 RATETAB_ENT(B43_OFDM_RATE_18MB, 0),
135 RATETAB_ENT(B43_OFDM_RATE_24MB, 0),
136 RATETAB_ENT(B43_OFDM_RATE_36MB, 0),
137 RATETAB_ENT(B43_OFDM_RATE_48MB, 0),
138 RATETAB_ENT(B43_OFDM_RATE_54MB, 0),
141 #define b43_a_ratetable (__b43_ratetable + 4)
142 #define b43_a_ratetable_size 8
143 #define b43_b_ratetable (__b43_ratetable + 0)
144 #define b43_b_ratetable_size 4
145 #define b43_g_ratetable (__b43_ratetable + 0)
146 #define b43_g_ratetable_size 12
148 #define CHAN4G(_channel, _freq, _flags) { \
149 .band = IEEE80211_BAND_2GHZ, \
150 .center_freq = (_freq), \
151 .hw_value = (_channel), \
153 .max_antenna_gain = 0, \
156 static struct ieee80211_channel b43_2ghz_chantable[] = {
174 #define CHAN5G(_channel, _flags) { \
175 .band = IEEE80211_BAND_5GHZ, \
176 .center_freq = 5000 + (5 * (_channel)), \
177 .hw_value = (_channel), \
179 .max_antenna_gain = 0, \
182 static struct ieee80211_channel b43_5ghz_nphy_chantable[] = {
183 CHAN5G(32, 0), CHAN5G(34, 0),
184 CHAN5G(36, 0), CHAN5G(38, 0),
185 CHAN5G(40, 0), CHAN5G(42, 0),
186 CHAN5G(44, 0), CHAN5G(46, 0),
187 CHAN5G(48, 0), CHAN5G(50, 0),
188 CHAN5G(52, 0), CHAN5G(54, 0),
189 CHAN5G(56, 0), CHAN5G(58, 0),
190 CHAN5G(60, 0), CHAN5G(62, 0),
191 CHAN5G(64, 0), CHAN5G(66, 0),
192 CHAN5G(68, 0), CHAN5G(70, 0),
193 CHAN5G(72, 0), CHAN5G(74, 0),
194 CHAN5G(76, 0), CHAN5G(78, 0),
195 CHAN5G(80, 0), CHAN5G(82, 0),
196 CHAN5G(84, 0), CHAN5G(86, 0),
197 CHAN5G(88, 0), CHAN5G(90, 0),
198 CHAN5G(92, 0), CHAN5G(94, 0),
199 CHAN5G(96, 0), CHAN5G(98, 0),
200 CHAN5G(100, 0), CHAN5G(102, 0),
201 CHAN5G(104, 0), CHAN5G(106, 0),
202 CHAN5G(108, 0), CHAN5G(110, 0),
203 CHAN5G(112, 0), CHAN5G(114, 0),
204 CHAN5G(116, 0), CHAN5G(118, 0),
205 CHAN5G(120, 0), CHAN5G(122, 0),
206 CHAN5G(124, 0), CHAN5G(126, 0),
207 CHAN5G(128, 0), CHAN5G(130, 0),
208 CHAN5G(132, 0), CHAN5G(134, 0),
209 CHAN5G(136, 0), CHAN5G(138, 0),
210 CHAN5G(140, 0), CHAN5G(142, 0),
211 CHAN5G(144, 0), CHAN5G(145, 0),
212 CHAN5G(146, 0), CHAN5G(147, 0),
213 CHAN5G(148, 0), CHAN5G(149, 0),
214 CHAN5G(150, 0), CHAN5G(151, 0),
215 CHAN5G(152, 0), CHAN5G(153, 0),
216 CHAN5G(154, 0), CHAN5G(155, 0),
217 CHAN5G(156, 0), CHAN5G(157, 0),
218 CHAN5G(158, 0), CHAN5G(159, 0),
219 CHAN5G(160, 0), CHAN5G(161, 0),
220 CHAN5G(162, 0), CHAN5G(163, 0),
221 CHAN5G(164, 0), CHAN5G(165, 0),
222 CHAN5G(166, 0), CHAN5G(168, 0),
223 CHAN5G(170, 0), CHAN5G(172, 0),
224 CHAN5G(174, 0), CHAN5G(176, 0),
225 CHAN5G(178, 0), CHAN5G(180, 0),
226 CHAN5G(182, 0), CHAN5G(184, 0),
227 CHAN5G(186, 0), CHAN5G(188, 0),
228 CHAN5G(190, 0), CHAN5G(192, 0),
229 CHAN5G(194, 0), CHAN5G(196, 0),
230 CHAN5G(198, 0), CHAN5G(200, 0),
231 CHAN5G(202, 0), CHAN5G(204, 0),
232 CHAN5G(206, 0), CHAN5G(208, 0),
233 CHAN5G(210, 0), CHAN5G(212, 0),
234 CHAN5G(214, 0), CHAN5G(216, 0),
235 CHAN5G(218, 0), CHAN5G(220, 0),
236 CHAN5G(222, 0), CHAN5G(224, 0),
237 CHAN5G(226, 0), CHAN5G(228, 0),
240 static struct ieee80211_channel b43_5ghz_aphy_chantable[] = {
241 CHAN5G(34, 0), CHAN5G(36, 0),
242 CHAN5G(38, 0), CHAN5G(40, 0),
243 CHAN5G(42, 0), CHAN5G(44, 0),
244 CHAN5G(46, 0), CHAN5G(48, 0),
245 CHAN5G(52, 0), CHAN5G(56, 0),
246 CHAN5G(60, 0), CHAN5G(64, 0),
247 CHAN5G(100, 0), CHAN5G(104, 0),
248 CHAN5G(108, 0), CHAN5G(112, 0),
249 CHAN5G(116, 0), CHAN5G(120, 0),
250 CHAN5G(124, 0), CHAN5G(128, 0),
251 CHAN5G(132, 0), CHAN5G(136, 0),
252 CHAN5G(140, 0), CHAN5G(149, 0),
253 CHAN5G(153, 0), CHAN5G(157, 0),
254 CHAN5G(161, 0), CHAN5G(165, 0),
255 CHAN5G(184, 0), CHAN5G(188, 0),
256 CHAN5G(192, 0), CHAN5G(196, 0),
257 CHAN5G(200, 0), CHAN5G(204, 0),
258 CHAN5G(208, 0), CHAN5G(212, 0),
263 static struct ieee80211_supported_band b43_band_5GHz_nphy = {
264 .band = IEEE80211_BAND_5GHZ,
265 .channels = b43_5ghz_nphy_chantable,
266 .n_channels = ARRAY_SIZE(b43_5ghz_nphy_chantable),
267 .bitrates = b43_a_ratetable,
268 .n_bitrates = b43_a_ratetable_size,
271 static struct ieee80211_supported_band b43_band_5GHz_aphy = {
272 .band = IEEE80211_BAND_5GHZ,
273 .channels = b43_5ghz_aphy_chantable,
274 .n_channels = ARRAY_SIZE(b43_5ghz_aphy_chantable),
275 .bitrates = b43_a_ratetable,
276 .n_bitrates = b43_a_ratetable_size,
279 static struct ieee80211_supported_band b43_band_2GHz = {
280 .band = IEEE80211_BAND_2GHZ,
281 .channels = b43_2ghz_chantable,
282 .n_channels = ARRAY_SIZE(b43_2ghz_chantable),
283 .bitrates = b43_g_ratetable,
284 .n_bitrates = b43_g_ratetable_size,
287 static void b43_wireless_core_exit(struct b43_wldev *dev);
288 static int b43_wireless_core_init(struct b43_wldev *dev);
289 static void b43_wireless_core_stop(struct b43_wldev *dev);
290 static int b43_wireless_core_start(struct b43_wldev *dev);
292 static int b43_ratelimit(struct b43_wl *wl)
294 if (!wl || !wl->current_dev)
296 if (b43_status(wl->current_dev) < B43_STAT_STARTED)
298 /* We are up and running.
299 * Ratelimit the messages to avoid DoS over the net. */
300 return net_ratelimit();
303 void b43info(struct b43_wl *wl, const char *fmt, ...)
307 if (b43_modparam_verbose < B43_VERBOSITY_INFO)
309 if (!b43_ratelimit(wl))
312 printk(KERN_INFO "b43-%s: ",
313 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
318 void b43err(struct b43_wl *wl, const char *fmt, ...)
322 if (b43_modparam_verbose < B43_VERBOSITY_ERROR)
324 if (!b43_ratelimit(wl))
327 printk(KERN_ERR "b43-%s ERROR: ",
328 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
333 void b43warn(struct b43_wl *wl, const char *fmt, ...)
337 if (b43_modparam_verbose < B43_VERBOSITY_WARN)
339 if (!b43_ratelimit(wl))
342 printk(KERN_WARNING "b43-%s warning: ",
343 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
348 void b43dbg(struct b43_wl *wl, const char *fmt, ...)
352 if (b43_modparam_verbose < B43_VERBOSITY_DEBUG)
355 printk(KERN_DEBUG "b43-%s debug: ",
356 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
361 static void b43_ram_write(struct b43_wldev *dev, u16 offset, u32 val)
365 B43_WARN_ON(offset % 4 != 0);
367 macctl = b43_read32(dev, B43_MMIO_MACCTL);
368 if (macctl & B43_MACCTL_BE)
371 b43_write32(dev, B43_MMIO_RAM_CONTROL, offset);
373 b43_write32(dev, B43_MMIO_RAM_DATA, val);
376 static inline void b43_shm_control_word(struct b43_wldev *dev,
377 u16 routing, u16 offset)
381 /* "offset" is the WORD offset. */
385 b43_write32(dev, B43_MMIO_SHM_CONTROL, control);
388 u32 __b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset)
392 if (routing == B43_SHM_SHARED) {
393 B43_WARN_ON(offset & 0x0001);
394 if (offset & 0x0003) {
395 /* Unaligned access */
396 b43_shm_control_word(dev, routing, offset >> 2);
397 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
399 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
400 ret |= b43_read16(dev, B43_MMIO_SHM_DATA);
406 b43_shm_control_word(dev, routing, offset);
407 ret = b43_read32(dev, B43_MMIO_SHM_DATA);
412 u32 b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset)
414 struct b43_wl *wl = dev->wl;
418 spin_lock_irqsave(&wl->shm_lock, flags);
419 ret = __b43_shm_read32(dev, routing, offset);
420 spin_unlock_irqrestore(&wl->shm_lock, flags);
425 u16 __b43_shm_read16(struct b43_wldev *dev, u16 routing, u16 offset)
429 if (routing == B43_SHM_SHARED) {
430 B43_WARN_ON(offset & 0x0001);
431 if (offset & 0x0003) {
432 /* Unaligned access */
433 b43_shm_control_word(dev, routing, offset >> 2);
434 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
440 b43_shm_control_word(dev, routing, offset);
441 ret = b43_read16(dev, B43_MMIO_SHM_DATA);
446 u16 b43_shm_read16(struct b43_wldev *dev, u16 routing, u16 offset)
448 struct b43_wl *wl = dev->wl;
452 spin_lock_irqsave(&wl->shm_lock, flags);
453 ret = __b43_shm_read16(dev, routing, offset);
454 spin_unlock_irqrestore(&wl->shm_lock, flags);
459 void __b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value)
461 if (routing == B43_SHM_SHARED) {
462 B43_WARN_ON(offset & 0x0001);
463 if (offset & 0x0003) {
464 /* Unaligned access */
465 b43_shm_control_word(dev, routing, offset >> 2);
466 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED,
467 (value >> 16) & 0xffff);
468 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
469 b43_write16(dev, B43_MMIO_SHM_DATA, value & 0xffff);
474 b43_shm_control_word(dev, routing, offset);
475 b43_write32(dev, B43_MMIO_SHM_DATA, value);
478 void b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value)
480 struct b43_wl *wl = dev->wl;
483 spin_lock_irqsave(&wl->shm_lock, flags);
484 __b43_shm_write32(dev, routing, offset, value);
485 spin_unlock_irqrestore(&wl->shm_lock, flags);
488 void __b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value)
490 if (routing == B43_SHM_SHARED) {
491 B43_WARN_ON(offset & 0x0001);
492 if (offset & 0x0003) {
493 /* Unaligned access */
494 b43_shm_control_word(dev, routing, offset >> 2);
495 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, value);
500 b43_shm_control_word(dev, routing, offset);
501 b43_write16(dev, B43_MMIO_SHM_DATA, value);
504 void b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value)
506 struct b43_wl *wl = dev->wl;
509 spin_lock_irqsave(&wl->shm_lock, flags);
510 __b43_shm_write16(dev, routing, offset, value);
511 spin_unlock_irqrestore(&wl->shm_lock, flags);
515 u64 b43_hf_read(struct b43_wldev *dev)
519 ret = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI);
521 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI);
523 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO);
528 /* Write HostFlags */
529 void b43_hf_write(struct b43_wldev *dev, u64 value)
533 lo = (value & 0x00000000FFFFULL);
534 mi = (value & 0x0000FFFF0000ULL) >> 16;
535 hi = (value & 0xFFFF00000000ULL) >> 32;
536 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO, lo);
537 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI, mi);
538 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI, hi);
541 /* Read the firmware capabilities bitmask (Opensource firmware only) */
542 static u16 b43_fwcapa_read(struct b43_wldev *dev)
544 B43_WARN_ON(!dev->fw.opensource);
545 return b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_FWCAPA);
548 void b43_tsf_read(struct b43_wldev *dev, u64 *tsf)
552 B43_WARN_ON(dev->dev->id.revision < 3);
554 /* The hardware guarantees us an atomic read, if we
555 * read the low register first. */
556 low = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_LOW);
557 high = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
564 static void b43_time_lock(struct b43_wldev *dev)
568 macctl = b43_read32(dev, B43_MMIO_MACCTL);
569 macctl |= B43_MACCTL_TBTTHOLD;
570 b43_write32(dev, B43_MMIO_MACCTL, macctl);
571 /* Commit the write */
572 b43_read32(dev, B43_MMIO_MACCTL);
575 static void b43_time_unlock(struct b43_wldev *dev)
579 macctl = b43_read32(dev, B43_MMIO_MACCTL);
580 macctl &= ~B43_MACCTL_TBTTHOLD;
581 b43_write32(dev, B43_MMIO_MACCTL, macctl);
582 /* Commit the write */
583 b43_read32(dev, B43_MMIO_MACCTL);
586 static void b43_tsf_write_locked(struct b43_wldev *dev, u64 tsf)
590 B43_WARN_ON(dev->dev->id.revision < 3);
594 /* The hardware guarantees us an atomic write, if we
595 * write the low register first. */
596 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, low);
598 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_HIGH, high);
602 void b43_tsf_write(struct b43_wldev *dev, u64 tsf)
605 b43_tsf_write_locked(dev, tsf);
606 b43_time_unlock(dev);
610 void b43_macfilter_set(struct b43_wldev *dev, u16 offset, const u8 *mac)
612 static const u8 zero_addr[ETH_ALEN] = { 0 };
619 b43_write16(dev, B43_MMIO_MACFILTER_CONTROL, offset);
623 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
626 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
629 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
632 static void b43_write_mac_bssid_templates(struct b43_wldev *dev)
636 u8 mac_bssid[ETH_ALEN * 2];
640 bssid = dev->wl->bssid;
641 mac = dev->wl->mac_addr;
643 b43_macfilter_set(dev, B43_MACFILTER_BSSID, bssid);
645 memcpy(mac_bssid, mac, ETH_ALEN);
646 memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
648 /* Write our MAC address and BSSID to template ram */
649 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) {
650 tmp = (u32) (mac_bssid[i + 0]);
651 tmp |= (u32) (mac_bssid[i + 1]) << 8;
652 tmp |= (u32) (mac_bssid[i + 2]) << 16;
653 tmp |= (u32) (mac_bssid[i + 3]) << 24;
654 b43_ram_write(dev, 0x20 + i, tmp);
658 static void b43_upload_card_macaddress(struct b43_wldev *dev)
660 b43_write_mac_bssid_templates(dev);
661 b43_macfilter_set(dev, B43_MACFILTER_SELF, dev->wl->mac_addr);
664 static void b43_set_slot_time(struct b43_wldev *dev, u16 slot_time)
666 /* slot_time is in usec. */
667 if (dev->phy.type != B43_PHYTYPE_G)
669 b43_write16(dev, 0x684, 510 + slot_time);
670 b43_shm_write16(dev, B43_SHM_SHARED, 0x0010, slot_time);
673 static void b43_short_slot_timing_enable(struct b43_wldev *dev)
675 b43_set_slot_time(dev, 9);
678 static void b43_short_slot_timing_disable(struct b43_wldev *dev)
680 b43_set_slot_time(dev, 20);
683 /* Synchronize IRQ top- and bottom-half.
684 * IRQs must be masked before calling this.
685 * This must not be called with the irq_lock held.
687 static void b43_synchronize_irq(struct b43_wldev *dev)
689 synchronize_irq(dev->dev->irq);
690 tasklet_kill(&dev->isr_tasklet);
693 /* DummyTransmission function, as documented on
694 * http://bcm-specs.sipsolutions.net/DummyTransmission
696 void b43_dummy_transmission(struct b43_wldev *dev)
698 struct b43_wl *wl = dev->wl;
699 struct b43_phy *phy = &dev->phy;
700 unsigned int i, max_loop;
713 buffer[0] = 0x000201CC;
718 buffer[0] = 0x000B846E;
725 spin_lock_irq(&wl->irq_lock);
726 write_lock(&wl->tx_lock);
728 for (i = 0; i < 5; i++)
729 b43_ram_write(dev, i * 4, buffer[i]);
732 b43_read32(dev, B43_MMIO_MACCTL);
734 b43_write16(dev, 0x0568, 0x0000);
735 b43_write16(dev, 0x07C0, 0x0000);
736 value = ((phy->type == B43_PHYTYPE_A) ? 1 : 0);
737 b43_write16(dev, 0x050C, value);
738 b43_write16(dev, 0x0508, 0x0000);
739 b43_write16(dev, 0x050A, 0x0000);
740 b43_write16(dev, 0x054C, 0x0000);
741 b43_write16(dev, 0x056A, 0x0014);
742 b43_write16(dev, 0x0568, 0x0826);
743 b43_write16(dev, 0x0500, 0x0000);
744 b43_write16(dev, 0x0502, 0x0030);
746 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
747 b43_radio_write16(dev, 0x0051, 0x0017);
748 for (i = 0x00; i < max_loop; i++) {
749 value = b43_read16(dev, 0x050E);
754 for (i = 0x00; i < 0x0A; i++) {
755 value = b43_read16(dev, 0x050E);
760 for (i = 0x00; i < 0x19; i++) {
761 value = b43_read16(dev, 0x0690);
762 if (!(value & 0x0100))
766 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
767 b43_radio_write16(dev, 0x0051, 0x0037);
769 write_unlock(&wl->tx_lock);
770 spin_unlock_irq(&wl->irq_lock);
773 static void key_write(struct b43_wldev *dev,
774 u8 index, u8 algorithm, const u8 *key)
781 /* Key index/algo block */
782 kidx = b43_kidx_to_fw(dev, index);
783 value = ((kidx << 4) | algorithm);
784 b43_shm_write16(dev, B43_SHM_SHARED,
785 B43_SHM_SH_KEYIDXBLOCK + (kidx * 2), value);
787 /* Write the key to the Key Table Pointer offset */
788 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
789 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
791 value |= (u16) (key[i + 1]) << 8;
792 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, value);
796 static void keymac_write(struct b43_wldev *dev, u8 index, const u8 *addr)
798 u32 addrtmp[2] = { 0, 0, };
799 u8 per_sta_keys_start = 8;
801 if (b43_new_kidx_api(dev))
802 per_sta_keys_start = 4;
804 B43_WARN_ON(index < per_sta_keys_start);
805 /* We have two default TX keys and possibly two default RX keys.
806 * Physical mac 0 is mapped to physical key 4 or 8, depending
807 * on the firmware version.
808 * So we must adjust the index here.
810 index -= per_sta_keys_start;
813 addrtmp[0] = addr[0];
814 addrtmp[0] |= ((u32) (addr[1]) << 8);
815 addrtmp[0] |= ((u32) (addr[2]) << 16);
816 addrtmp[0] |= ((u32) (addr[3]) << 24);
817 addrtmp[1] = addr[4];
818 addrtmp[1] |= ((u32) (addr[5]) << 8);
821 if (dev->dev->id.revision >= 5) {
822 /* Receive match transmitter address mechanism */
823 b43_shm_write32(dev, B43_SHM_RCMTA,
824 (index * 2) + 0, addrtmp[0]);
825 b43_shm_write16(dev, B43_SHM_RCMTA,
826 (index * 2) + 1, addrtmp[1]);
828 /* RXE (Receive Engine) and
829 * PSM (Programmable State Machine) mechanism
832 /* TODO write to RCM 16, 19, 22 and 25 */
834 b43_shm_write32(dev, B43_SHM_SHARED,
835 B43_SHM_SH_PSM + (index * 6) + 0,
837 b43_shm_write16(dev, B43_SHM_SHARED,
838 B43_SHM_SH_PSM + (index * 6) + 4,
844 static void do_key_write(struct b43_wldev *dev,
845 u8 index, u8 algorithm,
846 const u8 *key, size_t key_len, const u8 *mac_addr)
848 u8 buf[B43_SEC_KEYSIZE] = { 0, };
849 u8 per_sta_keys_start = 8;
851 if (b43_new_kidx_api(dev))
852 per_sta_keys_start = 4;
854 B43_WARN_ON(index >= dev->max_nr_keys);
855 B43_WARN_ON(key_len > B43_SEC_KEYSIZE);
857 if (index >= per_sta_keys_start)
858 keymac_write(dev, index, NULL); /* First zero out mac. */
860 memcpy(buf, key, key_len);
861 key_write(dev, index, algorithm, buf);
862 if (index >= per_sta_keys_start)
863 keymac_write(dev, index, mac_addr);
865 dev->key[index].algorithm = algorithm;
868 static int b43_key_write(struct b43_wldev *dev,
869 int index, u8 algorithm,
870 const u8 *key, size_t key_len,
872 struct ieee80211_key_conf *keyconf)
877 if (key_len > B43_SEC_KEYSIZE)
879 for (i = 0; i < dev->max_nr_keys; i++) {
880 /* Check that we don't already have this key. */
881 B43_WARN_ON(dev->key[i].keyconf == keyconf);
884 /* Pairwise key. Get an empty slot for the key. */
885 if (b43_new_kidx_api(dev))
889 for (i = sta_keys_start; i < dev->max_nr_keys; i++) {
890 if (!dev->key[i].keyconf) {
897 b43warn(dev->wl, "Out of hardware key memory\n");
901 B43_WARN_ON(index > 3);
903 do_key_write(dev, index, algorithm, key, key_len, mac_addr);
904 if ((index <= 3) && !b43_new_kidx_api(dev)) {
906 B43_WARN_ON(mac_addr);
907 do_key_write(dev, index + 4, algorithm, key, key_len, NULL);
909 keyconf->hw_key_idx = index;
910 dev->key[index].keyconf = keyconf;
915 static int b43_key_clear(struct b43_wldev *dev, int index)
917 if (B43_WARN_ON((index < 0) || (index >= dev->max_nr_keys)))
919 do_key_write(dev, index, B43_SEC_ALGO_NONE,
920 NULL, B43_SEC_KEYSIZE, NULL);
921 if ((index <= 3) && !b43_new_kidx_api(dev)) {
922 do_key_write(dev, index + 4, B43_SEC_ALGO_NONE,
923 NULL, B43_SEC_KEYSIZE, NULL);
925 dev->key[index].keyconf = NULL;
930 static void b43_clear_keys(struct b43_wldev *dev)
934 for (i = 0; i < dev->max_nr_keys; i++)
935 b43_key_clear(dev, i);
938 static void b43_dump_keymemory(struct b43_wldev *dev)
940 unsigned int i, index, offset;
948 if (!b43_debug(dev, B43_DBG_KEYS))
951 hf = b43_hf_read(dev);
952 b43dbg(dev->wl, "Hardware key memory dump: USEDEFKEYS=%u\n",
953 !!(hf & B43_HF_USEDEFKEYS));
954 for (index = 0; index < dev->max_nr_keys; index++) {
955 key = &(dev->key[index]);
956 printk(KERN_DEBUG "Key slot %02u: %s",
957 index, (key->keyconf == NULL) ? " " : "*");
958 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
959 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
960 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, offset + i);
961 printk("%02X%02X", (tmp & 0xFF), ((tmp >> 8) & 0xFF));
964 algo = b43_shm_read16(dev, B43_SHM_SHARED,
965 B43_SHM_SH_KEYIDXBLOCK + (index * 2));
966 printk(" Algo: %04X/%02X", algo, key->algorithm);
969 rcmta0 = b43_shm_read32(dev, B43_SHM_RCMTA,
970 ((index - 4) * 2) + 0);
971 rcmta1 = b43_shm_read16(dev, B43_SHM_RCMTA,
972 ((index - 4) * 2) + 1);
973 *((__le32 *)(&mac[0])) = cpu_to_le32(rcmta0);
974 *((__le16 *)(&mac[4])) = cpu_to_le16(rcmta1);
975 printk(" MAC: %pM", mac);
977 printk(" DEFAULT KEY");
982 void b43_power_saving_ctl_bits(struct b43_wldev *dev, unsigned int ps_flags)
990 B43_WARN_ON((ps_flags & B43_PS_ENABLED) &&
991 (ps_flags & B43_PS_DISABLED));
992 B43_WARN_ON((ps_flags & B43_PS_AWAKE) && (ps_flags & B43_PS_ASLEEP));
994 if (ps_flags & B43_PS_ENABLED) {
996 } else if (ps_flags & B43_PS_DISABLED) {
999 //TODO: If powersave is not off and FIXME is not set and we are not in adhoc
1000 // and thus is not an AP and we are associated, set bit 25
1002 if (ps_flags & B43_PS_AWAKE) {
1004 } else if (ps_flags & B43_PS_ASLEEP) {
1007 //TODO: If the device is awake or this is an AP, or we are scanning, or FIXME,
1008 // or we are associated, or FIXME, or the latest PS-Poll packet sent was
1009 // successful, set bit26
1012 /* FIXME: For now we force awake-on and hwps-off */
1016 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1018 macctl |= B43_MACCTL_HWPS;
1020 macctl &= ~B43_MACCTL_HWPS;
1022 macctl |= B43_MACCTL_AWAKE;
1024 macctl &= ~B43_MACCTL_AWAKE;
1025 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1027 b43_read32(dev, B43_MMIO_MACCTL);
1028 if (awake && dev->dev->id.revision >= 5) {
1029 /* Wait for the microcode to wake up. */
1030 for (i = 0; i < 100; i++) {
1031 ucstat = b43_shm_read16(dev, B43_SHM_SHARED,
1032 B43_SHM_SH_UCODESTAT);
1033 if (ucstat != B43_SHM_SH_UCODESTAT_SLEEP)
1040 void b43_wireless_core_reset(struct b43_wldev *dev, u32 flags)
1045 flags |= B43_TMSLOW_PHYCLKEN;
1046 flags |= B43_TMSLOW_PHYRESET;
1047 ssb_device_enable(dev->dev, flags);
1048 msleep(2); /* Wait for the PLL to turn on. */
1050 /* Now take the PHY out of Reset again */
1051 tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
1052 tmslow |= SSB_TMSLOW_FGC;
1053 tmslow &= ~B43_TMSLOW_PHYRESET;
1054 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
1055 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
1057 tmslow &= ~SSB_TMSLOW_FGC;
1058 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
1059 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
1062 /* Turn Analog ON, but only if we already know the PHY-type.
1063 * This protects against very early setup where we don't know the
1064 * PHY-type, yet. wireless_core_reset will be called once again later,
1065 * when we know the PHY-type. */
1067 dev->phy.ops->switch_analog(dev, 1);
1069 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1070 macctl &= ~B43_MACCTL_GMODE;
1071 if (flags & B43_TMSLOW_GMODE)
1072 macctl |= B43_MACCTL_GMODE;
1073 macctl |= B43_MACCTL_IHR_ENABLED;
1074 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1077 static void handle_irq_transmit_status(struct b43_wldev *dev)
1081 struct b43_txstatus stat;
1084 v0 = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1085 if (!(v0 & 0x00000001))
1087 v1 = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1089 stat.cookie = (v0 >> 16);
1090 stat.seq = (v1 & 0x0000FFFF);
1091 stat.phy_stat = ((v1 & 0x00FF0000) >> 16);
1092 tmp = (v0 & 0x0000FFFF);
1093 stat.frame_count = ((tmp & 0xF000) >> 12);
1094 stat.rts_count = ((tmp & 0x0F00) >> 8);
1095 stat.supp_reason = ((tmp & 0x001C) >> 2);
1096 stat.pm_indicated = !!(tmp & 0x0080);
1097 stat.intermediate = !!(tmp & 0x0040);
1098 stat.for_ampdu = !!(tmp & 0x0020);
1099 stat.acked = !!(tmp & 0x0002);
1101 b43_handle_txstatus(dev, &stat);
1105 static void drain_txstatus_queue(struct b43_wldev *dev)
1109 if (dev->dev->id.revision < 5)
1111 /* Read all entries from the microcode TXstatus FIFO
1112 * and throw them away.
1115 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1116 if (!(dummy & 0x00000001))
1118 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1122 static u32 b43_jssi_read(struct b43_wldev *dev)
1126 val = b43_shm_read16(dev, B43_SHM_SHARED, 0x08A);
1128 val |= b43_shm_read16(dev, B43_SHM_SHARED, 0x088);
1133 static void b43_jssi_write(struct b43_wldev *dev, u32 jssi)
1135 b43_shm_write16(dev, B43_SHM_SHARED, 0x088, (jssi & 0x0000FFFF));
1136 b43_shm_write16(dev, B43_SHM_SHARED, 0x08A, (jssi & 0xFFFF0000) >> 16);
1139 static void b43_generate_noise_sample(struct b43_wldev *dev)
1141 b43_jssi_write(dev, 0x7F7F7F7F);
1142 b43_write32(dev, B43_MMIO_MACCMD,
1143 b43_read32(dev, B43_MMIO_MACCMD) | B43_MACCMD_BGNOISE);
1146 static void b43_calculate_link_quality(struct b43_wldev *dev)
1148 /* Top half of Link Quality calculation. */
1150 if (dev->phy.type != B43_PHYTYPE_G)
1152 if (dev->noisecalc.calculation_running)
1154 dev->noisecalc.calculation_running = 1;
1155 dev->noisecalc.nr_samples = 0;
1157 b43_generate_noise_sample(dev);
1160 static void handle_irq_noise(struct b43_wldev *dev)
1162 struct b43_phy_g *phy = dev->phy.g;
1168 /* Bottom half of Link Quality calculation. */
1170 if (dev->phy.type != B43_PHYTYPE_G)
1173 /* Possible race condition: It might be possible that the user
1174 * changed to a different channel in the meantime since we
1175 * started the calculation. We ignore that fact, since it's
1176 * not really that much of a problem. The background noise is
1177 * an estimation only anyway. Slightly wrong results will get damped
1178 * by the averaging of the 8 sample rounds. Additionally the
1179 * value is shortlived. So it will be replaced by the next noise
1180 * calculation round soon. */
1182 B43_WARN_ON(!dev->noisecalc.calculation_running);
1183 *((__le32 *)noise) = cpu_to_le32(b43_jssi_read(dev));
1184 if (noise[0] == 0x7F || noise[1] == 0x7F ||
1185 noise[2] == 0x7F || noise[3] == 0x7F)
1188 /* Get the noise samples. */
1189 B43_WARN_ON(dev->noisecalc.nr_samples >= 8);
1190 i = dev->noisecalc.nr_samples;
1191 noise[0] = clamp_val(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1192 noise[1] = clamp_val(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1193 noise[2] = clamp_val(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1194 noise[3] = clamp_val(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1195 dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
1196 dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
1197 dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
1198 dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
1199 dev->noisecalc.nr_samples++;
1200 if (dev->noisecalc.nr_samples == 8) {
1201 /* Calculate the Link Quality by the noise samples. */
1203 for (i = 0; i < 8; i++) {
1204 for (j = 0; j < 4; j++)
1205 average += dev->noisecalc.samples[i][j];
1211 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x40C);
1212 tmp = (tmp / 128) & 0x1F;
1222 dev->stats.link_noise = average;
1223 dev->noisecalc.calculation_running = 0;
1227 b43_generate_noise_sample(dev);
1230 static void handle_irq_tbtt_indication(struct b43_wldev *dev)
1232 if (b43_is_mode(dev->wl, NL80211_IFTYPE_AP)) {
1235 if (1 /*FIXME: the last PSpoll frame was sent successfully */ )
1236 b43_power_saving_ctl_bits(dev, 0);
1238 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC))
1242 static void handle_irq_atim_end(struct b43_wldev *dev)
1244 if (dev->dfq_valid) {
1245 b43_write32(dev, B43_MMIO_MACCMD,
1246 b43_read32(dev, B43_MMIO_MACCMD)
1247 | B43_MACCMD_DFQ_VALID);
1252 static void handle_irq_pmq(struct b43_wldev *dev)
1259 tmp = b43_read32(dev, B43_MMIO_PS_STATUS);
1260 if (!(tmp & 0x00000008))
1263 /* 16bit write is odd, but correct. */
1264 b43_write16(dev, B43_MMIO_PS_STATUS, 0x0002);
1267 static void b43_write_template_common(struct b43_wldev *dev,
1268 const u8 *data, u16 size,
1270 u16 shm_size_offset, u8 rate)
1273 struct b43_plcp_hdr4 plcp;
1276 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
1277 b43_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
1278 ram_offset += sizeof(u32);
1279 /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
1280 * So leave the first two bytes of the next write blank.
1282 tmp = (u32) (data[0]) << 16;
1283 tmp |= (u32) (data[1]) << 24;
1284 b43_ram_write(dev, ram_offset, tmp);
1285 ram_offset += sizeof(u32);
1286 for (i = 2; i < size; i += sizeof(u32)) {
1287 tmp = (u32) (data[i + 0]);
1289 tmp |= (u32) (data[i + 1]) << 8;
1291 tmp |= (u32) (data[i + 2]) << 16;
1293 tmp |= (u32) (data[i + 3]) << 24;
1294 b43_ram_write(dev, ram_offset + i - 2, tmp);
1296 b43_shm_write16(dev, B43_SHM_SHARED, shm_size_offset,
1297 size + sizeof(struct b43_plcp_hdr6));
1300 /* Check if the use of the antenna that ieee80211 told us to
1301 * use is possible. This will fall back to DEFAULT.
1302 * "antenna_nr" is the antenna identifier we got from ieee80211. */
1303 u8 b43_ieee80211_antenna_sanitize(struct b43_wldev *dev,
1308 if (antenna_nr == 0) {
1309 /* Zero means "use default antenna". That's always OK. */
1313 /* Get the mask of available antennas. */
1315 antenna_mask = dev->dev->bus->sprom.ant_available_bg;
1317 antenna_mask = dev->dev->bus->sprom.ant_available_a;
1319 if (!(antenna_mask & (1 << (antenna_nr - 1)))) {
1320 /* This antenna is not available. Fall back to default. */
1327 /* Convert a b43 antenna number value to the PHY TX control value. */
1328 static u16 b43_antenna_to_phyctl(int antenna)
1332 return B43_TXH_PHY_ANT0;
1334 return B43_TXH_PHY_ANT1;
1336 return B43_TXH_PHY_ANT2;
1338 return B43_TXH_PHY_ANT3;
1339 case B43_ANTENNA_AUTO:
1340 return B43_TXH_PHY_ANT01AUTO;
1346 static void b43_write_beacon_template(struct b43_wldev *dev,
1348 u16 shm_size_offset)
1350 unsigned int i, len, variable_len;
1351 const struct ieee80211_mgmt *bcn;
1357 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(dev->wl->current_beacon);
1359 bcn = (const struct ieee80211_mgmt *)(dev->wl->current_beacon->data);
1360 len = min((size_t) dev->wl->current_beacon->len,
1361 0x200 - sizeof(struct b43_plcp_hdr6));
1362 rate = ieee80211_get_tx_rate(dev->wl->hw, info)->hw_value;
1364 b43_write_template_common(dev, (const u8 *)bcn,
1365 len, ram_offset, shm_size_offset, rate);
1367 /* Write the PHY TX control parameters. */
1368 antenna = B43_ANTENNA_DEFAULT;
1369 antenna = b43_antenna_to_phyctl(antenna);
1370 ctl = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL);
1371 /* We can't send beacons with short preamble. Would get PHY errors. */
1372 ctl &= ~B43_TXH_PHY_SHORTPRMBL;
1373 ctl &= ~B43_TXH_PHY_ANT;
1374 ctl &= ~B43_TXH_PHY_ENC;
1376 if (b43_is_cck_rate(rate))
1377 ctl |= B43_TXH_PHY_ENC_CCK;
1379 ctl |= B43_TXH_PHY_ENC_OFDM;
1380 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
1382 /* Find the position of the TIM and the DTIM_period value
1383 * and write them to SHM. */
1384 ie = bcn->u.beacon.variable;
1385 variable_len = len - offsetof(struct ieee80211_mgmt, u.beacon.variable);
1386 for (i = 0; i < variable_len - 2; ) {
1387 uint8_t ie_id, ie_len;
1394 /* This is the TIM Information Element */
1396 /* Check whether the ie_len is in the beacon data range. */
1397 if (variable_len < ie_len + 2 + i)
1399 /* A valid TIM is at least 4 bytes long. */
1404 tim_position = sizeof(struct b43_plcp_hdr6);
1405 tim_position += offsetof(struct ieee80211_mgmt, u.beacon.variable);
1408 dtim_period = ie[i + 3];
1410 b43_shm_write16(dev, B43_SHM_SHARED,
1411 B43_SHM_SH_TIMBPOS, tim_position);
1412 b43_shm_write16(dev, B43_SHM_SHARED,
1413 B43_SHM_SH_DTIMPER, dtim_period);
1420 * If ucode wants to modify TIM do it behind the beacon, this
1421 * will happen, for example, when doing mesh networking.
1423 b43_shm_write16(dev, B43_SHM_SHARED,
1425 len + sizeof(struct b43_plcp_hdr6));
1426 b43_shm_write16(dev, B43_SHM_SHARED,
1427 B43_SHM_SH_DTIMPER, 0);
1429 b43dbg(dev->wl, "Updated beacon template at 0x%x\n", ram_offset);
1432 static void b43_write_probe_resp_plcp(struct b43_wldev *dev,
1433 u16 shm_offset, u16 size,
1434 struct ieee80211_rate *rate)
1436 struct b43_plcp_hdr4 plcp;
1441 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate->hw_value);
1442 dur = ieee80211_generic_frame_duration(dev->wl->hw,
1445 /* Write PLCP in two parts and timing for packet transfer */
1446 tmp = le32_to_cpu(plcp.data);
1447 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset, tmp & 0xFFFF);
1448 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset + 2, tmp >> 16);
1449 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset + 6, le16_to_cpu(dur));
1452 /* Instead of using custom probe response template, this function
1453 * just patches custom beacon template by:
1454 * 1) Changing packet type
1455 * 2) Patching duration field
1458 static const u8 *b43_generate_probe_resp(struct b43_wldev *dev,
1460 struct ieee80211_rate *rate)
1464 u16 src_size, elem_size, src_pos, dest_pos;
1466 struct ieee80211_hdr *hdr;
1469 src_size = dev->wl->current_beacon->len;
1470 src_data = (const u8 *)dev->wl->current_beacon->data;
1472 /* Get the start offset of the variable IEs in the packet. */
1473 ie_start = offsetof(struct ieee80211_mgmt, u.probe_resp.variable);
1474 B43_WARN_ON(ie_start != offsetof(struct ieee80211_mgmt, u.beacon.variable));
1476 if (B43_WARN_ON(src_size < ie_start))
1479 dest_data = kmalloc(src_size, GFP_ATOMIC);
1480 if (unlikely(!dest_data))
1483 /* Copy the static data and all Information Elements, except the TIM. */
1484 memcpy(dest_data, src_data, ie_start);
1486 dest_pos = ie_start;
1487 for ( ; src_pos < src_size - 2; src_pos += elem_size) {
1488 elem_size = src_data[src_pos + 1] + 2;
1489 if (src_data[src_pos] == 5) {
1490 /* This is the TIM. */
1493 memcpy(dest_data + dest_pos, src_data + src_pos,
1495 dest_pos += elem_size;
1497 *dest_size = dest_pos;
1498 hdr = (struct ieee80211_hdr *)dest_data;
1500 /* Set the frame control. */
1501 hdr->frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT |
1502 IEEE80211_STYPE_PROBE_RESP);
1503 dur = ieee80211_generic_frame_duration(dev->wl->hw,
1504 dev->wl->vif, *dest_size,
1506 hdr->duration_id = dur;
1511 static void b43_write_probe_resp_template(struct b43_wldev *dev,
1513 u16 shm_size_offset,
1514 struct ieee80211_rate *rate)
1516 const u8 *probe_resp_data;
1519 size = dev->wl->current_beacon->len;
1520 probe_resp_data = b43_generate_probe_resp(dev, &size, rate);
1521 if (unlikely(!probe_resp_data))
1524 /* Looks like PLCP headers plus packet timings are stored for
1525 * all possible basic rates
1527 b43_write_probe_resp_plcp(dev, 0x31A, size, &b43_b_ratetable[0]);
1528 b43_write_probe_resp_plcp(dev, 0x32C, size, &b43_b_ratetable[1]);
1529 b43_write_probe_resp_plcp(dev, 0x33E, size, &b43_b_ratetable[2]);
1530 b43_write_probe_resp_plcp(dev, 0x350, size, &b43_b_ratetable[3]);
1532 size = min((size_t) size, 0x200 - sizeof(struct b43_plcp_hdr6));
1533 b43_write_template_common(dev, probe_resp_data,
1534 size, ram_offset, shm_size_offset,
1536 kfree(probe_resp_data);
1539 static void b43_upload_beacon0(struct b43_wldev *dev)
1541 struct b43_wl *wl = dev->wl;
1543 if (wl->beacon0_uploaded)
1545 b43_write_beacon_template(dev, 0x68, 0x18);
1546 /* FIXME: Probe resp upload doesn't really belong here,
1547 * but we don't use that feature anyway. */
1548 b43_write_probe_resp_template(dev, 0x268, 0x4A,
1549 &__b43_ratetable[3]);
1550 wl->beacon0_uploaded = 1;
1553 static void b43_upload_beacon1(struct b43_wldev *dev)
1555 struct b43_wl *wl = dev->wl;
1557 if (wl->beacon1_uploaded)
1559 b43_write_beacon_template(dev, 0x468, 0x1A);
1560 wl->beacon1_uploaded = 1;
1563 static void handle_irq_beacon(struct b43_wldev *dev)
1565 struct b43_wl *wl = dev->wl;
1566 u32 cmd, beacon0_valid, beacon1_valid;
1568 if (!b43_is_mode(wl, NL80211_IFTYPE_AP) &&
1569 !b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT))
1572 /* This is the bottom half of the asynchronous beacon update. */
1574 /* Ignore interrupt in the future. */
1575 dev->irq_mask &= ~B43_IRQ_BEACON;
1577 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1578 beacon0_valid = (cmd & B43_MACCMD_BEACON0_VALID);
1579 beacon1_valid = (cmd & B43_MACCMD_BEACON1_VALID);
1581 /* Schedule interrupt manually, if busy. */
1582 if (beacon0_valid && beacon1_valid) {
1583 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_BEACON);
1584 dev->irq_mask |= B43_IRQ_BEACON;
1588 if (unlikely(wl->beacon_templates_virgin)) {
1589 /* We never uploaded a beacon before.
1590 * Upload both templates now, but only mark one valid. */
1591 wl->beacon_templates_virgin = 0;
1592 b43_upload_beacon0(dev);
1593 b43_upload_beacon1(dev);
1594 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1595 cmd |= B43_MACCMD_BEACON0_VALID;
1596 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1598 if (!beacon0_valid) {
1599 b43_upload_beacon0(dev);
1600 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1601 cmd |= B43_MACCMD_BEACON0_VALID;
1602 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1603 } else if (!beacon1_valid) {
1604 b43_upload_beacon1(dev);
1605 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1606 cmd |= B43_MACCMD_BEACON1_VALID;
1607 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1612 static void b43_beacon_update_trigger_work(struct work_struct *work)
1614 struct b43_wl *wl = container_of(work, struct b43_wl,
1615 beacon_update_trigger);
1616 struct b43_wldev *dev;
1618 mutex_lock(&wl->mutex);
1619 dev = wl->current_dev;
1620 if (likely(dev && (b43_status(dev) >= B43_STAT_INITIALIZED))) {
1621 spin_lock_irq(&wl->irq_lock);
1622 /* update beacon right away or defer to irq */
1623 handle_irq_beacon(dev);
1624 /* The handler might have updated the IRQ mask. */
1625 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
1627 spin_unlock_irq(&wl->irq_lock);
1629 mutex_unlock(&wl->mutex);
1632 /* Asynchronously update the packet templates in template RAM.
1633 * Locking: Requires wl->irq_lock to be locked. */
1634 static void b43_update_templates(struct b43_wl *wl)
1636 struct sk_buff *beacon;
1638 /* This is the top half of the ansynchronous beacon update.
1639 * The bottom half is the beacon IRQ.
1640 * Beacon update must be asynchronous to avoid sending an
1641 * invalid beacon. This can happen for example, if the firmware
1642 * transmits a beacon while we are updating it. */
1644 /* We could modify the existing beacon and set the aid bit in
1645 * the TIM field, but that would probably require resizing and
1646 * moving of data within the beacon template.
1647 * Simply request a new beacon and let mac80211 do the hard work. */
1648 beacon = ieee80211_beacon_get(wl->hw, wl->vif);
1649 if (unlikely(!beacon))
1652 if (wl->current_beacon)
1653 dev_kfree_skb_any(wl->current_beacon);
1654 wl->current_beacon = beacon;
1655 wl->beacon0_uploaded = 0;
1656 wl->beacon1_uploaded = 0;
1657 ieee80211_queue_work(wl->hw, &wl->beacon_update_trigger);
1660 static void b43_set_beacon_int(struct b43_wldev *dev, u16 beacon_int)
1663 if (dev->dev->id.revision >= 3) {
1664 b43_write32(dev, B43_MMIO_TSF_CFP_REP, (beacon_int << 16));
1665 b43_write32(dev, B43_MMIO_TSF_CFP_START, (beacon_int << 10));
1667 b43_write16(dev, 0x606, (beacon_int >> 6));
1668 b43_write16(dev, 0x610, beacon_int);
1670 b43_time_unlock(dev);
1671 b43dbg(dev->wl, "Set beacon interval to %u\n", beacon_int);
1674 static void b43_handle_firmware_panic(struct b43_wldev *dev)
1678 /* Read the register that contains the reason code for the panic. */
1679 reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_FWPANIC_REASON_REG);
1680 b43err(dev->wl, "Whoopsy, firmware panic! Reason: %u\n", reason);
1684 b43dbg(dev->wl, "The panic reason is unknown.\n");
1686 case B43_FWPANIC_DIE:
1687 /* Do not restart the controller or firmware.
1688 * The device is nonfunctional from now on.
1689 * Restarting would result in this panic to trigger again,
1690 * so we avoid that recursion. */
1692 case B43_FWPANIC_RESTART:
1693 b43_controller_restart(dev, "Microcode panic");
1698 static void handle_irq_ucode_debug(struct b43_wldev *dev)
1700 unsigned int i, cnt;
1701 u16 reason, marker_id, marker_line;
1704 /* The proprietary firmware doesn't have this IRQ. */
1705 if (!dev->fw.opensource)
1708 /* Read the register that contains the reason code for this IRQ. */
1709 reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_DEBUGIRQ_REASON_REG);
1712 case B43_DEBUGIRQ_PANIC:
1713 b43_handle_firmware_panic(dev);
1715 case B43_DEBUGIRQ_DUMP_SHM:
1717 break; /* Only with driver debugging enabled. */
1718 buf = kmalloc(4096, GFP_ATOMIC);
1720 b43dbg(dev->wl, "SHM-dump: Failed to allocate memory\n");
1723 for (i = 0; i < 4096; i += 2) {
1724 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, i);
1725 buf[i / 2] = cpu_to_le16(tmp);
1727 b43info(dev->wl, "Shared memory dump:\n");
1728 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET,
1729 16, 2, buf, 4096, 1);
1732 case B43_DEBUGIRQ_DUMP_REGS:
1734 break; /* Only with driver debugging enabled. */
1735 b43info(dev->wl, "Microcode register dump:\n");
1736 for (i = 0, cnt = 0; i < 64; i++) {
1737 u16 tmp = b43_shm_read16(dev, B43_SHM_SCRATCH, i);
1740 printk("r%02u: 0x%04X ", i, tmp);
1749 case B43_DEBUGIRQ_MARKER:
1751 break; /* Only with driver debugging enabled. */
1752 marker_id = b43_shm_read16(dev, B43_SHM_SCRATCH,
1754 marker_line = b43_shm_read16(dev, B43_SHM_SCRATCH,
1755 B43_MARKER_LINE_REG);
1756 b43info(dev->wl, "The firmware just executed the MARKER(%u) "
1757 "at line number %u\n",
1758 marker_id, marker_line);
1761 b43dbg(dev->wl, "Debug-IRQ triggered for unknown reason: %u\n",
1765 /* Acknowledge the debug-IRQ, so the firmware can continue. */
1766 b43_shm_write16(dev, B43_SHM_SCRATCH,
1767 B43_DEBUGIRQ_REASON_REG, B43_DEBUGIRQ_ACK);
1770 /* Interrupt handler bottom-half */
1771 static void b43_interrupt_tasklet(struct b43_wldev *dev)
1774 u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
1775 u32 merged_dma_reason = 0;
1777 unsigned long flags;
1779 spin_lock_irqsave(&dev->wl->irq_lock, flags);
1781 B43_WARN_ON(b43_status(dev) != B43_STAT_STARTED);
1783 reason = dev->irq_reason;
1784 for (i = 0; i < ARRAY_SIZE(dma_reason); i++) {
1785 dma_reason[i] = dev->dma_reason[i];
1786 merged_dma_reason |= dma_reason[i];
1789 if (unlikely(reason & B43_IRQ_MAC_TXERR))
1790 b43err(dev->wl, "MAC transmission error\n");
1792 if (unlikely(reason & B43_IRQ_PHY_TXERR)) {
1793 b43err(dev->wl, "PHY transmission error\n");
1795 if (unlikely(atomic_dec_and_test(&dev->phy.txerr_cnt))) {
1796 atomic_set(&dev->phy.txerr_cnt,
1797 B43_PHY_TX_BADNESS_LIMIT);
1798 b43err(dev->wl, "Too many PHY TX errors, "
1799 "restarting the controller\n");
1800 b43_controller_restart(dev, "PHY TX errors");
1804 if (unlikely(merged_dma_reason & (B43_DMAIRQ_FATALMASK |
1805 B43_DMAIRQ_NONFATALMASK))) {
1806 if (merged_dma_reason & B43_DMAIRQ_FATALMASK) {
1807 b43err(dev->wl, "Fatal DMA error: "
1808 "0x%08X, 0x%08X, 0x%08X, "
1809 "0x%08X, 0x%08X, 0x%08X\n",
1810 dma_reason[0], dma_reason[1],
1811 dma_reason[2], dma_reason[3],
1812 dma_reason[4], dma_reason[5]);
1813 b43_controller_restart(dev, "DMA error");
1815 spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1818 if (merged_dma_reason & B43_DMAIRQ_NONFATALMASK) {
1819 b43err(dev->wl, "DMA error: "
1820 "0x%08X, 0x%08X, 0x%08X, "
1821 "0x%08X, 0x%08X, 0x%08X\n",
1822 dma_reason[0], dma_reason[1],
1823 dma_reason[2], dma_reason[3],
1824 dma_reason[4], dma_reason[5]);
1828 if (unlikely(reason & B43_IRQ_UCODE_DEBUG))
1829 handle_irq_ucode_debug(dev);
1830 if (reason & B43_IRQ_TBTT_INDI)
1831 handle_irq_tbtt_indication(dev);
1832 if (reason & B43_IRQ_ATIM_END)
1833 handle_irq_atim_end(dev);
1834 if (reason & B43_IRQ_BEACON)
1835 handle_irq_beacon(dev);
1836 if (reason & B43_IRQ_PMQ)
1837 handle_irq_pmq(dev);
1838 if (reason & B43_IRQ_TXFIFO_FLUSH_OK)
1840 if (reason & B43_IRQ_NOISESAMPLE_OK)
1841 handle_irq_noise(dev);
1843 /* Check the DMA reason registers for received data. */
1844 if (dma_reason[0] & B43_DMAIRQ_RX_DONE) {
1845 if (b43_using_pio_transfers(dev))
1846 b43_pio_rx(dev->pio.rx_queue);
1848 b43_dma_rx(dev->dma.rx_ring);
1850 B43_WARN_ON(dma_reason[1] & B43_DMAIRQ_RX_DONE);
1851 B43_WARN_ON(dma_reason[2] & B43_DMAIRQ_RX_DONE);
1852 B43_WARN_ON(dma_reason[3] & B43_DMAIRQ_RX_DONE);
1853 B43_WARN_ON(dma_reason[4] & B43_DMAIRQ_RX_DONE);
1854 B43_WARN_ON(dma_reason[5] & B43_DMAIRQ_RX_DONE);
1856 if (reason & B43_IRQ_TX_OK)
1857 handle_irq_transmit_status(dev);
1859 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
1861 spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1864 static void b43_interrupt_ack(struct b43_wldev *dev, u32 reason)
1866 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, reason);
1868 b43_write32(dev, B43_MMIO_DMA0_REASON, dev->dma_reason[0]);
1869 b43_write32(dev, B43_MMIO_DMA1_REASON, dev->dma_reason[1]);
1870 b43_write32(dev, B43_MMIO_DMA2_REASON, dev->dma_reason[2]);
1871 b43_write32(dev, B43_MMIO_DMA3_REASON, dev->dma_reason[3]);
1872 b43_write32(dev, B43_MMIO_DMA4_REASON, dev->dma_reason[4]);
1874 b43_write32(dev, B43_MMIO_DMA5_REASON, dev->dma_reason[5]);
1878 /* Interrupt handler top-half */
1879 static irqreturn_t b43_interrupt_handler(int irq, void *dev_id)
1881 irqreturn_t ret = IRQ_NONE;
1882 struct b43_wldev *dev = dev_id;
1887 spin_lock(&dev->wl->irq_lock);
1889 if (unlikely(b43_status(dev) < B43_STAT_STARTED)) {
1890 /* This can only happen on shared IRQ lines. */
1893 reason = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1894 if (reason == 0xffffffff) /* shared IRQ */
1897 reason &= dev->irq_mask;
1901 dev->dma_reason[0] = b43_read32(dev, B43_MMIO_DMA0_REASON)
1903 dev->dma_reason[1] = b43_read32(dev, B43_MMIO_DMA1_REASON)
1905 dev->dma_reason[2] = b43_read32(dev, B43_MMIO_DMA2_REASON)
1907 dev->dma_reason[3] = b43_read32(dev, B43_MMIO_DMA3_REASON)
1909 dev->dma_reason[4] = b43_read32(dev, B43_MMIO_DMA4_REASON)
1912 dev->dma_reason[5] = b43_read32(dev, B43_MMIO_DMA5_REASON)
1916 b43_interrupt_ack(dev, reason);
1917 /* disable all IRQs. They are enabled again in the bottom half. */
1918 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
1919 /* save the reason code and call our bottom half. */
1920 dev->irq_reason = reason;
1921 tasklet_schedule(&dev->isr_tasklet);
1924 spin_unlock(&dev->wl->irq_lock);
1929 void b43_do_release_fw(struct b43_firmware_file *fw)
1931 release_firmware(fw->data);
1933 fw->filename = NULL;
1936 static void b43_release_firmware(struct b43_wldev *dev)
1938 b43_do_release_fw(&dev->fw.ucode);
1939 b43_do_release_fw(&dev->fw.pcm);
1940 b43_do_release_fw(&dev->fw.initvals);
1941 b43_do_release_fw(&dev->fw.initvals_band);
1944 static void b43_print_fw_helptext(struct b43_wl *wl, bool error)
1948 "http://wireless.kernel.org/en/users/Drivers/b43#devicefirmware " \
1949 "and download the correct firmware for this driver version. " \
1950 "Please carefully read all instructions on this website.\n";
1958 int b43_do_request_fw(struct b43_request_fw_context *ctx,
1960 struct b43_firmware_file *fw)
1962 const struct firmware *blob;
1963 struct b43_fw_header *hdr;
1968 /* Don't fetch anything. Free possibly cached firmware. */
1969 /* FIXME: We should probably keep it anyway, to save some headache
1970 * on suspend/resume with multiband devices. */
1971 b43_do_release_fw(fw);
1975 if ((fw->type == ctx->req_type) &&
1976 (strcmp(fw->filename, name) == 0))
1977 return 0; /* Already have this fw. */
1978 /* Free the cached firmware first. */
1979 /* FIXME: We should probably do this later after we successfully
1980 * got the new fw. This could reduce headache with multiband devices.
1981 * We could also redesign this to cache the firmware for all possible
1982 * bands all the time. */
1983 b43_do_release_fw(fw);
1986 switch (ctx->req_type) {
1987 case B43_FWTYPE_PROPRIETARY:
1988 snprintf(ctx->fwname, sizeof(ctx->fwname),
1990 modparam_fwpostfix, name);
1992 case B43_FWTYPE_OPENSOURCE:
1993 snprintf(ctx->fwname, sizeof(ctx->fwname),
1995 modparam_fwpostfix, name);
2001 err = request_firmware(&blob, ctx->fwname, ctx->dev->dev->dev);
2002 if (err == -ENOENT) {
2003 snprintf(ctx->errors[ctx->req_type],
2004 sizeof(ctx->errors[ctx->req_type]),
2005 "Firmware file \"%s\" not found\n", ctx->fwname);
2008 snprintf(ctx->errors[ctx->req_type],
2009 sizeof(ctx->errors[ctx->req_type]),
2010 "Firmware file \"%s\" request failed (err=%d)\n",
2014 if (blob->size < sizeof(struct b43_fw_header))
2016 hdr = (struct b43_fw_header *)(blob->data);
2017 switch (hdr->type) {
2018 case B43_FW_TYPE_UCODE:
2019 case B43_FW_TYPE_PCM:
2020 size = be32_to_cpu(hdr->size);
2021 if (size != blob->size - sizeof(struct b43_fw_header))
2024 case B43_FW_TYPE_IV:
2033 fw->filename = name;
2034 fw->type = ctx->req_type;
2039 snprintf(ctx->errors[ctx->req_type],
2040 sizeof(ctx->errors[ctx->req_type]),
2041 "Firmware file \"%s\" format error.\n", ctx->fwname);
2042 release_firmware(blob);
2047 static int b43_try_request_fw(struct b43_request_fw_context *ctx)
2049 struct b43_wldev *dev = ctx->dev;
2050 struct b43_firmware *fw = &ctx->dev->fw;
2051 const u8 rev = ctx->dev->dev->id.revision;
2052 const char *filename;
2057 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
2058 if ((rev >= 5) && (rev <= 10))
2059 filename = "ucode5";
2060 else if ((rev >= 11) && (rev <= 12))
2061 filename = "ucode11";
2063 filename = "ucode13";
2066 err = b43_do_request_fw(ctx, filename, &fw->ucode);
2071 if ((rev >= 5) && (rev <= 10))
2077 fw->pcm_request_failed = 0;
2078 err = b43_do_request_fw(ctx, filename, &fw->pcm);
2079 if (err == -ENOENT) {
2080 /* We did not find a PCM file? Not fatal, but
2081 * core rev <= 10 must do without hwcrypto then. */
2082 fw->pcm_request_failed = 1;
2087 switch (dev->phy.type) {
2089 if ((rev >= 5) && (rev <= 10)) {
2090 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
2091 filename = "a0g1initvals5";
2093 filename = "a0g0initvals5";
2095 goto err_no_initvals;
2098 if ((rev >= 5) && (rev <= 10))
2099 filename = "b0g0initvals5";
2101 filename = "b0g0initvals13";
2103 goto err_no_initvals;
2106 if ((rev >= 11) && (rev <= 12))
2107 filename = "n0initvals11";
2109 goto err_no_initvals;
2112 goto err_no_initvals;
2114 err = b43_do_request_fw(ctx, filename, &fw->initvals);
2118 /* Get bandswitch initvals */
2119 switch (dev->phy.type) {
2121 if ((rev >= 5) && (rev <= 10)) {
2122 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
2123 filename = "a0g1bsinitvals5";
2125 filename = "a0g0bsinitvals5";
2126 } else if (rev >= 11)
2129 goto err_no_initvals;
2132 if ((rev >= 5) && (rev <= 10))
2133 filename = "b0g0bsinitvals5";
2137 goto err_no_initvals;
2140 if ((rev >= 11) && (rev <= 12))
2141 filename = "n0bsinitvals11";
2143 goto err_no_initvals;
2146 goto err_no_initvals;
2148 err = b43_do_request_fw(ctx, filename, &fw->initvals_band);
2155 err = ctx->fatal_failure = -EOPNOTSUPP;
2156 b43err(dev->wl, "The driver does not know which firmware (ucode) "
2157 "is required for your device (wl-core rev %u)\n", rev);
2161 err = ctx->fatal_failure = -EOPNOTSUPP;
2162 b43err(dev->wl, "The driver does not know which firmware (PCM) "
2163 "is required for your device (wl-core rev %u)\n", rev);
2167 err = ctx->fatal_failure = -EOPNOTSUPP;
2168 b43err(dev->wl, "The driver does not know which firmware (initvals) "
2169 "is required for your device (wl-core rev %u)\n", rev);
2173 /* We failed to load this firmware image. The error message
2174 * already is in ctx->errors. Return and let our caller decide
2179 b43_release_firmware(dev);
2183 static int b43_request_firmware(struct b43_wldev *dev)
2185 struct b43_request_fw_context *ctx;
2190 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
2195 ctx->req_type = B43_FWTYPE_PROPRIETARY;
2196 err = b43_try_request_fw(ctx);
2198 goto out; /* Successfully loaded it. */
2199 err = ctx->fatal_failure;
2203 ctx->req_type = B43_FWTYPE_OPENSOURCE;
2204 err = b43_try_request_fw(ctx);
2206 goto out; /* Successfully loaded it. */
2207 err = ctx->fatal_failure;
2211 /* Could not find a usable firmware. Print the errors. */
2212 for (i = 0; i < B43_NR_FWTYPES; i++) {
2213 errmsg = ctx->errors[i];
2215 b43err(dev->wl, errmsg);
2217 b43_print_fw_helptext(dev->wl, 1);
2225 static int b43_upload_microcode(struct b43_wldev *dev)
2227 const size_t hdr_len = sizeof(struct b43_fw_header);
2229 unsigned int i, len;
2230 u16 fwrev, fwpatch, fwdate, fwtime;
2234 /* Jump the microcode PSM to offset 0 */
2235 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2236 B43_WARN_ON(macctl & B43_MACCTL_PSM_RUN);
2237 macctl |= B43_MACCTL_PSM_JMP0;
2238 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2239 /* Zero out all microcode PSM registers and shared memory. */
2240 for (i = 0; i < 64; i++)
2241 b43_shm_write16(dev, B43_SHM_SCRATCH, i, 0);
2242 for (i = 0; i < 4096; i += 2)
2243 b43_shm_write16(dev, B43_SHM_SHARED, i, 0);
2245 /* Upload Microcode. */
2246 data = (__be32 *) (dev->fw.ucode.data->data + hdr_len);
2247 len = (dev->fw.ucode.data->size - hdr_len) / sizeof(__be32);
2248 b43_shm_control_word(dev, B43_SHM_UCODE | B43_SHM_AUTOINC_W, 0x0000);
2249 for (i = 0; i < len; i++) {
2250 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
2254 if (dev->fw.pcm.data) {
2255 /* Upload PCM data. */
2256 data = (__be32 *) (dev->fw.pcm.data->data + hdr_len);
2257 len = (dev->fw.pcm.data->size - hdr_len) / sizeof(__be32);
2258 b43_shm_control_word(dev, B43_SHM_HW, 0x01EA);
2259 b43_write32(dev, B43_MMIO_SHM_DATA, 0x00004000);
2260 /* No need for autoinc bit in SHM_HW */
2261 b43_shm_control_word(dev, B43_SHM_HW, 0x01EB);
2262 for (i = 0; i < len; i++) {
2263 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
2268 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_ALL);
2270 /* Start the microcode PSM */
2271 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2272 macctl &= ~B43_MACCTL_PSM_JMP0;
2273 macctl |= B43_MACCTL_PSM_RUN;
2274 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2276 /* Wait for the microcode to load and respond */
2279 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2280 if (tmp == B43_IRQ_MAC_SUSPENDED)
2284 b43err(dev->wl, "Microcode not responding\n");
2285 b43_print_fw_helptext(dev->wl, 1);
2289 msleep_interruptible(50);
2290 if (signal_pending(current)) {
2295 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); /* dummy read */
2297 /* Get and check the revisions. */
2298 fwrev = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEREV);
2299 fwpatch = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEPATCH);
2300 fwdate = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEDATE);
2301 fwtime = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODETIME);
2303 if (fwrev <= 0x128) {
2304 b43err(dev->wl, "YOUR FIRMWARE IS TOO OLD. Firmware from "
2305 "binary drivers older than version 4.x is unsupported. "
2306 "You must upgrade your firmware files.\n");
2307 b43_print_fw_helptext(dev->wl, 1);
2311 dev->fw.rev = fwrev;
2312 dev->fw.patch = fwpatch;
2313 dev->fw.opensource = (fwdate == 0xFFFF);
2315 /* Default to use-all-queues. */
2316 dev->wl->hw->queues = dev->wl->mac80211_initially_registered_queues;
2317 dev->qos_enabled = !!modparam_qos;
2318 /* Default to firmware/hardware crypto acceleration. */
2319 dev->hwcrypto_enabled = 1;
2321 if (dev->fw.opensource) {
2324 /* Patchlevel info is encoded in the "time" field. */
2325 dev->fw.patch = fwtime;
2326 b43info(dev->wl, "Loading OpenSource firmware version %u.%u\n",
2327 dev->fw.rev, dev->fw.patch);
2329 fwcapa = b43_fwcapa_read(dev);
2330 if (!(fwcapa & B43_FWCAPA_HWCRYPTO) || dev->fw.pcm_request_failed) {
2331 b43info(dev->wl, "Hardware crypto acceleration not supported by firmware\n");
2332 /* Disable hardware crypto and fall back to software crypto. */
2333 dev->hwcrypto_enabled = 0;
2335 if (!(fwcapa & B43_FWCAPA_QOS)) {
2336 b43info(dev->wl, "QoS not supported by firmware\n");
2337 /* Disable QoS. Tweak hw->queues to 1. It will be restored before
2338 * ieee80211_unregister to make sure the networking core can
2339 * properly free possible resources. */
2340 dev->wl->hw->queues = 1;
2341 dev->qos_enabled = 0;
2344 b43info(dev->wl, "Loading firmware version %u.%u "
2345 "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n",
2347 (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
2348 (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, fwtime & 0x1F);
2349 if (dev->fw.pcm_request_failed) {
2350 b43warn(dev->wl, "No \"pcm5.fw\" firmware file found. "
2351 "Hardware accelerated cryptography is disabled.\n");
2352 b43_print_fw_helptext(dev->wl, 0);
2356 if (b43_is_old_txhdr_format(dev)) {
2357 /* We're over the deadline, but we keep support for old fw
2358 * until it turns out to be in major conflict with something new. */
2359 b43warn(dev->wl, "You are using an old firmware image. "
2360 "Support for old firmware will be removed soon "
2361 "(official deadline was July 2008).\n");
2362 b43_print_fw_helptext(dev->wl, 0);
2368 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2369 macctl &= ~B43_MACCTL_PSM_RUN;
2370 macctl |= B43_MACCTL_PSM_JMP0;
2371 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2376 static int b43_write_initvals(struct b43_wldev *dev,
2377 const struct b43_iv *ivals,
2381 const struct b43_iv *iv;
2386 BUILD_BUG_ON(sizeof(struct b43_iv) != 6);
2388 for (i = 0; i < count; i++) {
2389 if (array_size < sizeof(iv->offset_size))
2391 array_size -= sizeof(iv->offset_size);
2392 offset = be16_to_cpu(iv->offset_size);
2393 bit32 = !!(offset & B43_IV_32BIT);
2394 offset &= B43_IV_OFFSET_MASK;
2395 if (offset >= 0x1000)
2400 if (array_size < sizeof(iv->data.d32))
2402 array_size -= sizeof(iv->data.d32);
2404 value = get_unaligned_be32(&iv->data.d32);
2405 b43_write32(dev, offset, value);
2407 iv = (const struct b43_iv *)((const uint8_t *)iv +
2413 if (array_size < sizeof(iv->data.d16))
2415 array_size -= sizeof(iv->data.d16);
2417 value = be16_to_cpu(iv->data.d16);
2418 b43_write16(dev, offset, value);
2420 iv = (const struct b43_iv *)((const uint8_t *)iv +
2431 b43err(dev->wl, "Initial Values Firmware file-format error.\n");
2432 b43_print_fw_helptext(dev->wl, 1);
2437 static int b43_upload_initvals(struct b43_wldev *dev)
2439 const size_t hdr_len = sizeof(struct b43_fw_header);
2440 const struct b43_fw_header *hdr;
2441 struct b43_firmware *fw = &dev->fw;
2442 const struct b43_iv *ivals;
2446 hdr = (const struct b43_fw_header *)(fw->initvals.data->data);
2447 ivals = (const struct b43_iv *)(fw->initvals.data->data + hdr_len);
2448 count = be32_to_cpu(hdr->size);
2449 err = b43_write_initvals(dev, ivals, count,
2450 fw->initvals.data->size - hdr_len);
2453 if (fw->initvals_band.data) {
2454 hdr = (const struct b43_fw_header *)(fw->initvals_band.data->data);
2455 ivals = (const struct b43_iv *)(fw->initvals_band.data->data + hdr_len);
2456 count = be32_to_cpu(hdr->size);
2457 err = b43_write_initvals(dev, ivals, count,
2458 fw->initvals_band.data->size - hdr_len);
2467 /* Initialize the GPIOs
2468 * http://bcm-specs.sipsolutions.net/GPIO
2470 static int b43_gpio_init(struct b43_wldev *dev)
2472 struct ssb_bus *bus = dev->dev->bus;
2473 struct ssb_device *gpiodev, *pcidev = NULL;
2476 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2477 & ~B43_MACCTL_GPOUTSMSK);
2479 b43_write16(dev, B43_MMIO_GPIO_MASK, b43_read16(dev, B43_MMIO_GPIO_MASK)
2484 if (dev->dev->bus->chip_id == 0x4301) {
2488 if (0 /* FIXME: conditional unknown */ ) {
2489 b43_write16(dev, B43_MMIO_GPIO_MASK,
2490 b43_read16(dev, B43_MMIO_GPIO_MASK)
2495 if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_PACTRL) {
2496 b43_write16(dev, B43_MMIO_GPIO_MASK,
2497 b43_read16(dev, B43_MMIO_GPIO_MASK)
2502 if (dev->dev->id.revision >= 2)
2503 mask |= 0x0010; /* FIXME: This is redundant. */
2505 #ifdef CONFIG_SSB_DRIVER_PCICORE
2506 pcidev = bus->pcicore.dev;
2508 gpiodev = bus->chipco.dev ? : pcidev;
2511 ssb_write32(gpiodev, B43_GPIO_CONTROL,
2512 (ssb_read32(gpiodev, B43_GPIO_CONTROL)
2518 /* Turn off all GPIO stuff. Call this on module unload, for example. */
2519 static void b43_gpio_cleanup(struct b43_wldev *dev)
2521 struct ssb_bus *bus = dev->dev->bus;
2522 struct ssb_device *gpiodev, *pcidev = NULL;
2524 #ifdef CONFIG_SSB_DRIVER_PCICORE
2525 pcidev = bus->pcicore.dev;
2527 gpiodev = bus->chipco.dev ? : pcidev;
2530 ssb_write32(gpiodev, B43_GPIO_CONTROL, 0);
2533 /* http://bcm-specs.sipsolutions.net/EnableMac */
2534 void b43_mac_enable(struct b43_wldev *dev)
2536 if (b43_debug(dev, B43_DBG_FIRMWARE)) {
2539 fwstate = b43_shm_read16(dev, B43_SHM_SHARED,
2540 B43_SHM_SH_UCODESTAT);
2541 if ((fwstate != B43_SHM_SH_UCODESTAT_SUSP) &&
2542 (fwstate != B43_SHM_SH_UCODESTAT_SLEEP)) {
2543 b43err(dev->wl, "b43_mac_enable(): The firmware "
2544 "should be suspended, but current state is %u\n",
2549 dev->mac_suspended--;
2550 B43_WARN_ON(dev->mac_suspended < 0);
2551 if (dev->mac_suspended == 0) {
2552 b43_write32(dev, B43_MMIO_MACCTL,
2553 b43_read32(dev, B43_MMIO_MACCTL)
2554 | B43_MACCTL_ENABLED);
2555 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON,
2556 B43_IRQ_MAC_SUSPENDED);
2558 b43_read32(dev, B43_MMIO_MACCTL);
2559 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2560 b43_power_saving_ctl_bits(dev, 0);
2564 /* http://bcm-specs.sipsolutions.net/SuspendMAC */
2565 void b43_mac_suspend(struct b43_wldev *dev)
2571 B43_WARN_ON(dev->mac_suspended < 0);
2573 if (dev->mac_suspended == 0) {
2574 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
2575 b43_write32(dev, B43_MMIO_MACCTL,
2576 b43_read32(dev, B43_MMIO_MACCTL)
2577 & ~B43_MACCTL_ENABLED);
2578 /* force pci to flush the write */
2579 b43_read32(dev, B43_MMIO_MACCTL);
2580 for (i = 35; i; i--) {
2581 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2582 if (tmp & B43_IRQ_MAC_SUSPENDED)
2586 /* Hm, it seems this will take some time. Use msleep(). */
2587 for (i = 40; i; i--) {
2588 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2589 if (tmp & B43_IRQ_MAC_SUSPENDED)
2593 b43err(dev->wl, "MAC suspend failed\n");
2596 dev->mac_suspended++;
2599 static void b43_adjust_opmode(struct b43_wldev *dev)
2601 struct b43_wl *wl = dev->wl;
2605 ctl = b43_read32(dev, B43_MMIO_MACCTL);
2606 /* Reset status to STA infrastructure mode. */
2607 ctl &= ~B43_MACCTL_AP;
2608 ctl &= ~B43_MACCTL_KEEP_CTL;
2609 ctl &= ~B43_MACCTL_KEEP_BADPLCP;
2610 ctl &= ~B43_MACCTL_KEEP_BAD;
2611 ctl &= ~B43_MACCTL_PROMISC;
2612 ctl &= ~B43_MACCTL_BEACPROMISC;
2613 ctl |= B43_MACCTL_INFRA;
2615 if (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
2616 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT))
2617 ctl |= B43_MACCTL_AP;
2618 else if (b43_is_mode(wl, NL80211_IFTYPE_ADHOC))
2619 ctl &= ~B43_MACCTL_INFRA;
2621 if (wl->filter_flags & FIF_CONTROL)
2622 ctl |= B43_MACCTL_KEEP_CTL;
2623 if (wl->filter_flags & FIF_FCSFAIL)
2624 ctl |= B43_MACCTL_KEEP_BAD;
2625 if (wl->filter_flags & FIF_PLCPFAIL)
2626 ctl |= B43_MACCTL_KEEP_BADPLCP;
2627 if (wl->filter_flags & FIF_PROMISC_IN_BSS)
2628 ctl |= B43_MACCTL_PROMISC;
2629 if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC)
2630 ctl |= B43_MACCTL_BEACPROMISC;
2632 /* Workaround: On old hardware the HW-MAC-address-filter
2633 * doesn't work properly, so always run promisc in filter
2634 * it in software. */
2635 if (dev->dev->id.revision <= 4)
2636 ctl |= B43_MACCTL_PROMISC;
2638 b43_write32(dev, B43_MMIO_MACCTL, ctl);
2641 if ((ctl & B43_MACCTL_INFRA) && !(ctl & B43_MACCTL_AP)) {
2642 if (dev->dev->bus->chip_id == 0x4306 &&
2643 dev->dev->bus->chip_rev == 3)
2648 b43_write16(dev, 0x612, cfp_pretbtt);
2651 static void b43_rate_memory_write(struct b43_wldev *dev, u16 rate, int is_ofdm)
2657 offset += (b43_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
2660 offset += (b43_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
2662 b43_shm_write16(dev, B43_SHM_SHARED, offset + 0x20,
2663 b43_shm_read16(dev, B43_SHM_SHARED, offset));
2666 static void b43_rate_memory_init(struct b43_wldev *dev)
2668 switch (dev->phy.type) {
2672 b43_rate_memory_write(dev, B43_OFDM_RATE_6MB, 1);
2673 b43_rate_memory_write(dev, B43_OFDM_RATE_12MB, 1);
2674 b43_rate_memory_write(dev, B43_OFDM_RATE_18MB, 1);
2675 b43_rate_memory_write(dev, B43_OFDM_RATE_24MB, 1);
2676 b43_rate_memory_write(dev, B43_OFDM_RATE_36MB, 1);
2677 b43_rate_memory_write(dev, B43_OFDM_RATE_48MB, 1);
2678 b43_rate_memory_write(dev, B43_OFDM_RATE_54MB, 1);
2679 if (dev->phy.type == B43_PHYTYPE_A)
2683 b43_rate_memory_write(dev, B43_CCK_RATE_1MB, 0);
2684 b43_rate_memory_write(dev, B43_CCK_RATE_2MB, 0);
2685 b43_rate_memory_write(dev, B43_CCK_RATE_5MB, 0);
2686 b43_rate_memory_write(dev, B43_CCK_RATE_11MB, 0);
2693 /* Set the default values for the PHY TX Control Words. */
2694 static void b43_set_phytxctl_defaults(struct b43_wldev *dev)
2698 ctl |= B43_TXH_PHY_ENC_CCK;
2699 ctl |= B43_TXH_PHY_ANT01AUTO;
2700 ctl |= B43_TXH_PHY_TXPWR;
2702 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
2703 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, ctl);
2704 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, ctl);
2707 /* Set the TX-Antenna for management frames sent by firmware. */
2708 static void b43_mgmtframe_txantenna(struct b43_wldev *dev, int antenna)
2713 ant = b43_antenna_to_phyctl(antenna);
2716 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL);
2717 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
2718 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, tmp);
2719 /* For Probe Resposes */
2720 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL);
2721 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
2722 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, tmp);
2725 /* This is the opposite of b43_chip_init() */
2726 static void b43_chip_exit(struct b43_wldev *dev)
2729 b43_gpio_cleanup(dev);
2730 /* firmware is released later */
2733 /* Initialize the chip
2734 * http://bcm-specs.sipsolutions.net/ChipInit
2736 static int b43_chip_init(struct b43_wldev *dev)
2738 struct b43_phy *phy = &dev->phy;
2740 u32 value32, macctl;
2743 /* Initialize the MAC control */
2744 macctl = B43_MACCTL_IHR_ENABLED | B43_MACCTL_SHM_ENABLED;
2746 macctl |= B43_MACCTL_GMODE;
2747 macctl |= B43_MACCTL_INFRA;
2748 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2750 err = b43_request_firmware(dev);
2753 err = b43_upload_microcode(dev);
2755 goto out; /* firmware is released later */
2757 err = b43_gpio_init(dev);
2759 goto out; /* firmware is released later */
2761 err = b43_upload_initvals(dev);
2763 goto err_gpio_clean;
2765 /* Turn the Analog on and initialize the PHY. */
2766 phy->ops->switch_analog(dev, 1);
2767 err = b43_phy_init(dev);
2769 goto err_gpio_clean;
2771 /* Disable Interference Mitigation. */
2772 if (phy->ops->interf_mitigation)
2773 phy->ops->interf_mitigation(dev, B43_INTERFMODE_NONE);
2775 /* Select the antennae */
2776 if (phy->ops->set_rx_antenna)
2777 phy->ops->set_rx_antenna(dev, B43_ANTENNA_DEFAULT);
2778 b43_mgmtframe_txantenna(dev, B43_ANTENNA_DEFAULT);
2780 if (phy->type == B43_PHYTYPE_B) {
2781 value16 = b43_read16(dev, 0x005E);
2783 b43_write16(dev, 0x005E, value16);
2785 b43_write32(dev, 0x0100, 0x01000000);
2786 if (dev->dev->id.revision < 5)
2787 b43_write32(dev, 0x010C, 0x01000000);
2789 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2790 & ~B43_MACCTL_INFRA);
2791 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2792 | B43_MACCTL_INFRA);
2794 /* Probe Response Timeout value */
2795 /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
2796 b43_shm_write16(dev, B43_SHM_SHARED, 0x0074, 0x0000);
2798 /* Initially set the wireless operation mode. */
2799 b43_adjust_opmode(dev);
2801 if (dev->dev->id.revision < 3) {
2802 b43_write16(dev, 0x060E, 0x0000);
2803 b43_write16(dev, 0x0610, 0x8000);
2804 b43_write16(dev, 0x0604, 0x0000);
2805 b43_write16(dev, 0x0606, 0x0200);
2807 b43_write32(dev, 0x0188, 0x80000000);
2808 b43_write32(dev, 0x018C, 0x02000000);
2810 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 0x00004000);
2811 b43_write32(dev, B43_MMIO_DMA0_IRQ_MASK, 0x0001DC00);
2812 b43_write32(dev, B43_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
2813 b43_write32(dev, B43_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
2814 b43_write32(dev, B43_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
2815 b43_write32(dev, B43_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
2816 b43_write32(dev, B43_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
2818 value32 = ssb_read32(dev->dev, SSB_TMSLOW);
2819 value32 |= 0x00100000;
2820 ssb_write32(dev->dev, SSB_TMSLOW, value32);
2822 b43_write16(dev, B43_MMIO_POWERUP_DELAY,
2823 dev->dev->bus->chipco.fast_pwrup_delay);
2826 b43dbg(dev->wl, "Chip initialized\n");
2831 b43_gpio_cleanup(dev);
2835 static void b43_periodic_every60sec(struct b43_wldev *dev)
2837 const struct b43_phy_operations *ops = dev->phy.ops;
2839 if (ops->pwork_60sec)
2840 ops->pwork_60sec(dev);
2842 /* Force check the TX power emission now. */
2843 b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME);
2846 static void b43_periodic_every30sec(struct b43_wldev *dev)
2848 /* Update device statistics. */
2849 b43_calculate_link_quality(dev);
2852 static void b43_periodic_every15sec(struct b43_wldev *dev)
2854 struct b43_phy *phy = &dev->phy;
2857 if (dev->fw.opensource) {
2858 /* Check if the firmware is still alive.
2859 * It will reset the watchdog counter to 0 in its idle loop. */
2860 wdr = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_WATCHDOG_REG);
2861 if (unlikely(wdr)) {
2862 b43err(dev->wl, "Firmware watchdog: The firmware died!\n");
2863 b43_controller_restart(dev, "Firmware watchdog");
2866 b43_shm_write16(dev, B43_SHM_SCRATCH,
2867 B43_WATCHDOG_REG, 1);
2871 if (phy->ops->pwork_15sec)
2872 phy->ops->pwork_15sec(dev);
2874 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
2878 static void do_periodic_work(struct b43_wldev *dev)
2882 state = dev->periodic_state;
2884 b43_periodic_every60sec(dev);
2886 b43_periodic_every30sec(dev);
2887 b43_periodic_every15sec(dev);
2890 /* Periodic work locking policy:
2891 * The whole periodic work handler is protected by
2892 * wl->mutex. If another lock is needed somewhere in the
2893 * pwork callchain, it's aquired in-place, where it's needed.
2895 static void b43_periodic_work_handler(struct work_struct *work)
2897 struct b43_wldev *dev = container_of(work, struct b43_wldev,
2898 periodic_work.work);
2899 struct b43_wl *wl = dev->wl;
2900 unsigned long delay;
2902 mutex_lock(&wl->mutex);
2904 if (unlikely(b43_status(dev) != B43_STAT_STARTED))
2906 if (b43_debug(dev, B43_DBG_PWORK_STOP))
2909 do_periodic_work(dev);
2911 dev->periodic_state++;
2913 if (b43_debug(dev, B43_DBG_PWORK_FAST))
2914 delay = msecs_to_jiffies(50);
2916 delay = round_jiffies_relative(HZ * 15);
2917 ieee80211_queue_delayed_work(wl->hw, &dev->periodic_work, delay);
2919 mutex_unlock(&wl->mutex);
2922 static void b43_periodic_tasks_setup(struct b43_wldev *dev)
2924 struct delayed_work *work = &dev->periodic_work;
2926 dev->periodic_state = 0;
2927 INIT_DELAYED_WORK(work, b43_periodic_work_handler);
2928 ieee80211_queue_delayed_work(dev->wl->hw, work, 0);
2931 /* Check if communication with the device works correctly. */
2932 static int b43_validate_chipaccess(struct b43_wldev *dev)
2936 backup = b43_shm_read32(dev, B43_SHM_SHARED, 0);
2938 /* Check for read/write and endianness problems. */
2939 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0x55AAAA55);
2940 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0x55AAAA55)
2942 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0xAA5555AA);
2943 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0xAA5555AA)
2946 b43_shm_write32(dev, B43_SHM_SHARED, 0, backup);
2948 if ((dev->dev->id.revision >= 3) && (dev->dev->id.revision <= 10)) {
2949 /* The 32bit register shadows the two 16bit registers
2950 * with update sideeffects. Validate this. */
2951 b43_write16(dev, B43_MMIO_TSF_CFP_START, 0xAAAA);
2952 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0xCCCCBBBB);
2953 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_LOW) != 0xBBBB)
2955 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_HIGH) != 0xCCCC)
2958 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0);
2960 v = b43_read32(dev, B43_MMIO_MACCTL);
2961 v |= B43_MACCTL_GMODE;
2962 if (v != (B43_MACCTL_GMODE | B43_MACCTL_IHR_ENABLED))
2967 b43err(dev->wl, "Failed to validate the chipaccess\n");
2971 static void b43_security_init(struct b43_wldev *dev)
2973 dev->max_nr_keys = (dev->dev->id.revision >= 5) ? 58 : 20;
2974 B43_WARN_ON(dev->max_nr_keys > ARRAY_SIZE(dev->key));
2975 dev->ktp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_KTP);
2976 /* KTP is a word address, but we address SHM bytewise.
2977 * So multiply by two.
2980 if (dev->dev->id.revision >= 5) {
2981 /* Number of RCMTA address slots */
2982 b43_write16(dev, B43_MMIO_RCMTA_COUNT, dev->max_nr_keys - 8);
2984 b43_clear_keys(dev);
2987 #ifdef CONFIG_B43_HWRNG
2988 static int b43_rng_read(struct hwrng *rng, u32 *data)
2990 struct b43_wl *wl = (struct b43_wl *)rng->priv;
2991 unsigned long flags;
2993 /* Don't take wl->mutex here, as it could deadlock with
2994 * hwrng internal locking. It's not needed to take
2995 * wl->mutex here, anyway. */
2997 spin_lock_irqsave(&wl->irq_lock, flags);
2998 *data = b43_read16(wl->current_dev, B43_MMIO_RNG);
2999 spin_unlock_irqrestore(&wl->irq_lock, flags);
3001 return (sizeof(u16));
3003 #endif /* CONFIG_B43_HWRNG */
3005 static void b43_rng_exit(struct b43_wl *wl)
3007 #ifdef CONFIG_B43_HWRNG
3008 if (wl->rng_initialized)
3009 hwrng_unregister(&wl->rng);
3010 #endif /* CONFIG_B43_HWRNG */
3013 static int b43_rng_init(struct b43_wl *wl)
3017 #ifdef CONFIG_B43_HWRNG
3018 snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name),
3019 "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy));
3020 wl->rng.name = wl->rng_name;
3021 wl->rng.data_read = b43_rng_read;
3022 wl->rng.priv = (unsigned long)wl;
3023 wl->rng_initialized = 1;
3024 err = hwrng_register(&wl->rng);
3026 wl->rng_initialized = 0;
3027 b43err(wl, "Failed to register the random "
3028 "number generator (%d)\n", err);
3030 #endif /* CONFIG_B43_HWRNG */
3035 static int b43_op_tx(struct ieee80211_hw *hw,
3036 struct sk_buff *skb)
3038 struct b43_wl *wl = hw_to_b43_wl(hw);
3039 struct b43_wldev *dev = wl->current_dev;
3040 unsigned long flags;
3043 if (unlikely(skb->len < 2 + 2 + 6)) {
3044 /* Too short, this can't be a valid frame. */
3047 B43_WARN_ON(skb_shinfo(skb)->nr_frags);
3051 /* Transmissions on seperate queues can run concurrently. */
3052 read_lock_irqsave(&wl->tx_lock, flags);
3055 if (likely(b43_status(dev) >= B43_STAT_STARTED)) {
3056 if (b43_using_pio_transfers(dev))
3057 err = b43_pio_tx(dev, skb);
3059 err = b43_dma_tx(dev, skb);
3062 read_unlock_irqrestore(&wl->tx_lock, flags);
3066 return NETDEV_TX_OK;
3069 /* We can not transmit this packet. Drop it. */
3070 dev_kfree_skb_any(skb);
3071 return NETDEV_TX_OK;
3074 /* Locking: wl->irq_lock */
3075 static void b43_qos_params_upload(struct b43_wldev *dev,
3076 const struct ieee80211_tx_queue_params *p,
3079 u16 params[B43_NR_QOSPARAMS];
3083 bslots = b43_read16(dev, B43_MMIO_RNG) & p->cw_min;
3085 memset(¶ms, 0, sizeof(params));
3087 params[B43_QOSPARAM_TXOP] = p->txop * 32;
3088 params[B43_QOSPARAM_CWMIN] = p->cw_min;
3089 params[B43_QOSPARAM_CWMAX] = p->cw_max;
3090 params[B43_QOSPARAM_CWCUR] = p->cw_min;
3091 params[B43_QOSPARAM_AIFS] = p->aifs;
3092 params[B43_QOSPARAM_BSLOTS] = bslots;
3093 params[B43_QOSPARAM_REGGAP] = bslots + p->aifs;
3095 for (i = 0; i < ARRAY_SIZE(params); i++) {
3096 if (i == B43_QOSPARAM_STATUS) {
3097 tmp = b43_shm_read16(dev, B43_SHM_SHARED,
3098 shm_offset + (i * 2));
3099 /* Mark the parameters as updated. */
3101 b43_shm_write16(dev, B43_SHM_SHARED,
3102 shm_offset + (i * 2),
3105 b43_shm_write16(dev, B43_SHM_SHARED,
3106 shm_offset + (i * 2),
3112 /* Mapping of mac80211 queue numbers to b43 QoS SHM offsets. */
3113 static const u16 b43_qos_shm_offsets[] = {
3114 /* [mac80211-queue-nr] = SHM_OFFSET, */
3115 [0] = B43_QOS_VOICE,
3116 [1] = B43_QOS_VIDEO,
3117 [2] = B43_QOS_BESTEFFORT,
3118 [3] = B43_QOS_BACKGROUND,
3121 /* Update all QOS parameters in hardware. */
3122 static void b43_qos_upload_all(struct b43_wldev *dev)
3124 struct b43_wl *wl = dev->wl;
3125 struct b43_qos_params *params;
3128 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3129 ARRAY_SIZE(wl->qos_params));
3131 b43_mac_suspend(dev);
3132 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
3133 params = &(wl->qos_params[i]);
3134 b43_qos_params_upload(dev, &(params->p),
3135 b43_qos_shm_offsets[i]);
3137 b43_mac_enable(dev);
3140 static void b43_qos_clear(struct b43_wl *wl)
3142 struct b43_qos_params *params;
3145 /* Initialize QoS parameters to sane defaults. */
3147 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3148 ARRAY_SIZE(wl->qos_params));
3150 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
3151 params = &(wl->qos_params[i]);
3153 switch (b43_qos_shm_offsets[i]) {
3157 params->p.cw_min = 0x0001;
3158 params->p.cw_max = 0x0001;
3163 params->p.cw_min = 0x0001;
3164 params->p.cw_max = 0x0001;
3166 case B43_QOS_BESTEFFORT:
3169 params->p.cw_min = 0x0001;
3170 params->p.cw_max = 0x03FF;
3172 case B43_QOS_BACKGROUND:
3175 params->p.cw_min = 0x0001;
3176 params->p.cw_max = 0x03FF;
3184 /* Initialize the core's QOS capabilities */
3185 static void b43_qos_init(struct b43_wldev *dev)
3187 /* Upload the current QOS parameters. */
3188 b43_qos_upload_all(dev);
3190 /* Enable QOS support. */
3191 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_EDCF);
3192 b43_write16(dev, B43_MMIO_IFSCTL,
3193 b43_read16(dev, B43_MMIO_IFSCTL)
3194 | B43_MMIO_IFSCTL_USE_EDCF);
3197 static int b43_op_conf_tx(struct ieee80211_hw *hw, u16 _queue,
3198 const struct ieee80211_tx_queue_params *params)
3200 struct b43_wl *wl = hw_to_b43_wl(hw);
3201 struct b43_wldev *dev;
3202 unsigned int queue = (unsigned int)_queue;
3205 if (queue >= ARRAY_SIZE(wl->qos_params)) {
3206 /* Queue not available or don't support setting
3207 * params on this queue. Return success to not
3208 * confuse mac80211. */
3211 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3212 ARRAY_SIZE(wl->qos_params));
3214 mutex_lock(&wl->mutex);
3215 dev = wl->current_dev;
3216 if (unlikely(!dev || (b43_status(dev) < B43_STAT_INITIALIZED)))
3219 memcpy(&(wl->qos_params[queue].p), params, sizeof(*params));
3220 b43_mac_suspend(dev);
3221 b43_qos_params_upload(dev, &(wl->qos_params[queue].p),
3222 b43_qos_shm_offsets[queue]);
3223 b43_mac_enable(dev);
3227 mutex_unlock(&wl->mutex);
3232 static int b43_op_get_tx_stats(struct ieee80211_hw *hw,
3233 struct ieee80211_tx_queue_stats *stats)
3235 struct b43_wl *wl = hw_to_b43_wl(hw);
3236 struct b43_wldev *dev = wl->current_dev;
3237 unsigned long flags;
3242 spin_lock_irqsave(&wl->irq_lock, flags);
3243 if (likely(b43_status(dev) >= B43_STAT_STARTED)) {
3244 if (b43_using_pio_transfers(dev))
3245 b43_pio_get_tx_stats(dev, stats);
3247 b43_dma_get_tx_stats(dev, stats);
3250 spin_unlock_irqrestore(&wl->irq_lock, flags);
3255 static int b43_op_get_stats(struct ieee80211_hw *hw,
3256 struct ieee80211_low_level_stats *stats)
3258 struct b43_wl *wl = hw_to_b43_wl(hw);
3259 unsigned long flags;
3261 spin_lock_irqsave(&wl->irq_lock, flags);
3262 memcpy(stats, &wl->ieee_stats, sizeof(*stats));
3263 spin_unlock_irqrestore(&wl->irq_lock, flags);
3268 static u64 b43_op_get_tsf(struct ieee80211_hw *hw)
3270 struct b43_wl *wl = hw_to_b43_wl(hw);
3271 struct b43_wldev *dev;
3274 mutex_lock(&wl->mutex);
3275 spin_lock_irq(&wl->irq_lock);
3276 dev = wl->current_dev;
3278 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED))
3279 b43_tsf_read(dev, &tsf);
3283 spin_unlock_irq(&wl->irq_lock);
3284 mutex_unlock(&wl->mutex);
3289 static void b43_op_set_tsf(struct ieee80211_hw *hw, u64 tsf)
3291 struct b43_wl *wl = hw_to_b43_wl(hw);
3292 struct b43_wldev *dev;
3294 mutex_lock(&wl->mutex);
3295 spin_lock_irq(&wl->irq_lock);
3296 dev = wl->current_dev;
3298 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED))
3299 b43_tsf_write(dev, tsf);
3301 spin_unlock_irq(&wl->irq_lock);
3302 mutex_unlock(&wl->mutex);
3305 static void b43_put_phy_into_reset(struct b43_wldev *dev)
3307 struct ssb_device *sdev = dev->dev;
3310 tmslow = ssb_read32(sdev, SSB_TMSLOW);
3311 tmslow &= ~B43_TMSLOW_GMODE;
3312 tmslow |= B43_TMSLOW_PHYRESET;
3313 tmslow |= SSB_TMSLOW_FGC;
3314 ssb_write32(sdev, SSB_TMSLOW, tmslow);
3317 tmslow = ssb_read32(sdev, SSB_TMSLOW);
3318 tmslow &= ~SSB_TMSLOW_FGC;
3319 tmslow |= B43_TMSLOW_PHYRESET;
3320 ssb_write32(sdev, SSB_TMSLOW, tmslow);
3324 static const char *band_to_string(enum ieee80211_band band)
3327 case IEEE80211_BAND_5GHZ:
3329 case IEEE80211_BAND_2GHZ:
3338 /* Expects wl->mutex locked */
3339 static int b43_switch_band(struct b43_wl *wl, struct ieee80211_channel *chan)
3341 struct b43_wldev *up_dev = NULL;
3342 struct b43_wldev *down_dev;
3343 struct b43_wldev *d;
3345 bool uninitialized_var(gmode);
3348 /* Find a device and PHY which supports the band. */
3349 list_for_each_entry(d, &wl->devlist, list) {
3350 switch (chan->band) {
3351 case IEEE80211_BAND_5GHZ:
3352 if (d->phy.supports_5ghz) {
3357 case IEEE80211_BAND_2GHZ:
3358 if (d->phy.supports_2ghz) {
3371 b43err(wl, "Could not find a device for %s-GHz band operation\n",
3372 band_to_string(chan->band));
3375 if ((up_dev == wl->current_dev) &&
3376 (!!wl->current_dev->phy.gmode == !!gmode)) {
3377 /* This device is already running. */
3380 b43dbg(wl, "Switching to %s-GHz band\n",
3381 band_to_string(chan->band));
3382 down_dev = wl->current_dev;
3384 prev_status = b43_status(down_dev);
3385 /* Shutdown the currently running core. */
3386 if (prev_status >= B43_STAT_STARTED)
3387 b43_wireless_core_stop(down_dev);
3388 if (prev_status >= B43_STAT_INITIALIZED)
3389 b43_wireless_core_exit(down_dev);
3391 if (down_dev != up_dev) {
3392 /* We switch to a different core, so we put PHY into
3393 * RESET on the old core. */
3394 b43_put_phy_into_reset(down_dev);
3397 /* Now start the new core. */
3398 up_dev->phy.gmode = gmode;
3399 if (prev_status >= B43_STAT_INITIALIZED) {
3400 err = b43_wireless_core_init(up_dev);
3402 b43err(wl, "Fatal: Could not initialize device for "
3403 "selected %s-GHz band\n",
3404 band_to_string(chan->band));
3408 if (prev_status >= B43_STAT_STARTED) {
3409 err = b43_wireless_core_start(up_dev);
3411 b43err(wl, "Fatal: Coult not start device for "
3412 "selected %s-GHz band\n",
3413 band_to_string(chan->band));
3414 b43_wireless_core_exit(up_dev);
3418 B43_WARN_ON(b43_status(up_dev) != prev_status);
3420 wl->current_dev = up_dev;
3424 /* Whoops, failed to init the new core. No core is operating now. */
3425 wl->current_dev = NULL;
3429 /* Write the short and long frame retry limit values. */
3430 static void b43_set_retry_limits(struct b43_wldev *dev,
3431 unsigned int short_retry,
3432 unsigned int long_retry)
3434 /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing
3435 * the chip-internal counter. */
3436 short_retry = min(short_retry, (unsigned int)0xF);
3437 long_retry = min(long_retry, (unsigned int)0xF);
3439 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_SRLIMIT,
3441 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_LRLIMIT,
3445 static int b43_op_config(struct ieee80211_hw *hw, u32 changed)
3447 struct b43_wl *wl = hw_to_b43_wl(hw);
3448 struct b43_wldev *dev;
3449 struct b43_phy *phy;
3450 struct ieee80211_conf *conf = &hw->conf;
3451 unsigned long flags;
3455 mutex_lock(&wl->mutex);
3457 /* Switch the band (if necessary). This might change the active core. */
3458 err = b43_switch_band(wl, conf->channel);
3460 goto out_unlock_mutex;
3461 dev = wl->current_dev;
3464 b43_mac_suspend(dev);
3466 if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
3467 b43_set_retry_limits(dev, conf->short_frame_max_tx_count,
3468 conf->long_frame_max_tx_count);
3469 changed &= ~IEEE80211_CONF_CHANGE_RETRY_LIMITS;
3471 goto out_mac_enable;
3473 /* Switch to the requested channel.
3474 * The firmware takes care of races with the TX handler. */
3475 if (conf->channel->hw_value != phy->channel)
3476 b43_switch_channel(dev, conf->channel->hw_value);
3478 dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_RADIOTAP);
3480 /* Adjust the desired TX power level. */
3481 if (conf->power_level != 0) {
3482 spin_lock_irqsave(&wl->irq_lock, flags);
3483 if (conf->power_level != phy->desired_txpower) {
3484 phy->desired_txpower = conf->power_level;
3485 b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME |
3486 B43_TXPWR_IGNORE_TSSI);
3488 spin_unlock_irqrestore(&wl->irq_lock, flags);
3491 /* Antennas for RX and management frame TX. */
3492 antenna = B43_ANTENNA_DEFAULT;
3493 b43_mgmtframe_txantenna(dev, antenna);
3494 antenna = B43_ANTENNA_DEFAULT;
3495 if (phy->ops->set_rx_antenna)
3496 phy->ops->set_rx_antenna(dev, antenna);
3498 if (wl->radio_enabled != phy->radio_on) {
3499 if (wl->radio_enabled) {
3500 b43_software_rfkill(dev, false);
3501 b43info(dev->wl, "Radio turned on by software\n");
3502 if (!dev->radio_hw_enable) {
3503 b43info(dev->wl, "The hardware RF-kill button "
3504 "still turns the radio physically off. "
3505 "Press the button to turn it on.\n");
3508 b43_software_rfkill(dev, true);
3509 b43info(dev->wl, "Radio turned off by software\n");
3514 b43_mac_enable(dev);
3516 mutex_unlock(&wl->mutex);
3521 static void b43_update_basic_rates(struct b43_wldev *dev, u32 brates)
3523 struct ieee80211_supported_band *sband =
3524 dev->wl->hw->wiphy->bands[b43_current_band(dev->wl)];
3525 struct ieee80211_rate *rate;
3527 u16 basic, direct, offset, basic_offset, rateptr;
3529 for (i = 0; i < sband->n_bitrates; i++) {
3530 rate = &sband->bitrates[i];
3532 if (b43_is_cck_rate(rate->hw_value)) {
3533 direct = B43_SHM_SH_CCKDIRECT;
3534 basic = B43_SHM_SH_CCKBASIC;
3535 offset = b43_plcp_get_ratecode_cck(rate->hw_value);
3538 direct = B43_SHM_SH_OFDMDIRECT;
3539 basic = B43_SHM_SH_OFDMBASIC;
3540 offset = b43_plcp_get_ratecode_ofdm(rate->hw_value);
3544 rate = ieee80211_get_response_rate(sband, brates, rate->bitrate);
3546 if (b43_is_cck_rate(rate->hw_value)) {
3547 basic_offset = b43_plcp_get_ratecode_cck(rate->hw_value);
3548 basic_offset &= 0xF;
3550 basic_offset = b43_plcp_get_ratecode_ofdm(rate->hw_value);
3551 basic_offset &= 0xF;
3555 * Get the pointer that we need to point to
3556 * from the direct map
3558 rateptr = b43_shm_read16(dev, B43_SHM_SHARED,
3559 direct + 2 * basic_offset);
3560 /* and write it to the basic map */
3561 b43_shm_write16(dev, B43_SHM_SHARED, basic + 2 * offset,
3566 static void b43_op_bss_info_changed(struct ieee80211_hw *hw,
3567 struct ieee80211_vif *vif,
3568 struct ieee80211_bss_conf *conf,
3571 struct b43_wl *wl = hw_to_b43_wl(hw);
3572 struct b43_wldev *dev;
3573 unsigned long flags;
3575 mutex_lock(&wl->mutex);
3577 dev = wl->current_dev;
3578 if (!dev || b43_status(dev) < B43_STAT_STARTED)
3579 goto out_unlock_mutex;
3581 B43_WARN_ON(wl->vif != vif);
3583 spin_lock_irqsave(&wl->irq_lock, flags);
3584 if (changed & BSS_CHANGED_BSSID) {
3586 memcpy(wl->bssid, conf->bssid, ETH_ALEN);
3588 memset(wl->bssid, 0, ETH_ALEN);
3591 if (b43_status(dev) >= B43_STAT_INITIALIZED) {
3592 if (changed & BSS_CHANGED_BEACON &&
3593 (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
3594 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) ||
3595 b43_is_mode(wl, NL80211_IFTYPE_ADHOC)))
3596 b43_update_templates(wl);
3598 if (changed & BSS_CHANGED_BSSID)
3599 b43_write_mac_bssid_templates(dev);
3601 spin_unlock_irqrestore(&wl->irq_lock, flags);
3603 b43_mac_suspend(dev);
3605 /* Update templates for AP/mesh mode. */
3606 if (changed & BSS_CHANGED_BEACON_INT &&
3607 (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
3608 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) ||
3609 b43_is_mode(wl, NL80211_IFTYPE_ADHOC)))
3610 b43_set_beacon_int(dev, conf->beacon_int);
3612 if (changed & BSS_CHANGED_BASIC_RATES)
3613 b43_update_basic_rates(dev, conf->basic_rates);
3615 if (changed & BSS_CHANGED_ERP_SLOT) {
3616 if (conf->use_short_slot)
3617 b43_short_slot_timing_enable(dev);
3619 b43_short_slot_timing_disable(dev);
3622 b43_mac_enable(dev);
3624 mutex_unlock(&wl->mutex);
3627 static int b43_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
3628 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
3629 struct ieee80211_key_conf *key)
3631 struct b43_wl *wl = hw_to_b43_wl(hw);
3632 struct b43_wldev *dev;
3636 static const u8 bcast_addr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
3638 if (modparam_nohwcrypt)
3639 return -ENOSPC; /* User disabled HW-crypto */
3641 mutex_lock(&wl->mutex);
3642 spin_lock_irq(&wl->irq_lock);
3643 write_lock(&wl->tx_lock);
3644 /* Why do we need all this locking here?
3645 * mutex -> Every config operation must take it.
3646 * irq_lock -> We modify the dev->key array, which is accessed
3647 * in the IRQ handlers.
3648 * tx_lock -> We modify the dev->key array, which is accessed
3649 * in the TX handler.
3652 dev = wl->current_dev;
3654 if (!dev || b43_status(dev) < B43_STAT_INITIALIZED)
3657 if (dev->fw.pcm_request_failed || !dev->hwcrypto_enabled) {
3658 /* We don't have firmware for the crypto engine.
3659 * Must use software-crypto. */
3667 if (key->keylen == WLAN_KEY_LEN_WEP40)
3668 algorithm = B43_SEC_ALGO_WEP40;
3670 algorithm = B43_SEC_ALGO_WEP104;
3673 algorithm = B43_SEC_ALGO_TKIP;
3676 algorithm = B43_SEC_ALGO_AES;
3682 index = (u8) (key->keyidx);
3688 if (algorithm == B43_SEC_ALGO_TKIP) {
3689 /* FIXME: No TKIP hardware encryption for now. */
3694 if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) {
3695 if (WARN_ON(!sta)) {
3699 /* Pairwise key with an assigned MAC address. */
3700 err = b43_key_write(dev, -1, algorithm,
3701 key->key, key->keylen,
3705 err = b43_key_write(dev, index, algorithm,
3706 key->key, key->keylen, NULL, key);
3711 if (algorithm == B43_SEC_ALGO_WEP40 ||
3712 algorithm == B43_SEC_ALGO_WEP104) {
3713 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_USEDEFKEYS);
3716 b43_hf_read(dev) & ~B43_HF_USEDEFKEYS);
3718 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
3721 err = b43_key_clear(dev, key->hw_key_idx);
3732 b43dbg(wl, "%s hardware based encryption for keyidx: %d, "
3734 cmd == SET_KEY ? "Using" : "Disabling", key->keyidx,
3735 sta ? sta->addr : bcast_addr);
3736 b43_dump_keymemory(dev);
3738 write_unlock(&wl->tx_lock);
3739 spin_unlock_irq(&wl->irq_lock);
3740 mutex_unlock(&wl->mutex);
3745 static void b43_op_configure_filter(struct ieee80211_hw *hw,
3746 unsigned int changed, unsigned int *fflags,
3747 int mc_count, struct dev_addr_list *mc_list)
3749 struct b43_wl *wl = hw_to_b43_wl(hw);
3750 struct b43_wldev *dev = wl->current_dev;
3751 unsigned long flags;
3758 spin_lock_irqsave(&wl->irq_lock, flags);
3759 *fflags &= FIF_PROMISC_IN_BSS |
3765 FIF_BCN_PRBRESP_PROMISC;
3767 changed &= FIF_PROMISC_IN_BSS |
3773 FIF_BCN_PRBRESP_PROMISC;
3775 wl->filter_flags = *fflags;
3777 if (changed && b43_status(dev) >= B43_STAT_INITIALIZED)
3778 b43_adjust_opmode(dev);
3779 spin_unlock_irqrestore(&wl->irq_lock, flags);
3782 /* Locking: wl->mutex */
3783 static void b43_wireless_core_stop(struct b43_wldev *dev)
3785 struct b43_wl *wl = dev->wl;
3786 unsigned long flags;
3788 if (b43_status(dev) < B43_STAT_STARTED)
3791 /* Disable and sync interrupts. We must do this before than
3792 * setting the status to INITIALIZED, as the interrupt handler
3793 * won't care about IRQs then. */
3794 spin_lock_irqsave(&wl->irq_lock, flags);
3795 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
3796 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* flush */
3797 spin_unlock_irqrestore(&wl->irq_lock, flags);
3798 b43_synchronize_irq(dev);
3800 write_lock_irqsave(&wl->tx_lock, flags);
3801 b43_set_status(dev, B43_STAT_INITIALIZED);
3802 write_unlock_irqrestore(&wl->tx_lock, flags);
3805 mutex_unlock(&wl->mutex);
3806 /* Must unlock as it would otherwise deadlock. No races here.
3807 * Cancel the possibly running self-rearming periodic work. */
3808 cancel_delayed_work_sync(&dev->periodic_work);
3809 mutex_lock(&wl->mutex);
3811 b43_mac_suspend(dev);
3812 free_irq(dev->dev->irq, dev);
3813 b43dbg(wl, "Wireless interface stopped\n");
3816 /* Locking: wl->mutex */
3817 static int b43_wireless_core_start(struct b43_wldev *dev)
3821 B43_WARN_ON(b43_status(dev) != B43_STAT_INITIALIZED);
3823 drain_txstatus_queue(dev);
3824 err = request_irq(dev->dev->irq, b43_interrupt_handler,
3825 IRQF_SHARED, KBUILD_MODNAME, dev);
3827 b43err(dev->wl, "Cannot request IRQ-%d\n", dev->dev->irq);
3831 /* We are ready to run. */
3832 b43_set_status(dev, B43_STAT_STARTED);
3834 /* Start data flow (TX/RX). */
3835 b43_mac_enable(dev);
3836 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
3838 /* Start maintainance work */
3839 b43_periodic_tasks_setup(dev);
3841 b43dbg(dev->wl, "Wireless interface started\n");
3846 /* Get PHY and RADIO versioning numbers */
3847 static int b43_phy_versioning(struct b43_wldev *dev)
3849 struct b43_phy *phy = &dev->phy;
3857 int unsupported = 0;
3859 /* Get PHY versioning */
3860 tmp = b43_read16(dev, B43_MMIO_PHY_VER);
3861 analog_type = (tmp & B43_PHYVER_ANALOG) >> B43_PHYVER_ANALOG_SHIFT;
3862 phy_type = (tmp & B43_PHYVER_TYPE) >> B43_PHYVER_TYPE_SHIFT;
3863 phy_rev = (tmp & B43_PHYVER_VERSION);
3870 if (phy_rev != 2 && phy_rev != 4 && phy_rev != 6
3878 #ifdef CONFIG_B43_NPHY
3884 #ifdef CONFIG_B43_PHY_LP
3885 case B43_PHYTYPE_LP:
3894 b43err(dev->wl, "FOUND UNSUPPORTED PHY "
3895 "(Analog %u, Type %u, Revision %u)\n",
3896 analog_type, phy_type, phy_rev);
3899 b43dbg(dev->wl, "Found PHY: Analog %u, Type %u, Revision %u\n",
3900 analog_type, phy_type, phy_rev);
3902 /* Get RADIO versioning */
3903 if (dev->dev->bus->chip_id == 0x4317) {
3904 if (dev->dev->bus->chip_rev == 0)
3906 else if (dev->dev->bus->chip_rev == 1)
3911 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
3912 tmp = b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
3913 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
3914 tmp |= (u32)b43_read16(dev, B43_MMIO_RADIO_DATA_HIGH) << 16;
3916 radio_manuf = (tmp & 0x00000FFF);
3917 radio_ver = (tmp & 0x0FFFF000) >> 12;
3918 radio_rev = (tmp & 0xF0000000) >> 28;
3919 if (radio_manuf != 0x17F /* Broadcom */)
3923 if (radio_ver != 0x2060)
3927 if (radio_manuf != 0x17F)
3931 if ((radio_ver & 0xFFF0) != 0x2050)
3935 if (radio_ver != 0x2050)
3939 if (radio_ver != 0x2055 && radio_ver != 0x2056)
3942 case B43_PHYTYPE_LP:
3943 if (radio_ver != 0x2062)
3950 b43err(dev->wl, "FOUND UNSUPPORTED RADIO "
3951 "(Manuf 0x%X, Version 0x%X, Revision %u)\n",
3952 radio_manuf, radio_ver, radio_rev);
3955 b43dbg(dev->wl, "Found Radio: Manuf 0x%X, Version 0x%X, Revision %u\n",
3956 radio_manuf, radio_ver, radio_rev);
3958 phy->radio_manuf = radio_manuf;
3959 phy->radio_ver = radio_ver;
3960 phy->radio_rev = radio_rev;
3962 phy->analog = analog_type;
3963 phy->type = phy_type;
3969 static void setup_struct_phy_for_init(struct b43_wldev *dev,
3970 struct b43_phy *phy)
3972 phy->hardware_power_control = !!modparam_hwpctl;
3973 phy->next_txpwr_check_time = jiffies;
3974 /* PHY TX errors counter. */
3975 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
3978 phy->phy_locked = 0;
3979 phy->radio_locked = 0;
3983 static void setup_struct_wldev_for_init(struct b43_wldev *dev)
3987 /* Assume the radio is enabled. If it's not enabled, the state will
3988 * immediately get fixed on the first periodic work run. */
3989 dev->radio_hw_enable = 1;
3992 memset(&dev->stats, 0, sizeof(dev->stats));
3994 setup_struct_phy_for_init(dev, &dev->phy);
3996 /* IRQ related flags */
3997 dev->irq_reason = 0;
3998 memset(dev->dma_reason, 0, sizeof(dev->dma_reason));
3999 dev->irq_mask = B43_IRQ_MASKTEMPLATE;
4000 if (b43_modparam_verbose < B43_VERBOSITY_DEBUG)
4001 dev->irq_mask &= ~B43_IRQ_PHY_TXERR;
4003 dev->mac_suspended = 1;
4005 /* Noise calculation context */
4006 memset(&dev->noisecalc, 0, sizeof(dev->noisecalc));
4009 static void b43_bluetooth_coext_enable(struct b43_wldev *dev)
4011 struct ssb_sprom *sprom = &dev->dev->bus->sprom;
4014 if (!modparam_btcoex)
4016 if (!(sprom->boardflags_lo & B43_BFL_BTCOEXIST))
4018 if (dev->phy.type != B43_PHYTYPE_B && !dev->phy.gmode)
4021 hf = b43_hf_read(dev);
4022 if (sprom->boardflags_lo & B43_BFL_BTCMOD)
4023 hf |= B43_HF_BTCOEXALT;
4025 hf |= B43_HF_BTCOEX;
4026 b43_hf_write(dev, hf);
4029 static void b43_bluetooth_coext_disable(struct b43_wldev *dev)
4031 if (!modparam_btcoex)
4036 static void b43_imcfglo_timeouts_workaround(struct b43_wldev *dev)
4038 #ifdef CONFIG_SSB_DRIVER_PCICORE
4039 struct ssb_bus *bus = dev->dev->bus;
4042 if (bus->pcicore.dev &&
4043 bus->pcicore.dev->id.coreid == SSB_DEV_PCI &&
4044 bus->pcicore.dev->id.revision <= 5) {
4045 /* IMCFGLO timeouts workaround. */
4046 tmp = ssb_read32(dev->dev, SSB_IMCFGLO);
4047 tmp &= ~SSB_IMCFGLO_REQTO;
4048 tmp &= ~SSB_IMCFGLO_SERTO;
4049 switch (bus->bustype) {
4050 case SSB_BUSTYPE_PCI:
4051 case SSB_BUSTYPE_PCMCIA:
4054 case SSB_BUSTYPE_SSB:
4058 ssb_write32(dev->dev, SSB_IMCFGLO, tmp);
4060 #endif /* CONFIG_SSB_DRIVER_PCICORE */
4063 static void b43_set_synth_pu_delay(struct b43_wldev *dev, bool idle)
4067 /* The time value is in microseconds. */
4068 if (dev->phy.type == B43_PHYTYPE_A)
4072 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC) || idle)
4074 if ((dev->phy.radio_ver == 0x2050) && (dev->phy.radio_rev == 8))
4075 pu_delay = max(pu_delay, (u16)2400);
4077 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SPUWKUP, pu_delay);
4080 /* Set the TSF CFP pre-TargetBeaconTransmissionTime. */
4081 static void b43_set_pretbtt(struct b43_wldev *dev)
4085 /* The time value is in microseconds. */
4086 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC)) {
4089 if (dev->phy.type == B43_PHYTYPE_A)
4094 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRETBTT, pretbtt);
4095 b43_write16(dev, B43_MMIO_TSF_CFP_PRETBTT, pretbtt);
4098 /* Shutdown a wireless core */
4099 /* Locking: wl->mutex */
4100 static void b43_wireless_core_exit(struct b43_wldev *dev)
4104 B43_WARN_ON(b43_status(dev) > B43_STAT_INITIALIZED);
4105 if (b43_status(dev) != B43_STAT_INITIALIZED)
4107 b43_set_status(dev, B43_STAT_UNINIT);
4109 /* Stop the microcode PSM. */
4110 macctl = b43_read32(dev, B43_MMIO_MACCTL);
4111 macctl &= ~B43_MACCTL_PSM_RUN;
4112 macctl |= B43_MACCTL_PSM_JMP0;
4113 b43_write32(dev, B43_MMIO_MACCTL, macctl);
4115 if (!dev->suspend_in_progress) {
4117 b43_rng_exit(dev->wl);
4122 dev->phy.ops->switch_analog(dev, 0);
4123 if (dev->wl->current_beacon) {
4124 dev_kfree_skb_any(dev->wl->current_beacon);
4125 dev->wl->current_beacon = NULL;
4128 ssb_device_disable(dev->dev, 0);
4129 ssb_bus_may_powerdown(dev->dev->bus);
4132 /* Initialize a wireless core */
4133 static int b43_wireless_core_init(struct b43_wldev *dev)
4135 struct b43_wl *wl = dev->wl;
4136 struct ssb_bus *bus = dev->dev->bus;
4137 struct ssb_sprom *sprom = &bus->sprom;
4138 struct b43_phy *phy = &dev->phy;
4143 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
4145 err = ssb_bus_powerup(bus, 0);
4148 if (!ssb_device_is_enabled(dev->dev)) {
4149 tmp = phy->gmode ? B43_TMSLOW_GMODE : 0;
4150 b43_wireless_core_reset(dev, tmp);
4153 /* Reset all data structures. */
4154 setup_struct_wldev_for_init(dev);
4155 phy->ops->prepare_structs(dev);
4157 /* Enable IRQ routing to this device. */
4158 ssb_pcicore_dev_irqvecs_enable(&bus->pcicore, dev->dev);
4160 b43_imcfglo_timeouts_workaround(dev);
4161 b43_bluetooth_coext_disable(dev);
4162 if (phy->ops->prepare_hardware) {
4163 err = phy->ops->prepare_hardware(dev);
4167 err = b43_chip_init(dev);
4170 b43_shm_write16(dev, B43_SHM_SHARED,
4171 B43_SHM_SH_WLCOREREV, dev->dev->id.revision);
4172 hf = b43_hf_read(dev);
4173 if (phy->type == B43_PHYTYPE_G) {
4177 if (sprom->boardflags_lo & B43_BFL_PACTRL)
4178 hf |= B43_HF_OFDMPABOOST;
4180 if (phy->radio_ver == 0x2050) {
4181 if (phy->radio_rev == 6)
4182 hf |= B43_HF_4318TSSI;
4183 if (phy->radio_rev < 6)
4184 hf |= B43_HF_VCORECALC;
4186 if (sprom->boardflags_lo & B43_BFL_XTAL_NOSLOW)
4187 hf |= B43_HF_DSCRQ; /* Disable slowclock requests from ucode. */
4188 #ifdef CONFIG_SSB_DRIVER_PCICORE
4189 if ((bus->bustype == SSB_BUSTYPE_PCI) &&
4190 (bus->pcicore.dev->id.revision <= 10))
4191 hf |= B43_HF_PCISCW; /* PCI slow clock workaround. */
4193 hf &= ~B43_HF_SKCFPUP;
4194 b43_hf_write(dev, hf);
4196 b43_set_retry_limits(dev, B43_DEFAULT_SHORT_RETRY_LIMIT,
4197 B43_DEFAULT_LONG_RETRY_LIMIT);
4198 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SFFBLIM, 3);
4199 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_LFFBLIM, 2);
4201 /* Disable sending probe responses from firmware.
4202 * Setting the MaxTime to one usec will always trigger
4203 * a timeout, so we never send any probe resp.
4204 * A timeout of zero is infinite. */
4205 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 1);
4207 b43_rate_memory_init(dev);
4208 b43_set_phytxctl_defaults(dev);
4210 /* Minimum Contention Window */
4211 if (phy->type == B43_PHYTYPE_B) {
4212 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0x1F);
4214 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0xF);
4216 /* Maximum Contention Window */
4217 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MAXCONT, 0x3FF);
4219 if ((dev->dev->bus->bustype == SSB_BUSTYPE_PCMCIA) || B43_FORCE_PIO) {
4220 dev->__using_pio_transfers = 1;
4221 err = b43_pio_init(dev);
4223 dev->__using_pio_transfers = 0;
4224 err = b43_dma_init(dev);
4229 b43_set_synth_pu_delay(dev, 1);
4230 b43_bluetooth_coext_enable(dev);
4232 ssb_bus_powerup(bus, !(sprom->boardflags_lo & B43_BFL_XTAL_NOSLOW));
4233 b43_upload_card_macaddress(dev);
4234 b43_security_init(dev);
4235 if (!dev->suspend_in_progress)
4238 b43_set_status(dev, B43_STAT_INITIALIZED);
4240 if (!dev->suspend_in_progress)
4248 ssb_bus_may_powerdown(bus);
4249 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
4253 static int b43_op_add_interface(struct ieee80211_hw *hw,
4254 struct ieee80211_if_init_conf *conf)
4256 struct b43_wl *wl = hw_to_b43_wl(hw);
4257 struct b43_wldev *dev;
4258 unsigned long flags;
4259 int err = -EOPNOTSUPP;
4261 /* TODO: allow WDS/AP devices to coexist */
4263 if (conf->type != NL80211_IFTYPE_AP &&
4264 conf->type != NL80211_IFTYPE_MESH_POINT &&
4265 conf->type != NL80211_IFTYPE_STATION &&
4266 conf->type != NL80211_IFTYPE_WDS &&
4267 conf->type != NL80211_IFTYPE_ADHOC)
4270 mutex_lock(&wl->mutex);
4272 goto out_mutex_unlock;
4274 b43dbg(wl, "Adding Interface type %d\n", conf->type);
4276 dev = wl->current_dev;
4278 wl->vif = conf->vif;
4279 wl->if_type = conf->type;
4280 memcpy(wl->mac_addr, conf->mac_addr, ETH_ALEN);
4282 spin_lock_irqsave(&wl->irq_lock, flags);
4283 b43_adjust_opmode(dev);
4284 b43_set_pretbtt(dev);
4285 b43_set_synth_pu_delay(dev, 0);
4286 b43_upload_card_macaddress(dev);
4287 spin_unlock_irqrestore(&wl->irq_lock, flags);
4291 mutex_unlock(&wl->mutex);
4296 static void b43_op_remove_interface(struct ieee80211_hw *hw,
4297 struct ieee80211_if_init_conf *conf)
4299 struct b43_wl *wl = hw_to_b43_wl(hw);
4300 struct b43_wldev *dev = wl->current_dev;
4301 unsigned long flags;
4303 b43dbg(wl, "Removing Interface type %d\n", conf->type);
4305 mutex_lock(&wl->mutex);
4307 B43_WARN_ON(!wl->operating);
4308 B43_WARN_ON(wl->vif != conf->vif);
4313 spin_lock_irqsave(&wl->irq_lock, flags);
4314 b43_adjust_opmode(dev);
4315 memset(wl->mac_addr, 0, ETH_ALEN);
4316 b43_upload_card_macaddress(dev);
4317 spin_unlock_irqrestore(&wl->irq_lock, flags);
4319 mutex_unlock(&wl->mutex);
4322 static int b43_op_start(struct ieee80211_hw *hw)
4324 struct b43_wl *wl = hw_to_b43_wl(hw);
4325 struct b43_wldev *dev = wl->current_dev;
4329 /* Kill all old instance specific information to make sure
4330 * the card won't use it in the short timeframe between start
4331 * and mac80211 reconfiguring it. */
4332 memset(wl->bssid, 0, ETH_ALEN);
4333 memset(wl->mac_addr, 0, ETH_ALEN);
4334 wl->filter_flags = 0;
4335 wl->radiotap_enabled = 0;
4337 wl->beacon0_uploaded = 0;
4338 wl->beacon1_uploaded = 0;
4339 wl->beacon_templates_virgin = 1;
4340 wl->radio_enabled = 1;
4342 mutex_lock(&wl->mutex);
4344 if (b43_status(dev) < B43_STAT_INITIALIZED) {
4345 err = b43_wireless_core_init(dev);
4347 goto out_mutex_unlock;
4351 if (b43_status(dev) < B43_STAT_STARTED) {
4352 err = b43_wireless_core_start(dev);
4355 b43_wireless_core_exit(dev);
4356 goto out_mutex_unlock;
4360 /* XXX: only do if device doesn't support rfkill irq */
4361 wiphy_rfkill_start_polling(hw->wiphy);
4364 mutex_unlock(&wl->mutex);
4369 static void b43_op_stop(struct ieee80211_hw *hw)
4371 struct b43_wl *wl = hw_to_b43_wl(hw);
4372 struct b43_wldev *dev = wl->current_dev;
4374 cancel_work_sync(&(wl->beacon_update_trigger));
4376 mutex_lock(&wl->mutex);
4377 if (b43_status(dev) >= B43_STAT_STARTED)
4378 b43_wireless_core_stop(dev);
4379 b43_wireless_core_exit(dev);
4380 wl->radio_enabled = 0;
4381 mutex_unlock(&wl->mutex);
4383 cancel_work_sync(&(wl->txpower_adjust_work));
4386 static int b43_op_beacon_set_tim(struct ieee80211_hw *hw,
4387 struct ieee80211_sta *sta, bool set)
4389 struct b43_wl *wl = hw_to_b43_wl(hw);
4390 unsigned long flags;
4392 spin_lock_irqsave(&wl->irq_lock, flags);
4393 b43_update_templates(wl);
4394 spin_unlock_irqrestore(&wl->irq_lock, flags);
4399 static void b43_op_sta_notify(struct ieee80211_hw *hw,
4400 struct ieee80211_vif *vif,
4401 enum sta_notify_cmd notify_cmd,
4402 struct ieee80211_sta *sta)
4404 struct b43_wl *wl = hw_to_b43_wl(hw);
4406 B43_WARN_ON(!vif || wl->vif != vif);
4409 static void b43_op_sw_scan_start_notifier(struct ieee80211_hw *hw)
4411 struct b43_wl *wl = hw_to_b43_wl(hw);
4412 struct b43_wldev *dev;
4414 mutex_lock(&wl->mutex);
4415 dev = wl->current_dev;
4416 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) {
4417 /* Disable CFP update during scan on other channels. */
4418 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_SKCFPUP);
4420 mutex_unlock(&wl->mutex);
4423 static void b43_op_sw_scan_complete_notifier(struct ieee80211_hw *hw)
4425 struct b43_wl *wl = hw_to_b43_wl(hw);
4426 struct b43_wldev *dev;
4428 mutex_lock(&wl->mutex);
4429 dev = wl->current_dev;
4430 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) {
4431 /* Re-enable CFP update. */
4432 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_SKCFPUP);
4434 mutex_unlock(&wl->mutex);
4437 static const struct ieee80211_ops b43_hw_ops = {
4439 .conf_tx = b43_op_conf_tx,
4440 .add_interface = b43_op_add_interface,
4441 .remove_interface = b43_op_remove_interface,
4442 .config = b43_op_config,
4443 .bss_info_changed = b43_op_bss_info_changed,
4444 .configure_filter = b43_op_configure_filter,
4445 .set_key = b43_op_set_key,
4446 .get_stats = b43_op_get_stats,
4447 .get_tx_stats = b43_op_get_tx_stats,
4448 .get_tsf = b43_op_get_tsf,
4449 .set_tsf = b43_op_set_tsf,
4450 .start = b43_op_start,
4451 .stop = b43_op_stop,
4452 .set_tim = b43_op_beacon_set_tim,
4453 .sta_notify = b43_op_sta_notify,
4454 .sw_scan_start = b43_op_sw_scan_start_notifier,
4455 .sw_scan_complete = b43_op_sw_scan_complete_notifier,
4456 .rfkill_poll = b43_rfkill_poll,
4459 /* Hard-reset the chip. Do not call this directly.
4460 * Use b43_controller_restart()
4462 static void b43_chip_reset(struct work_struct *work)
4464 struct b43_wldev *dev =
4465 container_of(work, struct b43_wldev, restart_work);
4466 struct b43_wl *wl = dev->wl;
4470 mutex_lock(&wl->mutex);
4472 prev_status = b43_status(dev);
4473 /* Bring the device down... */
4474 if (prev_status >= B43_STAT_STARTED)
4475 b43_wireless_core_stop(dev);
4476 if (prev_status >= B43_STAT_INITIALIZED)
4477 b43_wireless_core_exit(dev);
4479 /* ...and up again. */
4480 if (prev_status >= B43_STAT_INITIALIZED) {
4481 err = b43_wireless_core_init(dev);
4485 if (prev_status >= B43_STAT_STARTED) {
4486 err = b43_wireless_core_start(dev);
4488 b43_wireless_core_exit(dev);
4494 wl->current_dev = NULL; /* Failed to init the dev. */
4495 mutex_unlock(&wl->mutex);
4497 b43err(wl, "Controller restart FAILED\n");
4499 b43info(wl, "Controller restarted\n");
4502 static int b43_setup_bands(struct b43_wldev *dev,
4503 bool have_2ghz_phy, bool have_5ghz_phy)
4505 struct ieee80211_hw *hw = dev->wl->hw;
4508 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &b43_band_2GHz;
4509 if (dev->phy.type == B43_PHYTYPE_N) {
4511 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_nphy;
4514 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_aphy;
4517 dev->phy.supports_2ghz = have_2ghz_phy;
4518 dev->phy.supports_5ghz = have_5ghz_phy;
4523 static void b43_wireless_core_detach(struct b43_wldev *dev)
4525 /* We release firmware that late to not be required to re-request
4526 * is all the time when we reinit the core. */
4527 b43_release_firmware(dev);
4531 static int b43_wireless_core_attach(struct b43_wldev *dev)
4533 struct b43_wl *wl = dev->wl;
4534 struct ssb_bus *bus = dev->dev->bus;
4535 struct pci_dev *pdev = bus->host_pci;
4537 bool have_2ghz_phy = 0, have_5ghz_phy = 0;
4540 /* Do NOT do any device initialization here.
4541 * Do it in wireless_core_init() instead.
4542 * This function is for gathering basic information about the HW, only.
4543 * Also some structs may be set up here. But most likely you want to have
4544 * that in core_init(), too.
4547 err = ssb_bus_powerup(bus, 0);
4549 b43err(wl, "Bus powerup failed\n");
4552 /* Get the PHY type. */
4553 if (dev->dev->id.revision >= 5) {
4556 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
4557 have_2ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY);
4558 have_5ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_5GHZ_PHY);
4562 dev->phy.gmode = have_2ghz_phy;
4563 dev->phy.radio_on = 1;
4564 tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
4565 b43_wireless_core_reset(dev, tmp);
4567 err = b43_phy_versioning(dev);
4570 /* Check if this device supports multiband. */
4572 (pdev->device != 0x4312 &&
4573 pdev->device != 0x4319 && pdev->device != 0x4324)) {
4574 /* No multiband support. */
4577 switch (dev->phy.type) {
4583 case B43_PHYTYPE_LP:
4590 if (dev->phy.type == B43_PHYTYPE_A) {
4592 b43err(wl, "IEEE 802.11a devices are unsupported\n");
4596 if (1 /* disable A-PHY */) {
4597 /* FIXME: For now we disable the A-PHY on multi-PHY devices. */
4598 if (dev->phy.type != B43_PHYTYPE_N) {
4604 err = b43_phy_allocate(dev);
4608 dev->phy.gmode = have_2ghz_phy;
4609 tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
4610 b43_wireless_core_reset(dev, tmp);
4612 err = b43_validate_chipaccess(dev);
4615 err = b43_setup_bands(dev, have_2ghz_phy, have_5ghz_phy);
4619 /* Now set some default "current_dev" */
4620 if (!wl->current_dev)
4621 wl->current_dev = dev;
4622 INIT_WORK(&dev->restart_work, b43_chip_reset);
4624 dev->phy.ops->switch_analog(dev, 0);
4625 ssb_device_disable(dev->dev, 0);
4626 ssb_bus_may_powerdown(bus);
4634 ssb_bus_may_powerdown(bus);
4638 static void b43_one_core_detach(struct ssb_device *dev)
4640 struct b43_wldev *wldev;
4643 /* Do not cancel ieee80211-workqueue based work here.
4644 * See comment in b43_remove(). */
4646 wldev = ssb_get_drvdata(dev);
4648 b43_debugfs_remove_device(wldev);
4649 b43_wireless_core_detach(wldev);
4650 list_del(&wldev->list);
4652 ssb_set_drvdata(dev, NULL);
4656 static int b43_one_core_attach(struct ssb_device *dev, struct b43_wl *wl)
4658 struct b43_wldev *wldev;
4659 struct pci_dev *pdev;
4662 if (!list_empty(&wl->devlist)) {
4663 /* We are not the first core on this chip. */
4664 pdev = dev->bus->host_pci;
4665 /* Only special chips support more than one wireless
4666 * core, although some of the other chips have more than
4667 * one wireless core as well. Check for this and
4671 ((pdev->device != 0x4321) &&
4672 (pdev->device != 0x4313) && (pdev->device != 0x431A))) {
4673 b43dbg(wl, "Ignoring unconnected 802.11 core\n");
4678 wldev = kzalloc(sizeof(*wldev), GFP_KERNEL);
4684 b43_set_status(wldev, B43_STAT_UNINIT);
4685 wldev->bad_frames_preempt = modparam_bad_frames_preempt;
4686 tasklet_init(&wldev->isr_tasklet,
4687 (void (*)(unsigned long))b43_interrupt_tasklet,
4688 (unsigned long)wldev);
4689 INIT_LIST_HEAD(&wldev->list);
4691 err = b43_wireless_core_attach(wldev);
4693 goto err_kfree_wldev;
4695 list_add(&wldev->list, &wl->devlist);
4697 ssb_set_drvdata(dev, wldev);
4698 b43_debugfs_add_device(wldev);
4708 #define IS_PDEV(pdev, _vendor, _device, _subvendor, _subdevice) ( \
4709 (pdev->vendor == PCI_VENDOR_ID_##_vendor) && \
4710 (pdev->device == _device) && \
4711 (pdev->subsystem_vendor == PCI_VENDOR_ID_##_subvendor) && \
4712 (pdev->subsystem_device == _subdevice) )
4714 static void b43_sprom_fixup(struct ssb_bus *bus)
4716 struct pci_dev *pdev;
4718 /* boardflags workarounds */
4719 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_DELL &&
4720 bus->chip_id == 0x4301 && bus->boardinfo.rev == 0x74)
4721 bus->sprom.boardflags_lo |= B43_BFL_BTCOEXIST;
4722 if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
4723 bus->boardinfo.type == 0x4E && bus->boardinfo.rev > 0x40)
4724 bus->sprom.boardflags_lo |= B43_BFL_PACTRL;
4725 if (bus->bustype == SSB_BUSTYPE_PCI) {
4726 pdev = bus->host_pci;
4727 if (IS_PDEV(pdev, BROADCOM, 0x4318, ASUSTEK, 0x100F) ||
4728 IS_PDEV(pdev, BROADCOM, 0x4320, DELL, 0x0003) ||
4729 IS_PDEV(pdev, BROADCOM, 0x4320, HP, 0x12f8) ||
4730 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0015) ||
4731 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0014) ||
4732 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0013) ||
4733 IS_PDEV(pdev, BROADCOM, 0x4320, MOTOROLA, 0x7010))
4734 bus->sprom.boardflags_lo &= ~B43_BFL_BTCOEXIST;
4738 static void b43_wireless_exit(struct ssb_device *dev, struct b43_wl *wl)
4740 struct ieee80211_hw *hw = wl->hw;
4742 ssb_set_devtypedata(dev, NULL);
4743 ieee80211_free_hw(hw);
4746 static int b43_wireless_init(struct ssb_device *dev)
4748 struct ssb_sprom *sprom = &dev->bus->sprom;
4749 struct ieee80211_hw *hw;
4753 b43_sprom_fixup(dev->bus);
4755 hw = ieee80211_alloc_hw(sizeof(*wl), &b43_hw_ops);
4757 b43err(NULL, "Could not allocate ieee80211 device\n");
4760 wl = hw_to_b43_wl(hw);
4763 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
4764 IEEE80211_HW_SIGNAL_DBM |
4765 IEEE80211_HW_NOISE_DBM;
4767 hw->wiphy->interface_modes =
4768 BIT(NL80211_IFTYPE_AP) |
4769 BIT(NL80211_IFTYPE_MESH_POINT) |
4770 BIT(NL80211_IFTYPE_STATION) |
4771 BIT(NL80211_IFTYPE_WDS) |
4772 BIT(NL80211_IFTYPE_ADHOC);
4774 hw->queues = modparam_qos ? 4 : 1;
4775 wl->mac80211_initially_registered_queues = hw->queues;
4777 SET_IEEE80211_DEV(hw, dev->dev);
4778 if (is_valid_ether_addr(sprom->et1mac))
4779 SET_IEEE80211_PERM_ADDR(hw, sprom->et1mac);
4781 SET_IEEE80211_PERM_ADDR(hw, sprom->il0mac);
4783 /* Initialize struct b43_wl */
4785 spin_lock_init(&wl->irq_lock);
4786 rwlock_init(&wl->tx_lock);
4787 spin_lock_init(&wl->leds_lock);
4788 spin_lock_init(&wl->shm_lock);
4789 mutex_init(&wl->mutex);
4790 INIT_LIST_HEAD(&wl->devlist);
4791 INIT_WORK(&wl->beacon_update_trigger, b43_beacon_update_trigger_work);
4792 INIT_WORK(&wl->txpower_adjust_work, b43_phy_txpower_adjust_work);
4794 ssb_set_devtypedata(dev, wl);
4795 b43info(wl, "Broadcom %04X WLAN found (core revision %u)\n",
4796 dev->bus->chip_id, dev->id.revision);
4802 static int b43_probe(struct ssb_device *dev, const struct ssb_device_id *id)
4808 wl = ssb_get_devtypedata(dev);
4810 /* Probing the first core. Must setup common struct b43_wl */
4812 err = b43_wireless_init(dev);
4815 wl = ssb_get_devtypedata(dev);
4818 err = b43_one_core_attach(dev, wl);
4820 goto err_wireless_exit;
4823 err = ieee80211_register_hw(wl->hw);
4825 goto err_one_core_detach;
4831 err_one_core_detach:
4832 b43_one_core_detach(dev);
4835 b43_wireless_exit(dev, wl);
4839 static void b43_remove(struct ssb_device *dev)
4841 struct b43_wl *wl = ssb_get_devtypedata(dev);
4842 struct b43_wldev *wldev = ssb_get_drvdata(dev);
4844 /* We must cancel any work here before unregistering from ieee80211,
4845 * as the ieee80211 unreg will destroy the workqueue. */
4846 cancel_work_sync(&wldev->restart_work);
4849 if (wl->current_dev == wldev) {
4850 /* Restore the queues count before unregistering, because firmware detect
4851 * might have modified it. Restoring is important, so the networking
4852 * stack can properly free resources. */
4853 wl->hw->queues = wl->mac80211_initially_registered_queues;
4854 ieee80211_unregister_hw(wl->hw);
4857 b43_one_core_detach(dev);
4859 if (list_empty(&wl->devlist)) {
4860 /* Last core on the chip unregistered.
4861 * We can destroy common struct b43_wl.
4863 b43_wireless_exit(dev, wl);
4867 /* Perform a hardware reset. This can be called from any context. */
4868 void b43_controller_restart(struct b43_wldev *dev, const char *reason)
4870 /* Must avoid requeueing, if we are in shutdown. */
4871 if (b43_status(dev) < B43_STAT_INITIALIZED)
4873 b43info(dev->wl, "Controller RESET (%s) ...\n", reason);
4874 ieee80211_queue_work(dev->wl->hw, &dev->restart_work);
4879 static int b43_suspend(struct ssb_device *dev, pm_message_t state)
4881 struct b43_wldev *wldev = ssb_get_drvdata(dev);
4882 struct b43_wl *wl = wldev->wl;
4884 b43dbg(wl, "Suspending...\n");
4886 mutex_lock(&wl->mutex);
4887 wldev->suspend_in_progress = true;
4888 wldev->suspend_init_status = b43_status(wldev);
4889 if (wldev->suspend_init_status >= B43_STAT_STARTED)
4890 b43_wireless_core_stop(wldev);
4891 if (wldev->suspend_init_status >= B43_STAT_INITIALIZED)
4892 b43_wireless_core_exit(wldev);
4893 mutex_unlock(&wl->mutex);
4895 b43dbg(wl, "Device suspended.\n");
4900 static int b43_resume(struct ssb_device *dev)
4902 struct b43_wldev *wldev = ssb_get_drvdata(dev);
4903 struct b43_wl *wl = wldev->wl;
4906 b43dbg(wl, "Resuming...\n");
4908 mutex_lock(&wl->mutex);
4909 if (wldev->suspend_init_status >= B43_STAT_INITIALIZED) {
4910 err = b43_wireless_core_init(wldev);
4912 b43err(wl, "Resume failed at core init\n");
4916 if (wldev->suspend_init_status >= B43_STAT_STARTED) {
4917 err = b43_wireless_core_start(wldev);
4919 b43_leds_exit(wldev);
4920 b43_rng_exit(wldev->wl);
4921 b43_wireless_core_exit(wldev);
4922 b43err(wl, "Resume failed at core start\n");
4926 b43dbg(wl, "Device resumed.\n");
4928 wldev->suspend_in_progress = false;
4929 mutex_unlock(&wl->mutex);
4933 #else /* CONFIG_PM */
4934 # define b43_suspend NULL
4935 # define b43_resume NULL
4936 #endif /* CONFIG_PM */
4938 static struct ssb_driver b43_ssb_driver = {
4939 .name = KBUILD_MODNAME,
4940 .id_table = b43_ssb_tbl,
4942 .remove = b43_remove,
4943 .suspend = b43_suspend,
4944 .resume = b43_resume,
4947 static void b43_print_driverinfo(void)
4949 const char *feat_pci = "", *feat_pcmcia = "", *feat_nphy = "",
4952 #ifdef CONFIG_B43_PCI_AUTOSELECT
4955 #ifdef CONFIG_B43_PCMCIA
4958 #ifdef CONFIG_B43_NPHY
4961 #ifdef CONFIG_B43_LEDS
4964 printk(KERN_INFO "Broadcom 43xx driver loaded "
4965 "[ Features: %s%s%s%s, Firmware-ID: "
4966 B43_SUPPORTED_FIRMWARE_ID " ]\n",
4967 feat_pci, feat_pcmcia, feat_nphy,
4971 static int __init b43_init(void)
4976 err = b43_pcmcia_init();
4979 err = ssb_driver_register(&b43_ssb_driver);
4981 goto err_pcmcia_exit;
4982 b43_print_driverinfo();
4993 static void __exit b43_exit(void)
4995 ssb_driver_unregister(&b43_ssb_driver);
5000 module_init(b43_init)
5001 module_exit(b43_exit)