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   1 /*
   2
   3   Broadcom B43 wireless driver
   4
   5   Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
   6   Copyright (c) 2005 Stefano Brivio <stefano.brivio@polimi.it>
   7   Copyright (c) 2005, 2006 Michael Buesch <mb@bu3sch.de>
   8   Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
   9   Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
  10
  11   Some parts of the code in this file are derived from the ipw2200
  12   driver  Copyright(c) 2003 - 2004 Intel Corporation.
  13
  14   This program is free software; you can redistribute it and/or modify
  15   it under the terms of the GNU General Public License as published by
  16   the Free Software Foundation; either version 2 of the License, or
  17   (at your option) any later version.
  18
  19   This program is distributed in the hope that it will be useful,
  20   but WITHOUT ANY WARRANTY; without even the implied warranty of
  21   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22   GNU General Public License for more details.
  23
  24   You should have received a copy of the GNU General Public License
  25   along with this program; see the file COPYING.  If not, write to
  26   the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
  27   Boston, MA 02110-1301, USA.
  28
  29 */
  30
  31 #include <linux/delay.h>
  32 #include <linux/init.h>
  33 #include <linux/moduleparam.h>
  34 #include <linux/if_arp.h>
  35 #include <linux/etherdevice.h>
  36 #include <linux/version.h>
  37 #include <linux/firmware.h>
  38 #include <linux/wireless.h>
  39 #include <linux/workqueue.h>
  40 #include <linux/skbuff.h>
  41 #include <linux/dma-mapping.h>
  42 #include <asm/unaligned.h>
  43
  44 #include "b43.h"
  45 #include "main.h"
  46 #include "debugfs.h"
  47 #include "phy.h"
  48 #include "dma.h"
  49 #include "sysfs.h"
  50 #include "xmit.h"
  51 #include "lo.h"
  52 #include "pcmcia.h"
  53
  54 MODULE_DESCRIPTION("Broadcom B43 wireless driver");
  55 MODULE_AUTHOR("Martin Langer");
  56 MODULE_AUTHOR("Stefano Brivio");
  57 MODULE_AUTHOR("Michael Buesch");
  58 MODULE_LICENSE("GPL");
  59
  60
  61 static int modparam_bad_frames_preempt;
  62 module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
  63 MODULE_PARM_DESC(bad_frames_preempt,
  64                  "enable(1) / disable(0) Bad Frames Preemption");
  65
  66 static char modparam_fwpostfix[16];
  67 module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444);
  68 MODULE_PARM_DESC(fwpostfix, "Postfix for the .fw files to load.");
  69
  70 static int modparam_hwpctl;
  71 module_param_named(hwpctl, modparam_hwpctl, int, 0444);
  72 MODULE_PARM_DESC(hwpctl, "Enable hardware-side power control (default off)");
  73
  74 static int modparam_nohwcrypt;
  75 module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
  76 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
  77
  78 static const struct ssb_device_id b43_ssb_tbl[] = {
  79         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 5),
  80         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 6),
  81         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 7),
  82         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 9),
  83         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 10),
  84         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 11),
  85         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 13),
  86         SSB_DEVTABLE_END
  87 };
  88
  89 MODULE_DEVICE_TABLE(ssb, b43_ssb_tbl);
  90
  91 /* Channel and ratetables are shared for all devices.
  92  * They can't be const, because ieee80211 puts some precalculated
  93  * data in there. This data is the same for all devices, so we don't
  94  * get concurrency issues */
  95 #define RATETAB_ENT(_rateid, _flags) \
  96         {                                                       \
  97                 .rate   = B43_RATE_TO_BASE100KBPS(_rateid),     \
  98                 .val    = (_rateid),                            \
  99                 .val2   = (_rateid),                            \
 100                 .flags  = (_flags),                             \
 101         }
 102 static struct ieee80211_rate __b43_ratetable[] = {
 103         RATETAB_ENT(B43_CCK_RATE_1MB, IEEE80211_RATE_CCK),
 104         RATETAB_ENT(B43_CCK_RATE_2MB, IEEE80211_RATE_CCK_2),
 105         RATETAB_ENT(B43_CCK_RATE_5MB, IEEE80211_RATE_CCK_2),
 106         RATETAB_ENT(B43_CCK_RATE_11MB, IEEE80211_RATE_CCK_2),
 107         RATETAB_ENT(B43_OFDM_RATE_6MB, IEEE80211_RATE_OFDM),
 108         RATETAB_ENT(B43_OFDM_RATE_9MB, IEEE80211_RATE_OFDM),
 109         RATETAB_ENT(B43_OFDM_RATE_12MB, IEEE80211_RATE_OFDM),
 110         RATETAB_ENT(B43_OFDM_RATE_18MB, IEEE80211_RATE_OFDM),
 111         RATETAB_ENT(B43_OFDM_RATE_24MB, IEEE80211_RATE_OFDM),
 112         RATETAB_ENT(B43_OFDM_RATE_36MB, IEEE80211_RATE_OFDM),
 113         RATETAB_ENT(B43_OFDM_RATE_48MB, IEEE80211_RATE_OFDM),
 114         RATETAB_ENT(B43_OFDM_RATE_54MB, IEEE80211_RATE_OFDM),
 115 };
 116
 117 #define b43_a_ratetable         (__b43_ratetable + 4)
 118 #define b43_a_ratetable_size    8
 119 #define b43_b_ratetable         (__b43_ratetable + 0)
 120 #define b43_b_ratetable_size    4
 121 #define b43_g_ratetable         (__b43_ratetable + 0)
 122 #define b43_g_ratetable_size    12
 123
 124 #define CHANTAB_ENT(_chanid, _freq) \
 125         {                                                       \
 126                 .chan   = (_chanid),                            \
 127                 .freq   = (_freq),                              \
 128                 .val    = (_chanid),                            \
 129                 .flag   = IEEE80211_CHAN_W_SCAN |               \
 130                           IEEE80211_CHAN_W_ACTIVE_SCAN |        \
 131                           IEEE80211_CHAN_W_IBSS,                \
 132                 .power_level    = 0xFF,                         \
 133                 .antenna_max    = 0xFF,                         \
 134         }
 135 static struct ieee80211_channel b43_2ghz_chantable[] = {
 136         CHANTAB_ENT(1, 2412),
 137         CHANTAB_ENT(2, 2417),
 138         CHANTAB_ENT(3, 2422),
 139         CHANTAB_ENT(4, 2427),
 140         CHANTAB_ENT(5, 2432),
 141         CHANTAB_ENT(6, 2437),
 142         CHANTAB_ENT(7, 2442),
 143         CHANTAB_ENT(8, 2447),
 144         CHANTAB_ENT(9, 2452),
 145         CHANTAB_ENT(10, 2457),
 146         CHANTAB_ENT(11, 2462),
 147         CHANTAB_ENT(12, 2467),
 148         CHANTAB_ENT(13, 2472),
 149         CHANTAB_ENT(14, 2484),
 150 };
 151 #define b43_2ghz_chantable_size ARRAY_SIZE(b43_2ghz_chantable)
 152
 153 #if 0
 154 static struct ieee80211_channel b43_5ghz_chantable[] = {
 155         CHANTAB_ENT(36, 5180),
 156         CHANTAB_ENT(40, 5200),
 157         CHANTAB_ENT(44, 5220),
 158         CHANTAB_ENT(48, 5240),
 159         CHANTAB_ENT(52, 5260),
 160         CHANTAB_ENT(56, 5280),
 161         CHANTAB_ENT(60, 5300),
 162         CHANTAB_ENT(64, 5320),
 163         CHANTAB_ENT(149, 5745),
 164         CHANTAB_ENT(153, 5765),
 165         CHANTAB_ENT(157, 5785),
 166         CHANTAB_ENT(161, 5805),
 167         CHANTAB_ENT(165, 5825),
 168 };
 169 #define b43_5ghz_chantable_size ARRAY_SIZE(b43_5ghz_chantable)
 170 #endif
 171
 172 static void b43_wireless_core_exit(struct b43_wldev *dev);
 173 static int b43_wireless_core_init(struct b43_wldev *dev);
 174 static void b43_wireless_core_stop(struct b43_wldev *dev);
 175 static int b43_wireless_core_start(struct b43_wldev *dev);
 176
 177 static int b43_ratelimit(struct b43_wl *wl)
 178 {
 179         if (!wl || !wl->current_dev)
 180                 return 1;
 181         if (b43_status(wl->current_dev) < B43_STAT_STARTED)
 182                 return 1;
 183         /* We are up and running.
 184          * Ratelimit the messages to avoid DoS over the net. */
 185         return net_ratelimit();
 186 }
 187
 188 void b43info(struct b43_wl *wl, const char *fmt, ...)
 189 {
 190         va_list args;
 191
 192         if (!b43_ratelimit(wl))
 193                 return;
 194         va_start(args, fmt);
 195         printk(KERN_INFO "b43-%s: ",
 196                (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
 197         vprintk(fmt, args);
 198         va_end(args);
 199 }
 200
 201 void b43err(struct b43_wl *wl, const char *fmt, ...)
 202 {
 203         va_list args;
 204
 205         if (!b43_ratelimit(wl))
 206                 return;
 207         va_start(args, fmt);
 208         printk(KERN_ERR "b43-%s ERROR: ",
 209                (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
 210         vprintk(fmt, args);
 211         va_end(args);
 212 }
 213
 214 void b43warn(struct b43_wl *wl, const char *fmt, ...)
 215 {
 216         va_list args;
 217
 218         if (!b43_ratelimit(wl))
 219                 return;
 220         va_start(args, fmt);
 221         printk(KERN_WARNING "b43-%s warning: ",
 222                (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
 223         vprintk(fmt, args);
 224         va_end(args);
 225 }
 226
 227 #if B43_DEBUG
 228 void b43dbg(struct b43_wl *wl, const char *fmt, ...)
 229 {
 230         va_list args;
 231
 232         va_start(args, fmt);
 233         printk(KERN_DEBUG "b43-%s debug: ",
 234                (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
 235         vprintk(fmt, args);
 236         va_end(args);
 237 }
 238 #endif /* DEBUG */
 239
 240 static void b43_ram_write(struct b43_wldev *dev, u16 offset, u32 val)
 241 {
 242         u32 macctl;
 243
 244         B43_WARN_ON(offset % 4 != 0);
 245
 246         macctl = b43_read32(dev, B43_MMIO_MACCTL);
 247         if (macctl & B43_MACCTL_BE)
 248                 val = swab32(val);
 249
 250         b43_write32(dev, B43_MMIO_RAM_CONTROL, offset);
 251         mmiowb();
 252         b43_write32(dev, B43_MMIO_RAM_DATA, val);
 253 }
 254
 255 static inline void b43_shm_control_word(struct b43_wldev *dev,
 256                                         u16 routing, u16 offset)
 257 {
 258         u32 control;
 259
 260         /* "offset" is the WORD offset. */
 261         control = routing;
 262         control <<= 16;
 263         control |= offset;
 264         b43_write32(dev, B43_MMIO_SHM_CONTROL, control);
 265 }
 266
 267 u32 b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset)
 268 {
 269         struct b43_wl *wl = dev->wl;
 270         unsigned long flags;
 271         u32 ret;
 272
 273         spin_lock_irqsave(&wl->shm_lock, flags);
 274         if (routing == B43_SHM_SHARED) {
 275                 B43_WARN_ON(offset & 0x0001);
 276                 if (offset & 0x0003) {
 277                         /* Unaligned access */
 278                         b43_shm_control_word(dev, routing, offset >> 2);
 279                         ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
 280                         ret <<= 16;
 281                         b43_shm_control_word(dev, routing, (offset >> 2) + 1);
 282                         ret |= b43_read16(dev, B43_MMIO_SHM_DATA);
 283
 284                         goto out;
 285                 }
 286                 offset >>= 2;
 287         }
 288         b43_shm_control_word(dev, routing, offset);
 289         ret = b43_read32(dev, B43_MMIO_SHM_DATA);
 290 out:
 291         spin_unlock_irqrestore(&wl->shm_lock, flags);
 292
 293         return ret;
 294 }
 295
 296 u16 b43_shm_read16(struct b43_wldev * dev, u16 routing, u16 offset)
 297 {
 298         struct b43_wl *wl = dev->wl;
 299         unsigned long flags;
 300         u16 ret;
 301
 302         spin_lock_irqsave(&wl->shm_lock, flags);
 303         if (routing == B43_SHM_SHARED) {
 304                 B43_WARN_ON(offset & 0x0001);
 305                 if (offset & 0x0003) {
 306                         /* Unaligned access */
 307                         b43_shm_control_word(dev, routing, offset >> 2);
 308                         ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
 309
 310                         goto out;
 311                 }
 312                 offset >>= 2;
 313         }
 314         b43_shm_control_word(dev, routing, offset);
 315         ret = b43_read16(dev, B43_MMIO_SHM_DATA);
 316 out:
 317         spin_unlock_irqrestore(&wl->shm_lock, flags);
 318
 319         return ret;
 320 }
 321
 322 void b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value)
 323 {
 324         struct b43_wl *wl = dev->wl;
 325         unsigned long flags;
 326
 327         spin_lock_irqsave(&wl->shm_lock, flags);
 328         if (routing == B43_SHM_SHARED) {
 329                 B43_WARN_ON(offset & 0x0001);
 330                 if (offset & 0x0003) {
 331                         /* Unaligned access */
 332                         b43_shm_control_word(dev, routing, offset >> 2);
 333                         b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED,
 334                                     (value >> 16) & 0xffff);
 335                         b43_shm_control_word(dev, routing, (offset >> 2) + 1);
 336                         b43_write16(dev, B43_MMIO_SHM_DATA, value & 0xffff);
 337                         goto out;
 338                 }
 339                 offset >>= 2;
 340         }
 341         b43_shm_control_word(dev, routing, offset);
 342         b43_write32(dev, B43_MMIO_SHM_DATA, value);
 343 out:
 344         spin_unlock_irqrestore(&wl->shm_lock, flags);
 345 }
 346
 347 void b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value)
 348 {
 349         struct b43_wl *wl = dev->wl;
 350         unsigned long flags;
 351
 352         spin_lock_irqsave(&wl->shm_lock, flags);
 353         if (routing == B43_SHM_SHARED) {
 354                 B43_WARN_ON(offset & 0x0001);
 355                 if (offset & 0x0003) {
 356                         /* Unaligned access */
 357                         b43_shm_control_word(dev, routing, offset >> 2);
 358                         b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, value);
 359                         goto out;
 360                 }
 361                 offset >>= 2;
 362         }
 363         b43_shm_control_word(dev, routing, offset);
 364         b43_write16(dev, B43_MMIO_SHM_DATA, value);
 365 out:
 366         spin_unlock_irqrestore(&wl->shm_lock, flags);
 367 }
 368
 369 /* Read HostFlags */
 370 u32 b43_hf_read(struct b43_wldev * dev)
 371 {
 372         u32 ret;
 373
 374         ret = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI);
 375         ret <<= 16;
 376         ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO);
 377
 378         return ret;
 379 }
 380
 381 /* Write HostFlags */
 382 void b43_hf_write(struct b43_wldev *dev, u32 value)
 383 {
 384         b43_shm_write16(dev, B43_SHM_SHARED,
 385                         B43_SHM_SH_HOSTFLO, (value & 0x0000FFFF));
 386         b43_shm_write16(dev, B43_SHM_SHARED,
 387                         B43_SHM_SH_HOSTFHI, ((value & 0xFFFF0000) >> 16));
 388 }
 389
 390 void b43_tsf_read(struct b43_wldev *dev, u64 * tsf)
 391 {
 392         /* We need to be careful. As we read the TSF from multiple
 393          * registers, we should take care of register overflows.
 394          * In theory, the whole tsf read process should be atomic.
 395          * We try to be atomic here, by restaring the read process,
 396          * if any of the high registers changed (overflew).
 397          */
 398         if (dev->dev->id.revision >= 3) {
 399                 u32 low, high, high2;
 400
 401                 do {
 402                         high = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
 403                         low = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_LOW);
 404                         high2 = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
 405                 } while (unlikely(high != high2));
 406
 407                 *tsf = high;
 408                 *tsf <<= 32;
 409                 *tsf |= low;
 410         } else {
 411                 u64 tmp;
 412                 u16 v0, v1, v2, v3;
 413                 u16 test1, test2, test3;
 414
 415                 do {
 416                         v3 = b43_read16(dev, B43_MMIO_TSF_3);
 417                         v2 = b43_read16(dev, B43_MMIO_TSF_2);
 418                         v1 = b43_read16(dev, B43_MMIO_TSF_1);
 419                         v0 = b43_read16(dev, B43_MMIO_TSF_0);
 420
 421                         test3 = b43_read16(dev, B43_MMIO_TSF_3);
 422                         test2 = b43_read16(dev, B43_MMIO_TSF_2);
 423                         test1 = b43_read16(dev, B43_MMIO_TSF_1);
 424                 } while (v3 != test3 || v2 != test2 || v1 != test1);
 425
 426                 *tsf = v3;
 427                 *tsf <<= 48;
 428                 tmp = v2;
 429                 tmp <<= 32;
 430                 *tsf |= tmp;
 431                 tmp = v1;
 432                 tmp <<= 16;
 433                 *tsf |= tmp;
 434                 *tsf |= v0;
 435         }
 436 }
 437
 438 static void b43_time_lock(struct b43_wldev *dev)
 439 {
 440         u32 macctl;
 441
 442         macctl = b43_read32(dev, B43_MMIO_MACCTL);
 443         macctl |= B43_MACCTL_TBTTHOLD;
 444         b43_write32(dev, B43_MMIO_MACCTL, macctl);
 445         /* Commit the write */
 446         b43_read32(dev, B43_MMIO_MACCTL);
 447 }
 448
 449 static void b43_time_unlock(struct b43_wldev *dev)
 450 {
 451         u32 macctl;
 452
 453         macctl = b43_read32(dev, B43_MMIO_MACCTL);
 454         macctl &= ~B43_MACCTL_TBTTHOLD;
 455         b43_write32(dev, B43_MMIO_MACCTL, macctl);
 456         /* Commit the write */
 457         b43_read32(dev, B43_MMIO_MACCTL);
 458 }
 459
 460 static void b43_tsf_write_locked(struct b43_wldev *dev, u64 tsf)
 461 {
 462         /* Be careful with the in-progress timer.
 463          * First zero out the low register, so we have a full
 464          * register-overflow duration to complete the operation.
 465          */
 466         if (dev->dev->id.revision >= 3) {
 467                 u32 lo = (tsf & 0x00000000FFFFFFFFULL);
 468                 u32 hi = (tsf & 0xFFFFFFFF00000000ULL) >> 32;
 469
 470                 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, 0);
 471                 mmiowb();
 472                 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_HIGH, hi);
 473                 mmiowb();
 474                 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, lo);
 475         } else {
 476                 u16 v0 = (tsf & 0x000000000000FFFFULL);
 477                 u16 v1 = (tsf & 0x00000000FFFF0000ULL) >> 16;
 478                 u16 v2 = (tsf & 0x0000FFFF00000000ULL) >> 32;
 479                 u16 v3 = (tsf & 0xFFFF000000000000ULL) >> 48;
 480
 481                 b43_write16(dev, B43_MMIO_TSF_0, 0);
 482                 mmiowb();
 483                 b43_write16(dev, B43_MMIO_TSF_3, v3);
 484                 mmiowb();
 485                 b43_write16(dev, B43_MMIO_TSF_2, v2);
 486                 mmiowb();
 487                 b43_write16(dev, B43_MMIO_TSF_1, v1);
 488                 mmiowb();
 489                 b43_write16(dev, B43_MMIO_TSF_0, v0);
 490         }
 491 }
 492
 493 void b43_tsf_write(struct b43_wldev *dev, u64 tsf)
 494 {
 495         b43_time_lock(dev);
 496         b43_tsf_write_locked(dev, tsf);
 497         b43_time_unlock(dev);
 498 }
 499
 500 static
 501 void b43_macfilter_set(struct b43_wldev *dev, u16 offset, const u8 * mac)
 502 {
 503         static const u8 zero_addr[ETH_ALEN] = { 0 };
 504         u16 data;
 505
 506         if (!mac)
 507                 mac = zero_addr;
 508
 509         offset |= 0x0020;
 510         b43_write16(dev, B43_MMIO_MACFILTER_CONTROL, offset);
 511
 512         data = mac[0];
 513         data |= mac[1] << 8;
 514         b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
 515         data = mac[2];
 516         data |= mac[3] << 8;
 517         b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
 518         data = mac[4];
 519         data |= mac[5] << 8;
 520         b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
 521 }
 522
 523 static void b43_write_mac_bssid_templates(struct b43_wldev *dev)
 524 {
 525         const u8 *mac;
 526         const u8 *bssid;
 527         u8 mac_bssid[ETH_ALEN * 2];
 528         int i;
 529         u32 tmp;
 530
 531         bssid = dev->wl->bssid;
 532         mac = dev->wl->mac_addr;
 533
 534         b43_macfilter_set(dev, B43_MACFILTER_BSSID, bssid);
 535
 536         memcpy(mac_bssid, mac, ETH_ALEN);
 537         memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
 538
 539         /* Write our MAC address and BSSID to template ram */
 540         for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) {
 541                 tmp = (u32) (mac_bssid[i + 0]);
 542                 tmp |= (u32) (mac_bssid[i + 1]) << 8;
 543                 tmp |= (u32) (mac_bssid[i + 2]) << 16;
 544                 tmp |= (u32) (mac_bssid[i + 3]) << 24;
 545                 b43_ram_write(dev, 0x20 + i, tmp);
 546         }
 547 }
 548
 549 static void b43_upload_card_macaddress(struct b43_wldev *dev)
 550 {
 551         b43_write_mac_bssid_templates(dev);
 552         b43_macfilter_set(dev, B43_MACFILTER_SELF, dev->wl->mac_addr);
 553 }
 554
 555 static void b43_set_slot_time(struct b43_wldev *dev, u16 slot_time)
 556 {
 557         /* slot_time is in usec. */
 558         if (dev->phy.type != B43_PHYTYPE_G)
 559                 return;
 560         b43_write16(dev, 0x684, 510 + slot_time);
 561         b43_shm_write16(dev, B43_SHM_SHARED, 0x0010, slot_time);
 562 }
 563
 564 static void b43_short_slot_timing_enable(struct b43_wldev *dev)
 565 {
 566         b43_set_slot_time(dev, 9);
 567         dev->short_slot = 1;
 568 }
 569
 570 static void b43_short_slot_timing_disable(struct b43_wldev *dev)
 571 {
 572         b43_set_slot_time(dev, 20);
 573         dev->short_slot = 0;
 574 }
 575
 576 /* Enable a Generic IRQ. "mask" is the mask of which IRQs to enable.
 577  * Returns the _previously_ enabled IRQ mask.
 578  */
 579 static inline u32 b43_interrupt_enable(struct b43_wldev *dev, u32 mask)
 580 {
 581         u32 old_mask;
 582
 583         old_mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
 584         b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, old_mask | mask);
 585
 586         return old_mask;
 587 }
 588
 589 /* Disable a Generic IRQ. "mask" is the mask of which IRQs to disable.
 590  * Returns the _previously_ enabled IRQ mask.
 591  */
 592 static inline u32 b43_interrupt_disable(struct b43_wldev *dev, u32 mask)
 593 {
 594         u32 old_mask;
 595
 596         old_mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
 597         b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, old_mask & ~mask);
 598
 599         return old_mask;
 600 }
 601
 602 /* Synchronize IRQ top- and bottom-half.
 603  * IRQs must be masked before calling this.
 604  * This must not be called with the irq_lock held.
 605  */
 606 static void b43_synchronize_irq(struct b43_wldev *dev)
 607 {
 608         synchronize_irq(dev->dev->irq);
 609         tasklet_kill(&dev->isr_tasklet);
 610 }
 611
 612 /* DummyTransmission function, as documented on
 613  * http://bcm-specs.sipsolutions.net/DummyTransmission
 614  */
 615 void b43_dummy_transmission(struct b43_wldev *dev)
 616 {
 617         struct b43_phy *phy = &dev->phy;
 618         unsigned int i, max_loop;
 619         u16 value;
 620         u32 buffer[5] = {
 621                 0x00000000,
 622                 0x00D40000,
 623                 0x00000000,
 624                 0x01000000,
 625                 0x00000000,
 626         };
 627
 628         switch (phy->type) {
 629         case B43_PHYTYPE_A:
 630                 max_loop = 0x1E;
 631                 buffer[0] = 0x000201CC;
 632                 break;
 633         case B43_PHYTYPE_B:
 634         case B43_PHYTYPE_G:
 635                 max_loop = 0xFA;
 636                 buffer[0] = 0x000B846E;
 637                 break;
 638         default:
 639                 B43_WARN_ON(1);
 640                 return;
 641         }
 642
 643         for (i = 0; i < 5; i++)
 644                 b43_ram_write(dev, i * 4, buffer[i]);
 645
 646         /* Commit writes */
 647         b43_read32(dev, B43_MMIO_MACCTL);
 648
 649         b43_write16(dev, 0x0568, 0x0000);
 650         b43_write16(dev, 0x07C0, 0x0000);
 651         value = ((phy->type == B43_PHYTYPE_A) ? 1 : 0);
 652         b43_write16(dev, 0x050C, value);
 653         b43_write16(dev, 0x0508, 0x0000);
 654         b43_write16(dev, 0x050A, 0x0000);
 655         b43_write16(dev, 0x054C, 0x0000);
 656         b43_write16(dev, 0x056A, 0x0014);
 657         b43_write16(dev, 0x0568, 0x0826);
 658         b43_write16(dev, 0x0500, 0x0000);
 659         b43_write16(dev, 0x0502, 0x0030);
 660
 661         if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
 662                 b43_radio_write16(dev, 0x0051, 0x0017);
 663         for (i = 0x00; i < max_loop; i++) {
 664                 value = b43_read16(dev, 0x050E);
 665                 if (value & 0x0080)
 666                         break;
 667                 udelay(10);
 668         }
 669         for (i = 0x00; i < 0x0A; i++) {
 670                 value = b43_read16(dev, 0x050E);
 671                 if (value & 0x0400)
 672                         break;
 673                 udelay(10);
 674         }
 675         for (i = 0x00; i < 0x0A; i++) {
 676                 value = b43_read16(dev, 0x0690);
 677                 if (!(value & 0x0100))
 678                         break;
 679                 udelay(10);
 680         }
 681         if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
 682                 b43_radio_write16(dev, 0x0051, 0x0037);
 683 }
 684
 685 static void key_write(struct b43_wldev *dev,
 686                       u8 index, u8 algorithm, const u8 * key)
 687 {
 688         unsigned int i;
 689         u32 offset;
 690         u16 value;
 691         u16 kidx;
 692
 693         /* Key index/algo block */
 694         kidx = b43_kidx_to_fw(dev, index);
 695         value = ((kidx << 4) | algorithm);
 696         b43_shm_write16(dev, B43_SHM_SHARED,
 697                         B43_SHM_SH_KEYIDXBLOCK + (kidx * 2), value);
 698
 699         /* Write the key to the Key Table Pointer offset */
 700         offset = dev->ktp + (index * B43_SEC_KEYSIZE);
 701         for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
 702                 value = key[i];
 703                 value |= (u16) (key[i + 1]) << 8;
 704                 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, value);
 705         }
 706 }
 707
 708 static void keymac_write(struct b43_wldev *dev, u8 index, const u8 * addr)
 709 {
 710         u32 addrtmp[2] = { 0, 0, };
 711         u8 per_sta_keys_start = 8;
 712
 713         if (b43_new_kidx_api(dev))
 714                 per_sta_keys_start = 4;
 715
 716         B43_WARN_ON(index < per_sta_keys_start);
 717         /* We have two default TX keys and possibly two default RX keys.
 718          * Physical mac 0 is mapped to physical key 4 or 8, depending
 719          * on the firmware version.
 720          * So we must adjust the index here.
 721          */
 722         index -= per_sta_keys_start;
 723
 724         if (addr) {
 725                 addrtmp[0] = addr[0];
 726                 addrtmp[0] |= ((u32) (addr[1]) << 8);
 727                 addrtmp[0] |= ((u32) (addr[2]) << 16);
 728                 addrtmp[0] |= ((u32) (addr[3]) << 24);
 729                 addrtmp[1] = addr[4];
 730                 addrtmp[1] |= ((u32) (addr[5]) << 8);
 731         }
 732
 733         if (dev->dev->id.revision >= 5) {
 734                 /* Receive match transmitter address mechanism */
 735                 b43_shm_write32(dev, B43_SHM_RCMTA,
 736                                 (index * 2) + 0, addrtmp[0]);
 737                 b43_shm_write16(dev, B43_SHM_RCMTA,
 738                                 (index * 2) + 1, addrtmp[1]);
 739         } else {
 740                 /* RXE (Receive Engine) and
 741                  * PSM (Programmable State Machine) mechanism
 742                  */
 743                 if (index < 8) {
 744                         /* TODO write to RCM 16, 19, 22 and 25 */
 745                 } else {
 746                         b43_shm_write32(dev, B43_SHM_SHARED,
 747                                         B43_SHM_SH_PSM + (index * 6) + 0,
 748                                         addrtmp[0]);
 749                         b43_shm_write16(dev, B43_SHM_SHARED,
 750                                         B43_SHM_SH_PSM + (index * 6) + 4,
 751                                         addrtmp[1]);
 752                 }
 753         }
 754 }
 755
 756 static void do_key_write(struct b43_wldev *dev,
 757                          u8 index, u8 algorithm,
 758                          const u8 * key, size_t key_len, const u8 * mac_addr)
 759 {
 760         u8 buf[B43_SEC_KEYSIZE] = { 0, };
 761         u8 per_sta_keys_start = 8;
 762
 763         if (b43_new_kidx_api(dev))
 764                 per_sta_keys_start = 4;
 765
 766         B43_WARN_ON(index >= dev->max_nr_keys);
 767         B43_WARN_ON(key_len > B43_SEC_KEYSIZE);
 768
 769         if (index >= per_sta_keys_start)
 770                 keymac_write(dev, index, NULL); /* First zero out mac. */
 771         if (key)
 772                 memcpy(buf, key, key_len);
 773         key_write(dev, index, algorithm, buf);
 774         if (index >= per_sta_keys_start)
 775                 keymac_write(dev, index, mac_addr);
 776
 777         dev->key[index].algorithm = algorithm;
 778 }
 779
 780 static int b43_key_write(struct b43_wldev *dev,
 781                          int index, u8 algorithm,
 782                          const u8 * key, size_t key_len,
 783                          const u8 * mac_addr,
 784                          struct ieee80211_key_conf *keyconf)
 785 {
 786         int i;
 787         int sta_keys_start;
 788
 789         if (key_len > B43_SEC_KEYSIZE)
 790                 return -EINVAL;
 791         for (i = 0; i < dev->max_nr_keys; i++) {
 792                 /* Check that we don't already have this key. */
 793                 B43_WARN_ON(dev->key[i].keyconf == keyconf);
 794         }
 795         if (index < 0) {
 796                 /* Either pairwise key or address is 00:00:00:00:00:00
 797                  * for transmit-only keys. Search the index. */
 798                 if (b43_new_kidx_api(dev))
 799                         sta_keys_start = 4;
 800                 else
 801                         sta_keys_start = 8;
 802                 for (i = sta_keys_start; i < dev->max_nr_keys; i++) {
 803                         if (!dev->key[i].keyconf) {
 804                                 /* found empty */
 805                                 index = i;
 806                                 break;
 807                         }
 808                 }
 809                 if (index < 0) {
 810                         b43err(dev->wl, "Out of hardware key memory\n");
 811                         return -ENOSPC;
 812                 }
 813         } else
 814                 B43_WARN_ON(index > 3);
 815
 816         do_key_write(dev, index, algorithm, key, key_len, mac_addr);
 817         if ((index <= 3) && !b43_new_kidx_api(dev)) {
 818                 /* Default RX key */
 819                 B43_WARN_ON(mac_addr);
 820                 do_key_write(dev, index + 4, algorithm, key, key_len, NULL);
 821         }
 822         keyconf->hw_key_idx = index;
 823         dev->key[index].keyconf = keyconf;
 824
 825         return 0;
 826 }
 827
 828 static int b43_key_clear(struct b43_wldev *dev, int index)
 829 {
 830         if (B43_WARN_ON((index < 0) || (index >= dev->max_nr_keys)))
 831                 return -EINVAL;
 832         do_key_write(dev, index, B43_SEC_ALGO_NONE,
 833                      NULL, B43_SEC_KEYSIZE, NULL);
 834         if ((index <= 3) && !b43_new_kidx_api(dev)) {
 835                 do_key_write(dev, index + 4, B43_SEC_ALGO_NONE,
 836                              NULL, B43_SEC_KEYSIZE, NULL);
 837         }
 838         dev->key[index].keyconf = NULL;
 839
 840         return 0;
 841 }
 842
 843 static void b43_clear_keys(struct b43_wldev *dev)
 844 {
 845         int i;
 846
 847         for (i = 0; i < dev->max_nr_keys; i++)
 848                 b43_key_clear(dev, i);
 849 }
 850
 851 void b43_power_saving_ctl_bits(struct b43_wldev *dev, unsigned int ps_flags)
 852 {
 853         u32 macctl;
 854         u16 ucstat;
 855         bool hwps;
 856         bool awake;
 857         int i;
 858
 859         B43_WARN_ON((ps_flags & B43_PS_ENABLED) &&
 860                     (ps_flags & B43_PS_DISABLED));
 861         B43_WARN_ON((ps_flags & B43_PS_AWAKE) && (ps_flags & B43_PS_ASLEEP));
 862
 863         if (ps_flags & B43_PS_ENABLED) {
 864                 hwps = 1;
 865         } else if (ps_flags & B43_PS_DISABLED) {
 866                 hwps = 0;
 867         } else {
 868                 //TODO: If powersave is not off and FIXME is not set and we are not in adhoc
 869                 //      and thus is not an AP and we are associated, set bit 25
 870         }
 871         if (ps_flags & B43_PS_AWAKE) {
 872                 awake = 1;
 873         } else if (ps_flags & B43_PS_ASLEEP) {
 874                 awake = 0;
 875         } else {
 876                 //TODO: If the device is awake or this is an AP, or we are scanning, or FIXME,
 877                 //      or we are associated, or FIXME, or the latest PS-Poll packet sent was
 878                 //      successful, set bit26
 879         }
 880
 881 /* FIXME: For now we force awake-on and hwps-off */
 882         hwps = 0;
 883         awake = 1;
 884
 885         macctl = b43_read32(dev, B43_MMIO_MACCTL);
 886         if (hwps)
 887                 macctl |= B43_MACCTL_HWPS;
 888         else
 889                 macctl &= ~B43_MACCTL_HWPS;
 890         if (awake)
 891                 macctl |= B43_MACCTL_AWAKE;
 892         else
 893                 macctl &= ~B43_MACCTL_AWAKE;
 894         b43_write32(dev, B43_MMIO_MACCTL, macctl);
 895         /* Commit write */
 896         b43_read32(dev, B43_MMIO_MACCTL);
 897         if (awake && dev->dev->id.revision >= 5) {
 898                 /* Wait for the microcode to wake up. */
 899                 for (i = 0; i < 100; i++) {
 900                         ucstat = b43_shm_read16(dev, B43_SHM_SHARED,
 901                                                 B43_SHM_SH_UCODESTAT);
 902                         if (ucstat != B43_SHM_SH_UCODESTAT_SLEEP)
 903                                 break;
 904                         udelay(10);
 905                 }
 906         }
 907 }
 908
 909 /* Turn the Analog ON/OFF */
 910 static void b43_switch_analog(struct b43_wldev *dev, int on)
 911 {
 912         b43_write16(dev, B43_MMIO_PHY0, on ? 0 : 0xF4);
 913 }
 914
 915 void b43_wireless_core_reset(struct b43_wldev *dev, u32 flags)
 916 {
 917         u32 tmslow;
 918         u32 macctl;
 919
 920         flags |= B43_TMSLOW_PHYCLKEN;
 921         flags |= B43_TMSLOW_PHYRESET;
 922         ssb_device_enable(dev->dev, flags);
 923         msleep(2);              /* Wait for the PLL to turn on. */
 924
 925         /* Now take the PHY out of Reset again */
 926         tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
 927         tmslow |= SSB_TMSLOW_FGC;
 928         tmslow &= ~B43_TMSLOW_PHYRESET;
 929         ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
 930         ssb_read32(dev->dev, SSB_TMSLOW);       /* flush */
 931         msleep(1);
 932         tmslow &= ~SSB_TMSLOW_FGC;
 933         ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
 934         ssb_read32(dev->dev, SSB_TMSLOW);       /* flush */
 935         msleep(1);
 936
 937         /* Turn Analog ON */
 938         b43_switch_analog(dev, 1);
 939
 940         macctl = b43_read32(dev, B43_MMIO_MACCTL);
 941         macctl &= ~B43_MACCTL_GMODE;
 942         if (flags & B43_TMSLOW_GMODE)
 943                 macctl |= B43_MACCTL_GMODE;
 944         macctl |= B43_MACCTL_IHR_ENABLED;
 945         b43_write32(dev, B43_MMIO_MACCTL, macctl);
 946 }
 947
 948 static void handle_irq_transmit_status(struct b43_wldev *dev)
 949 {
 950         u32 v0, v1;
 951         u16 tmp;
 952         struct b43_txstatus stat;
 953
 954         while (1) {
 955                 v0 = b43_read32(dev, B43_MMIO_XMITSTAT_0);
 956                 if (!(v0 & 0x00000001))
 957                         break;
 958                 v1 = b43_read32(dev, B43_MMIO_XMITSTAT_1);
 959
 960                 stat.cookie = (v0 >> 16);
 961                 stat.seq = (v1 & 0x0000FFFF);
 962                 stat.phy_stat = ((v1 & 0x00FF0000) >> 16);
 963                 tmp = (v0 & 0x0000FFFF);
 964                 stat.frame_count = ((tmp & 0xF000) >> 12);
 965                 stat.rts_count = ((tmp & 0x0F00) >> 8);
 966                 stat.supp_reason = ((tmp & 0x001C) >> 2);
 967                 stat.pm_indicated = !!(tmp & 0x0080);
 968                 stat.intermediate = !!(tmp & 0x0040);
 969                 stat.for_ampdu = !!(tmp & 0x0020);
 970                 stat.acked = !!(tmp & 0x0002);
 971
 972                 b43_handle_txstatus(dev, &stat);
 973         }
 974 }
 975
 976 static void drain_txstatus_queue(struct b43_wldev *dev)
 977 {
 978         u32 dummy;
 979
 980         if (dev->dev->id.revision < 5)
 981                 return;
 982         /* Read all entries from the microcode TXstatus FIFO
 983          * and throw them away.
 984          */
 985         while (1) {
 986                 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_0);
 987                 if (!(dummy & 0x00000001))
 988                         break;
 989                 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_1);
 990         }
 991 }
 992
 993 static u32 b43_jssi_read(struct b43_wldev *dev)
 994 {
 995         u32 val = 0;
 996
 997         val = b43_shm_read16(dev, B43_SHM_SHARED, 0x08A);
 998         val <<= 16;
 999         val |= b43_shm_read16(dev, B43_SHM_SHARED, 0x088);
1000
1001         return val;
1002 }
1003
1004 static void b43_jssi_write(struct b43_wldev *dev, u32 jssi)
1005 {
1006         b43_shm_write16(dev, B43_SHM_SHARED, 0x088, (jssi & 0x0000FFFF));
1007         b43_shm_write16(dev, B43_SHM_SHARED, 0x08A, (jssi & 0xFFFF0000) >> 16);
1008 }
1009
1010 static void b43_generate_noise_sample(struct b43_wldev *dev)
1011 {
1012         b43_jssi_write(dev, 0x7F7F7F7F);
1013         b43_write32(dev, B43_MMIO_MACCMD,
1014                     b43_read32(dev, B43_MMIO_MACCMD) | B43_MACCMD_BGNOISE);
1015         B43_WARN_ON(dev->noisecalc.channel_at_start != dev->phy.channel);
1016 }
1017
1018 static void b43_calculate_link_quality(struct b43_wldev *dev)
1019 {
1020         /* Top half of Link Quality calculation. */
1021
1022         if (dev->noisecalc.calculation_running)
1023                 return;
1024         dev->noisecalc.channel_at_start = dev->phy.channel;
1025         dev->noisecalc.calculation_running = 1;
1026         dev->noisecalc.nr_samples = 0;
1027
1028         b43_generate_noise_sample(dev);
1029 }
1030
1031 static void handle_irq_noise(struct b43_wldev *dev)
1032 {
1033         struct b43_phy *phy = &dev->phy;
1034         u16 tmp;
1035         u8 noise[4];
1036         u8 i, j;
1037         s32 average;
1038
1039         /* Bottom half of Link Quality calculation. */
1040
1041         B43_WARN_ON(!dev->noisecalc.calculation_running);
1042         if (dev->noisecalc.channel_at_start != phy->channel)
1043                 goto drop_calculation;
1044         *((__le32 *)noise) = cpu_to_le32(b43_jssi_read(dev));
1045         if (noise[0] == 0x7F || noise[1] == 0x7F ||
1046             noise[2] == 0x7F || noise[3] == 0x7F)
1047                 goto generate_new;
1048
1049         /* Get the noise samples. */
1050         B43_WARN_ON(dev->noisecalc.nr_samples >= 8);
1051         i = dev->noisecalc.nr_samples;
1052         noise[0] = limit_value(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1053         noise[1] = limit_value(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1054         noise[2] = limit_value(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1055         noise[3] = limit_value(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1056         dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
1057         dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
1058         dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
1059         dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
1060         dev->noisecalc.nr_samples++;
1061         if (dev->noisecalc.nr_samples == 8) {
1062                 /* Calculate the Link Quality by the noise samples. */
1063                 average = 0;
1064                 for (i = 0; i < 8; i++) {
1065                         for (j = 0; j < 4; j++)
1066                                 average += dev->noisecalc.samples[i][j];
1067                 }
1068                 average /= (8 * 4);
1069                 average *= 125;
1070                 average += 64;
1071                 average /= 128;
1072                 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x40C);
1073                 tmp = (tmp / 128) & 0x1F;
1074                 if (tmp >= 8)
1075                         average += 2;
1076                 else
1077                         average -= 25;
1078                 if (tmp == 8)
1079                         average -= 72;
1080                 else
1081                         average -= 48;
1082
1083                 dev->stats.link_noise = average;
1084               drop_calculation:
1085                 dev->noisecalc.calculation_running = 0;
1086                 return;
1087         }
1088       generate_new:
1089         b43_generate_noise_sample(dev);
1090 }
1091
1092 static void handle_irq_tbtt_indication(struct b43_wldev *dev)
1093 {
1094         if (b43_is_mode(dev->wl, IEEE80211_IF_TYPE_AP)) {
1095                 ///TODO: PS TBTT
1096         } else {
1097                 if (1 /*FIXME: the last PSpoll frame was sent successfully */ )
1098                         b43_power_saving_ctl_bits(dev, 0);
1099         }
1100         if (b43_is_mode(dev->wl, IEEE80211_IF_TYPE_IBSS))
1101                 dev->dfq_valid = 1;
1102 }
1103
1104 static void handle_irq_atim_end(struct b43_wldev *dev)
1105 {
1106         if (dev->dfq_valid) {
1107                 b43_write32(dev, B43_MMIO_MACCMD,
1108                             b43_read32(dev, B43_MMIO_MACCMD)
1109                             | B43_MACCMD_DFQ_VALID);
1110                 dev->dfq_valid = 0;
1111         }
1112 }
1113
1114 static void handle_irq_pmq(struct b43_wldev *dev)
1115 {
1116         u32 tmp;
1117
1118         //TODO: AP mode.
1119
1120         while (1) {
1121                 tmp = b43_read32(dev, B43_MMIO_PS_STATUS);
1122                 if (!(tmp & 0x00000008))
1123                         break;
1124         }
1125         /* 16bit write is odd, but correct. */
1126         b43_write16(dev, B43_MMIO_PS_STATUS, 0x0002);
1127 }
1128
1129 static void b43_write_template_common(struct b43_wldev *dev,
1130                                       const u8 * data, u16 size,
1131                                       u16 ram_offset,
1132                                       u16 shm_size_offset, u8 rate)
1133 {
1134         u32 i, tmp;
1135         struct b43_plcp_hdr4 plcp;
1136
1137         plcp.data = 0;
1138         b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
1139         b43_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
1140         ram_offset += sizeof(u32);
1141         /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
1142          * So leave the first two bytes of the next write blank.
1143          */
1144         tmp = (u32) (data[0]) << 16;
1145         tmp |= (u32) (data[1]) << 24;
1146         b43_ram_write(dev, ram_offset, tmp);
1147         ram_offset += sizeof(u32);
1148         for (i = 2; i < size; i += sizeof(u32)) {
1149                 tmp = (u32) (data[i + 0]);
1150                 if (i + 1 < size)
1151                         tmp |= (u32) (data[i + 1]) << 8;
1152                 if (i + 2 < size)
1153                         tmp |= (u32) (data[i + 2]) << 16;
1154                 if (i + 3 < size)
1155                         tmp |= (u32) (data[i + 3]) << 24;
1156                 b43_ram_write(dev, ram_offset + i - 2, tmp);
1157         }
1158         b43_shm_write16(dev, B43_SHM_SHARED, shm_size_offset,
1159                         size + sizeof(struct b43_plcp_hdr6));
1160 }
1161
1162 static void b43_write_beacon_template(struct b43_wldev *dev,
1163                                       u16 ram_offset,
1164                                       u16 shm_size_offset, u8 rate)
1165 {
1166         unsigned int i, len, variable_len;
1167         const struct ieee80211_mgmt *bcn;
1168         const u8 *ie;
1169         bool tim_found = 0;
1170
1171         bcn = (const struct ieee80211_mgmt *)(dev->wl->current_beacon->data);
1172         len = min((size_t) dev->wl->current_beacon->len,
1173                   0x200 - sizeof(struct b43_plcp_hdr6));
1174
1175         b43_write_template_common(dev, (const u8 *)bcn,
1176                                   len, ram_offset, shm_size_offset, rate);
1177
1178         /* Find the position of the TIM and the DTIM_period value
1179          * and write them to SHM. */
1180         ie = bcn->u.beacon.variable;
1181         variable_len = len - offsetof(struct ieee80211_mgmt, u.beacon.variable);
1182         for (i = 0; i < variable_len - 2; ) {
1183                 uint8_t ie_id, ie_len;
1184
1185                 ie_id = ie[i];
1186                 ie_len = ie[i + 1];
1187                 if (ie_id == 5) {
1188                         u16 tim_position;
1189                         u16 dtim_period;
1190                         /* This is the TIM Information Element */
1191
1192                         /* Check whether the ie_len is in the beacon data range. */
1193                         if (variable_len < ie_len + 2 + i)
1194                                 break;
1195                         /* A valid TIM is at least 4 bytes long. */
1196                         if (ie_len < 4)
1197                                 break;
1198                         tim_found = 1;
1199
1200                         tim_position = sizeof(struct b43_plcp_hdr6);
1201                         tim_position += offsetof(struct ieee80211_mgmt, u.beacon.variable);
1202                         tim_position += i;
1203
1204                         dtim_period = ie[i + 3];
1205
1206                         b43_shm_write16(dev, B43_SHM_SHARED,
1207                                         B43_SHM_SH_TIMBPOS, tim_position);
1208                         b43_shm_write16(dev, B43_SHM_SHARED,
1209                                         B43_SHM_SH_DTIMPER, dtim_period);
1210                         break;
1211                 }
1212                 i += ie_len + 2;
1213         }
1214         if (!tim_found) {
1215                 b43warn(dev->wl, "Did not find a valid TIM IE in "
1216                         "the beacon template packet. AP or IBSS operation "
1217                         "may be broken.\n");
1218         }
1219 }
1220
1221 static void b43_write_probe_resp_plcp(struct b43_wldev *dev,
1222                                       u16 shm_offset, u16 size, u8 rate)
1223 {
1224         struct b43_plcp_hdr4 plcp;
1225         u32 tmp;
1226         __le16 dur;
1227
1228         plcp.data = 0;
1229         b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
1230         dur = ieee80211_generic_frame_duration(dev->wl->hw,
1231                                                dev->wl->vif, size,
1232                                                B43_RATE_TO_BASE100KBPS(rate));
1233         /* Write PLCP in two parts and timing for packet transfer */
1234         tmp = le32_to_cpu(plcp.data);
1235         b43_shm_write16(dev, B43_SHM_SHARED, shm_offset, tmp & 0xFFFF);
1236         b43_shm_write16(dev, B43_SHM_SHARED, shm_offset + 2, tmp >> 16);
1237         b43_shm_write16(dev, B43_SHM_SHARED, shm_offset + 6, le16_to_cpu(dur));
1238 }
1239
1240 /* Instead of using custom probe response template, this function
1241  * just patches custom beacon template by:
1242  * 1) Changing packet type
1243  * 2) Patching duration field
1244  * 3) Stripping TIM
1245  */
1246 static const u8 * b43_generate_probe_resp(struct b43_wldev *dev,
1247                                           u16 *dest_size, u8 rate)
1248 {
1249         const u8 *src_data;
1250         u8 *dest_data;
1251         u16 src_size, elem_size, src_pos, dest_pos;
1252         __le16 dur;
1253         struct ieee80211_hdr *hdr;
1254         size_t ie_start;
1255
1256         src_size = dev->wl->current_beacon->len;
1257         src_data = (const u8 *)dev->wl->current_beacon->data;
1258
1259         /* Get the start offset of the variable IEs in the packet. */
1260         ie_start = offsetof(struct ieee80211_mgmt, u.probe_resp.variable);
1261         B43_WARN_ON(ie_start != offsetof(struct ieee80211_mgmt, u.beacon.variable));
1262
1263         if (B43_WARN_ON(src_size < ie_start))
1264                 return NULL;
1265
1266         dest_data = kmalloc(src_size, GFP_ATOMIC);
1267         if (unlikely(!dest_data))
1268                 return NULL;
1269
1270         /* Copy the static data and all Information Elements, except the TIM. */
1271         memcpy(dest_data, src_data, ie_start);
1272         src_pos = ie_start;
1273         dest_pos = ie_start;
1274         for ( ; src_pos < src_size - 2; src_pos += elem_size) {
1275                 elem_size = src_data[src_pos + 1] + 2;
1276                 if (src_data[src_pos] == 5) {
1277                         /* This is the TIM. */
1278                         continue;
1279                 }
1280                 memcpy(dest_data + dest_pos, src_data + src_pos,
1281                        elem_size);
1282                 dest_pos += elem_size;
1283         }
1284         *dest_size = dest_pos;
1285         hdr = (struct ieee80211_hdr *)dest_data;
1286
1287         /* Set the frame control. */
1288         hdr->frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT |
1289                                          IEEE80211_STYPE_PROBE_RESP);
1290         dur = ieee80211_generic_frame_duration(dev->wl->hw,
1291                                                dev->wl->vif, *dest_size,
1292                                                B43_RATE_TO_BASE100KBPS(rate));
1293         hdr->duration_id = dur;
1294
1295         return dest_data;
1296 }
1297
1298 static void b43_write_probe_resp_template(struct b43_wldev *dev,
1299                                           u16 ram_offset,
1300                                           u16 shm_size_offset, u8 rate)
1301 {
1302         const u8 *probe_resp_data;
1303         u16 size;
1304
1305         size = dev->wl->current_beacon->len;
1306         probe_resp_data = b43_generate_probe_resp(dev, &size, rate);
1307         if (unlikely(!probe_resp_data))
1308                 return;
1309
1310         /* Looks like PLCP headers plus packet timings are stored for
1311          * all possible basic rates
1312          */
1313         b43_write_probe_resp_plcp(dev, 0x31A, size, B43_CCK_RATE_1MB);
1314         b43_write_probe_resp_plcp(dev, 0x32C, size, B43_CCK_RATE_2MB);
1315         b43_write_probe_resp_plcp(dev, 0x33E, size, B43_CCK_RATE_5MB);
1316         b43_write_probe_resp_plcp(dev, 0x350, size, B43_CCK_RATE_11MB);
1317
1318         size = min((size_t) size, 0x200 - sizeof(struct b43_plcp_hdr6));
1319         b43_write_template_common(dev, probe_resp_data,
1320                                   size, ram_offset, shm_size_offset, rate);
1321         kfree(probe_resp_data);
1322 }
1323
1324 /* Asynchronously update the packet templates in template RAM.
1325  * Locking: Requires wl->irq_lock to be locked. */
1326 static void b43_update_templates(struct b43_wl *wl, struct sk_buff *beacon)
1327 {
1328         /* This is the top half of the ansynchronous beacon update.
1329          * The bottom half is the beacon IRQ.
1330          * Beacon update must be asynchronous to avoid sending an
1331          * invalid beacon. This can happen for example, if the firmware
1332          * transmits a beacon while we are updating it. */
1333
1334         if (wl->current_beacon)
1335                 dev_kfree_skb_any(wl->current_beacon);
1336         wl->current_beacon = beacon;
1337         wl->beacon0_uploaded = 0;
1338         wl->beacon1_uploaded = 0;
1339 }
1340
1341 static void b43_set_ssid(struct b43_wldev *dev, const u8 * ssid, u8 ssid_len)
1342 {
1343         u32 tmp;
1344         u16 i, len;
1345
1346         len = min((u16) ssid_len, (u16) 0x100);
1347         for (i = 0; i < len; i += sizeof(u32)) {
1348                 tmp = (u32) (ssid[i + 0]);
1349                 if (i + 1 < len)
1350                         tmp |= (u32) (ssid[i + 1]) << 8;
1351                 if (i + 2 < len)
1352                         tmp |= (u32) (ssid[i + 2]) << 16;
1353                 if (i + 3 < len)
1354                         tmp |= (u32) (ssid[i + 3]) << 24;
1355                 b43_shm_write32(dev, B43_SHM_SHARED, 0x380 + i, tmp);
1356         }
1357         b43_shm_write16(dev, B43_SHM_SHARED, 0x48, len);
1358 }
1359
1360 static void b43_set_beacon_int(struct b43_wldev *dev, u16 beacon_int)
1361 {
1362         b43_time_lock(dev);
1363         if (dev->dev->id.revision >= 3) {
1364                 b43_write32(dev, 0x188, (beacon_int << 16));
1365         } else {
1366                 b43_write16(dev, 0x606, (beacon_int >> 6));
1367                 b43_write16(dev, 0x610, beacon_int);
1368         }
1369         b43_time_unlock(dev);
1370 }
1371
1372 static void handle_irq_beacon(struct b43_wldev *dev)
1373 {
1374         struct b43_wl *wl = dev->wl;
1375         u32 cmd;
1376
1377         if (!b43_is_mode(wl, IEEE80211_IF_TYPE_AP))
1378                 return;
1379
1380         /* This is the bottom half of the asynchronous beacon update. */
1381
1382         cmd = b43_read32(dev, B43_MMIO_MACCMD);
1383         if (!(cmd & B43_MACCMD_BEACON0_VALID)) {
1384                 if (!wl->beacon0_uploaded) {
1385                         b43_write_beacon_template(dev, 0x68, 0x18,
1386                                                   B43_CCK_RATE_1MB);
1387                         b43_write_probe_resp_template(dev, 0x268, 0x4A,
1388                                                       B43_CCK_RATE_11MB);
1389                         wl->beacon0_uploaded = 1;
1390                 }
1391                 cmd |= B43_MACCMD_BEACON0_VALID;
1392         }
1393         if (!(cmd & B43_MACCMD_BEACON1_VALID)) {
1394                 if (!wl->beacon1_uploaded) {
1395                         b43_write_beacon_template(dev, 0x468, 0x1A,
1396                                                   B43_CCK_RATE_1MB);
1397                         wl->beacon1_uploaded = 1;
1398                 }
1399                 cmd |= B43_MACCMD_BEACON1_VALID;
1400         }
1401         b43_write32(dev, B43_MMIO_MACCMD, cmd);
1402 }
1403
1404 static void handle_irq_ucode_debug(struct b43_wldev *dev)
1405 {
1406         //TODO
1407 }
1408
1409 /* Interrupt handler bottom-half */
1410 static void b43_interrupt_tasklet(struct b43_wldev *dev)
1411 {
1412         u32 reason;
1413         u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
1414         u32 merged_dma_reason = 0;
1415         int i;
1416         unsigned long flags;
1417
1418         spin_lock_irqsave(&dev->wl->irq_lock, flags);
1419
1420         B43_WARN_ON(b43_status(dev) != B43_STAT_STARTED);
1421
1422         reason = dev->irq_reason;
1423         for (i = 0; i < ARRAY_SIZE(dma_reason); i++) {
1424                 dma_reason[i] = dev->dma_reason[i];
1425                 merged_dma_reason |= dma_reason[i];
1426         }
1427
1428         if (unlikely(reason & B43_IRQ_MAC_TXERR))
1429                 b43err(dev->wl, "MAC transmission error\n");
1430
1431         if (unlikely(reason & B43_IRQ_PHY_TXERR)) {
1432                 b43err(dev->wl, "PHY transmission error\n");
1433                 rmb();
1434                 if (unlikely(atomic_dec_and_test(&dev->phy.txerr_cnt))) {
1435                         atomic_set(&dev->phy.txerr_cnt,
1436                                    B43_PHY_TX_BADNESS_LIMIT);
1437                         b43err(dev->wl, "Too many PHY TX errors, "
1438                                         "restarting the controller\n");
1439                         b43_controller_restart(dev, "PHY TX errors");
1440                 }
1441         }
1442
1443         if (unlikely(merged_dma_reason & (B43_DMAIRQ_FATALMASK |
1444                                           B43_DMAIRQ_NONFATALMASK))) {
1445                 if (merged_dma_reason & B43_DMAIRQ_FATALMASK) {
1446                         b43err(dev->wl, "Fatal DMA error: "
1447                                "0x%08X, 0x%08X, 0x%08X, "
1448                                "0x%08X, 0x%08X, 0x%08X\n",
1449                                dma_reason[0], dma_reason[1],
1450                                dma_reason[2], dma_reason[3],
1451                                dma_reason[4], dma_reason[5]);
1452                         b43_controller_restart(dev, "DMA error");
1453                         mmiowb();
1454                         spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1455                         return;
1456                 }
1457                 if (merged_dma_reason & B43_DMAIRQ_NONFATALMASK) {
1458                         b43err(dev->wl, "DMA error: "
1459                                "0x%08X, 0x%08X, 0x%08X, "
1460                                "0x%08X, 0x%08X, 0x%08X\n",
1461                                dma_reason[0], dma_reason[1],
1462                                dma_reason[2], dma_reason[3],
1463                                dma_reason[4], dma_reason[5]);
1464                 }
1465         }
1466
1467         if (unlikely(reason & B43_IRQ_UCODE_DEBUG))
1468                 handle_irq_ucode_debug(dev);
1469         if (reason & B43_IRQ_TBTT_INDI)
1470                 handle_irq_tbtt_indication(dev);
1471         if (reason & B43_IRQ_ATIM_END)
1472                 handle_irq_atim_end(dev);
1473         if (reason & B43_IRQ_BEACON)
1474                 handle_irq_beacon(dev);
1475         if (reason & B43_IRQ_PMQ)
1476                 handle_irq_pmq(dev);
1477         if (reason & B43_IRQ_TXFIFO_FLUSH_OK)
1478                 ;/* TODO */
1479         if (reason & B43_IRQ_NOISESAMPLE_OK)
1480                 handle_irq_noise(dev);
1481
1482         /* Check the DMA reason registers for received data. */
1483         if (dma_reason[0] & B43_DMAIRQ_RX_DONE)
1484                 b43_dma_rx(dev->dma.rx_ring0);
1485         if (dma_reason[3] & B43_DMAIRQ_RX_DONE)
1486                 b43_dma_rx(dev->dma.rx_ring3);
1487         B43_WARN_ON(dma_reason[1] & B43_DMAIRQ_RX_DONE);
1488         B43_WARN_ON(dma_reason[2] & B43_DMAIRQ_RX_DONE);
1489         B43_WARN_ON(dma_reason[4] & B43_DMAIRQ_RX_DONE);
1490         B43_WARN_ON(dma_reason[5] & B43_DMAIRQ_RX_DONE);
1491
1492         if (reason & B43_IRQ_TX_OK)
1493                 handle_irq_transmit_status(dev);
1494
1495         b43_interrupt_enable(dev, dev->irq_savedstate);
1496         mmiowb();
1497         spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1498 }
1499
1500 static void b43_interrupt_ack(struct b43_wldev *dev, u32 reason)
1501 {
1502         b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, reason);
1503
1504         b43_write32(dev, B43_MMIO_DMA0_REASON, dev->dma_reason[0]);
1505         b43_write32(dev, B43_MMIO_DMA1_REASON, dev->dma_reason[1]);
1506         b43_write32(dev, B43_MMIO_DMA2_REASON, dev->dma_reason[2]);
1507         b43_write32(dev, B43_MMIO_DMA3_REASON, dev->dma_reason[3]);
1508         b43_write32(dev, B43_MMIO_DMA4_REASON, dev->dma_reason[4]);
1509         b43_write32(dev, B43_MMIO_DMA5_REASON, dev->dma_reason[5]);
1510 }
1511
1512 /* Interrupt handler top-half */
1513 static irqreturn_t b43_interrupt_handler(int irq, void *dev_id)
1514 {
1515         irqreturn_t ret = IRQ_NONE;
1516         struct b43_wldev *dev = dev_id;
1517         u32 reason;
1518
1519         if (!dev)
1520                 return IRQ_NONE;
1521
1522         spin_lock(&dev->wl->irq_lock);
1523
1524         if (b43_status(dev) < B43_STAT_STARTED)
1525                 goto out;
1526         reason = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1527         if (reason == 0xffffffff)       /* shared IRQ */
1528                 goto out;
1529         ret = IRQ_HANDLED;
1530         reason &= b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
1531         if (!reason)
1532                 goto out;
1533
1534         dev->dma_reason[0] = b43_read32(dev, B43_MMIO_DMA0_REASON)
1535             & 0x0001DC00;
1536         dev->dma_reason[1] = b43_read32(dev, B43_MMIO_DMA1_REASON)
1537             & 0x0000DC00;
1538         dev->dma_reason[2] = b43_read32(dev, B43_MMIO_DMA2_REASON)
1539             & 0x0000DC00;
1540         dev->dma_reason[3] = b43_read32(dev, B43_MMIO_DMA3_REASON)
1541             & 0x0001DC00;
1542         dev->dma_reason[4] = b43_read32(dev, B43_MMIO_DMA4_REASON)
1543             & 0x0000DC00;
1544         dev->dma_reason[5] = b43_read32(dev, B43_MMIO_DMA5_REASON)
1545             & 0x0000DC00;
1546
1547         b43_interrupt_ack(dev, reason);
1548         /* disable all IRQs. They are enabled again in the bottom half. */
1549         dev->irq_savedstate = b43_interrupt_disable(dev, B43_IRQ_ALL);
1550         /* save the reason code and call our bottom half. */
1551         dev->irq_reason = reason;
1552         tasklet_schedule(&dev->isr_tasklet);
1553       out:
1554         mmiowb();
1555         spin_unlock(&dev->wl->irq_lock);
1556
1557         return ret;
1558 }
1559
1560 static void b43_release_firmware(struct b43_wldev *dev)
1561 {
1562         release_firmware(dev->fw.ucode);
1563         dev->fw.ucode = NULL;
1564         release_firmware(dev->fw.pcm);
1565         dev->fw.pcm = NULL;
1566         release_firmware(dev->fw.initvals);
1567         dev->fw.initvals = NULL;
1568         release_firmware(dev->fw.initvals_band);
1569         dev->fw.initvals_band = NULL;
1570 }
1571
1572 static void b43_print_fw_helptext(struct b43_wl *wl)
1573 {
1574         b43err(wl, "You must go to "
1575                "http://linuxwireless.org/en/users/Drivers/b43#devicefirmware "
1576                "and download the correct firmware (version 4).\n");
1577 }
1578
1579 static int do_request_fw(struct b43_wldev *dev,
1580                          const char *name,
1581                          const struct firmware **fw)
1582 {
1583         char path[sizeof(modparam_fwpostfix) + 32];
1584         struct b43_fw_header *hdr;
1585         u32 size;
1586         int err;
1587
1588         if (!name)
1589                 return 0;
1590
1591         snprintf(path, ARRAY_SIZE(path),
1592                  "b43%s/%s.fw",
1593                  modparam_fwpostfix, name);
1594         err = request_firmware(fw, path, dev->dev->dev);
1595         if (err) {
1596                 b43err(dev->wl, "Firmware file \"%s\" not found "
1597                        "or load failed.\n", path);
1598                 return err;
1599         }
1600         if ((*fw)->size < sizeof(struct b43_fw_header))
1601                 goto err_format;
1602         hdr = (struct b43_fw_header *)((*fw)->data);
1603         switch (hdr->type) {
1604         case B43_FW_TYPE_UCODE:
1605         case B43_FW_TYPE_PCM:
1606                 size = be32_to_cpu(hdr->size);
1607                 if (size != (*fw)->size - sizeof(struct b43_fw_header))
1608                         goto err_format;
1609                 /* fallthrough */
1610         case B43_FW_TYPE_IV:
1611                 if (hdr->ver != 1)
1612                         goto err_format;
1613                 break;
1614         default:
1615                 goto err_format;
1616         }
1617
1618         return err;
1619
1620 err_format:
1621         b43err(dev->wl, "Firmware file \"%s\" format error.\n", path);
1622         return -EPROTO;
1623 }
1624
1625 static int b43_request_firmware(struct b43_wldev *dev)
1626 {
1627         struct b43_firmware *fw = &dev->fw;
1628         const u8 rev = dev->dev->id.revision;
1629         const char *filename;
1630         u32 tmshigh;
1631         int err;
1632
1633         tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
1634         if (!fw->ucode) {
1635                 if ((rev >= 5) && (rev <= 10))
1636                         filename = "ucode5";
1637                 else if ((rev >= 11) && (rev <= 12))
1638                         filename = "ucode11";
1639                 else if (rev >= 13)
1640                         filename = "ucode13";
1641                 else
1642                         goto err_no_ucode;
1643                 err = do_request_fw(dev, filename, &fw->ucode);
1644                 if (err)
1645                         goto err_load;
1646         }
1647         if (!fw->pcm) {
1648                 if ((rev >= 5) && (rev <= 10))
1649                         filename = "pcm5";
1650                 else if (rev >= 11)
1651                         filename = NULL;
1652                 else
1653                         goto err_no_pcm;
1654                 err = do_request_fw(dev, filename, &fw->pcm);
1655                 if (err)
1656                         goto err_load;
1657         }
1658         if (!fw->initvals) {
1659                 switch (dev->phy.type) {
1660                 case B43_PHYTYPE_A:
1661                         if ((rev >= 5) && (rev <= 10)) {
1662                                 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
1663                                         filename = "a0g1initvals5";
1664                                 else
1665                                         filename = "a0g0initvals5";
1666                         } else
1667                                 goto err_no_initvals;
1668                         break;
1669                 case B43_PHYTYPE_G:
1670                         if ((rev >= 5) && (rev <= 10))
1671                                 filename = "b0g0initvals5";
1672                         else if (rev >= 13)
1673                                 filename = "lp0initvals13";
1674                         else
1675                                 goto err_no_initvals;
1676                         break;
1677                 case B43_PHYTYPE_N:
1678                         if ((rev >= 11) && (rev <= 12))
1679                                 filename = "n0initvals11";
1680                         else
1681                                 goto err_no_initvals;
1682                         break;
1683                 default:
1684                         goto err_no_initvals;
1685                 }
1686                 err = do_request_fw(dev, filename, &fw->initvals);
1687                 if (err)
1688                         goto err_load;
1689         }
1690         if (!fw->initvals_band) {
1691                 switch (dev->phy.type) {
1692                 case B43_PHYTYPE_A:
1693                         if ((rev >= 5) && (rev <= 10)) {
1694                                 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
1695                                         filename = "a0g1bsinitvals5";
1696                                 else
1697                                         filename = "a0g0bsinitvals5";
1698                         } else if (rev >= 11)
1699                                 filename = NULL;
1700                         else
1701                                 goto err_no_initvals;
1702                         break;
1703                 case B43_PHYTYPE_G:
1704                         if ((rev >= 5) && (rev <= 10))
1705                                 filename = "b0g0bsinitvals5";
1706                         else if (rev >= 11)
1707                                 filename = NULL;
1708                         else
1709                                 goto err_no_initvals;
1710                         break;
1711                 case B43_PHYTYPE_N:
1712                         if ((rev >= 11) && (rev <= 12))
1713                                 filename = "n0bsinitvals11";
1714                         else
1715                                 goto err_no_initvals;
1716                         break;
1717                 default:
1718                         goto err_no_initvals;
1719                 }
1720                 err = do_request_fw(dev, filename, &fw->initvals_band);
1721                 if (err)
1722                         goto err_load;
1723         }
1724
1725         return 0;
1726
1727 err_load:
1728         b43_print_fw_helptext(dev->wl);
1729         goto error;
1730
1731 err_no_ucode:
1732         err = -ENODEV;
1733         b43err(dev->wl, "No microcode available for core rev %u\n", rev);
1734         goto error;
1735
1736 err_no_pcm:
1737         err = -ENODEV;
1738         b43err(dev->wl, "No PCM available for core rev %u\n", rev);
1739         goto error;
1740
1741 err_no_initvals:
1742         err = -ENODEV;
1743         b43err(dev->wl, "No Initial Values firmware file for PHY %u, "
1744                "core rev %u\n", dev->phy.type, rev);
1745         goto error;
1746
1747 error:
1748         b43_release_firmware(dev);
1749         return err;
1750 }
1751
1752 static int b43_upload_microcode(struct b43_wldev *dev)
1753 {
1754         const size_t hdr_len = sizeof(struct b43_fw_header);
1755         const __be32 *data;
1756         unsigned int i, len;
1757         u16 fwrev, fwpatch, fwdate, fwtime;
1758         u32 tmp;
1759         int err = 0;
1760
1761         /* Upload Microcode. */
1762         data = (__be32 *) (dev->fw.ucode->data + hdr_len);
1763         len = (dev->fw.ucode->size - hdr_len) / sizeof(__be32);
1764         b43_shm_control_word(dev, B43_SHM_UCODE | B43_SHM_AUTOINC_W, 0x0000);
1765         for (i = 0; i < len; i++) {
1766                 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
1767                 udelay(10);
1768         }
1769
1770         if (dev->fw.pcm) {
1771                 /* Upload PCM data. */
1772                 data = (__be32 *) (dev->fw.pcm->data + hdr_len);
1773                 len = (dev->fw.pcm->size - hdr_len) / sizeof(__be32);
1774                 b43_shm_control_word(dev, B43_SHM_HW, 0x01EA);
1775                 b43_write32(dev, B43_MMIO_SHM_DATA, 0x00004000);
1776                 /* No need for autoinc bit in SHM_HW */
1777                 b43_shm_control_word(dev, B43_SHM_HW, 0x01EB);
1778                 for (i = 0; i < len; i++) {
1779                         b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
1780                         udelay(10);
1781                 }
1782         }
1783
1784         b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_ALL);
1785         b43_write32(dev, B43_MMIO_MACCTL,
1786                     B43_MACCTL_PSM_RUN |
1787                     B43_MACCTL_IHR_ENABLED | B43_MACCTL_INFRA);
1788
1789         /* Wait for the microcode to load and respond */
1790         i = 0;
1791         while (1) {
1792                 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1793                 if (tmp == B43_IRQ_MAC_SUSPENDED)
1794                         break;
1795                 i++;
1796                 if (i >= 50) {
1797                         b43err(dev->wl, "Microcode not responding\n");
1798                         b43_print_fw_helptext(dev->wl);
1799                         err = -ENODEV;
1800                         goto out;
1801                 }
1802                 udelay(10);
1803         }
1804         b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);       /* dummy read */
1805
1806         /* Get and check the revisions. */
1807         fwrev = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEREV);
1808         fwpatch = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEPATCH);
1809         fwdate = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEDATE);
1810         fwtime = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODETIME);
1811
1812         if (fwrev <= 0x128) {
1813                 b43err(dev->wl, "YOUR FIRMWARE IS TOO OLD. Firmware from "
1814                        "binary drivers older than version 4.x is unsupported. "
1815                        "You must upgrade your firmware files.\n");
1816                 b43_print_fw_helptext(dev->wl);
1817                 b43_write32(dev, B43_MMIO_MACCTL, 0);
1818                 err = -EOPNOTSUPP;
1819                 goto out;
1820         }
1821         b43dbg(dev->wl, "Loading firmware version %u.%u "
1822                "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n",
1823                fwrev, fwpatch,
1824                (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
1825                (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, fwtime & 0x1F);
1826
1827         dev->fw.rev = fwrev;
1828         dev->fw.patch = fwpatch;
1829
1830       out:
1831         return err;
1832 }
1833
1834 static int b43_write_initvals(struct b43_wldev *dev,
1835                               const struct b43_iv *ivals,
1836                               size_t count,
1837                               size_t array_size)
1838 {
1839         const struct b43_iv *iv;
1840         u16 offset;
1841         size_t i;
1842         bool bit32;
1843
1844         BUILD_BUG_ON(sizeof(struct b43_iv) != 6);
1845         iv = ivals;
1846         for (i = 0; i < count; i++) {
1847                 if (array_size < sizeof(iv->offset_size))
1848                         goto err_format;
1849                 array_size -= sizeof(iv->offset_size);
1850                 offset = be16_to_cpu(iv->offset_size);
1851                 bit32 = !!(offset & B43_IV_32BIT);
1852                 offset &= B43_IV_OFFSET_MASK;
1853                 if (offset >= 0x1000)
1854                         goto err_format;
1855                 if (bit32) {
1856                         u32 value;
1857
1858                         if (array_size < sizeof(iv->data.d32))
1859                                 goto err_format;
1860                         array_size -= sizeof(iv->data.d32);
1861
1862                         value = be32_to_cpu(get_unaligned(&iv->data.d32));
1863                         b43_write32(dev, offset, value);
1864
1865                         iv = (const struct b43_iv *)((const uint8_t *)iv +
1866                                                         sizeof(__be16) +
1867                                                         sizeof(__be32));
1868                 } else {
1869                         u16 value;
1870
1871                         if (array_size < sizeof(iv->data.d16))
1872                                 goto err_format;
1873                         array_size -= sizeof(iv->data.d16);
1874
1875                         value = be16_to_cpu(iv->data.d16);
1876                         b43_write16(dev, offset, value);
1877
1878                         iv = (const struct b43_iv *)((const uint8_t *)iv +
1879                                                         sizeof(__be16) +
1880                                                         sizeof(__be16));
1881                 }
1882         }
1883         if (array_size)
1884                 goto err_format;
1885
1886         return 0;
1887
1888 err_format:
1889         b43err(dev->wl, "Initial Values Firmware file-format error.\n");
1890         b43_print_fw_helptext(dev->wl);
1891
1892         return -EPROTO;
1893 }
1894
1895 static int b43_upload_initvals(struct b43_wldev *dev)
1896 {
1897         const size_t hdr_len = sizeof(struct b43_fw_header);
1898         const struct b43_fw_header *hdr;
1899         struct b43_firmware *fw = &dev->fw;
1900         const struct b43_iv *ivals;
1901         size_t count;
1902         int err;
1903
1904         hdr = (const struct b43_fw_header *)(fw->initvals->data);
1905         ivals = (const struct b43_iv *)(fw->initvals->data + hdr_len);
1906         count = be32_to_cpu(hdr->size);
1907         err = b43_write_initvals(dev, ivals, count,
1908                                  fw->initvals->size - hdr_len);
1909         if (err)
1910                 goto out;
1911         if (fw->initvals_band) {
1912                 hdr = (const struct b43_fw_header *)(fw->initvals_band->data);
1913                 ivals = (const struct b43_iv *)(fw->initvals_band->data + hdr_len);
1914                 count = be32_to_cpu(hdr->size);
1915                 err = b43_write_initvals(dev, ivals, count,
1916                                          fw->initvals_band->size - hdr_len);
1917                 if (err)
1918                         goto out;
1919         }
1920 out:
1921
1922         return err;
1923 }
1924
1925 /* Initialize the GPIOs
1926  * http://bcm-specs.sipsolutions.net/GPIO
1927  */
1928 static int b43_gpio_init(struct b43_wldev *dev)
1929 {
1930         struct ssb_bus *bus = dev->dev->bus;
1931         struct ssb_device *gpiodev, *pcidev = NULL;
1932         u32 mask, set;
1933
1934         b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
1935                     & ~B43_MACCTL_GPOUTSMSK);
1936
1937         b43_write16(dev, B43_MMIO_GPIO_MASK, b43_read16(dev, B43_MMIO_GPIO_MASK)
1938                     | 0x000F);
1939
1940         mask = 0x0000001F;
1941         set = 0x0000000F;
1942         if (dev->dev->bus->chip_id == 0x4301) {
1943                 mask |= 0x0060;
1944                 set |= 0x0060;
1945         }
1946         if (0 /* FIXME: conditional unknown */ ) {
1947                 b43_write16(dev, B43_MMIO_GPIO_MASK,
1948                             b43_read16(dev, B43_MMIO_GPIO_MASK)
1949                             | 0x0100);
1950                 mask |= 0x0180;
1951                 set |= 0x0180;
1952         }
1953         if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_PACTRL) {
1954                 b43_write16(dev, B43_MMIO_GPIO_MASK,
1955                             b43_read16(dev, B43_MMIO_GPIO_MASK)
1956                             | 0x0200);
1957                 mask |= 0x0200;
1958                 set |= 0x0200;
1959         }
1960         if (dev->dev->id.revision >= 2)
1961                 mask |= 0x0010; /* FIXME: This is redundant. */
1962
1963 #ifdef CONFIG_SSB_DRIVER_PCICORE
1964         pcidev = bus->pcicore.dev;
1965 #endif
1966         gpiodev = bus->chipco.dev ? : pcidev;
1967         if (!gpiodev)
1968                 return 0;
1969         ssb_write32(gpiodev, B43_GPIO_CONTROL,
1970                     (ssb_read32(gpiodev, B43_GPIO_CONTROL)
1971                      & mask) | set);
1972
1973         return 0;
1974 }
1975
1976 /* Turn off all GPIO stuff. Call this on module unload, for example. */
1977 static void b43_gpio_cleanup(struct b43_wldev *dev)
1978 {
1979         struct ssb_bus *bus = dev->dev->bus;
1980         struct ssb_device *gpiodev, *pcidev = NULL;
1981
1982 #ifdef CONFIG_SSB_DRIVER_PCICORE
1983         pcidev = bus->pcicore.dev;
1984 #endif
1985         gpiodev = bus->chipco.dev ? : pcidev;
1986         if (!gpiodev)
1987                 return;
1988         ssb_write32(gpiodev, B43_GPIO_CONTROL, 0);
1989 }
1990
1991 /* http://bcm-specs.sipsolutions.net/EnableMac */
1992 void b43_mac_enable(struct b43_wldev *dev)
1993 {
1994         dev->mac_suspended--;
1995         B43_WARN_ON(dev->mac_suspended < 0);
1996         B43_WARN_ON(irqs_disabled());
1997         if (dev->mac_suspended == 0) {
1998                 b43_write32(dev, B43_MMIO_MACCTL,
1999                             b43_read32(dev, B43_MMIO_MACCTL)
2000                             | B43_MACCTL_ENABLED);
2001                 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON,
2002                             B43_IRQ_MAC_SUSPENDED);
2003                 /* Commit writes */
2004                 b43_read32(dev, B43_MMIO_MACCTL);
2005                 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2006                 b43_power_saving_ctl_bits(dev, 0);
2007
2008                 /* Re-enable IRQs. */
2009                 spin_lock_irq(&dev->wl->irq_lock);
2010                 b43_interrupt_enable(dev, dev->irq_savedstate);
2011                 spin_unlock_irq(&dev->wl->irq_lock);
2012         }
2013 }
2014
2015 /* http://bcm-specs.sipsolutions.net/SuspendMAC */
2016 void b43_mac_suspend(struct b43_wldev *dev)
2017 {
2018         int i;
2019         u32 tmp;
2020
2021         might_sleep();
2022         B43_WARN_ON(irqs_disabled());
2023         B43_WARN_ON(dev->mac_suspended < 0);
2024
2025         if (dev->mac_suspended == 0) {
2026                 /* Mask IRQs before suspending MAC. Otherwise
2027                  * the MAC stays busy and won't suspend. */
2028                 spin_lock_irq(&dev->wl->irq_lock);
2029                 tmp = b43_interrupt_disable(dev, B43_IRQ_ALL);
2030                 spin_unlock_irq(&dev->wl->irq_lock);
2031                 b43_synchronize_irq(dev);
2032                 dev->irq_savedstate = tmp;
2033
2034                 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
2035                 b43_write32(dev, B43_MMIO_MACCTL,
2036                             b43_read32(dev, B43_MMIO_MACCTL)
2037                             & ~B43_MACCTL_ENABLED);
2038                 /* force pci to flush the write */
2039                 b43_read32(dev, B43_MMIO_MACCTL);
2040                 for (i = 40; i; i--) {
2041                         tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2042                         if (tmp & B43_IRQ_MAC_SUSPENDED)
2043                                 goto out;
2044                         msleep(1);
2045                 }
2046                 b43err(dev->wl, "MAC suspend failed\n");
2047         }
2048 out:
2049         dev->mac_suspended++;
2050 }
2051
2052 static void b43_adjust_opmode(struct b43_wldev *dev)
2053 {
2054         struct b43_wl *wl = dev->wl;
2055         u32 ctl;
2056         u16 cfp_pretbtt;
2057
2058         ctl = b43_read32(dev, B43_MMIO_MACCTL);
2059         /* Reset status to STA infrastructure mode. */
2060         ctl &= ~B43_MACCTL_AP;
2061         ctl &= ~B43_MACCTL_KEEP_CTL;
2062         ctl &= ~B43_MACCTL_KEEP_BADPLCP;
2063         ctl &= ~B43_MACCTL_KEEP_BAD;
2064         ctl &= ~B43_MACCTL_PROMISC;
2065         ctl &= ~B43_MACCTL_BEACPROMISC;
2066         ctl |= B43_MACCTL_INFRA;
2067
2068         if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP))
2069                 ctl |= B43_MACCTL_AP;
2070         else if (b43_is_mode(wl, IEEE80211_IF_TYPE_IBSS))
2071                 ctl &= ~B43_MACCTL_INFRA;
2072
2073         if (wl->filter_flags & FIF_CONTROL)
2074                 ctl |= B43_MACCTL_KEEP_CTL;
2075         if (wl->filter_flags & FIF_FCSFAIL)
2076                 ctl |= B43_MACCTL_KEEP_BAD;
2077         if (wl->filter_flags & FIF_PLCPFAIL)
2078                 ctl |= B43_MACCTL_KEEP_BADPLCP;
2079         if (wl->filter_flags & FIF_PROMISC_IN_BSS)
2080                 ctl |= B43_MACCTL_PROMISC;
2081         if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC)
2082                 ctl |= B43_MACCTL_BEACPROMISC;
2083
2084         /* Workaround: On old hardware the HW-MAC-address-filter
2085          * doesn't work properly, so always run promisc in filter
2086          * it in software. */
2087         if (dev->dev->id.revision <= 4)
2088                 ctl |= B43_MACCTL_PROMISC;
2089
2090         b43_write32(dev, B43_MMIO_MACCTL, ctl);
2091
2092         cfp_pretbtt = 2;
2093         if ((ctl & B43_MACCTL_INFRA) && !(ctl & B43_MACCTL_AP)) {
2094                 if (dev->dev->bus->chip_id == 0x4306 &&
2095                     dev->dev->bus->chip_rev == 3)
2096                         cfp_pretbtt = 100;
2097                 else
2098                         cfp_pretbtt = 50;
2099         }
2100         b43_write16(dev, 0x612, cfp_pretbtt);
2101 }
2102
2103 static void b43_rate_memory_write(struct b43_wldev *dev, u16 rate, int is_ofdm)
2104 {
2105         u16 offset;
2106
2107         if (is_ofdm) {
2108                 offset = 0x480;
2109                 offset += (b43_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
2110         } else {
2111                 offset = 0x4C0;
2112                 offset += (b43_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
2113         }
2114         b43_shm_write16(dev, B43_SHM_SHARED, offset + 0x20,
2115                         b43_shm_read16(dev, B43_SHM_SHARED, offset));
2116 }
2117
2118 static void b43_rate_memory_init(struct b43_wldev *dev)
2119 {
2120         switch (dev->phy.type) {
2121         case B43_PHYTYPE_A:
2122         case B43_PHYTYPE_G:
2123                 b43_rate_memory_write(dev, B43_OFDM_RATE_6MB, 1);
2124                 b43_rate_memory_write(dev, B43_OFDM_RATE_12MB, 1);
2125                 b43_rate_memory_write(dev, B43_OFDM_RATE_18MB, 1);
2126                 b43_rate_memory_write(dev, B43_OFDM_RATE_24MB, 1);
2127                 b43_rate_memory_write(dev, B43_OFDM_RATE_36MB, 1);
2128                 b43_rate_memory_write(dev, B43_OFDM_RATE_48MB, 1);
2129                 b43_rate_memory_write(dev, B43_OFDM_RATE_54MB, 1);
2130                 if (dev->phy.type == B43_PHYTYPE_A)
2131                         break;
2132                 /* fallthrough */
2133         case B43_PHYTYPE_B:
2134                 b43_rate_memory_write(dev, B43_CCK_RATE_1MB, 0);
2135                 b43_rate_memory_write(dev, B43_CCK_RATE_2MB, 0);
2136                 b43_rate_memory_write(dev, B43_CCK_RATE_5MB, 0);
2137                 b43_rate_memory_write(dev, B43_CCK_RATE_11MB, 0);
2138                 break;
2139         default:
2140                 B43_WARN_ON(1);
2141         }
2142 }
2143
2144 /* Set the TX-Antenna for management frames sent by firmware. */
2145 static void b43_mgmtframe_txantenna(struct b43_wldev *dev, int antenna)
2146 {
2147         u16 ant = 0;
2148         u16 tmp;
2149
2150         switch (antenna) {
2151         case B43_ANTENNA0:
2152                 ant |= B43_TX4_PHY_ANT0;
2153                 break;
2154         case B43_ANTENNA1:
2155                 ant |= B43_TX4_PHY_ANT1;
2156                 break;
2157         case B43_ANTENNA_AUTO:
2158                 ant |= B43_TX4_PHY_ANTLAST;
2159                 break;
2160         default:
2161                 B43_WARN_ON(1);
2162         }
2163
2164         /* FIXME We also need to set the other flags of the PHY control field somewhere. */
2165
2166         /* For Beacons */
2167         tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL);
2168         tmp = (tmp & ~B43_TX4_PHY_ANT) | ant;
2169         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, tmp);
2170         /* For ACK/CTS */
2171         tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL);
2172         tmp = (tmp & ~B43_TX4_PHY_ANT) | ant;
2173         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, tmp);
2174         /* For Probe Resposes */
2175         tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL);
2176         tmp = (tmp & ~B43_TX4_PHY_ANT) | ant;
2177         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, tmp);
2178 }
2179
2180 /* This is the opposite of b43_chip_init() */
2181 static void b43_chip_exit(struct b43_wldev *dev)
2182 {
2183         b43_radio_turn_off(dev, 1);
2184         b43_gpio_cleanup(dev);
2185         /* firmware is released later */
2186 }
2187
2188 /* Initialize the chip
2189  * http://bcm-specs.sipsolutions.net/ChipInit
2190  */
2191 static int b43_chip_init(struct b43_wldev *dev)
2192 {
2193         struct b43_phy *phy = &dev->phy;
2194         int err, tmp;
2195         u32 value32;
2196         u16 value16;
2197
2198         b43_write32(dev, B43_MMIO_MACCTL,
2199                     B43_MACCTL_PSM_JMP0 | B43_MACCTL_IHR_ENABLED);
2200
2201         err = b43_request_firmware(dev);
2202         if (err)
2203                 goto out;
2204         err = b43_upload_microcode(dev);
2205         if (err)
2206                 goto out;       /* firmware is released later */
2207
2208         err = b43_gpio_init(dev);
2209         if (err)
2210                 goto out;       /* firmware is released later */
2211
2212         err = b43_upload_initvals(dev);
2213         if (err)
2214                 goto err_gpio_clean;
2215         b43_radio_turn_on(dev);
2216
2217         b43_write16(dev, 0x03E6, 0x0000);
2218         err = b43_phy_init(dev);
2219         if (err)
2220                 goto err_radio_off;
2221
2222         /* Select initial Interference Mitigation. */
2223         tmp = phy->interfmode;
2224         phy->interfmode = B43_INTERFMODE_NONE;
2225         b43_radio_set_interference_mitigation(dev, tmp);
2226
2227         b43_set_rx_antenna(dev, B43_ANTENNA_DEFAULT);
2228         b43_mgmtframe_txantenna(dev, B43_ANTENNA_DEFAULT);
2229
2230         if (phy->type == B43_PHYTYPE_B) {
2231                 value16 = b43_read16(dev, 0x005E);
2232                 value16 |= 0x0004;
2233                 b43_write16(dev, 0x005E, value16);
2234         }
2235         b43_write32(dev, 0x0100, 0x01000000);
2236         if (dev->dev->id.revision < 5)
2237                 b43_write32(dev, 0x010C, 0x01000000);
2238
2239         b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2240                     & ~B43_MACCTL_INFRA);
2241         b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2242                     | B43_MACCTL_INFRA);
2243
2244         /* Probe Response Timeout value */
2245         /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
2246         b43_shm_write16(dev, B43_SHM_SHARED, 0x0074, 0x0000);
2247
2248         /* Initially set the wireless operation mode. */
2249         b43_adjust_opmode(dev);
2250
2251         if (dev->dev->id.revision < 3) {
2252                 b43_write16(dev, 0x060E, 0x0000);
2253                 b43_write16(dev, 0x0610, 0x8000);
2254                 b43_write16(dev, 0x0604, 0x0000);
2255                 b43_write16(dev, 0x0606, 0x0200);
2256         } else {
2257                 b43_write32(dev, 0x0188, 0x80000000);
2258                 b43_write32(dev, 0x018C, 0x02000000);
2259         }
2260         b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 0x00004000);
2261         b43_write32(dev, B43_MMIO_DMA0_IRQ_MASK, 0x0001DC00);
2262         b43_write32(dev, B43_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
2263         b43_write32(dev, B43_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
2264         b43_write32(dev, B43_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
2265         b43_write32(dev, B43_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
2266         b43_write32(dev, B43_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
2267
2268         value32 = ssb_read32(dev->dev, SSB_TMSLOW);
2269         value32 |= 0x00100000;
2270         ssb_write32(dev->dev, SSB_TMSLOW, value32);
2271
2272         b43_write16(dev, B43_MMIO_POWERUP_DELAY,
2273                     dev->dev->bus->chipco.fast_pwrup_delay);
2274
2275         err = 0;
2276         b43dbg(dev->wl, "Chip initialized\n");
2277 out:
2278         return err;
2279
2280 err_radio_off:
2281         b43_radio_turn_off(dev, 1);
2282 err_gpio_clean:
2283         b43_gpio_cleanup(dev);
2284         return err;
2285 }
2286
2287 static void b43_periodic_every120sec(struct b43_wldev *dev)
2288 {
2289         struct b43_phy *phy = &dev->phy;
2290
2291         if (phy->type != B43_PHYTYPE_G || phy->rev < 2)
2292                 return;
2293
2294         b43_mac_suspend(dev);
2295         b43_lo_g_measure(dev);
2296         b43_mac_enable(dev);
2297         if (b43_has_hardware_pctl(phy))
2298                 b43_lo_g_ctl_mark_all_unused(dev);
2299 }
2300
2301 static void b43_periodic_every60sec(struct b43_wldev *dev)
2302 {
2303         struct b43_phy *phy = &dev->phy;
2304
2305         if (!b43_has_hardware_pctl(phy))
2306                 b43_lo_g_ctl_mark_all_unused(dev);
2307         if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_RSSI) {
2308                 b43_mac_suspend(dev);
2309                 b43_calc_nrssi_slope(dev);
2310                 if ((phy->radio_ver == 0x2050) && (phy->radio_rev == 8)) {
2311                         u8 old_chan = phy->channel;
2312
2313                         /* VCO Calibration */
2314                         if (old_chan >= 8)
2315                                 b43_radio_selectchannel(dev, 1, 0);
2316                         else
2317                                 b43_radio_selectchannel(dev, 13, 0);
2318                         b43_radio_selectchannel(dev, old_chan, 0);
2319                 }
2320                 b43_mac_enable(dev);
2321         }
2322 }
2323
2324 static void b43_periodic_every30sec(struct b43_wldev *dev)
2325 {
2326         /* Update device statistics. */
2327         b43_calculate_link_quality(dev);
2328 }
2329
2330 static void b43_periodic_every15sec(struct b43_wldev *dev)
2331 {
2332         struct b43_phy *phy = &dev->phy;
2333
2334         if (phy->type == B43_PHYTYPE_G) {
2335                 //TODO: update_aci_moving_average
2336                 if (phy->aci_enable && phy->aci_wlan_automatic) {
2337                         b43_mac_suspend(dev);
2338                         if (!phy->aci_enable && 1 /*TODO: not scanning? */ ) {
2339                                 if (0 /*TODO: bunch of conditions */ ) {
2340                                         b43_radio_set_interference_mitigation
2341                                             (dev, B43_INTERFMODE_MANUALWLAN);
2342                                 }
2343                         } else if (1 /*TODO*/) {
2344                                 /*
2345                                    if ((aci_average > 1000) && !(b43_radio_aci_scan(dev))) {
2346                                    b43_radio_set_interference_mitigation(dev,
2347                                    B43_INTERFMODE_NONE);
2348                                    }
2349                                  */
2350                         }
2351                         b43_mac_enable(dev);
2352                 } else if (phy->interfmode == B43_INTERFMODE_NONWLAN &&
2353                            phy->rev == 1) {
2354                         //TODO: implement rev1 workaround
2355                 }
2356         }
2357         b43_phy_xmitpower(dev); //FIXME: unless scanning?
2358         //TODO for APHY (temperature?)
2359
2360         atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
2361         wmb();
2362 }
2363
2364 static void do_periodic_work(struct b43_wldev *dev)
2365 {
2366         unsigned int state;
2367
2368         state = dev->periodic_state;
2369         if (state % 8 == 0)
2370                 b43_periodic_every120sec(dev);
2371         if (state % 4 == 0)
2372                 b43_periodic_every60sec(dev);
2373         if (state % 2 == 0)
2374                 b43_periodic_every30sec(dev);
2375         b43_periodic_every15sec(dev);
2376 }
2377
2378 /* Periodic work locking policy:
2379  *      The whole periodic work handler is protected by
2380  *      wl->mutex. If another lock is needed somewhere in the
2381  *      pwork callchain, it's aquired in-place, where it's needed.
2382  */
2383 static void b43_periodic_work_handler(struct work_struct *work)
2384 {
2385         struct b43_wldev *dev = container_of(work, struct b43_wldev,
2386                                              periodic_work.work);
2387         struct b43_wl *wl = dev->wl;
2388         unsigned long delay;
2389
2390         mutex_lock(&wl->mutex);
2391
2392         if (unlikely(b43_status(dev) != B43_STAT_STARTED))
2393                 goto out;
2394         if (b43_debug(dev, B43_DBG_PWORK_STOP))
2395                 goto out_requeue;
2396
2397         do_periodic_work(dev);
2398
2399         dev->periodic_state++;
2400 out_requeue:
2401         if (b43_debug(dev, B43_DBG_PWORK_FAST))
2402                 delay = msecs_to_jiffies(50);
2403         else
2404                 delay = round_jiffies_relative(HZ * 15);
2405         queue_delayed_work(wl->hw->workqueue, &dev->periodic_work, delay);
2406 out:
2407         mutex_unlock(&wl->mutex);
2408 }
2409
2410 static void b43_periodic_tasks_setup(struct b43_wldev *dev)
2411 {
2412         struct delayed_work *work = &dev->periodic_work;
2413
2414         dev->periodic_state = 0;
2415         INIT_DELAYED_WORK(work, b43_periodic_work_handler);
2416         queue_delayed_work(dev->wl->hw->workqueue, work, 0);
2417 }
2418
2419 /* Check if communication with the device works correctly. */
2420 static int b43_validate_chipaccess(struct b43_wldev *dev)
2421 {
2422         u32 v, backup;
2423
2424         backup = b43_shm_read32(dev, B43_SHM_SHARED, 0);
2425
2426         /* Check for read/write and endianness problems. */
2427         b43_shm_write32(dev, B43_SHM_SHARED, 0, 0x55AAAA55);
2428         if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0x55AAAA55)
2429                 goto error;
2430         b43_shm_write32(dev, B43_SHM_SHARED, 0, 0xAA5555AA);
2431         if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0xAA5555AA)
2432                 goto error;
2433
2434         b43_shm_write32(dev, B43_SHM_SHARED, 0, backup);
2435
2436         if ((dev->dev->id.revision >= 3) && (dev->dev->id.revision <= 10)) {
2437                 /* The 32bit register shadows the two 16bit registers
2438                  * with update sideeffects. Validate this. */
2439                 b43_write16(dev, B43_MMIO_TSF_CFP_START, 0xAAAA);
2440                 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0xCCCCBBBB);
2441                 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_LOW) != 0xBBBB)
2442                         goto error;
2443                 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_HIGH) != 0xCCCC)
2444                         goto error;
2445         }
2446         b43_write32(dev, B43_MMIO_TSF_CFP_START, 0);
2447
2448         v = b43_read32(dev, B43_MMIO_MACCTL);
2449         v |= B43_MACCTL_GMODE;
2450         if (v != (B43_MACCTL_GMODE | B43_MACCTL_IHR_ENABLED))
2451                 goto error;
2452
2453         return 0;
2454 error:
2455         b43err(dev->wl, "Failed to validate the chipaccess\n");
2456         return -ENODEV;
2457 }
2458
2459 static void b43_security_init(struct b43_wldev *dev)
2460 {
2461         dev->max_nr_keys = (dev->dev->id.revision >= 5) ? 58 : 20;
2462         B43_WARN_ON(dev->max_nr_keys > ARRAY_SIZE(dev->key));
2463         dev->ktp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_KTP);
2464         /* KTP is a word address, but we address SHM bytewise.
2465          * So multiply by two.
2466          */
2467         dev->ktp *= 2;
2468         if (dev->dev->id.revision >= 5) {
2469                 /* Number of RCMTA address slots */
2470                 b43_write16(dev, B43_MMIO_RCMTA_COUNT, dev->max_nr_keys - 8);
2471         }
2472         b43_clear_keys(dev);
2473 }
2474
2475 static int b43_rng_read(struct hwrng *rng, u32 * data)
2476 {
2477         struct b43_wl *wl = (struct b43_wl *)rng->priv;
2478         unsigned long flags;
2479
2480         /* Don't take wl->mutex here, as it could deadlock with
2481          * hwrng internal locking. It's not needed to take
2482          * wl->mutex here, anyway. */
2483
2484         spin_lock_irqsave(&wl->irq_lock, flags);
2485         *data = b43_read16(wl->current_dev, B43_MMIO_RNG);
2486         spin_unlock_irqrestore(&wl->irq_lock, flags);
2487
2488         return (sizeof(u16));
2489 }
2490
2491 static void b43_rng_exit(struct b43_wl *wl)
2492 {
2493         if (wl->rng_initialized)
2494                 hwrng_unregister(&wl->rng);
2495 }
2496
2497 static int b43_rng_init(struct b43_wl *wl)
2498 {
2499         int err;
2500
2501         snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name),
2502                  "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy));
2503         wl->rng.name = wl->rng_name;
2504         wl->rng.data_read = b43_rng_read;
2505         wl->rng.priv = (unsigned long)wl;
2506         wl->rng_initialized = 1;
2507         err = hwrng_register(&wl->rng);
2508         if (err) {
2509                 wl->rng_initialized = 0;
2510                 b43err(wl, "Failed to register the random "
2511                        "number generator (%d)\n", err);
2512         }
2513
2514         return err;
2515 }
2516
2517 static int b43_op_tx(struct ieee80211_hw *hw,
2518                      struct sk_buff *skb,
2519                      struct ieee80211_tx_control *ctl)
2520 {
2521         struct b43_wl *wl = hw_to_b43_wl(hw);
2522         struct b43_wldev *dev = wl->current_dev;
2523         int err = -ENODEV;
2524
2525         if (unlikely(!dev))
2526                 goto out;
2527         if (unlikely(b43_status(dev) < B43_STAT_STARTED))
2528                 goto out;
2529         /* DMA-TX is done without a global lock. */
2530         err = b43_dma_tx(dev, skb, ctl);
2531 out:
2532         if (unlikely(err))
2533                 return NETDEV_TX_BUSY;
2534         return NETDEV_TX_OK;
2535 }
2536
2537 static int b43_op_conf_tx(struct ieee80211_hw *hw,
2538                           int queue,
2539                           const struct ieee80211_tx_queue_params *params)
2540 {
2541         return 0;
2542 }
2543
2544 static int b43_op_get_tx_stats(struct ieee80211_hw *hw,
2545                                struct ieee80211_tx_queue_stats *stats)
2546 {
2547         struct b43_wl *wl = hw_to_b43_wl(hw);
2548         struct b43_wldev *dev = wl->current_dev;
2549         unsigned long flags;
2550         int err = -ENODEV;
2551
2552         if (!dev)
2553                 goto out;
2554         spin_lock_irqsave(&wl->irq_lock, flags);
2555         if (likely(b43_status(dev) >= B43_STAT_STARTED)) {
2556                 b43_dma_get_tx_stats(dev, stats);
2557                 err = 0;
2558         }
2559         spin_unlock_irqrestore(&wl->irq_lock, flags);
2560 out:
2561         return err;
2562 }
2563
2564 static int b43_op_get_stats(struct ieee80211_hw *hw,
2565                             struct ieee80211_low_level_stats *stats)
2566 {
2567         struct b43_wl *wl = hw_to_b43_wl(hw);
2568         unsigned long flags;
2569
2570         spin_lock_irqsave(&wl->irq_lock, flags);
2571         memcpy(stats, &wl->ieee_stats, sizeof(*stats));
2572         spin_unlock_irqrestore(&wl->irq_lock, flags);
2573
2574         return 0;
2575 }
2576
2577 static const char *phymode_to_string(unsigned int phymode)
2578 {
2579         switch (phymode) {
2580         case B43_PHYMODE_A:
2581                 return "A";
2582         case B43_PHYMODE_B:
2583                 return "B";
2584         case B43_PHYMODE_G:
2585                 return "G";
2586         default:
2587                 B43_WARN_ON(1);
2588         }
2589         return "";
2590 }
2591
2592 static int find_wldev_for_phymode(struct b43_wl *wl,
2593                                   unsigned int phymode,
2594                                   struct b43_wldev **dev, bool * gmode)
2595 {
2596         struct b43_wldev *d;
2597
2598         list_for_each_entry(d, &wl->devlist, list) {
2599                 if (d->phy.possible_phymodes & phymode) {
2600                         /* Ok, this device supports the PHY-mode.
2601                          * Now figure out how the gmode bit has to be
2602                          * set to support it. */
2603                         if (phymode == B43_PHYMODE_A)
2604                                 *gmode = 0;
2605                         else
2606                                 *gmode = 1;
2607                         *dev = d;
2608
2609                         return 0;
2610                 }
2611         }
2612
2613         return -ESRCH;
2614 }
2615
2616 static void b43_put_phy_into_reset(struct b43_wldev *dev)
2617 {
2618         struct ssb_device *sdev = dev->dev;
2619         u32 tmslow;
2620
2621         tmslow = ssb_read32(sdev, SSB_TMSLOW);
2622         tmslow &= ~B43_TMSLOW_GMODE;
2623         tmslow |= B43_TMSLOW_PHYRESET;
2624         tmslow |= SSB_TMSLOW_FGC;
2625         ssb_write32(sdev, SSB_TMSLOW, tmslow);
2626         msleep(1);
2627
2628         tmslow = ssb_read32(sdev, SSB_TMSLOW);
2629         tmslow &= ~SSB_TMSLOW_FGC;
2630         tmslow |= B43_TMSLOW_PHYRESET;
2631         ssb_write32(sdev, SSB_TMSLOW, tmslow);
2632         msleep(1);
2633 }
2634
2635 /* Expects wl->mutex locked */
2636 static int b43_switch_phymode(struct b43_wl *wl, unsigned int new_mode)
2637 {
2638         struct b43_wldev *up_dev;
2639         struct b43_wldev *down_dev;
2640         int err;
2641         bool gmode = 0;
2642         int prev_status;
2643
2644         err = find_wldev_for_phymode(wl, new_mode, &up_dev, &gmode);
2645         if (err) {
2646                 b43err(wl, "Could not find a device for %s-PHY mode\n",
2647                        phymode_to_string(new_mode));
2648                 return err;
2649         }
2650         if ((up_dev == wl->current_dev) &&
2651             (!!wl->current_dev->phy.gmode == !!gmode)) {
2652                 /* This device is already running. */
2653                 return 0;
2654         }
2655         b43dbg(wl, "Reconfiguring PHYmode to %s-PHY\n",
2656                phymode_to_string(new_mode));
2657         down_dev = wl->current_dev;
2658
2659         prev_status = b43_status(down_dev);
2660         /* Shutdown the currently running core. */
2661         if (prev_status >= B43_STAT_STARTED)
2662                 b43_wireless_core_stop(down_dev);
2663         if (prev_status >= B43_STAT_INITIALIZED)
2664                 b43_wireless_core_exit(down_dev);
2665
2666         if (down_dev != up_dev) {
2667                 /* We switch to a different core, so we put PHY into
2668                  * RESET on the old core. */
2669                 b43_put_phy_into_reset(down_dev);
2670         }
2671
2672         /* Now start the new core. */
2673         up_dev->phy.gmode = gmode;
2674         if (prev_status >= B43_STAT_INITIALIZED) {
2675                 err = b43_wireless_core_init(up_dev);
2676                 if (err) {
2677                         b43err(wl, "Fatal: Could not initialize device for "
2678                                "newly selected %s-PHY mode\n",
2679                                phymode_to_string(new_mode));
2680                         goto init_failure;
2681                 }
2682         }
2683         if (prev_status >= B43_STAT_STARTED) {
2684                 err = b43_wireless_core_start(up_dev);
2685                 if (err) {
2686                         b43err(wl, "Fatal: Coult not start device for "
2687                                "newly selected %s-PHY mode\n",
2688                                phymode_to_string(new_mode));
2689                         b43_wireless_core_exit(up_dev);
2690                         goto init_failure;
2691                 }
2692         }
2693         B43_WARN_ON(b43_status(up_dev) != prev_status);
2694
2695         wl->current_dev = up_dev;
2696
2697         return 0;
2698       init_failure:
2699         /* Whoops, failed to init the new core. No core is operating now. */
2700         wl->current_dev = NULL;
2701         return err;
2702 }
2703
2704 /* Check if the use of the antenna that ieee80211 told us to
2705  * use is possible. This will fall back to DEFAULT.
2706  * "antenna_nr" is the antenna identifier we got from ieee80211. */
2707 u8 b43_ieee80211_antenna_sanitize(struct b43_wldev *dev,
2708                                   u8 antenna_nr)
2709 {
2710         u8 antenna_mask;
2711
2712         if (antenna_nr == 0) {
2713                 /* Zero means "use default antenna". That's always OK. */
2714                 return 0;
2715         }
2716
2717         /* Get the mask of available antennas. */
2718         if (dev->phy.gmode)
2719                 antenna_mask = dev->dev->bus->sprom.ant_available_bg;
2720         else
2721                 antenna_mask = dev->dev->bus->sprom.ant_available_a;
2722
2723         if (!(antenna_mask & (1 << (antenna_nr - 1)))) {
2724                 /* This antenna is not available. Fall back to default. */
2725                 return 0;
2726         }
2727
2728         return antenna_nr;
2729 }
2730
2731 static int b43_antenna_from_ieee80211(struct b43_wldev *dev, u8 antenna)
2732 {
2733         antenna = b43_ieee80211_antenna_sanitize(dev, antenna);
2734         switch (antenna) {
2735         case 0:         /* default/diversity */
2736                 return B43_ANTENNA_DEFAULT;
2737         case 1:         /* Antenna 0 */
2738                 return B43_ANTENNA0;
2739         case 2:         /* Antenna 1 */
2740                 return B43_ANTENNA1;
2741         default:
2742                 return B43_ANTENNA_DEFAULT;
2743         }
2744 }
2745
2746 static int b43_op_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf)
2747 {
2748         struct b43_wl *wl = hw_to_b43_wl(hw);
2749         struct b43_wldev *dev;
2750         struct b43_phy *phy;
2751         unsigned long flags;
2752         unsigned int new_phymode = 0xFFFF;
2753         int antenna;
2754         int err = 0;
2755         u32 savedirqs;
2756
2757         mutex_lock(&wl->mutex);
2758
2759         /* Switch the PHY mode (if necessary). */
2760         switch (conf->phymode) {
2761         case MODE_IEEE80211A:
2762                 new_phymode = B43_PHYMODE_A;
2763                 break;
2764         case MODE_IEEE80211B:
2765                 new_phymode = B43_PHYMODE_B;
2766                 break;
2767         case MODE_IEEE80211G:
2768                 new_phymode = B43_PHYMODE_G;
2769                 break;
2770         default:
2771                 B43_WARN_ON(1);
2772         }
2773         err = b43_switch_phymode(wl, new_phymode);
2774         if (err)
2775                 goto out_unlock_mutex;
2776         dev = wl->current_dev;
2777         phy = &dev->phy;
2778
2779         /* Disable IRQs while reconfiguring the device.
2780          * This makes it possible to drop the spinlock throughout
2781          * the reconfiguration process. */
2782         spin_lock_irqsave(&wl->irq_lock, flags);
2783         if (b43_status(dev) < B43_STAT_STARTED) {
2784                 spin_unlock_irqrestore(&wl->irq_lock, flags);
2785                 goto out_unlock_mutex;
2786         }
2787         savedirqs = b43_interrupt_disable(dev, B43_IRQ_ALL);
2788         spin_unlock_irqrestore(&wl->irq_lock, flags);
2789         b43_synchronize_irq(dev);
2790
2791         /* Switch to the requested channel.
2792          * The firmware takes care of races with the TX handler. */
2793         if (conf->channel_val != phy->channel)
2794                 b43_radio_selectchannel(dev, conf->channel_val, 0);
2795
2796         /* Enable/Disable ShortSlot timing. */
2797         if ((!!(conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME)) !=
2798             dev->short_slot) {
2799                 B43_WARN_ON(phy->type != B43_PHYTYPE_G);
2800                 if (conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME)
2801                         b43_short_slot_timing_enable(dev);
2802                 else
2803                         b43_short_slot_timing_disable(dev);
2804         }
2805
2806         dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_RADIOTAP);
2807
2808         /* Adjust the desired TX power level. */
2809         if (conf->power_level != 0) {
2810                 if (conf->power_level != phy->power_level) {
2811                         phy->power_level = conf->power_level;
2812                         b43_phy_xmitpower(dev);
2813                 }
2814         }
2815
2816         /* Antennas for RX and management frame TX. */
2817         antenna = b43_antenna_from_ieee80211(dev, conf->antenna_sel_tx);
2818         b43_mgmtframe_txantenna(dev, antenna);
2819         antenna = b43_antenna_from_ieee80211(dev, conf->antenna_sel_rx);
2820         b43_set_rx_antenna(dev, antenna);
2821
2822         /* Update templates for AP mode. */
2823         if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP))
2824                 b43_set_beacon_int(dev, conf->beacon_int);
2825
2826         if (!!conf->radio_enabled != phy->radio_on) {
2827                 if (conf->radio_enabled) {
2828                         b43_radio_turn_on(dev);
2829                         b43info(dev->wl, "Radio turned on by software\n");
2830                         if (!dev->radio_hw_enable) {
2831                                 b43info(dev->wl, "The hardware RF-kill button "
2832                                         "still turns the radio physically off. "
2833                                         "Press the button to turn it on.\n");
2834                         }
2835                 } else {
2836                         b43_radio_turn_off(dev, 0);
2837                         b43info(dev->wl, "Radio turned off by software\n");
2838                 }
2839         }
2840
2841         spin_lock_irqsave(&wl->irq_lock, flags);
2842         b43_interrupt_enable(dev, savedirqs);
2843         mmiowb();
2844         spin_unlock_irqrestore(&wl->irq_lock, flags);
2845       out_unlock_mutex:
2846         mutex_unlock(&wl->mutex);
2847
2848         return err;
2849 }
2850
2851 static int b43_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
2852                            const u8 *local_addr, const u8 *addr,
2853                            struct ieee80211_key_conf *key)
2854 {
2855         struct b43_wl *wl = hw_to_b43_wl(hw);
2856         struct b43_wldev *dev;
2857         unsigned long flags;
2858         u8 algorithm;
2859         u8 index;
2860         int err;
2861         DECLARE_MAC_BUF(mac);
2862
2863         if (modparam_nohwcrypt)
2864                 return -ENOSPC; /* User disabled HW-crypto */
2865
2866         mutex_lock(&wl->mutex);
2867         spin_lock_irqsave(&wl->irq_lock, flags);
2868
2869         dev = wl->current_dev;
2870         err = -ENODEV;
2871         if (!dev || b43_status(dev) < B43_STAT_INITIALIZED)
2872                 goto out_unlock;
2873
2874         err = -EINVAL;
2875         switch (key->alg) {
2876         case ALG_WEP:
2877                 if (key->keylen == 5)
2878                         algorithm = B43_SEC_ALGO_WEP40;
2879                 else
2880                         algorithm = B43_SEC_ALGO_WEP104;
2881                 break;
2882         case ALG_TKIP:
2883                 algorithm = B43_SEC_ALGO_TKIP;
2884                 break;
2885         case ALG_CCMP:
2886                 algorithm = B43_SEC_ALGO_AES;
2887                 break;
2888         default:
2889                 B43_WARN_ON(1);
2890                 goto out_unlock;
2891         }
2892         index = (u8) (key->keyidx);
2893         if (index > 3)
2894                 goto out_unlock;
2895
2896         switch (cmd) {
2897         case SET_KEY:
2898                 if (algorithm == B43_SEC_ALGO_TKIP) {
2899                         /* FIXME: No TKIP hardware encryption for now. */
2900                         err = -EOPNOTSUPP;
2901                         goto out_unlock;
2902                 }
2903
2904                 if (is_broadcast_ether_addr(addr)) {
2905                         /* addr is FF:FF:FF:FF:FF:FF for default keys */
2906                         err = b43_key_write(dev, index, algorithm,
2907                                             key->key, key->keylen, NULL, key);
2908                 } else {
2909                         /*
2910                          * either pairwise key or address is 00:00:00:00:00:00
2911                          * for transmit-only keys
2912                          */
2913                         err = b43_key_write(dev, -1, algorithm,
2914                                             key->key, key->keylen, addr, key);
2915                 }
2916                 if (err)
2917                         goto out_unlock;
2918
2919                 if (algorithm == B43_SEC_ALGO_WEP40 ||
2920                     algorithm == B43_SEC_ALGO_WEP104) {
2921                         b43_hf_write(dev, b43_hf_read(dev) | B43_HF_USEDEFKEYS);
2922                 } else {
2923                         b43_hf_write(dev,
2924                                      b43_hf_read(dev) & ~B43_HF_USEDEFKEYS);
2925                 }
2926                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2927                 break;
2928         case DISABLE_KEY: {
2929                 err = b43_key_clear(dev, key->hw_key_idx);
2930                 if (err)
2931                         goto out_unlock;
2932                 break;
2933         }
2934         default:
2935                 B43_WARN_ON(1);
2936         }
2937 out_unlock:
2938         spin_unlock_irqrestore(&wl->irq_lock, flags);
2939         mutex_unlock(&wl->mutex);
2940         if (!err) {
2941                 b43dbg(wl, "%s hardware based encryption for keyidx: %d, "
2942                        "mac: %s\n",
2943                        cmd == SET_KEY ? "Using" : "Disabling", key->keyidx,
2944                        print_mac(mac, addr));
2945         }
2946         return err;
2947 }
2948
2949 static void b43_op_configure_filter(struct ieee80211_hw *hw,
2950                                     unsigned int changed, unsigned int *fflags,
2951                                     int mc_count, struct dev_addr_list *mc_list)
2952 {
2953         struct b43_wl *wl = hw_to_b43_wl(hw);
2954         struct b43_wldev *dev = wl->current_dev;
2955         unsigned long flags;
2956
2957         if (!dev) {
2958                 *fflags = 0;
2959                 return;
2960         }
2961
2962         spin_lock_irqsave(&wl->irq_lock, flags);
2963         *fflags &= FIF_PROMISC_IN_BSS |
2964                   FIF_ALLMULTI |
2965                   FIF_FCSFAIL |
2966                   FIF_PLCPFAIL |
2967                   FIF_CONTROL |
2968                   FIF_OTHER_BSS |
2969                   FIF_BCN_PRBRESP_PROMISC;
2970
2971         changed &= FIF_PROMISC_IN_BSS |
2972                    FIF_ALLMULTI |
2973                    FIF_FCSFAIL |
2974                    FIF_PLCPFAIL |
2975                    FIF_CONTROL |
2976                    FIF_OTHER_BSS |
2977                    FIF_BCN_PRBRESP_PROMISC;
2978
2979         wl->filter_flags = *fflags;
2980
2981         if (changed && b43_status(dev) >= B43_STAT_INITIALIZED)
2982                 b43_adjust_opmode(dev);
2983         spin_unlock_irqrestore(&wl->irq_lock, flags);
2984 }
2985
2986 static int b43_op_config_interface(struct ieee80211_hw *hw,
2987                                    struct ieee80211_vif *vif,
2988                                    struct ieee80211_if_conf *conf)
2989 {
2990         struct b43_wl *wl = hw_to_b43_wl(hw);
2991         struct b43_wldev *dev = wl->current_dev;
2992         unsigned long flags;
2993
2994         if (!dev)
2995                 return -ENODEV;
2996         mutex_lock(&wl->mutex);
2997         spin_lock_irqsave(&wl->irq_lock, flags);
2998         B43_WARN_ON(wl->vif != vif);
2999         if (conf->bssid)
3000                 memcpy(wl->bssid, conf->bssid, ETH_ALEN);
3001         else
3002                 memset(wl->bssid, 0, ETH_ALEN);
3003         if (b43_status(dev) >= B43_STAT_INITIALIZED) {
3004                 if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP)) {
3005                         B43_WARN_ON(conf->type != IEEE80211_IF_TYPE_AP);
3006                         b43_set_ssid(dev, conf->ssid, conf->ssid_len);
3007                         if (conf->beacon)
3008                                 b43_update_templates(wl, conf->beacon);
3009                 }
3010                 b43_write_mac_bssid_templates(dev);
3011         }
3012         spin_unlock_irqrestore(&wl->irq_lock, flags);
3013         mutex_unlock(&wl->mutex);
3014
3015         return 0;
3016 }
3017
3018 /* Locking: wl->mutex */
3019 static void b43_wireless_core_stop(struct b43_wldev *dev)
3020 {
3021         struct b43_wl *wl = dev->wl;
3022         unsigned long flags;
3023
3024         if (b43_status(dev) < B43_STAT_STARTED)
3025                 return;
3026
3027         /* Disable and sync interrupts. We must do this before than
3028          * setting the status to INITIALIZED, as the interrupt handler
3029          * won't care about IRQs then. */
3030         spin_lock_irqsave(&wl->irq_lock, flags);
3031         dev->irq_savedstate = b43_interrupt_disable(dev, B43_IRQ_ALL);
3032         b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* flush */
3033         spin_unlock_irqrestore(&wl->irq_lock, flags);
3034         b43_synchronize_irq(dev);
3035
3036         b43_set_status(dev, B43_STAT_INITIALIZED);
3037
3038         mutex_unlock(&wl->mutex);
3039         /* Must unlock as it would otherwise deadlock. No races here.
3040          * Cancel the possibly running self-rearming periodic work. */
3041         cancel_delayed_work_sync(&dev->periodic_work);
3042         mutex_lock(&wl->mutex);
3043
3044         ieee80211_stop_queues(wl->hw);  //FIXME this could cause a deadlock, as mac80211 seems buggy.
3045
3046         b43_mac_suspend(dev);
3047         free_irq(dev->dev->irq, dev);
3048         b43dbg(wl, "Wireless interface stopped\n");
3049 }
3050
3051 /* Locking: wl->mutex */
3052 static int b43_wireless_core_start(struct b43_wldev *dev)
3053 {
3054         int err;
3055
3056         B43_WARN_ON(b43_status(dev) != B43_STAT_INITIALIZED);
3057
3058         drain_txstatus_queue(dev);
3059         err = request_irq(dev->dev->irq, b43_interrupt_handler,
3060                           IRQF_SHARED, KBUILD_MODNAME, dev);
3061         if (err) {
3062                 b43err(dev->wl, "Cannot request IRQ-%d\n", dev->dev->irq);
3063                 goto out;
3064         }
3065
3066         /* We are ready to run. */
3067         b43_set_status(dev, B43_STAT_STARTED);
3068
3069         /* Start data flow (TX/RX). */
3070         b43_mac_enable(dev);
3071         b43_interrupt_enable(dev, dev->irq_savedstate);
3072         ieee80211_start_queues(dev->wl->hw);
3073
3074         /* Start maintainance work */
3075         b43_periodic_tasks_setup(dev);
3076
3077         b43dbg(dev->wl, "Wireless interface started\n");
3078       out:
3079         return err;
3080 }
3081
3082 /* Get PHY and RADIO versioning numbers */
3083 static int b43_phy_versioning(struct b43_wldev *dev)
3084 {
3085         struct b43_phy *phy = &dev->phy;
3086         u32 tmp;
3087         u8 analog_type;
3088         u8 phy_type;
3089         u8 phy_rev;
3090         u16 radio_manuf;
3091         u16 radio_ver;
3092         u16 radio_rev;
3093         int unsupported = 0;
3094
3095         /* Get PHY versioning */
3096         tmp = b43_read16(dev, B43_MMIO_PHY_VER);
3097         analog_type = (tmp & B43_PHYVER_ANALOG) >> B43_PHYVER_ANALOG_SHIFT;
3098         phy_type = (tmp & B43_PHYVER_TYPE) >> B43_PHYVER_TYPE_SHIFT;
3099         phy_rev = (tmp & B43_PHYVER_VERSION);
3100         switch (phy_type) {
3101         case B43_PHYTYPE_A:
3102                 if (phy_rev >= 4)
3103                         unsupported = 1;
3104                 break;
3105         case B43_PHYTYPE_B:
3106                 if (phy_rev != 2 && phy_rev != 4 && phy_rev != 6
3107                     && phy_rev != 7)
3108                         unsupported = 1;
3109                 break;
3110         case B43_PHYTYPE_G:
3111                 if (phy_rev > 9)
3112                         unsupported = 1;
3113                 break;
3114 #ifdef CONFIG_B43_NPHY
3115         case B43_PHYTYPE_N:
3116                 if (phy_rev > 1)
3117                         unsupported = 1;
3118                 break;
3119 #endif
3120         default:
3121                 unsupported = 1;
3122         };
3123         if (unsupported) {
3124                 b43err(dev->wl, "FOUND UNSUPPORTED PHY "
3125                        "(Analog %u, Type %u, Revision %u)\n",
3126                        analog_type, phy_type, phy_rev);
3127                 return -EOPNOTSUPP;
3128         }
3129         b43dbg(dev->wl, "Found PHY: Analog %u, Type %u, Revision %u\n",
3130                analog_type, phy_type, phy_rev);
3131
3132         /* Get RADIO versioning */
3133         if (dev->dev->bus->chip_id == 0x4317) {
3134                 if (dev->dev->bus->chip_rev == 0)
3135                         tmp = 0x3205017F;
3136                 else if (dev->dev->bus->chip_rev == 1)
3137                         tmp = 0x4205017F;
3138                 else
3139                         tmp = 0x5205017F;
3140         } else {
3141                 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
3142                 tmp = b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
3143                 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
3144                 tmp |= (u32)b43_read16(dev, B43_MMIO_RADIO_DATA_HIGH) << 16;
3145         }
3146         radio_manuf = (tmp & 0x00000FFF);
3147         radio_ver = (tmp & 0x0FFFF000) >> 12;
3148         radio_rev = (tmp & 0xF0000000) >> 28;
3149         if (radio_manuf != 0x17F /* Broadcom */)
3150                 unsupported = 1;
3151         switch (phy_type) {
3152         case B43_PHYTYPE_A:
3153                 if (radio_ver != 0x2060)
3154                         unsupported = 1;
3155                 if (radio_rev != 1)
3156                         unsupported = 1;
3157                 if (radio_manuf != 0x17F)
3158                         unsupported = 1;
3159                 break;
3160         case B43_PHYTYPE_B:
3161                 if ((radio_ver & 0xFFF0) != 0x2050)
3162                         unsupported = 1;
3163                 break;
3164         case B43_PHYTYPE_G:
3165                 if (radio_ver != 0x2050)
3166                         unsupported = 1;
3167                 break;
3168         case B43_PHYTYPE_N:
3169                 if (radio_ver != 0x2055)
3170                         unsupported = 1;
3171                 break;
3172         default:
3173                 B43_WARN_ON(1);
3174         }
3175         if (unsupported) {
3176                 b43err(dev->wl, "FOUND UNSUPPORTED RADIO "
3177                        "(Manuf 0x%X, Version 0x%X, Revision %u)\n",
3178                        radio_manuf, radio_ver, radio_rev);
3179                 return -EOPNOTSUPP;
3180         }
3181         b43dbg(dev->wl, "Found Radio: Manuf 0x%X, Version 0x%X, Revision %u\n",
3182                radio_manuf, radio_ver, radio_rev);
3183
3184         phy->radio_manuf = radio_manuf;
3185         phy->radio_ver = radio_ver;
3186         phy->radio_rev = radio_rev;
3187
3188         phy->analog = analog_type;
3189         phy->type = phy_type;
3190         phy->rev = phy_rev;
3191
3192         return 0;
3193 }
3194
3195 static void setup_struct_phy_for_init(struct b43_wldev *dev,
3196                                       struct b43_phy *phy)
3197 {
3198         struct b43_txpower_lo_control *lo;
3199         int i;
3200
3201         memset(phy->minlowsig, 0xFF, sizeof(phy->minlowsig));
3202         memset(phy->minlowsigpos, 0, sizeof(phy->minlowsigpos));
3203
3204         phy->aci_enable = 0;
3205         phy->aci_wlan_automatic = 0;
3206         phy->aci_hw_rssi = 0;
3207
3208         phy->radio_off_context.valid = 0;
3209
3210         lo = phy->lo_control;
3211         if (lo) {
3212                 memset(lo, 0, sizeof(*(phy->lo_control)));
3213                 lo->rebuild = 1;
3214                 lo->tx_bias = 0xFF;
3215         }
3216         phy->max_lb_gain = 0;
3217         phy->trsw_rx_gain = 0;
3218         phy->txpwr_offset = 0;
3219
3220         /* NRSSI */
3221         phy->nrssislope = 0;
3222         for (i = 0; i < ARRAY_SIZE(phy->nrssi); i++)
3223                 phy->nrssi[i] = -1000;
3224         for (i = 0; i < ARRAY_SIZE(phy->nrssi_lt); i++)
3225                 phy->nrssi_lt[i] = i;
3226
3227         phy->lofcal = 0xFFFF;
3228         phy->initval = 0xFFFF;
3229
3230         phy->interfmode = B43_INTERFMODE_NONE;
3231         phy->channel = 0xFF;
3232
3233         phy->hardware_power_control = !!modparam_hwpctl;
3234
3235         /* PHY TX errors counter. */
3236         atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
3237
3238         /* OFDM-table address caching. */
3239         phy->ofdmtab_addr_direction = B43_OFDMTAB_DIRECTION_UNKNOWN;
3240 }
3241
3242 static void setup_struct_wldev_for_init(struct b43_wldev *dev)
3243 {
3244         dev->dfq_valid = 0;
3245
3246         /* Assume the radio is enabled. If it's not enabled, the state will
3247          * immediately get fixed on the first periodic work run. */
3248         dev->radio_hw_enable = 1;
3249
3250         /* Stats */
3251         memset(&dev->stats, 0, sizeof(dev->stats));
3252
3253         setup_struct_phy_for_init(dev, &dev->phy);
3254
3255         /* IRQ related flags */
3256         dev->irq_reason = 0;
3257         memset(dev->dma_reason, 0, sizeof(dev->dma_reason));
3258         dev->irq_savedstate = B43_IRQ_MASKTEMPLATE;
3259
3260         dev->mac_suspended = 1;
3261
3262         /* Noise calculation context */
3263         memset(&dev->noisecalc, 0, sizeof(dev->noisecalc));
3264 }
3265
3266 static void b43_bluetooth_coext_enable(struct b43_wldev *dev)
3267 {
3268         struct ssb_sprom *sprom = &dev->dev->bus->sprom;
3269         u32 hf;
3270
3271         if (!(sprom->boardflags_lo & B43_BFL_BTCOEXIST))
3272                 return;
3273         if (dev->phy.type != B43_PHYTYPE_B && !dev->phy.gmode)
3274                 return;
3275
3276         hf = b43_hf_read(dev);
3277         if (sprom->boardflags_lo & B43_BFL_BTCMOD)
3278                 hf |= B43_HF_BTCOEXALT;
3279         else
3280                 hf |= B43_HF_BTCOEX;
3281         b43_hf_write(dev, hf);
3282         //TODO
3283 }
3284
3285 static void b43_bluetooth_coext_disable(struct b43_wldev *dev)
3286 {                               //TODO
3287 }
3288
3289 static void b43_imcfglo_timeouts_workaround(struct b43_wldev *dev)
3290 {
3291 #ifdef CONFIG_SSB_DRIVER_PCICORE
3292         struct ssb_bus *bus = dev->dev->bus;
3293         u32 tmp;
3294
3295         if (bus->pcicore.dev &&
3296             bus->pcicore.dev->id.coreid == SSB_DEV_PCI &&
3297             bus->pcicore.dev->id.revision <= 5) {
3298                 /* IMCFGLO timeouts workaround. */
3299                 tmp = ssb_read32(dev->dev, SSB_IMCFGLO);
3300                 tmp &= ~SSB_IMCFGLO_REQTO;
3301                 tmp &= ~SSB_IMCFGLO_SERTO;
3302                 switch (bus->bustype) {
3303                 case SSB_BUSTYPE_PCI:
3304                 case SSB_BUSTYPE_PCMCIA:
3305                         tmp |= 0x32;
3306                         break;
3307                 case SSB_BUSTYPE_SSB:
3308                         tmp |= 0x53;
3309                         break;
3310                 }
3311                 ssb_write32(dev->dev, SSB_IMCFGLO, tmp);
3312         }
3313 #endif /* CONFIG_SSB_DRIVER_PCICORE */
3314 }
3315
3316 /* Write the short and long frame retry limit values. */
3317 static void b43_set_retry_limits(struct b43_wldev *dev,
3318                                  unsigned int short_retry,
3319                                  unsigned int long_retry)
3320 {
3321         /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing
3322          * the chip-internal counter. */
3323         short_retry = min(short_retry, (unsigned int)0xF);
3324         long_retry = min(long_retry, (unsigned int)0xF);
3325
3326         b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_SRLIMIT,
3327                         short_retry);
3328         b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_LRLIMIT,
3329                         long_retry);
3330 }
3331
3332 /* Shutdown a wireless core */
3333 /* Locking: wl->mutex */
3334 static void b43_wireless_core_exit(struct b43_wldev *dev)
3335 {
3336         struct b43_phy *phy = &dev->phy;
3337
3338         B43_WARN_ON(b43_status(dev) > B43_STAT_INITIALIZED);
3339         if (b43_status(dev) != B43_STAT_INITIALIZED)
3340                 return;
3341         b43_set_status(dev, B43_STAT_UNINIT);
3342
3343         b43_leds_exit(dev);
3344         b43_rng_exit(dev->wl);
3345         b43_dma_free(dev);
3346         b43_chip_exit(dev);
3347         b43_radio_turn_off(dev, 1);
3348         b43_switch_analog(dev, 0);
3349         if (phy->dyn_tssi_tbl)
3350                 kfree(phy->tssi2dbm);
3351         kfree(phy->lo_control);
3352         phy->lo_control = NULL;
3353         if (dev->wl->current_beacon) {
3354                 dev_kfree_skb_any(dev->wl->current_beacon);
3355                 dev->wl->current_beacon = NULL;
3356         }
3357
3358         ssb_device_disable(dev->dev, 0);
3359         ssb_bus_may_powerdown(dev->dev->bus);
3360 }
3361
3362 /* Initialize a wireless core */
3363 static int b43_wireless_core_init(struct b43_wldev *dev)
3364 {
3365         struct b43_wl *wl = dev->wl;
3366         struct ssb_bus *bus = dev->dev->bus;
3367         struct ssb_sprom *sprom = &bus->sprom;
3368         struct b43_phy *phy = &dev->phy;
3369         int err;
3370         u32 hf, tmp;
3371
3372         B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
3373
3374         err = ssb_bus_powerup(bus, 0);
3375         if (err)
3376                 goto out;
3377         if (!ssb_device_is_enabled(dev->dev)) {
3378                 tmp = phy->gmode ? B43_TMSLOW_GMODE : 0;
3379                 b43_wireless_core_reset(dev, tmp);
3380         }
3381
3382         if ((phy->type == B43_PHYTYPE_B) || (phy->type == B43_PHYTYPE_G)) {
3383                 phy->lo_control =
3384                     kzalloc(sizeof(*(phy->lo_control)), GFP_KERNEL);
3385                 if (!phy->lo_control) {
3386                         err = -ENOMEM;
3387                         goto err_busdown;
3388                 }
3389         }
3390         setup_struct_wldev_for_init(dev);
3391
3392         err = b43_phy_init_tssi2dbm_table(dev);
3393         if (err)
3394                 goto err_kfree_lo_control;
3395
3396         /* Enable IRQ routing to this device. */
3397         ssb_pcicore_dev_irqvecs_enable(&bus->pcicore, dev->dev);
3398
3399         b43_imcfglo_timeouts_workaround(dev);
3400         b43_bluetooth_coext_disable(dev);
3401         b43_phy_early_init(dev);
3402         err = b43_chip_init(dev);
3403         if (err)
3404                 goto err_kfree_tssitbl;
3405         b43_shm_write16(dev, B43_SHM_SHARED,
3406                         B43_SHM_SH_WLCOREREV, dev->dev->id.revision);
3407         hf = b43_hf_read(dev);
3408         if (phy->type == B43_PHYTYPE_G) {
3409                 hf |= B43_HF_SYMW;
3410                 if (phy->rev == 1)
3411                         hf |= B43_HF_GDCW;
3412                 if (sprom->boardflags_lo & B43_BFL_PACTRL)
3413                         hf |= B43_HF_OFDMPABOOST;
3414         } else if (phy->type == B43_PHYTYPE_B) {
3415                 hf |= B43_HF_SYMW;
3416                 if (phy->rev >= 2 && phy->radio_ver == 0x2050)
3417                         hf &= ~B43_HF_GDCW;
3418         }
3419         b43_hf_write(dev, hf);
3420
3421         b43_set_retry_limits(dev, B43_DEFAULT_SHORT_RETRY_LIMIT,
3422                              B43_DEFAULT_LONG_RETRY_LIMIT);
3423         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SFFBLIM, 3);
3424         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_LFFBLIM, 2);
3425
3426         /* Disable sending probe responses from firmware.
3427          * Setting the MaxTime to one usec will always trigger
3428          * a timeout, so we never send any probe resp.
3429          * A timeout of zero is infinite. */
3430         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 1);
3431
3432         b43_rate_memory_init(dev);
3433
3434         /* Minimum Contention Window */
3435         if (phy->type == B43_PHYTYPE_B) {
3436                 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0x1F);
3437         } else {
3438                 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0xF);
3439         }
3440         /* Maximum Contention Window */
3441         b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MAXCONT, 0x3FF);
3442
3443         err = b43_dma_init(dev);
3444         if (err)
3445                 goto err_chip_exit;
3446         b43_qos_init(dev);
3447
3448 //FIXME
3449 #if 1
3450         b43_write16(dev, 0x0612, 0x0050);
3451         b43_shm_write16(dev, B43_SHM_SHARED, 0x0416, 0x0050);
3452         b43_shm_write16(dev, B43_SHM_SHARED, 0x0414, 0x01F4);
3453 #endif
3454
3455         b43_bluetooth_coext_enable(dev);
3456
3457         ssb_bus_powerup(bus, 1);        /* Enable dynamic PCTL */
3458         memset(wl->bssid, 0, ETH_ALEN);
3459         memset(wl->mac_addr, 0, ETH_ALEN);
3460         b43_upload_card_macaddress(dev);
3461         b43_security_init(dev);
3462         b43_rng_init(wl);
3463
3464         b43_set_status(dev, B43_STAT_INITIALIZED);
3465
3466         b43_leds_init(dev);
3467 out:
3468         return err;
3469
3470       err_chip_exit:
3471         b43_chip_exit(dev);
3472       err_kfree_tssitbl:
3473         if (phy->dyn_tssi_tbl)
3474                 kfree(phy->tssi2dbm);
3475       err_kfree_lo_control:
3476         kfree(phy->lo_control);
3477         phy->lo_control = NULL;
3478       err_busdown:
3479         ssb_bus_may_powerdown(bus);
3480         B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
3481         return err;
3482 }
3483
3484 static int b43_op_add_interface(struct ieee80211_hw *hw,
3485                                 struct ieee80211_if_init_conf *conf)
3486 {
3487         struct b43_wl *wl = hw_to_b43_wl(hw);
3488         struct b43_wldev *dev;
3489         unsigned long flags;
3490         int err = -EOPNOTSUPP;
3491
3492         /* TODO: allow WDS/AP devices to coexist */
3493
3494         if (conf->type != IEEE80211_IF_TYPE_AP &&
3495             conf->type != IEEE80211_IF_TYPE_STA &&
3496             conf->type != IEEE80211_IF_TYPE_WDS &&
3497             conf->type != IEEE80211_IF_TYPE_IBSS)
3498                 return -EOPNOTSUPP;
3499
3500         mutex_lock(&wl->mutex);
3501         if (wl->operating)
3502                 goto out_mutex_unlock;
3503
3504         b43dbg(wl, "Adding Interface type %d\n", conf->type);
3505
3506         dev = wl->current_dev;
3507         wl->operating = 1;
3508         wl->vif = conf->vif;
3509         wl->if_type = conf->type;
3510         memcpy(wl->mac_addr, conf->mac_addr, ETH_ALEN);
3511
3512         spin_lock_irqsave(&wl->irq_lock, flags);
3513         b43_adjust_opmode(dev);
3514         b43_upload_card_macaddress(dev);
3515         spin_unlock_irqrestore(&wl->irq_lock, flags);
3516
3517         err = 0;
3518  out_mutex_unlock:
3519         mutex_unlock(&wl->mutex);
3520
3521         return err;
3522 }
3523
3524 static void b43_op_remove_interface(struct ieee80211_hw *hw,
3525                                     struct ieee80211_if_init_conf *conf)
3526 {
3527         struct b43_wl *wl = hw_to_b43_wl(hw);
3528         struct b43_wldev *dev = wl->current_dev;
3529         unsigned long flags;
3530
3531         b43dbg(wl, "Removing Interface type %d\n", conf->type);
3532
3533         mutex_lock(&wl->mutex);
3534
3535         B43_WARN_ON(!wl->operating);
3536         B43_WARN_ON(wl->vif != conf->vif);
3537         wl->vif = NULL;
3538
3539         wl->operating = 0;
3540
3541         spin_lock_irqsave(&wl->irq_lock, flags);
3542         b43_adjust_opmode(dev);
3543         memset(wl->mac_addr, 0, ETH_ALEN);
3544         b43_upload_card_macaddress(dev);
3545         spin_unlock_irqrestore(&wl->irq_lock, flags);
3546
3547         mutex_unlock(&wl->mutex);
3548 }
3549
3550 static int b43_op_start(struct ieee80211_hw *hw)
3551 {
3552         struct b43_wl *wl = hw_to_b43_wl(hw);
3553         struct b43_wldev *dev = wl->current_dev;
3554         int did_init = 0;
3555         int err = 0;
3556
3557         /* First register RFkill.
3558          * LEDs that are registered later depend on it. */
3559         b43_rfkill_init(dev);
3560
3561         mutex_lock(&wl->mutex);
3562
3563         if (b43_status(dev) < B43_STAT_INITIALIZED) {
3564                 err = b43_wireless_core_init(dev);
3565                 if (err)
3566                         goto out_mutex_unlock;
3567                 did_init = 1;
3568         }
3569
3570         if (b43_status(dev) < B43_STAT_STARTED) {
3571                 err = b43_wireless_core_start(dev);
3572                 if (err) {
3573                         if (did_init)
3574                                 b43_wireless_core_exit(dev);
3575                         goto out_mutex_unlock;
3576                 }
3577         }
3578
3579  out_mutex_unlock:
3580         mutex_unlock(&wl->mutex);
3581
3582         return err;
3583 }
3584
3585 static void b43_op_stop(struct ieee80211_hw *hw)
3586 {
3587         struct b43_wl *wl = hw_to_b43_wl(hw);
3588         struct b43_wldev *dev = wl->current_dev;
3589
3590         b43_rfkill_exit(dev);
3591
3592         mutex_lock(&wl->mutex);
3593         if (b43_status(dev) >= B43_STAT_STARTED)
3594                 b43_wireless_core_stop(dev);
3595         b43_wireless_core_exit(dev);
3596         mutex_unlock(&wl->mutex);
3597 }
3598
3599 static int b43_op_set_retry_limit(struct ieee80211_hw *hw,
3600                                   u32 short_retry_limit, u32 long_retry_limit)
3601 {
3602         struct b43_wl *wl = hw_to_b43_wl(hw);
3603         struct b43_wldev *dev;
3604         int err = 0;
3605
3606         mutex_lock(&wl->mutex);
3607         dev = wl->current_dev;
3608         if (unlikely(!dev || (b43_status(dev) < B43_STAT_INITIALIZED))) {
3609                 err = -ENODEV;
3610                 goto out_unlock;
3611         }
3612         b43_set_retry_limits(dev, short_retry_limit, long_retry_limit);
3613 out_unlock:
3614         mutex_unlock(&wl->mutex);
3615
3616         return err;
3617 }
3618
3619 static int b43_op_beacon_set_tim(struct ieee80211_hw *hw, int aid, int set)
3620 {
3621         struct b43_wl *wl = hw_to_b43_wl(hw);
3622         struct sk_buff *beacon;
3623         unsigned long flags;
3624
3625         /* We could modify the existing beacon and set the aid bit in
3626          * the TIM field, but that would probably require resizing and
3627          * moving of data within the beacon template.
3628          * Simply request a new beacon and let mac80211 do the hard work. */
3629         beacon = ieee80211_beacon_get(hw, wl->vif, NULL);
3630         if (unlikely(!beacon))
3631                 return -ENOMEM;
3632         spin_lock_irqsave(&wl->irq_lock, flags);
3633         b43_update_templates(wl, beacon);
3634         spin_unlock_irqrestore(&wl->irq_lock, flags);
3635
3636         return 0;
3637 }
3638
3639 static int b43_op_ibss_beacon_update(struct ieee80211_hw *hw,
3640                                      struct sk_buff *beacon,
3641                                      struct ieee80211_tx_control *ctl)
3642 {
3643         struct b43_wl *wl = hw_to_b43_wl(hw);
3644         unsigned long flags;
3645
3646         spin_lock_irqsave(&wl->irq_lock, flags);
3647         b43_update_templates(wl, beacon);
3648         spin_unlock_irqrestore(&wl->irq_lock, flags);
3649
3650         return 0;
3651 }
3652
3653 static const struct ieee80211_ops b43_hw_ops = {
3654         .tx                     = b43_op_tx,
3655         .conf_tx                = b43_op_conf_tx,
3656         .add_interface          = b43_op_add_interface,
3657         .remove_interface       = b43_op_remove_interface,
3658         .config                 = b43_op_config,
3659         .config_interface       = b43_op_config_interface,
3660         .configure_filter       = b43_op_configure_filter,
3661         .set_key                = b43_op_set_key,
3662         .get_stats              = b43_op_get_stats,
3663         .get_tx_stats           = b43_op_get_tx_stats,
3664         .start                  = b43_op_start,
3665         .stop                   = b43_op_stop,
3666         .set_retry_limit        = b43_op_set_retry_limit,
3667         .set_tim                = b43_op_beacon_set_tim,
3668         .beacon_update          = b43_op_ibss_beacon_update,
3669 };
3670
3671 /* Hard-reset the chip. Do not call this directly.
3672  * Use b43_controller_restart()
3673  */
3674 static void b43_chip_reset(struct work_struct *work)
3675 {
3676         struct b43_wldev *dev =
3677             container_of(work, struct b43_wldev, restart_work);
3678         struct b43_wl *wl = dev->wl;
3679         int err = 0;
3680         int prev_status;
3681
3682         mutex_lock(&wl->mutex);
3683
3684         prev_status = b43_status(dev);
3685         /* Bring the device down... */
3686         if (prev_status >= B43_STAT_STARTED)
3687                 b43_wireless_core_stop(dev);
3688         if (prev_status >= B43_STAT_INITIALIZED)
3689                 b43_wireless_core_exit(dev);
3690
3691         /* ...and up again. */
3692         if (prev_status >= B43_STAT_INITIALIZED) {
3693                 err = b43_wireless_core_init(dev);
3694                 if (err)
3695                         goto out;
3696         }
3697         if (prev_status >= B43_STAT_STARTED) {
3698                 err = b43_wireless_core_start(dev);
3699                 if (err) {
3700                         b43_wireless_core_exit(dev);
3701                         goto out;
3702                 }
3703         }
3704       out:
3705         mutex_unlock(&wl->mutex);
3706         if (err)
3707                 b43err(wl, "Controller restart FAILED\n");
3708         else
3709                 b43info(wl, "Controller restarted\n");
3710 }
3711
3712 static int b43_setup_modes(struct b43_wldev *dev,
3713                            bool have_2ghz_phy, bool have_5ghz_phy)
3714 {
3715         struct ieee80211_hw *hw = dev->wl->hw;
3716         struct ieee80211_hw_mode *mode;
3717         struct b43_phy *phy = &dev->phy;
3718         int err;
3719
3720         /* XXX: This function will go away soon, when mac80211
3721          *      band stuff is rewritten. So this is just a hack.
3722          *      For now we always claim GPHY mode, as there is no
3723          *      support for NPHY and APHY in the device, yet.
3724          *      This assumption is OK, as any B, N or A PHY will already
3725          *      have died a horrible sanity check death earlier. */
3726
3727         mode = &phy->hwmodes[0];
3728         mode->mode = MODE_IEEE80211G;
3729         mode->num_channels = b43_2ghz_chantable_size;
3730         mode->channels = b43_2ghz_chantable;
3731         mode->num_rates = b43_g_ratetable_size;
3732         mode->rates = b43_g_ratetable;
3733         err = ieee80211_register_hwmode(hw, mode);
3734         if (err)
3735                 return err;
3736         phy->possible_phymodes |= B43_PHYMODE_G;
3737
3738         return 0;
3739 }
3740
3741 static void b43_wireless_core_detach(struct b43_wldev *dev)
3742 {
3743         /* We release firmware that late to not be required to re-request
3744          * is all the time when we reinit the core. */
3745         b43_release_firmware(dev);
3746 }
3747
3748 static int b43_wireless_core_attach(struct b43_wldev *dev)
3749 {
3750         struct b43_wl *wl = dev->wl;
3751         struct ssb_bus *bus = dev->dev->bus;
3752         struct pci_dev *pdev = bus->host_pci;
3753         int err;
3754         bool have_2ghz_phy = 0, have_5ghz_phy = 0;
3755         u32 tmp;
3756
3757         /* Do NOT do any device initialization here.
3758          * Do it in wireless_core_init() instead.
3759          * This function is for gathering basic information about the HW, only.
3760          * Also some structs may be set up here. But most likely you want to have
3761          * that in core_init(), too.
3762          */
3763
3764         err = ssb_bus_powerup(bus, 0);
3765         if (err) {
3766                 b43err(wl, "Bus powerup failed\n");
3767                 goto out;
3768         }
3769         /* Get the PHY type. */
3770         if (dev->dev->id.revision >= 5) {
3771                 u32 tmshigh;
3772
3773                 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
3774                 have_2ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY);
3775                 have_5ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_5GHZ_PHY);
3776         } else
3777                 B43_WARN_ON(1);
3778
3779         dev->phy.gmode = have_2ghz_phy;
3780         tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
3781         b43_wireless_core_reset(dev, tmp);
3782
3783         err = b43_phy_versioning(dev);
3784         if (err)
3785                 goto err_powerdown;
3786         /* Check if this device supports multiband. */
3787         if (!pdev ||
3788             (pdev->device != 0x4312 &&
3789              pdev->device != 0x4319 && pdev->device != 0x4324)) {
3790                 /* No multiband support. */
3791                 have_2ghz_phy = 0;
3792                 have_5ghz_phy = 0;
3793                 switch (dev->phy.type) {
3794                 case B43_PHYTYPE_A:
3795                         have_5ghz_phy = 1;
3796                         break;
3797                 case B43_PHYTYPE_G:
3798                 case B43_PHYTYPE_N:
3799                         have_2ghz_phy = 1;
3800                         break;
3801                 default:
3802                         B43_WARN_ON(1);
3803                 }
3804         }
3805         if (dev->phy.type == B43_PHYTYPE_A) {
3806                 /* FIXME */
3807                 b43err(wl, "IEEE 802.11a devices are unsupported\n");
3808                 err = -EOPNOTSUPP;
3809                 goto err_powerdown;
3810         }
3811         dev->phy.gmode = have_2ghz_phy;
3812         tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
3813         b43_wireless_core_reset(dev, tmp);
3814
3815         err = b43_validate_chipaccess(dev);
3816         if (err)
3817                 goto err_powerdown;
3818         err = b43_setup_modes(dev, have_2ghz_phy, have_5ghz_phy);
3819         if (err)
3820                 goto err_powerdown;
3821
3822         /* Now set some default "current_dev" */
3823         if (!wl->current_dev)
3824                 wl->current_dev = dev;
3825         INIT_WORK(&dev->restart_work, b43_chip_reset);
3826
3827         b43_radio_turn_off(dev, 1);
3828         b43_switch_analog(dev, 0);
3829         ssb_device_disable(dev->dev, 0);
3830         ssb_bus_may_powerdown(bus);
3831
3832 out:
3833         return err;
3834
3835 err_powerdown:
3836         ssb_bus_may_powerdown(bus);
3837         return err;
3838 }
3839
3840 static void b43_one_core_detach(struct ssb_device *dev)
3841 {
3842         struct b43_wldev *wldev;
3843         struct b43_wl *wl;
3844
3845         wldev = ssb_get_drvdata(dev);
3846         wl = wldev->wl;
3847         cancel_work_sync(&wldev->restart_work);
3848         b43_debugfs_remove_device(wldev);
3849         b43_wireless_core_detach(wldev);
3850         list_del(&wldev->list);
3851         wl->nr_devs--;
3852         ssb_set_drvdata(dev, NULL);
3853         kfree(wldev);
3854 }
3855
3856 static int b43_one_core_attach(struct ssb_device *dev, struct b43_wl *wl)
3857 {
3858         struct b43_wldev *wldev;
3859         struct pci_dev *pdev;
3860         int err = -ENOMEM;
3861
3862         if (!list_empty(&wl->devlist)) {
3863                 /* We are not the first core on this chip. */
3864                 pdev = dev->bus->host_pci;
3865                 /* Only special chips support more than one wireless
3866                  * core, although some of the other chips have more than
3867                  * one wireless core as well. Check for this and
3868                  * bail out early.
3869                  */
3870                 if (!pdev ||
3871                     ((pdev->device != 0x4321) &&
3872                      (pdev->device != 0x4313) && (pdev->device != 0x431A))) {
3873                         b43dbg(wl, "Ignoring unconnected 802.11 core\n");
3874                         return -ENODEV;
3875                 }
3876         }
3877
3878         wldev = kzalloc(sizeof(*wldev), GFP_KERNEL);
3879         if (!wldev)
3880                 goto out;
3881
3882         wldev->dev = dev;
3883         wldev->wl = wl;
3884         b43_set_status(wldev, B43_STAT_UNINIT);
3885         wldev->bad_frames_preempt = modparam_bad_frames_preempt;
3886         tasklet_init(&wldev->isr_tasklet,
3887                      (void (*)(unsigned long))b43_interrupt_tasklet,
3888                      (unsigned long)wldev);
3889         INIT_LIST_HEAD(&wldev->list);
3890
3891         err = b43_wireless_core_attach(wldev);
3892         if (err)
3893                 goto err_kfree_wldev;
3894
3895         list_add(&wldev->list, &wl->devlist);
3896         wl->nr_devs++;
3897         ssb_set_drvdata(dev, wldev);
3898         b43_debugfs_add_device(wldev);
3899
3900       out:
3901         return err;
3902
3903       err_kfree_wldev:
3904         kfree(wldev);
3905         return err;
3906 }
3907
3908 static void b43_sprom_fixup(struct ssb_bus *bus)
3909 {
3910         /* boardflags workarounds */
3911         if (bus->boardinfo.vendor == SSB_BOARDVENDOR_DELL &&
3912             bus->chip_id == 0x4301 && bus->boardinfo.rev == 0x74)
3913                 bus->sprom.boardflags_lo |= B43_BFL_BTCOEXIST;
3914         if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
3915             bus->boardinfo.type == 0x4E && bus->boardinfo.rev > 0x40)
3916                 bus->sprom.boardflags_lo |= B43_BFL_PACTRL;
3917 }
3918
3919 static void b43_wireless_exit(struct ssb_device *dev, struct b43_wl *wl)
3920 {
3921         struct ieee80211_hw *hw = wl->hw;
3922
3923         ssb_set_devtypedata(dev, NULL);
3924         ieee80211_free_hw(hw);
3925 }
3926
3927 static int b43_wireless_init(struct ssb_device *dev)
3928 {
3929         struct ssb_sprom *sprom = &dev->bus->sprom;
3930         struct ieee80211_hw *hw;
3931         struct b43_wl *wl;
3932         int err = -ENOMEM;
3933
3934         b43_sprom_fixup(dev->bus);
3935
3936         hw = ieee80211_alloc_hw(sizeof(*wl), &b43_hw_ops);
3937         if (!hw) {
3938                 b43err(NULL, "Could not allocate ieee80211 device\n");
3939                 goto out;
3940         }
3941
3942         /* fill hw info */
3943         hw->flags = IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE |
3944                     IEEE80211_HW_RX_INCLUDES_FCS;
3945         hw->max_signal = 100;
3946         hw->max_rssi = -110;
3947         hw->max_noise = -110;
3948         hw->queues = 1;         /* FIXME: hardware has more queues */
3949         SET_IEEE80211_DEV(hw, dev->dev);
3950         if (is_valid_ether_addr(sprom->et1mac))
3951                 SET_IEEE80211_PERM_ADDR(hw, sprom->et1mac);
3952         else
3953                 SET_IEEE80211_PERM_ADDR(hw, sprom->il0mac);
3954
3955         /* Get and initialize struct b43_wl */
3956         wl = hw_to_b43_wl(hw);
3957         memset(wl, 0, sizeof(*wl));
3958         wl->hw = hw;
3959         spin_lock_init(&wl->irq_lock);
3960         spin_lock_init(&wl->leds_lock);
3961         spin_lock_init(&wl->shm_lock);
3962         mutex_init(&wl->mutex);
3963         INIT_LIST_HEAD(&wl->devlist);
3964
3965         ssb_set_devtypedata(dev, wl);
3966         b43info(wl, "Broadcom %04X WLAN found\n", dev->bus->chip_id);
3967         err = 0;
3968       out:
3969         return err;
3970 }
3971
3972 static int b43_probe(struct ssb_device *dev, const struct ssb_device_id *id)
3973 {
3974         struct b43_wl *wl;
3975         int err;
3976         int first = 0;
3977
3978         wl = ssb_get_devtypedata(dev);
3979         if (!wl) {
3980                 /* Probing the first core. Must setup common struct b43_wl */
3981                 first = 1;
3982                 err = b43_wireless_init(dev);
3983                 if (err)
3984                         goto out;
3985                 wl = ssb_get_devtypedata(dev);
3986                 B43_WARN_ON(!wl);
3987         }
3988         err = b43_one_core_attach(dev, wl);
3989         if (err)
3990                 goto err_wireless_exit;
3991
3992         if (first) {
3993                 err = ieee80211_register_hw(wl->hw);
3994                 if (err)
3995                         goto err_one_core_detach;
3996         }
3997
3998       out:
3999         return err;
4000
4001       err_one_core_detach:
4002         b43_one_core_detach(dev);
4003       err_wireless_exit:
4004         if (first)
4005                 b43_wireless_exit(dev, wl);
4006         return err;
4007 }
4008
4009 static void b43_remove(struct ssb_device *dev)
4010 {
4011         struct b43_wl *wl = ssb_get_devtypedata(dev);
4012         struct b43_wldev *wldev = ssb_get_drvdata(dev);
4013
4014         B43_WARN_ON(!wl);
4015         if (wl->current_dev == wldev)
4016                 ieee80211_unregister_hw(wl->hw);
4017
4018         b43_one_core_detach(dev);
4019
4020         if (list_empty(&wl->devlist)) {
4021                 /* Last core on the chip unregistered.
4022                  * We can destroy common struct b43_wl.
4023                  */
4024                 b43_wireless_exit(dev, wl);
4025         }
4026 }
4027
4028 /* Perform a hardware reset. This can be called from any context. */
4029 void b43_controller_restart(struct b43_wldev *dev, const char *reason)
4030 {
4031         /* Must avoid requeueing, if we are in shutdown. */
4032         if (b43_status(dev) < B43_STAT_INITIALIZED)
4033                 return;
4034         b43info(dev->wl, "Controller RESET (%s) ...\n", reason);
4035         queue_work(dev->wl->hw->workqueue, &dev->restart_work);
4036 }
4037
4038 #ifdef CONFIG_PM
4039
4040 static int b43_suspend(struct ssb_device *dev, pm_message_t state)
4041 {
4042         struct b43_wldev *wldev = ssb_get_drvdata(dev);
4043         struct b43_wl *wl = wldev->wl;
4044
4045         b43dbg(wl, "Suspending...\n");
4046
4047         mutex_lock(&wl->mutex);
4048         wldev->suspend_init_status = b43_status(wldev);
4049         if (wldev->suspend_init_status >= B43_STAT_STARTED)
4050                 b43_wireless_core_stop(wldev);
4051         if (wldev->suspend_init_status >= B43_STAT_INITIALIZED)
4052                 b43_wireless_core_exit(wldev);
4053         mutex_unlock(&wl->mutex);
4054
4055         b43dbg(wl, "Device suspended.\n");
4056
4057         return 0;
4058 }
4059
4060 static int b43_resume(struct ssb_device *dev)
4061 {
4062         struct b43_wldev *wldev = ssb_get_drvdata(dev);
4063         struct b43_wl *wl = wldev->wl;
4064         int err = 0;
4065
4066         b43dbg(wl, "Resuming...\n");
4067
4068         mutex_lock(&wl->mutex);
4069         if (wldev->suspend_init_status >= B43_STAT_INITIALIZED) {
4070                 err = b43_wireless_core_init(wldev);
4071                 if (err) {
4072                         b43err(wl, "Resume failed at core init\n");
4073                         goto out;
4074                 }
4075         }
4076         if (wldev->suspend_init_status >= B43_STAT_STARTED) {
4077                 err = b43_wireless_core_start(wldev);
4078                 if (err) {
4079                         b43_wireless_core_exit(wldev);
4080                         b43err(wl, "Resume failed at core start\n");
4081                         goto out;
4082                 }
4083         }
4084         mutex_unlock(&wl->mutex);
4085
4086         b43dbg(wl, "Device resumed.\n");
4087       out:
4088         return err;
4089 }
4090
4091 #else /* CONFIG_PM */
4092 # define b43_suspend    NULL
4093 # define b43_resume     NULL
4094 #endif /* CONFIG_PM */
4095
4096 static struct ssb_driver b43_ssb_driver = {
4097         .name           = KBUILD_MODNAME,
4098         .id_table       = b43_ssb_tbl,
4099         .probe          = b43_probe,
4100         .remove         = b43_remove,
4101         .suspend        = b43_suspend,
4102         .resume         = b43_resume,
4103 };
4104
4105 static int __init b43_init(void)
4106 {
4107         int err;
4108
4109         b43_debugfs_init();
4110         err = b43_pcmcia_init();
4111         if (err)
4112                 goto err_dfs_exit;
4113         err = ssb_driver_register(&b43_ssb_driver);
4114         if (err)
4115                 goto err_pcmcia_exit;
4116
4117         return err;
4118
4119 err_pcmcia_exit:
4120         b43_pcmcia_exit();
4121 err_dfs_exit:
4122         b43_debugfs_exit();
4123         return err;
4124 }
4125
4126 static void __exit b43_exit(void)
4127 {
4128         ssb_driver_unregister(&b43_ssb_driver);
4129         b43_pcmcia_exit();
4130         b43_debugfs_exit();
4131 }
4132
4133 module_init(b43_init)
4134 module_exit(b43_exit)