SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/net/wireless/ath9k/main.c

   1 /*
   2  * Copyright (c) 2008 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/nl80211.h>
  18 #include "ath9k.h"
  19
  20 #define ATH_PCI_VERSION "0.1"
  21
  22 static char *dev_info = "ath9k";
  23
  24 MODULE_AUTHOR("Atheros Communications");
  25 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
  26 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
  27 MODULE_LICENSE("Dual BSD/GPL");
  28
  29 static int modparam_nohwcrypt;
  30 module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
  31 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
  32
  33 /* We use the hw_value as an index into our private channel structure */
  34
  35 #define CHAN2G(_freq, _idx)  { \
  36         .center_freq = (_freq), \
  37         .hw_value = (_idx), \
  38         .max_power = 30, \
  39 }
  40
  41 #define CHAN5G(_freq, _idx) { \
  42         .band = IEEE80211_BAND_5GHZ, \
  43         .center_freq = (_freq), \
  44         .hw_value = (_idx), \
  45         .max_power = 30, \
  46 }
  47
  48 /* Some 2 GHz radios are actually tunable on 2312-2732
  49  * on 5 MHz steps, we support the channels which we know
  50  * we have calibration data for all cards though to make
  51  * this static */
  52 static struct ieee80211_channel ath9k_2ghz_chantable[] = {
  53         CHAN2G(2412, 0), /* Channel 1 */
  54         CHAN2G(2417, 1), /* Channel 2 */
  55         CHAN2G(2422, 2), /* Channel 3 */
  56         CHAN2G(2427, 3), /* Channel 4 */
  57         CHAN2G(2432, 4), /* Channel 5 */
  58         CHAN2G(2437, 5), /* Channel 6 */
  59         CHAN2G(2442, 6), /* Channel 7 */
  60         CHAN2G(2447, 7), /* Channel 8 */
  61         CHAN2G(2452, 8), /* Channel 9 */
  62         CHAN2G(2457, 9), /* Channel 10 */
  63         CHAN2G(2462, 10), /* Channel 11 */
  64         CHAN2G(2467, 11), /* Channel 12 */
  65         CHAN2G(2472, 12), /* Channel 13 */
  66         CHAN2G(2484, 13), /* Channel 14 */
  67 };
  68
  69 /* Some 5 GHz radios are actually tunable on XXXX-YYYY
  70  * on 5 MHz steps, we support the channels which we know
  71  * we have calibration data for all cards though to make
  72  * this static */
  73 static struct ieee80211_channel ath9k_5ghz_chantable[] = {
  74         /* _We_ call this UNII 1 */
  75         CHAN5G(5180, 14), /* Channel 36 */
  76         CHAN5G(5200, 15), /* Channel 40 */
  77         CHAN5G(5220, 16), /* Channel 44 */
  78         CHAN5G(5240, 17), /* Channel 48 */
  79         /* _We_ call this UNII 2 */
  80         CHAN5G(5260, 18), /* Channel 52 */
  81         CHAN5G(5280, 19), /* Channel 56 */
  82         CHAN5G(5300, 20), /* Channel 60 */
  83         CHAN5G(5320, 21), /* Channel 64 */
  84         /* _We_ call this "Middle band" */
  85         CHAN5G(5500, 22), /* Channel 100 */
  86         CHAN5G(5520, 23), /* Channel 104 */
  87         CHAN5G(5540, 24), /* Channel 108 */
  88         CHAN5G(5560, 25), /* Channel 112 */
  89         CHAN5G(5580, 26), /* Channel 116 */
  90         CHAN5G(5600, 27), /* Channel 120 */
  91         CHAN5G(5620, 28), /* Channel 124 */
  92         CHAN5G(5640, 29), /* Channel 128 */
  93         CHAN5G(5660, 30), /* Channel 132 */
  94         CHAN5G(5680, 31), /* Channel 136 */
  95         CHAN5G(5700, 32), /* Channel 140 */
  96         /* _We_ call this UNII 3 */
  97         CHAN5G(5745, 33), /* Channel 149 */
  98         CHAN5G(5765, 34), /* Channel 153 */
  99         CHAN5G(5785, 35), /* Channel 157 */
 100         CHAN5G(5805, 36), /* Channel 161 */
 101         CHAN5G(5825, 37), /* Channel 165 */
 102 };
 103
 104 static void ath_cache_conf_rate(struct ath_softc *sc,
 105                                 struct ieee80211_conf *conf)
 106 {
 107         switch (conf->channel->band) {
 108         case IEEE80211_BAND_2GHZ:
 109                 if (conf_is_ht20(conf))
 110                         sc->cur_rate_table =
 111                           sc->hw_rate_table[ATH9K_MODE_11NG_HT20];
 112                 else if (conf_is_ht40_minus(conf))
 113                         sc->cur_rate_table =
 114                           sc->hw_rate_table[ATH9K_MODE_11NG_HT40MINUS];
 115                 else if (conf_is_ht40_plus(conf))
 116                         sc->cur_rate_table =
 117                           sc->hw_rate_table[ATH9K_MODE_11NG_HT40PLUS];
 118                 else
 119                         sc->cur_rate_table =
 120                           sc->hw_rate_table[ATH9K_MODE_11G];
 121                 break;
 122         case IEEE80211_BAND_5GHZ:
 123                 if (conf_is_ht20(conf))
 124                         sc->cur_rate_table =
 125                           sc->hw_rate_table[ATH9K_MODE_11NA_HT20];
 126                 else if (conf_is_ht40_minus(conf))
 127                         sc->cur_rate_table =
 128                           sc->hw_rate_table[ATH9K_MODE_11NA_HT40MINUS];
 129                 else if (conf_is_ht40_plus(conf))
 130                         sc->cur_rate_table =
 131                           sc->hw_rate_table[ATH9K_MODE_11NA_HT40PLUS];
 132                 else
 133                         sc->cur_rate_table =
 134                           sc->hw_rate_table[ATH9K_MODE_11A];
 135                 break;
 136         default:
 137                 BUG_ON(1);
 138                 break;
 139         }
 140 }
 141
 142 static void ath_update_txpow(struct ath_softc *sc)
 143 {
 144         struct ath_hw *ah = sc->sc_ah;
 145         u32 txpow;
 146
 147         if (sc->curtxpow != sc->config.txpowlimit) {
 148                 ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit);
 149                 /* read back in case value is clamped */
 150                 ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
 151                 sc->curtxpow = txpow;
 152         }
 153 }
 154
 155 static u8 parse_mpdudensity(u8 mpdudensity)
 156 {
 157         /*
 158          * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
 159          *   0 for no restriction
 160          *   1 for 1/4 us
 161          *   2 for 1/2 us
 162          *   3 for 1 us
 163          *   4 for 2 us
 164          *   5 for 4 us
 165          *   6 for 8 us
 166          *   7 for 16 us
 167          */
 168         switch (mpdudensity) {
 169         case 0:
 170                 return 0;
 171         case 1:
 172         case 2:
 173         case 3:
 174                 /* Our lower layer calculations limit our precision to
 175                    1 microsecond */
 176                 return 1;
 177         case 4:
 178                 return 2;
 179         case 5:
 180                 return 4;
 181         case 6:
 182                 return 8;
 183         case 7:
 184                 return 16;
 185         default:
 186                 return 0;
 187         }
 188 }
 189
 190 static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band)
 191 {
 192         struct ath_rate_table *rate_table = NULL;
 193         struct ieee80211_supported_band *sband;
 194         struct ieee80211_rate *rate;
 195         int i, maxrates;
 196
 197         switch (band) {
 198         case IEEE80211_BAND_2GHZ:
 199                 rate_table = sc->hw_rate_table[ATH9K_MODE_11G];
 200                 break;
 201         case IEEE80211_BAND_5GHZ:
 202                 rate_table = sc->hw_rate_table[ATH9K_MODE_11A];
 203                 break;
 204         default:
 205                 break;
 206         }
 207
 208         if (rate_table == NULL)
 209                 return;
 210
 211         sband = &sc->sbands[band];
 212         rate = sc->rates[band];
 213
 214         if (rate_table->rate_cnt > ATH_RATE_MAX)
 215                 maxrates = ATH_RATE_MAX;
 216         else
 217                 maxrates = rate_table->rate_cnt;
 218
 219         for (i = 0; i < maxrates; i++) {
 220                 rate[i].bitrate = rate_table->info[i].ratekbps / 100;
 221                 rate[i].hw_value = rate_table->info[i].ratecode;
 222                 if (rate_table->info[i].short_preamble) {
 223                         rate[i].hw_value_short = rate_table->info[i].ratecode |
 224                                 rate_table->info[i].short_preamble;
 225                         rate[i].flags = IEEE80211_RATE_SHORT_PREAMBLE;
 226                 }
 227                 sband->n_bitrates++;
 228
 229                 DPRINTF(sc, ATH_DBG_CONFIG, "Rate: %2dMbps, ratecode: %2d\n",
 230                         rate[i].bitrate / 10, rate[i].hw_value);
 231         }
 232 }
 233
 234 /*
 235  * Set/change channels.  If the channel is really being changed, it's done
 236  * by reseting the chip.  To accomplish this we must first cleanup any pending
 237  * DMA, then restart stuff.
 238 */
 239 static int ath_set_channel(struct ath_softc *sc, struct ath9k_channel *hchan)
 240 {
 241         struct ath_hw *ah = sc->sc_ah;
 242         bool fastcc = true, stopped;
 243         struct ieee80211_hw *hw = sc->hw;
 244         struct ieee80211_channel *channel = hw->conf.channel;
 245         int r;
 246
 247         if (sc->sc_flags & SC_OP_INVALID)
 248                 return -EIO;
 249
 250         ath9k_ps_wakeup(sc);
 251
 252         /*
 253          * This is only performed if the channel settings have
 254          * actually changed.
 255          *
 256          * To switch channels clear any pending DMA operations;
 257          * wait long enough for the RX fifo to drain, reset the
 258          * hardware at the new frequency, and then re-enable
 259          * the relevant bits of the h/w.
 260          */
 261         ath9k_hw_set_interrupts(ah, 0);
 262         ath_drain_all_txq(sc, false);
 263         stopped = ath_stoprecv(sc);
 264
 265         /* XXX: do not flush receive queue here. We don't want
 266          * to flush data frames already in queue because of
 267          * changing channel. */
 268
 269         if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
 270                 fastcc = false;
 271
 272         DPRINTF(sc, ATH_DBG_CONFIG,
 273                 "(%u MHz) -> (%u MHz), chanwidth: %d\n",
 274                 sc->sc_ah->curchan->channel,
 275                 channel->center_freq, sc->tx_chan_width);
 276
 277         spin_lock_bh(&sc->sc_resetlock);
 278
 279         r = ath9k_hw_reset(ah, hchan, fastcc);
 280         if (r) {
 281                 DPRINTF(sc, ATH_DBG_FATAL,
 282                         "Unable to reset channel (%u Mhz) "
 283                         "reset status %u\n",
 284                         channel->center_freq, r);
 285                 spin_unlock_bh(&sc->sc_resetlock);
 286                 return r;
 287         }
 288         spin_unlock_bh(&sc->sc_resetlock);
 289
 290         sc->sc_flags &= ~SC_OP_CHAINMASK_UPDATE;
 291         sc->sc_flags &= ~SC_OP_FULL_RESET;
 292
 293         if (ath_startrecv(sc) != 0) {
 294                 DPRINTF(sc, ATH_DBG_FATAL,
 295                         "Unable to restart recv logic\n");
 296                 return -EIO;
 297         }
 298
 299         ath_cache_conf_rate(sc, &hw->conf);
 300         ath_update_txpow(sc);
 301         ath9k_hw_set_interrupts(ah, sc->imask);
 302         ath9k_ps_restore(sc);
 303         return 0;
 304 }
 305
 306 /*
 307  *  This routine performs the periodic noise floor calibration function
 308  *  that is used to adjust and optimize the chip performance.  This
 309  *  takes environmental changes (location, temperature) into account.
 310  *  When the task is complete, it reschedules itself depending on the
 311  *  appropriate interval that was calculated.
 312  */
 313 static void ath_ani_calibrate(unsigned long data)
 314 {
 315         struct ath_softc *sc = (struct ath_softc *)data;
 316         struct ath_hw *ah = sc->sc_ah;
 317         bool longcal = false;
 318         bool shortcal = false;
 319         bool aniflag = false;
 320         unsigned int timestamp = jiffies_to_msecs(jiffies);
 321         u32 cal_interval, short_cal_interval;
 322
 323         short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
 324                 ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
 325
 326         /*
 327         * don't calibrate when we're scanning.
 328         * we are most likely not on our home channel.
 329         */
 330         if (sc->sc_flags & SC_OP_SCANNING)
 331                 goto set_timer;
 332
 333         /* Long calibration runs independently of short calibration. */
 334         if ((timestamp - sc->ani.longcal_timer) >= ATH_LONG_CALINTERVAL) {
 335                 longcal = true;
 336                 DPRINTF(sc, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
 337                 sc->ani.longcal_timer = timestamp;
 338         }
 339
 340         /* Short calibration applies only while caldone is false */
 341         if (!sc->ani.caldone) {
 342                 if ((timestamp - sc->ani.shortcal_timer) >= short_cal_interval) {
 343                         shortcal = true;
 344                         DPRINTF(sc, ATH_DBG_ANI, "shortcal @%lu\n", jiffies);
 345                         sc->ani.shortcal_timer = timestamp;
 346                         sc->ani.resetcal_timer = timestamp;
 347                 }
 348         } else {
 349                 if ((timestamp - sc->ani.resetcal_timer) >=
 350                     ATH_RESTART_CALINTERVAL) {
 351                         sc->ani.caldone = ath9k_hw_reset_calvalid(ah);
 352                         if (sc->ani.caldone)
 353                                 sc->ani.resetcal_timer = timestamp;
 354                 }
 355         }
 356
 357         /* Verify whether we must check ANI */
 358         if ((timestamp - sc->ani.checkani_timer) >= ATH_ANI_POLLINTERVAL) {
 359                 aniflag = true;
 360                 sc->ani.checkani_timer = timestamp;
 361         }
 362
 363         /* Skip all processing if there's nothing to do. */
 364         if (longcal || shortcal || aniflag) {
 365                 /* Call ANI routine if necessary */
 366                 if (aniflag)
 367                         ath9k_hw_ani_monitor(ah, &sc->nodestats, ah->curchan);
 368
 369                 /* Perform calibration if necessary */
 370                 if (longcal || shortcal) {
 371                         bool iscaldone = false;
 372
 373                         if (ath9k_hw_calibrate(ah, ah->curchan,
 374                                                sc->rx_chainmask, longcal,
 375                                                &iscaldone)) {
 376                                 if (longcal)
 377                                         sc->ani.noise_floor =
 378                                                 ath9k_hw_getchan_noise(ah,
 379                                                                ah->curchan);
 380
 381                                 DPRINTF(sc, ATH_DBG_ANI,
 382                                         "calibrate chan %u/%x nf: %d\n",
 383                                         ah->curchan->channel,
 384                                         ah->curchan->channelFlags,
 385                                         sc->ani.noise_floor);
 386                         } else {
 387                                 DPRINTF(sc, ATH_DBG_ANY,
 388                                         "calibrate chan %u/%x failed\n",
 389                                         ah->curchan->channel,
 390                                         ah->curchan->channelFlags);
 391                         }
 392                         sc->ani.caldone = iscaldone;
 393                 }
 394         }
 395
 396 set_timer:
 397         /*
 398         * Set timer interval based on previous results.
 399         * The interval must be the shortest necessary to satisfy ANI,
 400         * short calibration and long calibration.
 401         */
 402         cal_interval = ATH_LONG_CALINTERVAL;
 403         if (sc->sc_ah->config.enable_ani)
 404                 cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL);
 405         if (!sc->ani.caldone)
 406                 cal_interval = min(cal_interval, (u32)short_cal_interval);
 407
 408         mod_timer(&sc->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
 409 }
 410
 411 /*
 412  * Update tx/rx chainmask. For legacy association,
 413  * hard code chainmask to 1x1, for 11n association, use
 414  * the chainmask configuration, for bt coexistence, use
 415  * the chainmask configuration even in legacy mode.
 416  */
 417 static void ath_update_chainmask(struct ath_softc *sc, int is_ht)
 418 {
 419         sc->sc_flags |= SC_OP_CHAINMASK_UPDATE;
 420         if (is_ht ||
 421             (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BT_COEX)) {
 422                 sc->tx_chainmask = sc->sc_ah->caps.tx_chainmask;
 423                 sc->rx_chainmask = sc->sc_ah->caps.rx_chainmask;
 424         } else {
 425                 sc->tx_chainmask = 1;
 426                 sc->rx_chainmask = 1;
 427         }
 428
 429         DPRINTF(sc, ATH_DBG_CONFIG, "tx chmask: %d, rx chmask: %d\n",
 430                 sc->tx_chainmask, sc->rx_chainmask);
 431 }
 432
 433 static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
 434 {
 435         struct ath_node *an;
 436
 437         an = (struct ath_node *)sta->drv_priv;
 438
 439         if (sc->sc_flags & SC_OP_TXAGGR)
 440                 ath_tx_node_init(sc, an);
 441
 442         an->maxampdu = 1 << (IEEE80211_HTCAP_MAXRXAMPDU_FACTOR +
 443                              sta->ht_cap.ampdu_factor);
 444         an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
 445 }
 446
 447 static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
 448 {
 449         struct ath_node *an = (struct ath_node *)sta->drv_priv;
 450
 451         if (sc->sc_flags & SC_OP_TXAGGR)
 452                 ath_tx_node_cleanup(sc, an);
 453 }
 454
 455 static void ath9k_tasklet(unsigned long data)
 456 {
 457         struct ath_softc *sc = (struct ath_softc *)data;
 458         u32 status = sc->intrstatus;
 459
 460         if (status & ATH9K_INT_FATAL) {
 461                 /* need a chip reset */
 462                 ath_reset(sc, false);
 463                 return;
 464         } else {
 465
 466                 if (status &
 467                     (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
 468                         spin_lock_bh(&sc->rx.rxflushlock);
 469                         ath_rx_tasklet(sc, 0);
 470                         spin_unlock_bh(&sc->rx.rxflushlock);
 471                 }
 472                 /* XXX: optimize this */
 473                 if (status & ATH9K_INT_TX)
 474                         ath_tx_tasklet(sc);
 475         }
 476
 477         /* re-enable hardware interrupt */
 478         ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
 479 }
 480
 481 irqreturn_t ath_isr(int irq, void *dev)
 482 {
 483         struct ath_softc *sc = dev;
 484         struct ath_hw *ah = sc->sc_ah;
 485         enum ath9k_int status;
 486         bool sched = false;
 487
 488         do {
 489                 if (sc->sc_flags & SC_OP_INVALID) {
 490                         /*
 491                          * The hardware is not ready/present, don't
 492                          * touch anything. Note this can happen early
 493                          * on if the IRQ is shared.
 494                          */
 495                         return IRQ_NONE;
 496                 }
 497                 if (!ath9k_hw_intrpend(ah)) {   /* shared irq, not for us */
 498                         return IRQ_NONE;
 499                 }
 500
 501                 /*
 502                  * Figure out the reason(s) for the interrupt.  Note
 503                  * that the hal returns a pseudo-ISR that may include
 504                  * bits we haven't explicitly enabled so we mask the
 505                  * value to insure we only process bits we requested.
 506                  */
 507                 ath9k_hw_getisr(ah, &status);   /* NB: clears ISR too */
 508
 509                 status &= sc->imask;    /* discard unasked-for bits */
 510
 511                 /*
 512                  * If there are no status bits set, then this interrupt was not
 513                  * for me (should have been caught above).
 514                  */
 515                 if (!status)
 516                         return IRQ_NONE;
 517
 518                 sc->intrstatus = status;
 519                 ath9k_ps_wakeup(sc);
 520
 521                 if (status & ATH9K_INT_FATAL) {
 522                         /* need a chip reset */
 523                         sched = true;
 524                 } else if (status & ATH9K_INT_RXORN) {
 525                         /* need a chip reset */
 526                         sched = true;
 527                 } else {
 528                         if (status & ATH9K_INT_SWBA) {
 529                                 /* schedule a tasklet for beacon handling */
 530                                 tasklet_schedule(&sc->bcon_tasklet);
 531                         }
 532                         if (status & ATH9K_INT_RXEOL) {
 533                                 /*
 534                                  * NB: the hardware should re-read the link when
 535                                  *     RXE bit is written, but it doesn't work
 536                                  *     at least on older hardware revs.
 537                                  */
 538                                 sched = true;
 539                         }
 540
 541                         if (status & ATH9K_INT_TXURN)
 542                                 /* bump tx trigger level */
 543                                 ath9k_hw_updatetxtriglevel(ah, true);
 544                         /* XXX: optimize this */
 545                         if (status & ATH9K_INT_RX)
 546                                 sched = true;
 547                         if (status & ATH9K_INT_TX)
 548                                 sched = true;
 549                         if (status & ATH9K_INT_BMISS)
 550                                 sched = true;
 551                         /* carrier sense timeout */
 552                         if (status & ATH9K_INT_CST)
 553                                 sched = true;
 554                         if (status & ATH9K_INT_MIB) {
 555                                 /*
 556                                  * Disable interrupts until we service the MIB
 557                                  * interrupt; otherwise it will continue to
 558                                  * fire.
 559                                  */
 560                                 ath9k_hw_set_interrupts(ah, 0);
 561                                 /*
 562                                  * Let the hal handle the event. We assume
 563                                  * it will clear whatever condition caused
 564                                  * the interrupt.
 565                                  */
 566                                 ath9k_hw_procmibevent(ah, &sc->nodestats);
 567                                 ath9k_hw_set_interrupts(ah, sc->imask);
 568                         }
 569                         if (status & ATH9K_INT_TIM_TIMER) {
 570                                 if (!(ah->caps.hw_caps &
 571                                       ATH9K_HW_CAP_AUTOSLEEP)) {
 572                                         /* Clear RxAbort bit so that we can
 573                                          * receive frames */
 574                                         ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
 575                                         ath9k_hw_setrxabort(ah, 0);
 576                                         sched = true;
 577                                         sc->sc_flags |= SC_OP_WAIT_FOR_BEACON;
 578                                 }
 579                         }
 580                         if (status & ATH9K_INT_TSFOOR) {
 581                                 /* FIXME: Handle this interrupt for power save */
 582                                 sched = true;
 583                         }
 584                 }
 585                 ath9k_ps_restore(sc);
 586         } while (0);
 587
 588         ath_debug_stat_interrupt(sc, status);
 589
 590         if (sched) {
 591                 /* turn off every interrupt except SWBA */
 592                 ath9k_hw_set_interrupts(ah, (sc->imask & ATH9K_INT_SWBA));
 593                 tasklet_schedule(&sc->intr_tq);
 594         }
 595
 596         return IRQ_HANDLED;
 597 }
 598
 599 static u32 ath_get_extchanmode(struct ath_softc *sc,
 600                                struct ieee80211_channel *chan,
 601                                enum nl80211_channel_type channel_type)
 602 {
 603         u32 chanmode = 0;
 604
 605         switch (chan->band) {
 606         case IEEE80211_BAND_2GHZ:
 607                 switch(channel_type) {
 608                 case NL80211_CHAN_NO_HT:
 609                 case NL80211_CHAN_HT20:
 610                         chanmode = CHANNEL_G_HT20;
 611                         break;
 612                 case NL80211_CHAN_HT40PLUS:
 613                         chanmode = CHANNEL_G_HT40PLUS;
 614                         break;
 615                 case NL80211_CHAN_HT40MINUS:
 616                         chanmode = CHANNEL_G_HT40MINUS;
 617                         break;
 618                 }
 619                 break;
 620         case IEEE80211_BAND_5GHZ:
 621                 switch(channel_type) {
 622                 case NL80211_CHAN_NO_HT:
 623                 case NL80211_CHAN_HT20:
 624                         chanmode = CHANNEL_A_HT20;
 625                         break;
 626                 case NL80211_CHAN_HT40PLUS:
 627                         chanmode = CHANNEL_A_HT40PLUS;
 628                         break;
 629                 case NL80211_CHAN_HT40MINUS:
 630                         chanmode = CHANNEL_A_HT40MINUS;
 631                         break;
 632                 }
 633                 break;
 634         default:
 635                 break;
 636         }
 637
 638         return chanmode;
 639 }
 640
 641 static int ath_setkey_tkip(struct ath_softc *sc, u16 keyix, const u8 *key,
 642                            struct ath9k_keyval *hk, const u8 *addr,
 643                            bool authenticator)
 644 {
 645         const u8 *key_rxmic;
 646         const u8 *key_txmic;
 647
 648         key_txmic = key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
 649         key_rxmic = key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
 650
 651         if (addr == NULL) {
 652                 /*
 653                  * Group key installation - only two key cache entries are used
 654                  * regardless of splitmic capability since group key is only
 655                  * used either for TX or RX.
 656                  */
 657                 if (authenticator) {
 658                         memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
 659                         memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_mic));
 660                 } else {
 661                         memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
 662                         memcpy(hk->kv_txmic, key_rxmic, sizeof(hk->kv_mic));
 663                 }
 664                 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
 665         }
 666         if (!sc->splitmic) {
 667                 /* TX and RX keys share the same key cache entry. */
 668                 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
 669                 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
 670                 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
 671         }
 672
 673         /* Separate key cache entries for TX and RX */
 674
 675         /* TX key goes at first index, RX key at +32. */
 676         memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
 677         if (!ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, NULL)) {
 678                 /* TX MIC entry failed. No need to proceed further */
 679                 DPRINTF(sc, ATH_DBG_KEYCACHE,
 680                         "Setting TX MIC Key Failed\n");
 681                 return 0;
 682         }
 683
 684         memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
 685         /* XXX delete tx key on failure? */
 686         return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix + 32, hk, addr);
 687 }
 688
 689 static int ath_reserve_key_cache_slot_tkip(struct ath_softc *sc)
 690 {
 691         int i;
 692
 693         for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
 694                 if (test_bit(i, sc->keymap) ||
 695                     test_bit(i + 64, sc->keymap))
 696                         continue; /* At least one part of TKIP key allocated */
 697                 if (sc->splitmic &&
 698                     (test_bit(i + 32, sc->keymap) ||
 699                      test_bit(i + 64 + 32, sc->keymap)))
 700                         continue; /* At least one part of TKIP key allocated */
 701
 702                 /* Found a free slot for a TKIP key */
 703                 return i;
 704         }
 705         return -1;
 706 }
 707
 708 static int ath_reserve_key_cache_slot(struct ath_softc *sc)
 709 {
 710         int i;
 711
 712         /* First, try to find slots that would not be available for TKIP. */
 713         if (sc->splitmic) {
 714                 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 4; i++) {
 715                         if (!test_bit(i, sc->keymap) &&
 716                             (test_bit(i + 32, sc->keymap) ||
 717                              test_bit(i + 64, sc->keymap) ||
 718                              test_bit(i + 64 + 32, sc->keymap)))
 719                                 return i;
 720                         if (!test_bit(i + 32, sc->keymap) &&
 721                             (test_bit(i, sc->keymap) ||
 722                              test_bit(i + 64, sc->keymap) ||
 723                              test_bit(i + 64 + 32, sc->keymap)))
 724                                 return i + 32;
 725                         if (!test_bit(i + 64, sc->keymap) &&
 726                             (test_bit(i , sc->keymap) ||
 727                              test_bit(i + 32, sc->keymap) ||
 728                              test_bit(i + 64 + 32, sc->keymap)))
 729                                 return i + 64;
 730                         if (!test_bit(i + 64 + 32, sc->keymap) &&
 731                             (test_bit(i, sc->keymap) ||
 732                              test_bit(i + 32, sc->keymap) ||
 733                              test_bit(i + 64, sc->keymap)))
 734                                 return i + 64 + 32;
 735                 }
 736         } else {
 737                 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
 738                         if (!test_bit(i, sc->keymap) &&
 739                             test_bit(i + 64, sc->keymap))
 740                                 return i;
 741                         if (test_bit(i, sc->keymap) &&
 742                             !test_bit(i + 64, sc->keymap))
 743                                 return i + 64;
 744                 }
 745         }
 746
 747         /* No partially used TKIP slots, pick any available slot */
 748         for (i = IEEE80211_WEP_NKID; i < sc->keymax; i++) {
 749                 /* Do not allow slots that could be needed for TKIP group keys
 750                  * to be used. This limitation could be removed if we know that
 751                  * TKIP will not be used. */
 752                 if (i >= 64 && i < 64 + IEEE80211_WEP_NKID)
 753                         continue;
 754                 if (sc->splitmic) {
 755                         if (i >= 32 && i < 32 + IEEE80211_WEP_NKID)
 756                                 continue;
 757                         if (i >= 64 + 32 && i < 64 + 32 + IEEE80211_WEP_NKID)
 758                                 continue;
 759                 }
 760
 761                 if (!test_bit(i, sc->keymap))
 762                         return i; /* Found a free slot for a key */
 763         }
 764
 765         /* No free slot found */
 766         return -1;
 767 }
 768
 769 static int ath_key_config(struct ath_softc *sc,
 770                           struct ieee80211_vif *vif,
 771                           struct ieee80211_sta *sta,
 772                           struct ieee80211_key_conf *key)
 773 {
 774         struct ath9k_keyval hk;
 775         const u8 *mac = NULL;
 776         int ret = 0;
 777         int idx;
 778
 779         memset(&hk, 0, sizeof(hk));
 780
 781         switch (key->alg) {
 782         case ALG_WEP:
 783                 hk.kv_type = ATH9K_CIPHER_WEP;
 784                 break;
 785         case ALG_TKIP:
 786                 hk.kv_type = ATH9K_CIPHER_TKIP;
 787                 break;
 788         case ALG_CCMP:
 789                 hk.kv_type = ATH9K_CIPHER_AES_CCM;
 790                 break;
 791         default:
 792                 return -EOPNOTSUPP;
 793         }
 794
 795         hk.kv_len = key->keylen;
 796         memcpy(hk.kv_val, key->key, key->keylen);
 797
 798         if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
 799                 /* For now, use the default keys for broadcast keys. This may
 800                  * need to change with virtual interfaces. */
 801                 idx = key->keyidx;
 802         } else if (key->keyidx) {
 803                 if (WARN_ON(!sta))
 804                         return -EOPNOTSUPP;
 805                 mac = sta->addr;
 806
 807                 if (vif->type != NL80211_IFTYPE_AP) {
 808                         /* Only keyidx 0 should be used with unicast key, but
 809                          * allow this for client mode for now. */
 810                         idx = key->keyidx;
 811                 } else
 812                         return -EIO;
 813         } else {
 814                 if (WARN_ON(!sta))
 815                         return -EOPNOTSUPP;
 816                 mac = sta->addr;
 817
 818                 if (key->alg == ALG_TKIP)
 819                         idx = ath_reserve_key_cache_slot_tkip(sc);
 820                 else
 821                         idx = ath_reserve_key_cache_slot(sc);
 822                 if (idx < 0)
 823                         return -ENOSPC; /* no free key cache entries */
 824         }
 825
 826         if (key->alg == ALG_TKIP)
 827                 ret = ath_setkey_tkip(sc, idx, key->key, &hk, mac,
 828                                       vif->type == NL80211_IFTYPE_AP);
 829         else
 830                 ret = ath9k_hw_set_keycache_entry(sc->sc_ah, idx, &hk, mac);
 831
 832         if (!ret)
 833                 return -EIO;
 834
 835         set_bit(idx, sc->keymap);
 836         if (key->alg == ALG_TKIP) {
 837                 set_bit(idx + 64, sc->keymap);
 838                 if (sc->splitmic) {
 839                         set_bit(idx + 32, sc->keymap);
 840                         set_bit(idx + 64 + 32, sc->keymap);
 841                 }
 842         }
 843
 844         return idx;
 845 }
 846
 847 static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key)
 848 {
 849         ath9k_hw_keyreset(sc->sc_ah, key->hw_key_idx);
 850         if (key->hw_key_idx < IEEE80211_WEP_NKID)
 851                 return;
 852
 853         clear_bit(key->hw_key_idx, sc->keymap);
 854         if (key->alg != ALG_TKIP)
 855                 return;
 856
 857         clear_bit(key->hw_key_idx + 64, sc->keymap);
 858         if (sc->splitmic) {
 859                 clear_bit(key->hw_key_idx + 32, sc->keymap);
 860                 clear_bit(key->hw_key_idx + 64 + 32, sc->keymap);
 861         }
 862 }
 863
 864 static void setup_ht_cap(struct ath_softc *sc,
 865                          struct ieee80211_sta_ht_cap *ht_info)
 866 {
 867 #define ATH9K_HT_CAP_MAXRXAMPDU_65536 0x3       /* 2 ^ 16 */
 868 #define ATH9K_HT_CAP_MPDUDENSITY_8 0x6          /* 8 usec */
 869
 870         ht_info->ht_supported = true;
 871         ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
 872                        IEEE80211_HT_CAP_SM_PS |
 873                        IEEE80211_HT_CAP_SGI_40 |
 874                        IEEE80211_HT_CAP_DSSSCCK40;
 875
 876         ht_info->ampdu_factor = ATH9K_HT_CAP_MAXRXAMPDU_65536;
 877         ht_info->ampdu_density = ATH9K_HT_CAP_MPDUDENSITY_8;
 878
 879         /* set up supported mcs set */
 880         memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
 881
 882         switch(sc->rx_chainmask) {
 883         case 1:
 884                 ht_info->mcs.rx_mask[0] = 0xff;
 885                 break;
 886         case 3:
 887         case 5:
 888         case 7:
 889         default:
 890                 ht_info->mcs.rx_mask[0] = 0xff;
 891                 ht_info->mcs.rx_mask[1] = 0xff;
 892                 break;
 893         }
 894
 895         ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
 896 }
 897
 898 static void ath9k_bss_assoc_info(struct ath_softc *sc,
 899                                  struct ieee80211_vif *vif,
 900                                  struct ieee80211_bss_conf *bss_conf)
 901 {
 902         struct ath_vif *avp = (void *)vif->drv_priv;
 903
 904         if (bss_conf->assoc) {
 905                 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info ASSOC %d, bssid: %pM\n",
 906                         bss_conf->aid, sc->curbssid);
 907
 908                 /* New association, store aid */
 909                 if (avp->av_opmode == NL80211_IFTYPE_STATION) {
 910                         sc->curaid = bss_conf->aid;
 911                         ath9k_hw_write_associd(sc);
 912                 }
 913
 914                 /* Configure the beacon */
 915                 ath_beacon_config(sc, vif);
 916
 917                 /* Reset rssi stats */
 918                 sc->nodestats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
 919                 sc->nodestats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
 920                 sc->nodestats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
 921                 sc->nodestats.ns_avgtxrate = ATH_RATE_DUMMY_MARKER;
 922
 923                 /* Start ANI */
 924                 mod_timer(&sc->ani.timer,
 925                           jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
 926         } else {
 927                 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info DISSOC\n");
 928                 sc->curaid = 0;
 929         }
 930 }
 931
 932 /********************************/
 933 /*       LED functions          */
 934 /********************************/
 935
 936 static void ath_led_blink_work(struct work_struct *work)
 937 {
 938         struct ath_softc *sc = container_of(work, struct ath_softc,
 939                                             ath_led_blink_work.work);
 940
 941         if (!(sc->sc_flags & SC_OP_LED_ASSOCIATED))
 942                 return;
 943         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
 944                           (sc->sc_flags & SC_OP_LED_ON) ? 1 : 0);
 945
 946         queue_delayed_work(sc->hw->workqueue, &sc->ath_led_blink_work,
 947                            (sc->sc_flags & SC_OP_LED_ON) ?
 948                            msecs_to_jiffies(sc->led_off_duration) :
 949                            msecs_to_jiffies(sc->led_on_duration));
 950
 951         sc->led_on_duration =
 952                         max((ATH_LED_ON_DURATION_IDLE - sc->led_on_cnt), 25);
 953         sc->led_off_duration =
 954                         max((ATH_LED_OFF_DURATION_IDLE - sc->led_off_cnt), 10);
 955         sc->led_on_cnt = sc->led_off_cnt = 0;
 956         if (sc->sc_flags & SC_OP_LED_ON)
 957                 sc->sc_flags &= ~SC_OP_LED_ON;
 958         else
 959                 sc->sc_flags |= SC_OP_LED_ON;
 960 }
 961
 962 static void ath_led_brightness(struct led_classdev *led_cdev,
 963                                enum led_brightness brightness)
 964 {
 965         struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
 966         struct ath_softc *sc = led->sc;
 967
 968         switch (brightness) {
 969         case LED_OFF:
 970                 if (led->led_type == ATH_LED_ASSOC ||
 971                     led->led_type == ATH_LED_RADIO) {
 972                         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
 973                                 (led->led_type == ATH_LED_RADIO));
 974                         sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
 975                         if (led->led_type == ATH_LED_RADIO)
 976                                 sc->sc_flags &= ~SC_OP_LED_ON;
 977                 } else {
 978                         sc->led_off_cnt++;
 979                 }
 980                 break;
 981         case LED_FULL:
 982                 if (led->led_type == ATH_LED_ASSOC) {
 983                         sc->sc_flags |= SC_OP_LED_ASSOCIATED;
 984                         queue_delayed_work(sc->hw->workqueue,
 985                                            &sc->ath_led_blink_work, 0);
 986                 } else if (led->led_type == ATH_LED_RADIO) {
 987                         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
 988                         sc->sc_flags |= SC_OP_LED_ON;
 989                 } else {
 990                         sc->led_on_cnt++;
 991                 }
 992                 break;
 993         default:
 994                 break;
 995         }
 996 }
 997
 998 static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
 999                             char *trigger)
1000 {
1001         int ret;
1002
1003         led->sc = sc;
1004         led->led_cdev.name = led->name;
1005         led->led_cdev.default_trigger = trigger;
1006         led->led_cdev.brightness_set = ath_led_brightness;
1007
1008         ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
1009         if (ret)
1010                 DPRINTF(sc, ATH_DBG_FATAL,
1011                         "Failed to register led:%s", led->name);
1012         else
1013                 led->registered = 1;
1014         return ret;
1015 }
1016
1017 static void ath_unregister_led(struct ath_led *led)
1018 {
1019         if (led->registered) {
1020                 led_classdev_unregister(&led->led_cdev);
1021                 led->registered = 0;
1022         }
1023 }
1024
1025 static void ath_deinit_leds(struct ath_softc *sc)
1026 {
1027         cancel_delayed_work_sync(&sc->ath_led_blink_work);
1028         ath_unregister_led(&sc->assoc_led);
1029         sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
1030         ath_unregister_led(&sc->tx_led);
1031         ath_unregister_led(&sc->rx_led);
1032         ath_unregister_led(&sc->radio_led);
1033         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
1034 }
1035
1036 static void ath_init_leds(struct ath_softc *sc)
1037 {
1038         char *trigger;
1039         int ret;
1040
1041         /* Configure gpio 1 for output */
1042         ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
1043                             AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1044         /* LED off, active low */
1045         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
1046
1047         INIT_DELAYED_WORK(&sc->ath_led_blink_work, ath_led_blink_work);
1048
1049         trigger = ieee80211_get_radio_led_name(sc->hw);
1050         snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
1051                 "ath9k-%s::radio", wiphy_name(sc->hw->wiphy));
1052         ret = ath_register_led(sc, &sc->radio_led, trigger);
1053         sc->radio_led.led_type = ATH_LED_RADIO;
1054         if (ret)
1055                 goto fail;
1056
1057         trigger = ieee80211_get_assoc_led_name(sc->hw);
1058         snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
1059                 "ath9k-%s::assoc", wiphy_name(sc->hw->wiphy));
1060         ret = ath_register_led(sc, &sc->assoc_led, trigger);
1061         sc->assoc_led.led_type = ATH_LED_ASSOC;
1062         if (ret)
1063                 goto fail;
1064
1065         trigger = ieee80211_get_tx_led_name(sc->hw);
1066         snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
1067                 "ath9k-%s::tx", wiphy_name(sc->hw->wiphy));
1068         ret = ath_register_led(sc, &sc->tx_led, trigger);
1069         sc->tx_led.led_type = ATH_LED_TX;
1070         if (ret)
1071                 goto fail;
1072
1073         trigger = ieee80211_get_rx_led_name(sc->hw);
1074         snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
1075                 "ath9k-%s::rx", wiphy_name(sc->hw->wiphy));
1076         ret = ath_register_led(sc, &sc->rx_led, trigger);
1077         sc->rx_led.led_type = ATH_LED_RX;
1078         if (ret)
1079                 goto fail;
1080
1081         return;
1082
1083 fail:
1084         ath_deinit_leds(sc);
1085 }
1086
1087 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1088
1089 /*******************/
1090 /*      Rfkill     */
1091 /*******************/
1092
1093 static void ath_radio_enable(struct ath_softc *sc)
1094 {
1095         struct ath_hw *ah = sc->sc_ah;
1096         struct ieee80211_channel *channel = sc->hw->conf.channel;
1097         int r;
1098
1099         ath9k_ps_wakeup(sc);
1100         spin_lock_bh(&sc->sc_resetlock);
1101
1102         r = ath9k_hw_reset(ah, ah->curchan, false);
1103
1104         if (r) {
1105                 DPRINTF(sc, ATH_DBG_FATAL,
1106                         "Unable to reset channel %u (%uMhz) ",
1107                         "reset status %u\n",
1108                         channel->center_freq, r);
1109         }
1110         spin_unlock_bh(&sc->sc_resetlock);
1111
1112         ath_update_txpow(sc);
1113         if (ath_startrecv(sc) != 0) {
1114                 DPRINTF(sc, ATH_DBG_FATAL,
1115                         "Unable to restart recv logic\n");
1116                 return;
1117         }
1118
1119         if (sc->sc_flags & SC_OP_BEACONS)
1120                 ath_beacon_config(sc, NULL);    /* restart beacons */
1121
1122         /* Re-Enable  interrupts */
1123         ath9k_hw_set_interrupts(ah, sc->imask);
1124
1125         /* Enable LED */
1126         ath9k_hw_cfg_output(ah, ATH_LED_PIN,
1127                             AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1128         ath9k_hw_set_gpio(ah, ATH_LED_PIN, 0);
1129
1130         ieee80211_wake_queues(sc->hw);
1131         ath9k_ps_restore(sc);
1132 }
1133
1134 static void ath_radio_disable(struct ath_softc *sc)
1135 {
1136         struct ath_hw *ah = sc->sc_ah;
1137         struct ieee80211_channel *channel = sc->hw->conf.channel;
1138         int r;
1139
1140         ath9k_ps_wakeup(sc);
1141         ieee80211_stop_queues(sc->hw);
1142
1143         /* Disable LED */
1144         ath9k_hw_set_gpio(ah, ATH_LED_PIN, 1);
1145         ath9k_hw_cfg_gpio_input(ah, ATH_LED_PIN);
1146
1147         /* Disable interrupts */
1148         ath9k_hw_set_interrupts(ah, 0);
1149
1150         ath_drain_all_txq(sc, false);   /* clear pending tx frames */
1151         ath_stoprecv(sc);               /* turn off frame recv */
1152         ath_flushrecv(sc);              /* flush recv queue */
1153
1154         spin_lock_bh(&sc->sc_resetlock);
1155         r = ath9k_hw_reset(ah, ah->curchan, false);
1156         if (r) {
1157                 DPRINTF(sc, ATH_DBG_FATAL,
1158                         "Unable to reset channel %u (%uMhz) "
1159                         "reset status %u\n",
1160                         channel->center_freq, r);
1161         }
1162         spin_unlock_bh(&sc->sc_resetlock);
1163
1164         ath9k_hw_phy_disable(ah);
1165         ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1166         ath9k_ps_restore(sc);
1167 }
1168
1169 static bool ath_is_rfkill_set(struct ath_softc *sc)
1170 {
1171         struct ath_hw *ah = sc->sc_ah;
1172
1173         return ath9k_hw_gpio_get(ah, ah->rfkill_gpio) ==
1174                                   ah->rfkill_polarity;
1175 }
1176
1177 /* h/w rfkill poll function */
1178 static void ath_rfkill_poll(struct work_struct *work)
1179 {
1180         struct ath_softc *sc = container_of(work, struct ath_softc,
1181                                             rf_kill.rfkill_poll.work);
1182         bool radio_on;
1183
1184         if (sc->sc_flags & SC_OP_INVALID)
1185                 return;
1186
1187         radio_on = !ath_is_rfkill_set(sc);
1188
1189         /*
1190          * enable/disable radio only when there is a
1191          * state change in RF switch
1192          */
1193         if (radio_on == !!(sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED)) {
1194                 enum rfkill_state state;
1195
1196                 if (sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED) {
1197                         state = radio_on ? RFKILL_STATE_SOFT_BLOCKED
1198                                 : RFKILL_STATE_HARD_BLOCKED;
1199                 } else if (radio_on) {
1200                         ath_radio_enable(sc);
1201                         state = RFKILL_STATE_UNBLOCKED;
1202                 } else {
1203                         ath_radio_disable(sc);
1204                         state = RFKILL_STATE_HARD_BLOCKED;
1205                 }
1206
1207                 if (state == RFKILL_STATE_HARD_BLOCKED)
1208                         sc->sc_flags |= SC_OP_RFKILL_HW_BLOCKED;
1209                 else
1210                         sc->sc_flags &= ~SC_OP_RFKILL_HW_BLOCKED;
1211
1212                 rfkill_force_state(sc->rf_kill.rfkill, state);
1213         }
1214
1215         queue_delayed_work(sc->hw->workqueue, &sc->rf_kill.rfkill_poll,
1216                            msecs_to_jiffies(ATH_RFKILL_POLL_INTERVAL));
1217 }
1218
1219 /* s/w rfkill handler */
1220 static int ath_sw_toggle_radio(void *data, enum rfkill_state state)
1221 {
1222         struct ath_softc *sc = data;
1223
1224         switch (state) {
1225         case RFKILL_STATE_SOFT_BLOCKED:
1226                 if (!(sc->sc_flags & (SC_OP_RFKILL_HW_BLOCKED |
1227                     SC_OP_RFKILL_SW_BLOCKED)))
1228                         ath_radio_disable(sc);
1229                 sc->sc_flags |= SC_OP_RFKILL_SW_BLOCKED;
1230                 return 0;
1231         case RFKILL_STATE_UNBLOCKED:
1232                 if ((sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED)) {
1233                         sc->sc_flags &= ~SC_OP_RFKILL_SW_BLOCKED;
1234                         if (sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED) {
1235                                 DPRINTF(sc, ATH_DBG_FATAL, "Can't turn on the"
1236                                         "radio as it is disabled by h/w\n");
1237                                 return -EPERM;
1238                         }
1239                         ath_radio_enable(sc);
1240                 }
1241                 return 0;
1242         default:
1243                 return -EINVAL;
1244         }
1245 }
1246
1247 /* Init s/w rfkill */
1248 static int ath_init_sw_rfkill(struct ath_softc *sc)
1249 {
1250         sc->rf_kill.rfkill = rfkill_allocate(wiphy_dev(sc->hw->wiphy),
1251                                              RFKILL_TYPE_WLAN);
1252         if (!sc->rf_kill.rfkill) {
1253                 DPRINTF(sc, ATH_DBG_FATAL, "Failed to allocate rfkill\n");
1254                 return -ENOMEM;
1255         }
1256
1257         snprintf(sc->rf_kill.rfkill_name, sizeof(sc->rf_kill.rfkill_name),
1258                 "ath9k-%s::rfkill", wiphy_name(sc->hw->wiphy));
1259         sc->rf_kill.rfkill->name = sc->rf_kill.rfkill_name;
1260         sc->rf_kill.rfkill->data = sc;
1261         sc->rf_kill.rfkill->toggle_radio = ath_sw_toggle_radio;
1262         sc->rf_kill.rfkill->state = RFKILL_STATE_UNBLOCKED;
1263         sc->rf_kill.rfkill->user_claim_unsupported = 1;
1264
1265         return 0;
1266 }
1267
1268 /* Deinitialize rfkill */
1269 static void ath_deinit_rfkill(struct ath_softc *sc)
1270 {
1271         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1272                 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
1273
1274         if (sc->sc_flags & SC_OP_RFKILL_REGISTERED) {
1275                 rfkill_unregister(sc->rf_kill.rfkill);
1276                 sc->sc_flags &= ~SC_OP_RFKILL_REGISTERED;
1277                 sc->rf_kill.rfkill = NULL;
1278         }
1279 }
1280
1281 static int ath_start_rfkill_poll(struct ath_softc *sc)
1282 {
1283         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1284                 queue_delayed_work(sc->hw->workqueue,
1285                                    &sc->rf_kill.rfkill_poll, 0);
1286
1287         if (!(sc->sc_flags & SC_OP_RFKILL_REGISTERED)) {
1288                 if (rfkill_register(sc->rf_kill.rfkill)) {
1289                         DPRINTF(sc, ATH_DBG_FATAL,
1290                                 "Unable to register rfkill\n");
1291                         rfkill_free(sc->rf_kill.rfkill);
1292
1293                         /* Deinitialize the device */
1294                         ath_cleanup(sc);
1295                         return -EIO;
1296                 } else {
1297                         sc->sc_flags |= SC_OP_RFKILL_REGISTERED;
1298                 }
1299         }
1300
1301         return 0;
1302 }
1303 #endif /* CONFIG_RFKILL */
1304
1305 void ath_cleanup(struct ath_softc *sc)
1306 {
1307         ath_detach(sc);
1308         free_irq(sc->irq, sc);
1309         ath_bus_cleanup(sc);
1310         ieee80211_free_hw(sc->hw);
1311 }
1312
1313 void ath_detach(struct ath_softc *sc)
1314 {
1315         struct ieee80211_hw *hw = sc->hw;
1316         int i = 0;
1317
1318         ath9k_ps_wakeup(sc);
1319
1320         DPRINTF(sc, ATH_DBG_CONFIG, "Detach ATH hw\n");
1321
1322 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1323         ath_deinit_rfkill(sc);
1324 #endif
1325         ath_deinit_leds(sc);
1326
1327         ieee80211_unregister_hw(hw);
1328         ath_rx_cleanup(sc);
1329         ath_tx_cleanup(sc);
1330
1331         tasklet_kill(&sc->intr_tq);
1332         tasklet_kill(&sc->bcon_tasklet);
1333
1334         if (!(sc->sc_flags & SC_OP_INVALID))
1335                 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
1336
1337         /* cleanup tx queues */
1338         for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1339                 if (ATH_TXQ_SETUP(sc, i))
1340                         ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1341
1342         ath9k_hw_detach(sc->sc_ah);
1343         ath9k_exit_debug(sc);
1344         ath9k_ps_restore(sc);
1345 }
1346
1347 static int ath_init(u16 devid, struct ath_softc *sc)
1348 {
1349         struct ath_hw *ah = NULL;
1350         int status;
1351         int error = 0, i;
1352         int csz = 0;
1353
1354         /* XXX: hardware will not be ready until ath_open() being called */
1355         sc->sc_flags |= SC_OP_INVALID;
1356
1357         if (ath9k_init_debug(sc) < 0)
1358                 printk(KERN_ERR "Unable to create debugfs files\n");
1359
1360         spin_lock_init(&sc->sc_resetlock);
1361         mutex_init(&sc->mutex);
1362         tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
1363         tasklet_init(&sc->bcon_tasklet, ath_beacon_tasklet,
1364                      (unsigned long)sc);
1365
1366         /*
1367          * Cache line size is used to size and align various
1368          * structures used to communicate with the hardware.
1369          */
1370         ath_read_cachesize(sc, &csz);
1371         /* XXX assert csz is non-zero */
1372         sc->cachelsz = csz << 2;        /* convert to bytes */
1373
1374         ah = ath9k_hw_attach(devid, sc, &status);
1375         if (ah == NULL) {
1376                 DPRINTF(sc, ATH_DBG_FATAL,
1377                         "Unable to attach hardware; HAL status %d\n", status);
1378                 error = -ENXIO;
1379                 goto bad;
1380         }
1381         sc->sc_ah = ah;
1382
1383         /* Get the hardware key cache size. */
1384         sc->keymax = ah->caps.keycache_size;
1385         if (sc->keymax > ATH_KEYMAX) {
1386                 DPRINTF(sc, ATH_DBG_KEYCACHE,
1387                         "Warning, using only %u entries in %u key cache\n",
1388                         ATH_KEYMAX, sc->keymax);
1389                 sc->keymax = ATH_KEYMAX;
1390         }
1391
1392         /*
1393          * Reset the key cache since some parts do not
1394          * reset the contents on initial power up.
1395          */
1396         for (i = 0; i < sc->keymax; i++)
1397                 ath9k_hw_keyreset(ah, (u16) i);
1398
1399         if (ath9k_regd_init(sc->sc_ah))
1400                 goto bad;
1401
1402         /* default to MONITOR mode */
1403         sc->sc_ah->opmode = NL80211_IFTYPE_MONITOR;
1404
1405         /* Setup rate tables */
1406
1407         ath_rate_attach(sc);
1408         ath_setup_rates(sc, IEEE80211_BAND_2GHZ);
1409         ath_setup_rates(sc, IEEE80211_BAND_5GHZ);
1410
1411         /*
1412          * Allocate hardware transmit queues: one queue for
1413          * beacon frames and one data queue for each QoS
1414          * priority.  Note that the hal handles reseting
1415          * these queues at the needed time.
1416          */
1417         sc->beacon.beaconq = ath_beaconq_setup(ah);
1418         if (sc->beacon.beaconq == -1) {
1419                 DPRINTF(sc, ATH_DBG_FATAL,
1420                         "Unable to setup a beacon xmit queue\n");
1421                 error = -EIO;
1422                 goto bad2;
1423         }
1424         sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
1425         if (sc->beacon.cabq == NULL) {
1426                 DPRINTF(sc, ATH_DBG_FATAL,
1427                         "Unable to setup CAB xmit queue\n");
1428                 error = -EIO;
1429                 goto bad2;
1430         }
1431
1432         sc->config.cabqReadytime = ATH_CABQ_READY_TIME;
1433         ath_cabq_update(sc);
1434
1435         for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++)
1436                 sc->tx.hwq_map[i] = -1;
1437
1438         /* Setup data queues */
1439         /* NB: ensure BK queue is the lowest priority h/w queue */
1440         if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
1441                 DPRINTF(sc, ATH_DBG_FATAL,
1442                         "Unable to setup xmit queue for BK traffic\n");
1443                 error = -EIO;
1444                 goto bad2;
1445         }
1446
1447         if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
1448                 DPRINTF(sc, ATH_DBG_FATAL,
1449                         "Unable to setup xmit queue for BE traffic\n");
1450                 error = -EIO;
1451                 goto bad2;
1452         }
1453         if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
1454                 DPRINTF(sc, ATH_DBG_FATAL,
1455                         "Unable to setup xmit queue for VI traffic\n");
1456                 error = -EIO;
1457                 goto bad2;
1458         }
1459         if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
1460                 DPRINTF(sc, ATH_DBG_FATAL,
1461                         "Unable to setup xmit queue for VO traffic\n");
1462                 error = -EIO;
1463                 goto bad2;
1464         }
1465
1466         /* Initializes the noise floor to a reasonable default value.
1467          * Later on this will be updated during ANI processing. */
1468
1469         sc->ani.noise_floor = ATH_DEFAULT_NOISE_FLOOR;
1470         setup_timer(&sc->ani.timer, ath_ani_calibrate, (unsigned long)sc);
1471
1472         if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1473                                    ATH9K_CIPHER_TKIP, NULL)) {
1474                 /*
1475                  * Whether we should enable h/w TKIP MIC.
1476                  * XXX: if we don't support WME TKIP MIC, then we wouldn't
1477                  * report WMM capable, so it's always safe to turn on
1478                  * TKIP MIC in this case.
1479                  */
1480                 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC,
1481                                        0, 1, NULL);
1482         }
1483
1484         /*
1485          * Check whether the separate key cache entries
1486          * are required to handle both tx+rx MIC keys.
1487          * With split mic keys the number of stations is limited
1488          * to 27 otherwise 59.
1489          */
1490         if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1491                                    ATH9K_CIPHER_TKIP, NULL)
1492             && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1493                                       ATH9K_CIPHER_MIC, NULL)
1494             && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT,
1495                                       0, NULL))
1496                 sc->splitmic = 1;
1497
1498         /* turn on mcast key search if possible */
1499         if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
1500                 (void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1,
1501                                              1, NULL);
1502
1503         sc->config.txpowlimit = ATH_TXPOWER_MAX;
1504
1505         /* 11n Capabilities */
1506         if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
1507                 sc->sc_flags |= SC_OP_TXAGGR;
1508                 sc->sc_flags |= SC_OP_RXAGGR;
1509         }
1510
1511         sc->tx_chainmask = ah->caps.tx_chainmask;
1512         sc->rx_chainmask = ah->caps.rx_chainmask;
1513
1514         ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
1515         sc->rx.defant = ath9k_hw_getdefantenna(ah);
1516
1517         if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
1518                 memcpy(sc->bssidmask, ath_bcast_mac, ETH_ALEN);
1519
1520         sc->beacon.slottime = ATH9K_SLOT_TIME_9;        /* default to short slot time */
1521
1522         /* initialize beacon slots */
1523         for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++)
1524                 sc->beacon.bslot[i] = NULL;
1525
1526         /* save MISC configurations */
1527         sc->config.swBeaconProcess = 1;
1528
1529         /* setup channels and rates */
1530
1531         sc->sbands[IEEE80211_BAND_2GHZ].channels = ath9k_2ghz_chantable;
1532         sc->sbands[IEEE80211_BAND_2GHZ].bitrates =
1533                 sc->rates[IEEE80211_BAND_2GHZ];
1534         sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
1535         sc->sbands[IEEE80211_BAND_2GHZ].n_channels =
1536                 ARRAY_SIZE(ath9k_2ghz_chantable);
1537
1538         if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes)) {
1539                 sc->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_chantable;
1540                 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
1541                         sc->rates[IEEE80211_BAND_5GHZ];
1542                 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
1543                 sc->sbands[IEEE80211_BAND_5GHZ].n_channels =
1544                         ARRAY_SIZE(ath9k_5ghz_chantable);
1545         }
1546
1547         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BT_COEX)
1548                 ath9k_hw_btcoex_enable(sc->sc_ah);
1549
1550         return 0;
1551 bad2:
1552         /* cleanup tx queues */
1553         for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1554                 if (ATH_TXQ_SETUP(sc, i))
1555                         ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1556 bad:
1557         if (ah)
1558                 ath9k_hw_detach(ah);
1559         ath9k_exit_debug(sc);
1560
1561         return error;
1562 }
1563
1564 int ath_attach(u16 devid, struct ath_softc *sc)
1565 {
1566         struct ieee80211_hw *hw = sc->hw;
1567         const struct ieee80211_regdomain *regd;
1568         int error = 0, i;
1569
1570         DPRINTF(sc, ATH_DBG_CONFIG, "Attach ATH hw\n");
1571
1572         error = ath_init(devid, sc);
1573         if (error != 0)
1574                 return error;
1575
1576         /* get mac address from hardware and set in mac80211 */
1577
1578         SET_IEEE80211_PERM_ADDR(hw, sc->sc_ah->macaddr);
1579
1580         hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
1581                 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1582                 IEEE80211_HW_SIGNAL_DBM |
1583                 IEEE80211_HW_AMPDU_AGGREGATION |
1584                 IEEE80211_HW_SUPPORTS_PS |
1585                 IEEE80211_HW_PS_NULLFUNC_STACK;
1586
1587         if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || modparam_nohwcrypt)
1588                 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
1589
1590         hw->wiphy->interface_modes =
1591                 BIT(NL80211_IFTYPE_AP) |
1592                 BIT(NL80211_IFTYPE_STATION) |
1593                 BIT(NL80211_IFTYPE_ADHOC);
1594
1595         hw->wiphy->reg_notifier = ath9k_reg_notifier;
1596         hw->wiphy->strict_regulatory = true;
1597
1598         hw->queues = 4;
1599         hw->max_rates = 4;
1600         hw->channel_change_time = 5000;
1601         hw->max_rate_tries = ATH_11N_TXMAXTRY;
1602         hw->sta_data_size = sizeof(struct ath_node);
1603         hw->vif_data_size = sizeof(struct ath_vif);
1604
1605         hw->rate_control_algorithm = "ath9k_rate_control";
1606
1607         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
1608                 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
1609                 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
1610                         setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
1611         }
1612
1613         hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &sc->sbands[IEEE80211_BAND_2GHZ];
1614         if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
1615                 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
1616                         &sc->sbands[IEEE80211_BAND_5GHZ];
1617
1618         /* initialize tx/rx engine */
1619         error = ath_tx_init(sc, ATH_TXBUF);
1620         if (error != 0)
1621                 goto error_attach;
1622
1623         error = ath_rx_init(sc, ATH_RXBUF);
1624         if (error != 0)
1625                 goto error_attach;
1626
1627 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1628         /* Initialze h/w Rfkill */
1629         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1630                 INIT_DELAYED_WORK(&sc->rf_kill.rfkill_poll, ath_rfkill_poll);
1631
1632         /* Initialize s/w rfkill */
1633         error = ath_init_sw_rfkill(sc);
1634         if (error)
1635                 goto error_attach;
1636 #endif
1637
1638         if (ath9k_is_world_regd(sc->sc_ah)) {
1639                 /* Anything applied here (prior to wiphy registration) gets
1640                  * saved on the wiphy orig_* parameters */
1641                 regd = ath9k_world_regdomain(sc->sc_ah);
1642                 hw->wiphy->custom_regulatory = true;
1643                 hw->wiphy->strict_regulatory = false;
1644         } else {
1645                 /* This gets applied in the case of the absense of CRDA,
1646                  * it's our own custom world regulatory domain, similar to
1647                  * cfg80211's but we enable passive scanning */
1648                 regd = ath9k_default_world_regdomain();
1649         }
1650         wiphy_apply_custom_regulatory(hw->wiphy, regd);
1651         ath9k_reg_apply_radar_flags(hw->wiphy);
1652         ath9k_reg_apply_world_flags(hw->wiphy, REGDOM_SET_BY_INIT);
1653
1654         error = ieee80211_register_hw(hw);
1655
1656         if (!ath9k_is_world_regd(sc->sc_ah)) {
1657                 error = regulatory_hint(hw->wiphy,
1658                         sc->sc_ah->regulatory.alpha2);
1659                 if (error)
1660                         goto error_attach;
1661         }
1662
1663         /* Initialize LED control */
1664         ath_init_leds(sc);
1665
1666
1667         return 0;
1668
1669 error_attach:
1670         /* cleanup tx queues */
1671         for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1672                 if (ATH_TXQ_SETUP(sc, i))
1673                         ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1674
1675         ath9k_hw_detach(sc->sc_ah);
1676         ath9k_exit_debug(sc);
1677
1678         return error;
1679 }
1680
1681 int ath_reset(struct ath_softc *sc, bool retry_tx)
1682 {
1683         struct ath_hw *ah = sc->sc_ah;
1684         struct ieee80211_hw *hw = sc->hw;
1685         int r;
1686
1687         ath9k_hw_set_interrupts(ah, 0);
1688         ath_drain_all_txq(sc, retry_tx);
1689         ath_stoprecv(sc);
1690         ath_flushrecv(sc);
1691
1692         spin_lock_bh(&sc->sc_resetlock);
1693         r = ath9k_hw_reset(ah, sc->sc_ah->curchan, false);
1694         if (r)
1695                 DPRINTF(sc, ATH_DBG_FATAL,
1696                         "Unable to reset hardware; reset status %u\n", r);
1697         spin_unlock_bh(&sc->sc_resetlock);
1698
1699         if (ath_startrecv(sc) != 0)
1700                 DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n");
1701
1702         /*
1703          * We may be doing a reset in response to a request
1704          * that changes the channel so update any state that
1705          * might change as a result.
1706          */
1707         ath_cache_conf_rate(sc, &hw->conf);
1708
1709         ath_update_txpow(sc);
1710
1711         if (sc->sc_flags & SC_OP_BEACONS)
1712                 ath_beacon_config(sc, NULL);    /* restart beacons */
1713
1714         ath9k_hw_set_interrupts(ah, sc->imask);
1715
1716         if (retry_tx) {
1717                 int i;
1718                 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1719                         if (ATH_TXQ_SETUP(sc, i)) {
1720                                 spin_lock_bh(&sc->tx.txq[i].axq_lock);
1721                                 ath_txq_schedule(sc, &sc->tx.txq[i]);
1722                                 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
1723                         }
1724                 }
1725         }
1726
1727         return r;
1728 }
1729
1730 /*
1731  *  This function will allocate both the DMA descriptor structure, and the
1732  *  buffers it contains.  These are used to contain the descriptors used
1733  *  by the system.
1734 */
1735 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
1736                       struct list_head *head, const char *name,
1737                       int nbuf, int ndesc)
1738 {
1739 #define DS2PHYS(_dd, _ds)                                               \
1740         ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
1741 #define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
1742 #define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
1743
1744         struct ath_desc *ds;
1745         struct ath_buf *bf;
1746         int i, bsize, error;
1747
1748         DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
1749                 name, nbuf, ndesc);
1750
1751         /* ath_desc must be a multiple of DWORDs */
1752         if ((sizeof(struct ath_desc) % 4) != 0) {
1753                 DPRINTF(sc, ATH_DBG_FATAL, "ath_desc not DWORD aligned\n");
1754                 ASSERT((sizeof(struct ath_desc) % 4) == 0);
1755                 error = -ENOMEM;
1756                 goto fail;
1757         }
1758
1759         dd->dd_name = name;
1760         dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
1761
1762         /*
1763          * Need additional DMA memory because we can't use
1764          * descriptors that cross the 4K page boundary. Assume
1765          * one skipped descriptor per 4K page.
1766          */
1767         if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1768                 u32 ndesc_skipped =
1769                         ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
1770                 u32 dma_len;
1771
1772                 while (ndesc_skipped) {
1773                         dma_len = ndesc_skipped * sizeof(struct ath_desc);
1774                         dd->dd_desc_len += dma_len;
1775
1776                         ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
1777                 };
1778         }
1779
1780         /* allocate descriptors */
1781         dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
1782                                          &dd->dd_desc_paddr, GFP_ATOMIC);
1783         if (dd->dd_desc == NULL) {
1784                 error = -ENOMEM;
1785                 goto fail;
1786         }
1787         ds = dd->dd_desc;
1788         DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
1789                 dd->dd_name, ds, (u32) dd->dd_desc_len,
1790                 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
1791
1792         /* allocate buffers */
1793         bsize = sizeof(struct ath_buf) * nbuf;
1794         bf = kmalloc(bsize, GFP_KERNEL);
1795         if (bf == NULL) {
1796                 error = -ENOMEM;
1797                 goto fail2;
1798         }
1799         memset(bf, 0, bsize);
1800         dd->dd_bufptr = bf;
1801
1802         INIT_LIST_HEAD(head);
1803         for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
1804                 bf->bf_desc = ds;
1805                 bf->bf_daddr = DS2PHYS(dd, ds);
1806
1807                 if (!(sc->sc_ah->caps.hw_caps &
1808                       ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1809                         /*
1810                          * Skip descriptor addresses which can cause 4KB
1811                          * boundary crossing (addr + length) with a 32 dword
1812                          * descriptor fetch.
1813                          */
1814                         while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
1815                                 ASSERT((caddr_t) bf->bf_desc <
1816                                        ((caddr_t) dd->dd_desc +
1817                                         dd->dd_desc_len));
1818
1819                                 ds += ndesc;
1820                                 bf->bf_desc = ds;
1821                                 bf->bf_daddr = DS2PHYS(dd, ds);
1822                         }
1823                 }
1824                 list_add_tail(&bf->list, head);
1825         }
1826         return 0;
1827 fail2:
1828         dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1829                           dd->dd_desc_paddr);
1830 fail:
1831         memset(dd, 0, sizeof(*dd));
1832         return error;
1833 #undef ATH_DESC_4KB_BOUND_CHECK
1834 #undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
1835 #undef DS2PHYS
1836 }
1837
1838 void ath_descdma_cleanup(struct ath_softc *sc,
1839                          struct ath_descdma *dd,
1840                          struct list_head *head)
1841 {
1842         dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1843                           dd->dd_desc_paddr);
1844
1845         INIT_LIST_HEAD(head);
1846         kfree(dd->dd_bufptr);
1847         memset(dd, 0, sizeof(*dd));
1848 }
1849
1850 int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
1851 {
1852         int qnum;
1853
1854         switch (queue) {
1855         case 0:
1856                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VO];
1857                 break;
1858         case 1:
1859                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VI];
1860                 break;
1861         case 2:
1862                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
1863                 break;
1864         case 3:
1865                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BK];
1866                 break;
1867         default:
1868                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
1869                 break;
1870         }
1871
1872         return qnum;
1873 }
1874
1875 int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
1876 {
1877         int qnum;
1878
1879         switch (queue) {
1880         case ATH9K_WME_AC_VO:
1881                 qnum = 0;
1882                 break;
1883         case ATH9K_WME_AC_VI:
1884                 qnum = 1;
1885                 break;
1886         case ATH9K_WME_AC_BE:
1887                 qnum = 2;
1888                 break;
1889         case ATH9K_WME_AC_BK:
1890                 qnum = 3;
1891                 break;
1892         default:
1893                 qnum = -1;
1894                 break;
1895         }
1896
1897         return qnum;
1898 }
1899
1900 /* XXX: Remove me once we don't depend on ath9k_channel for all
1901  * this redundant data */
1902 static void ath9k_update_ichannel(struct ath_softc *sc,
1903                           struct ath9k_channel *ichan)
1904 {
1905         struct ieee80211_hw *hw = sc->hw;
1906         struct ieee80211_channel *chan = hw->conf.channel;
1907         struct ieee80211_conf *conf = &hw->conf;
1908
1909         ichan->channel = chan->center_freq;
1910         ichan->chan = chan;
1911
1912         if (chan->band == IEEE80211_BAND_2GHZ) {
1913                 ichan->chanmode = CHANNEL_G;
1914                 ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM;
1915         } else {
1916                 ichan->chanmode = CHANNEL_A;
1917                 ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM;
1918         }
1919
1920         sc->tx_chan_width = ATH9K_HT_MACMODE_20;
1921
1922         if (conf_is_ht(conf)) {
1923                 if (conf_is_ht40(conf))
1924                         sc->tx_chan_width = ATH9K_HT_MACMODE_2040;
1925
1926                 ichan->chanmode = ath_get_extchanmode(sc, chan,
1927                                             conf->channel_type);
1928         }
1929 }
1930
1931 /**********************/
1932 /* mac80211 callbacks */
1933 /**********************/
1934
1935 static int ath9k_start(struct ieee80211_hw *hw)
1936 {
1937         struct ath_softc *sc = hw->priv;
1938         struct ieee80211_channel *curchan = hw->conf.channel;
1939         struct ath9k_channel *init_channel;
1940         int r, pos;
1941
1942         DPRINTF(sc, ATH_DBG_CONFIG, "Starting driver with "
1943                 "initial channel: %d MHz\n", curchan->center_freq);
1944
1945         mutex_lock(&sc->mutex);
1946
1947         /* setup initial channel */
1948
1949         pos = curchan->hw_value;
1950
1951         init_channel = &sc->sc_ah->channels[pos];
1952         ath9k_update_ichannel(sc, init_channel);
1953
1954         /* Reset SERDES registers */
1955         ath9k_hw_configpcipowersave(sc->sc_ah, 0);
1956
1957         /*
1958          * The basic interface to setting the hardware in a good
1959          * state is ``reset''.  On return the hardware is known to
1960          * be powered up and with interrupts disabled.  This must
1961          * be followed by initialization of the appropriate bits
1962          * and then setup of the interrupt mask.
1963          */
1964         spin_lock_bh(&sc->sc_resetlock);
1965         r = ath9k_hw_reset(sc->sc_ah, init_channel, false);
1966         if (r) {
1967                 DPRINTF(sc, ATH_DBG_FATAL,
1968                         "Unable to reset hardware; reset status %u "
1969                         "(freq %u MHz)\n", r,
1970                         curchan->center_freq);
1971                 spin_unlock_bh(&sc->sc_resetlock);
1972                 goto mutex_unlock;
1973         }
1974         spin_unlock_bh(&sc->sc_resetlock);
1975
1976         /*
1977          * This is needed only to setup initial state
1978          * but it's best done after a reset.
1979          */
1980         ath_update_txpow(sc);
1981
1982         /*
1983          * Setup the hardware after reset:
1984          * The receive engine is set going.
1985          * Frame transmit is handled entirely
1986          * in the frame output path; there's nothing to do
1987          * here except setup the interrupt mask.
1988          */
1989         if (ath_startrecv(sc) != 0) {
1990                 DPRINTF(sc, ATH_DBG_FATAL,
1991                         "Unable to start recv logic\n");
1992                 r = -EIO;
1993                 goto mutex_unlock;
1994         }
1995
1996         /* Setup our intr mask. */
1997         sc->imask = ATH9K_INT_RX | ATH9K_INT_TX
1998                 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
1999                 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
2000
2001         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_GTT)
2002                 sc->imask |= ATH9K_INT_GTT;
2003
2004         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
2005                 sc->imask |= ATH9K_INT_CST;
2006
2007         ath_cache_conf_rate(sc, &hw->conf);
2008
2009         sc->sc_flags &= ~SC_OP_INVALID;
2010
2011         /* Disable BMISS interrupt when we're not associated */
2012         sc->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
2013         ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
2014
2015         ieee80211_wake_queues(sc->hw);
2016
2017 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2018         r = ath_start_rfkill_poll(sc);
2019 #endif
2020
2021 mutex_unlock:
2022         mutex_unlock(&sc->mutex);
2023
2024         return r;
2025 }
2026
2027 static int ath9k_tx(struct ieee80211_hw *hw,
2028                     struct sk_buff *skb)
2029 {
2030         struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2031         struct ath_softc *sc = hw->priv;
2032         struct ath_tx_control txctl;
2033         int hdrlen, padsize;
2034
2035         memset(&txctl, 0, sizeof(struct ath_tx_control));
2036
2037         /*
2038          * As a temporary workaround, assign seq# here; this will likely need
2039          * to be cleaned up to work better with Beacon transmission and virtual
2040          * BSSes.
2041          */
2042         if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
2043                 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2044                 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
2045                         sc->tx.seq_no += 0x10;
2046                 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
2047                 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
2048         }
2049
2050         /* Add the padding after the header if this is not already done */
2051         hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2052         if (hdrlen & 3) {
2053                 padsize = hdrlen % 4;
2054                 if (skb_headroom(skb) < padsize)
2055                         return -1;
2056                 skb_push(skb, padsize);
2057                 memmove(skb->data, skb->data + padsize, hdrlen);
2058         }
2059
2060         /* Check if a tx queue is available */
2061
2062         txctl.txq = ath_test_get_txq(sc, skb);
2063         if (!txctl.txq)
2064                 goto exit;
2065
2066         DPRINTF(sc, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
2067
2068         if (ath_tx_start(sc, skb, &txctl) != 0) {
2069                 DPRINTF(sc, ATH_DBG_XMIT, "TX failed\n");
2070                 goto exit;
2071         }
2072
2073         return 0;
2074 exit:
2075         dev_kfree_skb_any(skb);
2076         return 0;
2077 }
2078
2079 static void ath9k_stop(struct ieee80211_hw *hw)
2080 {
2081         struct ath_softc *sc = hw->priv;
2082
2083         if (sc->sc_flags & SC_OP_INVALID) {
2084                 DPRINTF(sc, ATH_DBG_ANY, "Device not present\n");
2085                 return;
2086         }
2087
2088         mutex_lock(&sc->mutex);
2089
2090         ieee80211_stop_queues(sc->hw);
2091
2092         /* make sure h/w will not generate any interrupt
2093          * before setting the invalid flag. */
2094         ath9k_hw_set_interrupts(sc->sc_ah, 0);
2095
2096         if (!(sc->sc_flags & SC_OP_INVALID)) {
2097                 ath_drain_all_txq(sc, false);
2098                 ath_stoprecv(sc);
2099                 ath9k_hw_phy_disable(sc->sc_ah);
2100         } else
2101                 sc->rx.rxlink = NULL;
2102
2103 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2104         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2105                 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
2106 #endif
2107         /* disable HAL and put h/w to sleep */
2108         ath9k_hw_disable(sc->sc_ah);
2109         ath9k_hw_configpcipowersave(sc->sc_ah, 1);
2110
2111         sc->sc_flags |= SC_OP_INVALID;
2112
2113         mutex_unlock(&sc->mutex);
2114
2115         DPRINTF(sc, ATH_DBG_CONFIG, "Driver halt\n");
2116 }
2117
2118 static int ath9k_add_interface(struct ieee80211_hw *hw,
2119                                struct ieee80211_if_init_conf *conf)
2120 {
2121         struct ath_softc *sc = hw->priv;
2122         struct ath_vif *avp = (void *)conf->vif->drv_priv;
2123         enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
2124         int ret = 0;
2125
2126         mutex_lock(&sc->mutex);
2127
2128         if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) &&
2129             sc->nvifs > 0) {
2130                 ret = -ENOBUFS;
2131                 goto out;
2132         }
2133
2134         switch (conf->type) {
2135         case NL80211_IFTYPE_STATION:
2136                 ic_opmode = NL80211_IFTYPE_STATION;
2137                 break;
2138         case NL80211_IFTYPE_ADHOC:
2139                 if (sc->nbcnvifs >= ATH_BCBUF) {
2140                         ret = -ENOBUFS;
2141                         goto out;
2142                 }
2143                 ic_opmode = NL80211_IFTYPE_ADHOC;
2144                 break;
2145         case NL80211_IFTYPE_AP:
2146                 if (sc->nbcnvifs >= ATH_BCBUF) {
2147                         ret = -ENOBUFS;
2148                         goto out;
2149                 }
2150                 ic_opmode = NL80211_IFTYPE_AP;
2151                 break;
2152         default:
2153                 DPRINTF(sc, ATH_DBG_FATAL,
2154                         "Interface type %d not yet supported\n", conf->type);
2155                 ret = -EOPNOTSUPP;
2156                 goto out;
2157         }
2158
2159         DPRINTF(sc, ATH_DBG_CONFIG, "Attach a VIF of type: %d\n", ic_opmode);
2160
2161         /* Set the VIF opmode */
2162         avp->av_opmode = ic_opmode;
2163         avp->av_bslot = -1;
2164
2165         sc->nvifs++;
2166
2167         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
2168                 ath9k_set_bssid_mask(hw);
2169
2170         if (sc->nvifs > 1)
2171                 goto out; /* skip global settings for secondary vif */
2172
2173         if (ic_opmode == NL80211_IFTYPE_AP) {
2174                 ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
2175                 sc->sc_flags |= SC_OP_TSF_RESET;
2176         }
2177
2178         /* Set the device opmode */
2179         sc->sc_ah->opmode = ic_opmode;
2180
2181         /*
2182          * Enable MIB interrupts when there are hardware phy counters.
2183          * Note we only do this (at the moment) for station mode.
2184          */
2185         if ((conf->type == NL80211_IFTYPE_STATION) ||
2186             (conf->type == NL80211_IFTYPE_ADHOC)) {
2187                 if (ath9k_hw_phycounters(sc->sc_ah))
2188                         sc->imask |= ATH9K_INT_MIB;
2189                 sc->imask |= ATH9K_INT_TSFOOR;
2190         }
2191
2192         /*
2193          * Some hardware processes the TIM IE and fires an
2194          * interrupt when the TIM bit is set.  For hardware
2195          * that does, if not overridden by configuration,
2196          * enable the TIM interrupt when operating as station.
2197          */
2198         if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_ENHANCEDPM) &&
2199             (conf->type == NL80211_IFTYPE_STATION) &&
2200             !sc->config.swBeaconProcess)
2201                 sc->imask |= ATH9K_INT_TIM;
2202
2203         ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
2204
2205         if (conf->type == NL80211_IFTYPE_AP) {
2206                 /* TODO: is this a suitable place to start ANI for AP mode? */
2207                 /* Start ANI */
2208                 mod_timer(&sc->ani.timer,
2209                           jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
2210         }
2211
2212 out:
2213         mutex_unlock(&sc->mutex);
2214         return ret;
2215 }
2216
2217 static void ath9k_remove_interface(struct ieee80211_hw *hw,
2218                                    struct ieee80211_if_init_conf *conf)
2219 {
2220         struct ath_softc *sc = hw->priv;
2221         struct ath_vif *avp = (void *)conf->vif->drv_priv;
2222         int i;
2223
2224         DPRINTF(sc, ATH_DBG_CONFIG, "Detach Interface\n");
2225
2226         mutex_lock(&sc->mutex);
2227
2228         /* Stop ANI */
2229         del_timer_sync(&sc->ani.timer);
2230
2231         /* Reclaim beacon resources */
2232         if (sc->sc_ah->opmode == NL80211_IFTYPE_AP ||
2233             sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) {
2234                 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2235                 ath_beacon_return(sc, avp);
2236         }
2237
2238         sc->sc_flags &= ~SC_OP_BEACONS;
2239
2240         for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
2241                 if (sc->beacon.bslot[i] == conf->vif) {
2242                         printk(KERN_DEBUG "%s: vif had allocated beacon "
2243                                "slot\n", __func__);
2244                         sc->beacon.bslot[i] = NULL;
2245                 }
2246         }
2247
2248         sc->nvifs--;
2249
2250         mutex_unlock(&sc->mutex);
2251 }
2252
2253 static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
2254 {
2255         struct ath_softc *sc = hw->priv;
2256         struct ieee80211_conf *conf = &hw->conf;
2257
2258         mutex_lock(&sc->mutex);
2259
2260         if (changed & IEEE80211_CONF_CHANGE_PS) {
2261                 if (conf->flags & IEEE80211_CONF_PS) {
2262                         if ((sc->imask & ATH9K_INT_TIM_TIMER) == 0) {
2263                                 sc->imask |= ATH9K_INT_TIM_TIMER;
2264                                 ath9k_hw_set_interrupts(sc->sc_ah,
2265                                                 sc->imask);
2266                         }
2267                         ath9k_hw_setrxabort(sc->sc_ah, 1);
2268                         ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
2269                 } else {
2270                         ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
2271                         ath9k_hw_setrxabort(sc->sc_ah, 0);
2272                         sc->sc_flags &= ~SC_OP_WAIT_FOR_BEACON;
2273                         if (sc->imask & ATH9K_INT_TIM_TIMER) {
2274                                 sc->imask &= ~ATH9K_INT_TIM_TIMER;
2275                                 ath9k_hw_set_interrupts(sc->sc_ah,
2276                                                 sc->imask);
2277                         }
2278                 }
2279         }
2280
2281         if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
2282                 struct ieee80211_channel *curchan = hw->conf.channel;
2283                 int pos = curchan->hw_value;
2284
2285                 DPRINTF(sc, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
2286                         curchan->center_freq);
2287
2288                 /* XXX: remove me eventualy */
2289                 ath9k_update_ichannel(sc, &sc->sc_ah->channels[pos]);
2290
2291                 ath_update_chainmask(sc, conf_is_ht(conf));
2292
2293                 if (ath_set_channel(sc, &sc->sc_ah->channels[pos]) < 0) {
2294                         DPRINTF(sc, ATH_DBG_FATAL, "Unable to set channel\n");
2295                         mutex_unlock(&sc->mutex);
2296                         return -EINVAL;
2297                 }
2298         }
2299
2300         if (changed & IEEE80211_CONF_CHANGE_POWER)
2301                 sc->config.txpowlimit = 2 * conf->power_level;
2302
2303         /*
2304          * The HW TSF has to be reset when the beacon interval changes.
2305          * We set the flag here, and ath_beacon_config_ap() would take this
2306          * into account when it gets called through the subsequent
2307          * config_interface() call - with IFCC_BEACON in the changed field.
2308          */
2309
2310         if (changed & IEEE80211_CONF_CHANGE_BEACON_INTERVAL)
2311                 sc->sc_flags |= SC_OP_TSF_RESET;
2312
2313         mutex_unlock(&sc->mutex);
2314
2315         return 0;
2316 }
2317
2318 static int ath9k_config_interface(struct ieee80211_hw *hw,
2319                                   struct ieee80211_vif *vif,
2320                                   struct ieee80211_if_conf *conf)
2321 {
2322         struct ath_softc *sc = hw->priv;
2323         struct ath_hw *ah = sc->sc_ah;
2324         struct ath_vif *avp = (void *)vif->drv_priv;
2325         u32 rfilt = 0;
2326         int error, i;
2327
2328         mutex_lock(&sc->mutex);
2329
2330         /* TODO: Need to decide which hw opmode to use for multi-interface
2331          * cases */
2332         if (vif->type == NL80211_IFTYPE_AP &&
2333             ah->opmode != NL80211_IFTYPE_AP) {
2334                 ah->opmode = NL80211_IFTYPE_STATION;
2335                 ath9k_hw_setopmode(ah);
2336                 memcpy(sc->curbssid, sc->sc_ah->macaddr, ETH_ALEN);
2337                 sc->curaid = 0;
2338                 ath9k_hw_write_associd(sc);
2339                 /* Request full reset to get hw opmode changed properly */
2340                 sc->sc_flags |= SC_OP_FULL_RESET;
2341         }
2342
2343         if ((conf->changed & IEEE80211_IFCC_BSSID) &&
2344             !is_zero_ether_addr(conf->bssid)) {
2345                 switch (vif->type) {
2346                 case NL80211_IFTYPE_STATION:
2347                 case NL80211_IFTYPE_ADHOC:
2348                         /* Set BSSID */
2349                         memcpy(sc->curbssid, conf->bssid, ETH_ALEN);
2350                         sc->curaid = 0;
2351                         ath9k_hw_write_associd(sc);
2352
2353                         /* Set aggregation protection mode parameters */
2354                         sc->config.ath_aggr_prot = 0;
2355
2356                         DPRINTF(sc, ATH_DBG_CONFIG,
2357                                 "RX filter 0x%x bssid %pM aid 0x%x\n",
2358                                 rfilt, sc->curbssid, sc->curaid);
2359
2360                         /* need to reconfigure the beacon */
2361                         sc->sc_flags &= ~SC_OP_BEACONS ;
2362
2363                         break;
2364                 default:
2365                         break;
2366                 }
2367         }
2368
2369         if ((vif->type == NL80211_IFTYPE_ADHOC) ||
2370             (vif->type == NL80211_IFTYPE_AP)) {
2371                 if ((conf->changed & IEEE80211_IFCC_BEACON) ||
2372                     (conf->changed & IEEE80211_IFCC_BEACON_ENABLED &&
2373                      conf->enable_beacon)) {
2374                         /*
2375                          * Allocate and setup the beacon frame.
2376                          *
2377                          * Stop any previous beacon DMA.  This may be
2378                          * necessary, for example, when an ibss merge
2379                          * causes reconfiguration; we may be called
2380                          * with beacon transmission active.
2381                          */
2382                         ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2383
2384                         error = ath_beacon_alloc(sc, vif);
2385                         if (error != 0) {
2386                                 mutex_unlock(&sc->mutex);
2387                                 return error;
2388                         }
2389
2390                         ath_beacon_config(sc, vif);
2391                 }
2392         }
2393
2394         /* Check for WLAN_CAPABILITY_PRIVACY ? */
2395         if ((avp->av_opmode != NL80211_IFTYPE_STATION)) {
2396                 for (i = 0; i < IEEE80211_WEP_NKID; i++)
2397                         if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i))
2398                                 ath9k_hw_keysetmac(sc->sc_ah,
2399                                                    (u16)i,
2400                                                    sc->curbssid);
2401         }
2402
2403         /* Only legacy IBSS for now */
2404         if (vif->type == NL80211_IFTYPE_ADHOC)
2405                 ath_update_chainmask(sc, 0);
2406
2407         mutex_unlock(&sc->mutex);
2408
2409         return 0;
2410 }
2411
2412 #define SUPPORTED_FILTERS                       \
2413         (FIF_PROMISC_IN_BSS |                   \
2414         FIF_ALLMULTI |                          \
2415         FIF_CONTROL |                           \
2416         FIF_OTHER_BSS |                         \
2417         FIF_BCN_PRBRESP_PROMISC |               \
2418         FIF_FCSFAIL)
2419
2420 /* FIXME: sc->sc_full_reset ? */
2421 static void ath9k_configure_filter(struct ieee80211_hw *hw,
2422                                    unsigned int changed_flags,
2423                                    unsigned int *total_flags,
2424                                    int mc_count,
2425                                    struct dev_mc_list *mclist)
2426 {
2427         struct ath_softc *sc = hw->priv;
2428         u32 rfilt;
2429
2430         changed_flags &= SUPPORTED_FILTERS;
2431         *total_flags &= SUPPORTED_FILTERS;
2432
2433         sc->rx.rxfilter = *total_flags;
2434         rfilt = ath_calcrxfilter(sc);
2435         ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
2436
2437         DPRINTF(sc, ATH_DBG_CONFIG, "Set HW RX filter: 0x%x\n", sc->rx.rxfilter);
2438 }
2439
2440 static void ath9k_sta_notify(struct ieee80211_hw *hw,
2441                              struct ieee80211_vif *vif,
2442                              enum sta_notify_cmd cmd,
2443                              struct ieee80211_sta *sta)
2444 {
2445         struct ath_softc *sc = hw->priv;
2446
2447         switch (cmd) {
2448         case STA_NOTIFY_ADD:
2449                 ath_node_attach(sc, sta);
2450                 break;
2451         case STA_NOTIFY_REMOVE:
2452                 ath_node_detach(sc, sta);
2453                 break;
2454         default:
2455                 break;
2456         }
2457 }
2458
2459 static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
2460                          const struct ieee80211_tx_queue_params *params)
2461 {
2462         struct ath_softc *sc = hw->priv;
2463         struct ath9k_tx_queue_info qi;
2464         int ret = 0, qnum;
2465
2466         if (queue >= WME_NUM_AC)
2467                 return 0;
2468
2469         mutex_lock(&sc->mutex);
2470
2471         qi.tqi_aifs = params->aifs;
2472         qi.tqi_cwmin = params->cw_min;
2473         qi.tqi_cwmax = params->cw_max;
2474         qi.tqi_burstTime = params->txop;
2475         qnum = ath_get_hal_qnum(queue, sc);
2476
2477         DPRINTF(sc, ATH_DBG_CONFIG,
2478                 "Configure tx [queue/halq] [%d/%d],  "
2479                 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
2480                 queue, qnum, params->aifs, params->cw_min,
2481                 params->cw_max, params->txop);
2482
2483         ret = ath_txq_update(sc, qnum, &qi);
2484         if (ret)
2485                 DPRINTF(sc, ATH_DBG_FATAL, "TXQ Update failed\n");
2486
2487         mutex_unlock(&sc->mutex);
2488
2489         return ret;
2490 }
2491
2492 static int ath9k_set_key(struct ieee80211_hw *hw,
2493                          enum set_key_cmd cmd,
2494                          struct ieee80211_vif *vif,
2495                          struct ieee80211_sta *sta,
2496                          struct ieee80211_key_conf *key)
2497 {
2498         struct ath_softc *sc = hw->priv;
2499         int ret = 0;
2500
2501         if (modparam_nohwcrypt)
2502                 return -ENOSPC;
2503
2504         mutex_lock(&sc->mutex);
2505         ath9k_ps_wakeup(sc);
2506         DPRINTF(sc, ATH_DBG_KEYCACHE, "Set HW Key\n");
2507
2508         switch (cmd) {
2509         case SET_KEY:
2510                 ret = ath_key_config(sc, vif, sta, key);
2511                 if (ret >= 0) {
2512                         key->hw_key_idx = ret;
2513                         /* push IV and Michael MIC generation to stack */
2514                         key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2515                         if (key->alg == ALG_TKIP)
2516                                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
2517                         if (sc->sc_ah->sw_mgmt_crypto && key->alg == ALG_CCMP)
2518                                 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
2519                         ret = 0;
2520                 }
2521                 break;
2522         case DISABLE_KEY:
2523                 ath_key_delete(sc, key);
2524                 break;
2525         default:
2526                 ret = -EINVAL;
2527         }
2528
2529         ath9k_ps_restore(sc);
2530         mutex_unlock(&sc->mutex);
2531
2532         return ret;
2533 }
2534
2535 static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2536                                    struct ieee80211_vif *vif,
2537                                    struct ieee80211_bss_conf *bss_conf,
2538                                    u32 changed)
2539 {
2540         struct ath_softc *sc = hw->priv;
2541
2542         mutex_lock(&sc->mutex);
2543
2544         if (changed & BSS_CHANGED_ERP_PREAMBLE) {
2545                 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
2546                         bss_conf->use_short_preamble);
2547                 if (bss_conf->use_short_preamble)
2548                         sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
2549                 else
2550                         sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
2551         }
2552
2553         if (changed & BSS_CHANGED_ERP_CTS_PROT) {
2554                 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
2555                         bss_conf->use_cts_prot);
2556                 if (bss_conf->use_cts_prot &&
2557                     hw->conf.channel->band != IEEE80211_BAND_5GHZ)
2558                         sc->sc_flags |= SC_OP_PROTECT_ENABLE;
2559                 else
2560                         sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
2561         }
2562
2563         if (changed & BSS_CHANGED_ASSOC) {
2564                 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
2565                         bss_conf->assoc);
2566                 ath9k_bss_assoc_info(sc, vif, bss_conf);
2567         }
2568
2569         mutex_unlock(&sc->mutex);
2570 }
2571
2572 static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
2573 {
2574         u64 tsf;
2575         struct ath_softc *sc = hw->priv;
2576
2577         mutex_lock(&sc->mutex);
2578         tsf = ath9k_hw_gettsf64(sc->sc_ah);
2579         mutex_unlock(&sc->mutex);
2580
2581         return tsf;
2582 }
2583
2584 static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
2585 {
2586         struct ath_softc *sc = hw->priv;
2587
2588         mutex_lock(&sc->mutex);
2589         ath9k_hw_settsf64(sc->sc_ah, tsf);
2590         mutex_unlock(&sc->mutex);
2591 }
2592
2593 static void ath9k_reset_tsf(struct ieee80211_hw *hw)
2594 {
2595         struct ath_softc *sc = hw->priv;
2596
2597         mutex_lock(&sc->mutex);
2598         ath9k_hw_reset_tsf(sc->sc_ah);
2599         mutex_unlock(&sc->mutex);
2600 }
2601
2602 static int ath9k_ampdu_action(struct ieee80211_hw *hw,
2603                               enum ieee80211_ampdu_mlme_action action,
2604                               struct ieee80211_sta *sta,
2605                               u16 tid, u16 *ssn)
2606 {
2607         struct ath_softc *sc = hw->priv;
2608         int ret = 0;
2609
2610         switch (action) {
2611         case IEEE80211_AMPDU_RX_START:
2612                 if (!(sc->sc_flags & SC_OP_RXAGGR))
2613                         ret = -ENOTSUPP;
2614                 break;
2615         case IEEE80211_AMPDU_RX_STOP:
2616                 break;
2617         case IEEE80211_AMPDU_TX_START:
2618                 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
2619                 if (ret < 0)
2620                         DPRINTF(sc, ATH_DBG_FATAL,
2621                                 "Unable to start TX aggregation\n");
2622                 else
2623                         ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid);
2624                 break;
2625         case IEEE80211_AMPDU_TX_STOP:
2626                 ret = ath_tx_aggr_stop(sc, sta, tid);
2627                 if (ret < 0)
2628                         DPRINTF(sc, ATH_DBG_FATAL,
2629                                 "Unable to stop TX aggregation\n");
2630
2631                 ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid);
2632                 break;
2633         case IEEE80211_AMPDU_TX_RESUME:
2634                 ath_tx_aggr_resume(sc, sta, tid);
2635                 break;
2636         default:
2637                 DPRINTF(sc, ATH_DBG_FATAL, "Unknown AMPDU action\n");
2638         }
2639
2640         return ret;
2641 }
2642
2643 static void ath9k_sw_scan_start(struct ieee80211_hw *hw)
2644 {
2645         struct ath_softc *sc = hw->priv;
2646
2647         mutex_lock(&sc->mutex);
2648         sc->sc_flags |= SC_OP_SCANNING;
2649         mutex_unlock(&sc->mutex);
2650 }
2651
2652 static void ath9k_sw_scan_complete(struct ieee80211_hw *hw)
2653 {
2654         struct ath_softc *sc = hw->priv;
2655
2656         mutex_lock(&sc->mutex);
2657         sc->sc_flags &= ~SC_OP_SCANNING;
2658         mutex_unlock(&sc->mutex);
2659 }
2660
2661 struct ieee80211_ops ath9k_ops = {
2662         .tx                 = ath9k_tx,
2663         .start              = ath9k_start,
2664         .stop               = ath9k_stop,
2665         .add_interface      = ath9k_add_interface,
2666         .remove_interface   = ath9k_remove_interface,
2667         .config             = ath9k_config,
2668         .config_interface   = ath9k_config_interface,
2669         .configure_filter   = ath9k_configure_filter,
2670         .sta_notify         = ath9k_sta_notify,
2671         .conf_tx            = ath9k_conf_tx,
2672         .bss_info_changed   = ath9k_bss_info_changed,
2673         .set_key            = ath9k_set_key,
2674         .get_tsf            = ath9k_get_tsf,
2675         .set_tsf            = ath9k_set_tsf,
2676         .reset_tsf          = ath9k_reset_tsf,
2677         .ampdu_action       = ath9k_ampdu_action,
2678         .sw_scan_start      = ath9k_sw_scan_start,
2679         .sw_scan_complete   = ath9k_sw_scan_complete,
2680 };
2681
2682 static struct {
2683         u32 version;
2684         const char * name;
2685 } ath_mac_bb_names[] = {
2686         { AR_SREV_VERSION_5416_PCI,     "5416" },
2687         { AR_SREV_VERSION_5416_PCIE,    "5418" },
2688         { AR_SREV_VERSION_9100,         "9100" },
2689         { AR_SREV_VERSION_9160,         "9160" },
2690         { AR_SREV_VERSION_9280,         "9280" },
2691         { AR_SREV_VERSION_9285,         "9285" }
2692 };
2693
2694 static struct {
2695         u16 version;
2696         const char * name;
2697 } ath_rf_names[] = {
2698         { 0,                            "5133" },
2699         { AR_RAD5133_SREV_MAJOR,        "5133" },
2700         { AR_RAD5122_SREV_MAJOR,        "5122" },
2701         { AR_RAD2133_SREV_MAJOR,        "2133" },
2702         { AR_RAD2122_SREV_MAJOR,        "2122" }
2703 };
2704
2705 /*
2706  * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2707  */
2708 const char *
2709 ath_mac_bb_name(u32 mac_bb_version)
2710 {
2711         int i;
2712
2713         for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2714                 if (ath_mac_bb_names[i].version == mac_bb_version) {
2715                         return ath_mac_bb_names[i].name;
2716                 }
2717         }
2718
2719         return "????";
2720 }
2721
2722 /*
2723  * Return the RF name. "????" is returned if the RF is unknown.
2724  */
2725 const char *
2726 ath_rf_name(u16 rf_version)
2727 {
2728         int i;
2729
2730         for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2731                 if (ath_rf_names[i].version == rf_version) {
2732                         return ath_rf_names[i].name;
2733                 }
2734         }
2735
2736         return "????";
2737 }
2738
2739 static int __init ath9k_init(void)
2740 {
2741         int error;
2742
2743         /* Register rate control algorithm */
2744         error = ath_rate_control_register();
2745         if (error != 0) {
2746                 printk(KERN_ERR
2747                         "ath9k: Unable to register rate control "
2748                         "algorithm: %d\n",
2749                         error);
2750                 goto err_out;
2751         }
2752
2753         error = ath_pci_init();
2754         if (error < 0) {
2755                 printk(KERN_ERR
2756                         "ath9k: No PCI devices found, driver not installed.\n");
2757                 error = -ENODEV;
2758                 goto err_rate_unregister;
2759         }
2760
2761         error = ath_ahb_init();
2762         if (error < 0) {
2763                 error = -ENODEV;
2764                 goto err_pci_exit;
2765         }
2766
2767         return 0;
2768
2769  err_pci_exit:
2770         ath_pci_exit();
2771
2772  err_rate_unregister:
2773         ath_rate_control_unregister();
2774  err_out:
2775         return error;
2776 }
2777 module_init(ath9k_init);
2778
2779 static void __exit ath9k_exit(void)
2780 {
2781         ath_ahb_exit();
2782         ath_pci_exit();
2783         ath_rate_control_unregister();
2784         printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
2785 }
2786 module_exit(ath9k_exit);