SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/net/wireless/ath/ath9k/main.c

   1 /*
   2  * Copyright (c) 2008-2009 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/nl80211.h>
  18 #include "ath9k.h"
  19 #include "btcoex.h"
  20
  21 static char *dev_info = "ath9k";
  22
  23 MODULE_AUTHOR("Atheros Communications");
  24 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
  25 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
  26 MODULE_LICENSE("Dual BSD/GPL");
  27
  28 static int modparam_nohwcrypt;
  29 module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
  30 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
  31
  32 /* We use the hw_value as an index into our private channel structure */
  33
  34 #define CHAN2G(_freq, _idx)  { \
  35         .center_freq = (_freq), \
  36         .hw_value = (_idx), \
  37         .max_power = 20, \
  38 }
  39
  40 #define CHAN5G(_freq, _idx) { \
  41         .band = IEEE80211_BAND_5GHZ, \
  42         .center_freq = (_freq), \
  43         .hw_value = (_idx), \
  44         .max_power = 20, \
  45 }
  46
  47 /* Some 2 GHz radios are actually tunable on 2312-2732
  48  * on 5 MHz steps, we support the channels which we know
  49  * we have calibration data for all cards though to make
  50  * this static */
  51 static struct ieee80211_channel ath9k_2ghz_chantable[] = {
  52         CHAN2G(2412, 0), /* Channel 1 */
  53         CHAN2G(2417, 1), /* Channel 2 */
  54         CHAN2G(2422, 2), /* Channel 3 */
  55         CHAN2G(2427, 3), /* Channel 4 */
  56         CHAN2G(2432, 4), /* Channel 5 */
  57         CHAN2G(2437, 5), /* Channel 6 */
  58         CHAN2G(2442, 6), /* Channel 7 */
  59         CHAN2G(2447, 7), /* Channel 8 */
  60         CHAN2G(2452, 8), /* Channel 9 */
  61         CHAN2G(2457, 9), /* Channel 10 */
  62         CHAN2G(2462, 10), /* Channel 11 */
  63         CHAN2G(2467, 11), /* Channel 12 */
  64         CHAN2G(2472, 12), /* Channel 13 */
  65         CHAN2G(2484, 13), /* Channel 14 */
  66 };
  67
  68 /* Some 5 GHz radios are actually tunable on XXXX-YYYY
  69  * on 5 MHz steps, we support the channels which we know
  70  * we have calibration data for all cards though to make
  71  * this static */
  72 static struct ieee80211_channel ath9k_5ghz_chantable[] = {
  73         /* _We_ call this UNII 1 */
  74         CHAN5G(5180, 14), /* Channel 36 */
  75         CHAN5G(5200, 15), /* Channel 40 */
  76         CHAN5G(5220, 16), /* Channel 44 */
  77         CHAN5G(5240, 17), /* Channel 48 */
  78         /* _We_ call this UNII 2 */
  79         CHAN5G(5260, 18), /* Channel 52 */
  80         CHAN5G(5280, 19), /* Channel 56 */
  81         CHAN5G(5300, 20), /* Channel 60 */
  82         CHAN5G(5320, 21), /* Channel 64 */
  83         /* _We_ call this "Middle band" */
  84         CHAN5G(5500, 22), /* Channel 100 */
  85         CHAN5G(5520, 23), /* Channel 104 */
  86         CHAN5G(5540, 24), /* Channel 108 */
  87         CHAN5G(5560, 25), /* Channel 112 */
  88         CHAN5G(5580, 26), /* Channel 116 */
  89         CHAN5G(5600, 27), /* Channel 120 */
  90         CHAN5G(5620, 28), /* Channel 124 */
  91         CHAN5G(5640, 29), /* Channel 128 */
  92         CHAN5G(5660, 30), /* Channel 132 */
  93         CHAN5G(5680, 31), /* Channel 136 */
  94         CHAN5G(5700, 32), /* Channel 140 */
  95         /* _We_ call this UNII 3 */
  96         CHAN5G(5745, 33), /* Channel 149 */
  97         CHAN5G(5765, 34), /* Channel 153 */
  98         CHAN5G(5785, 35), /* Channel 157 */
  99         CHAN5G(5805, 36), /* Channel 161 */
 100         CHAN5G(5825, 37), /* Channel 165 */
 101 };
 102
 103 static void ath_cache_conf_rate(struct ath_softc *sc,
 104                                 struct ieee80211_conf *conf)
 105 {
 106         switch (conf->channel->band) {
 107         case IEEE80211_BAND_2GHZ:
 108                 if (conf_is_ht20(conf))
 109                         sc->cur_rate_table =
 110                           sc->hw_rate_table[ATH9K_MODE_11NG_HT20];
 111                 else if (conf_is_ht40_minus(conf))
 112                         sc->cur_rate_table =
 113                           sc->hw_rate_table[ATH9K_MODE_11NG_HT40MINUS];
 114                 else if (conf_is_ht40_plus(conf))
 115                         sc->cur_rate_table =
 116                           sc->hw_rate_table[ATH9K_MODE_11NG_HT40PLUS];
 117                 else
 118                         sc->cur_rate_table =
 119                           sc->hw_rate_table[ATH9K_MODE_11G];
 120                 break;
 121         case IEEE80211_BAND_5GHZ:
 122                 if (conf_is_ht20(conf))
 123                         sc->cur_rate_table =
 124                           sc->hw_rate_table[ATH9K_MODE_11NA_HT20];
 125                 else if (conf_is_ht40_minus(conf))
 126                         sc->cur_rate_table =
 127                           sc->hw_rate_table[ATH9K_MODE_11NA_HT40MINUS];
 128                 else if (conf_is_ht40_plus(conf))
 129                         sc->cur_rate_table =
 130                           sc->hw_rate_table[ATH9K_MODE_11NA_HT40PLUS];
 131                 else
 132                         sc->cur_rate_table =
 133                           sc->hw_rate_table[ATH9K_MODE_11A];
 134                 break;
 135         default:
 136                 BUG_ON(1);
 137                 break;
 138         }
 139 }
 140
 141 static void ath_update_txpow(struct ath_softc *sc)
 142 {
 143         struct ath_hw *ah = sc->sc_ah;
 144         u32 txpow;
 145
 146         if (sc->curtxpow != sc->config.txpowlimit) {
 147                 ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit);
 148                 /* read back in case value is clamped */
 149                 ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
 150                 sc->curtxpow = txpow;
 151         }
 152 }
 153
 154 static u8 parse_mpdudensity(u8 mpdudensity)
 155 {
 156         /*
 157          * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
 158          *   0 for no restriction
 159          *   1 for 1/4 us
 160          *   2 for 1/2 us
 161          *   3 for 1 us
 162          *   4 for 2 us
 163          *   5 for 4 us
 164          *   6 for 8 us
 165          *   7 for 16 us
 166          */
 167         switch (mpdudensity) {
 168         case 0:
 169                 return 0;
 170         case 1:
 171         case 2:
 172         case 3:
 173                 /* Our lower layer calculations limit our precision to
 174                    1 microsecond */
 175                 return 1;
 176         case 4:
 177                 return 2;
 178         case 5:
 179                 return 4;
 180         case 6:
 181                 return 8;
 182         case 7:
 183                 return 16;
 184         default:
 185                 return 0;
 186         }
 187 }
 188
 189 static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band)
 190 {
 191         const struct ath_rate_table *rate_table = NULL;
 192         struct ieee80211_supported_band *sband;
 193         struct ieee80211_rate *rate;
 194         int i, maxrates;
 195
 196         switch (band) {
 197         case IEEE80211_BAND_2GHZ:
 198                 rate_table = sc->hw_rate_table[ATH9K_MODE_11G];
 199                 break;
 200         case IEEE80211_BAND_5GHZ:
 201                 rate_table = sc->hw_rate_table[ATH9K_MODE_11A];
 202                 break;
 203         default:
 204                 break;
 205         }
 206
 207         if (rate_table == NULL)
 208                 return;
 209
 210         sband = &sc->sbands[band];
 211         rate = sc->rates[band];
 212
 213         if (rate_table->rate_cnt > ATH_RATE_MAX)
 214                 maxrates = ATH_RATE_MAX;
 215         else
 216                 maxrates = rate_table->rate_cnt;
 217
 218         for (i = 0; i < maxrates; i++) {
 219                 rate[i].bitrate = rate_table->info[i].ratekbps / 100;
 220                 rate[i].hw_value = rate_table->info[i].ratecode;
 221                 if (rate_table->info[i].short_preamble) {
 222                         rate[i].hw_value_short = rate_table->info[i].ratecode |
 223                                 rate_table->info[i].short_preamble;
 224                         rate[i].flags = IEEE80211_RATE_SHORT_PREAMBLE;
 225                 }
 226                 sband->n_bitrates++;
 227
 228                 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "Rate: %2dMbps, ratecode: %2d\n",
 229                         rate[i].bitrate / 10, rate[i].hw_value);
 230         }
 231 }
 232
 233 static struct ath9k_channel *ath_get_curchannel(struct ath_softc *sc,
 234                                                 struct ieee80211_hw *hw)
 235 {
 236         struct ieee80211_channel *curchan = hw->conf.channel;
 237         struct ath9k_channel *channel;
 238         u8 chan_idx;
 239
 240         chan_idx = curchan->hw_value;
 241         channel = &sc->sc_ah->channels[chan_idx];
 242         ath9k_update_ichannel(sc, hw, channel);
 243         return channel;
 244 }
 245
 246 static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
 247 {
 248         unsigned long flags;
 249         bool ret;
 250
 251         spin_lock_irqsave(&sc->sc_pm_lock, flags);
 252         ret = ath9k_hw_setpower(sc->sc_ah, mode);
 253         spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
 254
 255         return ret;
 256 }
 257
 258 void ath9k_ps_wakeup(struct ath_softc *sc)
 259 {
 260         unsigned long flags;
 261
 262         spin_lock_irqsave(&sc->sc_pm_lock, flags);
 263         if (++sc->ps_usecount != 1)
 264                 goto unlock;
 265
 266         ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
 267
 268  unlock:
 269         spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
 270 }
 271
 272 void ath9k_ps_restore(struct ath_softc *sc)
 273 {
 274         unsigned long flags;
 275
 276         spin_lock_irqsave(&sc->sc_pm_lock, flags);
 277         if (--sc->ps_usecount != 0)
 278                 goto unlock;
 279
 280         if (sc->ps_enabled &&
 281             !(sc->sc_flags & (SC_OP_WAIT_FOR_BEACON |
 282                               SC_OP_WAIT_FOR_CAB |
 283                               SC_OP_WAIT_FOR_PSPOLL_DATA |
 284                               SC_OP_WAIT_FOR_TX_ACK)))
 285                 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
 286
 287  unlock:
 288         spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
 289 }
 290
 291 /*
 292  * Set/change channels.  If the channel is really being changed, it's done
 293  * by reseting the chip.  To accomplish this we must first cleanup any pending
 294  * DMA, then restart stuff.
 295 */
 296 int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
 297                     struct ath9k_channel *hchan)
 298 {
 299         struct ath_hw *ah = sc->sc_ah;
 300         bool fastcc = true, stopped;
 301         struct ieee80211_channel *channel = hw->conf.channel;
 302         int r;
 303
 304         if (sc->sc_flags & SC_OP_INVALID)
 305                 return -EIO;
 306
 307         ath9k_ps_wakeup(sc);
 308
 309         /*
 310          * This is only performed if the channel settings have
 311          * actually changed.
 312          *
 313          * To switch channels clear any pending DMA operations;
 314          * wait long enough for the RX fifo to drain, reset the
 315          * hardware at the new frequency, and then re-enable
 316          * the relevant bits of the h/w.
 317          */
 318         ath9k_hw_set_interrupts(ah, 0);
 319         ath_drain_all_txq(sc, false);
 320         stopped = ath_stoprecv(sc);
 321
 322         /* XXX: do not flush receive queue here. We don't want
 323          * to flush data frames already in queue because of
 324          * changing channel. */
 325
 326         if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
 327                 fastcc = false;
 328
 329         DPRINTF(sc->sc_ah, ATH_DBG_CONFIG,
 330                 "(%u MHz) -> (%u MHz), chanwidth: %d\n",
 331                 sc->sc_ah->curchan->channel,
 332                 channel->center_freq, sc->tx_chan_width);
 333
 334         spin_lock_bh(&sc->sc_resetlock);
 335
 336         r = ath9k_hw_reset(ah, hchan, fastcc);
 337         if (r) {
 338                 DPRINTF(sc->sc_ah, ATH_DBG_FATAL,
 339                         "Unable to reset channel (%u Mhz) "
 340                         "reset status %d\n",
 341                         channel->center_freq, r);
 342                 spin_unlock_bh(&sc->sc_resetlock);
 343                 goto ps_restore;
 344         }
 345         spin_unlock_bh(&sc->sc_resetlock);
 346
 347         sc->sc_flags &= ~SC_OP_FULL_RESET;
 348
 349         if (ath_startrecv(sc) != 0) {
 350                 DPRINTF(sc->sc_ah, ATH_DBG_FATAL,
 351                         "Unable to restart recv logic\n");
 352                 r = -EIO;
 353                 goto ps_restore;
 354         }
 355
 356         ath_cache_conf_rate(sc, &hw->conf);
 357         ath_update_txpow(sc);
 358         ath9k_hw_set_interrupts(ah, sc->imask);
 359
 360  ps_restore:
 361         ath9k_ps_restore(sc);
 362         return r;
 363 }
 364
 365 /*
 366  *  This routine performs the periodic noise floor calibration function
 367  *  that is used to adjust and optimize the chip performance.  This
 368  *  takes environmental changes (location, temperature) into account.
 369  *  When the task is complete, it reschedules itself depending on the
 370  *  appropriate interval that was calculated.
 371  */
 372 static void ath_ani_calibrate(unsigned long data)
 373 {
 374         struct ath_softc *sc = (struct ath_softc *)data;
 375         struct ath_hw *ah = sc->sc_ah;
 376         bool longcal = false;
 377         bool shortcal = false;
 378         bool aniflag = false;
 379         unsigned int timestamp = jiffies_to_msecs(jiffies);
 380         u32 cal_interval, short_cal_interval;
 381
 382         short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
 383                 ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
 384
 385         /*
 386         * don't calibrate when we're scanning.
 387         * we are most likely not on our home channel.
 388         */
 389         spin_lock(&sc->ani_lock);
 390         if (sc->sc_flags & SC_OP_SCANNING)
 391                 goto set_timer;
 392
 393         /* Only calibrate if awake */
 394         if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE)
 395                 goto set_timer;
 396
 397         ath9k_ps_wakeup(sc);
 398
 399         /* Long calibration runs independently of short calibration. */
 400         if ((timestamp - sc->ani.longcal_timer) >= ATH_LONG_CALINTERVAL) {
 401                 longcal = true;
 402                 DPRINTF(sc->sc_ah, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
 403                 sc->ani.longcal_timer = timestamp;
 404         }
 405
 406         /* Short calibration applies only while caldone is false */
 407         if (!sc->ani.caldone) {
 408                 if ((timestamp - sc->ani.shortcal_timer) >= short_cal_interval) {
 409                         shortcal = true;
 410                         DPRINTF(sc->sc_ah, ATH_DBG_ANI, "shortcal @%lu\n", jiffies);
 411                         sc->ani.shortcal_timer = timestamp;
 412                         sc->ani.resetcal_timer = timestamp;
 413                 }
 414         } else {
 415                 if ((timestamp - sc->ani.resetcal_timer) >=
 416                     ATH_RESTART_CALINTERVAL) {
 417                         sc->ani.caldone = ath9k_hw_reset_calvalid(ah);
 418                         if (sc->ani.caldone)
 419                                 sc->ani.resetcal_timer = timestamp;
 420                 }
 421         }
 422
 423         /* Verify whether we must check ANI */
 424         if ((timestamp - sc->ani.checkani_timer) >= ATH_ANI_POLLINTERVAL) {
 425                 aniflag = true;
 426                 sc->ani.checkani_timer = timestamp;
 427         }
 428
 429         /* Skip all processing if there's nothing to do. */
 430         if (longcal || shortcal || aniflag) {
 431                 /* Call ANI routine if necessary */
 432                 if (aniflag)
 433                         ath9k_hw_ani_monitor(ah, ah->curchan);
 434
 435                 /* Perform calibration if necessary */
 436                 if (longcal || shortcal) {
 437                         sc->ani.caldone = ath9k_hw_calibrate(ah, ah->curchan,
 438                                                      sc->rx_chainmask, longcal);
 439
 440                         if (longcal)
 441                                 sc->ani.noise_floor = ath9k_hw_getchan_noise(ah,
 442                                                                      ah->curchan);
 443
 444                         DPRINTF(sc->sc_ah, ATH_DBG_ANI," calibrate chan %u/%x nf: %d\n",
 445                                 ah->curchan->channel, ah->curchan->channelFlags,
 446                                 sc->ani.noise_floor);
 447                 }
 448         }
 449
 450         ath9k_ps_restore(sc);
 451
 452 set_timer:
 453         spin_unlock(&sc->ani_lock);
 454         /*
 455         * Set timer interval based on previous results.
 456         * The interval must be the shortest necessary to satisfy ANI,
 457         * short calibration and long calibration.
 458         */
 459         cal_interval = ATH_LONG_CALINTERVAL;
 460         if (sc->sc_ah->config.enable_ani)
 461                 cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL);
 462         if (!sc->ani.caldone)
 463                 cal_interval = min(cal_interval, (u32)short_cal_interval);
 464
 465         mod_timer(&sc->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
 466 }
 467
 468 static void ath_start_ani(struct ath_softc *sc)
 469 {
 470         unsigned long timestamp = jiffies_to_msecs(jiffies);
 471
 472         sc->ani.longcal_timer = timestamp;
 473         sc->ani.shortcal_timer = timestamp;
 474         sc->ani.checkani_timer = timestamp;
 475
 476         mod_timer(&sc->ani.timer,
 477                   jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
 478 }
 479
 480 /*
 481  * Update tx/rx chainmask. For legacy association,
 482  * hard code chainmask to 1x1, for 11n association, use
 483  * the chainmask configuration, for bt coexistence, use
 484  * the chainmask configuration even in legacy mode.
 485  */
 486 void ath_update_chainmask(struct ath_softc *sc, int is_ht)
 487 {
 488         struct ath_hw *ah = sc->sc_ah;
 489
 490         if ((sc->sc_flags & SC_OP_SCANNING) || is_ht ||
 491             (ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE)) {
 492                 sc->tx_chainmask = sc->sc_ah->caps.tx_chainmask;
 493                 sc->rx_chainmask = sc->sc_ah->caps.rx_chainmask;
 494         } else {
 495                 sc->tx_chainmask = 1;
 496                 sc->rx_chainmask = 1;
 497         }
 498
 499         DPRINTF(ah, ATH_DBG_CONFIG, "tx chmask: %d, rx chmask: %d\n",
 500                 sc->tx_chainmask, sc->rx_chainmask);
 501 }
 502
 503 static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
 504 {
 505         struct ath_node *an;
 506
 507         an = (struct ath_node *)sta->drv_priv;
 508
 509         if (sc->sc_flags & SC_OP_TXAGGR) {
 510                 ath_tx_node_init(sc, an);
 511                 an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
 512                                      sta->ht_cap.ampdu_factor);
 513                 an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
 514                 an->last_rssi = ATH_RSSI_DUMMY_MARKER;
 515         }
 516 }
 517
 518 static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
 519 {
 520         struct ath_node *an = (struct ath_node *)sta->drv_priv;
 521
 522         if (sc->sc_flags & SC_OP_TXAGGR)
 523                 ath_tx_node_cleanup(sc, an);
 524 }
 525
 526 static void ath9k_tasklet(unsigned long data)
 527 {
 528         struct ath_softc *sc = (struct ath_softc *)data;
 529         struct ath_hw *ah = sc->sc_ah;
 530
 531         u32 status = sc->intrstatus;
 532
 533         ath9k_ps_wakeup(sc);
 534
 535         if (status & ATH9K_INT_FATAL) {
 536                 ath_reset(sc, false);
 537                 ath9k_ps_restore(sc);
 538                 return;
 539         }
 540
 541         if (status & (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
 542                 spin_lock_bh(&sc->rx.rxflushlock);
 543                 ath_rx_tasklet(sc, 0);
 544                 spin_unlock_bh(&sc->rx.rxflushlock);
 545         }
 546
 547         if (status & ATH9K_INT_TX)
 548                 ath_tx_tasklet(sc);
 549
 550         if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
 551                 /*
 552                  * TSF sync does not look correct; remain awake to sync with
 553                  * the next Beacon.
 554                  */
 555                 DPRINTF(ah, ATH_DBG_PS, "TSFOOR - Sync with next Beacon\n");
 556                 sc->sc_flags |= SC_OP_WAIT_FOR_BEACON | SC_OP_BEACON_SYNC;
 557         }
 558
 559         if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
 560                 if (status & ATH9K_INT_GENTIMER)
 561                         ath_gen_timer_isr(sc->sc_ah);
 562
 563         /* re-enable hardware interrupt */
 564         ath9k_hw_set_interrupts(ah, sc->imask);
 565         ath9k_ps_restore(sc);
 566 }
 567
 568 irqreturn_t ath_isr(int irq, void *dev)
 569 {
 570 #define SCHED_INTR (                            \
 571                 ATH9K_INT_FATAL |               \
 572                 ATH9K_INT_RXORN |               \
 573                 ATH9K_INT_RXEOL |               \
 574                 ATH9K_INT_RX |                  \
 575                 ATH9K_INT_TX |                  \
 576                 ATH9K_INT_BMISS |               \
 577                 ATH9K_INT_CST |                 \
 578                 ATH9K_INT_TSFOOR |              \
 579                 ATH9K_INT_GENTIMER)
 580
 581         struct ath_softc *sc = dev;
 582         struct ath_hw *ah = sc->sc_ah;
 583         enum ath9k_int status;
 584         bool sched = false;
 585
 586         /*
 587          * The hardware is not ready/present, don't
 588          * touch anything. Note this can happen early
 589          * on if the IRQ is shared.
 590          */
 591         if (sc->sc_flags & SC_OP_INVALID)
 592                 return IRQ_NONE;
 593
 594
 595         /* shared irq, not for us */
 596
 597         if (!ath9k_hw_intrpend(ah))
 598                 return IRQ_NONE;
 599
 600         /*
 601          * Figure out the reason(s) for the interrupt.  Note
 602          * that the hal returns a pseudo-ISR that may include
 603          * bits we haven't explicitly enabled so we mask the
 604          * value to insure we only process bits we requested.
 605          */
 606         ath9k_hw_getisr(ah, &status);   /* NB: clears ISR too */
 607         status &= sc->imask;    /* discard unasked-for bits */
 608
 609         /*
 610          * If there are no status bits set, then this interrupt was not
 611          * for me (should have been caught above).
 612          */
 613         if (!status)
 614                 return IRQ_NONE;
 615
 616         /* Cache the status */
 617         sc->intrstatus = status;
 618
 619         if (status & SCHED_INTR)
 620                 sched = true;
 621
 622         /*
 623          * If a FATAL or RXORN interrupt is received, we have to reset the
 624          * chip immediately.
 625          */
 626         if (status & (ATH9K_INT_FATAL | ATH9K_INT_RXORN))
 627                 goto chip_reset;
 628
 629         if (status & ATH9K_INT_SWBA)
 630                 tasklet_schedule(&sc->bcon_tasklet);
 631
 632         if (status & ATH9K_INT_TXURN)
 633                 ath9k_hw_updatetxtriglevel(ah, true);
 634
 635         if (status & ATH9K_INT_MIB) {
 636                 /*
 637                  * Disable interrupts until we service the MIB
 638                  * interrupt; otherwise it will continue to
 639                  * fire.
 640                  */
 641                 ath9k_hw_set_interrupts(ah, 0);
 642                 /*
 643                  * Let the hal handle the event. We assume
 644                  * it will clear whatever condition caused
 645                  * the interrupt.
 646                  */
 647                 ath9k_hw_procmibevent(ah);
 648                 ath9k_hw_set_interrupts(ah, sc->imask);
 649         }
 650
 651         if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
 652                 if (status & ATH9K_INT_TIM_TIMER) {
 653                         /* Clear RxAbort bit so that we can
 654                          * receive frames */
 655                         ath9k_setpower(sc, ATH9K_PM_AWAKE);
 656                         ath9k_hw_setrxabort(sc->sc_ah, 0);
 657                         sc->sc_flags |= SC_OP_WAIT_FOR_BEACON;
 658                 }
 659
 660 chip_reset:
 661
 662         ath_debug_stat_interrupt(sc, status);
 663
 664         if (sched) {
 665                 /* turn off every interrupt except SWBA */
 666                 ath9k_hw_set_interrupts(ah, (sc->imask & ATH9K_INT_SWBA));
 667                 tasklet_schedule(&sc->intr_tq);
 668         }
 669
 670         return IRQ_HANDLED;
 671
 672 #undef SCHED_INTR
 673 }
 674
 675 static u32 ath_get_extchanmode(struct ath_softc *sc,
 676                                struct ieee80211_channel *chan,
 677                                enum nl80211_channel_type channel_type)
 678 {
 679         u32 chanmode = 0;
 680
 681         switch (chan->band) {
 682         case IEEE80211_BAND_2GHZ:
 683                 switch(channel_type) {
 684                 case NL80211_CHAN_NO_HT:
 685                 case NL80211_CHAN_HT20:
 686                         chanmode = CHANNEL_G_HT20;
 687                         break;
 688                 case NL80211_CHAN_HT40PLUS:
 689                         chanmode = CHANNEL_G_HT40PLUS;
 690                         break;
 691                 case NL80211_CHAN_HT40MINUS:
 692                         chanmode = CHANNEL_G_HT40MINUS;
 693                         break;
 694                 }
 695                 break;
 696         case IEEE80211_BAND_5GHZ:
 697                 switch(channel_type) {
 698                 case NL80211_CHAN_NO_HT:
 699                 case NL80211_CHAN_HT20:
 700                         chanmode = CHANNEL_A_HT20;
 701                         break;
 702                 case NL80211_CHAN_HT40PLUS:
 703                         chanmode = CHANNEL_A_HT40PLUS;
 704                         break;
 705                 case NL80211_CHAN_HT40MINUS:
 706                         chanmode = CHANNEL_A_HT40MINUS;
 707                         break;
 708                 }
 709                 break;
 710         default:
 711                 break;
 712         }
 713
 714         return chanmode;
 715 }
 716
 717 static int ath_setkey_tkip(struct ath_softc *sc, u16 keyix, const u8 *key,
 718                            struct ath9k_keyval *hk, const u8 *addr,
 719                            bool authenticator)
 720 {
 721         const u8 *key_rxmic;
 722         const u8 *key_txmic;
 723
 724         key_txmic = key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
 725         key_rxmic = key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
 726
 727         if (addr == NULL) {
 728                 /*
 729                  * Group key installation - only two key cache entries are used
 730                  * regardless of splitmic capability since group key is only
 731                  * used either for TX or RX.
 732                  */
 733                 if (authenticator) {
 734                         memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
 735                         memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_mic));
 736                 } else {
 737                         memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
 738                         memcpy(hk->kv_txmic, key_rxmic, sizeof(hk->kv_mic));
 739                 }
 740                 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
 741         }
 742         if (!sc->splitmic) {
 743                 /* TX and RX keys share the same key cache entry. */
 744                 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
 745                 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
 746                 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
 747         }
 748
 749         /* Separate key cache entries for TX and RX */
 750
 751         /* TX key goes at first index, RX key at +32. */
 752         memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
 753         if (!ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, NULL)) {
 754                 /* TX MIC entry failed. No need to proceed further */
 755                 DPRINTF(sc->sc_ah, ATH_DBG_FATAL,
 756                         "Setting TX MIC Key Failed\n");
 757                 return 0;
 758         }
 759
 760         memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
 761         /* XXX delete tx key on failure? */
 762         return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix + 32, hk, addr);
 763 }
 764
 765 static int ath_reserve_key_cache_slot_tkip(struct ath_softc *sc)
 766 {
 767         int i;
 768
 769         for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
 770                 if (test_bit(i, sc->keymap) ||
 771                     test_bit(i + 64, sc->keymap))
 772                         continue; /* At least one part of TKIP key allocated */
 773                 if (sc->splitmic &&
 774                     (test_bit(i + 32, sc->keymap) ||
 775                      test_bit(i + 64 + 32, sc->keymap)))
 776                         continue; /* At least one part of TKIP key allocated */
 777
 778                 /* Found a free slot for a TKIP key */
 779                 return i;
 780         }
 781         return -1;
 782 }
 783
 784 static int ath_reserve_key_cache_slot(struct ath_softc *sc)
 785 {
 786         int i;
 787
 788         /* First, try to find slots that would not be available for TKIP. */
 789         if (sc->splitmic) {
 790                 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 4; i++) {
 791                         if (!test_bit(i, sc->keymap) &&
 792                             (test_bit(i + 32, sc->keymap) ||
 793                              test_bit(i + 64, sc->keymap) ||
 794                              test_bit(i + 64 + 32, sc->keymap)))
 795                                 return i;
 796                         if (!test_bit(i + 32, sc->keymap) &&
 797                             (test_bit(i, sc->keymap) ||
 798                              test_bit(i + 64, sc->keymap) ||
 799                              test_bit(i + 64 + 32, sc->keymap)))
 800                                 return i + 32;
 801                         if (!test_bit(i + 64, sc->keymap) &&
 802                             (test_bit(i , sc->keymap) ||
 803                              test_bit(i + 32, sc->keymap) ||
 804                              test_bit(i + 64 + 32, sc->keymap)))
 805                                 return i + 64;
 806                         if (!test_bit(i + 64 + 32, sc->keymap) &&
 807                             (test_bit(i, sc->keymap) ||
 808                              test_bit(i + 32, sc->keymap) ||
 809                              test_bit(i + 64, sc->keymap)))
 810                                 return i + 64 + 32;
 811                 }
 812         } else {
 813                 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
 814                         if (!test_bit(i, sc->keymap) &&
 815                             test_bit(i + 64, sc->keymap))
 816                                 return i;
 817                         if (test_bit(i, sc->keymap) &&
 818                             !test_bit(i + 64, sc->keymap))
 819                                 return i + 64;
 820                 }
 821         }
 822
 823         /* No partially used TKIP slots, pick any available slot */
 824         for (i = IEEE80211_WEP_NKID; i < sc->keymax; i++) {
 825                 /* Do not allow slots that could be needed for TKIP group keys
 826                  * to be used. This limitation could be removed if we know that
 827                  * TKIP will not be used. */
 828                 if (i >= 64 && i < 64 + IEEE80211_WEP_NKID)
 829                         continue;
 830                 if (sc->splitmic) {
 831                         if (i >= 32 && i < 32 + IEEE80211_WEP_NKID)
 832                                 continue;
 833                         if (i >= 64 + 32 && i < 64 + 32 + IEEE80211_WEP_NKID)
 834                                 continue;
 835                 }
 836
 837                 if (!test_bit(i, sc->keymap))
 838                         return i; /* Found a free slot for a key */
 839         }
 840
 841         /* No free slot found */
 842         return -1;
 843 }
 844
 845 static int ath_key_config(struct ath_softc *sc,
 846                           struct ieee80211_vif *vif,
 847                           struct ieee80211_sta *sta,
 848                           struct ieee80211_key_conf *key)
 849 {
 850         struct ath9k_keyval hk;
 851         const u8 *mac = NULL;
 852         int ret = 0;
 853         int idx;
 854
 855         memset(&hk, 0, sizeof(hk));
 856
 857         switch (key->alg) {
 858         case ALG_WEP:
 859                 hk.kv_type = ATH9K_CIPHER_WEP;
 860                 break;
 861         case ALG_TKIP:
 862                 hk.kv_type = ATH9K_CIPHER_TKIP;
 863                 break;
 864         case ALG_CCMP:
 865                 hk.kv_type = ATH9K_CIPHER_AES_CCM;
 866                 break;
 867         default:
 868                 return -EOPNOTSUPP;
 869         }
 870
 871         hk.kv_len = key->keylen;
 872         memcpy(hk.kv_val, key->key, key->keylen);
 873
 874         if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
 875                 /* For now, use the default keys for broadcast keys. This may
 876                  * need to change with virtual interfaces. */
 877                 idx = key->keyidx;
 878         } else if (key->keyidx) {
 879                 if (WARN_ON(!sta))
 880                         return -EOPNOTSUPP;
 881                 mac = sta->addr;
 882
 883                 if (vif->type != NL80211_IFTYPE_AP) {
 884                         /* Only keyidx 0 should be used with unicast key, but
 885                          * allow this for client mode for now. */
 886                         idx = key->keyidx;
 887                 } else
 888                         return -EIO;
 889         } else {
 890                 if (WARN_ON(!sta))
 891                         return -EOPNOTSUPP;
 892                 mac = sta->addr;
 893
 894                 if (key->alg == ALG_TKIP)
 895                         idx = ath_reserve_key_cache_slot_tkip(sc);
 896                 else
 897                         idx = ath_reserve_key_cache_slot(sc);
 898                 if (idx < 0)
 899                         return -ENOSPC; /* no free key cache entries */
 900         }
 901
 902         if (key->alg == ALG_TKIP)
 903                 ret = ath_setkey_tkip(sc, idx, key->key, &hk, mac,
 904                                       vif->type == NL80211_IFTYPE_AP);
 905         else
 906                 ret = ath9k_hw_set_keycache_entry(sc->sc_ah, idx, &hk, mac);
 907
 908         if (!ret)
 909                 return -EIO;
 910
 911         set_bit(idx, sc->keymap);
 912         if (key->alg == ALG_TKIP) {
 913                 set_bit(idx + 64, sc->keymap);
 914                 if (sc->splitmic) {
 915                         set_bit(idx + 32, sc->keymap);
 916                         set_bit(idx + 64 + 32, sc->keymap);
 917                 }
 918         }
 919
 920         return idx;
 921 }
 922
 923 static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key)
 924 {
 925         ath9k_hw_keyreset(sc->sc_ah, key->hw_key_idx);
 926         if (key->hw_key_idx < IEEE80211_WEP_NKID)
 927                 return;
 928
 929         clear_bit(key->hw_key_idx, sc->keymap);
 930         if (key->alg != ALG_TKIP)
 931                 return;
 932
 933         clear_bit(key->hw_key_idx + 64, sc->keymap);
 934         if (sc->splitmic) {
 935                 clear_bit(key->hw_key_idx + 32, sc->keymap);
 936                 clear_bit(key->hw_key_idx + 64 + 32, sc->keymap);
 937         }
 938 }
 939
 940 static void setup_ht_cap(struct ath_softc *sc,
 941                          struct ieee80211_sta_ht_cap *ht_info)
 942 {
 943         u8 tx_streams, rx_streams;
 944
 945         ht_info->ht_supported = true;
 946         ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
 947                        IEEE80211_HT_CAP_SM_PS |
 948                        IEEE80211_HT_CAP_SGI_40 |
 949                        IEEE80211_HT_CAP_DSSSCCK40;
 950
 951         ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
 952         ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_8;
 953
 954         /* set up supported mcs set */
 955         memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
 956         tx_streams = !(sc->tx_chainmask & (sc->tx_chainmask - 1)) ? 1 : 2;
 957         rx_streams = !(sc->rx_chainmask & (sc->rx_chainmask - 1)) ? 1 : 2;
 958
 959         if (tx_streams != rx_streams) {
 960                 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "TX streams %d, RX streams: %d\n",
 961                         tx_streams, rx_streams);
 962                 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
 963                 ht_info->mcs.tx_params |= ((tx_streams - 1) <<
 964                                 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
 965         }
 966
 967         ht_info->mcs.rx_mask[0] = 0xff;
 968         if (rx_streams >= 2)
 969                 ht_info->mcs.rx_mask[1] = 0xff;
 970
 971         ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_DEFINED;
 972 }
 973
 974 static void ath9k_bss_assoc_info(struct ath_softc *sc,
 975                                  struct ieee80211_vif *vif,
 976                                  struct ieee80211_bss_conf *bss_conf)
 977 {
 978         struct ath_hw *ah = sc->sc_ah;
 979
 980         if (bss_conf->assoc) {
 981                 DPRINTF(ah, ATH_DBG_CONFIG, "Bss Info ASSOC %d, bssid: %pM\n",
 982                         bss_conf->aid, sc->curbssid);
 983
 984                 /* New association, store aid */
 985                 sc->curaid = bss_conf->aid;
 986                 ath9k_hw_write_associd(ah);
 987
 988                 /*
 989                  * Request a re-configuration of Beacon related timers
 990                  * on the receipt of the first Beacon frame (i.e.,
 991                  * after time sync with the AP).
 992                  */
 993                 sc->sc_flags |= SC_OP_BEACON_SYNC;
 994
 995                 /* Configure the beacon */
 996                 ath_beacon_config(sc, vif);
 997
 998                 /* Reset rssi stats */
 999                 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
1000
1001                 ath_start_ani(sc);
1002         } else {
1003                 DPRINTF(ah, ATH_DBG_CONFIG, "Bss Info DISASSOC\n");
1004                 sc->curaid = 0;
1005                 /* Stop ANI */
1006                 del_timer_sync(&sc->ani.timer);
1007         }
1008 }
1009
1010 /********************************/
1011 /*       LED functions          */
1012 /********************************/
1013
1014 static void ath_led_blink_work(struct work_struct *work)
1015 {
1016         struct ath_softc *sc = container_of(work, struct ath_softc,
1017                                             ath_led_blink_work.work);
1018
1019         if (!(sc->sc_flags & SC_OP_LED_ASSOCIATED))
1020                 return;
1021
1022         if ((sc->led_on_duration == ATH_LED_ON_DURATION_IDLE) ||
1023             (sc->led_off_duration == ATH_LED_OFF_DURATION_IDLE))
1024                 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 0);
1025         else
1026                 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin,
1027                                   (sc->sc_flags & SC_OP_LED_ON) ? 1 : 0);
1028
1029         ieee80211_queue_delayed_work(sc->hw,
1030                                      &sc->ath_led_blink_work,
1031                                      (sc->sc_flags & SC_OP_LED_ON) ?
1032                                         msecs_to_jiffies(sc->led_off_duration) :
1033                                         msecs_to_jiffies(sc->led_on_duration));
1034
1035         sc->led_on_duration = sc->led_on_cnt ?
1036                         max((ATH_LED_ON_DURATION_IDLE - sc->led_on_cnt), 25) :
1037                         ATH_LED_ON_DURATION_IDLE;
1038         sc->led_off_duration = sc->led_off_cnt ?
1039                         max((ATH_LED_OFF_DURATION_IDLE - sc->led_off_cnt), 10) :
1040                         ATH_LED_OFF_DURATION_IDLE;
1041         sc->led_on_cnt = sc->led_off_cnt = 0;
1042         if (sc->sc_flags & SC_OP_LED_ON)
1043                 sc->sc_flags &= ~SC_OP_LED_ON;
1044         else
1045                 sc->sc_flags |= SC_OP_LED_ON;
1046 }
1047
1048 static void ath_led_brightness(struct led_classdev *led_cdev,
1049                                enum led_brightness brightness)
1050 {
1051         struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
1052         struct ath_softc *sc = led->sc;
1053
1054         switch (brightness) {
1055         case LED_OFF:
1056                 if (led->led_type == ATH_LED_ASSOC ||
1057                     led->led_type == ATH_LED_RADIO) {
1058                         ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin,
1059                                 (led->led_type == ATH_LED_RADIO));
1060                         sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
1061                         if (led->led_type == ATH_LED_RADIO)
1062                                 sc->sc_flags &= ~SC_OP_LED_ON;
1063                 } else {
1064                         sc->led_off_cnt++;
1065                 }
1066                 break;
1067         case LED_FULL:
1068                 if (led->led_type == ATH_LED_ASSOC) {
1069                         sc->sc_flags |= SC_OP_LED_ASSOCIATED;
1070                         ieee80211_queue_delayed_work(sc->hw,
1071                                                      &sc->ath_led_blink_work, 0);
1072                 } else if (led->led_type == ATH_LED_RADIO) {
1073                         ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 0);
1074                         sc->sc_flags |= SC_OP_LED_ON;
1075                 } else {
1076                         sc->led_on_cnt++;
1077                 }
1078                 break;
1079         default:
1080                 break;
1081         }
1082 }
1083
1084 static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
1085                             char *trigger)
1086 {
1087         int ret;
1088
1089         led->sc = sc;
1090         led->led_cdev.name = led->name;
1091         led->led_cdev.default_trigger = trigger;
1092         led->led_cdev.brightness_set = ath_led_brightness;
1093
1094         ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
1095         if (ret)
1096                 DPRINTF(sc->sc_ah, ATH_DBG_FATAL,
1097                         "Failed to register led:%s", led->name);
1098         else
1099                 led->registered = 1;
1100         return ret;
1101 }
1102
1103 static void ath_unregister_led(struct ath_led *led)
1104 {
1105         if (led->registered) {
1106                 led_classdev_unregister(&led->led_cdev);
1107                 led->registered = 0;
1108         }
1109 }
1110
1111 static void ath_deinit_leds(struct ath_softc *sc)
1112 {
1113         ath_unregister_led(&sc->assoc_led);
1114         sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
1115         ath_unregister_led(&sc->tx_led);
1116         ath_unregister_led(&sc->rx_led);
1117         ath_unregister_led(&sc->radio_led);
1118         ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);
1119 }
1120
1121 static void ath_init_leds(struct ath_softc *sc)
1122 {
1123         char *trigger;
1124         int ret;
1125
1126         if (AR_SREV_9287(sc->sc_ah))
1127                 sc->sc_ah->led_pin = ATH_LED_PIN_9287;
1128         else
1129                 sc->sc_ah->led_pin = ATH_LED_PIN_DEF;
1130
1131         /* Configure gpio 1 for output */
1132         ath9k_hw_cfg_output(sc->sc_ah, sc->sc_ah->led_pin,
1133                             AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1134         /* LED off, active low */
1135         ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);
1136
1137         INIT_DELAYED_WORK(&sc->ath_led_blink_work, ath_led_blink_work);
1138
1139         trigger = ieee80211_get_radio_led_name(sc->hw);
1140         snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
1141                 "ath9k-%s::radio", wiphy_name(sc->hw->wiphy));
1142         ret = ath_register_led(sc, &sc->radio_led, trigger);
1143         sc->radio_led.led_type = ATH_LED_RADIO;
1144         if (ret)
1145                 goto fail;
1146
1147         trigger = ieee80211_get_assoc_led_name(sc->hw);
1148         snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
1149                 "ath9k-%s::assoc", wiphy_name(sc->hw->wiphy));
1150         ret = ath_register_led(sc, &sc->assoc_led, trigger);
1151         sc->assoc_led.led_type = ATH_LED_ASSOC;
1152         if (ret)
1153                 goto fail;
1154
1155         trigger = ieee80211_get_tx_led_name(sc->hw);
1156         snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
1157                 "ath9k-%s::tx", wiphy_name(sc->hw->wiphy));
1158         ret = ath_register_led(sc, &sc->tx_led, trigger);
1159         sc->tx_led.led_type = ATH_LED_TX;
1160         if (ret)
1161                 goto fail;
1162
1163         trigger = ieee80211_get_rx_led_name(sc->hw);
1164         snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
1165                 "ath9k-%s::rx", wiphy_name(sc->hw->wiphy));
1166         ret = ath_register_led(sc, &sc->rx_led, trigger);
1167         sc->rx_led.led_type = ATH_LED_RX;
1168         if (ret)
1169                 goto fail;
1170
1171         return;
1172
1173 fail:
1174         cancel_delayed_work_sync(&sc->ath_led_blink_work);
1175         ath_deinit_leds(sc);
1176 }
1177
1178 void ath_radio_enable(struct ath_softc *sc)
1179 {
1180         struct ath_hw *ah = sc->sc_ah;
1181         struct ieee80211_channel *channel = sc->hw->conf.channel;
1182         int r;
1183
1184         ath9k_ps_wakeup(sc);
1185         ath9k_hw_configpcipowersave(ah, 0, 0);
1186
1187         if (!ah->curchan)
1188                 ah->curchan = ath_get_curchannel(sc, sc->hw);
1189
1190         spin_lock_bh(&sc->sc_resetlock);
1191         r = ath9k_hw_reset(ah, ah->curchan, false);
1192         if (r) {
1193                 DPRINTF(sc->sc_ah, ATH_DBG_FATAL,
1194                         "Unable to reset channel %u (%uMhz) ",
1195                         "reset status %d\n",
1196                         channel->center_freq, r);
1197         }
1198         spin_unlock_bh(&sc->sc_resetlock);
1199
1200         ath_update_txpow(sc);
1201         if (ath_startrecv(sc) != 0) {
1202                 DPRINTF(sc->sc_ah, ATH_DBG_FATAL,
1203                         "Unable to restart recv logic\n");
1204                 return;
1205         }
1206
1207         if (sc->sc_flags & SC_OP_BEACONS)
1208                 ath_beacon_config(sc, NULL);    /* restart beacons */
1209
1210         /* Re-Enable  interrupts */
1211         ath9k_hw_set_interrupts(ah, sc->imask);
1212
1213         /* Enable LED */
1214         ath9k_hw_cfg_output(ah, ah->led_pin,
1215                             AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1216         ath9k_hw_set_gpio(ah, ah->led_pin, 0);
1217
1218         ieee80211_wake_queues(sc->hw);
1219         ath9k_ps_restore(sc);
1220 }
1221
1222 void ath_radio_disable(struct ath_softc *sc)
1223 {
1224         struct ath_hw *ah = sc->sc_ah;
1225         struct ieee80211_channel *channel = sc->hw->conf.channel;
1226         int r;
1227
1228         ath9k_ps_wakeup(sc);
1229         ieee80211_stop_queues(sc->hw);
1230
1231         /* Disable LED */
1232         ath9k_hw_set_gpio(ah, ah->led_pin, 1);
1233         ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
1234
1235         /* Disable interrupts */
1236         ath9k_hw_set_interrupts(ah, 0);
1237
1238         ath_drain_all_txq(sc, false);   /* clear pending tx frames */
1239         ath_stoprecv(sc);               /* turn off frame recv */
1240         ath_flushrecv(sc);              /* flush recv queue */
1241
1242         if (!ah->curchan)
1243                 ah->curchan = ath_get_curchannel(sc, sc->hw);
1244
1245         spin_lock_bh(&sc->sc_resetlock);
1246         r = ath9k_hw_reset(ah, ah->curchan, false);
1247         if (r) {
1248                 DPRINTF(sc->sc_ah, ATH_DBG_FATAL,
1249                         "Unable to reset channel %u (%uMhz) "
1250                         "reset status %d\n",
1251                         channel->center_freq, r);
1252         }
1253         spin_unlock_bh(&sc->sc_resetlock);
1254
1255         ath9k_hw_phy_disable(ah);
1256         ath9k_hw_configpcipowersave(ah, 1, 1);
1257         ath9k_ps_restore(sc);
1258         ath9k_setpower(sc, ATH9K_PM_FULL_SLEEP);
1259 }
1260
1261 /*******************/
1262 /*      Rfkill     */
1263 /*******************/
1264
1265 static bool ath_is_rfkill_set(struct ath_softc *sc)
1266 {
1267         struct ath_hw *ah = sc->sc_ah;
1268
1269         return ath9k_hw_gpio_get(ah, ah->rfkill_gpio) ==
1270                                   ah->rfkill_polarity;
1271 }
1272
1273 static void ath9k_rfkill_poll_state(struct ieee80211_hw *hw)
1274 {
1275         struct ath_wiphy *aphy = hw->priv;
1276         struct ath_softc *sc = aphy->sc;
1277         bool blocked = !!ath_is_rfkill_set(sc);
1278
1279         wiphy_rfkill_set_hw_state(hw->wiphy, blocked);
1280 }
1281
1282 static void ath_start_rfkill_poll(struct ath_softc *sc)
1283 {
1284         struct ath_hw *ah = sc->sc_ah;
1285
1286         if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1287                 wiphy_rfkill_start_polling(sc->hw->wiphy);
1288 }
1289
1290 void ath_cleanup(struct ath_softc *sc)
1291 {
1292         ath_detach(sc);
1293         free_irq(sc->irq, sc);
1294         ath_bus_cleanup(sc);
1295         kfree(sc->sec_wiphy);
1296         ieee80211_free_hw(sc->hw);
1297 }
1298
1299 void ath_detach(struct ath_softc *sc)
1300 {
1301         struct ieee80211_hw *hw = sc->hw;
1302         struct ath_hw *ah = sc->sc_ah;
1303         int i = 0;
1304
1305         ath9k_ps_wakeup(sc);
1306
1307         dev_dbg(sc->dev, "Detach ATH hw\n");
1308
1309         ath_deinit_leds(sc);
1310         wiphy_rfkill_stop_polling(sc->hw->wiphy);
1311
1312         for (i = 0; i < sc->num_sec_wiphy; i++) {
1313                 struct ath_wiphy *aphy = sc->sec_wiphy[i];
1314                 if (aphy == NULL)
1315                         continue;
1316                 sc->sec_wiphy[i] = NULL;
1317                 ieee80211_unregister_hw(aphy->hw);
1318                 ieee80211_free_hw(aphy->hw);
1319         }
1320         ieee80211_unregister_hw(hw);
1321         ath_rx_cleanup(sc);
1322         ath_tx_cleanup(sc);
1323
1324         tasklet_kill(&sc->intr_tq);
1325         tasklet_kill(&sc->bcon_tasklet);
1326
1327         if (!(sc->sc_flags & SC_OP_INVALID))
1328                 ath9k_setpower(sc, ATH9K_PM_AWAKE);
1329
1330         /* cleanup tx queues */
1331         for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1332                 if (ATH_TXQ_SETUP(sc, i))
1333                         ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1334
1335         if ((sc->btcoex.no_stomp_timer) &&
1336             ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
1337                 ath_gen_timer_free(ah, sc->btcoex.no_stomp_timer);
1338
1339         ath9k_hw_detach(ah);
1340         ath9k_exit_debug(ah);
1341         sc->sc_ah = NULL;
1342 }
1343
1344 static int ath9k_reg_notifier(struct wiphy *wiphy,
1345                               struct regulatory_request *request)
1346 {
1347         struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
1348         struct ath_wiphy *aphy = hw->priv;
1349         struct ath_softc *sc = aphy->sc;
1350         struct ath_regulatory *reg = &sc->common.regulatory;
1351
1352         return ath_reg_notifier_apply(wiphy, request, reg);
1353 }
1354
1355 /*
1356  * Detects if there is any priority bt traffic
1357  */
1358 static void ath_detect_bt_priority(struct ath_softc *sc)
1359 {
1360         struct ath_btcoex *btcoex = &sc->btcoex;
1361         struct ath_hw *ah = sc->sc_ah;
1362
1363         if (ath9k_hw_gpio_get(sc->sc_ah, ah->btcoex_hw.btpriority_gpio))
1364                 btcoex->bt_priority_cnt++;
1365
1366         if (time_after(jiffies, btcoex->bt_priority_time +
1367                         msecs_to_jiffies(ATH_BT_PRIORITY_TIME_THRESHOLD))) {
1368                 if (btcoex->bt_priority_cnt >= ATH_BT_CNT_THRESHOLD) {
1369                         DPRINTF(sc->sc_ah, ATH_DBG_BTCOEX,
1370                                 "BT priority traffic detected");
1371                         sc->sc_flags |= SC_OP_BT_PRIORITY_DETECTED;
1372                 } else {
1373                         sc->sc_flags &= ~SC_OP_BT_PRIORITY_DETECTED;
1374                 }
1375
1376                 btcoex->bt_priority_cnt = 0;
1377                 btcoex->bt_priority_time = jiffies;
1378         }
1379 }
1380
1381 /*
1382  * Configures appropriate weight based on stomp type.
1383  */
1384 static void ath9k_btcoex_bt_stomp(struct ath_softc *sc,
1385                                   enum ath_stomp_type stomp_type)
1386 {
1387         struct ath_hw *ah = sc->sc_ah;
1388
1389         switch (stomp_type) {
1390         case ATH_BTCOEX_STOMP_ALL:
1391                 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
1392                                            AR_STOMP_ALL_WLAN_WGHT);
1393                 break;
1394         case ATH_BTCOEX_STOMP_LOW:
1395                 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
1396                                            AR_STOMP_LOW_WLAN_WGHT);
1397                 break;
1398         case ATH_BTCOEX_STOMP_NONE:
1399                 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
1400                                            AR_STOMP_NONE_WLAN_WGHT);
1401                 break;
1402         default:
1403                 DPRINTF(ah, ATH_DBG_BTCOEX, "Invalid Stomptype\n");
1404                 break;
1405         }
1406
1407         ath9k_hw_btcoex_enable(ah);
1408 }
1409
1410 /*
1411  * This is the master bt coex timer which runs for every
1412  * 45ms, bt traffic will be given priority during 55% of this
1413  * period while wlan gets remaining 45%
1414  */
1415 static void ath_btcoex_period_timer(unsigned long data)
1416 {
1417         struct ath_softc *sc = (struct ath_softc *) data;
1418         struct ath_hw *ah = sc->sc_ah;
1419         struct ath_btcoex *btcoex = &sc->btcoex;
1420
1421         ath_detect_bt_priority(sc);
1422
1423         spin_lock_bh(&btcoex->btcoex_lock);
1424
1425         ath9k_btcoex_bt_stomp(sc, btcoex->bt_stomp_type);
1426
1427         spin_unlock_bh(&btcoex->btcoex_lock);
1428
1429         if (btcoex->btcoex_period != btcoex->btcoex_no_stomp) {
1430                 if (btcoex->hw_timer_enabled)
1431                         ath_gen_timer_stop(ah, btcoex->no_stomp_timer);
1432
1433                 ath_gen_timer_start(ah,
1434                         btcoex->no_stomp_timer,
1435                         (ath9k_hw_gettsf32(ah) +
1436                                 btcoex->btcoex_no_stomp),
1437                                 btcoex->btcoex_no_stomp * 10);
1438                 btcoex->hw_timer_enabled = true;
1439         }
1440
1441         mod_timer(&btcoex->period_timer, jiffies +
1442                                   msecs_to_jiffies(ATH_BTCOEX_DEF_BT_PERIOD));
1443 }
1444
1445 /*
1446  * Generic tsf based hw timer which configures weight
1447  * registers to time slice between wlan and bt traffic
1448  */
1449 static void ath_btcoex_no_stomp_timer(void *arg)
1450 {
1451         struct ath_softc *sc = (struct ath_softc *)arg;
1452         struct ath_hw *ah = sc->sc_ah;
1453         struct ath_btcoex *btcoex = &sc->btcoex;
1454
1455         DPRINTF(ah, ATH_DBG_BTCOEX, "no stomp timer running \n");
1456
1457         spin_lock_bh(&btcoex->btcoex_lock);
1458
1459         if (btcoex->bt_stomp_type == ATH_BTCOEX_STOMP_LOW)
1460                 ath9k_btcoex_bt_stomp(sc, ATH_BTCOEX_STOMP_NONE);
1461          else if (btcoex->bt_stomp_type == ATH_BTCOEX_STOMP_ALL)
1462                 ath9k_btcoex_bt_stomp(sc, ATH_BTCOEX_STOMP_LOW);
1463
1464         spin_unlock_bh(&btcoex->btcoex_lock);
1465 }
1466
1467 static int ath_init_btcoex_timer(struct ath_softc *sc)
1468 {
1469         struct ath_btcoex *btcoex = &sc->btcoex;
1470
1471         btcoex->btcoex_period = ATH_BTCOEX_DEF_BT_PERIOD * 1000;
1472         btcoex->btcoex_no_stomp = (100 - ATH_BTCOEX_DEF_DUTY_CYCLE) *
1473                 btcoex->btcoex_period / 100;
1474
1475         setup_timer(&btcoex->period_timer, ath_btcoex_period_timer,
1476                         (unsigned long) sc);
1477
1478         spin_lock_init(&btcoex->btcoex_lock);
1479
1480         btcoex->no_stomp_timer = ath_gen_timer_alloc(sc->sc_ah,
1481                         ath_btcoex_no_stomp_timer,
1482                         ath_btcoex_no_stomp_timer,
1483                         (void *) sc, AR_FIRST_NDP_TIMER);
1484
1485         if (!btcoex->no_stomp_timer)
1486                 return -ENOMEM;
1487
1488         return 0;
1489 }
1490
1491 /*
1492  * Initialize and fill ath_softc, ath_sofct is the
1493  * "Software Carrier" struct. Historically it has existed
1494  * to allow the separation between hardware specific
1495  * variables (now in ath_hw) and driver specific variables.
1496  */
1497 static int ath_init_softc(u16 devid, struct ath_softc *sc, u16 subsysid)
1498 {
1499         struct ath_hw *ah = NULL;
1500         int r = 0, i;
1501         int csz = 0;
1502         int qnum;
1503
1504         /* XXX: hardware will not be ready until ath_open() being called */
1505         sc->sc_flags |= SC_OP_INVALID;
1506
1507         spin_lock_init(&sc->wiphy_lock);
1508         spin_lock_init(&sc->sc_resetlock);
1509         spin_lock_init(&sc->sc_serial_rw);
1510         spin_lock_init(&sc->ani_lock);
1511         spin_lock_init(&sc->sc_pm_lock);
1512         mutex_init(&sc->mutex);
1513         tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
1514         tasklet_init(&sc->bcon_tasklet, ath_beacon_tasklet,
1515                      (unsigned long)sc);
1516
1517         /*
1518          * Cache line size is used to size and align various
1519          * structures used to communicate with the hardware.
1520          */
1521         ath_read_cachesize(sc, &csz);
1522         /* XXX assert csz is non-zero */
1523         sc->common.cachelsz = csz << 2; /* convert to bytes */
1524
1525         ah = kzalloc(sizeof(struct ath_hw), GFP_KERNEL);
1526         if (!ah) {
1527                 r = -ENOMEM;
1528                 goto bad_no_ah;
1529         }
1530
1531         ah->ah_sc = sc;
1532         ah->hw_version.devid = devid;
1533         ah->hw_version.subsysid = subsysid;
1534         sc->sc_ah = ah;
1535
1536         if (ath9k_init_debug(ah) < 0)
1537                 dev_err(sc->dev, "Unable to create debugfs files\n");
1538
1539         r = ath9k_hw_init(ah);
1540         if (r) {
1541                 DPRINTF(ah, ATH_DBG_FATAL,
1542                         "Unable to initialize hardware; "
1543                         "initialization status: %d\n", r);
1544                 goto bad;
1545         }
1546
1547         /* Get the hardware key cache size. */
1548         sc->keymax = ah->caps.keycache_size;
1549         if (sc->keymax > ATH_KEYMAX) {
1550                 DPRINTF(ah, ATH_DBG_ANY,
1551                         "Warning, using only %u entries in %u key cache\n",
1552                         ATH_KEYMAX, sc->keymax);
1553                 sc->keymax = ATH_KEYMAX;
1554         }
1555
1556         /*
1557          * Reset the key cache since some parts do not
1558          * reset the contents on initial power up.
1559          */
1560         for (i = 0; i < sc->keymax; i++)
1561                 ath9k_hw_keyreset(ah, (u16) i);
1562
1563         /* default to MONITOR mode */
1564         sc->sc_ah->opmode = NL80211_IFTYPE_MONITOR;
1565
1566         /* Setup rate tables */
1567
1568         ath_rate_attach(sc);
1569         ath_setup_rates(sc, IEEE80211_BAND_2GHZ);
1570         ath_setup_rates(sc, IEEE80211_BAND_5GHZ);
1571
1572         /*
1573          * Allocate hardware transmit queues: one queue for
1574          * beacon frames and one data queue for each QoS
1575          * priority.  Note that the hal handles reseting
1576          * these queues at the needed time.
1577          */
1578         sc->beacon.beaconq = ath_beaconq_setup(ah);
1579         if (sc->beacon.beaconq == -1) {
1580                 DPRINTF(ah, ATH_DBG_FATAL,
1581                         "Unable to setup a beacon xmit queue\n");
1582                 r = -EIO;
1583                 goto bad2;
1584         }
1585         sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
1586         if (sc->beacon.cabq == NULL) {
1587                 DPRINTF(ah, ATH_DBG_FATAL,
1588                         "Unable to setup CAB xmit queue\n");
1589                 r = -EIO;
1590                 goto bad2;
1591         }
1592
1593         sc->config.cabqReadytime = ATH_CABQ_READY_TIME;
1594         ath_cabq_update(sc);
1595
1596         for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++)
1597                 sc->tx.hwq_map[i] = -1;
1598
1599         /* Setup data queues */
1600         /* NB: ensure BK queue is the lowest priority h/w queue */
1601         if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
1602                 DPRINTF(ah, ATH_DBG_FATAL,
1603                         "Unable to setup xmit queue for BK traffic\n");
1604                 r = -EIO;
1605                 goto bad2;
1606         }
1607
1608         if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
1609                 DPRINTF(ah, ATH_DBG_FATAL,
1610                         "Unable to setup xmit queue for BE traffic\n");
1611                 r = -EIO;
1612                 goto bad2;
1613         }
1614         if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
1615                 DPRINTF(ah, ATH_DBG_FATAL,
1616                         "Unable to setup xmit queue for VI traffic\n");
1617                 r = -EIO;
1618                 goto bad2;
1619         }
1620         if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
1621                 DPRINTF(ah, ATH_DBG_FATAL,
1622                         "Unable to setup xmit queue for VO traffic\n");
1623                 r = -EIO;
1624                 goto bad2;
1625         }
1626
1627         /* Initializes the noise floor to a reasonable default value.
1628          * Later on this will be updated during ANI processing. */
1629
1630         sc->ani.noise_floor = ATH_DEFAULT_NOISE_FLOOR;
1631         setup_timer(&sc->ani.timer, ath_ani_calibrate, (unsigned long)sc);
1632
1633         if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1634                                    ATH9K_CIPHER_TKIP, NULL)) {
1635                 /*
1636                  * Whether we should enable h/w TKIP MIC.
1637                  * XXX: if we don't support WME TKIP MIC, then we wouldn't
1638                  * report WMM capable, so it's always safe to turn on
1639                  * TKIP MIC in this case.
1640                  */
1641                 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC,
1642                                        0, 1, NULL);
1643         }
1644
1645         /*
1646          * Check whether the separate key cache entries
1647          * are required to handle both tx+rx MIC keys.
1648          * With split mic keys the number of stations is limited
1649          * to 27 otherwise 59.
1650          */
1651         if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1652                                    ATH9K_CIPHER_TKIP, NULL)
1653             && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1654                                       ATH9K_CIPHER_MIC, NULL)
1655             && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT,
1656                                       0, NULL))
1657                 sc->splitmic = 1;
1658
1659         /* turn on mcast key search if possible */
1660         if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
1661                 (void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1,
1662                                              1, NULL);
1663
1664         sc->config.txpowlimit = ATH_TXPOWER_MAX;
1665
1666         /* 11n Capabilities */
1667         if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
1668                 sc->sc_flags |= SC_OP_TXAGGR;
1669                 sc->sc_flags |= SC_OP_RXAGGR;
1670         }
1671
1672         sc->tx_chainmask = ah->caps.tx_chainmask;
1673         sc->rx_chainmask = ah->caps.rx_chainmask;
1674
1675         ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
1676         sc->rx.defant = ath9k_hw_getdefantenna(ah);
1677
1678         if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
1679                 memcpy(sc->bssidmask, ath_bcast_mac, ETH_ALEN);
1680
1681         sc->beacon.slottime = ATH9K_SLOT_TIME_9;        /* default to short slot time */
1682
1683         /* initialize beacon slots */
1684         for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
1685                 sc->beacon.bslot[i] = NULL;
1686                 sc->beacon.bslot_aphy[i] = NULL;
1687         }
1688
1689         /* setup channels and rates */
1690
1691         sc->sbands[IEEE80211_BAND_2GHZ].channels = ath9k_2ghz_chantable;
1692         sc->sbands[IEEE80211_BAND_2GHZ].bitrates =
1693                 sc->rates[IEEE80211_BAND_2GHZ];
1694         sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
1695         sc->sbands[IEEE80211_BAND_2GHZ].n_channels =
1696                 ARRAY_SIZE(ath9k_2ghz_chantable);
1697
1698         if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes)) {
1699                 sc->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_chantable;
1700                 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
1701                         sc->rates[IEEE80211_BAND_5GHZ];
1702                 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
1703                 sc->sbands[IEEE80211_BAND_5GHZ].n_channels =
1704                         ARRAY_SIZE(ath9k_5ghz_chantable);
1705         }
1706
1707         switch (ah->btcoex_hw.scheme) {
1708         case ATH_BTCOEX_CFG_NONE:
1709                 break;
1710         case ATH_BTCOEX_CFG_2WIRE:
1711                 ath9k_hw_btcoex_init_2wire(ah);
1712                 break;
1713         case ATH_BTCOEX_CFG_3WIRE:
1714                 ath9k_hw_btcoex_init_3wire(ah);
1715                 r = ath_init_btcoex_timer(sc);
1716                 if (r)
1717                         goto bad2;
1718                 qnum = ath_tx_get_qnum(sc, ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BE);
1719                 ath9k_hw_init_btcoex_hw(ah, qnum);
1720                 sc->btcoex.bt_stomp_type = ATH_BTCOEX_STOMP_LOW;
1721                 break;
1722         default:
1723                 WARN_ON(1);
1724                 break;
1725         }
1726
1727         return 0;
1728 bad2:
1729         /* cleanup tx queues */
1730         for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1731                 if (ATH_TXQ_SETUP(sc, i))
1732                         ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1733 bad:
1734         ath9k_hw_detach(ah);
1735 bad_no_ah:
1736         ath9k_exit_debug(sc->sc_ah);
1737         sc->sc_ah = NULL;
1738
1739         return r;
1740 }
1741
1742 void ath_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
1743 {
1744         hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
1745                 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1746                 IEEE80211_HW_SIGNAL_DBM |
1747                 IEEE80211_HW_AMPDU_AGGREGATION |
1748                 IEEE80211_HW_SUPPORTS_PS |
1749                 IEEE80211_HW_PS_NULLFUNC_STACK |
1750                 IEEE80211_HW_SPECTRUM_MGMT;
1751
1752         if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || modparam_nohwcrypt)
1753                 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
1754
1755         hw->wiphy->interface_modes =
1756                 BIT(NL80211_IFTYPE_AP) |
1757                 BIT(NL80211_IFTYPE_STATION) |
1758                 BIT(NL80211_IFTYPE_ADHOC) |
1759                 BIT(NL80211_IFTYPE_MESH_POINT);
1760
1761         hw->queues = 4;
1762         hw->max_rates = 4;
1763         hw->channel_change_time = 5000;
1764         hw->max_listen_interval = 10;
1765         /* Hardware supports 10 but we use 4 */
1766         hw->max_rate_tries = 4;
1767         hw->sta_data_size = sizeof(struct ath_node);
1768         hw->vif_data_size = sizeof(struct ath_vif);
1769
1770         hw->rate_control_algorithm = "ath9k_rate_control";
1771
1772         hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
1773                 &sc->sbands[IEEE80211_BAND_2GHZ];
1774         if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
1775                 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
1776                         &sc->sbands[IEEE80211_BAND_5GHZ];
1777 }
1778
1779 /* Device driver core initialization */
1780 int ath_init_device(u16 devid, struct ath_softc *sc, u16 subsysid)
1781 {
1782         struct ieee80211_hw *hw = sc->hw;
1783         struct ath_hw *ah;
1784         int error = 0, i;
1785         struct ath_regulatory *reg;
1786
1787         dev_dbg(sc->dev, "Attach ATH hw\n");
1788
1789         error = ath_init_softc(devid, sc, subsysid);
1790         if (error != 0)
1791                 return error;
1792
1793         ah = sc->sc_ah;
1794
1795         /* get mac address from hardware and set in mac80211 */
1796
1797         SET_IEEE80211_PERM_ADDR(hw, ah->macaddr);
1798
1799         ath_set_hw_capab(sc, hw);
1800
1801         error = ath_regd_init(&sc->common.regulatory, sc->hw->wiphy,
1802                               ath9k_reg_notifier);
1803         if (error)
1804                 return error;
1805
1806         reg = &sc->common.regulatory;
1807
1808         if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
1809                 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
1810                 if (test_bit(ATH9K_MODE_11A, ah->caps.wireless_modes))
1811                         setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
1812         }
1813
1814         /* initialize tx/rx engine */
1815         error = ath_tx_init(sc, ATH_TXBUF);
1816         if (error != 0)
1817                 goto error_attach;
1818
1819         error = ath_rx_init(sc, ATH_RXBUF);
1820         if (error != 0)
1821                 goto error_attach;
1822
1823         INIT_WORK(&sc->chan_work, ath9k_wiphy_chan_work);
1824         INIT_DELAYED_WORK(&sc->wiphy_work, ath9k_wiphy_work);
1825         sc->wiphy_scheduler_int = msecs_to_jiffies(500);
1826
1827         error = ieee80211_register_hw(hw);
1828
1829         if (!ath_is_world_regd(reg)) {
1830                 error = regulatory_hint(hw->wiphy, reg->alpha2);
1831                 if (error)
1832                         goto error_attach;
1833         }
1834
1835         /* Initialize LED control */
1836         ath_init_leds(sc);
1837
1838         ath_start_rfkill_poll(sc);
1839
1840         return 0;
1841
1842 error_attach:
1843         /* cleanup tx queues */
1844         for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1845                 if (ATH_TXQ_SETUP(sc, i))
1846                         ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1847
1848         ath9k_hw_detach(ah);
1849         ath9k_exit_debug(ah);
1850         sc->sc_ah = NULL;
1851
1852         return error;
1853 }
1854
1855 int ath_reset(struct ath_softc *sc, bool retry_tx)
1856 {
1857         struct ath_hw *ah = sc->sc_ah;
1858         struct ieee80211_hw *hw = sc->hw;
1859         int r;
1860
1861         ath9k_hw_set_interrupts(ah, 0);
1862         ath_drain_all_txq(sc, retry_tx);
1863         ath_stoprecv(sc);
1864         ath_flushrecv(sc);
1865
1866         spin_lock_bh(&sc->sc_resetlock);
1867         r = ath9k_hw_reset(ah, sc->sc_ah->curchan, false);
1868         if (r)
1869                 DPRINTF(ah, ATH_DBG_FATAL,
1870                         "Unable to reset hardware; reset status %d\n", r);
1871         spin_unlock_bh(&sc->sc_resetlock);
1872
1873         if (ath_startrecv(sc) != 0)
1874                 DPRINTF(ah, ATH_DBG_FATAL, "Unable to start recv logic\n");
1875
1876         /*
1877          * We may be doing a reset in response to a request
1878          * that changes the channel so update any state that
1879          * might change as a result.
1880          */
1881         ath_cache_conf_rate(sc, &hw->conf);
1882
1883         ath_update_txpow(sc);
1884
1885         if (sc->sc_flags & SC_OP_BEACONS)
1886                 ath_beacon_config(sc, NULL);    /* restart beacons */
1887
1888         ath9k_hw_set_interrupts(ah, sc->imask);
1889
1890         if (retry_tx) {
1891                 int i;
1892                 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1893                         if (ATH_TXQ_SETUP(sc, i)) {
1894                                 spin_lock_bh(&sc->tx.txq[i].axq_lock);
1895                                 ath_txq_schedule(sc, &sc->tx.txq[i]);
1896                                 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
1897                         }
1898                 }
1899         }
1900
1901         return r;
1902 }
1903
1904 /*
1905  *  This function will allocate both the DMA descriptor structure, and the
1906  *  buffers it contains.  These are used to contain the descriptors used
1907  *  by the system.
1908 */
1909 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
1910                       struct list_head *head, const char *name,
1911                       int nbuf, int ndesc)
1912 {
1913 #define DS2PHYS(_dd, _ds)                                               \
1914         ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
1915 #define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
1916 #define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
1917
1918         struct ath_desc *ds;
1919         struct ath_buf *bf;
1920         int i, bsize, error;
1921
1922         DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
1923                 name, nbuf, ndesc);
1924
1925         INIT_LIST_HEAD(head);
1926         /* ath_desc must be a multiple of DWORDs */
1927         if ((sizeof(struct ath_desc) % 4) != 0) {
1928                 DPRINTF(sc->sc_ah, ATH_DBG_FATAL, "ath_desc not DWORD aligned\n");
1929                 ASSERT((sizeof(struct ath_desc) % 4) == 0);
1930                 error = -ENOMEM;
1931                 goto fail;
1932         }
1933
1934         dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
1935
1936         /*
1937          * Need additional DMA memory because we can't use
1938          * descriptors that cross the 4K page boundary. Assume
1939          * one skipped descriptor per 4K page.
1940          */
1941         if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1942                 u32 ndesc_skipped =
1943                         ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
1944                 u32 dma_len;
1945
1946                 while (ndesc_skipped) {
1947                         dma_len = ndesc_skipped * sizeof(struct ath_desc);
1948                         dd->dd_desc_len += dma_len;
1949
1950                         ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
1951                 };
1952         }
1953
1954         /* allocate descriptors */
1955         dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
1956                                          &dd->dd_desc_paddr, GFP_KERNEL);
1957         if (dd->dd_desc == NULL) {
1958                 error = -ENOMEM;
1959                 goto fail;
1960         }
1961         ds = dd->dd_desc;
1962         DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
1963                 name, ds, (u32) dd->dd_desc_len,
1964                 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
1965
1966         /* allocate buffers */
1967         bsize = sizeof(struct ath_buf) * nbuf;
1968         bf = kzalloc(bsize, GFP_KERNEL);
1969         if (bf == NULL) {
1970                 error = -ENOMEM;
1971                 goto fail2;
1972         }
1973         dd->dd_bufptr = bf;
1974
1975         for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
1976                 bf->bf_desc = ds;
1977                 bf->bf_daddr = DS2PHYS(dd, ds);
1978
1979                 if (!(sc->sc_ah->caps.hw_caps &
1980                       ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1981                         /*
1982                          * Skip descriptor addresses which can cause 4KB
1983                          * boundary crossing (addr + length) with a 32 dword
1984                          * descriptor fetch.
1985                          */
1986                         while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
1987                                 ASSERT((caddr_t) bf->bf_desc <
1988                                        ((caddr_t) dd->dd_desc +
1989                                         dd->dd_desc_len));
1990
1991                                 ds += ndesc;
1992                                 bf->bf_desc = ds;
1993                                 bf->bf_daddr = DS2PHYS(dd, ds);
1994                         }
1995                 }
1996                 list_add_tail(&bf->list, head);
1997         }
1998         return 0;
1999 fail2:
2000         dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
2001                           dd->dd_desc_paddr);
2002 fail:
2003         memset(dd, 0, sizeof(*dd));
2004         return error;
2005 #undef ATH_DESC_4KB_BOUND_CHECK
2006 #undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
2007 #undef DS2PHYS
2008 }
2009
2010 void ath_descdma_cleanup(struct ath_softc *sc,
2011                          struct ath_descdma *dd,
2012                          struct list_head *head)
2013 {
2014         dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
2015                           dd->dd_desc_paddr);
2016
2017         INIT_LIST_HEAD(head);
2018         kfree(dd->dd_bufptr);
2019         memset(dd, 0, sizeof(*dd));
2020 }
2021
2022 int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
2023 {
2024         int qnum;
2025
2026         switch (queue) {
2027         case 0:
2028                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VO];
2029                 break;
2030         case 1:
2031                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VI];
2032                 break;
2033         case 2:
2034                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
2035                 break;
2036         case 3:
2037                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BK];
2038                 break;
2039         default:
2040                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
2041                 break;
2042         }
2043
2044         return qnum;
2045 }
2046
2047 int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
2048 {
2049         int qnum;
2050
2051         switch (queue) {
2052         case ATH9K_WME_AC_VO:
2053                 qnum = 0;
2054                 break;
2055         case ATH9K_WME_AC_VI:
2056                 qnum = 1;
2057                 break;
2058         case ATH9K_WME_AC_BE:
2059                 qnum = 2;
2060                 break;
2061         case ATH9K_WME_AC_BK:
2062                 qnum = 3;
2063                 break;
2064         default:
2065                 qnum = -1;
2066                 break;
2067         }
2068
2069         return qnum;
2070 }
2071
2072 /* XXX: Remove me once we don't depend on ath9k_channel for all
2073  * this redundant data */
2074 void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw,
2075                            struct ath9k_channel *ichan)
2076 {
2077         struct ieee80211_channel *chan = hw->conf.channel;
2078         struct ieee80211_conf *conf = &hw->conf;
2079
2080         ichan->channel = chan->center_freq;
2081         ichan->chan = chan;
2082
2083         if (chan->band == IEEE80211_BAND_2GHZ) {
2084                 ichan->chanmode = CHANNEL_G;
2085                 ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM | CHANNEL_G;
2086         } else {
2087                 ichan->chanmode = CHANNEL_A;
2088                 ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM;
2089         }
2090
2091         sc->tx_chan_width = ATH9K_HT_MACMODE_20;
2092
2093         if (conf_is_ht(conf)) {
2094                 if (conf_is_ht40(conf))
2095                         sc->tx_chan_width = ATH9K_HT_MACMODE_2040;
2096
2097                 ichan->chanmode = ath_get_extchanmode(sc, chan,
2098                                             conf->channel_type);
2099         }
2100 }
2101
2102 /**********************/
2103 /* mac80211 callbacks */
2104 /**********************/
2105
2106 /*
2107  * (Re)start btcoex timers
2108  */
2109 static void ath9k_btcoex_timer_resume(struct ath_softc *sc)
2110 {
2111         struct ath_btcoex *btcoex = &sc->btcoex;
2112         struct ath_hw *ah = sc->sc_ah;
2113
2114         DPRINTF(ah, ATH_DBG_BTCOEX, "Starting btcoex timers");
2115
2116         /* make sure duty cycle timer is also stopped when resuming */
2117         if (btcoex->hw_timer_enabled)
2118                 ath_gen_timer_stop(sc->sc_ah, btcoex->no_stomp_timer);
2119
2120         btcoex->bt_priority_cnt = 0;
2121         btcoex->bt_priority_time = jiffies;
2122         sc->sc_flags &= ~SC_OP_BT_PRIORITY_DETECTED;
2123
2124         mod_timer(&btcoex->period_timer, jiffies);
2125 }
2126
2127 static int ath9k_start(struct ieee80211_hw *hw)
2128 {
2129         struct ath_wiphy *aphy = hw->priv;
2130         struct ath_softc *sc = aphy->sc;
2131         struct ath_hw *ah = sc->sc_ah;
2132         struct ieee80211_channel *curchan = hw->conf.channel;
2133         struct ath9k_channel *init_channel;
2134         int r;
2135
2136         DPRINTF(ah, ATH_DBG_CONFIG, "Starting driver with "
2137                 "initial channel: %d MHz\n", curchan->center_freq);
2138
2139         mutex_lock(&sc->mutex);
2140
2141         if (ath9k_wiphy_started(sc)) {
2142                 if (sc->chan_idx == curchan->hw_value) {
2143                         /*
2144                          * Already on the operational channel, the new wiphy
2145                          * can be marked active.
2146                          */
2147                         aphy->state = ATH_WIPHY_ACTIVE;
2148                         ieee80211_wake_queues(hw);
2149                 } else {
2150                         /*
2151                          * Another wiphy is on another channel, start the new
2152                          * wiphy in paused state.
2153                          */
2154                         aphy->state = ATH_WIPHY_PAUSED;
2155                         ieee80211_stop_queues(hw);
2156                 }
2157                 mutex_unlock(&sc->mutex);
2158                 return 0;
2159         }
2160         aphy->state = ATH_WIPHY_ACTIVE;
2161
2162         /* setup initial channel */
2163
2164         sc->chan_idx = curchan->hw_value;
2165
2166         init_channel = ath_get_curchannel(sc, hw);
2167
2168         /* Reset SERDES registers */
2169         ath9k_hw_configpcipowersave(ah, 0, 0);
2170
2171         /*
2172          * The basic interface to setting the hardware in a good
2173          * state is ``reset''.  On return the hardware is known to
2174          * be powered up and with interrupts disabled.  This must
2175          * be followed by initialization of the appropriate bits
2176          * and then setup of the interrupt mask.
2177          */
2178         spin_lock_bh(&sc->sc_resetlock);
2179         r = ath9k_hw_reset(ah, init_channel, false);
2180         if (r) {
2181                 DPRINTF(ah, ATH_DBG_FATAL,
2182                         "Unable to reset hardware; reset status %d "
2183                         "(freq %u MHz)\n", r,
2184                         curchan->center_freq);
2185                 spin_unlock_bh(&sc->sc_resetlock);
2186                 goto mutex_unlock;
2187         }
2188         spin_unlock_bh(&sc->sc_resetlock);
2189
2190         /*
2191          * This is needed only to setup initial state
2192          * but it's best done after a reset.
2193          */
2194         ath_update_txpow(sc);
2195
2196         /*
2197          * Setup the hardware after reset:
2198          * The receive engine is set going.
2199          * Frame transmit is handled entirely
2200          * in the frame output path; there's nothing to do
2201          * here except setup the interrupt mask.
2202          */
2203         if (ath_startrecv(sc) != 0) {
2204                 DPRINTF(ah, ATH_DBG_FATAL, "Unable to start recv logic\n");
2205                 r = -EIO;
2206                 goto mutex_unlock;
2207         }
2208
2209         /* Setup our intr mask. */
2210         sc->imask = ATH9K_INT_RX | ATH9K_INT_TX
2211                 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
2212                 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
2213
2214         if (ah->caps.hw_caps & ATH9K_HW_CAP_GTT)
2215                 sc->imask |= ATH9K_INT_GTT;
2216
2217         if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
2218                 sc->imask |= ATH9K_INT_CST;
2219
2220         ath_cache_conf_rate(sc, &hw->conf);
2221
2222         sc->sc_flags &= ~SC_OP_INVALID;
2223
2224         /* Disable BMISS interrupt when we're not associated */
2225         sc->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
2226         ath9k_hw_set_interrupts(ah, sc->imask);
2227
2228         ieee80211_wake_queues(hw);
2229
2230         ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
2231
2232         if ((ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE) &&
2233             !ah->btcoex_hw.enabled) {
2234                 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
2235                                            AR_STOMP_LOW_WLAN_WGHT);
2236                 ath9k_hw_btcoex_enable(ah);
2237
2238                 ath_pcie_aspm_disable(sc);
2239                 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
2240                         ath9k_btcoex_timer_resume(sc);
2241         }
2242
2243 mutex_unlock:
2244         mutex_unlock(&sc->mutex);
2245
2246         return r;
2247 }
2248
2249 static int ath9k_tx(struct ieee80211_hw *hw,
2250                     struct sk_buff *skb)
2251 {
2252         struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2253         struct ath_wiphy *aphy = hw->priv;
2254         struct ath_softc *sc = aphy->sc;
2255         struct ath_tx_control txctl;
2256         int hdrlen, padsize;
2257
2258         if (aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN) {
2259                 printk(KERN_DEBUG "ath9k: %s: TX in unexpected wiphy state "
2260                        "%d\n", wiphy_name(hw->wiphy), aphy->state);
2261                 goto exit;
2262         }
2263
2264         if (sc->ps_enabled) {
2265                 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2266                 /*
2267                  * mac80211 does not set PM field for normal data frames, so we
2268                  * need to update that based on the current PS mode.
2269                  */
2270                 if (ieee80211_is_data(hdr->frame_control) &&
2271                     !ieee80211_is_nullfunc(hdr->frame_control) &&
2272                     !ieee80211_has_pm(hdr->frame_control)) {
2273                         DPRINTF(sc->sc_ah, ATH_DBG_PS, "Add PM=1 for a TX frame "
2274                                 "while in PS mode\n");
2275                         hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
2276                 }
2277         }
2278
2279         if (unlikely(sc->sc_ah->power_mode != ATH9K_PM_AWAKE)) {
2280                 /*
2281                  * We are using PS-Poll and mac80211 can request TX while in
2282                  * power save mode. Need to wake up hardware for the TX to be
2283                  * completed and if needed, also for RX of buffered frames.
2284                  */
2285                 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2286                 ath9k_ps_wakeup(sc);
2287                 ath9k_hw_setrxabort(sc->sc_ah, 0);
2288                 if (ieee80211_is_pspoll(hdr->frame_control)) {
2289                         DPRINTF(sc->sc_ah, ATH_DBG_PS, "Sending PS-Poll to pick a "
2290                                 "buffered frame\n");
2291                         sc->sc_flags |= SC_OP_WAIT_FOR_PSPOLL_DATA;
2292                 } else {
2293                         DPRINTF(sc->sc_ah, ATH_DBG_PS, "Wake up to complete TX\n");
2294                         sc->sc_flags |= SC_OP_WAIT_FOR_TX_ACK;
2295                 }
2296                 /*
2297                  * The actual restore operation will happen only after
2298                  * the sc_flags bit is cleared. We are just dropping
2299                  * the ps_usecount here.
2300                  */
2301                 ath9k_ps_restore(sc);
2302         }
2303
2304         memset(&txctl, 0, sizeof(struct ath_tx_control));
2305
2306         /*
2307          * As a temporary workaround, assign seq# here; this will likely need
2308          * to be cleaned up to work better with Beacon transmission and virtual
2309          * BSSes.
2310          */
2311         if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
2312                 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2313                 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
2314                         sc->tx.seq_no += 0x10;
2315                 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
2316                 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
2317         }
2318
2319         /* Add the padding after the header if this is not already done */
2320         hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2321         if (hdrlen & 3) {
2322                 padsize = hdrlen % 4;
2323                 if (skb_headroom(skb) < padsize)
2324                         return -1;
2325                 skb_push(skb, padsize);
2326                 memmove(skb->data, skb->data + padsize, hdrlen);
2327         }
2328
2329         /* Check if a tx queue is available */
2330
2331         txctl.txq = ath_test_get_txq(sc, skb);
2332         if (!txctl.txq)
2333                 goto exit;
2334
2335         DPRINTF(sc->sc_ah, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
2336
2337         if (ath_tx_start(hw, skb, &txctl) != 0) {
2338                 DPRINTF(sc->sc_ah, ATH_DBG_XMIT, "TX failed\n");
2339                 goto exit;
2340         }
2341
2342         return 0;
2343 exit:
2344         dev_kfree_skb_any(skb);
2345         return 0;
2346 }
2347
2348 /*
2349  * Pause btcoex timer and bt duty cycle timer
2350  */
2351 static void ath9k_btcoex_timer_pause(struct ath_softc *sc)
2352 {
2353         struct ath_btcoex *btcoex = &sc->btcoex;
2354         struct ath_hw *ah = sc->sc_ah;
2355
2356         del_timer_sync(&btcoex->period_timer);
2357
2358         if (btcoex->hw_timer_enabled)
2359                 ath_gen_timer_stop(ah, btcoex->no_stomp_timer);
2360
2361         btcoex->hw_timer_enabled = false;
2362 }
2363
2364 static void ath9k_stop(struct ieee80211_hw *hw)
2365 {
2366         struct ath_wiphy *aphy = hw->priv;
2367         struct ath_softc *sc = aphy->sc;
2368         struct ath_hw *ah = sc->sc_ah;
2369
2370         mutex_lock(&sc->mutex);
2371
2372         aphy->state = ATH_WIPHY_INACTIVE;
2373
2374         cancel_delayed_work_sync(&sc->ath_led_blink_work);
2375         cancel_delayed_work_sync(&sc->tx_complete_work);
2376
2377         if (!sc->num_sec_wiphy) {
2378                 cancel_delayed_work_sync(&sc->wiphy_work);
2379                 cancel_work_sync(&sc->chan_work);
2380         }
2381
2382         if (sc->sc_flags & SC_OP_INVALID) {
2383                 DPRINTF(ah, ATH_DBG_ANY, "Device not present\n");
2384                 mutex_unlock(&sc->mutex);
2385                 return;
2386         }
2387
2388         if (ath9k_wiphy_started(sc)) {
2389                 mutex_unlock(&sc->mutex);
2390                 return; /* another wiphy still in use */
2391         }
2392
2393         if (ah->btcoex_hw.enabled) {
2394                 ath9k_hw_btcoex_disable(ah);
2395                 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
2396                         ath9k_btcoex_timer_pause(sc);
2397         }
2398
2399         /* make sure h/w will not generate any interrupt
2400          * before setting the invalid flag. */
2401         ath9k_hw_set_interrupts(ah, 0);
2402
2403         if (!(sc->sc_flags & SC_OP_INVALID)) {
2404                 ath_drain_all_txq(sc, false);
2405                 ath_stoprecv(sc);
2406                 ath9k_hw_phy_disable(ah);
2407         } else
2408                 sc->rx.rxlink = NULL;
2409
2410         /* disable HAL and put h/w to sleep */
2411         ath9k_hw_disable(ah);
2412         ath9k_hw_configpcipowersave(ah, 1, 1);
2413         ath9k_setpower(sc, ATH9K_PM_FULL_SLEEP);
2414
2415         sc->sc_flags |= SC_OP_INVALID;
2416
2417         mutex_unlock(&sc->mutex);
2418
2419         DPRINTF(ah, ATH_DBG_CONFIG, "Driver halt\n");
2420 }
2421
2422 static int ath9k_add_interface(struct ieee80211_hw *hw,
2423                                struct ieee80211_if_init_conf *conf)
2424 {
2425         struct ath_wiphy *aphy = hw->priv;
2426         struct ath_softc *sc = aphy->sc;
2427         struct ath_vif *avp = (void *)conf->vif->drv_priv;
2428         enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
2429         int ret = 0;
2430
2431         mutex_lock(&sc->mutex);
2432
2433         if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) &&
2434             sc->nvifs > 0) {
2435                 ret = -ENOBUFS;
2436                 goto out;
2437         }
2438
2439         switch (conf->type) {
2440         case NL80211_IFTYPE_STATION:
2441                 ic_opmode = NL80211_IFTYPE_STATION;
2442                 break;
2443         case NL80211_IFTYPE_ADHOC:
2444         case NL80211_IFTYPE_AP:
2445         case NL80211_IFTYPE_MESH_POINT:
2446                 if (sc->nbcnvifs >= ATH_BCBUF) {
2447                         ret = -ENOBUFS;
2448                         goto out;
2449                 }
2450                 ic_opmode = conf->type;
2451                 break;
2452         default:
2453                 DPRINTF(sc->sc_ah, ATH_DBG_FATAL,
2454                         "Interface type %d not yet supported\n", conf->type);
2455                 ret = -EOPNOTSUPP;
2456                 goto out;
2457         }
2458
2459         DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "Attach a VIF of type: %d\n", ic_opmode);
2460
2461         /* Set the VIF opmode */
2462         avp->av_opmode = ic_opmode;
2463         avp->av_bslot = -1;
2464
2465         sc->nvifs++;
2466
2467         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
2468                 ath9k_set_bssid_mask(hw);
2469
2470         if (sc->nvifs > 1)
2471                 goto out; /* skip global settings for secondary vif */
2472
2473         if (ic_opmode == NL80211_IFTYPE_AP) {
2474                 ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
2475                 sc->sc_flags |= SC_OP_TSF_RESET;
2476         }
2477
2478         /* Set the device opmode */
2479         sc->sc_ah->opmode = ic_opmode;
2480
2481         /*
2482          * Enable MIB interrupts when there are hardware phy counters.
2483          * Note we only do this (at the moment) for station mode.
2484          */
2485         if ((conf->type == NL80211_IFTYPE_STATION) ||
2486             (conf->type == NL80211_IFTYPE_ADHOC) ||
2487             (conf->type == NL80211_IFTYPE_MESH_POINT)) {
2488                 sc->imask |= ATH9K_INT_MIB;
2489                 sc->imask |= ATH9K_INT_TSFOOR;
2490         }
2491
2492         ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
2493
2494         if (conf->type == NL80211_IFTYPE_AP    ||
2495             conf->type == NL80211_IFTYPE_ADHOC ||
2496             conf->type == NL80211_IFTYPE_MONITOR)
2497                 ath_start_ani(sc);
2498
2499 out:
2500         mutex_unlock(&sc->mutex);
2501         return ret;
2502 }
2503
2504 static void ath9k_remove_interface(struct ieee80211_hw *hw,
2505                                    struct ieee80211_if_init_conf *conf)
2506 {
2507         struct ath_wiphy *aphy = hw->priv;
2508         struct ath_softc *sc = aphy->sc;
2509         struct ath_vif *avp = (void *)conf->vif->drv_priv;
2510         int i;
2511
2512         DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "Detach Interface\n");
2513
2514         mutex_lock(&sc->mutex);
2515
2516         /* Stop ANI */
2517         del_timer_sync(&sc->ani.timer);
2518
2519         /* Reclaim beacon resources */
2520         if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) ||
2521             (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) ||
2522             (sc->sc_ah->opmode == NL80211_IFTYPE_MESH_POINT)) {
2523                 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2524                 ath_beacon_return(sc, avp);
2525         }
2526
2527         sc->sc_flags &= ~SC_OP_BEACONS;
2528
2529         for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
2530                 if (sc->beacon.bslot[i] == conf->vif) {
2531                         printk(KERN_DEBUG "%s: vif had allocated beacon "
2532                                "slot\n", __func__);
2533                         sc->beacon.bslot[i] = NULL;
2534                         sc->beacon.bslot_aphy[i] = NULL;
2535                 }
2536         }
2537
2538         sc->nvifs--;
2539
2540         mutex_unlock(&sc->mutex);
2541 }
2542
2543 static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
2544 {
2545         struct ath_wiphy *aphy = hw->priv;
2546         struct ath_softc *sc = aphy->sc;
2547         struct ieee80211_conf *conf = &hw->conf;
2548         struct ath_hw *ah = sc->sc_ah;
2549         bool all_wiphys_idle = false, disable_radio = false;
2550
2551         mutex_lock(&sc->mutex);
2552
2553         /* Leave this as the first check */
2554         if (changed & IEEE80211_CONF_CHANGE_IDLE) {
2555
2556                 spin_lock_bh(&sc->wiphy_lock);
2557                 all_wiphys_idle =  ath9k_all_wiphys_idle(sc);
2558                 spin_unlock_bh(&sc->wiphy_lock);
2559
2560                 if (conf->flags & IEEE80211_CONF_IDLE){
2561                         if (all_wiphys_idle)
2562                                 disable_radio = true;
2563                 }
2564                 else if (all_wiphys_idle) {
2565                         ath_radio_enable(sc);
2566                         DPRINTF(sc->sc_ah, ATH_DBG_CONFIG,
2567                                 "not-idle: enabling radio\n");
2568                 }
2569         }
2570
2571         if (changed & IEEE80211_CONF_CHANGE_PS) {
2572                 if (conf->flags & IEEE80211_CONF_PS) {
2573                         if (!(ah->caps.hw_caps &
2574                               ATH9K_HW_CAP_AUTOSLEEP)) {
2575                                 if ((sc->imask & ATH9K_INT_TIM_TIMER) == 0) {
2576                                         sc->imask |= ATH9K_INT_TIM_TIMER;
2577                                         ath9k_hw_set_interrupts(sc->sc_ah,
2578                                                         sc->imask);
2579                                 }
2580                                 ath9k_hw_setrxabort(sc->sc_ah, 1);
2581                         }
2582                         sc->ps_enabled = true;
2583                 } else {
2584                         sc->ps_enabled = false;
2585                         ath9k_setpower(sc, ATH9K_PM_AWAKE);
2586                         if (!(ah->caps.hw_caps &
2587                               ATH9K_HW_CAP_AUTOSLEEP)) {
2588                                 ath9k_hw_setrxabort(sc->sc_ah, 0);
2589                                 sc->sc_flags &= ~(SC_OP_WAIT_FOR_BEACON |
2590                                                   SC_OP_WAIT_FOR_CAB |
2591                                                   SC_OP_WAIT_FOR_PSPOLL_DATA |
2592                                                   SC_OP_WAIT_FOR_TX_ACK);
2593                                 if (sc->imask & ATH9K_INT_TIM_TIMER) {
2594                                         sc->imask &= ~ATH9K_INT_TIM_TIMER;
2595                                         ath9k_hw_set_interrupts(sc->sc_ah,
2596                                                         sc->imask);
2597                                 }
2598                         }
2599                 }
2600         }
2601
2602         if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
2603                 struct ieee80211_channel *curchan = hw->conf.channel;
2604                 int pos = curchan->hw_value;
2605
2606                 aphy->chan_idx = pos;
2607                 aphy->chan_is_ht = conf_is_ht(conf);
2608
2609                 if (aphy->state == ATH_WIPHY_SCAN ||
2610                     aphy->state == ATH_WIPHY_ACTIVE)
2611                         ath9k_wiphy_pause_all_forced(sc, aphy);
2612                 else {
2613                         /*
2614                          * Do not change operational channel based on a paused
2615                          * wiphy changes.
2616                          */
2617                         goto skip_chan_change;
2618                 }
2619
2620                 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
2621                         curchan->center_freq);
2622
2623                 /* XXX: remove me eventualy */
2624                 ath9k_update_ichannel(sc, hw, &sc->sc_ah->channels[pos]);
2625
2626                 ath_update_chainmask(sc, conf_is_ht(conf));
2627
2628                 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
2629                         DPRINTF(sc->sc_ah, ATH_DBG_FATAL, "Unable to set channel\n");
2630                         mutex_unlock(&sc->mutex);
2631                         return -EINVAL;
2632                 }
2633         }
2634
2635 skip_chan_change:
2636         if (changed & IEEE80211_CONF_CHANGE_POWER)
2637                 sc->config.txpowlimit = 2 * conf->power_level;
2638
2639         if (disable_radio) {
2640                 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "idle: disabling radio\n");
2641                 ath_radio_disable(sc);
2642         }
2643
2644         mutex_unlock(&sc->mutex);
2645
2646         return 0;
2647 }
2648
2649 #define SUPPORTED_FILTERS                       \
2650         (FIF_PROMISC_IN_BSS |                   \
2651         FIF_ALLMULTI |                          \
2652         FIF_CONTROL |                           \
2653         FIF_PSPOLL |                            \
2654         FIF_OTHER_BSS |                         \
2655         FIF_BCN_PRBRESP_PROMISC |               \
2656         FIF_FCSFAIL)
2657
2658 /* FIXME: sc->sc_full_reset ? */
2659 static void ath9k_configure_filter(struct ieee80211_hw *hw,
2660                                    unsigned int changed_flags,
2661                                    unsigned int *total_flags,
2662                                    u64 multicast)
2663 {
2664         struct ath_wiphy *aphy = hw->priv;
2665         struct ath_softc *sc = aphy->sc;
2666         u32 rfilt;
2667
2668         changed_flags &= SUPPORTED_FILTERS;
2669         *total_flags &= SUPPORTED_FILTERS;
2670
2671         sc->rx.rxfilter = *total_flags;
2672         ath9k_ps_wakeup(sc);
2673         rfilt = ath_calcrxfilter(sc);
2674         ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
2675         ath9k_ps_restore(sc);
2676
2677         DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "Set HW RX filter: 0x%x\n", rfilt);
2678 }
2679
2680 static void ath9k_sta_notify(struct ieee80211_hw *hw,
2681                              struct ieee80211_vif *vif,
2682                              enum sta_notify_cmd cmd,
2683                              struct ieee80211_sta *sta)
2684 {
2685         struct ath_wiphy *aphy = hw->priv;
2686         struct ath_softc *sc = aphy->sc;
2687
2688         switch (cmd) {
2689         case STA_NOTIFY_ADD:
2690                 ath_node_attach(sc, sta);
2691                 break;
2692         case STA_NOTIFY_REMOVE:
2693                 ath_node_detach(sc, sta);
2694                 break;
2695         default:
2696                 break;
2697         }
2698 }
2699
2700 static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
2701                          const struct ieee80211_tx_queue_params *params)
2702 {
2703         struct ath_wiphy *aphy = hw->priv;
2704         struct ath_softc *sc = aphy->sc;
2705         struct ath9k_tx_queue_info qi;
2706         int ret = 0, qnum;
2707
2708         if (queue >= WME_NUM_AC)
2709                 return 0;
2710
2711         mutex_lock(&sc->mutex);
2712
2713         memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
2714
2715         qi.tqi_aifs = params->aifs;
2716         qi.tqi_cwmin = params->cw_min;
2717         qi.tqi_cwmax = params->cw_max;
2718         qi.tqi_burstTime = params->txop;
2719         qnum = ath_get_hal_qnum(queue, sc);
2720
2721         DPRINTF(sc->sc_ah, ATH_DBG_CONFIG,
2722                 "Configure tx [queue/halq] [%d/%d],  "
2723                 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
2724                 queue, qnum, params->aifs, params->cw_min,
2725                 params->cw_max, params->txop);
2726
2727         ret = ath_txq_update(sc, qnum, &qi);
2728         if (ret)
2729                 DPRINTF(sc->sc_ah, ATH_DBG_FATAL, "TXQ Update failed\n");
2730
2731         mutex_unlock(&sc->mutex);
2732
2733         return ret;
2734 }
2735
2736 static int ath9k_set_key(struct ieee80211_hw *hw,
2737                          enum set_key_cmd cmd,
2738                          struct ieee80211_vif *vif,
2739                          struct ieee80211_sta *sta,
2740                          struct ieee80211_key_conf *key)
2741 {
2742         struct ath_wiphy *aphy = hw->priv;
2743         struct ath_softc *sc = aphy->sc;
2744         int ret = 0;
2745
2746         if (modparam_nohwcrypt)
2747                 return -ENOSPC;
2748
2749         mutex_lock(&sc->mutex);
2750         ath9k_ps_wakeup(sc);
2751         DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "Set HW Key\n");
2752
2753         switch (cmd) {
2754         case SET_KEY:
2755                 ret = ath_key_config(sc, vif, sta, key);
2756                 if (ret >= 0) {
2757                         key->hw_key_idx = ret;
2758                         /* push IV and Michael MIC generation to stack */
2759                         key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2760                         if (key->alg == ALG_TKIP)
2761                                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
2762                         if (sc->sc_ah->sw_mgmt_crypto && key->alg == ALG_CCMP)
2763                                 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
2764                         ret = 0;
2765                 }
2766                 break;
2767         case DISABLE_KEY:
2768                 ath_key_delete(sc, key);
2769                 break;
2770         default:
2771                 ret = -EINVAL;
2772         }
2773
2774         ath9k_ps_restore(sc);
2775         mutex_unlock(&sc->mutex);
2776
2777         return ret;
2778 }
2779
2780 static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2781                                    struct ieee80211_vif *vif,
2782                                    struct ieee80211_bss_conf *bss_conf,
2783                                    u32 changed)
2784 {
2785         struct ath_wiphy *aphy = hw->priv;
2786         struct ath_softc *sc = aphy->sc;
2787         struct ath_hw *ah = sc->sc_ah;
2788         struct ath_vif *avp = (void *)vif->drv_priv;
2789         u32 rfilt = 0;
2790         int error, i;
2791
2792         mutex_lock(&sc->mutex);
2793
2794         /*
2795          * TODO: Need to decide which hw opmode to use for
2796          *       multi-interface cases
2797          * XXX: This belongs into add_interface!
2798          */
2799         if (vif->type == NL80211_IFTYPE_AP &&
2800             ah->opmode != NL80211_IFTYPE_AP) {
2801                 ah->opmode = NL80211_IFTYPE_STATION;
2802                 ath9k_hw_setopmode(ah);
2803                 memcpy(sc->curbssid, sc->sc_ah->macaddr, ETH_ALEN);
2804                 sc->curaid = 0;
2805                 ath9k_hw_write_associd(ah);
2806                 /* Request full reset to get hw opmode changed properly */
2807                 sc->sc_flags |= SC_OP_FULL_RESET;
2808         }
2809
2810         if ((changed & BSS_CHANGED_BSSID) &&
2811             !is_zero_ether_addr(bss_conf->bssid)) {
2812                 switch (vif->type) {
2813                 case NL80211_IFTYPE_STATION:
2814                 case NL80211_IFTYPE_ADHOC:
2815                 case NL80211_IFTYPE_MESH_POINT:
2816                         /* Set BSSID */
2817                         memcpy(sc->curbssid, bss_conf->bssid, ETH_ALEN);
2818                         memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN);
2819                         sc->curaid = 0;
2820                         ath9k_hw_write_associd(ah);
2821
2822                         /* Set aggregation protection mode parameters */
2823                         sc->config.ath_aggr_prot = 0;
2824
2825                         DPRINTF(sc->sc_ah, ATH_DBG_CONFIG,
2826                                 "RX filter 0x%x bssid %pM aid 0x%x\n",
2827                                 rfilt, sc->curbssid, sc->curaid);
2828
2829                         /* need to reconfigure the beacon */
2830                         sc->sc_flags &= ~SC_OP_BEACONS ;
2831
2832                         break;
2833                 default:
2834                         break;
2835                 }
2836         }
2837
2838         if ((vif->type == NL80211_IFTYPE_ADHOC) ||
2839             (vif->type == NL80211_IFTYPE_AP) ||
2840             (vif->type == NL80211_IFTYPE_MESH_POINT)) {
2841                 if ((changed & BSS_CHANGED_BEACON) ||
2842                     (changed & BSS_CHANGED_BEACON_ENABLED &&
2843                      bss_conf->enable_beacon)) {
2844                         /*
2845                          * Allocate and setup the beacon frame.
2846                          *
2847                          * Stop any previous beacon DMA.  This may be
2848                          * necessary, for example, when an ibss merge
2849                          * causes reconfiguration; we may be called
2850                          * with beacon transmission active.
2851                          */
2852                         ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2853
2854                         error = ath_beacon_alloc(aphy, vif);
2855                         if (!error)
2856                                 ath_beacon_config(sc, vif);
2857                 }
2858         }
2859
2860         /* Check for WLAN_CAPABILITY_PRIVACY ? */
2861         if ((avp->av_opmode != NL80211_IFTYPE_STATION)) {
2862                 for (i = 0; i < IEEE80211_WEP_NKID; i++)
2863                         if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i))
2864                                 ath9k_hw_keysetmac(sc->sc_ah,
2865                                                    (u16)i,
2866                                                    sc->curbssid);
2867         }
2868
2869         /* Only legacy IBSS for now */
2870         if (vif->type == NL80211_IFTYPE_ADHOC)
2871                 ath_update_chainmask(sc, 0);
2872
2873         if (changed & BSS_CHANGED_ERP_PREAMBLE) {
2874                 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
2875                         bss_conf->use_short_preamble);
2876                 if (bss_conf->use_short_preamble)
2877                         sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
2878                 else
2879                         sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
2880         }
2881
2882         if (changed & BSS_CHANGED_ERP_CTS_PROT) {
2883                 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
2884                         bss_conf->use_cts_prot);
2885                 if (bss_conf->use_cts_prot &&
2886                     hw->conf.channel->band != IEEE80211_BAND_5GHZ)
2887                         sc->sc_flags |= SC_OP_PROTECT_ENABLE;
2888                 else
2889                         sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
2890         }
2891
2892         if (changed & BSS_CHANGED_ASSOC) {
2893                 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
2894                         bss_conf->assoc);
2895                 ath9k_bss_assoc_info(sc, vif, bss_conf);
2896         }
2897
2898         /*
2899          * The HW TSF has to be reset when the beacon interval changes.
2900          * We set the flag here, and ath_beacon_config_ap() would take this
2901          * into account when it gets called through the subsequent
2902          * config_interface() call - with IFCC_BEACON in the changed field.
2903          */
2904
2905         if (changed & BSS_CHANGED_BEACON_INT) {
2906                 sc->sc_flags |= SC_OP_TSF_RESET;
2907                 sc->beacon_interval = bss_conf->beacon_int;
2908         }
2909
2910         mutex_unlock(&sc->mutex);
2911 }
2912
2913 static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
2914 {
2915         u64 tsf;
2916         struct ath_wiphy *aphy = hw->priv;
2917         struct ath_softc *sc = aphy->sc;
2918
2919         mutex_lock(&sc->mutex);
2920         tsf = ath9k_hw_gettsf64(sc->sc_ah);
2921         mutex_unlock(&sc->mutex);
2922
2923         return tsf;
2924 }
2925
2926 static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
2927 {
2928         struct ath_wiphy *aphy = hw->priv;
2929         struct ath_softc *sc = aphy->sc;
2930
2931         mutex_lock(&sc->mutex);
2932         ath9k_hw_settsf64(sc->sc_ah, tsf);
2933         mutex_unlock(&sc->mutex);
2934 }
2935
2936 static void ath9k_reset_tsf(struct ieee80211_hw *hw)
2937 {
2938         struct ath_wiphy *aphy = hw->priv;
2939         struct ath_softc *sc = aphy->sc;
2940
2941         mutex_lock(&sc->mutex);
2942
2943         ath9k_ps_wakeup(sc);
2944         ath9k_hw_reset_tsf(sc->sc_ah);
2945         ath9k_ps_restore(sc);
2946
2947         mutex_unlock(&sc->mutex);
2948 }
2949
2950 static int ath9k_ampdu_action(struct ieee80211_hw *hw,
2951                               enum ieee80211_ampdu_mlme_action action,
2952                               struct ieee80211_sta *sta,
2953                               u16 tid, u16 *ssn)
2954 {
2955         struct ath_wiphy *aphy = hw->priv;
2956         struct ath_softc *sc = aphy->sc;
2957         int ret = 0;
2958
2959         switch (action) {
2960         case IEEE80211_AMPDU_RX_START:
2961                 if (!(sc->sc_flags & SC_OP_RXAGGR))
2962                         ret = -ENOTSUPP;
2963                 break;
2964         case IEEE80211_AMPDU_RX_STOP:
2965                 break;
2966         case IEEE80211_AMPDU_TX_START:
2967                 ath_tx_aggr_start(sc, sta, tid, ssn);
2968                 ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid);
2969                 break;
2970         case IEEE80211_AMPDU_TX_STOP:
2971                 ath_tx_aggr_stop(sc, sta, tid);
2972                 ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid);
2973                 break;
2974         case IEEE80211_AMPDU_TX_OPERATIONAL:
2975                 ath_tx_aggr_resume(sc, sta, tid);
2976                 break;
2977         default:
2978                 DPRINTF(sc->sc_ah, ATH_DBG_FATAL, "Unknown AMPDU action\n");
2979         }
2980
2981         return ret;
2982 }
2983
2984 static void ath9k_sw_scan_start(struct ieee80211_hw *hw)
2985 {
2986         struct ath_wiphy *aphy = hw->priv;
2987         struct ath_softc *sc = aphy->sc;
2988
2989         mutex_lock(&sc->mutex);
2990         if (ath9k_wiphy_scanning(sc)) {
2991                 printk(KERN_DEBUG "ath9k: Two wiphys trying to scan at the "
2992                        "same time\n");
2993                 /*
2994                  * Do not allow the concurrent scanning state for now. This
2995                  * could be improved with scanning control moved into ath9k.
2996                  */
2997                 mutex_unlock(&sc->mutex);
2998                 return;
2999         }
3000
3001         aphy->state = ATH_WIPHY_SCAN;
3002         ath9k_wiphy_pause_all_forced(sc, aphy);
3003
3004         spin_lock_bh(&sc->ani_lock);
3005         sc->sc_flags |= SC_OP_SCANNING;
3006         spin_unlock_bh(&sc->ani_lock);
3007         mutex_unlock(&sc->mutex);
3008 }
3009
3010 static void ath9k_sw_scan_complete(struct ieee80211_hw *hw)
3011 {
3012         struct ath_wiphy *aphy = hw->priv;
3013         struct ath_softc *sc = aphy->sc;
3014
3015         mutex_lock(&sc->mutex);
3016         spin_lock_bh(&sc->ani_lock);
3017         aphy->state = ATH_WIPHY_ACTIVE;
3018         sc->sc_flags &= ~SC_OP_SCANNING;
3019         sc->sc_flags |= SC_OP_FULL_RESET;
3020         spin_unlock_bh(&sc->ani_lock);
3021         ath_beacon_config(sc, NULL);
3022         mutex_unlock(&sc->mutex);
3023 }
3024
3025 struct ieee80211_ops ath9k_ops = {
3026         .tx                 = ath9k_tx,
3027         .start              = ath9k_start,
3028         .stop               = ath9k_stop,
3029         .add_interface      = ath9k_add_interface,
3030         .remove_interface   = ath9k_remove_interface,
3031         .config             = ath9k_config,
3032         .configure_filter   = ath9k_configure_filter,
3033         .sta_notify         = ath9k_sta_notify,
3034         .conf_tx            = ath9k_conf_tx,
3035         .bss_info_changed   = ath9k_bss_info_changed,
3036         .set_key            = ath9k_set_key,
3037         .get_tsf            = ath9k_get_tsf,
3038         .set_tsf            = ath9k_set_tsf,
3039         .reset_tsf          = ath9k_reset_tsf,
3040         .ampdu_action       = ath9k_ampdu_action,
3041         .sw_scan_start      = ath9k_sw_scan_start,
3042         .sw_scan_complete   = ath9k_sw_scan_complete,
3043         .rfkill_poll        = ath9k_rfkill_poll_state,
3044 };
3045
3046 static struct {
3047         u32 version;
3048         const char * name;
3049 } ath_mac_bb_names[] = {
3050         { AR_SREV_VERSION_5416_PCI,     "5416" },
3051         { AR_SREV_VERSION_5416_PCIE,    "5418" },
3052         { AR_SREV_VERSION_9100,         "9100" },
3053         { AR_SREV_VERSION_9160,         "9160" },
3054         { AR_SREV_VERSION_9280,         "9280" },
3055         { AR_SREV_VERSION_9285,         "9285" },
3056         { AR_SREV_VERSION_9287,         "9287" }
3057 };
3058
3059 static struct {
3060         u16 version;
3061         const char * name;
3062 } ath_rf_names[] = {
3063         { 0,                            "5133" },
3064         { AR_RAD5133_SREV_MAJOR,        "5133" },
3065         { AR_RAD5122_SREV_MAJOR,        "5122" },
3066         { AR_RAD2133_SREV_MAJOR,        "2133" },
3067         { AR_RAD2122_SREV_MAJOR,        "2122" }
3068 };
3069
3070 /*
3071  * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
3072  */
3073 const char *
3074 ath_mac_bb_name(u32 mac_bb_version)
3075 {
3076         int i;
3077
3078         for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
3079                 if (ath_mac_bb_names[i].version == mac_bb_version) {
3080                         return ath_mac_bb_names[i].name;
3081                 }
3082         }
3083
3084         return "????";
3085 }
3086
3087 /*
3088  * Return the RF name. "????" is returned if the RF is unknown.
3089  */
3090 const char *
3091 ath_rf_name(u16 rf_version)
3092 {
3093         int i;
3094
3095         for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
3096                 if (ath_rf_names[i].version == rf_version) {
3097                         return ath_rf_names[i].name;
3098                 }
3099         }
3100
3101         return "????";
3102 }
3103
3104 static int __init ath9k_init(void)
3105 {
3106         int error;
3107
3108         /* Register rate control algorithm */
3109         error = ath_rate_control_register();
3110         if (error != 0) {
3111                 printk(KERN_ERR
3112                         "ath9k: Unable to register rate control "
3113                         "algorithm: %d\n",
3114                         error);
3115                 goto err_out;
3116         }
3117
3118         error = ath9k_debug_create_root();
3119         if (error) {
3120                 printk(KERN_ERR
3121                         "ath9k: Unable to create debugfs root: %d\n",
3122                         error);
3123                 goto err_rate_unregister;
3124         }
3125
3126         error = ath_pci_init();
3127         if (error < 0) {
3128                 printk(KERN_ERR
3129                         "ath9k: No PCI devices found, driver not installed.\n");
3130                 error = -ENODEV;
3131                 goto err_remove_root;
3132         }
3133
3134         error = ath_ahb_init();
3135         if (error < 0) {
3136                 error = -ENODEV;
3137                 goto err_pci_exit;
3138         }
3139
3140         return 0;
3141
3142  err_pci_exit:
3143         ath_pci_exit();
3144
3145  err_remove_root:
3146         ath9k_debug_remove_root();
3147  err_rate_unregister:
3148         ath_rate_control_unregister();
3149  err_out:
3150         return error;
3151 }
3152 module_init(ath9k_init);
3153
3154 static void __exit ath9k_exit(void)
3155 {
3156         ath_ahb_exit();
3157         ath_pci_exit();
3158         ath9k_debug_remove_root();
3159         ath_rate_control_unregister();
3160         printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
3161 }
3162 module_exit(ath9k_exit);