SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/net/wireless/ath/ath9k/hw.c

   1 /*
   2  * Copyright (c) 2008-2010 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/io.h>
  18 #include <asm/unaligned.h>
  19
  20 #include "hw.h"
  21 #include "hw-ops.h"
  22 #include "rc.h"
  23 #include "ar9003_mac.h"
  24
  25 #define ATH9K_CLOCK_RATE_CCK            22
  26 #define ATH9K_CLOCK_RATE_5GHZ_OFDM      40
  27 #define ATH9K_CLOCK_RATE_2GHZ_OFDM      44
  28
  29 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
  30
  31 MODULE_AUTHOR("Atheros Communications");
  32 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
  33 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
  34 MODULE_LICENSE("Dual BSD/GPL");
  35
  36 static int __init ath9k_init(void)
  37 {
  38         return 0;
  39 }
  40 module_init(ath9k_init);
  41
  42 static void __exit ath9k_exit(void)
  43 {
  44         return;
  45 }
  46 module_exit(ath9k_exit);
  47
  48 /* Private hardware callbacks */
  49
  50 static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
  51 {
  52         ath9k_hw_private_ops(ah)->init_cal_settings(ah);
  53 }
  54
  55 static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
  56 {
  57         ath9k_hw_private_ops(ah)->init_mode_regs(ah);
  58 }
  59
  60 static bool ath9k_hw_macversion_supported(struct ath_hw *ah)
  61 {
  62         struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
  63
  64         return priv_ops->macversion_supported(ah->hw_version.macVersion);
  65 }
  66
  67 static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah,
  68                                         struct ath9k_channel *chan)
  69 {
  70         return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan);
  71 }
  72
  73 static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
  74 {
  75         if (!ath9k_hw_private_ops(ah)->init_mode_gain_regs)
  76                 return;
  77
  78         ath9k_hw_private_ops(ah)->init_mode_gain_regs(ah);
  79 }
  80
  81 /********************/
  82 /* Helper Functions */
  83 /********************/
  84
  85 static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
  86 {
  87         struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
  88
  89         if (!ah->curchan) /* should really check for CCK instead */
  90                 return usecs *ATH9K_CLOCK_RATE_CCK;
  91         if (conf->channel->band == IEEE80211_BAND_2GHZ)
  92                 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM;
  93         return usecs *ATH9K_CLOCK_RATE_5GHZ_OFDM;
  94 }
  95
  96 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
  97 {
  98         struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
  99
 100         if (conf_is_ht40(conf))
 101                 return ath9k_hw_mac_clks(ah, usecs) * 2;
 102         else
 103                 return ath9k_hw_mac_clks(ah, usecs);
 104 }
 105
 106 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
 107 {
 108         int i;
 109
 110         BUG_ON(timeout < AH_TIME_QUANTUM);
 111
 112         for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
 113                 if ((REG_READ(ah, reg) & mask) == val)
 114                         return true;
 115
 116                 udelay(AH_TIME_QUANTUM);
 117         }
 118
 119         ath_print(ath9k_hw_common(ah), ATH_DBG_ANY,
 120                   "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
 121                   timeout, reg, REG_READ(ah, reg), mask, val);
 122
 123         return false;
 124 }
 125 EXPORT_SYMBOL(ath9k_hw_wait);
 126
 127 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
 128 {
 129         u32 retval;
 130         int i;
 131
 132         for (i = 0, retval = 0; i < n; i++) {
 133                 retval = (retval << 1) | (val & 1);
 134                 val >>= 1;
 135         }
 136         return retval;
 137 }
 138
 139 bool ath9k_get_channel_edges(struct ath_hw *ah,
 140                              u16 flags, u16 *low,
 141                              u16 *high)
 142 {
 143         struct ath9k_hw_capabilities *pCap = &ah->caps;
 144
 145         if (flags & CHANNEL_5GHZ) {
 146                 *low = pCap->low_5ghz_chan;
 147                 *high = pCap->high_5ghz_chan;
 148                 return true;
 149         }
 150         if ((flags & CHANNEL_2GHZ)) {
 151                 *low = pCap->low_2ghz_chan;
 152                 *high = pCap->high_2ghz_chan;
 153                 return true;
 154         }
 155         return false;
 156 }
 157
 158 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
 159                            u8 phy, int kbps,
 160                            u32 frameLen, u16 rateix,
 161                            bool shortPreamble)
 162 {
 163         u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
 164
 165         if (kbps == 0)
 166                 return 0;
 167
 168         switch (phy) {
 169         case WLAN_RC_PHY_CCK:
 170                 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
 171                 if (shortPreamble)
 172                         phyTime >>= 1;
 173                 numBits = frameLen << 3;
 174                 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
 175                 break;
 176         case WLAN_RC_PHY_OFDM:
 177                 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
 178                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
 179                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 180                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 181                         txTime = OFDM_SIFS_TIME_QUARTER
 182                                 + OFDM_PREAMBLE_TIME_QUARTER
 183                                 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
 184                 } else if (ah->curchan &&
 185                            IS_CHAN_HALF_RATE(ah->curchan)) {
 186                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
 187                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 188                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 189                         txTime = OFDM_SIFS_TIME_HALF +
 190                                 OFDM_PREAMBLE_TIME_HALF
 191                                 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
 192                 } else {
 193                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
 194                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 195                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 196                         txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
 197                                 + (numSymbols * OFDM_SYMBOL_TIME);
 198                 }
 199                 break;
 200         default:
 201                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
 202                           "Unknown phy %u (rate ix %u)\n", phy, rateix);
 203                 txTime = 0;
 204                 break;
 205         }
 206
 207         return txTime;
 208 }
 209 EXPORT_SYMBOL(ath9k_hw_computetxtime);
 210
 211 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
 212                                   struct ath9k_channel *chan,
 213                                   struct chan_centers *centers)
 214 {
 215         int8_t extoff;
 216
 217         if (!IS_CHAN_HT40(chan)) {
 218                 centers->ctl_center = centers->ext_center =
 219                         centers->synth_center = chan->channel;
 220                 return;
 221         }
 222
 223         if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
 224             (chan->chanmode == CHANNEL_G_HT40PLUS)) {
 225                 centers->synth_center =
 226                         chan->channel + HT40_CHANNEL_CENTER_SHIFT;
 227                 extoff = 1;
 228         } else {
 229                 centers->synth_center =
 230                         chan->channel - HT40_CHANNEL_CENTER_SHIFT;
 231                 extoff = -1;
 232         }
 233
 234         centers->ctl_center =
 235                 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
 236         /* 25 MHz spacing is supported by hw but not on upper layers */
 237         centers->ext_center =
 238                 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
 239 }
 240
 241 /******************/
 242 /* Chip Revisions */
 243 /******************/
 244
 245 static void ath9k_hw_read_revisions(struct ath_hw *ah)
 246 {
 247         u32 val;
 248
 249         val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
 250
 251         if (val == 0xFF) {
 252                 val = REG_READ(ah, AR_SREV);
 253                 ah->hw_version.macVersion =
 254                         (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
 255                 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
 256                 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
 257         } else {
 258                 if (!AR_SREV_9100(ah))
 259                         ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
 260
 261                 ah->hw_version.macRev = val & AR_SREV_REVISION;
 262
 263                 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
 264                         ah->is_pciexpress = true;
 265         }
 266 }
 267
 268 /************************************/
 269 /* HW Attach, Detach, Init Routines */
 270 /************************************/
 271
 272 static void ath9k_hw_disablepcie(struct ath_hw *ah)
 273 {
 274         if (AR_SREV_9100(ah))
 275                 return;
 276
 277         ENABLE_REGWRITE_BUFFER(ah);
 278
 279         REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
 280         REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
 281         REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
 282         REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
 283         REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
 284         REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
 285         REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
 286         REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
 287         REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
 288
 289         REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
 290
 291         REGWRITE_BUFFER_FLUSH(ah);
 292         DISABLE_REGWRITE_BUFFER(ah);
 293 }
 294
 295 /* This should work for all families including legacy */
 296 static bool ath9k_hw_chip_test(struct ath_hw *ah)
 297 {
 298         struct ath_common *common = ath9k_hw_common(ah);
 299         u32 regAddr[2] = { AR_STA_ID0 };
 300         u32 regHold[2];
 301         u32 patternData[4] = { 0x55555555,
 302                                0xaaaaaaaa,
 303                                0x66666666,
 304                                0x99999999 };
 305         int i, j, loop_max;
 306
 307         if (!AR_SREV_9300_20_OR_LATER(ah)) {
 308                 loop_max = 2;
 309                 regAddr[1] = AR_PHY_BASE + (8 << 2);
 310         } else
 311                 loop_max = 1;
 312
 313         for (i = 0; i < loop_max; i++) {
 314                 u32 addr = regAddr[i];
 315                 u32 wrData, rdData;
 316
 317                 regHold[i] = REG_READ(ah, addr);
 318                 for (j = 0; j < 0x100; j++) {
 319                         wrData = (j << 16) | j;
 320                         REG_WRITE(ah, addr, wrData);
 321                         rdData = REG_READ(ah, addr);
 322                         if (rdData != wrData) {
 323                                 ath_print(common, ATH_DBG_FATAL,
 324                                           "address test failed "
 325                                           "addr: 0x%08x - wr:0x%08x != "
 326                                           "rd:0x%08x\n",
 327                                           addr, wrData, rdData);
 328                                 return false;
 329                         }
 330                 }
 331                 for (j = 0; j < 4; j++) {
 332                         wrData = patternData[j];
 333                         REG_WRITE(ah, addr, wrData);
 334                         rdData = REG_READ(ah, addr);
 335                         if (wrData != rdData) {
 336                                 ath_print(common, ATH_DBG_FATAL,
 337                                           "address test failed "
 338                                           "addr: 0x%08x - wr:0x%08x != "
 339                                           "rd:0x%08x\n",
 340                                           addr, wrData, rdData);
 341                                 return false;
 342                         }
 343                 }
 344                 REG_WRITE(ah, regAddr[i], regHold[i]);
 345         }
 346         udelay(100);
 347
 348         return true;
 349 }
 350
 351 static void ath9k_hw_init_config(struct ath_hw *ah)
 352 {
 353         int i;
 354
 355         ah->config.dma_beacon_response_time = 2;
 356         ah->config.sw_beacon_response_time = 10;
 357         ah->config.additional_swba_backoff = 0;
 358         ah->config.ack_6mb = 0x0;
 359         ah->config.cwm_ignore_extcca = 0;
 360         ah->config.pcie_powersave_enable = 0;
 361         ah->config.pcie_clock_req = 0;
 362         ah->config.pcie_waen = 0;
 363         ah->config.analog_shiftreg = 1;
 364         ah->config.ofdm_trig_low = 200;
 365         ah->config.ofdm_trig_high = 500;
 366         ah->config.cck_trig_high = 200;
 367         ah->config.cck_trig_low = 100;
 368
 369         /*
 370          * For now ANI is disabled for AR9003, it is still
 371          * being tested.
 372          */
 373         if (!AR_SREV_9300_20_OR_LATER(ah))
 374                 ah->config.enable_ani = 1;
 375
 376         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
 377                 ah->config.spurchans[i][0] = AR_NO_SPUR;
 378                 ah->config.spurchans[i][1] = AR_NO_SPUR;
 379         }
 380
 381         if (ah->hw_version.devid != AR2427_DEVID_PCIE)
 382                 ah->config.ht_enable = 1;
 383         else
 384                 ah->config.ht_enable = 0;
 385
 386         ah->config.rx_intr_mitigation = true;
 387
 388         /*
 389          * Tx IQ Calibration (ah->config.tx_iq_calibration) is only
 390          * used by AR9003, but it is showing reliability issues.
 391          * It will take a while to fix so this is currently disabled.
 392          */
 393
 394         /*
 395          * We need this for PCI devices only (Cardbus, PCI, miniPCI)
 396          * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
 397          * This means we use it for all AR5416 devices, and the few
 398          * minor PCI AR9280 devices out there.
 399          *
 400          * Serialization is required because these devices do not handle
 401          * well the case of two concurrent reads/writes due to the latency
 402          * involved. During one read/write another read/write can be issued
 403          * on another CPU while the previous read/write may still be working
 404          * on our hardware, if we hit this case the hardware poops in a loop.
 405          * We prevent this by serializing reads and writes.
 406          *
 407          * This issue is not present on PCI-Express devices or pre-AR5416
 408          * devices (legacy, 802.11abg).
 409          */
 410         if (num_possible_cpus() > 1)
 411                 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
 412 }
 413
 414 static void ath9k_hw_init_defaults(struct ath_hw *ah)
 415 {
 416         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
 417
 418         regulatory->country_code = CTRY_DEFAULT;
 419         regulatory->power_limit = MAX_RATE_POWER;
 420         regulatory->tp_scale = ATH9K_TP_SCALE_MAX;
 421
 422         ah->hw_version.magic = AR5416_MAGIC;
 423         ah->hw_version.subvendorid = 0;
 424
 425         ah->ah_flags = 0;
 426         if (!AR_SREV_9100(ah))
 427                 ah->ah_flags = AH_USE_EEPROM;
 428
 429         ah->atim_window = 0;
 430         ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
 431         ah->beacon_interval = 100;
 432         ah->enable_32kHz_clock = DONT_USE_32KHZ;
 433         ah->slottime = (u32) -1;
 434         ah->globaltxtimeout = (u32) -1;
 435         ah->power_mode = ATH9K_PM_UNDEFINED;
 436 }
 437
 438 static int ath9k_hw_init_macaddr(struct ath_hw *ah)
 439 {
 440         struct ath_common *common = ath9k_hw_common(ah);
 441         u32 sum;
 442         int i;
 443         u16 eeval;
 444         u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW };
 445
 446         sum = 0;
 447         for (i = 0; i < 3; i++) {
 448                 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]);
 449                 sum += eeval;
 450                 common->macaddr[2 * i] = eeval >> 8;
 451                 common->macaddr[2 * i + 1] = eeval & 0xff;
 452         }
 453         if (sum == 0 || sum == 0xffff * 3)
 454                 return -EADDRNOTAVAIL;
 455
 456         return 0;
 457 }
 458
 459 static int ath9k_hw_post_init(struct ath_hw *ah)
 460 {
 461         int ecode;
 462
 463         if (!AR_SREV_9271(ah)) {
 464                 if (!ath9k_hw_chip_test(ah))
 465                         return -ENODEV;
 466         }
 467
 468         if (!AR_SREV_9300_20_OR_LATER(ah)) {
 469                 ecode = ar9002_hw_rf_claim(ah);
 470                 if (ecode != 0)
 471                         return ecode;
 472         }
 473
 474         ecode = ath9k_hw_eeprom_init(ah);
 475         if (ecode != 0)
 476                 return ecode;
 477
 478         ath_print(ath9k_hw_common(ah), ATH_DBG_CONFIG,
 479                   "Eeprom VER: %d, REV: %d\n",
 480                   ah->eep_ops->get_eeprom_ver(ah),
 481                   ah->eep_ops->get_eeprom_rev(ah));
 482
 483         ecode = ath9k_hw_rf_alloc_ext_banks(ah);
 484         if (ecode) {
 485                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
 486                           "Failed allocating banks for "
 487                           "external radio\n");
 488                 return ecode;
 489         }
 490
 491         if (!AR_SREV_9100(ah)) {
 492                 ath9k_hw_ani_setup(ah);
 493                 ath9k_hw_ani_init(ah);
 494         }
 495
 496         return 0;
 497 }
 498
 499 static void ath9k_hw_attach_ops(struct ath_hw *ah)
 500 {
 501         if (AR_SREV_9300_20_OR_LATER(ah))
 502                 ar9003_hw_attach_ops(ah);
 503         else
 504                 ar9002_hw_attach_ops(ah);
 505 }
 506
 507 /* Called for all hardware families */
 508 static int __ath9k_hw_init(struct ath_hw *ah)
 509 {
 510         struct ath_common *common = ath9k_hw_common(ah);
 511         int r = 0;
 512
 513         if (ah->hw_version.devid == AR5416_AR9100_DEVID)
 514                 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
 515
 516         if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
 517                 ath_print(common, ATH_DBG_FATAL,
 518                           "Couldn't reset chip\n");
 519                 return -EIO;
 520         }
 521
 522         ath9k_hw_init_defaults(ah);
 523         ath9k_hw_init_config(ah);
 524
 525         ath9k_hw_attach_ops(ah);
 526
 527         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
 528                 ath_print(common, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
 529                 return -EIO;
 530         }
 531
 532         if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
 533                 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
 534                     (AR_SREV_9280(ah) && !ah->is_pciexpress)) {
 535                         ah->config.serialize_regmode =
 536                                 SER_REG_MODE_ON;
 537                 } else {
 538                         ah->config.serialize_regmode =
 539                                 SER_REG_MODE_OFF;
 540                 }
 541         }
 542
 543         ath_print(common, ATH_DBG_RESET, "serialize_regmode is %d\n",
 544                 ah->config.serialize_regmode);
 545
 546         if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
 547                 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
 548         else
 549                 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
 550
 551         if (!ath9k_hw_macversion_supported(ah)) {
 552                 ath_print(common, ATH_DBG_FATAL,
 553                           "Mac Chip Rev 0x%02x.%x is not supported by "
 554                           "this driver\n", ah->hw_version.macVersion,
 555                           ah->hw_version.macRev);
 556                 return -EOPNOTSUPP;
 557         }
 558
 559         if (AR_SREV_9271(ah) || AR_SREV_9100(ah))
 560                 ah->is_pciexpress = false;
 561
 562         ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
 563         ath9k_hw_init_cal_settings(ah);
 564
 565         ah->ani_function = ATH9K_ANI_ALL;
 566         if (AR_SREV_9280_10_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah))
 567                 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
 568
 569         ath9k_hw_init_mode_regs(ah);
 570
 571         if (ah->is_pciexpress)
 572                 ath9k_hw_configpcipowersave(ah, 0, 0);
 573         else
 574                 ath9k_hw_disablepcie(ah);
 575
 576         if (!AR_SREV_9300_20_OR_LATER(ah))
 577                 ar9002_hw_cck_chan14_spread(ah);
 578
 579         r = ath9k_hw_post_init(ah);
 580         if (r)
 581                 return r;
 582
 583         ath9k_hw_init_mode_gain_regs(ah);
 584         r = ath9k_hw_fill_cap_info(ah);
 585         if (r)
 586                 return r;
 587
 588         r = ath9k_hw_init_macaddr(ah);
 589         if (r) {
 590                 ath_print(common, ATH_DBG_FATAL,
 591                           "Failed to initialize MAC address\n");
 592                 return r;
 593         }
 594
 595         if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
 596                 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
 597         else
 598                 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
 599
 600         if (AR_SREV_9300_20_OR_LATER(ah))
 601                 ar9003_hw_set_nf_limits(ah);
 602
 603         ath9k_init_nfcal_hist_buffer(ah);
 604
 605         common->state = ATH_HW_INITIALIZED;
 606
 607         return 0;
 608 }
 609
 610 int ath9k_hw_init(struct ath_hw *ah)
 611 {
 612         int ret;
 613         struct ath_common *common = ath9k_hw_common(ah);
 614
 615         /* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */
 616         switch (ah->hw_version.devid) {
 617         case AR5416_DEVID_PCI:
 618         case AR5416_DEVID_PCIE:
 619         case AR5416_AR9100_DEVID:
 620         case AR9160_DEVID_PCI:
 621         case AR9280_DEVID_PCI:
 622         case AR9280_DEVID_PCIE:
 623         case AR9285_DEVID_PCIE:
 624         case AR9287_DEVID_PCI:
 625         case AR9287_DEVID_PCIE:
 626         case AR2427_DEVID_PCIE:
 627         case AR9300_DEVID_PCIE:
 628                 break;
 629         default:
 630                 if (common->bus_ops->ath_bus_type == ATH_USB)
 631                         break;
 632                 ath_print(common, ATH_DBG_FATAL,
 633                           "Hardware device ID 0x%04x not supported\n",
 634                           ah->hw_version.devid);
 635                 return -EOPNOTSUPP;
 636         }
 637
 638         ret = __ath9k_hw_init(ah);
 639         if (ret) {
 640                 ath_print(common, ATH_DBG_FATAL,
 641                           "Unable to initialize hardware; "
 642                           "initialization status: %d\n", ret);
 643                 return ret;
 644         }
 645
 646         return 0;
 647 }
 648 EXPORT_SYMBOL(ath9k_hw_init);
 649
 650 static void ath9k_hw_init_qos(struct ath_hw *ah)
 651 {
 652         ENABLE_REGWRITE_BUFFER(ah);
 653
 654         REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
 655         REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
 656
 657         REG_WRITE(ah, AR_QOS_NO_ACK,
 658                   SM(2, AR_QOS_NO_ACK_TWO_BIT) |
 659                   SM(5, AR_QOS_NO_ACK_BIT_OFF) |
 660                   SM(0, AR_QOS_NO_ACK_BYTE_OFF));
 661
 662         REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
 663         REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
 664         REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
 665         REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
 666         REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
 667
 668         REGWRITE_BUFFER_FLUSH(ah);
 669         DISABLE_REGWRITE_BUFFER(ah);
 670 }
 671
 672 static void ath9k_hw_init_pll(struct ath_hw *ah,
 673                               struct ath9k_channel *chan)
 674 {
 675         u32 pll = ath9k_hw_compute_pll_control(ah, chan);
 676
 677         REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
 678
 679         /* Switch the core clock for ar9271 to 117Mhz */
 680         if (AR_SREV_9271(ah)) {
 681                 udelay(500);
 682                 REG_WRITE(ah, 0x50040, 0x304);
 683         }
 684
 685         udelay(RTC_PLL_SETTLE_DELAY);
 686
 687         REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
 688 }
 689
 690 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
 691                                           enum nl80211_iftype opmode)
 692 {
 693         u32 imr_reg = AR_IMR_TXERR |
 694                 AR_IMR_TXURN |
 695                 AR_IMR_RXERR |
 696                 AR_IMR_RXORN |
 697                 AR_IMR_BCNMISC;
 698
 699         if (AR_SREV_9300_20_OR_LATER(ah)) {
 700                 imr_reg |= AR_IMR_RXOK_HP;
 701                 if (ah->config.rx_intr_mitigation)
 702                         imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
 703                 else
 704                         imr_reg |= AR_IMR_RXOK_LP;
 705
 706         } else {
 707                 if (ah->config.rx_intr_mitigation)
 708                         imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
 709                 else
 710                         imr_reg |= AR_IMR_RXOK;
 711         }
 712
 713         if (ah->config.tx_intr_mitigation)
 714                 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR;
 715         else
 716                 imr_reg |= AR_IMR_TXOK;
 717
 718         if (opmode == NL80211_IFTYPE_AP)
 719                 imr_reg |= AR_IMR_MIB;
 720
 721         ENABLE_REGWRITE_BUFFER(ah);
 722
 723         REG_WRITE(ah, AR_IMR, imr_reg);
 724         ah->imrs2_reg |= AR_IMR_S2_GTT;
 725         REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
 726
 727         if (!AR_SREV_9100(ah)) {
 728                 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
 729                 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
 730                 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
 731         }
 732
 733         REGWRITE_BUFFER_FLUSH(ah);
 734         DISABLE_REGWRITE_BUFFER(ah);
 735
 736         if (AR_SREV_9300_20_OR_LATER(ah)) {
 737                 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0);
 738                 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0);
 739                 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0);
 740                 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0);
 741         }
 742 }
 743
 744 static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
 745 {
 746         u32 val = ath9k_hw_mac_to_clks(ah, us);
 747         val = min(val, (u32) 0xFFFF);
 748         REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
 749 }
 750
 751 static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
 752 {
 753         u32 val = ath9k_hw_mac_to_clks(ah, us);
 754         val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
 755         REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
 756 }
 757
 758 static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
 759 {
 760         u32 val = ath9k_hw_mac_to_clks(ah, us);
 761         val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
 762         REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
 763 }
 764
 765 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
 766 {
 767         if (tu > 0xFFFF) {
 768                 ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT,
 769                           "bad global tx timeout %u\n", tu);
 770                 ah->globaltxtimeout = (u32) -1;
 771                 return false;
 772         } else {
 773                 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
 774                 ah->globaltxtimeout = tu;
 775                 return true;
 776         }
 777 }
 778
 779 void ath9k_hw_init_global_settings(struct ath_hw *ah)
 780 {
 781         struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
 782         int acktimeout;
 783         int slottime;
 784         int sifstime;
 785
 786         ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
 787                   ah->misc_mode);
 788
 789         if (ah->misc_mode != 0)
 790                 REG_WRITE(ah, AR_PCU_MISC,
 791                           REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
 792
 793         if (conf->channel && conf->channel->band == IEEE80211_BAND_5GHZ)
 794                 sifstime = 16;
 795         else
 796                 sifstime = 10;
 797
 798         /* As defined by IEEE 802.11-2007 17.3.8.6 */
 799         slottime = ah->slottime + 3 * ah->coverage_class;
 800         acktimeout = slottime + sifstime;
 801
 802         /*
 803          * Workaround for early ACK timeouts, add an offset to match the
 804          * initval's 64us ack timeout value.
 805          * This was initially only meant to work around an issue with delayed
 806          * BA frames in some implementations, but it has been found to fix ACK
 807          * timeout issues in other cases as well.
 808          */
 809         if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ)
 810                 acktimeout += 64 - sifstime - ah->slottime;
 811
 812         ath9k_hw_setslottime(ah, slottime);
 813         ath9k_hw_set_ack_timeout(ah, acktimeout);
 814         ath9k_hw_set_cts_timeout(ah, acktimeout);
 815         if (ah->globaltxtimeout != (u32) -1)
 816                 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
 817 }
 818 EXPORT_SYMBOL(ath9k_hw_init_global_settings);
 819
 820 void ath9k_hw_deinit(struct ath_hw *ah)
 821 {
 822         struct ath_common *common = ath9k_hw_common(ah);
 823
 824         if (common->state < ATH_HW_INITIALIZED)
 825                 goto free_hw;
 826
 827         ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
 828
 829 free_hw:
 830         ath9k_hw_rf_free_ext_banks(ah);
 831 }
 832 EXPORT_SYMBOL(ath9k_hw_deinit);
 833
 834 /*******/
 835 /* INI */
 836 /*******/
 837
 838 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
 839 {
 840         u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
 841
 842         if (IS_CHAN_B(chan))
 843                 ctl |= CTL_11B;
 844         else if (IS_CHAN_G(chan))
 845                 ctl |= CTL_11G;
 846         else
 847                 ctl |= CTL_11A;
 848
 849         return ctl;
 850 }
 851
 852 /****************************************/
 853 /* Reset and Channel Switching Routines */
 854 /****************************************/
 855
 856 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
 857 {
 858         struct ath_common *common = ath9k_hw_common(ah);
 859         u32 regval;
 860
 861         ENABLE_REGWRITE_BUFFER(ah);
 862
 863         /*
 864          * set AHB_MODE not to do cacheline prefetches
 865         */
 866         if (!AR_SREV_9300_20_OR_LATER(ah)) {
 867                 regval = REG_READ(ah, AR_AHB_MODE);
 868                 REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
 869         }
 870
 871         /*
 872          * let mac dma reads be in 128 byte chunks
 873          */
 874         regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
 875         REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
 876
 877         REGWRITE_BUFFER_FLUSH(ah);
 878         DISABLE_REGWRITE_BUFFER(ah);
 879
 880         /*
 881          * Restore TX Trigger Level to its pre-reset value.
 882          * The initial value depends on whether aggregation is enabled, and is
 883          * adjusted whenever underruns are detected.
 884          */
 885         if (!AR_SREV_9300_20_OR_LATER(ah))
 886                 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
 887
 888         ENABLE_REGWRITE_BUFFER(ah);
 889
 890         /*
 891          * let mac dma writes be in 128 byte chunks
 892          */
 893         regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
 894         REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
 895
 896         /*
 897          * Setup receive FIFO threshold to hold off TX activities
 898          */
 899         REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
 900
 901         if (AR_SREV_9300_20_OR_LATER(ah)) {
 902                 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1);
 903                 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1);
 904
 905                 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
 906                         ah->caps.rx_status_len);
 907         }
 908
 909         /*
 910          * reduce the number of usable entries in PCU TXBUF to avoid
 911          * wrap around issues.
 912          */
 913         if (AR_SREV_9285(ah)) {
 914                 /* For AR9285 the number of Fifos are reduced to half.
 915                  * So set the usable tx buf size also to half to
 916                  * avoid data/delimiter underruns
 917                  */
 918                 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
 919                           AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
 920         } else if (!AR_SREV_9271(ah)) {
 921                 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
 922                           AR_PCU_TXBUF_CTRL_USABLE_SIZE);
 923         }
 924
 925         REGWRITE_BUFFER_FLUSH(ah);
 926         DISABLE_REGWRITE_BUFFER(ah);
 927
 928         if (AR_SREV_9300_20_OR_LATER(ah))
 929                 ath9k_hw_reset_txstatus_ring(ah);
 930 }
 931
 932 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
 933 {
 934         u32 val;
 935
 936         val = REG_READ(ah, AR_STA_ID1);
 937         val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
 938         switch (opmode) {
 939         case NL80211_IFTYPE_AP:
 940                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
 941                           | AR_STA_ID1_KSRCH_MODE);
 942                 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
 943                 break;
 944         case NL80211_IFTYPE_ADHOC:
 945         case NL80211_IFTYPE_MESH_POINT:
 946                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
 947                           | AR_STA_ID1_KSRCH_MODE);
 948                 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
 949                 break;
 950         case NL80211_IFTYPE_STATION:
 951         case NL80211_IFTYPE_MONITOR:
 952                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
 953                 break;
 954         }
 955 }
 956
 957 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
 958                                    u32 *coef_mantissa, u32 *coef_exponent)
 959 {
 960         u32 coef_exp, coef_man;
 961
 962         for (coef_exp = 31; coef_exp > 0; coef_exp--)
 963                 if ((coef_scaled >> coef_exp) & 0x1)
 964                         break;
 965
 966         coef_exp = 14 - (coef_exp - COEF_SCALE_S);
 967
 968         coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
 969
 970         *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
 971         *coef_exponent = coef_exp - 16;
 972 }
 973
 974 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
 975 {
 976         u32 rst_flags;
 977         u32 tmpReg;
 978
 979         if (AR_SREV_9100(ah)) {
 980                 u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK);
 981                 val &= ~AR_RTC_DERIVED_CLK_PERIOD;
 982                 val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
 983                 REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
 984                 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
 985         }
 986
 987         ENABLE_REGWRITE_BUFFER(ah);
 988
 989         REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
 990                   AR_RTC_FORCE_WAKE_ON_INT);
 991
 992         if (AR_SREV_9100(ah)) {
 993                 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
 994                         AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
 995         } else {
 996                 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
 997                 if (tmpReg &
 998                     (AR_INTR_SYNC_LOCAL_TIMEOUT |
 999                      AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1000                         u32 val;
1001                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1002
1003                         val = AR_RC_HOSTIF;
1004                         if (!AR_SREV_9300_20_OR_LATER(ah))
1005                                 val |= AR_RC_AHB;
1006                         REG_WRITE(ah, AR_RC, val);
1007
1008                 } else if (!AR_SREV_9300_20_OR_LATER(ah))
1009                         REG_WRITE(ah, AR_RC, AR_RC_AHB);
1010
1011                 rst_flags = AR_RTC_RC_MAC_WARM;
1012                 if (type == ATH9K_RESET_COLD)
1013                         rst_flags |= AR_RTC_RC_MAC_COLD;
1014         }
1015
1016         REG_WRITE(ah, AR_RTC_RC, rst_flags);
1017
1018         REGWRITE_BUFFER_FLUSH(ah);
1019         DISABLE_REGWRITE_BUFFER(ah);
1020
1021         udelay(50);
1022
1023         REG_WRITE(ah, AR_RTC_RC, 0);
1024         if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1025                 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1026                           "RTC stuck in MAC reset\n");
1027                 return false;
1028         }
1029
1030         if (!AR_SREV_9100(ah))
1031                 REG_WRITE(ah, AR_RC, 0);
1032
1033         if (AR_SREV_9100(ah))
1034                 udelay(50);
1035
1036         return true;
1037 }
1038
1039 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1040 {
1041         ENABLE_REGWRITE_BUFFER(ah);
1042
1043         REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1044                   AR_RTC_FORCE_WAKE_ON_INT);
1045
1046         if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1047                 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1048
1049         REG_WRITE(ah, AR_RTC_RESET, 0);
1050
1051         REGWRITE_BUFFER_FLUSH(ah);
1052         DISABLE_REGWRITE_BUFFER(ah);
1053
1054         if (!AR_SREV_9300_20_OR_LATER(ah))
1055                 udelay(2);
1056
1057         if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1058                 REG_WRITE(ah, AR_RC, 0);
1059
1060         REG_WRITE(ah, AR_RTC_RESET, 1);
1061
1062         if (!ath9k_hw_wait(ah,
1063                            AR_RTC_STATUS,
1064                            AR_RTC_STATUS_M,
1065                            AR_RTC_STATUS_ON,
1066                            AH_WAIT_TIMEOUT)) {
1067                 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1068                           "RTC not waking up\n");
1069                 return false;
1070         }
1071
1072         ath9k_hw_read_revisions(ah);
1073
1074         return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1075 }
1076
1077 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1078 {
1079         REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1080                   AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1081
1082         switch (type) {
1083         case ATH9K_RESET_POWER_ON:
1084                 return ath9k_hw_set_reset_power_on(ah);
1085         case ATH9K_RESET_WARM:
1086         case ATH9K_RESET_COLD:
1087                 return ath9k_hw_set_reset(ah, type);
1088         default:
1089                 return false;
1090         }
1091 }
1092
1093 static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1094                                 struct ath9k_channel *chan)
1095 {
1096         if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) {
1097                 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1098                         return false;
1099         } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1100                 return false;
1101
1102         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1103                 return false;
1104
1105         ah->chip_fullsleep = false;
1106         ath9k_hw_init_pll(ah, chan);
1107         ath9k_hw_set_rfmode(ah, chan);
1108
1109         return true;
1110 }
1111
1112 static bool ath9k_hw_channel_change(struct ath_hw *ah,
1113                                     struct ath9k_channel *chan)
1114 {
1115         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1116         struct ath_common *common = ath9k_hw_common(ah);
1117         struct ieee80211_channel *channel = chan->chan;
1118         u32 qnum;
1119         int r;
1120
1121         for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1122                 if (ath9k_hw_numtxpending(ah, qnum)) {
1123                         ath_print(common, ATH_DBG_QUEUE,
1124                                   "Transmit frames pending on "
1125                                   "queue %d\n", qnum);
1126                         return false;
1127                 }
1128         }
1129
1130         if (!ath9k_hw_rfbus_req(ah)) {
1131                 ath_print(common, ATH_DBG_FATAL,
1132                           "Could not kill baseband RX\n");
1133                 return false;
1134         }
1135
1136         ath9k_hw_set_channel_regs(ah, chan);
1137
1138         r = ath9k_hw_rf_set_freq(ah, chan);
1139         if (r) {
1140                 ath_print(common, ATH_DBG_FATAL,
1141                           "Failed to set channel\n");
1142                 return false;
1143         }
1144
1145         ah->eep_ops->set_txpower(ah, chan,
1146                              ath9k_regd_get_ctl(regulatory, chan),
1147                              channel->max_antenna_gain * 2,
1148                              channel->max_power * 2,
1149                              min((u32) MAX_RATE_POWER,
1150                              (u32) regulatory->power_limit));
1151
1152         ath9k_hw_rfbus_done(ah);
1153
1154         if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1155                 ath9k_hw_set_delta_slope(ah, chan);
1156
1157         ath9k_hw_spur_mitigate_freq(ah, chan);
1158
1159         if (!chan->oneTimeCalsDone)
1160                 chan->oneTimeCalsDone = true;
1161
1162         return true;
1163 }
1164
1165 bool ath9k_hw_check_alive(struct ath_hw *ah)
1166 {
1167         int count = 50;
1168         u32 reg;
1169
1170         if (AR_SREV_9285_10_OR_LATER(ah))
1171                 return true;
1172
1173         do {
1174                 reg = REG_READ(ah, AR_OBS_BUS_1);
1175
1176                 if ((reg & 0x7E7FFFEF) == 0x00702400)
1177                         continue;
1178
1179                 switch (reg & 0x7E000B00) {
1180                 case 0x1E000000:
1181                 case 0x52000B00:
1182                 case 0x18000B00:
1183                         continue;
1184                 default:
1185                         return true;
1186                 }
1187         } while (count-- > 0);
1188
1189         return false;
1190 }
1191 EXPORT_SYMBOL(ath9k_hw_check_alive);
1192
1193 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1194                     bool bChannelChange)
1195 {
1196         struct ath_common *common = ath9k_hw_common(ah);
1197         u32 saveLedState;
1198         struct ath9k_channel *curchan = ah->curchan;
1199         u32 saveDefAntenna;
1200         u32 macStaId1;
1201         u64 tsf = 0;
1202         int i, r;
1203
1204         ah->txchainmask = common->tx_chainmask;
1205         ah->rxchainmask = common->rx_chainmask;
1206
1207         if (!ah->chip_fullsleep) {
1208                 ath9k_hw_abortpcurecv(ah);
1209                 if (!ath9k_hw_stopdmarecv(ah))
1210                         ath_print(common, ATH_DBG_XMIT,
1211                                 "Failed to stop receive dma\n");
1212         }
1213
1214         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1215                 return -EIO;
1216
1217         if (curchan && !ah->chip_fullsleep)
1218                 ath9k_hw_getnf(ah, curchan);
1219
1220         if (bChannelChange &&
1221             (ah->chip_fullsleep != true) &&
1222             (ah->curchan != NULL) &&
1223             (chan->channel != ah->curchan->channel) &&
1224             ((chan->channelFlags & CHANNEL_ALL) ==
1225              (ah->curchan->channelFlags & CHANNEL_ALL)) &&
1226              !(AR_SREV_9280(ah) || IS_CHAN_A_5MHZ_SPACED(chan) ||
1227              IS_CHAN_A_5MHZ_SPACED(ah->curchan))) {
1228
1229                 if (ath9k_hw_channel_change(ah, chan)) {
1230                         ath9k_hw_loadnf(ah, ah->curchan);
1231                         ath9k_hw_start_nfcal(ah);
1232                         return 0;
1233                 }
1234         }
1235
1236         saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1237         if (saveDefAntenna == 0)
1238                 saveDefAntenna = 1;
1239
1240         macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1241
1242         /* For chips on which RTC reset is done, save TSF before it gets cleared */
1243         if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1244                 tsf = ath9k_hw_gettsf64(ah);
1245
1246         saveLedState = REG_READ(ah, AR_CFG_LED) &
1247                 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1248                  AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1249
1250         ath9k_hw_mark_phy_inactive(ah);
1251
1252         /* Only required on the first reset */
1253         if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1254                 REG_WRITE(ah,
1255                           AR9271_RESET_POWER_DOWN_CONTROL,
1256                           AR9271_RADIO_RF_RST);
1257                 udelay(50);
1258         }
1259
1260         if (!ath9k_hw_chip_reset(ah, chan)) {
1261                 ath_print(common, ATH_DBG_FATAL, "Chip reset failed\n");
1262                 return -EINVAL;
1263         }
1264
1265         /* Only required on the first reset */
1266         if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1267                 ah->htc_reset_init = false;
1268                 REG_WRITE(ah,
1269                           AR9271_RESET_POWER_DOWN_CONTROL,
1270                           AR9271_GATE_MAC_CTL);
1271                 udelay(50);
1272         }
1273
1274         /* Restore TSF */
1275         if (tsf && AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1276                 ath9k_hw_settsf64(ah, tsf);
1277
1278         if (AR_SREV_9280_10_OR_LATER(ah))
1279                 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
1280
1281         r = ath9k_hw_process_ini(ah, chan);
1282         if (r)
1283                 return r;
1284
1285         /* Setup MFP options for CCMP */
1286         if (AR_SREV_9280_20_OR_LATER(ah)) {
1287                 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1288                  * frames when constructing CCMP AAD. */
1289                 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
1290                               0xc7ff);
1291                 ah->sw_mgmt_crypto = false;
1292         } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1293                 /* Disable hardware crypto for management frames */
1294                 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
1295                             AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
1296                 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1297                             AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
1298                 ah->sw_mgmt_crypto = true;
1299         } else
1300                 ah->sw_mgmt_crypto = true;
1301
1302         if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1303                 ath9k_hw_set_delta_slope(ah, chan);
1304
1305         ath9k_hw_spur_mitigate_freq(ah, chan);
1306         ah->eep_ops->set_board_values(ah, chan);
1307
1308         ath9k_hw_set_operating_mode(ah, ah->opmode);
1309
1310         ENABLE_REGWRITE_BUFFER(ah);
1311
1312         REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
1313         REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
1314                   | macStaId1
1315                   | AR_STA_ID1_RTS_USE_DEF
1316                   | (ah->config.
1317                      ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
1318                   | ah->sta_id1_defaults);
1319         ath_hw_setbssidmask(common);
1320         REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
1321         ath9k_hw_write_associd(ah);
1322         REG_WRITE(ah, AR_ISR, ~0);
1323         REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
1324
1325         REGWRITE_BUFFER_FLUSH(ah);
1326         DISABLE_REGWRITE_BUFFER(ah);
1327
1328         r = ath9k_hw_rf_set_freq(ah, chan);
1329         if (r)
1330                 return r;
1331
1332         ENABLE_REGWRITE_BUFFER(ah);
1333
1334         for (i = 0; i < AR_NUM_DCU; i++)
1335                 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
1336
1337         REGWRITE_BUFFER_FLUSH(ah);
1338         DISABLE_REGWRITE_BUFFER(ah);
1339
1340         ah->intr_txqs = 0;
1341         for (i = 0; i < ah->caps.total_queues; i++)
1342                 ath9k_hw_resettxqueue(ah, i);
1343
1344         ath9k_hw_init_interrupt_masks(ah, ah->opmode);
1345         ath9k_hw_init_qos(ah);
1346
1347         if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1348                 ath9k_enable_rfkill(ah);
1349
1350         ath9k_hw_init_global_settings(ah);
1351
1352         if (!AR_SREV_9300_20_OR_LATER(ah)) {
1353                 ar9002_hw_enable_async_fifo(ah);
1354                 ar9002_hw_enable_wep_aggregation(ah);
1355         }
1356
1357         REG_WRITE(ah, AR_STA_ID1,
1358                   REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
1359
1360         ath9k_hw_set_dma(ah);
1361
1362         REG_WRITE(ah, AR_OBS, 8);
1363
1364         if (ah->config.rx_intr_mitigation) {
1365                 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
1366                 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
1367         }
1368
1369         if (ah->config.tx_intr_mitigation) {
1370                 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300);
1371                 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750);
1372         }
1373
1374         ath9k_hw_init_bb(ah, chan);
1375
1376         if (!ath9k_hw_init_cal(ah, chan))
1377                 return -EIO;
1378
1379         ENABLE_REGWRITE_BUFFER(ah);
1380
1381         ath9k_hw_restore_chainmask(ah);
1382         REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
1383
1384         REGWRITE_BUFFER_FLUSH(ah);
1385         DISABLE_REGWRITE_BUFFER(ah);
1386
1387         /*
1388          * For big endian systems turn on swapping for descriptors
1389          */
1390         if (AR_SREV_9100(ah)) {
1391                 u32 mask;
1392                 mask = REG_READ(ah, AR_CFG);
1393                 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
1394                         ath_print(common, ATH_DBG_RESET,
1395                                 "CFG Byte Swap Set 0x%x\n", mask);
1396                 } else {
1397                         mask =
1398                                 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
1399                         REG_WRITE(ah, AR_CFG, mask);
1400                         ath_print(common, ATH_DBG_RESET,
1401                                 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
1402                 }
1403         } else {
1404                 /* Configure AR9271 target WLAN */
1405                 if (AR_SREV_9271(ah))
1406                         REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
1407 #ifdef __BIG_ENDIAN
1408                 else
1409                         REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1410 #endif
1411         }
1412
1413         if (ah->btcoex_hw.enabled)
1414                 ath9k_hw_btcoex_enable(ah);
1415
1416         if (AR_SREV_9300_20_OR_LATER(ah)) {
1417                 ath9k_hw_loadnf(ah, curchan);
1418                 ath9k_hw_start_nfcal(ah);
1419         }
1420
1421         return 0;
1422 }
1423 EXPORT_SYMBOL(ath9k_hw_reset);
1424
1425 /************************/
1426 /* Key Cache Management */
1427 /************************/
1428
1429 bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
1430 {
1431         u32 keyType;
1432
1433         if (entry >= ah->caps.keycache_size) {
1434                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1435                           "keychache entry %u out of range\n", entry);
1436                 return false;
1437         }
1438
1439         keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
1440
1441         REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
1442         REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
1443         REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
1444         REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
1445         REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
1446         REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
1447         REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
1448         REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
1449
1450         if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
1451                 u16 micentry = entry + 64;
1452
1453                 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
1454                 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
1455                 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
1456                 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
1457
1458         }
1459
1460         return true;
1461 }
1462 EXPORT_SYMBOL(ath9k_hw_keyreset);
1463
1464 bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
1465 {
1466         u32 macHi, macLo;
1467
1468         if (entry >= ah->caps.keycache_size) {
1469                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1470                           "keychache entry %u out of range\n", entry);
1471                 return false;
1472         }
1473
1474         if (mac != NULL) {
1475                 macHi = (mac[5] << 8) | mac[4];
1476                 macLo = (mac[3] << 24) |
1477                         (mac[2] << 16) |
1478                         (mac[1] << 8) |
1479                         mac[0];
1480                 macLo >>= 1;
1481                 macLo |= (macHi & 1) << 31;
1482                 macHi >>= 1;
1483         } else {
1484                 macLo = macHi = 0;
1485         }
1486         REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
1487         REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
1488
1489         return true;
1490 }
1491 EXPORT_SYMBOL(ath9k_hw_keysetmac);
1492
1493 bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
1494                                  const struct ath9k_keyval *k,
1495                                  const u8 *mac)
1496 {
1497         const struct ath9k_hw_capabilities *pCap = &ah->caps;
1498         struct ath_common *common = ath9k_hw_common(ah);
1499         u32 key0, key1, key2, key3, key4;
1500         u32 keyType;
1501
1502         if (entry >= pCap->keycache_size) {
1503                 ath_print(common, ATH_DBG_FATAL,
1504                           "keycache entry %u out of range\n", entry);
1505                 return false;
1506         }
1507
1508         switch (k->kv_type) {
1509         case ATH9K_CIPHER_AES_OCB:
1510                 keyType = AR_KEYTABLE_TYPE_AES;
1511                 break;
1512         case ATH9K_CIPHER_AES_CCM:
1513                 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
1514                         ath_print(common, ATH_DBG_ANY,
1515                                   "AES-CCM not supported by mac rev 0x%x\n",
1516                                   ah->hw_version.macRev);
1517                         return false;
1518                 }
1519                 keyType = AR_KEYTABLE_TYPE_CCM;
1520                 break;
1521         case ATH9K_CIPHER_TKIP:
1522                 keyType = AR_KEYTABLE_TYPE_TKIP;
1523                 if (ATH9K_IS_MIC_ENABLED(ah)
1524                     && entry + 64 >= pCap->keycache_size) {
1525                         ath_print(common, ATH_DBG_ANY,
1526                                   "entry %u inappropriate for TKIP\n", entry);
1527                         return false;
1528                 }
1529                 break;
1530         case ATH9K_CIPHER_WEP:
1531                 if (k->kv_len < WLAN_KEY_LEN_WEP40) {
1532                         ath_print(common, ATH_DBG_ANY,
1533                                   "WEP key length %u too small\n", k->kv_len);
1534                         return false;
1535                 }
1536                 if (k->kv_len <= WLAN_KEY_LEN_WEP40)
1537                         keyType = AR_KEYTABLE_TYPE_40;
1538                 else if (k->kv_len <= WLAN_KEY_LEN_WEP104)
1539                         keyType = AR_KEYTABLE_TYPE_104;
1540                 else
1541                         keyType = AR_KEYTABLE_TYPE_128;
1542                 break;
1543         case ATH9K_CIPHER_CLR:
1544                 keyType = AR_KEYTABLE_TYPE_CLR;
1545                 break;
1546         default:
1547                 ath_print(common, ATH_DBG_FATAL,
1548                           "cipher %u not supported\n", k->kv_type);
1549                 return false;
1550         }
1551
1552         key0 = get_unaligned_le32(k->kv_val + 0);
1553         key1 = get_unaligned_le16(k->kv_val + 4);
1554         key2 = get_unaligned_le32(k->kv_val + 6);
1555         key3 = get_unaligned_le16(k->kv_val + 10);
1556         key4 = get_unaligned_le32(k->kv_val + 12);
1557         if (k->kv_len <= WLAN_KEY_LEN_WEP104)
1558                 key4 &= 0xff;
1559
1560         /*
1561          * Note: Key cache registers access special memory area that requires
1562          * two 32-bit writes to actually update the values in the internal
1563          * memory. Consequently, the exact order and pairs used here must be
1564          * maintained.
1565          */
1566
1567         if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
1568                 u16 micentry = entry + 64;
1569
1570                 /*
1571                  * Write inverted key[47:0] first to avoid Michael MIC errors
1572                  * on frames that could be sent or received at the same time.
1573                  * The correct key will be written in the end once everything
1574                  * else is ready.
1575                  */
1576                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
1577                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
1578
1579                 /* Write key[95:48] */
1580                 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
1581                 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
1582
1583                 /* Write key[127:96] and key type */
1584                 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
1585                 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
1586
1587                 /* Write MAC address for the entry */
1588                 (void) ath9k_hw_keysetmac(ah, entry, mac);
1589
1590                 if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) {
1591                         /*
1592                          * TKIP uses two key cache entries:
1593                          * Michael MIC TX/RX keys in the same key cache entry
1594                          * (idx = main index + 64):
1595                          * key0 [31:0] = RX key [31:0]
1596                          * key1 [15:0] = TX key [31:16]
1597                          * key1 [31:16] = reserved
1598                          * key2 [31:0] = RX key [63:32]
1599                          * key3 [15:0] = TX key [15:0]
1600                          * key3 [31:16] = reserved
1601                          * key4 [31:0] = TX key [63:32]
1602                          */
1603                         u32 mic0, mic1, mic2, mic3, mic4;
1604
1605                         mic0 = get_unaligned_le32(k->kv_mic + 0);
1606                         mic2 = get_unaligned_le32(k->kv_mic + 4);
1607                         mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
1608                         mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
1609                         mic4 = get_unaligned_le32(k->kv_txmic + 4);
1610
1611                         /* Write RX[31:0] and TX[31:16] */
1612                         REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
1613                         REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
1614
1615                         /* Write RX[63:32] and TX[15:0] */
1616                         REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
1617                         REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
1618
1619                         /* Write TX[63:32] and keyType(reserved) */
1620                         REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
1621                         REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
1622                                   AR_KEYTABLE_TYPE_CLR);
1623
1624                 } else {
1625                         /*
1626                          * TKIP uses four key cache entries (two for group
1627                          * keys):
1628                          * Michael MIC TX/RX keys are in different key cache
1629                          * entries (idx = main index + 64 for TX and
1630                          * main index + 32 + 96 for RX):
1631                          * key0 [31:0] = TX/RX MIC key [31:0]
1632                          * key1 [31:0] = reserved
1633                          * key2 [31:0] = TX/RX MIC key [63:32]
1634                          * key3 [31:0] = reserved
1635                          * key4 [31:0] = reserved
1636                          *
1637                          * Upper layer code will call this function separately
1638                          * for TX and RX keys when these registers offsets are
1639                          * used.
1640                          */
1641                         u32 mic0, mic2;
1642
1643                         mic0 = get_unaligned_le32(k->kv_mic + 0);
1644                         mic2 = get_unaligned_le32(k->kv_mic + 4);
1645
1646                         /* Write MIC key[31:0] */
1647                         REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
1648                         REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
1649
1650                         /* Write MIC key[63:32] */
1651                         REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
1652                         REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
1653
1654                         /* Write TX[63:32] and keyType(reserved) */
1655                         REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
1656                         REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
1657                                   AR_KEYTABLE_TYPE_CLR);
1658                 }
1659
1660                 /* MAC address registers are reserved for the MIC entry */
1661                 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
1662                 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
1663
1664                 /*
1665                  * Write the correct (un-inverted) key[47:0] last to enable
1666                  * TKIP now that all other registers are set with correct
1667                  * values.
1668                  */
1669                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
1670                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
1671         } else {
1672                 /* Write key[47:0] */
1673                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
1674                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
1675
1676                 /* Write key[95:48] */
1677                 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
1678                 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
1679
1680                 /* Write key[127:96] and key type */
1681                 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
1682                 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
1683
1684                 /* Write MAC address for the entry */
1685                 (void) ath9k_hw_keysetmac(ah, entry, mac);
1686         }
1687
1688         return true;
1689 }
1690 EXPORT_SYMBOL(ath9k_hw_set_keycache_entry);
1691
1692 bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry)
1693 {
1694         if (entry < ah->caps.keycache_size) {
1695                 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
1696                 if (val & AR_KEYTABLE_VALID)
1697                         return true;
1698         }
1699         return false;
1700 }
1701 EXPORT_SYMBOL(ath9k_hw_keyisvalid);
1702
1703 /******************************/
1704 /* Power Management (Chipset) */
1705 /******************************/
1706
1707 /*
1708  * Notify Power Mgt is disabled in self-generated frames.
1709  * If requested, force chip to sleep.
1710  */
1711 static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
1712 {
1713         REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1714         if (setChip) {
1715                 /*
1716                  * Clear the RTC force wake bit to allow the
1717                  * mac to go to sleep.
1718                  */
1719                 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
1720                             AR_RTC_FORCE_WAKE_EN);
1721                 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1722                         REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1723
1724                 /* Shutdown chip. Active low */
1725                 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah))
1726                         REG_CLR_BIT(ah, (AR_RTC_RESET),
1727                                     AR_RTC_RESET_EN);
1728         }
1729 }
1730
1731 /*
1732  * Notify Power Management is enabled in self-generating
1733  * frames. If request, set power mode of chip to
1734  * auto/normal.  Duration in units of 128us (1/8 TU).
1735  */
1736 static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
1737 {
1738         REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1739         if (setChip) {
1740                 struct ath9k_hw_capabilities *pCap = &ah->caps;
1741
1742                 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1743                         /* Set WakeOnInterrupt bit; clear ForceWake bit */
1744                         REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1745                                   AR_RTC_FORCE_WAKE_ON_INT);
1746                 } else {
1747                         /*
1748                          * Clear the RTC force wake bit to allow the
1749                          * mac to go to sleep.
1750                          */
1751                         REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
1752                                     AR_RTC_FORCE_WAKE_EN);
1753                 }
1754         }
1755 }
1756
1757 static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
1758 {
1759         u32 val;
1760         int i;
1761
1762         if (setChip) {
1763                 if ((REG_READ(ah, AR_RTC_STATUS) &
1764                      AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
1765                         if (ath9k_hw_set_reset_reg(ah,
1766                                            ATH9K_RESET_POWER_ON) != true) {
1767                                 return false;
1768                         }
1769                         if (!AR_SREV_9300_20_OR_LATER(ah))
1770                                 ath9k_hw_init_pll(ah, NULL);
1771                 }
1772                 if (AR_SREV_9100(ah))
1773                         REG_SET_BIT(ah, AR_RTC_RESET,
1774                                     AR_RTC_RESET_EN);
1775
1776                 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
1777                             AR_RTC_FORCE_WAKE_EN);
1778                 udelay(50);
1779
1780                 for (i = POWER_UP_TIME / 50; i > 0; i--) {
1781                         val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
1782                         if (val == AR_RTC_STATUS_ON)
1783                                 break;
1784                         udelay(50);
1785                         REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
1786                                     AR_RTC_FORCE_WAKE_EN);
1787                 }
1788                 if (i == 0) {
1789                         ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1790                                   "Failed to wakeup in %uus\n",
1791                                   POWER_UP_TIME / 20);
1792                         return false;
1793                 }
1794         }
1795
1796         REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1797
1798         return true;
1799 }
1800
1801 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
1802 {
1803         struct ath_common *common = ath9k_hw_common(ah);
1804         int status = true, setChip = true;
1805         static const char *modes[] = {
1806                 "AWAKE",
1807                 "FULL-SLEEP",
1808                 "NETWORK SLEEP",
1809                 "UNDEFINED"
1810         };
1811
1812         if (ah->power_mode == mode)
1813                 return status;
1814
1815         ath_print(common, ATH_DBG_RESET, "%s -> %s\n",
1816                   modes[ah->power_mode], modes[mode]);
1817
1818         switch (mode) {
1819         case ATH9K_PM_AWAKE:
1820                 status = ath9k_hw_set_power_awake(ah, setChip);
1821                 break;
1822         case ATH9K_PM_FULL_SLEEP:
1823                 ath9k_set_power_sleep(ah, setChip);
1824                 ah->chip_fullsleep = true;
1825                 break;
1826         case ATH9K_PM_NETWORK_SLEEP:
1827                 ath9k_set_power_network_sleep(ah, setChip);
1828                 break;
1829         default:
1830                 ath_print(common, ATH_DBG_FATAL,
1831                           "Unknown power mode %u\n", mode);
1832                 return false;
1833         }
1834         ah->power_mode = mode;
1835
1836         return status;
1837 }
1838 EXPORT_SYMBOL(ath9k_hw_setpower);
1839
1840 /*******************/
1841 /* Beacon Handling */
1842 /*******************/
1843
1844 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
1845 {
1846         int flags = 0;
1847
1848         ah->beacon_interval = beacon_period;
1849
1850         ENABLE_REGWRITE_BUFFER(ah);
1851
1852         switch (ah->opmode) {
1853         case NL80211_IFTYPE_STATION:
1854         case NL80211_IFTYPE_MONITOR:
1855                 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
1856                 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
1857                 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
1858                 flags |= AR_TBTT_TIMER_EN;
1859                 break;
1860         case NL80211_IFTYPE_ADHOC:
1861         case NL80211_IFTYPE_MESH_POINT:
1862                 REG_SET_BIT(ah, AR_TXCFG,
1863                             AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
1864                 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
1865                           TU_TO_USEC(next_beacon +
1866                                      (ah->atim_window ? ah->
1867                                       atim_window : 1)));
1868                 flags |= AR_NDP_TIMER_EN;
1869         case NL80211_IFTYPE_AP:
1870                 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
1871                 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
1872                           TU_TO_USEC(next_beacon -
1873                                      ah->config.
1874                                      dma_beacon_response_time));
1875                 REG_WRITE(ah, AR_NEXT_SWBA,
1876                           TU_TO_USEC(next_beacon -
1877                                      ah->config.
1878                                      sw_beacon_response_time));
1879                 flags |=
1880                         AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
1881                 break;
1882         default:
1883                 ath_print(ath9k_hw_common(ah), ATH_DBG_BEACON,
1884                           "%s: unsupported opmode: %d\n",
1885                           __func__, ah->opmode);
1886                 return;
1887                 break;
1888         }
1889
1890         REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
1891         REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
1892         REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
1893         REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
1894
1895         REGWRITE_BUFFER_FLUSH(ah);
1896         DISABLE_REGWRITE_BUFFER(ah);
1897
1898         beacon_period &= ~ATH9K_BEACON_ENA;
1899         if (beacon_period & ATH9K_BEACON_RESET_TSF) {
1900                 ath9k_hw_reset_tsf(ah);
1901         }
1902
1903         REG_SET_BIT(ah, AR_TIMER_MODE, flags);
1904 }
1905 EXPORT_SYMBOL(ath9k_hw_beaconinit);
1906
1907 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
1908                                     const struct ath9k_beacon_state *bs)
1909 {
1910         u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
1911         struct ath9k_hw_capabilities *pCap = &ah->caps;
1912         struct ath_common *common = ath9k_hw_common(ah);
1913
1914         ENABLE_REGWRITE_BUFFER(ah);
1915
1916         REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
1917
1918         REG_WRITE(ah, AR_BEACON_PERIOD,
1919                   TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
1920         REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
1921                   TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
1922
1923         REGWRITE_BUFFER_FLUSH(ah);
1924         DISABLE_REGWRITE_BUFFER(ah);
1925
1926         REG_RMW_FIELD(ah, AR_RSSI_THR,
1927                       AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
1928
1929         beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
1930
1931         if (bs->bs_sleepduration > beaconintval)
1932                 beaconintval = bs->bs_sleepduration;
1933
1934         dtimperiod = bs->bs_dtimperiod;
1935         if (bs->bs_sleepduration > dtimperiod)
1936                 dtimperiod = bs->bs_sleepduration;
1937
1938         if (beaconintval == dtimperiod)
1939                 nextTbtt = bs->bs_nextdtim;
1940         else
1941                 nextTbtt = bs->bs_nexttbtt;
1942
1943         ath_print(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
1944         ath_print(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
1945         ath_print(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
1946         ath_print(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
1947
1948         ENABLE_REGWRITE_BUFFER(ah);
1949
1950         REG_WRITE(ah, AR_NEXT_DTIM,
1951                   TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
1952         REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
1953
1954         REG_WRITE(ah, AR_SLEEP1,
1955                   SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
1956                   | AR_SLEEP1_ASSUME_DTIM);
1957
1958         if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
1959                 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
1960         else
1961                 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
1962
1963         REG_WRITE(ah, AR_SLEEP2,
1964                   SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
1965
1966         REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
1967         REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
1968
1969         REGWRITE_BUFFER_FLUSH(ah);
1970         DISABLE_REGWRITE_BUFFER(ah);
1971
1972         REG_SET_BIT(ah, AR_TIMER_MODE,
1973                     AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
1974                     AR_DTIM_TIMER_EN);
1975
1976         /* TSF Out of Range Threshold */
1977         REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
1978 }
1979 EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
1980
1981 /*******************/
1982 /* HW Capabilities */
1983 /*******************/
1984
1985 int ath9k_hw_fill_cap_info(struct ath_hw *ah)
1986 {
1987         struct ath9k_hw_capabilities *pCap = &ah->caps;
1988         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1989         struct ath_common *common = ath9k_hw_common(ah);
1990         struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
1991
1992         u16 capField = 0, eeval;
1993
1994         eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
1995         regulatory->current_rd = eeval;
1996
1997         eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
1998         if (AR_SREV_9285_10_OR_LATER(ah))
1999                 eeval |= AR9285_RDEXT_DEFAULT;
2000         regulatory->current_rd_ext = eeval;
2001
2002         capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
2003
2004         if (ah->opmode != NL80211_IFTYPE_AP &&
2005             ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
2006                 if (regulatory->current_rd == 0x64 ||
2007                     regulatory->current_rd == 0x65)
2008                         regulatory->current_rd += 5;
2009                 else if (regulatory->current_rd == 0x41)
2010                         regulatory->current_rd = 0x43;
2011                 ath_print(common, ATH_DBG_REGULATORY,
2012                           "regdomain mapped to 0x%x\n", regulatory->current_rd);
2013         }
2014
2015         eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
2016         if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
2017                 ath_print(common, ATH_DBG_FATAL,
2018                           "no band has been marked as supported in EEPROM.\n");
2019                 return -EINVAL;
2020         }
2021
2022         bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
2023
2024         if (eeval & AR5416_OPFLAGS_11A) {
2025                 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
2026                 if (ah->config.ht_enable) {
2027                         if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
2028                                 set_bit(ATH9K_MODE_11NA_HT20,
2029                                         pCap->wireless_modes);
2030                         if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
2031                                 set_bit(ATH9K_MODE_11NA_HT40PLUS,
2032                                         pCap->wireless_modes);
2033                                 set_bit(ATH9K_MODE_11NA_HT40MINUS,
2034                                         pCap->wireless_modes);
2035                         }
2036                 }
2037         }
2038
2039         if (eeval & AR5416_OPFLAGS_11G) {
2040                 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
2041                 if (ah->config.ht_enable) {
2042                         if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
2043                                 set_bit(ATH9K_MODE_11NG_HT20,
2044                                         pCap->wireless_modes);
2045                         if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
2046                                 set_bit(ATH9K_MODE_11NG_HT40PLUS,
2047                                         pCap->wireless_modes);
2048                                 set_bit(ATH9K_MODE_11NG_HT40MINUS,
2049                                         pCap->wireless_modes);
2050                         }
2051                 }
2052         }
2053
2054         pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
2055         /*
2056          * For AR9271 we will temporarilly uses the rx chainmax as read from
2057          * the EEPROM.
2058          */
2059         if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
2060             !(eeval & AR5416_OPFLAGS_11A) &&
2061             !(AR_SREV_9271(ah)))
2062                 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
2063                 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
2064         else
2065                 /* Use rx_chainmask from EEPROM. */
2066                 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
2067
2068         if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0)))
2069                 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
2070
2071         pCap->low_2ghz_chan = 2312;
2072         pCap->high_2ghz_chan = 2732;
2073
2074         pCap->low_5ghz_chan = 4920;
2075         pCap->high_5ghz_chan = 6100;
2076
2077         pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
2078         pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
2079         pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
2080
2081         pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
2082         pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
2083         pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
2084
2085         if (ah->config.ht_enable)
2086                 pCap->hw_caps |= ATH9K_HW_CAP_HT;
2087         else
2088                 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
2089
2090         pCap->hw_caps |= ATH9K_HW_CAP_GTT;
2091         pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
2092         pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
2093         pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
2094
2095         if (capField & AR_EEPROM_EEPCAP_MAXQCU)
2096                 pCap->total_queues =
2097                         MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
2098         else
2099                 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
2100
2101         if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
2102                 pCap->keycache_size =
2103                         1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
2104         else
2105                 pCap->keycache_size = AR_KEYTABLE_SIZE;
2106
2107         pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
2108
2109         if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
2110                 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD >> 1;
2111         else
2112                 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
2113
2114         if (AR_SREV_9271(ah))
2115                 pCap->num_gpio_pins = AR9271_NUM_GPIO;
2116         else if (AR_SREV_9285_10_OR_LATER(ah))
2117                 pCap->num_gpio_pins = AR9285_NUM_GPIO;
2118         else if (AR_SREV_9280_10_OR_LATER(ah))
2119                 pCap->num_gpio_pins = AR928X_NUM_GPIO;
2120         else
2121                 pCap->num_gpio_pins = AR_NUM_GPIO;
2122
2123         if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
2124                 pCap->hw_caps |= ATH9K_HW_CAP_CST;
2125                 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
2126         } else {
2127                 pCap->rts_aggr_limit = (8 * 1024);
2128         }
2129
2130         pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
2131
2132 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2133         ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
2134         if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
2135                 ah->rfkill_gpio =
2136                         MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
2137                 ah->rfkill_polarity =
2138                         MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
2139
2140                 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
2141         }
2142 #endif
2143         if (AR_SREV_9271(ah))
2144                 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
2145         else
2146                 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
2147
2148         if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
2149                 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
2150         else
2151                 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
2152
2153         if (regulatory->current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
2154                 pCap->reg_cap =
2155                         AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
2156                         AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
2157                         AR_EEPROM_EEREGCAP_EN_KK_U2 |
2158                         AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
2159         } else {
2160                 pCap->reg_cap =
2161                         AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
2162                         AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
2163         }
2164
2165         /* Advertise midband for AR5416 with FCC midband set in eeprom */
2166         if (regulatory->current_rd_ext & (1 << REG_EXT_FCC_MIDBAND) &&
2167             AR_SREV_5416(ah))
2168                 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
2169
2170         pCap->num_antcfg_5ghz =
2171                 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
2172         pCap->num_antcfg_2ghz =
2173                 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
2174
2175         if (AR_SREV_9280_10_OR_LATER(ah) &&
2176             ath9k_hw_btcoex_supported(ah)) {
2177                 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO;
2178                 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO;
2179
2180                 if (AR_SREV_9285(ah)) {
2181                         btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
2182                         btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO;
2183                 } else {
2184                         btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE;
2185                 }
2186         } else {
2187                 btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE;
2188         }
2189
2190         if (AR_SREV_9300_20_OR_LATER(ah)) {
2191                 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_LDPC;
2192                 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
2193                 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
2194                 pCap->rx_status_len = sizeof(struct ar9003_rxs);
2195                 pCap->tx_desc_len = sizeof(struct ar9003_txc);
2196                 pCap->txs_len = sizeof(struct ar9003_txs);
2197         } else {
2198                 pCap->tx_desc_len = sizeof(struct ath_desc);
2199         }
2200
2201         if (AR_SREV_9300_20_OR_LATER(ah))
2202                 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;
2203
2204         return 0;
2205 }
2206
2207 bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
2208                             u32 capability, u32 *result)
2209 {
2210         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2211         switch (type) {
2212         case ATH9K_CAP_CIPHER:
2213                 switch (capability) {
2214                 case ATH9K_CIPHER_AES_CCM:
2215                 case ATH9K_CIPHER_AES_OCB:
2216                 case ATH9K_CIPHER_TKIP:
2217                 case ATH9K_CIPHER_WEP:
2218                 case ATH9K_CIPHER_MIC:
2219                 case ATH9K_CIPHER_CLR:
2220                         return true;
2221                 default:
2222                         return false;
2223                 }
2224         case ATH9K_CAP_TKIP_MIC:
2225                 switch (capability) {
2226                 case 0:
2227                         return true;
2228                 case 1:
2229                         return (ah->sta_id1_defaults &
2230                                 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
2231                         false;
2232                 }
2233         case ATH9K_CAP_TKIP_SPLIT:
2234                 return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
2235                         false : true;
2236         case ATH9K_CAP_MCAST_KEYSRCH:
2237                 switch (capability) {
2238                 case 0:
2239                         return true;
2240                 case 1:
2241                         if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
2242                                 return false;
2243                         } else {
2244                                 return (ah->sta_id1_defaults &
2245                                         AR_STA_ID1_MCAST_KSRCH) ? true :
2246                                         false;
2247                         }
2248                 }
2249                 return false;
2250         case ATH9K_CAP_TXPOW:
2251                 switch (capability) {
2252                 case 0:
2253                         return 0;
2254                 case 1:
2255                         *result = regulatory->power_limit;
2256                         return 0;
2257                 case 2:
2258                         *result = regulatory->max_power_level;
2259                         return 0;
2260                 case 3:
2261                         *result = regulatory->tp_scale;
2262                         return 0;
2263                 }
2264                 return false;
2265         case ATH9K_CAP_DS:
2266                 return (AR_SREV_9280_20_OR_LATER(ah) &&
2267                         (ah->eep_ops->get_eeprom(ah, EEP_RC_CHAIN_MASK) == 1))
2268                         ? false : true;
2269         default:
2270                 return false;
2271         }
2272 }
2273 EXPORT_SYMBOL(ath9k_hw_getcapability);
2274
2275 bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
2276                             u32 capability, u32 setting, int *status)
2277 {
2278         switch (type) {
2279         case ATH9K_CAP_TKIP_MIC:
2280                 if (setting)
2281                         ah->sta_id1_defaults |=
2282                                 AR_STA_ID1_CRPT_MIC_ENABLE;
2283                 else
2284                         ah->sta_id1_defaults &=
2285                                 ~AR_STA_ID1_CRPT_MIC_ENABLE;
2286                 return true;
2287         case ATH9K_CAP_MCAST_KEYSRCH:
2288                 if (setting)
2289                         ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH;
2290                 else
2291                         ah->sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH;
2292                 return true;
2293         default:
2294                 return false;
2295         }
2296 }
2297 EXPORT_SYMBOL(ath9k_hw_setcapability);
2298
2299 /****************************/
2300 /* GPIO / RFKILL / Antennae */
2301 /****************************/
2302
2303 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
2304                                          u32 gpio, u32 type)
2305 {
2306         int addr;
2307         u32 gpio_shift, tmp;
2308
2309         if (gpio > 11)
2310                 addr = AR_GPIO_OUTPUT_MUX3;
2311         else if (gpio > 5)
2312                 addr = AR_GPIO_OUTPUT_MUX2;
2313         else
2314                 addr = AR_GPIO_OUTPUT_MUX1;
2315
2316         gpio_shift = (gpio % 6) * 5;
2317
2318         if (AR_SREV_9280_20_OR_LATER(ah)
2319             || (addr != AR_GPIO_OUTPUT_MUX1)) {
2320                 REG_RMW(ah, addr, (type << gpio_shift),
2321                         (0x1f << gpio_shift));
2322         } else {
2323                 tmp = REG_READ(ah, addr);
2324                 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
2325                 tmp &= ~(0x1f << gpio_shift);
2326                 tmp |= (type << gpio_shift);
2327                 REG_WRITE(ah, addr, tmp);
2328         }
2329 }
2330
2331 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
2332 {
2333         u32 gpio_shift;
2334
2335         BUG_ON(gpio >= ah->caps.num_gpio_pins);
2336
2337         gpio_shift = gpio << 1;
2338
2339         REG_RMW(ah,
2340                 AR_GPIO_OE_OUT,
2341                 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
2342                 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2343 }
2344 EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
2345
2346 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
2347 {
2348 #define MS_REG_READ(x, y) \
2349         (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
2350
2351         if (gpio >= ah->caps.num_gpio_pins)
2352                 return 0xffffffff;
2353
2354         if (AR_SREV_9300_20_OR_LATER(ah))
2355                 return MS_REG_READ(AR9300, gpio) != 0;
2356         else if (AR_SREV_9271(ah))
2357                 return MS_REG_READ(AR9271, gpio) != 0;
2358         else if (AR_SREV_9287_10_OR_LATER(ah))
2359                 return MS_REG_READ(AR9287, gpio) != 0;
2360         else if (AR_SREV_9285_10_OR_LATER(ah))
2361                 return MS_REG_READ(AR9285, gpio) != 0;
2362         else if (AR_SREV_9280_10_OR_LATER(ah))
2363                 return MS_REG_READ(AR928X, gpio) != 0;
2364         else
2365                 return MS_REG_READ(AR, gpio) != 0;
2366 }
2367 EXPORT_SYMBOL(ath9k_hw_gpio_get);
2368
2369 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
2370                          u32 ah_signal_type)
2371 {
2372         u32 gpio_shift;
2373
2374         ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
2375
2376         gpio_shift = 2 * gpio;
2377
2378         REG_RMW(ah,
2379                 AR_GPIO_OE_OUT,
2380                 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
2381                 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2382 }
2383 EXPORT_SYMBOL(ath9k_hw_cfg_output);
2384
2385 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
2386 {
2387         if (AR_SREV_9271(ah))
2388                 val = ~val;
2389
2390         REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
2391                 AR_GPIO_BIT(gpio));
2392 }
2393 EXPORT_SYMBOL(ath9k_hw_set_gpio);
2394
2395 u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
2396 {
2397         return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
2398 }
2399 EXPORT_SYMBOL(ath9k_hw_getdefantenna);
2400
2401 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
2402 {
2403         REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
2404 }
2405 EXPORT_SYMBOL(ath9k_hw_setantenna);
2406
2407 /*********************/
2408 /* General Operation */
2409 /*********************/
2410
2411 u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
2412 {
2413         u32 bits = REG_READ(ah, AR_RX_FILTER);
2414         u32 phybits = REG_READ(ah, AR_PHY_ERR);
2415
2416         if (phybits & AR_PHY_ERR_RADAR)
2417                 bits |= ATH9K_RX_FILTER_PHYRADAR;
2418         if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
2419                 bits |= ATH9K_RX_FILTER_PHYERR;
2420
2421         return bits;
2422 }
2423 EXPORT_SYMBOL(ath9k_hw_getrxfilter);
2424
2425 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
2426 {
2427         u32 phybits;
2428
2429         ENABLE_REGWRITE_BUFFER(ah);
2430
2431         REG_WRITE(ah, AR_RX_FILTER, bits);
2432
2433         phybits = 0;
2434         if (bits & ATH9K_RX_FILTER_PHYRADAR)
2435                 phybits |= AR_PHY_ERR_RADAR;
2436         if (bits & ATH9K_RX_FILTER_PHYERR)
2437                 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
2438         REG_WRITE(ah, AR_PHY_ERR, phybits);
2439
2440         if (phybits)
2441                 REG_WRITE(ah, AR_RXCFG,
2442                           REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
2443         else
2444                 REG_WRITE(ah, AR_RXCFG,
2445                           REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
2446
2447         REGWRITE_BUFFER_FLUSH(ah);
2448         DISABLE_REGWRITE_BUFFER(ah);
2449 }
2450 EXPORT_SYMBOL(ath9k_hw_setrxfilter);
2451
2452 bool ath9k_hw_phy_disable(struct ath_hw *ah)
2453 {
2454         if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
2455                 return false;
2456
2457         ath9k_hw_init_pll(ah, NULL);
2458         return true;
2459 }
2460 EXPORT_SYMBOL(ath9k_hw_phy_disable);
2461
2462 bool ath9k_hw_disable(struct ath_hw *ah)
2463 {
2464         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
2465                 return false;
2466
2467         if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
2468                 return false;
2469
2470         ath9k_hw_init_pll(ah, NULL);
2471         return true;
2472 }
2473 EXPORT_SYMBOL(ath9k_hw_disable);
2474
2475 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
2476 {
2477         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2478         struct ath9k_channel *chan = ah->curchan;
2479         struct ieee80211_channel *channel = chan->chan;
2480
2481         regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER);
2482
2483         ah->eep_ops->set_txpower(ah, chan,
2484                                  ath9k_regd_get_ctl(regulatory, chan),
2485                                  channel->max_antenna_gain * 2,
2486                                  channel->max_power * 2,
2487                                  min((u32) MAX_RATE_POWER,
2488                                  (u32) regulatory->power_limit));
2489 }
2490 EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
2491
2492 void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac)
2493 {
2494         memcpy(ath9k_hw_common(ah)->macaddr, mac, ETH_ALEN);
2495 }
2496 EXPORT_SYMBOL(ath9k_hw_setmac);
2497
2498 void ath9k_hw_setopmode(struct ath_hw *ah)
2499 {
2500         ath9k_hw_set_operating_mode(ah, ah->opmode);
2501 }
2502 EXPORT_SYMBOL(ath9k_hw_setopmode);
2503
2504 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
2505 {
2506         REG_WRITE(ah, AR_MCAST_FIL0, filter0);
2507         REG_WRITE(ah, AR_MCAST_FIL1, filter1);
2508 }
2509 EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
2510
2511 void ath9k_hw_write_associd(struct ath_hw *ah)
2512 {
2513         struct ath_common *common = ath9k_hw_common(ah);
2514
2515         REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
2516         REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
2517                   ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
2518 }
2519 EXPORT_SYMBOL(ath9k_hw_write_associd);
2520
2521 #define ATH9K_MAX_TSF_READ 10
2522
2523 u64 ath9k_hw_gettsf64(struct ath_hw *ah)
2524 {
2525         u32 tsf_lower, tsf_upper1, tsf_upper2;
2526         int i;
2527
2528         tsf_upper1 = REG_READ(ah, AR_TSF_U32);
2529         for (i = 0; i < ATH9K_MAX_TSF_READ; i++) {
2530                 tsf_lower = REG_READ(ah, AR_TSF_L32);
2531                 tsf_upper2 = REG_READ(ah, AR_TSF_U32);
2532                 if (tsf_upper2 == tsf_upper1)
2533                         break;
2534                 tsf_upper1 = tsf_upper2;
2535         }
2536
2537         WARN_ON( i == ATH9K_MAX_TSF_READ );
2538
2539         return (((u64)tsf_upper1 << 32) | tsf_lower);
2540 }
2541 EXPORT_SYMBOL(ath9k_hw_gettsf64);
2542
2543 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
2544 {
2545         REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
2546         REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
2547 }
2548 EXPORT_SYMBOL(ath9k_hw_settsf64);
2549
2550 void ath9k_hw_reset_tsf(struct ath_hw *ah)
2551 {
2552         if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
2553                            AH_TSF_WRITE_TIMEOUT))
2554                 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
2555                           "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
2556
2557         REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
2558 }
2559 EXPORT_SYMBOL(ath9k_hw_reset_tsf);
2560
2561 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
2562 {
2563         if (setting)
2564                 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
2565         else
2566                 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
2567 }
2568 EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
2569
2570 /*
2571  *  Extend 15-bit time stamp from rx descriptor to
2572  *  a full 64-bit TSF using the current h/w TSF.
2573 */
2574 u64 ath9k_hw_extend_tsf(struct ath_hw *ah, u32 rstamp)
2575 {
2576         u64 tsf;
2577
2578         tsf = ath9k_hw_gettsf64(ah);
2579         if ((tsf & 0x7fff) < rstamp)
2580                 tsf -= 0x8000;
2581         return (tsf & ~0x7fff) | rstamp;
2582 }
2583 EXPORT_SYMBOL(ath9k_hw_extend_tsf);
2584
2585 void ath9k_hw_set11nmac2040(struct ath_hw *ah)
2586 {
2587         struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
2588         u32 macmode;
2589
2590         if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca)
2591                 macmode = AR_2040_JOINED_RX_CLEAR;
2592         else
2593                 macmode = 0;
2594
2595         REG_WRITE(ah, AR_2040_MODE, macmode);
2596 }
2597
2598 /* HW Generic timers configuration */
2599
2600 static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
2601 {
2602         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2603         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2604         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2605         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2606         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2607         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2608         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2609         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2610         {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
2611         {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
2612                                 AR_NDP2_TIMER_MODE, 0x0002},
2613         {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
2614                                 AR_NDP2_TIMER_MODE, 0x0004},
2615         {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
2616                                 AR_NDP2_TIMER_MODE, 0x0008},
2617         {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
2618                                 AR_NDP2_TIMER_MODE, 0x0010},
2619         {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
2620                                 AR_NDP2_TIMER_MODE, 0x0020},
2621         {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
2622                                 AR_NDP2_TIMER_MODE, 0x0040},
2623         {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
2624                                 AR_NDP2_TIMER_MODE, 0x0080}
2625 };
2626
2627 /* HW generic timer primitives */
2628
2629 /* compute and clear index of rightmost 1 */
2630 static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
2631 {
2632         u32 b;
2633
2634         b = *mask;
2635         b &= (0-b);
2636         *mask &= ~b;
2637         b *= debruijn32;
2638         b >>= 27;
2639
2640         return timer_table->gen_timer_index[b];
2641 }
2642
2643 u32 ath9k_hw_gettsf32(struct ath_hw *ah)
2644 {
2645         return REG_READ(ah, AR_TSF_L32);
2646 }
2647 EXPORT_SYMBOL(ath9k_hw_gettsf32);
2648
2649 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
2650                                           void (*trigger)(void *),
2651                                           void (*overflow)(void *),
2652                                           void *arg,
2653                                           u8 timer_index)
2654 {
2655         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2656         struct ath_gen_timer *timer;
2657
2658         timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
2659
2660         if (timer == NULL) {
2661                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2662                           "Failed to allocate memory"
2663                           "for hw timer[%d]\n", timer_index);
2664                 return NULL;
2665         }
2666
2667         /* allocate a hardware generic timer slot */
2668         timer_table->timers[timer_index] = timer;
2669         timer->index = timer_index;
2670         timer->trigger = trigger;
2671         timer->overflow = overflow;
2672         timer->arg = arg;
2673
2674         return timer;
2675 }
2676 EXPORT_SYMBOL(ath_gen_timer_alloc);
2677
2678 void ath9k_hw_gen_timer_start(struct ath_hw *ah,
2679                               struct ath_gen_timer *timer,
2680                               u32 timer_next,
2681                               u32 timer_period)
2682 {
2683         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2684         u32 tsf;
2685
2686         BUG_ON(!timer_period);
2687
2688         set_bit(timer->index, &timer_table->timer_mask.timer_bits);
2689
2690         tsf = ath9k_hw_gettsf32(ah);
2691
2692         ath_print(ath9k_hw_common(ah), ATH_DBG_HWTIMER,
2693                   "curent tsf %x period %x"
2694                   "timer_next %x\n", tsf, timer_period, timer_next);
2695
2696         /*
2697          * Pull timer_next forward if the current TSF already passed it
2698          * because of software latency
2699          */
2700         if (timer_next < tsf)
2701                 timer_next = tsf + timer_period;
2702
2703         /*
2704          * Program generic timer registers
2705          */
2706         REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
2707                  timer_next);
2708         REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
2709                   timer_period);
2710         REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2711                     gen_tmr_configuration[timer->index].mode_mask);
2712
2713         /* Enable both trigger and thresh interrupt masks */
2714         REG_SET_BIT(ah, AR_IMR_S5,
2715                 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2716                 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
2717 }
2718 EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
2719
2720 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
2721 {
2722         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2723
2724         if ((timer->index < AR_FIRST_NDP_TIMER) ||
2725                 (timer->index >= ATH_MAX_GEN_TIMER)) {
2726                 return;
2727         }
2728
2729         /* Clear generic timer enable bits. */
2730         REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2731                         gen_tmr_configuration[timer->index].mode_mask);
2732
2733         /* Disable both trigger and thresh interrupt masks */
2734         REG_CLR_BIT(ah, AR_IMR_S5,
2735                 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2736                 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
2737
2738         clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
2739 }
2740 EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
2741
2742 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
2743 {
2744         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2745
2746         /* free the hardware generic timer slot */
2747         timer_table->timers[timer->index] = NULL;
2748         kfree(timer);
2749 }
2750 EXPORT_SYMBOL(ath_gen_timer_free);
2751
2752 /*
2753  * Generic Timer Interrupts handling
2754  */
2755 void ath_gen_timer_isr(struct ath_hw *ah)
2756 {
2757         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2758         struct ath_gen_timer *timer;
2759         struct ath_common *common = ath9k_hw_common(ah);
2760         u32 trigger_mask, thresh_mask, index;
2761
2762         /* get hardware generic timer interrupt status */
2763         trigger_mask = ah->intr_gen_timer_trigger;
2764         thresh_mask = ah->intr_gen_timer_thresh;
2765         trigger_mask &= timer_table->timer_mask.val;
2766         thresh_mask &= timer_table->timer_mask.val;
2767
2768         trigger_mask &= ~thresh_mask;
2769
2770         while (thresh_mask) {
2771                 index = rightmost_index(timer_table, &thresh_mask);
2772                 timer = timer_table->timers[index];
2773                 BUG_ON(!timer);
2774                 ath_print(common, ATH_DBG_HWTIMER,
2775                           "TSF overflow for Gen timer %d\n", index);
2776                 timer->overflow(timer->arg);
2777         }
2778
2779         while (trigger_mask) {
2780                 index = rightmost_index(timer_table, &trigger_mask);
2781                 timer = timer_table->timers[index];
2782                 BUG_ON(!timer);
2783                 ath_print(common, ATH_DBG_HWTIMER,
2784                           "Gen timer[%d] trigger\n", index);
2785                 timer->trigger(timer->arg);
2786         }
2787 }
2788 EXPORT_SYMBOL(ath_gen_timer_isr);
2789
2790 /********/
2791 /* HTC  */
2792 /********/
2793
2794 void ath9k_hw_htc_resetinit(struct ath_hw *ah)
2795 {
2796         ah->htc_reset_init = true;
2797 }
2798 EXPORT_SYMBOL(ath9k_hw_htc_resetinit);
2799
2800 static struct {
2801         u32 version;
2802         const char * name;
2803 } ath_mac_bb_names[] = {
2804         /* Devices with external radios */
2805         { AR_SREV_VERSION_5416_PCI,     "5416" },
2806         { AR_SREV_VERSION_5416_PCIE,    "5418" },
2807         { AR_SREV_VERSION_9100,         "9100" },
2808         { AR_SREV_VERSION_9160,         "9160" },
2809         /* Single-chip solutions */
2810         { AR_SREV_VERSION_9280,         "9280" },
2811         { AR_SREV_VERSION_9285,         "9285" },
2812         { AR_SREV_VERSION_9287,         "9287" },
2813         { AR_SREV_VERSION_9271,         "9271" },
2814         { AR_SREV_VERSION_9300,         "9300" },
2815 };
2816
2817 /* For devices with external radios */
2818 static struct {
2819         u16 version;
2820         const char * name;
2821 } ath_rf_names[] = {
2822         { 0,                            "5133" },
2823         { AR_RAD5133_SREV_MAJOR,        "5133" },
2824         { AR_RAD5122_SREV_MAJOR,        "5122" },
2825         { AR_RAD2133_SREV_MAJOR,        "2133" },
2826         { AR_RAD2122_SREV_MAJOR,        "2122" }
2827 };
2828
2829 /*
2830  * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2831  */
2832 static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
2833 {
2834         int i;
2835
2836         for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2837                 if (ath_mac_bb_names[i].version == mac_bb_version) {
2838                         return ath_mac_bb_names[i].name;
2839                 }
2840         }
2841
2842         return "????";
2843 }
2844
2845 /*
2846  * Return the RF name. "????" is returned if the RF is unknown.
2847  * Used for devices with external radios.
2848  */
2849 static const char *ath9k_hw_rf_name(u16 rf_version)
2850 {
2851         int i;
2852
2853         for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2854                 if (ath_rf_names[i].version == rf_version) {
2855                         return ath_rf_names[i].name;
2856                 }
2857         }
2858
2859         return "????";
2860 }
2861
2862 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
2863 {
2864         int used;
2865
2866         /* chipsets >= AR9280 are single-chip */
2867         if (AR_SREV_9280_10_OR_LATER(ah)) {
2868                 used = snprintf(hw_name, len,
2869                                "Atheros AR%s Rev:%x",
2870                                ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
2871                                ah->hw_version.macRev);
2872         }
2873         else {
2874                 used = snprintf(hw_name, len,
2875                                "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
2876                                ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
2877                                ah->hw_version.macRev,
2878                                ath9k_hw_rf_name((ah->hw_version.analog5GhzRev &
2879                                                 AR_RADIO_SREV_MAJOR)),
2880                                ah->hw_version.phyRev);
2881         }
2882
2883         hw_name[used] = '\0';
2884 }
2885 EXPORT_SYMBOL(ath9k_hw_name);