SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/net/wireless/ath/ath9k/hw.c

   1 /*
   2  * Copyright (c) 2008-2009 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/io.h>
  18 #include <asm/unaligned.h>
  19
  20 #include "hw.h"
  21 #include "rc.h"
  22 #include "initvals.h"
  23
  24 #define ATH9K_CLOCK_RATE_CCK            22
  25 #define ATH9K_CLOCK_RATE_5GHZ_OFDM      40
  26 #define ATH9K_CLOCK_RATE_2GHZ_OFDM      44
  27
  28 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
  29 static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan);
  30 static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
  31                               struct ar5416_eeprom_def *pEepData,
  32                               u32 reg, u32 value);
  33
  34 MODULE_AUTHOR("Atheros Communications");
  35 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
  36 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
  37 MODULE_LICENSE("Dual BSD/GPL");
  38
  39 static int __init ath9k_init(void)
  40 {
  41         return 0;
  42 }
  43 module_init(ath9k_init);
  44
  45 static void __exit ath9k_exit(void)
  46 {
  47         return;
  48 }
  49 module_exit(ath9k_exit);
  50
  51 /********************/
  52 /* Helper Functions */
  53 /********************/
  54
  55 static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
  56 {
  57         struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
  58
  59         if (!ah->curchan) /* should really check for CCK instead */
  60                 return usecs *ATH9K_CLOCK_RATE_CCK;
  61         if (conf->channel->band == IEEE80211_BAND_2GHZ)
  62                 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM;
  63         return usecs *ATH9K_CLOCK_RATE_5GHZ_OFDM;
  64 }
  65
  66 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
  67 {
  68         struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
  69
  70         if (conf_is_ht40(conf))
  71                 return ath9k_hw_mac_clks(ah, usecs) * 2;
  72         else
  73                 return ath9k_hw_mac_clks(ah, usecs);
  74 }
  75
  76 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
  77 {
  78         int i;
  79
  80         BUG_ON(timeout < AH_TIME_QUANTUM);
  81
  82         for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
  83                 if ((REG_READ(ah, reg) & mask) == val)
  84                         return true;
  85
  86                 udelay(AH_TIME_QUANTUM);
  87         }
  88
  89         ath_print(ath9k_hw_common(ah), ATH_DBG_ANY,
  90                   "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
  91                   timeout, reg, REG_READ(ah, reg), mask, val);
  92
  93         return false;
  94 }
  95 EXPORT_SYMBOL(ath9k_hw_wait);
  96
  97 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
  98 {
  99         u32 retval;
 100         int i;
 101
 102         for (i = 0, retval = 0; i < n; i++) {
 103                 retval = (retval << 1) | (val & 1);
 104                 val >>= 1;
 105         }
 106         return retval;
 107 }
 108
 109 bool ath9k_get_channel_edges(struct ath_hw *ah,
 110                              u16 flags, u16 *low,
 111                              u16 *high)
 112 {
 113         struct ath9k_hw_capabilities *pCap = &ah->caps;
 114
 115         if (flags & CHANNEL_5GHZ) {
 116                 *low = pCap->low_5ghz_chan;
 117                 *high = pCap->high_5ghz_chan;
 118                 return true;
 119         }
 120         if ((flags & CHANNEL_2GHZ)) {
 121                 *low = pCap->low_2ghz_chan;
 122                 *high = pCap->high_2ghz_chan;
 123                 return true;
 124         }
 125         return false;
 126 }
 127
 128 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
 129                            u8 phy, int kbps,
 130                            u32 frameLen, u16 rateix,
 131                            bool shortPreamble)
 132 {
 133         u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
 134
 135         if (kbps == 0)
 136                 return 0;
 137
 138         switch (phy) {
 139         case WLAN_RC_PHY_CCK:
 140                 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
 141                 if (shortPreamble)
 142                         phyTime >>= 1;
 143                 numBits = frameLen << 3;
 144                 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
 145                 break;
 146         case WLAN_RC_PHY_OFDM:
 147                 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
 148                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
 149                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 150                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 151                         txTime = OFDM_SIFS_TIME_QUARTER
 152                                 + OFDM_PREAMBLE_TIME_QUARTER
 153                                 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
 154                 } else if (ah->curchan &&
 155                            IS_CHAN_HALF_RATE(ah->curchan)) {
 156                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
 157                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 158                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 159                         txTime = OFDM_SIFS_TIME_HALF +
 160                                 OFDM_PREAMBLE_TIME_HALF
 161                                 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
 162                 } else {
 163                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
 164                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 165                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 166                         txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
 167                                 + (numSymbols * OFDM_SYMBOL_TIME);
 168                 }
 169                 break;
 170         default:
 171                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
 172                           "Unknown phy %u (rate ix %u)\n", phy, rateix);
 173                 txTime = 0;
 174                 break;
 175         }
 176
 177         return txTime;
 178 }
 179 EXPORT_SYMBOL(ath9k_hw_computetxtime);
 180
 181 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
 182                                   struct ath9k_channel *chan,
 183                                   struct chan_centers *centers)
 184 {
 185         int8_t extoff;
 186
 187         if (!IS_CHAN_HT40(chan)) {
 188                 centers->ctl_center = centers->ext_center =
 189                         centers->synth_center = chan->channel;
 190                 return;
 191         }
 192
 193         if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
 194             (chan->chanmode == CHANNEL_G_HT40PLUS)) {
 195                 centers->synth_center =
 196                         chan->channel + HT40_CHANNEL_CENTER_SHIFT;
 197                 extoff = 1;
 198         } else {
 199                 centers->synth_center =
 200                         chan->channel - HT40_CHANNEL_CENTER_SHIFT;
 201                 extoff = -1;
 202         }
 203
 204         centers->ctl_center =
 205                 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
 206         /* 25 MHz spacing is supported by hw but not on upper layers */
 207         centers->ext_center =
 208                 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
 209 }
 210
 211 /******************/
 212 /* Chip Revisions */
 213 /******************/
 214
 215 static void ath9k_hw_read_revisions(struct ath_hw *ah)
 216 {
 217         u32 val;
 218
 219         val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
 220
 221         if (val == 0xFF) {
 222                 val = REG_READ(ah, AR_SREV);
 223                 ah->hw_version.macVersion =
 224                         (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
 225                 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
 226                 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
 227         } else {
 228                 if (!AR_SREV_9100(ah))
 229                         ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
 230
 231                 ah->hw_version.macRev = val & AR_SREV_REVISION;
 232
 233                 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
 234                         ah->is_pciexpress = true;
 235         }
 236 }
 237
 238 static int ath9k_hw_get_radiorev(struct ath_hw *ah)
 239 {
 240         u32 val;
 241         int i;
 242
 243         REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
 244
 245         for (i = 0; i < 8; i++)
 246                 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
 247         val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
 248         val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
 249
 250         return ath9k_hw_reverse_bits(val, 8);
 251 }
 252
 253 /************************************/
 254 /* HW Attach, Detach, Init Routines */
 255 /************************************/
 256
 257 static void ath9k_hw_disablepcie(struct ath_hw *ah)
 258 {
 259         if (AR_SREV_9100(ah))
 260                 return;
 261
 262         REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
 263         REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
 264         REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
 265         REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
 266         REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
 267         REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
 268         REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
 269         REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
 270         REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
 271
 272         REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
 273 }
 274
 275 static bool ath9k_hw_chip_test(struct ath_hw *ah)
 276 {
 277         struct ath_common *common = ath9k_hw_common(ah);
 278         u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
 279         u32 regHold[2];
 280         u32 patternData[4] = { 0x55555555,
 281                                0xaaaaaaaa,
 282                                0x66666666,
 283                                0x99999999 };
 284         int i, j;
 285
 286         for (i = 0; i < 2; i++) {
 287                 u32 addr = regAddr[i];
 288                 u32 wrData, rdData;
 289
 290                 regHold[i] = REG_READ(ah, addr);
 291                 for (j = 0; j < 0x100; j++) {
 292                         wrData = (j << 16) | j;
 293                         REG_WRITE(ah, addr, wrData);
 294                         rdData = REG_READ(ah, addr);
 295                         if (rdData != wrData) {
 296                                 ath_print(common, ATH_DBG_FATAL,
 297                                           "address test failed "
 298                                           "addr: 0x%08x - wr:0x%08x != "
 299                                           "rd:0x%08x\n",
 300                                           addr, wrData, rdData);
 301                                 return false;
 302                         }
 303                 }
 304                 for (j = 0; j < 4; j++) {
 305                         wrData = patternData[j];
 306                         REG_WRITE(ah, addr, wrData);
 307                         rdData = REG_READ(ah, addr);
 308                         if (wrData != rdData) {
 309                                 ath_print(common, ATH_DBG_FATAL,
 310                                           "address test failed "
 311                                           "addr: 0x%08x - wr:0x%08x != "
 312                                           "rd:0x%08x\n",
 313                                           addr, wrData, rdData);
 314                                 return false;
 315                         }
 316                 }
 317                 REG_WRITE(ah, regAddr[i], regHold[i]);
 318         }
 319         udelay(100);
 320
 321         return true;
 322 }
 323
 324 static void ath9k_hw_init_config(struct ath_hw *ah)
 325 {
 326         int i;
 327
 328         ah->config.dma_beacon_response_time = 2;
 329         ah->config.sw_beacon_response_time = 10;
 330         ah->config.additional_swba_backoff = 0;
 331         ah->config.ack_6mb = 0x0;
 332         ah->config.cwm_ignore_extcca = 0;
 333         ah->config.pcie_powersave_enable = 0;
 334         ah->config.pcie_clock_req = 0;
 335         ah->config.pcie_waen = 0;
 336         ah->config.analog_shiftreg = 1;
 337         ah->config.ht_enable = 1;
 338         ah->config.ofdm_trig_low = 200;
 339         ah->config.ofdm_trig_high = 500;
 340         ah->config.cck_trig_high = 200;
 341         ah->config.cck_trig_low = 100;
 342         ah->config.enable_ani = 1;
 343
 344         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
 345                 ah->config.spurchans[i][0] = AR_NO_SPUR;
 346                 ah->config.spurchans[i][1] = AR_NO_SPUR;
 347         }
 348
 349         ah->config.rx_intr_mitigation = true;
 350
 351         /*
 352          * We need this for PCI devices only (Cardbus, PCI, miniPCI)
 353          * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
 354          * This means we use it for all AR5416 devices, and the few
 355          * minor PCI AR9280 devices out there.
 356          *
 357          * Serialization is required because these devices do not handle
 358          * well the case of two concurrent reads/writes due to the latency
 359          * involved. During one read/write another read/write can be issued
 360          * on another CPU while the previous read/write may still be working
 361          * on our hardware, if we hit this case the hardware poops in a loop.
 362          * We prevent this by serializing reads and writes.
 363          *
 364          * This issue is not present on PCI-Express devices or pre-AR5416
 365          * devices (legacy, 802.11abg).
 366          */
 367         if (num_possible_cpus() > 1)
 368                 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
 369 }
 370 EXPORT_SYMBOL(ath9k_hw_init);
 371
 372 static void ath9k_hw_init_defaults(struct ath_hw *ah)
 373 {
 374         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
 375
 376         regulatory->country_code = CTRY_DEFAULT;
 377         regulatory->power_limit = MAX_RATE_POWER;
 378         regulatory->tp_scale = ATH9K_TP_SCALE_MAX;
 379
 380         ah->hw_version.magic = AR5416_MAGIC;
 381         ah->hw_version.subvendorid = 0;
 382
 383         ah->ah_flags = 0;
 384         if (ah->hw_version.devid == AR5416_AR9100_DEVID)
 385                 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
 386         if (!AR_SREV_9100(ah))
 387                 ah->ah_flags = AH_USE_EEPROM;
 388
 389         ah->atim_window = 0;
 390         ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
 391         ah->beacon_interval = 100;
 392         ah->enable_32kHz_clock = DONT_USE_32KHZ;
 393         ah->slottime = (u32) -1;
 394         ah->globaltxtimeout = (u32) -1;
 395         ah->power_mode = ATH9K_PM_UNDEFINED;
 396 }
 397
 398 static int ath9k_hw_rf_claim(struct ath_hw *ah)
 399 {
 400         u32 val;
 401
 402         REG_WRITE(ah, AR_PHY(0), 0x00000007);
 403
 404         val = ath9k_hw_get_radiorev(ah);
 405         switch (val & AR_RADIO_SREV_MAJOR) {
 406         case 0:
 407                 val = AR_RAD5133_SREV_MAJOR;
 408                 break;
 409         case AR_RAD5133_SREV_MAJOR:
 410         case AR_RAD5122_SREV_MAJOR:
 411         case AR_RAD2133_SREV_MAJOR:
 412         case AR_RAD2122_SREV_MAJOR:
 413                 break;
 414         default:
 415                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
 416                           "Radio Chip Rev 0x%02X not supported\n",
 417                           val & AR_RADIO_SREV_MAJOR);
 418                 return -EOPNOTSUPP;
 419         }
 420
 421         ah->hw_version.analog5GhzRev = val;
 422
 423         return 0;
 424 }
 425
 426 static int ath9k_hw_init_macaddr(struct ath_hw *ah)
 427 {
 428         struct ath_common *common = ath9k_hw_common(ah);
 429         u32 sum;
 430         int i;
 431         u16 eeval;
 432
 433         sum = 0;
 434         for (i = 0; i < 3; i++) {
 435                 eeval = ah->eep_ops->get_eeprom(ah, AR_EEPROM_MAC(i));
 436                 sum += eeval;
 437                 common->macaddr[2 * i] = eeval >> 8;
 438                 common->macaddr[2 * i + 1] = eeval & 0xff;
 439         }
 440         if (sum == 0 || sum == 0xffff * 3)
 441                 return -EADDRNOTAVAIL;
 442
 443         return 0;
 444 }
 445
 446 static void ath9k_hw_init_rxgain_ini(struct ath_hw *ah)
 447 {
 448         u32 rxgain_type;
 449
 450         if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) {
 451                 rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE);
 452
 453                 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
 454                         INIT_INI_ARRAY(&ah->iniModesRxGain,
 455                         ar9280Modes_backoff_13db_rxgain_9280_2,
 456                         ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6);
 457                 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
 458                         INIT_INI_ARRAY(&ah->iniModesRxGain,
 459                         ar9280Modes_backoff_23db_rxgain_9280_2,
 460                         ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6);
 461                 else
 462                         INIT_INI_ARRAY(&ah->iniModesRxGain,
 463                         ar9280Modes_original_rxgain_9280_2,
 464                         ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
 465         } else {
 466                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 467                         ar9280Modes_original_rxgain_9280_2,
 468                         ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
 469         }
 470 }
 471
 472 static void ath9k_hw_init_txgain_ini(struct ath_hw *ah)
 473 {
 474         u32 txgain_type;
 475
 476         if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) {
 477                 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
 478
 479                 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
 480                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 481                         ar9280Modes_high_power_tx_gain_9280_2,
 482                         ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6);
 483                 else
 484                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 485                         ar9280Modes_original_tx_gain_9280_2,
 486                         ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
 487         } else {
 488                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 489                 ar9280Modes_original_tx_gain_9280_2,
 490                 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
 491         }
 492 }
 493
 494 static int ath9k_hw_post_init(struct ath_hw *ah)
 495 {
 496         int ecode;
 497
 498         if (!ath9k_hw_chip_test(ah))
 499                 return -ENODEV;
 500
 501         ecode = ath9k_hw_rf_claim(ah);
 502         if (ecode != 0)
 503                 return ecode;
 504
 505         ecode = ath9k_hw_eeprom_init(ah);
 506         if (ecode != 0)
 507                 return ecode;
 508
 509         ath_print(ath9k_hw_common(ah), ATH_DBG_CONFIG,
 510                   "Eeprom VER: %d, REV: %d\n",
 511                   ah->eep_ops->get_eeprom_ver(ah),
 512                   ah->eep_ops->get_eeprom_rev(ah));
 513
 514         if (!AR_SREV_9280_10_OR_LATER(ah)) {
 515                 ecode = ath9k_hw_rf_alloc_ext_banks(ah);
 516                 if (ecode) {
 517                         ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
 518                                   "Failed allocating banks for "
 519                                   "external radio\n");
 520                         return ecode;
 521                 }
 522         }
 523
 524         if (!AR_SREV_9100(ah)) {
 525                 ath9k_hw_ani_setup(ah);
 526                 ath9k_hw_ani_init(ah);
 527         }
 528
 529         return 0;
 530 }
 531
 532 static bool ath9k_hw_devid_supported(u16 devid)
 533 {
 534         switch (devid) {
 535         case AR5416_DEVID_PCI:
 536         case AR5416_DEVID_PCIE:
 537         case AR5416_AR9100_DEVID:
 538         case AR9160_DEVID_PCI:
 539         case AR9280_DEVID_PCI:
 540         case AR9280_DEVID_PCIE:
 541         case AR9285_DEVID_PCIE:
 542         case AR5416_DEVID_AR9287_PCI:
 543         case AR5416_DEVID_AR9287_PCIE:
 544         case AR9271_USB:
 545                 return true;
 546         default:
 547                 break;
 548         }
 549         return false;
 550 }
 551
 552 static bool ath9k_hw_macversion_supported(u32 macversion)
 553 {
 554         switch (macversion) {
 555         case AR_SREV_VERSION_5416_PCI:
 556         case AR_SREV_VERSION_5416_PCIE:
 557         case AR_SREV_VERSION_9160:
 558         case AR_SREV_VERSION_9100:
 559         case AR_SREV_VERSION_9280:
 560         case AR_SREV_VERSION_9285:
 561         case AR_SREV_VERSION_9287:
 562         case AR_SREV_VERSION_9271:
 563                 return true;
 564         default:
 565                 break;
 566         }
 567         return false;
 568 }
 569
 570 static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
 571 {
 572         if (AR_SREV_9160_10_OR_LATER(ah)) {
 573                 if (AR_SREV_9280_10_OR_LATER(ah)) {
 574                         ah->iq_caldata.calData = &iq_cal_single_sample;
 575                         ah->adcgain_caldata.calData =
 576                                 &adc_gain_cal_single_sample;
 577                         ah->adcdc_caldata.calData =
 578                                 &adc_dc_cal_single_sample;
 579                         ah->adcdc_calinitdata.calData =
 580                                 &adc_init_dc_cal;
 581                 } else {
 582                         ah->iq_caldata.calData = &iq_cal_multi_sample;
 583                         ah->adcgain_caldata.calData =
 584                                 &adc_gain_cal_multi_sample;
 585                         ah->adcdc_caldata.calData =
 586                                 &adc_dc_cal_multi_sample;
 587                         ah->adcdc_calinitdata.calData =
 588                                 &adc_init_dc_cal;
 589                 }
 590                 ah->supp_cals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
 591         }
 592 }
 593
 594 static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
 595 {
 596         if (AR_SREV_9271(ah)) {
 597                 INIT_INI_ARRAY(&ah->iniModes, ar9271Modes_9271,
 598                                ARRAY_SIZE(ar9271Modes_9271), 6);
 599                 INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271,
 600                                ARRAY_SIZE(ar9271Common_9271), 2);
 601                 INIT_INI_ARRAY(&ah->iniModes_9271_1_0_only,
 602                                ar9271Modes_9271_1_0_only,
 603                                ARRAY_SIZE(ar9271Modes_9271_1_0_only), 6);
 604                 return;
 605         }
 606
 607         if (AR_SREV_9287_11_OR_LATER(ah)) {
 608                 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1,
 609                                 ARRAY_SIZE(ar9287Modes_9287_1_1), 6);
 610                 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_1,
 611                                 ARRAY_SIZE(ar9287Common_9287_1_1), 2);
 612                 if (ah->config.pcie_clock_req)
 613                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 614                         ar9287PciePhy_clkreq_off_L1_9287_1_1,
 615                         ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_1), 2);
 616                 else
 617                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 618                         ar9287PciePhy_clkreq_always_on_L1_9287_1_1,
 619                         ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_1),
 620                                         2);
 621         } else if (AR_SREV_9287_10_OR_LATER(ah)) {
 622                 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_0,
 623                                 ARRAY_SIZE(ar9287Modes_9287_1_0), 6);
 624                 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_0,
 625                                 ARRAY_SIZE(ar9287Common_9287_1_0), 2);
 626
 627                 if (ah->config.pcie_clock_req)
 628                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 629                         ar9287PciePhy_clkreq_off_L1_9287_1_0,
 630                         ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_0), 2);
 631                 else
 632                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 633                         ar9287PciePhy_clkreq_always_on_L1_9287_1_0,
 634                         ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_0),
 635                                   2);
 636         } else if (AR_SREV_9285_12_OR_LATER(ah)) {
 637
 638
 639                 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2,
 640                                ARRAY_SIZE(ar9285Modes_9285_1_2), 6);
 641                 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2,
 642                                ARRAY_SIZE(ar9285Common_9285_1_2), 2);
 643
 644                 if (ah->config.pcie_clock_req) {
 645                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 646                         ar9285PciePhy_clkreq_off_L1_9285_1_2,
 647                         ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2);
 648                 } else {
 649                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 650                         ar9285PciePhy_clkreq_always_on_L1_9285_1_2,
 651                         ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2),
 652                                   2);
 653                 }
 654         } else if (AR_SREV_9285_10_OR_LATER(ah)) {
 655                 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285,
 656                                ARRAY_SIZE(ar9285Modes_9285), 6);
 657                 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285,
 658                                ARRAY_SIZE(ar9285Common_9285), 2);
 659
 660                 if (ah->config.pcie_clock_req) {
 661                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 662                         ar9285PciePhy_clkreq_off_L1_9285,
 663                         ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2);
 664                 } else {
 665                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 666                         ar9285PciePhy_clkreq_always_on_L1_9285,
 667                         ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2);
 668                 }
 669         } else if (AR_SREV_9280_20_OR_LATER(ah)) {
 670                 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2,
 671                                ARRAY_SIZE(ar9280Modes_9280_2), 6);
 672                 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2,
 673                                ARRAY_SIZE(ar9280Common_9280_2), 2);
 674
 675                 if (ah->config.pcie_clock_req) {
 676                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 677                                ar9280PciePhy_clkreq_off_L1_9280,
 678                                ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2);
 679                 } else {
 680                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 681                                ar9280PciePhy_clkreq_always_on_L1_9280,
 682                                ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
 683                 }
 684                 INIT_INI_ARRAY(&ah->iniModesAdditional,
 685                                ar9280Modes_fast_clock_9280_2,
 686                                ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
 687         } else if (AR_SREV_9280_10_OR_LATER(ah)) {
 688                 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280,
 689                                ARRAY_SIZE(ar9280Modes_9280), 6);
 690                 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280,
 691                                ARRAY_SIZE(ar9280Common_9280), 2);
 692         } else if (AR_SREV_9160_10_OR_LATER(ah)) {
 693                 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160,
 694                                ARRAY_SIZE(ar5416Modes_9160), 6);
 695                 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160,
 696                                ARRAY_SIZE(ar5416Common_9160), 2);
 697                 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9160,
 698                                ARRAY_SIZE(ar5416Bank0_9160), 2);
 699                 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9160,
 700                                ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
 701                 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9160,
 702                                ARRAY_SIZE(ar5416Bank1_9160), 2);
 703                 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9160,
 704                                ARRAY_SIZE(ar5416Bank2_9160), 2);
 705                 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9160,
 706                                ARRAY_SIZE(ar5416Bank3_9160), 3);
 707                 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9160,
 708                                ARRAY_SIZE(ar5416Bank6_9160), 3);
 709                 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9160,
 710                                ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
 711                 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9160,
 712                                ARRAY_SIZE(ar5416Bank7_9160), 2);
 713                 if (AR_SREV_9160_11(ah)) {
 714                         INIT_INI_ARRAY(&ah->iniAddac,
 715                                        ar5416Addac_91601_1,
 716                                        ARRAY_SIZE(ar5416Addac_91601_1), 2);
 717                 } else {
 718                         INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160,
 719                                        ARRAY_SIZE(ar5416Addac_9160), 2);
 720                 }
 721         } else if (AR_SREV_9100_OR_LATER(ah)) {
 722                 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100,
 723                                ARRAY_SIZE(ar5416Modes_9100), 6);
 724                 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100,
 725                                ARRAY_SIZE(ar5416Common_9100), 2);
 726                 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9100,
 727                                ARRAY_SIZE(ar5416Bank0_9100), 2);
 728                 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9100,
 729                                ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
 730                 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9100,
 731                                ARRAY_SIZE(ar5416Bank1_9100), 2);
 732                 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9100,
 733                                ARRAY_SIZE(ar5416Bank2_9100), 2);
 734                 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9100,
 735                                ARRAY_SIZE(ar5416Bank3_9100), 3);
 736                 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100,
 737                                ARRAY_SIZE(ar5416Bank6_9100), 3);
 738                 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9100,
 739                                ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
 740                 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9100,
 741                                ARRAY_SIZE(ar5416Bank7_9100), 2);
 742                 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100,
 743                                ARRAY_SIZE(ar5416Addac_9100), 2);
 744         } else {
 745                 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes,
 746                                ARRAY_SIZE(ar5416Modes), 6);
 747                 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common,
 748                                ARRAY_SIZE(ar5416Common), 2);
 749                 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0,
 750                                ARRAY_SIZE(ar5416Bank0), 2);
 751                 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain,
 752                                ARRAY_SIZE(ar5416BB_RfGain), 3);
 753                 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1,
 754                                ARRAY_SIZE(ar5416Bank1), 2);
 755                 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2,
 756                                ARRAY_SIZE(ar5416Bank2), 2);
 757                 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3,
 758                                ARRAY_SIZE(ar5416Bank3), 3);
 759                 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6,
 760                                ARRAY_SIZE(ar5416Bank6), 3);
 761                 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC,
 762                                ARRAY_SIZE(ar5416Bank6TPC), 3);
 763                 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7,
 764                                ARRAY_SIZE(ar5416Bank7), 2);
 765                 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac,
 766                                ARRAY_SIZE(ar5416Addac), 2);
 767         }
 768 }
 769
 770 static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
 771 {
 772         if (AR_SREV_9287_11_OR_LATER(ah))
 773                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 774                 ar9287Modes_rx_gain_9287_1_1,
 775                 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_1), 6);
 776         else if (AR_SREV_9287_10(ah))
 777                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 778                 ar9287Modes_rx_gain_9287_1_0,
 779                 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_0), 6);
 780         else if (AR_SREV_9280_20(ah))
 781                 ath9k_hw_init_rxgain_ini(ah);
 782
 783         if (AR_SREV_9287_11_OR_LATER(ah)) {
 784                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 785                 ar9287Modes_tx_gain_9287_1_1,
 786                 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_1), 6);
 787         } else if (AR_SREV_9287_10(ah)) {
 788                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 789                 ar9287Modes_tx_gain_9287_1_0,
 790                 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_0), 6);
 791         } else if (AR_SREV_9280_20(ah)) {
 792                 ath9k_hw_init_txgain_ini(ah);
 793         } else if (AR_SREV_9285_12_OR_LATER(ah)) {
 794                 u32 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
 795
 796                 /* txgain table */
 797                 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) {
 798                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 799                         ar9285Modes_high_power_tx_gain_9285_1_2,
 800                         ARRAY_SIZE(ar9285Modes_high_power_tx_gain_9285_1_2), 6);
 801                 } else {
 802                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 803                         ar9285Modes_original_tx_gain_9285_1_2,
 804                         ARRAY_SIZE(ar9285Modes_original_tx_gain_9285_1_2), 6);
 805                 }
 806
 807         }
 808 }
 809
 810 static void ath9k_hw_init_eeprom_fix(struct ath_hw *ah)
 811 {
 812         u32 i, j;
 813
 814         if (ah->hw_version.devid == AR9280_DEVID_PCI) {
 815
 816                 /* EEPROM Fixup */
 817                 for (i = 0; i < ah->iniModes.ia_rows; i++) {
 818                         u32 reg = INI_RA(&ah->iniModes, i, 0);
 819
 820                         for (j = 1; j < ah->iniModes.ia_columns; j++) {
 821                                 u32 val = INI_RA(&ah->iniModes, i, j);
 822
 823                                 INI_RA(&ah->iniModes, i, j) =
 824                                         ath9k_hw_ini_fixup(ah,
 825                                                            &ah->eeprom.def,
 826                                                            reg, val);
 827                         }
 828                 }
 829         }
 830 }
 831
 832 int ath9k_hw_init(struct ath_hw *ah)
 833 {
 834         struct ath_common *common = ath9k_hw_common(ah);
 835         int r = 0;
 836
 837         if (!ath9k_hw_devid_supported(ah->hw_version.devid)) {
 838                 ath_print(common, ATH_DBG_FATAL,
 839                           "Unsupported device ID: 0x%0x\n",
 840                           ah->hw_version.devid);
 841                 return -EOPNOTSUPP;
 842         }
 843
 844         ath9k_hw_init_defaults(ah);
 845         ath9k_hw_init_config(ah);
 846
 847         if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
 848                 ath_print(common, ATH_DBG_FATAL,
 849                           "Couldn't reset chip\n");
 850                 return -EIO;
 851         }
 852
 853         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
 854                 ath_print(common, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
 855                 return -EIO;
 856         }
 857
 858         if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
 859                 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
 860                     (AR_SREV_9280(ah) && !ah->is_pciexpress)) {
 861                         ah->config.serialize_regmode =
 862                                 SER_REG_MODE_ON;
 863                 } else {
 864                         ah->config.serialize_regmode =
 865                                 SER_REG_MODE_OFF;
 866                 }
 867         }
 868
 869         ath_print(common, ATH_DBG_RESET, "serialize_regmode is %d\n",
 870                 ah->config.serialize_regmode);
 871
 872         if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
 873                 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
 874         else
 875                 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
 876
 877         if (!ath9k_hw_macversion_supported(ah->hw_version.macVersion)) {
 878                 ath_print(common, ATH_DBG_FATAL,
 879                           "Mac Chip Rev 0x%02x.%x is not supported by "
 880                           "this driver\n", ah->hw_version.macVersion,
 881                           ah->hw_version.macRev);
 882                 return -EOPNOTSUPP;
 883         }
 884
 885         if (AR_SREV_9100(ah)) {
 886                 ah->iq_caldata.calData = &iq_cal_multi_sample;
 887                 ah->supp_cals = IQ_MISMATCH_CAL;
 888                 ah->is_pciexpress = false;
 889         }
 890
 891         if (AR_SREV_9271(ah))
 892                 ah->is_pciexpress = false;
 893
 894         ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
 895
 896         ath9k_hw_init_cal_settings(ah);
 897
 898         ah->ani_function = ATH9K_ANI_ALL;
 899         if (AR_SREV_9280_10_OR_LATER(ah)) {
 900                 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
 901                 ah->ath9k_hw_rf_set_freq = &ath9k_hw_ar9280_set_channel;
 902                 ah->ath9k_hw_spur_mitigate_freq = &ath9k_hw_9280_spur_mitigate;
 903         } else {
 904                 ah->ath9k_hw_rf_set_freq = &ath9k_hw_set_channel;
 905                 ah->ath9k_hw_spur_mitigate_freq = &ath9k_hw_spur_mitigate;
 906         }
 907
 908         ath9k_hw_init_mode_regs(ah);
 909
 910         if (ah->is_pciexpress)
 911                 ath9k_hw_configpcipowersave(ah, 0, 0);
 912         else
 913                 ath9k_hw_disablepcie(ah);
 914
 915         /* Support for Japan ch.14 (2484) spread */
 916         if (AR_SREV_9287_11_OR_LATER(ah)) {
 917                 INIT_INI_ARRAY(&ah->iniCckfirNormal,
 918                        ar9287Common_normal_cck_fir_coeff_92871_1,
 919                        ARRAY_SIZE(ar9287Common_normal_cck_fir_coeff_92871_1), 2);
 920                 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
 921                        ar9287Common_japan_2484_cck_fir_coeff_92871_1,
 922                        ARRAY_SIZE(ar9287Common_japan_2484_cck_fir_coeff_92871_1), 2);
 923         }
 924
 925         r = ath9k_hw_post_init(ah);
 926         if (r)
 927                 return r;
 928
 929         ath9k_hw_init_mode_gain_regs(ah);
 930         r = ath9k_hw_fill_cap_info(ah);
 931         if (r)
 932                 return r;
 933
 934         ath9k_hw_init_eeprom_fix(ah);
 935
 936         r = ath9k_hw_init_macaddr(ah);
 937         if (r) {
 938                 ath_print(common, ATH_DBG_FATAL,
 939                           "Failed to initialize MAC address\n");
 940                 return r;
 941         }
 942
 943         if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
 944                 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
 945         else
 946                 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
 947
 948         ath9k_init_nfcal_hist_buffer(ah);
 949
 950         common->state = ATH_HW_INITIALIZED;
 951
 952         return 0;
 953 }
 954
 955 static void ath9k_hw_init_bb(struct ath_hw *ah,
 956                              struct ath9k_channel *chan)
 957 {
 958         u32 synthDelay;
 959
 960         synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
 961         if (IS_CHAN_B(chan))
 962                 synthDelay = (4 * synthDelay) / 22;
 963         else
 964                 synthDelay /= 10;
 965
 966         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
 967
 968         udelay(synthDelay + BASE_ACTIVATE_DELAY);
 969 }
 970
 971 static void ath9k_hw_init_qos(struct ath_hw *ah)
 972 {
 973         REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
 974         REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
 975
 976         REG_WRITE(ah, AR_QOS_NO_ACK,
 977                   SM(2, AR_QOS_NO_ACK_TWO_BIT) |
 978                   SM(5, AR_QOS_NO_ACK_BIT_OFF) |
 979                   SM(0, AR_QOS_NO_ACK_BYTE_OFF));
 980
 981         REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
 982         REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
 983         REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
 984         REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
 985         REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
 986 }
 987
 988 static void ath9k_hw_change_target_baud(struct ath_hw *ah, u32 freq, u32 baud)
 989 {
 990         u32 lcr;
 991         u32 baud_divider = freq * 1000 * 1000 / 16 / baud;
 992
 993         lcr = REG_READ(ah , 0x5100c);
 994         lcr |= 0x80;
 995
 996         REG_WRITE(ah, 0x5100c, lcr);
 997         REG_WRITE(ah, 0x51004, (baud_divider >> 8));
 998         REG_WRITE(ah, 0x51000, (baud_divider & 0xff));
 999
1000         lcr &= ~0x80;
1001         REG_WRITE(ah, 0x5100c, lcr);
1002 }
1003
1004 static void ath9k_hw_init_pll(struct ath_hw *ah,
1005                               struct ath9k_channel *chan)
1006 {
1007         u32 pll;
1008
1009         if (AR_SREV_9100(ah)) {
1010                 if (chan && IS_CHAN_5GHZ(chan))
1011                         pll = 0x1450;
1012                 else
1013                         pll = 0x1458;
1014         } else {
1015                 if (AR_SREV_9280_10_OR_LATER(ah)) {
1016                         pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1017
1018                         if (chan && IS_CHAN_HALF_RATE(chan))
1019                                 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1020                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
1021                                 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1022
1023                         if (chan && IS_CHAN_5GHZ(chan)) {
1024                                 pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
1025
1026
1027                                 if (AR_SREV_9280_20(ah)) {
1028                                         if (((chan->channel % 20) == 0)
1029                                             || ((chan->channel % 10) == 0))
1030                                                 pll = 0x2850;
1031                                         else
1032                                                 pll = 0x142c;
1033                                 }
1034                         } else {
1035                                 pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
1036                         }
1037
1038                 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1039
1040                         pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1041
1042                         if (chan && IS_CHAN_HALF_RATE(chan))
1043                                 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1044                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
1045                                 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1046
1047                         if (chan && IS_CHAN_5GHZ(chan))
1048                                 pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
1049                         else
1050                                 pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
1051                 } else {
1052                         pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
1053
1054                         if (chan && IS_CHAN_HALF_RATE(chan))
1055                                 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
1056                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
1057                                 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
1058
1059                         if (chan && IS_CHAN_5GHZ(chan))
1060                                 pll |= SM(0xa, AR_RTC_PLL_DIV);
1061                         else
1062                                 pll |= SM(0xb, AR_RTC_PLL_DIV);
1063                 }
1064         }
1065         REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
1066
1067         /* Switch the core clock for ar9271 to 117Mhz */
1068         if (AR_SREV_9271(ah)) {
1069                 if ((pll == 0x142c) || (pll == 0x2850) ) {
1070                         udelay(500);
1071                         /* set CLKOBS to output AHB clock */
1072                         REG_WRITE(ah, 0x7020, 0xe);
1073                         /*
1074                          * 0x304: 117Mhz, ahb_ratio: 1x1
1075                          * 0x306: 40Mhz, ahb_ratio: 1x1
1076                          */
1077                         REG_WRITE(ah, 0x50040, 0x304);
1078                         /*
1079                          * makes adjustments for the baud dividor to keep the
1080                          * targetted baud rate based on the used core clock.
1081                          */
1082                         ath9k_hw_change_target_baud(ah, AR9271_CORE_CLOCK,
1083                                                     AR9271_TARGET_BAUD_RATE);
1084                 }
1085         }
1086
1087         udelay(RTC_PLL_SETTLE_DELAY);
1088
1089         REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
1090 }
1091
1092 static void ath9k_hw_init_chain_masks(struct ath_hw *ah)
1093 {
1094         int rx_chainmask, tx_chainmask;
1095
1096         rx_chainmask = ah->rxchainmask;
1097         tx_chainmask = ah->txchainmask;
1098
1099         switch (rx_chainmask) {
1100         case 0x5:
1101                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1102                             AR_PHY_SWAP_ALT_CHAIN);
1103         case 0x3:
1104                 if (ah->hw_version.macVersion == AR_SREV_REVISION_5416_10) {
1105                         REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
1106                         REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
1107                         break;
1108                 }
1109         case 0x1:
1110         case 0x2:
1111         case 0x7:
1112                 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
1113                 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
1114                 break;
1115         default:
1116                 break;
1117         }
1118
1119         REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
1120         if (tx_chainmask == 0x5) {
1121                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1122                             AR_PHY_SWAP_ALT_CHAIN);
1123         }
1124         if (AR_SREV_9100(ah))
1125                 REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
1126                           REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
1127 }
1128
1129 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
1130                                           enum nl80211_iftype opmode)
1131 {
1132         ah->mask_reg = AR_IMR_TXERR |
1133                 AR_IMR_TXURN |
1134                 AR_IMR_RXERR |
1135                 AR_IMR_RXORN |
1136                 AR_IMR_BCNMISC;
1137
1138         if (ah->config.rx_intr_mitigation)
1139                 ah->mask_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
1140         else
1141                 ah->mask_reg |= AR_IMR_RXOK;
1142
1143         ah->mask_reg |= AR_IMR_TXOK;
1144
1145         if (opmode == NL80211_IFTYPE_AP)
1146                 ah->mask_reg |= AR_IMR_MIB;
1147
1148         REG_WRITE(ah, AR_IMR, ah->mask_reg);
1149         REG_WRITE(ah, AR_IMR_S2, REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT);
1150
1151         if (!AR_SREV_9100(ah)) {
1152                 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
1153                 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
1154                 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
1155         }
1156 }
1157
1158 static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
1159 {
1160         u32 val = ath9k_hw_mac_to_clks(ah, us);
1161         val = min(val, (u32) 0xFFFF);
1162         REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
1163 }
1164
1165 static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
1166 {
1167         u32 val = ath9k_hw_mac_to_clks(ah, us);
1168         val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
1169         REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
1170 }
1171
1172 static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
1173 {
1174         u32 val = ath9k_hw_mac_to_clks(ah, us);
1175         val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
1176         REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
1177 }
1178
1179 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
1180 {
1181         if (tu > 0xFFFF) {
1182                 ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT,
1183                           "bad global tx timeout %u\n", tu);
1184                 ah->globaltxtimeout = (u32) -1;
1185                 return false;
1186         } else {
1187                 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
1188                 ah->globaltxtimeout = tu;
1189                 return true;
1190         }
1191 }
1192
1193 void ath9k_hw_init_global_settings(struct ath_hw *ah)
1194 {
1195         struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
1196         int acktimeout;
1197         int slottime;
1198         int sifstime;
1199
1200         ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
1201                   ah->misc_mode);
1202
1203         if (ah->misc_mode != 0)
1204                 REG_WRITE(ah, AR_PCU_MISC,
1205                           REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
1206
1207         if (conf->channel && conf->channel->band == IEEE80211_BAND_5GHZ)
1208                 sifstime = 16;
1209         else
1210                 sifstime = 10;
1211
1212         /* As defined by IEEE 802.11-2007 17.3.8.6 */
1213         slottime = ah->slottime + 3 * ah->coverage_class;
1214         acktimeout = slottime + sifstime;
1215         ath9k_hw_setslottime(ah, slottime);
1216         ath9k_hw_set_ack_timeout(ah, acktimeout);
1217         ath9k_hw_set_cts_timeout(ah, acktimeout);
1218         if (ah->globaltxtimeout != (u32) -1)
1219                 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
1220 }
1221 EXPORT_SYMBOL(ath9k_hw_init_global_settings);
1222
1223 void ath9k_hw_deinit(struct ath_hw *ah)
1224 {
1225         struct ath_common *common = ath9k_hw_common(ah);
1226
1227         if (common->state <= ATH_HW_INITIALIZED)
1228                 goto free_hw;
1229
1230         if (!AR_SREV_9100(ah))
1231                 ath9k_hw_ani_disable(ah);
1232
1233         ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1234
1235 free_hw:
1236         if (!AR_SREV_9280_10_OR_LATER(ah))
1237                 ath9k_hw_rf_free_ext_banks(ah);
1238         kfree(ah);
1239         ah = NULL;
1240 }
1241 EXPORT_SYMBOL(ath9k_hw_deinit);
1242
1243 /*******/
1244 /* INI */
1245 /*******/
1246
1247 static void ath9k_hw_override_ini(struct ath_hw *ah,
1248                                   struct ath9k_channel *chan)
1249 {
1250         u32 val;
1251
1252         if (AR_SREV_9271(ah)) {
1253                 /*
1254                  * Enable spectral scan to solution for issues with stuck
1255                  * beacons on AR9271 1.0. The beacon stuck issue is not seeon on
1256                  * AR9271 1.1
1257                  */
1258                 if (AR_SREV_9271_10(ah)) {
1259                         val = REG_READ(ah, AR_PHY_SPECTRAL_SCAN) |
1260                               AR_PHY_SPECTRAL_SCAN_ENABLE;
1261                         REG_WRITE(ah, AR_PHY_SPECTRAL_SCAN, val);
1262                 }
1263                 else if (AR_SREV_9271_11(ah))
1264                         /*
1265                          * change AR_PHY_RF_CTL3 setting to fix MAC issue
1266                          * present on AR9271 1.1
1267                          */
1268                         REG_WRITE(ah, AR_PHY_RF_CTL3, 0x3a020001);
1269                 return;
1270         }
1271
1272         /*
1273          * Set the RX_ABORT and RX_DIS and clear if off only after
1274          * RXE is set for MAC. This prevents frames with corrupted
1275          * descriptor status.
1276          */
1277         REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
1278
1279         if (AR_SREV_9280_10_OR_LATER(ah)) {
1280                 val = REG_READ(ah, AR_PCU_MISC_MODE2) &
1281                                (~AR_PCU_MISC_MODE2_HWWAR1);
1282
1283                 if (AR_SREV_9287_10_OR_LATER(ah))
1284                         val = val & (~AR_PCU_MISC_MODE2_HWWAR2);
1285
1286                 REG_WRITE(ah, AR_PCU_MISC_MODE2, val);
1287         }
1288
1289         if (!AR_SREV_5416_20_OR_LATER(ah) ||
1290             AR_SREV_9280_10_OR_LATER(ah))
1291                 return;
1292         /*
1293          * Disable BB clock gating
1294          * Necessary to avoid issues on AR5416 2.0
1295          */
1296         REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
1297 }
1298
1299 static u32 ath9k_hw_def_ini_fixup(struct ath_hw *ah,
1300                               struct ar5416_eeprom_def *pEepData,
1301                               u32 reg, u32 value)
1302 {
1303         struct base_eep_header *pBase = &(pEepData->baseEepHeader);
1304         struct ath_common *common = ath9k_hw_common(ah);
1305
1306         switch (ah->hw_version.devid) {
1307         case AR9280_DEVID_PCI:
1308                 if (reg == 0x7894) {
1309                         ath_print(common, ATH_DBG_EEPROM,
1310                                 "ini VAL: %x  EEPROM: %x\n", value,
1311                                 (pBase->version & 0xff));
1312
1313                         if ((pBase->version & 0xff) > 0x0a) {
1314                                 ath_print(common, ATH_DBG_EEPROM,
1315                                           "PWDCLKIND: %d\n",
1316                                           pBase->pwdclkind);
1317                                 value &= ~AR_AN_TOP2_PWDCLKIND;
1318                                 value |= AR_AN_TOP2_PWDCLKIND &
1319                                         (pBase->pwdclkind << AR_AN_TOP2_PWDCLKIND_S);
1320                         } else {
1321                                 ath_print(common, ATH_DBG_EEPROM,
1322                                           "PWDCLKIND Earlier Rev\n");
1323                         }
1324
1325                         ath_print(common, ATH_DBG_EEPROM,
1326                                   "final ini VAL: %x\n", value);
1327                 }
1328                 break;
1329         }
1330
1331         return value;
1332 }
1333
1334 static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
1335                               struct ar5416_eeprom_def *pEepData,
1336                               u32 reg, u32 value)
1337 {
1338         if (ah->eep_map == EEP_MAP_4KBITS)
1339                 return value;
1340         else
1341                 return ath9k_hw_def_ini_fixup(ah, pEepData, reg, value);
1342 }
1343
1344 static void ath9k_olc_init(struct ath_hw *ah)
1345 {
1346         u32 i;
1347
1348         if (OLC_FOR_AR9287_10_LATER) {
1349                 REG_SET_BIT(ah, AR_PHY_TX_PWRCTRL9,
1350                                 AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL);
1351                 ath9k_hw_analog_shift_rmw(ah, AR9287_AN_TXPC0,
1352                                 AR9287_AN_TXPC0_TXPCMODE,
1353                                 AR9287_AN_TXPC0_TXPCMODE_S,
1354                                 AR9287_AN_TXPC0_TXPCMODE_TEMPSENSE);
1355                 udelay(100);
1356         } else {
1357                 for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++)
1358                         ah->originalGain[i] =
1359                                 MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4),
1360                                                 AR_PHY_TX_GAIN);
1361                 ah->PDADCdelta = 0;
1362         }
1363 }
1364
1365 static u32 ath9k_regd_get_ctl(struct ath_regulatory *reg,
1366                               struct ath9k_channel *chan)
1367 {
1368         u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
1369
1370         if (IS_CHAN_B(chan))
1371                 ctl |= CTL_11B;
1372         else if (IS_CHAN_G(chan))
1373                 ctl |= CTL_11G;
1374         else
1375                 ctl |= CTL_11A;
1376
1377         return ctl;
1378 }
1379
1380 static int ath9k_hw_process_ini(struct ath_hw *ah,
1381                                 struct ath9k_channel *chan)
1382 {
1383         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1384         int i, regWrites = 0;
1385         struct ieee80211_channel *channel = chan->chan;
1386         u32 modesIndex, freqIndex;
1387
1388         switch (chan->chanmode) {
1389         case CHANNEL_A:
1390         case CHANNEL_A_HT20:
1391                 modesIndex = 1;
1392                 freqIndex = 1;
1393                 break;
1394         case CHANNEL_A_HT40PLUS:
1395         case CHANNEL_A_HT40MINUS:
1396                 modesIndex = 2;
1397                 freqIndex = 1;
1398                 break;
1399         case CHANNEL_G:
1400         case CHANNEL_G_HT20:
1401         case CHANNEL_B:
1402                 modesIndex = 4;
1403                 freqIndex = 2;
1404                 break;
1405         case CHANNEL_G_HT40PLUS:
1406         case CHANNEL_G_HT40MINUS:
1407                 modesIndex = 3;
1408                 freqIndex = 2;
1409                 break;
1410
1411         default:
1412                 return -EINVAL;
1413         }
1414
1415         REG_WRITE(ah, AR_PHY(0), 0x00000007);
1416         REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
1417         ah->eep_ops->set_addac(ah, chan);
1418
1419         if (AR_SREV_5416_22_OR_LATER(ah)) {
1420                 REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites);
1421         } else {
1422                 struct ar5416IniArray temp;
1423                 u32 addacSize =
1424                         sizeof(u32) * ah->iniAddac.ia_rows *
1425                         ah->iniAddac.ia_columns;
1426
1427                 memcpy(ah->addac5416_21,
1428                        ah->iniAddac.ia_array, addacSize);
1429
1430                 (ah->addac5416_21)[31 * ah->iniAddac.ia_columns + 1] = 0;
1431
1432                 temp.ia_array = ah->addac5416_21;
1433                 temp.ia_columns = ah->iniAddac.ia_columns;
1434                 temp.ia_rows = ah->iniAddac.ia_rows;
1435                 REG_WRITE_ARRAY(&temp, 1, regWrites);
1436         }
1437
1438         REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
1439
1440         for (i = 0; i < ah->iniModes.ia_rows; i++) {
1441                 u32 reg = INI_RA(&ah->iniModes, i, 0);
1442                 u32 val = INI_RA(&ah->iniModes, i, modesIndex);
1443
1444                 REG_WRITE(ah, reg, val);
1445
1446                 if (reg >= 0x7800 && reg < 0x78a0
1447                     && ah->config.analog_shiftreg) {
1448                         udelay(100);
1449                 }
1450
1451                 DO_DELAY(regWrites);
1452         }
1453
1454         if (AR_SREV_9280(ah) || AR_SREV_9287_10_OR_LATER(ah))
1455                 REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites);
1456
1457         if (AR_SREV_9280(ah) || AR_SREV_9285_12_OR_LATER(ah) ||
1458             AR_SREV_9287_10_OR_LATER(ah))
1459                 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
1460
1461         for (i = 0; i < ah->iniCommon.ia_rows; i++) {
1462                 u32 reg = INI_RA(&ah->iniCommon, i, 0);
1463                 u32 val = INI_RA(&ah->iniCommon, i, 1);
1464
1465                 REG_WRITE(ah, reg, val);
1466
1467                 if (reg >= 0x7800 && reg < 0x78a0
1468                     && ah->config.analog_shiftreg) {
1469                         udelay(100);
1470                 }
1471
1472                 DO_DELAY(regWrites);
1473         }
1474
1475         ath9k_hw_write_regs(ah, freqIndex, regWrites);
1476
1477         if (AR_SREV_9271_10(ah))
1478                 REG_WRITE_ARRAY(&ah->iniModes_9271_1_0_only,
1479                                 modesIndex, regWrites);
1480
1481         if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
1482                 REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex,
1483                                 regWrites);
1484         }
1485
1486         ath9k_hw_override_ini(ah, chan);
1487         ath9k_hw_set_regs(ah, chan);
1488         ath9k_hw_init_chain_masks(ah);
1489
1490         if (OLC_FOR_AR9280_20_LATER)
1491                 ath9k_olc_init(ah);
1492
1493         ah->eep_ops->set_txpower(ah, chan,
1494                                  ath9k_regd_get_ctl(regulatory, chan),
1495                                  channel->max_antenna_gain * 2,
1496                                  channel->max_power * 2,
1497                                  min((u32) MAX_RATE_POWER,
1498                                  (u32) regulatory->power_limit));
1499
1500         if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
1501                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1502                           "ar5416SetRfRegs failed\n");
1503                 return -EIO;
1504         }
1505
1506         return 0;
1507 }
1508
1509 /****************************************/
1510 /* Reset and Channel Switching Routines */
1511 /****************************************/
1512
1513 static void ath9k_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan)
1514 {
1515         u32 rfMode = 0;
1516
1517         if (chan == NULL)
1518                 return;
1519
1520         rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
1521                 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
1522
1523         if (!AR_SREV_9280_10_OR_LATER(ah))
1524                 rfMode |= (IS_CHAN_5GHZ(chan)) ?
1525                         AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
1526
1527         if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan))
1528                 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
1529
1530         REG_WRITE(ah, AR_PHY_MODE, rfMode);
1531 }
1532
1533 static void ath9k_hw_mark_phy_inactive(struct ath_hw *ah)
1534 {
1535         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1536 }
1537
1538 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
1539 {
1540         u32 regval;
1541
1542         /*
1543          * set AHB_MODE not to do cacheline prefetches
1544         */
1545         regval = REG_READ(ah, AR_AHB_MODE);
1546         REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
1547
1548         /*
1549          * let mac dma reads be in 128 byte chunks
1550          */
1551         regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
1552         REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
1553
1554         /*
1555          * Restore TX Trigger Level to its pre-reset value.
1556          * The initial value depends on whether aggregation is enabled, and is
1557          * adjusted whenever underruns are detected.
1558          */
1559         REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
1560
1561         /*
1562          * let mac dma writes be in 128 byte chunks
1563          */
1564         regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
1565         REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
1566
1567         /*
1568          * Setup receive FIFO threshold to hold off TX activities
1569          */
1570         REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1571
1572         /*
1573          * reduce the number of usable entries in PCU TXBUF to avoid
1574          * wrap around issues.
1575          */
1576         if (AR_SREV_9285(ah)) {
1577                 /* For AR9285 the number of Fifos are reduced to half.
1578                  * So set the usable tx buf size also to half to
1579                  * avoid data/delimiter underruns
1580                  */
1581                 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1582                           AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
1583         } else if (!AR_SREV_9271(ah)) {
1584                 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1585                           AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1586         }
1587 }
1588
1589 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
1590 {
1591         u32 val;
1592
1593         val = REG_READ(ah, AR_STA_ID1);
1594         val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
1595         switch (opmode) {
1596         case NL80211_IFTYPE_AP:
1597                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
1598                           | AR_STA_ID1_KSRCH_MODE);
1599                 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1600                 break;
1601         case NL80211_IFTYPE_ADHOC:
1602         case NL80211_IFTYPE_MESH_POINT:
1603                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
1604                           | AR_STA_ID1_KSRCH_MODE);
1605                 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1606                 break;
1607         case NL80211_IFTYPE_STATION:
1608         case NL80211_IFTYPE_MONITOR:
1609                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
1610                 break;
1611         }
1612 }
1613
1614 static inline void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah,
1615                                                  u32 coef_scaled,
1616                                                  u32 *coef_mantissa,
1617                                                  u32 *coef_exponent)
1618 {
1619         u32 coef_exp, coef_man;
1620
1621         for (coef_exp = 31; coef_exp > 0; coef_exp--)
1622                 if ((coef_scaled >> coef_exp) & 0x1)
1623                         break;
1624
1625         coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1626
1627         coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1628
1629         *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1630         *coef_exponent = coef_exp - 16;
1631 }
1632
1633 static void ath9k_hw_set_delta_slope(struct ath_hw *ah,
1634                                      struct ath9k_channel *chan)
1635 {
1636         u32 coef_scaled, ds_coef_exp, ds_coef_man;
1637         u32 clockMhzScaled = 0x64000000;
1638         struct chan_centers centers;
1639
1640         if (IS_CHAN_HALF_RATE(chan))
1641                 clockMhzScaled = clockMhzScaled >> 1;
1642         else if (IS_CHAN_QUARTER_RATE(chan))
1643                 clockMhzScaled = clockMhzScaled >> 2;
1644
1645         ath9k_hw_get_channel_centers(ah, chan, &centers);
1646         coef_scaled = clockMhzScaled / centers.synth_center;
1647
1648         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1649                                       &ds_coef_exp);
1650
1651         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1652                       AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
1653         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1654                       AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
1655
1656         coef_scaled = (9 * coef_scaled) / 10;
1657
1658         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1659                                       &ds_coef_exp);
1660
1661         REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1662                       AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
1663         REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1664                       AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
1665 }
1666
1667 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1668 {
1669         u32 rst_flags;
1670         u32 tmpReg;
1671
1672         if (AR_SREV_9100(ah)) {
1673                 u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK);
1674                 val &= ~AR_RTC_DERIVED_CLK_PERIOD;
1675                 val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
1676                 REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
1677                 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1678         }
1679
1680         REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1681                   AR_RTC_FORCE_WAKE_ON_INT);
1682
1683         if (AR_SREV_9100(ah)) {
1684                 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1685                         AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1686         } else {
1687                 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1688                 if (tmpReg &
1689                     (AR_INTR_SYNC_LOCAL_TIMEOUT |
1690                      AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1691                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1692                         REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1693                 } else {
1694                         REG_WRITE(ah, AR_RC, AR_RC_AHB);
1695                 }
1696
1697                 rst_flags = AR_RTC_RC_MAC_WARM;
1698                 if (type == ATH9K_RESET_COLD)
1699                         rst_flags |= AR_RTC_RC_MAC_COLD;
1700         }
1701
1702         REG_WRITE(ah, AR_RTC_RC, rst_flags);
1703         udelay(50);
1704
1705         REG_WRITE(ah, AR_RTC_RC, 0);
1706         if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1707                 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1708                           "RTC stuck in MAC reset\n");
1709                 return false;
1710         }
1711
1712         if (!AR_SREV_9100(ah))
1713                 REG_WRITE(ah, AR_RC, 0);
1714
1715         if (AR_SREV_9100(ah))
1716                 udelay(50);
1717
1718         return true;
1719 }
1720
1721 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1722 {
1723         REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1724                   AR_RTC_FORCE_WAKE_ON_INT);
1725
1726         if (!AR_SREV_9100(ah))
1727                 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1728
1729         REG_WRITE(ah, AR_RTC_RESET, 0);
1730         udelay(2);
1731
1732         if (!AR_SREV_9100(ah))
1733                 REG_WRITE(ah, AR_RC, 0);
1734
1735         REG_WRITE(ah, AR_RTC_RESET, 1);
1736
1737         if (!ath9k_hw_wait(ah,
1738                            AR_RTC_STATUS,
1739                            AR_RTC_STATUS_M,
1740                            AR_RTC_STATUS_ON,
1741                            AH_WAIT_TIMEOUT)) {
1742                 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1743                           "RTC not waking up\n");
1744                 return false;
1745         }
1746
1747         ath9k_hw_read_revisions(ah);
1748
1749         return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1750 }
1751
1752 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1753 {
1754         REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1755                   AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1756
1757         switch (type) {
1758         case ATH9K_RESET_POWER_ON:
1759                 return ath9k_hw_set_reset_power_on(ah);
1760         case ATH9K_RESET_WARM:
1761         case ATH9K_RESET_COLD:
1762                 return ath9k_hw_set_reset(ah, type);
1763         default:
1764                 return false;
1765         }
1766 }
1767
1768 static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan)
1769 {
1770         u32 phymode;
1771         u32 enableDacFifo = 0;
1772
1773         if (AR_SREV_9285_10_OR_LATER(ah))
1774                 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
1775                                          AR_PHY_FC_ENABLE_DAC_FIFO);
1776
1777         phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
1778                 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo;
1779
1780         if (IS_CHAN_HT40(chan)) {
1781                 phymode |= AR_PHY_FC_DYN2040_EN;
1782
1783                 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
1784                     (chan->chanmode == CHANNEL_G_HT40PLUS))
1785                         phymode |= AR_PHY_FC_DYN2040_PRI_CH;
1786
1787         }
1788         REG_WRITE(ah, AR_PHY_TURBO, phymode);
1789
1790         ath9k_hw_set11nmac2040(ah);
1791
1792         REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
1793         REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
1794 }
1795
1796 static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1797                                 struct ath9k_channel *chan)
1798 {
1799         if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) {
1800                 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1801                         return false;
1802         } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1803                 return false;
1804
1805         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1806                 return false;
1807
1808         ah->chip_fullsleep = false;
1809         ath9k_hw_init_pll(ah, chan);
1810         ath9k_hw_set_rfmode(ah, chan);
1811
1812         return true;
1813 }
1814
1815 static bool ath9k_hw_channel_change(struct ath_hw *ah,
1816                                     struct ath9k_channel *chan)
1817 {
1818         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1819         struct ath_common *common = ath9k_hw_common(ah);
1820         struct ieee80211_channel *channel = chan->chan;
1821         u32 synthDelay, qnum;
1822         int r;
1823
1824         for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1825                 if (ath9k_hw_numtxpending(ah, qnum)) {
1826                         ath_print(common, ATH_DBG_QUEUE,
1827                                   "Transmit frames pending on "
1828                                   "queue %d\n", qnum);
1829                         return false;
1830                 }
1831         }
1832
1833         REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
1834         if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
1835                            AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT)) {
1836                 ath_print(common, ATH_DBG_FATAL,
1837                           "Could not kill baseband RX\n");
1838                 return false;
1839         }
1840
1841         ath9k_hw_set_regs(ah, chan);
1842
1843         r = ah->ath9k_hw_rf_set_freq(ah, chan);
1844         if (r) {
1845                 ath_print(common, ATH_DBG_FATAL,
1846                           "Failed to set channel\n");
1847                 return false;
1848         }
1849
1850         ah->eep_ops->set_txpower(ah, chan,
1851                              ath9k_regd_get_ctl(regulatory, chan),
1852                              channel->max_antenna_gain * 2,
1853                              channel->max_power * 2,
1854                              min((u32) MAX_RATE_POWER,
1855                              (u32) regulatory->power_limit));
1856
1857         synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
1858         if (IS_CHAN_B(chan))
1859                 synthDelay = (4 * synthDelay) / 22;
1860         else
1861                 synthDelay /= 10;
1862
1863         udelay(synthDelay + BASE_ACTIVATE_DELAY);
1864
1865         REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
1866
1867         if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1868                 ath9k_hw_set_delta_slope(ah, chan);
1869
1870         ah->ath9k_hw_spur_mitigate_freq(ah, chan);
1871
1872         if (!chan->oneTimeCalsDone)
1873                 chan->oneTimeCalsDone = true;
1874
1875         return true;
1876 }
1877
1878 static void ath9k_enable_rfkill(struct ath_hw *ah)
1879 {
1880         REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
1881                     AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
1882
1883         REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
1884                     AR_GPIO_INPUT_MUX2_RFSILENT);
1885
1886         ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
1887         REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
1888 }
1889
1890 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1891                     bool bChannelChange)
1892 {
1893         struct ath_common *common = ath9k_hw_common(ah);
1894         u32 saveLedState;
1895         struct ath9k_channel *curchan = ah->curchan;
1896         u32 saveDefAntenna;
1897         u32 macStaId1;
1898         u64 tsf = 0;
1899         int i, rx_chainmask, r;
1900
1901         ah->txchainmask = common->tx_chainmask;
1902         ah->rxchainmask = common->rx_chainmask;
1903
1904         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1905                 return -EIO;
1906
1907         if (curchan && !ah->chip_fullsleep)
1908                 ath9k_hw_getnf(ah, curchan);
1909
1910         if (bChannelChange &&
1911             (ah->chip_fullsleep != true) &&
1912             (ah->curchan != NULL) &&
1913             (chan->channel != ah->curchan->channel) &&
1914             ((chan->channelFlags & CHANNEL_ALL) ==
1915              (ah->curchan->channelFlags & CHANNEL_ALL)) &&
1916              !(AR_SREV_9280(ah) || IS_CHAN_A_5MHZ_SPACED(chan) ||
1917              IS_CHAN_A_5MHZ_SPACED(ah->curchan))) {
1918
1919                 if (ath9k_hw_channel_change(ah, chan)) {
1920                         ath9k_hw_loadnf(ah, ah->curchan);
1921                         ath9k_hw_start_nfcal(ah);
1922                         return 0;
1923                 }
1924         }
1925
1926         saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1927         if (saveDefAntenna == 0)
1928                 saveDefAntenna = 1;
1929
1930         macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1931
1932         /* For chips on which RTC reset is done, save TSF before it gets cleared */
1933         if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1934                 tsf = ath9k_hw_gettsf64(ah);
1935
1936         saveLedState = REG_READ(ah, AR_CFG_LED) &
1937                 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1938                  AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1939
1940         ath9k_hw_mark_phy_inactive(ah);
1941
1942         if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1943                 REG_WRITE(ah,
1944                           AR9271_RESET_POWER_DOWN_CONTROL,
1945                           AR9271_RADIO_RF_RST);
1946                 udelay(50);
1947         }
1948
1949         if (!ath9k_hw_chip_reset(ah, chan)) {
1950                 ath_print(common, ATH_DBG_FATAL, "Chip reset failed\n");
1951                 return -EINVAL;
1952         }
1953
1954         if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1955                 ah->htc_reset_init = false;
1956                 REG_WRITE(ah,
1957                           AR9271_RESET_POWER_DOWN_CONTROL,
1958                           AR9271_GATE_MAC_CTL);
1959                 udelay(50);
1960         }
1961
1962         /* Restore TSF */
1963         if (tsf && AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1964                 ath9k_hw_settsf64(ah, tsf);
1965
1966         if (AR_SREV_9280_10_OR_LATER(ah))
1967                 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
1968
1969         if (AR_SREV_9287_12_OR_LATER(ah)) {
1970                 /* Enable ASYNC FIFO */
1971                 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
1972                                 AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL);
1973                 REG_SET_BIT(ah, AR_PHY_MODE, AR_PHY_MODE_ASYNCFIFO);
1974                 REG_CLR_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
1975                                 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
1976                 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
1977                                 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
1978         }
1979         r = ath9k_hw_process_ini(ah, chan);
1980         if (r)
1981                 return r;
1982
1983         /* Setup MFP options for CCMP */
1984         if (AR_SREV_9280_20_OR_LATER(ah)) {
1985                 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1986                  * frames when constructing CCMP AAD. */
1987                 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
1988                               0xc7ff);
1989                 ah->sw_mgmt_crypto = false;
1990         } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1991                 /* Disable hardware crypto for management frames */
1992                 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
1993                             AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
1994                 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1995                             AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
1996                 ah->sw_mgmt_crypto = true;
1997         } else
1998                 ah->sw_mgmt_crypto = true;
1999
2000         if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
2001                 ath9k_hw_set_delta_slope(ah, chan);
2002
2003         ah->ath9k_hw_spur_mitigate_freq(ah, chan);
2004         ah->eep_ops->set_board_values(ah, chan);
2005
2006         REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
2007         REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
2008                   | macStaId1
2009                   | AR_STA_ID1_RTS_USE_DEF
2010                   | (ah->config.
2011                      ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
2012                   | ah->sta_id1_defaults);
2013         ath9k_hw_set_operating_mode(ah, ah->opmode);
2014
2015         ath_hw_setbssidmask(common);
2016
2017         REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
2018
2019         ath9k_hw_write_associd(ah);
2020
2021         REG_WRITE(ah, AR_ISR, ~0);
2022
2023         REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
2024
2025         r = ah->ath9k_hw_rf_set_freq(ah, chan);
2026         if (r)
2027                 return r;
2028
2029         for (i = 0; i < AR_NUM_DCU; i++)
2030                 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
2031
2032         ah->intr_txqs = 0;
2033         for (i = 0; i < ah->caps.total_queues; i++)
2034                 ath9k_hw_resettxqueue(ah, i);
2035
2036         ath9k_hw_init_interrupt_masks(ah, ah->opmode);
2037         ath9k_hw_init_qos(ah);
2038
2039         if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2040                 ath9k_enable_rfkill(ah);
2041
2042         ath9k_hw_init_global_settings(ah);
2043
2044         if (AR_SREV_9287_12_OR_LATER(ah)) {
2045                 REG_WRITE(ah, AR_D_GBL_IFS_SIFS,
2046                           AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR);
2047                 REG_WRITE(ah, AR_D_GBL_IFS_SLOT,
2048                           AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR);
2049                 REG_WRITE(ah, AR_D_GBL_IFS_EIFS,
2050                           AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR);
2051
2052                 REG_WRITE(ah, AR_TIME_OUT, AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR);
2053                 REG_WRITE(ah, AR_USEC, AR_USEC_ASYNC_FIFO_DUR);
2054
2055                 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
2056                             AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
2057                 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
2058                               AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
2059         }
2060         if (AR_SREV_9287_12_OR_LATER(ah)) {
2061                 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2062                                 AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
2063         }
2064
2065         REG_WRITE(ah, AR_STA_ID1,
2066                   REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
2067
2068         ath9k_hw_set_dma(ah);
2069
2070         REG_WRITE(ah, AR_OBS, 8);
2071
2072         if (ah->config.rx_intr_mitigation) {
2073                 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
2074                 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
2075         }
2076
2077         ath9k_hw_init_bb(ah, chan);
2078
2079         if (!ath9k_hw_init_cal(ah, chan))
2080                 return -EIO;
2081
2082         rx_chainmask = ah->rxchainmask;
2083         if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
2084                 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
2085                 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
2086         }
2087
2088         REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
2089
2090         /*
2091          * For big endian systems turn on swapping for descriptors
2092          */
2093         if (AR_SREV_9100(ah)) {
2094                 u32 mask;
2095                 mask = REG_READ(ah, AR_CFG);
2096                 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
2097                         ath_print(common, ATH_DBG_RESET,
2098                                 "CFG Byte Swap Set 0x%x\n", mask);
2099                 } else {
2100                         mask =
2101                                 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
2102                         REG_WRITE(ah, AR_CFG, mask);
2103                         ath_print(common, ATH_DBG_RESET,
2104                                 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
2105                 }
2106         } else {
2107                 /* Configure AR9271 target WLAN */
2108                 if (AR_SREV_9271(ah))
2109                         REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
2110 #ifdef __BIG_ENDIAN
2111                 else
2112                         REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
2113 #endif
2114         }
2115
2116         if (ah->btcoex_hw.enabled)
2117                 ath9k_hw_btcoex_enable(ah);
2118
2119         return 0;
2120 }
2121 EXPORT_SYMBOL(ath9k_hw_reset);
2122
2123 /************************/
2124 /* Key Cache Management */
2125 /************************/
2126
2127 bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
2128 {
2129         u32 keyType;
2130
2131         if (entry >= ah->caps.keycache_size) {
2132                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2133                           "keychache entry %u out of range\n", entry);
2134                 return false;
2135         }
2136
2137         keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
2138
2139         REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
2140         REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
2141         REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
2142         REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
2143         REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
2144         REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
2145         REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
2146         REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
2147
2148         if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2149                 u16 micentry = entry + 64;
2150
2151                 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
2152                 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2153                 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
2154                 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2155
2156         }
2157
2158         return true;
2159 }
2160 EXPORT_SYMBOL(ath9k_hw_keyreset);
2161
2162 bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
2163 {
2164         u32 macHi, macLo;
2165
2166         if (entry >= ah->caps.keycache_size) {
2167                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2168                           "keychache entry %u out of range\n", entry);
2169                 return false;
2170         }
2171
2172         if (mac != NULL) {
2173                 macHi = (mac[5] << 8) | mac[4];
2174                 macLo = (mac[3] << 24) |
2175                         (mac[2] << 16) |
2176                         (mac[1] << 8) |
2177                         mac[0];
2178                 macLo >>= 1;
2179                 macLo |= (macHi & 1) << 31;
2180                 macHi >>= 1;
2181         } else {
2182                 macLo = macHi = 0;
2183         }
2184         REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
2185         REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
2186
2187         return true;
2188 }
2189 EXPORT_SYMBOL(ath9k_hw_keysetmac);
2190
2191 bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
2192                                  const struct ath9k_keyval *k,
2193                                  const u8 *mac)
2194 {
2195         const struct ath9k_hw_capabilities *pCap = &ah->caps;
2196         struct ath_common *common = ath9k_hw_common(ah);
2197         u32 key0, key1, key2, key3, key4;
2198         u32 keyType;
2199
2200         if (entry >= pCap->keycache_size) {
2201                 ath_print(common, ATH_DBG_FATAL,
2202                           "keycache entry %u out of range\n", entry);
2203                 return false;
2204         }
2205
2206         switch (k->kv_type) {
2207         case ATH9K_CIPHER_AES_OCB:
2208                 keyType = AR_KEYTABLE_TYPE_AES;
2209                 break;
2210         case ATH9K_CIPHER_AES_CCM:
2211                 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
2212                         ath_print(common, ATH_DBG_ANY,
2213                                   "AES-CCM not supported by mac rev 0x%x\n",
2214                                   ah->hw_version.macRev);
2215                         return false;
2216                 }
2217                 keyType = AR_KEYTABLE_TYPE_CCM;
2218                 break;
2219         case ATH9K_CIPHER_TKIP:
2220                 keyType = AR_KEYTABLE_TYPE_TKIP;
2221                 if (ATH9K_IS_MIC_ENABLED(ah)
2222                     && entry + 64 >= pCap->keycache_size) {
2223                         ath_print(common, ATH_DBG_ANY,
2224                                   "entry %u inappropriate for TKIP\n", entry);
2225                         return false;
2226                 }
2227                 break;
2228         case ATH9K_CIPHER_WEP:
2229                 if (k->kv_len < WLAN_KEY_LEN_WEP40) {
2230                         ath_print(common, ATH_DBG_ANY,
2231                                   "WEP key length %u too small\n", k->kv_len);
2232                         return false;
2233                 }
2234                 if (k->kv_len <= WLAN_KEY_LEN_WEP40)
2235                         keyType = AR_KEYTABLE_TYPE_40;
2236                 else if (k->kv_len <= WLAN_KEY_LEN_WEP104)
2237                         keyType = AR_KEYTABLE_TYPE_104;
2238                 else
2239                         keyType = AR_KEYTABLE_TYPE_128;
2240                 break;
2241         case ATH9K_CIPHER_CLR:
2242                 keyType = AR_KEYTABLE_TYPE_CLR;
2243                 break;
2244         default:
2245                 ath_print(common, ATH_DBG_FATAL,
2246                           "cipher %u not supported\n", k->kv_type);
2247                 return false;
2248         }
2249
2250         key0 = get_unaligned_le32(k->kv_val + 0);
2251         key1 = get_unaligned_le16(k->kv_val + 4);
2252         key2 = get_unaligned_le32(k->kv_val + 6);
2253         key3 = get_unaligned_le16(k->kv_val + 10);
2254         key4 = get_unaligned_le32(k->kv_val + 12);
2255         if (k->kv_len <= WLAN_KEY_LEN_WEP104)
2256                 key4 &= 0xff;
2257
2258         /*
2259          * Note: Key cache registers access special memory area that requires
2260          * two 32-bit writes to actually update the values in the internal
2261          * memory. Consequently, the exact order and pairs used here must be
2262          * maintained.
2263          */
2264
2265         if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2266                 u16 micentry = entry + 64;
2267
2268                 /*
2269                  * Write inverted key[47:0] first to avoid Michael MIC errors
2270                  * on frames that could be sent or received at the same time.
2271                  * The correct key will be written in the end once everything
2272                  * else is ready.
2273                  */
2274                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
2275                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
2276
2277                 /* Write key[95:48] */
2278                 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2279                 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2280
2281                 /* Write key[127:96] and key type */
2282                 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2283                 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2284
2285                 /* Write MAC address for the entry */
2286                 (void) ath9k_hw_keysetmac(ah, entry, mac);
2287
2288                 if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) {
2289                         /*
2290                          * TKIP uses two key cache entries:
2291                          * Michael MIC TX/RX keys in the same key cache entry
2292                          * (idx = main index + 64):
2293                          * key0 [31:0] = RX key [31:0]
2294                          * key1 [15:0] = TX key [31:16]
2295                          * key1 [31:16] = reserved
2296                          * key2 [31:0] = RX key [63:32]
2297                          * key3 [15:0] = TX key [15:0]
2298                          * key3 [31:16] = reserved
2299                          * key4 [31:0] = TX key [63:32]
2300                          */
2301                         u32 mic0, mic1, mic2, mic3, mic4;
2302
2303                         mic0 = get_unaligned_le32(k->kv_mic + 0);
2304                         mic2 = get_unaligned_le32(k->kv_mic + 4);
2305                         mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
2306                         mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
2307                         mic4 = get_unaligned_le32(k->kv_txmic + 4);
2308
2309                         /* Write RX[31:0] and TX[31:16] */
2310                         REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2311                         REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
2312
2313                         /* Write RX[63:32] and TX[15:0] */
2314                         REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2315                         REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
2316
2317                         /* Write TX[63:32] and keyType(reserved) */
2318                         REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
2319                         REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2320                                   AR_KEYTABLE_TYPE_CLR);
2321
2322                 } else {
2323                         /*
2324                          * TKIP uses four key cache entries (two for group
2325                          * keys):
2326                          * Michael MIC TX/RX keys are in different key cache
2327                          * entries (idx = main index + 64 for TX and
2328                          * main index + 32 + 96 for RX):
2329                          * key0 [31:0] = TX/RX MIC key [31:0]
2330                          * key1 [31:0] = reserved
2331                          * key2 [31:0] = TX/RX MIC key [63:32]
2332                          * key3 [31:0] = reserved
2333                          * key4 [31:0] = reserved
2334                          *
2335                          * Upper layer code will call this function separately
2336                          * for TX and RX keys when these registers offsets are
2337                          * used.
2338                          */
2339                         u32 mic0, mic2;
2340
2341                         mic0 = get_unaligned_le32(k->kv_mic + 0);
2342                         mic2 = get_unaligned_le32(k->kv_mic + 4);
2343
2344                         /* Write MIC key[31:0] */
2345                         REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2346                         REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2347
2348                         /* Write MIC key[63:32] */
2349                         REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2350                         REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2351
2352                         /* Write TX[63:32] and keyType(reserved) */
2353                         REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
2354                         REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2355                                   AR_KEYTABLE_TYPE_CLR);
2356                 }
2357
2358                 /* MAC address registers are reserved for the MIC entry */
2359                 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
2360                 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
2361
2362                 /*
2363                  * Write the correct (un-inverted) key[47:0] last to enable
2364                  * TKIP now that all other registers are set with correct
2365                  * values.
2366                  */
2367                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2368                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2369         } else {
2370                 /* Write key[47:0] */
2371                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2372                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2373
2374                 /* Write key[95:48] */
2375                 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2376                 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2377
2378                 /* Write key[127:96] and key type */
2379                 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2380                 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2381
2382                 /* Write MAC address for the entry */
2383                 (void) ath9k_hw_keysetmac(ah, entry, mac);
2384         }
2385
2386         return true;
2387 }
2388 EXPORT_SYMBOL(ath9k_hw_set_keycache_entry);
2389
2390 bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry)
2391 {
2392         if (entry < ah->caps.keycache_size) {
2393                 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
2394                 if (val & AR_KEYTABLE_VALID)
2395                         return true;
2396         }
2397         return false;
2398 }
2399 EXPORT_SYMBOL(ath9k_hw_keyisvalid);
2400
2401 /******************************/
2402 /* Power Management (Chipset) */
2403 /******************************/
2404
2405 static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
2406 {
2407         REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2408         if (setChip) {
2409                 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2410                             AR_RTC_FORCE_WAKE_EN);
2411                 if (!AR_SREV_9100(ah))
2412                         REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
2413
2414                 if(!AR_SREV_5416(ah))
2415                         REG_CLR_BIT(ah, (AR_RTC_RESET),
2416                                     AR_RTC_RESET_EN);
2417         }
2418 }
2419
2420 static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
2421 {
2422         REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2423         if (setChip) {
2424                 struct ath9k_hw_capabilities *pCap = &ah->caps;
2425
2426                 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2427                         REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2428                                   AR_RTC_FORCE_WAKE_ON_INT);
2429                 } else {
2430                         REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2431                                     AR_RTC_FORCE_WAKE_EN);
2432                 }
2433         }
2434 }
2435
2436 static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
2437 {
2438         u32 val;
2439         int i;
2440
2441         if (setChip) {
2442                 if ((REG_READ(ah, AR_RTC_STATUS) &
2443                      AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2444                         if (ath9k_hw_set_reset_reg(ah,
2445                                            ATH9K_RESET_POWER_ON) != true) {
2446                                 return false;
2447                         }
2448                         ath9k_hw_init_pll(ah, NULL);
2449                 }
2450                 if (AR_SREV_9100(ah))
2451                         REG_SET_BIT(ah, AR_RTC_RESET,
2452                                     AR_RTC_RESET_EN);
2453
2454                 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2455                             AR_RTC_FORCE_WAKE_EN);
2456                 udelay(50);
2457
2458                 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2459                         val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2460                         if (val == AR_RTC_STATUS_ON)
2461                                 break;
2462                         udelay(50);
2463                         REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2464                                     AR_RTC_FORCE_WAKE_EN);
2465                 }
2466                 if (i == 0) {
2467                         ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2468                                   "Failed to wakeup in %uus\n",
2469                                   POWER_UP_TIME / 20);
2470                         return false;
2471                 }
2472         }
2473
2474         REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2475
2476         return true;
2477 }
2478
2479 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
2480 {
2481         struct ath_common *common = ath9k_hw_common(ah);
2482         int status = true, setChip = true;
2483         static const char *modes[] = {
2484                 "AWAKE",
2485                 "FULL-SLEEP",
2486                 "NETWORK SLEEP",
2487                 "UNDEFINED"
2488         };
2489
2490         if (ah->power_mode == mode)
2491                 return status;
2492
2493         ath_print(common, ATH_DBG_RESET, "%s -> %s\n",
2494                   modes[ah->power_mode], modes[mode]);
2495
2496         switch (mode) {
2497         case ATH9K_PM_AWAKE:
2498                 status = ath9k_hw_set_power_awake(ah, setChip);
2499                 break;
2500         case ATH9K_PM_FULL_SLEEP:
2501                 ath9k_set_power_sleep(ah, setChip);
2502                 ah->chip_fullsleep = true;
2503                 break;
2504         case ATH9K_PM_NETWORK_SLEEP:
2505                 ath9k_set_power_network_sleep(ah, setChip);
2506                 break;
2507         default:
2508                 ath_print(common, ATH_DBG_FATAL,
2509                           "Unknown power mode %u\n", mode);
2510                 return false;
2511         }
2512         ah->power_mode = mode;
2513
2514         return status;
2515 }
2516 EXPORT_SYMBOL(ath9k_hw_setpower);
2517
2518 /*
2519  * Helper for ASPM support.
2520  *
2521  * Disable PLL when in L0s as well as receiver clock when in L1.
2522  * This power saving option must be enabled through the SerDes.
2523  *
2524  * Programming the SerDes must go through the same 288 bit serial shift
2525  * register as the other analog registers.  Hence the 9 writes.
2526  */
2527 void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore, int power_off)
2528 {
2529         u8 i;
2530         u32 val;
2531
2532         if (ah->is_pciexpress != true)
2533                 return;
2534
2535         /* Do not touch SerDes registers */
2536         if (ah->config.pcie_powersave_enable == 2)
2537                 return;
2538
2539         /* Nothing to do on restore for 11N */
2540         if (!restore) {
2541                 if (AR_SREV_9280_20_OR_LATER(ah)) {
2542                         /*
2543                          * AR9280 2.0 or later chips use SerDes values from the
2544                          * initvals.h initialized depending on chipset during
2545                          * ath9k_hw_init()
2546                          */
2547                         for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) {
2548                                 REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0),
2549                                           INI_RA(&ah->iniPcieSerdes, i, 1));
2550                         }
2551                 } else if (AR_SREV_9280(ah) &&
2552                            (ah->hw_version.macRev == AR_SREV_REVISION_9280_10)) {
2553                         REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
2554                         REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2555
2556                         /* RX shut off when elecidle is asserted */
2557                         REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
2558                         REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
2559                         REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
2560
2561                         /* Shut off CLKREQ active in L1 */
2562                         if (ah->config.pcie_clock_req)
2563                                 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
2564                         else
2565                                 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
2566
2567                         REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2568                         REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2569                         REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
2570
2571                         /* Load the new settings */
2572                         REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2573
2574                 } else {
2575                         REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
2576                         REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2577
2578                         /* RX shut off when elecidle is asserted */
2579                         REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
2580                         REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
2581                         REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
2582
2583                         /*
2584                          * Ignore ah->ah_config.pcie_clock_req setting for
2585                          * pre-AR9280 11n
2586                          */
2587                         REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
2588
2589                         REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2590                         REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2591                         REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
2592
2593                         /* Load the new settings */
2594                         REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2595                 }
2596
2597                 udelay(1000);
2598
2599                 /* set bit 19 to allow forcing of pcie core into L1 state */
2600                 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
2601
2602                 /* Several PCIe massages to ensure proper behaviour */
2603                 if (ah->config.pcie_waen) {
2604                         val = ah->config.pcie_waen;
2605                         if (!power_off)
2606                                 val &= (~AR_WA_D3_L1_DISABLE);
2607                 } else {
2608                         if (AR_SREV_9285(ah) || AR_SREV_9271(ah) ||
2609                             AR_SREV_9287(ah)) {
2610                                 val = AR9285_WA_DEFAULT;
2611                                 if (!power_off)
2612                                         val &= (~AR_WA_D3_L1_DISABLE);
2613                         } else if (AR_SREV_9280(ah)) {
2614                                 /*
2615                                  * On AR9280 chips bit 22 of 0x4004 needs to be
2616                                  * set otherwise card may disappear.
2617                                  */
2618                                 val = AR9280_WA_DEFAULT;
2619                                 if (!power_off)
2620                                         val &= (~AR_WA_D3_L1_DISABLE);
2621                         } else
2622                                 val = AR_WA_DEFAULT;
2623                 }
2624
2625                 REG_WRITE(ah, AR_WA, val);
2626         }
2627
2628         if (power_off) {
2629                 /*
2630                  * Set PCIe workaround bits
2631                  * bit 14 in WA register (disable L1) should only
2632                  * be set when device enters D3 and be cleared
2633                  * when device comes back to D0.
2634                  */
2635                 if (ah->config.pcie_waen) {
2636                         if (ah->config.pcie_waen & AR_WA_D3_L1_DISABLE)
2637                                 REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE);
2638                 } else {
2639                         if (((AR_SREV_9285(ah) || AR_SREV_9271(ah) ||
2640                               AR_SREV_9287(ah)) &&
2641                              (AR9285_WA_DEFAULT & AR_WA_D3_L1_DISABLE)) ||
2642                             (AR_SREV_9280(ah) &&
2643                              (AR9280_WA_DEFAULT & AR_WA_D3_L1_DISABLE))) {
2644                                 REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE);
2645                         }
2646                 }
2647         }
2648 }
2649 EXPORT_SYMBOL(ath9k_hw_configpcipowersave);
2650
2651 /**********************/
2652 /* Interrupt Handling */
2653 /**********************/
2654
2655 bool ath9k_hw_intrpend(struct ath_hw *ah)
2656 {
2657         u32 host_isr;
2658
2659         if (AR_SREV_9100(ah))
2660                 return true;
2661
2662         host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
2663         if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
2664                 return true;
2665
2666         host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
2667         if ((host_isr & AR_INTR_SYNC_DEFAULT)
2668             && (host_isr != AR_INTR_SPURIOUS))
2669                 return true;
2670
2671         return false;
2672 }
2673 EXPORT_SYMBOL(ath9k_hw_intrpend);
2674
2675 bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
2676 {
2677         u32 isr = 0;
2678         u32 mask2 = 0;
2679         struct ath9k_hw_capabilities *pCap = &ah->caps;
2680         u32 sync_cause = 0;
2681         bool fatal_int = false;
2682         struct ath_common *common = ath9k_hw_common(ah);
2683
2684         if (!AR_SREV_9100(ah)) {
2685                 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
2686                         if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
2687                             == AR_RTC_STATUS_ON) {
2688                                 isr = REG_READ(ah, AR_ISR);
2689                         }
2690                 }
2691
2692                 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
2693                         AR_INTR_SYNC_DEFAULT;
2694
2695                 *masked = 0;
2696
2697                 if (!isr && !sync_cause)
2698                         return false;
2699         } else {
2700                 *masked = 0;
2701                 isr = REG_READ(ah, AR_ISR);
2702         }
2703
2704         if (isr) {
2705                 if (isr & AR_ISR_BCNMISC) {
2706                         u32 isr2;
2707                         isr2 = REG_READ(ah, AR_ISR_S2);
2708                         if (isr2 & AR_ISR_S2_TIM)
2709                                 mask2 |= ATH9K_INT_TIM;
2710                         if (isr2 & AR_ISR_S2_DTIM)
2711                                 mask2 |= ATH9K_INT_DTIM;
2712                         if (isr2 & AR_ISR_S2_DTIMSYNC)
2713                                 mask2 |= ATH9K_INT_DTIMSYNC;
2714                         if (isr2 & (AR_ISR_S2_CABEND))
2715                                 mask2 |= ATH9K_INT_CABEND;
2716                         if (isr2 & AR_ISR_S2_GTT)
2717                                 mask2 |= ATH9K_INT_GTT;
2718                         if (isr2 & AR_ISR_S2_CST)
2719                                 mask2 |= ATH9K_INT_CST;
2720                         if (isr2 & AR_ISR_S2_TSFOOR)
2721                                 mask2 |= ATH9K_INT_TSFOOR;
2722                 }
2723
2724                 isr = REG_READ(ah, AR_ISR_RAC);
2725                 if (isr == 0xffffffff) {
2726                         *masked = 0;
2727                         return false;
2728                 }
2729
2730                 *masked = isr & ATH9K_INT_COMMON;
2731
2732                 if (ah->config.rx_intr_mitigation) {
2733                         if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
2734                                 *masked |= ATH9K_INT_RX;
2735                 }
2736
2737                 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
2738                         *masked |= ATH9K_INT_RX;
2739                 if (isr &
2740                     (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
2741                      AR_ISR_TXEOL)) {
2742                         u32 s0_s, s1_s;
2743
2744                         *masked |= ATH9K_INT_TX;
2745
2746                         s0_s = REG_READ(ah, AR_ISR_S0_S);
2747                         ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
2748                         ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
2749
2750                         s1_s = REG_READ(ah, AR_ISR_S1_S);
2751                         ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
2752                         ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
2753                 }
2754
2755                 if (isr & AR_ISR_RXORN) {
2756                         ath_print(common, ATH_DBG_INTERRUPT,
2757                                   "receive FIFO overrun interrupt\n");
2758                 }
2759
2760                 if (!AR_SREV_9100(ah)) {
2761                         if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2762                                 u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
2763                                 if (isr5 & AR_ISR_S5_TIM_TIMER)
2764                                         *masked |= ATH9K_INT_TIM_TIMER;
2765                         }
2766                 }
2767
2768                 *masked |= mask2;
2769         }
2770
2771         if (AR_SREV_9100(ah))
2772                 return true;
2773
2774         if (isr & AR_ISR_GENTMR) {
2775                 u32 s5_s;
2776
2777                 s5_s = REG_READ(ah, AR_ISR_S5_S);
2778                 if (isr & AR_ISR_GENTMR) {
2779                         ah->intr_gen_timer_trigger =
2780                                 MS(s5_s, AR_ISR_S5_GENTIMER_TRIG);
2781
2782                         ah->intr_gen_timer_thresh =
2783                                 MS(s5_s, AR_ISR_S5_GENTIMER_THRESH);
2784
2785                         if (ah->intr_gen_timer_trigger)
2786                                 *masked |= ATH9K_INT_GENTIMER;
2787
2788                 }
2789         }
2790
2791         if (sync_cause) {
2792                 fatal_int =
2793                         (sync_cause &
2794                          (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
2795                         ? true : false;
2796
2797                 if (fatal_int) {
2798                         if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
2799                                 ath_print(common, ATH_DBG_ANY,
2800                                           "received PCI FATAL interrupt\n");
2801                         }
2802                         if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
2803                                 ath_print(common, ATH_DBG_ANY,
2804                                           "received PCI PERR interrupt\n");
2805                         }
2806                         *masked |= ATH9K_INT_FATAL;
2807                 }
2808                 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
2809                         ath_print(common, ATH_DBG_INTERRUPT,
2810                                   "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
2811                         REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
2812                         REG_WRITE(ah, AR_RC, 0);
2813                         *masked |= ATH9K_INT_FATAL;
2814                 }
2815                 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
2816                         ath_print(common, ATH_DBG_INTERRUPT,
2817                                   "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
2818                 }
2819
2820                 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
2821                 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
2822         }
2823
2824         return true;
2825 }
2826 EXPORT_SYMBOL(ath9k_hw_getisr);
2827
2828 enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
2829 {
2830         u32 omask = ah->mask_reg;
2831         u32 mask, mask2;
2832         struct ath9k_hw_capabilities *pCap = &ah->caps;
2833         struct ath_common *common = ath9k_hw_common(ah);
2834
2835         ath_print(common, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
2836
2837         if (omask & ATH9K_INT_GLOBAL) {
2838                 ath_print(common, ATH_DBG_INTERRUPT, "disable IER\n");
2839                 REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
2840                 (void) REG_READ(ah, AR_IER);
2841                 if (!AR_SREV_9100(ah)) {
2842                         REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
2843                         (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
2844
2845                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
2846                         (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
2847                 }
2848         }
2849
2850         mask = ints & ATH9K_INT_COMMON;
2851         mask2 = 0;
2852
2853         if (ints & ATH9K_INT_TX) {
2854                 if (ah->txok_interrupt_mask)
2855                         mask |= AR_IMR_TXOK;
2856                 if (ah->txdesc_interrupt_mask)
2857                         mask |= AR_IMR_TXDESC;
2858                 if (ah->txerr_interrupt_mask)
2859                         mask |= AR_IMR_TXERR;
2860                 if (ah->txeol_interrupt_mask)
2861                         mask |= AR_IMR_TXEOL;
2862         }
2863         if (ints & ATH9K_INT_RX) {
2864                 mask |= AR_IMR_RXERR;
2865                 if (ah->config.rx_intr_mitigation)
2866                         mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
2867                 else
2868                         mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
2869                 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
2870                         mask |= AR_IMR_GENTMR;
2871         }
2872
2873         if (ints & (ATH9K_INT_BMISC)) {
2874                 mask |= AR_IMR_BCNMISC;
2875                 if (ints & ATH9K_INT_TIM)
2876                         mask2 |= AR_IMR_S2_TIM;
2877                 if (ints & ATH9K_INT_DTIM)
2878                         mask2 |= AR_IMR_S2_DTIM;
2879                 if (ints & ATH9K_INT_DTIMSYNC)
2880                         mask2 |= AR_IMR_S2_DTIMSYNC;
2881                 if (ints & ATH9K_INT_CABEND)
2882                         mask2 |= AR_IMR_S2_CABEND;
2883                 if (ints & ATH9K_INT_TSFOOR)
2884                         mask2 |= AR_IMR_S2_TSFOOR;
2885         }
2886
2887         if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
2888                 mask |= AR_IMR_BCNMISC;
2889                 if (ints & ATH9K_INT_GTT)
2890                         mask2 |= AR_IMR_S2_GTT;
2891                 if (ints & ATH9K_INT_CST)
2892                         mask2 |= AR_IMR_S2_CST;
2893         }
2894
2895         ath_print(common, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
2896         REG_WRITE(ah, AR_IMR, mask);
2897         mask = REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM |
2898                                            AR_IMR_S2_DTIM |
2899                                            AR_IMR_S2_DTIMSYNC |
2900                                            AR_IMR_S2_CABEND |
2901                                            AR_IMR_S2_CABTO |
2902                                            AR_IMR_S2_TSFOOR |
2903                                            AR_IMR_S2_GTT | AR_IMR_S2_CST);
2904         REG_WRITE(ah, AR_IMR_S2, mask | mask2);
2905         ah->mask_reg = ints;
2906
2907         if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2908                 if (ints & ATH9K_INT_TIM_TIMER)
2909                         REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
2910                 else
2911                         REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
2912         }
2913
2914         if (ints & ATH9K_INT_GLOBAL) {
2915                 ath_print(common, ATH_DBG_INTERRUPT, "enable IER\n");
2916                 REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
2917                 if (!AR_SREV_9100(ah)) {
2918                         REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
2919                                   AR_INTR_MAC_IRQ);
2920                         REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
2921
2922
2923                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
2924                                   AR_INTR_SYNC_DEFAULT);
2925                         REG_WRITE(ah, AR_INTR_SYNC_MASK,
2926                                   AR_INTR_SYNC_DEFAULT);
2927                 }
2928                 ath_print(common, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
2929                           REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
2930         }
2931
2932         return omask;
2933 }
2934 EXPORT_SYMBOL(ath9k_hw_set_interrupts);
2935
2936 /*******************/
2937 /* Beacon Handling */
2938 /*******************/
2939
2940 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
2941 {
2942         int flags = 0;
2943
2944         ah->beacon_interval = beacon_period;
2945
2946         switch (ah->opmode) {
2947         case NL80211_IFTYPE_STATION:
2948         case NL80211_IFTYPE_MONITOR:
2949                 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
2950                 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
2951                 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
2952                 flags |= AR_TBTT_TIMER_EN;
2953                 break;
2954         case NL80211_IFTYPE_ADHOC:
2955         case NL80211_IFTYPE_MESH_POINT:
2956                 REG_SET_BIT(ah, AR_TXCFG,
2957                             AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
2958                 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
2959                           TU_TO_USEC(next_beacon +
2960                                      (ah->atim_window ? ah->
2961                                       atim_window : 1)));
2962                 flags |= AR_NDP_TIMER_EN;
2963         case NL80211_IFTYPE_AP:
2964                 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
2965                 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
2966                           TU_TO_USEC(next_beacon -
2967                                      ah->config.
2968                                      dma_beacon_response_time));
2969                 REG_WRITE(ah, AR_NEXT_SWBA,
2970                           TU_TO_USEC(next_beacon -
2971                                      ah->config.
2972                                      sw_beacon_response_time));
2973                 flags |=
2974                         AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
2975                 break;
2976         default:
2977                 ath_print(ath9k_hw_common(ah), ATH_DBG_BEACON,
2978                           "%s: unsupported opmode: %d\n",
2979                           __func__, ah->opmode);
2980                 return;
2981                 break;
2982         }
2983
2984         REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
2985         REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
2986         REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
2987         REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
2988
2989         beacon_period &= ~ATH9K_BEACON_ENA;
2990         if (beacon_period & ATH9K_BEACON_RESET_TSF) {
2991                 ath9k_hw_reset_tsf(ah);
2992         }
2993
2994         REG_SET_BIT(ah, AR_TIMER_MODE, flags);
2995 }
2996 EXPORT_SYMBOL(ath9k_hw_beaconinit);
2997
2998 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
2999                                     const struct ath9k_beacon_state *bs)
3000 {
3001         u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
3002         struct ath9k_hw_capabilities *pCap = &ah->caps;
3003         struct ath_common *common = ath9k_hw_common(ah);
3004
3005         REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
3006
3007         REG_WRITE(ah, AR_BEACON_PERIOD,
3008                   TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3009         REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
3010                   TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3011
3012         REG_RMW_FIELD(ah, AR_RSSI_THR,
3013                       AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
3014
3015         beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
3016
3017         if (bs->bs_sleepduration > beaconintval)
3018                 beaconintval = bs->bs_sleepduration;
3019
3020         dtimperiod = bs->bs_dtimperiod;
3021         if (bs->bs_sleepduration > dtimperiod)
3022                 dtimperiod = bs->bs_sleepduration;
3023
3024         if (beaconintval == dtimperiod)
3025                 nextTbtt = bs->bs_nextdtim;
3026         else
3027                 nextTbtt = bs->bs_nexttbtt;
3028
3029         ath_print(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
3030         ath_print(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
3031         ath_print(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
3032         ath_print(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
3033
3034         REG_WRITE(ah, AR_NEXT_DTIM,
3035                   TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
3036         REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
3037
3038         REG_WRITE(ah, AR_SLEEP1,
3039                   SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
3040                   | AR_SLEEP1_ASSUME_DTIM);
3041
3042         if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
3043                 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
3044         else
3045                 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
3046
3047         REG_WRITE(ah, AR_SLEEP2,
3048                   SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
3049
3050         REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
3051         REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
3052
3053         REG_SET_BIT(ah, AR_TIMER_MODE,
3054                     AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
3055                     AR_DTIM_TIMER_EN);
3056
3057         /* TSF Out of Range Threshold */
3058         REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
3059 }
3060 EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
3061
3062 /*******************/
3063 /* HW Capabilities */
3064 /*******************/
3065
3066 int ath9k_hw_fill_cap_info(struct ath_hw *ah)
3067 {
3068         struct ath9k_hw_capabilities *pCap = &ah->caps;
3069         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
3070         struct ath_common *common = ath9k_hw_common(ah);
3071         struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
3072
3073         u16 capField = 0, eeval;
3074
3075         eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
3076         regulatory->current_rd = eeval;
3077
3078         eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
3079         if (AR_SREV_9285_10_OR_LATER(ah))
3080                 eeval |= AR9285_RDEXT_DEFAULT;
3081         regulatory->current_rd_ext = eeval;
3082
3083         capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
3084
3085         if (ah->opmode != NL80211_IFTYPE_AP &&
3086             ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
3087                 if (regulatory->current_rd == 0x64 ||
3088                     regulatory->current_rd == 0x65)
3089                         regulatory->current_rd += 5;
3090                 else if (regulatory->current_rd == 0x41)
3091                         regulatory->current_rd = 0x43;
3092                 ath_print(common, ATH_DBG_REGULATORY,
3093                           "regdomain mapped to 0x%x\n", regulatory->current_rd);
3094         }
3095
3096         eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
3097         if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
3098                 ath_print(common, ATH_DBG_FATAL,
3099                           "no band has been marked as supported in EEPROM.\n");
3100                 return -EINVAL;
3101         }
3102
3103         bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
3104
3105         if (eeval & AR5416_OPFLAGS_11A) {
3106                 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
3107                 if (ah->config.ht_enable) {
3108                         if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
3109                                 set_bit(ATH9K_MODE_11NA_HT20,
3110                                         pCap->wireless_modes);
3111                         if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
3112                                 set_bit(ATH9K_MODE_11NA_HT40PLUS,
3113                                         pCap->wireless_modes);
3114                                 set_bit(ATH9K_MODE_11NA_HT40MINUS,
3115                                         pCap->wireless_modes);
3116                         }
3117                 }
3118         }
3119
3120         if (eeval & AR5416_OPFLAGS_11G) {
3121                 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
3122                 if (ah->config.ht_enable) {
3123                         if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
3124                                 set_bit(ATH9K_MODE_11NG_HT20,
3125                                         pCap->wireless_modes);
3126                         if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
3127                                 set_bit(ATH9K_MODE_11NG_HT40PLUS,
3128                                         pCap->wireless_modes);
3129                                 set_bit(ATH9K_MODE_11NG_HT40MINUS,
3130                                         pCap->wireless_modes);
3131                         }
3132                 }
3133         }
3134
3135         pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
3136         /*
3137          * For AR9271 we will temporarilly uses the rx chainmax as read from
3138          * the EEPROM.
3139          */
3140         if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
3141             !(eeval & AR5416_OPFLAGS_11A) &&
3142             !(AR_SREV_9271(ah)))
3143                 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
3144                 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
3145         else
3146                 /* Use rx_chainmask from EEPROM. */
3147                 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
3148
3149         if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0)))
3150                 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
3151
3152         pCap->low_2ghz_chan = 2312;
3153         pCap->high_2ghz_chan = 2732;
3154
3155         pCap->low_5ghz_chan = 4920;
3156         pCap->high_5ghz_chan = 6100;
3157
3158         pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
3159         pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
3160         pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
3161
3162         pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
3163         pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
3164         pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
3165
3166         if (ah->config.ht_enable)
3167                 pCap->hw_caps |= ATH9K_HW_CAP_HT;
3168         else
3169                 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
3170
3171         pCap->hw_caps |= ATH9K_HW_CAP_GTT;
3172         pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
3173         pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
3174         pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
3175
3176         if (capField & AR_EEPROM_EEPCAP_MAXQCU)
3177                 pCap->total_queues =
3178                         MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
3179         else
3180                 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
3181
3182         if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
3183                 pCap->keycache_size =
3184                         1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
3185         else
3186                 pCap->keycache_size = AR_KEYTABLE_SIZE;
3187
3188         pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
3189
3190         if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
3191                 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD >> 1;
3192         else
3193                 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
3194
3195         if (AR_SREV_9285_10_OR_LATER(ah))
3196                 pCap->num_gpio_pins = AR9285_NUM_GPIO;
3197         else if (AR_SREV_9280_10_OR_LATER(ah))
3198                 pCap->num_gpio_pins = AR928X_NUM_GPIO;
3199         else
3200                 pCap->num_gpio_pins = AR_NUM_GPIO;
3201
3202         if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
3203                 pCap->hw_caps |= ATH9K_HW_CAP_CST;
3204                 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
3205         } else {
3206                 pCap->rts_aggr_limit = (8 * 1024);
3207         }
3208
3209         pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
3210
3211 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
3212         ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
3213         if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
3214                 ah->rfkill_gpio =
3215                         MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
3216                 ah->rfkill_polarity =
3217                         MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
3218
3219                 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
3220         }
3221 #endif
3222
3223         pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
3224
3225         if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
3226                 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
3227         else
3228                 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
3229
3230         if (regulatory->current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
3231                 pCap->reg_cap =
3232                         AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3233                         AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
3234                         AR_EEPROM_EEREGCAP_EN_KK_U2 |
3235                         AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
3236         } else {
3237                 pCap->reg_cap =
3238                         AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3239                         AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
3240         }
3241
3242         /* Advertise midband for AR5416 with FCC midband set in eeprom */
3243         if (regulatory->current_rd_ext & (1 << REG_EXT_FCC_MIDBAND) &&
3244             AR_SREV_5416(ah))
3245                 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
3246
3247         pCap->num_antcfg_5ghz =
3248                 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
3249         pCap->num_antcfg_2ghz =
3250                 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
3251
3252         if (AR_SREV_9280_10_OR_LATER(ah) &&
3253             ath9k_hw_btcoex_supported(ah)) {
3254                 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO;
3255                 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO;
3256
3257                 if (AR_SREV_9285(ah)) {
3258                         btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
3259                         btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO;
3260                 } else {
3261                         btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE;
3262                 }
3263         } else {
3264                 btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE;
3265         }
3266
3267         return 0;
3268 }
3269
3270 bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3271                             u32 capability, u32 *result)
3272 {
3273         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
3274         switch (type) {
3275         case ATH9K_CAP_CIPHER:
3276                 switch (capability) {
3277                 case ATH9K_CIPHER_AES_CCM:
3278                 case ATH9K_CIPHER_AES_OCB:
3279                 case ATH9K_CIPHER_TKIP:
3280                 case ATH9K_CIPHER_WEP:
3281                 case ATH9K_CIPHER_MIC:
3282                 case ATH9K_CIPHER_CLR:
3283                         return true;
3284                 default:
3285                         return false;
3286                 }
3287         case ATH9K_CAP_TKIP_MIC:
3288                 switch (capability) {
3289                 case 0:
3290                         return true;
3291                 case 1:
3292                         return (ah->sta_id1_defaults &
3293                                 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
3294                         false;
3295                 }
3296         case ATH9K_CAP_TKIP_SPLIT:
3297                 return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
3298                         false : true;
3299         case ATH9K_CAP_DIVERSITY:
3300                 return (REG_READ(ah, AR_PHY_CCK_DETECT) &
3301                         AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
3302                         true : false;
3303         case ATH9K_CAP_MCAST_KEYSRCH:
3304                 switch (capability) {
3305                 case 0:
3306                         return true;
3307                 case 1:
3308                         if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
3309                                 return false;
3310                         } else {
3311                                 return (ah->sta_id1_defaults &
3312                                         AR_STA_ID1_MCAST_KSRCH) ? true :
3313                                         false;
3314                         }
3315                 }
3316                 return false;
3317         case ATH9K_CAP_TXPOW:
3318                 switch (capability) {
3319                 case 0:
3320                         return 0;
3321                 case 1:
3322                         *result = regulatory->power_limit;
3323                         return 0;
3324                 case 2:
3325                         *result = regulatory->max_power_level;
3326                         return 0;
3327                 case 3:
3328                         *result = regulatory->tp_scale;
3329                         return 0;
3330                 }
3331                 return false;
3332         case ATH9K_CAP_DS:
3333                 return (AR_SREV_9280_20_OR_LATER(ah) &&
3334                         (ah->eep_ops->get_eeprom(ah, EEP_RC_CHAIN_MASK) == 1))
3335                         ? false : true;
3336         default:
3337                 return false;
3338         }
3339 }
3340 EXPORT_SYMBOL(ath9k_hw_getcapability);
3341
3342 bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3343                             u32 capability, u32 setting, int *status)
3344 {
3345         u32 v;
3346
3347         switch (type) {
3348         case ATH9K_CAP_TKIP_MIC:
3349                 if (setting)
3350                         ah->sta_id1_defaults |=
3351                                 AR_STA_ID1_CRPT_MIC_ENABLE;
3352                 else
3353                         ah->sta_id1_defaults &=
3354                                 ~AR_STA_ID1_CRPT_MIC_ENABLE;
3355                 return true;
3356         case ATH9K_CAP_DIVERSITY:
3357                 v = REG_READ(ah, AR_PHY_CCK_DETECT);
3358                 if (setting)
3359                         v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3360                 else
3361                         v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3362                 REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
3363                 return true;
3364         case ATH9K_CAP_MCAST_KEYSRCH:
3365                 if (setting)
3366                         ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH;
3367                 else
3368                         ah->sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH;
3369                 return true;
3370         default:
3371                 return false;
3372         }
3373 }
3374 EXPORT_SYMBOL(ath9k_hw_setcapability);
3375
3376 /****************************/
3377 /* GPIO / RFKILL / Antennae */
3378 /****************************/
3379
3380 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
3381                                          u32 gpio, u32 type)
3382 {
3383         int addr;
3384         u32 gpio_shift, tmp;
3385
3386         if (gpio > 11)
3387                 addr = AR_GPIO_OUTPUT_MUX3;
3388         else if (gpio > 5)
3389                 addr = AR_GPIO_OUTPUT_MUX2;
3390         else
3391                 addr = AR_GPIO_OUTPUT_MUX1;
3392
3393         gpio_shift = (gpio % 6) * 5;
3394
3395         if (AR_SREV_9280_20_OR_LATER(ah)
3396             || (addr != AR_GPIO_OUTPUT_MUX1)) {
3397                 REG_RMW(ah, addr, (type << gpio_shift),
3398                         (0x1f << gpio_shift));
3399         } else {
3400                 tmp = REG_READ(ah, addr);
3401                 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
3402                 tmp &= ~(0x1f << gpio_shift);
3403                 tmp |= (type << gpio_shift);
3404                 REG_WRITE(ah, addr, tmp);
3405         }
3406 }
3407
3408 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
3409 {
3410         u32 gpio_shift;
3411
3412         BUG_ON(gpio >= ah->caps.num_gpio_pins);
3413
3414         gpio_shift = gpio << 1;
3415
3416         REG_RMW(ah,
3417                 AR_GPIO_OE_OUT,
3418                 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
3419                 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3420 }
3421 EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
3422
3423 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
3424 {
3425 #define MS_REG_READ(x, y) \
3426         (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
3427
3428         if (gpio >= ah->caps.num_gpio_pins)
3429                 return 0xffffffff;
3430
3431         if (AR_SREV_9287_10_OR_LATER(ah))
3432                 return MS_REG_READ(AR9287, gpio) != 0;
3433         else if (AR_SREV_9285_10_OR_LATER(ah))
3434                 return MS_REG_READ(AR9285, gpio) != 0;
3435         else if (AR_SREV_9280_10_OR_LATER(ah))
3436                 return MS_REG_READ(AR928X, gpio) != 0;
3437         else
3438                 return MS_REG_READ(AR, gpio) != 0;
3439 }
3440 EXPORT_SYMBOL(ath9k_hw_gpio_get);
3441
3442 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
3443                          u32 ah_signal_type)
3444 {
3445         u32 gpio_shift;
3446
3447         ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
3448
3449         gpio_shift = 2 * gpio;
3450
3451         REG_RMW(ah,
3452                 AR_GPIO_OE_OUT,
3453                 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
3454                 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3455 }
3456 EXPORT_SYMBOL(ath9k_hw_cfg_output);
3457
3458 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
3459 {
3460         REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
3461                 AR_GPIO_BIT(gpio));
3462 }
3463 EXPORT_SYMBOL(ath9k_hw_set_gpio);
3464
3465 u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
3466 {
3467         return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
3468 }
3469 EXPORT_SYMBOL(ath9k_hw_getdefantenna);
3470
3471 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
3472 {
3473         REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
3474 }
3475 EXPORT_SYMBOL(ath9k_hw_setantenna);
3476
3477 /*********************/
3478 /* General Operation */
3479 /*********************/
3480
3481 u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
3482 {
3483         u32 bits = REG_READ(ah, AR_RX_FILTER);
3484         u32 phybits = REG_READ(ah, AR_PHY_ERR);
3485
3486         if (phybits & AR_PHY_ERR_RADAR)
3487                 bits |= ATH9K_RX_FILTER_PHYRADAR;
3488         if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
3489                 bits |= ATH9K_RX_FILTER_PHYERR;
3490
3491         return bits;
3492 }
3493 EXPORT_SYMBOL(ath9k_hw_getrxfilter);
3494
3495 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
3496 {
3497         u32 phybits;
3498
3499         REG_WRITE(ah, AR_RX_FILTER, bits);
3500
3501         phybits = 0;
3502         if (bits & ATH9K_RX_FILTER_PHYRADAR)
3503                 phybits |= AR_PHY_ERR_RADAR;
3504         if (bits & ATH9K_RX_FILTER_PHYERR)
3505                 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
3506         REG_WRITE(ah, AR_PHY_ERR, phybits);
3507
3508         if (phybits)
3509                 REG_WRITE(ah, AR_RXCFG,
3510                           REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
3511         else
3512                 REG_WRITE(ah, AR_RXCFG,
3513                           REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
3514 }
3515 EXPORT_SYMBOL(ath9k_hw_setrxfilter);
3516
3517 bool ath9k_hw_phy_disable(struct ath_hw *ah)
3518 {
3519         if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
3520                 return false;
3521
3522         ath9k_hw_init_pll(ah, NULL);
3523         return true;
3524 }
3525 EXPORT_SYMBOL(ath9k_hw_phy_disable);
3526
3527 bool ath9k_hw_disable(struct ath_hw *ah)
3528 {
3529         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
3530                 return false;
3531
3532         if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
3533                 return false;
3534
3535         ath9k_hw_init_pll(ah, NULL);
3536         return true;
3537 }
3538 EXPORT_SYMBOL(ath9k_hw_disable);
3539
3540 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
3541 {
3542         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
3543         struct ath9k_channel *chan = ah->curchan;
3544         struct ieee80211_channel *channel = chan->chan;
3545
3546         regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER);
3547
3548         ah->eep_ops->set_txpower(ah, chan,
3549                                  ath9k_regd_get_ctl(regulatory, chan),
3550                                  channel->max_antenna_gain * 2,
3551                                  channel->max_power * 2,
3552                                  min((u32) MAX_RATE_POWER,
3553                                  (u32) regulatory->power_limit));
3554 }
3555 EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
3556
3557 void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac)
3558 {
3559         memcpy(ath9k_hw_common(ah)->macaddr, mac, ETH_ALEN);
3560 }
3561 EXPORT_SYMBOL(ath9k_hw_setmac);
3562
3563 void ath9k_hw_setopmode(struct ath_hw *ah)
3564 {
3565         ath9k_hw_set_operating_mode(ah, ah->opmode);
3566 }
3567 EXPORT_SYMBOL(ath9k_hw_setopmode);
3568
3569 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
3570 {
3571         REG_WRITE(ah, AR_MCAST_FIL0, filter0);
3572         REG_WRITE(ah, AR_MCAST_FIL1, filter1);
3573 }
3574 EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
3575
3576 void ath9k_hw_write_associd(struct ath_hw *ah)
3577 {
3578         struct ath_common *common = ath9k_hw_common(ah);
3579
3580         REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
3581         REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
3582                   ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
3583 }
3584 EXPORT_SYMBOL(ath9k_hw_write_associd);
3585
3586 u64 ath9k_hw_gettsf64(struct ath_hw *ah)
3587 {
3588         u64 tsf;
3589
3590         tsf = REG_READ(ah, AR_TSF_U32);
3591         tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32);
3592
3593         return tsf;
3594 }
3595 EXPORT_SYMBOL(ath9k_hw_gettsf64);
3596
3597 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
3598 {
3599         REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
3600         REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
3601 }
3602 EXPORT_SYMBOL(ath9k_hw_settsf64);
3603
3604 void ath9k_hw_reset_tsf(struct ath_hw *ah)
3605 {
3606         if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
3607                            AH_TSF_WRITE_TIMEOUT))
3608                 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
3609                           "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
3610
3611         REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
3612 }
3613 EXPORT_SYMBOL(ath9k_hw_reset_tsf);
3614
3615 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
3616 {
3617         if (setting)
3618                 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
3619         else
3620                 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
3621 }
3622 EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
3623
3624 /*
3625  *  Extend 15-bit time stamp from rx descriptor to
3626  *  a full 64-bit TSF using the current h/w TSF.
3627 */
3628 u64 ath9k_hw_extend_tsf(struct ath_hw *ah, u32 rstamp)
3629 {
3630         u64 tsf;
3631
3632         tsf = ath9k_hw_gettsf64(ah);
3633         if ((tsf & 0x7fff) < rstamp)
3634                 tsf -= 0x8000;
3635         return (tsf & ~0x7fff) | rstamp;
3636 }
3637 EXPORT_SYMBOL(ath9k_hw_extend_tsf);
3638
3639 void ath9k_hw_set11nmac2040(struct ath_hw *ah)
3640 {
3641         struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
3642         u32 macmode;
3643
3644         if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca)
3645                 macmode = AR_2040_JOINED_RX_CLEAR;
3646         else
3647                 macmode = 0;
3648
3649         REG_WRITE(ah, AR_2040_MODE, macmode);
3650 }
3651
3652 /* HW Generic timers configuration */
3653
3654 static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
3655 {
3656         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3657         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3658         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3659         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3660         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3661         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3662         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3663         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3664         {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
3665         {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
3666                                 AR_NDP2_TIMER_MODE, 0x0002},
3667         {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
3668                                 AR_NDP2_TIMER_MODE, 0x0004},
3669         {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
3670                                 AR_NDP2_TIMER_MODE, 0x0008},
3671         {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
3672                                 AR_NDP2_TIMER_MODE, 0x0010},
3673         {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
3674                                 AR_NDP2_TIMER_MODE, 0x0020},
3675         {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
3676                                 AR_NDP2_TIMER_MODE, 0x0040},
3677         {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
3678                                 AR_NDP2_TIMER_MODE, 0x0080}
3679 };
3680
3681 /* HW generic timer primitives */
3682
3683 /* compute and clear index of rightmost 1 */
3684 static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
3685 {
3686         u32 b;
3687
3688         b = *mask;
3689         b &= (0-b);
3690         *mask &= ~b;
3691         b *= debruijn32;
3692         b >>= 27;
3693
3694         return timer_table->gen_timer_index[b];
3695 }
3696
3697 u32 ath9k_hw_gettsf32(struct ath_hw *ah)
3698 {
3699         return REG_READ(ah, AR_TSF_L32);
3700 }
3701 EXPORT_SYMBOL(ath9k_hw_gettsf32);
3702
3703 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
3704                                           void (*trigger)(void *),
3705                                           void (*overflow)(void *),
3706                                           void *arg,
3707                                           u8 timer_index)
3708 {
3709         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3710         struct ath_gen_timer *timer;
3711
3712         timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
3713
3714         if (timer == NULL) {
3715                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
3716                           "Failed to allocate memory"
3717                           "for hw timer[%d]\n", timer_index);
3718                 return NULL;
3719         }
3720
3721         /* allocate a hardware generic timer slot */
3722         timer_table->timers[timer_index] = timer;
3723         timer->index = timer_index;
3724         timer->trigger = trigger;
3725         timer->overflow = overflow;
3726         timer->arg = arg;
3727
3728         return timer;
3729 }
3730 EXPORT_SYMBOL(ath_gen_timer_alloc);
3731
3732 void ath9k_hw_gen_timer_start(struct ath_hw *ah,
3733                               struct ath_gen_timer *timer,
3734                               u32 timer_next,
3735                               u32 timer_period)
3736 {
3737         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3738         u32 tsf;
3739
3740         BUG_ON(!timer_period);
3741
3742         set_bit(timer->index, &timer_table->timer_mask.timer_bits);
3743
3744         tsf = ath9k_hw_gettsf32(ah);
3745
3746         ath_print(ath9k_hw_common(ah), ATH_DBG_HWTIMER,
3747                   "curent tsf %x period %x"
3748                   "timer_next %x\n", tsf, timer_period, timer_next);
3749
3750         /*
3751          * Pull timer_next forward if the current TSF already passed it
3752          * because of software latency
3753          */
3754         if (timer_next < tsf)
3755                 timer_next = tsf + timer_period;
3756
3757         /*
3758          * Program generic timer registers
3759          */
3760         REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
3761                  timer_next);
3762         REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
3763                   timer_period);
3764         REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
3765                     gen_tmr_configuration[timer->index].mode_mask);
3766
3767         /* Enable both trigger and thresh interrupt masks */
3768         REG_SET_BIT(ah, AR_IMR_S5,
3769                 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
3770                 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
3771 }
3772 EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
3773
3774 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
3775 {
3776         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3777
3778         if ((timer->index < AR_FIRST_NDP_TIMER) ||
3779                 (timer->index >= ATH_MAX_GEN_TIMER)) {
3780                 return;
3781         }
3782
3783         /* Clear generic timer enable bits. */
3784         REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
3785                         gen_tmr_configuration[timer->index].mode_mask);
3786
3787         /* Disable both trigger and thresh interrupt masks */
3788         REG_CLR_BIT(ah, AR_IMR_S5,
3789                 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
3790                 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
3791
3792         clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
3793 }
3794 EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
3795
3796 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
3797 {
3798         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3799
3800         /* free the hardware generic timer slot */
3801         timer_table->timers[timer->index] = NULL;
3802         kfree(timer);
3803 }
3804 EXPORT_SYMBOL(ath_gen_timer_free);
3805
3806 /*
3807  * Generic Timer Interrupts handling
3808  */
3809 void ath_gen_timer_isr(struct ath_hw *ah)
3810 {
3811         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3812         struct ath_gen_timer *timer;
3813         struct ath_common *common = ath9k_hw_common(ah);
3814         u32 trigger_mask, thresh_mask, index;
3815
3816         /* get hardware generic timer interrupt status */
3817         trigger_mask = ah->intr_gen_timer_trigger;
3818         thresh_mask = ah->intr_gen_timer_thresh;
3819         trigger_mask &= timer_table->timer_mask.val;
3820         thresh_mask &= timer_table->timer_mask.val;
3821
3822         trigger_mask &= ~thresh_mask;
3823
3824         while (thresh_mask) {
3825                 index = rightmost_index(timer_table, &thresh_mask);
3826                 timer = timer_table->timers[index];
3827                 BUG_ON(!timer);
3828                 ath_print(common, ATH_DBG_HWTIMER,
3829                           "TSF overflow for Gen timer %d\n", index);
3830                 timer->overflow(timer->arg);
3831         }
3832
3833         while (trigger_mask) {
3834                 index = rightmost_index(timer_table, &trigger_mask);
3835                 timer = timer_table->timers[index];
3836                 BUG_ON(!timer);
3837                 ath_print(common, ATH_DBG_HWTIMER,
3838                           "Gen timer[%d] trigger\n", index);
3839                 timer->trigger(timer->arg);
3840         }
3841 }
3842 EXPORT_SYMBOL(ath_gen_timer_isr);
3843
3844 static struct {
3845         u32 version;
3846         const char * name;
3847 } ath_mac_bb_names[] = {
3848         /* Devices with external radios */
3849         { AR_SREV_VERSION_5416_PCI,     "5416" },
3850         { AR_SREV_VERSION_5416_PCIE,    "5418" },
3851         { AR_SREV_VERSION_9100,         "9100" },
3852         { AR_SREV_VERSION_9160,         "9160" },
3853         /* Single-chip solutions */
3854         { AR_SREV_VERSION_9280,         "9280" },
3855         { AR_SREV_VERSION_9285,         "9285" },
3856         { AR_SREV_VERSION_9287,         "9287" },
3857         { AR_SREV_VERSION_9271,         "9271" },
3858 };
3859
3860 /* For devices with external radios */
3861 static struct {
3862         u16 version;
3863         const char * name;
3864 } ath_rf_names[] = {
3865         { 0,                            "5133" },
3866         { AR_RAD5133_SREV_MAJOR,        "5133" },
3867         { AR_RAD5122_SREV_MAJOR,        "5122" },
3868         { AR_RAD2133_SREV_MAJOR,        "2133" },
3869         { AR_RAD2122_SREV_MAJOR,        "2122" }
3870 };
3871
3872 /*
3873  * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
3874  */
3875 static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
3876 {
3877         int i;
3878
3879         for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
3880                 if (ath_mac_bb_names[i].version == mac_bb_version) {
3881                         return ath_mac_bb_names[i].name;
3882                 }
3883         }
3884
3885         return "????";
3886 }
3887
3888 /*
3889  * Return the RF name. "????" is returned if the RF is unknown.
3890  * Used for devices with external radios.
3891  */
3892 static const char *ath9k_hw_rf_name(u16 rf_version)
3893 {
3894         int i;
3895
3896         for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
3897                 if (ath_rf_names[i].version == rf_version) {
3898                         return ath_rf_names[i].name;
3899                 }
3900         }
3901
3902         return "????";
3903 }
3904
3905 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
3906 {
3907         int used;
3908
3909         /* chipsets >= AR9280 are single-chip */
3910         if (AR_SREV_9280_10_OR_LATER(ah)) {
3911                 used = snprintf(hw_name, len,
3912                                "Atheros AR%s Rev:%x",
3913                                ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3914                                ah->hw_version.macRev);
3915         }
3916         else {
3917                 used = snprintf(hw_name, len,
3918                                "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
3919                                ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3920                                ah->hw_version.macRev,
3921                                ath9k_hw_rf_name((ah->hw_version.analog5GhzRev &
3922                                                 AR_RADIO_SREV_MAJOR)),
3923                                ah->hw_version.phyRev);
3924         }
3925
3926         hw_name[used] = '\0';
3927 }
3928 EXPORT_SYMBOL(ath9k_hw_name);