SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/net/wireless/ath/ath5k/phy.c

   1 /*
   2  * PHY functions
   3  *
   4  * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org>
   5  * Copyright (c) 2006-2009 Nick Kossifidis <mickflemm@gmail.com>
   6  * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com>
   7  * Copyright (c) 2008-2009 Felix Fietkau <nbd@openwrt.org>
   8  *
   9  * Permission to use, copy, modify, and distribute this software for any
  10  * purpose with or without fee is hereby granted, provided that the above
  11  * copyright notice and this permission notice appear in all copies.
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  14  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  15  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  16  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  17  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  18  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  19  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  20  *
  21  */
  22
  23 #include <linux/delay.h>
  24 #include <linux/slab.h>
  25
  26 #include "ath5k.h"
  27 #include "reg.h"
  28 #include "base.h"
  29 #include "rfbuffer.h"
  30 #include "rfgain.h"
  31
  32 /*
  33  * Used to modify RF Banks before writing them to AR5K_RF_BUFFER
  34  */
  35 static unsigned int ath5k_hw_rfb_op(struct ath5k_hw *ah,
  36                                         const struct ath5k_rf_reg *rf_regs,
  37                                         u32 val, u8 reg_id, bool set)
  38 {
  39         const struct ath5k_rf_reg *rfreg = NULL;
  40         u8 offset, bank, num_bits, col, position;
  41         u16 entry;
  42         u32 mask, data, last_bit, bits_shifted, first_bit;
  43         u32 *rfb;
  44         s32 bits_left;
  45         int i;
  46
  47         data = 0;
  48         rfb = ah->ah_rf_banks;
  49
  50         for (i = 0; i < ah->ah_rf_regs_count; i++) {
  51                 if (rf_regs[i].index == reg_id) {
  52                         rfreg = &rf_regs[i];
  53                         break;
  54                 }
  55         }
  56
  57         if (rfb == NULL || rfreg == NULL) {
  58                 ATH5K_PRINTF("Rf register not found!\n");
  59                 /* should not happen */
  60                 return 0;
  61         }
  62
  63         bank = rfreg->bank;
  64         num_bits = rfreg->field.len;
  65         first_bit = rfreg->field.pos;
  66         col = rfreg->field.col;
  67
  68         /* first_bit is an offset from bank's
  69          * start. Since we have all banks on
  70          * the same array, we use this offset
  71          * to mark each bank's start */
  72         offset = ah->ah_offset[bank];
  73
  74         /* Boundary check */
  75         if (!(col <= 3 && num_bits <= 32 && first_bit + num_bits <= 319)) {
  76                 ATH5K_PRINTF("invalid values at offset %u\n", offset);
  77                 return 0;
  78         }
  79
  80         entry = ((first_bit - 1) / 8) + offset;
  81         position = (first_bit - 1) % 8;
  82
  83         if (set)
  84                 data = ath5k_hw_bitswap(val, num_bits);
  85
  86         for (bits_shifted = 0, bits_left = num_bits; bits_left > 0;
  87         position = 0, entry++) {
  88
  89                 last_bit = (position + bits_left > 8) ? 8 :
  90                                         position + bits_left;
  91
  92                 mask = (((1 << last_bit) - 1) ^ ((1 << position) - 1)) <<
  93                                                                 (col * 8);
  94
  95                 if (set) {
  96                         rfb[entry] &= ~mask;
  97                         rfb[entry] |= ((data << position) << (col * 8)) & mask;
  98                         data >>= (8 - position);
  99                 } else {
 100                         data |= (((rfb[entry] & mask) >> (col * 8)) >> position)
 101                                 << bits_shifted;
 102                         bits_shifted += last_bit - position;
 103                 }
 104
 105                 bits_left -= 8 - position;
 106         }
 107
 108         data = set ? 1 : ath5k_hw_bitswap(data, num_bits);
 109
 110         return data;
 111 }
 112
 113 /**********************\
 114 * RF Gain optimization *
 115 \**********************/
 116
 117 /*
 118  * This code is used to optimize rf gain on different environments
 119  * (temperature mostly) based on feedback from a power detector.
 120  *
 121  * It's only used on RF5111 and RF5112, later RF chips seem to have
 122  * auto adjustment on hw -notice they have a much smaller BANK 7 and
 123  * no gain optimization ladder-.
 124  *
 125  * For more infos check out this patent doc
 126  * http://www.freepatentsonline.com/7400691.html
 127  *
 128  * This paper describes power drops as seen on the receiver due to
 129  * probe packets
 130  * http://www.cnri.dit.ie/publications/ICT08%20-%20Practical%20Issues
 131  * %20of%20Power%20Control.pdf
 132  *
 133  * And this is the MadWiFi bug entry related to the above
 134  * http://madwifi-project.org/ticket/1659
 135  * with various measurements and diagrams
 136  *
 137  * TODO: Deal with power drops due to probes by setting an apropriate
 138  * tx power on the probe packets ! Make this part of the calibration process.
 139  */
 140
 141 /* Initialize ah_gain durring attach */
 142 int ath5k_hw_rfgain_opt_init(struct ath5k_hw *ah)
 143 {
 144         /* Initialize the gain optimization values */
 145         switch (ah->ah_radio) {
 146         case AR5K_RF5111:
 147                 ah->ah_gain.g_step_idx = rfgain_opt_5111.go_default;
 148                 ah->ah_gain.g_low = 20;
 149                 ah->ah_gain.g_high = 35;
 150                 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
 151                 break;
 152         case AR5K_RF5112:
 153                 ah->ah_gain.g_step_idx = rfgain_opt_5112.go_default;
 154                 ah->ah_gain.g_low = 20;
 155                 ah->ah_gain.g_high = 85;
 156                 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
 157                 break;
 158         default:
 159                 return -EINVAL;
 160         }
 161
 162         return 0;
 163 }
 164
 165 /* Schedule a gain probe check on the next transmited packet.
 166  * That means our next packet is going to be sent with lower
 167  * tx power and a Peak to Average Power Detector (PAPD) will try
 168  * to measure the gain.
 169  *
 170  * XXX:  How about forcing a tx packet (bypassing PCU arbitrator etc)
 171  * just after we enable the probe so that we don't mess with
 172  * standard traffic ? Maybe it's time to use sw interrupts and
 173  * a probe tasklet !!!
 174  */
 175 static void ath5k_hw_request_rfgain_probe(struct ath5k_hw *ah)
 176 {
 177
 178         /* Skip if gain calibration is inactive or
 179          * we already handle a probe request */
 180         if (ah->ah_gain.g_state != AR5K_RFGAIN_ACTIVE)
 181                 return;
 182
 183         /* Send the packet with 2dB below max power as
 184          * patent doc suggest */
 185         ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txpower.txp_ofdm - 4,
 186                         AR5K_PHY_PAPD_PROBE_TXPOWER) |
 187                         AR5K_PHY_PAPD_PROBE_TX_NEXT, AR5K_PHY_PAPD_PROBE);
 188
 189         ah->ah_gain.g_state = AR5K_RFGAIN_READ_REQUESTED;
 190
 191 }
 192
 193 /* Calculate gain_F measurement correction
 194  * based on the current step for RF5112 rev. 2 */
 195 static u32 ath5k_hw_rf_gainf_corr(struct ath5k_hw *ah)
 196 {
 197         u32 mix, step;
 198         u32 *rf;
 199         const struct ath5k_gain_opt *go;
 200         const struct ath5k_gain_opt_step *g_step;
 201         const struct ath5k_rf_reg *rf_regs;
 202
 203         /* Only RF5112 Rev. 2 supports it */
 204         if ((ah->ah_radio != AR5K_RF5112) ||
 205         (ah->ah_radio_5ghz_revision <= AR5K_SREV_RAD_5112A))
 206                 return 0;
 207
 208         go = &rfgain_opt_5112;
 209         rf_regs = rf_regs_5112a;
 210         ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112a);
 211
 212         g_step = &go->go_step[ah->ah_gain.g_step_idx];
 213
 214         if (ah->ah_rf_banks == NULL)
 215                 return 0;
 216
 217         rf = ah->ah_rf_banks;
 218         ah->ah_gain.g_f_corr = 0;
 219
 220         /* No VGA (Variable Gain Amplifier) override, skip */
 221         if (ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXVGA_OVR, false) != 1)
 222                 return 0;
 223
 224         /* Mix gain stepping */
 225         step = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXGAIN_STEP, false);
 226
 227         /* Mix gain override */
 228         mix = g_step->gos_param[0];
 229
 230         switch (mix) {
 231         case 3:
 232                 ah->ah_gain.g_f_corr = step * 2;
 233                 break;
 234         case 2:
 235                 ah->ah_gain.g_f_corr = (step - 5) * 2;
 236                 break;
 237         case 1:
 238                 ah->ah_gain.g_f_corr = step;
 239                 break;
 240         default:
 241                 ah->ah_gain.g_f_corr = 0;
 242                 break;
 243         }
 244
 245         return ah->ah_gain.g_f_corr;
 246 }
 247
 248 /* Check if current gain_F measurement is in the range of our
 249  * power detector windows. If we get a measurement outside range
 250  * we know it's not accurate (detectors can't measure anything outside
 251  * their detection window) so we must ignore it */
 252 static bool ath5k_hw_rf_check_gainf_readback(struct ath5k_hw *ah)
 253 {
 254         const struct ath5k_rf_reg *rf_regs;
 255         u32 step, mix_ovr, level[4];
 256         u32 *rf;
 257
 258         if (ah->ah_rf_banks == NULL)
 259                 return false;
 260
 261         rf = ah->ah_rf_banks;
 262
 263         if (ah->ah_radio == AR5K_RF5111) {
 264
 265                 rf_regs = rf_regs_5111;
 266                 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5111);
 267
 268                 step = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_RFGAIN_STEP,
 269                         false);
 270
 271                 level[0] = 0;
 272                 level[1] = (step == 63) ? 50 : step + 4;
 273                 level[2] = (step != 63) ? 64 : level[0];
 274                 level[3] = level[2] + 50 ;
 275
 276                 ah->ah_gain.g_high = level[3] -
 277                         (step == 63 ? AR5K_GAIN_DYN_ADJUST_HI_MARGIN : -5);
 278                 ah->ah_gain.g_low = level[0] +
 279                         (step == 63 ? AR5K_GAIN_DYN_ADJUST_LO_MARGIN : 0);
 280         } else {
 281
 282                 rf_regs = rf_regs_5112;
 283                 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112);
 284
 285                 mix_ovr = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXVGA_OVR,
 286                         false);
 287
 288                 level[0] = level[2] = 0;
 289
 290                 if (mix_ovr == 1) {
 291                         level[1] = level[3] = 83;
 292                 } else {
 293                         level[1] = level[3] = 107;
 294                         ah->ah_gain.g_high = 55;
 295                 }
 296         }
 297
 298         return (ah->ah_gain.g_current >= level[0] &&
 299                         ah->ah_gain.g_current <= level[1]) ||
 300                 (ah->ah_gain.g_current >= level[2] &&
 301                         ah->ah_gain.g_current <= level[3]);
 302 }
 303
 304 /* Perform gain_F adjustment by choosing the right set
 305  * of parameters from rf gain optimization ladder */
 306 static s8 ath5k_hw_rf_gainf_adjust(struct ath5k_hw *ah)
 307 {
 308         const struct ath5k_gain_opt *go;
 309         const struct ath5k_gain_opt_step *g_step;
 310         int ret = 0;
 311
 312         switch (ah->ah_radio) {
 313         case AR5K_RF5111:
 314                 go = &rfgain_opt_5111;
 315                 break;
 316         case AR5K_RF5112:
 317                 go = &rfgain_opt_5112;
 318                 break;
 319         default:
 320                 return 0;
 321         }
 322
 323         g_step = &go->go_step[ah->ah_gain.g_step_idx];
 324
 325         if (ah->ah_gain.g_current >= ah->ah_gain.g_high) {
 326
 327                 /* Reached maximum */
 328                 if (ah->ah_gain.g_step_idx == 0)
 329                         return -1;
 330
 331                 for (ah->ah_gain.g_target = ah->ah_gain.g_current;
 332                                 ah->ah_gain.g_target >=  ah->ah_gain.g_high &&
 333                                 ah->ah_gain.g_step_idx > 0;
 334                                 g_step = &go->go_step[ah->ah_gain.g_step_idx])
 335                         ah->ah_gain.g_target -= 2 *
 336                             (go->go_step[--(ah->ah_gain.g_step_idx)].gos_gain -
 337                             g_step->gos_gain);
 338
 339                 ret = 1;
 340                 goto done;
 341         }
 342
 343         if (ah->ah_gain.g_current <= ah->ah_gain.g_low) {
 344
 345                 /* Reached minimum */
 346                 if (ah->ah_gain.g_step_idx == (go->go_steps_count - 1))
 347                         return -2;
 348
 349                 for (ah->ah_gain.g_target = ah->ah_gain.g_current;
 350                                 ah->ah_gain.g_target <= ah->ah_gain.g_low &&
 351                                 ah->ah_gain.g_step_idx < go->go_steps_count-1;
 352                                 g_step = &go->go_step[ah->ah_gain.g_step_idx])
 353                         ah->ah_gain.g_target -= 2 *
 354                             (go->go_step[++ah->ah_gain.g_step_idx].gos_gain -
 355                             g_step->gos_gain);
 356
 357                 ret = 2;
 358                 goto done;
 359         }
 360
 361 done:
 362         ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
 363                 "ret %d, gain step %u, current gain %u, target gain %u\n",
 364                 ret, ah->ah_gain.g_step_idx, ah->ah_gain.g_current,
 365                 ah->ah_gain.g_target);
 366
 367         return ret;
 368 }
 369
 370 /* Main callback for thermal rf gain calibration engine
 371  * Check for a new gain reading and schedule an adjustment
 372  * if needed.
 373  *
 374  * TODO: Use sw interrupt to schedule reset if gain_F needs
 375  * adjustment */
 376 enum ath5k_rfgain ath5k_hw_gainf_calibrate(struct ath5k_hw *ah)
 377 {
 378         u32 data, type;
 379         struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
 380
 381         ATH5K_TRACE(ah->ah_sc);
 382
 383         if (ah->ah_rf_banks == NULL ||
 384         ah->ah_gain.g_state == AR5K_RFGAIN_INACTIVE)
 385                 return AR5K_RFGAIN_INACTIVE;
 386
 387         /* No check requested, either engine is inactive
 388          * or an adjustment is already requested */
 389         if (ah->ah_gain.g_state != AR5K_RFGAIN_READ_REQUESTED)
 390                 goto done;
 391
 392         /* Read the PAPD (Peak to Average Power Detector)
 393          * register */
 394         data = ath5k_hw_reg_read(ah, AR5K_PHY_PAPD_PROBE);
 395
 396         /* No probe is scheduled, read gain_F measurement */
 397         if (!(data & AR5K_PHY_PAPD_PROBE_TX_NEXT)) {
 398                 ah->ah_gain.g_current = data >> AR5K_PHY_PAPD_PROBE_GAINF_S;
 399                 type = AR5K_REG_MS(data, AR5K_PHY_PAPD_PROBE_TYPE);
 400
 401                 /* If tx packet is CCK correct the gain_F measurement
 402                  * by cck ofdm gain delta */
 403                 if (type == AR5K_PHY_PAPD_PROBE_TYPE_CCK) {
 404                         if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A)
 405                                 ah->ah_gain.g_current +=
 406                                         ee->ee_cck_ofdm_gain_delta;
 407                         else
 408                                 ah->ah_gain.g_current +=
 409                                         AR5K_GAIN_CCK_PROBE_CORR;
 410                 }
 411
 412                 /* Further correct gain_F measurement for
 413                  * RF5112A radios */
 414                 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) {
 415                         ath5k_hw_rf_gainf_corr(ah);
 416                         ah->ah_gain.g_current =
 417                                 ah->ah_gain.g_current >= ah->ah_gain.g_f_corr ?
 418                                 (ah->ah_gain.g_current-ah->ah_gain.g_f_corr) :
 419                                 0;
 420                 }
 421
 422                 /* Check if measurement is ok and if we need
 423                  * to adjust gain, schedule a gain adjustment,
 424                  * else switch back to the acive state */
 425                 if (ath5k_hw_rf_check_gainf_readback(ah) &&
 426                 AR5K_GAIN_CHECK_ADJUST(&ah->ah_gain) &&
 427                 ath5k_hw_rf_gainf_adjust(ah)) {
 428                         ah->ah_gain.g_state = AR5K_RFGAIN_NEED_CHANGE;
 429                 } else {
 430                         ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
 431                 }
 432         }
 433
 434 done:
 435         return ah->ah_gain.g_state;
 436 }
 437
 438 /* Write initial rf gain table to set the RF sensitivity
 439  * this one works on all RF chips and has nothing to do
 440  * with gain_F calibration */
 441 int ath5k_hw_rfgain_init(struct ath5k_hw *ah, unsigned int freq)
 442 {
 443         const struct ath5k_ini_rfgain *ath5k_rfg;
 444         unsigned int i, size;
 445
 446         switch (ah->ah_radio) {
 447         case AR5K_RF5111:
 448                 ath5k_rfg = rfgain_5111;
 449                 size = ARRAY_SIZE(rfgain_5111);
 450                 break;
 451         case AR5K_RF5112:
 452                 ath5k_rfg = rfgain_5112;
 453                 size = ARRAY_SIZE(rfgain_5112);
 454                 break;
 455         case AR5K_RF2413:
 456                 ath5k_rfg = rfgain_2413;
 457                 size = ARRAY_SIZE(rfgain_2413);
 458                 break;
 459         case AR5K_RF2316:
 460                 ath5k_rfg = rfgain_2316;
 461                 size = ARRAY_SIZE(rfgain_2316);
 462                 break;
 463         case AR5K_RF5413:
 464                 ath5k_rfg = rfgain_5413;
 465                 size = ARRAY_SIZE(rfgain_5413);
 466                 break;
 467         case AR5K_RF2317:
 468         case AR5K_RF2425:
 469                 ath5k_rfg = rfgain_2425;
 470                 size = ARRAY_SIZE(rfgain_2425);
 471                 break;
 472         default:
 473                 return -EINVAL;
 474         }
 475
 476         switch (freq) {
 477         case AR5K_INI_RFGAIN_2GHZ:
 478         case AR5K_INI_RFGAIN_5GHZ:
 479                 break;
 480         default:
 481                 return -EINVAL;
 482         }
 483
 484         for (i = 0; i < size; i++) {
 485                 AR5K_REG_WAIT(i);
 486                 ath5k_hw_reg_write(ah, ath5k_rfg[i].rfg_value[freq],
 487                         (u32)ath5k_rfg[i].rfg_register);
 488         }
 489
 490         return 0;
 491 }
 492
 493
 494
 495 /********************\
 496 * RF Registers setup *
 497 \********************/
 498
 499
 500 /*
 501  * Setup RF registers by writing rf buffer on hw
 502  */
 503 int ath5k_hw_rfregs_init(struct ath5k_hw *ah, struct ieee80211_channel *channel,
 504                 unsigned int mode)
 505 {
 506         const struct ath5k_rf_reg *rf_regs;
 507         const struct ath5k_ini_rfbuffer *ini_rfb;
 508         const struct ath5k_gain_opt *go = NULL;
 509         const struct ath5k_gain_opt_step *g_step;
 510         struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
 511         u8 ee_mode = 0;
 512         u32 *rfb;
 513         int i, obdb = -1, bank = -1;
 514
 515         switch (ah->ah_radio) {
 516         case AR5K_RF5111:
 517                 rf_regs = rf_regs_5111;
 518                 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5111);
 519                 ini_rfb = rfb_5111;
 520                 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5111);
 521                 go = &rfgain_opt_5111;
 522                 break;
 523         case AR5K_RF5112:
 524                 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) {
 525                         rf_regs = rf_regs_5112a;
 526                         ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112a);
 527                         ini_rfb = rfb_5112a;
 528                         ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5112a);
 529                 } else {
 530                         rf_regs = rf_regs_5112;
 531                         ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112);
 532                         ini_rfb = rfb_5112;
 533                         ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5112);
 534                 }
 535                 go = &rfgain_opt_5112;
 536                 break;
 537         case AR5K_RF2413:
 538                 rf_regs = rf_regs_2413;
 539                 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2413);
 540                 ini_rfb = rfb_2413;
 541                 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2413);
 542                 break;
 543         case AR5K_RF2316:
 544                 rf_regs = rf_regs_2316;
 545                 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2316);
 546                 ini_rfb = rfb_2316;
 547                 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2316);
 548                 break;
 549         case AR5K_RF5413:
 550                 rf_regs = rf_regs_5413;
 551                 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5413);
 552                 ini_rfb = rfb_5413;
 553                 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5413);
 554                 break;
 555         case AR5K_RF2317:
 556                 rf_regs = rf_regs_2425;
 557                 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2425);
 558                 ini_rfb = rfb_2317;
 559                 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2317);
 560                 break;
 561         case AR5K_RF2425:
 562                 rf_regs = rf_regs_2425;
 563                 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2425);
 564                 if (ah->ah_mac_srev < AR5K_SREV_AR2417) {
 565                         ini_rfb = rfb_2425;
 566                         ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2425);
 567                 } else {
 568                         ini_rfb = rfb_2417;
 569                         ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2417);
 570                 }
 571                 break;
 572         default:
 573                 return -EINVAL;
 574         }
 575
 576         /* If it's the first time we set rf buffer, allocate
 577          * ah->ah_rf_banks based on ah->ah_rf_banks_size
 578          * we set above */
 579         if (ah->ah_rf_banks == NULL) {
 580                 ah->ah_rf_banks = kmalloc(sizeof(u32) * ah->ah_rf_banks_size,
 581                                                                 GFP_KERNEL);
 582                 if (ah->ah_rf_banks == NULL) {
 583                         ATH5K_ERR(ah->ah_sc, "out of memory\n");
 584                         return -ENOMEM;
 585                 }
 586         }
 587
 588         /* Copy values to modify them */
 589         rfb = ah->ah_rf_banks;
 590
 591         for (i = 0; i < ah->ah_rf_banks_size; i++) {
 592                 if (ini_rfb[i].rfb_bank >= AR5K_MAX_RF_BANKS) {
 593                         ATH5K_ERR(ah->ah_sc, "invalid bank\n");
 594                         return -EINVAL;
 595                 }
 596
 597                 /* Bank changed, write down the offset */
 598                 if (bank != ini_rfb[i].rfb_bank) {
 599                         bank = ini_rfb[i].rfb_bank;
 600                         ah->ah_offset[bank] = i;
 601                 }
 602
 603                 rfb[i] = ini_rfb[i].rfb_mode_data[mode];
 604         }
 605
 606         /* Set Output and Driver bias current (OB/DB) */
 607         if (channel->hw_value & CHANNEL_2GHZ) {
 608
 609                 if (channel->hw_value & CHANNEL_CCK)
 610                         ee_mode = AR5K_EEPROM_MODE_11B;
 611                 else
 612                         ee_mode = AR5K_EEPROM_MODE_11G;
 613
 614                 /* For RF511X/RF211X combination we
 615                  * use b_OB and b_DB parameters stored
 616                  * in eeprom on ee->ee_ob[ee_mode][0]
 617                  *
 618                  * For all other chips we use OB/DB for 2Ghz
 619                  * stored in the b/g modal section just like
 620                  * 802.11a on ee->ee_ob[ee_mode][1] */
 621                 if ((ah->ah_radio == AR5K_RF5111) ||
 622                 (ah->ah_radio == AR5K_RF5112))
 623                         obdb = 0;
 624                 else
 625                         obdb = 1;
 626
 627                 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_ob[ee_mode][obdb],
 628                                                 AR5K_RF_OB_2GHZ, true);
 629
 630                 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_db[ee_mode][obdb],
 631                                                 AR5K_RF_DB_2GHZ, true);
 632
 633         /* RF5111 always needs OB/DB for 5GHz, even if we use 2GHz */
 634         } else if ((channel->hw_value & CHANNEL_5GHZ) ||
 635                         (ah->ah_radio == AR5K_RF5111)) {
 636
 637                 /* For 11a, Turbo and XR we need to choose
 638                  * OB/DB based on frequency range */
 639                 ee_mode = AR5K_EEPROM_MODE_11A;
 640                 obdb =   channel->center_freq >= 5725 ? 3 :
 641                         (channel->center_freq >= 5500 ? 2 :
 642                         (channel->center_freq >= 5260 ? 1 :
 643                          (channel->center_freq > 4000 ? 0 : -1)));
 644
 645                 if (obdb < 0)
 646                         return -EINVAL;
 647
 648                 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_ob[ee_mode][obdb],
 649                                                 AR5K_RF_OB_5GHZ, true);
 650
 651                 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_db[ee_mode][obdb],
 652                                                 AR5K_RF_DB_5GHZ, true);
 653         }
 654
 655         g_step = &go->go_step[ah->ah_gain.g_step_idx];
 656
 657         /* Bank Modifications (chip-specific) */
 658         if (ah->ah_radio == AR5K_RF5111) {
 659
 660                 /* Set gain_F settings according to current step */
 661                 if (channel->hw_value & CHANNEL_OFDM) {
 662
 663                         AR5K_REG_WRITE_BITS(ah, AR5K_PHY_FRAME_CTL,
 664                                         AR5K_PHY_FRAME_CTL_TX_CLIP,
 665                                         g_step->gos_param[0]);
 666
 667                         ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[1],
 668                                                         AR5K_RF_PWD_90, true);
 669
 670                         ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[2],
 671                                                         AR5K_RF_PWD_84, true);
 672
 673                         ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[3],
 674                                                 AR5K_RF_RFGAIN_SEL, true);
 675
 676                         /* We programmed gain_F parameters, switch back
 677                          * to active state */
 678                         ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
 679
 680                 }
 681
 682                 /* Bank 6/7 setup */
 683
 684                 ath5k_hw_rfb_op(ah, rf_regs, !ee->ee_xpd[ee_mode],
 685                                                 AR5K_RF_PWD_XPD, true);
 686
 687                 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_x_gain[ee_mode],
 688                                                 AR5K_RF_XPD_GAIN, true);
 689
 690                 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_i_gain[ee_mode],
 691                                                 AR5K_RF_GAIN_I, true);
 692
 693                 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_xpd[ee_mode],
 694                                                 AR5K_RF_PLO_SEL, true);
 695
 696                 /* TODO: Half/quarter channel support */
 697         }
 698
 699         if (ah->ah_radio == AR5K_RF5112) {
 700
 701                 /* Set gain_F settings according to current step */
 702                 if (channel->hw_value & CHANNEL_OFDM) {
 703
 704                         ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[0],
 705                                                 AR5K_RF_MIXGAIN_OVR, true);
 706
 707                         ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[1],
 708                                                 AR5K_RF_PWD_138, true);
 709
 710                         ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[2],
 711                                                 AR5K_RF_PWD_137, true);
 712
 713                         ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[3],
 714                                                 AR5K_RF_PWD_136, true);
 715
 716                         ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[4],
 717                                                 AR5K_RF_PWD_132, true);
 718
 719                         ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[5],
 720                                                 AR5K_RF_PWD_131, true);
 721
 722                         ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[6],
 723                                                 AR5K_RF_PWD_130, true);
 724
 725                         /* We programmed gain_F parameters, switch back
 726                          * to active state */
 727                         ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
 728                 }
 729
 730                 /* Bank 6/7 setup */
 731
 732                 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_xpd[ee_mode],
 733                                                 AR5K_RF_XPD_SEL, true);
 734
 735                 if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_5112A) {
 736                         /* Rev. 1 supports only one xpd */
 737                         ath5k_hw_rfb_op(ah, rf_regs,
 738                                                 ee->ee_x_gain[ee_mode],
 739                                                 AR5K_RF_XPD_GAIN, true);
 740
 741                 } else {
 742                         u8 *pdg_curve_to_idx = ee->ee_pdc_to_idx[ee_mode];
 743                         if (ee->ee_pd_gains[ee_mode] > 1) {
 744                                 ath5k_hw_rfb_op(ah, rf_regs,
 745                                                 pdg_curve_to_idx[0],
 746                                                 AR5K_RF_PD_GAIN_LO, true);
 747                                 ath5k_hw_rfb_op(ah, rf_regs,
 748                                                 pdg_curve_to_idx[1],
 749                                                 AR5K_RF_PD_GAIN_HI, true);
 750                         } else {
 751                                 ath5k_hw_rfb_op(ah, rf_regs,
 752                                                 pdg_curve_to_idx[0],
 753                                                 AR5K_RF_PD_GAIN_LO, true);
 754                                 ath5k_hw_rfb_op(ah, rf_regs,
 755                                                 pdg_curve_to_idx[0],
 756                                                 AR5K_RF_PD_GAIN_HI, true);
 757                         }
 758
 759                         /* Lower synth voltage on Rev 2 */
 760                         ath5k_hw_rfb_op(ah, rf_regs, 2,
 761                                         AR5K_RF_HIGH_VC_CP, true);
 762
 763                         ath5k_hw_rfb_op(ah, rf_regs, 2,
 764                                         AR5K_RF_MID_VC_CP, true);
 765
 766                         ath5k_hw_rfb_op(ah, rf_regs, 2,
 767                                         AR5K_RF_LOW_VC_CP, true);
 768
 769                         ath5k_hw_rfb_op(ah, rf_regs, 2,
 770                                         AR5K_RF_PUSH_UP, true);
 771
 772                         /* Decrease power consumption on 5213+ BaseBand */
 773                         if (ah->ah_phy_revision >= AR5K_SREV_PHY_5212A) {
 774                                 ath5k_hw_rfb_op(ah, rf_regs, 1,
 775                                                 AR5K_RF_PAD2GND, true);
 776
 777                                 ath5k_hw_rfb_op(ah, rf_regs, 1,
 778                                                 AR5K_RF_XB2_LVL, true);
 779
 780                                 ath5k_hw_rfb_op(ah, rf_regs, 1,
 781                                                 AR5K_RF_XB5_LVL, true);
 782
 783                                 ath5k_hw_rfb_op(ah, rf_regs, 1,
 784                                                 AR5K_RF_PWD_167, true);
 785
 786                                 ath5k_hw_rfb_op(ah, rf_regs, 1,
 787                                                 AR5K_RF_PWD_166, true);
 788                         }
 789                 }
 790
 791                 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_i_gain[ee_mode],
 792                                                 AR5K_RF_GAIN_I, true);
 793
 794                 /* TODO: Half/quarter channel support */
 795
 796         }
 797
 798         if (ah->ah_radio == AR5K_RF5413 &&
 799         channel->hw_value & CHANNEL_2GHZ) {
 800
 801                 ath5k_hw_rfb_op(ah, rf_regs, 1, AR5K_RF_DERBY_CHAN_SEL_MODE,
 802                                                                         true);
 803
 804                 /* Set optimum value for early revisions (on pci-e chips) */
 805                 if (ah->ah_mac_srev >= AR5K_SREV_AR5424 &&
 806                 ah->ah_mac_srev < AR5K_SREV_AR5413)
 807                         ath5k_hw_rfb_op(ah, rf_regs, ath5k_hw_bitswap(6, 3),
 808                                                 AR5K_RF_PWD_ICLOBUF_2G, true);
 809
 810         }
 811
 812         /* Write RF banks on hw */
 813         for (i = 0; i < ah->ah_rf_banks_size; i++) {
 814                 AR5K_REG_WAIT(i);
 815                 ath5k_hw_reg_write(ah, rfb[i], ini_rfb[i].rfb_ctrl_register);
 816         }
 817
 818         return 0;
 819 }
 820
 821
 822 /**************************\
 823   PHY/RF channel functions
 824 \**************************/
 825
 826 /*
 827  * Check if a channel is supported
 828  */
 829 bool ath5k_channel_ok(struct ath5k_hw *ah, u16 freq, unsigned int flags)
 830 {
 831         /* Check if the channel is in our supported range */
 832         if (flags & CHANNEL_2GHZ) {
 833                 if ((freq >= ah->ah_capabilities.cap_range.range_2ghz_min) &&
 834                     (freq <= ah->ah_capabilities.cap_range.range_2ghz_max))
 835                         return true;
 836         } else if (flags & CHANNEL_5GHZ)
 837                 if ((freq >= ah->ah_capabilities.cap_range.range_5ghz_min) &&
 838                     (freq <= ah->ah_capabilities.cap_range.range_5ghz_max))
 839                         return true;
 840
 841         return false;
 842 }
 843
 844 /*
 845  * Convertion needed for RF5110
 846  */
 847 static u32 ath5k_hw_rf5110_chan2athchan(struct ieee80211_channel *channel)
 848 {
 849         u32 athchan;
 850
 851         /*
 852          * Convert IEEE channel/MHz to an internal channel value used
 853          * by the AR5210 chipset. This has not been verified with
 854          * newer chipsets like the AR5212A who have a completely
 855          * different RF/PHY part.
 856          */
 857         athchan = (ath5k_hw_bitswap(
 858                         (ieee80211_frequency_to_channel(
 859                                 channel->center_freq) - 24) / 2, 5)
 860                                 << 1) | (1 << 6) | 0x1;
 861         return athchan;
 862 }
 863
 864 /*
 865  * Set channel on RF5110
 866  */
 867 static int ath5k_hw_rf5110_channel(struct ath5k_hw *ah,
 868                 struct ieee80211_channel *channel)
 869 {
 870         u32 data;
 871
 872         /*
 873          * Set the channel and wait
 874          */
 875         data = ath5k_hw_rf5110_chan2athchan(channel);
 876         ath5k_hw_reg_write(ah, data, AR5K_RF_BUFFER);
 877         ath5k_hw_reg_write(ah, 0, AR5K_RF_BUFFER_CONTROL_0);
 878         mdelay(1);
 879
 880         return 0;
 881 }
 882
 883 /*
 884  * Convertion needed for 5111
 885  */
 886 static int ath5k_hw_rf5111_chan2athchan(unsigned int ieee,
 887                 struct ath5k_athchan_2ghz *athchan)
 888 {
 889         int channel;
 890
 891         /* Cast this value to catch negative channel numbers (>= -19) */
 892         channel = (int)ieee;
 893
 894         /*
 895          * Map 2GHz IEEE channel to 5GHz Atheros channel
 896          */
 897         if (channel <= 13) {
 898                 athchan->a2_athchan = 115 + channel;
 899                 athchan->a2_flags = 0x46;
 900         } else if (channel == 14) {
 901                 athchan->a2_athchan = 124;
 902                 athchan->a2_flags = 0x44;
 903         } else if (channel >= 15 && channel <= 26) {
 904                 athchan->a2_athchan = ((channel - 14) * 4) + 132;
 905                 athchan->a2_flags = 0x46;
 906         } else
 907                 return -EINVAL;
 908
 909         return 0;
 910 }
 911
 912 /*
 913  * Set channel on 5111
 914  */
 915 static int ath5k_hw_rf5111_channel(struct ath5k_hw *ah,
 916                 struct ieee80211_channel *channel)
 917 {
 918         struct ath5k_athchan_2ghz ath5k_channel_2ghz;
 919         unsigned int ath5k_channel =
 920                 ieee80211_frequency_to_channel(channel->center_freq);
 921         u32 data0, data1, clock;
 922         int ret;
 923
 924         /*
 925          * Set the channel on the RF5111 radio
 926          */
 927         data0 = data1 = 0;
 928
 929         if (channel->hw_value & CHANNEL_2GHZ) {
 930                 /* Map 2GHz channel to 5GHz Atheros channel ID */
 931                 ret = ath5k_hw_rf5111_chan2athchan(
 932                         ieee80211_frequency_to_channel(channel->center_freq),
 933                         &ath5k_channel_2ghz);
 934                 if (ret)
 935                         return ret;
 936
 937                 ath5k_channel = ath5k_channel_2ghz.a2_athchan;
 938                 data0 = ((ath5k_hw_bitswap(ath5k_channel_2ghz.a2_flags, 8) & 0xff)
 939                     << 5) | (1 << 4);
 940         }
 941
 942         if (ath5k_channel < 145 || !(ath5k_channel & 1)) {
 943                 clock = 1;
 944                 data1 = ((ath5k_hw_bitswap(ath5k_channel - 24, 8) & 0xff) << 2) |
 945                         (clock << 1) | (1 << 10) | 1;
 946         } else {
 947                 clock = 0;
 948                 data1 = ((ath5k_hw_bitswap((ath5k_channel - 24) / 2, 8) & 0xff)
 949                         << 2) | (clock << 1) | (1 << 10) | 1;
 950         }
 951
 952         ath5k_hw_reg_write(ah, (data1 & 0xff) | ((data0 & 0xff) << 8),
 953                         AR5K_RF_BUFFER);
 954         ath5k_hw_reg_write(ah, ((data1 >> 8) & 0xff) | (data0 & 0xff00),
 955                         AR5K_RF_BUFFER_CONTROL_3);
 956
 957         return 0;
 958 }
 959
 960 /*
 961  * Set channel on 5112 and newer
 962  */
 963 static int ath5k_hw_rf5112_channel(struct ath5k_hw *ah,
 964                 struct ieee80211_channel *channel)
 965 {
 966         u32 data, data0, data1, data2;
 967         u16 c;
 968
 969         data = data0 = data1 = data2 = 0;
 970         c = channel->center_freq;
 971
 972         if (c < 4800) {
 973                 if (!((c - 2224) % 5)) {
 974                         data0 = ((2 * (c - 704)) - 3040) / 10;
 975                         data1 = 1;
 976                 } else if (!((c - 2192) % 5)) {
 977                         data0 = ((2 * (c - 672)) - 3040) / 10;
 978                         data1 = 0;
 979                 } else
 980                         return -EINVAL;
 981
 982                 data0 = ath5k_hw_bitswap((data0 << 2) & 0xff, 8);
 983         } else if ((c - (c % 5)) != 2 || c > 5435) {
 984                 if (!(c % 20) && c >= 5120) {
 985                         data0 = ath5k_hw_bitswap(((c - 4800) / 20 << 2), 8);
 986                         data2 = ath5k_hw_bitswap(3, 2);
 987                 } else if (!(c % 10)) {
 988                         data0 = ath5k_hw_bitswap(((c - 4800) / 10 << 1), 8);
 989                         data2 = ath5k_hw_bitswap(2, 2);
 990                 } else if (!(c % 5)) {
 991                         data0 = ath5k_hw_bitswap((c - 4800) / 5, 8);
 992                         data2 = ath5k_hw_bitswap(1, 2);
 993                 } else
 994                         return -EINVAL;
 995         } else {
 996                 data0 = ath5k_hw_bitswap((10 * (c - 2) - 4800) / 25 + 1, 8);
 997                 data2 = ath5k_hw_bitswap(0, 2);
 998         }
 999
1000         data = (data0 << 4) | (data1 << 1) | (data2 << 2) | 0x1001;
1001
1002         ath5k_hw_reg_write(ah, data & 0xff, AR5K_RF_BUFFER);
1003         ath5k_hw_reg_write(ah, (data >> 8) & 0x7f, AR5K_RF_BUFFER_CONTROL_5);
1004
1005         return 0;
1006 }
1007
1008 /*
1009  * Set the channel on the RF2425
1010  */
1011 static int ath5k_hw_rf2425_channel(struct ath5k_hw *ah,
1012                 struct ieee80211_channel *channel)
1013 {
1014         u32 data, data0, data2;
1015         u16 c;
1016
1017         data = data0 = data2 = 0;
1018         c = channel->center_freq;
1019
1020         if (c < 4800) {
1021                 data0 = ath5k_hw_bitswap((c - 2272), 8);
1022                 data2 = 0;
1023         /* ? 5GHz ? */
1024         } else if ((c - (c % 5)) != 2 || c > 5435) {
1025                 if (!(c % 20) && c < 5120)
1026                         data0 = ath5k_hw_bitswap(((c - 4800) / 20 << 2), 8);
1027                 else if (!(c % 10))
1028                         data0 = ath5k_hw_bitswap(((c - 4800) / 10 << 1), 8);
1029                 else if (!(c % 5))
1030                         data0 = ath5k_hw_bitswap((c - 4800) / 5, 8);
1031                 else
1032                         return -EINVAL;
1033                 data2 = ath5k_hw_bitswap(1, 2);
1034         } else {
1035                 data0 = ath5k_hw_bitswap((10 * (c - 2) - 4800) / 25 + 1, 8);
1036                 data2 = ath5k_hw_bitswap(0, 2);
1037         }
1038
1039         data = (data0 << 4) | data2 << 2 | 0x1001;
1040
1041         ath5k_hw_reg_write(ah, data & 0xff, AR5K_RF_BUFFER);
1042         ath5k_hw_reg_write(ah, (data >> 8) & 0x7f, AR5K_RF_BUFFER_CONTROL_5);
1043
1044         return 0;
1045 }
1046
1047 /*
1048  * Set a channel on the radio chip
1049  */
1050 int ath5k_hw_channel(struct ath5k_hw *ah, struct ieee80211_channel *channel)
1051 {
1052         int ret;
1053         /*
1054          * Check bounds supported by the PHY (we don't care about regultory
1055          * restrictions at this point). Note: hw_value already has the band
1056          * (CHANNEL_2GHZ, or CHANNEL_5GHZ) so we inform ath5k_channel_ok()
1057          * of the band by that */
1058         if (!ath5k_channel_ok(ah, channel->center_freq, channel->hw_value)) {
1059                 ATH5K_ERR(ah->ah_sc,
1060                         "channel frequency (%u MHz) out of supported "
1061                         "band range\n",
1062                         channel->center_freq);
1063                         return -EINVAL;
1064         }
1065
1066         /*
1067          * Set the channel and wait
1068          */
1069         switch (ah->ah_radio) {
1070         case AR5K_RF5110:
1071                 ret = ath5k_hw_rf5110_channel(ah, channel);
1072                 break;
1073         case AR5K_RF5111:
1074                 ret = ath5k_hw_rf5111_channel(ah, channel);
1075                 break;
1076         case AR5K_RF2425:
1077                 ret = ath5k_hw_rf2425_channel(ah, channel);
1078                 break;
1079         default:
1080                 ret = ath5k_hw_rf5112_channel(ah, channel);
1081                 break;
1082         }
1083
1084         if (ret)
1085                 return ret;
1086
1087         /* Set JAPAN setting for channel 14 */
1088         if (channel->center_freq == 2484) {
1089                 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_CCKTXCTL,
1090                                 AR5K_PHY_CCKTXCTL_JAPAN);
1091         } else {
1092                 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_CCKTXCTL,
1093                                 AR5K_PHY_CCKTXCTL_WORLD);
1094         }
1095
1096         ah->ah_current_channel = channel;
1097         ah->ah_turbo = channel->hw_value == CHANNEL_T ? true : false;
1098
1099         return 0;
1100 }
1101
1102 /*****************\
1103   PHY calibration
1104 \*****************/
1105
1106 void
1107 ath5k_hw_calibration_poll(struct ath5k_hw *ah)
1108 {
1109         /* Calibration interval in jiffies */
1110         unsigned long cal_intval;
1111
1112         cal_intval = msecs_to_jiffies(ah->ah_cal_intval * 1000);
1113
1114         /* Initialize timestamp if needed */
1115         if (!ah->ah_cal_tstamp)
1116                 ah->ah_cal_tstamp = jiffies;
1117
1118         /* For now we always do full calibration
1119          * Mark software interrupt mask and fire software
1120          * interrupt (bit gets auto-cleared) */
1121         if (time_is_before_eq_jiffies(ah->ah_cal_tstamp + cal_intval)) {
1122                 ah->ah_cal_tstamp = jiffies;
1123                 ah->ah_swi_mask = AR5K_SWI_FULL_CALIBRATION;
1124                 AR5K_REG_ENABLE_BITS(ah, AR5K_CR, AR5K_CR_SWI);
1125         }
1126 }
1127
1128 static int sign_extend(int val, const int nbits)
1129 {
1130         int order = BIT(nbits-1);
1131         return (val ^ order) - order;
1132 }
1133
1134 static s32 ath5k_hw_read_measured_noise_floor(struct ath5k_hw *ah)
1135 {
1136         s32 val;
1137
1138         val = ath5k_hw_reg_read(ah, AR5K_PHY_NF);
1139         return sign_extend(AR5K_REG_MS(val, AR5K_PHY_NF_MINCCA_PWR), 9);
1140 }
1141
1142 void ath5k_hw_init_nfcal_hist(struct ath5k_hw *ah)
1143 {
1144         int i;
1145
1146         ah->ah_nfcal_hist.index = 0;
1147         for (i = 0; i < ATH5K_NF_CAL_HIST_MAX; i++)
1148                 ah->ah_nfcal_hist.nfval[i] = AR5K_TUNE_CCA_MAX_GOOD_VALUE;
1149 }
1150
1151 static void ath5k_hw_update_nfcal_hist(struct ath5k_hw *ah, s16 noise_floor)
1152 {
1153         struct ath5k_nfcal_hist *hist = &ah->ah_nfcal_hist;
1154         hist->index = (hist->index + 1) & (ATH5K_NF_CAL_HIST_MAX-1);
1155         hist->nfval[hist->index] = noise_floor;
1156 }
1157
1158 static s16 ath5k_hw_get_median_noise_floor(struct ath5k_hw *ah)
1159 {
1160         s16 sort[ATH5K_NF_CAL_HIST_MAX];
1161         s16 tmp;
1162         int i, j;
1163
1164         memcpy(sort, ah->ah_nfcal_hist.nfval, sizeof(sort));
1165         for (i = 0; i < ATH5K_NF_CAL_HIST_MAX - 1; i++) {
1166                 for (j = 1; j < ATH5K_NF_CAL_HIST_MAX - i; j++) {
1167                         if (sort[j] > sort[j-1]) {
1168                                 tmp = sort[j];
1169                                 sort[j] = sort[j-1];
1170                                 sort[j-1] = tmp;
1171                         }
1172                 }
1173         }
1174         for (i = 0; i < ATH5K_NF_CAL_HIST_MAX; i++) {
1175                 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
1176                         "cal %d:%d\n", i, sort[i]);
1177         }
1178         return sort[(ATH5K_NF_CAL_HIST_MAX-1) / 2];
1179 }
1180
1181 /*
1182  * When we tell the hardware to perform a noise floor calibration
1183  * by setting the AR5K_PHY_AGCCTL_NF bit, it will periodically
1184  * sample-and-hold the minimum noise level seen at the antennas.
1185  * This value is then stored in a ring buffer of recently measured
1186  * noise floor values so we have a moving window of the last few
1187  * samples.
1188  *
1189  * The median of the values in the history is then loaded into the
1190  * hardware for its own use for RSSI and CCA measurements.
1191  */
1192 static void ath5k_hw_update_noise_floor(struct ath5k_hw *ah)
1193 {
1194         struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1195         u32 val;
1196         s16 nf, threshold;
1197         u8 ee_mode;
1198
1199         /* keep last value if calibration hasn't completed */
1200         if (ath5k_hw_reg_read(ah, AR5K_PHY_AGCCTL) & AR5K_PHY_AGCCTL_NF) {
1201                 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
1202                         "NF did not complete in calibration window\n");
1203
1204                 return;
1205         }
1206
1207         switch (ah->ah_current_channel->hw_value & CHANNEL_MODES) {
1208         case CHANNEL_A:
1209         case CHANNEL_T:
1210         case CHANNEL_XR:
1211                 ee_mode = AR5K_EEPROM_MODE_11A;
1212                 break;
1213         case CHANNEL_G:
1214         case CHANNEL_TG:
1215                 ee_mode = AR5K_EEPROM_MODE_11G;
1216                 break;
1217         default:
1218         case CHANNEL_B:
1219                 ee_mode = AR5K_EEPROM_MODE_11B;
1220                 break;
1221         }
1222
1223
1224         /* completed NF calibration, test threshold */
1225         nf = ath5k_hw_read_measured_noise_floor(ah);
1226         threshold = ee->ee_noise_floor_thr[ee_mode];
1227
1228         if (nf > threshold) {
1229                 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
1230                         "noise floor failure detected; "
1231                         "read %d, threshold %d\n",
1232                         nf, threshold);
1233
1234                 nf = AR5K_TUNE_CCA_MAX_GOOD_VALUE;
1235         }
1236
1237         ath5k_hw_update_nfcal_hist(ah, nf);
1238         nf = ath5k_hw_get_median_noise_floor(ah);
1239
1240         /* load noise floor (in .5 dBm) so the hardware will use it */
1241         val = ath5k_hw_reg_read(ah, AR5K_PHY_NF) & ~AR5K_PHY_NF_M;
1242         val |= (nf * 2) & AR5K_PHY_NF_M;
1243         ath5k_hw_reg_write(ah, val, AR5K_PHY_NF);
1244
1245         AR5K_REG_MASKED_BITS(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_NF,
1246                 ~(AR5K_PHY_AGCCTL_NF_EN | AR5K_PHY_AGCCTL_NF_NOUPDATE));
1247
1248         ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_NF,
1249                 0, false);
1250
1251         /*
1252          * Load a high max CCA Power value (-50 dBm in .5 dBm units)
1253          * so that we're not capped by the median we just loaded.
1254          * This will be used as the initial value for the next noise
1255          * floor calibration.
1256          */
1257         val = (val & ~AR5K_PHY_NF_M) | ((-50 * 2) & AR5K_PHY_NF_M);
1258         ath5k_hw_reg_write(ah, val, AR5K_PHY_NF);
1259         AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
1260                 AR5K_PHY_AGCCTL_NF_EN |
1261                 AR5K_PHY_AGCCTL_NF_NOUPDATE |
1262                 AR5K_PHY_AGCCTL_NF);
1263
1264         ah->ah_noise_floor = nf;
1265
1266         ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
1267                 "noise floor calibrated: %d\n", nf);
1268 }
1269
1270 /*
1271  * Perform a PHY calibration on RF5110
1272  * -Fix BPSK/QAM Constellation (I/Q correction)
1273  * -Calculate Noise Floor
1274  */
1275 static int ath5k_hw_rf5110_calibrate(struct ath5k_hw *ah,
1276                 struct ieee80211_channel *channel)
1277 {
1278         u32 phy_sig, phy_agc, phy_sat, beacon;
1279         int ret;
1280
1281         /*
1282          * Disable beacons and RX/TX queues, wait
1283          */
1284         AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW_5210,
1285                 AR5K_DIAG_SW_DIS_TX | AR5K_DIAG_SW_DIS_RX_5210);
1286         beacon = ath5k_hw_reg_read(ah, AR5K_BEACON_5210);
1287         ath5k_hw_reg_write(ah, beacon & ~AR5K_BEACON_ENABLE, AR5K_BEACON_5210);
1288
1289         mdelay(2);
1290
1291         /*
1292          * Set the channel (with AGC turned off)
1293          */
1294         AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
1295         udelay(10);
1296         ret = ath5k_hw_channel(ah, channel);
1297
1298         /*
1299          * Activate PHY and wait
1300          */
1301         ath5k_hw_reg_write(ah, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT);
1302         mdelay(1);
1303
1304         AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
1305
1306         if (ret)
1307                 return ret;
1308
1309         /*
1310          * Calibrate the radio chip
1311          */
1312
1313         /* Remember normal state */
1314         phy_sig = ath5k_hw_reg_read(ah, AR5K_PHY_SIG);
1315         phy_agc = ath5k_hw_reg_read(ah, AR5K_PHY_AGCCOARSE);
1316         phy_sat = ath5k_hw_reg_read(ah, AR5K_PHY_ADCSAT);
1317
1318         /* Update radio registers */
1319         ath5k_hw_reg_write(ah, (phy_sig & ~(AR5K_PHY_SIG_FIRPWR)) |
1320                 AR5K_REG_SM(-1, AR5K_PHY_SIG_FIRPWR), AR5K_PHY_SIG);
1321
1322         ath5k_hw_reg_write(ah, (phy_agc & ~(AR5K_PHY_AGCCOARSE_HI |
1323                         AR5K_PHY_AGCCOARSE_LO)) |
1324                 AR5K_REG_SM(-1, AR5K_PHY_AGCCOARSE_HI) |
1325                 AR5K_REG_SM(-127, AR5K_PHY_AGCCOARSE_LO), AR5K_PHY_AGCCOARSE);
1326
1327         ath5k_hw_reg_write(ah, (phy_sat & ~(AR5K_PHY_ADCSAT_ICNT |
1328                         AR5K_PHY_ADCSAT_THR)) |
1329                 AR5K_REG_SM(2, AR5K_PHY_ADCSAT_ICNT) |
1330                 AR5K_REG_SM(12, AR5K_PHY_ADCSAT_THR), AR5K_PHY_ADCSAT);
1331
1332         udelay(20);
1333
1334         AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
1335         udelay(10);
1336         ath5k_hw_reg_write(ah, AR5K_PHY_RFSTG_DISABLE, AR5K_PHY_RFSTG);
1337         AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
1338
1339         mdelay(1);
1340
1341         /*
1342          * Enable calibration and wait until completion
1343          */
1344         AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_CAL);
1345
1346         ret = ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL,
1347                         AR5K_PHY_AGCCTL_CAL, 0, false);
1348
1349         /* Reset to normal state */
1350         ath5k_hw_reg_write(ah, phy_sig, AR5K_PHY_SIG);
1351         ath5k_hw_reg_write(ah, phy_agc, AR5K_PHY_AGCCOARSE);
1352         ath5k_hw_reg_write(ah, phy_sat, AR5K_PHY_ADCSAT);
1353
1354         if (ret) {
1355                 ATH5K_ERR(ah->ah_sc, "calibration timeout (%uMHz)\n",
1356                                 channel->center_freq);
1357                 return ret;
1358         }
1359
1360         ath5k_hw_update_noise_floor(ah);
1361
1362         /*
1363          * Re-enable RX/TX and beacons
1364          */
1365         AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW_5210,
1366                 AR5K_DIAG_SW_DIS_TX | AR5K_DIAG_SW_DIS_RX_5210);
1367         ath5k_hw_reg_write(ah, beacon, AR5K_BEACON_5210);
1368
1369         return 0;
1370 }
1371
1372 /*
1373  * Perform a PHY calibration on RF5111/5112 and newer chips
1374  */
1375 static int ath5k_hw_rf511x_calibrate(struct ath5k_hw *ah,
1376                 struct ieee80211_channel *channel)
1377 {
1378         u32 i_pwr, q_pwr;
1379         s32 iq_corr, i_coff, i_coffd, q_coff, q_coffd;
1380         int i;
1381         ATH5K_TRACE(ah->ah_sc);
1382
1383         if (!ah->ah_calibration ||
1384                 ath5k_hw_reg_read(ah, AR5K_PHY_IQ) & AR5K_PHY_IQ_RUN)
1385                 goto done;
1386
1387         /* Calibration has finished, get the results and re-run */
1388
1389         /* work around empty results which can apparently happen on 5212 */
1390         for (i = 0; i <= 10; i++) {
1391                 iq_corr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_CORR);
1392                 i_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_I);
1393                 q_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_Q);
1394                 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
1395                         "iq_corr:%x i_pwr:%x q_pwr:%x", iq_corr, i_pwr, q_pwr);
1396                 if (i_pwr && q_pwr)
1397                         break;
1398         }
1399
1400         i_coffd = ((i_pwr >> 1) + (q_pwr >> 1)) >> 7;
1401
1402         if (ah->ah_version == AR5K_AR5211)
1403                 q_coffd = q_pwr >> 6;
1404         else
1405                 q_coffd = q_pwr >> 7;
1406
1407         /* protect against divide by 0 and loss of sign bits */
1408         if (i_coffd == 0 || q_coffd < 2)
1409                 goto done;
1410
1411         i_coff = (-iq_corr) / i_coffd;
1412         i_coff = clamp(i_coff, -32, 31); /* signed 6 bit */
1413
1414         q_coff = (i_pwr / q_coffd) - 128;
1415         q_coff = clamp(q_coff, -16, 15); /* signed 5 bit */
1416
1417         ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
1418                         "new I:%d Q:%d (i_coffd:%x q_coffd:%x)",
1419                         i_coff, q_coff, i_coffd, q_coffd);
1420
1421         /* Commit new I/Q values (set enable bit last to match HAL sources) */
1422         AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_Q_I_COFF, i_coff);
1423         AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_Q_Q_COFF, q_coff);
1424         AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_ENABLE);
1425
1426         /* Re-enable calibration -if we don't we'll commit
1427          * the same values again and again */
1428         AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ,
1429                         AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15);
1430         AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_RUN);
1431
1432 done:
1433
1434         /* TODO: Separate noise floor calibration from I/Q calibration
1435          * since noise floor calibration interrupts rx path while I/Q
1436          * calibration doesn't. We don't need to run noise floor calibration
1437          * as often as I/Q calibration.*/
1438         ath5k_hw_update_noise_floor(ah);
1439
1440         /* Initiate a gain_F calibration */
1441         ath5k_hw_request_rfgain_probe(ah);
1442
1443         return 0;
1444 }
1445
1446 /*
1447  * Perform a PHY calibration
1448  */
1449 int ath5k_hw_phy_calibrate(struct ath5k_hw *ah,
1450                 struct ieee80211_channel *channel)
1451 {
1452         int ret;
1453
1454         if (ah->ah_radio == AR5K_RF5110)
1455                 ret = ath5k_hw_rf5110_calibrate(ah, channel);
1456         else
1457                 ret = ath5k_hw_rf511x_calibrate(ah, channel);
1458
1459         return ret;
1460 }
1461
1462 /***************************\
1463 * Spur mitigation functions *
1464 \***************************/
1465
1466 bool ath5k_hw_chan_has_spur_noise(struct ath5k_hw *ah,
1467                                 struct ieee80211_channel *channel)
1468 {
1469         u8 refclk_freq;
1470
1471         if ((ah->ah_radio == AR5K_RF5112) ||
1472         (ah->ah_radio == AR5K_RF5413) ||
1473         (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4)))
1474                 refclk_freq = 40;
1475         else
1476                 refclk_freq = 32;
1477
1478         if ((channel->center_freq % refclk_freq != 0) &&
1479         ((channel->center_freq % refclk_freq < 10) ||
1480         (channel->center_freq % refclk_freq > 22)))
1481                 return true;
1482         else
1483                 return false;
1484 }
1485
1486 void
1487 ath5k_hw_set_spur_mitigation_filter(struct ath5k_hw *ah,
1488                                 struct ieee80211_channel *channel)
1489 {
1490         struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1491         u32 mag_mask[4] = {0, 0, 0, 0};
1492         u32 pilot_mask[2] = {0, 0};
1493         /* Note: fbin values are scaled up by 2 */
1494         u16 spur_chan_fbin, chan_fbin, symbol_width, spur_detection_window;
1495         s32 spur_delta_phase, spur_freq_sigma_delta;
1496         s32 spur_offset, num_symbols_x16;
1497         u8 num_symbol_offsets, i, freq_band;
1498
1499         /* Convert current frequency to fbin value (the same way channels
1500          * are stored on EEPROM, check out ath5k_eeprom_bin2freq) and scale
1501          * up by 2 so we can compare it later */
1502         if (channel->hw_value & CHANNEL_2GHZ) {
1503                 chan_fbin = (channel->center_freq - 2300) * 10;
1504                 freq_band = AR5K_EEPROM_BAND_2GHZ;
1505         } else {
1506                 chan_fbin = (channel->center_freq - 4900) * 10;
1507                 freq_band = AR5K_EEPROM_BAND_5GHZ;
1508         }
1509
1510         /* Check if any spur_chan_fbin from EEPROM is
1511          * within our current channel's spur detection range */
1512         spur_chan_fbin = AR5K_EEPROM_NO_SPUR;
1513         spur_detection_window = AR5K_SPUR_CHAN_WIDTH;
1514         /* XXX: Half/Quarter channels ?*/
1515         if (channel->hw_value & CHANNEL_TURBO)
1516                 spur_detection_window *= 2;
1517
1518         for (i = 0; i < AR5K_EEPROM_N_SPUR_CHANS; i++) {
1519                 spur_chan_fbin = ee->ee_spur_chans[i][freq_band];
1520
1521                 /* Note: mask cleans AR5K_EEPROM_NO_SPUR flag
1522                  * so it's zero if we got nothing from EEPROM */
1523                 if (spur_chan_fbin == AR5K_EEPROM_NO_SPUR) {
1524                         spur_chan_fbin &= AR5K_EEPROM_SPUR_CHAN_MASK;
1525                         break;
1526                 }
1527
1528                 if ((chan_fbin - spur_detection_window <=
1529                 (spur_chan_fbin & AR5K_EEPROM_SPUR_CHAN_MASK)) &&
1530                 (chan_fbin + spur_detection_window >=
1531                 (spur_chan_fbin & AR5K_EEPROM_SPUR_CHAN_MASK))) {
1532                         spur_chan_fbin &= AR5K_EEPROM_SPUR_CHAN_MASK;
1533                         break;
1534                 }
1535         }
1536
1537         /* We need to enable spur filter for this channel */
1538         if (spur_chan_fbin) {
1539                 spur_offset = spur_chan_fbin - chan_fbin;
1540                 /*
1541                  * Calculate deltas:
1542                  * spur_freq_sigma_delta -> spur_offset / sample_freq << 21
1543                  * spur_delta_phase -> spur_offset / chip_freq << 11
1544                  * Note: Both values have 100KHz resolution
1545                  */
1546                 /* XXX: Half/Quarter rate channels ? */
1547                 switch (channel->hw_value) {
1548                 case CHANNEL_A:
1549                         /* Both sample_freq and chip_freq are 40MHz */
1550                         spur_delta_phase = (spur_offset << 17) / 25;
1551                         spur_freq_sigma_delta = (spur_delta_phase >> 10);
1552                         symbol_width = AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz;
1553                         break;
1554                 case CHANNEL_G:
1555                         /* sample_freq -> 40MHz chip_freq -> 44MHz
1556                          * (for b compatibility) */
1557                         spur_freq_sigma_delta = (spur_offset << 8) / 55;
1558                         spur_delta_phase = (spur_offset << 17) / 25;
1559                         symbol_width = AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz;
1560                         break;
1561                 case CHANNEL_T:
1562                 case CHANNEL_TG:
1563                         /* Both sample_freq and chip_freq are 80MHz */
1564                         spur_delta_phase = (spur_offset << 16) / 25;
1565                         spur_freq_sigma_delta = (spur_delta_phase >> 10);
1566                         symbol_width = AR5K_SPUR_SYMBOL_WIDTH_TURBO_100Hz;
1567                         break;
1568                 default:
1569                         return;
1570                 }
1571
1572                 /* Calculate pilot and magnitude masks */
1573
1574                 /* Scale up spur_offset by 1000 to switch to 100HZ resolution
1575                  * and divide by symbol_width to find how many symbols we have
1576                  * Note: number of symbols is scaled up by 16 */
1577                 num_symbols_x16 = ((spur_offset * 1000) << 4) / symbol_width;
1578
1579                 /* Spur is on a symbol if num_symbols_x16 % 16 is zero */
1580                 if (!(num_symbols_x16 & 0xF))
1581                         /* _X_ */
1582                         num_symbol_offsets = 3;
1583                 else
1584                         /* _xx_ */
1585                         num_symbol_offsets = 4;
1586
1587                 for (i = 0; i < num_symbol_offsets; i++) {
1588
1589                         /* Calculate pilot mask */
1590                         s32 curr_sym_off =
1591                                 (num_symbols_x16 / 16) + i + 25;
1592
1593                         /* Pilot magnitude mask seems to be a way to
1594                          * declare the boundaries for our detection
1595                          * window or something, it's 2 for the middle
1596                          * value(s) where the symbol is expected to be
1597                          * and 1 on the boundary values */
1598                         u8 plt_mag_map =
1599                                 (i == 0 || i == (num_symbol_offsets - 1))
1600                                                                 ? 1 : 2;
1601
1602                         if (curr_sym_off >= 0 && curr_sym_off <= 32) {
1603                                 if (curr_sym_off <= 25)
1604                                         pilot_mask[0] |= 1 << curr_sym_off;
1605                                 else if (curr_sym_off >= 27)
1606                                         pilot_mask[0] |= 1 << (curr_sym_off - 1);
1607                         } else if (curr_sym_off >= 33 && curr_sym_off <= 52)
1608                                 pilot_mask[1] |= 1 << (curr_sym_off - 33);
1609
1610                         /* Calculate magnitude mask (for viterbi decoder) */
1611                         if (curr_sym_off >= -1 && curr_sym_off <= 14)
1612                                 mag_mask[0] |=
1613                                         plt_mag_map << (curr_sym_off + 1) * 2;
1614                         else if (curr_sym_off >= 15 && curr_sym_off <= 30)
1615                                 mag_mask[1] |=
1616                                         plt_mag_map << (curr_sym_off - 15) * 2;
1617                         else if (curr_sym_off >= 31 && curr_sym_off <= 46)
1618                                 mag_mask[2] |=
1619                                         plt_mag_map << (curr_sym_off - 31) * 2;
1620                         else if (curr_sym_off >= 46 && curr_sym_off <= 53)
1621                                 mag_mask[3] |=
1622                                         plt_mag_map << (curr_sym_off - 47) * 2;
1623
1624                 }
1625
1626                 /* Write settings on hw to enable spur filter */
1627                 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL,
1628                                         AR5K_PHY_BIN_MASK_CTL_RATE, 0xff);
1629                 /* XXX: Self correlator also ? */
1630                 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ,
1631                                         AR5K_PHY_IQ_PILOT_MASK_EN |
1632                                         AR5K_PHY_IQ_CHAN_MASK_EN |
1633                                         AR5K_PHY_IQ_SPUR_FILT_EN);
1634
1635                 /* Set delta phase and freq sigma delta */
1636                 ath5k_hw_reg_write(ah,
1637                                 AR5K_REG_SM(spur_delta_phase,
1638                                         AR5K_PHY_TIMING_11_SPUR_DELTA_PHASE) |
1639                                 AR5K_REG_SM(spur_freq_sigma_delta,
1640                                 AR5K_PHY_TIMING_11_SPUR_FREQ_SD) |
1641                                 AR5K_PHY_TIMING_11_USE_SPUR_IN_AGC,
1642                                 AR5K_PHY_TIMING_11);
1643
1644                 /* Write pilot masks */
1645                 ath5k_hw_reg_write(ah, pilot_mask[0], AR5K_PHY_TIMING_7);
1646                 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_8,
1647                                         AR5K_PHY_TIMING_8_PILOT_MASK_2,
1648                                         pilot_mask[1]);
1649
1650                 ath5k_hw_reg_write(ah, pilot_mask[0], AR5K_PHY_TIMING_9);
1651                 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_10,
1652                                         AR5K_PHY_TIMING_10_PILOT_MASK_2,
1653                                         pilot_mask[1]);
1654
1655                 /* Write magnitude masks */
1656                 ath5k_hw_reg_write(ah, mag_mask[0], AR5K_PHY_BIN_MASK_1);
1657                 ath5k_hw_reg_write(ah, mag_mask[1], AR5K_PHY_BIN_MASK_2);
1658                 ath5k_hw_reg_write(ah, mag_mask[2], AR5K_PHY_BIN_MASK_3);
1659                 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL,
1660                                         AR5K_PHY_BIN_MASK_CTL_MASK_4,
1661                                         mag_mask[3]);
1662
1663                 ath5k_hw_reg_write(ah, mag_mask[0], AR5K_PHY_BIN_MASK2_1);
1664                 ath5k_hw_reg_write(ah, mag_mask[1], AR5K_PHY_BIN_MASK2_2);
1665                 ath5k_hw_reg_write(ah, mag_mask[2], AR5K_PHY_BIN_MASK2_3);
1666                 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK2_4,
1667                                         AR5K_PHY_BIN_MASK2_4_MASK_4,
1668                                         mag_mask[3]);
1669
1670         } else if (ath5k_hw_reg_read(ah, AR5K_PHY_IQ) &
1671         AR5K_PHY_IQ_SPUR_FILT_EN) {
1672                 /* Clean up spur mitigation settings and disable fliter */
1673                 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL,
1674                                         AR5K_PHY_BIN_MASK_CTL_RATE, 0);
1675                 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_IQ,
1676                                         AR5K_PHY_IQ_PILOT_MASK_EN |
1677                                         AR5K_PHY_IQ_CHAN_MASK_EN |
1678                                         AR5K_PHY_IQ_SPUR_FILT_EN);
1679                 ath5k_hw_reg_write(ah, 0, AR5K_PHY_TIMING_11);
1680
1681                 /* Clear pilot masks */
1682                 ath5k_hw_reg_write(ah, 0, AR5K_PHY_TIMING_7);
1683                 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_8,
1684                                         AR5K_PHY_TIMING_8_PILOT_MASK_2,
1685                                         0);
1686
1687                 ath5k_hw_reg_write(ah, 0, AR5K_PHY_TIMING_9);
1688                 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_10,
1689                                         AR5K_PHY_TIMING_10_PILOT_MASK_2,
1690                                         0);
1691
1692                 /* Clear magnitude masks */
1693                 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK_1);
1694                 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK_2);
1695                 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK_3);
1696                 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL,
1697                                         AR5K_PHY_BIN_MASK_CTL_MASK_4,
1698                                         0);
1699
1700                 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK2_1);
1701                 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK2_2);
1702                 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK2_3);
1703                 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK2_4,
1704                                         AR5K_PHY_BIN_MASK2_4_MASK_4,
1705                                         0);
1706         }
1707 }
1708
1709 /********************\
1710   Misc PHY functions
1711 \********************/
1712
1713 int ath5k_hw_phy_disable(struct ath5k_hw *ah)
1714 {
1715         ATH5K_TRACE(ah->ah_sc);
1716         /*Just a try M.F.*/
1717         ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT);
1718
1719         return 0;
1720 }
1721
1722 /*
1723  * Get the PHY Chip revision
1724  */
1725 u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, unsigned int chan)
1726 {
1727         unsigned int i;
1728         u32 srev;
1729         u16 ret;
1730
1731         ATH5K_TRACE(ah->ah_sc);
1732
1733         /*
1734          * Set the radio chip access register
1735          */
1736         switch (chan) {
1737         case CHANNEL_2GHZ:
1738                 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_2GHZ, AR5K_PHY(0));
1739                 break;
1740         case CHANNEL_5GHZ:
1741                 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
1742                 break;
1743         default:
1744                 return 0;
1745         }
1746
1747         mdelay(2);
1748
1749         /* ...wait until PHY is ready and read the selected radio revision */
1750         ath5k_hw_reg_write(ah, 0x00001c16, AR5K_PHY(0x34));
1751
1752         for (i = 0; i < 8; i++)
1753                 ath5k_hw_reg_write(ah, 0x00010000, AR5K_PHY(0x20));
1754
1755         if (ah->ah_version == AR5K_AR5210) {
1756                 srev = ath5k_hw_reg_read(ah, AR5K_PHY(256) >> 28) & 0xf;
1757                 ret = (u16)ath5k_hw_bitswap(srev, 4) + 1;
1758         } else {
1759                 srev = (ath5k_hw_reg_read(ah, AR5K_PHY(0x100)) >> 24) & 0xff;
1760                 ret = (u16)ath5k_hw_bitswap(((srev & 0xf0) >> 4) |
1761                                 ((srev & 0x0f) << 4), 8);
1762         }
1763
1764         /* Reset to the 5GHz mode */
1765         ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
1766
1767         return ret;
1768 }
1769
1770 /*****************\
1771 * Antenna control *
1772 \*****************/
1773
1774 static void /*TODO:Boundary check*/
1775 ath5k_hw_set_def_antenna(struct ath5k_hw *ah, u8 ant)
1776 {
1777         ATH5K_TRACE(ah->ah_sc);
1778
1779         if (ah->ah_version != AR5K_AR5210)
1780                 ath5k_hw_reg_write(ah, ant & 0x7, AR5K_DEFAULT_ANTENNA);
1781 }
1782
1783 /*
1784  * Enable/disable fast rx antenna diversity
1785  */
1786 static void
1787 ath5k_hw_set_fast_div(struct ath5k_hw *ah, u8 ee_mode, bool enable)
1788 {
1789         switch (ee_mode) {
1790         case AR5K_EEPROM_MODE_11G:
1791                 /* XXX: This is set to
1792                  * disabled on initvals !!! */
1793         case AR5K_EEPROM_MODE_11A:
1794                 if (enable)
1795                         AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGCCTL,
1796                                         AR5K_PHY_AGCCTL_OFDM_DIV_DIS);
1797                 else
1798                         AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
1799                                         AR5K_PHY_AGCCTL_OFDM_DIV_DIS);
1800                 break;
1801         case AR5K_EEPROM_MODE_11B:
1802                 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
1803                                         AR5K_PHY_AGCCTL_OFDM_DIV_DIS);
1804                 break;
1805         default:
1806                 return;
1807         }
1808
1809         if (enable) {
1810                 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RESTART,
1811                                 AR5K_PHY_RESTART_DIV_GC, 0xc);
1812
1813                 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_FAST_ANT_DIV,
1814                                         AR5K_PHY_FAST_ANT_DIV_EN);
1815         } else {
1816                 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RESTART,
1817                                 AR5K_PHY_RESTART_DIV_GC, 0x8);
1818
1819                 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_FAST_ANT_DIV,
1820                                         AR5K_PHY_FAST_ANT_DIV_EN);
1821         }
1822 }
1823
1824 /*
1825  * Set antenna operating mode
1826  */
1827 void
1828 ath5k_hw_set_antenna_mode(struct ath5k_hw *ah, u8 ant_mode)
1829 {
1830         struct ieee80211_channel *channel = ah->ah_current_channel;
1831         bool use_def_for_tx, update_def_on_tx, use_def_for_rts, fast_div;
1832         bool use_def_for_sg;
1833         u8 def_ant, tx_ant, ee_mode;
1834         u32 sta_id1 = 0;
1835
1836         def_ant = ah->ah_def_ant;
1837
1838         ATH5K_TRACE(ah->ah_sc);
1839
1840         switch (channel->hw_value & CHANNEL_MODES) {
1841         case CHANNEL_A:
1842         case CHANNEL_T:
1843         case CHANNEL_XR:
1844                 ee_mode = AR5K_EEPROM_MODE_11A;
1845                 break;
1846         case CHANNEL_G:
1847         case CHANNEL_TG:
1848                 ee_mode = AR5K_EEPROM_MODE_11G;
1849                 break;
1850         case CHANNEL_B:
1851                 ee_mode = AR5K_EEPROM_MODE_11B;
1852                 break;
1853         default:
1854                 ATH5K_ERR(ah->ah_sc,
1855                         "invalid channel: %d\n", channel->center_freq);
1856                 return;
1857         }
1858
1859         switch (ant_mode) {
1860         case AR5K_ANTMODE_DEFAULT:
1861                 tx_ant = 0;
1862                 use_def_for_tx = false;
1863                 update_def_on_tx = false;
1864                 use_def_for_rts = false;
1865                 use_def_for_sg = false;
1866                 fast_div = true;
1867                 break;
1868         case AR5K_ANTMODE_FIXED_A:
1869                 def_ant = 1;
1870                 tx_ant = 1;
1871                 use_def_for_tx = true;
1872                 update_def_on_tx = false;
1873                 use_def_for_rts = true;
1874                 use_def_for_sg = true;
1875                 fast_div = false;
1876                 break;
1877         case AR5K_ANTMODE_FIXED_B:
1878                 def_ant = 2;
1879                 tx_ant = 2;
1880                 use_def_for_tx = true;
1881                 update_def_on_tx = false;
1882                 use_def_for_rts = true;
1883                 use_def_for_sg = true;
1884                 fast_div = false;
1885                 break;
1886         case AR5K_ANTMODE_SINGLE_AP:
1887                 def_ant = 1;    /* updated on tx */
1888                 tx_ant = 0;
1889                 use_def_for_tx = true;
1890                 update_def_on_tx = true;
1891                 use_def_for_rts = true;
1892                 use_def_for_sg = true;
1893                 fast_div = true;
1894                 break;
1895         case AR5K_ANTMODE_SECTOR_AP:
1896                 tx_ant = 1;     /* variable */
1897                 use_def_for_tx = false;
1898                 update_def_on_tx = false;
1899                 use_def_for_rts = true;
1900                 use_def_for_sg = false;
1901                 fast_div = false;
1902                 break;
1903         case AR5K_ANTMODE_SECTOR_STA:
1904                 tx_ant = 1;     /* variable */
1905                 use_def_for_tx = true;
1906                 update_def_on_tx = false;
1907                 use_def_for_rts = true;
1908                 use_def_for_sg = false;
1909                 fast_div = true;
1910                 break;
1911         case AR5K_ANTMODE_DEBUG:
1912                 def_ant = 1;
1913                 tx_ant = 2;
1914                 use_def_for_tx = false;
1915                 update_def_on_tx = false;
1916                 use_def_for_rts = false;
1917                 use_def_for_sg = false;
1918                 fast_div = false;
1919                 break;
1920         default:
1921                 return;
1922         }
1923
1924         ah->ah_tx_ant = tx_ant;
1925         ah->ah_ant_mode = ant_mode;
1926         ah->ah_def_ant = def_ant;
1927
1928         sta_id1 |= use_def_for_tx ? AR5K_STA_ID1_DEFAULT_ANTENNA : 0;
1929         sta_id1 |= update_def_on_tx ? AR5K_STA_ID1_DESC_ANTENNA : 0;
1930         sta_id1 |= use_def_for_rts ? AR5K_STA_ID1_RTS_DEF_ANTENNA : 0;
1931         sta_id1 |= use_def_for_sg ? AR5K_STA_ID1_SELFGEN_DEF_ANT : 0;
1932
1933         AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, AR5K_STA_ID1_ANTENNA_SETTINGS);
1934
1935         if (sta_id1)
1936                 AR5K_REG_ENABLE_BITS(ah, AR5K_STA_ID1, sta_id1);
1937
1938         /* Note: set diversity before default antenna
1939          * because it won't work correctly */
1940         ath5k_hw_set_fast_div(ah, ee_mode, fast_div);
1941         ath5k_hw_set_def_antenna(ah, def_ant);
1942 }
1943
1944
1945 /****************\
1946 * TX power setup *
1947 \****************/
1948
1949 /*
1950  * Helper functions
1951  */
1952
1953 /*
1954  * Do linear interpolation between two given (x, y) points
1955  */
1956 static s16
1957 ath5k_get_interpolated_value(s16 target, s16 x_left, s16 x_right,
1958                                         s16 y_left, s16 y_right)
1959 {
1960         s16 ratio, result;
1961
1962         /* Avoid divide by zero and skip interpolation
1963          * if we have the same point */
1964         if ((x_left == x_right) || (y_left == y_right))
1965                 return y_left;
1966
1967         /*
1968          * Since we use ints and not fps, we need to scale up in
1969          * order to get a sane ratio value (or else we 'll eg. get
1970          * always 1 instead of 1.25, 1.75 etc). We scale up by 100
1971          * to have some accuracy both for 0.5 and 0.25 steps.
1972          */
1973         ratio = ((100 * y_right - 100 * y_left)/(x_right - x_left));
1974
1975         /* Now scale down to be in range */
1976         result = y_left + (ratio * (target - x_left) / 100);
1977
1978         return result;
1979 }
1980
1981 /*
1982  * Find vertical boundary (min pwr) for the linear PCDAC curve.
1983  *
1984  * Since we have the top of the curve and we draw the line below
1985  * until we reach 1 (1 pcdac step) we need to know which point
1986  * (x value) that is so that we don't go below y axis and have negative
1987  * pcdac values when creating the curve, or fill the table with zeroes.
1988  */
1989 static s16
1990 ath5k_get_linear_pcdac_min(const u8 *stepL, const u8 *stepR,
1991                                 const s16 *pwrL, const s16 *pwrR)
1992 {
1993         s8 tmp;
1994         s16 min_pwrL, min_pwrR;
1995         s16 pwr_i;
1996
1997         /* Some vendors write the same pcdac value twice !!! */
1998         if (stepL[0] == stepL[1] || stepR[0] == stepR[1])
1999                 return max(pwrL[0], pwrR[0]);
2000
2001         if (pwrL[0] == pwrL[1])
2002                 min_pwrL = pwrL[0];
2003         else {
2004                 pwr_i = pwrL[0];
2005                 do {
2006                         pwr_i--;
2007                         tmp = (s8) ath5k_get_interpolated_value(pwr_i,
2008                                                         pwrL[0], pwrL[1],
2009                                                         stepL[0], stepL[1]);
2010                 } while (tmp > 1);
2011
2012                 min_pwrL = pwr_i;
2013         }
2014
2015         if (pwrR[0] == pwrR[1])
2016                 min_pwrR = pwrR[0];
2017         else {
2018                 pwr_i = pwrR[0];
2019                 do {
2020                         pwr_i--;
2021                         tmp = (s8) ath5k_get_interpolated_value(pwr_i,
2022                                                         pwrR[0], pwrR[1],
2023                                                         stepR[0], stepR[1]);
2024                 } while (tmp > 1);
2025
2026                 min_pwrR = pwr_i;
2027         }
2028
2029         /* Keep the right boundary so that it works for both curves */
2030         return max(min_pwrL, min_pwrR);
2031 }
2032
2033 /*
2034  * Interpolate (pwr,vpd) points to create a Power to PDADC or a
2035  * Power to PCDAC curve.
2036  *
2037  * Each curve has power on x axis (in 0.5dB units) and PCDAC/PDADC
2038  * steps (offsets) on y axis. Power can go up to 31.5dB and max
2039  * PCDAC/PDADC step for each curve is 64 but we can write more than
2040  * one curves on hw so we can go up to 128 (which is the max step we
2041  * can write on the final table).
2042  *
2043  * We write y values (PCDAC/PDADC steps) on hw.
2044  */
2045 static void
2046 ath5k_create_power_curve(s16 pmin, s16 pmax,
2047                         const s16 *pwr, const u8 *vpd,
2048                         u8 num_points,
2049                         u8 *vpd_table, u8 type)
2050 {
2051         u8 idx[2] = { 0, 1 };
2052         s16 pwr_i = 2*pmin;
2053         int i;
2054
2055         if (num_points < 2)
2056                 return;
2057
2058         /* We want the whole line, so adjust boundaries
2059          * to cover the entire power range. Note that
2060          * power values are already 0.25dB so no need
2061          * to multiply pwr_i by 2 */
2062         if (type == AR5K_PWRTABLE_LINEAR_PCDAC) {
2063                 pwr_i = pmin;
2064                 pmin = 0;
2065                 pmax = 63;
2066         }
2067
2068         /* Find surrounding turning points (TPs)
2069          * and interpolate between them */
2070         for (i = 0; (i <= (u16) (pmax - pmin)) &&
2071         (i < AR5K_EEPROM_POWER_TABLE_SIZE); i++) {
2072
2073                 /* We passed the right TP, move to the next set of TPs
2074                  * if we pass the last TP, extrapolate above using the last
2075                  * two TPs for ratio */
2076                 if ((pwr_i > pwr[idx[1]]) && (idx[1] < num_points - 1)) {
2077                         idx[0]++;
2078                         idx[1]++;
2079                 }
2080
2081                 vpd_table[i] = (u8) ath5k_get_interpolated_value(pwr_i,
2082                                                 pwr[idx[0]], pwr[idx[1]],
2083                                                 vpd[idx[0]], vpd[idx[1]]);
2084
2085                 /* Increase by 0.5dB
2086                  * (0.25 dB units) */
2087                 pwr_i += 2;
2088         }
2089 }
2090
2091 /*
2092  * Get the surrounding per-channel power calibration piers
2093  * for a given frequency so that we can interpolate between
2094  * them and come up with an apropriate dataset for our current
2095  * channel.
2096  */
2097 static void
2098 ath5k_get_chan_pcal_surrounding_piers(struct ath5k_hw *ah,
2099                         struct ieee80211_channel *channel,
2100                         struct ath5k_chan_pcal_info **pcinfo_l,
2101                         struct ath5k_chan_pcal_info **pcinfo_r)
2102 {
2103         struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
2104         struct ath5k_chan_pcal_info *pcinfo;
2105         u8 idx_l, idx_r;
2106         u8 mode, max, i;
2107         u32 target = channel->center_freq;
2108
2109         idx_l = 0;
2110         idx_r = 0;
2111
2112         if (!(channel->hw_value & CHANNEL_OFDM)) {
2113                 pcinfo = ee->ee_pwr_cal_b;
2114                 mode = AR5K_EEPROM_MODE_11B;
2115         } else if (channel->hw_value & CHANNEL_2GHZ) {
2116                 pcinfo = ee->ee_pwr_cal_g;
2117                 mode = AR5K_EEPROM_MODE_11G;
2118         } else {
2119                 pcinfo = ee->ee_pwr_cal_a;
2120                 mode = AR5K_EEPROM_MODE_11A;
2121         }
2122         max = ee->ee_n_piers[mode] - 1;
2123
2124         /* Frequency is below our calibrated
2125          * range. Use the lowest power curve
2126          * we have */
2127         if (target < pcinfo[0].freq) {
2128                 idx_l = idx_r = 0;
2129                 goto done;
2130         }
2131
2132         /* Frequency is above our calibrated
2133          * range. Use the highest power curve
2134          * we have */
2135         if (target > pcinfo[max].freq) {
2136                 idx_l = idx_r = max;
2137                 goto done;
2138         }
2139
2140         /* Frequency is inside our calibrated
2141          * channel range. Pick the surrounding
2142          * calibration piers so that we can
2143          * interpolate */
2144         for (i = 0; i <= max; i++) {
2145
2146                 /* Frequency matches one of our calibration
2147                  * piers, no need to interpolate, just use
2148                  * that calibration pier */
2149                 if (pcinfo[i].freq == target) {
2150                         idx_l = idx_r = i;
2151                         goto done;
2152                 }
2153
2154                 /* We found a calibration pier that's above
2155                  * frequency, use this pier and the previous
2156                  * one to interpolate */
2157                 if (target < pcinfo[i].freq) {
2158                         idx_r = i;
2159                         idx_l = idx_r - 1;
2160                         goto done;
2161                 }
2162         }
2163
2164 done:
2165         *pcinfo_l = &pcinfo[idx_l];
2166         *pcinfo_r = &pcinfo[idx_r];
2167
2168         return;
2169 }
2170
2171 /*
2172  * Get the surrounding per-rate power calibration data
2173  * for a given frequency and interpolate between power
2174  * values to set max target power supported by hw for
2175  * each rate.
2176  */
2177 static void
2178 ath5k_get_rate_pcal_data(struct ath5k_hw *ah,
2179                         struct ieee80211_channel *channel,
2180                         struct ath5k_rate_pcal_info *rates)
2181 {
2182         struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
2183         struct ath5k_rate_pcal_info *rpinfo;
2184         u8 idx_l, idx_r;
2185         u8 mode, max, i;
2186         u32 target = channel->center_freq;
2187
2188         idx_l = 0;
2189         idx_r = 0;
2190
2191         if (!(channel->hw_value & CHANNEL_OFDM)) {
2192                 rpinfo = ee->ee_rate_tpwr_b;
2193                 mode = AR5K_EEPROM_MODE_11B;
2194         } else if (channel->hw_value & CHANNEL_2GHZ) {
2195                 rpinfo = ee->ee_rate_tpwr_g;
2196                 mode = AR5K_EEPROM_MODE_11G;
2197         } else {
2198                 rpinfo = ee->ee_rate_tpwr_a;
2199                 mode = AR5K_EEPROM_MODE_11A;
2200         }
2201         max = ee->ee_rate_target_pwr_num[mode] - 1;
2202
2203         /* Get the surrounding calibration
2204          * piers - same as above */
2205         if (target < rpinfo[0].freq) {
2206                 idx_l = idx_r = 0;
2207                 goto done;
2208         }
2209
2210         if (target > rpinfo[max].freq) {
2211                 idx_l = idx_r = max;
2212                 goto done;
2213         }
2214
2215         for (i = 0; i <= max; i++) {
2216
2217                 if (rpinfo[i].freq == target) {
2218                         idx_l = idx_r = i;
2219                         goto done;
2220                 }
2221
2222                 if (target < rpinfo[i].freq) {
2223                         idx_r = i;
2224                         idx_l = idx_r - 1;
2225                         goto done;
2226                 }
2227         }
2228
2229 done:
2230         /* Now interpolate power value, based on the frequency */
2231         rates->freq = target;
2232
2233         rates->target_power_6to24 =
2234                 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq,
2235                                         rpinfo[idx_r].freq,
2236                                         rpinfo[idx_l].target_power_6to24,
2237                                         rpinfo[idx_r].target_power_6to24);
2238
2239         rates->target_power_36 =
2240                 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq,
2241                                         rpinfo[idx_r].freq,
2242                                         rpinfo[idx_l].target_power_36,
2243                                         rpinfo[idx_r].target_power_36);
2244
2245         rates->target_power_48 =
2246                 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq,
2247                                         rpinfo[idx_r].freq,
2248                                         rpinfo[idx_l].target_power_48,
2249                                         rpinfo[idx_r].target_power_48);
2250
2251         rates->target_power_54 =
2252                 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq,
2253                                         rpinfo[idx_r].freq,
2254                                         rpinfo[idx_l].target_power_54,
2255                                         rpinfo[idx_r].target_power_54);
2256 }
2257
2258 /*
2259  * Get the max edge power for this channel if
2260  * we have such data from EEPROM's Conformance Test
2261  * Limits (CTL), and limit max power if needed.
2262  */
2263 static void
2264 ath5k_get_max_ctl_power(struct ath5k_hw *ah,
2265                         struct ieee80211_channel *channel)
2266 {
2267         struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah);
2268         struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
2269         struct ath5k_edge_power *rep = ee->ee_ctl_pwr;
2270         u8 *ctl_val = ee->ee_ctl;
2271         s16 max_chan_pwr = ah->ah_txpower.txp_max_pwr / 4;
2272         s16 edge_pwr = 0;
2273         u8 rep_idx;
2274         u8 i, ctl_mode;
2275         u8 ctl_idx = 0xFF;
2276         u32 target = channel->center_freq;
2277
2278         ctl_mode = ath_regd_get_band_ctl(regulatory, channel->band);
2279
2280         switch (channel->hw_value & CHANNEL_MODES) {
2281         case CHANNEL_A:
2282                 ctl_mode |= AR5K_CTL_11A;
2283                 break;
2284         case CHANNEL_G:
2285                 ctl_mode |= AR5K_CTL_11G;
2286                 break;
2287         case CHANNEL_B:
2288                 ctl_mode |= AR5K_CTL_11B;
2289                 break;
2290         case CHANNEL_T:
2291                 ctl_mode |= AR5K_CTL_TURBO;
2292                 break;
2293         case CHANNEL_TG:
2294                 ctl_mode |= AR5K_CTL_TURBOG;
2295                 break;
2296         case CHANNEL_XR:
2297                 /* Fall through */
2298         default:
2299                 return;
2300         }
2301
2302         for (i = 0; i < ee->ee_ctls; i++) {
2303                 if (ctl_val[i] == ctl_mode) {
2304                         ctl_idx = i;
2305                         break;
2306                 }
2307         }
2308
2309         /* If we have a CTL dataset available grab it and find the
2310          * edge power for our frequency */
2311         if (ctl_idx == 0xFF)
2312                 return;
2313
2314         /* Edge powers are sorted by frequency from lower
2315          * to higher. Each CTL corresponds to 8 edge power
2316          * measurements. */
2317         rep_idx = ctl_idx * AR5K_EEPROM_N_EDGES;
2318
2319         /* Don't do boundaries check because we
2320          * might have more that one bands defined
2321          * for this mode */
2322
2323         /* Get the edge power that's closer to our
2324          * frequency */
2325         for (i = 0; i < AR5K_EEPROM_N_EDGES; i++) {
2326                 rep_idx += i;
2327                 if (target <= rep[rep_idx].freq)
2328                         edge_pwr = (s16) rep[rep_idx].edge;
2329         }
2330
2331         if (edge_pwr)
2332                 ah->ah_txpower.txp_max_pwr = 4*min(edge_pwr, max_chan_pwr);
2333 }
2334
2335
2336 /*
2337  * Power to PCDAC table functions
2338  */
2339
2340 /*
2341  * Fill Power to PCDAC table on RF5111
2342  *
2343  * No further processing is needed for RF5111, the only thing we have to
2344  * do is fill the values below and above calibration range since eeprom data
2345  * may not cover the entire PCDAC table.
2346  */
2347 static void
2348 ath5k_fill_pwr_to_pcdac_table(struct ath5k_hw *ah, s16* table_min,
2349                                                         s16 *table_max)
2350 {
2351         u8      *pcdac_out = ah->ah_txpower.txp_pd_table;
2352         u8      *pcdac_tmp = ah->ah_txpower.tmpL[0];
2353         u8      pcdac_0, pcdac_n, pcdac_i, pwr_idx, i;
2354         s16     min_pwr, max_pwr;
2355
2356         /* Get table boundaries */
2357         min_pwr = table_min[0];
2358         pcdac_0 = pcdac_tmp[0];
2359
2360         max_pwr = table_max[0];
2361         pcdac_n = pcdac_tmp[table_max[0] - table_min[0]];
2362
2363         /* Extrapolate below minimum using pcdac_0 */
2364         pcdac_i = 0;
2365         for (i = 0; i < min_pwr; i++)
2366                 pcdac_out[pcdac_i++] = pcdac_0;
2367
2368         /* Copy values from pcdac_tmp */
2369         pwr_idx = min_pwr;
2370         for (i = 0 ; pwr_idx <= max_pwr &&
2371         pcdac_i < AR5K_EEPROM_POWER_TABLE_SIZE; i++) {
2372                 pcdac_out[pcdac_i++] = pcdac_tmp[i];
2373                 pwr_idx++;
2374         }
2375
2376         /* Extrapolate above maximum */
2377         while (pcdac_i < AR5K_EEPROM_POWER_TABLE_SIZE)
2378                 pcdac_out[pcdac_i++] = pcdac_n;
2379
2380 }
2381
2382 /*
2383  * Combine available XPD Curves and fill Linear Power to PCDAC table
2384  * on RF5112
2385  *
2386  * RFX112 can have up to 2 curves (one for low txpower range and one for
2387  * higher txpower range). We need to put them both on pcdac_out and place
2388  * them in the correct location. In case we only have one curve available
2389  * just fit it on pcdac_out (it's supposed to cover the entire range of
2390  * available pwr levels since it's always the higher power curve). Extrapolate
2391  * below and above final table if needed.
2392  */
2393 static void
2394 ath5k_combine_linear_pcdac_curves(struct ath5k_hw *ah, s16* table_min,
2395                                                 s16 *table_max, u8 pdcurves)
2396 {
2397         u8      *pcdac_out = ah->ah_txpower.txp_pd_table;
2398         u8      *pcdac_low_pwr;
2399         u8      *pcdac_high_pwr;
2400         u8      *pcdac_tmp;
2401         u8      pwr;
2402         s16     max_pwr_idx;
2403         s16     min_pwr_idx;
2404         s16     mid_pwr_idx = 0;
2405         /* Edge flag turs on the 7nth bit on the PCDAC
2406          * to delcare the higher power curve (force values
2407          * to be greater than 64). If we only have one curve
2408          * we don't need to set this, if we have 2 curves and
2409          * fill the table backwards this can also be used to
2410          * switch from higher power curve to lower power curve */
2411         u8      edge_flag;
2412         int     i;
2413
2414         /* When we have only one curve available
2415          * that's the higher power curve. If we have
2416          * two curves the first is the high power curve
2417          * and the next is the low power curve. */
2418         if (pdcurves > 1) {
2419                 pcdac_low_pwr = ah->ah_txpower.tmpL[1];
2420                 pcdac_high_pwr = ah->ah_txpower.tmpL[0];
2421                 mid_pwr_idx = table_max[1] - table_min[1] - 1;
2422                 max_pwr_idx = (table_max[0] - table_min[0]) / 2;
2423
2424                 /* If table size goes beyond 31.5dB, keep the
2425                  * upper 31.5dB range when setting tx power.
2426                  * Note: 126 = 31.5 dB in quarter dB steps */
2427                 if (table_max[0] - table_min[1] > 126)
2428                         min_pwr_idx = table_max[0] - 126;
2429                 else
2430                         min_pwr_idx = table_min[1];
2431
2432                 /* Since we fill table backwards
2433                  * start from high power curve */
2434                 pcdac_tmp = pcdac_high_pwr;
2435
2436                 edge_flag = 0x40;
2437         } else {
2438                 pcdac_low_pwr = ah->ah_txpower.tmpL[1]; /* Zeroed */
2439                 pcdac_high_pwr = ah->ah_txpower.tmpL[0];
2440                 min_pwr_idx = table_min[0];
2441                 max_pwr_idx = (table_max[0] - table_min[0]) / 2;
2442                 pcdac_tmp = pcdac_high_pwr;
2443                 edge_flag = 0;
2444         }
2445
2446         /* This is used when setting tx power*/
2447         ah->ah_txpower.txp_min_idx = min_pwr_idx/2;
2448
2449         /* Fill Power to PCDAC table backwards */
2450         pwr = max_pwr_idx;
2451         for (i = 63; i >= 0; i--) {
2452                 /* Entering lower power range, reset
2453                  * edge flag and set pcdac_tmp to lower
2454                  * power curve.*/
2455                 if (edge_flag == 0x40 &&
2456                 (2*pwr <= (table_max[1] - table_min[0]) || pwr == 0)) {
2457                         edge_flag = 0x00;
2458                         pcdac_tmp = pcdac_low_pwr;
2459                         pwr = mid_pwr_idx/2;
2460                 }
2461
2462                 /* Don't go below 1, extrapolate below if we have
2463                  * already swithced to the lower power curve -or
2464                  * we only have one curve and edge_flag is zero
2465                  * anyway */
2466                 if (pcdac_tmp[pwr] < 1 && (edge_flag == 0x00)) {
2467                         while (i >= 0) {
2468                                 pcdac_out[i] = pcdac_out[i + 1];
2469                                 i--;
2470                         }
2471                         break;
2472                 }
2473
2474                 pcdac_out[i] = pcdac_tmp[pwr] | edge_flag;
2475
2476                 /* Extrapolate above if pcdac is greater than
2477                  * 126 -this can happen because we OR pcdac_out
2478                  * value with edge_flag on high power curve */
2479                 if (pcdac_out[i] > 126)
2480                         pcdac_out[i] = 126;
2481
2482                 /* Decrease by a 0.5dB step */
2483                 pwr--;
2484         }
2485 }
2486
2487 /* Write PCDAC values on hw */
2488 static void
2489 ath5k_setup_pcdac_table(struct ath5k_hw *ah)
2490 {
2491         u8      *pcdac_out = ah->ah_txpower.txp_pd_table;
2492         int     i;
2493
2494         /*
2495          * Write TX power values
2496          */
2497         for (i = 0; i < (AR5K_EEPROM_POWER_TABLE_SIZE / 2); i++) {
2498                 ath5k_hw_reg_write(ah,
2499                         (((pcdac_out[2*i + 0] << 8 | 0xff) & 0xffff) << 0) |
2500                         (((pcdac_out[2*i + 1] << 8 | 0xff) & 0xffff) << 16),
2501                         AR5K_PHY_PCDAC_TXPOWER(i));
2502         }
2503 }
2504
2505
2506 /*
2507  * Power to PDADC table functions
2508  */
2509
2510 /*
2511  * Set the gain boundaries and create final Power to PDADC table
2512  *
2513  * We can have up to 4 pd curves, we need to do a simmilar process
2514  * as we do for RF5112. This time we don't have an edge_flag but we
2515  * set the gain boundaries on a separate register.
2516  */
2517 static void
2518 ath5k_combine_pwr_to_pdadc_curves(struct ath5k_hw *ah,
2519                         s16 *pwr_min, s16 *pwr_max, u8 pdcurves)
2520 {
2521         u8 gain_boundaries[AR5K_EEPROM_N_PD_GAINS];
2522         u8 *pdadc_out = ah->ah_txpower.txp_pd_table;
2523         u8 *pdadc_tmp;
2524         s16 pdadc_0;
2525         u8 pdadc_i, pdadc_n, pwr_step, pdg, max_idx, table_size;
2526         u8 pd_gain_overlap;
2527
2528         /* Note: Register value is initialized on initvals
2529          * there is no feedback from hw.
2530          * XXX: What about pd_gain_overlap from EEPROM ? */
2531         pd_gain_overlap = (u8) ath5k_hw_reg_read(ah, AR5K_PHY_TPC_RG5) &
2532                 AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP;
2533
2534         /* Create final PDADC table */
2535         for (pdg = 0, pdadc_i = 0; pdg < pdcurves; pdg++) {
2536                 pdadc_tmp = ah->ah_txpower.tmpL[pdg];
2537
2538                 if (pdg == pdcurves - 1)
2539                         /* 2 dB boundary stretch for last
2540                          * (higher power) curve */
2541                         gain_boundaries[pdg] = pwr_max[pdg] + 4;
2542                 else
2543                         /* Set gain boundary in the middle
2544                          * between this curve and the next one */
2545                         gain_boundaries[pdg] =
2546                                 (pwr_max[pdg] + pwr_min[pdg + 1]) / 2;
2547
2548                 /* Sanity check in case our 2 db stretch got out of
2549                  * range. */
2550                 if (gain_boundaries[pdg] > AR5K_TUNE_MAX_TXPOWER)
2551                         gain_boundaries[pdg] = AR5K_TUNE_MAX_TXPOWER;
2552
2553                 /* For the first curve (lower power)
2554                  * start from 0 dB */
2555                 if (pdg == 0)
2556                         pdadc_0 = 0;
2557                 else
2558                         /* For the other curves use the gain overlap */
2559                         pdadc_0 = (gain_boundaries[pdg - 1] - pwr_min[pdg]) -
2560                                                         pd_gain_overlap;
2561
2562                 /* Force each power step to be at least 0.5 dB */
2563                 if ((pdadc_tmp[1] - pdadc_tmp[0]) > 1)
2564                         pwr_step = pdadc_tmp[1] - pdadc_tmp[0];
2565                 else
2566                         pwr_step = 1;
2567
2568                 /* If pdadc_0 is negative, we need to extrapolate
2569                  * below this pdgain by a number of pwr_steps */
2570                 while ((pdadc_0 < 0) && (pdadc_i < 128)) {
2571                         s16 tmp = pdadc_tmp[0] + pdadc_0 * pwr_step;
2572                         pdadc_out[pdadc_i++] = (tmp < 0) ? 0 : (u8) tmp;
2573                         pdadc_0++;
2574                 }
2575
2576                 /* Set last pwr level, using gain boundaries */
2577                 pdadc_n = gain_boundaries[pdg] + pd_gain_overlap - pwr_min[pdg];
2578                 /* Limit it to be inside pwr range */
2579                 table_size = pwr_max[pdg] - pwr_min[pdg];
2580                 max_idx = (pdadc_n < table_size) ? pdadc_n : table_size;
2581
2582                 /* Fill pdadc_out table */
2583                 while (pdadc_0 < max_idx)
2584                         pdadc_out[pdadc_i++] = pdadc_tmp[pdadc_0++];
2585
2586                 /* Need to extrapolate above this pdgain? */
2587                 if (pdadc_n <= max_idx)
2588                         continue;
2589
2590                 /* Force each power step to be at least 0.5 dB */
2591                 if ((pdadc_tmp[table_size - 1] - pdadc_tmp[table_size - 2]) > 1)
2592                         pwr_step = pdadc_tmp[table_size - 1] -
2593                                                 pdadc_tmp[table_size - 2];
2594                 else
2595                         pwr_step = 1;
2596
2597                 /* Extrapolate above */
2598                 while ((pdadc_0 < (s16) pdadc_n) &&
2599                 (pdadc_i < AR5K_EEPROM_POWER_TABLE_SIZE * 2)) {
2600                         s16 tmp = pdadc_tmp[table_size - 1] +
2601                                         (pdadc_0 - max_idx) * pwr_step;
2602                         pdadc_out[pdadc_i++] = (tmp > 127) ? 127 : (u8) tmp;
2603                         pdadc_0++;
2604                 }
2605         }
2606
2607         while (pdg < AR5K_EEPROM_N_PD_GAINS) {
2608                 gain_boundaries[pdg] = gain_boundaries[pdg - 1];
2609                 pdg++;
2610         }
2611
2612         while (pdadc_i < AR5K_EEPROM_POWER_TABLE_SIZE * 2) {
2613                 pdadc_out[pdadc_i] = pdadc_out[pdadc_i - 1];
2614                 pdadc_i++;
2615         }
2616
2617         /* Set gain boundaries */
2618         ath5k_hw_reg_write(ah,
2619                 AR5K_REG_SM(pd_gain_overlap,
2620                         AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP) |
2621                 AR5K_REG_SM(gain_boundaries[0],
2622                         AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_1) |
2623                 AR5K_REG_SM(gain_boundaries[1],
2624                         AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_2) |
2625                 AR5K_REG_SM(gain_boundaries[2],
2626                         AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_3) |
2627                 AR5K_REG_SM(gain_boundaries[3],
2628                         AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_4),
2629                 AR5K_PHY_TPC_RG5);
2630
2631         /* Used for setting rate power table */
2632         ah->ah_txpower.txp_min_idx = pwr_min[0];
2633
2634 }
2635
2636 /* Write PDADC values on hw */
2637 static void
2638 ath5k_setup_pwr_to_pdadc_table(struct ath5k_hw *ah,
2639                         u8 pdcurves, u8 *pdg_to_idx)
2640 {
2641         u8 *pdadc_out = ah->ah_txpower.txp_pd_table;
2642         u32 reg;
2643         u8 i;
2644
2645         /* Select the right pdgain curves */
2646
2647         /* Clear current settings */
2648         reg = ath5k_hw_reg_read(ah, AR5K_PHY_TPC_RG1);
2649         reg &= ~(AR5K_PHY_TPC_RG1_PDGAIN_1 |
2650                 AR5K_PHY_TPC_RG1_PDGAIN_2 |
2651                 AR5K_PHY_TPC_RG1_PDGAIN_3 |
2652                 AR5K_PHY_TPC_RG1_NUM_PD_GAIN);
2653
2654         /*
2655          * Use pd_gains curve from eeprom
2656          *
2657          * This overrides the default setting from initvals
2658          * in case some vendors (e.g. Zcomax) don't use the default
2659          * curves. If we don't honor their settings we 'll get a
2660          * 5dB (1 * gain overlap ?) drop.
2661          */
2662         reg |= AR5K_REG_SM(pdcurves, AR5K_PHY_TPC_RG1_NUM_PD_GAIN);
2663
2664         switch (pdcurves) {
2665         case 3:
2666                 reg |= AR5K_REG_SM(pdg_to_idx[2], AR5K_PHY_TPC_RG1_PDGAIN_3);
2667                 /* Fall through */
2668         case 2:
2669                 reg |= AR5K_REG_SM(pdg_to_idx[1], AR5K_PHY_TPC_RG1_PDGAIN_2);
2670                 /* Fall through */
2671         case 1:
2672                 reg |= AR5K_REG_SM(pdg_to_idx[0], AR5K_PHY_TPC_RG1_PDGAIN_1);
2673                 break;
2674         }
2675         ath5k_hw_reg_write(ah, reg, AR5K_PHY_TPC_RG1);
2676
2677         /*
2678          * Write TX power values
2679          */
2680         for (i = 0; i < (AR5K_EEPROM_POWER_TABLE_SIZE / 2); i++) {
2681                 ath5k_hw_reg_write(ah,
2682                         ((pdadc_out[4*i + 0] & 0xff) << 0) |
2683                         ((pdadc_out[4*i + 1] & 0xff) << 8) |
2684                         ((pdadc_out[4*i + 2] & 0xff) << 16) |
2685                         ((pdadc_out[4*i + 3] & 0xff) << 24),
2686                         AR5K_PHY_PDADC_TXPOWER(i));
2687         }
2688 }
2689
2690
2691 /*
2692  * Common code for PCDAC/PDADC tables
2693  */
2694
2695 /*
2696  * This is the main function that uses all of the above
2697  * to set PCDAC/PDADC table on hw for the current channel.
2698  * This table is used for tx power calibration on the basband,
2699  * without it we get weird tx power levels and in some cases
2700  * distorted spectral mask
2701  */
2702 static int
2703 ath5k_setup_channel_powertable(struct ath5k_hw *ah,
2704                         struct ieee80211_channel *channel,
2705                         u8 ee_mode, u8 type)
2706 {
2707         struct ath5k_pdgain_info *pdg_L, *pdg_R;
2708         struct ath5k_chan_pcal_info *pcinfo_L;
2709         struct ath5k_chan_pcal_info *pcinfo_R;
2710         struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
2711         u8 *pdg_curve_to_idx = ee->ee_pdc_to_idx[ee_mode];
2712         s16 table_min[AR5K_EEPROM_N_PD_GAINS];
2713         s16 table_max[AR5K_EEPROM_N_PD_GAINS];
2714         u8 *tmpL;
2715         u8 *tmpR;
2716         u32 target = channel->center_freq;
2717         int pdg, i;
2718
2719         /* Get surounding freq piers for this channel */
2720         ath5k_get_chan_pcal_surrounding_piers(ah, channel,
2721                                                 &pcinfo_L,
2722                                                 &pcinfo_R);
2723
2724         /* Loop over pd gain curves on
2725          * surounding freq piers by index */
2726         for (pdg = 0; pdg < ee->ee_pd_gains[ee_mode]; pdg++) {
2727
2728                 /* Fill curves in reverse order
2729                  * from lower power (max gain)
2730                  * to higher power. Use curve -> idx
2731                  * backmapping we did on eeprom init */
2732                 u8 idx = pdg_curve_to_idx[pdg];
2733
2734                 /* Grab the needed curves by index */
2735                 pdg_L = &pcinfo_L->pd_curves[idx];
2736                 pdg_R = &pcinfo_R->pd_curves[idx];
2737
2738                 /* Initialize the temp tables */
2739                 tmpL = ah->ah_txpower.tmpL[pdg];
2740                 tmpR = ah->ah_txpower.tmpR[pdg];
2741
2742                 /* Set curve's x boundaries and create
2743                  * curves so that they cover the same
2744                  * range (if we don't do that one table
2745                  * will have values on some range and the
2746                  * other one won't have any so interpolation
2747                  * will fail) */
2748                 table_min[pdg] = min(pdg_L->pd_pwr[0],
2749                                         pdg_R->pd_pwr[0]) / 2;
2750
2751                 table_max[pdg] = max(pdg_L->pd_pwr[pdg_L->pd_points - 1],
2752                                 pdg_R->pd_pwr[pdg_R->pd_points - 1]) / 2;
2753
2754                 /* Now create the curves on surrounding channels
2755                  * and interpolate if needed to get the final
2756                  * curve for this gain on this channel */
2757                 switch (type) {
2758                 case AR5K_PWRTABLE_LINEAR_PCDAC:
2759                         /* Override min/max so that we don't loose
2760                          * accuracy (don't divide by 2) */
2761                         table_min[pdg] = min(pdg_L->pd_pwr[0],
2762                                                 pdg_R->pd_pwr[0]);
2763
2764                         table_max[pdg] =
2765                                 max(pdg_L->pd_pwr[pdg_L->pd_points - 1],
2766                                         pdg_R->pd_pwr[pdg_R->pd_points - 1]);
2767
2768                         /* Override minimum so that we don't get
2769                          * out of bounds while extrapolating
2770                          * below. Don't do this when we have 2
2771                          * curves and we are on the high power curve
2772                          * because table_min is ok in this case */
2773                         if (!(ee->ee_pd_gains[ee_mode] > 1 && pdg == 0)) {
2774
2775                                 table_min[pdg] =
2776                                         ath5k_get_linear_pcdac_min(pdg_L->pd_step,
2777                                                                 pdg_R->pd_step,
2778                                                                 pdg_L->pd_pwr,
2779                                                                 pdg_R->pd_pwr);
2780
2781                                 /* Don't go too low because we will
2782                                  * miss the upper part of the curve.
2783                                  * Note: 126 = 31.5dB (max power supported)
2784                                  * in 0.25dB units */
2785                                 if (table_max[pdg] - table_min[pdg] > 126)
2786                                         table_min[pdg] = table_max[pdg] - 126;
2787                         }
2788
2789                         /* Fall through */
2790                 case AR5K_PWRTABLE_PWR_TO_PCDAC:
2791                 case AR5K_PWRTABLE_PWR_TO_PDADC:
2792
2793                         ath5k_create_power_curve(table_min[pdg],
2794                                                 table_max[pdg],
2795                                                 pdg_L->pd_pwr,
2796                                                 pdg_L->pd_step,
2797                                                 pdg_L->pd_points, tmpL, type);
2798
2799                         /* We are in a calibration
2800                          * pier, no need to interpolate
2801                          * between freq piers */
2802                         if (pcinfo_L == pcinfo_R)
2803                                 continue;
2804
2805                         ath5k_create_power_curve(table_min[pdg],
2806                                                 table_max[pdg],
2807                                                 pdg_R->pd_pwr,
2808                                                 pdg_R->pd_step,
2809                                                 pdg_R->pd_points, tmpR, type);
2810                         break;
2811                 default:
2812                         return -EINVAL;
2813                 }
2814
2815                 /* Interpolate between curves
2816                  * of surounding freq piers to
2817                  * get the final curve for this
2818                  * pd gain. Re-use tmpL for interpolation
2819                  * output */
2820                 for (i = 0; (i < (u16) (table_max[pdg] - table_min[pdg])) &&
2821                 (i < AR5K_EEPROM_POWER_TABLE_SIZE); i++) {
2822                         tmpL[i] = (u8) ath5k_get_interpolated_value(target,
2823                                                         (s16) pcinfo_L->freq,
2824                                                         (s16) pcinfo_R->freq,
2825                                                         (s16) tmpL[i],
2826                                                         (s16) tmpR[i]);
2827                 }
2828         }
2829
2830         /* Now we have a set of curves for this
2831          * channel on tmpL (x range is table_max - table_min
2832          * and y values are tmpL[pdg][]) sorted in the same
2833          * order as EEPROM (because we've used the backmapping).
2834          * So for RF5112 it's from higher power to lower power
2835          * and for RF2413 it's from lower power to higher power.
2836          * For RF5111 we only have one curve. */
2837
2838         /* Fill min and max power levels for this
2839          * channel by interpolating the values on
2840          * surounding channels to complete the dataset */
2841         ah->ah_txpower.txp_min_pwr = ath5k_get_interpolated_value(target,
2842                                         (s16) pcinfo_L->freq,
2843                                         (s16) pcinfo_R->freq,
2844                                         pcinfo_L->min_pwr, pcinfo_R->min_pwr);
2845
2846         ah->ah_txpower.txp_max_pwr = ath5k_get_interpolated_value(target,
2847                                         (s16) pcinfo_L->freq,
2848                                         (s16) pcinfo_R->freq,
2849                                         pcinfo_L->max_pwr, pcinfo_R->max_pwr);
2850
2851         /* We are ready to go, fill PCDAC/PDADC
2852          * table and write settings on hardware */
2853         switch (type) {
2854         case AR5K_PWRTABLE_LINEAR_PCDAC:
2855                 /* For RF5112 we can have one or two curves
2856                  * and each curve covers a certain power lvl
2857                  * range so we need to do some more processing */
2858                 ath5k_combine_linear_pcdac_curves(ah, table_min, table_max,
2859                                                 ee->ee_pd_gains[ee_mode]);
2860
2861                 /* Set txp.offset so that we can
2862                  * match max power value with max
2863                  * table index */
2864                 ah->ah_txpower.txp_offset = 64 - (table_max[0] / 2);
2865
2866                 /* Write settings on hw */
2867                 ath5k_setup_pcdac_table(ah);
2868                 break;
2869         case AR5K_PWRTABLE_PWR_TO_PCDAC:
2870                 /* We are done for RF5111 since it has only
2871                  * one curve, just fit the curve on the table */
2872                 ath5k_fill_pwr_to_pcdac_table(ah, table_min, table_max);
2873
2874                 /* No rate powertable adjustment for RF5111 */
2875                 ah->ah_txpower.txp_min_idx = 0;
2876                 ah->ah_txpower.txp_offset = 0;
2877
2878                 /* Write settings on hw */
2879                 ath5k_setup_pcdac_table(ah);
2880                 break;
2881         case AR5K_PWRTABLE_PWR_TO_PDADC:
2882                 /* Set PDADC boundaries and fill
2883                  * final PDADC table */
2884                 ath5k_combine_pwr_to_pdadc_curves(ah, table_min, table_max,
2885                                                 ee->ee_pd_gains[ee_mode]);
2886
2887                 /* Write settings on hw */
2888                 ath5k_setup_pwr_to_pdadc_table(ah, pdg, pdg_curve_to_idx);
2889
2890                 /* Set txp.offset, note that table_min
2891                  * can be negative */
2892                 ah->ah_txpower.txp_offset = table_min[0];
2893                 break;
2894         default:
2895                 return -EINVAL;
2896         }
2897
2898         return 0;
2899 }
2900
2901
2902 /*
2903  * Per-rate tx power setting
2904  *
2905  * This is the code that sets the desired tx power (below
2906  * maximum) on hw for each rate (we also have TPC that sets
2907  * power per packet). We do that by providing an index on the
2908  * PCDAC/PDADC table we set up.
2909  */
2910
2911 /*
2912  * Set rate power table
2913  *
2914  * For now we only limit txpower based on maximum tx power
2915  * supported by hw (what's inside rate_info). We need to limit
2916  * this even more, based on regulatory domain etc.
2917  *
2918  * Rate power table contains indices to PCDAC/PDADC table (0.5dB steps)
2919  * and is indexed as follows:
2920  * rates[0] - rates[7] -> OFDM rates
2921  * rates[8] - rates[14] -> CCK rates
2922  * rates[15] -> XR rates (they all have the same power)
2923  */
2924 static void
2925 ath5k_setup_rate_powertable(struct ath5k_hw *ah, u16 max_pwr,
2926                         struct ath5k_rate_pcal_info *rate_info,
2927                         u8 ee_mode)
2928 {
2929         unsigned int i;
2930         u16 *rates;
2931
2932         /* max_pwr is power level we got from driver/user in 0.5dB
2933          * units, switch to 0.25dB units so we can compare */
2934         max_pwr *= 2;
2935         max_pwr = min(max_pwr, (u16) ah->ah_txpower.txp_max_pwr) / 2;
2936
2937         /* apply rate limits */
2938         rates = ah->ah_txpower.txp_rates_power_table;
2939
2940         /* OFDM rates 6 to 24Mb/s */
2941         for (i = 0; i < 5; i++)
2942                 rates[i] = min(max_pwr, rate_info->target_power_6to24);
2943
2944         /* Rest OFDM rates */
2945         rates[5] = min(rates[0], rate_info->target_power_36);
2946         rates[6] = min(rates[0], rate_info->target_power_48);
2947         rates[7] = min(rates[0], rate_info->target_power_54);
2948
2949         /* CCK rates */
2950         /* 1L */
2951         rates[8] = min(rates[0], rate_info->target_power_6to24);
2952         /* 2L */
2953         rates[9] = min(rates[0], rate_info->target_power_36);
2954         /* 2S */
2955         rates[10] = min(rates[0], rate_info->target_power_36);
2956         /* 5L */
2957         rates[11] = min(rates[0], rate_info->target_power_48);
2958         /* 5S */
2959         rates[12] = min(rates[0], rate_info->target_power_48);
2960         /* 11L */
2961         rates[13] = min(rates[0], rate_info->target_power_54);
2962         /* 11S */
2963         rates[14] = min(rates[0], rate_info->target_power_54);
2964
2965         /* XR rates */
2966         rates[15] = min(rates[0], rate_info->target_power_6to24);
2967
2968         /* CCK rates have different peak to average ratio
2969          * so we have to tweak their power so that gainf
2970          * correction works ok. For this we use OFDM to
2971          * CCK delta from eeprom */
2972         if ((ee_mode == AR5K_EEPROM_MODE_11G) &&
2973         (ah->ah_phy_revision < AR5K_SREV_PHY_5212A))
2974                 for (i = 8; i <= 15; i++)
2975                         rates[i] -= ah->ah_txpower.txp_cck_ofdm_gainf_delta;
2976
2977         /* Now that we have all rates setup use table offset to
2978          * match the power range set by user with the power indices
2979          * on PCDAC/PDADC table */
2980         for (i = 0; i < 16; i++) {
2981                 rates[i] += ah->ah_txpower.txp_offset;
2982                 /* Don't get out of bounds */
2983                 if (rates[i] > 63)
2984                         rates[i] = 63;
2985         }
2986
2987         /* Min/max in 0.25dB units */
2988         ah->ah_txpower.txp_min_pwr = 2 * rates[7];
2989         ah->ah_txpower.txp_max_pwr = 2 * rates[0];
2990         ah->ah_txpower.txp_ofdm = rates[7];
2991 }
2992
2993
2994 /*
2995  * Set transmition power
2996  */
2997 int
2998 ath5k_hw_txpower(struct ath5k_hw *ah, struct ieee80211_channel *channel,
2999                 u8 ee_mode, u8 txpower)
3000 {
3001         struct ath5k_rate_pcal_info rate_info;
3002         u8 type;
3003         int ret;
3004
3005         ATH5K_TRACE(ah->ah_sc);
3006         if (txpower > AR5K_TUNE_MAX_TXPOWER) {
3007                 ATH5K_ERR(ah->ah_sc, "invalid tx power: %u\n", txpower);
3008                 return -EINVAL;
3009         }
3010
3011         /* Reset TX power values */
3012         memset(&ah->ah_txpower, 0, sizeof(ah->ah_txpower));
3013         ah->ah_txpower.txp_tpc = AR5K_TUNE_TPC_TXPOWER;
3014         ah->ah_txpower.txp_min_pwr = 0;
3015         ah->ah_txpower.txp_max_pwr = AR5K_TUNE_MAX_TXPOWER;
3016
3017         /* Initialize TX power table */
3018         switch (ah->ah_radio) {
3019         case AR5K_RF5111:
3020                 type = AR5K_PWRTABLE_PWR_TO_PCDAC;
3021                 break;
3022         case AR5K_RF5112:
3023                 type = AR5K_PWRTABLE_LINEAR_PCDAC;
3024                 break;
3025         case AR5K_RF2413:
3026         case AR5K_RF5413:
3027         case AR5K_RF2316:
3028         case AR5K_RF2317:
3029         case AR5K_RF2425:
3030                 type = AR5K_PWRTABLE_PWR_TO_PDADC;
3031                 break;
3032         default:
3033                 return -EINVAL;
3034         }
3035
3036         /* FIXME: Only on channel/mode change */
3037         ret = ath5k_setup_channel_powertable(ah, channel, ee_mode, type);
3038         if (ret)
3039                 return ret;
3040
3041         /* Limit max power if we have a CTL available */
3042         ath5k_get_max_ctl_power(ah, channel);
3043
3044         /* FIXME: Tx power limit for this regdomain
3045          * XXX: Mac80211/CRDA will do that anyway ? */
3046
3047         /* FIXME: Antenna reduction stuff */
3048
3049         /* FIXME: Limit power on turbo modes */
3050
3051         /* FIXME: TPC scale reduction */
3052
3053         /* Get surounding channels for per-rate power table
3054          * calibration */
3055         ath5k_get_rate_pcal_data(ah, channel, &rate_info);
3056
3057         /* Setup rate power table */
3058         ath5k_setup_rate_powertable(ah, txpower, &rate_info, ee_mode);
3059
3060         /* Write rate power table on hw */
3061         ath5k_hw_reg_write(ah, AR5K_TXPOWER_OFDM(3, 24) |
3062                 AR5K_TXPOWER_OFDM(2, 16) | AR5K_TXPOWER_OFDM(1, 8) |
3063                 AR5K_TXPOWER_OFDM(0, 0), AR5K_PHY_TXPOWER_RATE1);
3064
3065         ath5k_hw_reg_write(ah, AR5K_TXPOWER_OFDM(7, 24) |
3066                 AR5K_TXPOWER_OFDM(6, 16) | AR5K_TXPOWER_OFDM(5, 8) |
3067                 AR5K_TXPOWER_OFDM(4, 0), AR5K_PHY_TXPOWER_RATE2);
3068
3069         ath5k_hw_reg_write(ah, AR5K_TXPOWER_CCK(10, 24) |
3070                 AR5K_TXPOWER_CCK(9, 16) | AR5K_TXPOWER_CCK(15, 8) |
3071                 AR5K_TXPOWER_CCK(8, 0), AR5K_PHY_TXPOWER_RATE3);
3072
3073         ath5k_hw_reg_write(ah, AR5K_TXPOWER_CCK(14, 24) |
3074                 AR5K_TXPOWER_CCK(13, 16) | AR5K_TXPOWER_CCK(12, 8) |
3075                 AR5K_TXPOWER_CCK(11, 0), AR5K_PHY_TXPOWER_RATE4);
3076
3077         /* FIXME: TPC support */
3078         if (ah->ah_txpower.txp_tpc) {
3079                 ath5k_hw_reg_write(ah, AR5K_PHY_TXPOWER_RATE_MAX_TPC_ENABLE |
3080                         AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX);
3081
3082                 ath5k_hw_reg_write(ah,
3083                         AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_ACK) |
3084                         AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_CTS) |
3085                         AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_CHIRP),
3086                         AR5K_TPC);
3087         } else {
3088                 ath5k_hw_reg_write(ah, AR5K_PHY_TXPOWER_RATE_MAX |
3089                         AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX);
3090         }
3091
3092         return 0;
3093 }
3094
3095 int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, u8 txpower)
3096 {
3097         /*Just a try M.F.*/
3098         struct ieee80211_channel *channel = ah->ah_current_channel;
3099         u8 ee_mode;
3100
3101         ATH5K_TRACE(ah->ah_sc);
3102
3103         switch (channel->hw_value & CHANNEL_MODES) {
3104         case CHANNEL_A:
3105         case CHANNEL_T:
3106         case CHANNEL_XR:
3107                 ee_mode = AR5K_EEPROM_MODE_11A;
3108                 break;
3109         case CHANNEL_G:
3110         case CHANNEL_TG:
3111                 ee_mode = AR5K_EEPROM_MODE_11G;
3112                 break;
3113         case CHANNEL_B:
3114                 ee_mode = AR5K_EEPROM_MODE_11B;
3115                 break;
3116         default:
3117                 ATH5K_ERR(ah->ah_sc,
3118                         "invalid channel: %d\n", channel->center_freq);
3119                 return -EINVAL;
3120         }
3121
3122         ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_TXPOWER,
3123                 "changing txpower to %d\n", txpower);
3124
3125         return ath5k_hw_txpower(ah, channel, ee_mode, txpower);
3126 }