2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
43 #include <linux/module.h>
44 #include <linux/delay.h>
45 #include <linux/hardirq.h>
48 #include <linux/netdevice.h>
49 #include <linux/cache.h>
50 #include <linux/pci.h>
51 #include <linux/ethtool.h>
52 #include <linux/uaccess.h>
54 #include <net/ieee80211_radiotap.h>
56 #include <asm/unaligned.h>
62 static u8 ath5k_calinterval = 10; /* Calibrate PHY every 10 secs (TODO: Fixme) */
63 static int modparam_nohwcrypt;
64 module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
65 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
67 static int modparam_all_channels;
68 module_param_named(all_channels, modparam_all_channels, bool, S_IRUGO);
69 MODULE_PARM_DESC(all_channels, "Expose all channels the device can use.");
77 MODULE_AUTHOR("Jiri Slaby");
78 MODULE_AUTHOR("Nick Kossifidis");
79 MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
80 MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
81 MODULE_LICENSE("Dual BSD/GPL");
82 MODULE_VERSION("0.6.0 (EXPERIMENTAL)");
86 static const struct pci_device_id ath5k_pci_id_table[] = {
87 { PCI_VDEVICE(ATHEROS, 0x0207) }, /* 5210 early */
88 { PCI_VDEVICE(ATHEROS, 0x0007) }, /* 5210 */
89 { PCI_VDEVICE(ATHEROS, 0x0011) }, /* 5311 - this is on AHB bus !*/
90 { PCI_VDEVICE(ATHEROS, 0x0012) }, /* 5211 */
91 { PCI_VDEVICE(ATHEROS, 0x0013) }, /* 5212 */
92 { PCI_VDEVICE(3COM_2, 0x0013) }, /* 3com 5212 */
93 { PCI_VDEVICE(3COM, 0x0013) }, /* 3com 3CRDAG675 5212 */
94 { PCI_VDEVICE(ATHEROS, 0x1014) }, /* IBM minipci 5212 */
95 { PCI_VDEVICE(ATHEROS, 0x0014) }, /* 5212 combatible */
96 { PCI_VDEVICE(ATHEROS, 0x0015) }, /* 5212 combatible */
97 { PCI_VDEVICE(ATHEROS, 0x0016) }, /* 5212 combatible */
98 { PCI_VDEVICE(ATHEROS, 0x0017) }, /* 5212 combatible */
99 { PCI_VDEVICE(ATHEROS, 0x0018) }, /* 5212 combatible */
100 { PCI_VDEVICE(ATHEROS, 0x0019) }, /* 5212 combatible */
101 { PCI_VDEVICE(ATHEROS, 0x001a) }, /* 2413 Griffin-lite */
102 { PCI_VDEVICE(ATHEROS, 0x001b) }, /* 5413 Eagle */
103 { PCI_VDEVICE(ATHEROS, 0x001c) }, /* PCI-E cards */
104 { PCI_VDEVICE(ATHEROS, 0x001d) }, /* 2417 Nala */
107 MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table);
110 static const struct ath5k_srev_name srev_names[] = {
111 { "5210", AR5K_VERSION_MAC, AR5K_SREV_AR5210 },
112 { "5311", AR5K_VERSION_MAC, AR5K_SREV_AR5311 },
113 { "5311A", AR5K_VERSION_MAC, AR5K_SREV_AR5311A },
114 { "5311B", AR5K_VERSION_MAC, AR5K_SREV_AR5311B },
115 { "5211", AR5K_VERSION_MAC, AR5K_SREV_AR5211 },
116 { "5212", AR5K_VERSION_MAC, AR5K_SREV_AR5212 },
117 { "5213", AR5K_VERSION_MAC, AR5K_SREV_AR5213 },
118 { "5213A", AR5K_VERSION_MAC, AR5K_SREV_AR5213A },
119 { "2413", AR5K_VERSION_MAC, AR5K_SREV_AR2413 },
120 { "2414", AR5K_VERSION_MAC, AR5K_SREV_AR2414 },
121 { "5424", AR5K_VERSION_MAC, AR5K_SREV_AR5424 },
122 { "5413", AR5K_VERSION_MAC, AR5K_SREV_AR5413 },
123 { "5414", AR5K_VERSION_MAC, AR5K_SREV_AR5414 },
124 { "2415", AR5K_VERSION_MAC, AR5K_SREV_AR2415 },
125 { "5416", AR5K_VERSION_MAC, AR5K_SREV_AR5416 },
126 { "5418", AR5K_VERSION_MAC, AR5K_SREV_AR5418 },
127 { "2425", AR5K_VERSION_MAC, AR5K_SREV_AR2425 },
128 { "2417", AR5K_VERSION_MAC, AR5K_SREV_AR2417 },
129 { "xxxxx", AR5K_VERSION_MAC, AR5K_SREV_UNKNOWN },
130 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 },
131 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 },
132 { "5111A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111A },
133 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 },
134 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 },
135 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A },
136 { "5112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112B },
137 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 },
138 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A },
139 { "2112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112B },
140 { "2413", AR5K_VERSION_RAD, AR5K_SREV_RAD_2413 },
141 { "5413", AR5K_VERSION_RAD, AR5K_SREV_RAD_5413 },
142 { "2316", AR5K_VERSION_RAD, AR5K_SREV_RAD_2316 },
143 { "2317", AR5K_VERSION_RAD, AR5K_SREV_RAD_2317 },
144 { "5424", AR5K_VERSION_RAD, AR5K_SREV_RAD_5424 },
145 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 },
146 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN },
149 static const struct ieee80211_rate ath5k_rates[] = {
151 .hw_value = ATH5K_RATE_CODE_1M, },
153 .hw_value = ATH5K_RATE_CODE_2M,
154 .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE,
155 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
157 .hw_value = ATH5K_RATE_CODE_5_5M,
158 .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE,
159 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
161 .hw_value = ATH5K_RATE_CODE_11M,
162 .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE,
163 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
165 .hw_value = ATH5K_RATE_CODE_6M,
168 .hw_value = ATH5K_RATE_CODE_9M,
171 .hw_value = ATH5K_RATE_CODE_12M,
174 .hw_value = ATH5K_RATE_CODE_18M,
177 .hw_value = ATH5K_RATE_CODE_24M,
180 .hw_value = ATH5K_RATE_CODE_36M,
183 .hw_value = ATH5K_RATE_CODE_48M,
186 .hw_value = ATH5K_RATE_CODE_54M,
192 * Prototypes - PCI stack related functions
194 static int __devinit ath5k_pci_probe(struct pci_dev *pdev,
195 const struct pci_device_id *id);
196 static void __devexit ath5k_pci_remove(struct pci_dev *pdev);
198 static int ath5k_pci_suspend(struct device *dev);
199 static int ath5k_pci_resume(struct device *dev);
201 SIMPLE_DEV_PM_OPS(ath5k_pm_ops, ath5k_pci_suspend, ath5k_pci_resume);
202 #define ATH5K_PM_OPS (&ath5k_pm_ops)
204 #define ATH5K_PM_OPS NULL
205 #endif /* CONFIG_PM */
207 static struct pci_driver ath5k_pci_driver = {
208 .name = KBUILD_MODNAME,
209 .id_table = ath5k_pci_id_table,
210 .probe = ath5k_pci_probe,
211 .remove = __devexit_p(ath5k_pci_remove),
212 .driver.pm = ATH5K_PM_OPS,
218 * Prototypes - MAC 802.11 stack related functions
220 static int ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb);
221 static int ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
222 struct ath5k_txq *txq);
223 static int ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan);
224 static int ath5k_reset_wake(struct ath5k_softc *sc);
225 static int ath5k_start(struct ieee80211_hw *hw);
226 static void ath5k_stop(struct ieee80211_hw *hw);
227 static int ath5k_add_interface(struct ieee80211_hw *hw,
228 struct ieee80211_if_init_conf *conf);
229 static void ath5k_remove_interface(struct ieee80211_hw *hw,
230 struct ieee80211_if_init_conf *conf);
231 static int ath5k_config(struct ieee80211_hw *hw, u32 changed);
232 static u64 ath5k_prepare_multicast(struct ieee80211_hw *hw,
233 int mc_count, struct dev_addr_list *mc_list);
234 static void ath5k_configure_filter(struct ieee80211_hw *hw,
235 unsigned int changed_flags,
236 unsigned int *new_flags,
238 static int ath5k_set_key(struct ieee80211_hw *hw,
239 enum set_key_cmd cmd,
240 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
241 struct ieee80211_key_conf *key);
242 static int ath5k_get_stats(struct ieee80211_hw *hw,
243 struct ieee80211_low_level_stats *stats);
244 static int ath5k_get_tx_stats(struct ieee80211_hw *hw,
245 struct ieee80211_tx_queue_stats *stats);
246 static u64 ath5k_get_tsf(struct ieee80211_hw *hw);
247 static void ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf);
248 static void ath5k_reset_tsf(struct ieee80211_hw *hw);
249 static int ath5k_beacon_update(struct ieee80211_hw *hw,
250 struct ieee80211_vif *vif);
251 static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
252 struct ieee80211_vif *vif,
253 struct ieee80211_bss_conf *bss_conf,
255 static void ath5k_sw_scan_start(struct ieee80211_hw *hw);
256 static void ath5k_sw_scan_complete(struct ieee80211_hw *hw);
258 static const struct ieee80211_ops ath5k_hw_ops = {
260 .start = ath5k_start,
262 .add_interface = ath5k_add_interface,
263 .remove_interface = ath5k_remove_interface,
264 .config = ath5k_config,
265 .prepare_multicast = ath5k_prepare_multicast,
266 .configure_filter = ath5k_configure_filter,
267 .set_key = ath5k_set_key,
268 .get_stats = ath5k_get_stats,
270 .get_tx_stats = ath5k_get_tx_stats,
271 .get_tsf = ath5k_get_tsf,
272 .set_tsf = ath5k_set_tsf,
273 .reset_tsf = ath5k_reset_tsf,
274 .bss_info_changed = ath5k_bss_info_changed,
275 .sw_scan_start = ath5k_sw_scan_start,
276 .sw_scan_complete = ath5k_sw_scan_complete,
280 * Prototypes - Internal functions
283 static int ath5k_attach(struct pci_dev *pdev,
284 struct ieee80211_hw *hw);
285 static void ath5k_detach(struct pci_dev *pdev,
286 struct ieee80211_hw *hw);
287 /* Channel/mode setup */
288 static inline short ath5k_ieee2mhz(short chan);
289 static unsigned int ath5k_copy_channels(struct ath5k_hw *ah,
290 struct ieee80211_channel *channels,
293 static int ath5k_setup_bands(struct ieee80211_hw *hw);
294 static int ath5k_chan_set(struct ath5k_softc *sc,
295 struct ieee80211_channel *chan);
296 static void ath5k_setcurmode(struct ath5k_softc *sc,
298 static void ath5k_mode_setup(struct ath5k_softc *sc);
300 /* Descriptor setup */
301 static int ath5k_desc_alloc(struct ath5k_softc *sc,
302 struct pci_dev *pdev);
303 static void ath5k_desc_free(struct ath5k_softc *sc,
304 struct pci_dev *pdev);
306 static int ath5k_rxbuf_setup(struct ath5k_softc *sc,
307 struct ath5k_buf *bf);
308 static int ath5k_txbuf_setup(struct ath5k_softc *sc,
309 struct ath5k_buf *bf,
310 struct ath5k_txq *txq);
311 static inline void ath5k_txbuf_free(struct ath5k_softc *sc,
312 struct ath5k_buf *bf)
317 pci_unmap_single(sc->pdev, bf->skbaddr, bf->skb->len,
319 dev_kfree_skb_any(bf->skb);
323 static inline void ath5k_rxbuf_free(struct ath5k_softc *sc,
324 struct ath5k_buf *bf)
326 struct ath5k_hw *ah = sc->ah;
327 struct ath_common *common = ath5k_hw_common(ah);
332 pci_unmap_single(sc->pdev, bf->skbaddr, common->rx_bufsize,
334 dev_kfree_skb_any(bf->skb);
340 static struct ath5k_txq *ath5k_txq_setup(struct ath5k_softc *sc,
341 int qtype, int subtype);
342 static int ath5k_beaconq_setup(struct ath5k_hw *ah);
343 static int ath5k_beaconq_config(struct ath5k_softc *sc);
344 static void ath5k_txq_drainq(struct ath5k_softc *sc,
345 struct ath5k_txq *txq);
346 static void ath5k_txq_cleanup(struct ath5k_softc *sc);
347 static void ath5k_txq_release(struct ath5k_softc *sc);
349 static int ath5k_rx_start(struct ath5k_softc *sc);
350 static void ath5k_rx_stop(struct ath5k_softc *sc);
351 static unsigned int ath5k_rx_decrypted(struct ath5k_softc *sc,
352 struct ath5k_desc *ds,
354 struct ath5k_rx_status *rs);
355 static void ath5k_tasklet_rx(unsigned long data);
357 static void ath5k_tx_processq(struct ath5k_softc *sc,
358 struct ath5k_txq *txq);
359 static void ath5k_tasklet_tx(unsigned long data);
360 /* Beacon handling */
361 static int ath5k_beacon_setup(struct ath5k_softc *sc,
362 struct ath5k_buf *bf);
363 static void ath5k_beacon_send(struct ath5k_softc *sc);
364 static void ath5k_beacon_config(struct ath5k_softc *sc);
365 static void ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf);
366 static void ath5k_tasklet_beacon(unsigned long data);
368 static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
370 u64 tsf = ath5k_hw_get_tsf64(ah);
372 if ((tsf & 0x7fff) < rstamp)
375 return (tsf & ~0x7fff) | rstamp;
378 /* Interrupt handling */
379 static int ath5k_init(struct ath5k_softc *sc);
380 static int ath5k_stop_locked(struct ath5k_softc *sc);
381 static int ath5k_stop_hw(struct ath5k_softc *sc);
382 static irqreturn_t ath5k_intr(int irq, void *dev_id);
383 static void ath5k_tasklet_reset(unsigned long data);
385 static void ath5k_tasklet_calibrate(unsigned long data);
388 * Module init/exit functions
397 ret = pci_register_driver(&ath5k_pci_driver);
399 printk(KERN_ERR "ath5k_pci: can't register pci driver\n");
409 pci_unregister_driver(&ath5k_pci_driver);
411 ath5k_debug_finish();
414 module_init(init_ath5k_pci);
415 module_exit(exit_ath5k_pci);
418 /********************\
419 * PCI Initialization *
420 \********************/
423 ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
425 const char *name = "xxxxx";
428 for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
429 if (srev_names[i].sr_type != type)
432 if ((val & 0xf0) == srev_names[i].sr_val)
433 name = srev_names[i].sr_name;
435 if ((val & 0xff) == srev_names[i].sr_val) {
436 name = srev_names[i].sr_name;
443 static unsigned int ath5k_ioread32(void *hw_priv, u32 reg_offset)
445 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
446 return ath5k_hw_reg_read(ah, reg_offset);
449 static void ath5k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
451 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
452 ath5k_hw_reg_write(ah, val, reg_offset);
455 static const struct ath_ops ath5k_common_ops = {
456 .read = ath5k_ioread32,
457 .write = ath5k_iowrite32,
461 ath5k_pci_probe(struct pci_dev *pdev,
462 const struct pci_device_id *id)
465 struct ath5k_softc *sc;
466 struct ath_common *common;
467 struct ieee80211_hw *hw;
471 ret = pci_enable_device(pdev);
473 dev_err(&pdev->dev, "can't enable device\n");
477 /* XXX 32-bit addressing only */
478 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
480 dev_err(&pdev->dev, "32-bit DMA not available\n");
485 * Cache line size is used to size and align various
486 * structures used to communicate with the hardware.
488 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
491 * Linux 2.4.18 (at least) writes the cache line size
492 * register as a 16-bit wide register which is wrong.
493 * We must have this setup properly for rx buffer
494 * DMA to work so force a reasonable value here if it
497 csz = L1_CACHE_BYTES >> 2;
498 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
501 * The default setting of latency timer yields poor results,
502 * set it to the value used by other systems. It may be worth
503 * tweaking this setting more.
505 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
507 /* Enable bus mastering */
508 pci_set_master(pdev);
511 * Disable the RETRY_TIMEOUT register (0x41) to keep
512 * PCI Tx retries from interfering with C3 CPU state.
514 pci_write_config_byte(pdev, 0x41, 0);
516 ret = pci_request_region(pdev, 0, "ath5k");
518 dev_err(&pdev->dev, "cannot reserve PCI memory region\n");
522 mem = pci_iomap(pdev, 0, 0);
524 dev_err(&pdev->dev, "cannot remap PCI memory region\n") ;
530 * Allocate hw (mac80211 main struct)
531 * and hw->priv (driver private data)
533 hw = ieee80211_alloc_hw(sizeof(*sc), &ath5k_hw_ops);
535 dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n");
540 dev_info(&pdev->dev, "registered as '%s'\n", wiphy_name(hw->wiphy));
542 /* Initialize driver private data */
543 SET_IEEE80211_DEV(hw, &pdev->dev);
544 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
545 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
546 IEEE80211_HW_SIGNAL_DBM |
547 IEEE80211_HW_NOISE_DBM;
549 hw->wiphy->interface_modes =
550 BIT(NL80211_IFTYPE_AP) |
551 BIT(NL80211_IFTYPE_STATION) |
552 BIT(NL80211_IFTYPE_ADHOC) |
553 BIT(NL80211_IFTYPE_MESH_POINT);
555 hw->extra_tx_headroom = 2;
556 hw->channel_change_time = 5000;
561 ath5k_debug_init_device(sc);
564 * Mark the device as detached to avoid processing
565 * interrupts until setup is complete.
567 __set_bit(ATH_STAT_INVALID, sc->status);
569 sc->iobase = mem; /* So we can unmap it on detach */
570 sc->opmode = NL80211_IFTYPE_STATION;
572 mutex_init(&sc->lock);
573 spin_lock_init(&sc->rxbuflock);
574 spin_lock_init(&sc->txbuflock);
575 spin_lock_init(&sc->block);
577 /* Set private data */
578 pci_set_drvdata(pdev, hw);
580 /* Setup interrupt handler */
581 ret = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
583 ATH5K_ERR(sc, "request_irq failed\n");
587 /*If we passed the test malloc a ath5k_hw struct*/
588 sc->ah = kzalloc(sizeof(struct ath5k_hw), GFP_KERNEL);
591 ATH5K_ERR(sc, "out of memory\n");
596 sc->ah->ah_iobase = sc->iobase;
597 common = ath5k_hw_common(sc->ah);
598 common->ops = &ath5k_common_ops;
601 common->cachelsz = csz << 2; /* convert to bytes */
603 /* Initialize device */
604 ret = ath5k_hw_attach(sc);
609 /* set up multi-rate retry capabilities */
610 if (sc->ah->ah_version == AR5K_AR5212) {
612 hw->max_rate_tries = 11;
615 /* Finish private driver data initialization */
616 ret = ath5k_attach(pdev, hw);
620 ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
621 ath5k_chip_name(AR5K_VERSION_MAC, sc->ah->ah_mac_srev),
623 sc->ah->ah_phy_revision);
625 if (!sc->ah->ah_single_chip) {
626 /* Single chip radio (!RF5111) */
627 if (sc->ah->ah_radio_5ghz_revision &&
628 !sc->ah->ah_radio_2ghz_revision) {
629 /* No 5GHz support -> report 2GHz radio */
630 if (!test_bit(AR5K_MODE_11A,
631 sc->ah->ah_capabilities.cap_mode)) {
632 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
633 ath5k_chip_name(AR5K_VERSION_RAD,
634 sc->ah->ah_radio_5ghz_revision),
635 sc->ah->ah_radio_5ghz_revision);
636 /* No 2GHz support (5110 and some
637 * 5Ghz only cards) -> report 5Ghz radio */
638 } else if (!test_bit(AR5K_MODE_11B,
639 sc->ah->ah_capabilities.cap_mode)) {
640 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
641 ath5k_chip_name(AR5K_VERSION_RAD,
642 sc->ah->ah_radio_5ghz_revision),
643 sc->ah->ah_radio_5ghz_revision);
644 /* Multiband radio */
646 ATH5K_INFO(sc, "RF%s multiband radio found"
648 ath5k_chip_name(AR5K_VERSION_RAD,
649 sc->ah->ah_radio_5ghz_revision),
650 sc->ah->ah_radio_5ghz_revision);
653 /* Multi chip radio (RF5111 - RF2111) ->
654 * report both 2GHz/5GHz radios */
655 else if (sc->ah->ah_radio_5ghz_revision &&
656 sc->ah->ah_radio_2ghz_revision){
657 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
658 ath5k_chip_name(AR5K_VERSION_RAD,
659 sc->ah->ah_radio_5ghz_revision),
660 sc->ah->ah_radio_5ghz_revision);
661 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
662 ath5k_chip_name(AR5K_VERSION_RAD,
663 sc->ah->ah_radio_2ghz_revision),
664 sc->ah->ah_radio_2ghz_revision);
669 /* ready to process interrupts */
670 __clear_bit(ATH_STAT_INVALID, sc->status);
674 ath5k_hw_detach(sc->ah);
676 free_irq(pdev->irq, sc);
680 ieee80211_free_hw(hw);
682 pci_iounmap(pdev, mem);
684 pci_release_region(pdev, 0);
686 pci_disable_device(pdev);
691 static void __devexit
692 ath5k_pci_remove(struct pci_dev *pdev)
694 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
695 struct ath5k_softc *sc = hw->priv;
697 ath5k_debug_finish_device(sc);
698 ath5k_detach(pdev, hw);
699 ath5k_hw_detach(sc->ah);
701 free_irq(pdev->irq, sc);
702 pci_iounmap(pdev, sc->iobase);
703 pci_release_region(pdev, 0);
704 pci_disable_device(pdev);
705 ieee80211_free_hw(hw);
709 static int ath5k_pci_suspend(struct device *dev)
711 struct ieee80211_hw *hw = pci_get_drvdata(to_pci_dev(dev));
712 struct ath5k_softc *sc = hw->priv;
718 static int ath5k_pci_resume(struct device *dev)
720 struct pci_dev *pdev = to_pci_dev(dev);
721 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
722 struct ath5k_softc *sc = hw->priv;
725 * Suspend/Resume resets the PCI configuration space, so we have to
726 * re-disable the RETRY_TIMEOUT register (0x41) to keep
727 * PCI Tx retries from interfering with C3 CPU state
729 pci_write_config_byte(pdev, 0x41, 0);
731 ath5k_led_enable(sc);
734 #endif /* CONFIG_PM */
737 /***********************\
738 * Driver Initialization *
739 \***********************/
741 static int ath5k_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request)
743 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
744 struct ath5k_softc *sc = hw->priv;
745 struct ath_regulatory *regulatory = ath5k_hw_regulatory(sc->ah);
747 return ath_reg_notifier_apply(wiphy, request, regulatory);
751 ath5k_attach(struct pci_dev *pdev, struct ieee80211_hw *hw)
753 struct ath5k_softc *sc = hw->priv;
754 struct ath5k_hw *ah = sc->ah;
755 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah);
756 u8 mac[ETH_ALEN] = {};
759 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "devid 0x%x\n", pdev->device);
762 * Check if the MAC has multi-rate retry support.
763 * We do this by trying to setup a fake extended
764 * descriptor. MAC's that don't have support will
765 * return false w/o doing anything. MAC's that do
766 * support it will return true w/o doing anything.
768 ret = ah->ah_setup_mrr_tx_desc(ah, NULL, 0, 0, 0, 0, 0, 0);
772 __set_bit(ATH_STAT_MRRETRY, sc->status);
775 * Collect the channel list. The 802.11 layer
776 * is resposible for filtering this list based
777 * on settings like the phy mode and regulatory
778 * domain restrictions.
780 ret = ath5k_setup_bands(hw);
782 ATH5K_ERR(sc, "can't get channels\n");
786 /* NB: setup here so ath5k_rate_update is happy */
787 if (test_bit(AR5K_MODE_11A, ah->ah_modes))
788 ath5k_setcurmode(sc, AR5K_MODE_11A);
790 ath5k_setcurmode(sc, AR5K_MODE_11B);
793 * Allocate tx+rx descriptors and populate the lists.
795 ret = ath5k_desc_alloc(sc, pdev);
797 ATH5K_ERR(sc, "can't allocate descriptors\n");
802 * Allocate hardware transmit queues: one queue for
803 * beacon frames and one data queue for each QoS
804 * priority. Note that hw functions handle reseting
805 * these queues at the needed time.
807 ret = ath5k_beaconq_setup(ah);
809 ATH5K_ERR(sc, "can't setup a beacon xmit queue\n");
813 sc->cabq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_CAB, 0);
814 if (IS_ERR(sc->cabq)) {
815 ATH5K_ERR(sc, "can't setup cab queue\n");
816 ret = PTR_ERR(sc->cabq);
820 sc->txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
821 if (IS_ERR(sc->txq)) {
822 ATH5K_ERR(sc, "can't setup xmit queue\n");
823 ret = PTR_ERR(sc->txq);
827 tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc);
828 tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc);
829 tasklet_init(&sc->restq, ath5k_tasklet_reset, (unsigned long)sc);
830 tasklet_init(&sc->calib, ath5k_tasklet_calibrate, (unsigned long)sc);
831 tasklet_init(&sc->beacontq, ath5k_tasklet_beacon, (unsigned long)sc);
833 ret = ath5k_eeprom_read_mac(ah, mac);
835 ATH5K_ERR(sc, "unable to read address from EEPROM: 0x%04x\n",
840 SET_IEEE80211_PERM_ADDR(hw, mac);
841 /* All MAC address bits matter for ACKs */
842 memcpy(sc->bssidmask, ath_bcast_mac, ETH_ALEN);
843 ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask);
845 regulatory->current_rd = ah->ah_capabilities.cap_eeprom.ee_regdomain;
846 ret = ath_regd_init(regulatory, hw->wiphy, ath5k_reg_notifier);
848 ATH5K_ERR(sc, "can't initialize regulatory system\n");
852 ret = ieee80211_register_hw(hw);
854 ATH5K_ERR(sc, "can't register ieee80211 hw\n");
858 if (!ath_is_world_regd(regulatory))
859 regulatory_hint(hw->wiphy, regulatory->alpha2);
865 ath5k_txq_release(sc);
867 ath5k_hw_release_tx_queue(ah, sc->bhalq);
869 ath5k_desc_free(sc, pdev);
875 ath5k_detach(struct pci_dev *pdev, struct ieee80211_hw *hw)
877 struct ath5k_softc *sc = hw->priv;
880 * NB: the order of these is important:
881 * o call the 802.11 layer before detaching ath5k_hw to
882 * insure callbacks into the driver to delete global
883 * key cache entries can be handled
884 * o reclaim the tx queue data structures after calling
885 * the 802.11 layer as we'll get called back to reclaim
886 * node state and potentially want to use them
887 * o to cleanup the tx queues the hal is called, so detach
889 * XXX: ??? detach ath5k_hw ???
890 * Other than that, it's straightforward...
892 ieee80211_unregister_hw(hw);
893 ath5k_desc_free(sc, pdev);
894 ath5k_txq_release(sc);
895 ath5k_hw_release_tx_queue(sc->ah, sc->bhalq);
896 ath5k_unregister_leds(sc);
899 * NB: can't reclaim these until after ieee80211_ifdetach
900 * returns because we'll get called back to reclaim node
901 * state and potentially want to use them.
908 /********************\
909 * Channel/mode setup *
910 \********************/
913 * Convert IEEE channel number to MHz frequency.
916 ath5k_ieee2mhz(short chan)
918 if (chan <= 14 || chan >= 27)
919 return ieee80211chan2mhz(chan);
921 return 2212 + chan * 20;
925 * Returns true for the channel numbers used without all_channels modparam.
927 static bool ath5k_is_standard_channel(short chan)
929 return ((chan <= 14) ||
931 ((chan & 3) == 0 && chan >= 36 && chan <= 64) ||
933 ((chan & 3) == 0 && chan >= 100 && chan <= 140) ||
935 ((chan & 3) == 1 && chan >= 149 && chan <= 165));
939 ath5k_copy_channels(struct ath5k_hw *ah,
940 struct ieee80211_channel *channels,
944 unsigned int i, count, size, chfreq, freq, ch;
946 if (!test_bit(mode, ah->ah_modes))
951 case AR5K_MODE_11A_TURBO:
952 /* 1..220, but 2GHz frequencies are filtered by check_channel */
954 chfreq = CHANNEL_5GHZ;
958 case AR5K_MODE_11G_TURBO:
960 chfreq = CHANNEL_2GHZ;
963 ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n");
967 for (i = 0, count = 0; i < size && max > 0; i++) {
969 freq = ath5k_ieee2mhz(ch);
971 /* Check if channel is supported by the chipset */
972 if (!ath5k_channel_ok(ah, freq, chfreq))
975 if (!modparam_all_channels && !ath5k_is_standard_channel(ch))
978 /* Write channel info and increment counter */
979 channels[count].center_freq = freq;
980 channels[count].band = (chfreq == CHANNEL_2GHZ) ?
981 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
985 channels[count].hw_value = chfreq | CHANNEL_OFDM;
987 case AR5K_MODE_11A_TURBO:
988 case AR5K_MODE_11G_TURBO:
989 channels[count].hw_value = chfreq |
990 CHANNEL_OFDM | CHANNEL_TURBO;
993 channels[count].hw_value = CHANNEL_B;
1004 ath5k_setup_rate_idx(struct ath5k_softc *sc, struct ieee80211_supported_band *b)
1008 for (i = 0; i < AR5K_MAX_RATES; i++)
1009 sc->rate_idx[b->band][i] = -1;
1011 for (i = 0; i < b->n_bitrates; i++) {
1012 sc->rate_idx[b->band][b->bitrates[i].hw_value] = i;
1013 if (b->bitrates[i].hw_value_short)
1014 sc->rate_idx[b->band][b->bitrates[i].hw_value_short] = i;
1019 ath5k_setup_bands(struct ieee80211_hw *hw)
1021 struct ath5k_softc *sc = hw->priv;
1022 struct ath5k_hw *ah = sc->ah;
1023 struct ieee80211_supported_band *sband;
1024 int max_c, count_c = 0;
1027 BUILD_BUG_ON(ARRAY_SIZE(sc->sbands) < IEEE80211_NUM_BANDS);
1028 max_c = ARRAY_SIZE(sc->channels);
1031 sband = &sc->sbands[IEEE80211_BAND_2GHZ];
1032 sband->band = IEEE80211_BAND_2GHZ;
1033 sband->bitrates = &sc->rates[IEEE80211_BAND_2GHZ][0];
1035 if (test_bit(AR5K_MODE_11G, sc->ah->ah_capabilities.cap_mode)) {
1037 memcpy(sband->bitrates, &ath5k_rates[0],
1038 sizeof(struct ieee80211_rate) * 12);
1039 sband->n_bitrates = 12;
1041 sband->channels = sc->channels;
1042 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
1043 AR5K_MODE_11G, max_c);
1045 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
1046 count_c = sband->n_channels;
1048 } else if (test_bit(AR5K_MODE_11B, sc->ah->ah_capabilities.cap_mode)) {
1050 memcpy(sband->bitrates, &ath5k_rates[0],
1051 sizeof(struct ieee80211_rate) * 4);
1052 sband->n_bitrates = 4;
1054 /* 5211 only supports B rates and uses 4bit rate codes
1055 * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B)
1058 if (ah->ah_version == AR5K_AR5211) {
1059 for (i = 0; i < 4; i++) {
1060 sband->bitrates[i].hw_value =
1061 sband->bitrates[i].hw_value & 0xF;
1062 sband->bitrates[i].hw_value_short =
1063 sband->bitrates[i].hw_value_short & 0xF;
1067 sband->channels = sc->channels;
1068 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
1069 AR5K_MODE_11B, max_c);
1071 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
1072 count_c = sband->n_channels;
1075 ath5k_setup_rate_idx(sc, sband);
1077 /* 5GHz band, A mode */
1078 if (test_bit(AR5K_MODE_11A, sc->ah->ah_capabilities.cap_mode)) {
1079 sband = &sc->sbands[IEEE80211_BAND_5GHZ];
1080 sband->band = IEEE80211_BAND_5GHZ;
1081 sband->bitrates = &sc->rates[IEEE80211_BAND_5GHZ][0];
1083 memcpy(sband->bitrates, &ath5k_rates[4],
1084 sizeof(struct ieee80211_rate) * 8);
1085 sband->n_bitrates = 8;
1087 sband->channels = &sc->channels[count_c];
1088 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
1089 AR5K_MODE_11A, max_c);
1091 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
1093 ath5k_setup_rate_idx(sc, sband);
1095 ath5k_debug_dump_bands(sc);
1101 * Set/change channels. We always reset the chip.
1102 * To accomplish this we must first cleanup any pending DMA,
1103 * then restart stuff after a la ath5k_init.
1105 * Called with sc->lock.
1108 ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)
1110 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "(%u MHz) -> (%u MHz)\n",
1111 sc->curchan->center_freq, chan->center_freq);
1114 * To switch channels clear any pending DMA operations;
1115 * wait long enough for the RX fifo to drain, reset the
1116 * hardware at the new frequency, and then re-enable
1117 * the relevant bits of the h/w.
1119 return ath5k_reset(sc, chan);
1123 ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode)
1127 if (mode == AR5K_MODE_11A) {
1128 sc->curband = &sc->sbands[IEEE80211_BAND_5GHZ];
1130 sc->curband = &sc->sbands[IEEE80211_BAND_2GHZ];
1135 ath5k_mode_setup(struct ath5k_softc *sc)
1137 struct ath5k_hw *ah = sc->ah;
1140 ah->ah_op_mode = sc->opmode;
1142 /* configure rx filter */
1143 rfilt = sc->filter_flags;
1144 ath5k_hw_set_rx_filter(ah, rfilt);
1146 if (ath5k_hw_hasbssidmask(ah))
1147 ath5k_hw_set_bssid_mask(ah, sc->bssidmask);
1149 /* configure operational mode */
1150 ath5k_hw_set_opmode(ah);
1152 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
1156 ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix)
1160 /* return base rate on errors */
1161 if (WARN(hw_rix < 0 || hw_rix >= AR5K_MAX_RATES,
1162 "hw_rix out of bounds: %x\n", hw_rix))
1165 rix = sc->rate_idx[sc->curband->band][hw_rix];
1166 if (WARN(rix < 0, "invalid hw_rix: %x\n", hw_rix))
1177 struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_softc *sc, dma_addr_t *skb_addr)
1179 struct ath_common *common = ath5k_hw_common(sc->ah);
1180 struct sk_buff *skb;
1183 * Allocate buffer with headroom_needed space for the
1184 * fake physical layer header at the start.
1186 skb = ath_rxbuf_alloc(common,
1191 ATH5K_ERR(sc, "can't alloc skbuff of size %u\n",
1192 common->rx_bufsize);
1196 *skb_addr = pci_map_single(sc->pdev,
1197 skb->data, common->rx_bufsize,
1198 PCI_DMA_FROMDEVICE);
1199 if (unlikely(pci_dma_mapping_error(sc->pdev, *skb_addr))) {
1200 ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__);
1208 ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1210 struct ath5k_hw *ah = sc->ah;
1211 struct sk_buff *skb = bf->skb;
1212 struct ath5k_desc *ds;
1215 skb = ath5k_rx_skb_alloc(sc, &bf->skbaddr);
1222 * Setup descriptors. For receive we always terminate
1223 * the descriptor list with a self-linked entry so we'll
1224 * not get overrun under high load (as can happen with a
1225 * 5212 when ANI processing enables PHY error frames).
1227 * To insure the last descriptor is self-linked we create
1228 * each descriptor as self-linked and add it to the end. As
1229 * each additional descriptor is added the previous self-linked
1230 * entry is ``fixed'' naturally. This should be safe even
1231 * if DMA is happening. When processing RX interrupts we
1232 * never remove/process the last, self-linked, entry on the
1233 * descriptor list. This insures the hardware always has
1234 * someplace to write a new frame.
1237 ds->ds_link = bf->daddr; /* link to self */
1238 ds->ds_data = bf->skbaddr;
1239 ah->ah_setup_rx_desc(ah, ds,
1240 skb_tailroom(skb), /* buffer size */
1243 if (sc->rxlink != NULL)
1244 *sc->rxlink = bf->daddr;
1245 sc->rxlink = &ds->ds_link;
1250 ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf,
1251 struct ath5k_txq *txq)
1253 struct ath5k_hw *ah = sc->ah;
1254 struct ath5k_desc *ds = bf->desc;
1255 struct sk_buff *skb = bf->skb;
1256 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1257 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
1258 struct ieee80211_rate *rate;
1259 unsigned int mrr_rate[3], mrr_tries[3];
1266 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
1268 /* XXX endianness */
1269 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1272 rate = ieee80211_get_tx_rate(sc->hw, info);
1274 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
1275 flags |= AR5K_TXDESC_NOACK;
1277 rc_flags = info->control.rates[0].flags;
1278 hw_rate = (rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) ?
1279 rate->hw_value_short : rate->hw_value;
1283 /* FIXME: If we are in g mode and rate is a CCK rate
1284 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
1285 * from tx power (value is in dB units already) */
1286 if (info->control.hw_key) {
1287 keyidx = info->control.hw_key->hw_key_idx;
1288 pktlen += info->control.hw_key->icv_len;
1290 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
1291 flags |= AR5K_TXDESC_RTSENA;
1292 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
1293 duration = le16_to_cpu(ieee80211_rts_duration(sc->hw,
1294 sc->vif, pktlen, info));
1296 if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
1297 flags |= AR5K_TXDESC_CTSENA;
1298 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
1299 duration = le16_to_cpu(ieee80211_ctstoself_duration(sc->hw,
1300 sc->vif, pktlen, info));
1302 ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
1303 ieee80211_get_hdrlen_from_skb(skb), AR5K_PKT_TYPE_NORMAL,
1304 (sc->power_level * 2),
1306 info->control.rates[0].count, keyidx, ah->ah_tx_ant, flags,
1307 cts_rate, duration);
1311 memset(mrr_rate, 0, sizeof(mrr_rate));
1312 memset(mrr_tries, 0, sizeof(mrr_tries));
1313 for (i = 0; i < 3; i++) {
1314 rate = ieee80211_get_alt_retry_rate(sc->hw, info, i);
1318 mrr_rate[i] = rate->hw_value;
1319 mrr_tries[i] = info->control.rates[i + 1].count;
1322 ah->ah_setup_mrr_tx_desc(ah, ds,
1323 mrr_rate[0], mrr_tries[0],
1324 mrr_rate[1], mrr_tries[1],
1325 mrr_rate[2], mrr_tries[2]);
1328 ds->ds_data = bf->skbaddr;
1330 spin_lock_bh(&txq->lock);
1331 list_add_tail(&bf->list, &txq->q);
1332 sc->tx_stats[txq->qnum].len++;
1333 if (txq->link == NULL) /* is this first packet? */
1334 ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr);
1335 else /* no, so only link it */
1336 *txq->link = bf->daddr;
1338 txq->link = &ds->ds_link;
1339 ath5k_hw_start_tx_dma(ah, txq->qnum);
1341 spin_unlock_bh(&txq->lock);
1345 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1349 /*******************\
1350 * Descriptors setup *
1351 \*******************/
1354 ath5k_desc_alloc(struct ath5k_softc *sc, struct pci_dev *pdev)
1356 struct ath5k_desc *ds;
1357 struct ath5k_buf *bf;
1362 /* allocate descriptors */
1363 sc->desc_len = sizeof(struct ath5k_desc) *
1364 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
1365 sc->desc = pci_alloc_consistent(pdev, sc->desc_len, &sc->desc_daddr);
1366 if (sc->desc == NULL) {
1367 ATH5K_ERR(sc, "can't allocate descriptors\n");
1372 da = sc->desc_daddr;
1373 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
1374 ds, sc->desc_len, (unsigned long long)sc->desc_daddr);
1376 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
1377 sizeof(struct ath5k_buf), GFP_KERNEL);
1379 ATH5K_ERR(sc, "can't allocate bufptr\n");
1385 INIT_LIST_HEAD(&sc->rxbuf);
1386 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
1389 list_add_tail(&bf->list, &sc->rxbuf);
1392 INIT_LIST_HEAD(&sc->txbuf);
1393 sc->txbuf_len = ATH_TXBUF;
1394 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++,
1395 da += sizeof(*ds)) {
1398 list_add_tail(&bf->list, &sc->txbuf);
1408 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1415 ath5k_desc_free(struct ath5k_softc *sc, struct pci_dev *pdev)
1417 struct ath5k_buf *bf;
1419 ath5k_txbuf_free(sc, sc->bbuf);
1420 list_for_each_entry(bf, &sc->txbuf, list)
1421 ath5k_txbuf_free(sc, bf);
1422 list_for_each_entry(bf, &sc->rxbuf, list)
1423 ath5k_rxbuf_free(sc, bf);
1425 /* Free memory associated with all descriptors */
1426 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1440 static struct ath5k_txq *
1441 ath5k_txq_setup(struct ath5k_softc *sc,
1442 int qtype, int subtype)
1444 struct ath5k_hw *ah = sc->ah;
1445 struct ath5k_txq *txq;
1446 struct ath5k_txq_info qi = {
1447 .tqi_subtype = subtype,
1448 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1449 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1450 .tqi_cw_max = AR5K_TXQ_USEDEFAULT
1455 * Enable interrupts only for EOL and DESC conditions.
1456 * We mark tx descriptors to receive a DESC interrupt
1457 * when a tx queue gets deep; otherwise waiting for the
1458 * EOL to reap descriptors. Note that this is done to
1459 * reduce interrupt load and this only defers reaping
1460 * descriptors, never transmitting frames. Aside from
1461 * reducing interrupts this also permits more concurrency.
1462 * The only potential downside is if the tx queue backs
1463 * up in which case the top half of the kernel may backup
1464 * due to a lack of tx descriptors.
1466 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
1467 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
1468 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
1471 * NB: don't print a message, this happens
1472 * normally on parts with too few tx queues
1474 return ERR_PTR(qnum);
1476 if (qnum >= ARRAY_SIZE(sc->txqs)) {
1477 ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n",
1478 qnum, ARRAY_SIZE(sc->txqs));
1479 ath5k_hw_release_tx_queue(ah, qnum);
1480 return ERR_PTR(-EINVAL);
1482 txq = &sc->txqs[qnum];
1486 INIT_LIST_HEAD(&txq->q);
1487 spin_lock_init(&txq->lock);
1490 return &sc->txqs[qnum];
1494 ath5k_beaconq_setup(struct ath5k_hw *ah)
1496 struct ath5k_txq_info qi = {
1497 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1498 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1499 .tqi_cw_max = AR5K_TXQ_USEDEFAULT,
1500 /* NB: for dynamic turbo, don't enable any other interrupts */
1501 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
1504 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
1508 ath5k_beaconq_config(struct ath5k_softc *sc)
1510 struct ath5k_hw *ah = sc->ah;
1511 struct ath5k_txq_info qi;
1514 ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi);
1517 if (sc->opmode == NL80211_IFTYPE_AP ||
1518 sc->opmode == NL80211_IFTYPE_MESH_POINT) {
1520 * Always burst out beacon and CAB traffic
1521 * (aifs = cwmin = cwmax = 0)
1526 } else if (sc->opmode == NL80211_IFTYPE_ADHOC) {
1528 * Adhoc mode; backoff between 0 and (2 * cw_min).
1532 qi.tqi_cw_max = 2 * ah->ah_cw_min;
1535 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1536 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1537 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
1539 ret = ath5k_hw_set_tx_queueprops(ah, sc->bhalq, &qi);
1541 ATH5K_ERR(sc, "%s: unable to update parameters for beacon "
1542 "hardware queue!\n", __func__);
1546 return ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */;
1550 ath5k_txq_drainq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1552 struct ath5k_buf *bf, *bf0;
1555 * NB: this assumes output has been stopped and
1556 * we do not need to block ath5k_tx_tasklet
1558 spin_lock_bh(&txq->lock);
1559 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1560 ath5k_debug_printtxbuf(sc, bf);
1562 ath5k_txbuf_free(sc, bf);
1564 spin_lock_bh(&sc->txbuflock);
1565 sc->tx_stats[txq->qnum].len--;
1566 list_move_tail(&bf->list, &sc->txbuf);
1568 spin_unlock_bh(&sc->txbuflock);
1571 spin_unlock_bh(&txq->lock);
1575 * Drain the transmit queues and reclaim resources.
1578 ath5k_txq_cleanup(struct ath5k_softc *sc)
1580 struct ath5k_hw *ah = sc->ah;
1583 /* XXX return value */
1584 if (likely(!test_bit(ATH_STAT_INVALID, sc->status))) {
1585 /* don't touch the hardware if marked invalid */
1586 ath5k_hw_stop_tx_dma(ah, sc->bhalq);
1587 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "beacon queue %x\n",
1588 ath5k_hw_get_txdp(ah, sc->bhalq));
1589 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1590 if (sc->txqs[i].setup) {
1591 ath5k_hw_stop_tx_dma(ah, sc->txqs[i].qnum);
1592 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "txq [%u] %x, "
1595 ath5k_hw_get_txdp(ah,
1600 ieee80211_wake_queues(sc->hw); /* XXX move to callers */
1602 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1603 if (sc->txqs[i].setup)
1604 ath5k_txq_drainq(sc, &sc->txqs[i]);
1608 ath5k_txq_release(struct ath5k_softc *sc)
1610 struct ath5k_txq *txq = sc->txqs;
1613 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++)
1615 ath5k_hw_release_tx_queue(sc->ah, txq->qnum);
1628 * Enable the receive h/w following a reset.
1631 ath5k_rx_start(struct ath5k_softc *sc)
1633 struct ath5k_hw *ah = sc->ah;
1634 struct ath_common *common = ath5k_hw_common(ah);
1635 struct ath5k_buf *bf;
1638 common->rx_bufsize = roundup(IEEE80211_MAX_LEN, common->cachelsz);
1640 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rx_bufsize %u\n",
1641 common->cachelsz, common->rx_bufsize);
1643 spin_lock_bh(&sc->rxbuflock);
1645 list_for_each_entry(bf, &sc->rxbuf, list) {
1646 ret = ath5k_rxbuf_setup(sc, bf);
1648 spin_unlock_bh(&sc->rxbuflock);
1652 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1653 ath5k_hw_set_rxdp(ah, bf->daddr);
1654 spin_unlock_bh(&sc->rxbuflock);
1656 ath5k_hw_start_rx_dma(ah); /* enable recv descriptors */
1657 ath5k_mode_setup(sc); /* set filters, etc. */
1658 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */
1666 * Disable the receive h/w in preparation for a reset.
1669 ath5k_rx_stop(struct ath5k_softc *sc)
1671 struct ath5k_hw *ah = sc->ah;
1673 ath5k_hw_stop_rx_pcu(ah); /* disable PCU */
1674 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */
1675 ath5k_hw_stop_rx_dma(ah); /* disable DMA engine */
1677 ath5k_debug_printrxbuffs(sc, ah);
1679 sc->rxlink = NULL; /* just in case */
1683 ath5k_rx_decrypted(struct ath5k_softc *sc, struct ath5k_desc *ds,
1684 struct sk_buff *skb, struct ath5k_rx_status *rs)
1686 struct ath5k_hw *ah = sc->ah;
1687 struct ath_common *common = ath5k_hw_common(ah);
1688 struct ieee80211_hdr *hdr = (void *)skb->data;
1689 unsigned int keyix, hlen;
1691 if (!(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1692 rs->rs_keyix != AR5K_RXKEYIX_INVALID)
1693 return RX_FLAG_DECRYPTED;
1695 /* Apparently when a default key is used to decrypt the packet
1696 the hw does not set the index used to decrypt. In such cases
1697 get the index from the packet. */
1698 hlen = ieee80211_hdrlen(hdr->frame_control);
1699 if (ieee80211_has_protected(hdr->frame_control) &&
1700 !(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1701 skb->len >= hlen + 4) {
1702 keyix = skb->data[hlen + 3] >> 6;
1704 if (test_bit(keyix, common->keymap))
1705 return RX_FLAG_DECRYPTED;
1713 ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb,
1714 struct ieee80211_rx_status *rxs)
1716 struct ath_common *common = ath5k_hw_common(sc->ah);
1719 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1721 if (ieee80211_is_beacon(mgmt->frame_control) &&
1722 le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS &&
1723 memcmp(mgmt->bssid, common->curbssid, ETH_ALEN) == 0) {
1725 * Received an IBSS beacon with the same BSSID. Hardware *must*
1726 * have updated the local TSF. We have to work around various
1727 * hardware bugs, though...
1729 tsf = ath5k_hw_get_tsf64(sc->ah);
1730 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp);
1731 hw_tu = TSF_TO_TU(tsf);
1733 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1734 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
1735 (unsigned long long)bc_tstamp,
1736 (unsigned long long)rxs->mactime,
1737 (unsigned long long)(rxs->mactime - bc_tstamp),
1738 (unsigned long long)tsf);
1741 * Sometimes the HW will give us a wrong tstamp in the rx
1742 * status, causing the timestamp extension to go wrong.
1743 * (This seems to happen especially with beacon frames bigger
1744 * than 78 byte (incl. FCS))
1745 * But we know that the receive timestamp must be later than the
1746 * timestamp of the beacon since HW must have synced to that.
1748 * NOTE: here we assume mactime to be after the frame was
1749 * received, not like mac80211 which defines it at the start.
1751 if (bc_tstamp > rxs->mactime) {
1752 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1753 "fixing mactime from %llx to %llx\n",
1754 (unsigned long long)rxs->mactime,
1755 (unsigned long long)tsf);
1760 * Local TSF might have moved higher than our beacon timers,
1761 * in that case we have to update them to continue sending
1762 * beacons. This also takes care of synchronizing beacon sending
1763 * times with other stations.
1765 if (hw_tu >= sc->nexttbtt)
1766 ath5k_beacon_update_timers(sc, bc_tstamp);
1771 ath5k_tasklet_rx(unsigned long data)
1773 struct ieee80211_rx_status *rxs;
1774 struct ath5k_rx_status rs = {};
1775 struct sk_buff *skb, *next_skb;
1776 dma_addr_t next_skb_addr;
1777 struct ath5k_softc *sc = (void *)data;
1778 struct ath5k_hw *ah = sc->ah;
1779 struct ath_common *common = ath5k_hw_common(ah);
1780 struct ath5k_buf *bf;
1781 struct ath5k_desc *ds;
1787 spin_lock(&sc->rxbuflock);
1788 if (list_empty(&sc->rxbuf)) {
1789 ATH5K_WARN(sc, "empty rx buf pool\n");
1795 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1796 BUG_ON(bf->skb == NULL);
1800 /* bail if HW is still using self-linked descriptor */
1801 if (ath5k_hw_get_rxdp(sc->ah) == bf->daddr)
1804 ret = sc->ah->ah_proc_rx_desc(sc->ah, ds, &rs);
1805 if (unlikely(ret == -EINPROGRESS))
1807 else if (unlikely(ret)) {
1808 ATH5K_ERR(sc, "error in processing rx descriptor\n");
1809 spin_unlock(&sc->rxbuflock);
1813 if (unlikely(rs.rs_more)) {
1814 ATH5K_WARN(sc, "unsupported jumbo\n");
1818 if (unlikely(rs.rs_status)) {
1819 if (rs.rs_status & AR5K_RXERR_PHY)
1821 if (rs.rs_status & AR5K_RXERR_DECRYPT) {
1823 * Decrypt error. If the error occurred
1824 * because there was no hardware key, then
1825 * let the frame through so the upper layers
1826 * can process it. This is necessary for 5210
1827 * parts which have no way to setup a ``clear''
1830 * XXX do key cache faulting
1832 if (rs.rs_keyix == AR5K_RXKEYIX_INVALID &&
1833 !(rs.rs_status & AR5K_RXERR_CRC))
1836 if (rs.rs_status & AR5K_RXERR_MIC) {
1837 rx_flag |= RX_FLAG_MMIC_ERROR;
1841 /* let crypto-error packets fall through in MNTR */
1843 ~(AR5K_RXERR_DECRYPT|AR5K_RXERR_MIC)) ||
1844 sc->opmode != NL80211_IFTYPE_MONITOR)
1848 next_skb = ath5k_rx_skb_alloc(sc, &next_skb_addr);
1851 * If we can't replace bf->skb with a new skb under memory
1852 * pressure, just skip this packet
1857 pci_unmap_single(sc->pdev, bf->skbaddr, common->rx_bufsize,
1858 PCI_DMA_FROMDEVICE);
1859 skb_put(skb, rs.rs_datalen);
1861 /* The MAC header is padded to have 32-bit boundary if the
1862 * packet payload is non-zero. The general calculation for
1863 * padsize would take into account odd header lengths:
1864 * padsize = (4 - hdrlen % 4) % 4; However, since only
1865 * even-length headers are used, padding can only be 0 or 2
1866 * bytes and we can optimize this a bit. In addition, we must
1867 * not try to remove padding from short control frames that do
1868 * not have payload. */
1869 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1870 padsize = ath5k_pad_size(hdrlen);
1872 memmove(skb->data + padsize, skb->data, hdrlen);
1873 skb_pull(skb, padsize);
1875 rxs = IEEE80211_SKB_RXCB(skb);
1878 * always extend the mac timestamp, since this information is
1879 * also needed for proper IBSS merging.
1881 * XXX: it might be too late to do it here, since rs_tstamp is
1882 * 15bit only. that means TSF extension has to be done within
1883 * 32768usec (about 32ms). it might be necessary to move this to
1884 * the interrupt handler, like it is done in madwifi.
1886 * Unfortunately we don't know when the hardware takes the rx
1887 * timestamp (beginning of phy frame, data frame, end of rx?).
1888 * The only thing we know is that it is hardware specific...
1889 * On AR5213 it seems the rx timestamp is at the end of the
1890 * frame, but i'm not sure.
1892 * NOTE: mac80211 defines mactime at the beginning of the first
1893 * data symbol. Since we don't have any time references it's
1894 * impossible to comply to that. This affects IBSS merge only
1895 * right now, so it's not too bad...
1897 rxs->mactime = ath5k_extend_tsf(sc->ah, rs.rs_tstamp);
1898 rxs->flag = rx_flag | RX_FLAG_TSFT;
1900 rxs->freq = sc->curchan->center_freq;
1901 rxs->band = sc->curband->band;
1903 rxs->noise = sc->ah->ah_noise_floor;
1904 rxs->signal = rxs->noise + rs.rs_rssi;
1906 rxs->antenna = rs.rs_antenna;
1907 rxs->rate_idx = ath5k_hw_to_driver_rix(sc, rs.rs_rate);
1908 rxs->flag |= ath5k_rx_decrypted(sc, ds, skb, &rs);
1910 if (rxs->rate_idx >= 0 && rs.rs_rate ==
1911 sc->curband->bitrates[rxs->rate_idx].hw_value_short)
1912 rxs->flag |= RX_FLAG_SHORTPRE;
1914 ath5k_debug_dump_skb(sc, skb, "RX ", 0);
1916 /* check beacons in IBSS mode */
1917 if (sc->opmode == NL80211_IFTYPE_ADHOC)
1918 ath5k_check_ibss_tsf(sc, skb, rxs);
1920 ieee80211_rx(sc->hw, skb);
1923 bf->skbaddr = next_skb_addr;
1925 list_move_tail(&bf->list, &sc->rxbuf);
1926 } while (ath5k_rxbuf_setup(sc, bf) == 0);
1928 spin_unlock(&sc->rxbuflock);
1939 ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1941 struct ath5k_tx_status ts = {};
1942 struct ath5k_buf *bf, *bf0;
1943 struct ath5k_desc *ds;
1944 struct sk_buff *skb;
1945 struct ieee80211_tx_info *info;
1948 spin_lock(&txq->lock);
1949 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1952 ret = sc->ah->ah_proc_tx_desc(sc->ah, ds, &ts);
1953 if (unlikely(ret == -EINPROGRESS))
1955 else if (unlikely(ret)) {
1956 ATH5K_ERR(sc, "error %d while processing queue %u\n",
1962 info = IEEE80211_SKB_CB(skb);
1965 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len,
1968 ieee80211_tx_info_clear_status(info);
1969 for (i = 0; i < 4; i++) {
1970 struct ieee80211_tx_rate *r =
1971 &info->status.rates[i];
1973 if (ts.ts_rate[i]) {
1974 r->idx = ath5k_hw_to_driver_rix(sc, ts.ts_rate[i]);
1975 r->count = ts.ts_retry[i];
1982 /* count the successful attempt as well */
1983 info->status.rates[ts.ts_final_idx].count++;
1985 if (unlikely(ts.ts_status)) {
1986 sc->ll_stats.dot11ACKFailureCount++;
1987 if (ts.ts_status & AR5K_TXERR_FILT)
1988 info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
1990 info->flags |= IEEE80211_TX_STAT_ACK;
1991 info->status.ack_signal = ts.ts_rssi;
1994 ieee80211_tx_status(sc->hw, skb);
1995 sc->tx_stats[txq->qnum].count++;
1997 spin_lock(&sc->txbuflock);
1998 sc->tx_stats[txq->qnum].len--;
1999 list_move_tail(&bf->list, &sc->txbuf);
2001 spin_unlock(&sc->txbuflock);
2003 if (likely(list_empty(&txq->q)))
2005 spin_unlock(&txq->lock);
2006 if (sc->txbuf_len > ATH_TXBUF / 5)
2007 ieee80211_wake_queues(sc->hw);
2011 ath5k_tasklet_tx(unsigned long data)
2014 struct ath5k_softc *sc = (void *)data;
2016 for (i=0; i < AR5K_NUM_TX_QUEUES; i++)
2017 if (sc->txqs[i].setup && (sc->ah->ah_txq_isr & BIT(i)))
2018 ath5k_tx_processq(sc, &sc->txqs[i]);
2027 * Setup the beacon frame for transmit.
2030 ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
2032 struct sk_buff *skb = bf->skb;
2033 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2034 struct ath5k_hw *ah = sc->ah;
2035 struct ath5k_desc *ds;
2040 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
2042 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
2043 "skbaddr %llx\n", skb, skb->data, skb->len,
2044 (unsigned long long)bf->skbaddr);
2045 if (pci_dma_mapping_error(sc->pdev, bf->skbaddr)) {
2046 ATH5K_ERR(sc, "beacon DMA mapping failed\n");
2051 antenna = ah->ah_tx_ant;
2053 flags = AR5K_TXDESC_NOACK;
2054 if (sc->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) {
2055 ds->ds_link = bf->daddr; /* self-linked */
2056 flags |= AR5K_TXDESC_VEOL;
2061 * If we use multiple antennas on AP and use
2062 * the Sectored AP scenario, switch antenna every
2063 * 4 beacons to make sure everybody hears our AP.
2064 * When a client tries to associate, hw will keep
2065 * track of the tx antenna to be used for this client
2066 * automaticaly, based on ACKed packets.
2068 * Note: AP still listens and transmits RTS on the
2069 * default antenna which is supposed to be an omni.
2071 * Note2: On sectored scenarios it's possible to have
2072 * multiple antennas (1omni -the default- and 14 sectors)
2073 * so if we choose to actually support this mode we need
2074 * to allow user to set how many antennas we have and tweak
2075 * the code below to send beacons on all of them.
2077 if (ah->ah_ant_mode == AR5K_ANTMODE_SECTOR_AP)
2078 antenna = sc->bsent & 4 ? 2 : 1;
2081 /* FIXME: If we are in g mode and rate is a CCK rate
2082 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
2083 * from tx power (value is in dB units already) */
2084 ds->ds_data = bf->skbaddr;
2085 ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
2086 ieee80211_get_hdrlen_from_skb(skb),
2087 AR5K_PKT_TYPE_BEACON, (sc->power_level * 2),
2088 ieee80211_get_tx_rate(sc->hw, info)->hw_value,
2089 1, AR5K_TXKEYIX_INVALID,
2090 antenna, flags, 0, 0);
2096 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
2101 * Transmit a beacon frame at SWBA. Dynamic updates to the
2102 * frame contents are done as needed and the slot time is
2103 * also adjusted based on current state.
2105 * This is called from software irq context (beacontq or restq
2106 * tasklets) or user context from ath5k_beacon_config.
2109 ath5k_beacon_send(struct ath5k_softc *sc)
2111 struct ath5k_buf *bf = sc->bbuf;
2112 struct ath5k_hw *ah = sc->ah;
2113 struct sk_buff *skb;
2115 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n");
2117 if (unlikely(bf->skb == NULL || sc->opmode == NL80211_IFTYPE_STATION ||
2118 sc->opmode == NL80211_IFTYPE_MONITOR)) {
2119 ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
2123 * Check if the previous beacon has gone out. If
2124 * not don't don't try to post another, skip this
2125 * period and wait for the next. Missed beacons
2126 * indicate a problem and should not occur. If we
2127 * miss too many consecutive beacons reset the device.
2129 if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) {
2131 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2132 "missed %u consecutive beacons\n", sc->bmisscount);
2133 if (sc->bmisscount > 10) { /* NB: 10 is a guess */
2134 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2135 "stuck beacon time (%u missed)\n",
2137 tasklet_schedule(&sc->restq);
2141 if (unlikely(sc->bmisscount != 0)) {
2142 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2143 "resume beacon xmit after %u misses\n",
2149 * Stop any current dma and put the new frame on the queue.
2150 * This should never fail since we check above that no frames
2151 * are still pending on the queue.
2153 if (unlikely(ath5k_hw_stop_tx_dma(ah, sc->bhalq))) {
2154 ATH5K_WARN(sc, "beacon queue %u didn't start/stop ?\n", sc->bhalq);
2155 /* NB: hw still stops DMA, so proceed */
2158 /* refresh the beacon for AP mode */
2159 if (sc->opmode == NL80211_IFTYPE_AP)
2160 ath5k_beacon_update(sc->hw, sc->vif);
2162 ath5k_hw_set_txdp(ah, sc->bhalq, bf->daddr);
2163 ath5k_hw_start_tx_dma(ah, sc->bhalq);
2164 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
2165 sc->bhalq, (unsigned long long)bf->daddr, bf->desc);
2167 skb = ieee80211_get_buffered_bc(sc->hw, sc->vif);
2169 ath5k_tx_queue(sc->hw, skb, sc->cabq);
2170 skb = ieee80211_get_buffered_bc(sc->hw, sc->vif);
2178 * ath5k_beacon_update_timers - update beacon timers
2180 * @sc: struct ath5k_softc pointer we are operating on
2181 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
2182 * beacon timer update based on the current HW TSF.
2184 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
2185 * of a received beacon or the current local hardware TSF and write it to the
2186 * beacon timer registers.
2188 * This is called in a variety of situations, e.g. when a beacon is received,
2189 * when a TSF update has been detected, but also when an new IBSS is created or
2190 * when we otherwise know we have to update the timers, but we keep it in this
2191 * function to have it all together in one place.
2194 ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
2196 struct ath5k_hw *ah = sc->ah;
2197 u32 nexttbtt, intval, hw_tu, bc_tu;
2200 intval = sc->bintval & AR5K_BEACON_PERIOD;
2201 if (WARN_ON(!intval))
2204 /* beacon TSF converted to TU */
2205 bc_tu = TSF_TO_TU(bc_tsf);
2207 /* current TSF converted to TU */
2208 hw_tsf = ath5k_hw_get_tsf64(ah);
2209 hw_tu = TSF_TO_TU(hw_tsf);
2212 /* we use FUDGE to make sure the next TBTT is ahead of the current TU */
2215 * no beacons received, called internally.
2216 * just need to refresh timers based on HW TSF.
2218 nexttbtt = roundup(hw_tu + FUDGE, intval);
2219 } else if (bc_tsf == 0) {
2221 * no beacon received, probably called by ath5k_reset_tsf().
2222 * reset TSF to start with 0.
2225 intval |= AR5K_BEACON_RESET_TSF;
2226 } else if (bc_tsf > hw_tsf) {
2228 * beacon received, SW merge happend but HW TSF not yet updated.
2229 * not possible to reconfigure timers yet, but next time we
2230 * receive a beacon with the same BSSID, the hardware will
2231 * automatically update the TSF and then we need to reconfigure
2234 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2235 "need to wait for HW TSF sync\n");
2239 * most important case for beacon synchronization between STA.
2241 * beacon received and HW TSF has been already updated by HW.
2242 * update next TBTT based on the TSF of the beacon, but make
2243 * sure it is ahead of our local TSF timer.
2245 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
2249 sc->nexttbtt = nexttbtt;
2251 intval |= AR5K_BEACON_ENA;
2252 ath5k_hw_init_beacon(ah, nexttbtt, intval);
2255 * debugging output last in order to preserve the time critical aspect
2259 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2260 "reconfigured timers based on HW TSF\n");
2261 else if (bc_tsf == 0)
2262 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2263 "reset HW TSF and timers\n");
2265 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2266 "updated timers based on beacon TSF\n");
2268 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2269 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2270 (unsigned long long) bc_tsf,
2271 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
2272 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
2273 intval & AR5K_BEACON_PERIOD,
2274 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
2275 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
2280 * ath5k_beacon_config - Configure the beacon queues and interrupts
2282 * @sc: struct ath5k_softc pointer we are operating on
2284 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
2285 * interrupts to detect TSF updates only.
2288 ath5k_beacon_config(struct ath5k_softc *sc)
2290 struct ath5k_hw *ah = sc->ah;
2291 unsigned long flags;
2293 spin_lock_irqsave(&sc->block, flags);
2295 sc->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA);
2297 if (sc->enable_beacon) {
2299 * In IBSS mode we use a self-linked tx descriptor and let the
2300 * hardware send the beacons automatically. We have to load it
2302 * We use the SWBA interrupt only to keep track of the beacon
2303 * timers in order to detect automatic TSF updates.
2305 ath5k_beaconq_config(sc);
2307 sc->imask |= AR5K_INT_SWBA;
2309 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
2310 if (ath5k_hw_hasveol(ah))
2311 ath5k_beacon_send(sc);
2313 ath5k_beacon_update_timers(sc, -1);
2315 ath5k_hw_stop_tx_dma(sc->ah, sc->bhalq);
2318 ath5k_hw_set_imr(ah, sc->imask);
2320 spin_unlock_irqrestore(&sc->block, flags);
2323 static void ath5k_tasklet_beacon(unsigned long data)
2325 struct ath5k_softc *sc = (struct ath5k_softc *) data;
2328 * Software beacon alert--time to send a beacon.
2330 * In IBSS mode we use this interrupt just to
2331 * keep track of the next TBTT (target beacon
2332 * transmission time) in order to detect wether
2333 * automatic TSF updates happened.
2335 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
2336 /* XXX: only if VEOL suppported */
2337 u64 tsf = ath5k_hw_get_tsf64(sc->ah);
2338 sc->nexttbtt += sc->bintval;
2339 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2340 "SWBA nexttbtt: %x hw_tu: %x "
2344 (unsigned long long) tsf);
2346 spin_lock(&sc->block);
2347 ath5k_beacon_send(sc);
2348 spin_unlock(&sc->block);
2353 /********************\
2354 * Interrupt handling *
2355 \********************/
2358 ath5k_init(struct ath5k_softc *sc)
2360 struct ath5k_hw *ah = sc->ah;
2363 mutex_lock(&sc->lock);
2365 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode);
2368 * Stop anything previously setup. This is safe
2369 * no matter this is the first time through or not.
2371 ath5k_stop_locked(sc);
2373 /* Set PHY calibration interval */
2374 ah->ah_cal_intval = ath5k_calinterval;
2377 * The basic interface to setting the hardware in a good
2378 * state is ``reset''. On return the hardware is known to
2379 * be powered up and with interrupts disabled. This must
2380 * be followed by initialization of the appropriate bits
2381 * and then setup of the interrupt mask.
2383 sc->curchan = sc->hw->conf.channel;
2384 sc->curband = &sc->sbands[sc->curchan->band];
2385 sc->imask = AR5K_INT_RXOK | AR5K_INT_RXERR | AR5K_INT_RXEOL |
2386 AR5K_INT_RXORN | AR5K_INT_TXDESC | AR5K_INT_TXEOL |
2387 AR5K_INT_FATAL | AR5K_INT_GLOBAL | AR5K_INT_SWI;
2388 ret = ath5k_reset(sc, NULL);
2392 ath5k_rfkill_hw_start(ah);
2395 * Reset the key cache since some parts do not reset the
2396 * contents on initial power up or resume from suspend.
2398 for (i = 0; i < AR5K_KEYTABLE_SIZE; i++)
2399 ath5k_hw_reset_key(ah, i);
2401 /* Set ack to be sent at low bit-rates */
2402 ath5k_hw_set_ack_bitrate_high(ah, false);
2406 mutex_unlock(&sc->lock);
2411 ath5k_stop_locked(struct ath5k_softc *sc)
2413 struct ath5k_hw *ah = sc->ah;
2415 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n",
2416 test_bit(ATH_STAT_INVALID, sc->status));
2419 * Shutdown the hardware and driver:
2420 * stop output from above
2421 * disable interrupts
2423 * turn off the radio
2424 * clear transmit machinery
2425 * clear receive machinery
2426 * drain and release tx queues
2427 * reclaim beacon resources
2428 * power down hardware
2430 * Note that some of this work is not possible if the
2431 * hardware is gone (invalid).
2433 ieee80211_stop_queues(sc->hw);
2435 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2437 ath5k_hw_set_imr(ah, 0);
2438 synchronize_irq(sc->pdev->irq);
2440 ath5k_txq_cleanup(sc);
2441 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2443 ath5k_hw_phy_disable(ah);
2451 * Stop the device, grabbing the top-level lock to protect
2452 * against concurrent entry through ath5k_init (which can happen
2453 * if another thread does a system call and the thread doing the
2454 * stop is preempted).
2457 ath5k_stop_hw(struct ath5k_softc *sc)
2461 mutex_lock(&sc->lock);
2462 ret = ath5k_stop_locked(sc);
2463 if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) {
2465 * Don't set the card in full sleep mode!
2467 * a) When the device is in this state it must be carefully
2468 * woken up or references to registers in the PCI clock
2469 * domain may freeze the bus (and system). This varies
2470 * by chip and is mostly an issue with newer parts
2471 * (madwifi sources mentioned srev >= 0x78) that go to
2472 * sleep more quickly.
2474 * b) On older chips full sleep results a weird behaviour
2475 * during wakeup. I tested various cards with srev < 0x78
2476 * and they don't wake up after module reload, a second
2477 * module reload is needed to bring the card up again.
2479 * Until we figure out what's going on don't enable
2480 * full chip reset on any chip (this is what Legacy HAL
2481 * and Sam's HAL do anyway). Instead Perform a full reset
2482 * on the device (same as initial state after attach) and
2483 * leave it idle (keep MAC/BB on warm reset) */
2484 ret = ath5k_hw_on_hold(sc->ah);
2486 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2487 "putting device to sleep\n");
2489 ath5k_txbuf_free(sc, sc->bbuf);
2492 mutex_unlock(&sc->lock);
2494 tasklet_kill(&sc->rxtq);
2495 tasklet_kill(&sc->txtq);
2496 tasklet_kill(&sc->restq);
2497 tasklet_kill(&sc->calib);
2498 tasklet_kill(&sc->beacontq);
2500 ath5k_rfkill_hw_stop(sc->ah);
2506 ath5k_intr(int irq, void *dev_id)
2508 struct ath5k_softc *sc = dev_id;
2509 struct ath5k_hw *ah = sc->ah;
2510 enum ath5k_int status;
2511 unsigned int counter = 1000;
2513 if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) ||
2514 !ath5k_hw_is_intr_pending(ah)))
2518 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */
2519 ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2521 if (unlikely(status & AR5K_INT_FATAL)) {
2523 * Fatal errors are unrecoverable.
2524 * Typically these are caused by DMA errors.
2526 tasklet_schedule(&sc->restq);
2527 } else if (unlikely(status & AR5K_INT_RXORN)) {
2528 tasklet_schedule(&sc->restq);
2530 if (status & AR5K_INT_SWBA) {
2531 tasklet_hi_schedule(&sc->beacontq);
2533 if (status & AR5K_INT_RXEOL) {
2535 * NB: the hardware should re-read the link when
2536 * RXE bit is written, but it doesn't work at
2537 * least on older hardware revs.
2541 if (status & AR5K_INT_TXURN) {
2542 /* bump tx trigger level */
2543 ath5k_hw_update_tx_triglevel(ah, true);
2545 if (status & (AR5K_INT_RXOK | AR5K_INT_RXERR))
2546 tasklet_schedule(&sc->rxtq);
2547 if (status & (AR5K_INT_TXOK | AR5K_INT_TXDESC
2548 | AR5K_INT_TXERR | AR5K_INT_TXEOL))
2549 tasklet_schedule(&sc->txtq);
2550 if (status & AR5K_INT_BMISS) {
2553 if (status & AR5K_INT_SWI) {
2554 tasklet_schedule(&sc->calib);
2556 if (status & AR5K_INT_MIB) {
2558 * These stats are also used for ANI i think
2559 * so how about updating them more often ?
2561 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
2563 if (status & AR5K_INT_GPIO)
2564 tasklet_schedule(&sc->rf_kill.toggleq);
2567 } while (ath5k_hw_is_intr_pending(ah) && --counter > 0);
2569 if (unlikely(!counter))
2570 ATH5K_WARN(sc, "too many interrupts, giving up for now\n");
2572 ath5k_hw_calibration_poll(ah);
2578 ath5k_tasklet_reset(unsigned long data)
2580 struct ath5k_softc *sc = (void *)data;
2582 ath5k_reset_wake(sc);
2586 * Periodically recalibrate the PHY to account
2587 * for temperature/environment changes.
2590 ath5k_tasklet_calibrate(unsigned long data)
2592 struct ath5k_softc *sc = (void *)data;
2593 struct ath5k_hw *ah = sc->ah;
2595 /* Only full calibration for now */
2596 if (ah->ah_swi_mask != AR5K_SWI_FULL_CALIBRATION)
2599 /* Stop queues so that calibration
2600 * doesn't interfere with tx */
2601 ieee80211_stop_queues(sc->hw);
2603 ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
2604 ieee80211_frequency_to_channel(sc->curchan->center_freq),
2605 sc->curchan->hw_value);
2607 if (ath5k_hw_gainf_calibrate(ah) == AR5K_RFGAIN_NEED_CHANGE) {
2609 * Rfgain is out of bounds, reset the chip
2610 * to load new gain values.
2612 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n");
2613 ath5k_reset_wake(sc);
2615 if (ath5k_hw_phy_calibrate(ah, sc->curchan))
2616 ATH5K_ERR(sc, "calibration of channel %u failed\n",
2617 ieee80211_frequency_to_channel(
2618 sc->curchan->center_freq));
2620 ah->ah_swi_mask = 0;
2623 ieee80211_wake_queues(sc->hw);
2628 /********************\
2629 * Mac80211 functions *
2630 \********************/
2633 ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
2635 struct ath5k_softc *sc = hw->priv;
2637 return ath5k_tx_queue(hw, skb, sc->txq);
2640 static int ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
2641 struct ath5k_txq *txq)
2643 struct ath5k_softc *sc = hw->priv;
2644 struct ath5k_buf *bf;
2645 unsigned long flags;
2649 ath5k_debug_dump_skb(sc, skb, "TX ", 1);
2651 if (sc->opmode == NL80211_IFTYPE_MONITOR)
2652 ATH5K_DBG(sc, ATH5K_DEBUG_XMIT, "tx in monitor (scan?)\n");
2655 * the hardware expects the header padded to 4 byte boundaries
2656 * if this is not the case we add the padding after the header
2658 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2659 padsize = ath5k_pad_size(hdrlen);
2662 if (skb_headroom(skb) < padsize) {
2663 ATH5K_ERR(sc, "tx hdrlen not %%4: %d not enough"
2664 " headroom to pad %d\n", hdrlen, padsize);
2667 skb_push(skb, padsize);
2668 memmove(skb->data, skb->data+padsize, hdrlen);
2671 spin_lock_irqsave(&sc->txbuflock, flags);
2672 if (list_empty(&sc->txbuf)) {
2673 ATH5K_ERR(sc, "no further txbuf available, dropping packet\n");
2674 spin_unlock_irqrestore(&sc->txbuflock, flags);
2675 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
2678 bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list);
2679 list_del(&bf->list);
2681 if (list_empty(&sc->txbuf))
2682 ieee80211_stop_queues(hw);
2683 spin_unlock_irqrestore(&sc->txbuflock, flags);
2687 if (ath5k_txbuf_setup(sc, bf, txq)) {
2689 spin_lock_irqsave(&sc->txbuflock, flags);
2690 list_add_tail(&bf->list, &sc->txbuf);
2692 spin_unlock_irqrestore(&sc->txbuflock, flags);
2695 return NETDEV_TX_OK;
2698 dev_kfree_skb_any(skb);
2699 return NETDEV_TX_OK;
2703 * Reset the hardware. If chan is not NULL, then also pause rx/tx
2704 * and change to the given channel.
2707 ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan)
2709 struct ath5k_hw *ah = sc->ah;
2712 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n");
2715 ath5k_hw_set_imr(ah, 0);
2716 ath5k_txq_cleanup(sc);
2720 sc->curband = &sc->sbands[chan->band];
2722 ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, chan != NULL);
2724 ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret);
2728 ret = ath5k_rx_start(sc);
2730 ATH5K_ERR(sc, "can't start recv logic\n");
2735 * Change channels and update the h/w rate map if we're switching;
2736 * e.g. 11a to 11b/g.
2738 * We may be doing a reset in response to an ioctl that changes the
2739 * channel so update any state that might change as a result.
2743 /* ath5k_chan_change(sc, c); */
2745 ath5k_beacon_config(sc);
2746 /* intrs are enabled by ath5k_beacon_config */
2754 ath5k_reset_wake(struct ath5k_softc *sc)
2758 ret = ath5k_reset(sc, sc->curchan);
2760 ieee80211_wake_queues(sc->hw);
2765 static int ath5k_start(struct ieee80211_hw *hw)
2767 return ath5k_init(hw->priv);
2770 static void ath5k_stop(struct ieee80211_hw *hw)
2772 ath5k_stop_hw(hw->priv);
2775 static int ath5k_add_interface(struct ieee80211_hw *hw,
2776 struct ieee80211_if_init_conf *conf)
2778 struct ath5k_softc *sc = hw->priv;
2781 mutex_lock(&sc->lock);
2787 sc->vif = conf->vif;
2789 switch (conf->type) {
2790 case NL80211_IFTYPE_AP:
2791 case NL80211_IFTYPE_STATION:
2792 case NL80211_IFTYPE_ADHOC:
2793 case NL80211_IFTYPE_MESH_POINT:
2794 case NL80211_IFTYPE_MONITOR:
2795 sc->opmode = conf->type;
2802 ath5k_hw_set_lladdr(sc->ah, conf->mac_addr);
2803 ath5k_mode_setup(sc);
2807 mutex_unlock(&sc->lock);
2812 ath5k_remove_interface(struct ieee80211_hw *hw,
2813 struct ieee80211_if_init_conf *conf)
2815 struct ath5k_softc *sc = hw->priv;
2816 u8 mac[ETH_ALEN] = {};
2818 mutex_lock(&sc->lock);
2819 if (sc->vif != conf->vif)
2822 ath5k_hw_set_lladdr(sc->ah, mac);
2825 mutex_unlock(&sc->lock);
2829 * TODO: Phy disable/diversity etc
2832 ath5k_config(struct ieee80211_hw *hw, u32 changed)
2834 struct ath5k_softc *sc = hw->priv;
2835 struct ath5k_hw *ah = sc->ah;
2836 struct ieee80211_conf *conf = &hw->conf;
2839 mutex_lock(&sc->lock);
2841 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
2842 ret = ath5k_chan_set(sc, conf->channel);
2847 if ((changed & IEEE80211_CONF_CHANGE_POWER) &&
2848 (sc->power_level != conf->power_level)) {
2849 sc->power_level = conf->power_level;
2852 ath5k_hw_set_txpower_limit(ah, (conf->power_level * 2));
2856 * 1) Move this on config_interface and handle each case
2857 * separately eg. when we have only one STA vif, use
2858 * AR5K_ANTMODE_SINGLE_AP
2860 * 2) Allow the user to change antenna mode eg. when only
2861 * one antenna is present
2863 * 3) Allow the user to set default/tx antenna when possible
2865 * 4) Default mode should handle 90% of the cases, together
2866 * with fixed a/b and single AP modes we should be able to
2867 * handle 99%. Sectored modes are extreme cases and i still
2868 * haven't found a usage for them. If we decide to support them,
2869 * then we must allow the user to set how many tx antennas we
2872 ath5k_hw_set_antenna_mode(ah, AR5K_ANTMODE_DEFAULT);
2875 mutex_unlock(&sc->lock);
2879 static u64 ath5k_prepare_multicast(struct ieee80211_hw *hw,
2880 int mc_count, struct dev_addr_list *mclist)
2889 for (i = 0; i < mc_count; i++) {
2892 /* calculate XOR of eight 6-bit values */
2893 val = get_unaligned_le32(mclist->dmi_addr + 0);
2894 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2895 val = get_unaligned_le32(mclist->dmi_addr + 3);
2896 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2898 mfilt[pos / 32] |= (1 << (pos % 32));
2899 /* XXX: we might be able to just do this instead,
2900 * but not sure, needs testing, if we do use this we'd
2901 * neet to inform below to not reset the mcast */
2902 /* ath5k_hw_set_mcast_filterindex(ah,
2903 * mclist->dmi_addr[5]); */
2904 mclist = mclist->next;
2907 return ((u64)(mfilt[1]) << 32) | mfilt[0];
2910 #define SUPPORTED_FIF_FLAGS \
2911 FIF_PROMISC_IN_BSS | FIF_ALLMULTI | FIF_FCSFAIL | \
2912 FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
2913 FIF_BCN_PRBRESP_PROMISC
2915 * o always accept unicast, broadcast, and multicast traffic
2916 * o multicast traffic for all BSSIDs will be enabled if mac80211
2918 * o maintain current state of phy ofdm or phy cck error reception.
2919 * If the hardware detects any of these type of errors then
2920 * ath5k_hw_get_rx_filter() will pass to us the respective
2921 * hardware filters to be able to receive these type of frames.
2922 * o probe request frames are accepted only when operating in
2923 * hostap, adhoc, or monitor modes
2924 * o enable promiscuous mode according to the interface state
2926 * - when operating in adhoc mode so the 802.11 layer creates
2927 * node table entries for peers,
2928 * - when operating in station mode for collecting rssi data when
2929 * the station is otherwise quiet, or
2932 static void ath5k_configure_filter(struct ieee80211_hw *hw,
2933 unsigned int changed_flags,
2934 unsigned int *new_flags,
2937 struct ath5k_softc *sc = hw->priv;
2938 struct ath5k_hw *ah = sc->ah;
2939 u32 mfilt[2], rfilt;
2941 mutex_lock(&sc->lock);
2943 mfilt[0] = multicast;
2944 mfilt[1] = multicast >> 32;
2946 /* Only deal with supported flags */
2947 changed_flags &= SUPPORTED_FIF_FLAGS;
2948 *new_flags &= SUPPORTED_FIF_FLAGS;
2950 /* If HW detects any phy or radar errors, leave those filters on.
2951 * Also, always enable Unicast, Broadcasts and Multicast
2952 * XXX: move unicast, bssid broadcasts and multicast to mac80211 */
2953 rfilt = (ath5k_hw_get_rx_filter(ah) & (AR5K_RX_FILTER_PHYERR)) |
2954 (AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST |
2955 AR5K_RX_FILTER_MCAST);
2957 if (changed_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) {
2958 if (*new_flags & FIF_PROMISC_IN_BSS) {
2959 rfilt |= AR5K_RX_FILTER_PROM;
2960 __set_bit(ATH_STAT_PROMISC, sc->status);
2962 __clear_bit(ATH_STAT_PROMISC, sc->status);
2966 /* Note, AR5K_RX_FILTER_MCAST is already enabled */
2967 if (*new_flags & FIF_ALLMULTI) {
2972 /* This is the best we can do */
2973 if (*new_flags & (FIF_FCSFAIL | FIF_PLCPFAIL))
2974 rfilt |= AR5K_RX_FILTER_PHYERR;
2976 /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
2977 * and probes for any BSSID, this needs testing */
2978 if (*new_flags & FIF_BCN_PRBRESP_PROMISC)
2979 rfilt |= AR5K_RX_FILTER_BEACON | AR5K_RX_FILTER_PROBEREQ;
2981 /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
2982 * set we should only pass on control frames for this
2983 * station. This needs testing. I believe right now this
2984 * enables *all* control frames, which is OK.. but
2985 * but we should see if we can improve on granularity */
2986 if (*new_flags & FIF_CONTROL)
2987 rfilt |= AR5K_RX_FILTER_CONTROL;
2989 /* Additional settings per mode -- this is per ath5k */
2991 /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */
2993 switch (sc->opmode) {
2994 case NL80211_IFTYPE_MESH_POINT:
2995 case NL80211_IFTYPE_MONITOR:
2996 rfilt |= AR5K_RX_FILTER_CONTROL |
2997 AR5K_RX_FILTER_BEACON |
2998 AR5K_RX_FILTER_PROBEREQ |
2999 AR5K_RX_FILTER_PROM;
3001 case NL80211_IFTYPE_AP:
3002 case NL80211_IFTYPE_ADHOC:
3003 rfilt |= AR5K_RX_FILTER_PROBEREQ |
3004 AR5K_RX_FILTER_BEACON;
3006 case NL80211_IFTYPE_STATION:
3008 rfilt |= AR5K_RX_FILTER_BEACON;
3014 ath5k_hw_set_rx_filter(ah, rfilt);
3016 /* Set multicast bits */
3017 ath5k_hw_set_mcast_filter(ah, mfilt[0], mfilt[1]);
3018 /* Set the cached hw filter flags, this will alter actually
3020 sc->filter_flags = rfilt;
3022 mutex_unlock(&sc->lock);
3026 ath5k_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
3027 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
3028 struct ieee80211_key_conf *key)
3030 struct ath5k_softc *sc = hw->priv;
3031 struct ath5k_hw *ah = sc->ah;
3032 struct ath_common *common = ath5k_hw_common(ah);
3035 if (modparam_nohwcrypt)
3038 if (sc->opmode == NL80211_IFTYPE_AP)
3046 if (sc->ah->ah_aes_support)
3055 mutex_lock(&sc->lock);
3059 ret = ath5k_hw_set_key(sc->ah, key->keyidx, key,
3060 sta ? sta->addr : NULL);
3062 ATH5K_ERR(sc, "can't set the key\n");
3065 __set_bit(key->keyidx, common->keymap);
3066 key->hw_key_idx = key->keyidx;
3067 key->flags |= (IEEE80211_KEY_FLAG_GENERATE_IV |
3068 IEEE80211_KEY_FLAG_GENERATE_MMIC);
3071 ath5k_hw_reset_key(sc->ah, key->keyidx);
3072 __clear_bit(key->keyidx, common->keymap);
3081 mutex_unlock(&sc->lock);
3086 ath5k_get_stats(struct ieee80211_hw *hw,
3087 struct ieee80211_low_level_stats *stats)
3089 struct ath5k_softc *sc = hw->priv;
3090 struct ath5k_hw *ah = sc->ah;
3093 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
3095 memcpy(stats, &sc->ll_stats, sizeof(sc->ll_stats));
3101 ath5k_get_tx_stats(struct ieee80211_hw *hw,
3102 struct ieee80211_tx_queue_stats *stats)
3104 struct ath5k_softc *sc = hw->priv;
3106 memcpy(stats, &sc->tx_stats, sizeof(sc->tx_stats));
3112 ath5k_get_tsf(struct ieee80211_hw *hw)
3114 struct ath5k_softc *sc = hw->priv;
3116 return ath5k_hw_get_tsf64(sc->ah);
3120 ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
3122 struct ath5k_softc *sc = hw->priv;
3124 ath5k_hw_set_tsf64(sc->ah, tsf);
3128 ath5k_reset_tsf(struct ieee80211_hw *hw)
3130 struct ath5k_softc *sc = hw->priv;
3133 * in IBSS mode we need to update the beacon timers too.
3134 * this will also reset the TSF if we call it with 0
3136 if (sc->opmode == NL80211_IFTYPE_ADHOC)
3137 ath5k_beacon_update_timers(sc, 0);
3139 ath5k_hw_reset_tsf(sc->ah);
3143 * Updates the beacon that is sent by ath5k_beacon_send. For adhoc,
3144 * this is called only once at config_bss time, for AP we do it every
3145 * SWBA interrupt so that the TIM will reflect buffered frames.
3147 * Called with the beacon lock.
3150 ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
3153 struct ath5k_softc *sc = hw->priv;
3154 struct sk_buff *skb;
3156 if (WARN_ON(!vif)) {
3161 skb = ieee80211_beacon_get(hw, vif);
3168 ath5k_debug_dump_skb(sc, skb, "BC ", 1);
3170 ath5k_txbuf_free(sc, sc->bbuf);
3171 sc->bbuf->skb = skb;
3172 ret = ath5k_beacon_setup(sc, sc->bbuf);
3174 sc->bbuf->skb = NULL;
3180 set_beacon_filter(struct ieee80211_hw *hw, bool enable)
3182 struct ath5k_softc *sc = hw->priv;
3183 struct ath5k_hw *ah = sc->ah;
3185 rfilt = ath5k_hw_get_rx_filter(ah);
3187 rfilt |= AR5K_RX_FILTER_BEACON;
3189 rfilt &= ~AR5K_RX_FILTER_BEACON;
3190 ath5k_hw_set_rx_filter(ah, rfilt);
3191 sc->filter_flags = rfilt;
3194 static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
3195 struct ieee80211_vif *vif,
3196 struct ieee80211_bss_conf *bss_conf,
3199 struct ath5k_softc *sc = hw->priv;
3200 struct ath5k_hw *ah = sc->ah;
3201 struct ath_common *common = ath5k_hw_common(ah);
3202 unsigned long flags;
3204 mutex_lock(&sc->lock);
3205 if (WARN_ON(sc->vif != vif))
3208 if (changes & BSS_CHANGED_BSSID) {
3209 /* Cache for later use during resets */
3210 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
3212 ath5k_hw_set_associd(ah);
3216 if (changes & BSS_CHANGED_BEACON_INT)
3217 sc->bintval = bss_conf->beacon_int;
3219 if (changes & BSS_CHANGED_ASSOC) {
3220 sc->assoc = bss_conf->assoc;
3221 if (sc->opmode == NL80211_IFTYPE_STATION)
3222 set_beacon_filter(hw, sc->assoc);
3223 ath5k_hw_set_ledstate(sc->ah, sc->assoc ?
3224 AR5K_LED_ASSOC : AR5K_LED_INIT);
3225 if (bss_conf->assoc) {
3226 ATH5K_DBG(sc, ATH5K_DEBUG_ANY,
3227 "Bss Info ASSOC %d, bssid: %pM\n",
3228 bss_conf->aid, common->curbssid);
3229 common->curaid = bss_conf->aid;
3230 ath5k_hw_set_associd(ah);
3231 /* Once ANI is available you would start it here */
3235 if (changes & BSS_CHANGED_BEACON) {
3236 spin_lock_irqsave(&sc->block, flags);
3237 ath5k_beacon_update(hw, vif);
3238 spin_unlock_irqrestore(&sc->block, flags);
3241 if (changes & BSS_CHANGED_BEACON_ENABLED)
3242 sc->enable_beacon = bss_conf->enable_beacon;
3244 if (changes & (BSS_CHANGED_BEACON | BSS_CHANGED_BEACON_ENABLED |
3245 BSS_CHANGED_BEACON_INT))
3246 ath5k_beacon_config(sc);
3249 mutex_unlock(&sc->lock);
3252 static void ath5k_sw_scan_start(struct ieee80211_hw *hw)
3254 struct ath5k_softc *sc = hw->priv;
3256 ath5k_hw_set_ledstate(sc->ah, AR5K_LED_SCAN);
3259 static void ath5k_sw_scan_complete(struct ieee80211_hw *hw)
3261 struct ath5k_softc *sc = hw->priv;
3262 ath5k_hw_set_ledstate(sc->ah, sc->assoc ?
3263 AR5K_LED_ASSOC : AR5K_LED_INIT);
git://ftp.safe.ca / safe / jmp / linux-2.6 / blob