2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
43 #include <linux/module.h>
44 #include <linux/delay.h>
45 #include <linux/hardirq.h>
48 #include <linux/netdevice.h>
49 #include <linux/cache.h>
50 #include <linux/pci.h>
51 #include <linux/ethtool.h>
52 #include <linux/uaccess.h>
54 #include <net/ieee80211_radiotap.h>
56 #include <asm/unaligned.h>
63 static int modparam_nohwcrypt;
64 module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
65 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
67 static int modparam_all_channels;
68 module_param_named(all_channels, modparam_all_channels, bool, S_IRUGO);
69 MODULE_PARM_DESC(all_channels, "Expose all channels the device can use.");
77 MODULE_AUTHOR("Jiri Slaby");
78 MODULE_AUTHOR("Nick Kossifidis");
79 MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
80 MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
81 MODULE_LICENSE("Dual BSD/GPL");
82 MODULE_VERSION("0.6.0 (EXPERIMENTAL)");
86 static DEFINE_PCI_DEVICE_TABLE(ath5k_pci_id_table) = {
87 { PCI_VDEVICE(ATHEROS, 0x0207) }, /* 5210 early */
88 { PCI_VDEVICE(ATHEROS, 0x0007) }, /* 5210 */
89 { PCI_VDEVICE(ATHEROS, 0x0011) }, /* 5311 - this is on AHB bus !*/
90 { PCI_VDEVICE(ATHEROS, 0x0012) }, /* 5211 */
91 { PCI_VDEVICE(ATHEROS, 0x0013) }, /* 5212 */
92 { PCI_VDEVICE(3COM_2, 0x0013) }, /* 3com 5212 */
93 { PCI_VDEVICE(3COM, 0x0013) }, /* 3com 3CRDAG675 5212 */
94 { PCI_VDEVICE(ATHEROS, 0x1014) }, /* IBM minipci 5212 */
95 { PCI_VDEVICE(ATHEROS, 0x0014) }, /* 5212 combatible */
96 { PCI_VDEVICE(ATHEROS, 0x0015) }, /* 5212 combatible */
97 { PCI_VDEVICE(ATHEROS, 0x0016) }, /* 5212 combatible */
98 { PCI_VDEVICE(ATHEROS, 0x0017) }, /* 5212 combatible */
99 { PCI_VDEVICE(ATHEROS, 0x0018) }, /* 5212 combatible */
100 { PCI_VDEVICE(ATHEROS, 0x0019) }, /* 5212 combatible */
101 { PCI_VDEVICE(ATHEROS, 0x001a) }, /* 2413 Griffin-lite */
102 { PCI_VDEVICE(ATHEROS, 0x001b) }, /* 5413 Eagle */
103 { PCI_VDEVICE(ATHEROS, 0x001c) }, /* PCI-E cards */
104 { PCI_VDEVICE(ATHEROS, 0x001d) }, /* 2417 Nala */
107 MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table);
110 static const struct ath5k_srev_name srev_names[] = {
111 { "5210", AR5K_VERSION_MAC, AR5K_SREV_AR5210 },
112 { "5311", AR5K_VERSION_MAC, AR5K_SREV_AR5311 },
113 { "5311A", AR5K_VERSION_MAC, AR5K_SREV_AR5311A },
114 { "5311B", AR5K_VERSION_MAC, AR5K_SREV_AR5311B },
115 { "5211", AR5K_VERSION_MAC, AR5K_SREV_AR5211 },
116 { "5212", AR5K_VERSION_MAC, AR5K_SREV_AR5212 },
117 { "5213", AR5K_VERSION_MAC, AR5K_SREV_AR5213 },
118 { "5213A", AR5K_VERSION_MAC, AR5K_SREV_AR5213A },
119 { "2413", AR5K_VERSION_MAC, AR5K_SREV_AR2413 },
120 { "2414", AR5K_VERSION_MAC, AR5K_SREV_AR2414 },
121 { "5424", AR5K_VERSION_MAC, AR5K_SREV_AR5424 },
122 { "5413", AR5K_VERSION_MAC, AR5K_SREV_AR5413 },
123 { "5414", AR5K_VERSION_MAC, AR5K_SREV_AR5414 },
124 { "2415", AR5K_VERSION_MAC, AR5K_SREV_AR2415 },
125 { "5416", AR5K_VERSION_MAC, AR5K_SREV_AR5416 },
126 { "5418", AR5K_VERSION_MAC, AR5K_SREV_AR5418 },
127 { "2425", AR5K_VERSION_MAC, AR5K_SREV_AR2425 },
128 { "2417", AR5K_VERSION_MAC, AR5K_SREV_AR2417 },
129 { "xxxxx", AR5K_VERSION_MAC, AR5K_SREV_UNKNOWN },
130 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 },
131 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 },
132 { "5111A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111A },
133 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 },
134 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 },
135 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A },
136 { "5112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112B },
137 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 },
138 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A },
139 { "2112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112B },
140 { "2413", AR5K_VERSION_RAD, AR5K_SREV_RAD_2413 },
141 { "5413", AR5K_VERSION_RAD, AR5K_SREV_RAD_5413 },
142 { "2316", AR5K_VERSION_RAD, AR5K_SREV_RAD_2316 },
143 { "2317", AR5K_VERSION_RAD, AR5K_SREV_RAD_2317 },
144 { "5424", AR5K_VERSION_RAD, AR5K_SREV_RAD_5424 },
145 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 },
146 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN },
149 static const struct ieee80211_rate ath5k_rates[] = {
151 .hw_value = ATH5K_RATE_CODE_1M, },
153 .hw_value = ATH5K_RATE_CODE_2M,
154 .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE,
155 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
157 .hw_value = ATH5K_RATE_CODE_5_5M,
158 .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE,
159 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
161 .hw_value = ATH5K_RATE_CODE_11M,
162 .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE,
163 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
165 .hw_value = ATH5K_RATE_CODE_6M,
168 .hw_value = ATH5K_RATE_CODE_9M,
171 .hw_value = ATH5K_RATE_CODE_12M,
174 .hw_value = ATH5K_RATE_CODE_18M,
177 .hw_value = ATH5K_RATE_CODE_24M,
180 .hw_value = ATH5K_RATE_CODE_36M,
183 .hw_value = ATH5K_RATE_CODE_48M,
186 .hw_value = ATH5K_RATE_CODE_54M,
192 * Prototypes - PCI stack related functions
194 static int __devinit ath5k_pci_probe(struct pci_dev *pdev,
195 const struct pci_device_id *id);
196 static void __devexit ath5k_pci_remove(struct pci_dev *pdev);
198 static int ath5k_pci_suspend(struct device *dev);
199 static int ath5k_pci_resume(struct device *dev);
201 static SIMPLE_DEV_PM_OPS(ath5k_pm_ops, ath5k_pci_suspend, ath5k_pci_resume);
202 #define ATH5K_PM_OPS (&ath5k_pm_ops)
204 #define ATH5K_PM_OPS NULL
205 #endif /* CONFIG_PM */
207 static struct pci_driver ath5k_pci_driver = {
208 .name = KBUILD_MODNAME,
209 .id_table = ath5k_pci_id_table,
210 .probe = ath5k_pci_probe,
211 .remove = __devexit_p(ath5k_pci_remove),
212 .driver.pm = ATH5K_PM_OPS,
218 * Prototypes - MAC 802.11 stack related functions
220 static int ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb);
221 static int ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
222 struct ath5k_txq *txq);
223 static int ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan);
224 static int ath5k_reset_wake(struct ath5k_softc *sc);
225 static int ath5k_start(struct ieee80211_hw *hw);
226 static void ath5k_stop(struct ieee80211_hw *hw);
227 static int ath5k_add_interface(struct ieee80211_hw *hw,
228 struct ieee80211_vif *vif);
229 static void ath5k_remove_interface(struct ieee80211_hw *hw,
230 struct ieee80211_vif *vif);
231 static int ath5k_config(struct ieee80211_hw *hw, u32 changed);
232 static u64 ath5k_prepare_multicast(struct ieee80211_hw *hw,
233 int mc_count, struct dev_addr_list *mc_list);
234 static void ath5k_configure_filter(struct ieee80211_hw *hw,
235 unsigned int changed_flags,
236 unsigned int *new_flags,
238 static int ath5k_set_key(struct ieee80211_hw *hw,
239 enum set_key_cmd cmd,
240 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
241 struct ieee80211_key_conf *key);
242 static int ath5k_get_stats(struct ieee80211_hw *hw,
243 struct ieee80211_low_level_stats *stats);
244 static int ath5k_get_survey(struct ieee80211_hw *hw,
245 int idx, struct survey_info *survey);
246 static u64 ath5k_get_tsf(struct ieee80211_hw *hw);
247 static void ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf);
248 static void ath5k_reset_tsf(struct ieee80211_hw *hw);
249 static int ath5k_beacon_update(struct ieee80211_hw *hw,
250 struct ieee80211_vif *vif);
251 static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
252 struct ieee80211_vif *vif,
253 struct ieee80211_bss_conf *bss_conf,
255 static void ath5k_sw_scan_start(struct ieee80211_hw *hw);
256 static void ath5k_sw_scan_complete(struct ieee80211_hw *hw);
257 static void ath5k_set_coverage_class(struct ieee80211_hw *hw,
260 static const struct ieee80211_ops ath5k_hw_ops = {
262 .start = ath5k_start,
264 .add_interface = ath5k_add_interface,
265 .remove_interface = ath5k_remove_interface,
266 .config = ath5k_config,
267 .prepare_multicast = ath5k_prepare_multicast,
268 .configure_filter = ath5k_configure_filter,
269 .set_key = ath5k_set_key,
270 .get_stats = ath5k_get_stats,
271 .get_survey = ath5k_get_survey,
273 .get_tsf = ath5k_get_tsf,
274 .set_tsf = ath5k_set_tsf,
275 .reset_tsf = ath5k_reset_tsf,
276 .bss_info_changed = ath5k_bss_info_changed,
277 .sw_scan_start = ath5k_sw_scan_start,
278 .sw_scan_complete = ath5k_sw_scan_complete,
279 .set_coverage_class = ath5k_set_coverage_class,
283 * Prototypes - Internal functions
286 static int ath5k_attach(struct pci_dev *pdev,
287 struct ieee80211_hw *hw);
288 static void ath5k_detach(struct pci_dev *pdev,
289 struct ieee80211_hw *hw);
290 /* Channel/mode setup */
291 static inline short ath5k_ieee2mhz(short chan);
292 static unsigned int ath5k_copy_channels(struct ath5k_hw *ah,
293 struct ieee80211_channel *channels,
296 static int ath5k_setup_bands(struct ieee80211_hw *hw);
297 static int ath5k_chan_set(struct ath5k_softc *sc,
298 struct ieee80211_channel *chan);
299 static void ath5k_setcurmode(struct ath5k_softc *sc,
301 static void ath5k_mode_setup(struct ath5k_softc *sc);
303 /* Descriptor setup */
304 static int ath5k_desc_alloc(struct ath5k_softc *sc,
305 struct pci_dev *pdev);
306 static void ath5k_desc_free(struct ath5k_softc *sc,
307 struct pci_dev *pdev);
309 static int ath5k_rxbuf_setup(struct ath5k_softc *sc,
310 struct ath5k_buf *bf);
311 static int ath5k_txbuf_setup(struct ath5k_softc *sc,
312 struct ath5k_buf *bf,
313 struct ath5k_txq *txq, int padsize);
314 static inline void ath5k_txbuf_free(struct ath5k_softc *sc,
315 struct ath5k_buf *bf)
320 pci_unmap_single(sc->pdev, bf->skbaddr, bf->skb->len,
322 dev_kfree_skb_any(bf->skb);
326 static inline void ath5k_rxbuf_free(struct ath5k_softc *sc,
327 struct ath5k_buf *bf)
329 struct ath5k_hw *ah = sc->ah;
330 struct ath_common *common = ath5k_hw_common(ah);
335 pci_unmap_single(sc->pdev, bf->skbaddr, common->rx_bufsize,
337 dev_kfree_skb_any(bf->skb);
343 static struct ath5k_txq *ath5k_txq_setup(struct ath5k_softc *sc,
344 int qtype, int subtype);
345 static int ath5k_beaconq_setup(struct ath5k_hw *ah);
346 static int ath5k_beaconq_config(struct ath5k_softc *sc);
347 static void ath5k_txq_drainq(struct ath5k_softc *sc,
348 struct ath5k_txq *txq);
349 static void ath5k_txq_cleanup(struct ath5k_softc *sc);
350 static void ath5k_txq_release(struct ath5k_softc *sc);
352 static int ath5k_rx_start(struct ath5k_softc *sc);
353 static void ath5k_rx_stop(struct ath5k_softc *sc);
354 static unsigned int ath5k_rx_decrypted(struct ath5k_softc *sc,
355 struct ath5k_desc *ds,
357 struct ath5k_rx_status *rs);
358 static void ath5k_tasklet_rx(unsigned long data);
360 static void ath5k_tx_processq(struct ath5k_softc *sc,
361 struct ath5k_txq *txq);
362 static void ath5k_tasklet_tx(unsigned long data);
363 /* Beacon handling */
364 static int ath5k_beacon_setup(struct ath5k_softc *sc,
365 struct ath5k_buf *bf);
366 static void ath5k_beacon_send(struct ath5k_softc *sc);
367 static void ath5k_beacon_config(struct ath5k_softc *sc);
368 static void ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf);
369 static void ath5k_tasklet_beacon(unsigned long data);
370 static void ath5k_tasklet_ani(unsigned long data);
372 static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
374 u64 tsf = ath5k_hw_get_tsf64(ah);
376 if ((tsf & 0x7fff) < rstamp)
379 return (tsf & ~0x7fff) | rstamp;
382 /* Interrupt handling */
383 static int ath5k_init(struct ath5k_softc *sc);
384 static int ath5k_stop_locked(struct ath5k_softc *sc);
385 static int ath5k_stop_hw(struct ath5k_softc *sc);
386 static irqreturn_t ath5k_intr(int irq, void *dev_id);
387 static void ath5k_tasklet_reset(unsigned long data);
389 static void ath5k_tasklet_calibrate(unsigned long data);
392 * Module init/exit functions
401 ret = pci_register_driver(&ath5k_pci_driver);
403 printk(KERN_ERR "ath5k_pci: can't register pci driver\n");
413 pci_unregister_driver(&ath5k_pci_driver);
415 ath5k_debug_finish();
418 module_init(init_ath5k_pci);
419 module_exit(exit_ath5k_pci);
422 /********************\
423 * PCI Initialization *
424 \********************/
427 ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
429 const char *name = "xxxxx";
432 for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
433 if (srev_names[i].sr_type != type)
436 if ((val & 0xf0) == srev_names[i].sr_val)
437 name = srev_names[i].sr_name;
439 if ((val & 0xff) == srev_names[i].sr_val) {
440 name = srev_names[i].sr_name;
447 static unsigned int ath5k_ioread32(void *hw_priv, u32 reg_offset)
449 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
450 return ath5k_hw_reg_read(ah, reg_offset);
453 static void ath5k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
455 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
456 ath5k_hw_reg_write(ah, val, reg_offset);
459 static const struct ath_ops ath5k_common_ops = {
460 .read = ath5k_ioread32,
461 .write = ath5k_iowrite32,
465 ath5k_pci_probe(struct pci_dev *pdev,
466 const struct pci_device_id *id)
469 struct ath5k_softc *sc;
470 struct ath_common *common;
471 struct ieee80211_hw *hw;
475 ret = pci_enable_device(pdev);
477 dev_err(&pdev->dev, "can't enable device\n");
481 /* XXX 32-bit addressing only */
482 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
484 dev_err(&pdev->dev, "32-bit DMA not available\n");
489 * Cache line size is used to size and align various
490 * structures used to communicate with the hardware.
492 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
495 * Linux 2.4.18 (at least) writes the cache line size
496 * register as a 16-bit wide register which is wrong.
497 * We must have this setup properly for rx buffer
498 * DMA to work so force a reasonable value here if it
501 csz = L1_CACHE_BYTES >> 2;
502 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
505 * The default setting of latency timer yields poor results,
506 * set it to the value used by other systems. It may be worth
507 * tweaking this setting more.
509 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
511 /* Enable bus mastering */
512 pci_set_master(pdev);
515 * Disable the RETRY_TIMEOUT register (0x41) to keep
516 * PCI Tx retries from interfering with C3 CPU state.
518 pci_write_config_byte(pdev, 0x41, 0);
520 ret = pci_request_region(pdev, 0, "ath5k");
522 dev_err(&pdev->dev, "cannot reserve PCI memory region\n");
526 mem = pci_iomap(pdev, 0, 0);
528 dev_err(&pdev->dev, "cannot remap PCI memory region\n") ;
534 * Allocate hw (mac80211 main struct)
535 * and hw->priv (driver private data)
537 hw = ieee80211_alloc_hw(sizeof(*sc), &ath5k_hw_ops);
539 dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n");
544 dev_info(&pdev->dev, "registered as '%s'\n", wiphy_name(hw->wiphy));
546 /* Initialize driver private data */
547 SET_IEEE80211_DEV(hw, &pdev->dev);
548 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
549 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
550 IEEE80211_HW_SIGNAL_DBM |
551 IEEE80211_HW_NOISE_DBM;
553 hw->wiphy->interface_modes =
554 BIT(NL80211_IFTYPE_AP) |
555 BIT(NL80211_IFTYPE_STATION) |
556 BIT(NL80211_IFTYPE_ADHOC) |
557 BIT(NL80211_IFTYPE_MESH_POINT);
559 hw->extra_tx_headroom = 2;
560 hw->channel_change_time = 5000;
565 ath5k_debug_init_device(sc);
568 * Mark the device as detached to avoid processing
569 * interrupts until setup is complete.
571 __set_bit(ATH_STAT_INVALID, sc->status);
573 sc->iobase = mem; /* So we can unmap it on detach */
574 sc->opmode = NL80211_IFTYPE_STATION;
576 mutex_init(&sc->lock);
577 spin_lock_init(&sc->rxbuflock);
578 spin_lock_init(&sc->txbuflock);
579 spin_lock_init(&sc->block);
581 /* Set private data */
582 pci_set_drvdata(pdev, hw);
584 /* Setup interrupt handler */
585 ret = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
587 ATH5K_ERR(sc, "request_irq failed\n");
591 /*If we passed the test malloc a ath5k_hw struct*/
592 sc->ah = kzalloc(sizeof(struct ath5k_hw), GFP_KERNEL);
595 ATH5K_ERR(sc, "out of memory\n");
600 sc->ah->ah_iobase = sc->iobase;
601 common = ath5k_hw_common(sc->ah);
602 common->ops = &ath5k_common_ops;
605 common->cachelsz = csz << 2; /* convert to bytes */
607 /* Initialize device */
608 ret = ath5k_hw_attach(sc);
613 /* set up multi-rate retry capabilities */
614 if (sc->ah->ah_version == AR5K_AR5212) {
616 hw->max_rate_tries = 11;
619 /* Finish private driver data initialization */
620 ret = ath5k_attach(pdev, hw);
624 ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
625 ath5k_chip_name(AR5K_VERSION_MAC, sc->ah->ah_mac_srev),
627 sc->ah->ah_phy_revision);
629 if (!sc->ah->ah_single_chip) {
630 /* Single chip radio (!RF5111) */
631 if (sc->ah->ah_radio_5ghz_revision &&
632 !sc->ah->ah_radio_2ghz_revision) {
633 /* No 5GHz support -> report 2GHz radio */
634 if (!test_bit(AR5K_MODE_11A,
635 sc->ah->ah_capabilities.cap_mode)) {
636 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
637 ath5k_chip_name(AR5K_VERSION_RAD,
638 sc->ah->ah_radio_5ghz_revision),
639 sc->ah->ah_radio_5ghz_revision);
640 /* No 2GHz support (5110 and some
641 * 5Ghz only cards) -> report 5Ghz radio */
642 } else if (!test_bit(AR5K_MODE_11B,
643 sc->ah->ah_capabilities.cap_mode)) {
644 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
645 ath5k_chip_name(AR5K_VERSION_RAD,
646 sc->ah->ah_radio_5ghz_revision),
647 sc->ah->ah_radio_5ghz_revision);
648 /* Multiband radio */
650 ATH5K_INFO(sc, "RF%s multiband radio found"
652 ath5k_chip_name(AR5K_VERSION_RAD,
653 sc->ah->ah_radio_5ghz_revision),
654 sc->ah->ah_radio_5ghz_revision);
657 /* Multi chip radio (RF5111 - RF2111) ->
658 * report both 2GHz/5GHz radios */
659 else if (sc->ah->ah_radio_5ghz_revision &&
660 sc->ah->ah_radio_2ghz_revision){
661 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
662 ath5k_chip_name(AR5K_VERSION_RAD,
663 sc->ah->ah_radio_5ghz_revision),
664 sc->ah->ah_radio_5ghz_revision);
665 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
666 ath5k_chip_name(AR5K_VERSION_RAD,
667 sc->ah->ah_radio_2ghz_revision),
668 sc->ah->ah_radio_2ghz_revision);
673 /* ready to process interrupts */
674 __clear_bit(ATH_STAT_INVALID, sc->status);
678 ath5k_hw_detach(sc->ah);
680 free_irq(pdev->irq, sc);
684 ieee80211_free_hw(hw);
686 pci_iounmap(pdev, mem);
688 pci_release_region(pdev, 0);
690 pci_disable_device(pdev);
695 static void __devexit
696 ath5k_pci_remove(struct pci_dev *pdev)
698 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
699 struct ath5k_softc *sc = hw->priv;
701 ath5k_debug_finish_device(sc);
702 ath5k_detach(pdev, hw);
703 ath5k_hw_detach(sc->ah);
705 free_irq(pdev->irq, sc);
706 pci_iounmap(pdev, sc->iobase);
707 pci_release_region(pdev, 0);
708 pci_disable_device(pdev);
709 ieee80211_free_hw(hw);
713 static int ath5k_pci_suspend(struct device *dev)
715 struct ieee80211_hw *hw = pci_get_drvdata(to_pci_dev(dev));
716 struct ath5k_softc *sc = hw->priv;
722 static int ath5k_pci_resume(struct device *dev)
724 struct pci_dev *pdev = to_pci_dev(dev);
725 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
726 struct ath5k_softc *sc = hw->priv;
729 * Suspend/Resume resets the PCI configuration space, so we have to
730 * re-disable the RETRY_TIMEOUT register (0x41) to keep
731 * PCI Tx retries from interfering with C3 CPU state
733 pci_write_config_byte(pdev, 0x41, 0);
735 ath5k_led_enable(sc);
738 #endif /* CONFIG_PM */
741 /***********************\
742 * Driver Initialization *
743 \***********************/
745 static int ath5k_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request)
747 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
748 struct ath5k_softc *sc = hw->priv;
749 struct ath_regulatory *regulatory = ath5k_hw_regulatory(sc->ah);
751 return ath_reg_notifier_apply(wiphy, request, regulatory);
755 ath5k_attach(struct pci_dev *pdev, struct ieee80211_hw *hw)
757 struct ath5k_softc *sc = hw->priv;
758 struct ath5k_hw *ah = sc->ah;
759 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah);
760 u8 mac[ETH_ALEN] = {};
763 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "devid 0x%x\n", pdev->device);
766 * Check if the MAC has multi-rate retry support.
767 * We do this by trying to setup a fake extended
768 * descriptor. MAC's that don't have support will
769 * return false w/o doing anything. MAC's that do
770 * support it will return true w/o doing anything.
772 ret = ah->ah_setup_mrr_tx_desc(ah, NULL, 0, 0, 0, 0, 0, 0);
776 __set_bit(ATH_STAT_MRRETRY, sc->status);
779 * Collect the channel list. The 802.11 layer
780 * is resposible for filtering this list based
781 * on settings like the phy mode and regulatory
782 * domain restrictions.
784 ret = ath5k_setup_bands(hw);
786 ATH5K_ERR(sc, "can't get channels\n");
790 /* NB: setup here so ath5k_rate_update is happy */
791 if (test_bit(AR5K_MODE_11A, ah->ah_modes))
792 ath5k_setcurmode(sc, AR5K_MODE_11A);
794 ath5k_setcurmode(sc, AR5K_MODE_11B);
797 * Allocate tx+rx descriptors and populate the lists.
799 ret = ath5k_desc_alloc(sc, pdev);
801 ATH5K_ERR(sc, "can't allocate descriptors\n");
806 * Allocate hardware transmit queues: one queue for
807 * beacon frames and one data queue for each QoS
808 * priority. Note that hw functions handle reseting
809 * these queues at the needed time.
811 ret = ath5k_beaconq_setup(ah);
813 ATH5K_ERR(sc, "can't setup a beacon xmit queue\n");
817 sc->cabq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_CAB, 0);
818 if (IS_ERR(sc->cabq)) {
819 ATH5K_ERR(sc, "can't setup cab queue\n");
820 ret = PTR_ERR(sc->cabq);
824 sc->txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
825 if (IS_ERR(sc->txq)) {
826 ATH5K_ERR(sc, "can't setup xmit queue\n");
827 ret = PTR_ERR(sc->txq);
831 tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc);
832 tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc);
833 tasklet_init(&sc->restq, ath5k_tasklet_reset, (unsigned long)sc);
834 tasklet_init(&sc->calib, ath5k_tasklet_calibrate, (unsigned long)sc);
835 tasklet_init(&sc->beacontq, ath5k_tasklet_beacon, (unsigned long)sc);
836 tasklet_init(&sc->ani_tasklet, ath5k_tasklet_ani, (unsigned long)sc);
838 ret = ath5k_eeprom_read_mac(ah, mac);
840 ATH5K_ERR(sc, "unable to read address from EEPROM: 0x%04x\n",
845 SET_IEEE80211_PERM_ADDR(hw, mac);
846 /* All MAC address bits matter for ACKs */
847 memcpy(sc->bssidmask, ath_bcast_mac, ETH_ALEN);
848 ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask);
850 regulatory->current_rd = ah->ah_capabilities.cap_eeprom.ee_regdomain;
851 ret = ath_regd_init(regulatory, hw->wiphy, ath5k_reg_notifier);
853 ATH5K_ERR(sc, "can't initialize regulatory system\n");
857 ret = ieee80211_register_hw(hw);
859 ATH5K_ERR(sc, "can't register ieee80211 hw\n");
863 if (!ath_is_world_regd(regulatory))
864 regulatory_hint(hw->wiphy, regulatory->alpha2);
870 ath5k_txq_release(sc);
872 ath5k_hw_release_tx_queue(ah, sc->bhalq);
874 ath5k_desc_free(sc, pdev);
880 ath5k_detach(struct pci_dev *pdev, struct ieee80211_hw *hw)
882 struct ath5k_softc *sc = hw->priv;
885 * NB: the order of these is important:
886 * o call the 802.11 layer before detaching ath5k_hw to
887 * insure callbacks into the driver to delete global
888 * key cache entries can be handled
889 * o reclaim the tx queue data structures after calling
890 * the 802.11 layer as we'll get called back to reclaim
891 * node state and potentially want to use them
892 * o to cleanup the tx queues the hal is called, so detach
894 * XXX: ??? detach ath5k_hw ???
895 * Other than that, it's straightforward...
897 ieee80211_unregister_hw(hw);
898 ath5k_desc_free(sc, pdev);
899 ath5k_txq_release(sc);
900 ath5k_hw_release_tx_queue(sc->ah, sc->bhalq);
901 ath5k_unregister_leds(sc);
904 * NB: can't reclaim these until after ieee80211_ifdetach
905 * returns because we'll get called back to reclaim node
906 * state and potentially want to use them.
913 /********************\
914 * Channel/mode setup *
915 \********************/
918 * Convert IEEE channel number to MHz frequency.
921 ath5k_ieee2mhz(short chan)
923 if (chan <= 14 || chan >= 27)
924 return ieee80211chan2mhz(chan);
926 return 2212 + chan * 20;
930 * Returns true for the channel numbers used without all_channels modparam.
932 static bool ath5k_is_standard_channel(short chan)
934 return ((chan <= 14) ||
936 ((chan & 3) == 0 && chan >= 36 && chan <= 64) ||
938 ((chan & 3) == 0 && chan >= 100 && chan <= 140) ||
940 ((chan & 3) == 1 && chan >= 149 && chan <= 165));
944 ath5k_copy_channels(struct ath5k_hw *ah,
945 struct ieee80211_channel *channels,
949 unsigned int i, count, size, chfreq, freq, ch;
951 if (!test_bit(mode, ah->ah_modes))
956 case AR5K_MODE_11A_TURBO:
957 /* 1..220, but 2GHz frequencies are filtered by check_channel */
959 chfreq = CHANNEL_5GHZ;
963 case AR5K_MODE_11G_TURBO:
965 chfreq = CHANNEL_2GHZ;
968 ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n");
972 for (i = 0, count = 0; i < size && max > 0; i++) {
974 freq = ath5k_ieee2mhz(ch);
976 /* Check if channel is supported by the chipset */
977 if (!ath5k_channel_ok(ah, freq, chfreq))
980 if (!modparam_all_channels && !ath5k_is_standard_channel(ch))
983 /* Write channel info and increment counter */
984 channels[count].center_freq = freq;
985 channels[count].band = (chfreq == CHANNEL_2GHZ) ?
986 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
990 channels[count].hw_value = chfreq | CHANNEL_OFDM;
992 case AR5K_MODE_11A_TURBO:
993 case AR5K_MODE_11G_TURBO:
994 channels[count].hw_value = chfreq |
995 CHANNEL_OFDM | CHANNEL_TURBO;
998 channels[count].hw_value = CHANNEL_B;
1009 ath5k_setup_rate_idx(struct ath5k_softc *sc, struct ieee80211_supported_band *b)
1013 for (i = 0; i < AR5K_MAX_RATES; i++)
1014 sc->rate_idx[b->band][i] = -1;
1016 for (i = 0; i < b->n_bitrates; i++) {
1017 sc->rate_idx[b->band][b->bitrates[i].hw_value] = i;
1018 if (b->bitrates[i].hw_value_short)
1019 sc->rate_idx[b->band][b->bitrates[i].hw_value_short] = i;
1024 ath5k_setup_bands(struct ieee80211_hw *hw)
1026 struct ath5k_softc *sc = hw->priv;
1027 struct ath5k_hw *ah = sc->ah;
1028 struct ieee80211_supported_band *sband;
1029 int max_c, count_c = 0;
1032 BUILD_BUG_ON(ARRAY_SIZE(sc->sbands) < IEEE80211_NUM_BANDS);
1033 max_c = ARRAY_SIZE(sc->channels);
1036 sband = &sc->sbands[IEEE80211_BAND_2GHZ];
1037 sband->band = IEEE80211_BAND_2GHZ;
1038 sband->bitrates = &sc->rates[IEEE80211_BAND_2GHZ][0];
1040 if (test_bit(AR5K_MODE_11G, sc->ah->ah_capabilities.cap_mode)) {
1042 memcpy(sband->bitrates, &ath5k_rates[0],
1043 sizeof(struct ieee80211_rate) * 12);
1044 sband->n_bitrates = 12;
1046 sband->channels = sc->channels;
1047 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
1048 AR5K_MODE_11G, max_c);
1050 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
1051 count_c = sband->n_channels;
1053 } else if (test_bit(AR5K_MODE_11B, sc->ah->ah_capabilities.cap_mode)) {
1055 memcpy(sband->bitrates, &ath5k_rates[0],
1056 sizeof(struct ieee80211_rate) * 4);
1057 sband->n_bitrates = 4;
1059 /* 5211 only supports B rates and uses 4bit rate codes
1060 * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B)
1063 if (ah->ah_version == AR5K_AR5211) {
1064 for (i = 0; i < 4; i++) {
1065 sband->bitrates[i].hw_value =
1066 sband->bitrates[i].hw_value & 0xF;
1067 sband->bitrates[i].hw_value_short =
1068 sband->bitrates[i].hw_value_short & 0xF;
1072 sband->channels = sc->channels;
1073 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
1074 AR5K_MODE_11B, max_c);
1076 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
1077 count_c = sband->n_channels;
1080 ath5k_setup_rate_idx(sc, sband);
1082 /* 5GHz band, A mode */
1083 if (test_bit(AR5K_MODE_11A, sc->ah->ah_capabilities.cap_mode)) {
1084 sband = &sc->sbands[IEEE80211_BAND_5GHZ];
1085 sband->band = IEEE80211_BAND_5GHZ;
1086 sband->bitrates = &sc->rates[IEEE80211_BAND_5GHZ][0];
1088 memcpy(sband->bitrates, &ath5k_rates[4],
1089 sizeof(struct ieee80211_rate) * 8);
1090 sband->n_bitrates = 8;
1092 sband->channels = &sc->channels[count_c];
1093 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
1094 AR5K_MODE_11A, max_c);
1096 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
1098 ath5k_setup_rate_idx(sc, sband);
1100 ath5k_debug_dump_bands(sc);
1106 * Set/change channels. We always reset the chip.
1107 * To accomplish this we must first cleanup any pending DMA,
1108 * then restart stuff after a la ath5k_init.
1110 * Called with sc->lock.
1113 ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)
1115 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "(%u MHz) -> (%u MHz)\n",
1116 sc->curchan->center_freq, chan->center_freq);
1119 * To switch channels clear any pending DMA operations;
1120 * wait long enough for the RX fifo to drain, reset the
1121 * hardware at the new frequency, and then re-enable
1122 * the relevant bits of the h/w.
1124 return ath5k_reset(sc, chan);
1128 ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode)
1132 if (mode == AR5K_MODE_11A) {
1133 sc->curband = &sc->sbands[IEEE80211_BAND_5GHZ];
1135 sc->curband = &sc->sbands[IEEE80211_BAND_2GHZ];
1140 ath5k_mode_setup(struct ath5k_softc *sc)
1142 struct ath5k_hw *ah = sc->ah;
1145 /* configure rx filter */
1146 rfilt = sc->filter_flags;
1147 ath5k_hw_set_rx_filter(ah, rfilt);
1149 if (ath5k_hw_hasbssidmask(ah))
1150 ath5k_hw_set_bssid_mask(ah, sc->bssidmask);
1152 /* configure operational mode */
1153 ath5k_hw_set_opmode(ah, sc->opmode);
1155 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "mode setup opmode %d\n", sc->opmode);
1156 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
1160 ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix)
1164 /* return base rate on errors */
1165 if (WARN(hw_rix < 0 || hw_rix >= AR5K_MAX_RATES,
1166 "hw_rix out of bounds: %x\n", hw_rix))
1169 rix = sc->rate_idx[sc->curband->band][hw_rix];
1170 if (WARN(rix < 0, "invalid hw_rix: %x\n", hw_rix))
1181 struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_softc *sc, dma_addr_t *skb_addr)
1183 struct ath_common *common = ath5k_hw_common(sc->ah);
1184 struct sk_buff *skb;
1187 * Allocate buffer with headroom_needed space for the
1188 * fake physical layer header at the start.
1190 skb = ath_rxbuf_alloc(common,
1195 ATH5K_ERR(sc, "can't alloc skbuff of size %u\n",
1196 common->rx_bufsize);
1200 *skb_addr = pci_map_single(sc->pdev,
1201 skb->data, common->rx_bufsize,
1202 PCI_DMA_FROMDEVICE);
1203 if (unlikely(pci_dma_mapping_error(sc->pdev, *skb_addr))) {
1204 ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__);
1212 ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1214 struct ath5k_hw *ah = sc->ah;
1215 struct sk_buff *skb = bf->skb;
1216 struct ath5k_desc *ds;
1219 skb = ath5k_rx_skb_alloc(sc, &bf->skbaddr);
1226 * Setup descriptors. For receive we always terminate
1227 * the descriptor list with a self-linked entry so we'll
1228 * not get overrun under high load (as can happen with a
1229 * 5212 when ANI processing enables PHY error frames).
1231 * To insure the last descriptor is self-linked we create
1232 * each descriptor as self-linked and add it to the end. As
1233 * each additional descriptor is added the previous self-linked
1234 * entry is ``fixed'' naturally. This should be safe even
1235 * if DMA is happening. When processing RX interrupts we
1236 * never remove/process the last, self-linked, entry on the
1237 * descriptor list. This insures the hardware always has
1238 * someplace to write a new frame.
1241 ds->ds_link = bf->daddr; /* link to self */
1242 ds->ds_data = bf->skbaddr;
1243 ah->ah_setup_rx_desc(ah, ds,
1244 skb_tailroom(skb), /* buffer size */
1247 if (sc->rxlink != NULL)
1248 *sc->rxlink = bf->daddr;
1249 sc->rxlink = &ds->ds_link;
1253 static enum ath5k_pkt_type get_hw_packet_type(struct sk_buff *skb)
1255 struct ieee80211_hdr *hdr;
1256 enum ath5k_pkt_type htype;
1259 hdr = (struct ieee80211_hdr *)skb->data;
1260 fc = hdr->frame_control;
1262 if (ieee80211_is_beacon(fc))
1263 htype = AR5K_PKT_TYPE_BEACON;
1264 else if (ieee80211_is_probe_resp(fc))
1265 htype = AR5K_PKT_TYPE_PROBE_RESP;
1266 else if (ieee80211_is_atim(fc))
1267 htype = AR5K_PKT_TYPE_ATIM;
1268 else if (ieee80211_is_pspoll(fc))
1269 htype = AR5K_PKT_TYPE_PSPOLL;
1271 htype = AR5K_PKT_TYPE_NORMAL;
1277 ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf,
1278 struct ath5k_txq *txq, int padsize)
1280 struct ath5k_hw *ah = sc->ah;
1281 struct ath5k_desc *ds = bf->desc;
1282 struct sk_buff *skb = bf->skb;
1283 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1284 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
1285 struct ieee80211_rate *rate;
1286 unsigned int mrr_rate[3], mrr_tries[3];
1293 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
1295 /* XXX endianness */
1296 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1299 rate = ieee80211_get_tx_rate(sc->hw, info);
1301 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
1302 flags |= AR5K_TXDESC_NOACK;
1304 rc_flags = info->control.rates[0].flags;
1305 hw_rate = (rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) ?
1306 rate->hw_value_short : rate->hw_value;
1310 /* FIXME: If we are in g mode and rate is a CCK rate
1311 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
1312 * from tx power (value is in dB units already) */
1313 if (info->control.hw_key) {
1314 keyidx = info->control.hw_key->hw_key_idx;
1315 pktlen += info->control.hw_key->icv_len;
1317 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
1318 flags |= AR5K_TXDESC_RTSENA;
1319 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
1320 duration = le16_to_cpu(ieee80211_rts_duration(sc->hw,
1321 sc->vif, pktlen, info));
1323 if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
1324 flags |= AR5K_TXDESC_CTSENA;
1325 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
1326 duration = le16_to_cpu(ieee80211_ctstoself_duration(sc->hw,
1327 sc->vif, pktlen, info));
1329 ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
1330 ieee80211_get_hdrlen_from_skb(skb), padsize,
1331 get_hw_packet_type(skb),
1332 (sc->power_level * 2),
1334 info->control.rates[0].count, keyidx, ah->ah_tx_ant, flags,
1335 cts_rate, duration);
1339 memset(mrr_rate, 0, sizeof(mrr_rate));
1340 memset(mrr_tries, 0, sizeof(mrr_tries));
1341 for (i = 0; i < 3; i++) {
1342 rate = ieee80211_get_alt_retry_rate(sc->hw, info, i);
1346 mrr_rate[i] = rate->hw_value;
1347 mrr_tries[i] = info->control.rates[i + 1].count;
1350 ah->ah_setup_mrr_tx_desc(ah, ds,
1351 mrr_rate[0], mrr_tries[0],
1352 mrr_rate[1], mrr_tries[1],
1353 mrr_rate[2], mrr_tries[2]);
1356 ds->ds_data = bf->skbaddr;
1358 spin_lock_bh(&txq->lock);
1359 list_add_tail(&bf->list, &txq->q);
1360 if (txq->link == NULL) /* is this first packet? */
1361 ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr);
1362 else /* no, so only link it */
1363 *txq->link = bf->daddr;
1365 txq->link = &ds->ds_link;
1366 ath5k_hw_start_tx_dma(ah, txq->qnum);
1368 spin_unlock_bh(&txq->lock);
1372 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1376 /*******************\
1377 * Descriptors setup *
1378 \*******************/
1381 ath5k_desc_alloc(struct ath5k_softc *sc, struct pci_dev *pdev)
1383 struct ath5k_desc *ds;
1384 struct ath5k_buf *bf;
1389 /* allocate descriptors */
1390 sc->desc_len = sizeof(struct ath5k_desc) *
1391 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
1392 sc->desc = pci_alloc_consistent(pdev, sc->desc_len, &sc->desc_daddr);
1393 if (sc->desc == NULL) {
1394 ATH5K_ERR(sc, "can't allocate descriptors\n");
1399 da = sc->desc_daddr;
1400 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
1401 ds, sc->desc_len, (unsigned long long)sc->desc_daddr);
1403 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
1404 sizeof(struct ath5k_buf), GFP_KERNEL);
1406 ATH5K_ERR(sc, "can't allocate bufptr\n");
1412 INIT_LIST_HEAD(&sc->rxbuf);
1413 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
1416 list_add_tail(&bf->list, &sc->rxbuf);
1419 INIT_LIST_HEAD(&sc->txbuf);
1420 sc->txbuf_len = ATH_TXBUF;
1421 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++,
1422 da += sizeof(*ds)) {
1425 list_add_tail(&bf->list, &sc->txbuf);
1435 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1442 ath5k_desc_free(struct ath5k_softc *sc, struct pci_dev *pdev)
1444 struct ath5k_buf *bf;
1446 ath5k_txbuf_free(sc, sc->bbuf);
1447 list_for_each_entry(bf, &sc->txbuf, list)
1448 ath5k_txbuf_free(sc, bf);
1449 list_for_each_entry(bf, &sc->rxbuf, list)
1450 ath5k_rxbuf_free(sc, bf);
1452 /* Free memory associated with all descriptors */
1453 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1467 static struct ath5k_txq *
1468 ath5k_txq_setup(struct ath5k_softc *sc,
1469 int qtype, int subtype)
1471 struct ath5k_hw *ah = sc->ah;
1472 struct ath5k_txq *txq;
1473 struct ath5k_txq_info qi = {
1474 .tqi_subtype = subtype,
1475 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1476 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1477 .tqi_cw_max = AR5K_TXQ_USEDEFAULT
1482 * Enable interrupts only for EOL and DESC conditions.
1483 * We mark tx descriptors to receive a DESC interrupt
1484 * when a tx queue gets deep; otherwise waiting for the
1485 * EOL to reap descriptors. Note that this is done to
1486 * reduce interrupt load and this only defers reaping
1487 * descriptors, never transmitting frames. Aside from
1488 * reducing interrupts this also permits more concurrency.
1489 * The only potential downside is if the tx queue backs
1490 * up in which case the top half of the kernel may backup
1491 * due to a lack of tx descriptors.
1493 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
1494 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
1495 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
1498 * NB: don't print a message, this happens
1499 * normally on parts with too few tx queues
1501 return ERR_PTR(qnum);
1503 if (qnum >= ARRAY_SIZE(sc->txqs)) {
1504 ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n",
1505 qnum, ARRAY_SIZE(sc->txqs));
1506 ath5k_hw_release_tx_queue(ah, qnum);
1507 return ERR_PTR(-EINVAL);
1509 txq = &sc->txqs[qnum];
1513 INIT_LIST_HEAD(&txq->q);
1514 spin_lock_init(&txq->lock);
1517 return &sc->txqs[qnum];
1521 ath5k_beaconq_setup(struct ath5k_hw *ah)
1523 struct ath5k_txq_info qi = {
1524 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1525 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1526 .tqi_cw_max = AR5K_TXQ_USEDEFAULT,
1527 /* NB: for dynamic turbo, don't enable any other interrupts */
1528 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
1531 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
1535 ath5k_beaconq_config(struct ath5k_softc *sc)
1537 struct ath5k_hw *ah = sc->ah;
1538 struct ath5k_txq_info qi;
1541 ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi);
1545 if (sc->opmode == NL80211_IFTYPE_AP ||
1546 sc->opmode == NL80211_IFTYPE_MESH_POINT) {
1548 * Always burst out beacon and CAB traffic
1549 * (aifs = cwmin = cwmax = 0)
1554 } else if (sc->opmode == NL80211_IFTYPE_ADHOC) {
1556 * Adhoc mode; backoff between 0 and (2 * cw_min).
1560 qi.tqi_cw_max = 2 * ah->ah_cw_min;
1563 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1564 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1565 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
1567 ret = ath5k_hw_set_tx_queueprops(ah, sc->bhalq, &qi);
1569 ATH5K_ERR(sc, "%s: unable to update parameters for beacon "
1570 "hardware queue!\n", __func__);
1573 ret = ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */
1577 /* reconfigure cabq with ready time to 80% of beacon_interval */
1578 ret = ath5k_hw_get_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi);
1582 qi.tqi_ready_time = (sc->bintval * 80) / 100;
1583 ret = ath5k_hw_set_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi);
1587 ret = ath5k_hw_reset_tx_queue(ah, AR5K_TX_QUEUE_ID_CAB);
1593 ath5k_txq_drainq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1595 struct ath5k_buf *bf, *bf0;
1598 * NB: this assumes output has been stopped and
1599 * we do not need to block ath5k_tx_tasklet
1601 spin_lock_bh(&txq->lock);
1602 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1603 ath5k_debug_printtxbuf(sc, bf);
1605 ath5k_txbuf_free(sc, bf);
1607 spin_lock_bh(&sc->txbuflock);
1608 list_move_tail(&bf->list, &sc->txbuf);
1610 spin_unlock_bh(&sc->txbuflock);
1613 spin_unlock_bh(&txq->lock);
1617 * Drain the transmit queues and reclaim resources.
1620 ath5k_txq_cleanup(struct ath5k_softc *sc)
1622 struct ath5k_hw *ah = sc->ah;
1625 /* XXX return value */
1626 if (likely(!test_bit(ATH_STAT_INVALID, sc->status))) {
1627 /* don't touch the hardware if marked invalid */
1628 ath5k_hw_stop_tx_dma(ah, sc->bhalq);
1629 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "beacon queue %x\n",
1630 ath5k_hw_get_txdp(ah, sc->bhalq));
1631 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1632 if (sc->txqs[i].setup) {
1633 ath5k_hw_stop_tx_dma(ah, sc->txqs[i].qnum);
1634 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "txq [%u] %x, "
1637 ath5k_hw_get_txdp(ah,
1643 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1644 if (sc->txqs[i].setup)
1645 ath5k_txq_drainq(sc, &sc->txqs[i]);
1649 ath5k_txq_release(struct ath5k_softc *sc)
1651 struct ath5k_txq *txq = sc->txqs;
1654 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++)
1656 ath5k_hw_release_tx_queue(sc->ah, txq->qnum);
1669 * Enable the receive h/w following a reset.
1672 ath5k_rx_start(struct ath5k_softc *sc)
1674 struct ath5k_hw *ah = sc->ah;
1675 struct ath_common *common = ath5k_hw_common(ah);
1676 struct ath5k_buf *bf;
1679 common->rx_bufsize = roundup(IEEE80211_MAX_LEN, common->cachelsz);
1681 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rx_bufsize %u\n",
1682 common->cachelsz, common->rx_bufsize);
1684 spin_lock_bh(&sc->rxbuflock);
1686 list_for_each_entry(bf, &sc->rxbuf, list) {
1687 ret = ath5k_rxbuf_setup(sc, bf);
1689 spin_unlock_bh(&sc->rxbuflock);
1693 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1694 ath5k_hw_set_rxdp(ah, bf->daddr);
1695 spin_unlock_bh(&sc->rxbuflock);
1697 ath5k_hw_start_rx_dma(ah); /* enable recv descriptors */
1698 ath5k_mode_setup(sc); /* set filters, etc. */
1699 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */
1707 * Disable the receive h/w in preparation for a reset.
1710 ath5k_rx_stop(struct ath5k_softc *sc)
1712 struct ath5k_hw *ah = sc->ah;
1714 ath5k_hw_stop_rx_pcu(ah); /* disable PCU */
1715 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */
1716 ath5k_hw_stop_rx_dma(ah); /* disable DMA engine */
1718 ath5k_debug_printrxbuffs(sc, ah);
1720 sc->rxlink = NULL; /* just in case */
1724 ath5k_rx_decrypted(struct ath5k_softc *sc, struct ath5k_desc *ds,
1725 struct sk_buff *skb, struct ath5k_rx_status *rs)
1727 struct ath5k_hw *ah = sc->ah;
1728 struct ath_common *common = ath5k_hw_common(ah);
1729 struct ieee80211_hdr *hdr = (void *)skb->data;
1730 unsigned int keyix, hlen;
1732 if (!(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1733 rs->rs_keyix != AR5K_RXKEYIX_INVALID)
1734 return RX_FLAG_DECRYPTED;
1736 /* Apparently when a default key is used to decrypt the packet
1737 the hw does not set the index used to decrypt. In such cases
1738 get the index from the packet. */
1739 hlen = ieee80211_hdrlen(hdr->frame_control);
1740 if (ieee80211_has_protected(hdr->frame_control) &&
1741 !(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1742 skb->len >= hlen + 4) {
1743 keyix = skb->data[hlen + 3] >> 6;
1745 if (test_bit(keyix, common->keymap))
1746 return RX_FLAG_DECRYPTED;
1754 ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb,
1755 struct ieee80211_rx_status *rxs)
1757 struct ath_common *common = ath5k_hw_common(sc->ah);
1760 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1762 if (ieee80211_is_beacon(mgmt->frame_control) &&
1763 le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS &&
1764 memcmp(mgmt->bssid, common->curbssid, ETH_ALEN) == 0) {
1766 * Received an IBSS beacon with the same BSSID. Hardware *must*
1767 * have updated the local TSF. We have to work around various
1768 * hardware bugs, though...
1770 tsf = ath5k_hw_get_tsf64(sc->ah);
1771 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp);
1772 hw_tu = TSF_TO_TU(tsf);
1774 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1775 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
1776 (unsigned long long)bc_tstamp,
1777 (unsigned long long)rxs->mactime,
1778 (unsigned long long)(rxs->mactime - bc_tstamp),
1779 (unsigned long long)tsf);
1782 * Sometimes the HW will give us a wrong tstamp in the rx
1783 * status, causing the timestamp extension to go wrong.
1784 * (This seems to happen especially with beacon frames bigger
1785 * than 78 byte (incl. FCS))
1786 * But we know that the receive timestamp must be later than the
1787 * timestamp of the beacon since HW must have synced to that.
1789 * NOTE: here we assume mactime to be after the frame was
1790 * received, not like mac80211 which defines it at the start.
1792 if (bc_tstamp > rxs->mactime) {
1793 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1794 "fixing mactime from %llx to %llx\n",
1795 (unsigned long long)rxs->mactime,
1796 (unsigned long long)tsf);
1801 * Local TSF might have moved higher than our beacon timers,
1802 * in that case we have to update them to continue sending
1803 * beacons. This also takes care of synchronizing beacon sending
1804 * times with other stations.
1806 if (hw_tu >= sc->nexttbtt)
1807 ath5k_beacon_update_timers(sc, bc_tstamp);
1812 ath5k_update_beacon_rssi(struct ath5k_softc *sc, struct sk_buff *skb, int rssi)
1814 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1815 struct ath5k_hw *ah = sc->ah;
1816 struct ath_common *common = ath5k_hw_common(ah);
1818 /* only beacons from our BSSID */
1819 if (!ieee80211_is_beacon(mgmt->frame_control) ||
1820 memcmp(mgmt->bssid, common->curbssid, ETH_ALEN) != 0)
1823 ah->ah_beacon_rssi_avg = ath5k_moving_average(ah->ah_beacon_rssi_avg,
1826 /* in IBSS mode we should keep RSSI statistics per neighbour */
1827 /* le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS */
1831 * Compute padding position. skb must contains an IEEE 802.11 frame
1833 static int ath5k_common_padpos(struct sk_buff *skb)
1835 struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data;
1836 __le16 frame_control = hdr->frame_control;
1839 if (ieee80211_has_a4(frame_control)) {
1842 if (ieee80211_is_data_qos(frame_control)) {
1843 padpos += IEEE80211_QOS_CTL_LEN;
1850 * This function expects a 802.11 frame and returns the number of
1851 * bytes added, or -1 if we don't have enought header room.
1854 static int ath5k_add_padding(struct sk_buff *skb)
1856 int padpos = ath5k_common_padpos(skb);
1857 int padsize = padpos & 3;
1859 if (padsize && skb->len>padpos) {
1861 if (skb_headroom(skb) < padsize)
1864 skb_push(skb, padsize);
1865 memmove(skb->data, skb->data+padsize, padpos);
1873 * This function expects a 802.11 frame and returns the number of
1877 static int ath5k_remove_padding(struct sk_buff *skb)
1879 int padpos = ath5k_common_padpos(skb);
1880 int padsize = padpos & 3;
1882 if (padsize && skb->len>=padpos+padsize) {
1883 memmove(skb->data + padsize, skb->data, padpos);
1884 skb_pull(skb, padsize);
1892 ath5k_tasklet_rx(unsigned long data)
1894 struct ieee80211_rx_status *rxs;
1895 struct ath5k_rx_status rs = {};
1896 struct sk_buff *skb, *next_skb;
1897 dma_addr_t next_skb_addr;
1898 struct ath5k_softc *sc = (void *)data;
1899 struct ath5k_hw *ah = sc->ah;
1900 struct ath_common *common = ath5k_hw_common(ah);
1901 struct ath5k_buf *bf;
1902 struct ath5k_desc *ds;
1906 spin_lock(&sc->rxbuflock);
1907 if (list_empty(&sc->rxbuf)) {
1908 ATH5K_WARN(sc, "empty rx buf pool\n");
1914 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1915 BUG_ON(bf->skb == NULL);
1919 /* bail if HW is still using self-linked descriptor */
1920 if (ath5k_hw_get_rxdp(sc->ah) == bf->daddr)
1923 ret = sc->ah->ah_proc_rx_desc(sc->ah, ds, &rs);
1924 if (unlikely(ret == -EINPROGRESS))
1926 else if (unlikely(ret)) {
1927 ATH5K_ERR(sc, "error in processing rx descriptor\n");
1928 sc->stats.rxerr_proc++;
1929 spin_unlock(&sc->rxbuflock);
1933 sc->stats.rx_all_count++;
1935 if (unlikely(rs.rs_more)) {
1936 ATH5K_WARN(sc, "unsupported jumbo\n");
1937 sc->stats.rxerr_jumbo++;
1941 if (unlikely(rs.rs_status)) {
1942 if (rs.rs_status & AR5K_RXERR_CRC)
1943 sc->stats.rxerr_crc++;
1944 if (rs.rs_status & AR5K_RXERR_FIFO)
1945 sc->stats.rxerr_fifo++;
1946 if (rs.rs_status & AR5K_RXERR_PHY) {
1947 sc->stats.rxerr_phy++;
1948 if (rs.rs_phyerr > 0 && rs.rs_phyerr < 32)
1949 sc->stats.rxerr_phy_code[rs.rs_phyerr]++;
1952 if (rs.rs_status & AR5K_RXERR_DECRYPT) {
1954 * Decrypt error. If the error occurred
1955 * because there was no hardware key, then
1956 * let the frame through so the upper layers
1957 * can process it. This is necessary for 5210
1958 * parts which have no way to setup a ``clear''
1961 * XXX do key cache faulting
1963 sc->stats.rxerr_decrypt++;
1964 if (rs.rs_keyix == AR5K_RXKEYIX_INVALID &&
1965 !(rs.rs_status & AR5K_RXERR_CRC))
1968 if (rs.rs_status & AR5K_RXERR_MIC) {
1969 rx_flag |= RX_FLAG_MMIC_ERROR;
1970 sc->stats.rxerr_mic++;
1974 /* let crypto-error packets fall through in MNTR */
1976 ~(AR5K_RXERR_DECRYPT|AR5K_RXERR_MIC)) ||
1977 sc->opmode != NL80211_IFTYPE_MONITOR)
1981 next_skb = ath5k_rx_skb_alloc(sc, &next_skb_addr);
1984 * If we can't replace bf->skb with a new skb under memory
1985 * pressure, just skip this packet
1990 pci_unmap_single(sc->pdev, bf->skbaddr, common->rx_bufsize,
1991 PCI_DMA_FROMDEVICE);
1992 skb_put(skb, rs.rs_datalen);
1994 /* The MAC header is padded to have 32-bit boundary if the
1995 * packet payload is non-zero. The general calculation for
1996 * padsize would take into account odd header lengths:
1997 * padsize = (4 - hdrlen % 4) % 4; However, since only
1998 * even-length headers are used, padding can only be 0 or 2
1999 * bytes and we can optimize this a bit. In addition, we must
2000 * not try to remove padding from short control frames that do
2001 * not have payload. */
2002 ath5k_remove_padding(skb);
2004 rxs = IEEE80211_SKB_RXCB(skb);
2007 * always extend the mac timestamp, since this information is
2008 * also needed for proper IBSS merging.
2010 * XXX: it might be too late to do it here, since rs_tstamp is
2011 * 15bit only. that means TSF extension has to be done within
2012 * 32768usec (about 32ms). it might be necessary to move this to
2013 * the interrupt handler, like it is done in madwifi.
2015 * Unfortunately we don't know when the hardware takes the rx
2016 * timestamp (beginning of phy frame, data frame, end of rx?).
2017 * The only thing we know is that it is hardware specific...
2018 * On AR5213 it seems the rx timestamp is at the end of the
2019 * frame, but i'm not sure.
2021 * NOTE: mac80211 defines mactime at the beginning of the first
2022 * data symbol. Since we don't have any time references it's
2023 * impossible to comply to that. This affects IBSS merge only
2024 * right now, so it's not too bad...
2026 rxs->mactime = ath5k_extend_tsf(sc->ah, rs.rs_tstamp);
2027 rxs->flag = rx_flag | RX_FLAG_TSFT;
2029 rxs->freq = sc->curchan->center_freq;
2030 rxs->band = sc->curband->band;
2032 rxs->noise = sc->ah->ah_noise_floor;
2033 rxs->signal = rxs->noise + rs.rs_rssi;
2035 rxs->antenna = rs.rs_antenna;
2037 if (rs.rs_antenna > 0 && rs.rs_antenna < 5)
2038 sc->stats.antenna_rx[rs.rs_antenna]++;
2040 sc->stats.antenna_rx[0]++; /* invalid */
2042 rxs->rate_idx = ath5k_hw_to_driver_rix(sc, rs.rs_rate);
2043 rxs->flag |= ath5k_rx_decrypted(sc, ds, skb, &rs);
2045 if (rxs->rate_idx >= 0 && rs.rs_rate ==
2046 sc->curband->bitrates[rxs->rate_idx].hw_value_short)
2047 rxs->flag |= RX_FLAG_SHORTPRE;
2049 ath5k_debug_dump_skb(sc, skb, "RX ", 0);
2051 ath5k_update_beacon_rssi(sc, skb, rs.rs_rssi);
2053 /* check beacons in IBSS mode */
2054 if (sc->opmode == NL80211_IFTYPE_ADHOC)
2055 ath5k_check_ibss_tsf(sc, skb, rxs);
2057 ieee80211_rx(sc->hw, skb);
2060 bf->skbaddr = next_skb_addr;
2062 list_move_tail(&bf->list, &sc->rxbuf);
2063 } while (ath5k_rxbuf_setup(sc, bf) == 0);
2065 spin_unlock(&sc->rxbuflock);
2076 ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
2078 struct ath5k_tx_status ts = {};
2079 struct ath5k_buf *bf, *bf0;
2080 struct ath5k_desc *ds;
2081 struct sk_buff *skb;
2082 struct ieee80211_tx_info *info;
2085 spin_lock(&txq->lock);
2086 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
2090 * It's possible that the hardware can say the buffer is
2091 * completed when it hasn't yet loaded the ds_link from
2092 * host memory and moved on. If there are more TX
2093 * descriptors in the queue, wait for TXDP to change
2094 * before processing this one.
2096 if (ath5k_hw_get_txdp(sc->ah, txq->qnum) == bf->daddr &&
2097 !list_is_last(&bf->list, &txq->q))
2100 ret = sc->ah->ah_proc_tx_desc(sc->ah, ds, &ts);
2101 if (unlikely(ret == -EINPROGRESS))
2103 else if (unlikely(ret)) {
2104 ATH5K_ERR(sc, "error %d while processing queue %u\n",
2109 sc->stats.tx_all_count++;
2111 info = IEEE80211_SKB_CB(skb);
2114 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len,
2117 ieee80211_tx_info_clear_status(info);
2118 for (i = 0; i < 4; i++) {
2119 struct ieee80211_tx_rate *r =
2120 &info->status.rates[i];
2122 if (ts.ts_rate[i]) {
2123 r->idx = ath5k_hw_to_driver_rix(sc, ts.ts_rate[i]);
2124 r->count = ts.ts_retry[i];
2131 /* count the successful attempt as well */
2132 info->status.rates[ts.ts_final_idx].count++;
2134 if (unlikely(ts.ts_status)) {
2135 sc->stats.ack_fail++;
2136 if (ts.ts_status & AR5K_TXERR_FILT) {
2137 info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
2138 sc->stats.txerr_filt++;
2140 if (ts.ts_status & AR5K_TXERR_XRETRY)
2141 sc->stats.txerr_retry++;
2142 if (ts.ts_status & AR5K_TXERR_FIFO)
2143 sc->stats.txerr_fifo++;
2145 info->flags |= IEEE80211_TX_STAT_ACK;
2146 info->status.ack_signal = ts.ts_rssi;
2150 * Remove MAC header padding before giving the frame
2153 ath5k_remove_padding(skb);
2155 if (ts.ts_antenna > 0 && ts.ts_antenna < 5)
2156 sc->stats.antenna_tx[ts.ts_antenna]++;
2158 sc->stats.antenna_tx[0]++; /* invalid */
2160 ieee80211_tx_status(sc->hw, skb);
2162 spin_lock(&sc->txbuflock);
2163 list_move_tail(&bf->list, &sc->txbuf);
2165 spin_unlock(&sc->txbuflock);
2167 if (likely(list_empty(&txq->q)))
2169 spin_unlock(&txq->lock);
2170 if (sc->txbuf_len > ATH_TXBUF / 5)
2171 ieee80211_wake_queues(sc->hw);
2175 ath5k_tasklet_tx(unsigned long data)
2178 struct ath5k_softc *sc = (void *)data;
2180 for (i=0; i < AR5K_NUM_TX_QUEUES; i++)
2181 if (sc->txqs[i].setup && (sc->ah->ah_txq_isr & BIT(i)))
2182 ath5k_tx_processq(sc, &sc->txqs[i]);
2191 * Setup the beacon frame for transmit.
2194 ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
2196 struct sk_buff *skb = bf->skb;
2197 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2198 struct ath5k_hw *ah = sc->ah;
2199 struct ath5k_desc *ds;
2203 const int padsize = 0;
2205 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
2207 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
2208 "skbaddr %llx\n", skb, skb->data, skb->len,
2209 (unsigned long long)bf->skbaddr);
2210 if (pci_dma_mapping_error(sc->pdev, bf->skbaddr)) {
2211 ATH5K_ERR(sc, "beacon DMA mapping failed\n");
2216 antenna = ah->ah_tx_ant;
2218 flags = AR5K_TXDESC_NOACK;
2219 if (sc->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) {
2220 ds->ds_link = bf->daddr; /* self-linked */
2221 flags |= AR5K_TXDESC_VEOL;
2226 * If we use multiple antennas on AP and use
2227 * the Sectored AP scenario, switch antenna every
2228 * 4 beacons to make sure everybody hears our AP.
2229 * When a client tries to associate, hw will keep
2230 * track of the tx antenna to be used for this client
2231 * automaticaly, based on ACKed packets.
2233 * Note: AP still listens and transmits RTS on the
2234 * default antenna which is supposed to be an omni.
2236 * Note2: On sectored scenarios it's possible to have
2237 * multiple antennas (1omni -the default- and 14 sectors)
2238 * so if we choose to actually support this mode we need
2239 * to allow user to set how many antennas we have and tweak
2240 * the code below to send beacons on all of them.
2242 if (ah->ah_ant_mode == AR5K_ANTMODE_SECTOR_AP)
2243 antenna = sc->bsent & 4 ? 2 : 1;
2246 /* FIXME: If we are in g mode and rate is a CCK rate
2247 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
2248 * from tx power (value is in dB units already) */
2249 ds->ds_data = bf->skbaddr;
2250 ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
2251 ieee80211_get_hdrlen_from_skb(skb), padsize,
2252 AR5K_PKT_TYPE_BEACON, (sc->power_level * 2),
2253 ieee80211_get_tx_rate(sc->hw, info)->hw_value,
2254 1, AR5K_TXKEYIX_INVALID,
2255 antenna, flags, 0, 0);
2261 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
2266 * Transmit a beacon frame at SWBA. Dynamic updates to the
2267 * frame contents are done as needed and the slot time is
2268 * also adjusted based on current state.
2270 * This is called from software irq context (beacontq or restq
2271 * tasklets) or user context from ath5k_beacon_config.
2274 ath5k_beacon_send(struct ath5k_softc *sc)
2276 struct ath5k_buf *bf = sc->bbuf;
2277 struct ath5k_hw *ah = sc->ah;
2278 struct sk_buff *skb;
2280 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n");
2282 if (unlikely(bf->skb == NULL || sc->opmode == NL80211_IFTYPE_STATION ||
2283 sc->opmode == NL80211_IFTYPE_MONITOR)) {
2284 ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
2288 * Check if the previous beacon has gone out. If
2289 * not don't don't try to post another, skip this
2290 * period and wait for the next. Missed beacons
2291 * indicate a problem and should not occur. If we
2292 * miss too many consecutive beacons reset the device.
2294 if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) {
2296 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2297 "missed %u consecutive beacons\n", sc->bmisscount);
2298 if (sc->bmisscount > 10) { /* NB: 10 is a guess */
2299 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2300 "stuck beacon time (%u missed)\n",
2302 tasklet_schedule(&sc->restq);
2306 if (unlikely(sc->bmisscount != 0)) {
2307 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2308 "resume beacon xmit after %u misses\n",
2314 * Stop any current dma and put the new frame on the queue.
2315 * This should never fail since we check above that no frames
2316 * are still pending on the queue.
2318 if (unlikely(ath5k_hw_stop_tx_dma(ah, sc->bhalq))) {
2319 ATH5K_WARN(sc, "beacon queue %u didn't start/stop ?\n", sc->bhalq);
2320 /* NB: hw still stops DMA, so proceed */
2323 /* refresh the beacon for AP mode */
2324 if (sc->opmode == NL80211_IFTYPE_AP)
2325 ath5k_beacon_update(sc->hw, sc->vif);
2327 ath5k_hw_set_txdp(ah, sc->bhalq, bf->daddr);
2328 ath5k_hw_start_tx_dma(ah, sc->bhalq);
2329 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
2330 sc->bhalq, (unsigned long long)bf->daddr, bf->desc);
2332 skb = ieee80211_get_buffered_bc(sc->hw, sc->vif);
2334 ath5k_tx_queue(sc->hw, skb, sc->cabq);
2335 skb = ieee80211_get_buffered_bc(sc->hw, sc->vif);
2343 * ath5k_beacon_update_timers - update beacon timers
2345 * @sc: struct ath5k_softc pointer we are operating on
2346 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
2347 * beacon timer update based on the current HW TSF.
2349 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
2350 * of a received beacon or the current local hardware TSF and write it to the
2351 * beacon timer registers.
2353 * This is called in a variety of situations, e.g. when a beacon is received,
2354 * when a TSF update has been detected, but also when an new IBSS is created or
2355 * when we otherwise know we have to update the timers, but we keep it in this
2356 * function to have it all together in one place.
2359 ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
2361 struct ath5k_hw *ah = sc->ah;
2362 u32 nexttbtt, intval, hw_tu, bc_tu;
2365 intval = sc->bintval & AR5K_BEACON_PERIOD;
2366 if (WARN_ON(!intval))
2369 /* beacon TSF converted to TU */
2370 bc_tu = TSF_TO_TU(bc_tsf);
2372 /* current TSF converted to TU */
2373 hw_tsf = ath5k_hw_get_tsf64(ah);
2374 hw_tu = TSF_TO_TU(hw_tsf);
2377 /* we use FUDGE to make sure the next TBTT is ahead of the current TU */
2380 * no beacons received, called internally.
2381 * just need to refresh timers based on HW TSF.
2383 nexttbtt = roundup(hw_tu + FUDGE, intval);
2384 } else if (bc_tsf == 0) {
2386 * no beacon received, probably called by ath5k_reset_tsf().
2387 * reset TSF to start with 0.
2390 intval |= AR5K_BEACON_RESET_TSF;
2391 } else if (bc_tsf > hw_tsf) {
2393 * beacon received, SW merge happend but HW TSF not yet updated.
2394 * not possible to reconfigure timers yet, but next time we
2395 * receive a beacon with the same BSSID, the hardware will
2396 * automatically update the TSF and then we need to reconfigure
2399 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2400 "need to wait for HW TSF sync\n");
2404 * most important case for beacon synchronization between STA.
2406 * beacon received and HW TSF has been already updated by HW.
2407 * update next TBTT based on the TSF of the beacon, but make
2408 * sure it is ahead of our local TSF timer.
2410 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
2414 sc->nexttbtt = nexttbtt;
2416 intval |= AR5K_BEACON_ENA;
2417 ath5k_hw_init_beacon(ah, nexttbtt, intval);
2420 * debugging output last in order to preserve the time critical aspect
2424 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2425 "reconfigured timers based on HW TSF\n");
2426 else if (bc_tsf == 0)
2427 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2428 "reset HW TSF and timers\n");
2430 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2431 "updated timers based on beacon TSF\n");
2433 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2434 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2435 (unsigned long long) bc_tsf,
2436 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
2437 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
2438 intval & AR5K_BEACON_PERIOD,
2439 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
2440 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
2445 * ath5k_beacon_config - Configure the beacon queues and interrupts
2447 * @sc: struct ath5k_softc pointer we are operating on
2449 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
2450 * interrupts to detect TSF updates only.
2453 ath5k_beacon_config(struct ath5k_softc *sc)
2455 struct ath5k_hw *ah = sc->ah;
2456 unsigned long flags;
2458 spin_lock_irqsave(&sc->block, flags);
2460 sc->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA);
2462 if (sc->enable_beacon) {
2464 * In IBSS mode we use a self-linked tx descriptor and let the
2465 * hardware send the beacons automatically. We have to load it
2467 * We use the SWBA interrupt only to keep track of the beacon
2468 * timers in order to detect automatic TSF updates.
2470 ath5k_beaconq_config(sc);
2472 sc->imask |= AR5K_INT_SWBA;
2474 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
2475 if (ath5k_hw_hasveol(ah))
2476 ath5k_beacon_send(sc);
2478 ath5k_beacon_update_timers(sc, -1);
2480 ath5k_hw_stop_tx_dma(sc->ah, sc->bhalq);
2483 ath5k_hw_set_imr(ah, sc->imask);
2485 spin_unlock_irqrestore(&sc->block, flags);
2488 static void ath5k_tasklet_beacon(unsigned long data)
2490 struct ath5k_softc *sc = (struct ath5k_softc *) data;
2493 * Software beacon alert--time to send a beacon.
2495 * In IBSS mode we use this interrupt just to
2496 * keep track of the next TBTT (target beacon
2497 * transmission time) in order to detect wether
2498 * automatic TSF updates happened.
2500 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
2501 /* XXX: only if VEOL suppported */
2502 u64 tsf = ath5k_hw_get_tsf64(sc->ah);
2503 sc->nexttbtt += sc->bintval;
2504 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2505 "SWBA nexttbtt: %x hw_tu: %x "
2509 (unsigned long long) tsf);
2511 spin_lock(&sc->block);
2512 ath5k_beacon_send(sc);
2513 spin_unlock(&sc->block);
2518 /********************\
2519 * Interrupt handling *
2520 \********************/
2523 ath5k_init(struct ath5k_softc *sc)
2525 struct ath5k_hw *ah = sc->ah;
2528 mutex_lock(&sc->lock);
2530 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode);
2533 * Stop anything previously setup. This is safe
2534 * no matter this is the first time through or not.
2536 ath5k_stop_locked(sc);
2539 * The basic interface to setting the hardware in a good
2540 * state is ``reset''. On return the hardware is known to
2541 * be powered up and with interrupts disabled. This must
2542 * be followed by initialization of the appropriate bits
2543 * and then setup of the interrupt mask.
2545 sc->curchan = sc->hw->conf.channel;
2546 sc->curband = &sc->sbands[sc->curchan->band];
2547 sc->imask = AR5K_INT_RXOK | AR5K_INT_RXERR | AR5K_INT_RXEOL |
2548 AR5K_INT_RXORN | AR5K_INT_TXDESC | AR5K_INT_TXEOL |
2549 AR5K_INT_FATAL | AR5K_INT_GLOBAL | AR5K_INT_MIB;
2551 ret = ath5k_reset(sc, NULL);
2555 ath5k_rfkill_hw_start(ah);
2558 * Reset the key cache since some parts do not reset the
2559 * contents on initial power up or resume from suspend.
2561 for (i = 0; i < AR5K_KEYTABLE_SIZE; i++)
2562 ath5k_hw_reset_key(ah, i);
2564 ath5k_hw_set_ack_bitrate_high(ah, true);
2568 mutex_unlock(&sc->lock);
2573 ath5k_stop_locked(struct ath5k_softc *sc)
2575 struct ath5k_hw *ah = sc->ah;
2577 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n",
2578 test_bit(ATH_STAT_INVALID, sc->status));
2581 * Shutdown the hardware and driver:
2582 * stop output from above
2583 * disable interrupts
2585 * turn off the radio
2586 * clear transmit machinery
2587 * clear receive machinery
2588 * drain and release tx queues
2589 * reclaim beacon resources
2590 * power down hardware
2592 * Note that some of this work is not possible if the
2593 * hardware is gone (invalid).
2595 ieee80211_stop_queues(sc->hw);
2597 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2599 ath5k_hw_set_imr(ah, 0);
2600 synchronize_irq(sc->pdev->irq);
2602 ath5k_txq_cleanup(sc);
2603 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2605 ath5k_hw_phy_disable(ah);
2613 * Stop the device, grabbing the top-level lock to protect
2614 * against concurrent entry through ath5k_init (which can happen
2615 * if another thread does a system call and the thread doing the
2616 * stop is preempted).
2619 ath5k_stop_hw(struct ath5k_softc *sc)
2623 mutex_lock(&sc->lock);
2624 ret = ath5k_stop_locked(sc);
2625 if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) {
2627 * Don't set the card in full sleep mode!
2629 * a) When the device is in this state it must be carefully
2630 * woken up or references to registers in the PCI clock
2631 * domain may freeze the bus (and system). This varies
2632 * by chip and is mostly an issue with newer parts
2633 * (madwifi sources mentioned srev >= 0x78) that go to
2634 * sleep more quickly.
2636 * b) On older chips full sleep results a weird behaviour
2637 * during wakeup. I tested various cards with srev < 0x78
2638 * and they don't wake up after module reload, a second
2639 * module reload is needed to bring the card up again.
2641 * Until we figure out what's going on don't enable
2642 * full chip reset on any chip (this is what Legacy HAL
2643 * and Sam's HAL do anyway). Instead Perform a full reset
2644 * on the device (same as initial state after attach) and
2645 * leave it idle (keep MAC/BB on warm reset) */
2646 ret = ath5k_hw_on_hold(sc->ah);
2648 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2649 "putting device to sleep\n");
2651 ath5k_txbuf_free(sc, sc->bbuf);
2654 mutex_unlock(&sc->lock);
2656 tasklet_kill(&sc->rxtq);
2657 tasklet_kill(&sc->txtq);
2658 tasklet_kill(&sc->restq);
2659 tasklet_kill(&sc->calib);
2660 tasklet_kill(&sc->beacontq);
2661 tasklet_kill(&sc->ani_tasklet);
2663 ath5k_rfkill_hw_stop(sc->ah);
2669 ath5k_intr_calibration_poll(struct ath5k_hw *ah)
2671 if (time_is_before_eq_jiffies(ah->ah_cal_next_ani) &&
2672 !(ah->ah_cal_mask & AR5K_CALIBRATION_FULL)) {
2673 /* run ANI only when full calibration is not active */
2674 ah->ah_cal_next_ani = jiffies +
2675 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_ANI);
2676 tasklet_schedule(&ah->ah_sc->ani_tasklet);
2678 } else if (time_is_before_eq_jiffies(ah->ah_cal_next_full)) {
2679 ah->ah_cal_next_full = jiffies +
2680 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_FULL);
2681 tasklet_schedule(&ah->ah_sc->calib);
2683 /* we could use SWI to generate enough interrupts to meet our
2684 * calibration interval requirements, if necessary:
2685 * AR5K_REG_ENABLE_BITS(ah, AR5K_CR, AR5K_CR_SWI); */
2689 ath5k_intr(int irq, void *dev_id)
2691 struct ath5k_softc *sc = dev_id;
2692 struct ath5k_hw *ah = sc->ah;
2693 enum ath5k_int status;
2694 unsigned int counter = 1000;
2696 if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) ||
2697 !ath5k_hw_is_intr_pending(ah)))
2701 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */
2702 ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2704 if (unlikely(status & AR5K_INT_FATAL)) {
2706 * Fatal errors are unrecoverable.
2707 * Typically these are caused by DMA errors.
2709 tasklet_schedule(&sc->restq);
2710 } else if (unlikely(status & AR5K_INT_RXORN)) {
2712 * Receive buffers are full. Either the bus is busy or
2713 * the CPU is not fast enough to process all received
2715 * Older chipsets need a reset to come out of this
2716 * condition, but we treat it as RX for newer chips.
2717 * We don't know exactly which versions need a reset -
2718 * this guess is copied from the HAL.
2720 sc->stats.rxorn_intr++;
2721 if (ah->ah_mac_srev < AR5K_SREV_AR5212)
2722 tasklet_schedule(&sc->restq);
2724 tasklet_schedule(&sc->rxtq);
2726 if (status & AR5K_INT_SWBA) {
2727 tasklet_hi_schedule(&sc->beacontq);
2729 if (status & AR5K_INT_RXEOL) {
2731 * NB: the hardware should re-read the link when
2732 * RXE bit is written, but it doesn't work at
2733 * least on older hardware revs.
2737 if (status & AR5K_INT_TXURN) {
2738 /* bump tx trigger level */
2739 ath5k_hw_update_tx_triglevel(ah, true);
2741 if (status & (AR5K_INT_RXOK | AR5K_INT_RXERR))
2742 tasklet_schedule(&sc->rxtq);
2743 if (status & (AR5K_INT_TXOK | AR5K_INT_TXDESC
2744 | AR5K_INT_TXERR | AR5K_INT_TXEOL))
2745 tasklet_schedule(&sc->txtq);
2746 if (status & AR5K_INT_BMISS) {
2749 if (status & AR5K_INT_MIB) {
2750 sc->stats.mib_intr++;
2751 ath5k_hw_update_mib_counters(ah);
2752 ath5k_ani_mib_intr(ah);
2754 if (status & AR5K_INT_GPIO)
2755 tasklet_schedule(&sc->rf_kill.toggleq);
2758 } while (ath5k_hw_is_intr_pending(ah) && --counter > 0);
2760 if (unlikely(!counter))
2761 ATH5K_WARN(sc, "too many interrupts, giving up for now\n");
2763 ath5k_intr_calibration_poll(ah);
2769 ath5k_tasklet_reset(unsigned long data)
2771 struct ath5k_softc *sc = (void *)data;
2773 ath5k_reset_wake(sc);
2777 * Periodically recalibrate the PHY to account
2778 * for temperature/environment changes.
2781 ath5k_tasklet_calibrate(unsigned long data)
2783 struct ath5k_softc *sc = (void *)data;
2784 struct ath5k_hw *ah = sc->ah;
2786 /* Only full calibration for now */
2787 ah->ah_cal_mask |= AR5K_CALIBRATION_FULL;
2789 /* Stop queues so that calibration
2790 * doesn't interfere with tx */
2791 ieee80211_stop_queues(sc->hw);
2793 ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
2794 ieee80211_frequency_to_channel(sc->curchan->center_freq),
2795 sc->curchan->hw_value);
2797 if (ath5k_hw_gainf_calibrate(ah) == AR5K_RFGAIN_NEED_CHANGE) {
2799 * Rfgain is out of bounds, reset the chip
2800 * to load new gain values.
2802 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n");
2803 ath5k_reset(sc, sc->curchan);
2805 if (ath5k_hw_phy_calibrate(ah, sc->curchan))
2806 ATH5K_ERR(sc, "calibration of channel %u failed\n",
2807 ieee80211_frequency_to_channel(
2808 sc->curchan->center_freq));
2811 ieee80211_wake_queues(sc->hw);
2813 ah->ah_cal_mask &= ~AR5K_CALIBRATION_FULL;
2818 ath5k_tasklet_ani(unsigned long data)
2820 struct ath5k_softc *sc = (void *)data;
2821 struct ath5k_hw *ah = sc->ah;
2823 ah->ah_cal_mask |= AR5K_CALIBRATION_ANI;
2824 ath5k_ani_calibration(ah);
2825 ah->ah_cal_mask &= ~AR5K_CALIBRATION_ANI;
2829 /********************\
2830 * Mac80211 functions *
2831 \********************/
2834 ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
2836 struct ath5k_softc *sc = hw->priv;
2838 return ath5k_tx_queue(hw, skb, sc->txq);
2841 static int ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
2842 struct ath5k_txq *txq)
2844 struct ath5k_softc *sc = hw->priv;
2845 struct ath5k_buf *bf;
2846 unsigned long flags;
2849 ath5k_debug_dump_skb(sc, skb, "TX ", 1);
2851 if (sc->opmode == NL80211_IFTYPE_MONITOR)
2852 ATH5K_DBG(sc, ATH5K_DEBUG_XMIT, "tx in monitor (scan?)\n");
2855 * the hardware expects the header padded to 4 byte boundaries
2856 * if this is not the case we add the padding after the header
2858 padsize = ath5k_add_padding(skb);
2860 ATH5K_ERR(sc, "tx hdrlen not %%4: not enough"
2861 " headroom to pad");
2865 spin_lock_irqsave(&sc->txbuflock, flags);
2866 if (list_empty(&sc->txbuf)) {
2867 ATH5K_ERR(sc, "no further txbuf available, dropping packet\n");
2868 spin_unlock_irqrestore(&sc->txbuflock, flags);
2869 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
2872 bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list);
2873 list_del(&bf->list);
2875 if (list_empty(&sc->txbuf))
2876 ieee80211_stop_queues(hw);
2877 spin_unlock_irqrestore(&sc->txbuflock, flags);
2881 if (ath5k_txbuf_setup(sc, bf, txq, padsize)) {
2883 spin_lock_irqsave(&sc->txbuflock, flags);
2884 list_add_tail(&bf->list, &sc->txbuf);
2886 spin_unlock_irqrestore(&sc->txbuflock, flags);
2889 return NETDEV_TX_OK;
2892 dev_kfree_skb_any(skb);
2893 return NETDEV_TX_OK;
2897 * Reset the hardware. If chan is not NULL, then also pause rx/tx
2898 * and change to the given channel.
2901 ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan)
2903 struct ath5k_hw *ah = sc->ah;
2906 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n");
2909 ath5k_hw_set_imr(ah, 0);
2910 ath5k_txq_cleanup(sc);
2914 sc->curband = &sc->sbands[chan->band];
2916 ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, chan != NULL);
2918 ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret);
2922 ret = ath5k_rx_start(sc);
2924 ATH5K_ERR(sc, "can't start recv logic\n");
2928 ath5k_ani_init(ah, ah->ah_sc->ani_state.ani_mode);
2931 * Change channels and update the h/w rate map if we're switching;
2932 * e.g. 11a to 11b/g.
2934 * We may be doing a reset in response to an ioctl that changes the
2935 * channel so update any state that might change as a result.
2939 /* ath5k_chan_change(sc, c); */
2941 ath5k_beacon_config(sc);
2942 /* intrs are enabled by ath5k_beacon_config */
2950 ath5k_reset_wake(struct ath5k_softc *sc)
2954 ret = ath5k_reset(sc, sc->curchan);
2956 ieee80211_wake_queues(sc->hw);
2961 static int ath5k_start(struct ieee80211_hw *hw)
2963 return ath5k_init(hw->priv);
2966 static void ath5k_stop(struct ieee80211_hw *hw)
2968 ath5k_stop_hw(hw->priv);
2971 static int ath5k_add_interface(struct ieee80211_hw *hw,
2972 struct ieee80211_vif *vif)
2974 struct ath5k_softc *sc = hw->priv;
2977 mutex_lock(&sc->lock);
2985 switch (vif->type) {
2986 case NL80211_IFTYPE_AP:
2987 case NL80211_IFTYPE_STATION:
2988 case NL80211_IFTYPE_ADHOC:
2989 case NL80211_IFTYPE_MESH_POINT:
2990 case NL80211_IFTYPE_MONITOR:
2991 sc->opmode = vif->type;
2998 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "add interface mode %d\n", sc->opmode);
3000 ath5k_hw_set_lladdr(sc->ah, vif->addr);
3001 ath5k_mode_setup(sc);
3005 mutex_unlock(&sc->lock);
3010 ath5k_remove_interface(struct ieee80211_hw *hw,
3011 struct ieee80211_vif *vif)
3013 struct ath5k_softc *sc = hw->priv;
3014 u8 mac[ETH_ALEN] = {};
3016 mutex_lock(&sc->lock);
3020 ath5k_hw_set_lladdr(sc->ah, mac);
3023 mutex_unlock(&sc->lock);
3027 * TODO: Phy disable/diversity etc
3030 ath5k_config(struct ieee80211_hw *hw, u32 changed)
3032 struct ath5k_softc *sc = hw->priv;
3033 struct ath5k_hw *ah = sc->ah;
3034 struct ieee80211_conf *conf = &hw->conf;
3037 mutex_lock(&sc->lock);
3039 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
3040 ret = ath5k_chan_set(sc, conf->channel);
3045 if ((changed & IEEE80211_CONF_CHANGE_POWER) &&
3046 (sc->power_level != conf->power_level)) {
3047 sc->power_level = conf->power_level;
3050 ath5k_hw_set_txpower_limit(ah, (conf->power_level * 2));
3054 * 1) Move this on config_interface and handle each case
3055 * separately eg. when we have only one STA vif, use
3056 * AR5K_ANTMODE_SINGLE_AP
3058 * 2) Allow the user to change antenna mode eg. when only
3059 * one antenna is present
3061 * 3) Allow the user to set default/tx antenna when possible
3063 * 4) Default mode should handle 90% of the cases, together
3064 * with fixed a/b and single AP modes we should be able to
3065 * handle 99%. Sectored modes are extreme cases and i still
3066 * haven't found a usage for them. If we decide to support them,
3067 * then we must allow the user to set how many tx antennas we
3070 ath5k_hw_set_antenna_mode(ah, ah->ah_ant_mode);
3073 mutex_unlock(&sc->lock);
3077 static u64 ath5k_prepare_multicast(struct ieee80211_hw *hw,
3078 int mc_count, struct dev_addr_list *mclist)
3087 for (i = 0; i < mc_count; i++) {
3090 /* calculate XOR of eight 6-bit values */
3091 val = get_unaligned_le32(mclist->dmi_addr + 0);
3092 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
3093 val = get_unaligned_le32(mclist->dmi_addr + 3);
3094 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
3096 mfilt[pos / 32] |= (1 << (pos % 32));
3097 /* XXX: we might be able to just do this instead,
3098 * but not sure, needs testing, if we do use this we'd
3099 * neet to inform below to not reset the mcast */
3100 /* ath5k_hw_set_mcast_filterindex(ah,
3101 * mclist->dmi_addr[5]); */
3102 mclist = mclist->next;
3105 return ((u64)(mfilt[1]) << 32) | mfilt[0];
3108 #define SUPPORTED_FIF_FLAGS \
3109 FIF_PROMISC_IN_BSS | FIF_ALLMULTI | FIF_FCSFAIL | \
3110 FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
3111 FIF_BCN_PRBRESP_PROMISC
3113 * o always accept unicast, broadcast, and multicast traffic
3114 * o multicast traffic for all BSSIDs will be enabled if mac80211
3116 * o maintain current state of phy ofdm or phy cck error reception.
3117 * If the hardware detects any of these type of errors then
3118 * ath5k_hw_get_rx_filter() will pass to us the respective
3119 * hardware filters to be able to receive these type of frames.
3120 * o probe request frames are accepted only when operating in
3121 * hostap, adhoc, or monitor modes
3122 * o enable promiscuous mode according to the interface state
3124 * - when operating in adhoc mode so the 802.11 layer creates
3125 * node table entries for peers,
3126 * - when operating in station mode for collecting rssi data when
3127 * the station is otherwise quiet, or
3130 static void ath5k_configure_filter(struct ieee80211_hw *hw,
3131 unsigned int changed_flags,
3132 unsigned int *new_flags,
3135 struct ath5k_softc *sc = hw->priv;
3136 struct ath5k_hw *ah = sc->ah;
3137 u32 mfilt[2], rfilt;
3139 mutex_lock(&sc->lock);
3141 mfilt[0] = multicast;
3142 mfilt[1] = multicast >> 32;
3144 /* Only deal with supported flags */
3145 changed_flags &= SUPPORTED_FIF_FLAGS;
3146 *new_flags &= SUPPORTED_FIF_FLAGS;
3148 /* If HW detects any phy or radar errors, leave those filters on.
3149 * Also, always enable Unicast, Broadcasts and Multicast
3150 * XXX: move unicast, bssid broadcasts and multicast to mac80211 */
3151 rfilt = (ath5k_hw_get_rx_filter(ah) & (AR5K_RX_FILTER_PHYERR)) |
3152 (AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST |
3153 AR5K_RX_FILTER_MCAST);
3155 if (changed_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) {
3156 if (*new_flags & FIF_PROMISC_IN_BSS) {
3157 rfilt |= AR5K_RX_FILTER_PROM;
3158 __set_bit(ATH_STAT_PROMISC, sc->status);
3160 __clear_bit(ATH_STAT_PROMISC, sc->status);
3164 /* Note, AR5K_RX_FILTER_MCAST is already enabled */
3165 if (*new_flags & FIF_ALLMULTI) {
3170 /* This is the best we can do */
3171 if (*new_flags & (FIF_FCSFAIL | FIF_PLCPFAIL))
3172 rfilt |= AR5K_RX_FILTER_PHYERR;
3174 /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
3175 * and probes for any BSSID, this needs testing */
3176 if (*new_flags & FIF_BCN_PRBRESP_PROMISC)
3177 rfilt |= AR5K_RX_FILTER_BEACON | AR5K_RX_FILTER_PROBEREQ;
3179 /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
3180 * set we should only pass on control frames for this
3181 * station. This needs testing. I believe right now this
3182 * enables *all* control frames, which is OK.. but
3183 * but we should see if we can improve on granularity */
3184 if (*new_flags & FIF_CONTROL)
3185 rfilt |= AR5K_RX_FILTER_CONTROL;
3187 /* Additional settings per mode -- this is per ath5k */
3189 /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */
3191 switch (sc->opmode) {
3192 case NL80211_IFTYPE_MESH_POINT:
3193 case NL80211_IFTYPE_MONITOR:
3194 rfilt |= AR5K_RX_FILTER_CONTROL |
3195 AR5K_RX_FILTER_BEACON |
3196 AR5K_RX_FILTER_PROBEREQ |
3197 AR5K_RX_FILTER_PROM;
3199 case NL80211_IFTYPE_AP:
3200 case NL80211_IFTYPE_ADHOC:
3201 rfilt |= AR5K_RX_FILTER_PROBEREQ |
3202 AR5K_RX_FILTER_BEACON;
3204 case NL80211_IFTYPE_STATION:
3206 rfilt |= AR5K_RX_FILTER_BEACON;
3212 ath5k_hw_set_rx_filter(ah, rfilt);
3214 /* Set multicast bits */
3215 ath5k_hw_set_mcast_filter(ah, mfilt[0], mfilt[1]);
3216 /* Set the cached hw filter flags, this will alter actually
3218 sc->filter_flags = rfilt;
3220 mutex_unlock(&sc->lock);
3224 ath5k_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
3225 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
3226 struct ieee80211_key_conf *key)
3228 struct ath5k_softc *sc = hw->priv;
3229 struct ath5k_hw *ah = sc->ah;
3230 struct ath_common *common = ath5k_hw_common(ah);
3233 if (modparam_nohwcrypt)
3236 if (sc->opmode == NL80211_IFTYPE_AP)
3244 if (sc->ah->ah_aes_support)
3253 mutex_lock(&sc->lock);
3257 ret = ath5k_hw_set_key(sc->ah, key->keyidx, key,
3258 sta ? sta->addr : NULL);
3260 ATH5K_ERR(sc, "can't set the key\n");
3263 __set_bit(key->keyidx, common->keymap);
3264 key->hw_key_idx = key->keyidx;
3265 key->flags |= (IEEE80211_KEY_FLAG_GENERATE_IV |
3266 IEEE80211_KEY_FLAG_GENERATE_MMIC);
3269 ath5k_hw_reset_key(sc->ah, key->keyidx);
3270 __clear_bit(key->keyidx, common->keymap);
3279 mutex_unlock(&sc->lock);
3284 ath5k_get_stats(struct ieee80211_hw *hw,
3285 struct ieee80211_low_level_stats *stats)
3287 struct ath5k_softc *sc = hw->priv;
3290 ath5k_hw_update_mib_counters(sc->ah);
3292 stats->dot11ACKFailureCount = sc->stats.ack_fail;
3293 stats->dot11RTSFailureCount = sc->stats.rts_fail;
3294 stats->dot11RTSSuccessCount = sc->stats.rts_ok;
3295 stats->dot11FCSErrorCount = sc->stats.fcs_error;
3300 static int ath5k_get_survey(struct ieee80211_hw *hw, int idx,
3301 struct survey_info *survey)
3303 struct ath5k_softc *sc = hw->priv;
3304 struct ieee80211_conf *conf = &hw->conf;
3309 survey->channel = conf->channel;
3310 survey->filled = SURVEY_INFO_NOISE_DBM;
3311 survey->noise = sc->ah->ah_noise_floor;
3317 ath5k_get_tsf(struct ieee80211_hw *hw)
3319 struct ath5k_softc *sc = hw->priv;
3321 return ath5k_hw_get_tsf64(sc->ah);
3325 ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
3327 struct ath5k_softc *sc = hw->priv;
3329 ath5k_hw_set_tsf64(sc->ah, tsf);
3333 ath5k_reset_tsf(struct ieee80211_hw *hw)
3335 struct ath5k_softc *sc = hw->priv;
3338 * in IBSS mode we need to update the beacon timers too.
3339 * this will also reset the TSF if we call it with 0
3341 if (sc->opmode == NL80211_IFTYPE_ADHOC)
3342 ath5k_beacon_update_timers(sc, 0);
3344 ath5k_hw_reset_tsf(sc->ah);
3348 * Updates the beacon that is sent by ath5k_beacon_send. For adhoc,
3349 * this is called only once at config_bss time, for AP we do it every
3350 * SWBA interrupt so that the TIM will reflect buffered frames.
3352 * Called with the beacon lock.
3355 ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
3358 struct ath5k_softc *sc = hw->priv;
3359 struct sk_buff *skb;
3361 if (WARN_ON(!vif)) {
3366 skb = ieee80211_beacon_get(hw, vif);
3373 ath5k_debug_dump_skb(sc, skb, "BC ", 1);
3375 ath5k_txbuf_free(sc, sc->bbuf);
3376 sc->bbuf->skb = skb;
3377 ret = ath5k_beacon_setup(sc, sc->bbuf);
3379 sc->bbuf->skb = NULL;
3385 set_beacon_filter(struct ieee80211_hw *hw, bool enable)
3387 struct ath5k_softc *sc = hw->priv;
3388 struct ath5k_hw *ah = sc->ah;
3390 rfilt = ath5k_hw_get_rx_filter(ah);
3392 rfilt |= AR5K_RX_FILTER_BEACON;
3394 rfilt &= ~AR5K_RX_FILTER_BEACON;
3395 ath5k_hw_set_rx_filter(ah, rfilt);
3396 sc->filter_flags = rfilt;
3399 static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
3400 struct ieee80211_vif *vif,
3401 struct ieee80211_bss_conf *bss_conf,
3404 struct ath5k_softc *sc = hw->priv;
3405 struct ath5k_hw *ah = sc->ah;
3406 struct ath_common *common = ath5k_hw_common(ah);
3407 unsigned long flags;
3409 mutex_lock(&sc->lock);
3410 if (WARN_ON(sc->vif != vif))
3413 if (changes & BSS_CHANGED_BSSID) {
3414 /* Cache for later use during resets */
3415 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
3417 ath5k_hw_set_associd(ah);
3421 if (changes & BSS_CHANGED_BEACON_INT)
3422 sc->bintval = bss_conf->beacon_int;
3424 if (changes & BSS_CHANGED_ASSOC) {
3425 sc->assoc = bss_conf->assoc;
3426 if (sc->opmode == NL80211_IFTYPE_STATION)
3427 set_beacon_filter(hw, sc->assoc);
3428 ath5k_hw_set_ledstate(sc->ah, sc->assoc ?
3429 AR5K_LED_ASSOC : AR5K_LED_INIT);
3430 if (bss_conf->assoc) {
3431 ATH5K_DBG(sc, ATH5K_DEBUG_ANY,
3432 "Bss Info ASSOC %d, bssid: %pM\n",
3433 bss_conf->aid, common->curbssid);
3434 common->curaid = bss_conf->aid;
3435 ath5k_hw_set_associd(ah);
3436 /* Once ANI is available you would start it here */
3440 if (changes & BSS_CHANGED_BEACON) {
3441 spin_lock_irqsave(&sc->block, flags);
3442 ath5k_beacon_update(hw, vif);
3443 spin_unlock_irqrestore(&sc->block, flags);
3446 if (changes & BSS_CHANGED_BEACON_ENABLED)
3447 sc->enable_beacon = bss_conf->enable_beacon;
3449 if (changes & (BSS_CHANGED_BEACON | BSS_CHANGED_BEACON_ENABLED |
3450 BSS_CHANGED_BEACON_INT))
3451 ath5k_beacon_config(sc);
3454 mutex_unlock(&sc->lock);
3457 static void ath5k_sw_scan_start(struct ieee80211_hw *hw)
3459 struct ath5k_softc *sc = hw->priv;
3461 ath5k_hw_set_ledstate(sc->ah, AR5K_LED_SCAN);
3464 static void ath5k_sw_scan_complete(struct ieee80211_hw *hw)
3466 struct ath5k_softc *sc = hw->priv;
3467 ath5k_hw_set_ledstate(sc->ah, sc->assoc ?
3468 AR5K_LED_ASSOC : AR5K_LED_INIT);
3472 * ath5k_set_coverage_class - Set IEEE 802.11 coverage class
3474 * @hw: struct ieee80211_hw pointer
3475 * @coverage_class: IEEE 802.11 coverage class number
3477 * Mac80211 callback. Sets slot time, ACK timeout and CTS timeout for given
3478 * coverage class. The values are persistent, they are restored after device
3481 static void ath5k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class)
3483 struct ath5k_softc *sc = hw->priv;
3485 mutex_lock(&sc->lock);
3486 ath5k_hw_set_coverage_class(sc->ah, coverage_class);
3487 mutex_unlock(&sc->lock);
git://ftp.safe.ca / safe / jmp / linux-2.6 / blob