SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/net/wireless/adm8211.c

   1
   2 /*
   3  * Linux device driver for ADMtek ADM8211 (IEEE 802.11b MAC/BBP)
   4  *
   5  * Copyright (c) 2003, Jouni Malinen <j@w1.fi>
   6  * Copyright (c) 2004-2007, Michael Wu <flamingice@sourmilk.net>
   7  * Some parts copyright (c) 2003 by David Young <dyoung@pobox.com>
   8  * and used with permission.
   9  *
  10  * Much thanks to Infineon-ADMtek for their support of this driver.
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License version 2 as
  14  * published by the Free Software Foundation. See README and COPYING for
  15  * more details.
  16  */
  17
  18 #include <linux/init.h>
  19 #include <linux/if.h>
  20 #include <linux/skbuff.h>
  21 #include <linux/etherdevice.h>
  22 #include <linux/pci.h>
  23 #include <linux/delay.h>
  24 #include <linux/crc32.h>
  25 #include <linux/eeprom_93cx6.h>
  26 #include <net/mac80211.h>
  27
  28 #include "adm8211.h"
  29
  30 MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>");
  31 MODULE_AUTHOR("Jouni Malinen <j@w1.fi>");
  32 MODULE_DESCRIPTION("Driver for IEEE 802.11b wireless cards based on ADMtek ADM8211");
  33 MODULE_SUPPORTED_DEVICE("ADM8211");
  34 MODULE_LICENSE("GPL");
  35
  36 static unsigned int tx_ring_size __read_mostly = 16;
  37 static unsigned int rx_ring_size __read_mostly = 16;
  38
  39 module_param(tx_ring_size, uint, 0);
  40 module_param(rx_ring_size, uint, 0);
  41
  42 static const char version[] = KERN_INFO "adm8211: "
  43 "Copyright 2003, Jouni Malinen <j@w1.fi>; "
  44 "Copyright 2004-2007, Michael Wu <flamingice@sourmilk.net>\n";
  45
  46
  47 static struct pci_device_id adm8211_pci_id_table[] __devinitdata = {
  48         /* ADMtek ADM8211 */
  49         { PCI_DEVICE(0x10B7, 0x6000) }, /* 3Com 3CRSHPW796 */
  50         { PCI_DEVICE(0x1200, 0x8201) }, /* ? */
  51         { PCI_DEVICE(0x1317, 0x8201) }, /* ADM8211A */
  52         { PCI_DEVICE(0x1317, 0x8211) }, /* ADM8211B/C */
  53         { 0 }
  54 };
  55
  56 static void adm8211_eeprom_register_read(struct eeprom_93cx6 *eeprom)
  57 {
  58         struct adm8211_priv *priv = eeprom->data;
  59         u32 reg = ADM8211_CSR_READ(SPR);
  60
  61         eeprom->reg_data_in = reg & ADM8211_SPR_SDI;
  62         eeprom->reg_data_out = reg & ADM8211_SPR_SDO;
  63         eeprom->reg_data_clock = reg & ADM8211_SPR_SCLK;
  64         eeprom->reg_chip_select = reg & ADM8211_SPR_SCS;
  65 }
  66
  67 static void adm8211_eeprom_register_write(struct eeprom_93cx6 *eeprom)
  68 {
  69         struct adm8211_priv *priv = eeprom->data;
  70         u32 reg = 0x4000 | ADM8211_SPR_SRS;
  71
  72         if (eeprom->reg_data_in)
  73                 reg |= ADM8211_SPR_SDI;
  74         if (eeprom->reg_data_out)
  75                 reg |= ADM8211_SPR_SDO;
  76         if (eeprom->reg_data_clock)
  77                 reg |= ADM8211_SPR_SCLK;
  78         if (eeprom->reg_chip_select)
  79                 reg |= ADM8211_SPR_SCS;
  80
  81         ADM8211_CSR_WRITE(SPR, reg);
  82         ADM8211_CSR_READ(SPR);          /* eeprom_delay */
  83 }
  84
  85 static int adm8211_read_eeprom(struct ieee80211_hw *dev)
  86 {
  87         struct adm8211_priv *priv = dev->priv;
  88         unsigned int words, i;
  89         struct ieee80211_chan_range chan_range;
  90         u16 cr49;
  91         struct eeprom_93cx6 eeprom = {
  92                 .data           = priv,
  93                 .register_read  = adm8211_eeprom_register_read,
  94                 .register_write = adm8211_eeprom_register_write
  95         };
  96
  97         if (ADM8211_CSR_READ(CSR_TEST0) & ADM8211_CSR_TEST0_EPTYP) {
  98                 /* 256 * 16-bit = 512 bytes */
  99                 eeprom.width = PCI_EEPROM_WIDTH_93C66;
 100                 words = 256;
 101         } else {
 102                 /* 64 * 16-bit = 128 bytes */
 103                 eeprom.width = PCI_EEPROM_WIDTH_93C46;
 104                 words = 64;
 105         }
 106
 107         priv->eeprom_len = words * 2;
 108         priv->eeprom = kmalloc(priv->eeprom_len, GFP_KERNEL);
 109         if (!priv->eeprom)
 110                 return -ENOMEM;
 111
 112         eeprom_93cx6_multiread(&eeprom, 0, (__le16 __force *)priv->eeprom, words);
 113
 114         cr49 = le16_to_cpu(priv->eeprom->cr49);
 115         priv->rf_type = (cr49 >> 3) & 0x7;
 116         switch (priv->rf_type) {
 117         case ADM8211_TYPE_INTERSIL:
 118         case ADM8211_TYPE_RFMD:
 119         case ADM8211_TYPE_MARVEL:
 120         case ADM8211_TYPE_AIROHA:
 121         case ADM8211_TYPE_ADMTEK:
 122                 break;
 123
 124         default:
 125                 if (priv->revid < ADM8211_REV_CA)
 126                         priv->rf_type = ADM8211_TYPE_RFMD;
 127                 else
 128                         priv->rf_type = ADM8211_TYPE_AIROHA;
 129
 130                 printk(KERN_WARNING "%s (adm8211): Unknown RFtype %d\n",
 131                        pci_name(priv->pdev), (cr49 >> 3) & 0x7);
 132         }
 133
 134         priv->bbp_type = cr49 & 0x7;
 135         switch (priv->bbp_type) {
 136         case ADM8211_TYPE_INTERSIL:
 137         case ADM8211_TYPE_RFMD:
 138         case ADM8211_TYPE_MARVEL:
 139         case ADM8211_TYPE_AIROHA:
 140         case ADM8211_TYPE_ADMTEK:
 141                 break;
 142         default:
 143                 if (priv->revid < ADM8211_REV_CA)
 144                         priv->bbp_type = ADM8211_TYPE_RFMD;
 145                 else
 146                         priv->bbp_type = ADM8211_TYPE_ADMTEK;
 147
 148                 printk(KERN_WARNING "%s (adm8211): Unknown BBPtype: %d\n",
 149                        pci_name(priv->pdev), cr49 >> 3);
 150         }
 151
 152         if (priv->eeprom->country_code >= ARRAY_SIZE(cranges)) {
 153                 printk(KERN_WARNING "%s (adm8211): Invalid country code (%d)\n",
 154                        pci_name(priv->pdev), priv->eeprom->country_code);
 155
 156                 chan_range = cranges[2];
 157         } else
 158                 chan_range = cranges[priv->eeprom->country_code];
 159
 160         printk(KERN_DEBUG "%s (adm8211): Channel range: %d - %d\n",
 161                pci_name(priv->pdev), (int)chan_range.min, (int)chan_range.max);
 162
 163         priv->modes[0].num_channels = chan_range.max - chan_range.min + 1;
 164         priv->modes[0].channels = priv->channels;
 165
 166         memcpy(priv->channels, adm8211_channels, sizeof(adm8211_channels));
 167
 168         for (i = 1; i <= ARRAY_SIZE(adm8211_channels); i++)
 169                 if (i >= chan_range.min && i <= chan_range.max)
 170                         priv->channels[i - 1].flag =
 171                                 IEEE80211_CHAN_W_SCAN |
 172                                 IEEE80211_CHAN_W_ACTIVE_SCAN |
 173                                 IEEE80211_CHAN_W_IBSS;
 174
 175         switch (priv->eeprom->specific_bbptype) {
 176         case ADM8211_BBP_RFMD3000:
 177         case ADM8211_BBP_RFMD3002:
 178         case ADM8211_BBP_ADM8011:
 179                 priv->specific_bbptype = priv->eeprom->specific_bbptype;
 180                 break;
 181
 182         default:
 183                 if (priv->revid < ADM8211_REV_CA)
 184                         priv->specific_bbptype = ADM8211_BBP_RFMD3000;
 185                 else
 186                         priv->specific_bbptype = ADM8211_BBP_ADM8011;
 187
 188                 printk(KERN_WARNING "%s (adm8211): Unknown specific BBP: %d\n",
 189                        pci_name(priv->pdev), priv->eeprom->specific_bbptype);
 190         }
 191
 192         switch (priv->eeprom->specific_rftype) {
 193         case ADM8211_RFMD2948:
 194         case ADM8211_RFMD2958:
 195         case ADM8211_RFMD2958_RF3000_CONTROL_POWER:
 196         case ADM8211_MAX2820:
 197         case ADM8211_AL2210L:
 198                 priv->transceiver_type = priv->eeprom->specific_rftype;
 199                 break;
 200
 201         default:
 202                 if (priv->revid == ADM8211_REV_BA)
 203                         priv->transceiver_type = ADM8211_RFMD2958_RF3000_CONTROL_POWER;
 204                 else if (priv->revid == ADM8211_REV_CA)
 205                         priv->transceiver_type = ADM8211_AL2210L;
 206                 else if (priv->revid == ADM8211_REV_AB)
 207                         priv->transceiver_type = ADM8211_RFMD2948;
 208
 209                 printk(KERN_WARNING "%s (adm8211): Unknown transceiver: %d\n",
 210                        pci_name(priv->pdev), priv->eeprom->specific_rftype);
 211
 212                 break;
 213         }
 214
 215         printk(KERN_DEBUG "%s (adm8211): RFtype=%d BBPtype=%d Specific BBP=%d "
 216                "Transceiver=%d\n", pci_name(priv->pdev), priv->rf_type,
 217                priv->bbp_type, priv->specific_bbptype, priv->transceiver_type);
 218
 219         return 0;
 220 }
 221
 222 static inline void adm8211_write_sram(struct ieee80211_hw *dev,
 223                                       u32 addr, u32 data)
 224 {
 225         struct adm8211_priv *priv = dev->priv;
 226
 227         ADM8211_CSR_WRITE(WEPCTL, addr | ADM8211_WEPCTL_TABLE_WR |
 228                           (priv->revid < ADM8211_REV_BA ?
 229                            0 : ADM8211_WEPCTL_SEL_WEPTABLE ));
 230         ADM8211_CSR_READ(WEPCTL);
 231         msleep(1);
 232
 233         ADM8211_CSR_WRITE(WESK, data);
 234         ADM8211_CSR_READ(WESK);
 235         msleep(1);
 236 }
 237
 238 static void adm8211_write_sram_bytes(struct ieee80211_hw *dev,
 239                                      unsigned int addr, u8 *buf,
 240                                      unsigned int len)
 241 {
 242         struct adm8211_priv *priv = dev->priv;
 243         u32 reg = ADM8211_CSR_READ(WEPCTL);
 244         unsigned int i;
 245
 246         if (priv->revid < ADM8211_REV_BA) {
 247                 for (i = 0; i < len; i += 2) {
 248                         u16 val = buf[i] | (buf[i + 1] << 8);
 249                         adm8211_write_sram(dev, addr + i / 2, val);
 250                 }
 251         } else {
 252                 for (i = 0; i < len; i += 4) {
 253                         u32 val = (buf[i + 0] << 0 ) | (buf[i + 1] << 8 ) |
 254                                   (buf[i + 2] << 16) | (buf[i + 3] << 24);
 255                         adm8211_write_sram(dev, addr + i / 4, val);
 256                 }
 257         }
 258
 259         ADM8211_CSR_WRITE(WEPCTL, reg);
 260 }
 261
 262 static void adm8211_clear_sram(struct ieee80211_hw *dev)
 263 {
 264         struct adm8211_priv *priv = dev->priv;
 265         u32 reg = ADM8211_CSR_READ(WEPCTL);
 266         unsigned int addr;
 267
 268         for (addr = 0; addr < ADM8211_SRAM_SIZE; addr++)
 269                 adm8211_write_sram(dev, addr, 0);
 270
 271         ADM8211_CSR_WRITE(WEPCTL, reg);
 272 }
 273
 274 static int adm8211_get_stats(struct ieee80211_hw *dev,
 275                              struct ieee80211_low_level_stats *stats)
 276 {
 277         struct adm8211_priv *priv = dev->priv;
 278
 279         memcpy(stats, &priv->stats, sizeof(*stats));
 280
 281         return 0;
 282 }
 283
 284 static int adm8211_get_tx_stats(struct ieee80211_hw *dev,
 285                                 struct ieee80211_tx_queue_stats *stats)
 286 {
 287         struct adm8211_priv *priv = dev->priv;
 288         struct ieee80211_tx_queue_stats_data *data = &stats->data[0];
 289
 290         data->len = priv->cur_tx - priv->dirty_tx;
 291         data->limit = priv->tx_ring_size - 2;
 292         data->count = priv->dirty_tx;
 293
 294         return 0;
 295 }
 296
 297 static void adm8211_interrupt_tci(struct ieee80211_hw *dev)
 298 {
 299         struct adm8211_priv *priv = dev->priv;
 300         unsigned int dirty_tx;
 301
 302         spin_lock(&priv->lock);
 303
 304         for (dirty_tx = priv->dirty_tx; priv->cur_tx - dirty_tx; dirty_tx++) {
 305                 unsigned int entry = dirty_tx % priv->tx_ring_size;
 306                 u32 status = le32_to_cpu(priv->tx_ring[entry].status);
 307                 struct adm8211_tx_ring_info *info;
 308                 struct sk_buff *skb;
 309
 310                 if (status & TDES0_CONTROL_OWN ||
 311                     !(status & TDES0_CONTROL_DONE))
 312                         break;
 313
 314                 info = &priv->tx_buffers[entry];
 315                 skb = info->skb;
 316
 317                 /* TODO: check TDES0_STATUS_TUF and TDES0_STATUS_TRO */
 318
 319                 pci_unmap_single(priv->pdev, info->mapping,
 320                                  info->skb->len, PCI_DMA_TODEVICE);
 321
 322                 if (info->tx_control.flags & IEEE80211_TXCTL_REQ_TX_STATUS) {
 323                         struct ieee80211_tx_status tx_status = {{0}};
 324                         struct ieee80211_hdr *hdr;
 325                         size_t hdrlen = info->hdrlen;
 326
 327                         skb_pull(skb, sizeof(struct adm8211_tx_hdr));
 328                         hdr = (struct ieee80211_hdr *)skb_push(skb, hdrlen);
 329                         memcpy(hdr, skb->cb, hdrlen);
 330                         memcpy(&tx_status.control, &info->tx_control,
 331                                sizeof(tx_status.control));
 332                         if (!(status & TDES0_STATUS_ES))
 333                                 tx_status.flags |= IEEE80211_TX_STATUS_ACK;
 334                         ieee80211_tx_status_irqsafe(dev, skb, &tx_status);
 335                 } else
 336                         dev_kfree_skb_irq(skb);
 337                 info->skb = NULL;
 338         }
 339
 340         if (priv->cur_tx - dirty_tx < priv->tx_ring_size - 2)
 341                 ieee80211_wake_queue(dev, 0);
 342
 343         priv->dirty_tx = dirty_tx;
 344         spin_unlock(&priv->lock);
 345 }
 346
 347
 348 static void adm8211_interrupt_rci(struct ieee80211_hw *dev)
 349 {
 350         struct adm8211_priv *priv = dev->priv;
 351         unsigned int entry = priv->cur_rx % priv->rx_ring_size;
 352         u32 status;
 353         unsigned int pktlen;
 354         struct sk_buff *skb, *newskb;
 355         unsigned int limit = priv->rx_ring_size;
 356         static const u8 rate_tbl[] = {10, 20, 55, 110, 220};
 357         u8 rssi, rate;
 358
 359         while (!(priv->rx_ring[entry].status & cpu_to_le32(RDES0_STATUS_OWN))) {
 360                 if (!limit--)
 361                         break;
 362
 363                 status = le32_to_cpu(priv->rx_ring[entry].status);
 364                 rate = (status & RDES0_STATUS_RXDR) >> 12;
 365                 rssi = le32_to_cpu(priv->rx_ring[entry].length) &
 366                         RDES1_STATUS_RSSI;
 367
 368                 pktlen = status & RDES0_STATUS_FL;
 369                 if (pktlen > RX_PKT_SIZE) {
 370                         if (net_ratelimit())
 371                                 printk(KERN_DEBUG "%s: frame too long (%d)\n",
 372                                        wiphy_name(dev->wiphy), pktlen);
 373                         pktlen = RX_PKT_SIZE;
 374                 }
 375
 376                 if (!priv->soft_rx_crc && status & RDES0_STATUS_ES) {
 377                         skb = NULL; /* old buffer will be reused */
 378                         /* TODO: update RX error stats */
 379                         /* TODO: check RDES0_STATUS_CRC*E */
 380                 } else if (pktlen < RX_COPY_BREAK) {
 381                         skb = dev_alloc_skb(pktlen);
 382                         if (skb) {
 383                                 pci_dma_sync_single_for_cpu(
 384                                         priv->pdev,
 385                                         priv->rx_buffers[entry].mapping,
 386                                         pktlen, PCI_DMA_FROMDEVICE);
 387                                 memcpy(skb_put(skb, pktlen),
 388                                        skb_tail_pointer(priv->rx_buffers[entry].skb),
 389                                        pktlen);
 390                                 pci_dma_sync_single_for_device(
 391                                         priv->pdev,
 392                                         priv->rx_buffers[entry].mapping,
 393                                         RX_PKT_SIZE, PCI_DMA_FROMDEVICE);
 394                         }
 395                 } else {
 396                         newskb = dev_alloc_skb(RX_PKT_SIZE);
 397                         if (newskb) {
 398                                 skb = priv->rx_buffers[entry].skb;
 399                                 skb_put(skb, pktlen);
 400                                 pci_unmap_single(
 401                                         priv->pdev,
 402                                         priv->rx_buffers[entry].mapping,
 403                                         RX_PKT_SIZE, PCI_DMA_FROMDEVICE);
 404                                 priv->rx_buffers[entry].skb = newskb;
 405                                 priv->rx_buffers[entry].mapping =
 406                                         pci_map_single(priv->pdev,
 407                                                        skb_tail_pointer(newskb),
 408                                                        RX_PKT_SIZE,
 409                                                        PCI_DMA_FROMDEVICE);
 410                         } else {
 411                                 skb = NULL;
 412                                 /* TODO: update rx dropped stats */
 413                         }
 414
 415                         priv->rx_ring[entry].buffer1 =
 416                                 cpu_to_le32(priv->rx_buffers[entry].mapping);
 417                 }
 418
 419                 priv->rx_ring[entry].status = cpu_to_le32(RDES0_STATUS_OWN |
 420                                                           RDES0_STATUS_SQL);
 421                 priv->rx_ring[entry].length =
 422                         cpu_to_le32(RX_PKT_SIZE |
 423                                     (entry == priv->rx_ring_size - 1 ?
 424                                      RDES1_CONTROL_RER : 0));
 425
 426                 if (skb) {
 427                         struct ieee80211_rx_status rx_status = {0};
 428
 429                         if (priv->revid < ADM8211_REV_CA)
 430                                 rx_status.ssi = rssi;
 431                         else
 432                                 rx_status.ssi = 100 - rssi;
 433
 434                         if (rate <= 4)
 435                                 rx_status.rate = rate_tbl[rate];
 436
 437                         rx_status.channel = priv->channel;
 438                         rx_status.freq = adm8211_channels[priv->channel - 1].freq;
 439                         rx_status.phymode = MODE_IEEE80211B;
 440
 441                         ieee80211_rx_irqsafe(dev, skb, &rx_status);
 442                 }
 443
 444                 entry = (++priv->cur_rx) % priv->rx_ring_size;
 445         }
 446
 447         /* TODO: check LPC and update stats? */
 448 }
 449
 450
 451 static irqreturn_t adm8211_interrupt(int irq, void *dev_id)
 452 {
 453 #define ADM8211_INT(x)                                                     \
 454 do {                                                                       \
 455         if (unlikely(stsr & ADM8211_STSR_ ## x))                           \
 456                 printk(KERN_DEBUG "%s: " #x "\n", wiphy_name(dev->wiphy)); \
 457 } while (0)
 458
 459         struct ieee80211_hw *dev = dev_id;
 460         struct adm8211_priv *priv = dev->priv;
 461         u32 stsr = ADM8211_CSR_READ(STSR);
 462         ADM8211_CSR_WRITE(STSR, stsr);
 463         if (stsr == 0xffffffff)
 464                 return IRQ_HANDLED;
 465
 466         if (!(stsr & (ADM8211_STSR_NISS | ADM8211_STSR_AISS)))
 467                 return IRQ_HANDLED;
 468
 469         if (stsr & ADM8211_STSR_RCI)
 470                 adm8211_interrupt_rci(dev);
 471         if (stsr & ADM8211_STSR_TCI)
 472                 adm8211_interrupt_tci(dev);
 473
 474         /*ADM8211_INT(LinkOn);*/
 475         /*ADM8211_INT(LinkOff);*/
 476
 477         ADM8211_INT(PCF);
 478         ADM8211_INT(BCNTC);
 479         ADM8211_INT(GPINT);
 480         ADM8211_INT(ATIMTC);
 481         ADM8211_INT(TSFTF);
 482         ADM8211_INT(TSCZ);
 483         ADM8211_INT(SQL);
 484         ADM8211_INT(WEPTD);
 485         ADM8211_INT(ATIME);
 486         /*ADM8211_INT(TBTT);*/
 487         ADM8211_INT(TEIS);
 488         ADM8211_INT(FBE);
 489         ADM8211_INT(REIS);
 490         ADM8211_INT(GPTT);
 491         ADM8211_INT(RPS);
 492         ADM8211_INT(RDU);
 493         ADM8211_INT(TUF);
 494         /*ADM8211_INT(TRT);*/
 495         /*ADM8211_INT(TLT);*/
 496         /*ADM8211_INT(TDU);*/
 497         ADM8211_INT(TPS);
 498
 499         return IRQ_HANDLED;
 500
 501 #undef ADM8211_INT
 502 }
 503
 504 #define WRITE_SYN(name,v_mask,v_shift,a_mask,a_shift,bits,prewrite,postwrite)\
 505 static void adm8211_rf_write_syn_ ## name (struct ieee80211_hw *dev,         \
 506                                            u16 addr, u32 value) {            \
 507         struct adm8211_priv *priv = dev->priv;                               \
 508         unsigned int i;                                                      \
 509         u32 reg, bitbuf;                                                     \
 510                                                                              \
 511         value &= v_mask;                                                     \
 512         addr &= a_mask;                                                      \
 513         bitbuf = (value << v_shift) | (addr << a_shift);                     \
 514                                                                              \
 515         ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_IF_SELECT_1);                 \
 516         ADM8211_CSR_READ(SYNRF);                                             \
 517         ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_IF_SELECT_0);                 \
 518         ADM8211_CSR_READ(SYNRF);                                             \
 519                                                                              \
 520         if (prewrite) {                                                      \
 521                 ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_WRITE_SYNDATA_0);     \
 522                 ADM8211_CSR_READ(SYNRF);                                     \
 523         }                                                                    \
 524                                                                              \
 525         for (i = 0; i <= bits; i++) {                                        \
 526                 if (bitbuf & (1 << (bits - i)))                              \
 527                         reg = ADM8211_SYNRF_WRITE_SYNDATA_1;                 \
 528                 else                                                         \
 529                         reg = ADM8211_SYNRF_WRITE_SYNDATA_0;                 \
 530                                                                              \
 531                 ADM8211_CSR_WRITE(SYNRF, reg);                               \
 532                 ADM8211_CSR_READ(SYNRF);                                     \
 533                                                                              \
 534                 ADM8211_CSR_WRITE(SYNRF, reg | ADM8211_SYNRF_WRITE_CLOCK_1); \
 535                 ADM8211_CSR_READ(SYNRF);                                     \
 536                 ADM8211_CSR_WRITE(SYNRF, reg | ADM8211_SYNRF_WRITE_CLOCK_0); \
 537                 ADM8211_CSR_READ(SYNRF);                                     \
 538         }                                                                    \
 539                                                                              \
 540         if (postwrite == 1) {                                                \
 541                 ADM8211_CSR_WRITE(SYNRF, reg | ADM8211_SYNRF_IF_SELECT_0);   \
 542                 ADM8211_CSR_READ(SYNRF);                                     \
 543         }                                                                    \
 544         if (postwrite == 2) {                                                \
 545                 ADM8211_CSR_WRITE(SYNRF, reg | ADM8211_SYNRF_IF_SELECT_1);   \
 546                 ADM8211_CSR_READ(SYNRF);                                     \
 547         }                                                                    \
 548                                                                              \
 549         ADM8211_CSR_WRITE(SYNRF, 0);                                         \
 550         ADM8211_CSR_READ(SYNRF);                                             \
 551 }
 552
 553 WRITE_SYN(max2820,  0x00FFF, 0, 0x0F, 12, 15, 1, 1)
 554 WRITE_SYN(al2210l,  0xFFFFF, 4, 0x0F,  0, 23, 1, 1)
 555 WRITE_SYN(rfmd2958, 0x3FFFF, 0, 0x1F, 18, 23, 0, 1)
 556 WRITE_SYN(rfmd2948, 0x0FFFF, 4, 0x0F,  0, 21, 0, 2)
 557
 558 #undef WRITE_SYN
 559
 560 static int adm8211_write_bbp(struct ieee80211_hw *dev, u8 addr, u8 data)
 561 {
 562         struct adm8211_priv *priv = dev->priv;
 563         unsigned int timeout;
 564         u32 reg;
 565
 566         timeout = 10;
 567         while (timeout > 0) {
 568                 reg = ADM8211_CSR_READ(BBPCTL);
 569                 if (!(reg & (ADM8211_BBPCTL_WR | ADM8211_BBPCTL_RD)))
 570                         break;
 571                 timeout--;
 572                 msleep(2);
 573         }
 574
 575         if (timeout == 0) {
 576                 printk(KERN_DEBUG "%s: adm8211_write_bbp(%d,%d) failed"
 577                        " prewrite (reg=0x%08x)\n",
 578                        wiphy_name(dev->wiphy), addr, data, reg);
 579                 return -ETIMEDOUT;
 580         }
 581
 582         switch (priv->bbp_type) {
 583         case ADM8211_TYPE_INTERSIL:
 584                 reg = ADM8211_BBPCTL_MMISEL;    /* three wire interface */
 585                 break;
 586         case ADM8211_TYPE_RFMD:
 587                 reg = (0x20 << 24) | ADM8211_BBPCTL_TXCE | ADM8211_BBPCTL_CCAP |
 588                       (0x01 << 18);
 589                 break;
 590         case ADM8211_TYPE_ADMTEK:
 591                 reg = (0x20 << 24) | ADM8211_BBPCTL_TXCE | ADM8211_BBPCTL_CCAP |
 592                       (0x05 << 18);
 593                 break;
 594         }
 595         reg |= ADM8211_BBPCTL_WR | (addr << 8) | data;
 596
 597         ADM8211_CSR_WRITE(BBPCTL, reg);
 598
 599         timeout = 10;
 600         while (timeout > 0) {
 601                 reg = ADM8211_CSR_READ(BBPCTL);
 602                 if (!(reg & ADM8211_BBPCTL_WR))
 603                         break;
 604                 timeout--;
 605                 msleep(2);
 606         }
 607
 608         if (timeout == 0) {
 609                 ADM8211_CSR_WRITE(BBPCTL, ADM8211_CSR_READ(BBPCTL) &
 610                                   ~ADM8211_BBPCTL_WR);
 611                 printk(KERN_DEBUG "%s: adm8211_write_bbp(%d,%d) failed"
 612                        " postwrite (reg=0x%08x)\n",
 613                        wiphy_name(dev->wiphy), addr, data, reg);
 614                 return -ETIMEDOUT;
 615         }
 616
 617         return 0;
 618 }
 619
 620 static int adm8211_rf_set_channel(struct ieee80211_hw *dev, unsigned int chan)
 621 {
 622         static const u32 adm8211_rfmd2958_reg5[] =
 623                 {0x22BD, 0x22D2, 0x22E8, 0x22FE, 0x2314, 0x232A, 0x2340,
 624                  0x2355, 0x236B, 0x2381, 0x2397, 0x23AD, 0x23C2, 0x23F7};
 625         static const u32 adm8211_rfmd2958_reg6[] =
 626                 {0x05D17, 0x3A2E8, 0x2E8BA, 0x22E8B, 0x1745D, 0x0BA2E, 0x00000,
 627                  0x345D1, 0x28BA2, 0x1D174, 0x11745, 0x05D17, 0x3A2E8, 0x11745};
 628
 629         struct adm8211_priv *priv = dev->priv;
 630         u8 ant_power = priv->ant_power > 0x3F ?
 631                 priv->eeprom->antenna_power[chan - 1] : priv->ant_power;
 632         u8 tx_power = priv->tx_power > 0x3F ?
 633                 priv->eeprom->tx_power[chan - 1] : priv->tx_power;
 634         u8 lpf_cutoff = priv->lpf_cutoff == 0xFF ?
 635                 priv->eeprom->lpf_cutoff[chan - 1] : priv->lpf_cutoff;
 636         u8 lnags_thresh = priv->lnags_threshold == 0xFF ?
 637                 priv->eeprom->lnags_threshold[chan - 1] : priv->lnags_threshold;
 638         u32 reg;
 639
 640         ADM8211_IDLE();
 641
 642         /* Program synthesizer to new channel */
 643         switch (priv->transceiver_type) {
 644         case ADM8211_RFMD2958:
 645         case ADM8211_RFMD2958_RF3000_CONTROL_POWER:
 646                 adm8211_rf_write_syn_rfmd2958(dev, 0x00, 0x04007);
 647                 adm8211_rf_write_syn_rfmd2958(dev, 0x02, 0x00033);
 648
 649                 adm8211_rf_write_syn_rfmd2958(dev, 0x05,
 650                         adm8211_rfmd2958_reg5[chan - 1]);
 651                 adm8211_rf_write_syn_rfmd2958(dev, 0x06,
 652                         adm8211_rfmd2958_reg6[chan - 1]);
 653                 break;
 654
 655         case ADM8211_RFMD2948:
 656                 adm8211_rf_write_syn_rfmd2948(dev, SI4126_MAIN_CONF,
 657                                               SI4126_MAIN_XINDIV2);
 658                 adm8211_rf_write_syn_rfmd2948(dev, SI4126_POWERDOWN,
 659                                               SI4126_POWERDOWN_PDIB |
 660                                               SI4126_POWERDOWN_PDRB);
 661                 adm8211_rf_write_syn_rfmd2948(dev, SI4126_PHASE_DET_GAIN, 0);
 662                 adm8211_rf_write_syn_rfmd2948(dev, SI4126_RF2_N_DIV,
 663                                               (chan == 14 ?
 664                                                2110 : (2033 + (chan * 5))));
 665                 adm8211_rf_write_syn_rfmd2948(dev, SI4126_IF_N_DIV, 1496);
 666                 adm8211_rf_write_syn_rfmd2948(dev, SI4126_RF2_R_DIV, 44);
 667                 adm8211_rf_write_syn_rfmd2948(dev, SI4126_IF_R_DIV, 44);
 668                 break;
 669
 670         case ADM8211_MAX2820:
 671                 adm8211_rf_write_syn_max2820(dev, 0x3,
 672                         (chan == 14 ? 0x054 : (0x7 + (chan * 5))));
 673                 break;
 674
 675         case ADM8211_AL2210L:
 676                 adm8211_rf_write_syn_al2210l(dev, 0x0,
 677                         (chan == 14 ? 0x229B4 : (0x22967 + (chan * 5))));
 678                 break;
 679
 680         default:
 681                 printk(KERN_DEBUG "%s: unsupported transceiver type %d\n",
 682                        wiphy_name(dev->wiphy), priv->transceiver_type);
 683                 break;
 684         }
 685
 686         /* write BBP regs */
 687         if (priv->bbp_type == ADM8211_TYPE_RFMD) {
 688
 689         /* SMC 2635W specific? adm8211b doesn't use the 2948 though.. */
 690         /* TODO: remove if SMC 2635W doesn't need this */
 691         if (priv->transceiver_type == ADM8211_RFMD2948) {
 692                 reg = ADM8211_CSR_READ(GPIO);
 693                 reg &= 0xfffc0000;
 694                 reg |= ADM8211_CSR_GPIO_EN0;
 695                 if (chan != 14)
 696                         reg |= ADM8211_CSR_GPIO_O0;
 697                 ADM8211_CSR_WRITE(GPIO, reg);
 698         }
 699
 700         if (priv->transceiver_type == ADM8211_RFMD2958) {
 701                 /* set PCNT2 */
 702                 adm8211_rf_write_syn_rfmd2958(dev, 0x0B, 0x07100);
 703                 /* set PCNT1 P_DESIRED/MID_BIAS */
 704                 reg = le16_to_cpu(priv->eeprom->cr49);
 705                 reg >>= 13;
 706                 reg <<= 15;
 707                 reg |= ant_power << 9;
 708                 adm8211_rf_write_syn_rfmd2958(dev, 0x0A, reg);
 709                 /* set TXRX TX_GAIN */
 710                 adm8211_rf_write_syn_rfmd2958(dev, 0x09, 0x00050 |
 711                         (priv->revid < ADM8211_REV_CA ? tx_power : 0));
 712         } else {
 713                 reg = ADM8211_CSR_READ(PLCPHD);
 714                 reg &= 0xff00ffff;
 715                 reg |= tx_power << 18;
 716                 ADM8211_CSR_WRITE(PLCPHD, reg);
 717         }
 718
 719         ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_SELRF |
 720                           ADM8211_SYNRF_PE1 | ADM8211_SYNRF_PHYRST);
 721         ADM8211_CSR_READ(SYNRF);
 722         msleep(30);
 723
 724         /* RF3000 BBP */
 725         if (priv->transceiver_type != ADM8211_RFMD2958)
 726                 adm8211_write_bbp(dev, RF3000_TX_VAR_GAIN__TX_LEN_EXT,
 727                                   tx_power<<2);
 728         adm8211_write_bbp(dev, RF3000_LOW_GAIN_CALIB, lpf_cutoff);
 729         adm8211_write_bbp(dev, RF3000_HIGH_GAIN_CALIB, lnags_thresh);
 730         adm8211_write_bbp(dev, 0x1c, priv->revid == ADM8211_REV_BA ?
 731                                      priv->eeprom->cr28 : 0);
 732         adm8211_write_bbp(dev, 0x1d, priv->eeprom->cr29);
 733
 734         ADM8211_CSR_WRITE(SYNRF, 0);
 735
 736         /* Nothing to do for ADMtek BBP */
 737         } else if (priv->bbp_type != ADM8211_TYPE_ADMTEK)
 738                 printk(KERN_DEBUG "%s: unsupported BBP type %d\n",
 739                        wiphy_name(dev->wiphy), priv->bbp_type);
 740
 741         ADM8211_RESTORE();
 742
 743         /* update current channel for adhoc (and maybe AP mode) */
 744         reg = ADM8211_CSR_READ(CAP0);
 745         reg &= ~0xF;
 746         reg |= chan;
 747         ADM8211_CSR_WRITE(CAP0, reg);
 748
 749         return 0;
 750 }
 751
 752 static void adm8211_update_mode(struct ieee80211_hw *dev)
 753 {
 754         struct adm8211_priv *priv = dev->priv;
 755
 756         ADM8211_IDLE();
 757
 758         priv->soft_rx_crc = 0;
 759         switch (priv->mode) {
 760         case IEEE80211_IF_TYPE_STA:
 761                 priv->nar &= ~(ADM8211_NAR_PR | ADM8211_NAR_EA);
 762                 priv->nar |= ADM8211_NAR_ST | ADM8211_NAR_SR;
 763                 break;
 764         case IEEE80211_IF_TYPE_IBSS:
 765                 priv->nar &= ~ADM8211_NAR_PR;
 766                 priv->nar |= ADM8211_NAR_EA | ADM8211_NAR_ST | ADM8211_NAR_SR;
 767
 768                 /* don't trust the error bits on rev 0x20 and up in adhoc */
 769                 if (priv->revid >= ADM8211_REV_BA)
 770                         priv->soft_rx_crc = 1;
 771                 break;
 772         case IEEE80211_IF_TYPE_MNTR:
 773                 priv->nar &= ~(ADM8211_NAR_EA | ADM8211_NAR_ST);
 774                 priv->nar |= ADM8211_NAR_PR | ADM8211_NAR_SR;
 775                 break;
 776         }
 777
 778         ADM8211_RESTORE();
 779 }
 780
 781 static void adm8211_hw_init_syn(struct ieee80211_hw *dev)
 782 {
 783         struct adm8211_priv *priv = dev->priv;
 784
 785         switch (priv->transceiver_type) {
 786         case ADM8211_RFMD2958:
 787         case ADM8211_RFMD2958_RF3000_CONTROL_POWER:
 788                 /* comments taken from ADMtek vendor driver */
 789
 790                 /* Reset RF2958 after power on */
 791                 adm8211_rf_write_syn_rfmd2958(dev, 0x1F, 0x00000);
 792                 /* Initialize RF VCO Core Bias to maximum */
 793                 adm8211_rf_write_syn_rfmd2958(dev, 0x0C, 0x3001F);
 794                 /* Initialize IF PLL */
 795                 adm8211_rf_write_syn_rfmd2958(dev, 0x01, 0x29C03);
 796                 /* Initialize IF PLL Coarse Tuning */
 797                 adm8211_rf_write_syn_rfmd2958(dev, 0x03, 0x1FF6F);
 798                 /* Initialize RF PLL */
 799                 adm8211_rf_write_syn_rfmd2958(dev, 0x04, 0x29403);
 800                 /* Initialize RF PLL Coarse Tuning */
 801                 adm8211_rf_write_syn_rfmd2958(dev, 0x07, 0x1456F);
 802                 /* Initialize TX gain and filter BW (R9) */
 803                 adm8211_rf_write_syn_rfmd2958(dev, 0x09,
 804                         (priv->transceiver_type == ADM8211_RFMD2958 ?
 805                          0x10050 : 0x00050));
 806                 /* Initialize CAL register */
 807                 adm8211_rf_write_syn_rfmd2958(dev, 0x08, 0x3FFF8);
 808                 break;
 809
 810         case ADM8211_MAX2820:
 811                 adm8211_rf_write_syn_max2820(dev, 0x1, 0x01E);
 812                 adm8211_rf_write_syn_max2820(dev, 0x2, 0x001);
 813                 adm8211_rf_write_syn_max2820(dev, 0x3, 0x054);
 814                 adm8211_rf_write_syn_max2820(dev, 0x4, 0x310);
 815                 adm8211_rf_write_syn_max2820(dev, 0x5, 0x000);
 816                 break;
 817
 818         case ADM8211_AL2210L:
 819                 adm8211_rf_write_syn_al2210l(dev, 0x0, 0x0196C);
 820                 adm8211_rf_write_syn_al2210l(dev, 0x1, 0x007CB);
 821                 adm8211_rf_write_syn_al2210l(dev, 0x2, 0x3582F);
 822                 adm8211_rf_write_syn_al2210l(dev, 0x3, 0x010A9);
 823                 adm8211_rf_write_syn_al2210l(dev, 0x4, 0x77280);
 824                 adm8211_rf_write_syn_al2210l(dev, 0x5, 0x45641);
 825                 adm8211_rf_write_syn_al2210l(dev, 0x6, 0xEA130);
 826                 adm8211_rf_write_syn_al2210l(dev, 0x7, 0x80000);
 827                 adm8211_rf_write_syn_al2210l(dev, 0x8, 0x7850F);
 828                 adm8211_rf_write_syn_al2210l(dev, 0x9, 0xF900C);
 829                 adm8211_rf_write_syn_al2210l(dev, 0xA, 0x00000);
 830                 adm8211_rf_write_syn_al2210l(dev, 0xB, 0x00000);
 831                 break;
 832
 833         case ADM8211_RFMD2948:
 834         default:
 835                 break;
 836         }
 837 }
 838
 839 static int adm8211_hw_init_bbp(struct ieee80211_hw *dev)
 840 {
 841         struct adm8211_priv *priv = dev->priv;
 842         u32 reg;
 843
 844         /* write addresses */
 845         if (priv->bbp_type == ADM8211_TYPE_INTERSIL) {
 846                 ADM8211_CSR_WRITE(MMIWA,  0x100E0C0A);
 847                 ADM8211_CSR_WRITE(MMIRD0, 0x00007C7E);
 848                 ADM8211_CSR_WRITE(MMIRD1, 0x00100000);
 849         } else if (priv->bbp_type == ADM8211_TYPE_RFMD ||
 850                    priv->bbp_type == ADM8211_TYPE_ADMTEK) {
 851                 /* check specific BBP type */
 852                 switch (priv->specific_bbptype) {
 853                 case ADM8211_BBP_RFMD3000:
 854                 case ADM8211_BBP_RFMD3002:
 855                         ADM8211_CSR_WRITE(MMIWA,  0x00009101);
 856                         ADM8211_CSR_WRITE(MMIRD0, 0x00000301);
 857                         break;
 858
 859                 case ADM8211_BBP_ADM8011:
 860                         ADM8211_CSR_WRITE(MMIWA,  0x00008903);
 861                         ADM8211_CSR_WRITE(MMIRD0, 0x00001716);
 862
 863                         reg = ADM8211_CSR_READ(BBPCTL);
 864                         reg &= ~ADM8211_BBPCTL_TYPE;
 865                         reg |= 0x5 << 18;
 866                         ADM8211_CSR_WRITE(BBPCTL, reg);
 867                         break;
 868                 }
 869
 870                 switch (priv->revid) {
 871                 case ADM8211_REV_CA:
 872                         if (priv->transceiver_type == ADM8211_RFMD2958 ||
 873                             priv->transceiver_type == ADM8211_RFMD2958_RF3000_CONTROL_POWER ||
 874                             priv->transceiver_type == ADM8211_RFMD2948)
 875                                 ADM8211_CSR_WRITE(SYNCTL, 0x1 << 22);
 876                         else if (priv->transceiver_type == ADM8211_MAX2820 ||
 877                                  priv->transceiver_type == ADM8211_AL2210L)
 878                                 ADM8211_CSR_WRITE(SYNCTL, 0x3 << 22);
 879                         break;
 880
 881                 case ADM8211_REV_BA:
 882                         reg  = ADM8211_CSR_READ(MMIRD1);
 883                         reg &= 0x0000FFFF;
 884                         reg |= 0x7e100000;
 885                         ADM8211_CSR_WRITE(MMIRD1, reg);
 886                         break;
 887
 888                 case ADM8211_REV_AB:
 889                 case ADM8211_REV_AF:
 890                 default:
 891                         ADM8211_CSR_WRITE(MMIRD1, 0x7e100000);
 892                         break;
 893                 }
 894
 895                 /* For RFMD */
 896                 ADM8211_CSR_WRITE(MACTEST, 0x800);
 897         }
 898
 899         adm8211_hw_init_syn(dev);
 900
 901         /* Set RF Power control IF pin to PE1+PHYRST# */
 902         ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_SELRF |
 903                           ADM8211_SYNRF_PE1 | ADM8211_SYNRF_PHYRST);
 904         ADM8211_CSR_READ(SYNRF);
 905         msleep(20);
 906
 907         /* write BBP regs */
 908         if (priv->bbp_type == ADM8211_TYPE_RFMD) {
 909                 /* RF3000 BBP */
 910                 /* another set:
 911                  * 11: c8
 912                  * 14: 14
 913                  * 15: 50 (chan 1..13; chan 14: d0)
 914                  * 1c: 00
 915                  * 1d: 84
 916                  */
 917                 adm8211_write_bbp(dev, RF3000_CCA_CTRL, 0x80);
 918                 /* antenna selection: diversity */
 919                 adm8211_write_bbp(dev, RF3000_DIVERSITY__RSSI, 0x80);
 920                 adm8211_write_bbp(dev, RF3000_TX_VAR_GAIN__TX_LEN_EXT, 0x74);
 921                 adm8211_write_bbp(dev, RF3000_LOW_GAIN_CALIB, 0x38);
 922                 adm8211_write_bbp(dev, RF3000_HIGH_GAIN_CALIB, 0x40);
 923
 924                 if (priv->eeprom->major_version < 2) {
 925                         adm8211_write_bbp(dev, 0x1c, 0x00);
 926                         adm8211_write_bbp(dev, 0x1d, 0x80);
 927                 } else {
 928                         if (priv->revid == ADM8211_REV_BA)
 929                                 adm8211_write_bbp(dev, 0x1c, priv->eeprom->cr28);
 930                         else
 931                                 adm8211_write_bbp(dev, 0x1c, 0x00);
 932
 933                         adm8211_write_bbp(dev, 0x1d, priv->eeprom->cr29);
 934                 }
 935         } else if (priv->bbp_type == ADM8211_TYPE_ADMTEK) {
 936                 /* reset baseband */
 937                 adm8211_write_bbp(dev, 0x00, 0xFF);
 938                 /* antenna selection: diversity */
 939                 adm8211_write_bbp(dev, 0x07, 0x0A);
 940
 941                 /* TODO: find documentation for this */
 942                 switch (priv->transceiver_type) {
 943                 case ADM8211_RFMD2958:
 944                 case ADM8211_RFMD2958_RF3000_CONTROL_POWER:
 945                         adm8211_write_bbp(dev, 0x00, 0x00);
 946                         adm8211_write_bbp(dev, 0x01, 0x00);
 947                         adm8211_write_bbp(dev, 0x02, 0x00);
 948                         adm8211_write_bbp(dev, 0x03, 0x00);
 949                         adm8211_write_bbp(dev, 0x06, 0x0f);
 950                         adm8211_write_bbp(dev, 0x09, 0x00);
 951                         adm8211_write_bbp(dev, 0x0a, 0x00);
 952                         adm8211_write_bbp(dev, 0x0b, 0x00);
 953                         adm8211_write_bbp(dev, 0x0c, 0x00);
 954                         adm8211_write_bbp(dev, 0x0f, 0xAA);
 955                         adm8211_write_bbp(dev, 0x10, 0x8c);
 956                         adm8211_write_bbp(dev, 0x11, 0x43);
 957                         adm8211_write_bbp(dev, 0x18, 0x40);
 958                         adm8211_write_bbp(dev, 0x20, 0x23);
 959                         adm8211_write_bbp(dev, 0x21, 0x02);
 960                         adm8211_write_bbp(dev, 0x22, 0x28);
 961                         adm8211_write_bbp(dev, 0x23, 0x30);
 962                         adm8211_write_bbp(dev, 0x24, 0x2d);
 963                         adm8211_write_bbp(dev, 0x28, 0x35);
 964                         adm8211_write_bbp(dev, 0x2a, 0x8c);
 965                         adm8211_write_bbp(dev, 0x2b, 0x81);
 966                         adm8211_write_bbp(dev, 0x2c, 0x44);
 967                         adm8211_write_bbp(dev, 0x2d, 0x0A);
 968                         adm8211_write_bbp(dev, 0x29, 0x40);
 969                         adm8211_write_bbp(dev, 0x60, 0x08);
 970                         adm8211_write_bbp(dev, 0x64, 0x01);
 971                         break;
 972
 973                 case ADM8211_MAX2820:
 974                         adm8211_write_bbp(dev, 0x00, 0x00);
 975                         adm8211_write_bbp(dev, 0x01, 0x00);
 976                         adm8211_write_bbp(dev, 0x02, 0x00);
 977                         adm8211_write_bbp(dev, 0x03, 0x00);
 978                         adm8211_write_bbp(dev, 0x06, 0x0f);
 979                         adm8211_write_bbp(dev, 0x09, 0x05);
 980                         adm8211_write_bbp(dev, 0x0a, 0x02);
 981                         adm8211_write_bbp(dev, 0x0b, 0x00);
 982                         adm8211_write_bbp(dev, 0x0c, 0x0f);
 983                         adm8211_write_bbp(dev, 0x0f, 0x55);
 984                         adm8211_write_bbp(dev, 0x10, 0x8d);
 985                         adm8211_write_bbp(dev, 0x11, 0x43);
 986                         adm8211_write_bbp(dev, 0x18, 0x4a);
 987                         adm8211_write_bbp(dev, 0x20, 0x20);
 988                         adm8211_write_bbp(dev, 0x21, 0x02);
 989                         adm8211_write_bbp(dev, 0x22, 0x23);
 990                         adm8211_write_bbp(dev, 0x23, 0x30);
 991                         adm8211_write_bbp(dev, 0x24, 0x2d);
 992                         adm8211_write_bbp(dev, 0x2a, 0x8c);
 993                         adm8211_write_bbp(dev, 0x2b, 0x81);
 994                         adm8211_write_bbp(dev, 0x2c, 0x44);
 995                         adm8211_write_bbp(dev, 0x29, 0x4a);
 996                         adm8211_write_bbp(dev, 0x60, 0x2b);
 997                         adm8211_write_bbp(dev, 0x64, 0x01);
 998                         break;
 999
1000                 case ADM8211_AL2210L:
1001                         adm8211_write_bbp(dev, 0x00, 0x00);
1002                         adm8211_write_bbp(dev, 0x01, 0x00);
1003                         adm8211_write_bbp(dev, 0x02, 0x00);
1004                         adm8211_write_bbp(dev, 0x03, 0x00);
1005                         adm8211_write_bbp(dev, 0x06, 0x0f);
1006                         adm8211_write_bbp(dev, 0x07, 0x05);
1007                         adm8211_write_bbp(dev, 0x08, 0x03);
1008                         adm8211_write_bbp(dev, 0x09, 0x00);
1009                         adm8211_write_bbp(dev, 0x0a, 0x00);
1010                         adm8211_write_bbp(dev, 0x0b, 0x00);
1011                         adm8211_write_bbp(dev, 0x0c, 0x10);
1012                         adm8211_write_bbp(dev, 0x0f, 0x55);
1013                         adm8211_write_bbp(dev, 0x10, 0x8d);
1014                         adm8211_write_bbp(dev, 0x11, 0x43);
1015                         adm8211_write_bbp(dev, 0x18, 0x4a);
1016                         adm8211_write_bbp(dev, 0x20, 0x20);
1017                         adm8211_write_bbp(dev, 0x21, 0x02);
1018                         adm8211_write_bbp(dev, 0x22, 0x23);
1019                         adm8211_write_bbp(dev, 0x23, 0x30);
1020                         adm8211_write_bbp(dev, 0x24, 0x2d);
1021                         adm8211_write_bbp(dev, 0x2a, 0xaa);
1022                         adm8211_write_bbp(dev, 0x2b, 0x81);
1023                         adm8211_write_bbp(dev, 0x2c, 0x44);
1024                         adm8211_write_bbp(dev, 0x29, 0xfa);
1025                         adm8211_write_bbp(dev, 0x60, 0x2d);
1026                         adm8211_write_bbp(dev, 0x64, 0x01);
1027                         break;
1028
1029                 case ADM8211_RFMD2948:
1030                         break;
1031
1032                 default:
1033                         printk(KERN_DEBUG "%s: unsupported transceiver %d\n",
1034                                wiphy_name(dev->wiphy), priv->transceiver_type);
1035                         break;
1036                 }
1037         } else
1038                 printk(KERN_DEBUG "%s: unsupported BBP %d\n",
1039                        wiphy_name(dev->wiphy), priv->bbp_type);
1040
1041         ADM8211_CSR_WRITE(SYNRF, 0);
1042
1043         /* Set RF CAL control source to MAC control */
1044         reg = ADM8211_CSR_READ(SYNCTL);
1045         reg |= ADM8211_SYNCTL_SELCAL;
1046         ADM8211_CSR_WRITE(SYNCTL, reg);
1047
1048         return 0;
1049 }
1050
1051 /* configures hw beacons/probe responses */
1052 static int adm8211_set_rate(struct ieee80211_hw *dev)
1053 {
1054         struct adm8211_priv *priv = dev->priv;
1055         u32 reg;
1056         int i = 0;
1057         u8 rate_buf[12] = {0};
1058
1059         /* write supported rates */
1060         if (priv->revid != ADM8211_REV_BA) {
1061                 rate_buf[0] = ARRAY_SIZE(adm8211_rates);
1062                 for (i = 0; i < ARRAY_SIZE(adm8211_rates); i++)
1063                         rate_buf[i + 1] = (adm8211_rates[i].rate / 5) | 0x80;
1064         } else {
1065                 /* workaround for rev BA specific bug */
1066                 rate_buf[0] = 0x04;
1067                 rate_buf[1] = 0x82;
1068                 rate_buf[2] = 0x04;
1069                 rate_buf[3] = 0x0b;
1070                 rate_buf[4] = 0x16;
1071         }
1072
1073         adm8211_write_sram_bytes(dev, ADM8211_SRAM_SUPP_RATE, rate_buf,
1074                                  ARRAY_SIZE(adm8211_rates) + 1);
1075
1076         reg = ADM8211_CSR_READ(PLCPHD) & 0x00FFFFFF; /* keep bits 0-23 */
1077         reg |= 1 << 15; /* short preamble */
1078         reg |= 110 << 24;
1079         ADM8211_CSR_WRITE(PLCPHD, reg);
1080
1081         /* MTMLT   = 512 TU (max TX MSDU lifetime)
1082          * BCNTSIG = plcp_signal (beacon, probe resp, and atim TX rate)
1083          * SRTYLIM = 224 (short retry limit, TX header value is default) */
1084         ADM8211_CSR_WRITE(TXLMT, (512 << 16) | (110 << 8) | (224 << 0));
1085
1086         return 0;
1087 }
1088
1089 static void adm8211_hw_init(struct ieee80211_hw *dev)
1090 {
1091         struct adm8211_priv *priv = dev->priv;
1092         u32 reg;
1093         u8 cline;
1094
1095         reg = le32_to_cpu(ADM8211_CSR_READ(PAR));
1096         reg |= ADM8211_PAR_MRLE | ADM8211_PAR_MRME;
1097         reg &= ~(ADM8211_PAR_BAR | ADM8211_PAR_CAL);
1098
1099         if (!pci_set_mwi(priv->pdev)) {
1100                 reg |= 0x1 << 24;
1101                 pci_read_config_byte(priv->pdev, PCI_CACHE_LINE_SIZE, &cline);
1102
1103                 switch (cline) {
1104                 case  0x8: reg |= (0x1 << 14);
1105                            break;
1106                 case 0x16: reg |= (0x2 << 14);
1107                            break;
1108                 case 0x32: reg |= (0x3 << 14);
1109                            break;
1110                   default: reg |= (0x0 << 14);
1111                            break;
1112                 }
1113         }
1114
1115         ADM8211_CSR_WRITE(PAR, reg);
1116
1117         reg = ADM8211_CSR_READ(CSR_TEST1);
1118         reg &= ~(0xF << 28);
1119         reg |= (1 << 28) | (1 << 31);
1120         ADM8211_CSR_WRITE(CSR_TEST1, reg);
1121
1122         /* lose link after 4 lost beacons */
1123         reg = (0x04 << 21) | ADM8211_WCSR_TSFTWE | ADM8211_WCSR_LSOE;
1124         ADM8211_CSR_WRITE(WCSR, reg);
1125
1126         /* Disable APM, enable receive FIFO threshold, and set drain receive
1127          * threshold to store-and-forward */
1128         reg = ADM8211_CSR_READ(CMDR);
1129         reg &= ~(ADM8211_CMDR_APM | ADM8211_CMDR_DRT);
1130         reg |= ADM8211_CMDR_RTE | ADM8211_CMDR_DRT_SF;
1131         ADM8211_CSR_WRITE(CMDR, reg);
1132
1133         adm8211_set_rate(dev);
1134
1135         /* 4-bit values:
1136          * PWR1UP   = 8 * 2 ms
1137          * PWR0PAPE = 8 us or 5 us
1138          * PWR1PAPE = 1 us or 3 us
1139          * PWR0TRSW = 5 us
1140          * PWR1TRSW = 12 us
1141          * PWR0PE2  = 13 us
1142          * PWR1PE2  = 1 us
1143          * PWR0TXPE = 8 or 6 */
1144         if (priv->revid < ADM8211_REV_CA)
1145                 ADM8211_CSR_WRITE(TOFS2, 0x8815cd18);
1146         else
1147                 ADM8211_CSR_WRITE(TOFS2, 0x8535cd16);
1148
1149         /* Enable store and forward for transmit */
1150         priv->nar = ADM8211_NAR_SF | ADM8211_NAR_PB;
1151         ADM8211_CSR_WRITE(NAR, priv->nar);
1152
1153         /* Reset RF */
1154         ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_RADIO);
1155         ADM8211_CSR_READ(SYNRF);
1156         msleep(10);
1157         ADM8211_CSR_WRITE(SYNRF, 0);
1158         ADM8211_CSR_READ(SYNRF);
1159         msleep(5);
1160
1161         /* Set CFP Max Duration to 0x10 TU */
1162         reg = ADM8211_CSR_READ(CFPP);
1163         reg &= ~(0xffff << 8);
1164         reg |= 0x0010 << 8;
1165         ADM8211_CSR_WRITE(CFPP, reg);
1166
1167         /* USCNT = 0x16 (number of system clocks, 22 MHz, in 1us
1168          * TUCNT = 0x3ff - Tu counter 1024 us  */
1169         ADM8211_CSR_WRITE(TOFS0, (0x16 << 24) | 0x3ff);
1170
1171         /* SLOT=20 us, SIFS=110 cycles of 22 MHz (5 us),
1172          * DIFS=50 us, EIFS=100 us */
1173         if (priv->revid < ADM8211_REV_CA)
1174                 ADM8211_CSR_WRITE(IFST, (20 << 23) | (110 << 15) |
1175                                         (50 << 9)  | 100);
1176         else
1177                 ADM8211_CSR_WRITE(IFST, (20 << 23) | (24 << 15) |
1178                                         (50 << 9)  | 100);
1179
1180         /* PCNT = 1 (MAC idle time awake/sleep, unit S)
1181          * RMRD = 2346 * 8 + 1 us (max RX duration)  */
1182         ADM8211_CSR_WRITE(RMD, (1 << 16) | 18769);
1183
1184         /* MART=65535 us, MIRT=256 us, TSFTOFST=0 us */
1185         ADM8211_CSR_WRITE(RSPT, 0xffffff00);
1186
1187         /* Initialize BBP (and SYN) */
1188         adm8211_hw_init_bbp(dev);
1189
1190         /* make sure interrupts are off */
1191         ADM8211_CSR_WRITE(IER, 0);
1192
1193         /* ACK interrupts */
1194         ADM8211_CSR_WRITE(STSR, ADM8211_CSR_READ(STSR));
1195
1196         /* Setup WEP (turns it off for now) */
1197         reg = ADM8211_CSR_READ(MACTEST);
1198         reg &= ~(7 << 20);
1199         ADM8211_CSR_WRITE(MACTEST, reg);
1200
1201         reg = ADM8211_CSR_READ(WEPCTL);
1202         reg &= ~ADM8211_WEPCTL_WEPENABLE;
1203         reg |= ADM8211_WEPCTL_WEPRXBYP;
1204         ADM8211_CSR_WRITE(WEPCTL, reg);
1205
1206         /* Clear the missed-packet counter. */
1207         ADM8211_CSR_READ(LPC);
1208 }
1209
1210 static int adm8211_hw_reset(struct ieee80211_hw *dev)
1211 {
1212         struct adm8211_priv *priv = dev->priv;
1213         u32 reg, tmp;
1214         int timeout = 100;
1215
1216         /* Power-on issue */
1217         /* TODO: check if this is necessary */
1218         ADM8211_CSR_WRITE(FRCTL, 0);
1219
1220         /* Reset the chip */
1221         tmp = ADM8211_CSR_READ(PAR);
1222         ADM8211_CSR_WRITE(PAR, ADM8211_PAR_SWR);
1223
1224         while ((ADM8211_CSR_READ(PAR) & ADM8211_PAR_SWR) && timeout--)
1225                 msleep(50);
1226
1227         if (timeout <= 0)
1228                 return -ETIMEDOUT;
1229
1230         ADM8211_CSR_WRITE(PAR, tmp);
1231
1232         if (priv->revid == ADM8211_REV_BA &&
1233             (priv->transceiver_type == ADM8211_RFMD2958_RF3000_CONTROL_POWER ||
1234              priv->transceiver_type == ADM8211_RFMD2958)) {
1235                 reg = ADM8211_CSR_READ(CSR_TEST1);
1236                 reg |= (1 << 4) | (1 << 5);
1237                 ADM8211_CSR_WRITE(CSR_TEST1, reg);
1238         } else if (priv->revid == ADM8211_REV_CA) {
1239                 reg = ADM8211_CSR_READ(CSR_TEST1);
1240                 reg &= ~((1 << 4) | (1 << 5));
1241                 ADM8211_CSR_WRITE(CSR_TEST1, reg);
1242         }
1243
1244         ADM8211_CSR_WRITE(FRCTL, 0);
1245
1246         reg = ADM8211_CSR_READ(CSR_TEST0);
1247         reg |= ADM8211_CSR_TEST0_EPRLD; /* EEPROM Recall */
1248         ADM8211_CSR_WRITE(CSR_TEST0, reg);
1249
1250         adm8211_clear_sram(dev);
1251
1252         return 0;
1253 }
1254
1255 static u64 adm8211_get_tsft(struct ieee80211_hw *dev)
1256 {
1257         struct adm8211_priv *priv = dev->priv;
1258         u32 tsftl;
1259         u64 tsft;
1260
1261         tsftl = ADM8211_CSR_READ(TSFTL);
1262         tsft = ADM8211_CSR_READ(TSFTH);
1263         tsft <<= 32;
1264         tsft |= tsftl;
1265
1266         return tsft;
1267 }
1268
1269 static void adm8211_set_interval(struct ieee80211_hw *dev,
1270                                  unsigned short bi, unsigned short li)
1271 {
1272         struct adm8211_priv *priv = dev->priv;
1273         u32 reg;
1274
1275         /* BP (beacon interval) = data->beacon_interval
1276          * LI (listen interval) = data->listen_interval (in beacon intervals) */
1277         reg = (bi << 16) | li;
1278         ADM8211_CSR_WRITE(BPLI, reg);
1279 }
1280
1281 static void adm8211_set_bssid(struct ieee80211_hw *dev, const u8 *bssid)
1282 {
1283         struct adm8211_priv *priv = dev->priv;
1284         u32 reg;
1285
1286         reg = bssid[0] | (bssid[1] << 8) | (bssid[2] << 16) | (bssid[3] << 24);
1287         ADM8211_CSR_WRITE(BSSID0, reg);
1288         reg = ADM8211_CSR_READ(ABDA1);
1289         reg &= 0x0000ffff;
1290         reg |= (bssid[4] << 16) | (bssid[5] << 24);
1291         ADM8211_CSR_WRITE(ABDA1, reg);
1292 }
1293
1294 static int adm8211_set_ssid(struct ieee80211_hw *dev, u8 *ssid, size_t ssid_len)
1295 {
1296         struct adm8211_priv *priv = dev->priv;
1297         u8 buf[36];
1298
1299         if (ssid_len > 32)
1300                 return -EINVAL;
1301
1302         memset(buf, 0, sizeof(buf));
1303         buf[0] = ssid_len;
1304         memcpy(buf + 1, ssid, ssid_len);
1305         adm8211_write_sram_bytes(dev, ADM8211_SRAM_SSID, buf, 33);
1306         /* TODO: configure beacon for adhoc? */
1307         return 0;
1308 }
1309
1310 static int adm8211_config(struct ieee80211_hw *dev, struct ieee80211_conf *conf)
1311 {
1312         struct adm8211_priv *priv = dev->priv;
1313
1314         if (conf->channel != priv->channel) {
1315                 priv->channel = conf->channel;
1316                 adm8211_rf_set_channel(dev, priv->channel);
1317         }
1318
1319         return 0;
1320 }
1321
1322 static int adm8211_config_interface(struct ieee80211_hw *dev, int if_id,
1323                                     struct ieee80211_if_conf *conf)
1324 {
1325         struct adm8211_priv *priv = dev->priv;
1326
1327         if (memcmp(conf->bssid, priv->bssid, ETH_ALEN)) {
1328                 adm8211_set_bssid(dev, conf->bssid);
1329                 memcpy(priv->bssid, conf->bssid, ETH_ALEN);
1330         }
1331
1332         if (conf->ssid_len != priv->ssid_len ||
1333             memcmp(conf->ssid, priv->ssid, conf->ssid_len)) {
1334                 adm8211_set_ssid(dev, conf->ssid, conf->ssid_len);
1335                 priv->ssid_len = conf->ssid_len;
1336                 memcpy(priv->ssid, conf->ssid, conf->ssid_len);
1337         }
1338
1339         return 0;
1340 }
1341
1342 static void adm8211_configure_filter(struct ieee80211_hw *dev,
1343                                      unsigned int changed_flags,
1344                                      unsigned int *total_flags,
1345                                      int mc_count, struct dev_mc_list *mclist)
1346 {
1347         static const u8 bcast[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
1348         struct adm8211_priv *priv = dev->priv;
1349         unsigned int bit_nr, new_flags;
1350         u32 mc_filter[2];
1351         int i;
1352
1353         new_flags = 0;
1354
1355         if (*total_flags & FIF_PROMISC_IN_BSS) {
1356                 new_flags |= FIF_PROMISC_IN_BSS;
1357                 priv->nar |= ADM8211_NAR_PR;
1358                 priv->nar &= ~ADM8211_NAR_MM;
1359                 mc_filter[1] = mc_filter[0] = ~0;
1360         } else if ((*total_flags & FIF_ALLMULTI) || (mc_count > 32)) {
1361                 new_flags |= FIF_ALLMULTI;
1362                 priv->nar &= ~ADM8211_NAR_PR;
1363                 priv->nar |= ADM8211_NAR_MM;
1364                 mc_filter[1] = mc_filter[0] = ~0;
1365         } else {
1366                 priv->nar &= ~(ADM8211_NAR_MM | ADM8211_NAR_PR);
1367                 mc_filter[1] = mc_filter[0] = 0;
1368                 for (i = 0; i < mc_count; i++) {
1369                         if (!mclist)
1370                                 break;
1371                         bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
1372
1373                         bit_nr &= 0x3F;
1374                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
1375                         mclist = mclist->next;
1376                 }
1377         }
1378
1379         ADM8211_IDLE_RX();
1380
1381         ADM8211_CSR_WRITE(MAR0, mc_filter[0]);
1382         ADM8211_CSR_WRITE(MAR1, mc_filter[1]);
1383         ADM8211_CSR_READ(NAR);
1384
1385         if (priv->nar & ADM8211_NAR_PR)
1386                 dev->flags |= IEEE80211_HW_RX_INCLUDES_FCS;
1387         else
1388                 dev->flags &= ~IEEE80211_HW_RX_INCLUDES_FCS;
1389
1390         if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
1391                 adm8211_set_bssid(dev, bcast);
1392         else
1393                 adm8211_set_bssid(dev, priv->bssid);
1394
1395         ADM8211_RESTORE();
1396
1397         *total_flags = new_flags;
1398 }
1399
1400 static int adm8211_add_interface(struct ieee80211_hw *dev,
1401                                  struct ieee80211_if_init_conf *conf)
1402 {
1403         struct adm8211_priv *priv = dev->priv;
1404         if (priv->mode != IEEE80211_IF_TYPE_MNTR)
1405                 return -EOPNOTSUPP;
1406
1407         switch (conf->type) {
1408         case IEEE80211_IF_TYPE_STA:
1409                 priv->mode = conf->type;
1410                 break;
1411         default:
1412                 return -EOPNOTSUPP;
1413         }
1414
1415         ADM8211_IDLE();
1416
1417         ADM8211_CSR_WRITE(PAR0, *(u32 *)conf->mac_addr);
1418         ADM8211_CSR_WRITE(PAR1, *(u16 *)(conf->mac_addr + 4));
1419
1420         adm8211_update_mode(dev);
1421
1422         ADM8211_RESTORE();
1423
1424         return 0;
1425 }
1426
1427 static void adm8211_remove_interface(struct ieee80211_hw *dev,
1428                                      struct ieee80211_if_init_conf *conf)
1429 {
1430         struct adm8211_priv *priv = dev->priv;
1431         priv->mode = IEEE80211_IF_TYPE_MNTR;
1432 }
1433
1434 static int adm8211_init_rings(struct ieee80211_hw *dev)
1435 {
1436         struct adm8211_priv *priv = dev->priv;
1437         struct adm8211_desc *desc = NULL;
1438         struct adm8211_rx_ring_info *rx_info;
1439         struct adm8211_tx_ring_info *tx_info;
1440         unsigned int i;
1441
1442         for (i = 0; i < priv->rx_ring_size; i++) {
1443                 desc = &priv->rx_ring[i];
1444                 desc->status = 0;
1445                 desc->length = cpu_to_le32(RX_PKT_SIZE);
1446                 priv->rx_buffers[i].skb = NULL;
1447         }
1448         /* Mark the end of RX ring; hw returns to base address after this
1449          * descriptor */
1450         desc->length |= cpu_to_le32(RDES1_CONTROL_RER);
1451
1452         for (i = 0; i < priv->rx_ring_size; i++) {
1453                 desc = &priv->rx_ring[i];
1454                 rx_info = &priv->rx_buffers[i];
1455
1456                 rx_info->skb = dev_alloc_skb(RX_PKT_SIZE);
1457                 if (rx_info->skb == NULL)
1458                         break;
1459                 rx_info->mapping = pci_map_single(priv->pdev,
1460                                                   skb_tail_pointer(rx_info->skb),
1461                                                   RX_PKT_SIZE,
1462                                                   PCI_DMA_FROMDEVICE);
1463                 desc->buffer1 = cpu_to_le32(rx_info->mapping);
1464                 desc->status = cpu_to_le32(RDES0_STATUS_OWN | RDES0_STATUS_SQL);
1465         }
1466
1467         /* Setup TX ring. TX buffers descriptors will be filled in as needed */
1468         for (i = 0; i < priv->tx_ring_size; i++) {
1469                 desc = &priv->tx_ring[i];
1470                 tx_info = &priv->tx_buffers[i];
1471
1472                 tx_info->skb = NULL;
1473                 tx_info->mapping = 0;
1474                 desc->status = 0;
1475         }
1476         desc->length = cpu_to_le32(TDES1_CONTROL_TER);
1477
1478         priv->cur_rx = priv->cur_tx = priv->dirty_tx = 0;
1479         ADM8211_CSR_WRITE(RDB, priv->rx_ring_dma);
1480         ADM8211_CSR_WRITE(TDBD, priv->tx_ring_dma);
1481
1482         return 0;
1483 }
1484
1485 static void adm8211_free_rings(struct ieee80211_hw *dev)
1486 {
1487         struct adm8211_priv *priv = dev->priv;
1488         unsigned int i;
1489
1490         for (i = 0; i < priv->rx_ring_size; i++) {
1491                 if (!priv->rx_buffers[i].skb)
1492                         continue;
1493
1494                 pci_unmap_single(
1495                         priv->pdev,
1496                         priv->rx_buffers[i].mapping,
1497                         RX_PKT_SIZE, PCI_DMA_FROMDEVICE);
1498
1499                 dev_kfree_skb(priv->rx_buffers[i].skb);
1500         }
1501
1502         for (i = 0; i < priv->tx_ring_size; i++) {
1503                 if (!priv->tx_buffers[i].skb)
1504                         continue;
1505
1506                 pci_unmap_single(priv->pdev,
1507                                  priv->tx_buffers[i].mapping,
1508                                  priv->tx_buffers[i].skb->len,
1509                                  PCI_DMA_TODEVICE);
1510
1511                 dev_kfree_skb(priv->tx_buffers[i].skb);
1512         }
1513 }
1514
1515 static int adm8211_start(struct ieee80211_hw *dev)
1516 {
1517         struct adm8211_priv *priv = dev->priv;
1518         int retval;
1519
1520         /* Power up MAC and RF chips */
1521         retval = adm8211_hw_reset(dev);
1522         if (retval) {
1523                 printk(KERN_ERR "%s: hardware reset failed\n",
1524                        wiphy_name(dev->wiphy));
1525                 goto fail;
1526         }
1527
1528         retval = adm8211_init_rings(dev);
1529         if (retval) {
1530                 printk(KERN_ERR "%s: failed to initialize rings\n",
1531                        wiphy_name(dev->wiphy));
1532                 goto fail;
1533         }
1534
1535         /* Init hardware */
1536         adm8211_hw_init(dev);
1537         adm8211_rf_set_channel(dev, priv->channel);
1538
1539         retval = request_irq(priv->pdev->irq, &adm8211_interrupt,
1540                              IRQF_SHARED, "adm8211", dev);
1541         if (retval) {
1542                 printk(KERN_ERR "%s: failed to register IRQ handler\n",
1543                        wiphy_name(dev->wiphy));
1544                 goto fail;
1545         }
1546
1547         ADM8211_CSR_WRITE(IER, ADM8211_IER_NIE | ADM8211_IER_AIE |
1548                                ADM8211_IER_RCIE | ADM8211_IER_TCIE |
1549                                ADM8211_IER_TDUIE | ADM8211_IER_GPTIE);
1550         adm8211_update_mode(dev);
1551         ADM8211_CSR_WRITE(RDR, 0);
1552
1553         adm8211_set_interval(dev, 100, 10);
1554         return 0;
1555
1556 fail:
1557         return retval;
1558 }
1559
1560 static void adm8211_stop(struct ieee80211_hw *dev)
1561 {
1562         struct adm8211_priv *priv = dev->priv;
1563
1564         priv->nar = 0;
1565         ADM8211_CSR_WRITE(NAR, 0);
1566         ADM8211_CSR_WRITE(IER, 0);
1567         ADM8211_CSR_READ(NAR);
1568
1569         free_irq(priv->pdev->irq, dev);
1570
1571         adm8211_free_rings(dev);
1572 }
1573
1574 static void adm8211_calc_durations(int *dur, int *plcp, size_t payload_len, int len,
1575                                    int plcp_signal, int short_preamble)
1576 {
1577         /* Alternative calculation from NetBSD: */
1578
1579 /* IEEE 802.11b durations for DSSS PHY in microseconds */
1580 #define IEEE80211_DUR_DS_LONG_PREAMBLE  144
1581 #define IEEE80211_DUR_DS_SHORT_PREAMBLE 72
1582 #define IEEE80211_DUR_DS_FAST_PLCPHDR   24
1583 #define IEEE80211_DUR_DS_SLOW_PLCPHDR   48
1584 #define IEEE80211_DUR_DS_SLOW_ACK       112
1585 #define IEEE80211_DUR_DS_FAST_ACK       56
1586 #define IEEE80211_DUR_DS_SLOW_CTS       112
1587 #define IEEE80211_DUR_DS_FAST_CTS       56
1588 #define IEEE80211_DUR_DS_SLOT           20
1589 #define IEEE80211_DUR_DS_SIFS           10
1590
1591         int remainder;
1592
1593         *dur = (80 * (24 + payload_len) + plcp_signal - 1)
1594                 / plcp_signal;
1595
1596         if (plcp_signal <= PLCP_SIGNAL_2M)
1597                 /* 1-2Mbps WLAN: send ACK/CTS at 1Mbps */
1598                 *dur += 3 * (IEEE80211_DUR_DS_SIFS +
1599                              IEEE80211_DUR_DS_SHORT_PREAMBLE +
1600                              IEEE80211_DUR_DS_FAST_PLCPHDR) +
1601                              IEEE80211_DUR_DS_SLOW_CTS + IEEE80211_DUR_DS_SLOW_ACK;
1602         else
1603                 /* 5-11Mbps WLAN: send ACK/CTS at 2Mbps */
1604                 *dur += 3 * (IEEE80211_DUR_DS_SIFS +
1605                              IEEE80211_DUR_DS_SHORT_PREAMBLE +
1606                              IEEE80211_DUR_DS_FAST_PLCPHDR) +
1607                              IEEE80211_DUR_DS_FAST_CTS + IEEE80211_DUR_DS_FAST_ACK;
1608
1609         /* lengthen duration if long preamble */
1610         if (!short_preamble)
1611                 *dur += 3 * (IEEE80211_DUR_DS_LONG_PREAMBLE -
1612                              IEEE80211_DUR_DS_SHORT_PREAMBLE) +
1613                         3 * (IEEE80211_DUR_DS_SLOW_PLCPHDR -
1614                              IEEE80211_DUR_DS_FAST_PLCPHDR);
1615
1616
1617         *plcp = (80 * len) / plcp_signal;
1618         remainder = (80 * len) % plcp_signal;
1619         if (plcp_signal == PLCP_SIGNAL_11M &&
1620             remainder <= 30 && remainder > 0)
1621                 *plcp = (*plcp | 0x8000) + 1;
1622         else if (remainder)
1623                 (*plcp)++;
1624 }
1625
1626 /* Transmit skb w/adm8211_tx_hdr (802.11 header created by hardware) */
1627 static void adm8211_tx_raw(struct ieee80211_hw *dev, struct sk_buff *skb,
1628                            u16 plcp_signal,
1629                            struct ieee80211_tx_control *control,
1630                            size_t hdrlen)
1631 {
1632         struct adm8211_priv *priv = dev->priv;
1633         unsigned long flags;
1634         dma_addr_t mapping;
1635         unsigned int entry;
1636         u32 flag;
1637
1638         mapping = pci_map_single(priv->pdev, skb->data, skb->len,
1639                                  PCI_DMA_TODEVICE);
1640
1641         spin_lock_irqsave(&priv->lock, flags);
1642
1643         if (priv->cur_tx - priv->dirty_tx == priv->tx_ring_size / 2)
1644                 flag = TDES1_CONTROL_IC | TDES1_CONTROL_LS | TDES1_CONTROL_FS;
1645         else
1646                 flag = TDES1_CONTROL_LS | TDES1_CONTROL_FS;
1647
1648         if (priv->cur_tx - priv->dirty_tx == priv->tx_ring_size - 2)
1649                 ieee80211_stop_queue(dev, 0);
1650
1651         entry = priv->cur_tx % priv->tx_ring_size;
1652
1653         priv->tx_buffers[entry].skb = skb;
1654         priv->tx_buffers[entry].mapping = mapping;
1655         memcpy(&priv->tx_buffers[entry].tx_control, control, sizeof(*control));
1656         priv->tx_buffers[entry].hdrlen = hdrlen;
1657         priv->tx_ring[entry].buffer1 = cpu_to_le32(mapping);
1658
1659         if (entry == priv->tx_ring_size - 1)
1660                 flag |= TDES1_CONTROL_TER;
1661         priv->tx_ring[entry].length = cpu_to_le32(flag | skb->len);
1662
1663         /* Set TX rate (SIGNAL field in PLCP PPDU format) */
1664         flag = TDES0_CONTROL_OWN | (plcp_signal << 20) | 8 /* ? */;
1665         priv->tx_ring[entry].status = cpu_to_le32(flag);
1666
1667         priv->cur_tx++;
1668
1669         spin_unlock_irqrestore(&priv->lock, flags);
1670
1671         /* Trigger transmit poll */
1672         ADM8211_CSR_WRITE(TDR, 0);
1673 }
1674
1675 /* Put adm8211_tx_hdr on skb and transmit */
1676 static int adm8211_tx(struct ieee80211_hw *dev, struct sk_buff *skb,
1677                       struct ieee80211_tx_control *control)
1678 {
1679         struct adm8211_tx_hdr *txhdr;
1680         u16 fc;
1681         size_t payload_len, hdrlen;
1682         int plcp, dur, len, plcp_signal, short_preamble;
1683         struct ieee80211_hdr *hdr;
1684
1685         if (control->tx_rate < 0) {
1686                 short_preamble = 1;
1687                 plcp_signal = -control->tx_rate;
1688         } else {
1689                 short_preamble = 0;
1690                 plcp_signal = control->tx_rate;
1691         }
1692
1693         hdr = (struct ieee80211_hdr *)skb->data;
1694         fc = le16_to_cpu(hdr->frame_control) & ~IEEE80211_FCTL_PROTECTED;
1695         hdrlen = ieee80211_get_hdrlen(fc);
1696         memcpy(skb->cb, skb->data, hdrlen);
1697         hdr = (struct ieee80211_hdr *)skb->cb;
1698         skb_pull(skb, hdrlen);
1699         payload_len = skb->len;
1700
1701         txhdr = (struct adm8211_tx_hdr *) skb_push(skb, sizeof(*txhdr));
1702         memset(txhdr, 0, sizeof(*txhdr));
1703         memcpy(txhdr->da, ieee80211_get_DA(hdr), ETH_ALEN);
1704         txhdr->signal = plcp_signal;
1705         txhdr->frame_body_size = cpu_to_le16(payload_len);
1706         txhdr->frame_control = hdr->frame_control;
1707
1708         len = hdrlen + payload_len + FCS_LEN;
1709         if (fc & IEEE80211_FCTL_PROTECTED)
1710                 len += 8;
1711
1712         txhdr->frag = cpu_to_le16(0x0FFF);
1713         adm8211_calc_durations(&dur, &plcp, payload_len,
1714                                len, plcp_signal, short_preamble);
1715         txhdr->plcp_frag_head_len = cpu_to_le16(plcp);
1716         txhdr->plcp_frag_tail_len = cpu_to_le16(plcp);
1717         txhdr->dur_frag_head = cpu_to_le16(dur);
1718         txhdr->dur_frag_tail = cpu_to_le16(dur);
1719
1720         txhdr->header_control = cpu_to_le16(ADM8211_TXHDRCTL_ENABLE_EXTEND_HEADER);
1721
1722         if (short_preamble)
1723                 txhdr->header_control |= cpu_to_le16(ADM8211_TXHDRCTL_SHORT_PREAMBLE);
1724
1725         if (control->flags & IEEE80211_TXCTL_USE_RTS_CTS)
1726                 txhdr->header_control |= cpu_to_le16(ADM8211_TXHDRCTL_ENABLE_RTS);
1727
1728         if (fc & IEEE80211_FCTL_PROTECTED)
1729                 txhdr->header_control |= cpu_to_le16(ADM8211_TXHDRCTL_ENABLE_WEP_ENGINE);
1730
1731         txhdr->retry_limit = control->retry_limit;
1732
1733         adm8211_tx_raw(dev, skb, plcp_signal, control, hdrlen);
1734
1735         return NETDEV_TX_OK;
1736 }
1737
1738 static int adm8211_alloc_rings(struct ieee80211_hw *dev)
1739 {
1740         struct adm8211_priv *priv = dev->priv;
1741         unsigned int ring_size;
1742
1743         priv->rx_buffers = kmalloc(sizeof(*priv->rx_buffers) * priv->rx_ring_size +
1744                                    sizeof(*priv->tx_buffers) * priv->tx_ring_size, GFP_KERNEL);
1745         if (!priv->rx_buffers)
1746                 return -ENOMEM;
1747
1748         priv->tx_buffers = (void *)priv->rx_buffers +
1749                            sizeof(*priv->rx_buffers) * priv->rx_ring_size;
1750
1751         /* Allocate TX/RX descriptors */
1752         ring_size = sizeof(struct adm8211_desc) * priv->rx_ring_size +
1753                     sizeof(struct adm8211_desc) * priv->tx_ring_size;
1754         priv->rx_ring = pci_alloc_consistent(priv->pdev, ring_size,
1755                                              &priv->rx_ring_dma);
1756
1757         if (!priv->rx_ring) {
1758                 kfree(priv->rx_buffers);
1759                 priv->rx_buffers = NULL;
1760                 priv->tx_buffers = NULL;
1761                 return -ENOMEM;
1762         }
1763
1764         priv->tx_ring = (struct adm8211_desc *)(priv->rx_ring +
1765                                                 priv->rx_ring_size);
1766         priv->tx_ring_dma = priv->rx_ring_dma +
1767                             sizeof(struct adm8211_desc) * priv->rx_ring_size;
1768
1769         return 0;
1770 }
1771
1772 static const struct ieee80211_ops adm8211_ops = {
1773         .tx                     = adm8211_tx,
1774         .start                  = adm8211_start,
1775         .stop                   = adm8211_stop,
1776         .add_interface          = adm8211_add_interface,
1777         .remove_interface       = adm8211_remove_interface,
1778         .config                 = adm8211_config,
1779         .config_interface       = adm8211_config_interface,
1780         .configure_filter       = adm8211_configure_filter,
1781         .get_stats              = adm8211_get_stats,
1782         .get_tx_stats           = adm8211_get_tx_stats,
1783         .get_tsf                = adm8211_get_tsft
1784 };
1785
1786 static int __devinit adm8211_probe(struct pci_dev *pdev,
1787                                    const struct pci_device_id *id)
1788 {
1789         struct ieee80211_hw *dev;
1790         struct adm8211_priv *priv;
1791         unsigned long mem_addr, mem_len;
1792         unsigned int io_addr, io_len;
1793         int err;
1794         u32 reg;
1795         u8 perm_addr[ETH_ALEN];
1796         DECLARE_MAC_BUF(mac);
1797
1798 #ifndef MODULE
1799         static unsigned int cardidx;
1800         if (!cardidx++)
1801                 printk(version);
1802 #endif
1803
1804         err = pci_enable_device(pdev);
1805         if (err) {
1806                 printk(KERN_ERR "%s (adm8211): Cannot enable new PCI device\n",
1807                        pci_name(pdev));
1808                 return err;
1809         }
1810
1811         io_addr = pci_resource_start(pdev, 0);
1812         io_len = pci_resource_len(pdev, 0);
1813         mem_addr = pci_resource_start(pdev, 1);
1814         mem_len = pci_resource_len(pdev, 1);
1815         if (io_len < 256 || mem_len < 1024) {
1816                 printk(KERN_ERR "%s (adm8211): Too short PCI resources\n",
1817                        pci_name(pdev));
1818                 goto err_disable_pdev;
1819         }
1820
1821
1822         /* check signature */
1823         pci_read_config_dword(pdev, 0x80 /* CR32 */, &reg);
1824         if (reg != ADM8211_SIG1 && reg != ADM8211_SIG2) {
1825                 printk(KERN_ERR "%s (adm8211): Invalid signature (0x%x)\n",
1826                        pci_name(pdev), reg);
1827                 goto err_disable_pdev;
1828         }
1829
1830         err = pci_request_regions(pdev, "adm8211");
1831         if (err) {
1832                 printk(KERN_ERR "%s (adm8211): Cannot obtain PCI resources\n",
1833                        pci_name(pdev));
1834                 return err; /* someone else grabbed it? don't disable it */
1835         }
1836
1837         if (pci_set_dma_mask(pdev, DMA_32BIT_MASK) ||
1838             pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK)) {
1839                 printk(KERN_ERR "%s (adm8211): No suitable DMA available\n",
1840                        pci_name(pdev));
1841                 goto err_free_reg;
1842         }
1843
1844         pci_set_master(pdev);
1845
1846         dev = ieee80211_alloc_hw(sizeof(*priv), &adm8211_ops);
1847         if (!dev) {
1848                 printk(KERN_ERR "%s (adm8211): ieee80211 alloc failed\n",
1849                        pci_name(pdev));
1850                 err = -ENOMEM;
1851                 goto err_free_reg;
1852         }
1853         priv = dev->priv;
1854         priv->pdev = pdev;
1855
1856         spin_lock_init(&priv->lock);
1857
1858         SET_IEEE80211_DEV(dev, &pdev->dev);
1859
1860         pci_set_drvdata(pdev, dev);
1861
1862         priv->map = pci_iomap(pdev, 1, mem_len);
1863         if (!priv->map)
1864                 priv->map = pci_iomap(pdev, 0, io_len);
1865
1866         if (!priv->map) {
1867                 printk(KERN_ERR "%s (adm8211): Cannot map device memory\n",
1868                        pci_name(pdev));
1869                 goto err_free_dev;
1870         }
1871
1872         priv->rx_ring_size = rx_ring_size;
1873         priv->tx_ring_size = tx_ring_size;
1874
1875         if (adm8211_alloc_rings(dev)) {
1876                 printk(KERN_ERR "%s (adm8211): Cannot allocate TX/RX ring\n",
1877                        pci_name(pdev));
1878                 goto err_iounmap;
1879         }
1880
1881         pci_read_config_byte(pdev, PCI_CLASS_REVISION, &priv->revid);
1882
1883         *(u32 *)perm_addr = le32_to_cpu((__force __le32)ADM8211_CSR_READ(PAR0));
1884         *(u16 *)&perm_addr[4] =
1885                 le16_to_cpu((__force __le16)ADM8211_CSR_READ(PAR1) & 0xFFFF);
1886
1887         if (!is_valid_ether_addr(perm_addr)) {
1888                 printk(KERN_WARNING "%s (adm8211): Invalid hwaddr in EEPROM!\n",
1889                        pci_name(pdev));
1890                 random_ether_addr(perm_addr);
1891         }
1892         SET_IEEE80211_PERM_ADDR(dev, perm_addr);
1893
1894         dev->extra_tx_headroom = sizeof(struct adm8211_tx_hdr);
1895         dev->flags = IEEE80211_HW_DEFAULT_REG_DOMAIN_CONFIGURED;
1896         /* IEEE80211_HW_RX_INCLUDES_FCS in promisc mode */
1897
1898         dev->channel_change_time = 1000;
1899         dev->max_rssi = 100;    /* FIXME: find better value */
1900
1901         priv->modes[0].mode = MODE_IEEE80211B;
1902         /* channel info filled in by adm8211_read_eeprom */
1903         memcpy(priv->rates, adm8211_rates, sizeof(adm8211_rates));
1904         priv->modes[0].num_rates = ARRAY_SIZE(adm8211_rates);
1905         priv->modes[0].rates = priv->rates;
1906
1907         dev->queues = 1; /* ADM8211C supports more, maybe ADM8211B too */
1908
1909         priv->retry_limit = 3;
1910         priv->ant_power = 0x40;
1911         priv->tx_power = 0x40;
1912         priv->lpf_cutoff = 0xFF;
1913         priv->lnags_threshold = 0xFF;
1914         priv->mode = IEEE80211_IF_TYPE_MNTR;
1915
1916         /* Power-on issue. EEPROM won't read correctly without */
1917         if (priv->revid >= ADM8211_REV_BA) {
1918                 ADM8211_CSR_WRITE(FRCTL, 0);
1919                 ADM8211_CSR_READ(FRCTL);
1920                 ADM8211_CSR_WRITE(FRCTL, 1);
1921                 ADM8211_CSR_READ(FRCTL);
1922                 msleep(100);
1923         }
1924
1925         err = adm8211_read_eeprom(dev);
1926         if (err) {
1927                 printk(KERN_ERR "%s (adm8211): Can't alloc eeprom buffer\n",
1928                        pci_name(pdev));
1929                 goto err_free_desc;
1930         }
1931
1932         priv->channel = priv->modes[0].channels[0].chan;
1933
1934         err = ieee80211_register_hwmode(dev, &priv->modes[0]);
1935         if (err) {
1936                 printk(KERN_ERR "%s (adm8211): Can't register hwmode\n",
1937                        pci_name(pdev));
1938                 goto err_free_desc;
1939         }
1940
1941         err = ieee80211_register_hw(dev);
1942         if (err) {
1943                 printk(KERN_ERR "%s (adm8211): Cannot register device\n",
1944                        pci_name(pdev));
1945                 goto err_free_desc;
1946         }
1947
1948         printk(KERN_INFO "%s: hwaddr %s, Rev 0x%02x\n",
1949                wiphy_name(dev->wiphy), print_mac(mac, dev->wiphy->perm_addr),
1950                priv->revid);
1951
1952         return 0;
1953
1954  err_free_desc:
1955         pci_free_consistent(pdev,
1956                             sizeof(struct adm8211_desc) * priv->rx_ring_size +
1957                             sizeof(struct adm8211_desc) * priv->tx_ring_size,
1958                             priv->rx_ring, priv->rx_ring_dma);
1959         kfree(priv->rx_buffers);
1960
1961  err_iounmap:
1962         pci_iounmap(pdev, priv->map);
1963
1964  err_free_dev:
1965         pci_set_drvdata(pdev, NULL);
1966         ieee80211_free_hw(dev);
1967
1968  err_free_reg:
1969         pci_release_regions(pdev);
1970
1971  err_disable_pdev:
1972         pci_disable_device(pdev);
1973         return err;
1974 }
1975
1976
1977 static void __devexit adm8211_remove(struct pci_dev *pdev)
1978 {
1979         struct ieee80211_hw *dev = pci_get_drvdata(pdev);
1980         struct adm8211_priv *priv;
1981
1982         if (!dev)
1983                 return;
1984
1985         ieee80211_unregister_hw(dev);
1986
1987         priv = dev->priv;
1988
1989         pci_free_consistent(pdev,
1990                             sizeof(struct adm8211_desc) * priv->rx_ring_size +
1991                             sizeof(struct adm8211_desc) * priv->tx_ring_size,
1992                             priv->rx_ring, priv->rx_ring_dma);
1993
1994         kfree(priv->rx_buffers);
1995         kfree(priv->eeprom);
1996         pci_iounmap(pdev, priv->map);
1997         pci_release_regions(pdev);
1998         pci_disable_device(pdev);
1999         ieee80211_free_hw(dev);
2000 }
2001
2002
2003 #ifdef CONFIG_PM
2004 static int adm8211_suspend(struct pci_dev *pdev, pm_message_t state)
2005 {
2006         struct ieee80211_hw *dev = pci_get_drvdata(pdev);
2007         struct adm8211_priv *priv = dev->priv;
2008
2009         if (priv->mode != IEEE80211_IF_TYPE_MNTR) {
2010                 ieee80211_stop_queues(dev);
2011                 adm8211_stop(dev);
2012         }
2013
2014         pci_save_state(pdev);
2015         pci_set_power_state(pdev, pci_choose_state(pdev, state));
2016         return 0;
2017 }
2018
2019 static int adm8211_resume(struct pci_dev *pdev)
2020 {
2021         struct ieee80211_hw *dev = pci_get_drvdata(pdev);
2022         struct adm8211_priv *priv = dev->priv;
2023
2024         pci_set_power_state(pdev, PCI_D0);
2025         pci_restore_state(pdev);
2026
2027         if (priv->mode != IEEE80211_IF_TYPE_MNTR) {
2028                 adm8211_start(dev);
2029                 ieee80211_start_queues(dev);
2030         }
2031
2032         return 0;
2033 }
2034 #endif /* CONFIG_PM */
2035
2036
2037 MODULE_DEVICE_TABLE(pci, adm8211_pci_id_table);
2038
2039 /* TODO: implement enable_wake */
2040 static struct pci_driver adm8211_driver = {
2041         .name           = "adm8211",
2042         .id_table       = adm8211_pci_id_table,
2043         .probe          = adm8211_probe,
2044         .remove         = __devexit_p(adm8211_remove),
2045 #ifdef CONFIG_PM
2046         .suspend        = adm8211_suspend,
2047         .resume         = adm8211_resume,
2048 #endif /* CONFIG_PM */
2049 };
2050
2051
2052
2053 static int __init adm8211_init(void)
2054 {
2055 #ifdef MODULE
2056         printk(version);
2057 #endif
2058
2059         return pci_register_driver(&adm8211_driver);
2060 }
2061
2062
2063 static void __exit adm8211_exit(void)
2064 {
2065         pci_unregister_driver(&adm8211_driver);
2066 }
2067
2068
2069 module_init(adm8211_init);
2070 module_exit(adm8211_exit);