SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/net/wireless/adm8211.c

   1
   2 /*
   3  * Linux device driver for ADMtek ADM8211 (IEEE 802.11b MAC/BBP)
   4  *
   5  * Copyright (c) 2003, Jouni Malinen <j@w1.fi>
   6  * Copyright (c) 2004-2007, Michael Wu <flamingice@sourmilk.net>
   7  * Some parts copyright (c) 2003 by David Young <dyoung@pobox.com>
   8  * and used with permission.
   9  *
  10  * Much thanks to Infineon-ADMtek for their support of this driver.
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License version 2 as
  14  * published by the Free Software Foundation. See README and COPYING for
  15  * more details.
  16  */
  17
  18 #include <linux/init.h>
  19 #include <linux/if.h>
  20 #include <linux/skbuff.h>
  21 #include <linux/slab.h>
  22 #include <linux/etherdevice.h>
  23 #include <linux/pci.h>
  24 #include <linux/delay.h>
  25 #include <linux/crc32.h>
  26 #include <linux/eeprom_93cx6.h>
  27 #include <net/mac80211.h>
  28
  29 #include "adm8211.h"
  30
  31 MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>");
  32 MODULE_AUTHOR("Jouni Malinen <j@w1.fi>");
  33 MODULE_DESCRIPTION("Driver for IEEE 802.11b wireless cards based on ADMtek ADM8211");
  34 MODULE_SUPPORTED_DEVICE("ADM8211");
  35 MODULE_LICENSE("GPL");
  36
  37 static unsigned int tx_ring_size __read_mostly = 16;
  38 static unsigned int rx_ring_size __read_mostly = 16;
  39
  40 module_param(tx_ring_size, uint, 0);
  41 module_param(rx_ring_size, uint, 0);
  42
  43 static DEFINE_PCI_DEVICE_TABLE(adm8211_pci_id_table) = {
  44         /* ADMtek ADM8211 */
  45         { PCI_DEVICE(0x10B7, 0x6000) }, /* 3Com 3CRSHPW796 */
  46         { PCI_DEVICE(0x1200, 0x8201) }, /* ? */
  47         { PCI_DEVICE(0x1317, 0x8201) }, /* ADM8211A */
  48         { PCI_DEVICE(0x1317, 0x8211) }, /* ADM8211B/C */
  49         { 0 }
  50 };
  51
  52 static struct ieee80211_rate adm8211_rates[] = {
  53         { .bitrate = 10, .flags = IEEE80211_RATE_SHORT_PREAMBLE },
  54         { .bitrate = 20, .flags = IEEE80211_RATE_SHORT_PREAMBLE },
  55         { .bitrate = 55, .flags = IEEE80211_RATE_SHORT_PREAMBLE },
  56         { .bitrate = 110, .flags = IEEE80211_RATE_SHORT_PREAMBLE },
  57         { .bitrate = 220, .flags = IEEE80211_RATE_SHORT_PREAMBLE }, /* XX ?? */
  58 };
  59
  60 static const struct ieee80211_channel adm8211_channels[] = {
  61         { .center_freq = 2412},
  62         { .center_freq = 2417},
  63         { .center_freq = 2422},
  64         { .center_freq = 2427},
  65         { .center_freq = 2432},
  66         { .center_freq = 2437},
  67         { .center_freq = 2442},
  68         { .center_freq = 2447},
  69         { .center_freq = 2452},
  70         { .center_freq = 2457},
  71         { .center_freq = 2462},
  72         { .center_freq = 2467},
  73         { .center_freq = 2472},
  74         { .center_freq = 2484},
  75 };
  76
  77
  78 static void adm8211_eeprom_register_read(struct eeprom_93cx6 *eeprom)
  79 {
  80         struct adm8211_priv *priv = eeprom->data;
  81         u32 reg = ADM8211_CSR_READ(SPR);
  82
  83         eeprom->reg_data_in = reg & ADM8211_SPR_SDI;
  84         eeprom->reg_data_out = reg & ADM8211_SPR_SDO;
  85         eeprom->reg_data_clock = reg & ADM8211_SPR_SCLK;
  86         eeprom->reg_chip_select = reg & ADM8211_SPR_SCS;
  87 }
  88
  89 static void adm8211_eeprom_register_write(struct eeprom_93cx6 *eeprom)
  90 {
  91         struct adm8211_priv *priv = eeprom->data;
  92         u32 reg = 0x4000 | ADM8211_SPR_SRS;
  93
  94         if (eeprom->reg_data_in)
  95                 reg |= ADM8211_SPR_SDI;
  96         if (eeprom->reg_data_out)
  97                 reg |= ADM8211_SPR_SDO;
  98         if (eeprom->reg_data_clock)
  99                 reg |= ADM8211_SPR_SCLK;
 100         if (eeprom->reg_chip_select)
 101                 reg |= ADM8211_SPR_SCS;
 102
 103         ADM8211_CSR_WRITE(SPR, reg);
 104         ADM8211_CSR_READ(SPR);          /* eeprom_delay */
 105 }
 106
 107 static int adm8211_read_eeprom(struct ieee80211_hw *dev)
 108 {
 109         struct adm8211_priv *priv = dev->priv;
 110         unsigned int words, i;
 111         struct ieee80211_chan_range chan_range;
 112         u16 cr49;
 113         struct eeprom_93cx6 eeprom = {
 114                 .data           = priv,
 115                 .register_read  = adm8211_eeprom_register_read,
 116                 .register_write = adm8211_eeprom_register_write
 117         };
 118
 119         if (ADM8211_CSR_READ(CSR_TEST0) & ADM8211_CSR_TEST0_EPTYP) {
 120                 /* 256 * 16-bit = 512 bytes */
 121                 eeprom.width = PCI_EEPROM_WIDTH_93C66;
 122                 words = 256;
 123         } else {
 124                 /* 64 * 16-bit = 128 bytes */
 125                 eeprom.width = PCI_EEPROM_WIDTH_93C46;
 126                 words = 64;
 127         }
 128
 129         priv->eeprom_len = words * 2;
 130         priv->eeprom = kmalloc(priv->eeprom_len, GFP_KERNEL);
 131         if (!priv->eeprom)
 132                 return -ENOMEM;
 133
 134         eeprom_93cx6_multiread(&eeprom, 0, (__le16 *)priv->eeprom, words);
 135
 136         cr49 = le16_to_cpu(priv->eeprom->cr49);
 137         priv->rf_type = (cr49 >> 3) & 0x7;
 138         switch (priv->rf_type) {
 139         case ADM8211_TYPE_INTERSIL:
 140         case ADM8211_TYPE_RFMD:
 141         case ADM8211_TYPE_MARVEL:
 142         case ADM8211_TYPE_AIROHA:
 143         case ADM8211_TYPE_ADMTEK:
 144                 break;
 145
 146         default:
 147                 if (priv->pdev->revision < ADM8211_REV_CA)
 148                         priv->rf_type = ADM8211_TYPE_RFMD;
 149                 else
 150                         priv->rf_type = ADM8211_TYPE_AIROHA;
 151
 152                 printk(KERN_WARNING "%s (adm8211): Unknown RFtype %d\n",
 153                        pci_name(priv->pdev), (cr49 >> 3) & 0x7);
 154         }
 155
 156         priv->bbp_type = cr49 & 0x7;
 157         switch (priv->bbp_type) {
 158         case ADM8211_TYPE_INTERSIL:
 159         case ADM8211_TYPE_RFMD:
 160         case ADM8211_TYPE_MARVEL:
 161         case ADM8211_TYPE_AIROHA:
 162         case ADM8211_TYPE_ADMTEK:
 163                 break;
 164         default:
 165                 if (priv->pdev->revision < ADM8211_REV_CA)
 166                         priv->bbp_type = ADM8211_TYPE_RFMD;
 167                 else
 168                         priv->bbp_type = ADM8211_TYPE_ADMTEK;
 169
 170                 printk(KERN_WARNING "%s (adm8211): Unknown BBPtype: %d\n",
 171                        pci_name(priv->pdev), cr49 >> 3);
 172         }
 173
 174         if (priv->eeprom->country_code >= ARRAY_SIZE(cranges)) {
 175                 printk(KERN_WARNING "%s (adm8211): Invalid country code (%d)\n",
 176                        pci_name(priv->pdev), priv->eeprom->country_code);
 177
 178                 chan_range = cranges[2];
 179         } else
 180                 chan_range = cranges[priv->eeprom->country_code];
 181
 182         printk(KERN_DEBUG "%s (adm8211): Channel range: %d - %d\n",
 183                pci_name(priv->pdev), (int)chan_range.min, (int)chan_range.max);
 184
 185         BUILD_BUG_ON(sizeof(priv->channels) != sizeof(adm8211_channels));
 186
 187         memcpy(priv->channels, adm8211_channels, sizeof(priv->channels));
 188         priv->band.channels = priv->channels;
 189         priv->band.n_channels = ARRAY_SIZE(adm8211_channels);
 190         priv->band.bitrates = adm8211_rates;
 191         priv->band.n_bitrates = ARRAY_SIZE(adm8211_rates);
 192
 193         for (i = 1; i <= ARRAY_SIZE(adm8211_channels); i++)
 194                 if (i < chan_range.min || i > chan_range.max)
 195                         priv->channels[i - 1].flags |= IEEE80211_CHAN_DISABLED;
 196
 197         switch (priv->eeprom->specific_bbptype) {
 198         case ADM8211_BBP_RFMD3000:
 199         case ADM8211_BBP_RFMD3002:
 200         case ADM8211_BBP_ADM8011:
 201                 priv->specific_bbptype = priv->eeprom->specific_bbptype;
 202                 break;
 203
 204         default:
 205                 if (priv->pdev->revision < ADM8211_REV_CA)
 206                         priv->specific_bbptype = ADM8211_BBP_RFMD3000;
 207                 else
 208                         priv->specific_bbptype = ADM8211_BBP_ADM8011;
 209
 210                 printk(KERN_WARNING "%s (adm8211): Unknown specific BBP: %d\n",
 211                        pci_name(priv->pdev), priv->eeprom->specific_bbptype);
 212         }
 213
 214         switch (priv->eeprom->specific_rftype) {
 215         case ADM8211_RFMD2948:
 216         case ADM8211_RFMD2958:
 217         case ADM8211_RFMD2958_RF3000_CONTROL_POWER:
 218         case ADM8211_MAX2820:
 219         case ADM8211_AL2210L:
 220                 priv->transceiver_type = priv->eeprom->specific_rftype;
 221                 break;
 222
 223         default:
 224                 if (priv->pdev->revision == ADM8211_REV_BA)
 225                         priv->transceiver_type = ADM8211_RFMD2958_RF3000_CONTROL_POWER;
 226                 else if (priv->pdev->revision == ADM8211_REV_CA)
 227                         priv->transceiver_type = ADM8211_AL2210L;
 228                 else if (priv->pdev->revision == ADM8211_REV_AB)
 229                         priv->transceiver_type = ADM8211_RFMD2948;
 230
 231                 printk(KERN_WARNING "%s (adm8211): Unknown transceiver: %d\n",
 232                        pci_name(priv->pdev), priv->eeprom->specific_rftype);
 233
 234                 break;
 235         }
 236
 237         printk(KERN_DEBUG "%s (adm8211): RFtype=%d BBPtype=%d Specific BBP=%d "
 238                "Transceiver=%d\n", pci_name(priv->pdev), priv->rf_type,
 239                priv->bbp_type, priv->specific_bbptype, priv->transceiver_type);
 240
 241         return 0;
 242 }
 243
 244 static inline void adm8211_write_sram(struct ieee80211_hw *dev,
 245                                       u32 addr, u32 data)
 246 {
 247         struct adm8211_priv *priv = dev->priv;
 248
 249         ADM8211_CSR_WRITE(WEPCTL, addr | ADM8211_WEPCTL_TABLE_WR |
 250                           (priv->pdev->revision < ADM8211_REV_BA ?
 251                            0 : ADM8211_WEPCTL_SEL_WEPTABLE ));
 252         ADM8211_CSR_READ(WEPCTL);
 253         msleep(1);
 254
 255         ADM8211_CSR_WRITE(WESK, data);
 256         ADM8211_CSR_READ(WESK);
 257         msleep(1);
 258 }
 259
 260 static void adm8211_write_sram_bytes(struct ieee80211_hw *dev,
 261                                      unsigned int addr, u8 *buf,
 262                                      unsigned int len)
 263 {
 264         struct adm8211_priv *priv = dev->priv;
 265         u32 reg = ADM8211_CSR_READ(WEPCTL);
 266         unsigned int i;
 267
 268         if (priv->pdev->revision < ADM8211_REV_BA) {
 269                 for (i = 0; i < len; i += 2) {
 270                         u16 val = buf[i] | (buf[i + 1] << 8);
 271                         adm8211_write_sram(dev, addr + i / 2, val);
 272                 }
 273         } else {
 274                 for (i = 0; i < len; i += 4) {
 275                         u32 val = (buf[i + 0] << 0 ) | (buf[i + 1] << 8 ) |
 276                                   (buf[i + 2] << 16) | (buf[i + 3] << 24);
 277                         adm8211_write_sram(dev, addr + i / 4, val);
 278                 }
 279         }
 280
 281         ADM8211_CSR_WRITE(WEPCTL, reg);
 282 }
 283
 284 static void adm8211_clear_sram(struct ieee80211_hw *dev)
 285 {
 286         struct adm8211_priv *priv = dev->priv;
 287         u32 reg = ADM8211_CSR_READ(WEPCTL);
 288         unsigned int addr;
 289
 290         for (addr = 0; addr < ADM8211_SRAM_SIZE; addr++)
 291                 adm8211_write_sram(dev, addr, 0);
 292
 293         ADM8211_CSR_WRITE(WEPCTL, reg);
 294 }
 295
 296 static int adm8211_get_stats(struct ieee80211_hw *dev,
 297                              struct ieee80211_low_level_stats *stats)
 298 {
 299         struct adm8211_priv *priv = dev->priv;
 300
 301         memcpy(stats, &priv->stats, sizeof(*stats));
 302
 303         return 0;
 304 }
 305
 306 static void adm8211_interrupt_tci(struct ieee80211_hw *dev)
 307 {
 308         struct adm8211_priv *priv = dev->priv;
 309         unsigned int dirty_tx;
 310
 311         spin_lock(&priv->lock);
 312
 313         for (dirty_tx = priv->dirty_tx; priv->cur_tx - dirty_tx; dirty_tx++) {
 314                 unsigned int entry = dirty_tx % priv->tx_ring_size;
 315                 u32 status = le32_to_cpu(priv->tx_ring[entry].status);
 316                 struct ieee80211_tx_info *txi;
 317                 struct adm8211_tx_ring_info *info;
 318                 struct sk_buff *skb;
 319
 320                 if (status & TDES0_CONTROL_OWN ||
 321                     !(status & TDES0_CONTROL_DONE))
 322                         break;
 323
 324                 info = &priv->tx_buffers[entry];
 325                 skb = info->skb;
 326                 txi = IEEE80211_SKB_CB(skb);
 327
 328                 /* TODO: check TDES0_STATUS_TUF and TDES0_STATUS_TRO */
 329
 330                 pci_unmap_single(priv->pdev, info->mapping,
 331                                  info->skb->len, PCI_DMA_TODEVICE);
 332
 333                 ieee80211_tx_info_clear_status(txi);
 334
 335                 skb_pull(skb, sizeof(struct adm8211_tx_hdr));
 336                 memcpy(skb_push(skb, info->hdrlen), skb->cb, info->hdrlen);
 337                 if (!(txi->flags & IEEE80211_TX_CTL_NO_ACK) &&
 338                     !(status & TDES0_STATUS_ES))
 339                         txi->flags |= IEEE80211_TX_STAT_ACK;
 340
 341                 ieee80211_tx_status_irqsafe(dev, skb);
 342
 343                 info->skb = NULL;
 344         }
 345
 346         if (priv->cur_tx - dirty_tx < priv->tx_ring_size - 2)
 347                 ieee80211_wake_queue(dev, 0);
 348
 349         priv->dirty_tx = dirty_tx;
 350         spin_unlock(&priv->lock);
 351 }
 352
 353
 354 static void adm8211_interrupt_rci(struct ieee80211_hw *dev)
 355 {
 356         struct adm8211_priv *priv = dev->priv;
 357         unsigned int entry = priv->cur_rx % priv->rx_ring_size;
 358         u32 status;
 359         unsigned int pktlen;
 360         struct sk_buff *skb, *newskb;
 361         unsigned int limit = priv->rx_ring_size;
 362         u8 rssi, rate;
 363
 364         while (!(priv->rx_ring[entry].status & cpu_to_le32(RDES0_STATUS_OWN))) {
 365                 if (!limit--)
 366                         break;
 367
 368                 status = le32_to_cpu(priv->rx_ring[entry].status);
 369                 rate = (status & RDES0_STATUS_RXDR) >> 12;
 370                 rssi = le32_to_cpu(priv->rx_ring[entry].length) &
 371                         RDES1_STATUS_RSSI;
 372
 373                 pktlen = status & RDES0_STATUS_FL;
 374                 if (pktlen > RX_PKT_SIZE) {
 375                         if (net_ratelimit())
 376                                 printk(KERN_DEBUG "%s: frame too long (%d)\n",
 377                                        wiphy_name(dev->wiphy), pktlen);
 378                         pktlen = RX_PKT_SIZE;
 379                 }
 380
 381                 if (!priv->soft_rx_crc && status & RDES0_STATUS_ES) {
 382                         skb = NULL; /* old buffer will be reused */
 383                         /* TODO: update RX error stats */
 384                         /* TODO: check RDES0_STATUS_CRC*E */
 385                 } else if (pktlen < RX_COPY_BREAK) {
 386                         skb = dev_alloc_skb(pktlen);
 387                         if (skb) {
 388                                 pci_dma_sync_single_for_cpu(
 389                                         priv->pdev,
 390                                         priv->rx_buffers[entry].mapping,
 391                                         pktlen, PCI_DMA_FROMDEVICE);
 392                                 memcpy(skb_put(skb, pktlen),
 393                                        skb_tail_pointer(priv->rx_buffers[entry].skb),
 394                                        pktlen);
 395                                 pci_dma_sync_single_for_device(
 396                                         priv->pdev,
 397                                         priv->rx_buffers[entry].mapping,
 398                                         RX_PKT_SIZE, PCI_DMA_FROMDEVICE);
 399                         }
 400                 } else {
 401                         newskb = dev_alloc_skb(RX_PKT_SIZE);
 402                         if (newskb) {
 403                                 skb = priv->rx_buffers[entry].skb;
 404                                 skb_put(skb, pktlen);
 405                                 pci_unmap_single(
 406                                         priv->pdev,
 407                                         priv->rx_buffers[entry].mapping,
 408                                         RX_PKT_SIZE, PCI_DMA_FROMDEVICE);
 409                                 priv->rx_buffers[entry].skb = newskb;
 410                                 priv->rx_buffers[entry].mapping =
 411                                         pci_map_single(priv->pdev,
 412                                                        skb_tail_pointer(newskb),
 413                                                        RX_PKT_SIZE,
 414                                                        PCI_DMA_FROMDEVICE);
 415                         } else {
 416                                 skb = NULL;
 417                                 /* TODO: update rx dropped stats */
 418                         }
 419
 420                         priv->rx_ring[entry].buffer1 =
 421                                 cpu_to_le32(priv->rx_buffers[entry].mapping);
 422                 }
 423
 424                 priv->rx_ring[entry].status = cpu_to_le32(RDES0_STATUS_OWN |
 425                                                           RDES0_STATUS_SQL);
 426                 priv->rx_ring[entry].length =
 427                         cpu_to_le32(RX_PKT_SIZE |
 428                                     (entry == priv->rx_ring_size - 1 ?
 429                                      RDES1_CONTROL_RER : 0));
 430
 431                 if (skb) {
 432                         struct ieee80211_rx_status rx_status = {0};
 433
 434                         if (priv->pdev->revision < ADM8211_REV_CA)
 435                                 rx_status.signal = rssi;
 436                         else
 437                                 rx_status.signal = 100 - rssi;
 438
 439                         rx_status.rate_idx = rate;
 440
 441                         rx_status.freq = adm8211_channels[priv->channel - 1].center_freq;
 442                         rx_status.band = IEEE80211_BAND_2GHZ;
 443
 444                         memcpy(IEEE80211_SKB_RXCB(skb), &rx_status, sizeof(rx_status));
 445                         ieee80211_rx_irqsafe(dev, skb);
 446                 }
 447
 448                 entry = (++priv->cur_rx) % priv->rx_ring_size;
 449         }
 450
 451         /* TODO: check LPC and update stats? */
 452 }
 453
 454
 455 static irqreturn_t adm8211_interrupt(int irq, void *dev_id)
 456 {
 457 #define ADM8211_INT(x)                                                     \
 458 do {                                                                       \
 459         if (unlikely(stsr & ADM8211_STSR_ ## x))                           \
 460                 printk(KERN_DEBUG "%s: " #x "\n", wiphy_name(dev->wiphy)); \
 461 } while (0)
 462
 463         struct ieee80211_hw *dev = dev_id;
 464         struct adm8211_priv *priv = dev->priv;
 465         u32 stsr = ADM8211_CSR_READ(STSR);
 466         ADM8211_CSR_WRITE(STSR, stsr);
 467         if (stsr == 0xffffffff)
 468                 return IRQ_HANDLED;
 469
 470         if (!(stsr & (ADM8211_STSR_NISS | ADM8211_STSR_AISS)))
 471                 return IRQ_HANDLED;
 472
 473         if (stsr & ADM8211_STSR_RCI)
 474                 adm8211_interrupt_rci(dev);
 475         if (stsr & ADM8211_STSR_TCI)
 476                 adm8211_interrupt_tci(dev);
 477
 478         ADM8211_INT(PCF);
 479         ADM8211_INT(BCNTC);
 480         ADM8211_INT(GPINT);
 481         ADM8211_INT(ATIMTC);
 482         ADM8211_INT(TSFTF);
 483         ADM8211_INT(TSCZ);
 484         ADM8211_INT(SQL);
 485         ADM8211_INT(WEPTD);
 486         ADM8211_INT(ATIME);
 487         ADM8211_INT(TEIS);
 488         ADM8211_INT(FBE);
 489         ADM8211_INT(REIS);
 490         ADM8211_INT(GPTT);
 491         ADM8211_INT(RPS);
 492         ADM8211_INT(RDU);
 493         ADM8211_INT(TUF);
 494         ADM8211_INT(TPS);
 495
 496         return IRQ_HANDLED;
 497
 498 #undef ADM8211_INT
 499 }
 500
 501 #define WRITE_SYN(name,v_mask,v_shift,a_mask,a_shift,bits,prewrite,postwrite)\
 502 static void adm8211_rf_write_syn_ ## name (struct ieee80211_hw *dev,         \
 503                                            u16 addr, u32 value) {            \
 504         struct adm8211_priv *priv = dev->priv;                               \
 505         unsigned int i;                                                      \
 506         u32 reg, bitbuf;                                                     \
 507                                                                              \
 508         value &= v_mask;                                                     \
 509         addr &= a_mask;                                                      \
 510         bitbuf = (value << v_shift) | (addr << a_shift);                     \
 511                                                                              \
 512         ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_IF_SELECT_1);                 \
 513         ADM8211_CSR_READ(SYNRF);                                             \
 514         ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_IF_SELECT_0);                 \
 515         ADM8211_CSR_READ(SYNRF);                                             \
 516                                                                              \
 517         if (prewrite) {                                                      \
 518                 ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_WRITE_SYNDATA_0);     \
 519                 ADM8211_CSR_READ(SYNRF);                                     \
 520         }                                                                    \
 521                                                                              \
 522         for (i = 0; i <= bits; i++) {                                        \
 523                 if (bitbuf & (1 << (bits - i)))                              \
 524                         reg = ADM8211_SYNRF_WRITE_SYNDATA_1;                 \
 525                 else                                                         \
 526                         reg = ADM8211_SYNRF_WRITE_SYNDATA_0;                 \
 527                                                                              \
 528                 ADM8211_CSR_WRITE(SYNRF, reg);                               \
 529                 ADM8211_CSR_READ(SYNRF);                                     \
 530                                                                              \
 531                 ADM8211_CSR_WRITE(SYNRF, reg | ADM8211_SYNRF_WRITE_CLOCK_1); \
 532                 ADM8211_CSR_READ(SYNRF);                                     \
 533                 ADM8211_CSR_WRITE(SYNRF, reg | ADM8211_SYNRF_WRITE_CLOCK_0); \
 534                 ADM8211_CSR_READ(SYNRF);                                     \
 535         }                                                                    \
 536                                                                              \
 537         if (postwrite == 1) {                                                \
 538                 ADM8211_CSR_WRITE(SYNRF, reg | ADM8211_SYNRF_IF_SELECT_0);   \
 539                 ADM8211_CSR_READ(SYNRF);                                     \
 540         }                                                                    \
 541         if (postwrite == 2) {                                                \
 542                 ADM8211_CSR_WRITE(SYNRF, reg | ADM8211_SYNRF_IF_SELECT_1);   \
 543                 ADM8211_CSR_READ(SYNRF);                                     \
 544         }                                                                    \
 545                                                                              \
 546         ADM8211_CSR_WRITE(SYNRF, 0);                                         \
 547         ADM8211_CSR_READ(SYNRF);                                             \
 548 }
 549
 550 WRITE_SYN(max2820,  0x00FFF, 0, 0x0F, 12, 15, 1, 1)
 551 WRITE_SYN(al2210l,  0xFFFFF, 4, 0x0F,  0, 23, 1, 1)
 552 WRITE_SYN(rfmd2958, 0x3FFFF, 0, 0x1F, 18, 23, 0, 1)
 553 WRITE_SYN(rfmd2948, 0x0FFFF, 4, 0x0F,  0, 21, 0, 2)
 554
 555 #undef WRITE_SYN
 556
 557 static int adm8211_write_bbp(struct ieee80211_hw *dev, u8 addr, u8 data)
 558 {
 559         struct adm8211_priv *priv = dev->priv;
 560         unsigned int timeout;
 561         u32 reg;
 562
 563         timeout = 10;
 564         while (timeout > 0) {
 565                 reg = ADM8211_CSR_READ(BBPCTL);
 566                 if (!(reg & (ADM8211_BBPCTL_WR | ADM8211_BBPCTL_RD)))
 567                         break;
 568                 timeout--;
 569                 msleep(2);
 570         }
 571
 572         if (timeout == 0) {
 573                 printk(KERN_DEBUG "%s: adm8211_write_bbp(%d,%d) failed"
 574                        " prewrite (reg=0x%08x)\n",
 575                        wiphy_name(dev->wiphy), addr, data, reg);
 576                 return -ETIMEDOUT;
 577         }
 578
 579         switch (priv->bbp_type) {
 580         case ADM8211_TYPE_INTERSIL:
 581                 reg = ADM8211_BBPCTL_MMISEL;    /* three wire interface */
 582                 break;
 583         case ADM8211_TYPE_RFMD:
 584                 reg = (0x20 << 24) | ADM8211_BBPCTL_TXCE | ADM8211_BBPCTL_CCAP |
 585                       (0x01 << 18);
 586                 break;
 587         case ADM8211_TYPE_ADMTEK:
 588                 reg = (0x20 << 24) | ADM8211_BBPCTL_TXCE | ADM8211_BBPCTL_CCAP |
 589                       (0x05 << 18);
 590                 break;
 591         }
 592         reg |= ADM8211_BBPCTL_WR | (addr << 8) | data;
 593
 594         ADM8211_CSR_WRITE(BBPCTL, reg);
 595
 596         timeout = 10;
 597         while (timeout > 0) {
 598                 reg = ADM8211_CSR_READ(BBPCTL);
 599                 if (!(reg & ADM8211_BBPCTL_WR))
 600                         break;
 601                 timeout--;
 602                 msleep(2);
 603         }
 604
 605         if (timeout == 0) {
 606                 ADM8211_CSR_WRITE(BBPCTL, ADM8211_CSR_READ(BBPCTL) &
 607                                   ~ADM8211_BBPCTL_WR);
 608                 printk(KERN_DEBUG "%s: adm8211_write_bbp(%d,%d) failed"
 609                        " postwrite (reg=0x%08x)\n",
 610                        wiphy_name(dev->wiphy), addr, data, reg);
 611                 return -ETIMEDOUT;
 612         }
 613
 614         return 0;
 615 }
 616
 617 static int adm8211_rf_set_channel(struct ieee80211_hw *dev, unsigned int chan)
 618 {
 619         static const u32 adm8211_rfmd2958_reg5[] =
 620                 {0x22BD, 0x22D2, 0x22E8, 0x22FE, 0x2314, 0x232A, 0x2340,
 621                  0x2355, 0x236B, 0x2381, 0x2397, 0x23AD, 0x23C2, 0x23F7};
 622         static const u32 adm8211_rfmd2958_reg6[] =
 623                 {0x05D17, 0x3A2E8, 0x2E8BA, 0x22E8B, 0x1745D, 0x0BA2E, 0x00000,
 624                  0x345D1, 0x28BA2, 0x1D174, 0x11745, 0x05D17, 0x3A2E8, 0x11745};
 625
 626         struct adm8211_priv *priv = dev->priv;
 627         u8 ant_power = priv->ant_power > 0x3F ?
 628                 priv->eeprom->antenna_power[chan - 1] : priv->ant_power;
 629         u8 tx_power = priv->tx_power > 0x3F ?
 630                 priv->eeprom->tx_power[chan - 1] : priv->tx_power;
 631         u8 lpf_cutoff = priv->lpf_cutoff == 0xFF ?
 632                 priv->eeprom->lpf_cutoff[chan - 1] : priv->lpf_cutoff;
 633         u8 lnags_thresh = priv->lnags_threshold == 0xFF ?
 634                 priv->eeprom->lnags_threshold[chan - 1] : priv->lnags_threshold;
 635         u32 reg;
 636
 637         ADM8211_IDLE();
 638
 639         /* Program synthesizer to new channel */
 640         switch (priv->transceiver_type) {
 641         case ADM8211_RFMD2958:
 642         case ADM8211_RFMD2958_RF3000_CONTROL_POWER:
 643                 adm8211_rf_write_syn_rfmd2958(dev, 0x00, 0x04007);
 644                 adm8211_rf_write_syn_rfmd2958(dev, 0x02, 0x00033);
 645
 646                 adm8211_rf_write_syn_rfmd2958(dev, 0x05,
 647                         adm8211_rfmd2958_reg5[chan - 1]);
 648                 adm8211_rf_write_syn_rfmd2958(dev, 0x06,
 649                         adm8211_rfmd2958_reg6[chan - 1]);
 650                 break;
 651
 652         case ADM8211_RFMD2948:
 653                 adm8211_rf_write_syn_rfmd2948(dev, SI4126_MAIN_CONF,
 654                                               SI4126_MAIN_XINDIV2);
 655                 adm8211_rf_write_syn_rfmd2948(dev, SI4126_POWERDOWN,
 656                                               SI4126_POWERDOWN_PDIB |
 657                                               SI4126_POWERDOWN_PDRB);
 658                 adm8211_rf_write_syn_rfmd2948(dev, SI4126_PHASE_DET_GAIN, 0);
 659                 adm8211_rf_write_syn_rfmd2948(dev, SI4126_RF2_N_DIV,
 660                                               (chan == 14 ?
 661                                                2110 : (2033 + (chan * 5))));
 662                 adm8211_rf_write_syn_rfmd2948(dev, SI4126_IF_N_DIV, 1496);
 663                 adm8211_rf_write_syn_rfmd2948(dev, SI4126_RF2_R_DIV, 44);
 664                 adm8211_rf_write_syn_rfmd2948(dev, SI4126_IF_R_DIV, 44);
 665                 break;
 666
 667         case ADM8211_MAX2820:
 668                 adm8211_rf_write_syn_max2820(dev, 0x3,
 669                         (chan == 14 ? 0x054 : (0x7 + (chan * 5))));
 670                 break;
 671
 672         case ADM8211_AL2210L:
 673                 adm8211_rf_write_syn_al2210l(dev, 0x0,
 674                         (chan == 14 ? 0x229B4 : (0x22967 + (chan * 5))));
 675                 break;
 676
 677         default:
 678                 printk(KERN_DEBUG "%s: unsupported transceiver type %d\n",
 679                        wiphy_name(dev->wiphy), priv->transceiver_type);
 680                 break;
 681         }
 682
 683         /* write BBP regs */
 684         if (priv->bbp_type == ADM8211_TYPE_RFMD) {
 685
 686         /* SMC 2635W specific? adm8211b doesn't use the 2948 though.. */
 687         /* TODO: remove if SMC 2635W doesn't need this */
 688         if (priv->transceiver_type == ADM8211_RFMD2948) {
 689                 reg = ADM8211_CSR_READ(GPIO);
 690                 reg &= 0xfffc0000;
 691                 reg |= ADM8211_CSR_GPIO_EN0;
 692                 if (chan != 14)
 693                         reg |= ADM8211_CSR_GPIO_O0;
 694                 ADM8211_CSR_WRITE(GPIO, reg);
 695         }
 696
 697         if (priv->transceiver_type == ADM8211_RFMD2958) {
 698                 /* set PCNT2 */
 699                 adm8211_rf_write_syn_rfmd2958(dev, 0x0B, 0x07100);
 700                 /* set PCNT1 P_DESIRED/MID_BIAS */
 701                 reg = le16_to_cpu(priv->eeprom->cr49);
 702                 reg >>= 13;
 703                 reg <<= 15;
 704                 reg |= ant_power << 9;
 705                 adm8211_rf_write_syn_rfmd2958(dev, 0x0A, reg);
 706                 /* set TXRX TX_GAIN */
 707                 adm8211_rf_write_syn_rfmd2958(dev, 0x09, 0x00050 |
 708                         (priv->pdev->revision < ADM8211_REV_CA ? tx_power : 0));
 709         } else {
 710                 reg = ADM8211_CSR_READ(PLCPHD);
 711                 reg &= 0xff00ffff;
 712                 reg |= tx_power << 18;
 713                 ADM8211_CSR_WRITE(PLCPHD, reg);
 714         }
 715
 716         ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_SELRF |
 717                           ADM8211_SYNRF_PE1 | ADM8211_SYNRF_PHYRST);
 718         ADM8211_CSR_READ(SYNRF);
 719         msleep(30);
 720
 721         /* RF3000 BBP */
 722         if (priv->transceiver_type != ADM8211_RFMD2958)
 723                 adm8211_write_bbp(dev, RF3000_TX_VAR_GAIN__TX_LEN_EXT,
 724                                   tx_power<<2);
 725         adm8211_write_bbp(dev, RF3000_LOW_GAIN_CALIB, lpf_cutoff);
 726         adm8211_write_bbp(dev, RF3000_HIGH_GAIN_CALIB, lnags_thresh);
 727         adm8211_write_bbp(dev, 0x1c, priv->pdev->revision == ADM8211_REV_BA ?
 728                                      priv->eeprom->cr28 : 0);
 729         adm8211_write_bbp(dev, 0x1d, priv->eeprom->cr29);
 730
 731         ADM8211_CSR_WRITE(SYNRF, 0);
 732
 733         /* Nothing to do for ADMtek BBP */
 734         } else if (priv->bbp_type != ADM8211_TYPE_ADMTEK)
 735                 printk(KERN_DEBUG "%s: unsupported BBP type %d\n",
 736                        wiphy_name(dev->wiphy), priv->bbp_type);
 737
 738         ADM8211_RESTORE();
 739
 740         /* update current channel for adhoc (and maybe AP mode) */
 741         reg = ADM8211_CSR_READ(CAP0);
 742         reg &= ~0xF;
 743         reg |= chan;
 744         ADM8211_CSR_WRITE(CAP0, reg);
 745
 746         return 0;
 747 }
 748
 749 static void adm8211_update_mode(struct ieee80211_hw *dev)
 750 {
 751         struct adm8211_priv *priv = dev->priv;
 752
 753         ADM8211_IDLE();
 754
 755         priv->soft_rx_crc = 0;
 756         switch (priv->mode) {
 757         case NL80211_IFTYPE_STATION:
 758                 priv->nar &= ~(ADM8211_NAR_PR | ADM8211_NAR_EA);
 759                 priv->nar |= ADM8211_NAR_ST | ADM8211_NAR_SR;
 760                 break;
 761         case NL80211_IFTYPE_ADHOC:
 762                 priv->nar &= ~ADM8211_NAR_PR;
 763                 priv->nar |= ADM8211_NAR_EA | ADM8211_NAR_ST | ADM8211_NAR_SR;
 764
 765                 /* don't trust the error bits on rev 0x20 and up in adhoc */
 766                 if (priv->pdev->revision >= ADM8211_REV_BA)
 767                         priv->soft_rx_crc = 1;
 768                 break;
 769         case NL80211_IFTYPE_MONITOR:
 770                 priv->nar &= ~(ADM8211_NAR_EA | ADM8211_NAR_ST);
 771                 priv->nar |= ADM8211_NAR_PR | ADM8211_NAR_SR;
 772                 break;
 773         }
 774
 775         ADM8211_RESTORE();
 776 }
 777
 778 static void adm8211_hw_init_syn(struct ieee80211_hw *dev)
 779 {
 780         struct adm8211_priv *priv = dev->priv;
 781
 782         switch (priv->transceiver_type) {
 783         case ADM8211_RFMD2958:
 784         case ADM8211_RFMD2958_RF3000_CONTROL_POWER:
 785                 /* comments taken from ADMtek vendor driver */
 786
 787                 /* Reset RF2958 after power on */
 788                 adm8211_rf_write_syn_rfmd2958(dev, 0x1F, 0x00000);
 789                 /* Initialize RF VCO Core Bias to maximum */
 790                 adm8211_rf_write_syn_rfmd2958(dev, 0x0C, 0x3001F);
 791                 /* Initialize IF PLL */
 792                 adm8211_rf_write_syn_rfmd2958(dev, 0x01, 0x29C03);
 793                 /* Initialize IF PLL Coarse Tuning */
 794                 adm8211_rf_write_syn_rfmd2958(dev, 0x03, 0x1FF6F);
 795                 /* Initialize RF PLL */
 796                 adm8211_rf_write_syn_rfmd2958(dev, 0x04, 0x29403);
 797                 /* Initialize RF PLL Coarse Tuning */
 798                 adm8211_rf_write_syn_rfmd2958(dev, 0x07, 0x1456F);
 799                 /* Initialize TX gain and filter BW (R9) */
 800                 adm8211_rf_write_syn_rfmd2958(dev, 0x09,
 801                         (priv->transceiver_type == ADM8211_RFMD2958 ?
 802                          0x10050 : 0x00050));
 803                 /* Initialize CAL register */
 804                 adm8211_rf_write_syn_rfmd2958(dev, 0x08, 0x3FFF8);
 805                 break;
 806
 807         case ADM8211_MAX2820:
 808                 adm8211_rf_write_syn_max2820(dev, 0x1, 0x01E);
 809                 adm8211_rf_write_syn_max2820(dev, 0x2, 0x001);
 810                 adm8211_rf_write_syn_max2820(dev, 0x3, 0x054);
 811                 adm8211_rf_write_syn_max2820(dev, 0x4, 0x310);
 812                 adm8211_rf_write_syn_max2820(dev, 0x5, 0x000);
 813                 break;
 814
 815         case ADM8211_AL2210L:
 816                 adm8211_rf_write_syn_al2210l(dev, 0x0, 0x0196C);
 817                 adm8211_rf_write_syn_al2210l(dev, 0x1, 0x007CB);
 818                 adm8211_rf_write_syn_al2210l(dev, 0x2, 0x3582F);
 819                 adm8211_rf_write_syn_al2210l(dev, 0x3, 0x010A9);
 820                 adm8211_rf_write_syn_al2210l(dev, 0x4, 0x77280);
 821                 adm8211_rf_write_syn_al2210l(dev, 0x5, 0x45641);
 822                 adm8211_rf_write_syn_al2210l(dev, 0x6, 0xEA130);
 823                 adm8211_rf_write_syn_al2210l(dev, 0x7, 0x80000);
 824                 adm8211_rf_write_syn_al2210l(dev, 0x8, 0x7850F);
 825                 adm8211_rf_write_syn_al2210l(dev, 0x9, 0xF900C);
 826                 adm8211_rf_write_syn_al2210l(dev, 0xA, 0x00000);
 827                 adm8211_rf_write_syn_al2210l(dev, 0xB, 0x00000);
 828                 break;
 829
 830         case ADM8211_RFMD2948:
 831         default:
 832                 break;
 833         }
 834 }
 835
 836 static int adm8211_hw_init_bbp(struct ieee80211_hw *dev)
 837 {
 838         struct adm8211_priv *priv = dev->priv;
 839         u32 reg;
 840
 841         /* write addresses */
 842         if (priv->bbp_type == ADM8211_TYPE_INTERSIL) {
 843                 ADM8211_CSR_WRITE(MMIWA,  0x100E0C0A);
 844                 ADM8211_CSR_WRITE(MMIRD0, 0x00007C7E);
 845                 ADM8211_CSR_WRITE(MMIRD1, 0x00100000);
 846         } else if (priv->bbp_type == ADM8211_TYPE_RFMD ||
 847                    priv->bbp_type == ADM8211_TYPE_ADMTEK) {
 848                 /* check specific BBP type */
 849                 switch (priv->specific_bbptype) {
 850                 case ADM8211_BBP_RFMD3000:
 851                 case ADM8211_BBP_RFMD3002:
 852                         ADM8211_CSR_WRITE(MMIWA,  0x00009101);
 853                         ADM8211_CSR_WRITE(MMIRD0, 0x00000301);
 854                         break;
 855
 856                 case ADM8211_BBP_ADM8011:
 857                         ADM8211_CSR_WRITE(MMIWA,  0x00008903);
 858                         ADM8211_CSR_WRITE(MMIRD0, 0x00001716);
 859
 860                         reg = ADM8211_CSR_READ(BBPCTL);
 861                         reg &= ~ADM8211_BBPCTL_TYPE;
 862                         reg |= 0x5 << 18;
 863                         ADM8211_CSR_WRITE(BBPCTL, reg);
 864                         break;
 865                 }
 866
 867                 switch (priv->pdev->revision) {
 868                 case ADM8211_REV_CA:
 869                         if (priv->transceiver_type == ADM8211_RFMD2958 ||
 870                             priv->transceiver_type == ADM8211_RFMD2958_RF3000_CONTROL_POWER ||
 871                             priv->transceiver_type == ADM8211_RFMD2948)
 872                                 ADM8211_CSR_WRITE(SYNCTL, 0x1 << 22);
 873                         else if (priv->transceiver_type == ADM8211_MAX2820 ||
 874                                  priv->transceiver_type == ADM8211_AL2210L)
 875                                 ADM8211_CSR_WRITE(SYNCTL, 0x3 << 22);
 876                         break;
 877
 878                 case ADM8211_REV_BA:
 879                         reg  = ADM8211_CSR_READ(MMIRD1);
 880                         reg &= 0x0000FFFF;
 881                         reg |= 0x7e100000;
 882                         ADM8211_CSR_WRITE(MMIRD1, reg);
 883                         break;
 884
 885                 case ADM8211_REV_AB:
 886                 case ADM8211_REV_AF:
 887                 default:
 888                         ADM8211_CSR_WRITE(MMIRD1, 0x7e100000);
 889                         break;
 890                 }
 891
 892                 /* For RFMD */
 893                 ADM8211_CSR_WRITE(MACTEST, 0x800);
 894         }
 895
 896         adm8211_hw_init_syn(dev);
 897
 898         /* Set RF Power control IF pin to PE1+PHYRST# */
 899         ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_SELRF |
 900                           ADM8211_SYNRF_PE1 | ADM8211_SYNRF_PHYRST);
 901         ADM8211_CSR_READ(SYNRF);
 902         msleep(20);
 903
 904         /* write BBP regs */
 905         if (priv->bbp_type == ADM8211_TYPE_RFMD) {
 906                 /* RF3000 BBP */
 907                 /* another set:
 908                  * 11: c8
 909                  * 14: 14
 910                  * 15: 50 (chan 1..13; chan 14: d0)
 911                  * 1c: 00
 912                  * 1d: 84
 913                  */
 914                 adm8211_write_bbp(dev, RF3000_CCA_CTRL, 0x80);
 915                 /* antenna selection: diversity */
 916                 adm8211_write_bbp(dev, RF3000_DIVERSITY__RSSI, 0x80);
 917                 adm8211_write_bbp(dev, RF3000_TX_VAR_GAIN__TX_LEN_EXT, 0x74);
 918                 adm8211_write_bbp(dev, RF3000_LOW_GAIN_CALIB, 0x38);
 919                 adm8211_write_bbp(dev, RF3000_HIGH_GAIN_CALIB, 0x40);
 920
 921                 if (priv->eeprom->major_version < 2) {
 922                         adm8211_write_bbp(dev, 0x1c, 0x00);
 923                         adm8211_write_bbp(dev, 0x1d, 0x80);
 924                 } else {
 925                         if (priv->pdev->revision == ADM8211_REV_BA)
 926                                 adm8211_write_bbp(dev, 0x1c, priv->eeprom->cr28);
 927                         else
 928                                 adm8211_write_bbp(dev, 0x1c, 0x00);
 929
 930                         adm8211_write_bbp(dev, 0x1d, priv->eeprom->cr29);
 931                 }
 932         } else if (priv->bbp_type == ADM8211_TYPE_ADMTEK) {
 933                 /* reset baseband */
 934                 adm8211_write_bbp(dev, 0x00, 0xFF);
 935                 /* antenna selection: diversity */
 936                 adm8211_write_bbp(dev, 0x07, 0x0A);
 937
 938                 /* TODO: find documentation for this */
 939                 switch (priv->transceiver_type) {
 940                 case ADM8211_RFMD2958:
 941                 case ADM8211_RFMD2958_RF3000_CONTROL_POWER:
 942                         adm8211_write_bbp(dev, 0x00, 0x00);
 943                         adm8211_write_bbp(dev, 0x01, 0x00);
 944                         adm8211_write_bbp(dev, 0x02, 0x00);
 945                         adm8211_write_bbp(dev, 0x03, 0x00);
 946                         adm8211_write_bbp(dev, 0x06, 0x0f);
 947                         adm8211_write_bbp(dev, 0x09, 0x00);
 948                         adm8211_write_bbp(dev, 0x0a, 0x00);
 949                         adm8211_write_bbp(dev, 0x0b, 0x00);
 950                         adm8211_write_bbp(dev, 0x0c, 0x00);
 951                         adm8211_write_bbp(dev, 0x0f, 0xAA);
 952                         adm8211_write_bbp(dev, 0x10, 0x8c);
 953                         adm8211_write_bbp(dev, 0x11, 0x43);
 954                         adm8211_write_bbp(dev, 0x18, 0x40);
 955                         adm8211_write_bbp(dev, 0x20, 0x23);
 956                         adm8211_write_bbp(dev, 0x21, 0x02);
 957                         adm8211_write_bbp(dev, 0x22, 0x28);
 958                         adm8211_write_bbp(dev, 0x23, 0x30);
 959                         adm8211_write_bbp(dev, 0x24, 0x2d);
 960                         adm8211_write_bbp(dev, 0x28, 0x35);
 961                         adm8211_write_bbp(dev, 0x2a, 0x8c);
 962                         adm8211_write_bbp(dev, 0x2b, 0x81);
 963                         adm8211_write_bbp(dev, 0x2c, 0x44);
 964                         adm8211_write_bbp(dev, 0x2d, 0x0A);
 965                         adm8211_write_bbp(dev, 0x29, 0x40);
 966                         adm8211_write_bbp(dev, 0x60, 0x08);
 967                         adm8211_write_bbp(dev, 0x64, 0x01);
 968                         break;
 969
 970                 case ADM8211_MAX2820:
 971                         adm8211_write_bbp(dev, 0x00, 0x00);
 972                         adm8211_write_bbp(dev, 0x01, 0x00);
 973                         adm8211_write_bbp(dev, 0x02, 0x00);
 974                         adm8211_write_bbp(dev, 0x03, 0x00);
 975                         adm8211_write_bbp(dev, 0x06, 0x0f);
 976                         adm8211_write_bbp(dev, 0x09, 0x05);
 977                         adm8211_write_bbp(dev, 0x0a, 0x02);
 978                         adm8211_write_bbp(dev, 0x0b, 0x00);
 979                         adm8211_write_bbp(dev, 0x0c, 0x0f);
 980                         adm8211_write_bbp(dev, 0x0f, 0x55);
 981                         adm8211_write_bbp(dev, 0x10, 0x8d);
 982                         adm8211_write_bbp(dev, 0x11, 0x43);
 983                         adm8211_write_bbp(dev, 0x18, 0x4a);
 984                         adm8211_write_bbp(dev, 0x20, 0x20);
 985                         adm8211_write_bbp(dev, 0x21, 0x02);
 986                         adm8211_write_bbp(dev, 0x22, 0x23);
 987                         adm8211_write_bbp(dev, 0x23, 0x30);
 988                         adm8211_write_bbp(dev, 0x24, 0x2d);
 989                         adm8211_write_bbp(dev, 0x2a, 0x8c);
 990                         adm8211_write_bbp(dev, 0x2b, 0x81);
 991                         adm8211_write_bbp(dev, 0x2c, 0x44);
 992                         adm8211_write_bbp(dev, 0x29, 0x4a);
 993                         adm8211_write_bbp(dev, 0x60, 0x2b);
 994                         adm8211_write_bbp(dev, 0x64, 0x01);
 995                         break;
 996
 997                 case ADM8211_AL2210L:
 998                         adm8211_write_bbp(dev, 0x00, 0x00);
 999                         adm8211_write_bbp(dev, 0x01, 0x00);
1000                         adm8211_write_bbp(dev, 0x02, 0x00);
1001                         adm8211_write_bbp(dev, 0x03, 0x00);
1002                         adm8211_write_bbp(dev, 0x06, 0x0f);
1003                         adm8211_write_bbp(dev, 0x07, 0x05);
1004                         adm8211_write_bbp(dev, 0x08, 0x03);
1005                         adm8211_write_bbp(dev, 0x09, 0x00);
1006                         adm8211_write_bbp(dev, 0x0a, 0x00);
1007                         adm8211_write_bbp(dev, 0x0b, 0x00);
1008                         adm8211_write_bbp(dev, 0x0c, 0x10);
1009                         adm8211_write_bbp(dev, 0x0f, 0x55);
1010                         adm8211_write_bbp(dev, 0x10, 0x8d);
1011                         adm8211_write_bbp(dev, 0x11, 0x43);
1012                         adm8211_write_bbp(dev, 0x18, 0x4a);
1013                         adm8211_write_bbp(dev, 0x20, 0x20);
1014                         adm8211_write_bbp(dev, 0x21, 0x02);
1015                         adm8211_write_bbp(dev, 0x22, 0x23);
1016                         adm8211_write_bbp(dev, 0x23, 0x30);
1017                         adm8211_write_bbp(dev, 0x24, 0x2d);
1018                         adm8211_write_bbp(dev, 0x2a, 0xaa);
1019                         adm8211_write_bbp(dev, 0x2b, 0x81);
1020                         adm8211_write_bbp(dev, 0x2c, 0x44);
1021                         adm8211_write_bbp(dev, 0x29, 0xfa);
1022                         adm8211_write_bbp(dev, 0x60, 0x2d);
1023                         adm8211_write_bbp(dev, 0x64, 0x01);
1024                         break;
1025
1026                 case ADM8211_RFMD2948:
1027                         break;
1028
1029                 default:
1030                         printk(KERN_DEBUG "%s: unsupported transceiver %d\n",
1031                                wiphy_name(dev->wiphy), priv->transceiver_type);
1032                         break;
1033                 }
1034         } else
1035                 printk(KERN_DEBUG "%s: unsupported BBP %d\n",
1036                        wiphy_name(dev->wiphy), priv->bbp_type);
1037
1038         ADM8211_CSR_WRITE(SYNRF, 0);
1039
1040         /* Set RF CAL control source to MAC control */
1041         reg = ADM8211_CSR_READ(SYNCTL);
1042         reg |= ADM8211_SYNCTL_SELCAL;
1043         ADM8211_CSR_WRITE(SYNCTL, reg);
1044
1045         return 0;
1046 }
1047
1048 /* configures hw beacons/probe responses */
1049 static int adm8211_set_rate(struct ieee80211_hw *dev)
1050 {
1051         struct adm8211_priv *priv = dev->priv;
1052         u32 reg;
1053         int i = 0;
1054         u8 rate_buf[12] = {0};
1055
1056         /* write supported rates */
1057         if (priv->pdev->revision != ADM8211_REV_BA) {
1058                 rate_buf[0] = ARRAY_SIZE(adm8211_rates);
1059                 for (i = 0; i < ARRAY_SIZE(adm8211_rates); i++)
1060                         rate_buf[i + 1] = (adm8211_rates[i].bitrate / 5) | 0x80;
1061         } else {
1062                 /* workaround for rev BA specific bug */
1063                 rate_buf[0] = 0x04;
1064                 rate_buf[1] = 0x82;
1065                 rate_buf[2] = 0x04;
1066                 rate_buf[3] = 0x0b;
1067                 rate_buf[4] = 0x16;
1068         }
1069
1070         adm8211_write_sram_bytes(dev, ADM8211_SRAM_SUPP_RATE, rate_buf,
1071                                  ARRAY_SIZE(adm8211_rates) + 1);
1072
1073         reg = ADM8211_CSR_READ(PLCPHD) & 0x00FFFFFF; /* keep bits 0-23 */
1074         reg |= 1 << 15; /* short preamble */
1075         reg |= 110 << 24;
1076         ADM8211_CSR_WRITE(PLCPHD, reg);
1077
1078         /* MTMLT   = 512 TU (max TX MSDU lifetime)
1079          * BCNTSIG = plcp_signal (beacon, probe resp, and atim TX rate)
1080          * SRTYLIM = 224 (short retry limit, TX header value is default) */
1081         ADM8211_CSR_WRITE(TXLMT, (512 << 16) | (110 << 8) | (224 << 0));
1082
1083         return 0;
1084 }
1085
1086 static void adm8211_hw_init(struct ieee80211_hw *dev)
1087 {
1088         struct adm8211_priv *priv = dev->priv;
1089         u32 reg;
1090         u8 cline;
1091
1092         reg = ADM8211_CSR_READ(PAR);
1093         reg |= ADM8211_PAR_MRLE | ADM8211_PAR_MRME;
1094         reg &= ~(ADM8211_PAR_BAR | ADM8211_PAR_CAL);
1095
1096         if (!pci_set_mwi(priv->pdev)) {
1097                 reg |= 0x1 << 24;
1098                 pci_read_config_byte(priv->pdev, PCI_CACHE_LINE_SIZE, &cline);
1099
1100                 switch (cline) {
1101                 case  0x8: reg |= (0x1 << 14);
1102                            break;
1103                 case 0x16: reg |= (0x2 << 14);
1104                            break;
1105                 case 0x32: reg |= (0x3 << 14);
1106                            break;
1107                   default: reg |= (0x0 << 14);
1108                            break;
1109                 }
1110         }
1111
1112         ADM8211_CSR_WRITE(PAR, reg);
1113
1114         reg = ADM8211_CSR_READ(CSR_TEST1);
1115         reg &= ~(0xF << 28);
1116         reg |= (1 << 28) | (1 << 31);
1117         ADM8211_CSR_WRITE(CSR_TEST1, reg);
1118
1119         /* lose link after 4 lost beacons */
1120         reg = (0x04 << 21) | ADM8211_WCSR_TSFTWE | ADM8211_WCSR_LSOE;
1121         ADM8211_CSR_WRITE(WCSR, reg);
1122
1123         /* Disable APM, enable receive FIFO threshold, and set drain receive
1124          * threshold to store-and-forward */
1125         reg = ADM8211_CSR_READ(CMDR);
1126         reg &= ~(ADM8211_CMDR_APM | ADM8211_CMDR_DRT);
1127         reg |= ADM8211_CMDR_RTE | ADM8211_CMDR_DRT_SF;
1128         ADM8211_CSR_WRITE(CMDR, reg);
1129
1130         adm8211_set_rate(dev);
1131
1132         /* 4-bit values:
1133          * PWR1UP   = 8 * 2 ms
1134          * PWR0PAPE = 8 us or 5 us
1135          * PWR1PAPE = 1 us or 3 us
1136          * PWR0TRSW = 5 us
1137          * PWR1TRSW = 12 us
1138          * PWR0PE2  = 13 us
1139          * PWR1PE2  = 1 us
1140          * PWR0TXPE = 8 or 6 */
1141         if (priv->pdev->revision < ADM8211_REV_CA)
1142                 ADM8211_CSR_WRITE(TOFS2, 0x8815cd18);
1143         else
1144                 ADM8211_CSR_WRITE(TOFS2, 0x8535cd16);
1145
1146         /* Enable store and forward for transmit */
1147         priv->nar = ADM8211_NAR_SF | ADM8211_NAR_PB;
1148         ADM8211_CSR_WRITE(NAR, priv->nar);
1149
1150         /* Reset RF */
1151         ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_RADIO);
1152         ADM8211_CSR_READ(SYNRF);
1153         msleep(10);
1154         ADM8211_CSR_WRITE(SYNRF, 0);
1155         ADM8211_CSR_READ(SYNRF);
1156         msleep(5);
1157
1158         /* Set CFP Max Duration to 0x10 TU */
1159         reg = ADM8211_CSR_READ(CFPP);
1160         reg &= ~(0xffff << 8);
1161         reg |= 0x0010 << 8;
1162         ADM8211_CSR_WRITE(CFPP, reg);
1163
1164         /* USCNT = 0x16 (number of system clocks, 22 MHz, in 1us
1165          * TUCNT = 0x3ff - Tu counter 1024 us  */
1166         ADM8211_CSR_WRITE(TOFS0, (0x16 << 24) | 0x3ff);
1167
1168         /* SLOT=20 us, SIFS=110 cycles of 22 MHz (5 us),
1169          * DIFS=50 us, EIFS=100 us */
1170         if (priv->pdev->revision < ADM8211_REV_CA)
1171                 ADM8211_CSR_WRITE(IFST, (20 << 23) | (110 << 15) |
1172                                         (50 << 9)  | 100);
1173         else
1174                 ADM8211_CSR_WRITE(IFST, (20 << 23) | (24 << 15) |
1175                                         (50 << 9)  | 100);
1176
1177         /* PCNT = 1 (MAC idle time awake/sleep, unit S)
1178          * RMRD = 2346 * 8 + 1 us (max RX duration)  */
1179         ADM8211_CSR_WRITE(RMD, (1 << 16) | 18769);
1180
1181         /* MART=65535 us, MIRT=256 us, TSFTOFST=0 us */
1182         ADM8211_CSR_WRITE(RSPT, 0xffffff00);
1183
1184         /* Initialize BBP (and SYN) */
1185         adm8211_hw_init_bbp(dev);
1186
1187         /* make sure interrupts are off */
1188         ADM8211_CSR_WRITE(IER, 0);
1189
1190         /* ACK interrupts */
1191         ADM8211_CSR_WRITE(STSR, ADM8211_CSR_READ(STSR));
1192
1193         /* Setup WEP (turns it off for now) */
1194         reg = ADM8211_CSR_READ(MACTEST);
1195         reg &= ~(7 << 20);
1196         ADM8211_CSR_WRITE(MACTEST, reg);
1197
1198         reg = ADM8211_CSR_READ(WEPCTL);
1199         reg &= ~ADM8211_WEPCTL_WEPENABLE;
1200         reg |= ADM8211_WEPCTL_WEPRXBYP;
1201         ADM8211_CSR_WRITE(WEPCTL, reg);
1202
1203         /* Clear the missed-packet counter. */
1204         ADM8211_CSR_READ(LPC);
1205 }
1206
1207 static int adm8211_hw_reset(struct ieee80211_hw *dev)
1208 {
1209         struct adm8211_priv *priv = dev->priv;
1210         u32 reg, tmp;
1211         int timeout = 100;
1212
1213         /* Power-on issue */
1214         /* TODO: check if this is necessary */
1215         ADM8211_CSR_WRITE(FRCTL, 0);
1216
1217         /* Reset the chip */
1218         tmp = ADM8211_CSR_READ(PAR);
1219         ADM8211_CSR_WRITE(PAR, ADM8211_PAR_SWR);
1220
1221         while ((ADM8211_CSR_READ(PAR) & ADM8211_PAR_SWR) && timeout--)
1222                 msleep(50);
1223
1224         if (timeout <= 0)
1225                 return -ETIMEDOUT;
1226
1227         ADM8211_CSR_WRITE(PAR, tmp);
1228
1229         if (priv->pdev->revision == ADM8211_REV_BA &&
1230             (priv->transceiver_type == ADM8211_RFMD2958_RF3000_CONTROL_POWER ||
1231              priv->transceiver_type == ADM8211_RFMD2958)) {
1232                 reg = ADM8211_CSR_READ(CSR_TEST1);
1233                 reg |= (1 << 4) | (1 << 5);
1234                 ADM8211_CSR_WRITE(CSR_TEST1, reg);
1235         } else if (priv->pdev->revision == ADM8211_REV_CA) {
1236                 reg = ADM8211_CSR_READ(CSR_TEST1);
1237                 reg &= ~((1 << 4) | (1 << 5));
1238                 ADM8211_CSR_WRITE(CSR_TEST1, reg);
1239         }
1240
1241         ADM8211_CSR_WRITE(FRCTL, 0);
1242
1243         reg = ADM8211_CSR_READ(CSR_TEST0);
1244         reg |= ADM8211_CSR_TEST0_EPRLD; /* EEPROM Recall */
1245         ADM8211_CSR_WRITE(CSR_TEST0, reg);
1246
1247         adm8211_clear_sram(dev);
1248
1249         return 0;
1250 }
1251
1252 static u64 adm8211_get_tsft(struct ieee80211_hw *dev)
1253 {
1254         struct adm8211_priv *priv = dev->priv;
1255         u32 tsftl;
1256         u64 tsft;
1257
1258         tsftl = ADM8211_CSR_READ(TSFTL);
1259         tsft = ADM8211_CSR_READ(TSFTH);
1260         tsft <<= 32;
1261         tsft |= tsftl;
1262
1263         return tsft;
1264 }
1265
1266 static void adm8211_set_interval(struct ieee80211_hw *dev,
1267                                  unsigned short bi, unsigned short li)
1268 {
1269         struct adm8211_priv *priv = dev->priv;
1270         u32 reg;
1271
1272         /* BP (beacon interval) = data->beacon_interval
1273          * LI (listen interval) = data->listen_interval (in beacon intervals) */
1274         reg = (bi << 16) | li;
1275         ADM8211_CSR_WRITE(BPLI, reg);
1276 }
1277
1278 static void adm8211_set_bssid(struct ieee80211_hw *dev, const u8 *bssid)
1279 {
1280         struct adm8211_priv *priv = dev->priv;
1281         u32 reg;
1282
1283         ADM8211_CSR_WRITE(BSSID0, le32_to_cpu(*(__le32 *)bssid));
1284         reg = ADM8211_CSR_READ(ABDA1);
1285         reg &= 0x0000ffff;
1286         reg |= (bssid[4] << 16) | (bssid[5] << 24);
1287         ADM8211_CSR_WRITE(ABDA1, reg);
1288 }
1289
1290 static int adm8211_config(struct ieee80211_hw *dev, u32 changed)
1291 {
1292         struct adm8211_priv *priv = dev->priv;
1293         struct ieee80211_conf *conf = &dev->conf;
1294         int channel = ieee80211_frequency_to_channel(conf->channel->center_freq);
1295
1296         if (channel != priv->channel) {
1297                 priv->channel = channel;
1298                 adm8211_rf_set_channel(dev, priv->channel);
1299         }
1300
1301         return 0;
1302 }
1303
1304 static void adm8211_bss_info_changed(struct ieee80211_hw *dev,
1305                                      struct ieee80211_vif *vif,
1306                                      struct ieee80211_bss_conf *conf,
1307                                      u32 changes)
1308 {
1309         struct adm8211_priv *priv = dev->priv;
1310
1311         if (!(changes & BSS_CHANGED_BSSID))
1312                 return;
1313
1314         if (memcmp(conf->bssid, priv->bssid, ETH_ALEN)) {
1315                 adm8211_set_bssid(dev, conf->bssid);
1316                 memcpy(priv->bssid, conf->bssid, ETH_ALEN);
1317         }
1318 }
1319
1320 static u64 adm8211_prepare_multicast(struct ieee80211_hw *hw,
1321                                      struct netdev_hw_addr_list *mc_list)
1322 {
1323         unsigned int bit_nr;
1324         u32 mc_filter[2];
1325         struct netdev_hw_addr *ha;
1326
1327         mc_filter[1] = mc_filter[0] = 0;
1328
1329         netdev_hw_addr_list_for_each(ha, mc_list) {
1330                 bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
1331
1332                 bit_nr &= 0x3F;
1333                 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
1334         }
1335
1336         return mc_filter[0] | ((u64)(mc_filter[1]) << 32);
1337 }
1338
1339 static void adm8211_configure_filter(struct ieee80211_hw *dev,
1340                                      unsigned int changed_flags,
1341                                      unsigned int *total_flags,
1342                                      u64 multicast)
1343 {
1344         static const u8 bcast[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
1345         struct adm8211_priv *priv = dev->priv;
1346         unsigned int new_flags;
1347         u32 mc_filter[2];
1348
1349         mc_filter[0] = multicast;
1350         mc_filter[1] = multicast >> 32;
1351
1352         new_flags = 0;
1353
1354         if (*total_flags & FIF_PROMISC_IN_BSS) {
1355                 new_flags |= FIF_PROMISC_IN_BSS;
1356                 priv->nar |= ADM8211_NAR_PR;
1357                 priv->nar &= ~ADM8211_NAR_MM;
1358                 mc_filter[1] = mc_filter[0] = ~0;
1359         } else if (*total_flags & FIF_ALLMULTI || multicast == ~(0ULL)) {
1360                 new_flags |= FIF_ALLMULTI;
1361                 priv->nar &= ~ADM8211_NAR_PR;
1362                 priv->nar |= ADM8211_NAR_MM;
1363                 mc_filter[1] = mc_filter[0] = ~0;
1364         } else {
1365                 priv->nar &= ~(ADM8211_NAR_MM | ADM8211_NAR_PR);
1366         }
1367
1368         ADM8211_IDLE_RX();
1369
1370         ADM8211_CSR_WRITE(MAR0, mc_filter[0]);
1371         ADM8211_CSR_WRITE(MAR1, mc_filter[1]);
1372         ADM8211_CSR_READ(NAR);
1373
1374         if (priv->nar & ADM8211_NAR_PR)
1375                 dev->flags |= IEEE80211_HW_RX_INCLUDES_FCS;
1376         else
1377                 dev->flags &= ~IEEE80211_HW_RX_INCLUDES_FCS;
1378
1379         if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
1380                 adm8211_set_bssid(dev, bcast);
1381         else
1382                 adm8211_set_bssid(dev, priv->bssid);
1383
1384         ADM8211_RESTORE();
1385
1386         *total_flags = new_flags;
1387 }
1388
1389 static int adm8211_add_interface(struct ieee80211_hw *dev,
1390                                  struct ieee80211_vif *vif)
1391 {
1392         struct adm8211_priv *priv = dev->priv;
1393         if (priv->mode != NL80211_IFTYPE_MONITOR)
1394                 return -EOPNOTSUPP;
1395
1396         switch (vif->type) {
1397         case NL80211_IFTYPE_STATION:
1398                 priv->mode = vif->type;
1399                 break;
1400         default:
1401                 return -EOPNOTSUPP;
1402         }
1403
1404         ADM8211_IDLE();
1405
1406         ADM8211_CSR_WRITE(PAR0, le32_to_cpu(*(__le32 *)vif->addr));
1407         ADM8211_CSR_WRITE(PAR1, le16_to_cpu(*(__le16 *)(vif->addr + 4)));
1408
1409         adm8211_update_mode(dev);
1410
1411         ADM8211_RESTORE();
1412
1413         return 0;
1414 }
1415
1416 static void adm8211_remove_interface(struct ieee80211_hw *dev,
1417                                      struct ieee80211_vif *vif)
1418 {
1419         struct adm8211_priv *priv = dev->priv;
1420         priv->mode = NL80211_IFTYPE_MONITOR;
1421 }
1422
1423 static int adm8211_init_rings(struct ieee80211_hw *dev)
1424 {
1425         struct adm8211_priv *priv = dev->priv;
1426         struct adm8211_desc *desc = NULL;
1427         struct adm8211_rx_ring_info *rx_info;
1428         struct adm8211_tx_ring_info *tx_info;
1429         unsigned int i;
1430
1431         for (i = 0; i < priv->rx_ring_size; i++) {
1432                 desc = &priv->rx_ring[i];
1433                 desc->status = 0;
1434                 desc->length = cpu_to_le32(RX_PKT_SIZE);
1435                 priv->rx_buffers[i].skb = NULL;
1436         }
1437         /* Mark the end of RX ring; hw returns to base address after this
1438          * descriptor */
1439         desc->length |= cpu_to_le32(RDES1_CONTROL_RER);
1440
1441         for (i = 0; i < priv->rx_ring_size; i++) {
1442                 desc = &priv->rx_ring[i];
1443                 rx_info = &priv->rx_buffers[i];
1444
1445                 rx_info->skb = dev_alloc_skb(RX_PKT_SIZE);
1446                 if (rx_info->skb == NULL)
1447                         break;
1448                 rx_info->mapping = pci_map_single(priv->pdev,
1449                                                   skb_tail_pointer(rx_info->skb),
1450                                                   RX_PKT_SIZE,
1451                                                   PCI_DMA_FROMDEVICE);
1452                 desc->buffer1 = cpu_to_le32(rx_info->mapping);
1453                 desc->status = cpu_to_le32(RDES0_STATUS_OWN | RDES0_STATUS_SQL);
1454         }
1455
1456         /* Setup TX ring. TX buffers descriptors will be filled in as needed */
1457         for (i = 0; i < priv->tx_ring_size; i++) {
1458                 desc = &priv->tx_ring[i];
1459                 tx_info = &priv->tx_buffers[i];
1460
1461                 tx_info->skb = NULL;
1462                 tx_info->mapping = 0;
1463                 desc->status = 0;
1464         }
1465         desc->length = cpu_to_le32(TDES1_CONTROL_TER);
1466
1467         priv->cur_rx = priv->cur_tx = priv->dirty_tx = 0;
1468         ADM8211_CSR_WRITE(RDB, priv->rx_ring_dma);
1469         ADM8211_CSR_WRITE(TDBD, priv->tx_ring_dma);
1470
1471         return 0;
1472 }
1473
1474 static void adm8211_free_rings(struct ieee80211_hw *dev)
1475 {
1476         struct adm8211_priv *priv = dev->priv;
1477         unsigned int i;
1478
1479         for (i = 0; i < priv->rx_ring_size; i++) {
1480                 if (!priv->rx_buffers[i].skb)
1481                         continue;
1482
1483                 pci_unmap_single(
1484                         priv->pdev,
1485                         priv->rx_buffers[i].mapping,
1486                         RX_PKT_SIZE, PCI_DMA_FROMDEVICE);
1487
1488                 dev_kfree_skb(priv->rx_buffers[i].skb);
1489         }
1490
1491         for (i = 0; i < priv->tx_ring_size; i++) {
1492                 if (!priv->tx_buffers[i].skb)
1493                         continue;
1494
1495                 pci_unmap_single(priv->pdev,
1496                                  priv->tx_buffers[i].mapping,
1497                                  priv->tx_buffers[i].skb->len,
1498                                  PCI_DMA_TODEVICE);
1499
1500                 dev_kfree_skb(priv->tx_buffers[i].skb);
1501         }
1502 }
1503
1504 static int adm8211_start(struct ieee80211_hw *dev)
1505 {
1506         struct adm8211_priv *priv = dev->priv;
1507         int retval;
1508
1509         /* Power up MAC and RF chips */
1510         retval = adm8211_hw_reset(dev);
1511         if (retval) {
1512                 printk(KERN_ERR "%s: hardware reset failed\n",
1513                        wiphy_name(dev->wiphy));
1514                 goto fail;
1515         }
1516
1517         retval = adm8211_init_rings(dev);
1518         if (retval) {
1519                 printk(KERN_ERR "%s: failed to initialize rings\n",
1520                        wiphy_name(dev->wiphy));
1521                 goto fail;
1522         }
1523
1524         /* Init hardware */
1525         adm8211_hw_init(dev);
1526         adm8211_rf_set_channel(dev, priv->channel);
1527
1528         retval = request_irq(priv->pdev->irq, adm8211_interrupt,
1529                              IRQF_SHARED, "adm8211", dev);
1530         if (retval) {
1531                 printk(KERN_ERR "%s: failed to register IRQ handler\n",
1532                        wiphy_name(dev->wiphy));
1533                 goto fail;
1534         }
1535
1536         ADM8211_CSR_WRITE(IER, ADM8211_IER_NIE | ADM8211_IER_AIE |
1537                                ADM8211_IER_RCIE | ADM8211_IER_TCIE |
1538                                ADM8211_IER_TDUIE | ADM8211_IER_GPTIE);
1539         priv->mode = NL80211_IFTYPE_MONITOR;
1540         adm8211_update_mode(dev);
1541         ADM8211_CSR_WRITE(RDR, 0);
1542
1543         adm8211_set_interval(dev, 100, 10);
1544         return 0;
1545
1546 fail:
1547         return retval;
1548 }
1549
1550 static void adm8211_stop(struct ieee80211_hw *dev)
1551 {
1552         struct adm8211_priv *priv = dev->priv;
1553
1554         priv->mode = NL80211_IFTYPE_UNSPECIFIED;
1555         priv->nar = 0;
1556         ADM8211_CSR_WRITE(NAR, 0);
1557         ADM8211_CSR_WRITE(IER, 0);
1558         ADM8211_CSR_READ(NAR);
1559
1560         free_irq(priv->pdev->irq, dev);
1561
1562         adm8211_free_rings(dev);
1563 }
1564
1565 static void adm8211_calc_durations(int *dur, int *plcp, size_t payload_len, int len,
1566                                    int plcp_signal, int short_preamble)
1567 {
1568         /* Alternative calculation from NetBSD: */
1569
1570 /* IEEE 802.11b durations for DSSS PHY in microseconds */
1571 #define IEEE80211_DUR_DS_LONG_PREAMBLE  144
1572 #define IEEE80211_DUR_DS_SHORT_PREAMBLE 72
1573 #define IEEE80211_DUR_DS_FAST_PLCPHDR   24
1574 #define IEEE80211_DUR_DS_SLOW_PLCPHDR   48
1575 #define IEEE80211_DUR_DS_SLOW_ACK       112
1576 #define IEEE80211_DUR_DS_FAST_ACK       56
1577 #define IEEE80211_DUR_DS_SLOW_CTS       112
1578 #define IEEE80211_DUR_DS_FAST_CTS       56
1579 #define IEEE80211_DUR_DS_SLOT           20
1580 #define IEEE80211_DUR_DS_SIFS           10
1581
1582         int remainder;
1583
1584         *dur = (80 * (24 + payload_len) + plcp_signal - 1)
1585                 / plcp_signal;
1586
1587         if (plcp_signal <= PLCP_SIGNAL_2M)
1588                 /* 1-2Mbps WLAN: send ACK/CTS at 1Mbps */
1589                 *dur += 3 * (IEEE80211_DUR_DS_SIFS +
1590                              IEEE80211_DUR_DS_SHORT_PREAMBLE +
1591                              IEEE80211_DUR_DS_FAST_PLCPHDR) +
1592                              IEEE80211_DUR_DS_SLOW_CTS + IEEE80211_DUR_DS_SLOW_ACK;
1593         else
1594                 /* 5-11Mbps WLAN: send ACK/CTS at 2Mbps */
1595                 *dur += 3 * (IEEE80211_DUR_DS_SIFS +
1596                              IEEE80211_DUR_DS_SHORT_PREAMBLE +
1597                              IEEE80211_DUR_DS_FAST_PLCPHDR) +
1598                              IEEE80211_DUR_DS_FAST_CTS + IEEE80211_DUR_DS_FAST_ACK;
1599
1600         /* lengthen duration if long preamble */
1601         if (!short_preamble)
1602                 *dur += 3 * (IEEE80211_DUR_DS_LONG_PREAMBLE -
1603                              IEEE80211_DUR_DS_SHORT_PREAMBLE) +
1604                         3 * (IEEE80211_DUR_DS_SLOW_PLCPHDR -
1605                              IEEE80211_DUR_DS_FAST_PLCPHDR);
1606
1607
1608         *plcp = (80 * len) / plcp_signal;
1609         remainder = (80 * len) % plcp_signal;
1610         if (plcp_signal == PLCP_SIGNAL_11M &&
1611             remainder <= 30 && remainder > 0)
1612                 *plcp = (*plcp | 0x8000) + 1;
1613         else if (remainder)
1614                 (*plcp)++;
1615 }
1616
1617 /* Transmit skb w/adm8211_tx_hdr (802.11 header created by hardware) */
1618 static void adm8211_tx_raw(struct ieee80211_hw *dev, struct sk_buff *skb,
1619                            u16 plcp_signal,
1620                            size_t hdrlen)
1621 {
1622         struct adm8211_priv *priv = dev->priv;
1623         unsigned long flags;
1624         dma_addr_t mapping;
1625         unsigned int entry;
1626         u32 flag;
1627
1628         mapping = pci_map_single(priv->pdev, skb->data, skb->len,
1629                                  PCI_DMA_TODEVICE);
1630
1631         spin_lock_irqsave(&priv->lock, flags);
1632
1633         if (priv->cur_tx - priv->dirty_tx == priv->tx_ring_size / 2)
1634                 flag = TDES1_CONTROL_IC | TDES1_CONTROL_LS | TDES1_CONTROL_FS;
1635         else
1636                 flag = TDES1_CONTROL_LS | TDES1_CONTROL_FS;
1637
1638         if (priv->cur_tx - priv->dirty_tx == priv->tx_ring_size - 2)
1639                 ieee80211_stop_queue(dev, 0);
1640
1641         entry = priv->cur_tx % priv->tx_ring_size;
1642
1643         priv->tx_buffers[entry].skb = skb;
1644         priv->tx_buffers[entry].mapping = mapping;
1645         priv->tx_buffers[entry].hdrlen = hdrlen;
1646         priv->tx_ring[entry].buffer1 = cpu_to_le32(mapping);
1647
1648         if (entry == priv->tx_ring_size - 1)
1649                 flag |= TDES1_CONTROL_TER;
1650         priv->tx_ring[entry].length = cpu_to_le32(flag | skb->len);
1651
1652         /* Set TX rate (SIGNAL field in PLCP PPDU format) */
1653         flag = TDES0_CONTROL_OWN | (plcp_signal << 20) | 8 /* ? */;
1654         priv->tx_ring[entry].status = cpu_to_le32(flag);
1655
1656         priv->cur_tx++;
1657
1658         spin_unlock_irqrestore(&priv->lock, flags);
1659
1660         /* Trigger transmit poll */
1661         ADM8211_CSR_WRITE(TDR, 0);
1662 }
1663
1664 /* Put adm8211_tx_hdr on skb and transmit */
1665 static int adm8211_tx(struct ieee80211_hw *dev, struct sk_buff *skb)
1666 {
1667         struct adm8211_tx_hdr *txhdr;
1668         size_t payload_len, hdrlen;
1669         int plcp, dur, len, plcp_signal, short_preamble;
1670         struct ieee80211_hdr *hdr;
1671         struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1672         struct ieee80211_rate *txrate = ieee80211_get_tx_rate(dev, info);
1673         u8 rc_flags;
1674
1675         rc_flags = info->control.rates[0].flags;
1676         short_preamble = !!(rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE);
1677         plcp_signal = txrate->bitrate;
1678
1679         hdr = (struct ieee80211_hdr *)skb->data;
1680         hdrlen = ieee80211_hdrlen(hdr->frame_control);
1681         memcpy(skb->cb, skb->data, hdrlen);
1682         hdr = (struct ieee80211_hdr *)skb->cb;
1683         skb_pull(skb, hdrlen);
1684         payload_len = skb->len;
1685
1686         txhdr = (struct adm8211_tx_hdr *) skb_push(skb, sizeof(*txhdr));
1687         memset(txhdr, 0, sizeof(*txhdr));
1688         memcpy(txhdr->da, ieee80211_get_DA(hdr), ETH_ALEN);
1689         txhdr->signal = plcp_signal;
1690         txhdr->frame_body_size = cpu_to_le16(payload_len);
1691         txhdr->frame_control = hdr->frame_control;
1692
1693         len = hdrlen + payload_len + FCS_LEN;
1694
1695         txhdr->frag = cpu_to_le16(0x0FFF);
1696         adm8211_calc_durations(&dur, &plcp, payload_len,
1697                                len, plcp_signal, short_preamble);
1698         txhdr->plcp_frag_head_len = cpu_to_le16(plcp);
1699         txhdr->plcp_frag_tail_len = cpu_to_le16(plcp);
1700         txhdr->dur_frag_head = cpu_to_le16(dur);
1701         txhdr->dur_frag_tail = cpu_to_le16(dur);
1702
1703         txhdr->header_control = cpu_to_le16(ADM8211_TXHDRCTL_ENABLE_EXTEND_HEADER);
1704
1705         if (short_preamble)
1706                 txhdr->header_control |= cpu_to_le16(ADM8211_TXHDRCTL_SHORT_PREAMBLE);
1707
1708         if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS)
1709                 txhdr->header_control |= cpu_to_le16(ADM8211_TXHDRCTL_ENABLE_RTS);
1710
1711         txhdr->retry_limit = info->control.rates[0].count;
1712
1713         adm8211_tx_raw(dev, skb, plcp_signal, hdrlen);
1714
1715         return NETDEV_TX_OK;
1716 }
1717
1718 static int adm8211_alloc_rings(struct ieee80211_hw *dev)
1719 {
1720         struct adm8211_priv *priv = dev->priv;
1721         unsigned int ring_size;
1722
1723         priv->rx_buffers = kmalloc(sizeof(*priv->rx_buffers) * priv->rx_ring_size +
1724                                    sizeof(*priv->tx_buffers) * priv->tx_ring_size, GFP_KERNEL);
1725         if (!priv->rx_buffers)
1726                 return -ENOMEM;
1727
1728         priv->tx_buffers = (void *)priv->rx_buffers +
1729                            sizeof(*priv->rx_buffers) * priv->rx_ring_size;
1730
1731         /* Allocate TX/RX descriptors */
1732         ring_size = sizeof(struct adm8211_desc) * priv->rx_ring_size +
1733                     sizeof(struct adm8211_desc) * priv->tx_ring_size;
1734         priv->rx_ring = pci_alloc_consistent(priv->pdev, ring_size,
1735                                              &priv->rx_ring_dma);
1736
1737         if (!priv->rx_ring) {
1738                 kfree(priv->rx_buffers);
1739                 priv->rx_buffers = NULL;
1740                 priv->tx_buffers = NULL;
1741                 return -ENOMEM;
1742         }
1743
1744         priv->tx_ring = (struct adm8211_desc *)(priv->rx_ring +
1745                                                 priv->rx_ring_size);
1746         priv->tx_ring_dma = priv->rx_ring_dma +
1747                             sizeof(struct adm8211_desc) * priv->rx_ring_size;
1748
1749         return 0;
1750 }
1751
1752 static const struct ieee80211_ops adm8211_ops = {
1753         .tx                     = adm8211_tx,
1754         .start                  = adm8211_start,
1755         .stop                   = adm8211_stop,
1756         .add_interface          = adm8211_add_interface,
1757         .remove_interface       = adm8211_remove_interface,
1758         .config                 = adm8211_config,
1759         .bss_info_changed       = adm8211_bss_info_changed,
1760         .prepare_multicast      = adm8211_prepare_multicast,
1761         .configure_filter       = adm8211_configure_filter,
1762         .get_stats              = adm8211_get_stats,
1763         .get_tsf                = adm8211_get_tsft
1764 };
1765
1766 static int __devinit adm8211_probe(struct pci_dev *pdev,
1767                                    const struct pci_device_id *id)
1768 {
1769         struct ieee80211_hw *dev;
1770         struct adm8211_priv *priv;
1771         unsigned long mem_addr, mem_len;
1772         unsigned int io_addr, io_len;
1773         int err;
1774         u32 reg;
1775         u8 perm_addr[ETH_ALEN];
1776
1777         err = pci_enable_device(pdev);
1778         if (err) {
1779                 printk(KERN_ERR "%s (adm8211): Cannot enable new PCI device\n",
1780                        pci_name(pdev));
1781                 return err;
1782         }
1783
1784         io_addr = pci_resource_start(pdev, 0);
1785         io_len = pci_resource_len(pdev, 0);
1786         mem_addr = pci_resource_start(pdev, 1);
1787         mem_len = pci_resource_len(pdev, 1);
1788         if (io_len < 256 || mem_len < 1024) {
1789                 printk(KERN_ERR "%s (adm8211): Too short PCI resources\n",
1790                        pci_name(pdev));
1791                 goto err_disable_pdev;
1792         }
1793
1794
1795         /* check signature */
1796         pci_read_config_dword(pdev, 0x80 /* CR32 */, &reg);
1797         if (reg != ADM8211_SIG1 && reg != ADM8211_SIG2) {
1798                 printk(KERN_ERR "%s (adm8211): Invalid signature (0x%x)\n",
1799                        pci_name(pdev), reg);
1800                 goto err_disable_pdev;
1801         }
1802
1803         err = pci_request_regions(pdev, "adm8211");
1804         if (err) {
1805                 printk(KERN_ERR "%s (adm8211): Cannot obtain PCI resources\n",
1806                        pci_name(pdev));
1807                 return err; /* someone else grabbed it? don't disable it */
1808         }
1809
1810         if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) ||
1811             pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) {
1812                 printk(KERN_ERR "%s (adm8211): No suitable DMA available\n",
1813                        pci_name(pdev));
1814                 goto err_free_reg;
1815         }
1816
1817         pci_set_master(pdev);
1818
1819         dev = ieee80211_alloc_hw(sizeof(*priv), &adm8211_ops);
1820         if (!dev) {
1821                 printk(KERN_ERR "%s (adm8211): ieee80211 alloc failed\n",
1822                        pci_name(pdev));
1823                 err = -ENOMEM;
1824                 goto err_free_reg;
1825         }
1826         priv = dev->priv;
1827         priv->pdev = pdev;
1828
1829         spin_lock_init(&priv->lock);
1830
1831         SET_IEEE80211_DEV(dev, &pdev->dev);
1832
1833         pci_set_drvdata(pdev, dev);
1834
1835         priv->map = pci_iomap(pdev, 1, mem_len);
1836         if (!priv->map)
1837                 priv->map = pci_iomap(pdev, 0, io_len);
1838
1839         if (!priv->map) {
1840                 printk(KERN_ERR "%s (adm8211): Cannot map device memory\n",
1841                        pci_name(pdev));
1842                 goto err_free_dev;
1843         }
1844
1845         priv->rx_ring_size = rx_ring_size;
1846         priv->tx_ring_size = tx_ring_size;
1847
1848         if (adm8211_alloc_rings(dev)) {
1849                 printk(KERN_ERR "%s (adm8211): Cannot allocate TX/RX ring\n",
1850                        pci_name(pdev));
1851                 goto err_iounmap;
1852         }
1853
1854         *(__le32 *)perm_addr = cpu_to_le32(ADM8211_CSR_READ(PAR0));
1855         *(__le16 *)&perm_addr[4] =
1856                 cpu_to_le16(ADM8211_CSR_READ(PAR1) & 0xFFFF);
1857
1858         if (!is_valid_ether_addr(perm_addr)) {
1859                 printk(KERN_WARNING "%s (adm8211): Invalid hwaddr in EEPROM!\n",
1860                        pci_name(pdev));
1861                 random_ether_addr(perm_addr);
1862         }
1863         SET_IEEE80211_PERM_ADDR(dev, perm_addr);
1864
1865         dev->extra_tx_headroom = sizeof(struct adm8211_tx_hdr);
1866         /* dev->flags = IEEE80211_HW_RX_INCLUDES_FCS in promisc mode */
1867         dev->flags = IEEE80211_HW_SIGNAL_UNSPEC;
1868         dev->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION);
1869
1870         dev->channel_change_time = 1000;
1871         dev->max_signal = 100;    /* FIXME: find better value */
1872
1873         dev->queues = 1; /* ADM8211C supports more, maybe ADM8211B too */
1874
1875         priv->retry_limit = 3;
1876         priv->ant_power = 0x40;
1877         priv->tx_power = 0x40;
1878         priv->lpf_cutoff = 0xFF;
1879         priv->lnags_threshold = 0xFF;
1880         priv->mode = NL80211_IFTYPE_UNSPECIFIED;
1881
1882         /* Power-on issue. EEPROM won't read correctly without */
1883         if (pdev->revision >= ADM8211_REV_BA) {
1884                 ADM8211_CSR_WRITE(FRCTL, 0);
1885                 ADM8211_CSR_READ(FRCTL);
1886                 ADM8211_CSR_WRITE(FRCTL, 1);
1887                 ADM8211_CSR_READ(FRCTL);
1888                 msleep(100);
1889         }
1890
1891         err = adm8211_read_eeprom(dev);
1892         if (err) {
1893                 printk(KERN_ERR "%s (adm8211): Can't alloc eeprom buffer\n",
1894                        pci_name(pdev));
1895                 goto err_free_desc;
1896         }
1897
1898         priv->channel = 1;
1899
1900         dev->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band;
1901
1902         err = ieee80211_register_hw(dev);
1903         if (err) {
1904                 printk(KERN_ERR "%s (adm8211): Cannot register device\n",
1905                        pci_name(pdev));
1906                 goto err_free_desc;
1907         }
1908
1909         printk(KERN_INFO "%s: hwaddr %pM, Rev 0x%02x\n",
1910                wiphy_name(dev->wiphy), dev->wiphy->perm_addr,
1911                pdev->revision);
1912
1913         return 0;
1914
1915  err_free_desc:
1916         pci_free_consistent(pdev,
1917                             sizeof(struct adm8211_desc) * priv->rx_ring_size +
1918                             sizeof(struct adm8211_desc) * priv->tx_ring_size,
1919                             priv->rx_ring, priv->rx_ring_dma);
1920         kfree(priv->rx_buffers);
1921
1922  err_iounmap:
1923         pci_iounmap(pdev, priv->map);
1924
1925  err_free_dev:
1926         pci_set_drvdata(pdev, NULL);
1927         ieee80211_free_hw(dev);
1928
1929  err_free_reg:
1930         pci_release_regions(pdev);
1931
1932  err_disable_pdev:
1933         pci_disable_device(pdev);
1934         return err;
1935 }
1936
1937
1938 static void __devexit adm8211_remove(struct pci_dev *pdev)
1939 {
1940         struct ieee80211_hw *dev = pci_get_drvdata(pdev);
1941         struct adm8211_priv *priv;
1942
1943         if (!dev)
1944                 return;
1945
1946         ieee80211_unregister_hw(dev);
1947
1948         priv = dev->priv;
1949
1950         pci_free_consistent(pdev,
1951                             sizeof(struct adm8211_desc) * priv->rx_ring_size +
1952                             sizeof(struct adm8211_desc) * priv->tx_ring_size,
1953                             priv->rx_ring, priv->rx_ring_dma);
1954
1955         kfree(priv->rx_buffers);
1956         kfree(priv->eeprom);
1957         pci_iounmap(pdev, priv->map);
1958         pci_release_regions(pdev);
1959         pci_disable_device(pdev);
1960         ieee80211_free_hw(dev);
1961 }
1962
1963
1964 #ifdef CONFIG_PM
1965 static int adm8211_suspend(struct pci_dev *pdev, pm_message_t state)
1966 {
1967         pci_save_state(pdev);
1968         pci_set_power_state(pdev, pci_choose_state(pdev, state));
1969         return 0;
1970 }
1971
1972 static int adm8211_resume(struct pci_dev *pdev)
1973 {
1974         pci_set_power_state(pdev, PCI_D0);
1975         pci_restore_state(pdev);
1976         return 0;
1977 }
1978 #endif /* CONFIG_PM */
1979
1980
1981 MODULE_DEVICE_TABLE(pci, adm8211_pci_id_table);
1982
1983 /* TODO: implement enable_wake */
1984 static struct pci_driver adm8211_driver = {
1985         .name           = "adm8211",
1986         .id_table       = adm8211_pci_id_table,
1987         .probe          = adm8211_probe,
1988         .remove         = __devexit_p(adm8211_remove),
1989 #ifdef CONFIG_PM
1990         .suspend        = adm8211_suspend,
1991         .resume         = adm8211_resume,
1992 #endif /* CONFIG_PM */
1993 };
1994
1995
1996
1997 static int __init adm8211_init(void)
1998 {
1999         return pci_register_driver(&adm8211_driver);
2000 }
2001
2002
2003 static void __exit adm8211_exit(void)
2004 {
2005         pci_unregister_driver(&adm8211_driver);
2006 }
2007
2008
2009 module_init(adm8211_init);
2010 module_exit(adm8211_exit);