SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/net/wireless/adm8211.c

   1
   2 /*
   3  * Linux device driver for ADMtek ADM8211 (IEEE 802.11b MAC/BBP)
   4  *
   5  * Copyright (c) 2003, Jouni Malinen <j@w1.fi>
   6  * Copyright (c) 2004-2007, Michael Wu <flamingice@sourmilk.net>
   7  * Some parts copyright (c) 2003 by David Young <dyoung@pobox.com>
   8  * and used with permission.
   9  *
  10  * Much thanks to Infineon-ADMtek for their support of this driver.
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License version 2 as
  14  * published by the Free Software Foundation. See README and COPYING for
  15  * more details.
  16  */
  17
  18 #include <linux/init.h>
  19 #include <linux/if.h>
  20 #include <linux/skbuff.h>
  21 #include <linux/etherdevice.h>
  22 #include <linux/pci.h>
  23 #include <linux/delay.h>
  24 #include <linux/crc32.h>
  25 #include <linux/eeprom_93cx6.h>
  26 #include <net/mac80211.h>
  27
  28 #include "adm8211.h"
  29
  30 MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>");
  31 MODULE_AUTHOR("Jouni Malinen <j@w1.fi>");
  32 MODULE_DESCRIPTION("Driver for IEEE 802.11b wireless cards based on ADMtek ADM8211");
  33 MODULE_SUPPORTED_DEVICE("ADM8211");
  34 MODULE_LICENSE("GPL");
  35
  36 static unsigned int tx_ring_size __read_mostly = 16;
  37 static unsigned int rx_ring_size __read_mostly = 16;
  38
  39 module_param(tx_ring_size, uint, 0);
  40 module_param(rx_ring_size, uint, 0);
  41
  42 static const char version[] = KERN_INFO "adm8211: "
  43 "Copyright 2003, Jouni Malinen <j@w1.fi>; "
  44 "Copyright 2004-2007, Michael Wu <flamingice@sourmilk.net>\n";
  45
  46
  47 static struct pci_device_id adm8211_pci_id_table[] __devinitdata = {
  48         /* ADMtek ADM8211 */
  49         { PCI_DEVICE(0x10B7, 0x6000) }, /* 3Com 3CRSHPW796 */
  50         { PCI_DEVICE(0x1200, 0x8201) }, /* ? */
  51         { PCI_DEVICE(0x1317, 0x8201) }, /* ADM8211A */
  52         { PCI_DEVICE(0x1317, 0x8211) }, /* ADM8211B/C */
  53         { 0 }
  54 };
  55
  56 static void adm8211_eeprom_register_read(struct eeprom_93cx6 *eeprom)
  57 {
  58         struct adm8211_priv *priv = eeprom->data;
  59         u32 reg = ADM8211_CSR_READ(SPR);
  60
  61         eeprom->reg_data_in = reg & ADM8211_SPR_SDI;
  62         eeprom->reg_data_out = reg & ADM8211_SPR_SDO;
  63         eeprom->reg_data_clock = reg & ADM8211_SPR_SCLK;
  64         eeprom->reg_chip_select = reg & ADM8211_SPR_SCS;
  65 }
  66
  67 static void adm8211_eeprom_register_write(struct eeprom_93cx6 *eeprom)
  68 {
  69         struct adm8211_priv *priv = eeprom->data;
  70         u32 reg = 0x4000 | ADM8211_SPR_SRS;
  71
  72         if (eeprom->reg_data_in)
  73                 reg |= ADM8211_SPR_SDI;
  74         if (eeprom->reg_data_out)
  75                 reg |= ADM8211_SPR_SDO;
  76         if (eeprom->reg_data_clock)
  77                 reg |= ADM8211_SPR_SCLK;
  78         if (eeprom->reg_chip_select)
  79                 reg |= ADM8211_SPR_SCS;
  80
  81         ADM8211_CSR_WRITE(SPR, reg);
  82         ADM8211_CSR_READ(SPR);          /* eeprom_delay */
  83 }
  84
  85 static int adm8211_read_eeprom(struct ieee80211_hw *dev)
  86 {
  87         struct adm8211_priv *priv = dev->priv;
  88         unsigned int words, i;
  89         struct ieee80211_chan_range chan_range;
  90         u16 cr49;
  91         struct eeprom_93cx6 eeprom = {
  92                 .data           = priv,
  93                 .register_read  = adm8211_eeprom_register_read,
  94                 .register_write = adm8211_eeprom_register_write
  95         };
  96
  97         if (ADM8211_CSR_READ(CSR_TEST0) & ADM8211_CSR_TEST0_EPTYP) {
  98                 /* 256 * 16-bit = 512 bytes */
  99                 eeprom.width = PCI_EEPROM_WIDTH_93C66;
 100                 words = 256;
 101         } else {
 102                 /* 64 * 16-bit = 128 bytes */
 103                 eeprom.width = PCI_EEPROM_WIDTH_93C46;
 104                 words = 64;
 105         }
 106
 107         priv->eeprom_len = words * 2;
 108         priv->eeprom = kmalloc(priv->eeprom_len, GFP_KERNEL);
 109         if (!priv->eeprom)
 110                 return -ENOMEM;
 111
 112         eeprom_93cx6_multiread(&eeprom, 0, (__le16 __force *)priv->eeprom, words);
 113
 114         cr49 = le16_to_cpu(priv->eeprom->cr49);
 115         priv->rf_type = (cr49 >> 3) & 0x7;
 116         switch (priv->rf_type) {
 117         case ADM8211_TYPE_INTERSIL:
 118         case ADM8211_TYPE_RFMD:
 119         case ADM8211_TYPE_MARVEL:
 120         case ADM8211_TYPE_AIROHA:
 121         case ADM8211_TYPE_ADMTEK:
 122                 break;
 123
 124         default:
 125                 if (priv->revid < ADM8211_REV_CA)
 126                         priv->rf_type = ADM8211_TYPE_RFMD;
 127                 else
 128                         priv->rf_type = ADM8211_TYPE_AIROHA;
 129
 130                 printk(KERN_WARNING "%s (adm8211): Unknown RFtype %d\n",
 131                        pci_name(priv->pdev), (cr49 >> 3) & 0x7);
 132         }
 133
 134         priv->bbp_type = cr49 & 0x7;
 135         switch (priv->bbp_type) {
 136         case ADM8211_TYPE_INTERSIL:
 137         case ADM8211_TYPE_RFMD:
 138         case ADM8211_TYPE_MARVEL:
 139         case ADM8211_TYPE_AIROHA:
 140         case ADM8211_TYPE_ADMTEK:
 141                 break;
 142         default:
 143                 if (priv->revid < ADM8211_REV_CA)
 144                         priv->bbp_type = ADM8211_TYPE_RFMD;
 145                 else
 146                         priv->bbp_type = ADM8211_TYPE_ADMTEK;
 147
 148                 printk(KERN_WARNING "%s (adm8211): Unknown BBPtype: %d\n",
 149                        pci_name(priv->pdev), cr49 >> 3);
 150         }
 151
 152         if (priv->eeprom->country_code >= ARRAY_SIZE(cranges)) {
 153                 printk(KERN_WARNING "%s (adm8211): Invalid country code (%d)\n",
 154                        pci_name(priv->pdev), priv->eeprom->country_code);
 155
 156                 chan_range = cranges[2];
 157         } else
 158                 chan_range = cranges[priv->eeprom->country_code];
 159
 160         printk(KERN_DEBUG "%s (adm8211): Channel range: %d - %d\n",
 161                pci_name(priv->pdev), (int)chan_range.min, (int)chan_range.max);
 162
 163         priv->modes[0].num_channels = chan_range.max - chan_range.min + 1;
 164         priv->modes[0].channels = priv->channels;
 165
 166         memcpy(priv->channels, adm8211_channels, sizeof(adm8211_channels));
 167
 168         for (i = 1; i <= ARRAY_SIZE(adm8211_channels); i++)
 169                 if (i >= chan_range.min && i <= chan_range.max)
 170                         priv->channels[i - 1].flag =
 171                                 IEEE80211_CHAN_W_SCAN |
 172                                 IEEE80211_CHAN_W_ACTIVE_SCAN |
 173                                 IEEE80211_CHAN_W_IBSS;
 174
 175         switch (priv->eeprom->specific_bbptype) {
 176         case ADM8211_BBP_RFMD3000:
 177         case ADM8211_BBP_RFMD3002:
 178         case ADM8211_BBP_ADM8011:
 179                 priv->specific_bbptype = priv->eeprom->specific_bbptype;
 180                 break;
 181
 182         default:
 183                 if (priv->revid < ADM8211_REV_CA)
 184                         priv->specific_bbptype = ADM8211_BBP_RFMD3000;
 185                 else
 186                         priv->specific_bbptype = ADM8211_BBP_ADM8011;
 187
 188                 printk(KERN_WARNING "%s (adm8211): Unknown specific BBP: %d\n",
 189                        pci_name(priv->pdev), priv->eeprom->specific_bbptype);
 190         }
 191
 192         switch (priv->eeprom->specific_rftype) {
 193         case ADM8211_RFMD2948:
 194         case ADM8211_RFMD2958:
 195         case ADM8211_RFMD2958_RF3000_CONTROL_POWER:
 196         case ADM8211_MAX2820:
 197         case ADM8211_AL2210L:
 198                 priv->transceiver_type = priv->eeprom->specific_rftype;
 199                 break;
 200
 201         default:
 202                 if (priv->revid == ADM8211_REV_BA)
 203                         priv->transceiver_type = ADM8211_RFMD2958_RF3000_CONTROL_POWER;
 204                 else if (priv->revid == ADM8211_REV_CA)
 205                         priv->transceiver_type = ADM8211_AL2210L;
 206                 else if (priv->revid == ADM8211_REV_AB)
 207                         priv->transceiver_type = ADM8211_RFMD2948;
 208
 209                 printk(KERN_WARNING "%s (adm8211): Unknown transceiver: %d\n",
 210                        pci_name(priv->pdev), priv->eeprom->specific_rftype);
 211
 212                 break;
 213         }
 214
 215         printk(KERN_DEBUG "%s (adm8211): RFtype=%d BBPtype=%d Specific BBP=%d "
 216                "Transceiver=%d\n", pci_name(priv->pdev), priv->rf_type,
 217                priv->bbp_type, priv->specific_bbptype, priv->transceiver_type);
 218
 219         return 0;
 220 }
 221
 222 static inline void adm8211_write_sram(struct ieee80211_hw *dev,
 223                                       u32 addr, u32 data)
 224 {
 225         struct adm8211_priv *priv = dev->priv;
 226
 227         ADM8211_CSR_WRITE(WEPCTL, addr | ADM8211_WEPCTL_TABLE_WR |
 228                           (priv->revid < ADM8211_REV_BA ?
 229                            0 : ADM8211_WEPCTL_SEL_WEPTABLE ));
 230         ADM8211_CSR_READ(WEPCTL);
 231         msleep(1);
 232
 233         ADM8211_CSR_WRITE(WESK, data);
 234         ADM8211_CSR_READ(WESK);
 235         msleep(1);
 236 }
 237
 238 static void adm8211_write_sram_bytes(struct ieee80211_hw *dev,
 239                                      unsigned int addr, u8 *buf,
 240                                      unsigned int len)
 241 {
 242         struct adm8211_priv *priv = dev->priv;
 243         u32 reg = ADM8211_CSR_READ(WEPCTL);
 244         unsigned int i;
 245
 246         if (priv->revid < ADM8211_REV_BA) {
 247                 for (i = 0; i < len; i += 2) {
 248                         u16 val = buf[i] | (buf[i + 1] << 8);
 249                         adm8211_write_sram(dev, addr + i / 2, val);
 250                 }
 251         } else {
 252                 for (i = 0; i < len; i += 4) {
 253                         u32 val = (buf[i + 0] << 0 ) | (buf[i + 1] << 8 ) |
 254                                   (buf[i + 2] << 16) | (buf[i + 3] << 24);
 255                         adm8211_write_sram(dev, addr + i / 4, val);
 256                 }
 257         }
 258
 259         ADM8211_CSR_WRITE(WEPCTL, reg);
 260 }
 261
 262 static void adm8211_clear_sram(struct ieee80211_hw *dev)
 263 {
 264         struct adm8211_priv *priv = dev->priv;
 265         u32 reg = ADM8211_CSR_READ(WEPCTL);
 266         unsigned int addr;
 267
 268         for (addr = 0; addr < ADM8211_SRAM_SIZE; addr++)
 269                 adm8211_write_sram(dev, addr, 0);
 270
 271         ADM8211_CSR_WRITE(WEPCTL, reg);
 272 }
 273
 274 static int adm8211_get_stats(struct ieee80211_hw *dev,
 275                              struct ieee80211_low_level_stats *stats)
 276 {
 277         struct adm8211_priv *priv = dev->priv;
 278
 279         memcpy(stats, &priv->stats, sizeof(*stats));
 280
 281         return 0;
 282 }
 283
 284 static int adm8211_get_tx_stats(struct ieee80211_hw *dev,
 285                                 struct ieee80211_tx_queue_stats *stats)
 286 {
 287         struct adm8211_priv *priv = dev->priv;
 288         struct ieee80211_tx_queue_stats_data *data = &stats->data[0];
 289
 290         data->len = priv->cur_tx - priv->dirty_tx;
 291         data->limit = priv->tx_ring_size - 2;
 292         data->count = priv->dirty_tx;
 293
 294         return 0;
 295 }
 296
 297 static void adm8211_interrupt_tci(struct ieee80211_hw *dev)
 298 {
 299         struct adm8211_priv *priv = dev->priv;
 300         unsigned int dirty_tx;
 301
 302         spin_lock(&priv->lock);
 303
 304         for (dirty_tx = priv->dirty_tx; priv->cur_tx - dirty_tx; dirty_tx++) {
 305                 unsigned int entry = dirty_tx % priv->tx_ring_size;
 306                 u32 status = le32_to_cpu(priv->tx_ring[entry].status);
 307                 struct adm8211_tx_ring_info *info;
 308                 struct sk_buff *skb;
 309
 310                 if (status & TDES0_CONTROL_OWN ||
 311                     !(status & TDES0_CONTROL_DONE))
 312                         break;
 313
 314                 info = &priv->tx_buffers[entry];
 315                 skb = info->skb;
 316
 317                 /* TODO: check TDES0_STATUS_TUF and TDES0_STATUS_TRO */
 318
 319                 pci_unmap_single(priv->pdev, info->mapping,
 320                                  info->skb->len, PCI_DMA_TODEVICE);
 321
 322                 if (info->tx_control.flags & IEEE80211_TXCTL_REQ_TX_STATUS) {
 323                         struct ieee80211_tx_status tx_status = {{0}};
 324                         struct ieee80211_hdr *hdr;
 325                         size_t hdrlen = info->hdrlen;
 326
 327                         skb_pull(skb, sizeof(struct adm8211_tx_hdr));
 328                         hdr = (struct ieee80211_hdr *)skb_push(skb, hdrlen);
 329                         memcpy(hdr, skb->cb, hdrlen);
 330                         memcpy(&tx_status.control, &info->tx_control,
 331                                sizeof(tx_status.control));
 332                         if (!(status & TDES0_STATUS_ES))
 333                                 tx_status.flags |= IEEE80211_TX_STATUS_ACK;
 334                         ieee80211_tx_status_irqsafe(dev, skb, &tx_status);
 335                 } else
 336                         dev_kfree_skb_irq(skb);
 337                 info->skb = NULL;
 338         }
 339
 340         if (priv->cur_tx - dirty_tx < priv->tx_ring_size - 2)
 341                 ieee80211_wake_queue(dev, 0);
 342
 343         priv->dirty_tx = dirty_tx;
 344         spin_unlock(&priv->lock);
 345 }
 346
 347
 348 static void adm8211_interrupt_rci(struct ieee80211_hw *dev)
 349 {
 350         struct adm8211_priv *priv = dev->priv;
 351         unsigned int entry = priv->cur_rx % priv->rx_ring_size;
 352         u32 status;
 353         unsigned int pktlen;
 354         struct sk_buff *skb, *newskb;
 355         unsigned int limit = priv->rx_ring_size;
 356         static const u8 rate_tbl[] = {10, 20, 55, 110, 220};
 357         u8 rssi, rate;
 358
 359         while (!(priv->rx_ring[entry].status & cpu_to_le32(RDES0_STATUS_OWN))) {
 360                 if (!limit--)
 361                         break;
 362
 363                 status = le32_to_cpu(priv->rx_ring[entry].status);
 364                 rate = (status & RDES0_STATUS_RXDR) >> 12;
 365                 rssi = le32_to_cpu(priv->rx_ring[entry].length) &
 366                         RDES1_STATUS_RSSI;
 367
 368                 pktlen = status & RDES0_STATUS_FL;
 369                 if (pktlen > RX_PKT_SIZE) {
 370                         if (net_ratelimit())
 371                                 printk(KERN_DEBUG "%s: frame too long (%d)\n",
 372                                        wiphy_name(dev->wiphy), pktlen);
 373                         pktlen = RX_PKT_SIZE;
 374                 }
 375
 376                 if (!priv->soft_rx_crc && status & RDES0_STATUS_ES) {
 377                         skb = NULL; /* old buffer will be reused */
 378                         /* TODO: update RX error stats */
 379                         /* TODO: check RDES0_STATUS_CRC*E */
 380                 } else if (pktlen < RX_COPY_BREAK) {
 381                         skb = dev_alloc_skb(pktlen);
 382                         if (skb) {
 383                                 pci_dma_sync_single_for_cpu(
 384                                         priv->pdev,
 385                                         priv->rx_buffers[entry].mapping,
 386                                         pktlen, PCI_DMA_FROMDEVICE);
 387                                 memcpy(skb_put(skb, pktlen),
 388                                        skb_tail_pointer(priv->rx_buffers[entry].skb),
 389                                        pktlen);
 390                                 pci_dma_sync_single_for_device(
 391                                         priv->pdev,
 392                                         priv->rx_buffers[entry].mapping,
 393                                         RX_PKT_SIZE, PCI_DMA_FROMDEVICE);
 394                         }
 395                 } else {
 396                         newskb = dev_alloc_skb(RX_PKT_SIZE);
 397                         if (newskb) {
 398                                 skb = priv->rx_buffers[entry].skb;
 399                                 skb_put(skb, pktlen);
 400                                 pci_unmap_single(
 401                                         priv->pdev,
 402                                         priv->rx_buffers[entry].mapping,
 403                                         RX_PKT_SIZE, PCI_DMA_FROMDEVICE);
 404                                 priv->rx_buffers[entry].skb = newskb;
 405                                 priv->rx_buffers[entry].mapping =
 406                                         pci_map_single(priv->pdev,
 407                                                        skb_tail_pointer(newskb),
 408                                                        RX_PKT_SIZE,
 409                                                        PCI_DMA_FROMDEVICE);
 410                         } else {
 411                                 skb = NULL;
 412                                 /* TODO: update rx dropped stats */
 413                         }
 414
 415                         priv->rx_ring[entry].buffer1 =
 416                                 cpu_to_le32(priv->rx_buffers[entry].mapping);
 417                 }
 418
 419                 priv->rx_ring[entry].status = cpu_to_le32(RDES0_STATUS_OWN |
 420                                                           RDES0_STATUS_SQL);
 421                 priv->rx_ring[entry].length =
 422                         cpu_to_le32(RX_PKT_SIZE |
 423                                     (entry == priv->rx_ring_size - 1 ?
 424                                      RDES1_CONTROL_RER : 0));
 425
 426                 if (skb) {
 427                         struct ieee80211_rx_status rx_status = {0};
 428
 429                         if (priv->revid < ADM8211_REV_CA)
 430                                 rx_status.ssi = rssi;
 431                         else
 432                                 rx_status.ssi = 100 - rssi;
 433
 434                         if (rate <= 4)
 435                                 rx_status.rate = rate_tbl[rate];
 436
 437                         rx_status.channel = priv->channel;
 438                         rx_status.freq = adm8211_channels[priv->channel - 1].freq;
 439                         rx_status.phymode = MODE_IEEE80211B;
 440
 441                         ieee80211_rx_irqsafe(dev, skb, &rx_status);
 442                 }
 443
 444                 entry = (++priv->cur_rx) % priv->rx_ring_size;
 445         }
 446
 447         /* TODO: check LPC and update stats? */
 448 }
 449
 450
 451 static irqreturn_t adm8211_interrupt(int irq, void *dev_id)
 452 {
 453 #define ADM8211_INT(x)                                                     \
 454 do {                                                                       \
 455         if (unlikely(stsr & ADM8211_STSR_ ## x))                           \
 456                 printk(KERN_DEBUG "%s: " #x "\n", wiphy_name(dev->wiphy)); \
 457 } while (0)
 458
 459         struct ieee80211_hw *dev = dev_id;
 460         struct adm8211_priv *priv = dev->priv;
 461         unsigned int count = 0;
 462         u32 stsr;
 463
 464         do {
 465                 stsr = ADM8211_CSR_READ(STSR);
 466                 ADM8211_CSR_WRITE(STSR, stsr);
 467                 if (stsr == 0xffffffff)
 468                         return IRQ_HANDLED;
 469
 470                 if (!(stsr & (ADM8211_STSR_NISS | ADM8211_STSR_AISS)))
 471                         break;
 472
 473                 if (stsr & ADM8211_STSR_RCI)
 474                         adm8211_interrupt_rci(dev);
 475                 if (stsr & ADM8211_STSR_TCI)
 476                         adm8211_interrupt_tci(dev);
 477
 478                 /*ADM8211_INT(LinkOn);*/
 479                 /*ADM8211_INT(LinkOff);*/
 480
 481                 ADM8211_INT(PCF);
 482                 ADM8211_INT(BCNTC);
 483                 ADM8211_INT(GPINT);
 484                 ADM8211_INT(ATIMTC);
 485                 ADM8211_INT(TSFTF);
 486                 ADM8211_INT(TSCZ);
 487                 ADM8211_INT(SQL);
 488                 ADM8211_INT(WEPTD);
 489                 ADM8211_INT(ATIME);
 490                 /*ADM8211_INT(TBTT);*/
 491                 ADM8211_INT(TEIS);
 492                 ADM8211_INT(FBE);
 493                 ADM8211_INT(REIS);
 494                 ADM8211_INT(GPTT);
 495                 ADM8211_INT(RPS);
 496                 ADM8211_INT(RDU);
 497                 ADM8211_INT(TUF);
 498                 /*ADM8211_INT(TRT);*/
 499                 /*ADM8211_INT(TLT);*/
 500                 /*ADM8211_INT(TDU);*/
 501                 ADM8211_INT(TPS);
 502
 503         } while (count++ < 20);
 504
 505         return IRQ_RETVAL(count);
 506
 507 #undef ADM8211_INT
 508 }
 509
 510 #define WRITE_SYN(name,v_mask,v_shift,a_mask,a_shift,bits,prewrite,postwrite)\
 511 static void adm8211_rf_write_syn_ ## name (struct ieee80211_hw *dev,         \
 512                                            u16 addr, u32 value) {            \
 513         struct adm8211_priv *priv = dev->priv;                               \
 514         unsigned int i;                                                      \
 515         u32 reg, bitbuf;                                                     \
 516                                                                              \
 517         value &= v_mask;                                                     \
 518         addr &= a_mask;                                                      \
 519         bitbuf = (value << v_shift) | (addr << a_shift);                     \
 520                                                                              \
 521         ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_IF_SELECT_1);                 \
 522         ADM8211_CSR_READ(SYNRF);                                             \
 523         ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_IF_SELECT_0);                 \
 524         ADM8211_CSR_READ(SYNRF);                                             \
 525                                                                              \
 526         if (prewrite) {                                                      \
 527                 ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_WRITE_SYNDATA_0);     \
 528                 ADM8211_CSR_READ(SYNRF);                                     \
 529         }                                                                    \
 530                                                                              \
 531         for (i = 0; i <= bits; i++) {                                        \
 532                 if (bitbuf & (1 << (bits - i)))                              \
 533                         reg = ADM8211_SYNRF_WRITE_SYNDATA_1;                 \
 534                 else                                                         \
 535                         reg = ADM8211_SYNRF_WRITE_SYNDATA_0;                 \
 536                                                                              \
 537                 ADM8211_CSR_WRITE(SYNRF, reg);                               \
 538                 ADM8211_CSR_READ(SYNRF);                                     \
 539                                                                              \
 540                 ADM8211_CSR_WRITE(SYNRF, reg | ADM8211_SYNRF_WRITE_CLOCK_1); \
 541                 ADM8211_CSR_READ(SYNRF);                                     \
 542                 ADM8211_CSR_WRITE(SYNRF, reg | ADM8211_SYNRF_WRITE_CLOCK_0); \
 543                 ADM8211_CSR_READ(SYNRF);                                     \
 544         }                                                                    \
 545                                                                              \
 546         if (postwrite == 1) {                                                \
 547                 ADM8211_CSR_WRITE(SYNRF, reg | ADM8211_SYNRF_IF_SELECT_0);   \
 548                 ADM8211_CSR_READ(SYNRF);                                     \
 549         }                                                                    \
 550         if (postwrite == 2) {                                                \
 551                 ADM8211_CSR_WRITE(SYNRF, reg | ADM8211_SYNRF_IF_SELECT_1);   \
 552                 ADM8211_CSR_READ(SYNRF);                                     \
 553         }                                                                    \
 554                                                                              \
 555         ADM8211_CSR_WRITE(SYNRF, 0);                                         \
 556         ADM8211_CSR_READ(SYNRF);                                             \
 557 }
 558
 559 WRITE_SYN(max2820,  0x00FFF, 0, 0x0F, 12, 15, 1, 1)
 560 WRITE_SYN(al2210l,  0xFFFFF, 4, 0x0F,  0, 23, 1, 1)
 561 WRITE_SYN(rfmd2958, 0x3FFFF, 0, 0x1F, 18, 23, 0, 1)
 562 WRITE_SYN(rfmd2948, 0x0FFFF, 4, 0x0F,  0, 21, 0, 2)
 563
 564 #undef WRITE_SYN
 565
 566 static int adm8211_write_bbp(struct ieee80211_hw *dev, u8 addr, u8 data)
 567 {
 568         struct adm8211_priv *priv = dev->priv;
 569         unsigned int timeout;
 570         u32 reg;
 571
 572         timeout = 10;
 573         while (timeout > 0) {
 574                 reg = ADM8211_CSR_READ(BBPCTL);
 575                 if (!(reg & (ADM8211_BBPCTL_WR | ADM8211_BBPCTL_RD)))
 576                         break;
 577                 timeout--;
 578                 msleep(2);
 579         }
 580
 581         if (timeout == 0) {
 582                 printk(KERN_DEBUG "%s: adm8211_write_bbp(%d,%d) failed"
 583                        " prewrite (reg=0x%08x)\n",
 584                        wiphy_name(dev->wiphy), addr, data, reg);
 585                 return -ETIMEDOUT;
 586         }
 587
 588         switch (priv->bbp_type) {
 589         case ADM8211_TYPE_INTERSIL:
 590                 reg = ADM8211_BBPCTL_MMISEL;    /* three wire interface */
 591                 break;
 592         case ADM8211_TYPE_RFMD:
 593                 reg = (0x20 << 24) | ADM8211_BBPCTL_TXCE | ADM8211_BBPCTL_CCAP |
 594                       (0x01 << 18);
 595                 break;
 596         case ADM8211_TYPE_ADMTEK:
 597                 reg = (0x20 << 24) | ADM8211_BBPCTL_TXCE | ADM8211_BBPCTL_CCAP |
 598                       (0x05 << 18);
 599                 break;
 600         }
 601         reg |= ADM8211_BBPCTL_WR | (addr << 8) | data;
 602
 603         ADM8211_CSR_WRITE(BBPCTL, reg);
 604
 605         timeout = 10;
 606         while (timeout > 0) {
 607                 reg = ADM8211_CSR_READ(BBPCTL);
 608                 if (!(reg & ADM8211_BBPCTL_WR))
 609                         break;
 610                 timeout--;
 611                 msleep(2);
 612         }
 613
 614         if (timeout == 0) {
 615                 ADM8211_CSR_WRITE(BBPCTL, ADM8211_CSR_READ(BBPCTL) &
 616                                   ~ADM8211_BBPCTL_WR);
 617                 printk(KERN_DEBUG "%s: adm8211_write_bbp(%d,%d) failed"
 618                        " postwrite (reg=0x%08x)\n",
 619                        wiphy_name(dev->wiphy), addr, data, reg);
 620                 return -ETIMEDOUT;
 621         }
 622
 623         return 0;
 624 }
 625
 626 static int adm8211_rf_set_channel(struct ieee80211_hw *dev, unsigned int chan)
 627 {
 628         static const u32 adm8211_rfmd2958_reg5[] =
 629                 {0x22BD, 0x22D2, 0x22E8, 0x22FE, 0x2314, 0x232A, 0x2340,
 630                  0x2355, 0x236B, 0x2381, 0x2397, 0x23AD, 0x23C2, 0x23F7};
 631         static const u32 adm8211_rfmd2958_reg6[] =
 632                 {0x05D17, 0x3A2E8, 0x2E8BA, 0x22E8B, 0x1745D, 0x0BA2E, 0x00000,
 633                  0x345D1, 0x28BA2, 0x1D174, 0x11745, 0x05D17, 0x3A2E8, 0x11745};
 634
 635         struct adm8211_priv *priv = dev->priv;
 636         u8 ant_power = priv->ant_power > 0x3F ?
 637                 priv->eeprom->antenna_power[chan - 1] : priv->ant_power;
 638         u8 tx_power = priv->tx_power > 0x3F ?
 639                 priv->eeprom->tx_power[chan - 1] : priv->tx_power;
 640         u8 lpf_cutoff = priv->lpf_cutoff == 0xFF ?
 641                 priv->eeprom->lpf_cutoff[chan - 1] : priv->lpf_cutoff;
 642         u8 lnags_thresh = priv->lnags_threshold == 0xFF ?
 643                 priv->eeprom->lnags_threshold[chan - 1] : priv->lnags_threshold;
 644         u32 reg;
 645
 646         ADM8211_IDLE();
 647
 648         /* Program synthesizer to new channel */
 649         switch (priv->transceiver_type) {
 650         case ADM8211_RFMD2958:
 651         case ADM8211_RFMD2958_RF3000_CONTROL_POWER:
 652                 adm8211_rf_write_syn_rfmd2958(dev, 0x00, 0x04007);
 653                 adm8211_rf_write_syn_rfmd2958(dev, 0x02, 0x00033);
 654
 655                 adm8211_rf_write_syn_rfmd2958(dev, 0x05,
 656                         adm8211_rfmd2958_reg5[chan - 1]);
 657                 adm8211_rf_write_syn_rfmd2958(dev, 0x06,
 658                         adm8211_rfmd2958_reg6[chan - 1]);
 659                 break;
 660
 661         case ADM8211_RFMD2948:
 662                 adm8211_rf_write_syn_rfmd2948(dev, SI4126_MAIN_CONF,
 663                                               SI4126_MAIN_XINDIV2);
 664                 adm8211_rf_write_syn_rfmd2948(dev, SI4126_POWERDOWN,
 665                                               SI4126_POWERDOWN_PDIB |
 666                                               SI4126_POWERDOWN_PDRB);
 667                 adm8211_rf_write_syn_rfmd2948(dev, SI4126_PHASE_DET_GAIN, 0);
 668                 adm8211_rf_write_syn_rfmd2948(dev, SI4126_RF2_N_DIV,
 669                                               (chan == 14 ?
 670                                                2110 : (2033 + (chan * 5))));
 671                 adm8211_rf_write_syn_rfmd2948(dev, SI4126_IF_N_DIV, 1496);
 672                 adm8211_rf_write_syn_rfmd2948(dev, SI4126_RF2_R_DIV, 44);
 673                 adm8211_rf_write_syn_rfmd2948(dev, SI4126_IF_R_DIV, 44);
 674                 break;
 675
 676         case ADM8211_MAX2820:
 677                 adm8211_rf_write_syn_max2820(dev, 0x3,
 678                         (chan == 14 ? 0x054 : (0x7 + (chan * 5))));
 679                 break;
 680
 681         case ADM8211_AL2210L:
 682                 adm8211_rf_write_syn_al2210l(dev, 0x0,
 683                         (chan == 14 ? 0x229B4 : (0x22967 + (chan * 5))));
 684                 break;
 685
 686         default:
 687                 printk(KERN_DEBUG "%s: unsupported transceiver type %d\n",
 688                        wiphy_name(dev->wiphy), priv->transceiver_type);
 689                 break;
 690         }
 691
 692         /* write BBP regs */
 693         if (priv->bbp_type == ADM8211_TYPE_RFMD) {
 694
 695         /* SMC 2635W specific? adm8211b doesn't use the 2948 though.. */
 696         /* TODO: remove if SMC 2635W doesn't need this */
 697         if (priv->transceiver_type == ADM8211_RFMD2948) {
 698                 reg = ADM8211_CSR_READ(GPIO);
 699                 reg &= 0xfffc0000;
 700                 reg |= ADM8211_CSR_GPIO_EN0;
 701                 if (chan != 14)
 702                         reg |= ADM8211_CSR_GPIO_O0;
 703                 ADM8211_CSR_WRITE(GPIO, reg);
 704         }
 705
 706         if (priv->transceiver_type == ADM8211_RFMD2958) {
 707                 /* set PCNT2 */
 708                 adm8211_rf_write_syn_rfmd2958(dev, 0x0B, 0x07100);
 709                 /* set PCNT1 P_DESIRED/MID_BIAS */
 710                 reg = le16_to_cpu(priv->eeprom->cr49);
 711                 reg >>= 13;
 712                 reg <<= 15;
 713                 reg |= ant_power << 9;
 714                 adm8211_rf_write_syn_rfmd2958(dev, 0x0A, reg);
 715                 /* set TXRX TX_GAIN */
 716                 adm8211_rf_write_syn_rfmd2958(dev, 0x09, 0x00050 |
 717                         (priv->revid < ADM8211_REV_CA ? tx_power : 0));
 718         } else {
 719                 reg = ADM8211_CSR_READ(PLCPHD);
 720                 reg &= 0xff00ffff;
 721                 reg |= tx_power << 18;
 722                 ADM8211_CSR_WRITE(PLCPHD, reg);
 723         }
 724
 725         ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_SELRF |
 726                           ADM8211_SYNRF_PE1 | ADM8211_SYNRF_PHYRST);
 727         ADM8211_CSR_READ(SYNRF);
 728         msleep(30);
 729
 730         /* RF3000 BBP */
 731         if (priv->transceiver_type != ADM8211_RFMD2958)
 732                 adm8211_write_bbp(dev, RF3000_TX_VAR_GAIN__TX_LEN_EXT,
 733                                   tx_power<<2);
 734         adm8211_write_bbp(dev, RF3000_LOW_GAIN_CALIB, lpf_cutoff);
 735         adm8211_write_bbp(dev, RF3000_HIGH_GAIN_CALIB, lnags_thresh);
 736         adm8211_write_bbp(dev, 0x1c, priv->revid == ADM8211_REV_BA ?
 737                                      priv->eeprom->cr28 : 0);
 738         adm8211_write_bbp(dev, 0x1d, priv->eeprom->cr29);
 739
 740         ADM8211_CSR_WRITE(SYNRF, 0);
 741
 742         /* Nothing to do for ADMtek BBP */
 743         } else if (priv->bbp_type != ADM8211_TYPE_ADMTEK)
 744                 printk(KERN_DEBUG "%s: unsupported BBP type %d\n",
 745                        wiphy_name(dev->wiphy), priv->bbp_type);
 746
 747         ADM8211_RESTORE();
 748
 749         /* update current channel for adhoc (and maybe AP mode) */
 750         reg = ADM8211_CSR_READ(CAP0);
 751         reg &= ~0xF;
 752         reg |= chan;
 753         ADM8211_CSR_WRITE(CAP0, reg);
 754
 755         return 0;
 756 }
 757
 758 static void adm8211_update_mode(struct ieee80211_hw *dev)
 759 {
 760         struct adm8211_priv *priv = dev->priv;
 761
 762         ADM8211_IDLE();
 763
 764         priv->soft_rx_crc = 0;
 765         switch (priv->mode) {
 766         case IEEE80211_IF_TYPE_STA:
 767                 priv->nar &= ~(ADM8211_NAR_PR | ADM8211_NAR_EA);
 768                 priv->nar |= ADM8211_NAR_ST | ADM8211_NAR_SR;
 769                 break;
 770         case IEEE80211_IF_TYPE_IBSS:
 771                 priv->nar &= ~ADM8211_NAR_PR;
 772                 priv->nar |= ADM8211_NAR_EA | ADM8211_NAR_ST | ADM8211_NAR_SR;
 773
 774                 /* don't trust the error bits on rev 0x20 and up in adhoc */
 775                 if (priv->revid >= ADM8211_REV_BA)
 776                         priv->soft_rx_crc = 1;
 777                 break;
 778         case IEEE80211_IF_TYPE_MNTR:
 779                 priv->nar &= ~(ADM8211_NAR_EA | ADM8211_NAR_ST);
 780                 priv->nar |= ADM8211_NAR_PR | ADM8211_NAR_SR;
 781                 break;
 782         }
 783
 784         ADM8211_RESTORE();
 785 }
 786
 787 static void adm8211_hw_init_syn(struct ieee80211_hw *dev)
 788 {
 789         struct adm8211_priv *priv = dev->priv;
 790
 791         switch (priv->transceiver_type) {
 792         case ADM8211_RFMD2958:
 793         case ADM8211_RFMD2958_RF3000_CONTROL_POWER:
 794                 /* comments taken from ADMtek vendor driver */
 795
 796                 /* Reset RF2958 after power on */
 797                 adm8211_rf_write_syn_rfmd2958(dev, 0x1F, 0x00000);
 798                 /* Initialize RF VCO Core Bias to maximum */
 799                 adm8211_rf_write_syn_rfmd2958(dev, 0x0C, 0x3001F);
 800                 /* Initialize IF PLL */
 801                 adm8211_rf_write_syn_rfmd2958(dev, 0x01, 0x29C03);
 802                 /* Initialize IF PLL Coarse Tuning */
 803                 adm8211_rf_write_syn_rfmd2958(dev, 0x03, 0x1FF6F);
 804                 /* Initialize RF PLL */
 805                 adm8211_rf_write_syn_rfmd2958(dev, 0x04, 0x29403);
 806                 /* Initialize RF PLL Coarse Tuning */
 807                 adm8211_rf_write_syn_rfmd2958(dev, 0x07, 0x1456F);
 808                 /* Initialize TX gain and filter BW (R9) */
 809                 adm8211_rf_write_syn_rfmd2958(dev, 0x09,
 810                         (priv->transceiver_type == ADM8211_RFMD2958 ?
 811                          0x10050 : 0x00050));
 812                 /* Initialize CAL register */
 813                 adm8211_rf_write_syn_rfmd2958(dev, 0x08, 0x3FFF8);
 814                 break;
 815
 816         case ADM8211_MAX2820:
 817                 adm8211_rf_write_syn_max2820(dev, 0x1, 0x01E);
 818                 adm8211_rf_write_syn_max2820(dev, 0x2, 0x001);
 819                 adm8211_rf_write_syn_max2820(dev, 0x3, 0x054);
 820                 adm8211_rf_write_syn_max2820(dev, 0x4, 0x310);
 821                 adm8211_rf_write_syn_max2820(dev, 0x5, 0x000);
 822                 break;
 823
 824         case ADM8211_AL2210L:
 825                 adm8211_rf_write_syn_al2210l(dev, 0x0, 0x0196C);
 826                 adm8211_rf_write_syn_al2210l(dev, 0x1, 0x007CB);
 827                 adm8211_rf_write_syn_al2210l(dev, 0x2, 0x3582F);
 828                 adm8211_rf_write_syn_al2210l(dev, 0x3, 0x010A9);
 829                 adm8211_rf_write_syn_al2210l(dev, 0x4, 0x77280);
 830                 adm8211_rf_write_syn_al2210l(dev, 0x5, 0x45641);
 831                 adm8211_rf_write_syn_al2210l(dev, 0x6, 0xEA130);
 832                 adm8211_rf_write_syn_al2210l(dev, 0x7, 0x80000);
 833                 adm8211_rf_write_syn_al2210l(dev, 0x8, 0x7850F);
 834                 adm8211_rf_write_syn_al2210l(dev, 0x9, 0xF900C);
 835                 adm8211_rf_write_syn_al2210l(dev, 0xA, 0x00000);
 836                 adm8211_rf_write_syn_al2210l(dev, 0xB, 0x00000);
 837                 break;
 838
 839         case ADM8211_RFMD2948:
 840         default:
 841                 break;
 842         }
 843 }
 844
 845 static int adm8211_hw_init_bbp(struct ieee80211_hw *dev)
 846 {
 847         struct adm8211_priv *priv = dev->priv;
 848         u32 reg;
 849
 850         /* write addresses */
 851         if (priv->bbp_type == ADM8211_TYPE_INTERSIL) {
 852                 ADM8211_CSR_WRITE(MMIWA,  0x100E0C0A);
 853                 ADM8211_CSR_WRITE(MMIRD0, 0x00007C7E);
 854                 ADM8211_CSR_WRITE(MMIRD1, 0x00100000);
 855         } else if (priv->bbp_type == ADM8211_TYPE_RFMD ||
 856                    priv->bbp_type == ADM8211_TYPE_ADMTEK) {
 857                 /* check specific BBP type */
 858                 switch (priv->specific_bbptype) {
 859                 case ADM8211_BBP_RFMD3000:
 860                 case ADM8211_BBP_RFMD3002:
 861                         ADM8211_CSR_WRITE(MMIWA,  0x00009101);
 862                         ADM8211_CSR_WRITE(MMIRD0, 0x00000301);
 863                         break;
 864
 865                 case ADM8211_BBP_ADM8011:
 866                         ADM8211_CSR_WRITE(MMIWA,  0x00008903);
 867                         ADM8211_CSR_WRITE(MMIRD0, 0x00001716);
 868
 869                         reg = ADM8211_CSR_READ(BBPCTL);
 870                         reg &= ~ADM8211_BBPCTL_TYPE;
 871                         reg |= 0x5 << 18;
 872                         ADM8211_CSR_WRITE(BBPCTL, reg);
 873                         break;
 874                 }
 875
 876                 switch (priv->revid) {
 877                 case ADM8211_REV_CA:
 878                         if (priv->transceiver_type == ADM8211_RFMD2958 ||
 879                             priv->transceiver_type == ADM8211_RFMD2958_RF3000_CONTROL_POWER ||
 880                             priv->transceiver_type == ADM8211_RFMD2948)
 881                                 ADM8211_CSR_WRITE(SYNCTL, 0x1 << 22);
 882                         else if (priv->transceiver_type == ADM8211_MAX2820 ||
 883                                  priv->transceiver_type == ADM8211_AL2210L)
 884                                 ADM8211_CSR_WRITE(SYNCTL, 0x3 << 22);
 885                         break;
 886
 887                 case ADM8211_REV_BA:
 888                         reg  = ADM8211_CSR_READ(MMIRD1);
 889                         reg &= 0x0000FFFF;
 890                         reg |= 0x7e100000;
 891                         ADM8211_CSR_WRITE(MMIRD1, reg);
 892                         break;
 893
 894                 case ADM8211_REV_AB:
 895                 case ADM8211_REV_AF:
 896                 default:
 897                         ADM8211_CSR_WRITE(MMIRD1, 0x7e100000);
 898                         break;
 899                 }
 900
 901                 /* For RFMD */
 902                 ADM8211_CSR_WRITE(MACTEST, 0x800);
 903         }
 904
 905         adm8211_hw_init_syn(dev);
 906
 907         /* Set RF Power control IF pin to PE1+PHYRST# */
 908         ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_SELRF |
 909                           ADM8211_SYNRF_PE1 | ADM8211_SYNRF_PHYRST);
 910         ADM8211_CSR_READ(SYNRF);
 911         msleep(20);
 912
 913         /* write BBP regs */
 914         if (priv->bbp_type == ADM8211_TYPE_RFMD) {
 915                 /* RF3000 BBP */
 916                 /* another set:
 917                  * 11: c8
 918                  * 14: 14
 919                  * 15: 50 (chan 1..13; chan 14: d0)
 920                  * 1c: 00
 921                  * 1d: 84
 922                  */
 923                 adm8211_write_bbp(dev, RF3000_CCA_CTRL, 0x80);
 924                 /* antenna selection: diversity */
 925                 adm8211_write_bbp(dev, RF3000_DIVERSITY__RSSI, 0x80);
 926                 adm8211_write_bbp(dev, RF3000_TX_VAR_GAIN__TX_LEN_EXT, 0x74);
 927                 adm8211_write_bbp(dev, RF3000_LOW_GAIN_CALIB, 0x38);
 928                 adm8211_write_bbp(dev, RF3000_HIGH_GAIN_CALIB, 0x40);
 929
 930                 if (priv->eeprom->major_version < 2) {
 931                         adm8211_write_bbp(dev, 0x1c, 0x00);
 932                         adm8211_write_bbp(dev, 0x1d, 0x80);
 933                 } else {
 934                         if (priv->revid == ADM8211_REV_BA)
 935                                 adm8211_write_bbp(dev, 0x1c, priv->eeprom->cr28);
 936                         else
 937                                 adm8211_write_bbp(dev, 0x1c, 0x00);
 938
 939                         adm8211_write_bbp(dev, 0x1d, priv->eeprom->cr29);
 940                 }
 941         } else if (priv->bbp_type == ADM8211_TYPE_ADMTEK) {
 942                 /* reset baseband */
 943                 adm8211_write_bbp(dev, 0x00, 0xFF);
 944                 /* antenna selection: diversity */
 945                 adm8211_write_bbp(dev, 0x07, 0x0A);
 946
 947                 /* TODO: find documentation for this */
 948                 switch (priv->transceiver_type) {
 949                 case ADM8211_RFMD2958:
 950                 case ADM8211_RFMD2958_RF3000_CONTROL_POWER:
 951                         adm8211_write_bbp(dev, 0x00, 0x00);
 952                         adm8211_write_bbp(dev, 0x01, 0x00);
 953                         adm8211_write_bbp(dev, 0x02, 0x00);
 954                         adm8211_write_bbp(dev, 0x03, 0x00);
 955                         adm8211_write_bbp(dev, 0x06, 0x0f);
 956                         adm8211_write_bbp(dev, 0x09, 0x00);
 957                         adm8211_write_bbp(dev, 0x0a, 0x00);
 958                         adm8211_write_bbp(dev, 0x0b, 0x00);
 959                         adm8211_write_bbp(dev, 0x0c, 0x00);
 960                         adm8211_write_bbp(dev, 0x0f, 0xAA);
 961                         adm8211_write_bbp(dev, 0x10, 0x8c);
 962                         adm8211_write_bbp(dev, 0x11, 0x43);
 963                         adm8211_write_bbp(dev, 0x18, 0x40);
 964                         adm8211_write_bbp(dev, 0x20, 0x23);
 965                         adm8211_write_bbp(dev, 0x21, 0x02);
 966                         adm8211_write_bbp(dev, 0x22, 0x28);
 967                         adm8211_write_bbp(dev, 0x23, 0x30);
 968                         adm8211_write_bbp(dev, 0x24, 0x2d);
 969                         adm8211_write_bbp(dev, 0x28, 0x35);
 970                         adm8211_write_bbp(dev, 0x2a, 0x8c);
 971                         adm8211_write_bbp(dev, 0x2b, 0x81);
 972                         adm8211_write_bbp(dev, 0x2c, 0x44);
 973                         adm8211_write_bbp(dev, 0x2d, 0x0A);
 974                         adm8211_write_bbp(dev, 0x29, 0x40);
 975                         adm8211_write_bbp(dev, 0x60, 0x08);
 976                         adm8211_write_bbp(dev, 0x64, 0x01);
 977                         break;
 978
 979                 case ADM8211_MAX2820:
 980                         adm8211_write_bbp(dev, 0x00, 0x00);
 981                         adm8211_write_bbp(dev, 0x01, 0x00);
 982                         adm8211_write_bbp(dev, 0x02, 0x00);
 983                         adm8211_write_bbp(dev, 0x03, 0x00);
 984                         adm8211_write_bbp(dev, 0x06, 0x0f);
 985                         adm8211_write_bbp(dev, 0x09, 0x05);
 986                         adm8211_write_bbp(dev, 0x0a, 0x02);
 987                         adm8211_write_bbp(dev, 0x0b, 0x00);
 988                         adm8211_write_bbp(dev, 0x0c, 0x0f);
 989                         adm8211_write_bbp(dev, 0x0f, 0x55);
 990                         adm8211_write_bbp(dev, 0x10, 0x8d);
 991                         adm8211_write_bbp(dev, 0x11, 0x43);
 992                         adm8211_write_bbp(dev, 0x18, 0x4a);
 993                         adm8211_write_bbp(dev, 0x20, 0x20);
 994                         adm8211_write_bbp(dev, 0x21, 0x02);
 995                         adm8211_write_bbp(dev, 0x22, 0x23);
 996                         adm8211_write_bbp(dev, 0x23, 0x30);
 997                         adm8211_write_bbp(dev, 0x24, 0x2d);
 998                         adm8211_write_bbp(dev, 0x2a, 0x8c);
 999                         adm8211_write_bbp(dev, 0x2b, 0x81);
1000                         adm8211_write_bbp(dev, 0x2c, 0x44);
1001                         adm8211_write_bbp(dev, 0x29, 0x4a);
1002                         adm8211_write_bbp(dev, 0x60, 0x2b);
1003                         adm8211_write_bbp(dev, 0x64, 0x01);
1004                         break;
1005
1006                 case ADM8211_AL2210L:
1007                         adm8211_write_bbp(dev, 0x00, 0x00);
1008                         adm8211_write_bbp(dev, 0x01, 0x00);
1009                         adm8211_write_bbp(dev, 0x02, 0x00);
1010                         adm8211_write_bbp(dev, 0x03, 0x00);
1011                         adm8211_write_bbp(dev, 0x06, 0x0f);
1012                         adm8211_write_bbp(dev, 0x07, 0x05);
1013                         adm8211_write_bbp(dev, 0x08, 0x03);
1014                         adm8211_write_bbp(dev, 0x09, 0x00);
1015                         adm8211_write_bbp(dev, 0x0a, 0x00);
1016                         adm8211_write_bbp(dev, 0x0b, 0x00);
1017                         adm8211_write_bbp(dev, 0x0c, 0x10);
1018                         adm8211_write_bbp(dev, 0x0f, 0x55);
1019                         adm8211_write_bbp(dev, 0x10, 0x8d);
1020                         adm8211_write_bbp(dev, 0x11, 0x43);
1021                         adm8211_write_bbp(dev, 0x18, 0x4a);
1022                         adm8211_write_bbp(dev, 0x20, 0x20);
1023                         adm8211_write_bbp(dev, 0x21, 0x02);
1024                         adm8211_write_bbp(dev, 0x22, 0x23);
1025                         adm8211_write_bbp(dev, 0x23, 0x30);
1026                         adm8211_write_bbp(dev, 0x24, 0x2d);
1027                         adm8211_write_bbp(dev, 0x2a, 0xaa);
1028                         adm8211_write_bbp(dev, 0x2b, 0x81);
1029                         adm8211_write_bbp(dev, 0x2c, 0x44);
1030                         adm8211_write_bbp(dev, 0x29, 0xfa);
1031                         adm8211_write_bbp(dev, 0x60, 0x2d);
1032                         adm8211_write_bbp(dev, 0x64, 0x01);
1033                         break;
1034
1035                 case ADM8211_RFMD2948:
1036                         break;
1037
1038                 default:
1039                         printk(KERN_DEBUG "%s: unsupported transceiver %d\n",
1040                                wiphy_name(dev->wiphy), priv->transceiver_type);
1041                         break;
1042                 }
1043         } else
1044                 printk(KERN_DEBUG "%s: unsupported BBP %d\n",
1045                        wiphy_name(dev->wiphy), priv->bbp_type);
1046
1047         ADM8211_CSR_WRITE(SYNRF, 0);
1048
1049         /* Set RF CAL control source to MAC control */
1050         reg = ADM8211_CSR_READ(SYNCTL);
1051         reg |= ADM8211_SYNCTL_SELCAL;
1052         ADM8211_CSR_WRITE(SYNCTL, reg);
1053
1054         return 0;
1055 }
1056
1057 /* configures hw beacons/probe responses */
1058 static int adm8211_set_rate(struct ieee80211_hw *dev)
1059 {
1060         struct adm8211_priv *priv = dev->priv;
1061         u32 reg;
1062         int i = 0;
1063         u8 rate_buf[12] = {0};
1064
1065         /* write supported rates */
1066         if (priv->revid != ADM8211_REV_BA) {
1067                 rate_buf[0] = ARRAY_SIZE(adm8211_rates);
1068                 for (i = 0; i < ARRAY_SIZE(adm8211_rates); i++)
1069                         rate_buf[i + 1] = (adm8211_rates[i].rate / 5) | 0x80;
1070         } else {
1071                 /* workaround for rev BA specific bug */
1072                 rate_buf[0] = 0x04;
1073                 rate_buf[1] = 0x82;
1074                 rate_buf[2] = 0x04;
1075                 rate_buf[3] = 0x0b;
1076                 rate_buf[4] = 0x16;
1077         }
1078
1079         adm8211_write_sram_bytes(dev, ADM8211_SRAM_SUPP_RATE, rate_buf,
1080                                  ARRAY_SIZE(adm8211_rates) + 1);
1081
1082         reg = ADM8211_CSR_READ(PLCPHD) & 0x00FFFFFF; /* keep bits 0-23 */
1083         reg |= 1 << 15; /* short preamble */
1084         reg |= 110 << 24;
1085         ADM8211_CSR_WRITE(PLCPHD, reg);
1086
1087         /* MTMLT   = 512 TU (max TX MSDU lifetime)
1088          * BCNTSIG = plcp_signal (beacon, probe resp, and atim TX rate)
1089          * SRTYLIM = 224 (short retry limit, TX header value is default) */
1090         ADM8211_CSR_WRITE(TXLMT, (512 << 16) | (110 << 8) | (224 << 0));
1091
1092         return 0;
1093 }
1094
1095 static void adm8211_hw_init(struct ieee80211_hw *dev)
1096 {
1097         struct adm8211_priv *priv = dev->priv;
1098         u32 reg;
1099         u8 cline;
1100
1101         reg = le32_to_cpu(ADM8211_CSR_READ(PAR));
1102         reg |= ADM8211_PAR_MRLE | ADM8211_PAR_MRME;
1103         reg &= ~(ADM8211_PAR_BAR | ADM8211_PAR_CAL);
1104
1105         if (!pci_set_mwi(priv->pdev)) {
1106                 reg |= 0x1 << 24;
1107                 pci_read_config_byte(priv->pdev, PCI_CACHE_LINE_SIZE, &cline);
1108
1109                 switch (cline) {
1110                 case  0x8: reg |= (0x1 << 14);
1111                            break;
1112                 case 0x16: reg |= (0x2 << 14);
1113                            break;
1114                 case 0x32: reg |= (0x3 << 14);
1115                            break;
1116                   default: reg |= (0x0 << 14);
1117                            break;
1118                 }
1119         }
1120
1121         ADM8211_CSR_WRITE(PAR, reg);
1122
1123         reg = ADM8211_CSR_READ(CSR_TEST1);
1124         reg &= ~(0xF << 28);
1125         reg |= (1 << 28) | (1 << 31);
1126         ADM8211_CSR_WRITE(CSR_TEST1, reg);
1127
1128         /* lose link after 4 lost beacons */
1129         reg = (0x04 << 21) | ADM8211_WCSR_TSFTWE | ADM8211_WCSR_LSOE;
1130         ADM8211_CSR_WRITE(WCSR, reg);
1131
1132         /* Disable APM, enable receive FIFO threshold, and set drain receive
1133          * threshold to store-and-forward */
1134         reg = ADM8211_CSR_READ(CMDR);
1135         reg &= ~(ADM8211_CMDR_APM | ADM8211_CMDR_DRT);
1136         reg |= ADM8211_CMDR_RTE | ADM8211_CMDR_DRT_SF;
1137         ADM8211_CSR_WRITE(CMDR, reg);
1138
1139         adm8211_set_rate(dev);
1140
1141         /* 4-bit values:
1142          * PWR1UP   = 8 * 2 ms
1143          * PWR0PAPE = 8 us or 5 us
1144          * PWR1PAPE = 1 us or 3 us
1145          * PWR0TRSW = 5 us
1146          * PWR1TRSW = 12 us
1147          * PWR0PE2  = 13 us
1148          * PWR1PE2  = 1 us
1149          * PWR0TXPE = 8 or 6 */
1150         if (priv->revid < ADM8211_REV_CA)
1151                 ADM8211_CSR_WRITE(TOFS2, 0x8815cd18);
1152         else
1153                 ADM8211_CSR_WRITE(TOFS2, 0x8535cd16);
1154
1155         /* Enable store and forward for transmit */
1156         priv->nar = ADM8211_NAR_SF | ADM8211_NAR_PB;
1157         ADM8211_CSR_WRITE(NAR, priv->nar);
1158
1159         /* Reset RF */
1160         ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_RADIO);
1161         ADM8211_CSR_READ(SYNRF);
1162         msleep(10);
1163         ADM8211_CSR_WRITE(SYNRF, 0);
1164         ADM8211_CSR_READ(SYNRF);
1165         msleep(5);
1166
1167         /* Set CFP Max Duration to 0x10 TU */
1168         reg = ADM8211_CSR_READ(CFPP);
1169         reg &= ~(0xffff << 8);
1170         reg |= 0x0010 << 8;
1171         ADM8211_CSR_WRITE(CFPP, reg);
1172
1173         /* USCNT = 0x16 (number of system clocks, 22 MHz, in 1us
1174          * TUCNT = 0x3ff - Tu counter 1024 us  */
1175         ADM8211_CSR_WRITE(TOFS0, (0x16 << 24) | 0x3ff);
1176
1177         /* SLOT=20 us, SIFS=110 cycles of 22 MHz (5 us),
1178          * DIFS=50 us, EIFS=100 us */
1179         if (priv->revid < ADM8211_REV_CA)
1180                 ADM8211_CSR_WRITE(IFST, (20 << 23) | (110 << 15) |
1181                                         (50 << 9)  | 100);
1182         else
1183                 ADM8211_CSR_WRITE(IFST, (20 << 23) | (24 << 15) |
1184                                         (50 << 9)  | 100);
1185
1186         /* PCNT = 1 (MAC idle time awake/sleep, unit S)
1187          * RMRD = 2346 * 8 + 1 us (max RX duration)  */
1188         ADM8211_CSR_WRITE(RMD, (1 << 16) | 18769);
1189
1190         /* MART=65535 us, MIRT=256 us, TSFTOFST=0 us */
1191         ADM8211_CSR_WRITE(RSPT, 0xffffff00);
1192
1193         /* Initialize BBP (and SYN) */
1194         adm8211_hw_init_bbp(dev);
1195
1196         /* make sure interrupts are off */
1197         ADM8211_CSR_WRITE(IER, 0);
1198
1199         /* ACK interrupts */
1200         ADM8211_CSR_WRITE(STSR, ADM8211_CSR_READ(STSR));
1201
1202         /* Setup WEP (turns it off for now) */
1203         reg = ADM8211_CSR_READ(MACTEST);
1204         reg &= ~(7 << 20);
1205         ADM8211_CSR_WRITE(MACTEST, reg);
1206
1207         reg = ADM8211_CSR_READ(WEPCTL);
1208         reg &= ~ADM8211_WEPCTL_WEPENABLE;
1209         reg |= ADM8211_WEPCTL_WEPRXBYP;
1210         ADM8211_CSR_WRITE(WEPCTL, reg);
1211
1212         /* Clear the missed-packet counter. */
1213         ADM8211_CSR_READ(LPC);
1214 }
1215
1216 static int adm8211_hw_reset(struct ieee80211_hw *dev)
1217 {
1218         struct adm8211_priv *priv = dev->priv;
1219         u32 reg, tmp;
1220         int timeout = 100;
1221
1222         /* Power-on issue */
1223         /* TODO: check if this is necessary */
1224         ADM8211_CSR_WRITE(FRCTL, 0);
1225
1226         /* Reset the chip */
1227         tmp = ADM8211_CSR_READ(PAR);
1228         ADM8211_CSR_WRITE(PAR, ADM8211_PAR_SWR);
1229
1230         while ((ADM8211_CSR_READ(PAR) & ADM8211_PAR_SWR) && timeout--)
1231                 msleep(50);
1232
1233         if (timeout <= 0)
1234                 return -ETIMEDOUT;
1235
1236         ADM8211_CSR_WRITE(PAR, tmp);
1237
1238         if (priv->revid == ADM8211_REV_BA &&
1239             (priv->transceiver_type == ADM8211_RFMD2958_RF3000_CONTROL_POWER ||
1240              priv->transceiver_type == ADM8211_RFMD2958)) {
1241                 reg = ADM8211_CSR_READ(CSR_TEST1);
1242                 reg |= (1 << 4) | (1 << 5);
1243                 ADM8211_CSR_WRITE(CSR_TEST1, reg);
1244         } else if (priv->revid == ADM8211_REV_CA) {
1245                 reg = ADM8211_CSR_READ(CSR_TEST1);
1246                 reg &= ~((1 << 4) | (1 << 5));
1247                 ADM8211_CSR_WRITE(CSR_TEST1, reg);
1248         }
1249
1250         ADM8211_CSR_WRITE(FRCTL, 0);
1251
1252         reg = ADM8211_CSR_READ(CSR_TEST0);
1253         reg |= ADM8211_CSR_TEST0_EPRLD; /* EEPROM Recall */
1254         ADM8211_CSR_WRITE(CSR_TEST0, reg);
1255
1256         adm8211_clear_sram(dev);
1257
1258         return 0;
1259 }
1260
1261 static u64 adm8211_get_tsft(struct ieee80211_hw *dev)
1262 {
1263         struct adm8211_priv *priv = dev->priv;
1264         u32 tsftl;
1265         u64 tsft;
1266
1267         tsftl = ADM8211_CSR_READ(TSFTL);
1268         tsft = ADM8211_CSR_READ(TSFTH);
1269         tsft <<= 32;
1270         tsft |= tsftl;
1271
1272         return tsft;
1273 }
1274
1275 static void adm8211_set_interval(struct ieee80211_hw *dev,
1276                                  unsigned short bi, unsigned short li)
1277 {
1278         struct adm8211_priv *priv = dev->priv;
1279         u32 reg;
1280
1281         /* BP (beacon interval) = data->beacon_interval
1282          * LI (listen interval) = data->listen_interval (in beacon intervals) */
1283         reg = (bi << 16) | li;
1284         ADM8211_CSR_WRITE(BPLI, reg);
1285 }
1286
1287 static void adm8211_set_bssid(struct ieee80211_hw *dev, const u8 *bssid)
1288 {
1289         struct adm8211_priv *priv = dev->priv;
1290         u32 reg;
1291
1292         reg = bssid[0] | (bssid[1] << 8) | (bssid[2] << 16) | (bssid[3] << 24);
1293         ADM8211_CSR_WRITE(BSSID0, reg);
1294         reg = ADM8211_CSR_READ(ABDA1);
1295         reg &= 0x0000ffff;
1296         reg |= (bssid[4] << 16) | (bssid[5] << 24);
1297         ADM8211_CSR_WRITE(ABDA1, reg);
1298 }
1299
1300 static int adm8211_set_ssid(struct ieee80211_hw *dev, u8 *ssid, size_t ssid_len)
1301 {
1302         struct adm8211_priv *priv = dev->priv;
1303         u8 buf[36];
1304
1305         if (ssid_len > 32)
1306                 return -EINVAL;
1307
1308         memset(buf, 0, sizeof(buf));
1309         buf[0] = ssid_len;
1310         memcpy(buf + 1, ssid, ssid_len);
1311         adm8211_write_sram_bytes(dev, ADM8211_SRAM_SSID, buf, 33);
1312         /* TODO: configure beacon for adhoc? */
1313         return 0;
1314 }
1315
1316 static int adm8211_config(struct ieee80211_hw *dev, struct ieee80211_conf *conf)
1317 {
1318         struct adm8211_priv *priv = dev->priv;
1319
1320         if (conf->channel != priv->channel) {
1321                 priv->channel = conf->channel;
1322                 adm8211_rf_set_channel(dev, priv->channel);
1323         }
1324
1325         return 0;
1326 }
1327
1328 static int adm8211_config_interface(struct ieee80211_hw *dev, int if_id,
1329                                     struct ieee80211_if_conf *conf)
1330 {
1331         struct adm8211_priv *priv = dev->priv;
1332
1333         if (memcmp(conf->bssid, priv->bssid, ETH_ALEN)) {
1334                 adm8211_set_bssid(dev, conf->bssid);
1335                 memcpy(priv->bssid, conf->bssid, ETH_ALEN);
1336         }
1337
1338         if (conf->ssid_len != priv->ssid_len ||
1339             memcmp(conf->ssid, priv->ssid, conf->ssid_len)) {
1340                 adm8211_set_ssid(dev, conf->ssid, conf->ssid_len);
1341                 priv->ssid_len = conf->ssid_len;
1342                 memcpy(priv->ssid, conf->ssid, conf->ssid_len);
1343         }
1344
1345         return 0;
1346 }
1347
1348 static void adm8211_configure_filter(struct ieee80211_hw *dev,
1349                                      unsigned int changed_flags,
1350                                      unsigned int *total_flags,
1351                                      int mc_count, struct dev_mc_list *mclist)
1352 {
1353         static const u8 bcast[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
1354         struct adm8211_priv *priv = dev->priv;
1355         unsigned int bit_nr, new_flags;
1356         u32 mc_filter[2];
1357         int i;
1358
1359         new_flags = 0;
1360
1361         if (*total_flags & FIF_PROMISC_IN_BSS) {
1362                 new_flags |= FIF_PROMISC_IN_BSS;
1363                 priv->nar |= ADM8211_NAR_PR;
1364                 priv->nar &= ~ADM8211_NAR_MM;
1365                 mc_filter[1] = mc_filter[0] = ~0;
1366         } else if ((*total_flags & FIF_ALLMULTI) || (mc_count > 32)) {
1367                 new_flags |= FIF_ALLMULTI;
1368                 priv->nar &= ~ADM8211_NAR_PR;
1369                 priv->nar |= ADM8211_NAR_MM;
1370                 mc_filter[1] = mc_filter[0] = ~0;
1371         } else {
1372                 priv->nar &= ~(ADM8211_NAR_MM | ADM8211_NAR_PR);
1373                 mc_filter[1] = mc_filter[0] = 0;
1374                 for (i = 0; i < mc_count; i++) {
1375                         if (!mclist)
1376                                 break;
1377                         bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
1378
1379                         bit_nr &= 0x3F;
1380                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
1381                         mclist = mclist->next;
1382                 }
1383         }
1384
1385         ADM8211_IDLE_RX();
1386
1387         ADM8211_CSR_WRITE(MAR0, mc_filter[0]);
1388         ADM8211_CSR_WRITE(MAR1, mc_filter[1]);
1389         ADM8211_CSR_READ(NAR);
1390
1391         if (priv->nar & ADM8211_NAR_PR)
1392                 dev->flags |= IEEE80211_HW_RX_INCLUDES_FCS;
1393         else
1394                 dev->flags &= ~IEEE80211_HW_RX_INCLUDES_FCS;
1395
1396         if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
1397                 adm8211_set_bssid(dev, bcast);
1398         else
1399                 adm8211_set_bssid(dev, priv->bssid);
1400
1401         ADM8211_RESTORE();
1402
1403         *total_flags = new_flags;
1404 }
1405
1406 static int adm8211_add_interface(struct ieee80211_hw *dev,
1407                                  struct ieee80211_if_init_conf *conf)
1408 {
1409         struct adm8211_priv *priv = dev->priv;
1410         if (priv->mode != IEEE80211_IF_TYPE_MNTR)
1411                 return -EOPNOTSUPP;
1412
1413         switch (conf->type) {
1414         case IEEE80211_IF_TYPE_STA:
1415                 priv->mode = conf->type;
1416                 break;
1417         default:
1418                 return -EOPNOTSUPP;
1419         }
1420
1421         ADM8211_IDLE();
1422
1423         ADM8211_CSR_WRITE(PAR0, *(u32 *)conf->mac_addr);
1424         ADM8211_CSR_WRITE(PAR1, *(u16 *)(conf->mac_addr + 4));
1425
1426         adm8211_update_mode(dev);
1427
1428         ADM8211_RESTORE();
1429
1430         return 0;
1431 }
1432
1433 static void adm8211_remove_interface(struct ieee80211_hw *dev,
1434                                      struct ieee80211_if_init_conf *conf)
1435 {
1436         struct adm8211_priv *priv = dev->priv;
1437         priv->mode = IEEE80211_IF_TYPE_MNTR;
1438 }
1439
1440 static int adm8211_init_rings(struct ieee80211_hw *dev)
1441 {
1442         struct adm8211_priv *priv = dev->priv;
1443         struct adm8211_desc *desc = NULL;
1444         struct adm8211_rx_ring_info *rx_info;
1445         struct adm8211_tx_ring_info *tx_info;
1446         unsigned int i;
1447
1448         for (i = 0; i < priv->rx_ring_size; i++) {
1449                 desc = &priv->rx_ring[i];
1450                 desc->status = 0;
1451                 desc->length = cpu_to_le32(RX_PKT_SIZE);
1452                 priv->rx_buffers[i].skb = NULL;
1453         }
1454         /* Mark the end of RX ring; hw returns to base address after this
1455          * descriptor */
1456         desc->length |= cpu_to_le32(RDES1_CONTROL_RER);
1457
1458         for (i = 0; i < priv->rx_ring_size; i++) {
1459                 desc = &priv->rx_ring[i];
1460                 rx_info = &priv->rx_buffers[i];
1461
1462                 rx_info->skb = dev_alloc_skb(RX_PKT_SIZE);
1463                 if (rx_info->skb == NULL)
1464                         break;
1465                 rx_info->mapping = pci_map_single(priv->pdev,
1466                                                   skb_tail_pointer(rx_info->skb),
1467                                                   RX_PKT_SIZE,
1468                                                   PCI_DMA_FROMDEVICE);
1469                 desc->buffer1 = cpu_to_le32(rx_info->mapping);
1470                 desc->status = cpu_to_le32(RDES0_STATUS_OWN | RDES0_STATUS_SQL);
1471         }
1472
1473         /* Setup TX ring. TX buffers descriptors will be filled in as needed */
1474         for (i = 0; i < priv->tx_ring_size; i++) {
1475                 desc = &priv->tx_ring[i];
1476                 tx_info = &priv->tx_buffers[i];
1477
1478                 tx_info->skb = NULL;
1479                 tx_info->mapping = 0;
1480                 desc->status = 0;
1481         }
1482         desc->length = cpu_to_le32(TDES1_CONTROL_TER);
1483
1484         priv->cur_rx = priv->cur_tx = priv->dirty_tx = 0;
1485         ADM8211_CSR_WRITE(RDB, priv->rx_ring_dma);
1486         ADM8211_CSR_WRITE(TDBD, priv->tx_ring_dma);
1487
1488         return 0;
1489 }
1490
1491 static void adm8211_free_rings(struct ieee80211_hw *dev)
1492 {
1493         struct adm8211_priv *priv = dev->priv;
1494         unsigned int i;
1495
1496         for (i = 0; i < priv->rx_ring_size; i++) {
1497                 if (!priv->rx_buffers[i].skb)
1498                         continue;
1499
1500                 pci_unmap_single(
1501                         priv->pdev,
1502                         priv->rx_buffers[i].mapping,
1503                         RX_PKT_SIZE, PCI_DMA_FROMDEVICE);
1504
1505                 dev_kfree_skb(priv->rx_buffers[i].skb);
1506         }
1507
1508         for (i = 0; i < priv->tx_ring_size; i++) {
1509                 if (!priv->tx_buffers[i].skb)
1510                         continue;
1511
1512                 pci_unmap_single(priv->pdev,
1513                                  priv->tx_buffers[i].mapping,
1514                                  priv->tx_buffers[i].skb->len,
1515                                  PCI_DMA_TODEVICE);
1516
1517                 dev_kfree_skb(priv->tx_buffers[i].skb);
1518         }
1519 }
1520
1521 static int adm8211_start(struct ieee80211_hw *dev)
1522 {
1523         struct adm8211_priv *priv = dev->priv;
1524         int retval;
1525
1526         /* Power up MAC and RF chips */
1527         retval = adm8211_hw_reset(dev);
1528         if (retval) {
1529                 printk(KERN_ERR "%s: hardware reset failed\n",
1530                        wiphy_name(dev->wiphy));
1531                 goto fail;
1532         }
1533
1534         retval = adm8211_init_rings(dev);
1535         if (retval) {
1536                 printk(KERN_ERR "%s: failed to initialize rings\n",
1537                        wiphy_name(dev->wiphy));
1538                 goto fail;
1539         }
1540
1541         /* Init hardware */
1542         adm8211_hw_init(dev);
1543         adm8211_rf_set_channel(dev, priv->channel);
1544
1545         retval = request_irq(priv->pdev->irq, &adm8211_interrupt,
1546                              IRQF_SHARED, "adm8211", dev);
1547         if (retval) {
1548                 printk(KERN_ERR "%s: failed to register IRQ handler\n",
1549                        wiphy_name(dev->wiphy));
1550                 goto fail;
1551         }
1552
1553         ADM8211_CSR_WRITE(IER, ADM8211_IER_NIE | ADM8211_IER_AIE |
1554                                ADM8211_IER_RCIE | ADM8211_IER_TCIE |
1555                                ADM8211_IER_TDUIE | ADM8211_IER_GPTIE);
1556         adm8211_update_mode(dev);
1557         ADM8211_CSR_WRITE(RDR, 0);
1558
1559         adm8211_set_interval(dev, 100, 10);
1560         return 0;
1561
1562 fail:
1563         return retval;
1564 }
1565
1566 static void adm8211_stop(struct ieee80211_hw *dev)
1567 {
1568         struct adm8211_priv *priv = dev->priv;
1569
1570         priv->nar = 0;
1571         ADM8211_CSR_WRITE(NAR, 0);
1572         ADM8211_CSR_WRITE(IER, 0);
1573         ADM8211_CSR_READ(NAR);
1574
1575         free_irq(priv->pdev->irq, dev);
1576
1577         adm8211_free_rings(dev);
1578 }
1579
1580 static void adm8211_calc_durations(int *dur, int *plcp, size_t payload_len, int len,
1581                                    int plcp_signal, int short_preamble)
1582 {
1583         /* Alternative calculation from NetBSD: */
1584
1585 /* IEEE 802.11b durations for DSSS PHY in microseconds */
1586 #define IEEE80211_DUR_DS_LONG_PREAMBLE  144
1587 #define IEEE80211_DUR_DS_SHORT_PREAMBLE 72
1588 #define IEEE80211_DUR_DS_FAST_PLCPHDR   24
1589 #define IEEE80211_DUR_DS_SLOW_PLCPHDR   48
1590 #define IEEE80211_DUR_DS_SLOW_ACK       112
1591 #define IEEE80211_DUR_DS_FAST_ACK       56
1592 #define IEEE80211_DUR_DS_SLOW_CTS       112
1593 #define IEEE80211_DUR_DS_FAST_CTS       56
1594 #define IEEE80211_DUR_DS_SLOT           20
1595 #define IEEE80211_DUR_DS_SIFS           10
1596
1597         int remainder;
1598
1599         *dur = (80 * (24 + payload_len) + plcp_signal - 1)
1600                 / plcp_signal;
1601
1602         if (plcp_signal <= PLCP_SIGNAL_2M)
1603                 /* 1-2Mbps WLAN: send ACK/CTS at 1Mbps */
1604                 *dur += 3 * (IEEE80211_DUR_DS_SIFS +
1605                              IEEE80211_DUR_DS_SHORT_PREAMBLE +
1606                              IEEE80211_DUR_DS_FAST_PLCPHDR) +
1607                              IEEE80211_DUR_DS_SLOW_CTS + IEEE80211_DUR_DS_SLOW_ACK;
1608         else
1609                 /* 5-11Mbps WLAN: send ACK/CTS at 2Mbps */
1610                 *dur += 3 * (IEEE80211_DUR_DS_SIFS +
1611                              IEEE80211_DUR_DS_SHORT_PREAMBLE +
1612                              IEEE80211_DUR_DS_FAST_PLCPHDR) +
1613                              IEEE80211_DUR_DS_FAST_CTS + IEEE80211_DUR_DS_FAST_ACK;
1614
1615         /* lengthen duration if long preamble */
1616         if (!short_preamble)
1617                 *dur += 3 * (IEEE80211_DUR_DS_LONG_PREAMBLE -
1618                              IEEE80211_DUR_DS_SHORT_PREAMBLE) +
1619                         3 * (IEEE80211_DUR_DS_SLOW_PLCPHDR -
1620                              IEEE80211_DUR_DS_FAST_PLCPHDR);
1621
1622
1623         *plcp = (80 * len) / plcp_signal;
1624         remainder = (80 * len) % plcp_signal;
1625         if (plcp_signal == PLCP_SIGNAL_11M &&
1626             remainder <= 30 && remainder > 0)
1627                 *plcp = (*plcp | 0x8000) + 1;
1628         else if (remainder)
1629                 (*plcp)++;
1630 }
1631
1632 /* Transmit skb w/adm8211_tx_hdr (802.11 header created by hardware) */
1633 static void adm8211_tx_raw(struct ieee80211_hw *dev, struct sk_buff *skb,
1634                            u16 plcp_signal,
1635                            struct ieee80211_tx_control *control,
1636                            size_t hdrlen)
1637 {
1638         struct adm8211_priv *priv = dev->priv;
1639         unsigned long flags;
1640         dma_addr_t mapping;
1641         unsigned int entry;
1642         u32 flag;
1643
1644         mapping = pci_map_single(priv->pdev, skb->data, skb->len,
1645                                  PCI_DMA_TODEVICE);
1646
1647         spin_lock_irqsave(&priv->lock, flags);
1648
1649         if (priv->cur_tx - priv->dirty_tx == priv->tx_ring_size / 2)
1650                 flag = TDES1_CONTROL_IC | TDES1_CONTROL_LS | TDES1_CONTROL_FS;
1651         else
1652                 flag = TDES1_CONTROL_LS | TDES1_CONTROL_FS;
1653
1654         if (priv->cur_tx - priv->dirty_tx == priv->tx_ring_size - 2)
1655                 ieee80211_stop_queue(dev, 0);
1656
1657         entry = priv->cur_tx % priv->tx_ring_size;
1658
1659         priv->tx_buffers[entry].skb = skb;
1660         priv->tx_buffers[entry].mapping = mapping;
1661         memcpy(&priv->tx_buffers[entry].tx_control, control, sizeof(*control));
1662         priv->tx_buffers[entry].hdrlen = hdrlen;
1663         priv->tx_ring[entry].buffer1 = cpu_to_le32(mapping);
1664
1665         if (entry == priv->tx_ring_size - 1)
1666                 flag |= TDES1_CONTROL_TER;
1667         priv->tx_ring[entry].length = cpu_to_le32(flag | skb->len);
1668
1669         /* Set TX rate (SIGNAL field in PLCP PPDU format) */
1670         flag = TDES0_CONTROL_OWN | (plcp_signal << 20) | 8 /* ? */;
1671         priv->tx_ring[entry].status = cpu_to_le32(flag);
1672
1673         priv->cur_tx++;
1674
1675         spin_unlock_irqrestore(&priv->lock, flags);
1676
1677         /* Trigger transmit poll */
1678         ADM8211_CSR_WRITE(TDR, 0);
1679 }
1680
1681 /* Put adm8211_tx_hdr on skb and transmit */
1682 static int adm8211_tx(struct ieee80211_hw *dev, struct sk_buff *skb,
1683                       struct ieee80211_tx_control *control)
1684 {
1685         struct adm8211_tx_hdr *txhdr;
1686         u16 fc;
1687         size_t payload_len, hdrlen;
1688         int plcp, dur, len, plcp_signal, short_preamble;
1689         struct ieee80211_hdr *hdr;
1690
1691         if (control->tx_rate < 0) {
1692                 short_preamble = 1;
1693                 plcp_signal = -control->tx_rate;
1694         } else {
1695                 short_preamble = 0;
1696                 plcp_signal = control->tx_rate;
1697         }
1698
1699         hdr = (struct ieee80211_hdr *)skb->data;
1700         fc = le16_to_cpu(hdr->frame_control) & ~IEEE80211_FCTL_PROTECTED;
1701         hdrlen = ieee80211_get_hdrlen(fc);
1702         memcpy(skb->cb, skb->data, hdrlen);
1703         hdr = (struct ieee80211_hdr *)skb->cb;
1704         skb_pull(skb, hdrlen);
1705         payload_len = skb->len;
1706
1707         txhdr = (struct adm8211_tx_hdr *) skb_push(skb, sizeof(*txhdr));
1708         memset(txhdr, 0, sizeof(*txhdr));
1709         memcpy(txhdr->da, ieee80211_get_DA(hdr), ETH_ALEN);
1710         txhdr->signal = plcp_signal;
1711         txhdr->frame_body_size = cpu_to_le16(payload_len);
1712         txhdr->frame_control = hdr->frame_control;
1713
1714         len = hdrlen + payload_len + FCS_LEN;
1715         if (fc & IEEE80211_FCTL_PROTECTED)
1716                 len += 8;
1717
1718         txhdr->frag = cpu_to_le16(0x0FFF);
1719         adm8211_calc_durations(&dur, &plcp, payload_len,
1720                                len, plcp_signal, short_preamble);
1721         txhdr->plcp_frag_head_len = cpu_to_le16(plcp);
1722         txhdr->plcp_frag_tail_len = cpu_to_le16(plcp);
1723         txhdr->dur_frag_head = cpu_to_le16(dur);
1724         txhdr->dur_frag_tail = cpu_to_le16(dur);
1725
1726         txhdr->header_control = cpu_to_le16(ADM8211_TXHDRCTL_ENABLE_EXTEND_HEADER);
1727
1728         if (short_preamble)
1729                 txhdr->header_control |= cpu_to_le16(ADM8211_TXHDRCTL_SHORT_PREAMBLE);
1730
1731         if (control->flags & IEEE80211_TXCTL_USE_RTS_CTS)
1732                 txhdr->header_control |= cpu_to_le16(ADM8211_TXHDRCTL_ENABLE_RTS);
1733
1734         if (fc & IEEE80211_FCTL_PROTECTED)
1735                 txhdr->header_control |= cpu_to_le16(ADM8211_TXHDRCTL_ENABLE_WEP_ENGINE);
1736
1737         txhdr->retry_limit = control->retry_limit;
1738
1739         adm8211_tx_raw(dev, skb, plcp_signal, control, hdrlen);
1740
1741         return NETDEV_TX_OK;
1742 }
1743
1744 static int adm8211_alloc_rings(struct ieee80211_hw *dev)
1745 {
1746         struct adm8211_priv *priv = dev->priv;
1747         unsigned int ring_size;
1748
1749         priv->rx_buffers = kmalloc(sizeof(*priv->rx_buffers) * priv->rx_ring_size +
1750                                    sizeof(*priv->tx_buffers) * priv->tx_ring_size, GFP_KERNEL);
1751         if (!priv->rx_buffers)
1752                 return -ENOMEM;
1753
1754         priv->tx_buffers = (void *)priv->rx_buffers +
1755                            sizeof(*priv->rx_buffers) * priv->rx_ring_size;
1756
1757         /* Allocate TX/RX descriptors */
1758         ring_size = sizeof(struct adm8211_desc) * priv->rx_ring_size +
1759                     sizeof(struct adm8211_desc) * priv->tx_ring_size;
1760         priv->rx_ring = pci_alloc_consistent(priv->pdev, ring_size,
1761                                              &priv->rx_ring_dma);
1762
1763         if (!priv->rx_ring) {
1764                 kfree(priv->rx_buffers);
1765                 priv->rx_buffers = NULL;
1766                 priv->tx_buffers = NULL;
1767                 return -ENOMEM;
1768         }
1769
1770         priv->tx_ring = (struct adm8211_desc *)(priv->rx_ring +
1771                                                 priv->rx_ring_size);
1772         priv->tx_ring_dma = priv->rx_ring_dma +
1773                             sizeof(struct adm8211_desc) * priv->rx_ring_size;
1774
1775         return 0;
1776 }
1777
1778 static const struct ieee80211_ops adm8211_ops = {
1779         .tx                     = adm8211_tx,
1780         .start                  = adm8211_start,
1781         .stop                   = adm8211_stop,
1782         .add_interface          = adm8211_add_interface,
1783         .remove_interface       = adm8211_remove_interface,
1784         .config                 = adm8211_config,
1785         .config_interface       = adm8211_config_interface,
1786         .configure_filter       = adm8211_configure_filter,
1787         .get_stats              = adm8211_get_stats,
1788         .get_tx_stats           = adm8211_get_tx_stats,
1789         .get_tsf                = adm8211_get_tsft
1790 };
1791
1792 static int __devinit adm8211_probe(struct pci_dev *pdev,
1793                                    const struct pci_device_id *id)
1794 {
1795         struct ieee80211_hw *dev;
1796         struct adm8211_priv *priv;
1797         unsigned long mem_addr, mem_len;
1798         unsigned int io_addr, io_len;
1799         int err;
1800         u32 reg;
1801         u8 perm_addr[ETH_ALEN];
1802         DECLARE_MAC_BUF(mac);
1803
1804 #ifndef MODULE
1805         static unsigned int cardidx;
1806         if (!cardidx++)
1807                 printk(version);
1808 #endif
1809
1810         err = pci_enable_device(pdev);
1811         if (err) {
1812                 printk(KERN_ERR "%s (adm8211): Cannot enable new PCI device\n",
1813                        pci_name(pdev));
1814                 return err;
1815         }
1816
1817         io_addr = pci_resource_start(pdev, 0);
1818         io_len = pci_resource_len(pdev, 0);
1819         mem_addr = pci_resource_start(pdev, 1);
1820         mem_len = pci_resource_len(pdev, 1);
1821         if (io_len < 256 || mem_len < 1024) {
1822                 printk(KERN_ERR "%s (adm8211): Too short PCI resources\n",
1823                        pci_name(pdev));
1824                 goto err_disable_pdev;
1825         }
1826
1827
1828         /* check signature */
1829         pci_read_config_dword(pdev, 0x80 /* CR32 */, &reg);
1830         if (reg != ADM8211_SIG1 && reg != ADM8211_SIG2) {
1831                 printk(KERN_ERR "%s (adm8211): Invalid signature (0x%x)\n",
1832                        pci_name(pdev), reg);
1833                 goto err_disable_pdev;
1834         }
1835
1836         err = pci_request_regions(pdev, "adm8211");
1837         if (err) {
1838                 printk(KERN_ERR "%s (adm8211): Cannot obtain PCI resources\n",
1839                        pci_name(pdev));
1840                 return err; /* someone else grabbed it? don't disable it */
1841         }
1842
1843         if (pci_set_dma_mask(pdev, DMA_32BIT_MASK) ||
1844             pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK)) {
1845                 printk(KERN_ERR "%s (adm8211): No suitable DMA available\n",
1846                        pci_name(pdev));
1847                 goto err_free_reg;
1848         }
1849
1850         pci_set_master(pdev);
1851
1852         dev = ieee80211_alloc_hw(sizeof(*priv), &adm8211_ops);
1853         if (!dev) {
1854                 printk(KERN_ERR "%s (adm8211): ieee80211 alloc failed\n",
1855                        pci_name(pdev));
1856                 err = -ENOMEM;
1857                 goto err_free_reg;
1858         }
1859         priv = dev->priv;
1860         priv->pdev = pdev;
1861
1862         spin_lock_init(&priv->lock);
1863
1864         SET_IEEE80211_DEV(dev, &pdev->dev);
1865
1866         pci_set_drvdata(pdev, dev);
1867
1868         priv->map = pci_iomap(pdev, 1, mem_len);
1869         if (!priv->map)
1870                 priv->map = pci_iomap(pdev, 0, io_len);
1871
1872         if (!priv->map) {
1873                 printk(KERN_ERR "%s (adm8211): Cannot map device memory\n",
1874                        pci_name(pdev));
1875                 goto err_free_dev;
1876         }
1877
1878         priv->rx_ring_size = rx_ring_size;
1879         priv->tx_ring_size = tx_ring_size;
1880
1881         if (adm8211_alloc_rings(dev)) {
1882                 printk(KERN_ERR "%s (adm8211): Cannot allocate TX/RX ring\n",
1883                        pci_name(pdev));
1884                 goto err_iounmap;
1885         }
1886
1887         pci_read_config_byte(pdev, PCI_CLASS_REVISION, &priv->revid);
1888
1889         *(u32 *)perm_addr = le32_to_cpu((__force __le32)ADM8211_CSR_READ(PAR0));
1890         *(u16 *)&perm_addr[4] =
1891                 le16_to_cpu((__force __le16)ADM8211_CSR_READ(PAR1) & 0xFFFF);
1892
1893         if (!is_valid_ether_addr(perm_addr)) {
1894                 printk(KERN_WARNING "%s (adm8211): Invalid hwaddr in EEPROM!\n",
1895                        pci_name(pdev));
1896                 random_ether_addr(perm_addr);
1897         }
1898         SET_IEEE80211_PERM_ADDR(dev, perm_addr);
1899
1900         dev->extra_tx_headroom = sizeof(struct adm8211_tx_hdr);
1901         dev->flags = IEEE80211_HW_DEFAULT_REG_DOMAIN_CONFIGURED;
1902         /* IEEE80211_HW_RX_INCLUDES_FCS in promisc mode */
1903
1904         dev->channel_change_time = 1000;
1905         dev->max_rssi = 100;    /* FIXME: find better value */
1906
1907         priv->modes[0].mode = MODE_IEEE80211B;
1908         /* channel info filled in by adm8211_read_eeprom */
1909         memcpy(priv->rates, adm8211_rates, sizeof(adm8211_rates));
1910         priv->modes[0].num_rates = ARRAY_SIZE(adm8211_rates);
1911         priv->modes[0].rates = priv->rates;
1912
1913         dev->queues = 1; /* ADM8211C supports more, maybe ADM8211B too */
1914
1915         priv->retry_limit = 3;
1916         priv->ant_power = 0x40;
1917         priv->tx_power = 0x40;
1918         priv->lpf_cutoff = 0xFF;
1919         priv->lnags_threshold = 0xFF;
1920         priv->mode = IEEE80211_IF_TYPE_MNTR;
1921
1922         /* Power-on issue. EEPROM won't read correctly without */
1923         if (priv->revid >= ADM8211_REV_BA) {
1924                 ADM8211_CSR_WRITE(FRCTL, 0);
1925                 ADM8211_CSR_READ(FRCTL);
1926                 ADM8211_CSR_WRITE(FRCTL, 1);
1927                 ADM8211_CSR_READ(FRCTL);
1928                 msleep(100);
1929         }
1930
1931         err = adm8211_read_eeprom(dev);
1932         if (err) {
1933                 printk(KERN_ERR "%s (adm8211): Can't alloc eeprom buffer\n",
1934                        pci_name(pdev));
1935                 goto err_free_desc;
1936         }
1937
1938         priv->channel = priv->modes[0].channels[0].chan;
1939
1940         err = ieee80211_register_hwmode(dev, &priv->modes[0]);
1941         if (err) {
1942                 printk(KERN_ERR "%s (adm8211): Can't register hwmode\n",
1943                        pci_name(pdev));
1944                 goto err_free_desc;
1945         }
1946
1947         err = ieee80211_register_hw(dev);
1948         if (err) {
1949                 printk(KERN_ERR "%s (adm8211): Cannot register device\n",
1950                        pci_name(pdev));
1951                 goto err_free_desc;
1952         }
1953
1954         printk(KERN_INFO "%s: hwaddr %s, Rev 0x%02x\n",
1955                wiphy_name(dev->wiphy), print_mac(mac, dev->wiphy->perm_addr),
1956                priv->revid);
1957
1958         return 0;
1959
1960  err_free_desc:
1961         pci_free_consistent(pdev,
1962                             sizeof(struct adm8211_desc) * priv->rx_ring_size +
1963                             sizeof(struct adm8211_desc) * priv->tx_ring_size,
1964                             priv->rx_ring, priv->rx_ring_dma);
1965         kfree(priv->rx_buffers);
1966
1967  err_iounmap:
1968         pci_iounmap(pdev, priv->map);
1969
1970  err_free_dev:
1971         pci_set_drvdata(pdev, NULL);
1972         ieee80211_free_hw(dev);
1973
1974  err_free_reg:
1975         pci_release_regions(pdev);
1976
1977  err_disable_pdev:
1978         pci_disable_device(pdev);
1979         return err;
1980 }
1981
1982
1983 static void __devexit adm8211_remove(struct pci_dev *pdev)
1984 {
1985         struct ieee80211_hw *dev = pci_get_drvdata(pdev);
1986         struct adm8211_priv *priv;
1987
1988         if (!dev)
1989                 return;
1990
1991         ieee80211_unregister_hw(dev);
1992
1993         priv = dev->priv;
1994
1995         pci_free_consistent(pdev,
1996                             sizeof(struct adm8211_desc) * priv->rx_ring_size +
1997                             sizeof(struct adm8211_desc) * priv->tx_ring_size,
1998                             priv->rx_ring, priv->rx_ring_dma);
1999
2000         kfree(priv->rx_buffers);
2001         kfree(priv->eeprom);
2002         pci_iounmap(pdev, priv->map);
2003         pci_release_regions(pdev);
2004         pci_disable_device(pdev);
2005         ieee80211_free_hw(dev);
2006 }
2007
2008
2009 #ifdef CONFIG_PM
2010 static int adm8211_suspend(struct pci_dev *pdev, pm_message_t state)
2011 {
2012         struct ieee80211_hw *dev = pci_get_drvdata(pdev);
2013         struct adm8211_priv *priv = dev->priv;
2014
2015         if (priv->mode != IEEE80211_IF_TYPE_MNTR) {
2016                 ieee80211_stop_queues(dev);
2017                 adm8211_stop(dev);
2018         }
2019
2020         pci_save_state(pdev);
2021         pci_set_power_state(pdev, pci_choose_state(pdev, state));
2022         return 0;
2023 }
2024
2025 static int adm8211_resume(struct pci_dev *pdev)
2026 {
2027         struct ieee80211_hw *dev = pci_get_drvdata(pdev);
2028         struct adm8211_priv *priv = dev->priv;
2029
2030         pci_set_power_state(pdev, PCI_D0);
2031         pci_restore_state(pdev);
2032
2033         if (priv->mode != IEEE80211_IF_TYPE_MNTR) {
2034                 adm8211_start(dev);
2035                 ieee80211_start_queues(dev);
2036         }
2037
2038         return 0;
2039 }
2040 #endif /* CONFIG_PM */
2041
2042
2043 MODULE_DEVICE_TABLE(pci, adm8211_pci_id_table);
2044
2045 /* TODO: implement enable_wake */
2046 static struct pci_driver adm8211_driver = {
2047         .name           = "adm8211",
2048         .id_table       = adm8211_pci_id_table,
2049         .probe          = adm8211_probe,
2050         .remove         = __devexit_p(adm8211_remove),
2051 #ifdef CONFIG_PM
2052         .suspend        = adm8211_suspend,
2053         .resume         = adm8211_resume,
2054 #endif /* CONFIG_PM */
2055 };
2056
2057
2058
2059 static int __init adm8211_init(void)
2060 {
2061 #ifdef MODULE
2062         printk(version);
2063 #endif
2064
2065         return pci_register_driver(&adm8211_driver);
2066 }
2067
2068
2069 static void __exit adm8211_exit(void)
2070 {
2071         pci_unregister_driver(&adm8211_driver);
2072 }
2073
2074
2075 module_init(adm8211_init);
2076 module_exit(adm8211_exit);