SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/net/wan/pc300_drv.c

   1 #define USE_PCI_CLOCK
   2 static char rcsid[] =
   3 "Revision: 3.4.5 Date: 2002/03/07 ";
   4
   5 /*
   6  * pc300.c      Cyclades-PC300(tm) Driver.
   7  *
   8  * Author:      Ivan Passos <ivan@cyclades.com>
   9  * Maintainer:  PC300 Maintainer <pc300@cyclades.com>
  10  *
  11  * Copyright:   (c) 1999-2003 Cyclades Corp.
  12  *
  13  *      This program is free software; you can redistribute it and/or
  14  *      modify it under the terms of the GNU General Public License
  15  *      as published by the Free Software Foundation; either version
  16  *      2 of the License, or (at your option) any later version.
  17  *
  18  *      Using tabstop = 4.
  19  *
  20  * $Log: pc300_drv.c,v $
  21  * Revision 3.23  2002/03/20 13:58:40  henrique
  22  * Fixed ortographic mistakes
  23  *
  24  * Revision 3.22  2002/03/13 16:56:56  henrique
  25  * Take out the debug messages
  26  *
  27  * Revision 3.21  2002/03/07 14:17:09  henrique
  28  * License data fixed
  29  *
  30  * Revision 3.20  2002/01/17 17:58:52  ivan
  31  * Support for PC300-TE/M (PMC).
  32  *
  33  * Revision 3.19  2002/01/03 17:08:47  daniela
  34  * Enables DMA reception when the SCA-II disables it improperly.
  35  *
  36  * Revision 3.18  2001/12/03 18:47:50  daniela
  37  * Esthetic changes.
  38  *
  39  * Revision 3.17  2001/10/19 16:50:13  henrique
  40  * Patch to kernel 2.4.12 and new generic hdlc.
  41  *
  42  * Revision 3.16  2001/10/16 15:12:31  regina
  43  * clear statistics
  44  *
  45  * Revision 3.11 to 3.15  2001/10/11 20:26:04  daniela
  46  * More DMA fixes for noisy lines.
  47  * Return the size of bad frames in dma_get_rx_frame_size, so that the Rx buffer
  48  * descriptors can be cleaned by dma_buf_read (called in cpc_net_rx).
  49  * Renamed dma_start routine to rx_dma_start. Improved Rx statistics.
  50  * Fixed BOF interrupt treatment. Created dma_start routine.
  51  * Changed min and max to cpc_min and cpc_max.
  52  *
  53  * Revision 3.10  2001/08/06 12:01:51  regina
  54  * Fixed problem in DSR_DE bit.
  55  *
  56  * Revision 3.9  2001/07/18 19:27:26  daniela
  57  * Added some history comments.
  58  *
  59  * Revision 3.8  2001/07/12 13:11:19  regina
  60  * bug fix - DCD-OFF in pc300 tty driver
  61  *
  62  * Revision 3.3 to 3.7  2001/07/06 15:00:20  daniela
  63  * Removing kernel 2.4.3 and previous support.
  64  * DMA transmission bug fix.
  65  * MTU check in cpc_net_rx fixed.
  66  * Boot messages reviewed.
  67  * New configuration parameters (line code, CRC calculation and clock).
  68  *
  69  * Revision 3.2 2001/06/22 13:13:02  regina
  70  * MLPPP implementation. Changed the header of message trace to include
  71  * the device name. New format : "hdlcX[R/T]: ".
  72  * Default configuration changed.
  73  *
  74  * Revision 3.1 2001/06/15 regina
  75  * in cpc_queue_xmit, netif_stop_queue is called if don't have free descriptor
  76  * upping major version number
  77  *
  78  * Revision 1.1.1.1  2001/06/13 20:25:04  daniela
  79  * PC300 initial CVS version (3.4.0-pre1)
  80  *
  81  * Revision 3.0.1.2 2001/06/08 daniela
  82  * Did some changes in the DMA programming implementation to avoid the
  83  * occurrence of a SCA-II bug when CDA is accessed during a DMA transfer.
  84  *
  85  * Revision 3.0.1.1 2001/05/02 daniela
  86  * Added kernel 2.4.3 support.
  87  *
  88  * Revision 3.0.1.0 2001/03/13 daniela, henrique
  89  * Added Frame Relay Support.
  90  * Driver now uses HDLC generic driver to provide protocol support.
  91  *
  92  * Revision 3.0.0.8 2001/03/02 daniela
  93  * Fixed ram size detection.
  94  * Changed SIOCGPC300CONF ioctl, to give hw information to pc300util.
  95  *
  96  * Revision 3.0.0.7 2001/02/23 daniela
  97  * netif_stop_queue called before the SCA-II transmition commands in
  98  * cpc_queue_xmit, and with interrupts disabled to avoid race conditions with
  99  * transmition interrupts.
 100  * Fixed falc_check_status for Unframed E1.
 101  *
 102  * Revision 3.0.0.6 2000/12/13 daniela
 103  * Implemented pc300util support: trace, statistics, status and loopback
 104  * tests for the PC300 TE boards.
 105  *
 106  * Revision 3.0.0.5 2000/12/12 ivan
 107  * Added support for Unframed E1.
 108  * Implemented monitor mode.
 109  * Fixed DCD sensitivity on the second channel.
 110  * Driver now complies with new PCI kernel architecture.
 111  *
 112  * Revision 3.0.0.4 2000/09/28 ivan
 113  * Implemented DCD sensitivity.
 114  * Moved hardware-specific open to the end of cpc_open, to avoid race
 115  * conditions with early reception interrupts.
 116  * Included code for [request|release]_mem_region().
 117  * Changed location of pc300.h .
 118  * Minor code revision (contrib. of Jeff Garzik).
 119  *
 120  * Revision 3.0.0.3 2000/07/03 ivan
 121  * Previous bugfix for the framing errors with external clock made X21
 122  * boards stop working. This version fixes it.
 123  *
 124  * Revision 3.0.0.2 2000/06/23 ivan
 125  * Revisited cpc_queue_xmit to prevent race conditions on Tx DMA buffer
 126  * handling when Tx timeouts occur.
 127  * Revisited Rx statistics.
 128  * Fixed a bug in the SCA-II programming that would cause framing errors
 129  * when external clock was configured.
 130  *
 131  * Revision 3.0.0.1 2000/05/26 ivan
 132  * Added logic in the SCA interrupt handler so that no board can monopolize
 133  * the driver.
 134  * Request PLX I/O region, although driver doesn't use it, to avoid
 135  * problems with other drivers accessing it.
 136  *
 137  * Revision 3.0.0.0 2000/05/15 ivan
 138  * Did some changes in the DMA programming implementation to avoid the
 139  * occurrence of a SCA-II bug in the second channel.
 140  * Implemented workaround for PLX9050 bug that would cause a system lockup
 141  * in certain systems, depending on the MMIO addresses allocated to the
 142  * board.
 143  * Fixed the FALC chip programming to avoid synchronization problems in the
 144  * second channel (TE only).
 145  * Implemented a cleaner and faster Tx DMA descriptor cleanup procedure in
 146  * cpc_queue_xmit().
 147  * Changed the built-in driver implementation so that the driver can use the
 148  * general 'hdlcN' naming convention instead of proprietary device names.
 149  * Driver load messages are now device-centric, instead of board-centric.
 150  * Dynamic allocation of net_device structures.
 151  * Code is now compliant with the new module interface (module_[init|exit]).
 152  * Make use of the PCI helper functions to access PCI resources.
 153  *
 154  * Revision 2.0.0.0 2000/04/15 ivan
 155  * Added support for the PC300/TE boards (T1/FT1/E1/FE1).
 156  *
 157  * Revision 1.1.0.0 2000/02/28 ivan
 158  * Major changes in the driver architecture.
 159  * Softnet compliancy implemented.
 160  * Driver now reports physical instead of virtual memory addresses.
 161  * Added cpc_change_mtu function.
 162  *
 163  * Revision 1.0.0.0 1999/12/16 ivan
 164  * First official release.
 165  * Support for 1- and 2-channel boards (which use distinct PCI Device ID's).
 166  * Support for monolythic installation (i.e., drv built into the kernel).
 167  * X.25 additional checking when lapb_[dis]connect_request returns an error.
 168  * SCA programming now covers X.21 as well.
 169  *
 170  * Revision 0.3.1.0 1999/11/18 ivan
 171  * Made X.25 support configuration-dependent (as it depends on external
 172  * modules to work).
 173  * Changed X.25-specific function names to comply with adopted convention.
 174  * Fixed typos in X.25 functions that would cause compile errors (Daniela).
 175  * Fixed bug in ch_config that would disable interrupts on a previously
 176  * enabled channel if the other channel on the same board was enabled later.
 177  *
 178  * Revision 0.3.0.0 1999/11/16 daniela
 179  * X.25 support.
 180  *
 181  * Revision 0.2.3.0 1999/11/15 ivan
 182  * Function cpc_ch_status now provides more detailed information.
 183  * Added support for X.21 clock configuration.
 184  * Changed TNR1 setting in order to prevent Tx FIFO overaccesses by the SCA.
 185  * Now using PCI clock instead of internal oscillator clock for the SCA.
 186  *
 187  * Revision 0.2.2.0 1999/11/10 ivan
 188  * Changed the *_dma_buf_check functions so that they would print only
 189  * the useful info instead of the whole buffer descriptor bank.
 190  * Fixed bug in cpc_queue_xmit that would eventually crash the system
 191  * in case of a packet drop.
 192  * Implemented TX underrun handling.
 193  * Improved SCA fine tuning to boost up its performance.
 194  *
 195  * Revision 0.2.1.0 1999/11/03 ivan
 196  * Added functions *dma_buf_pt_init to allow independent initialization
 197  * of the next-descr. and DMA buffer pointers on the DMA descriptors.
 198  * Kernel buffer release and tbusy clearing is now done in the interrupt
 199  * handler.
 200  * Fixed bug in cpc_open that would cause an interface reopen to fail.
 201  * Added a protocol-specific code section in cpc_net_rx.
 202  * Removed printk level defs (they might be added back after the beta phase).
 203  *
 204  * Revision 0.2.0.0 1999/10/28 ivan
 205  * Revisited the code so that new protocols can be easily added / supported.
 206  *
 207  * Revision 0.1.0.1 1999/10/20 ivan
 208  * Mostly "esthetic" changes.
 209  *
 210  * Revision 0.1.0.0 1999/10/11 ivan
 211  * Initial version.
 212  *
 213  */
 214
 215 #include <linux/module.h>
 216 #include <linux/kernel.h>
 217 #include <linux/mm.h>
 218 #include <linux/ioport.h>
 219 #include <linux/pci.h>
 220 #include <linux/errno.h>
 221 #include <linux/string.h>
 222 #include <linux/init.h>
 223 #include <linux/delay.h>
 224 #include <linux/net.h>
 225 #include <linux/skbuff.h>
 226 #include <linux/if_arp.h>
 227 #include <linux/netdevice.h>
 228 #include <linux/spinlock.h>
 229 #include <linux/if.h>
 230
 231 #include <net/syncppp.h>
 232 #include <net/arp.h>
 233
 234 #include <asm/io.h>
 235 #include <asm/uaccess.h>
 236
 237 #include "pc300.h"
 238
 239 #define CPC_LOCK(card,flags)            \
 240                 do {                                            \
 241                 spin_lock_irqsave(&card->card_lock, flags);     \
 242                 } while (0)
 243
 244 #define CPC_UNLOCK(card,flags)                  \
 245                 do {                                                    \
 246                 spin_unlock_irqrestore(&card->card_lock, flags);        \
 247                 } while (0)
 248
 249 #undef  PC300_DEBUG_PCI
 250 #undef  PC300_DEBUG_INTR
 251 #undef  PC300_DEBUG_TX
 252 #undef  PC300_DEBUG_RX
 253 #undef  PC300_DEBUG_OTHER
 254
 255 static struct pci_device_id cpc_pci_dev_id[] __devinitdata = {
 256         /* PC300/RSV or PC300/X21, 2 chan */
 257         {0x120e, 0x300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0x300},
 258         /* PC300/RSV or PC300/X21, 1 chan */
 259         {0x120e, 0x301, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0x301},
 260         /* PC300/TE, 2 chan */
 261         {0x120e, 0x310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0x310},
 262         /* PC300/TE, 1 chan */
 263         {0x120e, 0x311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0x311},
 264         /* PC300/TE-M, 2 chan */
 265         {0x120e, 0x320, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0x320},
 266         /* PC300/TE-M, 1 chan */
 267         {0x120e, 0x321, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0x321},
 268         /* End of table */
 269         {0,},
 270 };
 271 MODULE_DEVICE_TABLE(pci, cpc_pci_dev_id);
 272
 273 #ifndef cpc_min
 274 #define cpc_min(a,b)    (((a)<(b))?(a):(b))
 275 #endif
 276 #ifndef cpc_max
 277 #define cpc_max(a,b)    (((a)>(b))?(a):(b))
 278 #endif
 279
 280 /* prototypes */
 281 static void tx_dma_buf_pt_init(pc300_t *, int);
 282 static void tx_dma_buf_init(pc300_t *, int);
 283 static void rx_dma_buf_pt_init(pc300_t *, int);
 284 static void rx_dma_buf_init(pc300_t *, int);
 285 static void tx_dma_buf_check(pc300_t *, int);
 286 static void rx_dma_buf_check(pc300_t *, int);
 287 static irqreturn_t cpc_intr(int, void *, struct pt_regs *);
 288 static struct net_device_stats *cpc_get_stats(struct net_device *);
 289 static int clock_rate_calc(uclong, uclong, int *);
 290 static uclong detect_ram(pc300_t *);
 291 static void plx_init(pc300_t *);
 292 static void cpc_trace(struct net_device *, struct sk_buff *, char);
 293 static int cpc_attach(struct net_device *, unsigned short, unsigned short);
 294
 295 #ifdef CONFIG_PC300_MLPPP
 296 void cpc_tty_init(pc300dev_t * dev);
 297 void cpc_tty_unregister_service(pc300dev_t * pc300dev);
 298 void cpc_tty_receive(pc300dev_t * pc300dev);
 299 void cpc_tty_trigger_poll(pc300dev_t * pc300dev);
 300 void cpc_tty_reset_var(void);
 301 #endif
 302
 303 /************************/
 304 /***   DMA Routines   ***/
 305 /************************/
 306 static void tx_dma_buf_pt_init(pc300_t * card, int ch)
 307 {
 308         int i;
 309         int ch_factor = ch * N_DMA_TX_BUF;
 310         volatile pcsca_bd_t __iomem *ptdescr = (card->hw.rambase
 311                                        + DMA_TX_BD_BASE + ch_factor * sizeof(pcsca_bd_t));
 312
 313         for (i = 0; i < N_DMA_TX_BUF; i++, ptdescr++) {
 314                 cpc_writel(&ptdescr->next, (uclong) (DMA_TX_BD_BASE +
 315                         (ch_factor + ((i + 1) & (N_DMA_TX_BUF - 1))) * sizeof(pcsca_bd_t)));
 316                 cpc_writel(&ptdescr->ptbuf,
 317                                                 (uclong) (DMA_TX_BASE + (ch_factor + i) * BD_DEF_LEN));
 318         }
 319 }
 320
 321 static void tx_dma_buf_init(pc300_t * card, int ch)
 322 {
 323         int i;
 324         int ch_factor = ch * N_DMA_TX_BUF;
 325         volatile pcsca_bd_t __iomem *ptdescr = (card->hw.rambase
 326                                + DMA_TX_BD_BASE + ch_factor * sizeof(pcsca_bd_t));
 327
 328         for (i = 0; i < N_DMA_TX_BUF; i++, ptdescr++) {
 329                 memset_io(ptdescr, 0, sizeof(pcsca_bd_t));
 330                 cpc_writew(&ptdescr->len, 0);
 331                 cpc_writeb(&ptdescr->status, DST_OSB);
 332         }
 333         tx_dma_buf_pt_init(card, ch);
 334 }
 335
 336 static void rx_dma_buf_pt_init(pc300_t * card, int ch)
 337 {
 338         int i;
 339         int ch_factor = ch * N_DMA_RX_BUF;
 340         volatile pcsca_bd_t __iomem *ptdescr = (card->hw.rambase
 341                                        + DMA_RX_BD_BASE + ch_factor * sizeof(pcsca_bd_t));
 342
 343         for (i = 0; i < N_DMA_RX_BUF; i++, ptdescr++) {
 344                 cpc_writel(&ptdescr->next, (uclong) (DMA_RX_BD_BASE +
 345                 (ch_factor + ((i + 1) & (N_DMA_RX_BUF - 1))) * sizeof(pcsca_bd_t)));
 346                 cpc_writel(&ptdescr->ptbuf,
 347                            (uclong) (DMA_RX_BASE + (ch_factor + i) * BD_DEF_LEN));
 348         }
 349 }
 350
 351 static void rx_dma_buf_init(pc300_t * card, int ch)
 352 {
 353         int i;
 354         int ch_factor = ch * N_DMA_RX_BUF;
 355         volatile pcsca_bd_t __iomem *ptdescr = (card->hw.rambase
 356                                        + DMA_RX_BD_BASE + ch_factor * sizeof(pcsca_bd_t));
 357
 358         for (i = 0; i < N_DMA_RX_BUF; i++, ptdescr++) {
 359                 memset_io(ptdescr, 0, sizeof(pcsca_bd_t));
 360                 cpc_writew(&ptdescr->len, 0);
 361                 cpc_writeb(&ptdescr->status, 0);
 362         }
 363         rx_dma_buf_pt_init(card, ch);
 364 }
 365
 366 static void tx_dma_buf_check(pc300_t * card, int ch)
 367 {
 368         volatile pcsca_bd_t __iomem *ptdescr;
 369         int i;
 370         ucshort first_bd = card->chan[ch].tx_first_bd;
 371         ucshort next_bd = card->chan[ch].tx_next_bd;
 372
 373         printk("#CH%d: f_bd = %d(0x%08zx), n_bd = %d(0x%08zx)\n", ch,
 374                first_bd, TX_BD_ADDR(ch, first_bd),
 375                next_bd, TX_BD_ADDR(ch, next_bd));
 376         for (i = first_bd,
 377              ptdescr = (card->hw.rambase + TX_BD_ADDR(ch, first_bd));
 378              i != ((next_bd + 1) & (N_DMA_TX_BUF - 1));
 379              i = (i + 1) & (N_DMA_TX_BUF - 1),
 380                  ptdescr = (card->hw.rambase + TX_BD_ADDR(ch, i))) {
 381                 printk("\n CH%d TX%d: next=0x%x, ptbuf=0x%x, ST=0x%x, len=%d",
 382                        ch, i, cpc_readl(&ptdescr->next),
 383                        cpc_readl(&ptdescr->ptbuf),
 384                        cpc_readb(&ptdescr->status), cpc_readw(&ptdescr->len));
 385         }
 386         printk("\n");
 387 }
 388
 389 #ifdef  PC300_DEBUG_OTHER
 390 /* Show all TX buffer descriptors */
 391 static void tx1_dma_buf_check(pc300_t * card, int ch)
 392 {
 393         volatile pcsca_bd_t __iomem *ptdescr;
 394         int i;
 395         ucshort first_bd = card->chan[ch].tx_first_bd;
 396         ucshort next_bd = card->chan[ch].tx_next_bd;
 397         uclong scabase = card->hw.scabase;
 398
 399         printk ("\nnfree_tx_bd = %d \n", card->chan[ch].nfree_tx_bd);
 400         printk("#CH%d: f_bd = %d(0x%08x), n_bd = %d(0x%08x)\n", ch,
 401                first_bd, TX_BD_ADDR(ch, first_bd),
 402                next_bd, TX_BD_ADDR(ch, next_bd));
 403         printk("TX_CDA=0x%08x, TX_EDA=0x%08x\n",
 404                cpc_readl(scabase + DTX_REG(CDAL, ch)),
 405                cpc_readl(scabase + DTX_REG(EDAL, ch)));
 406         for (i = 0; i < N_DMA_TX_BUF; i++) {
 407                 ptdescr = (card->hw.rambase + TX_BD_ADDR(ch, i));
 408                 printk("\n CH%d TX%d: next=0x%x, ptbuf=0x%x, ST=0x%x, len=%d",
 409                        ch, i, cpc_readl(&ptdescr->next),
 410                        cpc_readl(&ptdescr->ptbuf),
 411                        cpc_readb(&ptdescr->status), cpc_readw(&ptdescr->len));
 412         }
 413         printk("\n");
 414 }
 415 #endif
 416
 417 static void rx_dma_buf_check(pc300_t * card, int ch)
 418 {
 419         volatile pcsca_bd_t __iomem *ptdescr;
 420         int i;
 421         ucshort first_bd = card->chan[ch].rx_first_bd;
 422         ucshort last_bd = card->chan[ch].rx_last_bd;
 423         int ch_factor;
 424
 425         ch_factor = ch * N_DMA_RX_BUF;
 426         printk("#CH%d: f_bd = %d, l_bd = %d\n", ch, first_bd, last_bd);
 427         for (i = 0, ptdescr = (card->hw.rambase +
 428                                               DMA_RX_BD_BASE + ch_factor * sizeof(pcsca_bd_t));
 429              i < N_DMA_RX_BUF; i++, ptdescr++) {
 430                 if (cpc_readb(&ptdescr->status) & DST_OSB)
 431                         printk ("\n CH%d RX%d: next=0x%x, ptbuf=0x%x, ST=0x%x, len=%d",
 432                                  ch, i, cpc_readl(&ptdescr->next),
 433                                  cpc_readl(&ptdescr->ptbuf),
 434                                  cpc_readb(&ptdescr->status),
 435                                  cpc_readw(&ptdescr->len));
 436         }
 437         printk("\n");
 438 }
 439
 440 int dma_get_rx_frame_size(pc300_t * card, int ch)
 441 {
 442         volatile pcsca_bd_t __iomem *ptdescr;
 443         ucshort first_bd = card->chan[ch].rx_first_bd;
 444         int rcvd = 0;
 445         volatile ucchar status;
 446
 447         ptdescr = (card->hw.rambase + RX_BD_ADDR(ch, first_bd));
 448         while ((status = cpc_readb(&ptdescr->status)) & DST_OSB) {
 449                 rcvd += cpc_readw(&ptdescr->len);
 450                 first_bd = (first_bd + 1) & (N_DMA_RX_BUF - 1);
 451                 if ((status & DST_EOM) || (first_bd == card->chan[ch].rx_last_bd)) {
 452                         /* Return the size of a good frame or incomplete bad frame
 453                         * (dma_buf_read will clean the buffer descriptors in this case). */
 454                         return (rcvd);
 455                 }
 456                 ptdescr = (card->hw.rambase + cpc_readl(&ptdescr->next));
 457         }
 458         return (-1);
 459 }
 460
 461 /*
 462  * dma_buf_write: writes a frame to the Tx DMA buffers
 463  * NOTE: this function writes one frame at a time.
 464  */
 465 int dma_buf_write(pc300_t * card, int ch, ucchar * ptdata, int len)
 466 {
 467         int i, nchar;
 468         volatile pcsca_bd_t __iomem *ptdescr;
 469         int tosend = len;
 470         ucchar nbuf = ((len - 1) / BD_DEF_LEN) + 1;
 471
 472         if (nbuf >= card->chan[ch].nfree_tx_bd) {
 473                 return -ENOMEM;
 474         }
 475
 476         for (i = 0; i < nbuf; i++) {
 477                 ptdescr = (card->hw.rambase +
 478                                           TX_BD_ADDR(ch, card->chan[ch].tx_next_bd));
 479                 nchar = cpc_min(BD_DEF_LEN, tosend);
 480                 if (cpc_readb(&ptdescr->status) & DST_OSB) {
 481                         memcpy_toio((card->hw.rambase + cpc_readl(&ptdescr->ptbuf)),
 482                                     &ptdata[len - tosend], nchar);
 483                         cpc_writew(&ptdescr->len, nchar);
 484                         card->chan[ch].nfree_tx_bd--;
 485                         if ((i + 1) == nbuf) {
 486                                 /* This must be the last BD to be used */
 487                                 cpc_writeb(&ptdescr->status, DST_EOM);
 488                         } else {
 489                                 cpc_writeb(&ptdescr->status, 0);
 490                         }
 491                 } else {
 492                         return -ENOMEM;
 493                 }
 494                 tosend -= nchar;
 495                 card->chan[ch].tx_next_bd =
 496                         (card->chan[ch].tx_next_bd + 1) & (N_DMA_TX_BUF - 1);
 497         }
 498         /* If it gets to here, it means we have sent the whole frame */
 499         return 0;
 500 }
 501
 502 /*
 503  * dma_buf_read: reads a frame from the Rx DMA buffers
 504  * NOTE: this function reads one frame at a time.
 505  */
 506 int dma_buf_read(pc300_t * card, int ch, struct sk_buff *skb)
 507 {
 508         int nchar;
 509         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
 510         volatile pcsca_bd_t __iomem *ptdescr;
 511         int rcvd = 0;
 512         volatile ucchar status;
 513
 514         ptdescr = (card->hw.rambase +
 515                                   RX_BD_ADDR(ch, chan->rx_first_bd));
 516         while ((status = cpc_readb(&ptdescr->status)) & DST_OSB) {
 517                 nchar = cpc_readw(&ptdescr->len);
 518                 if ((status & (DST_OVR | DST_CRC | DST_RBIT | DST_SHRT | DST_ABT))
 519                     || (nchar > BD_DEF_LEN)) {
 520
 521                         if (nchar > BD_DEF_LEN)
 522                                 status |= DST_RBIT;
 523                         rcvd = -status;
 524                         /* Discard remaining descriptors used by the bad frame */
 525                         while (chan->rx_first_bd != chan->rx_last_bd) {
 526                                 cpc_writeb(&ptdescr->status, 0);
 527                                 chan->rx_first_bd = (chan->rx_first_bd+1) & (N_DMA_RX_BUF-1);
 528                                 if (status & DST_EOM)
 529                                         break;
 530                                 ptdescr = (card->hw.rambase +
 531                                                           cpc_readl(&ptdescr->next));
 532                                 status = cpc_readb(&ptdescr->status);
 533                         }
 534                         break;
 535                 }
 536                 if (nchar != 0) {
 537                         if (skb) {
 538                                 memcpy_fromio(skb_put(skb, nchar),
 539                                  (card->hw.rambase+cpc_readl(&ptdescr->ptbuf)),nchar);
 540                         }
 541                         rcvd += nchar;
 542                 }
 543                 cpc_writeb(&ptdescr->status, 0);
 544                 cpc_writeb(&ptdescr->len, 0);
 545                 chan->rx_first_bd = (chan->rx_first_bd + 1) & (N_DMA_RX_BUF - 1);
 546
 547                 if (status & DST_EOM)
 548                         break;
 549
 550                 ptdescr = (card->hw.rambase + cpc_readl(&ptdescr->next));
 551         }
 552
 553         if (rcvd != 0) {
 554                 /* Update pointer */
 555                 chan->rx_last_bd = (chan->rx_first_bd - 1) & (N_DMA_RX_BUF - 1);
 556                 /* Update EDA */
 557                 cpc_writel(card->hw.scabase + DRX_REG(EDAL, ch),
 558                            RX_BD_ADDR(ch, chan->rx_last_bd));
 559         }
 560         return (rcvd);
 561 }
 562
 563 void tx_dma_stop(pc300_t * card, int ch)
 564 {
 565         void __iomem *scabase = card->hw.scabase;
 566         ucchar drr_ena_bit = 1 << (5 + 2 * ch);
 567         ucchar drr_rst_bit = 1 << (1 + 2 * ch);
 568
 569         /* Disable DMA */
 570         cpc_writeb(scabase + DRR, drr_ena_bit);
 571         cpc_writeb(scabase + DRR, drr_rst_bit & ~drr_ena_bit);
 572 }
 573
 574 void rx_dma_stop(pc300_t * card, int ch)
 575 {
 576         void __iomem *scabase = card->hw.scabase;
 577         ucchar drr_ena_bit = 1 << (4 + 2 * ch);
 578         ucchar drr_rst_bit = 1 << (2 * ch);
 579
 580         /* Disable DMA */
 581         cpc_writeb(scabase + DRR, drr_ena_bit);
 582         cpc_writeb(scabase + DRR, drr_rst_bit & ~drr_ena_bit);
 583 }
 584
 585 void rx_dma_start(pc300_t * card, int ch)
 586 {
 587         void __iomem *scabase = card->hw.scabase;
 588         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
 589
 590         /* Start DMA */
 591         cpc_writel(scabase + DRX_REG(CDAL, ch),
 592                    RX_BD_ADDR(ch, chan->rx_first_bd));
 593         if (cpc_readl(scabase + DRX_REG(CDAL,ch)) !=
 594                                   RX_BD_ADDR(ch, chan->rx_first_bd)) {
 595                 cpc_writel(scabase + DRX_REG(CDAL, ch),
 596                                    RX_BD_ADDR(ch, chan->rx_first_bd));
 597         }
 598         cpc_writel(scabase + DRX_REG(EDAL, ch),
 599                    RX_BD_ADDR(ch, chan->rx_last_bd));
 600         cpc_writew(scabase + DRX_REG(BFLL, ch), BD_DEF_LEN);
 601         cpc_writeb(scabase + DSR_RX(ch), DSR_DE);
 602         if (!(cpc_readb(scabase + DSR_RX(ch)) & DSR_DE)) {
 603         cpc_writeb(scabase + DSR_RX(ch), DSR_DE);
 604         }
 605 }
 606
 607 /*************************/
 608 /***   FALC Routines   ***/
 609 /*************************/
 610 void falc_issue_cmd(pc300_t * card, int ch, ucchar cmd)
 611 {
 612         void __iomem *falcbase = card->hw.falcbase;
 613         unsigned long i = 0;
 614
 615         while (cpc_readb(falcbase + F_REG(SIS, ch)) & SIS_CEC) {
 616                 if (i++ >= PC300_FALC_MAXLOOP) {
 617                         printk("%s: FALC command locked(cmd=0x%x).\n",
 618                                card->chan[ch].d.name, cmd);
 619                         break;
 620                 }
 621         }
 622         cpc_writeb(falcbase + F_REG(CMDR, ch), cmd);
 623 }
 624
 625 void falc_intr_enable(pc300_t * card, int ch)
 626 {
 627         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
 628         pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
 629         falc_t *pfalc = (falc_t *) & chan->falc;
 630         void __iomem *falcbase = card->hw.falcbase;
 631
 632         /* Interrupt pins are open-drain */
 633         cpc_writeb(falcbase + F_REG(IPC, ch),
 634                    cpc_readb(falcbase + F_REG(IPC, ch)) & ~IPC_IC0);
 635         /* Conters updated each second */
 636         cpc_writeb(falcbase + F_REG(FMR1, ch),
 637                    cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_ECM);
 638         /* Enable SEC and ES interrupts  */
 639         cpc_writeb(falcbase + F_REG(IMR3, ch),
 640                    cpc_readb(falcbase + F_REG(IMR3, ch)) & ~(IMR3_SEC | IMR3_ES));
 641         if (conf->fr_mode == PC300_FR_UNFRAMED) {
 642                 cpc_writeb(falcbase + F_REG(IMR4, ch),
 643                            cpc_readb(falcbase + F_REG(IMR4, ch)) & ~(IMR4_LOS));
 644         } else {
 645                 cpc_writeb(falcbase + F_REG(IMR4, ch),
 646                            cpc_readb(falcbase + F_REG(IMR4, ch)) &
 647                            ~(IMR4_LFA | IMR4_AIS | IMR4_LOS | IMR4_SLIP));
 648         }
 649         if (conf->media == IF_IFACE_T1) {
 650                 cpc_writeb(falcbase + F_REG(IMR3, ch),
 651                            cpc_readb(falcbase + F_REG(IMR3, ch)) & ~IMR3_LLBSC);
 652         } else {
 653                 cpc_writeb(falcbase + F_REG(IPC, ch),
 654                            cpc_readb(falcbase + F_REG(IPC, ch)) | IPC_SCI);
 655                 if (conf->fr_mode == PC300_FR_UNFRAMED) {
 656                         cpc_writeb(falcbase + F_REG(IMR2, ch),
 657                                    cpc_readb(falcbase + F_REG(IMR2, ch)) & ~(IMR2_LOS));
 658                 } else {
 659                         cpc_writeb(falcbase + F_REG(IMR2, ch),
 660                                    cpc_readb(falcbase + F_REG(IMR2, ch)) &
 661                                    ~(IMR2_FAR | IMR2_LFA | IMR2_AIS | IMR2_LOS));
 662                         if (pfalc->multiframe_mode) {
 663                                 cpc_writeb(falcbase + F_REG(IMR2, ch),
 664                                            cpc_readb(falcbase + F_REG(IMR2, ch)) &
 665                                            ~(IMR2_T400MS | IMR2_MFAR));
 666                         } else {
 667                                 cpc_writeb(falcbase + F_REG(IMR2, ch),
 668                                            cpc_readb(falcbase + F_REG(IMR2, ch)) |
 669                                            IMR2_T400MS | IMR2_MFAR);
 670                         }
 671                 }
 672         }
 673 }
 674
 675 void falc_open_timeslot(pc300_t * card, int ch, int timeslot)
 676 {
 677         void __iomem *falcbase = card->hw.falcbase;
 678         ucchar tshf = card->chan[ch].falc.offset;
 679
 680         cpc_writeb(falcbase + F_REG((ICB1 + (timeslot - tshf) / 8), ch),
 681                    cpc_readb(falcbase + F_REG((ICB1 + (timeslot - tshf) / 8), ch)) &
 682                         ~(0x80 >> ((timeslot - tshf) & 0x07)));
 683         cpc_writeb(falcbase + F_REG((TTR1 + timeslot / 8), ch),
 684                    cpc_readb(falcbase + F_REG((TTR1 + timeslot / 8), ch)) |
 685                         (0x80 >> (timeslot & 0x07)));
 686         cpc_writeb(falcbase + F_REG((RTR1 + timeslot / 8), ch),
 687                    cpc_readb(falcbase + F_REG((RTR1 + timeslot / 8), ch)) |
 688                         (0x80 >> (timeslot & 0x07)));
 689 }
 690
 691 void falc_close_timeslot(pc300_t * card, int ch, int timeslot)
 692 {
 693         void __iomem *falcbase = card->hw.falcbase;
 694         ucchar tshf = card->chan[ch].falc.offset;
 695
 696         cpc_writeb(falcbase + F_REG((ICB1 + (timeslot - tshf) / 8), ch),
 697                    cpc_readb(falcbase + F_REG((ICB1 + (timeslot - tshf) / 8), ch)) |
 698                    (0x80 >> ((timeslot - tshf) & 0x07)));
 699         cpc_writeb(falcbase + F_REG((TTR1 + timeslot / 8), ch),
 700                    cpc_readb(falcbase + F_REG((TTR1 + timeslot / 8), ch)) &
 701                    ~(0x80 >> (timeslot & 0x07)));
 702         cpc_writeb(falcbase + F_REG((RTR1 + timeslot / 8), ch),
 703                    cpc_readb(falcbase + F_REG((RTR1 + timeslot / 8), ch)) &
 704                    ~(0x80 >> (timeslot & 0x07)));
 705 }
 706
 707 void falc_close_all_timeslots(pc300_t * card, int ch)
 708 {
 709         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
 710         pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
 711         void __iomem *falcbase = card->hw.falcbase;
 712
 713         cpc_writeb(falcbase + F_REG(ICB1, ch), 0xff);
 714         cpc_writeb(falcbase + F_REG(TTR1, ch), 0);
 715         cpc_writeb(falcbase + F_REG(RTR1, ch), 0);
 716         cpc_writeb(falcbase + F_REG(ICB2, ch), 0xff);
 717         cpc_writeb(falcbase + F_REG(TTR2, ch), 0);
 718         cpc_writeb(falcbase + F_REG(RTR2, ch), 0);
 719         cpc_writeb(falcbase + F_REG(ICB3, ch), 0xff);
 720         cpc_writeb(falcbase + F_REG(TTR3, ch), 0);
 721         cpc_writeb(falcbase + F_REG(RTR3, ch), 0);
 722         if (conf->media == IF_IFACE_E1) {
 723                 cpc_writeb(falcbase + F_REG(ICB4, ch), 0xff);
 724                 cpc_writeb(falcbase + F_REG(TTR4, ch), 0);
 725                 cpc_writeb(falcbase + F_REG(RTR4, ch), 0);
 726         }
 727 }
 728
 729 void falc_open_all_timeslots(pc300_t * card, int ch)
 730 {
 731         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
 732         pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
 733         void __iomem *falcbase = card->hw.falcbase;
 734
 735         cpc_writeb(falcbase + F_REG(ICB1, ch), 0);
 736         if (conf->fr_mode == PC300_FR_UNFRAMED) {
 737                 cpc_writeb(falcbase + F_REG(TTR1, ch), 0xff);
 738                 cpc_writeb(falcbase + F_REG(RTR1, ch), 0xff);
 739         } else {
 740                 /* Timeslot 0 is never enabled */
 741                 cpc_writeb(falcbase + F_REG(TTR1, ch), 0x7f);
 742                 cpc_writeb(falcbase + F_REG(RTR1, ch), 0x7f);
 743         }
 744         cpc_writeb(falcbase + F_REG(ICB2, ch), 0);
 745         cpc_writeb(falcbase + F_REG(TTR2, ch), 0xff);
 746         cpc_writeb(falcbase + F_REG(RTR2, ch), 0xff);
 747         cpc_writeb(falcbase + F_REG(ICB3, ch), 0);
 748         cpc_writeb(falcbase + F_REG(TTR3, ch), 0xff);
 749         cpc_writeb(falcbase + F_REG(RTR3, ch), 0xff);
 750         if (conf->media == IF_IFACE_E1) {
 751                 cpc_writeb(falcbase + F_REG(ICB4, ch), 0);
 752                 cpc_writeb(falcbase + F_REG(TTR4, ch), 0xff);
 753                 cpc_writeb(falcbase + F_REG(RTR4, ch), 0xff);
 754         } else {
 755                 cpc_writeb(falcbase + F_REG(ICB4, ch), 0xff);
 756                 cpc_writeb(falcbase + F_REG(TTR4, ch), 0x80);
 757                 cpc_writeb(falcbase + F_REG(RTR4, ch), 0x80);
 758         }
 759 }
 760
 761 void falc_init_timeslot(pc300_t * card, int ch)
 762 {
 763         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
 764         pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
 765         falc_t *pfalc = (falc_t *) & chan->falc;
 766         int tslot;
 767
 768         for (tslot = 0; tslot < pfalc->num_channels; tslot++) {
 769                 if (conf->tslot_bitmap & (1 << tslot)) {
 770                         // Channel enabled
 771                         falc_open_timeslot(card, ch, tslot + 1);
 772                 } else {
 773                         // Channel disabled
 774                         falc_close_timeslot(card, ch, tslot + 1);
 775                 }
 776         }
 777 }
 778
 779 void falc_enable_comm(pc300_t * card, int ch)
 780 {
 781         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
 782         falc_t *pfalc = (falc_t *) & chan->falc;
 783
 784         if (pfalc->full_bandwidth) {
 785                 falc_open_all_timeslots(card, ch);
 786         } else {
 787                 falc_init_timeslot(card, ch);
 788         }
 789         // CTS/DCD ON
 790         cpc_writeb(card->hw.falcbase + card->hw.cpld_reg1,
 791                    cpc_readb(card->hw.falcbase + card->hw.cpld_reg1) &
 792                    ~((CPLD_REG1_FALC_DCD | CPLD_REG1_FALC_CTS) << (2 * ch)));
 793 }
 794
 795 void falc_disable_comm(pc300_t * card, int ch)
 796 {
 797         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
 798         falc_t *pfalc = (falc_t *) & chan->falc;
 799
 800         if (pfalc->loop_active != 2) {
 801                 falc_close_all_timeslots(card, ch);
 802         }
 803         // CTS/DCD OFF
 804         cpc_writeb(card->hw.falcbase + card->hw.cpld_reg1,
 805                    cpc_readb(card->hw.falcbase + card->hw.cpld_reg1) |
 806                    ((CPLD_REG1_FALC_DCD | CPLD_REG1_FALC_CTS) << (2 * ch)));
 807 }
 808
 809 void falc_init_t1(pc300_t * card, int ch)
 810 {
 811         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
 812         pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
 813         falc_t *pfalc = (falc_t *) & chan->falc;
 814         void __iomem *falcbase = card->hw.falcbase;
 815         ucchar dja = (ch ? (LIM2_DJA2 | LIM2_DJA1) : 0);
 816
 817         /* Switch to T1 mode (PCM 24) */
 818         cpc_writeb(falcbase + F_REG(FMR1, ch), FMR1_PMOD);
 819
 820         /* Wait 20 us for setup */
 821         udelay(20);
 822
 823         /* Transmit Buffer Size (1 frame) */
 824         cpc_writeb(falcbase + F_REG(SIC1, ch), SIC1_XBS0);
 825
 826         /* Clock mode */
 827         if (conf->phys_settings.clock_type == CLOCK_INT) { /* Master mode */
 828                 cpc_writeb(falcbase + F_REG(LIM0, ch),
 829                            cpc_readb(falcbase + F_REG(LIM0, ch)) | LIM0_MAS);
 830         } else { /* Slave mode */
 831                 cpc_writeb(falcbase + F_REG(LIM0, ch),
 832                            cpc_readb(falcbase + F_REG(LIM0, ch)) & ~LIM0_MAS);
 833                 cpc_writeb(falcbase + F_REG(LOOP, ch),
 834                            cpc_readb(falcbase + F_REG(LOOP, ch)) & ~LOOP_RTM);
 835         }
 836
 837         cpc_writeb(falcbase + F_REG(IPC, ch), IPC_SCI);
 838         cpc_writeb(falcbase + F_REG(FMR0, ch),
 839                    cpc_readb(falcbase + F_REG(FMR0, ch)) &
 840                    ~(FMR0_XC0 | FMR0_XC1 | FMR0_RC0 | FMR0_RC1));
 841
 842         switch (conf->lcode) {
 843                 case PC300_LC_AMI:
 844                         cpc_writeb(falcbase + F_REG(FMR0, ch),
 845                                    cpc_readb(falcbase + F_REG(FMR0, ch)) |
 846                                    FMR0_XC1 | FMR0_RC1);
 847                         /* Clear Channel register to ON for all channels */
 848                         cpc_writeb(falcbase + F_REG(CCB1, ch), 0xff);
 849                         cpc_writeb(falcbase + F_REG(CCB2, ch), 0xff);
 850                         cpc_writeb(falcbase + F_REG(CCB3, ch), 0xff);
 851                         break;
 852
 853                 case PC300_LC_B8ZS:
 854                         cpc_writeb(falcbase + F_REG(FMR0, ch),
 855                                    cpc_readb(falcbase + F_REG(FMR0, ch)) |
 856                                    FMR0_XC0 | FMR0_XC1 | FMR0_RC0 | FMR0_RC1);
 857                         break;
 858
 859                 case PC300_LC_NRZ:
 860                         cpc_writeb(falcbase + F_REG(FMR0, ch),
 861                                    cpc_readb(falcbase + F_REG(FMR0, ch)) | 0x00);
 862                         break;
 863         }
 864
 865         cpc_writeb(falcbase + F_REG(LIM0, ch),
 866                    cpc_readb(falcbase + F_REG(LIM0, ch)) | LIM0_ELOS);
 867         cpc_writeb(falcbase + F_REG(LIM0, ch),
 868                    cpc_readb(falcbase + F_REG(LIM0, ch)) & ~(LIM0_SCL1 | LIM0_SCL0));
 869         /* Set interface mode to 2 MBPS */
 870         cpc_writeb(falcbase + F_REG(FMR1, ch),
 871                    cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_IMOD);
 872
 873         switch (conf->fr_mode) {
 874                 case PC300_FR_ESF:
 875                         pfalc->multiframe_mode = 0;
 876                         cpc_writeb(falcbase + F_REG(FMR4, ch),
 877                                    cpc_readb(falcbase + F_REG(FMR4, ch)) | FMR4_FM1);
 878                         cpc_writeb(falcbase + F_REG(FMR1, ch),
 879                                    cpc_readb(falcbase + F_REG(FMR1, ch)) |
 880                                    FMR1_CRC | FMR1_EDL);
 881                         cpc_writeb(falcbase + F_REG(XDL1, ch), 0);
 882                         cpc_writeb(falcbase + F_REG(XDL2, ch), 0);
 883                         cpc_writeb(falcbase + F_REG(XDL3, ch), 0);
 884                         cpc_writeb(falcbase + F_REG(FMR0, ch),
 885                                    cpc_readb(falcbase + F_REG(FMR0, ch)) & ~FMR0_SRAF);
 886                         cpc_writeb(falcbase + F_REG(FMR2, ch),
 887                                    cpc_readb(falcbase + F_REG(FMR2,ch)) | FMR2_MCSP | FMR2_SSP);
 888                         break;
 889
 890                 case PC300_FR_D4:
 891                         pfalc->multiframe_mode = 1;
 892                         cpc_writeb(falcbase + F_REG(FMR4, ch),
 893                                    cpc_readb(falcbase + F_REG(FMR4, ch)) &
 894                                    ~(FMR4_FM1 | FMR4_FM0));
 895                         cpc_writeb(falcbase + F_REG(FMR0, ch),
 896                                    cpc_readb(falcbase + F_REG(FMR0, ch)) | FMR0_SRAF);
 897                         cpc_writeb(falcbase + F_REG(FMR2, ch),
 898                                    cpc_readb(falcbase + F_REG(FMR2, ch)) & ~FMR2_SSP);
 899                         break;
 900         }
 901
 902         /* Enable Automatic Resynchronization */
 903         cpc_writeb(falcbase + F_REG(FMR4, ch),
 904                    cpc_readb(falcbase + F_REG(FMR4, ch)) | FMR4_AUTO);
 905
 906         /* Transmit Automatic Remote Alarm */
 907         cpc_writeb(falcbase + F_REG(FMR2, ch),
 908                    cpc_readb(falcbase + F_REG(FMR2, ch)) | FMR2_AXRA);
 909
 910         /* Channel translation mode 1 : one to one */
 911         cpc_writeb(falcbase + F_REG(FMR1, ch),
 912                    cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_CTM);
 913
 914         /* No signaling */
 915         cpc_writeb(falcbase + F_REG(FMR1, ch),
 916                    cpc_readb(falcbase + F_REG(FMR1, ch)) & ~FMR1_SIGM);
 917         cpc_writeb(falcbase + F_REG(FMR5, ch),
 918                    cpc_readb(falcbase + F_REG(FMR5, ch)) &
 919                    ~(FMR5_EIBR | FMR5_SRS));
 920         cpc_writeb(falcbase + F_REG(CCR1, ch), 0);
 921
 922         cpc_writeb(falcbase + F_REG(LIM1, ch),
 923                    cpc_readb(falcbase + F_REG(LIM1, ch)) | LIM1_RIL0 | LIM1_RIL1);
 924
 925         switch (conf->lbo) {
 926                         /* Provides proper Line Build Out */
 927                 case PC300_LBO_0_DB:
 928                         cpc_writeb(falcbase + F_REG(LIM2, ch), (LIM2_LOS1 | dja));
 929                         cpc_writeb(falcbase + F_REG(XPM0, ch), 0x5a);
 930                         cpc_writeb(falcbase + F_REG(XPM1, ch), 0x8f);
 931                         cpc_writeb(falcbase + F_REG(XPM2, ch), 0x20);
 932                         break;
 933                 case PC300_LBO_7_5_DB:
 934                         cpc_writeb(falcbase + F_REG(LIM2, ch), (0x40 | LIM2_LOS1 | dja));
 935                         cpc_writeb(falcbase + F_REG(XPM0, ch), 0x11);
 936                         cpc_writeb(falcbase + F_REG(XPM1, ch), 0x02);
 937                         cpc_writeb(falcbase + F_REG(XPM2, ch), 0x20);
 938                         break;
 939                 case PC300_LBO_15_DB:
 940                         cpc_writeb(falcbase + F_REG(LIM2, ch), (0x80 | LIM2_LOS1 | dja));
 941                         cpc_writeb(falcbase + F_REG(XPM0, ch), 0x8e);
 942                         cpc_writeb(falcbase + F_REG(XPM1, ch), 0x01);
 943                         cpc_writeb(falcbase + F_REG(XPM2, ch), 0x20);
 944                         break;
 945                 case PC300_LBO_22_5_DB:
 946                         cpc_writeb(falcbase + F_REG(LIM2, ch), (0xc0 | LIM2_LOS1 | dja));
 947                         cpc_writeb(falcbase + F_REG(XPM0, ch), 0x09);
 948                         cpc_writeb(falcbase + F_REG(XPM1, ch), 0x01);
 949                         cpc_writeb(falcbase + F_REG(XPM2, ch), 0x20);
 950                         break;
 951         }
 952
 953         /* Transmit Clock-Slot Offset */
 954         cpc_writeb(falcbase + F_REG(XC0, ch),
 955                    cpc_readb(falcbase + F_REG(XC0, ch)) | 0x01);
 956         /* Transmit Time-slot Offset */
 957         cpc_writeb(falcbase + F_REG(XC1, ch), 0x3e);
 958         /* Receive  Clock-Slot offset */
 959         cpc_writeb(falcbase + F_REG(RC0, ch), 0x05);
 960         /* Receive  Time-slot offset */
 961         cpc_writeb(falcbase + F_REG(RC1, ch), 0x00);
 962
 963         /* LOS Detection after 176 consecutive 0s */
 964         cpc_writeb(falcbase + F_REG(PCDR, ch), 0x0a);
 965         /* LOS Recovery after 22 ones in the time window of PCD */
 966         cpc_writeb(falcbase + F_REG(PCRR, ch), 0x15);
 967
 968         cpc_writeb(falcbase + F_REG(IDLE, ch), 0x7f);
 969
 970         if (conf->fr_mode == PC300_FR_ESF_JAPAN) {
 971                 cpc_writeb(falcbase + F_REG(RC1, ch),
 972                            cpc_readb(falcbase + F_REG(RC1, ch)) | 0x80);
 973         }
 974
 975         falc_close_all_timeslots(card, ch);
 976 }
 977
 978 void falc_init_e1(pc300_t * card, int ch)
 979 {
 980         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
 981         pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
 982         falc_t *pfalc = (falc_t *) & chan->falc;
 983         void __iomem *falcbase = card->hw.falcbase;
 984         ucchar dja = (ch ? (LIM2_DJA2 | LIM2_DJA1) : 0);
 985
 986         /* Switch to E1 mode (PCM 30) */
 987         cpc_writeb(falcbase + F_REG(FMR1, ch),
 988                    cpc_readb(falcbase + F_REG(FMR1, ch)) & ~FMR1_PMOD);
 989
 990         /* Clock mode */
 991         if (conf->phys_settings.clock_type == CLOCK_INT) { /* Master mode */
 992                 cpc_writeb(falcbase + F_REG(LIM0, ch),
 993                            cpc_readb(falcbase + F_REG(LIM0, ch)) | LIM0_MAS);
 994         } else { /* Slave mode */
 995                 cpc_writeb(falcbase + F_REG(LIM0, ch),
 996                            cpc_readb(falcbase + F_REG(LIM0, ch)) & ~LIM0_MAS);
 997         }
 998         cpc_writeb(falcbase + F_REG(LOOP, ch),
 999                    cpc_readb(falcbase + F_REG(LOOP, ch)) & ~LOOP_SFM);
1000
1001         cpc_writeb(falcbase + F_REG(IPC, ch), IPC_SCI);
1002         cpc_writeb(falcbase + F_REG(FMR0, ch),
1003                    cpc_readb(falcbase + F_REG(FMR0, ch)) &
1004                    ~(FMR0_XC0 | FMR0_XC1 | FMR0_RC0 | FMR0_RC1));
1005
1006         switch (conf->lcode) {
1007                 case PC300_LC_AMI:
1008                         cpc_writeb(falcbase + F_REG(FMR0, ch),
1009                                    cpc_readb(falcbase + F_REG(FMR0, ch)) |
1010                                    FMR0_XC1 | FMR0_RC1);
1011                         break;
1012
1013                 case PC300_LC_HDB3:
1014                         cpc_writeb(falcbase + F_REG(FMR0, ch),
1015                                    cpc_readb(falcbase + F_REG(FMR0, ch)) |
1016                                    FMR0_XC0 | FMR0_XC1 | FMR0_RC0 | FMR0_RC1);
1017                         break;
1018
1019                 case PC300_LC_NRZ:
1020                         break;
1021         }
1022
1023         cpc_writeb(falcbase + F_REG(LIM0, ch),
1024                    cpc_readb(falcbase + F_REG(LIM0, ch)) & ~(LIM0_SCL1 | LIM0_SCL0));
1025         /* Set interface mode to 2 MBPS */
1026         cpc_writeb(falcbase + F_REG(FMR1, ch),
1027                    cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_IMOD);
1028
1029         cpc_writeb(falcbase + F_REG(XPM0, ch), 0x18);
1030         cpc_writeb(falcbase + F_REG(XPM1, ch), 0x03);
1031         cpc_writeb(falcbase + F_REG(XPM2, ch), 0x00);
1032
1033         switch (conf->fr_mode) {
1034                 case PC300_FR_MF_CRC4:
1035                         pfalc->multiframe_mode = 1;
1036                         cpc_writeb(falcbase + F_REG(FMR1, ch),
1037                                    cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_XFS);
1038                         cpc_writeb(falcbase + F_REG(FMR2, ch),
1039                                    cpc_readb(falcbase + F_REG(FMR2, ch)) | FMR2_RFS1);
1040                         cpc_writeb(falcbase + F_REG(FMR2, ch),
1041                                    cpc_readb(falcbase + F_REG(FMR2, ch)) & ~FMR2_RFS0);
1042                         cpc_writeb(falcbase + F_REG(FMR3, ch),
1043                                    cpc_readb(falcbase + F_REG(FMR3, ch)) & ~FMR3_EXTIW);
1044
1045                         /* MultiFrame Resynchronization */
1046                         cpc_writeb(falcbase + F_REG(FMR1, ch),
1047                                    cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_MFCS);
1048
1049                         /* Automatic Loss of Multiframe > 914 CRC errors */
1050                         cpc_writeb(falcbase + F_REG(FMR2, ch),
1051                                    cpc_readb(falcbase + F_REG(FMR2, ch)) | FMR2_ALMF);
1052
1053                         /* S1 and SI1/SI2 spare Bits set to 1 */
1054                         cpc_writeb(falcbase + F_REG(XSP, ch),
1055                                    cpc_readb(falcbase + F_REG(XSP, ch)) & ~XSP_AXS);
1056                         cpc_writeb(falcbase + F_REG(XSP, ch),
1057                                    cpc_readb(falcbase + F_REG(XSP, ch)) | XSP_EBP);
1058                         cpc_writeb(falcbase + F_REG(XSP, ch),
1059                                    cpc_readb(falcbase + F_REG(XSP, ch)) | XSP_XS13 | XSP_XS15);
1060
1061                         /* Automatic Force Resynchronization */
1062                         cpc_writeb(falcbase + F_REG(FMR1, ch),
1063                                    cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_AFR);
1064
1065                         /* Transmit Automatic Remote Alarm */
1066                         cpc_writeb(falcbase + F_REG(FMR2, ch),
1067                                    cpc_readb(falcbase + F_REG(FMR2, ch)) | FMR2_AXRA);
1068
1069                         /* Transmit Spare Bits for National Use (Y, Sn, Sa) */
1070                         cpc_writeb(falcbase + F_REG(XSW, ch),
1071                                    cpc_readb(falcbase + F_REG(XSW, ch)) |
1072                                    XSW_XY0 | XSW_XY1 | XSW_XY2 | XSW_XY3 | XSW_XY4);
1073                         break;
1074
1075                 case PC300_FR_MF_NON_CRC4:
1076                 case PC300_FR_D4:
1077                         pfalc->multiframe_mode = 0;
1078                         cpc_writeb(falcbase + F_REG(FMR1, ch),
1079                                    cpc_readb(falcbase + F_REG(FMR1, ch)) & ~FMR1_XFS);
1080                         cpc_writeb(falcbase + F_REG(FMR2, ch),
1081                                    cpc_readb(falcbase + F_REG(FMR2, ch)) &
1082                                    ~(FMR2_RFS1 | FMR2_RFS0));
1083                         cpc_writeb(falcbase + F_REG(XSW, ch),
1084                                    cpc_readb(falcbase + F_REG(XSW, ch)) | XSW_XSIS);
1085                         cpc_writeb(falcbase + F_REG(XSP, ch),
1086                                    cpc_readb(falcbase + F_REG(XSP, ch)) | XSP_XSIF);
1087
1088                         /* Automatic Force Resynchronization */
1089                         cpc_writeb(falcbase + F_REG(FMR1, ch),
1090                                    cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_AFR);
1091
1092                         /* Transmit Automatic Remote Alarm */
1093                         cpc_writeb(falcbase + F_REG(FMR2, ch),
1094                                    cpc_readb(falcbase + F_REG(FMR2, ch)) | FMR2_AXRA);
1095
1096                         /* Transmit Spare Bits for National Use (Y, Sn, Sa) */
1097                         cpc_writeb(falcbase + F_REG(XSW, ch),
1098                                    cpc_readb(falcbase + F_REG(XSW, ch)) |
1099                                    XSW_XY0 | XSW_XY1 | XSW_XY2 | XSW_XY3 | XSW_XY4);
1100                         break;
1101
1102                 case PC300_FR_UNFRAMED:
1103                         pfalc->multiframe_mode = 0;
1104                         cpc_writeb(falcbase + F_REG(FMR1, ch),
1105                                    cpc_readb(falcbase + F_REG(FMR1, ch)) & ~FMR1_XFS);
1106                         cpc_writeb(falcbase + F_REG(FMR2, ch),
1107                                    cpc_readb(falcbase + F_REG(FMR2, ch)) &
1108                                    ~(FMR2_RFS1 | FMR2_RFS0));
1109                         cpc_writeb(falcbase + F_REG(XSP, ch),
1110                                    cpc_readb(falcbase + F_REG(XSP, ch)) | XSP_TT0);
1111                         cpc_writeb(falcbase + F_REG(XSW, ch),
1112                                    cpc_readb(falcbase + F_REG(XSW, ch)) &
1113                                    ~(XSW_XTM|XSW_XY0|XSW_XY1|XSW_XY2|XSW_XY3|XSW_XY4));
1114                         cpc_writeb(falcbase + F_REG(TSWM, ch), 0xff);
1115                         cpc_writeb(falcbase + F_REG(FMR2, ch),
1116                                    cpc_readb(falcbase + F_REG(FMR2, ch)) |
1117                                    (FMR2_RTM | FMR2_DAIS));
1118                         cpc_writeb(falcbase + F_REG(FMR2, ch),
1119                                    cpc_readb(falcbase + F_REG(FMR2, ch)) & ~FMR2_AXRA);
1120                         cpc_writeb(falcbase + F_REG(FMR1, ch),
1121                                    cpc_readb(falcbase + F_REG(FMR1, ch)) & ~FMR1_AFR);
1122                         pfalc->sync = 1;
1123                         cpc_writeb(falcbase + card->hw.cpld_reg2,
1124                                    cpc_readb(falcbase + card->hw.cpld_reg2) |
1125                                    (CPLD_REG2_FALC_LED2 << (2 * ch)));
1126                         break;
1127         }
1128
1129         /* No signaling */
1130         cpc_writeb(falcbase + F_REG(XSP, ch),
1131                    cpc_readb(falcbase + F_REG(XSP, ch)) & ~XSP_CASEN);
1132         cpc_writeb(falcbase + F_REG(CCR1, ch), 0);
1133
1134         cpc_writeb(falcbase + F_REG(LIM1, ch),
1135                    cpc_readb(falcbase + F_REG(LIM1, ch)) | LIM1_RIL0 | LIM1_RIL1);
1136         cpc_writeb(falcbase + F_REG(LIM2, ch), (LIM2_LOS1 | dja));
1137
1138         /* Transmit Clock-Slot Offset */
1139         cpc_writeb(falcbase + F_REG(XC0, ch),
1140                    cpc_readb(falcbase + F_REG(XC0, ch)) | 0x01);
1141         /* Transmit Time-slot Offset */
1142         cpc_writeb(falcbase + F_REG(XC1, ch), 0x3e);
1143         /* Receive  Clock-Slot offset */
1144         cpc_writeb(falcbase + F_REG(RC0, ch), 0x05);
1145         /* Receive  Time-slot offset */
1146         cpc_writeb(falcbase + F_REG(RC1, ch), 0x00);
1147
1148         /* LOS Detection after 176 consecutive 0s */
1149         cpc_writeb(falcbase + F_REG(PCDR, ch), 0x0a);
1150         /* LOS Recovery after 22 ones in the time window of PCD */
1151         cpc_writeb(falcbase + F_REG(PCRR, ch), 0x15);
1152
1153         cpc_writeb(falcbase + F_REG(IDLE, ch), 0x7f);
1154
1155         falc_close_all_timeslots(card, ch);
1156 }
1157
1158 void falc_init_hdlc(pc300_t * card, int ch)
1159 {
1160         void __iomem *falcbase = card->hw.falcbase;
1161         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1162         pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1163
1164         /* Enable transparent data transfer */
1165         if (conf->fr_mode == PC300_FR_UNFRAMED) {
1166                 cpc_writeb(falcbase + F_REG(MODE, ch), 0);
1167         } else {
1168                 cpc_writeb(falcbase + F_REG(MODE, ch),
1169                            cpc_readb(falcbase + F_REG(MODE, ch)) |
1170                            (MODE_HRAC | MODE_MDS2));
1171                 cpc_writeb(falcbase + F_REG(RAH2, ch), 0xff);
1172                 cpc_writeb(falcbase + F_REG(RAH1, ch), 0xff);
1173                 cpc_writeb(falcbase + F_REG(RAL2, ch), 0xff);
1174                 cpc_writeb(falcbase + F_REG(RAL1, ch), 0xff);
1175         }
1176
1177         /* Tx/Rx reset  */
1178         falc_issue_cmd(card, ch, CMDR_RRES | CMDR_XRES | CMDR_SRES);
1179
1180         /* Enable interrupt sources */
1181         falc_intr_enable(card, ch);
1182 }
1183
1184 void te_config(pc300_t * card, int ch)
1185 {
1186         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1187         pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1188         falc_t *pfalc = (falc_t *) & chan->falc;
1189         void __iomem *falcbase = card->hw.falcbase;
1190         ucchar dummy;
1191         unsigned long flags;
1192
1193         memset(pfalc, 0, sizeof(falc_t));
1194         switch (conf->media) {
1195                 case IF_IFACE_T1:
1196                         pfalc->num_channels = NUM_OF_T1_CHANNELS;
1197                         pfalc->offset = 1;
1198                         break;
1199                 case IF_IFACE_E1:
1200                         pfalc->num_channels = NUM_OF_E1_CHANNELS;
1201                         pfalc->offset = 0;
1202                         break;
1203         }
1204         if (conf->tslot_bitmap == 0xffffffffUL)
1205                 pfalc->full_bandwidth = 1;
1206         else
1207                 pfalc->full_bandwidth = 0;
1208
1209         CPC_LOCK(card, flags);
1210         /* Reset the FALC chip */
1211         cpc_writeb(card->hw.falcbase + card->hw.cpld_reg1,
1212                    cpc_readb(card->hw.falcbase + card->hw.cpld_reg1) |
1213                    (CPLD_REG1_FALC_RESET << (2 * ch)));
1214         udelay(10000);
1215         cpc_writeb(card->hw.falcbase + card->hw.cpld_reg1,
1216                    cpc_readb(card->hw.falcbase + card->hw.cpld_reg1) &
1217                    ~(CPLD_REG1_FALC_RESET << (2 * ch)));
1218
1219         if (conf->media == IF_IFACE_T1) {
1220                 falc_init_t1(card, ch);
1221         } else {
1222                 falc_init_e1(card, ch);
1223         }
1224         falc_init_hdlc(card, ch);
1225         if (conf->rx_sens == PC300_RX_SENS_SH) {
1226                 cpc_writeb(falcbase + F_REG(LIM0, ch),
1227                            cpc_readb(falcbase + F_REG(LIM0, ch)) & ~LIM0_EQON);
1228         } else {
1229                 cpc_writeb(falcbase + F_REG(LIM0, ch),
1230                            cpc_readb(falcbase + F_REG(LIM0, ch)) | LIM0_EQON);
1231         }
1232         cpc_writeb(card->hw.falcbase + card->hw.cpld_reg2,
1233                    cpc_readb(card->hw.falcbase + card->hw.cpld_reg2) |
1234                    ((CPLD_REG2_FALC_TX_CLK | CPLD_REG2_FALC_RX_CLK) << (2 * ch)));
1235
1236         /* Clear all interrupt registers */
1237         dummy = cpc_readb(falcbase + F_REG(FISR0, ch)) +
1238                 cpc_readb(falcbase + F_REG(FISR1, ch)) +
1239                 cpc_readb(falcbase + F_REG(FISR2, ch)) +
1240                 cpc_readb(falcbase + F_REG(FISR3, ch));
1241         CPC_UNLOCK(card, flags);
1242 }
1243
1244 void falc_check_status(pc300_t * card, int ch, unsigned char frs0)
1245 {
1246         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1247         pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1248         falc_t *pfalc = (falc_t *) & chan->falc;
1249         void __iomem *falcbase = card->hw.falcbase;
1250
1251         /* Verify LOS */
1252         if (frs0 & FRS0_LOS) {
1253                 if (!pfalc->red_alarm) {
1254                         pfalc->red_alarm = 1;
1255                         pfalc->los++;
1256                         if (!pfalc->blue_alarm) {
1257                                 // EVENT_FALC_ABNORMAL
1258                                 if (conf->media == IF_IFACE_T1) {
1259                                         /* Disable this interrupt as it may otherwise interfere
1260                                          * with other working boards. */
1261                                         cpc_writeb(falcbase + F_REG(IMR0, ch),
1262                                                    cpc_readb(falcbase + F_REG(IMR0, ch))
1263                                                    | IMR0_PDEN);
1264                                 }
1265                                 falc_disable_comm(card, ch);
1266                                 // EVENT_FALC_ABNORMAL
1267                         }
1268                 }
1269         } else {
1270                 if (pfalc->red_alarm) {
1271                         pfalc->red_alarm = 0;
1272                         pfalc->losr++;
1273                 }
1274         }
1275
1276         if (conf->fr_mode != PC300_FR_UNFRAMED) {
1277                 /* Verify AIS alarm */
1278                 if (frs0 & FRS0_AIS) {
1279                         if (!pfalc->blue_alarm) {
1280                                 pfalc->blue_alarm = 1;
1281                                 pfalc->ais++;
1282                                 // EVENT_AIS
1283                                 if (conf->media == IF_IFACE_T1) {
1284                                         /* Disable this interrupt as it may otherwise interfere with                       other working boards. */
1285                                         cpc_writeb(falcbase + F_REG(IMR0, ch),
1286                                                    cpc_readb(falcbase + F_REG(IMR0, ch)) | IMR0_PDEN);
1287                                 }
1288                                 falc_disable_comm(card, ch);
1289                                 // EVENT_AIS
1290                         }
1291                 } else {
1292                         pfalc->blue_alarm = 0;
1293                 }
1294
1295                 /* Verify LFA */
1296                 if (frs0 & FRS0_LFA) {
1297                         if (!pfalc->loss_fa) {
1298                                 pfalc->loss_fa = 1;
1299                                 pfalc->lfa++;
1300                                 if (!pfalc->blue_alarm && !pfalc->red_alarm) {
1301                                         // EVENT_FALC_ABNORMAL
1302                                         if (conf->media == IF_IFACE_T1) {
1303                                                 /* Disable this interrupt as it may otherwise
1304                                                  * interfere with other working boards. */
1305                                                 cpc_writeb(falcbase + F_REG(IMR0, ch),
1306                                                            cpc_readb(falcbase + F_REG(IMR0, ch))
1307                                                            | IMR0_PDEN);
1308                                         }
1309                                         falc_disable_comm(card, ch);
1310                                         // EVENT_FALC_ABNORMAL
1311                                 }
1312                         }
1313                 } else {
1314                         if (pfalc->loss_fa) {
1315                                 pfalc->loss_fa = 0;
1316                                 pfalc->farec++;
1317                         }
1318                 }
1319
1320                 /* Verify LMFA */
1321                 if (pfalc->multiframe_mode && (frs0 & FRS0_LMFA)) {
1322                         /* D4 or CRC4 frame mode */
1323                         if (!pfalc->loss_mfa) {
1324                                 pfalc->loss_mfa = 1;
1325                                 pfalc->lmfa++;
1326                                 if (!pfalc->blue_alarm && !pfalc->red_alarm &&
1327                                     !pfalc->loss_fa) {
1328                                         // EVENT_FALC_ABNORMAL
1329                                         if (conf->media == IF_IFACE_T1) {
1330                                                 /* Disable this interrupt as it may otherwise
1331                                                  * interfere with other working boards. */
1332                                                 cpc_writeb(falcbase + F_REG(IMR0, ch),
1333                                                            cpc_readb(falcbase + F_REG(IMR0, ch))
1334                                                            | IMR0_PDEN);
1335                                         }
1336                                         falc_disable_comm(card, ch);
1337                                         // EVENT_FALC_ABNORMAL
1338                                 }
1339                         }
1340                 } else {
1341                         pfalc->loss_mfa = 0;
1342                 }
1343
1344                 /* Verify Remote Alarm */
1345                 if (frs0 & FRS0_RRA) {
1346                         if (!pfalc->yellow_alarm) {
1347                                 pfalc->yellow_alarm = 1;
1348                                 pfalc->rai++;
1349                                 if (pfalc->sync) {
1350                                         // EVENT_RAI
1351                                         falc_disable_comm(card, ch);
1352                                         // EVENT_RAI
1353                                 }
1354                         }
1355                 } else {
1356                         pfalc->yellow_alarm = 0;
1357                 }
1358         } /* if !PC300_UNFRAMED */
1359
1360         if (pfalc->red_alarm || pfalc->loss_fa ||
1361             pfalc->loss_mfa || pfalc->blue_alarm) {
1362                 if (pfalc->sync) {
1363                         pfalc->sync = 0;
1364                         chan->d.line_off++;
1365                         cpc_writeb(falcbase + card->hw.cpld_reg2,
1366                                    cpc_readb(falcbase + card->hw.cpld_reg2) &
1367                                    ~(CPLD_REG2_FALC_LED2 << (2 * ch)));
1368                 }
1369         } else {
1370                 if (!pfalc->sync) {
1371                         pfalc->sync = 1;
1372                         chan->d.line_on++;
1373                         cpc_writeb(falcbase + card->hw.cpld_reg2,
1374                                    cpc_readb(falcbase + card->hw.cpld_reg2) |
1375                                    (CPLD_REG2_FALC_LED2 << (2 * ch)));
1376                 }
1377         }
1378
1379         if (pfalc->sync && !pfalc->yellow_alarm) {
1380                 if (!pfalc->active) {
1381                         // EVENT_FALC_NORMAL
1382                         if (pfalc->loop_active) {
1383                                 return;
1384                         }
1385                         if (conf->media == IF_IFACE_T1) {
1386                                 cpc_writeb(falcbase + F_REG(IMR0, ch),
1387                                            cpc_readb(falcbase + F_REG(IMR0, ch)) & ~IMR0_PDEN);
1388                         }
1389                         falc_enable_comm(card, ch);
1390                         // EVENT_FALC_NORMAL
1391                         pfalc->active = 1;
1392                 }
1393         } else {
1394                 if (pfalc->active) {
1395                         pfalc->active = 0;
1396                 }
1397         }
1398 }
1399
1400 void falc_update_stats(pc300_t * card, int ch)
1401 {
1402         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1403         pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1404         falc_t *pfalc = (falc_t *) & chan->falc;
1405         void __iomem *falcbase = card->hw.falcbase;
1406         ucshort counter;
1407
1408         counter = cpc_readb(falcbase + F_REG(FECL, ch));
1409         counter |= cpc_readb(falcbase + F_REG(FECH, ch)) << 8;
1410         pfalc->fec += counter;
1411
1412         counter = cpc_readb(falcbase + F_REG(CVCL, ch));
1413         counter |= cpc_readb(falcbase + F_REG(CVCH, ch)) << 8;
1414         pfalc->cvc += counter;
1415
1416         counter = cpc_readb(falcbase + F_REG(CECL, ch));
1417         counter |= cpc_readb(falcbase + F_REG(CECH, ch)) << 8;
1418         pfalc->cec += counter;
1419
1420         counter = cpc_readb(falcbase + F_REG(EBCL, ch));
1421         counter |= cpc_readb(falcbase + F_REG(EBCH, ch)) << 8;
1422         pfalc->ebc += counter;
1423
1424         if (cpc_readb(falcbase + F_REG(LCR1, ch)) & LCR1_EPRM) {
1425                 mdelay(10);
1426                 counter = cpc_readb(falcbase + F_REG(BECL, ch));
1427                 counter |= cpc_readb(falcbase + F_REG(BECH, ch)) << 8;
1428                 pfalc->bec += counter;
1429
1430                 if (((conf->media == IF_IFACE_T1) &&
1431                      (cpc_readb(falcbase + F_REG(FRS1, ch)) & FRS1_LLBAD) &&
1432                      (!(cpc_readb(falcbase + F_REG(FRS1, ch)) & FRS1_PDEN)))
1433                     ||
1434                     ((conf->media == IF_IFACE_E1) &&
1435                      (cpc_readb(falcbase + F_REG(RSP, ch)) & RSP_LLBAD))) {
1436                         pfalc->prbs = 2;
1437                 } else {
1438                         pfalc->prbs = 1;
1439                 }
1440         }
1441 }
1442
1443 /*----------------------------------------------------------------------------
1444  * falc_remote_loop
1445  *----------------------------------------------------------------------------
1446  * Description: In the remote loopback mode the clock and data recovered
1447  *              from the line inputs RL1/2 or RDIP/RDIN are routed back
1448  *              to the line outputs XL1/2 or XDOP/XDON via the analog
1449  *              transmitter. As in normal mode they are processsed by
1450  *              the synchronizer and then sent to the system interface.
1451  *----------------------------------------------------------------------------
1452  */
1453 void falc_remote_loop(pc300_t * card, int ch, int loop_on)
1454 {
1455         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1456         pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1457         falc_t *pfalc = (falc_t *) & chan->falc;
1458         void __iomem *falcbase = card->hw.falcbase;
1459
1460         if (loop_on) {
1461                 // EVENT_FALC_ABNORMAL
1462                 if (conf->media == IF_IFACE_T1) {
1463                         /* Disable this interrupt as it may otherwise interfere with
1464                          * other working boards. */
1465                         cpc_writeb(falcbase + F_REG(IMR0, ch),
1466                                    cpc_readb(falcbase + F_REG(IMR0, ch)) | IMR0_PDEN);
1467                 }
1468                 falc_disable_comm(card, ch);
1469                 // EVENT_FALC_ABNORMAL
1470                 cpc_writeb(falcbase + F_REG(LIM1, ch),
1471                            cpc_readb(falcbase + F_REG(LIM1, ch)) | LIM1_RL);
1472                 pfalc->loop_active = 1;
1473         } else {
1474                 cpc_writeb(falcbase + F_REG(LIM1, ch),
1475                            cpc_readb(falcbase + F_REG(LIM1, ch)) & ~LIM1_RL);
1476                 pfalc->sync = 0;
1477                 cpc_writeb(falcbase + card->hw.cpld_reg2,
1478                            cpc_readb(falcbase + card->hw.cpld_reg2) &
1479                            ~(CPLD_REG2_FALC_LED2 << (2 * ch)));
1480                 pfalc->active = 0;
1481                 falc_issue_cmd(card, ch, CMDR_XRES);
1482                 pfalc->loop_active = 0;
1483         }
1484 }
1485
1486 /*----------------------------------------------------------------------------
1487  * falc_local_loop
1488  *----------------------------------------------------------------------------
1489  * Description: The local loopback mode disconnects the receive lines
1490  *              RL1/RL2 resp. RDIP/RDIN from the receiver. Instead of the
1491  *              signals coming from the line the data provided by system
1492  *              interface are routed through the analog receiver back to
1493  *              the system interface. The unipolar bit stream will be
1494  *              undisturbed transmitted on the line. Receiver and transmitter
1495  *              coding must be identical.
1496  *----------------------------------------------------------------------------
1497  */
1498 void falc_local_loop(pc300_t * card, int ch, int loop_on)
1499 {
1500         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1501         falc_t *pfalc = (falc_t *) & chan->falc;
1502         void __iomem *falcbase = card->hw.falcbase;
1503
1504         if (loop_on) {
1505                 cpc_writeb(falcbase + F_REG(LIM0, ch),
1506                            cpc_readb(falcbase + F_REG(LIM0, ch)) | LIM0_LL);
1507                 pfalc->loop_active = 1;
1508         } else {
1509                 cpc_writeb(falcbase + F_REG(LIM0, ch),
1510                            cpc_readb(falcbase + F_REG(LIM0, ch)) & ~LIM0_LL);
1511                 pfalc->loop_active = 0;
1512         }
1513 }
1514
1515 /*----------------------------------------------------------------------------
1516  * falc_payload_loop
1517  *----------------------------------------------------------------------------
1518  * Description: This routine allows to enable/disable payload loopback.
1519  *              When the payload loop is activated, the received 192 bits
1520  *              of payload data will be looped back to the transmit
1521  *              direction. The framing bits, CRC6 and DL bits are not
1522  *              looped. They are originated by the FALC-LH transmitter.
1523  *----------------------------------------------------------------------------
1524  */
1525 void falc_payload_loop(pc300_t * card, int ch, int loop_on)
1526 {
1527         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1528         pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1529         falc_t *pfalc = (falc_t *) & chan->falc;
1530         void __iomem *falcbase = card->hw.falcbase;
1531
1532         if (loop_on) {
1533                 // EVENT_FALC_ABNORMAL
1534                 if (conf->media == IF_IFACE_T1) {
1535                         /* Disable this interrupt as it may otherwise interfere with
1536                          * other working boards. */
1537                         cpc_writeb(falcbase + F_REG(IMR0, ch),
1538                                    cpc_readb(falcbase + F_REG(IMR0, ch)) | IMR0_PDEN);
1539                 }
1540                 falc_disable_comm(card, ch);
1541                 // EVENT_FALC_ABNORMAL
1542                 cpc_writeb(falcbase + F_REG(FMR2, ch),
1543                            cpc_readb(falcbase + F_REG(FMR2, ch)) | FMR2_PLB);
1544                 if (conf->media == IF_IFACE_T1) {
1545                         cpc_writeb(falcbase + F_REG(FMR4, ch),
1546                                    cpc_readb(falcbase + F_REG(FMR4, ch)) | FMR4_TM);
1547                 } else {
1548                         cpc_writeb(falcbase + F_REG(FMR5, ch),
1549                                    cpc_readb(falcbase + F_REG(FMR5, ch)) | XSP_TT0);
1550                 }
1551                 falc_open_all_timeslots(card, ch);
1552                 pfalc->loop_active = 2;
1553         } else {
1554                 cpc_writeb(falcbase + F_REG(FMR2, ch),
1555                            cpc_readb(falcbase + F_REG(FMR2, ch)) & ~FMR2_PLB);
1556                 if (conf->media == IF_IFACE_T1) {
1557                         cpc_writeb(falcbase + F_REG(FMR4, ch),
1558                                    cpc_readb(falcbase + F_REG(FMR4, ch)) & ~FMR4_TM);
1559                 } else {
1560                         cpc_writeb(falcbase + F_REG(FMR5, ch),
1561                                    cpc_readb(falcbase + F_REG(FMR5, ch)) & ~XSP_TT0);
1562                 }
1563                 pfalc->sync = 0;
1564                 cpc_writeb(falcbase + card->hw.cpld_reg2,
1565                            cpc_readb(falcbase + card->hw.cpld_reg2) &
1566                            ~(CPLD_REG2_FALC_LED2 << (2 * ch)));
1567                 pfalc->active = 0;
1568                 falc_issue_cmd(card, ch, CMDR_XRES);
1569                 pfalc->loop_active = 0;
1570         }
1571 }
1572
1573 /*----------------------------------------------------------------------------
1574  * turn_off_xlu
1575  *----------------------------------------------------------------------------
1576  * Description: Turns XLU bit off in the proper register
1577  *----------------------------------------------------------------------------
1578  */
1579 void turn_off_xlu(pc300_t * card, int ch)
1580 {
1581         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1582         pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1583         void __iomem *falcbase = card->hw.falcbase;
1584
1585         if (conf->media == IF_IFACE_T1) {
1586                 cpc_writeb(falcbase + F_REG(FMR5, ch),
1587                            cpc_readb(falcbase + F_REG(FMR5, ch)) & ~FMR5_XLU);
1588         } else {
1589                 cpc_writeb(falcbase + F_REG(FMR3, ch),
1590                            cpc_readb(falcbase + F_REG(FMR3, ch)) & ~FMR3_XLU);
1591         }
1592 }
1593
1594 /*----------------------------------------------------------------------------
1595  * turn_off_xld
1596  *----------------------------------------------------------------------------
1597  * Description: Turns XLD bit off in the proper register
1598  *----------------------------------------------------------------------------
1599  */
1600 void turn_off_xld(pc300_t * card, int ch)
1601 {
1602         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1603         pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1604         void __iomem *falcbase = card->hw.falcbase;
1605
1606         if (conf->media == IF_IFACE_T1) {
1607                 cpc_writeb(falcbase + F_REG(FMR5, ch),
1608                            cpc_readb(falcbase + F_REG(FMR5, ch)) & ~FMR5_XLD);
1609         } else {
1610                 cpc_writeb(falcbase + F_REG(FMR3, ch),
1611                            cpc_readb(falcbase + F_REG(FMR3, ch)) & ~FMR3_XLD);
1612         }
1613 }
1614
1615 /*----------------------------------------------------------------------------
1616  * falc_generate_loop_up_code
1617  *----------------------------------------------------------------------------
1618  * Description: This routine writes the proper FALC chip register in order
1619  *              to generate a LOOP activation code over a T1/E1 line.
1620  *----------------------------------------------------------------------------
1621  */
1622 void falc_generate_loop_up_code(pc300_t * card, int ch)
1623 {
1624         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1625         pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1626         falc_t *pfalc = (falc_t *) & chan->falc;
1627         void __iomem *falcbase = card->hw.falcbase;
1628
1629         if (conf->media == IF_IFACE_T1) {
1630                 cpc_writeb(falcbase + F_REG(FMR5, ch),
1631                            cpc_readb(falcbase + F_REG(FMR5, ch)) | FMR5_XLU);
1632         } else {
1633                 cpc_writeb(falcbase + F_REG(FMR3, ch),
1634                            cpc_readb(falcbase + F_REG(FMR3, ch)) | FMR3_XLU);
1635         }
1636         // EVENT_FALC_ABNORMAL
1637         if (conf->media == IF_IFACE_T1) {
1638                 /* Disable this interrupt as it may otherwise interfere with
1639                  * other working boards. */
1640                 cpc_writeb(falcbase + F_REG(IMR0, ch),
1641                            cpc_readb(falcbase + F_REG(IMR0, ch)) | IMR0_PDEN);
1642         }
1643         falc_disable_comm(card, ch);
1644         // EVENT_FALC_ABNORMAL
1645         pfalc->loop_gen = 1;
1646 }
1647
1648 /*----------------------------------------------------------------------------
1649  * falc_generate_loop_down_code
1650  *----------------------------------------------------------------------------
1651  * Description: This routine writes the proper FALC chip register in order
1652  *              to generate a LOOP deactivation code over a T1/E1 line.
1653  *----------------------------------------------------------------------------
1654  */
1655 void falc_generate_loop_down_code(pc300_t * card, int ch)
1656 {
1657         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1658         pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1659         falc_t *pfalc = (falc_t *) & chan->falc;
1660         void __iomem *falcbase = card->hw.falcbase;
1661
1662         if (conf->media == IF_IFACE_T1) {
1663                 cpc_writeb(falcbase + F_REG(FMR5, ch),
1664                            cpc_readb(falcbase + F_REG(FMR5, ch)) | FMR5_XLD);
1665         } else {
1666                 cpc_writeb(falcbase + F_REG(FMR3, ch),
1667                            cpc_readb(falcbase + F_REG(FMR3, ch)) | FMR3_XLD);
1668         }
1669         pfalc->sync = 0;
1670         cpc_writeb(falcbase + card->hw.cpld_reg2,
1671                    cpc_readb(falcbase + card->hw.cpld_reg2) &
1672                    ~(CPLD_REG2_FALC_LED2 << (2 * ch)));
1673         pfalc->active = 0;
1674 //?    falc_issue_cmd(card, ch, CMDR_XRES);
1675         pfalc->loop_gen = 0;
1676 }
1677
1678 /*----------------------------------------------------------------------------
1679  * falc_pattern_test
1680  *----------------------------------------------------------------------------
1681  * Description: This routine generates a pattern code and checks
1682  *              it on the reception side.
1683  *----------------------------------------------------------------------------
1684  */
1685 void falc_pattern_test(pc300_t * card, int ch, unsigned int activate)
1686 {
1687         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1688         pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1689         falc_t *pfalc = (falc_t *) & chan->falc;
1690         void __iomem *falcbase = card->hw.falcbase;
1691
1692         if (activate) {
1693                 pfalc->prbs = 1;
1694                 pfalc->bec = 0;
1695                 if (conf->media == IF_IFACE_T1) {
1696                         /* Disable local loop activation/deactivation detect */
1697                         cpc_writeb(falcbase + F_REG(IMR3, ch),
1698                                    cpc_readb(falcbase + F_REG(IMR3, ch)) | IMR3_LLBSC);
1699                 } else {
1700                         /* Disable local loop activation/deactivation detect */
1701                         cpc_writeb(falcbase + F_REG(IMR1, ch),
1702                                    cpc_readb(falcbase + F_REG(IMR1, ch)) | IMR1_LLBSC);
1703                 }
1704                 /* Activates generation and monitoring of PRBS
1705                  * (Pseudo Random Bit Sequence) */
1706                 cpc_writeb(falcbase + F_REG(LCR1, ch),
1707                            cpc_readb(falcbase + F_REG(LCR1, ch)) | LCR1_EPRM | LCR1_XPRBS);
1708         } else {
1709                 pfalc->prbs = 0;
1710                 /* Deactivates generation and monitoring of PRBS
1711                  * (Pseudo Random Bit Sequence) */
1712                 cpc_writeb(falcbase + F_REG(LCR1, ch),
1713                            cpc_readb(falcbase+F_REG(LCR1,ch)) & ~(LCR1_EPRM | LCR1_XPRBS));
1714                 if (conf->media == IF_IFACE_T1) {
1715                         /* Enable local loop activation/deactivation detect */
1716                         cpc_writeb(falcbase + F_REG(IMR3, ch),
1717                                    cpc_readb(falcbase + F_REG(IMR3, ch)) & ~IMR3_LLBSC);
1718                 } else {
1719                         /* Enable local loop activation/deactivation detect */
1720                         cpc_writeb(falcbase + F_REG(IMR1, ch),
1721                                    cpc_readb(falcbase + F_REG(IMR1, ch)) & ~IMR1_LLBSC);
1722                 }
1723         }
1724 }
1725
1726 /*----------------------------------------------------------------------------
1727  * falc_pattern_test_error
1728  *----------------------------------------------------------------------------
1729  * Description: This routine returns the bit error counter value
1730  *----------------------------------------------------------------------------
1731  */
1732 ucshort falc_pattern_test_error(pc300_t * card, int ch)
1733 {
1734         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1735         falc_t *pfalc = (falc_t *) & chan->falc;
1736
1737         return (pfalc->bec);
1738 }
1739
1740 /**********************************/
1741 /***   Net Interface Routines   ***/
1742 /**********************************/
1743
1744 static void
1745 cpc_trace(struct net_device *dev, struct sk_buff *skb_main, char rx_tx)
1746 {
1747         struct sk_buff *skb;
1748
1749         if ((skb = dev_alloc_skb(10 + skb_main->len)) == NULL) {
1750                 printk("%s: out of memory\n", dev->name);
1751                 return;
1752         }
1753         skb_put(skb, 10 + skb_main->len);
1754
1755         skb->dev = dev;
1756         skb->protocol = htons(ETH_P_CUST);
1757         skb->mac.raw = skb->data;
1758         skb->pkt_type = PACKET_HOST;
1759         skb->len = 10 + skb_main->len;
1760
1761         memcpy(skb->data, dev->name, 5);
1762         skb->data[5] = '[';
1763         skb->data[6] = rx_tx;
1764         skb->data[7] = ']';
1765         skb->data[8] = ':';
1766         skb->data[9] = ' ';
1767         memcpy(&skb->data[10], skb_main->data, skb_main->len);
1768
1769         netif_rx(skb);
1770 }
1771
1772 void cpc_tx_timeout(struct net_device *dev)
1773 {
1774         pc300dev_t *d = (pc300dev_t *) dev->priv;
1775         pc300ch_t *chan = (pc300ch_t *) d->chan;
1776         pc300_t *card = (pc300_t *) chan->card;
1777         struct net_device_stats *stats = hdlc_stats(dev);
1778         int ch = chan->channel;
1779         unsigned long flags;
1780         ucchar ilar;
1781
1782         stats->tx_errors++;
1783         stats->tx_aborted_errors++;
1784         CPC_LOCK(card, flags);
1785         if ((ilar = cpc_readb(card->hw.scabase + ILAR)) != 0) {
1786                 printk("%s: ILAR=0x%x\n", dev->name, ilar);
1787                 cpc_writeb(card->hw.scabase + ILAR, ilar);
1788                 cpc_writeb(card->hw.scabase + DMER, 0x80);
1789         }
1790         if (card->hw.type == PC300_TE) {
1791                 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg2,
1792                            cpc_readb(card->hw.falcbase + card->hw.cpld_reg2) &
1793                            ~(CPLD_REG2_FALC_LED1 << (2 * ch)));
1794         }
1795         dev->trans_start = jiffies;
1796         CPC_UNLOCK(card, flags);
1797         netif_wake_queue(dev);
1798 }
1799
1800 int cpc_queue_xmit(struct sk_buff *skb, struct net_device *dev)
1801 {
1802         pc300dev_t *d = (pc300dev_t *) dev->priv;
1803         pc300ch_t *chan = (pc300ch_t *) d->chan;
1804         pc300_t *card = (pc300_t *) chan->card;
1805         struct net_device_stats *stats = hdlc_stats(dev);
1806         int ch = chan->channel;
1807         unsigned long flags;
1808 #ifdef PC300_DEBUG_TX
1809         int i;
1810 #endif
1811
1812         if (chan->conf.monitor) {
1813                 /* In monitor mode no Tx is done: ignore packet */
1814                 dev_kfree_skb(skb);
1815                 return 0;
1816         } else if (!netif_carrier_ok(dev)) {
1817                 /* DCD must be OFF: drop packet */
1818                 dev_kfree_skb(skb);
1819                 stats->tx_errors++;
1820                 stats->tx_carrier_errors++;
1821                 return 0;
1822         } else if (cpc_readb(card->hw.scabase + M_REG(ST3, ch)) & ST3_DCD) {
1823                 printk("%s: DCD is OFF. Going administrative down.\n", dev->name);
1824                 stats->tx_errors++;
1825                 stats->tx_carrier_errors++;
1826                 dev_kfree_skb(skb);
1827                 netif_carrier_off(dev);
1828                 CPC_LOCK(card, flags);
1829                 cpc_writeb(card->hw.scabase + M_REG(CMD, ch), CMD_TX_BUF_CLR);
1830                 if (card->hw.type == PC300_TE) {
1831                         cpc_writeb(card->hw.falcbase + card->hw.cpld_reg2,
1832                                    cpc_readb(card->hw.falcbase + card->hw.cpld_reg2) &
1833                                                         ~(CPLD_REG2_FALC_LED1 << (2 * ch)));
1834                 }
1835                 CPC_UNLOCK(card, flags);
1836                 netif_wake_queue(dev);
1837                 return 0;
1838         }
1839
1840         /* Write buffer to DMA buffers */
1841         if (dma_buf_write(card, ch, (ucchar *) skb->data, skb->len) != 0) {
1842 //              printk("%s: write error. Dropping TX packet.\n", dev->name);
1843                 netif_stop_queue(dev);
1844                 dev_kfree_skb(skb);
1845                 stats->tx_errors++;
1846                 stats->tx_dropped++;
1847                 return 0;
1848         }
1849 #ifdef PC300_DEBUG_TX
1850         printk("%s T:", dev->name);
1851         for (i = 0; i < skb->len; i++)
1852                 printk(" %02x", *(skb->data + i));
1853         printk("\n");
1854 #endif
1855
1856         if (d->trace_on) {
1857                 cpc_trace(dev, skb, 'T');
1858         }
1859         dev->trans_start = jiffies;
1860
1861         /* Start transmission */
1862         CPC_LOCK(card, flags);
1863         /* verify if it has more than one free descriptor */
1864         if (card->chan[ch].nfree_tx_bd <= 1) {
1865                 /* don't have so stop the queue */
1866                 netif_stop_queue(dev);
1867         }
1868         cpc_writel(card->hw.scabase + DTX_REG(EDAL, ch),
1869                    TX_BD_ADDR(ch, chan->tx_next_bd));
1870         cpc_writeb(card->hw.scabase + M_REG(CMD, ch), CMD_TX_ENA);
1871         cpc_writeb(card->hw.scabase + DSR_TX(ch), DSR_DE);
1872         if (card->hw.type == PC300_TE) {
1873                 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg2,
1874                            cpc_readb(card->hw.falcbase + card->hw.cpld_reg2) |
1875                            (CPLD_REG2_FALC_LED1 << (2 * ch)));
1876         }
1877         CPC_UNLOCK(card, flags);
1878         dev_kfree_skb(skb);
1879
1880         return 0;
1881 }
1882
1883 void cpc_net_rx(struct net_device *dev)
1884 {
1885         pc300dev_t *d = (pc300dev_t *) dev->priv;
1886         pc300ch_t *chan = (pc300ch_t *) d->chan;
1887         pc300_t *card = (pc300_t *) chan->card;
1888         struct net_device_stats *stats = hdlc_stats(dev);
1889         int ch = chan->channel;
1890 #ifdef PC300_DEBUG_RX
1891         int i;
1892 #endif
1893         int rxb;
1894         struct sk_buff *skb;
1895
1896         while (1) {
1897                 if ((rxb = dma_get_rx_frame_size(card, ch)) == -1)
1898                         return;
1899
1900                 if (!netif_carrier_ok(dev)) {
1901                         /* DCD must be OFF: drop packet */
1902                     printk("%s : DCD is OFF - drop %d rx bytes\n", dev->name, rxb);
1903                         skb = NULL;
1904                 } else {
1905                         if (rxb > (dev->mtu + 40)) { /* add headers */
1906                                 printk("%s : MTU exceeded %d\n", dev->name, rxb);
1907                                 skb = NULL;
1908                         } else {
1909                                 skb = dev_alloc_skb(rxb);
1910                                 if (skb == NULL) {
1911                                         printk("%s: Memory squeeze!!\n", dev->name);
1912                                         return;
1913                                 }
1914                                 skb->dev = dev;
1915                         }
1916                 }
1917
1918                 if (((rxb = dma_buf_read(card, ch, skb)) <= 0) || (skb == NULL)) {
1919 #ifdef PC300_DEBUG_RX
1920                         printk("%s: rxb = %x\n", dev->name, rxb);
1921 #endif
1922                         if ((skb == NULL) && (rxb > 0)) {
1923                                 /* rxb > dev->mtu */
1924                                 stats->rx_errors++;
1925                                 stats->rx_length_errors++;
1926                                 continue;
1927                         }
1928
1929                         if (rxb < 0) {  /* Invalid frame */
1930                                 rxb = -rxb;
1931                                 if (rxb & DST_OVR) {
1932                                         stats->rx_errors++;
1933                                         stats->rx_fifo_errors++;
1934                                 }
1935                                 if (rxb & DST_CRC) {
1936                                         stats->rx_errors++;
1937                                         stats->rx_crc_errors++;
1938                                 }
1939                                 if (rxb & (DST_RBIT | DST_SHRT | DST_ABT)) {
1940                                         stats->rx_errors++;
1941                                         stats->rx_frame_errors++;
1942                                 }
1943                         }
1944                         if (skb) {
1945                                 dev_kfree_skb_irq(skb);
1946                         }
1947                         continue;
1948                 }
1949
1950                 stats->rx_bytes += rxb;
1951
1952 #ifdef PC300_DEBUG_RX
1953                 printk("%s R:", dev->name);
1954                 for (i = 0; i < skb->len; i++)
1955                         printk(" %02x", *(skb->data + i));
1956                 printk("\n");
1957 #endif
1958                 if (d->trace_on) {
1959                         cpc_trace(dev, skb, 'R');
1960                 }
1961                 stats->rx_packets++;
1962                 skb->protocol = hdlc_type_trans(skb, dev);
1963                 netif_rx(skb);
1964         }
1965 }
1966
1967 /************************************/
1968 /***   PC300 Interrupt Routines   ***/
1969 /************************************/
1970 static void sca_tx_intr(pc300dev_t *dev)
1971 {
1972         pc300ch_t *chan = (pc300ch_t *)dev->chan;
1973         pc300_t *card = (pc300_t *)chan->card;
1974         int ch = chan->channel;
1975         volatile pcsca_bd_t __iomem * ptdescr;
1976         struct net_device_stats *stats = hdlc_stats(dev->dev);
1977
1978     /* Clean up descriptors from previous transmission */
1979         ptdescr = (card->hw.rambase +
1980                                                 TX_BD_ADDR(ch,chan->tx_first_bd));
1981         while ((cpc_readl(card->hw.scabase + DTX_REG(CDAL,ch)) !=
1982                                                         TX_BD_ADDR(ch,chan->tx_first_bd)) &&
1983                         (cpc_readb(&ptdescr->status) & DST_OSB)) {
1984                 stats->tx_packets++;
1985                 stats->tx_bytes += cpc_readw(&ptdescr->len);
1986                 cpc_writeb(&ptdescr->status, DST_OSB);
1987                 cpc_writew(&ptdescr->len, 0);
1988                 chan->nfree_tx_bd++;
1989                 chan->tx_first_bd = (chan->tx_first_bd + 1) & (N_DMA_TX_BUF - 1);
1990                 ptdescr = (card->hw.rambase + TX_BD_ADDR(ch,chan->tx_first_bd));
1991     }
1992
1993 #ifdef CONFIG_PC300_MLPPP
1994         if (chan->conf.proto == PC300_PROTO_MLPPP) {
1995                         cpc_tty_trigger_poll(dev);
1996         } else {
1997 #endif
1998         /* Tell the upper layer we are ready to transmit more packets */
1999                 netif_wake_queue(dev->dev);
2000 #ifdef CONFIG_PC300_MLPPP
2001         }
2002 #endif
2003 }
2004
2005 static void sca_intr(pc300_t * card)
2006 {
2007         void __iomem *scabase = card->hw.scabase;
2008         volatile uclong status;
2009         int ch;
2010         int intr_count = 0;
2011         unsigned char dsr_rx;
2012
2013         while ((status = cpc_readl(scabase + ISR0)) != 0) {
2014                 for (ch = 0; ch < card->hw.nchan; ch++) {
2015                         pc300ch_t *chan = &card->chan[ch];
2016                         pc300dev_t *d = &chan->d;
2017                         struct net_device *dev = d->dev;
2018                         hdlc_device *hdlc = dev_to_hdlc(dev);
2019
2020                         spin_lock(&card->card_lock);
2021
2022             /**** Reception ****/
2023                         if (status & IR0_DRX((IR0_DMIA | IR0_DMIB), ch)) {
2024                                 ucchar drx_stat = cpc_readb(scabase + DSR_RX(ch));
2025
2026                                 /* Clear RX interrupts */
2027                                 cpc_writeb(scabase + DSR_RX(ch), drx_stat | DSR_DWE);
2028
2029 #ifdef PC300_DEBUG_INTR
2030                                 printk ("sca_intr: RX intr chan[%d] (st=0x%08lx, dsr=0x%02x)\n",
2031                                          ch, status, drx_stat);
2032 #endif
2033                                 if (status & IR0_DRX(IR0_DMIA, ch)) {
2034                                         if (drx_stat & DSR_BOF) {
2035 #ifdef CONFIG_PC300_MLPPP
2036                                                 if (chan->conf.proto == PC300_PROTO_MLPPP) {
2037                                                         /* verify if driver is TTY */
2038                                                         if ((cpc_readb(scabase + DSR_RX(ch)) & DSR_DE)) {
2039                                                                 rx_dma_stop(card, ch);
2040                                                         }
2041                                                         cpc_tty_receive(d);
2042                                                         rx_dma_start(card, ch);
2043                                                 } else
2044 #endif
2045                                                 {
2046                                                         if ((cpc_readb(scabase + DSR_RX(ch)) & DSR_DE)) {
2047                                                                 rx_dma_stop(card, ch);
2048                                                         }
2049                                                         cpc_net_rx(dev);
2050                                                         /* Discard invalid frames */
2051                                                         hdlc->stats.rx_errors++;
2052                                                         hdlc->stats.rx_over_errors++;
2053                                                         chan->rx_first_bd = 0;
2054                                                         chan->rx_last_bd = N_DMA_RX_BUF - 1;
2055                                                         rx_dma_start(card, ch);
2056                                                 }
2057                                         }
2058                                 }
2059                                 if (status & IR0_DRX(IR0_DMIB, ch)) {
2060                                         if (drx_stat & DSR_EOM) {
2061                                                 if (card->hw.type == PC300_TE) {
2062                                                         cpc_writeb(card->hw.falcbase +
2063                                                                    card->hw.cpld_reg2,
2064                                                                    cpc_readb (card->hw.falcbase +
2065                                                                         card->hw.cpld_reg2) |
2066                                                                    (CPLD_REG2_FALC_LED1 << (2 * ch)));
2067                                                 }
2068 #ifdef CONFIG_PC300_MLPPP
2069                                                 if (chan->conf.proto == PC300_PROTO_MLPPP) {
2070                                                         /* verify if driver is TTY */
2071                                                         cpc_tty_receive(d);
2072                                                 } else {
2073                                                         cpc_net_rx(dev);
2074                                                 }
2075 #else
2076                                                 cpc_net_rx(dev);
2077 #endif
2078                                                 if (card->hw.type == PC300_TE) {
2079                                                         cpc_writeb(card->hw.falcbase +
2080                                                                    card->hw.cpld_reg2,
2081                                                                    cpc_readb (card->hw.falcbase +
2082                                                                                 card->hw.cpld_reg2) &
2083                                                                    ~ (CPLD_REG2_FALC_LED1 << (2 * ch)));
2084                                                 }
2085                                         }
2086                                 }
2087                                 if (!(dsr_rx = cpc_readb(scabase + DSR_RX(ch)) & DSR_DE)) {
2088 #ifdef PC300_DEBUG_INTR
2089                 printk("%s: RX intr chan[%d] (st=0x%08lx, dsr=0x%02x, dsr2=0x%02x)\n",
2090                         dev->name, ch, status, drx_stat, dsr_rx);
2091 #endif
2092                                         cpc_writeb(scabase + DSR_RX(ch), (dsr_rx | DSR_DE) & 0xfe);
2093                                 }
2094                         }
2095
2096             /**** Transmission ****/
2097                         if (status & IR0_DTX((IR0_EFT | IR0_DMIA | IR0_DMIB), ch)) {
2098                                 ucchar dtx_stat = cpc_readb(scabase + DSR_TX(ch));
2099
2100                                 /* Clear TX interrupts */
2101                                 cpc_writeb(scabase + DSR_TX(ch), dtx_stat | DSR_DWE);
2102
2103 #ifdef PC300_DEBUG_INTR
2104                                 printk ("sca_intr: TX intr chan[%d] (st=0x%08lx, dsr=0x%02x)\n",
2105                                          ch, status, dtx_stat);
2106 #endif
2107                                 if (status & IR0_DTX(IR0_EFT, ch)) {
2108                                         if (dtx_stat & DSR_UDRF) {
2109                                                 if (cpc_readb (scabase + M_REG(TBN, ch)) != 0) {
2110                                                         cpc_writeb(scabase + M_REG(CMD,ch), CMD_TX_BUF_CLR);
2111                                                 }
2112                                                 if (card->hw.type == PC300_TE) {
2113                                                         cpc_writeb(card->hw.falcbase + card->hw.cpld_reg2,
2114                                                                    cpc_readb (card->hw.falcbase +
2115                                                                                    card->hw.cpld_reg2) &
2116                                                                    ~ (CPLD_REG2_FALC_LED1 << (2 * ch)));
2117                                                 }
2118                                                 hdlc->stats.tx_errors++;
2119                                                 hdlc->stats.tx_fifo_errors++;
2120                                                 sca_tx_intr(d);
2121                                         }
2122                                 }
2123                                 if (status & IR0_DTX(IR0_DMIA, ch)) {
2124                                         if (dtx_stat & DSR_BOF) {
2125                                         }
2126                                 }
2127                                 if (status & IR0_DTX(IR0_DMIB, ch)) {
2128                                         if (dtx_stat & DSR_EOM) {
2129                                                 if (card->hw.type == PC300_TE) {
2130                                                         cpc_writeb(card->hw.falcbase + card->hw.cpld_reg2,
2131                                                                    cpc_readb (card->hw.falcbase +
2132                                                                                         card->hw.cpld_reg2) &
2133                                                                    ~ (CPLD_REG2_FALC_LED1 << (2 * ch)));
2134                                                 }
2135                                                 sca_tx_intr(d);
2136                                         }
2137                                 }
2138                         }
2139
2140             /**** MSCI ****/
2141                         if (status & IR0_M(IR0_RXINTA, ch)) {
2142                                 ucchar st1 = cpc_readb(scabase + M_REG(ST1, ch));
2143
2144                                 /* Clear MSCI interrupts */
2145                                 cpc_writeb(scabase + M_REG(ST1, ch), st1);
2146
2147 #ifdef PC300_DEBUG_INTR
2148                                 printk("sca_intr: MSCI intr chan[%d] (st=0x%08lx, st1=0x%02x)\n",
2149                                          ch, status, st1);
2150 #endif
2151                                 if (st1 & ST1_CDCD) {   /* DCD changed */
2152                                         if (cpc_readb(scabase + M_REG(ST3, ch)) & ST3_DCD) {
2153                                                 printk ("%s: DCD is OFF. Going administrative down.\n",
2154                                                          dev->name);
2155 #ifdef CONFIG_PC300_MLPPP
2156                                                 if (chan->conf.proto != PC300_PROTO_MLPPP) {
2157                                                         netif_carrier_off(dev);
2158                                                 }
2159 #else
2160                                                 netif_carrier_off(dev);
2161
2162 #endif
2163                                                 card->chan[ch].d.line_off++;
2164                                         } else {        /* DCD = 1 */
2165                                                 printk ("%s: DCD is ON. Going administrative up.\n",
2166                                                          dev->name);
2167 #ifdef CONFIG_PC300_MLPPP
2168                                                 if (chan->conf.proto != PC300_PROTO_MLPPP)
2169                                                         /* verify if driver is not TTY */
2170 #endif
2171                                                         netif_carrier_on(dev);
2172                                                 card->chan[ch].d.line_on++;
2173                                         }
2174                                 }
2175                         }
2176                         spin_unlock(&card->card_lock);
2177                 }
2178                 if (++intr_count == 10)
2179                         /* Too much work at this board. Force exit */
2180                         break;
2181         }
2182 }
2183
2184 static void falc_t1_loop_detection(pc300_t * card, int ch, ucchar frs1)
2185 {
2186         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
2187         falc_t *pfalc = (falc_t *) & chan->falc;
2188         void __iomem *falcbase = card->hw.falcbase;
2189
2190         if (((cpc_readb(falcbase + F_REG(LCR1, ch)) & LCR1_XPRBS) == 0) &&
2191             !pfalc->loop_gen) {
2192                 if (frs1 & FRS1_LLBDD) {
2193                         // A Line Loop Back Deactivation signal detected
2194                         if (pfalc->loop_active) {
2195                                 falc_remote_loop(card, ch, 0);
2196                         }
2197                 } else {
2198                         if ((frs1 & FRS1_LLBAD) &&
2199                             ((cpc_readb(falcbase + F_REG(LCR1, ch)) & LCR1_EPRM) == 0)) {
2200                                 // A Line Loop Back Activation signal detected
2201                                 if (!pfalc->loop_active) {
2202                                         falc_remote_loop(card, ch, 1);
2203                                 }
2204                         }
2205                 }
2206         }
2207 }
2208
2209 static void falc_e1_loop_detection(pc300_t * card, int ch, ucchar rsp)
2210 {
2211         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
2212         falc_t *pfalc = (falc_t *) & chan->falc;
2213         void __iomem *falcbase = card->hw.falcbase;
2214
2215         if (((cpc_readb(falcbase + F_REG(LCR1, ch)) & LCR1_XPRBS) == 0) &&
2216             !pfalc->loop_gen) {
2217                 if (rsp & RSP_LLBDD) {
2218                         // A Line Loop Back Deactivation signal detected
2219                         if (pfalc->loop_active) {
2220                                 falc_remote_loop(card, ch, 0);
2221                         }
2222                 } else {
2223                         if ((rsp & RSP_LLBAD) &&
2224                             ((cpc_readb(falcbase + F_REG(LCR1, ch)) & LCR1_EPRM) == 0)) {
2225                                 // A Line Loop Back Activation signal detected
2226                                 if (!pfalc->loop_active) {
2227                                         falc_remote_loop(card, ch, 1);
2228                                 }
2229                         }
2230                 }
2231         }
2232 }
2233
2234 static void falc_t1_intr(pc300_t * card, int ch)
2235 {
2236         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
2237         falc_t *pfalc = (falc_t *) & chan->falc;
2238         void __iomem *falcbase = card->hw.falcbase;
2239         ucchar isr0, isr3, gis;
2240         ucchar dummy;
2241
2242         while ((gis = cpc_readb(falcbase + F_REG(GIS, ch))) != 0) {
2243                 if (gis & GIS_ISR0) {
2244                         isr0 = cpc_readb(falcbase + F_REG(FISR0, ch));
2245                         if (isr0 & FISR0_PDEN) {
2246                                 /* Read the bit to clear the situation */
2247                                 if (cpc_readb(falcbase + F_REG(FRS1, ch)) &
2248                                     FRS1_PDEN) {
2249                                         pfalc->pden++;
2250                                 }
2251                         }
2252                 }
2253
2254                 if (gis & GIS_ISR1) {
2255                         dummy = cpc_readb(falcbase + F_REG(FISR1, ch));
2256                 }
2257
2258                 if (gis & GIS_ISR2) {
2259                         dummy = cpc_readb(falcbase + F_REG(FISR2, ch));
2260                 }
2261
2262                 if (gis & GIS_ISR3) {
2263                         isr3 = cpc_readb(falcbase + F_REG(FISR3, ch));
2264                         if (isr3 & FISR3_SEC) {
2265                                 pfalc->sec++;
2266                                 falc_update_stats(card, ch);
2267                                 falc_check_status(card, ch,
2268                                                   cpc_readb(falcbase + F_REG(FRS0, ch)));
2269                         }
2270                         if (isr3 & FISR3_ES) {
2271                                 pfalc->es++;
2272                         }
2273                         if (isr3 & FISR3_LLBSC) {
2274                                 falc_t1_loop_detection(card, ch,
2275                                                        cpc_readb(falcbase + F_REG(FRS1, ch)));
2276                         }
2277                 }
2278         }
2279 }
2280
2281 static void falc_e1_intr(pc300_t * card, int ch)
2282 {
2283         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
2284         falc_t *pfalc = (falc_t *) & chan->falc;
2285         void __iomem *falcbase = card->hw.falcbase;
2286         ucchar isr1, isr2, isr3, gis, rsp;
2287         ucchar dummy;
2288
2289         while ((gis = cpc_readb(falcbase + F_REG(GIS, ch))) != 0) {
2290                 rsp = cpc_readb(falcbase + F_REG(RSP, ch));
2291
2292                 if (gis & GIS_ISR0) {
2293                         dummy = cpc_readb(falcbase + F_REG(FISR0, ch));
2294                 }
2295                 if (gis & GIS_ISR1) {
2296                         isr1 = cpc_readb(falcbase + F_REG(FISR1, ch));
2297                         if (isr1 & FISR1_XMB) {
2298                                 if ((pfalc->xmb_cause & 2)
2299                                     && pfalc->multiframe_mode) {
2300                                         if (cpc_readb (falcbase + F_REG(FRS0, ch)) &
2301                                                                         (FRS0_LOS | FRS0_AIS | FRS0_LFA)) {
2302                                                 cpc_writeb(falcbase + F_REG(XSP, ch),
2303                                                            cpc_readb(falcbase + F_REG(XSP, ch))
2304                                                            & ~XSP_AXS);
2305                                         } else {
2306                                                 cpc_writeb(falcbase + F_REG(XSP, ch),
2307                                                            cpc_readb(falcbase + F_REG(XSP, ch))
2308                                                            | XSP_AXS);
2309                                         }
2310                                 }
2311                                 pfalc->xmb_cause = 0;
2312                                 cpc_writeb(falcbase + F_REG(IMR1, ch),
2313                                            cpc_readb(falcbase + F_REG(IMR1, ch)) | IMR1_XMB);
2314                         }
2315                         if (isr1 & FISR1_LLBSC) {
2316                                 falc_e1_loop_detection(card, ch, rsp);
2317                         }
2318                 }
2319                 if (gis & GIS_ISR2) {
2320                         isr2 = cpc_readb(falcbase + F_REG(FISR2, ch));
2321                         if (isr2 & FISR2_T400MS) {
2322                                 cpc_writeb(falcbase + F_REG(XSW, ch),
2323                                            cpc_readb(falcbase + F_REG(XSW, ch)) | XSW_XRA);
2324                         }
2325                         if (isr2 & FISR2_MFAR) {
2326                                 cpc_writeb(falcbase + F_REG(XSW, ch),
2327                                            cpc_readb(falcbase + F_REG(XSW, ch)) & ~XSW_XRA);
2328                         }
2329                         if (isr2 & (FISR2_FAR | FISR2_LFA | FISR2_AIS | FISR2_LOS)) {
2330                                 pfalc->xmb_cause |= 2;
2331                                 cpc_writeb(falcbase + F_REG(IMR1, ch),
2332                                            cpc_readb(falcbase + F_REG(IMR1, ch)) & ~IMR1_XMB);
2333                         }
2334                 }
2335                 if (gis & GIS_ISR3) {
2336                         isr3 = cpc_readb(falcbase + F_REG(FISR3, ch));
2337                         if (isr3 & FISR3_SEC) {
2338                                 pfalc->sec++;
2339                                 falc_update_stats(card, ch);
2340                                 falc_check_status(card, ch,
2341                                                   cpc_readb(falcbase + F_REG(FRS0, ch)));
2342                         }
2343                         if (isr3 & FISR3_ES) {
2344                                 pfalc->es++;
2345                         }
2346                 }
2347         }
2348 }
2349
2350 static void falc_intr(pc300_t * card)
2351 {
2352         int ch;
2353
2354         for (ch = 0; ch < card->hw.nchan; ch++) {
2355                 pc300ch_t *chan = &card->chan[ch];
2356                 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
2357
2358                 if (conf->media == IF_IFACE_T1) {
2359                         falc_t1_intr(card, ch);
2360                 } else {
2361                         falc_e1_intr(card, ch);
2362                 }
2363         }
2364 }
2365
2366 static irqreturn_t cpc_intr(int irq, void *dev_id, struct pt_regs *regs)
2367 {
2368         pc300_t *card;
2369         volatile ucchar plx_status;
2370
2371         if ((card = (pc300_t *) dev_id) == 0) {
2372 #ifdef PC300_DEBUG_INTR
2373                 printk("cpc_intr: spurious intr %d\n", irq);
2374 #endif
2375                 return IRQ_NONE;                /* spurious intr */
2376         }
2377
2378         if (card->hw.rambase == 0) {
2379 #ifdef PC300_DEBUG_INTR
2380                 printk("cpc_intr: spurious intr2 %d\n", irq);
2381 #endif
2382                 return IRQ_NONE;                /* spurious intr */
2383         }
2384
2385         switch (card->hw.type) {
2386                 case PC300_RSV:
2387                 case PC300_X21:
2388                         sca_intr(card);
2389                         break;
2390
2391                 case PC300_TE:
2392                         while ( (plx_status = (cpc_readb(card->hw.plxbase + card->hw.intctl_reg) &
2393                                  (PLX_9050_LINT1_STATUS | PLX_9050_LINT2_STATUS))) != 0) {
2394                                 if (plx_status & PLX_9050_LINT1_STATUS) {       /* SCA Interrupt */
2395                                         sca_intr(card);
2396                                 }
2397                                 if (plx_status & PLX_9050_LINT2_STATUS) {       /* FALC Interrupt */
2398                                         falc_intr(card);
2399                                 }
2400                         }
2401                         break;
2402         }
2403         return IRQ_HANDLED;
2404 }
2405
2406 void cpc_sca_status(pc300_t * card, int ch)
2407 {
2408         ucchar ilar;
2409         void __iomem *scabase = card->hw.scabase;
2410         unsigned long flags;
2411
2412         tx_dma_buf_check(card, ch);
2413         rx_dma_buf_check(card, ch);
2414         ilar = cpc_readb(scabase + ILAR);
2415         printk ("ILAR=0x%02x, WCRL=0x%02x, PCR=0x%02x, BTCR=0x%02x, BOLR=0x%02x\n",
2416                  ilar, cpc_readb(scabase + WCRL), cpc_readb(scabase + PCR),
2417                  cpc_readb(scabase + BTCR), cpc_readb(scabase + BOLR));
2418         printk("TX_CDA=0x%08x, TX_EDA=0x%08x\n",
2419                cpc_readl(scabase + DTX_REG(CDAL, ch)),
2420                cpc_readl(scabase + DTX_REG(EDAL, ch)));
2421         printk("RX_CDA=0x%08x, RX_EDA=0x%08x, BFL=0x%04x\n",
2422                cpc_readl(scabase + DRX_REG(CDAL, ch)),
2423                cpc_readl(scabase + DRX_REG(EDAL, ch)),
2424                cpc_readw(scabase + DRX_REG(BFLL, ch)));
2425         printk("DMER=0x%02x, DSR_TX=0x%02x, DSR_RX=0x%02x\n",
2426                cpc_readb(scabase + DMER), cpc_readb(scabase + DSR_TX(ch)),
2427                cpc_readb(scabase + DSR_RX(ch)));
2428         printk("DMR_TX=0x%02x, DMR_RX=0x%02x, DIR_TX=0x%02x, DIR_RX=0x%02x\n",
2429                cpc_readb(scabase + DMR_TX(ch)), cpc_readb(scabase + DMR_RX(ch)),
2430                cpc_readb(scabase + DIR_TX(ch)),
2431                cpc_readb(scabase + DIR_RX(ch)));
2432         printk("DCR_TX=0x%02x, DCR_RX=0x%02x, FCT_TX=0x%02x, FCT_RX=0x%02x\n",
2433                cpc_readb(scabase + DCR_TX(ch)), cpc_readb(scabase + DCR_RX(ch)),
2434                cpc_readb(scabase + FCT_TX(ch)),
2435                cpc_readb(scabase + FCT_RX(ch)));
2436         printk("MD0=0x%02x, MD1=0x%02x, MD2=0x%02x, MD3=0x%02x, IDL=0x%02x\n",
2437                cpc_readb(scabase + M_REG(MD0, ch)),
2438                cpc_readb(scabase + M_REG(MD1, ch)),
2439                cpc_readb(scabase + M_REG(MD2, ch)),
2440                cpc_readb(scabase + M_REG(MD3, ch)),
2441                cpc_readb(scabase + M_REG(IDL, ch)));
2442         printk("CMD=0x%02x, SA0=0x%02x, SA1=0x%02x, TFN=0x%02x, CTL=0x%02x\n",
2443                cpc_readb(scabase + M_REG(CMD, ch)),
2444                cpc_readb(scabase + M_REG(SA0, ch)),
2445                cpc_readb(scabase + M_REG(SA1, ch)),
2446                cpc_readb(scabase + M_REG(TFN, ch)),
2447                cpc_readb(scabase + M_REG(CTL, ch)));
2448         printk("ST0=0x%02x, ST1=0x%02x, ST2=0x%02x, ST3=0x%02x, ST4=0x%02x\n",
2449                cpc_readb(scabase + M_REG(ST0, ch)),
2450                cpc_readb(scabase + M_REG(ST1, ch)),
2451                cpc_readb(scabase + M_REG(ST2, ch)),
2452                cpc_readb(scabase + M_REG(ST3, ch)),
2453                cpc_readb(scabase + M_REG(ST4, ch)));
2454         printk ("CST0=0x%02x, CST1=0x%02x, CST2=0x%02x, CST3=0x%02x, FST=0x%02x\n",
2455                  cpc_readb(scabase + M_REG(CST0, ch)),
2456                  cpc_readb(scabase + M_REG(CST1, ch)),
2457                  cpc_readb(scabase + M_REG(CST2, ch)),
2458                  cpc_readb(scabase + M_REG(CST3, ch)),
2459                  cpc_readb(scabase + M_REG(FST, ch)));
2460         printk("TRC0=0x%02x, TRC1=0x%02x, RRC=0x%02x, TBN=0x%02x, RBN=0x%02x\n",
2461                cpc_readb(scabase + M_REG(TRC0, ch)),
2462                cpc_readb(scabase + M_REG(TRC1, ch)),
2463                cpc_readb(scabase + M_REG(RRC, ch)),
2464                cpc_readb(scabase + M_REG(TBN, ch)),
2465                cpc_readb(scabase + M_REG(RBN, ch)));
2466         printk("TFS=0x%02x, TNR0=0x%02x, TNR1=0x%02x, RNR=0x%02x\n",
2467                cpc_readb(scabase + M_REG(TFS, ch)),
2468                cpc_readb(scabase + M_REG(TNR0, ch)),
2469                cpc_readb(scabase + M_REG(TNR1, ch)),
2470                cpc_readb(scabase + M_REG(RNR, ch)));
2471         printk("TCR=0x%02x, RCR=0x%02x, TNR1=0x%02x, RNR=0x%02x\n",
2472                cpc_readb(scabase + M_REG(TCR, ch)),
2473                cpc_readb(scabase + M_REG(RCR, ch)),
2474                cpc_readb(scabase + M_REG(TNR1, ch)),
2475                cpc_readb(scabase + M_REG(RNR, ch)));
2476         printk("TXS=0x%02x, RXS=0x%02x, EXS=0x%02x, TMCT=0x%02x, TMCR=0x%02x\n",
2477                cpc_readb(scabase + M_REG(TXS, ch)),
2478                cpc_readb(scabase + M_REG(RXS, ch)),
2479                cpc_readb(scabase + M_REG(EXS, ch)),
2480                cpc_readb(scabase + M_REG(TMCT, ch)),
2481                cpc_readb(scabase + M_REG(TMCR, ch)));
2482         printk("IE0=0x%02x, IE1=0x%02x, IE2=0x%02x, IE4=0x%02x, FIE=0x%02x\n",
2483                cpc_readb(scabase + M_REG(IE0, ch)),
2484                cpc_readb(scabase + M_REG(IE1, ch)),
2485                cpc_readb(scabase + M_REG(IE2, ch)),
2486                cpc_readb(scabase + M_REG(IE4, ch)),
2487                cpc_readb(scabase + M_REG(FIE, ch)));
2488         printk("IER0=0x%08x\n", cpc_readl(scabase + IER0));
2489
2490         if (ilar != 0) {
2491                 CPC_LOCK(card, flags);
2492                 cpc_writeb(scabase + ILAR, ilar);
2493                 cpc_writeb(scabase + DMER, 0x80);
2494                 CPC_UNLOCK(card, flags);
2495         }
2496 }
2497
2498 void cpc_falc_status(pc300_t * card, int ch)
2499 {
2500         pc300ch_t *chan = &card->chan[ch];
2501         falc_t *pfalc = (falc_t *) & chan->falc;
2502         unsigned long flags;
2503
2504         CPC_LOCK(card, flags);
2505         printk("CH%d:   %s %s  %d channels\n",
2506                ch, (pfalc->sync ? "SYNC" : ""), (pfalc->active ? "ACTIVE" : ""),
2507                pfalc->num_channels);
2508
2509         printk("        pden=%d,  los=%d,  losr=%d,  lfa=%d,  farec=%d\n",
2510                pfalc->pden, pfalc->los, pfalc->losr, pfalc->lfa, pfalc->farec);
2511         printk("        lmfa=%d,  ais=%d,  sec=%d,  es=%d,  rai=%d\n",
2512                pfalc->lmfa, pfalc->ais, pfalc->sec, pfalc->es, pfalc->rai);
2513         printk("        bec=%d,  fec=%d,  cvc=%d,  cec=%d,  ebc=%d\n",
2514                pfalc->bec, pfalc->fec, pfalc->cvc, pfalc->cec, pfalc->ebc);
2515
2516         printk("\n");
2517         printk("        STATUS: %s  %s  %s  %s  %s  %s\n",
2518                (pfalc->red_alarm ? "RED" : ""),
2519                (pfalc->blue_alarm ? "BLU" : ""),
2520                (pfalc->yellow_alarm ? "YEL" : ""),
2521                (pfalc->loss_fa ? "LFA" : ""),
2522                (pfalc->loss_mfa ? "LMF" : ""), (pfalc->prbs ? "PRB" : ""));
2523         CPC_UNLOCK(card, flags);
2524 }
2525
2526 int cpc_change_mtu(struct net_device *dev, int new_mtu)
2527 {
2528         if ((new_mtu < 128) || (new_mtu > PC300_DEF_MTU))
2529                 return -EINVAL;
2530         dev->mtu = new_mtu;
2531         return 0;
2532 }
2533
2534 int cpc_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2535 {
2536         hdlc_device *hdlc = dev_to_hdlc(dev);
2537         pc300dev_t *d = (pc300dev_t *) dev->priv;
2538         pc300ch_t *chan = (pc300ch_t *) d->chan;
2539         pc300_t *card = (pc300_t *) chan->card;
2540         pc300conf_t conf_aux;
2541         pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
2542         int ch = chan->channel;
2543         void __user *arg = ifr->ifr_data;
2544         struct if_settings *settings = &ifr->ifr_settings;
2545         void __iomem *scabase = card->hw.scabase;
2546
2547         if (!capable(CAP_NET_ADMIN))
2548                 return -EPERM;
2549
2550         switch (cmd) {
2551                 case SIOCGPC300CONF:
2552 #ifdef CONFIG_PC300_MLPPP
2553                         if (conf->proto != PC300_PROTO_MLPPP) {
2554                                 conf->proto = hdlc->proto.id;
2555                         }
2556 #else
2557                         conf->proto = hdlc->proto.id;
2558 #endif
2559                         memcpy(&conf_aux.conf, conf, sizeof(pc300chconf_t));
2560                         memcpy(&conf_aux.hw, &card->hw, sizeof(pc300hw_t));
2561                         if (!arg ||
2562                                 copy_to_user(arg, &conf_aux, sizeof(pc300conf_t)))
2563                                 return -EINVAL;
2564                         return 0;
2565                 case SIOCSPC300CONF:
2566                         if (!capable(CAP_NET_ADMIN))
2567                                 return -EPERM;
2568                         if (!arg ||
2569                                 copy_from_user(&conf_aux.conf, arg, sizeof(pc300chconf_t)))
2570                                 return -EINVAL;
2571                         if (card->hw.cpld_id < 0x02 &&
2572                             conf_aux.conf.fr_mode == PC300_FR_UNFRAMED) {
2573                                 /* CPLD_ID < 0x02 doesn't support Unframed E1 */
2574                                 return -EINVAL;
2575                         }
2576 #ifdef CONFIG_PC300_MLPPP
2577                         if (conf_aux.conf.proto == PC300_PROTO_MLPPP) {
2578                                 if (conf->proto != PC300_PROTO_MLPPP) {
2579                                         memcpy(conf, &conf_aux.conf, sizeof(pc300chconf_t));
2580                                         cpc_tty_init(d);        /* init TTY driver */
2581                                 }
2582                         } else {
2583                                 if (conf_aux.conf.proto == 0xffff) {
2584                                         if (conf->proto == PC300_PROTO_MLPPP){
2585                                                 /* ifdown interface */
2586                                                 cpc_close(dev);
2587                                         }
2588                                 } else {
2589                                         memcpy(conf, &conf_aux.conf, sizeof(pc300chconf_t));
2590                                         hdlc->proto.id = conf->proto;
2591                                 }
2592                         }
2593 #else
2594                         memcpy(conf, &conf_aux.conf, sizeof(pc300chconf_t));
2595                         hdlc->proto.id = conf->proto;
2596 #endif
2597                         return 0;
2598                 case SIOCGPC300STATUS:
2599                         cpc_sca_status(card, ch);
2600                         return 0;
2601                 case SIOCGPC300FALCSTATUS:
2602                         cpc_falc_status(card, ch);
2603                         return 0;
2604
2605                 case SIOCGPC300UTILSTATS:
2606                         {
2607                                 if (!arg) {     /* clear statistics */
2608                                         memset(&hdlc->stats, 0, sizeof(struct net_device_stats));
2609                                         if (card->hw.type == PC300_TE) {
2610                                                 memset(&chan->falc, 0, sizeof(falc_t));
2611                                         }
2612                                 } else {
2613                                         pc300stats_t pc300stats;
2614
2615                                         memset(&pc300stats, 0, sizeof(pc300stats_t));
2616                                         pc300stats.hw_type = card->hw.type;
2617                                         pc300stats.line_on = card->chan[ch].d.line_on;
2618                                         pc300stats.line_off = card->chan[ch].d.line_off;
2619                                         memcpy(&pc300stats.gen_stats, &hdlc->stats,
2620                                                sizeof(struct net_device_stats));
2621                                         if (card->hw.type == PC300_TE)
2622                                                 memcpy(&pc300stats.te_stats,&chan->falc,sizeof(falc_t));
2623                                         if (copy_to_user(arg, &pc300stats, sizeof(pc300stats_t)))
2624                                                 return -EFAULT;
2625                                 }
2626                                 return 0;
2627                         }
2628
2629                 case SIOCGPC300UTILSTATUS:
2630                         {
2631                                 struct pc300status pc300status;
2632
2633                                 pc300status.hw_type = card->hw.type;
2634                                 if (card->hw.type == PC300_TE) {
2635                                         pc300status.te_status.sync = chan->falc.sync;
2636                                         pc300status.te_status.red_alarm = chan->falc.red_alarm;
2637                                         pc300status.te_status.blue_alarm = chan->falc.blue_alarm;
2638                                         pc300status.te_status.loss_fa = chan->falc.loss_fa;
2639                                         pc300status.te_status.yellow_alarm =chan->falc.yellow_alarm;
2640                                         pc300status.te_status.loss_mfa = chan->falc.loss_mfa;
2641                                         pc300status.te_status.prbs = chan->falc.prbs;
2642                                 } else {
2643                                         pc300status.gen_status.dcd =
2644                                                 !(cpc_readb (scabase + M_REG(ST3, ch)) & ST3_DCD);
2645                                         pc300status.gen_status.cts =
2646                                                 !(cpc_readb (scabase + M_REG(ST3, ch)) & ST3_CTS);
2647                                         pc300status.gen_status.rts =
2648                                                 !(cpc_readb (scabase + M_REG(CTL, ch)) & CTL_RTS);
2649                                         pc300status.gen_status.dtr =
2650                                                 !(cpc_readb (scabase + M_REG(CTL, ch)) & CTL_DTR);
2651                                         /* There is no DSR in HD64572 */
2652                                 }
2653                                 if (!arg
2654                                     || copy_to_user(arg, &pc300status, sizeof(pc300status_t)))
2655                                                 return -EINVAL;
2656                                 return 0;
2657                         }
2658
2659                 case SIOCSPC300TRACE:
2660                         /* Sets/resets a trace_flag for the respective device */
2661                         if (!arg || copy_from_user(&d->trace_on, arg,sizeof(unsigned char)))
2662                                         return -EINVAL;
2663                         return 0;
2664
2665                 case SIOCSPC300LOOPBACK:
2666                         {
2667                                 struct pc300loopback pc300loop;
2668
2669                                 /* TE boards only */
2670                                 if (card->hw.type != PC300_TE)
2671                                         return -EINVAL;
2672
2673                                 if (!arg ||
2674                                         copy_from_user(&pc300loop, arg, sizeof(pc300loopback_t)))
2675                                                 return -EINVAL;
2676                                 switch (pc300loop.loop_type) {
2677                                         case PC300LOCLOOP:      /* Turn the local loop on/off */
2678                                                 falc_local_loop(card, ch, pc300loop.loop_on);
2679                                                 return 0;
2680
2681                                         case PC300REMLOOP:      /* Turn the remote loop on/off */
2682                                                 falc_remote_loop(card, ch, pc300loop.loop_on);
2683                                                 return 0;
2684
2685                                         case PC300PAYLOADLOOP:  /* Turn the payload loop on/off */
2686                                                 falc_payload_loop(card, ch, pc300loop.loop_on);
2687                                                 return 0;
2688
2689                                         case PC300GENLOOPUP:    /* Generate loop UP */
2690                                                 if (pc300loop.loop_on) {
2691                                                         falc_generate_loop_up_code (card, ch);
2692                                                 } else {
2693                                                         turn_off_xlu(card, ch);
2694                                                 }
2695                                                 return 0;
2696
2697                                         case PC300GENLOOPDOWN:  /* Generate loop DOWN */
2698                                                 if (pc300loop.loop_on) {
2699                                                         falc_generate_loop_down_code (card, ch);
2700                                                 } else {
2701                                                         turn_off_xld(card, ch);
2702                                                 }
2703                                                 return 0;
2704
2705                                         default:
2706                                                 return -EINVAL;
2707                                 }
2708                         }
2709
2710                 case SIOCSPC300PATTERNTEST:
2711                         /* Turn the pattern test on/off and show the errors counter */
2712                         {
2713                                 struct pc300patterntst pc300patrntst;
2714
2715                                 /* TE boards only */
2716                                 if (card->hw.type != PC300_TE)
2717                                         return -EINVAL;
2718
2719                                 if (card->hw.cpld_id < 0x02) {
2720                                         /* CPLD_ID < 0x02 doesn't support pattern test */
2721                                         return -EINVAL;
2722                                 }
2723
2724                                 if (!arg ||
2725                                         copy_from_user(&pc300patrntst,arg,sizeof(pc300patterntst_t)))
2726                                                 return -EINVAL;
2727                                 if (pc300patrntst.patrntst_on == 2) {
2728                                         if (chan->falc.prbs == 0) {
2729                                                 falc_pattern_test(card, ch, 1);
2730                                         }
2731                                         pc300patrntst.num_errors =
2732                                                 falc_pattern_test_error(card, ch);
2733                                         if (!arg
2734                                             || copy_to_user(arg, &pc300patrntst,
2735                                                             sizeof (pc300patterntst_t)))
2736                                                         return -EINVAL;
2737                                 } else {
2738                                         falc_pattern_test(card, ch, pc300patrntst.patrntst_on);
2739                                 }
2740                                 return 0;
2741                         }
2742
2743                 case SIOCWANDEV:
2744                         switch (ifr->ifr_settings.type) {
2745                                 case IF_GET_IFACE:
2746                                 {
2747                                         const size_t size = sizeof(sync_serial_settings);
2748                                         ifr->ifr_settings.type = conf->media;
2749                                         if (ifr->ifr_settings.size < size) {
2750                                                 /* data size wanted */
2751                                                 ifr->ifr_settings.size = size;
2752                                                 return -ENOBUFS;
2753                                         }
2754
2755                                         if (copy_to_user(settings->ifs_ifsu.sync,
2756                                                          &conf->phys_settings, size)) {
2757                                                 return -EFAULT;
2758                                         }
2759                                         return 0;
2760                                 }
2761
2762                                 case IF_IFACE_V35:
2763                                 case IF_IFACE_V24:
2764                                 case IF_IFACE_X21:
2765                                 {
2766                                         const size_t size = sizeof(sync_serial_settings);
2767
2768                                         if (!capable(CAP_NET_ADMIN)) {
2769                                                 return -EPERM;
2770                                         }
2771                                         /* incorrect data len? */
2772                                         if (ifr->ifr_settings.size != size) {
2773                                                 return -ENOBUFS;
2774                                         }
2775
2776                                         if (copy_from_user(&conf->phys_settings,
2777                                                            settings->ifs_ifsu.sync, size)) {
2778                                                 return -EFAULT;
2779                                         }
2780
2781                                         if (conf->phys_settings.loopback) {
2782                                                 cpc_writeb(card->hw.scabase + M_REG(MD2, ch),
2783                                                         cpc_readb(card->hw.scabase + M_REG(MD2, ch)) |
2784                                                         MD2_LOOP_MIR);
2785                                         }
2786                                         conf->media = ifr->ifr_settings.type;
2787                                         return 0;
2788                                 }
2789
2790                                 case IF_IFACE_T1:
2791                                 case IF_IFACE_E1:
2792                                 {
2793                                         const size_t te_size = sizeof(te1_settings);
2794                                         const size_t size = sizeof(sync_serial_settings);
2795
2796                                         if (!capable(CAP_NET_ADMIN)) {
2797                                                 return -EPERM;
2798                                         }
2799
2800                                         /* incorrect data len? */
2801                                         if (ifr->ifr_settings.size != te_size) {
2802                                                 return -ENOBUFS;
2803                                         }
2804
2805                                         if (copy_from_user(&conf->phys_settings,
2806                                                            settings->ifs_ifsu.te1, size)) {
2807                                                 return -EFAULT;
2808                                         }/* Ignoring HDLC slot_map for a while */
2809
2810                                         if (conf->phys_settings.loopback) {
2811                                                 cpc_writeb(card->hw.scabase + M_REG(MD2, ch),
2812                                                         cpc_readb(card->hw.scabase + M_REG(MD2, ch)) |
2813                                                         MD2_LOOP_MIR);
2814                                         }
2815                                         conf->media = ifr->ifr_settings.type;
2816                                         return 0;
2817                                 }
2818                                 default:
2819                                         return hdlc_ioctl(dev, ifr, cmd);
2820                         }
2821
2822                 default:
2823                         return hdlc_ioctl(dev, ifr, cmd);
2824         }
2825 }
2826
2827 static struct net_device_stats *cpc_get_stats(struct net_device *dev)
2828 {
2829         return hdlc_stats(dev);
2830 }
2831
2832 static int clock_rate_calc(uclong rate, uclong clock, int *br_io)
2833 {
2834         int br, tc;
2835         int br_pwr, error;
2836
2837         if (rate == 0)
2838                 return (0);
2839
2840         for (br = 0, br_pwr = 1; br <= 9; br++, br_pwr <<= 1) {
2841                 if ((tc = clock / br_pwr / rate) <= 0xff) {
2842                         *br_io = br;
2843                         break;
2844                 }
2845         }
2846
2847         if (tc <= 0xff) {
2848                 error = ((rate - (clock / br_pwr / rate)) / rate) * 1000;
2849                 /* Errors bigger than +/- 1% won't be tolerated */
2850                 if (error < -10 || error > 10)
2851                         return (-1);
2852                 else
2853                         return (tc);
2854         } else {
2855                 return (-1);
2856         }
2857 }
2858
2859 int ch_config(pc300dev_t * d)
2860 {
2861         pc300ch_t *chan = (pc300ch_t *) d->chan;
2862         pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
2863         pc300_t *card = (pc300_t *) chan->card;
2864         void __iomem *scabase = card->hw.scabase;
2865         void __iomem *plxbase = card->hw.plxbase;
2866         int ch = chan->channel;
2867         uclong clkrate = chan->conf.phys_settings.clock_rate;
2868         uclong clktype = chan->conf.phys_settings.clock_type;
2869         ucshort encoding = chan->conf.proto_settings.encoding;
2870         ucshort parity = chan->conf.proto_settings.parity;
2871         int tmc, br;
2872         ucchar md0, md2;
2873
2874         /* Reset the channel */
2875         cpc_writeb(scabase + M_REG(CMD, ch), CMD_CH_RST);
2876
2877         /* Configure the SCA registers */
2878         switch (parity) {
2879                 case PARITY_NONE:
2880                         md0 = MD0_BIT_SYNC;
2881                         break;
2882                 case PARITY_CRC16_PR0:
2883                         md0 = MD0_CRC16_0|MD0_CRCC0|MD0_BIT_SYNC;
2884                         break;
2885                 case PARITY_CRC16_PR1:
2886                         md0 = MD0_CRC16_1|MD0_CRCC0|MD0_BIT_SYNC;
2887                         break;
2888                 case PARITY_CRC32_PR1_CCITT:
2889                         md0 = MD0_CRC32|MD0_CRCC0|MD0_BIT_SYNC;
2890                         break;
2891                 case PARITY_CRC16_PR1_CCITT:
2892                 default:
2893                         md0 = MD0_CRC_CCITT|MD0_CRCC0|MD0_BIT_SYNC;
2894                         break;
2895         }
2896         switch (encoding) {
2897                 case ENCODING_NRZI:
2898                         md2 = MD2_F_DUPLEX|MD2_ADPLL_X8|MD2_NRZI;
2899                         break;
2900                 case ENCODING_FM_MARK:  /* FM1 */
2901                         md2 = MD2_F_DUPLEX|MD2_ADPLL_X8|MD2_FM|MD2_FM1;
2902                         break;
2903                 case ENCODING_FM_SPACE: /* FM0 */
2904                         md2 = MD2_F_DUPLEX|MD2_ADPLL_X8|MD2_FM|MD2_FM0;
2905                         break;
2906                 case ENCODING_MANCHESTER: /* It's not working... */
2907                         md2 = MD2_F_DUPLEX|MD2_ADPLL_X8|MD2_FM|MD2_MANCH;
2908                         break;
2909                 case ENCODING_NRZ:
2910                 default:
2911                         md2 = MD2_F_DUPLEX|MD2_ADPLL_X8|MD2_NRZ;
2912                         break;
2913         }
2914         cpc_writeb(scabase + M_REG(MD0, ch), md0);
2915         cpc_writeb(scabase + M_REG(MD1, ch), 0);
2916         cpc_writeb(scabase + M_REG(MD2, ch), md2);
2917         cpc_writeb(scabase + M_REG(IDL, ch), 0x7e);
2918         cpc_writeb(scabase + M_REG(CTL, ch), CTL_URSKP | CTL_IDLC);
2919
2920         /* Configure HW media */
2921         switch (card->hw.type) {
2922                 case PC300_RSV:
2923                         if (conf->media == IF_IFACE_V35) {
2924                                 cpc_writel((plxbase + card->hw.gpioc_reg),
2925                                            cpc_readl(plxbase + card->hw.gpioc_reg) | PC300_CHMEDIA_MASK(ch));
2926                         } else {
2927                                 cpc_writel((plxbase + card->hw.gpioc_reg),
2928                                            cpc_readl(plxbase + card->hw.gpioc_reg) & ~PC300_CHMEDIA_MASK(ch));
2929                         }
2930                         break;
2931
2932                 case PC300_X21:
2933                         break;
2934
2935                 case PC300_TE:
2936                         te_config(card, ch);
2937                         break;
2938         }
2939
2940         switch (card->hw.type) {
2941                 case PC300_RSV:
2942                 case PC300_X21:
2943                         if (clktype == CLOCK_INT || clktype == CLOCK_TXINT) {
2944                                 /* Calculate the clkrate parameters */
2945                                 tmc = clock_rate_calc(clkrate, card->hw.clock, &br);
2946                                 cpc_writeb(scabase + M_REG(TMCT, ch), tmc);
2947                                 cpc_writeb(scabase + M_REG(TXS, ch),
2948                                            (TXS_DTRXC | TXS_IBRG | br));
2949                                 if (clktype == CLOCK_INT) {
2950                                         cpc_writeb(scabase + M_REG(TMCR, ch), tmc);
2951                                         cpc_writeb(scabase + M_REG(RXS, ch),
2952                                                    (RXS_IBRG | br));
2953                                 } else {
2954                                         cpc_writeb(scabase + M_REG(TMCR, ch), 1);
2955                                         cpc_writeb(scabase + M_REG(RXS, ch), 0);
2956                                 }
2957                                 if (card->hw.type == PC300_X21) {
2958                                         cpc_writeb(scabase + M_REG(GPO, ch), 1);
2959                                         cpc_writeb(scabase + M_REG(EXS, ch), EXS_TES1 | EXS_RES1);
2960                                 } else {
2961                                         cpc_writeb(scabase + M_REG(EXS, ch), EXS_TES1);
2962                                 }
2963                         } else {
2964                                 cpc_writeb(scabase + M_REG(TMCT, ch), 1);
2965                                 if (clktype == CLOCK_EXT) {
2966                                         cpc_writeb(scabase + M_REG(TXS, ch),
2967                                                    TXS_DTRXC);
2968                                 } else {
2969                                         cpc_writeb(scabase + M_REG(TXS, ch),
2970                                                    TXS_DTRXC|TXS_RCLK);
2971                                 }
2972                                 cpc_writeb(scabase + M_REG(TMCR, ch), 1);
2973                                 cpc_writeb(scabase + M_REG(RXS, ch), 0);
2974                                 if (card->hw.type == PC300_X21) {
2975                                         cpc_writeb(scabase + M_REG(GPO, ch), 0);
2976                                         cpc_writeb(scabase + M_REG(EXS, ch), EXS_TES1 | EXS_RES1);
2977                                 } else {
2978                                         cpc_writeb(scabase + M_REG(EXS, ch), EXS_TES1);
2979                                 }
2980                         }
2981                         break;
2982
2983                 case PC300_TE:
2984                         /* SCA always receives clock from the FALC chip */
2985                         cpc_writeb(scabase + M_REG(TMCT, ch), 1);
2986                         cpc_writeb(scabase + M_REG(TXS, ch), 0);
2987                         cpc_writeb(scabase + M_REG(TMCR, ch), 1);
2988                         cpc_writeb(scabase + M_REG(RXS, ch), 0);
2989                         cpc_writeb(scabase + M_REG(EXS, ch), 0);
2990                         break;
2991         }
2992
2993         /* Enable Interrupts */
2994         cpc_writel(scabase + IER0,
2995                    cpc_readl(scabase + IER0) |
2996                    IR0_M(IR0_RXINTA, ch) |
2997                    IR0_DRX(IR0_EFT | IR0_DMIA | IR0_DMIB, ch) |
2998                    IR0_DTX(IR0_EFT | IR0_DMIA | IR0_DMIB, ch));
2999         cpc_writeb(scabase + M_REG(IE0, ch),
3000                    cpc_readl(scabase + M_REG(IE0, ch)) | IE0_RXINTA);
3001         cpc_writeb(scabase + M_REG(IE1, ch),
3002                    cpc_readl(scabase + M_REG(IE1, ch)) | IE1_CDCD);
3003
3004         return 0;
3005 }
3006
3007 int rx_config(pc300dev_t * d)
3008 {
3009         pc300ch_t *chan = (pc300ch_t *) d->chan;
3010         pc300_t *card = (pc300_t *) chan->card;
3011         void __iomem *scabase = card->hw.scabase;
3012         int ch = chan->channel;
3013
3014         cpc_writeb(scabase + DSR_RX(ch), 0);
3015
3016         /* General RX settings */
3017         cpc_writeb(scabase + M_REG(RRC, ch), 0);
3018         cpc_writeb(scabase + M_REG(RNR, ch), 16);
3019
3020         /* Enable reception */
3021         cpc_writeb(scabase + M_REG(CMD, ch), CMD_RX_CRC_INIT);
3022         cpc_writeb(scabase + M_REG(CMD, ch), CMD_RX_ENA);
3023
3024         /* Initialize DMA stuff */
3025         chan->rx_first_bd = 0;
3026         chan->rx_last_bd = N_DMA_RX_BUF - 1;
3027         rx_dma_buf_init(card, ch);
3028         cpc_writeb(scabase + DCR_RX(ch), DCR_FCT_CLR);
3029         cpc_writeb(scabase + DMR_RX(ch), (DMR_TMOD | DMR_NF));
3030         cpc_writeb(scabase + DIR_RX(ch), (DIR_EOM | DIR_BOF));
3031
3032         /* Start DMA */
3033         rx_dma_start(card, ch);
3034
3035         return 0;
3036 }
3037
3038 int tx_config(pc300dev_t * d)
3039 {
3040         pc300ch_t *chan = (pc300ch_t *) d->chan;
3041         pc300_t *card = (pc300_t *) chan->card;
3042         void __iomem *scabase = card->hw.scabase;
3043         int ch = chan->channel;
3044
3045         cpc_writeb(scabase + DSR_TX(ch), 0);
3046
3047         /* General TX settings */
3048         cpc_writeb(scabase + M_REG(TRC0, ch), 0);
3049         cpc_writeb(scabase + M_REG(TFS, ch), 32);
3050         cpc_writeb(scabase + M_REG(TNR0, ch), 20);
3051         cpc_writeb(scabase + M_REG(TNR1, ch), 48);
3052         cpc_writeb(scabase + M_REG(TCR, ch), 8);
3053
3054         /* Enable transmission */
3055         cpc_writeb(scabase + M_REG(CMD, ch), CMD_TX_CRC_INIT);
3056
3057         /* Initialize DMA stuff */
3058         chan->tx_first_bd = 0;
3059         chan->tx_next_bd = 0;
3060         tx_dma_buf_init(card, ch);
3061         cpc_writeb(scabase + DCR_TX(ch), DCR_FCT_CLR);
3062         cpc_writeb(scabase + DMR_TX(ch), (DMR_TMOD | DMR_NF));
3063         cpc_writeb(scabase + DIR_TX(ch), (DIR_EOM | DIR_BOF | DIR_UDRF));
3064         cpc_writel(scabase + DTX_REG(CDAL, ch), TX_BD_ADDR(ch, chan->tx_first_bd));
3065         cpc_writel(scabase + DTX_REG(EDAL, ch), TX_BD_ADDR(ch, chan->tx_next_bd));
3066
3067         return 0;
3068 }
3069
3070 static int cpc_attach(struct net_device *dev, unsigned short encoding,
3071                       unsigned short parity)
3072 {
3073         pc300dev_t *d = (pc300dev_t *)dev->priv;
3074         pc300ch_t *chan = (pc300ch_t *)d->chan;
3075         pc300_t *card = (pc300_t *)chan->card;
3076         pc300chconf_t *conf = (pc300chconf_t *)&chan->conf;
3077
3078         if (card->hw.type == PC300_TE) {
3079                 if (encoding != ENCODING_NRZ && encoding != ENCODING_NRZI) {
3080                         return -EINVAL;
3081                 }
3082         } else {
3083                 if (encoding != ENCODING_NRZ && encoding != ENCODING_NRZI &&
3084                     encoding != ENCODING_FM_MARK && encoding != ENCODING_FM_SPACE) {
3085                         /* Driver doesn't support ENCODING_MANCHESTER yet */
3086                         return -EINVAL;
3087                 }
3088         }
3089
3090         if (parity != PARITY_NONE && parity != PARITY_CRC16_PR0 &&
3091             parity != PARITY_CRC16_PR1 && parity != PARITY_CRC32_PR1_CCITT &&
3092             parity != PARITY_CRC16_PR1_CCITT) {
3093                 return -EINVAL;
3094         }
3095
3096         conf->proto_settings.encoding = encoding;
3097         conf->proto_settings.parity = parity;
3098         return 0;
3099 }
3100
3101 void cpc_opench(pc300dev_t * d)
3102 {
3103         pc300ch_t *chan = (pc300ch_t *) d->chan;
3104         pc300_t *card = (pc300_t *) chan->card;
3105         int ch = chan->channel;
3106         void __iomem *scabase = card->hw.scabase;
3107
3108         ch_config(d);
3109
3110         rx_config(d);
3111
3112         tx_config(d);
3113
3114         /* Assert RTS and DTR */
3115         cpc_writeb(scabase + M_REG(CTL, ch),
3116                    cpc_readb(scabase + M_REG(CTL, ch)) & ~(CTL_RTS | CTL_DTR));
3117 }
3118
3119 void cpc_closech(pc300dev_t * d)
3120 {
3121         pc300ch_t *chan = (pc300ch_t *) d->chan;
3122         pc300_t *card = (pc300_t *) chan->card;
3123         falc_t *pfalc = (falc_t *) & chan->falc;
3124         int ch = chan->channel;
3125
3126         cpc_writeb(card->hw.scabase + M_REG(CMD, ch), CMD_CH_RST);
3127         rx_dma_stop(card, ch);
3128         tx_dma_stop(card, ch);
3129
3130         if (card->hw.type == PC300_TE) {
3131                 memset(pfalc, 0, sizeof(falc_t));
3132                 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg2,
3133                            cpc_readb(card->hw.falcbase + card->hw.cpld_reg2) &
3134                            ~((CPLD_REG2_FALC_TX_CLK | CPLD_REG2_FALC_RX_CLK |
3135                               CPLD_REG2_FALC_LED2) << (2 * ch)));
3136                 /* Reset the FALC chip */
3137                 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg1,
3138                            cpc_readb(card->hw.falcbase + card->hw.cpld_reg1) |
3139                            (CPLD_REG1_FALC_RESET << (2 * ch)));
3140                 udelay(10000);
3141                 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg1,
3142                            cpc_readb(card->hw.falcbase + card->hw.cpld_reg1) &
3143                            ~(CPLD_REG1_FALC_RESET << (2 * ch)));
3144         }
3145 }
3146
3147 int cpc_open(struct net_device *dev)
3148 {
3149         hdlc_device *hdlc = dev_to_hdlc(dev);
3150         pc300dev_t *d = (pc300dev_t *) dev->priv;
3151         struct ifreq ifr;
3152         int result;
3153
3154 #ifdef  PC300_DEBUG_OTHER
3155         printk("pc300: cpc_open");
3156 #endif
3157
3158         if (hdlc->proto.id == IF_PROTO_PPP) {
3159                 d->if_ptr = &hdlc->state.ppp.pppdev;
3160         }
3161
3162         result = hdlc_open(dev);
3163         if (hdlc->proto.id == IF_PROTO_PPP) {
3164                 dev->priv = d;
3165         }
3166         if (result) {
3167                 return result;
3168         }
3169
3170         sprintf(ifr.ifr_name, "%s", dev->name);
3171         cpc_opench(d);
3172         netif_start_queue(dev);
3173         return 0;
3174 }
3175
3176 int cpc_close(struct net_device *dev)
3177 {
3178         hdlc_device *hdlc = dev_to_hdlc(dev);
3179         pc300dev_t *d = (pc300dev_t *) dev->priv;
3180         pc300ch_t *chan = (pc300ch_t *) d->chan;
3181         pc300_t *card = (pc300_t *) chan->card;
3182         unsigned long flags;
3183
3184 #ifdef  PC300_DEBUG_OTHER
3185         printk("pc300: cpc_close");
3186 #endif
3187
3188         netif_stop_queue(dev);
3189
3190         CPC_LOCK(card, flags);
3191         cpc_closech(d);
3192         CPC_UNLOCK(card, flags);
3193
3194         hdlc_close(dev);
3195         if (hdlc->proto.id == IF_PROTO_PPP) {
3196                 d->if_ptr = NULL;
3197         }
3198 #ifdef CONFIG_PC300_MLPPP
3199         if (chan->conf.proto == PC300_PROTO_MLPPP) {
3200                 cpc_tty_unregister_service(d);
3201                 chan->conf.proto = 0xffff;
3202         }
3203 #endif
3204
3205         return 0;
3206 }
3207
3208 static uclong detect_ram(pc300_t * card)
3209 {
3210         uclong i;
3211         ucchar data;
3212         void __iomem *rambase = card->hw.rambase;
3213
3214         card->hw.ramsize = PC300_RAMSIZE;
3215         /* Let's find out how much RAM is present on this board */
3216         for (i = 0; i < card->hw.ramsize; i++) {
3217                 data = (ucchar) (i & 0xff);
3218                 cpc_writeb(rambase + i, data);
3219                 if (cpc_readb(rambase + i) != data) {
3220                         break;
3221                 }
3222         }
3223         return (i);
3224 }
3225
3226 static void plx_init(pc300_t * card)
3227 {
3228         struct RUNTIME_9050 __iomem *plx_ctl = card->hw.plxbase;
3229
3230         /* Reset PLX */
3231         cpc_writel(&plx_ctl->init_ctrl,
3232                    cpc_readl(&plx_ctl->init_ctrl) | 0x40000000);
3233         udelay(10000L);
3234         cpc_writel(&plx_ctl->init_ctrl,
3235                    cpc_readl(&plx_ctl->init_ctrl) & ~0x40000000);
3236
3237         /* Reload Config. Registers from EEPROM */
3238         cpc_writel(&plx_ctl->init_ctrl,
3239                    cpc_readl(&plx_ctl->init_ctrl) | 0x20000000);
3240         udelay(10000L);
3241         cpc_writel(&plx_ctl->init_ctrl,
3242                    cpc_readl(&plx_ctl->init_ctrl) & ~0x20000000);
3243
3244 }
3245
3246 static inline void show_version(void)
3247 {
3248         char *rcsvers, *rcsdate, *tmp;
3249
3250         rcsvers = strchr(rcsid, ' ');
3251         rcsvers++;
3252         tmp = strchr(rcsvers, ' ');
3253         *tmp++ = '\0';
3254         rcsdate = strchr(tmp, ' ');
3255         rcsdate++;
3256         tmp = strrchr(rcsdate, ' ');
3257         *tmp = '\0';
3258         printk(KERN_INFO "Cyclades-PC300 driver %s %s (built %s %s)\n",
3259                 rcsvers, rcsdate, __DATE__, __TIME__);
3260 }                               /* show_version */
3261
3262 static void cpc_init_card(pc300_t * card)
3263 {
3264         int i, devcount = 0;
3265         static int board_nbr = 1;
3266
3267         /* Enable interrupts on the PCI bridge */
3268         plx_init(card);
3269         cpc_writew(card->hw.plxbase + card->hw.intctl_reg,
3270                    cpc_readw(card->hw.plxbase + card->hw.intctl_reg) | 0x0040);
3271
3272 #ifdef USE_PCI_CLOCK
3273         /* Set board clock to PCI clock */
3274         cpc_writel(card->hw.plxbase + card->hw.gpioc_reg,
3275                    cpc_readl(card->hw.plxbase + card->hw.gpioc_reg) | 0x00000004UL);
3276         card->hw.clock = PC300_PCI_CLOCK;
3277 #else
3278         /* Set board clock to internal oscillator clock */
3279         cpc_writel(card->hw.plxbase + card->hw.gpioc_reg,
3280                    cpc_readl(card->hw.plxbase + card->hw.gpioc_reg) & ~0x00000004UL);
3281         card->hw.clock = PC300_OSC_CLOCK;
3282 #endif
3283
3284         /* Detect actual on-board RAM size */
3285         card->hw.ramsize = detect_ram(card);
3286
3287         /* Set Global SCA-II registers */
3288         cpc_writeb(card->hw.scabase + PCR, PCR_PR2);
3289         cpc_writeb(card->hw.scabase + BTCR, 0x10);
3290         cpc_writeb(card->hw.scabase + WCRL, 0);
3291         cpc_writeb(card->hw.scabase + DMER, 0x80);
3292
3293         if (card->hw.type == PC300_TE) {
3294                 ucchar reg1;
3295
3296                 /* Check CPLD version */
3297                 reg1 = cpc_readb(card->hw.falcbase + CPLD_REG1);
3298                 cpc_writeb(card->hw.falcbase + CPLD_REG1, (reg1 + 0x5a));
3299                 if (cpc_readb(card->hw.falcbase + CPLD_REG1) == reg1) {
3300                         /* New CPLD */
3301                         card->hw.cpld_id = cpc_readb(card->hw.falcbase + CPLD_ID_REG);
3302                         card->hw.cpld_reg1 = CPLD_V2_REG1;
3303                         card->hw.cpld_reg2 = CPLD_V2_REG2;
3304                 } else {
3305                         /* old CPLD */
3306                         card->hw.cpld_id = 0;
3307                         card->hw.cpld_reg1 = CPLD_REG1;
3308                         card->hw.cpld_reg2 = CPLD_REG2;
3309                         cpc_writeb(card->hw.falcbase + CPLD_REG1, reg1);
3310                 }
3311
3312                 /* Enable the board's global clock */
3313                 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg1,
3314                            cpc_readb(card->hw.falcbase + card->hw.cpld_reg1) |
3315                            CPLD_REG1_GLOBAL_CLK);
3316
3317         }
3318
3319         for (i = 0; i < card->hw.nchan; i++) {
3320                 pc300ch_t *chan = &card->chan[i];
3321                 pc300dev_t *d = &chan->d;
3322                 hdlc_device *hdlc;
3323                 struct net_device *dev;
3324
3325                 chan->card = card;
3326                 chan->channel = i;
3327                 chan->conf.phys_settings.clock_rate = 0;
3328                 chan->conf.phys_settings.clock_type = CLOCK_EXT;
3329                 chan->conf.proto_settings.encoding = ENCODING_NRZ;
3330                 chan->conf.proto_settings.parity = PARITY_CRC16_PR1_CCITT;
3331                 switch (card->hw.type) {
3332                         case PC300_TE:
3333                                 chan->conf.media = IF_IFACE_T1;
3334                                 chan->conf.lcode = PC300_LC_B8ZS;
3335                                 chan->conf.fr_mode = PC300_FR_ESF;
3336                                 chan->conf.lbo = PC300_LBO_0_DB;
3337                                 chan->conf.rx_sens = PC300_RX_SENS_SH;
3338                                 chan->conf.tslot_bitmap = 0xffffffffUL;
3339                                 break;
3340
3341                         case PC300_X21:
3342                                 chan->conf.media = IF_IFACE_X21;
3343                                 break;
3344
3345                         case PC300_RSV:
3346                         default:
3347                                 chan->conf.media = IF_IFACE_V35;
3348                                 break;
3349                 }
3350                 chan->conf.proto = IF_PROTO_PPP;
3351                 chan->tx_first_bd = 0;
3352                 chan->tx_next_bd = 0;
3353                 chan->rx_first_bd = 0;
3354                 chan->rx_last_bd = N_DMA_RX_BUF - 1;
3355                 chan->nfree_tx_bd = N_DMA_TX_BUF;
3356
3357                 d->chan = chan;
3358                 d->tx_skb = NULL;
3359                 d->trace_on = 0;
3360                 d->line_on = 0;
3361                 d->line_off = 0;
3362
3363                 dev = alloc_hdlcdev(NULL);
3364                 if (dev == NULL)
3365                         continue;
3366
3367                 hdlc = dev_to_hdlc(dev);
3368                 hdlc->xmit = cpc_queue_xmit;
3369                 hdlc->attach = cpc_attach;
3370                 d->dev = dev;
3371                 dev->mem_start = card->hw.ramphys;
3372                 dev->mem_end = card->hw.ramphys + card->hw.ramsize - 1;
3373                 dev->irq = card->hw.irq;
3374                 dev->init = NULL;
3375                 dev->tx_queue_len = PC300_TX_QUEUE_LEN;
3376                 dev->mtu = PC300_DEF_MTU;
3377
3378                 dev->open = cpc_open;
3379                 dev->stop = cpc_close;
3380                 dev->tx_timeout = cpc_tx_timeout;
3381                 dev->watchdog_timeo = PC300_TX_TIMEOUT;
3382                 dev->get_stats = cpc_get_stats;
3383                 dev->set_multicast_list = NULL;
3384                 dev->set_mac_address = NULL;
3385                 dev->change_mtu = cpc_change_mtu;
3386                 dev->do_ioctl = cpc_ioctl;
3387
3388                 if (register_hdlc_device(dev) == 0) {
3389                         dev->priv = d;  /* We need 'priv', hdlc doesn't */
3390                         printk("%s: Cyclades-PC300/", dev->name);
3391                         switch (card->hw.type) {
3392                                 case PC300_TE:
3393                                         if (card->hw.bus == PC300_PMC) {
3394                                                 printk("TE-M");
3395                                         } else {
3396                                                 printk("TE  ");
3397                                         }
3398                                         break;
3399
3400                                 case PC300_X21:
3401                                         printk("X21 ");
3402                                         break;
3403
3404                                 case PC300_RSV:
3405                                 default:
3406                                         printk("RSV ");
3407                                         break;
3408                         }
3409                         printk (" #%d, %dKB of RAM at 0x%08x, IRQ%d, channel %d.\n",
3410                                  board_nbr, card->hw.ramsize / 1024,
3411                                  card->hw.ramphys, card->hw.irq, i + 1);
3412                         devcount++;
3413                 } else {
3414                         printk ("Dev%d on card(0x%08x): unable to allocate i/f name.\n",
3415                                  i + 1, card->hw.ramphys);
3416                         free_netdev(dev);
3417                         continue;
3418                 }
3419         }
3420         spin_lock_init(&card->card_lock);
3421
3422         board_nbr++;
3423 }
3424
3425 static int __devinit
3426 cpc_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
3427 {
3428         static int first_time = 1;
3429         ucchar cpc_rev_id;
3430         int err = 0, eeprom_outdated = 0;
3431         ucshort device_id;
3432         pc300_t *card;
3433
3434         if (first_time) {
3435                 first_time = 0;
3436                 show_version();
3437 #ifdef CONFIG_PC300_MLPPP
3438                 cpc_tty_reset_var();
3439 #endif
3440         }
3441
3442         card = (pc300_t *) kmalloc(sizeof(pc300_t), GFP_KERNEL);
3443         if (card == NULL) {
3444                 printk("PC300 found at RAM 0x%08lx, "
3445                        "but could not allocate card structure.\n",
3446                        pci_resource_start(pdev, 3));
3447                 return -ENOMEM;
3448         }
3449         memset(card, 0, sizeof(pc300_t));
3450
3451         /* read PCI configuration area */
3452         device_id = ent->device;
3453         card->hw.irq = pdev->irq;
3454         card->hw.iophys = pci_resource_start(pdev, 1);
3455         card->hw.iosize = pci_resource_len(pdev, 1);
3456         card->hw.scaphys = pci_resource_start(pdev, 2);
3457         card->hw.scasize = pci_resource_len(pdev, 2);
3458         card->hw.ramphys = pci_resource_start(pdev, 3);
3459         card->hw.alloc_ramsize = pci_resource_len(pdev, 3);
3460         card->hw.falcphys = pci_resource_start(pdev, 4);
3461         card->hw.falcsize = pci_resource_len(pdev, 4);
3462         card->hw.plxphys = pci_resource_start(pdev, 5);
3463         card->hw.plxsize = pci_resource_len(pdev, 5);
3464         pci_read_config_byte(pdev, PCI_REVISION_ID, &cpc_rev_id);
3465
3466         switch (device_id) {
3467                 case PCI_DEVICE_ID_PC300_RX_1:
3468                 case PCI_DEVICE_ID_PC300_TE_1:
3469                 case PCI_DEVICE_ID_PC300_TE_M_1:
3470                         card->hw.nchan = 1;
3471                         break;
3472
3473                 case PCI_DEVICE_ID_PC300_RX_2:
3474                 case PCI_DEVICE_ID_PC300_TE_2:
3475                 case PCI_DEVICE_ID_PC300_TE_M_2:
3476                 default:
3477                         card->hw.nchan = PC300_MAXCHAN;
3478                         break;
3479         }
3480 #ifdef PC300_DEBUG_PCI
3481         printk("cpc (bus=0x0%x,pci_id=0x%x,", pdev->bus->number, pdev->devfn);
3482         printk("rev_id=%d) IRQ%d\n", cpc_rev_id, card->hw.irq);
3483         printk("cpc:found  ramaddr=0x%08lx plxaddr=0x%08lx "
3484                "ctladdr=0x%08lx falcaddr=0x%08lx\n",
3485                card->hw.ramphys, card->hw.plxphys, card->hw.scaphys,
3486                card->hw.falcphys);
3487 #endif
3488         /* Although we don't use this I/O region, we should
3489          * request it from the kernel anyway, to avoid problems
3490          * with other drivers accessing it. */
3491         if (!request_region(card->hw.iophys, card->hw.iosize, "PLX Registers")) {
3492                 /* In case we can't allocate it, warn user */
3493                 printk("WARNING: couldn't allocate I/O region for PC300 board "
3494                        "at 0x%08x!\n", card->hw.ramphys);
3495         }
3496
3497         if (card->hw.plxphys) {
3498                 pci_write_config_dword(pdev, PCI_BASE_ADDRESS_0, card->hw.plxphys);
3499         } else {
3500                 eeprom_outdated = 1;
3501                 card->hw.plxphys = pci_resource_start(pdev, 0);
3502                 card->hw.plxsize = pci_resource_len(pdev, 0);
3503         }
3504
3505         if (!request_mem_region(card->hw.plxphys, card->hw.plxsize,
3506                                 "PLX Registers")) {
3507                 printk("PC300 found at RAM 0x%08x, "
3508                        "but could not allocate PLX mem region.\n",
3509                        card->hw.ramphys);
3510                 err = -ENODEV;
3511                 goto err_release_io;
3512         }
3513         if (!request_mem_region(card->hw.ramphys, card->hw.alloc_ramsize,
3514                                 "On-board RAM")) {
3515                 printk("PC300 found at RAM 0x%08x, "
3516                        "but could not allocate RAM mem region.\n",
3517                        card->hw.ramphys);
3518                 err = -ENODEV;
3519                 goto err_release_plx;
3520         }
3521         if (!request_mem_region(card->hw.scaphys, card->hw.scasize,
3522                                 "SCA-II Registers")) {
3523                 printk("PC300 found at RAM 0x%08x, "
3524                        "but could not allocate SCA mem region.\n",
3525                        card->hw.ramphys);
3526                 err = -ENODEV;
3527                 goto err_release_ram;
3528         }
3529
3530         if ((err = pci_enable_device(pdev)) != 0)
3531                 goto err_release_sca;
3532
3533         card->hw.plxbase = ioremap(card->hw.plxphys, card->hw.plxsize);
3534         card->hw.rambase = ioremap(card->hw.ramphys, card->hw.alloc_ramsize);
3535         card->hw.scabase = ioremap(card->hw.scaphys, card->hw.scasize);
3536         switch (device_id) {
3537                 case PCI_DEVICE_ID_PC300_TE_1:
3538                 case PCI_DEVICE_ID_PC300_TE_2:
3539                 case PCI_DEVICE_ID_PC300_TE_M_1:
3540                 case PCI_DEVICE_ID_PC300_TE_M_2:
3541                         request_mem_region(card->hw.falcphys, card->hw.falcsize,
3542                                            "FALC Registers");
3543                         card->hw.falcbase = ioremap(card->hw.falcphys, card->hw.falcsize);
3544                         break;
3545
3546                 case PCI_DEVICE_ID_PC300_RX_1:
3547                 case PCI_DEVICE_ID_PC300_RX_2:
3548                 default:
3549                         card->hw.falcbase = NULL;
3550                         break;
3551         }
3552
3553 #ifdef PC300_DEBUG_PCI
3554         printk("cpc: relocate ramaddr=0x%08lx plxaddr=0x%08lx "
3555                "ctladdr=0x%08lx falcaddr=0x%08lx\n",
3556                card->hw.rambase, card->hw.plxbase, card->hw.scabase,
3557                card->hw.falcbase);
3558 #endif
3559
3560         /* Set PCI drv pointer to the card structure */
3561         pci_set_drvdata(pdev, card);
3562
3563         /* Set board type */
3564         switch (device_id) {
3565                 case PCI_DEVICE_ID_PC300_TE_1:
3566                 case PCI_DEVICE_ID_PC300_TE_2:
3567                 case PCI_DEVICE_ID_PC300_TE_M_1:
3568                 case PCI_DEVICE_ID_PC300_TE_M_2:
3569                         card->hw.type = PC300_TE;
3570
3571                         if ((device_id == PCI_DEVICE_ID_PC300_TE_M_1) ||
3572                             (device_id == PCI_DEVICE_ID_PC300_TE_M_2)) {
3573                                 card->hw.bus = PC300_PMC;
3574                                 /* Set PLX register offsets */
3575                                 card->hw.gpioc_reg = 0x54;
3576                                 card->hw.intctl_reg = 0x4c;
3577                         } else {
3578                                 card->hw.bus = PC300_PCI;
3579                                 /* Set PLX register offsets */
3580                                 card->hw.gpioc_reg = 0x50;
3581                                 card->hw.intctl_reg = 0x4c;
3582                         }
3583                         break;
3584
3585                 case PCI_DEVICE_ID_PC300_RX_1:
3586                 case PCI_DEVICE_ID_PC300_RX_2:
3587                 default:
3588                         card->hw.bus = PC300_PCI;
3589                         /* Set PLX register offsets */
3590                         card->hw.gpioc_reg = 0x50;
3591                         card->hw.intctl_reg = 0x4c;
3592
3593                         if ((cpc_readl(card->hw.plxbase + card->hw.gpioc_reg) & PC300_CTYPE_MASK)) {
3594                                 card->hw.type = PC300_X21;
3595                         } else {
3596                                 card->hw.type = PC300_RSV;
3597                         }
3598                         break;
3599         }
3600
3601         /* Allocate IRQ */
3602         if (request_irq(card->hw.irq, cpc_intr, SA_SHIRQ, "Cyclades-PC300", card)) {
3603                 printk ("PC300 found at RAM 0x%08x, but could not allocate IRQ%d.\n",
3604                          card->hw.ramphys, card->hw.irq);
3605                 goto err_io_unmap;
3606         }
3607
3608         cpc_init_card(card);
3609
3610         if (eeprom_outdated)
3611                 printk("WARNING: PC300 with outdated EEPROM.\n");
3612         return 0;
3613
3614 err_io_unmap:
3615         iounmap(card->hw.plxbase);
3616         iounmap(card->hw.scabase);
3617         iounmap(card->hw.rambase);
3618         if (card->hw.type == PC300_TE) {
3619                 iounmap(card->hw.falcbase);
3620                 release_mem_region(card->hw.falcphys, card->hw.falcsize);
3621         }
3622 err_release_sca:
3623         release_mem_region(card->hw.scaphys, card->hw.scasize);
3624 err_release_ram:
3625         release_mem_region(card->hw.ramphys, card->hw.alloc_ramsize);
3626 err_release_plx:
3627         release_mem_region(card->hw.plxphys, card->hw.plxsize);
3628 err_release_io:
3629         release_region(card->hw.iophys, card->hw.iosize);
3630         kfree(card);
3631         return -ENODEV;
3632 }
3633
3634 static void __devexit cpc_remove_one(struct pci_dev *pdev)
3635 {
3636         pc300_t *card = pci_get_drvdata(pdev);
3637
3638         if (card->hw.rambase != 0) {
3639                 int i;
3640
3641                 /* Disable interrupts on the PCI bridge */
3642                 cpc_writew(card->hw.plxbase + card->hw.intctl_reg,
3643                            cpc_readw(card->hw.plxbase + card->hw.intctl_reg) & ~(0x0040));
3644
3645                 for (i = 0; i < card->hw.nchan; i++) {
3646                         unregister_hdlc_device(card->chan[i].d.dev);
3647                 }
3648                 iounmap(card->hw.plxbase);
3649                 iounmap(card->hw.scabase);
3650                 iounmap(card->hw.rambase);
3651                 release_mem_region(card->hw.plxphys, card->hw.plxsize);
3652                 release_mem_region(card->hw.ramphys, card->hw.alloc_ramsize);
3653                 release_mem_region(card->hw.scaphys, card->hw.scasize);
3654                 release_region(card->hw.iophys, card->hw.iosize);
3655                 if (card->hw.type == PC300_TE) {
3656                         iounmap(card->hw.falcbase);
3657                         release_mem_region(card->hw.falcphys, card->hw.falcsize);
3658                 }
3659                 for (i = 0; i < card->hw.nchan; i++)
3660                         if (card->chan[i].d.dev)
3661                                 free_netdev(card->chan[i].d.dev);
3662                 if (card->hw.irq)
3663                         free_irq(card->hw.irq, card);
3664                 kfree(card);
3665         }
3666 }
3667
3668 static struct pci_driver cpc_driver = {
3669         .name           = "pc300",
3670         .id_table       = cpc_pci_dev_id,
3671         .probe          = cpc_init_one,
3672         .remove         = __devexit_p(cpc_remove_one),
3673 };
3674
3675 static int __init cpc_init(void)
3676 {
3677         return pci_module_init(&cpc_driver);
3678 }
3679
3680 static void __exit cpc_cleanup_module(void)
3681 {
3682         pci_unregister_driver(&cpc_driver);
3683 }
3684
3685 module_init(cpc_init);
3686 module_exit(cpc_cleanup_module);
3687
3688 MODULE_DESCRIPTION("Cyclades-PC300 cards driver");
3689 MODULE_AUTHOR(  "Author: Ivan Passos <ivan@cyclades.com>\r\n"
3690                 "Maintainer: PC300 Maintainer <pc300@cyclades.com");
3691 MODULE_LICENSE("GPL");
3692