SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/net/tg3.c

   1 /*
   2  * tg3.c: Broadcom Tigon3 ethernet driver.
   3  *
   4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
   5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
   6  * Copyright (C) 2004 Sun Microsystems Inc.
   7  * Copyright (C) 2005-2009 Broadcom Corporation.
   8  *
   9  * Firmware is:
  10  *      Derived from proprietary unpublished source code,
  11  *      Copyright (C) 2000-2003 Broadcom Corporation.
  12  *
  13  *      Permission is hereby granted for the distribution of this firmware
  14  *      data in hexadecimal or equivalent format, provided this copyright
  15  *      notice is accompanying it.
  16  */
  17
  18
  19 #include <linux/module.h>
  20 #include <linux/moduleparam.h>
  21 #include <linux/kernel.h>
  22 #include <linux/types.h>
  23 #include <linux/compiler.h>
  24 #include <linux/slab.h>
  25 #include <linux/delay.h>
  26 #include <linux/in.h>
  27 #include <linux/init.h>
  28 #include <linux/ioport.h>
  29 #include <linux/pci.h>
  30 #include <linux/netdevice.h>
  31 #include <linux/etherdevice.h>
  32 #include <linux/skbuff.h>
  33 #include <linux/ethtool.h>
  34 #include <linux/mii.h>
  35 #include <linux/phy.h>
  36 #include <linux/brcmphy.h>
  37 #include <linux/if_vlan.h>
  38 #include <linux/ip.h>
  39 #include <linux/tcp.h>
  40 #include <linux/workqueue.h>
  41 #include <linux/prefetch.h>
  42 #include <linux/dma-mapping.h>
  43 #include <linux/firmware.h>
  44
  45 #include <net/checksum.h>
  46 #include <net/ip.h>
  47
  48 #include <asm/system.h>
  49 #include <asm/io.h>
  50 #include <asm/byteorder.h>
  51 #include <asm/uaccess.h>
  52
  53 #ifdef CONFIG_SPARC
  54 #include <asm/idprom.h>
  55 #include <asm/prom.h>
  56 #endif
  57
  58 #define BAR_0   0
  59 #define BAR_2   2
  60
  61 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  62 #define TG3_VLAN_TAG_USED 1
  63 #else
  64 #define TG3_VLAN_TAG_USED 0
  65 #endif
  66
  67 #include "tg3.h"
  68
  69 #define DRV_MODULE_NAME         "tg3"
  70 #define PFX DRV_MODULE_NAME     ": "
  71 #define DRV_MODULE_VERSION      "3.105"
  72 #define DRV_MODULE_RELDATE      "December 2, 2009"
  73
  74 #define TG3_DEF_MAC_MODE        0
  75 #define TG3_DEF_RX_MODE         0
  76 #define TG3_DEF_TX_MODE         0
  77 #define TG3_DEF_MSG_ENABLE        \
  78         (NETIF_MSG_DRV          | \
  79          NETIF_MSG_PROBE        | \
  80          NETIF_MSG_LINK         | \
  81          NETIF_MSG_TIMER        | \
  82          NETIF_MSG_IFDOWN       | \
  83          NETIF_MSG_IFUP         | \
  84          NETIF_MSG_RX_ERR       | \
  85          NETIF_MSG_TX_ERR)
  86
  87 /* length of time before we decide the hardware is borked,
  88  * and dev->tx_timeout() should be called to fix the problem
  89  */
  90 #define TG3_TX_TIMEOUT                  (5 * HZ)
  91
  92 /* hardware minimum and maximum for a single frame's data payload */
  93 #define TG3_MIN_MTU                     60
  94 #define TG3_MAX_MTU(tp) \
  95         ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
  96
  97 /* These numbers seem to be hard coded in the NIC firmware somehow.
  98  * You can't change the ring sizes, but you can change where you place
  99  * them in the NIC onboard memory.
 100  */
 101 #define TG3_RX_RING_SIZE                512
 102 #define TG3_DEF_RX_RING_PENDING         200
 103 #define TG3_RX_JUMBO_RING_SIZE          256
 104 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
 105 #define TG3_RSS_INDIR_TBL_SIZE 128
 106
 107 /* Do not place this n-ring entries value into the tp struct itself,
 108  * we really want to expose these constants to GCC so that modulo et
 109  * al.  operations are done with shifts and masks instead of with
 110  * hw multiply/modulo instructions.  Another solution would be to
 111  * replace things like '% foo' with '& (foo - 1)'.
 112  */
 113 #define TG3_RX_RCB_RING_SIZE(tp)        \
 114         (((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) && \
 115           !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) ? 1024 : 512)
 116
 117 #define TG3_TX_RING_SIZE                512
 118 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
 119
 120 #define TG3_RX_RING_BYTES       (sizeof(struct tg3_rx_buffer_desc) * \
 121                                  TG3_RX_RING_SIZE)
 122 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_ext_rx_buffer_desc) * \
 123                                  TG3_RX_JUMBO_RING_SIZE)
 124 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
 125                                  TG3_RX_RCB_RING_SIZE(tp))
 126 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
 127                                  TG3_TX_RING_SIZE)
 128 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
 129
 130 #define TG3_DMA_BYTE_ENAB               64
 131
 132 #define TG3_RX_STD_DMA_SZ               1536
 133 #define TG3_RX_JMB_DMA_SZ               9046
 134
 135 #define TG3_RX_DMA_TO_MAP_SZ(x)         ((x) + TG3_DMA_BYTE_ENAB)
 136
 137 #define TG3_RX_STD_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
 138 #define TG3_RX_JMB_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
 139
 140 #define TG3_RX_STD_BUFF_RING_SIZE \
 141         (sizeof(struct ring_info) * TG3_RX_RING_SIZE)
 142
 143 #define TG3_RX_JMB_BUFF_RING_SIZE \
 144         (sizeof(struct ring_info) * TG3_RX_JUMBO_RING_SIZE)
 145
 146 /* minimum number of free TX descriptors required to wake up TX process */
 147 #define TG3_TX_WAKEUP_THRESH(tnapi)             ((tnapi)->tx_pending / 4)
 148
 149 #define TG3_RAW_IP_ALIGN 2
 150
 151 /* number of ETHTOOL_GSTATS u64's */
 152 #define TG3_NUM_STATS           (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
 153
 154 #define TG3_NUM_TEST            6
 155
 156 #define FIRMWARE_TG3            "tigon/tg3.bin"
 157 #define FIRMWARE_TG3TSO         "tigon/tg3_tso.bin"
 158 #define FIRMWARE_TG3TSO5        "tigon/tg3_tso5.bin"
 159
 160 static char version[] __devinitdata =
 161         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
 162
 163 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
 164 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
 165 MODULE_LICENSE("GPL");
 166 MODULE_VERSION(DRV_MODULE_VERSION);
 167 MODULE_FIRMWARE(FIRMWARE_TG3);
 168 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
 169 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
 170
 171 #define TG3_RSS_MIN_NUM_MSIX_VECS       2
 172
 173 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
 174 module_param(tg3_debug, int, 0);
 175 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
 176
 177 static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
 178         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
 179         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
 180         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
 181         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
 182         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
 183         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
 184         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
 185         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
 186         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
 187         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
 188         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
 189         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
 190         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
 191         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
 192         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
 193         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
 194         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
 195         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
 196         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
 197         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
 198         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
 199         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
 200         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
 201         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
 202         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
 203         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
 204         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
 205         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
 206         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
 207         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
 208         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
 209         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
 210         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
 211         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
 212         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
 213         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
 214         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
 215         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
 216         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
 217         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
 218         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
 219         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
 220         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
 221         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
 222         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
 223         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
 224         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
 225         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
 226         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
 227         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
 228         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
 229         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
 230         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
 231         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
 232         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
 233         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
 234         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
 235         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
 236         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
 237         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
 238         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
 239         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
 240         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
 241         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
 242         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
 243         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
 244         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
 245         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
 246         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5724)},
 247         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
 248         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
 249         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
 250         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
 251         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
 252         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
 253         {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
 254         {}
 255 };
 256
 257 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
 258
 259 static const struct {
 260         const char string[ETH_GSTRING_LEN];
 261 } ethtool_stats_keys[TG3_NUM_STATS] = {
 262         { "rx_octets" },
 263         { "rx_fragments" },
 264         { "rx_ucast_packets" },
 265         { "rx_mcast_packets" },
 266         { "rx_bcast_packets" },
 267         { "rx_fcs_errors" },
 268         { "rx_align_errors" },
 269         { "rx_xon_pause_rcvd" },
 270         { "rx_xoff_pause_rcvd" },
 271         { "rx_mac_ctrl_rcvd" },
 272         { "rx_xoff_entered" },
 273         { "rx_frame_too_long_errors" },
 274         { "rx_jabbers" },
 275         { "rx_undersize_packets" },
 276         { "rx_in_length_errors" },
 277         { "rx_out_length_errors" },
 278         { "rx_64_or_less_octet_packets" },
 279         { "rx_65_to_127_octet_packets" },
 280         { "rx_128_to_255_octet_packets" },
 281         { "rx_256_to_511_octet_packets" },
 282         { "rx_512_to_1023_octet_packets" },
 283         { "rx_1024_to_1522_octet_packets" },
 284         { "rx_1523_to_2047_octet_packets" },
 285         { "rx_2048_to_4095_octet_packets" },
 286         { "rx_4096_to_8191_octet_packets" },
 287         { "rx_8192_to_9022_octet_packets" },
 288
 289         { "tx_octets" },
 290         { "tx_collisions" },
 291
 292         { "tx_xon_sent" },
 293         { "tx_xoff_sent" },
 294         { "tx_flow_control" },
 295         { "tx_mac_errors" },
 296         { "tx_single_collisions" },
 297         { "tx_mult_collisions" },
 298         { "tx_deferred" },
 299         { "tx_excessive_collisions" },
 300         { "tx_late_collisions" },
 301         { "tx_collide_2times" },
 302         { "tx_collide_3times" },
 303         { "tx_collide_4times" },
 304         { "tx_collide_5times" },
 305         { "tx_collide_6times" },
 306         { "tx_collide_7times" },
 307         { "tx_collide_8times" },
 308         { "tx_collide_9times" },
 309         { "tx_collide_10times" },
 310         { "tx_collide_11times" },
 311         { "tx_collide_12times" },
 312         { "tx_collide_13times" },
 313         { "tx_collide_14times" },
 314         { "tx_collide_15times" },
 315         { "tx_ucast_packets" },
 316         { "tx_mcast_packets" },
 317         { "tx_bcast_packets" },
 318         { "tx_carrier_sense_errors" },
 319         { "tx_discards" },
 320         { "tx_errors" },
 321
 322         { "dma_writeq_full" },
 323         { "dma_write_prioq_full" },
 324         { "rxbds_empty" },
 325         { "rx_discards" },
 326         { "rx_errors" },
 327         { "rx_threshold_hit" },
 328
 329         { "dma_readq_full" },
 330         { "dma_read_prioq_full" },
 331         { "tx_comp_queue_full" },
 332
 333         { "ring_set_send_prod_index" },
 334         { "ring_status_update" },
 335         { "nic_irqs" },
 336         { "nic_avoided_irqs" },
 337         { "nic_tx_threshold_hit" }
 338 };
 339
 340 static const struct {
 341         const char string[ETH_GSTRING_LEN];
 342 } ethtool_test_keys[TG3_NUM_TEST] = {
 343         { "nvram test     (online) " },
 344         { "link test      (online) " },
 345         { "register test  (offline)" },
 346         { "memory test    (offline)" },
 347         { "loopback test  (offline)" },
 348         { "interrupt test (offline)" },
 349 };
 350
 351 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
 352 {
 353         writel(val, tp->regs + off);
 354 }
 355
 356 static u32 tg3_read32(struct tg3 *tp, u32 off)
 357 {
 358         return (readl(tp->regs + off));
 359 }
 360
 361 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
 362 {
 363         writel(val, tp->aperegs + off);
 364 }
 365
 366 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
 367 {
 368         return (readl(tp->aperegs + off));
 369 }
 370
 371 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
 372 {
 373         unsigned long flags;
 374
 375         spin_lock_irqsave(&tp->indirect_lock, flags);
 376         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 377         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 378         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 379 }
 380
 381 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
 382 {
 383         writel(val, tp->regs + off);
 384         readl(tp->regs + off);
 385 }
 386
 387 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
 388 {
 389         unsigned long flags;
 390         u32 val;
 391
 392         spin_lock_irqsave(&tp->indirect_lock, flags);
 393         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 394         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 395         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 396         return val;
 397 }
 398
 399 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
 400 {
 401         unsigned long flags;
 402
 403         if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
 404                 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
 405                                        TG3_64BIT_REG_LOW, val);
 406                 return;
 407         }
 408         if (off == TG3_RX_STD_PROD_IDX_REG) {
 409                 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
 410                                        TG3_64BIT_REG_LOW, val);
 411                 return;
 412         }
 413
 414         spin_lock_irqsave(&tp->indirect_lock, flags);
 415         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 416         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 417         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 418
 419         /* In indirect mode when disabling interrupts, we also need
 420          * to clear the interrupt bit in the GRC local ctrl register.
 421          */
 422         if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
 423             (val == 0x1)) {
 424                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
 425                                        tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
 426         }
 427 }
 428
 429 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
 430 {
 431         unsigned long flags;
 432         u32 val;
 433
 434         spin_lock_irqsave(&tp->indirect_lock, flags);
 435         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 436         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 437         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 438         return val;
 439 }
 440
 441 /* usec_wait specifies the wait time in usec when writing to certain registers
 442  * where it is unsafe to read back the register without some delay.
 443  * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
 444  * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
 445  */
 446 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
 447 {
 448         if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
 449             (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 450                 /* Non-posted methods */
 451                 tp->write32(tp, off, val);
 452         else {
 453                 /* Posted method */
 454                 tg3_write32(tp, off, val);
 455                 if (usec_wait)
 456                         udelay(usec_wait);
 457                 tp->read32(tp, off);
 458         }
 459         /* Wait again after the read for the posted method to guarantee that
 460          * the wait time is met.
 461          */
 462         if (usec_wait)
 463                 udelay(usec_wait);
 464 }
 465
 466 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
 467 {
 468         tp->write32_mbox(tp, off, val);
 469         if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
 470             !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 471                 tp->read32_mbox(tp, off);
 472 }
 473
 474 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
 475 {
 476         void __iomem *mbox = tp->regs + off;
 477         writel(val, mbox);
 478         if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
 479                 writel(val, mbox);
 480         if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
 481                 readl(mbox);
 482 }
 483
 484 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
 485 {
 486         return (readl(tp->regs + off + GRCMBOX_BASE));
 487 }
 488
 489 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
 490 {
 491         writel(val, tp->regs + off + GRCMBOX_BASE);
 492 }
 493
 494 #define tw32_mailbox(reg, val)  tp->write32_mbox(tp, reg, val)
 495 #define tw32_mailbox_f(reg, val)        tw32_mailbox_flush(tp, (reg), (val))
 496 #define tw32_rx_mbox(reg, val)  tp->write32_rx_mbox(tp, reg, val)
 497 #define tw32_tx_mbox(reg, val)  tp->write32_tx_mbox(tp, reg, val)
 498 #define tr32_mailbox(reg)       tp->read32_mbox(tp, reg)
 499
 500 #define tw32(reg,val)           tp->write32(tp, reg, val)
 501 #define tw32_f(reg,val)         _tw32_flush(tp,(reg),(val), 0)
 502 #define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
 503 #define tr32(reg)               tp->read32(tp, reg)
 504
 505 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
 506 {
 507         unsigned long flags;
 508
 509         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 510             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
 511                 return;
 512
 513         spin_lock_irqsave(&tp->indirect_lock, flags);
 514         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 515                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 516                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 517
 518                 /* Always leave this as zero. */
 519                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 520         } else {
 521                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 522                 tw32_f(TG3PCI_MEM_WIN_DATA, val);
 523
 524                 /* Always leave this as zero. */
 525                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 526         }
 527         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 528 }
 529
 530 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
 531 {
 532         unsigned long flags;
 533
 534         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 535             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
 536                 *val = 0;
 537                 return;
 538         }
 539
 540         spin_lock_irqsave(&tp->indirect_lock, flags);
 541         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 542                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 543                 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 544
 545                 /* Always leave this as zero. */
 546                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 547         } else {
 548                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 549                 *val = tr32(TG3PCI_MEM_WIN_DATA);
 550
 551                 /* Always leave this as zero. */
 552                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 553         }
 554         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 555 }
 556
 557 static void tg3_ape_lock_init(struct tg3 *tp)
 558 {
 559         int i;
 560
 561         /* Make sure the driver hasn't any stale locks. */
 562         for (i = 0; i < 8; i++)
 563                 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + 4 * i,
 564                                 APE_LOCK_GRANT_DRIVER);
 565 }
 566
 567 static int tg3_ape_lock(struct tg3 *tp, int locknum)
 568 {
 569         int i, off;
 570         int ret = 0;
 571         u32 status;
 572
 573         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 574                 return 0;
 575
 576         switch (locknum) {
 577                 case TG3_APE_LOCK_GRC:
 578                 case TG3_APE_LOCK_MEM:
 579                         break;
 580                 default:
 581                         return -EINVAL;
 582         }
 583
 584         off = 4 * locknum;
 585
 586         tg3_ape_write32(tp, TG3_APE_LOCK_REQ + off, APE_LOCK_REQ_DRIVER);
 587
 588         /* Wait for up to 1 millisecond to acquire lock. */
 589         for (i = 0; i < 100; i++) {
 590                 status = tg3_ape_read32(tp, TG3_APE_LOCK_GRANT + off);
 591                 if (status == APE_LOCK_GRANT_DRIVER)
 592                         break;
 593                 udelay(10);
 594         }
 595
 596         if (status != APE_LOCK_GRANT_DRIVER) {
 597                 /* Revoke the lock request. */
 598                 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off,
 599                                 APE_LOCK_GRANT_DRIVER);
 600
 601                 ret = -EBUSY;
 602         }
 603
 604         return ret;
 605 }
 606
 607 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
 608 {
 609         int off;
 610
 611         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 612                 return;
 613
 614         switch (locknum) {
 615                 case TG3_APE_LOCK_GRC:
 616                 case TG3_APE_LOCK_MEM:
 617                         break;
 618                 default:
 619                         return;
 620         }
 621
 622         off = 4 * locknum;
 623         tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, APE_LOCK_GRANT_DRIVER);
 624 }
 625
 626 static void tg3_disable_ints(struct tg3 *tp)
 627 {
 628         int i;
 629
 630         tw32(TG3PCI_MISC_HOST_CTRL,
 631              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
 632         for (i = 0; i < tp->irq_max; i++)
 633                 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
 634 }
 635
 636 static void tg3_enable_ints(struct tg3 *tp)
 637 {
 638         int i;
 639         u32 coal_now = 0;
 640
 641         tp->irq_sync = 0;
 642         wmb();
 643
 644         tw32(TG3PCI_MISC_HOST_CTRL,
 645              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
 646
 647         for (i = 0; i < tp->irq_cnt; i++) {
 648                 struct tg3_napi *tnapi = &tp->napi[i];
 649                 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
 650                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
 651                         tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
 652
 653                 coal_now |= tnapi->coal_now;
 654         }
 655
 656         /* Force an initial interrupt */
 657         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 658             (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
 659                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
 660         else
 661                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 662                      HOSTCC_MODE_ENABLE | coal_now);
 663 }
 664
 665 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
 666 {
 667         struct tg3 *tp = tnapi->tp;
 668         struct tg3_hw_status *sblk = tnapi->hw_status;
 669         unsigned int work_exists = 0;
 670
 671         /* check for phy events */
 672         if (!(tp->tg3_flags &
 673               (TG3_FLAG_USE_LINKCHG_REG |
 674                TG3_FLAG_POLL_SERDES))) {
 675                 if (sblk->status & SD_STATUS_LINK_CHG)
 676                         work_exists = 1;
 677         }
 678         /* check for RX/TX work to do */
 679         if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
 680             *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
 681                 work_exists = 1;
 682
 683         return work_exists;
 684 }
 685
 686 /* tg3_int_reenable
 687  *  similar to tg3_enable_ints, but it accurately determines whether there
 688  *  is new work pending and can return without flushing the PIO write
 689  *  which reenables interrupts
 690  */
 691 static void tg3_int_reenable(struct tg3_napi *tnapi)
 692 {
 693         struct tg3 *tp = tnapi->tp;
 694
 695         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
 696         mmiowb();
 697
 698         /* When doing tagged status, this work check is unnecessary.
 699          * The last_tag we write above tells the chip which piece of
 700          * work we've completed.
 701          */
 702         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 703             tg3_has_work(tnapi))
 704                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 705                      HOSTCC_MODE_ENABLE | tnapi->coal_now);
 706 }
 707
 708 static void tg3_napi_disable(struct tg3 *tp)
 709 {
 710         int i;
 711
 712         for (i = tp->irq_cnt - 1; i >= 0; i--)
 713                 napi_disable(&tp->napi[i].napi);
 714 }
 715
 716 static void tg3_napi_enable(struct tg3 *tp)
 717 {
 718         int i;
 719
 720         for (i = 0; i < tp->irq_cnt; i++)
 721                 napi_enable(&tp->napi[i].napi);
 722 }
 723
 724 static inline void tg3_netif_stop(struct tg3 *tp)
 725 {
 726         tp->dev->trans_start = jiffies; /* prevent tx timeout */
 727         tg3_napi_disable(tp);
 728         netif_tx_disable(tp->dev);
 729 }
 730
 731 static inline void tg3_netif_start(struct tg3 *tp)
 732 {
 733         /* NOTE: unconditional netif_tx_wake_all_queues is only
 734          * appropriate so long as all callers are assured to
 735          * have free tx slots (such as after tg3_init_hw)
 736          */
 737         netif_tx_wake_all_queues(tp->dev);
 738
 739         tg3_napi_enable(tp);
 740         tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
 741         tg3_enable_ints(tp);
 742 }
 743
 744 static void tg3_switch_clocks(struct tg3 *tp)
 745 {
 746         u32 clock_ctrl;
 747         u32 orig_clock_ctrl;
 748
 749         if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
 750             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
 751                 return;
 752
 753         clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
 754
 755         orig_clock_ctrl = clock_ctrl;
 756         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
 757                        CLOCK_CTRL_CLKRUN_OENABLE |
 758                        0x1f);
 759         tp->pci_clock_ctrl = clock_ctrl;
 760
 761         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
 762                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
 763                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
 764                                     clock_ctrl | CLOCK_CTRL_625_CORE, 40);
 765                 }
 766         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
 767                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 768                             clock_ctrl |
 769                             (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
 770                             40);
 771                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 772                             clock_ctrl | (CLOCK_CTRL_ALTCLK),
 773                             40);
 774         }
 775         tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
 776 }
 777
 778 #define PHY_BUSY_LOOPS  5000
 779
 780 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
 781 {
 782         u32 frame_val;
 783         unsigned int loops;
 784         int ret;
 785
 786         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 787                 tw32_f(MAC_MI_MODE,
 788                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 789                 udelay(80);
 790         }
 791
 792         *val = 0x0;
 793
 794         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
 795                       MI_COM_PHY_ADDR_MASK);
 796         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 797                       MI_COM_REG_ADDR_MASK);
 798         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
 799
 800         tw32_f(MAC_MI_COM, frame_val);
 801
 802         loops = PHY_BUSY_LOOPS;
 803         while (loops != 0) {
 804                 udelay(10);
 805                 frame_val = tr32(MAC_MI_COM);
 806
 807                 if ((frame_val & MI_COM_BUSY) == 0) {
 808                         udelay(5);
 809                         frame_val = tr32(MAC_MI_COM);
 810                         break;
 811                 }
 812                 loops -= 1;
 813         }
 814
 815         ret = -EBUSY;
 816         if (loops != 0) {
 817                 *val = frame_val & MI_COM_DATA_MASK;
 818                 ret = 0;
 819         }
 820
 821         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 822                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 823                 udelay(80);
 824         }
 825
 826         return ret;
 827 }
 828
 829 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
 830 {
 831         u32 frame_val;
 832         unsigned int loops;
 833         int ret;
 834
 835         if ((tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
 836             (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
 837                 return 0;
 838
 839         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 840                 tw32_f(MAC_MI_MODE,
 841                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 842                 udelay(80);
 843         }
 844
 845         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
 846                       MI_COM_PHY_ADDR_MASK);
 847         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 848                       MI_COM_REG_ADDR_MASK);
 849         frame_val |= (val & MI_COM_DATA_MASK);
 850         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
 851
 852         tw32_f(MAC_MI_COM, frame_val);
 853
 854         loops = PHY_BUSY_LOOPS;
 855         while (loops != 0) {
 856                 udelay(10);
 857                 frame_val = tr32(MAC_MI_COM);
 858                 if ((frame_val & MI_COM_BUSY) == 0) {
 859                         udelay(5);
 860                         frame_val = tr32(MAC_MI_COM);
 861                         break;
 862                 }
 863                 loops -= 1;
 864         }
 865
 866         ret = -EBUSY;
 867         if (loops != 0)
 868                 ret = 0;
 869
 870         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 871                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 872                 udelay(80);
 873         }
 874
 875         return ret;
 876 }
 877
 878 static int tg3_bmcr_reset(struct tg3 *tp)
 879 {
 880         u32 phy_control;
 881         int limit, err;
 882
 883         /* OK, reset it, and poll the BMCR_RESET bit until it
 884          * clears or we time out.
 885          */
 886         phy_control = BMCR_RESET;
 887         err = tg3_writephy(tp, MII_BMCR, phy_control);
 888         if (err != 0)
 889                 return -EBUSY;
 890
 891         limit = 5000;
 892         while (limit--) {
 893                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
 894                 if (err != 0)
 895                         return -EBUSY;
 896
 897                 if ((phy_control & BMCR_RESET) == 0) {
 898                         udelay(40);
 899                         break;
 900                 }
 901                 udelay(10);
 902         }
 903         if (limit < 0)
 904                 return -EBUSY;
 905
 906         return 0;
 907 }
 908
 909 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
 910 {
 911         struct tg3 *tp = bp->priv;
 912         u32 val;
 913
 914         spin_lock_bh(&tp->lock);
 915
 916         if (tg3_readphy(tp, reg, &val))
 917                 val = -EIO;
 918
 919         spin_unlock_bh(&tp->lock);
 920
 921         return val;
 922 }
 923
 924 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
 925 {
 926         struct tg3 *tp = bp->priv;
 927         u32 ret = 0;
 928
 929         spin_lock_bh(&tp->lock);
 930
 931         if (tg3_writephy(tp, reg, val))
 932                 ret = -EIO;
 933
 934         spin_unlock_bh(&tp->lock);
 935
 936         return ret;
 937 }
 938
 939 static int tg3_mdio_reset(struct mii_bus *bp)
 940 {
 941         return 0;
 942 }
 943
 944 static void tg3_mdio_config_5785(struct tg3 *tp)
 945 {
 946         u32 val;
 947         struct phy_device *phydev;
 948
 949         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
 950         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
 951         case TG3_PHY_ID_BCM50610:
 952         case TG3_PHY_ID_BCM50610M:
 953                 val = MAC_PHYCFG2_50610_LED_MODES;
 954                 break;
 955         case TG3_PHY_ID_BCMAC131:
 956                 val = MAC_PHYCFG2_AC131_LED_MODES;
 957                 break;
 958         case TG3_PHY_ID_RTL8211C:
 959                 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
 960                 break;
 961         case TG3_PHY_ID_RTL8201E:
 962                 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
 963                 break;
 964         default:
 965                 return;
 966         }
 967
 968         if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
 969                 tw32(MAC_PHYCFG2, val);
 970
 971                 val = tr32(MAC_PHYCFG1);
 972                 val &= ~(MAC_PHYCFG1_RGMII_INT |
 973                          MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
 974                 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
 975                 tw32(MAC_PHYCFG1, val);
 976
 977                 return;
 978         }
 979
 980         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE))
 981                 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
 982                        MAC_PHYCFG2_FMODE_MASK_MASK |
 983                        MAC_PHYCFG2_GMODE_MASK_MASK |
 984                        MAC_PHYCFG2_ACT_MASK_MASK   |
 985                        MAC_PHYCFG2_QUAL_MASK_MASK |
 986                        MAC_PHYCFG2_INBAND_ENABLE;
 987
 988         tw32(MAC_PHYCFG2, val);
 989
 990         val = tr32(MAC_PHYCFG1);
 991         val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
 992                  MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
 993         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
 994                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
 995                         val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
 996                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
 997                         val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
 998         }
 999         val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1000                MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1001         tw32(MAC_PHYCFG1, val);
1002
1003         val = tr32(MAC_EXT_RGMII_MODE);
1004         val &= ~(MAC_RGMII_MODE_RX_INT_B |
1005                  MAC_RGMII_MODE_RX_QUALITY |
1006                  MAC_RGMII_MODE_RX_ACTIVITY |
1007                  MAC_RGMII_MODE_RX_ENG_DET |
1008                  MAC_RGMII_MODE_TX_ENABLE |
1009                  MAC_RGMII_MODE_TX_LOWPWR |
1010                  MAC_RGMII_MODE_TX_RESET);
1011         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
1012                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1013                         val |= MAC_RGMII_MODE_RX_INT_B |
1014                                MAC_RGMII_MODE_RX_QUALITY |
1015                                MAC_RGMII_MODE_RX_ACTIVITY |
1016                                MAC_RGMII_MODE_RX_ENG_DET;
1017                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1018                         val |= MAC_RGMII_MODE_TX_ENABLE |
1019                                MAC_RGMII_MODE_TX_LOWPWR |
1020                                MAC_RGMII_MODE_TX_RESET;
1021         }
1022         tw32(MAC_EXT_RGMII_MODE, val);
1023 }
1024
1025 static void tg3_mdio_start(struct tg3 *tp)
1026 {
1027         tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1028         tw32_f(MAC_MI_MODE, tp->mi_mode);
1029         udelay(80);
1030
1031         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
1032                 u32 funcnum, is_serdes;
1033
1034                 funcnum = tr32(TG3_CPMU_STATUS) & TG3_CPMU_STATUS_PCIE_FUNC;
1035                 if (funcnum)
1036                         tp->phy_addr = 2;
1037                 else
1038                         tp->phy_addr = 1;
1039
1040                 is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1041                 if (is_serdes)
1042                         tp->phy_addr += 7;
1043         } else
1044                 tp->phy_addr = TG3_PHY_MII_ADDR;
1045
1046         if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
1047             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1048                 tg3_mdio_config_5785(tp);
1049 }
1050
1051 static int tg3_mdio_init(struct tg3 *tp)
1052 {
1053         int i;
1054         u32 reg;
1055         struct phy_device *phydev;
1056
1057         tg3_mdio_start(tp);
1058
1059         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1060             (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1061                 return 0;
1062
1063         tp->mdio_bus = mdiobus_alloc();
1064         if (tp->mdio_bus == NULL)
1065                 return -ENOMEM;
1066
1067         tp->mdio_bus->name     = "tg3 mdio bus";
1068         snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1069                  (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1070         tp->mdio_bus->priv     = tp;
1071         tp->mdio_bus->parent   = &tp->pdev->dev;
1072         tp->mdio_bus->read     = &tg3_mdio_read;
1073         tp->mdio_bus->write    = &tg3_mdio_write;
1074         tp->mdio_bus->reset    = &tg3_mdio_reset;
1075         tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
1076         tp->mdio_bus->irq      = &tp->mdio_irq[0];
1077
1078         for (i = 0; i < PHY_MAX_ADDR; i++)
1079                 tp->mdio_bus->irq[i] = PHY_POLL;
1080
1081         /* The bus registration will look for all the PHYs on the mdio bus.
1082          * Unfortunately, it does not ensure the PHY is powered up before
1083          * accessing the PHY ID registers.  A chip reset is the
1084          * quickest way to bring the device back to an operational state..
1085          */
1086         if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1087                 tg3_bmcr_reset(tp);
1088
1089         i = mdiobus_register(tp->mdio_bus);
1090         if (i) {
1091                 printk(KERN_WARNING "%s: mdiobus_reg failed (0x%x)\n",
1092                         tp->dev->name, i);
1093                 mdiobus_free(tp->mdio_bus);
1094                 return i;
1095         }
1096
1097         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1098
1099         if (!phydev || !phydev->drv) {
1100                 printk(KERN_WARNING "%s: No PHY devices\n", tp->dev->name);
1101                 mdiobus_unregister(tp->mdio_bus);
1102                 mdiobus_free(tp->mdio_bus);
1103                 return -ENODEV;
1104         }
1105
1106         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1107         case TG3_PHY_ID_BCM57780:
1108                 phydev->interface = PHY_INTERFACE_MODE_GMII;
1109                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1110                 break;
1111         case TG3_PHY_ID_BCM50610:
1112         case TG3_PHY_ID_BCM50610M:
1113                 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
1114                                      PHY_BRCM_RX_REFCLK_UNUSED |
1115                                      PHY_BRCM_DIS_TXCRXC_NOENRGY |
1116                                      PHY_BRCM_AUTO_PWRDWN_ENABLE;
1117                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)
1118                         phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1119                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1120                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1121                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1122                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1123                 /* fallthru */
1124         case TG3_PHY_ID_RTL8211C:
1125                 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1126                 break;
1127         case TG3_PHY_ID_RTL8201E:
1128         case TG3_PHY_ID_BCMAC131:
1129                 phydev->interface = PHY_INTERFACE_MODE_MII;
1130                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1131                 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
1132                 break;
1133         }
1134
1135         tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1136
1137         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1138                 tg3_mdio_config_5785(tp);
1139
1140         return 0;
1141 }
1142
1143 static void tg3_mdio_fini(struct tg3 *tp)
1144 {
1145         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1146                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
1147                 mdiobus_unregister(tp->mdio_bus);
1148                 mdiobus_free(tp->mdio_bus);
1149         }
1150 }
1151
1152 /* tp->lock is held. */
1153 static inline void tg3_generate_fw_event(struct tg3 *tp)
1154 {
1155         u32 val;
1156
1157         val = tr32(GRC_RX_CPU_EVENT);
1158         val |= GRC_RX_CPU_DRIVER_EVENT;
1159         tw32_f(GRC_RX_CPU_EVENT, val);
1160
1161         tp->last_event_jiffies = jiffies;
1162 }
1163
1164 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1165
1166 /* tp->lock is held. */
1167 static void tg3_wait_for_event_ack(struct tg3 *tp)
1168 {
1169         int i;
1170         unsigned int delay_cnt;
1171         long time_remain;
1172
1173         /* If enough time has passed, no wait is necessary. */
1174         time_remain = (long)(tp->last_event_jiffies + 1 +
1175                       usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1176                       (long)jiffies;
1177         if (time_remain < 0)
1178                 return;
1179
1180         /* Check if we can shorten the wait time. */
1181         delay_cnt = jiffies_to_usecs(time_remain);
1182         if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1183                 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1184         delay_cnt = (delay_cnt >> 3) + 1;
1185
1186         for (i = 0; i < delay_cnt; i++) {
1187                 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1188                         break;
1189                 udelay(8);
1190         }
1191 }
1192
1193 /* tp->lock is held. */
1194 static void tg3_ump_link_report(struct tg3 *tp)
1195 {
1196         u32 reg;
1197         u32 val;
1198
1199         if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1200             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
1201                 return;
1202
1203         tg3_wait_for_event_ack(tp);
1204
1205         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1206
1207         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1208
1209         val = 0;
1210         if (!tg3_readphy(tp, MII_BMCR, &reg))
1211                 val = reg << 16;
1212         if (!tg3_readphy(tp, MII_BMSR, &reg))
1213                 val |= (reg & 0xffff);
1214         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1215
1216         val = 0;
1217         if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1218                 val = reg << 16;
1219         if (!tg3_readphy(tp, MII_LPA, &reg))
1220                 val |= (reg & 0xffff);
1221         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1222
1223         val = 0;
1224         if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
1225                 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1226                         val = reg << 16;
1227                 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1228                         val |= (reg & 0xffff);
1229         }
1230         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1231
1232         if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1233                 val = reg << 16;
1234         else
1235                 val = 0;
1236         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1237
1238         tg3_generate_fw_event(tp);
1239 }
1240
1241 static void tg3_link_report(struct tg3 *tp)
1242 {
1243         if (!netif_carrier_ok(tp->dev)) {
1244                 if (netif_msg_link(tp))
1245                         printk(KERN_INFO PFX "%s: Link is down.\n",
1246                                tp->dev->name);
1247                 tg3_ump_link_report(tp);
1248         } else if (netif_msg_link(tp)) {
1249                 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1250                        tp->dev->name,
1251                        (tp->link_config.active_speed == SPEED_1000 ?
1252                         1000 :
1253                         (tp->link_config.active_speed == SPEED_100 ?
1254                          100 : 10)),
1255                        (tp->link_config.active_duplex == DUPLEX_FULL ?
1256                         "full" : "half"));
1257
1258                 printk(KERN_INFO PFX
1259                        "%s: Flow control is %s for TX and %s for RX.\n",
1260                        tp->dev->name,
1261                        (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1262                        "on" : "off",
1263                        (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1264                        "on" : "off");
1265                 tg3_ump_link_report(tp);
1266         }
1267 }
1268
1269 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1270 {
1271         u16 miireg;
1272
1273         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1274                 miireg = ADVERTISE_PAUSE_CAP;
1275         else if (flow_ctrl & FLOW_CTRL_TX)
1276                 miireg = ADVERTISE_PAUSE_ASYM;
1277         else if (flow_ctrl & FLOW_CTRL_RX)
1278                 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1279         else
1280                 miireg = 0;
1281
1282         return miireg;
1283 }
1284
1285 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1286 {
1287         u16 miireg;
1288
1289         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1290                 miireg = ADVERTISE_1000XPAUSE;
1291         else if (flow_ctrl & FLOW_CTRL_TX)
1292                 miireg = ADVERTISE_1000XPSE_ASYM;
1293         else if (flow_ctrl & FLOW_CTRL_RX)
1294                 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1295         else
1296                 miireg = 0;
1297
1298         return miireg;
1299 }
1300
1301 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1302 {
1303         u8 cap = 0;
1304
1305         if (lcladv & ADVERTISE_1000XPAUSE) {
1306                 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1307                         if (rmtadv & LPA_1000XPAUSE)
1308                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1309                         else if (rmtadv & LPA_1000XPAUSE_ASYM)
1310                                 cap = FLOW_CTRL_RX;
1311                 } else {
1312                         if (rmtadv & LPA_1000XPAUSE)
1313                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1314                 }
1315         } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1316                 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1317                         cap = FLOW_CTRL_TX;
1318         }
1319
1320         return cap;
1321 }
1322
1323 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1324 {
1325         u8 autoneg;
1326         u8 flowctrl = 0;
1327         u32 old_rx_mode = tp->rx_mode;
1328         u32 old_tx_mode = tp->tx_mode;
1329
1330         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
1331                 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
1332         else
1333                 autoneg = tp->link_config.autoneg;
1334
1335         if (autoneg == AUTONEG_ENABLE &&
1336             (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1337                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1338                         flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1339                 else
1340                         flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1341         } else
1342                 flowctrl = tp->link_config.flowctrl;
1343
1344         tp->link_config.active_flowctrl = flowctrl;
1345
1346         if (flowctrl & FLOW_CTRL_RX)
1347                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1348         else
1349                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1350
1351         if (old_rx_mode != tp->rx_mode)
1352                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1353
1354         if (flowctrl & FLOW_CTRL_TX)
1355                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1356         else
1357                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1358
1359         if (old_tx_mode != tp->tx_mode)
1360                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1361 }
1362
1363 static void tg3_adjust_link(struct net_device *dev)
1364 {
1365         u8 oldflowctrl, linkmesg = 0;
1366         u32 mac_mode, lcl_adv, rmt_adv;
1367         struct tg3 *tp = netdev_priv(dev);
1368         struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1369
1370         spin_lock_bh(&tp->lock);
1371
1372         mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1373                                     MAC_MODE_HALF_DUPLEX);
1374
1375         oldflowctrl = tp->link_config.active_flowctrl;
1376
1377         if (phydev->link) {
1378                 lcl_adv = 0;
1379                 rmt_adv = 0;
1380
1381                 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1382                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1383                 else if (phydev->speed == SPEED_1000 ||
1384                          GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
1385                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
1386                 else
1387                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1388
1389                 if (phydev->duplex == DUPLEX_HALF)
1390                         mac_mode |= MAC_MODE_HALF_DUPLEX;
1391                 else {
1392                         lcl_adv = tg3_advert_flowctrl_1000T(
1393                                   tp->link_config.flowctrl);
1394
1395                         if (phydev->pause)
1396                                 rmt_adv = LPA_PAUSE_CAP;
1397                         if (phydev->asym_pause)
1398                                 rmt_adv |= LPA_PAUSE_ASYM;
1399                 }
1400
1401                 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1402         } else
1403                 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1404
1405         if (mac_mode != tp->mac_mode) {
1406                 tp->mac_mode = mac_mode;
1407                 tw32_f(MAC_MODE, tp->mac_mode);
1408                 udelay(40);
1409         }
1410
1411         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1412                 if (phydev->speed == SPEED_10)
1413                         tw32(MAC_MI_STAT,
1414                              MAC_MI_STAT_10MBPS_MODE |
1415                              MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1416                 else
1417                         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1418         }
1419
1420         if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1421                 tw32(MAC_TX_LENGTHS,
1422                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1423                       (6 << TX_LENGTHS_IPG_SHIFT) |
1424                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1425         else
1426                 tw32(MAC_TX_LENGTHS,
1427                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1428                       (6 << TX_LENGTHS_IPG_SHIFT) |
1429                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1430
1431         if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1432             (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1433             phydev->speed != tp->link_config.active_speed ||
1434             phydev->duplex != tp->link_config.active_duplex ||
1435             oldflowctrl != tp->link_config.active_flowctrl)
1436             linkmesg = 1;
1437
1438         tp->link_config.active_speed = phydev->speed;
1439         tp->link_config.active_duplex = phydev->duplex;
1440
1441         spin_unlock_bh(&tp->lock);
1442
1443         if (linkmesg)
1444                 tg3_link_report(tp);
1445 }
1446
1447 static int tg3_phy_init(struct tg3 *tp)
1448 {
1449         struct phy_device *phydev;
1450
1451         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
1452                 return 0;
1453
1454         /* Bring the PHY back to a known state. */
1455         tg3_bmcr_reset(tp);
1456
1457         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1458
1459         /* Attach the MAC to the PHY. */
1460         phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1461                              phydev->dev_flags, phydev->interface);
1462         if (IS_ERR(phydev)) {
1463                 printk(KERN_ERR "%s: Could not attach to PHY\n", tp->dev->name);
1464                 return PTR_ERR(phydev);
1465         }
1466
1467         /* Mask with MAC supported features. */
1468         switch (phydev->interface) {
1469         case PHY_INTERFACE_MODE_GMII:
1470         case PHY_INTERFACE_MODE_RGMII:
1471                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1472                         phydev->supported &= (PHY_GBIT_FEATURES |
1473                                               SUPPORTED_Pause |
1474                                               SUPPORTED_Asym_Pause);
1475                         break;
1476                 }
1477                 /* fallthru */
1478         case PHY_INTERFACE_MODE_MII:
1479                 phydev->supported &= (PHY_BASIC_FEATURES |
1480                                       SUPPORTED_Pause |
1481                                       SUPPORTED_Asym_Pause);
1482                 break;
1483         default:
1484                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1485                 return -EINVAL;
1486         }
1487
1488         tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED;
1489
1490         phydev->advertising = phydev->supported;
1491
1492         return 0;
1493 }
1494
1495 static void tg3_phy_start(struct tg3 *tp)
1496 {
1497         struct phy_device *phydev;
1498
1499         if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1500                 return;
1501
1502         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1503
1504         if (tp->link_config.phy_is_low_power) {
1505                 tp->link_config.phy_is_low_power = 0;
1506                 phydev->speed = tp->link_config.orig_speed;
1507                 phydev->duplex = tp->link_config.orig_duplex;
1508                 phydev->autoneg = tp->link_config.orig_autoneg;
1509                 phydev->advertising = tp->link_config.orig_advertising;
1510         }
1511
1512         phy_start(phydev);
1513
1514         phy_start_aneg(phydev);
1515 }
1516
1517 static void tg3_phy_stop(struct tg3 *tp)
1518 {
1519         if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1520                 return;
1521
1522         phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1523 }
1524
1525 static void tg3_phy_fini(struct tg3 *tp)
1526 {
1527         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
1528                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1529                 tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED;
1530         }
1531 }
1532
1533 static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1534 {
1535         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1536         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1537 }
1538
1539 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1540 {
1541         u32 phytest;
1542
1543         if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1544                 u32 phy;
1545
1546                 tg3_writephy(tp, MII_TG3_FET_TEST,
1547                              phytest | MII_TG3_FET_SHADOW_EN);
1548                 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1549                         if (enable)
1550                                 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1551                         else
1552                                 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1553                         tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1554                 }
1555                 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1556         }
1557 }
1558
1559 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1560 {
1561         u32 reg;
1562
1563         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1564                 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
1565              (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
1566                 return;
1567
1568         if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1569                 tg3_phy_fet_toggle_apd(tp, enable);
1570                 return;
1571         }
1572
1573         reg = MII_TG3_MISC_SHDW_WREN |
1574               MII_TG3_MISC_SHDW_SCR5_SEL |
1575               MII_TG3_MISC_SHDW_SCR5_LPED |
1576               MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1577               MII_TG3_MISC_SHDW_SCR5_SDTL |
1578               MII_TG3_MISC_SHDW_SCR5_C125OE;
1579         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1580                 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1581
1582         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1583
1584
1585         reg = MII_TG3_MISC_SHDW_WREN |
1586               MII_TG3_MISC_SHDW_APD_SEL |
1587               MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1588         if (enable)
1589                 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1590
1591         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1592 }
1593
1594 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1595 {
1596         u32 phy;
1597
1598         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1599             (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1600                 return;
1601
1602         if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1603                 u32 ephy;
1604
1605                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1606                         u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1607
1608                         tg3_writephy(tp, MII_TG3_FET_TEST,
1609                                      ephy | MII_TG3_FET_SHADOW_EN);
1610                         if (!tg3_readphy(tp, reg, &phy)) {
1611                                 if (enable)
1612                                         phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1613                                 else
1614                                         phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1615                                 tg3_writephy(tp, reg, phy);
1616                         }
1617                         tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
1618                 }
1619         } else {
1620                 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1621                       MII_TG3_AUXCTL_SHDWSEL_MISC;
1622                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1623                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1624                         if (enable)
1625                                 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1626                         else
1627                                 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1628                         phy |= MII_TG3_AUXCTL_MISC_WREN;
1629                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1630                 }
1631         }
1632 }
1633
1634 static void tg3_phy_set_wirespeed(struct tg3 *tp)
1635 {
1636         u32 val;
1637
1638         if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
1639                 return;
1640
1641         if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1642             !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1643                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1644                              (val | (1 << 15) | (1 << 4)));
1645 }
1646
1647 static void tg3_phy_apply_otp(struct tg3 *tp)
1648 {
1649         u32 otp, phy;
1650
1651         if (!tp->phy_otp)
1652                 return;
1653
1654         otp = tp->phy_otp;
1655
1656         /* Enable SM_DSP clock and tx 6dB coding. */
1657         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1658               MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1659               MII_TG3_AUXCTL_ACTL_TX_6DB;
1660         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1661
1662         phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1663         phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1664         tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1665
1666         phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1667               ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1668         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1669
1670         phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1671         phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1672         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1673
1674         phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1675         tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1676
1677         phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1678         tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1679
1680         phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1681               ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1682         tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1683
1684         /* Turn off SM_DSP clock. */
1685         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1686               MII_TG3_AUXCTL_ACTL_TX_6DB;
1687         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1688 }
1689
1690 static int tg3_wait_macro_done(struct tg3 *tp)
1691 {
1692         int limit = 100;
1693
1694         while (limit--) {
1695                 u32 tmp32;
1696
1697                 if (!tg3_readphy(tp, 0x16, &tmp32)) {
1698                         if ((tmp32 & 0x1000) == 0)
1699                                 break;
1700                 }
1701         }
1702         if (limit < 0)
1703                 return -EBUSY;
1704
1705         return 0;
1706 }
1707
1708 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1709 {
1710         static const u32 test_pat[4][6] = {
1711         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1712         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1713         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1714         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1715         };
1716         int chan;
1717
1718         for (chan = 0; chan < 4; chan++) {
1719                 int i;
1720
1721                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1722                              (chan * 0x2000) | 0x0200);
1723                 tg3_writephy(tp, 0x16, 0x0002);
1724
1725                 for (i = 0; i < 6; i++)
1726                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1727                                      test_pat[chan][i]);
1728
1729                 tg3_writephy(tp, 0x16, 0x0202);
1730                 if (tg3_wait_macro_done(tp)) {
1731                         *resetp = 1;
1732                         return -EBUSY;
1733                 }
1734
1735                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1736                              (chan * 0x2000) | 0x0200);
1737                 tg3_writephy(tp, 0x16, 0x0082);
1738                 if (tg3_wait_macro_done(tp)) {
1739                         *resetp = 1;
1740                         return -EBUSY;
1741                 }
1742
1743                 tg3_writephy(tp, 0x16, 0x0802);
1744                 if (tg3_wait_macro_done(tp)) {
1745                         *resetp = 1;
1746                         return -EBUSY;
1747                 }
1748
1749                 for (i = 0; i < 6; i += 2) {
1750                         u32 low, high;
1751
1752                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1753                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1754                             tg3_wait_macro_done(tp)) {
1755                                 *resetp = 1;
1756                                 return -EBUSY;
1757                         }
1758                         low &= 0x7fff;
1759                         high &= 0x000f;
1760                         if (low != test_pat[chan][i] ||
1761                             high != test_pat[chan][i+1]) {
1762                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1763                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1764                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1765
1766                                 return -EBUSY;
1767                         }
1768                 }
1769         }
1770
1771         return 0;
1772 }
1773
1774 static int tg3_phy_reset_chanpat(struct tg3 *tp)
1775 {
1776         int chan;
1777
1778         for (chan = 0; chan < 4; chan++) {
1779                 int i;
1780
1781                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1782                              (chan * 0x2000) | 0x0200);
1783                 tg3_writephy(tp, 0x16, 0x0002);
1784                 for (i = 0; i < 6; i++)
1785                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1786                 tg3_writephy(tp, 0x16, 0x0202);
1787                 if (tg3_wait_macro_done(tp))
1788                         return -EBUSY;
1789         }
1790
1791         return 0;
1792 }
1793
1794 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1795 {
1796         u32 reg32, phy9_orig;
1797         int retries, do_phy_reset, err;
1798
1799         retries = 10;
1800         do_phy_reset = 1;
1801         do {
1802                 if (do_phy_reset) {
1803                         err = tg3_bmcr_reset(tp);
1804                         if (err)
1805                                 return err;
1806                         do_phy_reset = 0;
1807                 }
1808
1809                 /* Disable transmitter and interrupt.  */
1810                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1811                         continue;
1812
1813                 reg32 |= 0x3000;
1814                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1815
1816                 /* Set full-duplex, 1000 mbps.  */
1817                 tg3_writephy(tp, MII_BMCR,
1818                              BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1819
1820                 /* Set to master mode.  */
1821                 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1822                         continue;
1823
1824                 tg3_writephy(tp, MII_TG3_CTRL,
1825                              (MII_TG3_CTRL_AS_MASTER |
1826                               MII_TG3_CTRL_ENABLE_AS_MASTER));
1827
1828                 /* Enable SM_DSP_CLOCK and 6dB.  */
1829                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1830
1831                 /* Block the PHY control access.  */
1832                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1833                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
1834
1835                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1836                 if (!err)
1837                         break;
1838         } while (--retries);
1839
1840         err = tg3_phy_reset_chanpat(tp);
1841         if (err)
1842                 return err;
1843
1844         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1845         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
1846
1847         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1848         tg3_writephy(tp, 0x16, 0x0000);
1849
1850         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1851             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1852                 /* Set Extended packet length bit for jumbo frames */
1853                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1854         }
1855         else {
1856                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1857         }
1858
1859         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1860
1861         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1862                 reg32 &= ~0x3000;
1863                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1864         } else if (!err)
1865                 err = -EBUSY;
1866
1867         return err;
1868 }
1869
1870 /* This will reset the tigon3 PHY if there is no valid
1871  * link unless the FORCE argument is non-zero.
1872  */
1873 static int tg3_phy_reset(struct tg3 *tp)
1874 {
1875         u32 cpmuctrl;
1876         u32 phy_status;
1877         int err;
1878
1879         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1880                 u32 val;
1881
1882                 val = tr32(GRC_MISC_CFG);
1883                 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1884                 udelay(40);
1885         }
1886         err  = tg3_readphy(tp, MII_BMSR, &phy_status);
1887         err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1888         if (err != 0)
1889                 return -EBUSY;
1890
1891         if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1892                 netif_carrier_off(tp->dev);
1893                 tg3_link_report(tp);
1894         }
1895
1896         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1897             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1898             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1899                 err = tg3_phy_reset_5703_4_5(tp);
1900                 if (err)
1901                         return err;
1902                 goto out;
1903         }
1904
1905         cpmuctrl = 0;
1906         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1907             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1908                 cpmuctrl = tr32(TG3_CPMU_CTRL);
1909                 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1910                         tw32(TG3_CPMU_CTRL,
1911                              cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1912         }
1913
1914         err = tg3_bmcr_reset(tp);
1915         if (err)
1916                 return err;
1917
1918         if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1919                 u32 phy;
1920
1921                 phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1922                 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
1923
1924                 tw32(TG3_CPMU_CTRL, cpmuctrl);
1925         }
1926
1927         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
1928             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
1929                 u32 val;
1930
1931                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1932                 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1933                     CPMU_LSPD_1000MB_MACCLK_12_5) {
1934                         val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1935                         udelay(40);
1936                         tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1937                 }
1938         }
1939
1940         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
1941             (tp->tg3_flags2 & TG3_FLG2_MII_SERDES))
1942                 return 0;
1943
1944         tg3_phy_apply_otp(tp);
1945
1946         if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
1947                 tg3_phy_toggle_apd(tp, true);
1948         else
1949                 tg3_phy_toggle_apd(tp, false);
1950
1951 out:
1952         if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1953                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1954                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1955                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1956                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1957                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1958                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1959         }
1960         if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1961                 tg3_writephy(tp, 0x1c, 0x8d68);
1962                 tg3_writephy(tp, 0x1c, 0x8d68);
1963         }
1964         if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1965                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1966                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1967                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1968                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1969                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1970                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1971                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1972                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1973         }
1974         else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1975                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1976                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1977                 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1978                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1979                         tg3_writephy(tp, MII_TG3_TEST1,
1980                                      MII_TG3_TEST1_TRIM_EN | 0x4);
1981                 } else
1982                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
1983                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1984         }
1985         /* Set Extended packet length bit (bit 14) on all chips that */
1986         /* support jumbo frames */
1987         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1988                 /* Cannot do read-modify-write on 5401 */
1989                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1990         } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1991                 u32 phy_reg;
1992
1993                 /* Set bit 14 with read-modify-write to preserve other bits */
1994                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1995                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1996                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1997         }
1998
1999         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2000          * jumbo frames transmission.
2001          */
2002         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2003                 u32 phy_reg;
2004
2005                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
2006                     tg3_writephy(tp, MII_TG3_EXT_CTRL,
2007                                  phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
2008         }
2009
2010         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2011                 /* adjust output voltage */
2012                 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
2013         }
2014
2015         tg3_phy_toggle_automdix(tp, 1);
2016         tg3_phy_set_wirespeed(tp);
2017         return 0;
2018 }
2019
2020 static void tg3_frob_aux_power(struct tg3 *tp)
2021 {
2022         struct tg3 *tp_peer = tp;
2023
2024         if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
2025                 return;
2026
2027         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2028             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
2029             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
2030                 struct net_device *dev_peer;
2031
2032                 dev_peer = pci_get_drvdata(tp->pdev_peer);
2033                 /* remove_one() may have been run on the peer. */
2034                 if (!dev_peer)
2035                         tp_peer = tp;
2036                 else
2037                         tp_peer = netdev_priv(dev_peer);
2038         }
2039
2040         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2041             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
2042             (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2043             (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
2044                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2045                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2046                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2047                                     (GRC_LCLCTRL_GPIO_OE0 |
2048                                      GRC_LCLCTRL_GPIO_OE1 |
2049                                      GRC_LCLCTRL_GPIO_OE2 |
2050                                      GRC_LCLCTRL_GPIO_OUTPUT0 |
2051                                      GRC_LCLCTRL_GPIO_OUTPUT1),
2052                                     100);
2053                 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2054                            tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2055                         /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2056                         u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2057                                              GRC_LCLCTRL_GPIO_OE1 |
2058                                              GRC_LCLCTRL_GPIO_OE2 |
2059                                              GRC_LCLCTRL_GPIO_OUTPUT0 |
2060                                              GRC_LCLCTRL_GPIO_OUTPUT1 |
2061                                              tp->grc_local_ctrl;
2062                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2063
2064                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2065                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2066
2067                         grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2068                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2069                 } else {
2070                         u32 no_gpio2;
2071                         u32 grc_local_ctrl = 0;
2072
2073                         if (tp_peer != tp &&
2074                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2075                                 return;
2076
2077                         /* Workaround to prevent overdrawing Amps. */
2078                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2079                             ASIC_REV_5714) {
2080                                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2081                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2082                                             grc_local_ctrl, 100);
2083                         }
2084
2085                         /* On 5753 and variants, GPIO2 cannot be used. */
2086                         no_gpio2 = tp->nic_sram_data_cfg &
2087                                     NIC_SRAM_DATA_CFG_NO_GPIO2;
2088
2089                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2090                                          GRC_LCLCTRL_GPIO_OE1 |
2091                                          GRC_LCLCTRL_GPIO_OE2 |
2092                                          GRC_LCLCTRL_GPIO_OUTPUT1 |
2093                                          GRC_LCLCTRL_GPIO_OUTPUT2;
2094                         if (no_gpio2) {
2095                                 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2096                                                     GRC_LCLCTRL_GPIO_OUTPUT2);
2097                         }
2098                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2099                                                     grc_local_ctrl, 100);
2100
2101                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2102
2103                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2104                                                     grc_local_ctrl, 100);
2105
2106                         if (!no_gpio2) {
2107                                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2108                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2109                                             grc_local_ctrl, 100);
2110                         }
2111                 }
2112         } else {
2113                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2114                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2115                         if (tp_peer != tp &&
2116                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2117                                 return;
2118
2119                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2120                                     (GRC_LCLCTRL_GPIO_OE1 |
2121                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2122
2123                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2124                                     GRC_LCLCTRL_GPIO_OE1, 100);
2125
2126                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2127                                     (GRC_LCLCTRL_GPIO_OE1 |
2128                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2129                 }
2130         }
2131 }
2132
2133 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2134 {
2135         if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2136                 return 1;
2137         else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) {
2138                 if (speed != SPEED_10)
2139                         return 1;
2140         } else if (speed == SPEED_10)
2141                 return 1;
2142
2143         return 0;
2144 }
2145
2146 static int tg3_setup_phy(struct tg3 *, int);
2147
2148 #define RESET_KIND_SHUTDOWN     0
2149 #define RESET_KIND_INIT         1
2150 #define RESET_KIND_SUSPEND      2
2151
2152 static void tg3_write_sig_post_reset(struct tg3 *, int);
2153 static int tg3_halt_cpu(struct tg3 *, u32);
2154
2155 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2156 {
2157         u32 val;
2158
2159         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2160                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2161                         u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2162                         u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2163
2164                         sg_dig_ctrl |=
2165                                 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2166                         tw32(SG_DIG_CTRL, sg_dig_ctrl);
2167                         tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2168                 }
2169                 return;
2170         }
2171
2172         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2173                 tg3_bmcr_reset(tp);
2174                 val = tr32(GRC_MISC_CFG);
2175                 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2176                 udelay(40);
2177                 return;
2178         } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
2179                 u32 phytest;
2180                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2181                         u32 phy;
2182
2183                         tg3_writephy(tp, MII_ADVERTISE, 0);
2184                         tg3_writephy(tp, MII_BMCR,
2185                                      BMCR_ANENABLE | BMCR_ANRESTART);
2186
2187                         tg3_writephy(tp, MII_TG3_FET_TEST,
2188                                      phytest | MII_TG3_FET_SHADOW_EN);
2189                         if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2190                                 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2191                                 tg3_writephy(tp,
2192                                              MII_TG3_FET_SHDW_AUXMODE4,
2193                                              phy);
2194                         }
2195                         tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2196                 }
2197                 return;
2198         } else if (do_low_power) {
2199                 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2200                              MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2201
2202                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2203                              MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2204                              MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2205                              MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2206                              MII_TG3_AUXCTL_PCTL_VREG_11V);
2207         }
2208
2209         /* The PHY should not be powered down on some chips because
2210          * of bugs.
2211          */
2212         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2213             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2214             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2215              (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
2216                 return;
2217
2218         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2219             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2220                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2221                 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2222                 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2223                 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2224         }
2225
2226         tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2227 }
2228
2229 /* tp->lock is held. */
2230 static int tg3_nvram_lock(struct tg3 *tp)
2231 {
2232         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2233                 int i;
2234
2235                 if (tp->nvram_lock_cnt == 0) {
2236                         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2237                         for (i = 0; i < 8000; i++) {
2238                                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2239                                         break;
2240                                 udelay(20);
2241                         }
2242                         if (i == 8000) {
2243                                 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2244                                 return -ENODEV;
2245                         }
2246                 }
2247                 tp->nvram_lock_cnt++;
2248         }
2249         return 0;
2250 }
2251
2252 /* tp->lock is held. */
2253 static void tg3_nvram_unlock(struct tg3 *tp)
2254 {
2255         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2256                 if (tp->nvram_lock_cnt > 0)
2257                         tp->nvram_lock_cnt--;
2258                 if (tp->nvram_lock_cnt == 0)
2259                         tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2260         }
2261 }
2262
2263 /* tp->lock is held. */
2264 static void tg3_enable_nvram_access(struct tg3 *tp)
2265 {
2266         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2267             !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2268                 u32 nvaccess = tr32(NVRAM_ACCESS);
2269
2270                 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2271         }
2272 }
2273
2274 /* tp->lock is held. */
2275 static void tg3_disable_nvram_access(struct tg3 *tp)
2276 {
2277         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2278             !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2279                 u32 nvaccess = tr32(NVRAM_ACCESS);
2280
2281                 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2282         }
2283 }
2284
2285 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2286                                         u32 offset, u32 *val)
2287 {
2288         u32 tmp;
2289         int i;
2290
2291         if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2292                 return -EINVAL;
2293
2294         tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2295                                         EEPROM_ADDR_DEVID_MASK |
2296                                         EEPROM_ADDR_READ);
2297         tw32(GRC_EEPROM_ADDR,
2298              tmp |
2299              (0 << EEPROM_ADDR_DEVID_SHIFT) |
2300              ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2301               EEPROM_ADDR_ADDR_MASK) |
2302              EEPROM_ADDR_READ | EEPROM_ADDR_START);
2303
2304         for (i = 0; i < 1000; i++) {
2305                 tmp = tr32(GRC_EEPROM_ADDR);
2306
2307                 if (tmp & EEPROM_ADDR_COMPLETE)
2308                         break;
2309                 msleep(1);
2310         }
2311         if (!(tmp & EEPROM_ADDR_COMPLETE))
2312                 return -EBUSY;
2313
2314         tmp = tr32(GRC_EEPROM_DATA);
2315
2316         /*
2317          * The data will always be opposite the native endian
2318          * format.  Perform a blind byteswap to compensate.
2319          */
2320         *val = swab32(tmp);
2321
2322         return 0;
2323 }
2324
2325 #define NVRAM_CMD_TIMEOUT 10000
2326
2327 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2328 {
2329         int i;
2330
2331         tw32(NVRAM_CMD, nvram_cmd);
2332         for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2333                 udelay(10);
2334                 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2335                         udelay(10);
2336                         break;
2337                 }
2338         }
2339
2340         if (i == NVRAM_CMD_TIMEOUT)
2341                 return -EBUSY;
2342
2343         return 0;
2344 }
2345
2346 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2347 {
2348         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2349             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2350             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2351            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2352             (tp->nvram_jedecnum == JEDEC_ATMEL))
2353
2354                 addr = ((addr / tp->nvram_pagesize) <<
2355                         ATMEL_AT45DB0X1B_PAGE_POS) +
2356                        (addr % tp->nvram_pagesize);
2357
2358         return addr;
2359 }
2360
2361 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2362 {
2363         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2364             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2365             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2366            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2367             (tp->nvram_jedecnum == JEDEC_ATMEL))
2368
2369                 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2370                         tp->nvram_pagesize) +
2371                        (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2372
2373         return addr;
2374 }
2375
2376 /* NOTE: Data read in from NVRAM is byteswapped according to
2377  * the byteswapping settings for all other register accesses.
2378  * tg3 devices are BE devices, so on a BE machine, the data
2379  * returned will be exactly as it is seen in NVRAM.  On a LE
2380  * machine, the 32-bit value will be byteswapped.
2381  */
2382 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2383 {
2384         int ret;
2385
2386         if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2387                 return tg3_nvram_read_using_eeprom(tp, offset, val);
2388
2389         offset = tg3_nvram_phys_addr(tp, offset);
2390
2391         if (offset > NVRAM_ADDR_MSK)
2392                 return -EINVAL;
2393
2394         ret = tg3_nvram_lock(tp);
2395         if (ret)
2396                 return ret;
2397
2398         tg3_enable_nvram_access(tp);
2399
2400         tw32(NVRAM_ADDR, offset);
2401         ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2402                 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2403
2404         if (ret == 0)
2405                 *val = tr32(NVRAM_RDDATA);
2406
2407         tg3_disable_nvram_access(tp);
2408
2409         tg3_nvram_unlock(tp);
2410
2411         return ret;
2412 }
2413
2414 /* Ensures NVRAM data is in bytestream format. */
2415 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
2416 {
2417         u32 v;
2418         int res = tg3_nvram_read(tp, offset, &v);
2419         if (!res)
2420                 *val = cpu_to_be32(v);
2421         return res;
2422 }
2423
2424 /* tp->lock is held. */
2425 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2426 {
2427         u32 addr_high, addr_low;
2428         int i;
2429
2430         addr_high = ((tp->dev->dev_addr[0] << 8) |
2431                      tp->dev->dev_addr[1]);
2432         addr_low = ((tp->dev->dev_addr[2] << 24) |
2433                     (tp->dev->dev_addr[3] << 16) |
2434                     (tp->dev->dev_addr[4] <<  8) |
2435                     (tp->dev->dev_addr[5] <<  0));
2436         for (i = 0; i < 4; i++) {
2437                 if (i == 1 && skip_mac_1)
2438                         continue;
2439                 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2440                 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2441         }
2442
2443         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2444             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2445                 for (i = 0; i < 12; i++) {
2446                         tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2447                         tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2448                 }
2449         }
2450
2451         addr_high = (tp->dev->dev_addr[0] +
2452                      tp->dev->dev_addr[1] +
2453                      tp->dev->dev_addr[2] +
2454                      tp->dev->dev_addr[3] +
2455                      tp->dev->dev_addr[4] +
2456                      tp->dev->dev_addr[5]) &
2457                 TX_BACKOFF_SEED_MASK;
2458         tw32(MAC_TX_BACKOFF_SEED, addr_high);
2459 }
2460
2461 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
2462 {
2463         u32 misc_host_ctrl;
2464         bool device_should_wake, do_low_power;
2465
2466         /* Make sure register accesses (indirect or otherwise)
2467          * will function correctly.
2468          */
2469         pci_write_config_dword(tp->pdev,
2470                                TG3PCI_MISC_HOST_CTRL,
2471                                tp->misc_host_ctrl);
2472
2473         switch (state) {
2474         case PCI_D0:
2475                 pci_enable_wake(tp->pdev, state, false);
2476                 pci_set_power_state(tp->pdev, PCI_D0);
2477
2478                 /* Switch out of Vaux if it is a NIC */
2479                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
2480                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
2481
2482                 return 0;
2483
2484         case PCI_D1:
2485         case PCI_D2:
2486         case PCI_D3hot:
2487                 break;
2488
2489         default:
2490                 printk(KERN_ERR PFX "%s: Invalid power state (D%d) requested\n",
2491                         tp->dev->name, state);
2492                 return -EINVAL;
2493         }
2494
2495         /* Restore the CLKREQ setting. */
2496         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2497                 u16 lnkctl;
2498
2499                 pci_read_config_word(tp->pdev,
2500                                      tp->pcie_cap + PCI_EXP_LNKCTL,
2501                                      &lnkctl);
2502                 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2503                 pci_write_config_word(tp->pdev,
2504                                       tp->pcie_cap + PCI_EXP_LNKCTL,
2505                                       lnkctl);
2506         }
2507
2508         misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2509         tw32(TG3PCI_MISC_HOST_CTRL,
2510              misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2511
2512         device_should_wake = pci_pme_capable(tp->pdev, state) &&
2513                              device_may_wakeup(&tp->pdev->dev) &&
2514                              (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2515
2516         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
2517                 do_low_power = false;
2518                 if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) &&
2519                     !tp->link_config.phy_is_low_power) {
2520                         struct phy_device *phydev;
2521                         u32 phyid, advertising;
2522
2523                         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
2524
2525                         tp->link_config.phy_is_low_power = 1;
2526
2527                         tp->link_config.orig_speed = phydev->speed;
2528                         tp->link_config.orig_duplex = phydev->duplex;
2529                         tp->link_config.orig_autoneg = phydev->autoneg;
2530                         tp->link_config.orig_advertising = phydev->advertising;
2531
2532                         advertising = ADVERTISED_TP |
2533                                       ADVERTISED_Pause |
2534                                       ADVERTISED_Autoneg |
2535                                       ADVERTISED_10baseT_Half;
2536
2537                         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2538                             device_should_wake) {
2539                                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2540                                         advertising |=
2541                                                 ADVERTISED_100baseT_Half |
2542                                                 ADVERTISED_100baseT_Full |
2543                                                 ADVERTISED_10baseT_Full;
2544                                 else
2545                                         advertising |= ADVERTISED_10baseT_Full;
2546                         }
2547
2548                         phydev->advertising = advertising;
2549
2550                         phy_start_aneg(phydev);
2551
2552                         phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2553                         if (phyid != TG3_PHY_ID_BCMAC131) {
2554                                 phyid &= TG3_PHY_OUI_MASK;
2555                                 if (phyid == TG3_PHY_OUI_1 ||
2556                                     phyid == TG3_PHY_OUI_2 ||
2557                                     phyid == TG3_PHY_OUI_3)
2558                                         do_low_power = true;
2559                         }
2560                 }
2561         } else {
2562                 do_low_power = true;
2563
2564                 if (tp->link_config.phy_is_low_power == 0) {
2565                         tp->link_config.phy_is_low_power = 1;
2566                         tp->link_config.orig_speed = tp->link_config.speed;
2567                         tp->link_config.orig_duplex = tp->link_config.duplex;
2568                         tp->link_config.orig_autoneg = tp->link_config.autoneg;
2569                 }
2570
2571                 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
2572                         tp->link_config.speed = SPEED_10;
2573                         tp->link_config.duplex = DUPLEX_HALF;
2574                         tp->link_config.autoneg = AUTONEG_ENABLE;
2575                         tg3_setup_phy(tp, 0);
2576                 }
2577         }
2578
2579         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2580                 u32 val;
2581
2582                 val = tr32(GRC_VCPU_EXT_CTRL);
2583                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2584         } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2585                 int i;
2586                 u32 val;
2587
2588                 for (i = 0; i < 200; i++) {
2589                         tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2590                         if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2591                                 break;
2592                         msleep(1);
2593                 }
2594         }
2595         if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2596                 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2597                                                      WOL_DRV_STATE_SHUTDOWN |
2598                                                      WOL_DRV_WOL |
2599                                                      WOL_SET_MAGIC_PKT);
2600
2601         if (device_should_wake) {
2602                 u32 mac_mode;
2603
2604                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
2605                         if (do_low_power) {
2606                                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2607                                 udelay(40);
2608                         }
2609
2610                         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
2611                                 mac_mode = MAC_MODE_PORT_MODE_GMII;
2612                         else
2613                                 mac_mode = MAC_MODE_PORT_MODE_MII;
2614
2615                         mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2616                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2617                             ASIC_REV_5700) {
2618                                 u32 speed = (tp->tg3_flags &
2619                                              TG3_FLAG_WOL_SPEED_100MB) ?
2620                                              SPEED_100 : SPEED_10;
2621                                 if (tg3_5700_link_polarity(tp, speed))
2622                                         mac_mode |= MAC_MODE_LINK_POLARITY;
2623                                 else
2624                                         mac_mode &= ~MAC_MODE_LINK_POLARITY;
2625                         }
2626                 } else {
2627                         mac_mode = MAC_MODE_PORT_MODE_TBI;
2628                 }
2629
2630                 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
2631                         tw32(MAC_LED_CTRL, tp->led_ctrl);
2632
2633                 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2634                 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2635                     !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2636                     ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2637                      (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2638                         mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
2639
2640                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2641                         mac_mode |= tp->mac_mode &
2642                                     (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2643                         if (mac_mode & MAC_MODE_APE_TX_EN)
2644                                 mac_mode |= MAC_MODE_TDE_ENABLE;
2645                 }
2646
2647                 tw32_f(MAC_MODE, mac_mode);
2648                 udelay(100);
2649
2650                 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2651                 udelay(10);
2652         }
2653
2654         if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2655             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2656              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2657                 u32 base_val;
2658
2659                 base_val = tp->pci_clock_ctrl;
2660                 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2661                              CLOCK_CTRL_TXCLK_DISABLE);
2662
2663                 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2664                             CLOCK_CTRL_PWRDOWN_PLL133, 40);
2665         } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
2666                    (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
2667                    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
2668                 /* do nothing */
2669         } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2670                      (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2671                 u32 newbits1, newbits2;
2672
2673                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2674                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2675                         newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2676                                     CLOCK_CTRL_TXCLK_DISABLE |
2677                                     CLOCK_CTRL_ALTCLK);
2678                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2679                 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2680                         newbits1 = CLOCK_CTRL_625_CORE;
2681                         newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2682                 } else {
2683                         newbits1 = CLOCK_CTRL_ALTCLK;
2684                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2685                 }
2686
2687                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2688                             40);
2689
2690                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2691                             40);
2692
2693                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2694                         u32 newbits3;
2695
2696                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2697                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2698                                 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2699                                             CLOCK_CTRL_TXCLK_DISABLE |
2700                                             CLOCK_CTRL_44MHZ_CORE);
2701                         } else {
2702                                 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2703                         }
2704
2705                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
2706                                     tp->pci_clock_ctrl | newbits3, 40);
2707                 }
2708         }
2709
2710         if (!(device_should_wake) &&
2711             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
2712                 tg3_power_down_phy(tp, do_low_power);
2713
2714         tg3_frob_aux_power(tp);
2715
2716         /* Workaround for unstable PLL clock */
2717         if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2718             (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2719                 u32 val = tr32(0x7d00);
2720
2721                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2722                 tw32(0x7d00, val);
2723                 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2724                         int err;
2725
2726                         err = tg3_nvram_lock(tp);
2727                         tg3_halt_cpu(tp, RX_CPU_BASE);
2728                         if (!err)
2729                                 tg3_nvram_unlock(tp);
2730                 }
2731         }
2732
2733         tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2734
2735         if (device_should_wake)
2736                 pci_enable_wake(tp->pdev, state, true);
2737
2738         /* Finally, set the new power state. */
2739         pci_set_power_state(tp->pdev, state);
2740
2741         return 0;
2742 }
2743
2744 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2745 {
2746         switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2747         case MII_TG3_AUX_STAT_10HALF:
2748                 *speed = SPEED_10;
2749                 *duplex = DUPLEX_HALF;
2750                 break;
2751
2752         case MII_TG3_AUX_STAT_10FULL:
2753                 *speed = SPEED_10;
2754                 *duplex = DUPLEX_FULL;
2755                 break;
2756
2757         case MII_TG3_AUX_STAT_100HALF:
2758                 *speed = SPEED_100;
2759                 *duplex = DUPLEX_HALF;
2760                 break;
2761
2762         case MII_TG3_AUX_STAT_100FULL:
2763                 *speed = SPEED_100;
2764                 *duplex = DUPLEX_FULL;
2765                 break;
2766
2767         case MII_TG3_AUX_STAT_1000HALF:
2768                 *speed = SPEED_1000;
2769                 *duplex = DUPLEX_HALF;
2770                 break;
2771
2772         case MII_TG3_AUX_STAT_1000FULL:
2773                 *speed = SPEED_1000;
2774                 *duplex = DUPLEX_FULL;
2775                 break;
2776
2777         default:
2778                 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
2779                         *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2780                                  SPEED_10;
2781                         *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2782                                   DUPLEX_HALF;
2783                         break;
2784                 }
2785                 *speed = SPEED_INVALID;
2786                 *duplex = DUPLEX_INVALID;
2787                 break;
2788         }
2789 }
2790
2791 static void tg3_phy_copper_begin(struct tg3 *tp)
2792 {
2793         u32 new_adv;
2794         int i;
2795
2796         if (tp->link_config.phy_is_low_power) {
2797                 /* Entering low power mode.  Disable gigabit and
2798                  * 100baseT advertisements.
2799                  */
2800                 tg3_writephy(tp, MII_TG3_CTRL, 0);
2801
2802                 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2803                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2804                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2805                         new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2806
2807                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2808         } else if (tp->link_config.speed == SPEED_INVALID) {
2809                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2810                         tp->link_config.advertising &=
2811                                 ~(ADVERTISED_1000baseT_Half |
2812                                   ADVERTISED_1000baseT_Full);
2813
2814                 new_adv = ADVERTISE_CSMA;
2815                 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2816                         new_adv |= ADVERTISE_10HALF;
2817                 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2818                         new_adv |= ADVERTISE_10FULL;
2819                 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2820                         new_adv |= ADVERTISE_100HALF;
2821                 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2822                         new_adv |= ADVERTISE_100FULL;
2823
2824                 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2825
2826                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2827
2828                 if (tp->link_config.advertising &
2829                     (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2830                         new_adv = 0;
2831                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2832                                 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2833                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2834                                 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2835                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
2836                             (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2837                              tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2838                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2839                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2840                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2841                 } else {
2842                         tg3_writephy(tp, MII_TG3_CTRL, 0);
2843                 }
2844         } else {
2845                 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2846                 new_adv |= ADVERTISE_CSMA;
2847
2848                 /* Asking for a specific link mode. */
2849                 if (tp->link_config.speed == SPEED_1000) {
2850                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2851
2852                         if (tp->link_config.duplex == DUPLEX_FULL)
2853                                 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2854                         else
2855                                 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2856                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2857                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2858                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2859                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2860                 } else {
2861                         if (tp->link_config.speed == SPEED_100) {
2862                                 if (tp->link_config.duplex == DUPLEX_FULL)
2863                                         new_adv |= ADVERTISE_100FULL;
2864                                 else
2865                                         new_adv |= ADVERTISE_100HALF;
2866                         } else {
2867                                 if (tp->link_config.duplex == DUPLEX_FULL)
2868                                         new_adv |= ADVERTISE_10FULL;
2869                                 else
2870                                         new_adv |= ADVERTISE_10HALF;
2871                         }
2872                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2873
2874                         new_adv = 0;
2875                 }
2876
2877                 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2878         }
2879
2880         if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2881             tp->link_config.speed != SPEED_INVALID) {
2882                 u32 bmcr, orig_bmcr;
2883
2884                 tp->link_config.active_speed = tp->link_config.speed;
2885                 tp->link_config.active_duplex = tp->link_config.duplex;
2886
2887                 bmcr = 0;
2888                 switch (tp->link_config.speed) {
2889                 default:
2890                 case SPEED_10:
2891                         break;
2892
2893                 case SPEED_100:
2894                         bmcr |= BMCR_SPEED100;
2895                         break;
2896
2897                 case SPEED_1000:
2898                         bmcr |= TG3_BMCR_SPEED1000;
2899                         break;
2900                 }
2901
2902                 if (tp->link_config.duplex == DUPLEX_FULL)
2903                         bmcr |= BMCR_FULLDPLX;
2904
2905                 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2906                     (bmcr != orig_bmcr)) {
2907                         tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2908                         for (i = 0; i < 1500; i++) {
2909                                 u32 tmp;
2910
2911                                 udelay(10);
2912                                 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2913                                     tg3_readphy(tp, MII_BMSR, &tmp))
2914                                         continue;
2915                                 if (!(tmp & BMSR_LSTATUS)) {
2916                                         udelay(40);
2917                                         break;
2918                                 }
2919                         }
2920                         tg3_writephy(tp, MII_BMCR, bmcr);
2921                         udelay(40);
2922                 }
2923         } else {
2924                 tg3_writephy(tp, MII_BMCR,
2925                              BMCR_ANENABLE | BMCR_ANRESTART);
2926         }
2927 }
2928
2929 static int tg3_init_5401phy_dsp(struct tg3 *tp)
2930 {
2931         int err;
2932
2933         /* Turn off tap power management. */
2934         /* Set Extended packet length bit */
2935         err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2936
2937         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
2938         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
2939
2940         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
2941         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
2942
2943         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2944         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
2945
2946         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2947         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
2948
2949         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2950         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
2951
2952         udelay(40);
2953
2954         return err;
2955 }
2956
2957 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
2958 {
2959         u32 adv_reg, all_mask = 0;
2960
2961         if (mask & ADVERTISED_10baseT_Half)
2962                 all_mask |= ADVERTISE_10HALF;
2963         if (mask & ADVERTISED_10baseT_Full)
2964                 all_mask |= ADVERTISE_10FULL;
2965         if (mask & ADVERTISED_100baseT_Half)
2966                 all_mask |= ADVERTISE_100HALF;
2967         if (mask & ADVERTISED_100baseT_Full)
2968                 all_mask |= ADVERTISE_100FULL;
2969
2970         if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
2971                 return 0;
2972
2973         if ((adv_reg & all_mask) != all_mask)
2974                 return 0;
2975         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
2976                 u32 tg3_ctrl;
2977
2978                 all_mask = 0;
2979                 if (mask & ADVERTISED_1000baseT_Half)
2980                         all_mask |= ADVERTISE_1000HALF;
2981                 if (mask & ADVERTISED_1000baseT_Full)
2982                         all_mask |= ADVERTISE_1000FULL;
2983
2984                 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
2985                         return 0;
2986
2987                 if ((tg3_ctrl & all_mask) != all_mask)
2988                         return 0;
2989         }
2990         return 1;
2991 }
2992
2993 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
2994 {
2995         u32 curadv, reqadv;
2996
2997         if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
2998                 return 1;
2999
3000         curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3001         reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
3002
3003         if (tp->link_config.active_duplex == DUPLEX_FULL) {
3004                 if (curadv != reqadv)
3005                         return 0;
3006
3007                 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
3008                         tg3_readphy(tp, MII_LPA, rmtadv);
3009         } else {
3010                 /* Reprogram the advertisement register, even if it
3011                  * does not affect the current link.  If the link
3012                  * gets renegotiated in the future, we can save an
3013                  * additional renegotiation cycle by advertising
3014                  * it correctly in the first place.
3015                  */
3016                 if (curadv != reqadv) {
3017                         *lcladv &= ~(ADVERTISE_PAUSE_CAP |
3018                                      ADVERTISE_PAUSE_ASYM);
3019                         tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
3020                 }
3021         }
3022
3023         return 1;
3024 }
3025
3026 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
3027 {
3028         int current_link_up;
3029         u32 bmsr, dummy;
3030         u32 lcl_adv, rmt_adv;
3031         u16 current_speed;
3032         u8 current_duplex;
3033         int i, err;
3034
3035         tw32(MAC_EVENT, 0);
3036
3037         tw32_f(MAC_STATUS,
3038              (MAC_STATUS_SYNC_CHANGED |
3039               MAC_STATUS_CFG_CHANGED |
3040               MAC_STATUS_MI_COMPLETION |
3041               MAC_STATUS_LNKSTATE_CHANGED));
3042         udelay(40);
3043
3044         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
3045                 tw32_f(MAC_MI_MODE,
3046                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
3047                 udelay(80);
3048         }
3049
3050         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
3051
3052         /* Some third-party PHYs need to be reset on link going
3053          * down.
3054          */
3055         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3056              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
3057              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
3058             netif_carrier_ok(tp->dev)) {
3059                 tg3_readphy(tp, MII_BMSR, &bmsr);
3060                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3061                     !(bmsr & BMSR_LSTATUS))
3062                         force_reset = 1;
3063         }
3064         if (force_reset)
3065                 tg3_phy_reset(tp);
3066
3067         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
3068                 tg3_readphy(tp, MII_BMSR, &bmsr);
3069                 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
3070                     !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
3071                         bmsr = 0;
3072
3073                 if (!(bmsr & BMSR_LSTATUS)) {
3074                         err = tg3_init_5401phy_dsp(tp);
3075                         if (err)
3076                                 return err;
3077
3078                         tg3_readphy(tp, MII_BMSR, &bmsr);
3079                         for (i = 0; i < 1000; i++) {
3080                                 udelay(10);
3081                                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3082                                     (bmsr & BMSR_LSTATUS)) {
3083                                         udelay(40);
3084                                         break;
3085                                 }
3086                         }
3087
3088                         if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
3089                             !(bmsr & BMSR_LSTATUS) &&
3090                             tp->link_config.active_speed == SPEED_1000) {
3091                                 err = tg3_phy_reset(tp);
3092                                 if (!err)
3093                                         err = tg3_init_5401phy_dsp(tp);
3094                                 if (err)
3095                                         return err;
3096                         }
3097                 }
3098         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3099                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3100                 /* 5701 {A0,B0} CRC bug workaround */
3101                 tg3_writephy(tp, 0x15, 0x0a75);
3102                 tg3_writephy(tp, 0x1c, 0x8c68);
3103                 tg3_writephy(tp, 0x1c, 0x8d68);
3104                 tg3_writephy(tp, 0x1c, 0x8c68);
3105         }
3106
3107         /* Clear pending interrupts... */
3108         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3109         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3110
3111         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
3112                 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
3113         else if (!(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
3114                 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3115
3116         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3117             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3118                 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3119                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
3120                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3121                 else
3122                         tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3123         }
3124
3125         current_link_up = 0;
3126         current_speed = SPEED_INVALID;
3127         current_duplex = DUPLEX_INVALID;
3128
3129         if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
3130                 u32 val;
3131
3132                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3133                 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3134                 if (!(val & (1 << 10))) {
3135                         val |= (1 << 10);
3136                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3137                         goto relink;
3138                 }
3139         }
3140
3141         bmsr = 0;
3142         for (i = 0; i < 100; i++) {
3143                 tg3_readphy(tp, MII_BMSR, &bmsr);
3144                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3145                     (bmsr & BMSR_LSTATUS))
3146                         break;
3147                 udelay(40);
3148         }
3149
3150         if (bmsr & BMSR_LSTATUS) {
3151                 u32 aux_stat, bmcr;
3152
3153                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3154                 for (i = 0; i < 2000; i++) {
3155                         udelay(10);
3156                         if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3157                             aux_stat)
3158                                 break;
3159                 }
3160
3161                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3162                                              &current_speed,
3163                                              &current_duplex);
3164
3165                 bmcr = 0;
3166                 for (i = 0; i < 200; i++) {
3167                         tg3_readphy(tp, MII_BMCR, &bmcr);
3168                         if (tg3_readphy(tp, MII_BMCR, &bmcr))
3169                                 continue;
3170                         if (bmcr && bmcr != 0x7fff)
3171                                 break;
3172                         udelay(10);
3173                 }
3174
3175                 lcl_adv = 0;
3176                 rmt_adv = 0;
3177
3178                 tp->link_config.active_speed = current_speed;
3179                 tp->link_config.active_duplex = current_duplex;
3180
3181                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3182                         if ((bmcr & BMCR_ANENABLE) &&
3183                             tg3_copper_is_advertising_all(tp,
3184                                                 tp->link_config.advertising)) {
3185                                 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3186                                                                   &rmt_adv))
3187                                         current_link_up = 1;
3188                         }
3189                 } else {
3190                         if (!(bmcr & BMCR_ANENABLE) &&
3191                             tp->link_config.speed == current_speed &&
3192                             tp->link_config.duplex == current_duplex &&
3193                             tp->link_config.flowctrl ==
3194                             tp->link_config.active_flowctrl) {
3195                                 current_link_up = 1;
3196                         }
3197                 }
3198
3199                 if (current_link_up == 1 &&
3200                     tp->link_config.active_duplex == DUPLEX_FULL)
3201                         tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
3202         }
3203
3204 relink:
3205         if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
3206                 u32 tmp;
3207
3208                 tg3_phy_copper_begin(tp);
3209
3210                 tg3_readphy(tp, MII_BMSR, &tmp);
3211                 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
3212                     (tmp & BMSR_LSTATUS))
3213                         current_link_up = 1;
3214         }
3215
3216         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3217         if (current_link_up == 1) {
3218                 if (tp->link_config.active_speed == SPEED_100 ||
3219                     tp->link_config.active_speed == SPEED_10)
3220                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3221                 else
3222                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3223         } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)
3224                 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3225         else
3226                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3227
3228         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3229         if (tp->link_config.active_duplex == DUPLEX_HALF)
3230                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3231
3232         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
3233                 if (current_link_up == 1 &&
3234                     tg3_5700_link_polarity(tp, tp->link_config.active_speed))
3235                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
3236                 else
3237                         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
3238         }
3239
3240         /* ??? Without this setting Netgear GA302T PHY does not
3241          * ??? send/receive packets...
3242          */
3243         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
3244             tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3245                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3246                 tw32_f(MAC_MI_MODE, tp->mi_mode);
3247                 udelay(80);
3248         }
3249
3250         tw32_f(MAC_MODE, tp->mac_mode);
3251         udelay(40);
3252
3253         if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3254                 /* Polled via timer. */
3255                 tw32_f(MAC_EVENT, 0);
3256         } else {
3257                 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3258         }
3259         udelay(40);
3260
3261         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3262             current_link_up == 1 &&
3263             tp->link_config.active_speed == SPEED_1000 &&
3264             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3265              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3266                 udelay(120);
3267                 tw32_f(MAC_STATUS,
3268                      (MAC_STATUS_SYNC_CHANGED |
3269                       MAC_STATUS_CFG_CHANGED));
3270                 udelay(40);
3271                 tg3_write_mem(tp,
3272                               NIC_SRAM_FIRMWARE_MBOX,
3273                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3274         }
3275
3276         /* Prevent send BD corruption. */
3277         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3278                 u16 oldlnkctl, newlnkctl;
3279
3280                 pci_read_config_word(tp->pdev,
3281                                      tp->pcie_cap + PCI_EXP_LNKCTL,
3282                                      &oldlnkctl);
3283                 if (tp->link_config.active_speed == SPEED_100 ||
3284                     tp->link_config.active_speed == SPEED_10)
3285                         newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3286                 else
3287                         newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3288                 if (newlnkctl != oldlnkctl)
3289                         pci_write_config_word(tp->pdev,
3290                                               tp->pcie_cap + PCI_EXP_LNKCTL,
3291                                               newlnkctl);
3292         }
3293
3294         if (current_link_up != netif_carrier_ok(tp->dev)) {
3295                 if (current_link_up)
3296                         netif_carrier_on(tp->dev);
3297                 else
3298                         netif_carrier_off(tp->dev);
3299                 tg3_link_report(tp);
3300         }
3301
3302         return 0;
3303 }
3304
3305 struct tg3_fiber_aneginfo {
3306         int state;
3307 #define ANEG_STATE_UNKNOWN              0
3308 #define ANEG_STATE_AN_ENABLE            1
3309 #define ANEG_STATE_RESTART_INIT         2
3310 #define ANEG_STATE_RESTART              3
3311 #define ANEG_STATE_DISABLE_LINK_OK      4
3312 #define ANEG_STATE_ABILITY_DETECT_INIT  5
3313 #define ANEG_STATE_ABILITY_DETECT       6
3314 #define ANEG_STATE_ACK_DETECT_INIT      7
3315 #define ANEG_STATE_ACK_DETECT           8
3316 #define ANEG_STATE_COMPLETE_ACK_INIT    9
3317 #define ANEG_STATE_COMPLETE_ACK         10
3318 #define ANEG_STATE_IDLE_DETECT_INIT     11
3319 #define ANEG_STATE_IDLE_DETECT          12
3320 #define ANEG_STATE_LINK_OK              13
3321 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
3322 #define ANEG_STATE_NEXT_PAGE_WAIT       15
3323
3324         u32 flags;
3325 #define MR_AN_ENABLE            0x00000001
3326 #define MR_RESTART_AN           0x00000002
3327 #define MR_AN_COMPLETE          0x00000004
3328 #define MR_PAGE_RX              0x00000008
3329 #define MR_NP_LOADED            0x00000010
3330 #define MR_TOGGLE_TX            0x00000020
3331 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
3332 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
3333 #define MR_LP_ADV_SYM_PAUSE     0x00000100
3334 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
3335 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3336 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3337 #define MR_LP_ADV_NEXT_PAGE     0x00001000
3338 #define MR_TOGGLE_RX            0x00002000
3339 #define MR_NP_RX                0x00004000
3340
3341 #define MR_LINK_OK              0x80000000
3342
3343         unsigned long link_time, cur_time;
3344
3345         u32 ability_match_cfg;
3346         int ability_match_count;
3347
3348         char ability_match, idle_match, ack_match;
3349
3350         u32 txconfig, rxconfig;
3351 #define ANEG_CFG_NP             0x00000080
3352 #define ANEG_CFG_ACK            0x00000040
3353 #define ANEG_CFG_RF2            0x00000020
3354 #define ANEG_CFG_RF1            0x00000010
3355 #define ANEG_CFG_PS2            0x00000001
3356 #define ANEG_CFG_PS1            0x00008000
3357 #define ANEG_CFG_HD             0x00004000
3358 #define ANEG_CFG_FD             0x00002000
3359 #define ANEG_CFG_INVAL          0x00001f06
3360
3361 };
3362 #define ANEG_OK         0
3363 #define ANEG_DONE       1
3364 #define ANEG_TIMER_ENAB 2
3365 #define ANEG_FAILED     -1
3366
3367 #define ANEG_STATE_SETTLE_TIME  10000
3368
3369 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3370                                    struct tg3_fiber_aneginfo *ap)
3371 {
3372         u16 flowctrl;
3373         unsigned long delta;
3374         u32 rx_cfg_reg;
3375         int ret;
3376
3377         if (ap->state == ANEG_STATE_UNKNOWN) {
3378                 ap->rxconfig = 0;
3379                 ap->link_time = 0;
3380                 ap->cur_time = 0;
3381                 ap->ability_match_cfg = 0;
3382                 ap->ability_match_count = 0;
3383                 ap->ability_match = 0;
3384                 ap->idle_match = 0;
3385                 ap->ack_match = 0;
3386         }
3387         ap->cur_time++;
3388
3389         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3390                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3391
3392                 if (rx_cfg_reg != ap->ability_match_cfg) {
3393                         ap->ability_match_cfg = rx_cfg_reg;
3394                         ap->ability_match = 0;
3395                         ap->ability_match_count = 0;
3396                 } else {
3397                         if (++ap->ability_match_count > 1) {
3398                                 ap->ability_match = 1;
3399                                 ap->ability_match_cfg = rx_cfg_reg;
3400                         }
3401                 }
3402                 if (rx_cfg_reg & ANEG_CFG_ACK)
3403                         ap->ack_match = 1;
3404                 else
3405                         ap->ack_match = 0;
3406
3407                 ap->idle_match = 0;
3408         } else {
3409                 ap->idle_match = 1;
3410                 ap->ability_match_cfg = 0;
3411                 ap->ability_match_count = 0;
3412                 ap->ability_match = 0;
3413                 ap->ack_match = 0;
3414
3415                 rx_cfg_reg = 0;
3416         }
3417
3418         ap->rxconfig = rx_cfg_reg;
3419         ret = ANEG_OK;
3420
3421         switch(ap->state) {
3422         case ANEG_STATE_UNKNOWN:
3423                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3424                         ap->state = ANEG_STATE_AN_ENABLE;
3425
3426                 /* fallthru */
3427         case ANEG_STATE_AN_ENABLE:
3428                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3429                 if (ap->flags & MR_AN_ENABLE) {
3430                         ap->link_time = 0;
3431                         ap->cur_time = 0;
3432                         ap->ability_match_cfg = 0;
3433                         ap->ability_match_count = 0;
3434                         ap->ability_match = 0;
3435                         ap->idle_match = 0;
3436                         ap->ack_match = 0;
3437
3438                         ap->state = ANEG_STATE_RESTART_INIT;
3439                 } else {
3440                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
3441                 }
3442                 break;
3443
3444         case ANEG_STATE_RESTART_INIT:
3445                 ap->link_time = ap->cur_time;
3446                 ap->flags &= ~(MR_NP_LOADED);
3447                 ap->txconfig = 0;
3448                 tw32(MAC_TX_AUTO_NEG, 0);
3449                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3450                 tw32_f(MAC_MODE, tp->mac_mode);
3451                 udelay(40);
3452
3453                 ret = ANEG_TIMER_ENAB;
3454                 ap->state = ANEG_STATE_RESTART;
3455
3456                 /* fallthru */
3457         case ANEG_STATE_RESTART:
3458                 delta = ap->cur_time - ap->link_time;
3459                 if (delta > ANEG_STATE_SETTLE_TIME) {
3460                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3461                 } else {
3462                         ret = ANEG_TIMER_ENAB;
3463                 }
3464                 break;
3465
3466         case ANEG_STATE_DISABLE_LINK_OK:
3467                 ret = ANEG_DONE;
3468                 break;
3469
3470         case ANEG_STATE_ABILITY_DETECT_INIT:
3471                 ap->flags &= ~(MR_TOGGLE_TX);
3472                 ap->txconfig = ANEG_CFG_FD;
3473                 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3474                 if (flowctrl & ADVERTISE_1000XPAUSE)
3475                         ap->txconfig |= ANEG_CFG_PS1;
3476                 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3477                         ap->txconfig |= ANEG_CFG_PS2;
3478                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3479                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3480                 tw32_f(MAC_MODE, tp->mac_mode);
3481                 udelay(40);
3482
3483                 ap->state = ANEG_STATE_ABILITY_DETECT;
3484                 break;
3485
3486         case ANEG_STATE_ABILITY_DETECT:
3487                 if (ap->ability_match != 0 && ap->rxconfig != 0) {
3488                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
3489                 }
3490                 break;
3491
3492         case ANEG_STATE_ACK_DETECT_INIT:
3493                 ap->txconfig |= ANEG_CFG_ACK;
3494                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3495                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3496                 tw32_f(MAC_MODE, tp->mac_mode);
3497                 udelay(40);
3498
3499                 ap->state = ANEG_STATE_ACK_DETECT;
3500
3501                 /* fallthru */
3502         case ANEG_STATE_ACK_DETECT:
3503                 if (ap->ack_match != 0) {
3504                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3505                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3506                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3507                         } else {
3508                                 ap->state = ANEG_STATE_AN_ENABLE;
3509                         }
3510                 } else if (ap->ability_match != 0 &&
3511                            ap->rxconfig == 0) {
3512                         ap->state = ANEG_STATE_AN_ENABLE;
3513                 }
3514                 break;
3515
3516         case ANEG_STATE_COMPLETE_ACK_INIT:
3517                 if (ap->rxconfig & ANEG_CFG_INVAL) {
3518                         ret = ANEG_FAILED;
3519                         break;
3520                 }
3521                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3522                                MR_LP_ADV_HALF_DUPLEX |
3523                                MR_LP_ADV_SYM_PAUSE |
3524                                MR_LP_ADV_ASYM_PAUSE |
3525                                MR_LP_ADV_REMOTE_FAULT1 |
3526                                MR_LP_ADV_REMOTE_FAULT2 |
3527                                MR_LP_ADV_NEXT_PAGE |
3528                                MR_TOGGLE_RX |
3529                                MR_NP_RX);
3530                 if (ap->rxconfig & ANEG_CFG_FD)
3531                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3532                 if (ap->rxconfig & ANEG_CFG_HD)
3533                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3534                 if (ap->rxconfig & ANEG_CFG_PS1)
3535                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
3536                 if (ap->rxconfig & ANEG_CFG_PS2)
3537                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3538                 if (ap->rxconfig & ANEG_CFG_RF1)
3539                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3540                 if (ap->rxconfig & ANEG_CFG_RF2)
3541                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3542                 if (ap->rxconfig & ANEG_CFG_NP)
3543                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
3544
3545                 ap->link_time = ap->cur_time;
3546
3547                 ap->flags ^= (MR_TOGGLE_TX);
3548                 if (ap->rxconfig & 0x0008)
3549                         ap->flags |= MR_TOGGLE_RX;
3550                 if (ap->rxconfig & ANEG_CFG_NP)
3551                         ap->flags |= MR_NP_RX;
3552                 ap->flags |= MR_PAGE_RX;
3553
3554                 ap->state = ANEG_STATE_COMPLETE_ACK;
3555                 ret = ANEG_TIMER_ENAB;
3556                 break;
3557
3558         case ANEG_STATE_COMPLETE_ACK:
3559                 if (ap->ability_match != 0 &&
3560                     ap->rxconfig == 0) {
3561                         ap->state = ANEG_STATE_AN_ENABLE;
3562                         break;
3563                 }
3564                 delta = ap->cur_time - ap->link_time;
3565                 if (delta > ANEG_STATE_SETTLE_TIME) {
3566                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3567                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3568                         } else {
3569                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3570                                     !(ap->flags & MR_NP_RX)) {
3571                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3572                                 } else {
3573                                         ret = ANEG_FAILED;
3574                                 }
3575                         }
3576                 }
3577                 break;
3578
3579         case ANEG_STATE_IDLE_DETECT_INIT:
3580                 ap->link_time = ap->cur_time;
3581                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3582                 tw32_f(MAC_MODE, tp->mac_mode);
3583                 udelay(40);
3584
3585                 ap->state = ANEG_STATE_IDLE_DETECT;
3586                 ret = ANEG_TIMER_ENAB;
3587                 break;
3588
3589         case ANEG_STATE_IDLE_DETECT:
3590                 if (ap->ability_match != 0 &&
3591                     ap->rxconfig == 0) {
3592                         ap->state = ANEG_STATE_AN_ENABLE;
3593                         break;
3594                 }
3595                 delta = ap->cur_time - ap->link_time;
3596                 if (delta > ANEG_STATE_SETTLE_TIME) {
3597                         /* XXX another gem from the Broadcom driver :( */
3598                         ap->state = ANEG_STATE_LINK_OK;
3599                 }
3600                 break;
3601
3602         case ANEG_STATE_LINK_OK:
3603                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3604                 ret = ANEG_DONE;
3605                 break;
3606
3607         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3608                 /* ??? unimplemented */
3609                 break;
3610
3611         case ANEG_STATE_NEXT_PAGE_WAIT:
3612                 /* ??? unimplemented */
3613                 break;
3614
3615         default:
3616                 ret = ANEG_FAILED;
3617                 break;
3618         }
3619
3620         return ret;
3621 }
3622
3623 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
3624 {
3625         int res = 0;
3626         struct tg3_fiber_aneginfo aninfo;
3627         int status = ANEG_FAILED;
3628         unsigned int tick;
3629         u32 tmp;
3630
3631         tw32_f(MAC_TX_AUTO_NEG, 0);
3632
3633         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3634         tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3635         udelay(40);
3636
3637         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3638         udelay(40);
3639
3640         memset(&aninfo, 0, sizeof(aninfo));
3641         aninfo.flags |= MR_AN_ENABLE;
3642         aninfo.state = ANEG_STATE_UNKNOWN;
3643         aninfo.cur_time = 0;
3644         tick = 0;
3645         while (++tick < 195000) {
3646                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3647                 if (status == ANEG_DONE || status == ANEG_FAILED)
3648                         break;
3649
3650                 udelay(1);
3651         }
3652
3653         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3654         tw32_f(MAC_MODE, tp->mac_mode);
3655         udelay(40);
3656
3657         *txflags = aninfo.txconfig;
3658         *rxflags = aninfo.flags;
3659
3660         if (status == ANEG_DONE &&
3661             (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3662                              MR_LP_ADV_FULL_DUPLEX)))
3663                 res = 1;
3664
3665         return res;
3666 }
3667
3668 static void tg3_init_bcm8002(struct tg3 *tp)
3669 {
3670         u32 mac_status = tr32(MAC_STATUS);
3671         int i;
3672
3673         /* Reset when initting first time or we have a link. */
3674         if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3675             !(mac_status & MAC_STATUS_PCS_SYNCED))
3676                 return;
3677
3678         /* Set PLL lock range. */
3679         tg3_writephy(tp, 0x16, 0x8007);
3680
3681         /* SW reset */
3682         tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3683
3684         /* Wait for reset to complete. */
3685         /* XXX schedule_timeout() ... */
3686         for (i = 0; i < 500; i++)
3687                 udelay(10);
3688
3689         /* Config mode; select PMA/Ch 1 regs. */
3690         tg3_writephy(tp, 0x10, 0x8411);
3691
3692         /* Enable auto-lock and comdet, select txclk for tx. */
3693         tg3_writephy(tp, 0x11, 0x0a10);
3694
3695         tg3_writephy(tp, 0x18, 0x00a0);
3696         tg3_writephy(tp, 0x16, 0x41ff);
3697
3698         /* Assert and deassert POR. */
3699         tg3_writephy(tp, 0x13, 0x0400);
3700         udelay(40);
3701         tg3_writephy(tp, 0x13, 0x0000);
3702
3703         tg3_writephy(tp, 0x11, 0x0a50);
3704         udelay(40);
3705         tg3_writephy(tp, 0x11, 0x0a10);
3706
3707         /* Wait for signal to stabilize */
3708         /* XXX schedule_timeout() ... */
3709         for (i = 0; i < 15000; i++)
3710                 udelay(10);
3711
3712         /* Deselect the channel register so we can read the PHYID
3713          * later.
3714          */
3715         tg3_writephy(tp, 0x10, 0x8011);
3716 }
3717
3718 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3719 {
3720         u16 flowctrl;
3721         u32 sg_dig_ctrl, sg_dig_status;
3722         u32 serdes_cfg, expected_sg_dig_ctrl;
3723         int workaround, port_a;
3724         int current_link_up;
3725
3726         serdes_cfg = 0;
3727         expected_sg_dig_ctrl = 0;
3728         workaround = 0;
3729         port_a = 1;
3730         current_link_up = 0;
3731
3732         if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3733             tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3734                 workaround = 1;
3735                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3736                         port_a = 0;
3737
3738                 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3739                 /* preserve bits 20-23 for voltage regulator */
3740                 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3741         }
3742
3743         sg_dig_ctrl = tr32(SG_DIG_CTRL);
3744
3745         if (tp->link_config.autoneg != AUTONEG_ENABLE) {
3746                 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
3747                         if (workaround) {
3748                                 u32 val = serdes_cfg;
3749
3750                                 if (port_a)
3751                                         val |= 0xc010000;
3752                                 else
3753                                         val |= 0x4010000;
3754                                 tw32_f(MAC_SERDES_CFG, val);
3755                         }
3756
3757                         tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3758                 }
3759                 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3760                         tg3_setup_flow_control(tp, 0, 0);
3761                         current_link_up = 1;
3762                 }
3763                 goto out;
3764         }
3765
3766         /* Want auto-negotiation.  */
3767         expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
3768
3769         flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3770         if (flowctrl & ADVERTISE_1000XPAUSE)
3771                 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3772         if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3773                 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
3774
3775         if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3776                 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
3777                     tp->serdes_counter &&
3778                     ((mac_status & (MAC_STATUS_PCS_SYNCED |
3779                                     MAC_STATUS_RCVD_CFG)) ==
3780                      MAC_STATUS_PCS_SYNCED)) {
3781                         tp->serdes_counter--;
3782                         current_link_up = 1;
3783                         goto out;
3784                 }
3785 restart_autoneg:
3786                 if (workaround)
3787                         tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
3788                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
3789                 udelay(5);
3790                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3791
3792                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3793                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3794         } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3795                                  MAC_STATUS_SIGNAL_DET)) {
3796                 sg_dig_status = tr32(SG_DIG_STATUS);
3797                 mac_status = tr32(MAC_STATUS);
3798
3799                 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
3800                     (mac_status & MAC_STATUS_PCS_SYNCED)) {
3801                         u32 local_adv = 0, remote_adv = 0;
3802
3803                         if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3804                                 local_adv |= ADVERTISE_1000XPAUSE;
3805                         if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3806                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3807
3808                         if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
3809                                 remote_adv |= LPA_1000XPAUSE;
3810                         if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
3811                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3812
3813                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3814                         current_link_up = 1;
3815                         tp->serdes_counter = 0;
3816                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3817                 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3818                         if (tp->serdes_counter)
3819                                 tp->serdes_counter--;
3820                         else {
3821                                 if (workaround) {
3822                                         u32 val = serdes_cfg;
3823
3824                                         if (port_a)
3825                                                 val |= 0xc010000;
3826                                         else
3827                                                 val |= 0x4010000;
3828
3829                                         tw32_f(MAC_SERDES_CFG, val);
3830                                 }
3831
3832                                 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3833                                 udelay(40);
3834
3835                                 /* Link parallel detection - link is up */
3836                                 /* only if we have PCS_SYNC and not */
3837                                 /* receiving config code words */
3838                                 mac_status = tr32(MAC_STATUS);
3839                                 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3840                                     !(mac_status & MAC_STATUS_RCVD_CFG)) {
3841                                         tg3_setup_flow_control(tp, 0, 0);
3842                                         current_link_up = 1;
3843                                         tp->tg3_flags2 |=
3844                                                 TG3_FLG2_PARALLEL_DETECT;
3845                                         tp->serdes_counter =
3846                                                 SERDES_PARALLEL_DET_TIMEOUT;
3847                                 } else
3848                                         goto restart_autoneg;
3849                         }
3850                 }
3851         } else {
3852                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3853                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3854         }
3855
3856 out:
3857         return current_link_up;
3858 }
3859
3860 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3861 {
3862         int current_link_up = 0;
3863
3864         if (!(mac_status & MAC_STATUS_PCS_SYNCED))
3865                 goto out;
3866
3867         if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3868                 u32 txflags, rxflags;
3869                 int i;
3870
3871                 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3872                         u32 local_adv = 0, remote_adv = 0;
3873
3874                         if (txflags & ANEG_CFG_PS1)
3875                                 local_adv |= ADVERTISE_1000XPAUSE;
3876                         if (txflags & ANEG_CFG_PS2)
3877                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3878
3879                         if (rxflags & MR_LP_ADV_SYM_PAUSE)
3880                                 remote_adv |= LPA_1000XPAUSE;
3881                         if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3882                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3883
3884                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3885
3886                         current_link_up = 1;
3887                 }
3888                 for (i = 0; i < 30; i++) {
3889                         udelay(20);
3890                         tw32_f(MAC_STATUS,
3891                                (MAC_STATUS_SYNC_CHANGED |
3892                                 MAC_STATUS_CFG_CHANGED));
3893                         udelay(40);
3894                         if ((tr32(MAC_STATUS) &
3895                              (MAC_STATUS_SYNC_CHANGED |
3896                               MAC_STATUS_CFG_CHANGED)) == 0)
3897                                 break;
3898                 }
3899
3900                 mac_status = tr32(MAC_STATUS);
3901                 if (current_link_up == 0 &&
3902                     (mac_status & MAC_STATUS_PCS_SYNCED) &&
3903                     !(mac_status & MAC_STATUS_RCVD_CFG))
3904                         current_link_up = 1;
3905         } else {
3906                 tg3_setup_flow_control(tp, 0, 0);
3907
3908                 /* Forcing 1000FD link up. */
3909                 current_link_up = 1;
3910
3911                 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3912                 udelay(40);
3913
3914                 tw32_f(MAC_MODE, tp->mac_mode);
3915                 udelay(40);
3916         }
3917
3918 out:
3919         return current_link_up;
3920 }
3921
3922 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3923 {
3924         u32 orig_pause_cfg;
3925         u16 orig_active_speed;
3926         u8 orig_active_duplex;
3927         u32 mac_status;
3928         int current_link_up;
3929         int i;
3930
3931         orig_pause_cfg = tp->link_config.active_flowctrl;
3932         orig_active_speed = tp->link_config.active_speed;
3933         orig_active_duplex = tp->link_config.active_duplex;
3934
3935         if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3936             netif_carrier_ok(tp->dev) &&
3937             (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3938                 mac_status = tr32(MAC_STATUS);
3939                 mac_status &= (MAC_STATUS_PCS_SYNCED |
3940                                MAC_STATUS_SIGNAL_DET |
3941                                MAC_STATUS_CFG_CHANGED |
3942                                MAC_STATUS_RCVD_CFG);
3943                 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3944                                    MAC_STATUS_SIGNAL_DET)) {
3945                         tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3946                                             MAC_STATUS_CFG_CHANGED));
3947                         return 0;
3948                 }
3949         }
3950
3951         tw32_f(MAC_TX_AUTO_NEG, 0);
3952
3953         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3954         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3955         tw32_f(MAC_MODE, tp->mac_mode);
3956         udelay(40);
3957
3958         if (tp->phy_id == PHY_ID_BCM8002)
3959                 tg3_init_bcm8002(tp);
3960
3961         /* Enable link change event even when serdes polling.  */
3962         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3963         udelay(40);
3964
3965         current_link_up = 0;
3966         mac_status = tr32(MAC_STATUS);
3967
3968         if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
3969                 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
3970         else
3971                 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
3972
3973         tp->napi[0].hw_status->status =
3974                 (SD_STATUS_UPDATED |
3975                  (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
3976
3977         for (i = 0; i < 100; i++) {
3978                 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3979                                     MAC_STATUS_CFG_CHANGED));
3980                 udelay(5);
3981                 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3982                                          MAC_STATUS_CFG_CHANGED |
3983                                          MAC_STATUS_LNKSTATE_CHANGED)) == 0)
3984                         break;
3985         }
3986
3987         mac_status = tr32(MAC_STATUS);
3988         if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
3989                 current_link_up = 0;
3990                 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
3991                     tp->serdes_counter == 0) {
3992                         tw32_f(MAC_MODE, (tp->mac_mode |
3993                                           MAC_MODE_SEND_CONFIGS));
3994                         udelay(1);
3995                         tw32_f(MAC_MODE, tp->mac_mode);
3996                 }
3997         }
3998
3999         if (current_link_up == 1) {
4000                 tp->link_config.active_speed = SPEED_1000;
4001                 tp->link_config.active_duplex = DUPLEX_FULL;
4002                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4003                                     LED_CTRL_LNKLED_OVERRIDE |
4004                                     LED_CTRL_1000MBPS_ON));
4005         } else {
4006                 tp->link_config.active_speed = SPEED_INVALID;
4007                 tp->link_config.active_duplex = DUPLEX_INVALID;
4008                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4009                                     LED_CTRL_LNKLED_OVERRIDE |
4010                                     LED_CTRL_TRAFFIC_OVERRIDE));
4011         }
4012
4013         if (current_link_up != netif_carrier_ok(tp->dev)) {
4014                 if (current_link_up)
4015                         netif_carrier_on(tp->dev);
4016                 else
4017                         netif_carrier_off(tp->dev);
4018                 tg3_link_report(tp);
4019         } else {
4020                 u32 now_pause_cfg = tp->link_config.active_flowctrl;
4021                 if (orig_pause_cfg != now_pause_cfg ||
4022                     orig_active_speed != tp->link_config.active_speed ||
4023                     orig_active_duplex != tp->link_config.active_duplex)
4024                         tg3_link_report(tp);
4025         }
4026
4027         return 0;
4028 }
4029
4030 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
4031 {
4032         int current_link_up, err = 0;
4033         u32 bmsr, bmcr;
4034         u16 current_speed;
4035         u8 current_duplex;
4036         u32 local_adv, remote_adv;
4037
4038         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4039         tw32_f(MAC_MODE, tp->mac_mode);
4040         udelay(40);
4041
4042         tw32(MAC_EVENT, 0);
4043
4044         tw32_f(MAC_STATUS,
4045              (MAC_STATUS_SYNC_CHANGED |
4046               MAC_STATUS_CFG_CHANGED |
4047               MAC_STATUS_MI_COMPLETION |
4048               MAC_STATUS_LNKSTATE_CHANGED));
4049         udelay(40);
4050
4051         if (force_reset)
4052                 tg3_phy_reset(tp);
4053
4054         current_link_up = 0;
4055         current_speed = SPEED_INVALID;
4056         current_duplex = DUPLEX_INVALID;
4057
4058         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4059         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4060         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
4061                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4062                         bmsr |= BMSR_LSTATUS;
4063                 else
4064                         bmsr &= ~BMSR_LSTATUS;
4065         }
4066
4067         err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4068
4069         if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
4070             (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4071                 /* do nothing, just check for link up at the end */
4072         } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4073                 u32 adv, new_adv;
4074
4075                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4076                 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4077                                   ADVERTISE_1000XPAUSE |
4078                                   ADVERTISE_1000XPSE_ASYM |
4079                                   ADVERTISE_SLCT);
4080
4081                 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4082
4083                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4084                         new_adv |= ADVERTISE_1000XHALF;
4085                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4086                         new_adv |= ADVERTISE_1000XFULL;
4087
4088                 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4089                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
4090                         bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4091                         tg3_writephy(tp, MII_BMCR, bmcr);
4092
4093                         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4094                         tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
4095                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4096
4097                         return err;
4098                 }
4099         } else {
4100                 u32 new_bmcr;
4101
4102                 bmcr &= ~BMCR_SPEED1000;
4103                 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4104
4105                 if (tp->link_config.duplex == DUPLEX_FULL)
4106                         new_bmcr |= BMCR_FULLDPLX;
4107
4108                 if (new_bmcr != bmcr) {
4109                         /* BMCR_SPEED1000 is a reserved bit that needs
4110                          * to be set on write.
4111                          */
4112                         new_bmcr |= BMCR_SPEED1000;
4113
4114                         /* Force a linkdown */
4115                         if (netif_carrier_ok(tp->dev)) {
4116                                 u32 adv;
4117
4118                                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4119                                 adv &= ~(ADVERTISE_1000XFULL |
4120                                          ADVERTISE_1000XHALF |
4121                                          ADVERTISE_SLCT);
4122                                 tg3_writephy(tp, MII_ADVERTISE, adv);
4123                                 tg3_writephy(tp, MII_BMCR, bmcr |
4124                                                            BMCR_ANRESTART |
4125                                                            BMCR_ANENABLE);
4126                                 udelay(10);
4127                                 netif_carrier_off(tp->dev);
4128                         }
4129                         tg3_writephy(tp, MII_BMCR, new_bmcr);
4130                         bmcr = new_bmcr;
4131                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4132                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4133                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4134                             ASIC_REV_5714) {
4135                                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4136                                         bmsr |= BMSR_LSTATUS;
4137                                 else
4138                                         bmsr &= ~BMSR_LSTATUS;
4139                         }
4140                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4141                 }
4142         }
4143
4144         if (bmsr & BMSR_LSTATUS) {
4145                 current_speed = SPEED_1000;
4146                 current_link_up = 1;
4147                 if (bmcr & BMCR_FULLDPLX)
4148                         current_duplex = DUPLEX_FULL;
4149                 else
4150                         current_duplex = DUPLEX_HALF;
4151
4152                 local_adv = 0;
4153                 remote_adv = 0;
4154
4155                 if (bmcr & BMCR_ANENABLE) {
4156                         u32 common;
4157
4158                         err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4159                         err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4160                         common = local_adv & remote_adv;
4161                         if (common & (ADVERTISE_1000XHALF |
4162                                       ADVERTISE_1000XFULL)) {
4163                                 if (common & ADVERTISE_1000XFULL)
4164                                         current_duplex = DUPLEX_FULL;
4165                                 else
4166                                         current_duplex = DUPLEX_HALF;
4167                         }
4168                         else
4169                                 current_link_up = 0;
4170                 }
4171         }
4172
4173         if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4174                 tg3_setup_flow_control(tp, local_adv, remote_adv);
4175
4176         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4177         if (tp->link_config.active_duplex == DUPLEX_HALF)
4178                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4179
4180         tw32_f(MAC_MODE, tp->mac_mode);
4181         udelay(40);
4182
4183         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4184
4185         tp->link_config.active_speed = current_speed;
4186         tp->link_config.active_duplex = current_duplex;
4187
4188         if (current_link_up != netif_carrier_ok(tp->dev)) {
4189                 if (current_link_up)
4190                         netif_carrier_on(tp->dev);
4191                 else {
4192                         netif_carrier_off(tp->dev);
4193                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4194                 }
4195                 tg3_link_report(tp);
4196         }
4197         return err;
4198 }
4199
4200 static void tg3_serdes_parallel_detect(struct tg3 *tp)
4201 {
4202         if (tp->serdes_counter) {
4203                 /* Give autoneg time to complete. */
4204                 tp->serdes_counter--;
4205                 return;
4206         }
4207         if (!netif_carrier_ok(tp->dev) &&
4208             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4209                 u32 bmcr;
4210
4211                 tg3_readphy(tp, MII_BMCR, &bmcr);
4212                 if (bmcr & BMCR_ANENABLE) {
4213                         u32 phy1, phy2;
4214
4215                         /* Select shadow register 0x1f */
4216                         tg3_writephy(tp, 0x1c, 0x7c00);
4217                         tg3_readphy(tp, 0x1c, &phy1);
4218
4219                         /* Select expansion interrupt status register */
4220                         tg3_writephy(tp, 0x17, 0x0f01);
4221                         tg3_readphy(tp, 0x15, &phy2);
4222                         tg3_readphy(tp, 0x15, &phy2);
4223
4224                         if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4225                                 /* We have signal detect and not receiving
4226                                  * config code words, link is up by parallel
4227                                  * detection.
4228                                  */
4229
4230                                 bmcr &= ~BMCR_ANENABLE;
4231                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4232                                 tg3_writephy(tp, MII_BMCR, bmcr);
4233                                 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
4234                         }
4235                 }
4236         }
4237         else if (netif_carrier_ok(tp->dev) &&
4238                  (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4239                  (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4240                 u32 phy2;
4241
4242                 /* Select expansion interrupt status register */
4243                 tg3_writephy(tp, 0x17, 0x0f01);
4244                 tg3_readphy(tp, 0x15, &phy2);
4245                 if (phy2 & 0x20) {
4246                         u32 bmcr;
4247
4248                         /* Config code words received, turn on autoneg. */
4249                         tg3_readphy(tp, MII_BMCR, &bmcr);
4250                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4251
4252                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4253
4254                 }
4255         }
4256 }
4257
4258 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4259 {
4260         int err;
4261
4262         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4263                 err = tg3_setup_fiber_phy(tp, force_reset);
4264         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
4265                 err = tg3_setup_fiber_mii_phy(tp, force_reset);
4266         } else {
4267                 err = tg3_setup_copper_phy(tp, force_reset);
4268         }
4269
4270         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
4271                 u32 val, scale;
4272
4273                 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4274                 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4275                         scale = 65;
4276                 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4277                         scale = 6;
4278                 else
4279                         scale = 12;
4280
4281                 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4282                 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4283                 tw32(GRC_MISC_CFG, val);
4284         }
4285
4286         if (tp->link_config.active_speed == SPEED_1000 &&
4287             tp->link_config.active_duplex == DUPLEX_HALF)
4288                 tw32(MAC_TX_LENGTHS,
4289                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4290                       (6 << TX_LENGTHS_IPG_SHIFT) |
4291                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4292         else
4293                 tw32(MAC_TX_LENGTHS,
4294                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4295                       (6 << TX_LENGTHS_IPG_SHIFT) |
4296                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4297
4298         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4299                 if (netif_carrier_ok(tp->dev)) {
4300                         tw32(HOSTCC_STAT_COAL_TICKS,
4301                              tp->coal.stats_block_coalesce_usecs);
4302                 } else {
4303                         tw32(HOSTCC_STAT_COAL_TICKS, 0);
4304                 }
4305         }
4306
4307         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4308                 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4309                 if (!netif_carrier_ok(tp->dev))
4310                         val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4311                               tp->pwrmgmt_thresh;
4312                 else
4313                         val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4314                 tw32(PCIE_PWR_MGMT_THRESH, val);
4315         }
4316
4317         return err;
4318 }
4319
4320 /* This is called whenever we suspect that the system chipset is re-
4321  * ordering the sequence of MMIO to the tx send mailbox. The symptom
4322  * is bogus tx completions. We try to recover by setting the
4323  * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4324  * in the workqueue.
4325  */
4326 static void tg3_tx_recover(struct tg3 *tp)
4327 {
4328         BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4329                tp->write32_tx_mbox == tg3_write_indirect_mbox);
4330
4331         printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
4332                "mapped I/O cycles to the network device, attempting to "
4333                "recover. Please report the problem to the driver maintainer "
4334                "and include system chipset information.\n", tp->dev->name);
4335
4336         spin_lock(&tp->lock);
4337         tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
4338         spin_unlock(&tp->lock);
4339 }
4340
4341 static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
4342 {
4343         smp_mb();
4344         return tnapi->tx_pending -
4345                ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
4346 }
4347
4348 /* Tigon3 never reports partial packet sends.  So we do not
4349  * need special logic to handle SKBs that have not had all
4350  * of their frags sent yet, like SunGEM does.
4351  */
4352 static void tg3_tx(struct tg3_napi *tnapi)
4353 {
4354         struct tg3 *tp = tnapi->tp;
4355         u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
4356         u32 sw_idx = tnapi->tx_cons;
4357         struct netdev_queue *txq;
4358         int index = tnapi - tp->napi;
4359
4360         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
4361                 index--;
4362
4363         txq = netdev_get_tx_queue(tp->dev, index);
4364
4365         while (sw_idx != hw_idx) {
4366                 struct ring_info *ri = &tnapi->tx_buffers[sw_idx];
4367                 struct sk_buff *skb = ri->skb;
4368                 int i, tx_bug = 0;
4369
4370                 if (unlikely(skb == NULL)) {
4371                         tg3_tx_recover(tp);
4372                         return;
4373                 }
4374
4375                 pci_unmap_single(tp->pdev,
4376                                  pci_unmap_addr(ri, mapping),
4377                                  skb_headlen(skb),
4378                                  PCI_DMA_TODEVICE);
4379
4380                 ri->skb = NULL;
4381
4382                 sw_idx = NEXT_TX(sw_idx);
4383
4384                 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
4385                         ri = &tnapi->tx_buffers[sw_idx];
4386                         if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4387                                 tx_bug = 1;
4388
4389                         pci_unmap_page(tp->pdev,
4390                                        pci_unmap_addr(ri, mapping),
4391                                        skb_shinfo(skb)->frags[i].size,
4392                                        PCI_DMA_TODEVICE);
4393                         sw_idx = NEXT_TX(sw_idx);
4394                 }
4395
4396                 dev_kfree_skb(skb);
4397
4398                 if (unlikely(tx_bug)) {
4399                         tg3_tx_recover(tp);
4400                         return;
4401                 }
4402         }
4403
4404         tnapi->tx_cons = sw_idx;
4405
4406         /* Need to make the tx_cons update visible to tg3_start_xmit()
4407          * before checking for netif_queue_stopped().  Without the
4408          * memory barrier, there is a small possibility that tg3_start_xmit()
4409          * will miss it and cause the queue to be stopped forever.
4410          */
4411         smp_mb();
4412
4413         if (unlikely(netif_tx_queue_stopped(txq) &&
4414                      (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
4415                 __netif_tx_lock(txq, smp_processor_id());
4416                 if (netif_tx_queue_stopped(txq) &&
4417                     (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
4418                         netif_tx_wake_queue(txq);
4419                 __netif_tx_unlock(txq);
4420         }
4421 }
4422
4423 static void tg3_rx_skb_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
4424 {
4425         if (!ri->skb)
4426                 return;
4427
4428         pci_unmap_single(tp->pdev, pci_unmap_addr(ri, mapping),
4429                          map_sz, PCI_DMA_FROMDEVICE);
4430         dev_kfree_skb_any(ri->skb);
4431         ri->skb = NULL;
4432 }
4433
4434 /* Returns size of skb allocated or < 0 on error.
4435  *
4436  * We only need to fill in the address because the other members
4437  * of the RX descriptor are invariant, see tg3_init_rings.
4438  *
4439  * Note the purposeful assymetry of cpu vs. chip accesses.  For
4440  * posting buffers we only dirty the first cache line of the RX
4441  * descriptor (containing the address).  Whereas for the RX status
4442  * buffers the cpu only reads the last cacheline of the RX descriptor
4443  * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4444  */
4445 static int tg3_alloc_rx_skb(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
4446                             u32 opaque_key, u32 dest_idx_unmasked)
4447 {
4448         struct tg3_rx_buffer_desc *desc;
4449         struct ring_info *map, *src_map;
4450         struct sk_buff *skb;
4451         dma_addr_t mapping;
4452         int skb_size, dest_idx;
4453
4454         src_map = NULL;
4455         switch (opaque_key) {
4456         case RXD_OPAQUE_RING_STD:
4457                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4458                 desc = &tpr->rx_std[dest_idx];
4459                 map = &tpr->rx_std_buffers[dest_idx];
4460                 skb_size = tp->rx_pkt_map_sz;
4461                 break;
4462
4463         case RXD_OPAQUE_RING_JUMBO:
4464                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4465                 desc = &tpr->rx_jmb[dest_idx].std;
4466                 map = &tpr->rx_jmb_buffers[dest_idx];
4467                 skb_size = TG3_RX_JMB_MAP_SZ;
4468                 break;
4469
4470         default:
4471                 return -EINVAL;
4472         }
4473
4474         /* Do not overwrite any of the map or rp information
4475          * until we are sure we can commit to a new buffer.
4476          *
4477          * Callers depend upon this behavior and assume that
4478          * we leave everything unchanged if we fail.
4479          */
4480         skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
4481         if (skb == NULL)
4482                 return -ENOMEM;
4483
4484         skb_reserve(skb, tp->rx_offset);
4485
4486         mapping = pci_map_single(tp->pdev, skb->data, skb_size,
4487                                  PCI_DMA_FROMDEVICE);
4488         if (pci_dma_mapping_error(tp->pdev, mapping)) {
4489                 dev_kfree_skb(skb);
4490                 return -EIO;
4491         }
4492
4493         map->skb = skb;
4494         pci_unmap_addr_set(map, mapping, mapping);
4495
4496         desc->addr_hi = ((u64)mapping >> 32);
4497         desc->addr_lo = ((u64)mapping & 0xffffffff);
4498
4499         return skb_size;
4500 }
4501
4502 /* We only need to move over in the address because the other
4503  * members of the RX descriptor are invariant.  See notes above
4504  * tg3_alloc_rx_skb for full details.
4505  */
4506 static void tg3_recycle_rx(struct tg3_napi *tnapi,
4507                            struct tg3_rx_prodring_set *dpr,
4508                            u32 opaque_key, int src_idx,
4509                            u32 dest_idx_unmasked)
4510 {
4511         struct tg3 *tp = tnapi->tp;
4512         struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4513         struct ring_info *src_map, *dest_map;
4514         int dest_idx;
4515         struct tg3_rx_prodring_set *spr = &tp->prodring[0];
4516
4517         switch (opaque_key) {
4518         case RXD_OPAQUE_RING_STD:
4519                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4520                 dest_desc = &dpr->rx_std[dest_idx];
4521                 dest_map = &dpr->rx_std_buffers[dest_idx];
4522                 src_desc = &spr->rx_std[src_idx];
4523                 src_map = &spr->rx_std_buffers[src_idx];
4524                 break;
4525
4526         case RXD_OPAQUE_RING_JUMBO:
4527                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4528                 dest_desc = &dpr->rx_jmb[dest_idx].std;
4529                 dest_map = &dpr->rx_jmb_buffers[dest_idx];
4530                 src_desc = &spr->rx_jmb[src_idx].std;
4531                 src_map = &spr->rx_jmb_buffers[src_idx];
4532                 break;
4533
4534         default:
4535                 return;
4536         }
4537
4538         dest_map->skb = src_map->skb;
4539         pci_unmap_addr_set(dest_map, mapping,
4540                            pci_unmap_addr(src_map, mapping));
4541         dest_desc->addr_hi = src_desc->addr_hi;
4542         dest_desc->addr_lo = src_desc->addr_lo;
4543         src_map->skb = NULL;
4544 }
4545
4546 /* The RX ring scheme is composed of multiple rings which post fresh
4547  * buffers to the chip, and one special ring the chip uses to report
4548  * status back to the host.
4549  *
4550  * The special ring reports the status of received packets to the
4551  * host.  The chip does not write into the original descriptor the
4552  * RX buffer was obtained from.  The chip simply takes the original
4553  * descriptor as provided by the host, updates the status and length
4554  * field, then writes this into the next status ring entry.
4555  *
4556  * Each ring the host uses to post buffers to the chip is described
4557  * by a TG3_BDINFO entry in the chips SRAM area.  When a packet arrives,
4558  * it is first placed into the on-chip ram.  When the packet's length
4559  * is known, it walks down the TG3_BDINFO entries to select the ring.
4560  * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4561  * which is within the range of the new packet's length is chosen.
4562  *
4563  * The "separate ring for rx status" scheme may sound queer, but it makes
4564  * sense from a cache coherency perspective.  If only the host writes
4565  * to the buffer post rings, and only the chip writes to the rx status
4566  * rings, then cache lines never move beyond shared-modified state.
4567  * If both the host and chip were to write into the same ring, cache line
4568  * eviction could occur since both entities want it in an exclusive state.
4569  */
4570 static int tg3_rx(struct tg3_napi *tnapi, int budget)
4571 {
4572         struct tg3 *tp = tnapi->tp;
4573         u32 work_mask, rx_std_posted = 0;
4574         u32 std_prod_idx, jmb_prod_idx;
4575         u32 sw_idx = tnapi->rx_rcb_ptr;
4576         u16 hw_idx;
4577         int received;
4578         struct tg3_rx_prodring_set *tpr = tnapi->prodring;
4579
4580         hw_idx = *(tnapi->rx_rcb_prod_idx);
4581         /*
4582          * We need to order the read of hw_idx and the read of
4583          * the opaque cookie.
4584          */
4585         rmb();
4586         work_mask = 0;
4587         received = 0;
4588         std_prod_idx = tpr->rx_std_prod_idx;
4589         jmb_prod_idx = tpr->rx_jmb_prod_idx;
4590         while (sw_idx != hw_idx && budget > 0) {
4591                 struct ring_info *ri;
4592                 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
4593                 unsigned int len;
4594                 struct sk_buff *skb;
4595                 dma_addr_t dma_addr;
4596                 u32 opaque_key, desc_idx, *post_ptr;
4597
4598                 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4599                 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4600                 if (opaque_key == RXD_OPAQUE_RING_STD) {
4601                         ri = &tp->prodring[0].rx_std_buffers[desc_idx];
4602                         dma_addr = pci_unmap_addr(ri, mapping);
4603                         skb = ri->skb;
4604                         post_ptr = &std_prod_idx;
4605                         rx_std_posted++;
4606                 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4607                         ri = &tp->prodring[0].rx_jmb_buffers[desc_idx];
4608                         dma_addr = pci_unmap_addr(ri, mapping);
4609                         skb = ri->skb;
4610                         post_ptr = &jmb_prod_idx;
4611                 } else
4612                         goto next_pkt_nopost;
4613
4614                 work_mask |= opaque_key;
4615
4616                 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4617                     (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4618                 drop_it:
4619                         tg3_recycle_rx(tnapi, tpr, opaque_key,
4620                                        desc_idx, *post_ptr);
4621                 drop_it_no_recycle:
4622                         /* Other statistics kept track of by card. */
4623                         tp->net_stats.rx_dropped++;
4624                         goto next_pkt;
4625                 }
4626
4627                 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4628                       ETH_FCS_LEN;
4629
4630                 if (len > RX_COPY_THRESHOLD &&
4631                     tp->rx_offset == NET_IP_ALIGN) {
4632                     /* rx_offset will likely not equal NET_IP_ALIGN
4633                      * if this is a 5701 card running in PCI-X mode
4634                      * [see tg3_get_invariants()]
4635                      */
4636                         int skb_size;
4637
4638                         skb_size = tg3_alloc_rx_skb(tp, tpr, opaque_key,
4639                                                     *post_ptr);
4640                         if (skb_size < 0)
4641                                 goto drop_it;
4642
4643                         ri->skb = NULL;
4644
4645                         pci_unmap_single(tp->pdev, dma_addr, skb_size,
4646                                          PCI_DMA_FROMDEVICE);
4647
4648                         skb_put(skb, len);
4649                 } else {
4650                         struct sk_buff *copy_skb;
4651
4652                         tg3_recycle_rx(tnapi, tpr, opaque_key,
4653                                        desc_idx, *post_ptr);
4654
4655                         copy_skb = netdev_alloc_skb(tp->dev,
4656                                                     len + TG3_RAW_IP_ALIGN);
4657                         if (copy_skb == NULL)
4658                                 goto drop_it_no_recycle;
4659
4660                         skb_reserve(copy_skb, TG3_RAW_IP_ALIGN);
4661                         skb_put(copy_skb, len);
4662                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4663                         skb_copy_from_linear_data(skb, copy_skb->data, len);
4664                         pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4665
4666                         /* We'll reuse the original ring buffer. */
4667                         skb = copy_skb;
4668                 }
4669
4670                 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4671                     (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4672                     (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4673                       >> RXD_TCPCSUM_SHIFT) == 0xffff))
4674                         skb->ip_summed = CHECKSUM_UNNECESSARY;
4675                 else
4676                         skb->ip_summed = CHECKSUM_NONE;
4677
4678                 skb->protocol = eth_type_trans(skb, tp->dev);
4679
4680                 if (len > (tp->dev->mtu + ETH_HLEN) &&
4681                     skb->protocol != htons(ETH_P_8021Q)) {
4682                         dev_kfree_skb(skb);
4683                         goto next_pkt;
4684                 }
4685
4686 #if TG3_VLAN_TAG_USED
4687                 if (tp->vlgrp != NULL &&
4688                     desc->type_flags & RXD_FLAG_VLAN) {
4689                         vlan_gro_receive(&tnapi->napi, tp->vlgrp,
4690                                          desc->err_vlan & RXD_VLAN_MASK, skb);
4691                 } else
4692 #endif
4693                         napi_gro_receive(&tnapi->napi, skb);
4694
4695                 received++;
4696                 budget--;
4697
4698 next_pkt:
4699                 (*post_ptr)++;
4700
4701                 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4702                         u32 idx = *post_ptr % TG3_RX_RING_SIZE;
4703                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, idx);
4704                         work_mask &= ~RXD_OPAQUE_RING_STD;
4705                         rx_std_posted = 0;
4706                 }
4707 next_pkt_nopost:
4708                 sw_idx++;
4709                 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
4710
4711                 /* Refresh hw_idx to see if there is new work */
4712                 if (sw_idx == hw_idx) {
4713                         hw_idx = *(tnapi->rx_rcb_prod_idx);
4714                         rmb();
4715                 }
4716         }
4717
4718         /* ACK the status ring. */
4719         tnapi->rx_rcb_ptr = sw_idx;
4720         tw32_rx_mbox(tnapi->consmbox, sw_idx);
4721
4722         /* Refill RX ring(s). */
4723         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) || tnapi == &tp->napi[1]) {
4724                 if (work_mask & RXD_OPAQUE_RING_STD) {
4725                         tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4726                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4727                                      tpr->rx_std_prod_idx);
4728                 }
4729                 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4730                         tpr->rx_jmb_prod_idx = jmb_prod_idx %
4731                                                TG3_RX_JUMBO_RING_SIZE;
4732                         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
4733                                      tpr->rx_jmb_prod_idx);
4734                 }
4735                 mmiowb();
4736         } else if (work_mask) {
4737                 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
4738                  * updated before the producer indices can be updated.
4739                  */
4740                 smp_wmb();
4741
4742                 tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4743                 tpr->rx_jmb_prod_idx = jmb_prod_idx % TG3_RX_JUMBO_RING_SIZE;
4744
4745                 napi_schedule(&tp->napi[1].napi);
4746         }
4747
4748         return received;
4749 }
4750
4751 static void tg3_poll_link(struct tg3 *tp)
4752 {
4753         /* handle link change and other phy events */
4754         if (!(tp->tg3_flags &
4755               (TG3_FLAG_USE_LINKCHG_REG |
4756                TG3_FLAG_POLL_SERDES))) {
4757                 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
4758
4759                 if (sblk->status & SD_STATUS_LINK_CHG) {
4760                         sblk->status = SD_STATUS_UPDATED |
4761                                        (sblk->status & ~SD_STATUS_LINK_CHG);
4762                         spin_lock(&tp->lock);
4763                         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4764                                 tw32_f(MAC_STATUS,
4765                                      (MAC_STATUS_SYNC_CHANGED |
4766                                       MAC_STATUS_CFG_CHANGED |
4767                                       MAC_STATUS_MI_COMPLETION |
4768                                       MAC_STATUS_LNKSTATE_CHANGED));
4769                                 udelay(40);
4770                         } else
4771                                 tg3_setup_phy(tp, 0);
4772                         spin_unlock(&tp->lock);
4773                 }
4774         }
4775 }
4776
4777 static void tg3_rx_prodring_xfer(struct tg3 *tp,
4778                                  struct tg3_rx_prodring_set *dpr,
4779                                  struct tg3_rx_prodring_set *spr)
4780 {
4781         u32 si, di, cpycnt, src_prod_idx;
4782         int i;
4783
4784         while (1) {
4785                 src_prod_idx = spr->rx_std_prod_idx;
4786
4787                 /* Make sure updates to the rx_std_buffers[] entries and the
4788                  * standard producer index are seen in the correct order.
4789                  */
4790                 smp_rmb();
4791
4792                 if (spr->rx_std_cons_idx == src_prod_idx)
4793                         break;
4794
4795                 if (spr->rx_std_cons_idx < src_prod_idx)
4796                         cpycnt = src_prod_idx - spr->rx_std_cons_idx;
4797                 else
4798                         cpycnt = TG3_RX_RING_SIZE - spr->rx_std_cons_idx;
4799
4800                 cpycnt = min(cpycnt, TG3_RX_RING_SIZE - dpr->rx_std_prod_idx);
4801
4802                 si = spr->rx_std_cons_idx;
4803                 di = dpr->rx_std_prod_idx;
4804
4805                 memcpy(&dpr->rx_std_buffers[di],
4806                        &spr->rx_std_buffers[si],
4807                        cpycnt * sizeof(struct ring_info));
4808
4809                 for (i = 0; i < cpycnt; i++, di++, si++) {
4810                         struct tg3_rx_buffer_desc *sbd, *dbd;
4811                         sbd = &spr->rx_std[si];
4812                         dbd = &dpr->rx_std[di];
4813                         dbd->addr_hi = sbd->addr_hi;
4814                         dbd->addr_lo = sbd->addr_lo;
4815                 }
4816
4817                 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) %
4818                                        TG3_RX_RING_SIZE;
4819                 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) %
4820                                        TG3_RX_RING_SIZE;
4821         }
4822
4823         while (1) {
4824                 src_prod_idx = spr->rx_jmb_prod_idx;
4825
4826                 /* Make sure updates to the rx_jmb_buffers[] entries and
4827                  * the jumbo producer index are seen in the correct order.
4828                  */
4829                 smp_rmb();
4830
4831                 if (spr->rx_jmb_cons_idx == src_prod_idx)
4832                         break;
4833
4834                 if (spr->rx_jmb_cons_idx < src_prod_idx)
4835                         cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
4836                 else
4837                         cpycnt = TG3_RX_JUMBO_RING_SIZE - spr->rx_jmb_cons_idx;
4838
4839                 cpycnt = min(cpycnt,
4840                              TG3_RX_JUMBO_RING_SIZE - dpr->rx_jmb_prod_idx);
4841
4842                 si = spr->rx_jmb_cons_idx;
4843                 di = dpr->rx_jmb_prod_idx;
4844
4845                 memcpy(&dpr->rx_jmb_buffers[di],
4846                        &spr->rx_jmb_buffers[si],
4847                        cpycnt * sizeof(struct ring_info));
4848
4849                 for (i = 0; i < cpycnt; i++, di++, si++) {
4850                         struct tg3_rx_buffer_desc *sbd, *dbd;
4851                         sbd = &spr->rx_jmb[si].std;
4852                         dbd = &dpr->rx_jmb[di].std;
4853                         dbd->addr_hi = sbd->addr_hi;
4854                         dbd->addr_lo = sbd->addr_lo;
4855                 }
4856
4857                 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) %
4858                                        TG3_RX_JUMBO_RING_SIZE;
4859                 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) %
4860                                        TG3_RX_JUMBO_RING_SIZE;
4861         }
4862 }
4863
4864 static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
4865 {
4866         struct tg3 *tp = tnapi->tp;
4867
4868         /* run TX completion thread */
4869         if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
4870                 tg3_tx(tnapi);
4871                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4872                         return work_done;
4873         }
4874
4875         /* run RX thread, within the bounds set by NAPI.
4876          * All RX "locking" is done by ensuring outside
4877          * code synchronizes with tg3->napi.poll()
4878          */
4879         if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
4880                 work_done += tg3_rx(tnapi, budget - work_done);
4881
4882         if ((tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) && tnapi == &tp->napi[1]) {
4883                 int i;
4884                 u32 std_prod_idx = tp->prodring[0].rx_std_prod_idx;
4885                 u32 jmb_prod_idx = tp->prodring[0].rx_jmb_prod_idx;
4886
4887                 for (i = 2; i < tp->irq_cnt; i++)
4888                         tg3_rx_prodring_xfer(tp, tnapi->prodring,
4889                                              tp->napi[i].prodring);
4890
4891                 wmb();
4892
4893                 if (std_prod_idx != tp->prodring[0].rx_std_prod_idx) {
4894                         u32 mbox = TG3_RX_STD_PROD_IDX_REG;
4895                         tw32_rx_mbox(mbox, tp->prodring[0].rx_std_prod_idx);
4896                 }
4897
4898                 if (jmb_prod_idx != tp->prodring[0].rx_jmb_prod_idx) {
4899                         u32 mbox = TG3_RX_JMB_PROD_IDX_REG;
4900                         tw32_rx_mbox(mbox, tp->prodring[0].rx_jmb_prod_idx);
4901                 }
4902
4903                 mmiowb();
4904         }
4905
4906         return work_done;
4907 }
4908
4909 static int tg3_poll_msix(struct napi_struct *napi, int budget)
4910 {
4911         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
4912         struct tg3 *tp = tnapi->tp;
4913         int work_done = 0;
4914         struct tg3_hw_status *sblk = tnapi->hw_status;
4915
4916         while (1) {
4917                 work_done = tg3_poll_work(tnapi, work_done, budget);
4918
4919                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4920                         goto tx_recovery;
4921
4922                 if (unlikely(work_done >= budget))
4923                         break;
4924
4925                 /* tp->last_tag is used in tg3_restart_ints() below
4926                  * to tell the hw how much work has been processed,
4927                  * so we must read it before checking for more work.
4928                  */
4929                 tnapi->last_tag = sblk->status_tag;
4930                 tnapi->last_irq_tag = tnapi->last_tag;
4931                 rmb();
4932
4933                 /* check for RX/TX work to do */
4934                 if (sblk->idx[0].tx_consumer == tnapi->tx_cons &&
4935                     *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr) {
4936                         napi_complete(napi);
4937                         /* Reenable interrupts. */
4938                         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
4939                         mmiowb();
4940                         break;
4941                 }
4942         }
4943
4944         return work_done;
4945
4946 tx_recovery:
4947         /* work_done is guaranteed to be less than budget. */
4948         napi_complete(napi);
4949         schedule_work(&tp->reset_task);
4950         return work_done;
4951 }
4952
4953 static int tg3_poll(struct napi_struct *napi, int budget)
4954 {
4955         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
4956         struct tg3 *tp = tnapi->tp;
4957         int work_done = 0;
4958         struct tg3_hw_status *sblk = tnapi->hw_status;
4959
4960         while (1) {
4961                 tg3_poll_link(tp);
4962
4963                 work_done = tg3_poll_work(tnapi, work_done, budget);
4964
4965                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4966                         goto tx_recovery;
4967
4968                 if (unlikely(work_done >= budget))
4969                         break;
4970
4971                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
4972                         /* tp->last_tag is used in tg3_int_reenable() below
4973                          * to tell the hw how much work has been processed,
4974                          * so we must read it before checking for more work.
4975                          */
4976                         tnapi->last_tag = sblk->status_tag;
4977                         tnapi->last_irq_tag = tnapi->last_tag;
4978                         rmb();
4979                 } else
4980                         sblk->status &= ~SD_STATUS_UPDATED;
4981
4982                 if (likely(!tg3_has_work(tnapi))) {
4983                         napi_complete(napi);
4984                         tg3_int_reenable(tnapi);
4985                         break;
4986                 }
4987         }
4988
4989         return work_done;
4990
4991 tx_recovery:
4992         /* work_done is guaranteed to be less than budget. */
4993         napi_complete(napi);
4994         schedule_work(&tp->reset_task);
4995         return work_done;
4996 }
4997
4998 static void tg3_irq_quiesce(struct tg3 *tp)
4999 {
5000         int i;
5001
5002         BUG_ON(tp->irq_sync);
5003
5004         tp->irq_sync = 1;
5005         smp_mb();
5006
5007         for (i = 0; i < tp->irq_cnt; i++)
5008                 synchronize_irq(tp->napi[i].irq_vec);
5009 }
5010
5011 static inline int tg3_irq_sync(struct tg3 *tp)
5012 {
5013         return tp->irq_sync;
5014 }
5015
5016 /* Fully shutdown all tg3 driver activity elsewhere in the system.
5017  * If irq_sync is non-zero, then the IRQ handler must be synchronized
5018  * with as well.  Most of the time, this is not necessary except when
5019  * shutting down the device.
5020  */
5021 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
5022 {
5023         spin_lock_bh(&tp->lock);
5024         if (irq_sync)
5025                 tg3_irq_quiesce(tp);
5026 }
5027
5028 static inline void tg3_full_unlock(struct tg3 *tp)
5029 {
5030         spin_unlock_bh(&tp->lock);
5031 }
5032
5033 /* One-shot MSI handler - Chip automatically disables interrupt
5034  * after sending MSI so driver doesn't have to do it.
5035  */
5036 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
5037 {
5038         struct tg3_napi *tnapi = dev_id;
5039         struct tg3 *tp = tnapi->tp;
5040
5041         prefetch(tnapi->hw_status);
5042         if (tnapi->rx_rcb)
5043                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5044
5045         if (likely(!tg3_irq_sync(tp)))
5046                 napi_schedule(&tnapi->napi);
5047
5048         return IRQ_HANDLED;
5049 }
5050
5051 /* MSI ISR - No need to check for interrupt sharing and no need to
5052  * flush status block and interrupt mailbox. PCI ordering rules
5053  * guarantee that MSI will arrive after the status block.
5054  */
5055 static irqreturn_t tg3_msi(int irq, void *dev_id)
5056 {
5057         struct tg3_napi *tnapi = dev_id;
5058         struct tg3 *tp = tnapi->tp;
5059
5060         prefetch(tnapi->hw_status);
5061         if (tnapi->rx_rcb)
5062                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5063         /*
5064          * Writing any value to intr-mbox-0 clears PCI INTA# and
5065          * chip-internal interrupt pending events.
5066          * Writing non-zero to intr-mbox-0 additional tells the
5067          * NIC to stop sending us irqs, engaging "in-intr-handler"
5068          * event coalescing.
5069          */
5070         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5071         if (likely(!tg3_irq_sync(tp)))
5072                 napi_schedule(&tnapi->napi);
5073
5074         return IRQ_RETVAL(1);
5075 }
5076
5077 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
5078 {
5079         struct tg3_napi *tnapi = dev_id;
5080         struct tg3 *tp = tnapi->tp;
5081         struct tg3_hw_status *sblk = tnapi->hw_status;
5082         unsigned int handled = 1;
5083
5084         /* In INTx mode, it is possible for the interrupt to arrive at
5085          * the CPU before the status block posted prior to the interrupt.
5086          * Reading the PCI State register will confirm whether the
5087          * interrupt is ours and will flush the status block.
5088          */
5089         if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
5090                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5091                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5092                         handled = 0;
5093                         goto out;
5094                 }
5095         }
5096
5097         /*
5098          * Writing any value to intr-mbox-0 clears PCI INTA# and
5099          * chip-internal interrupt pending events.
5100          * Writing non-zero to intr-mbox-0 additional tells the
5101          * NIC to stop sending us irqs, engaging "in-intr-handler"
5102          * event coalescing.
5103          *
5104          * Flush the mailbox to de-assert the IRQ immediately to prevent
5105          * spurious interrupts.  The flush impacts performance but
5106          * excessive spurious interrupts can be worse in some cases.
5107          */
5108         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5109         if (tg3_irq_sync(tp))
5110                 goto out;
5111         sblk->status &= ~SD_STATUS_UPDATED;
5112         if (likely(tg3_has_work(tnapi))) {
5113                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5114                 napi_schedule(&tnapi->napi);
5115         } else {
5116                 /* No work, shared interrupt perhaps?  re-enable
5117                  * interrupts, and flush that PCI write
5118                  */
5119                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
5120                                0x00000000);
5121         }
5122 out:
5123         return IRQ_RETVAL(handled);
5124 }
5125
5126 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
5127 {
5128         struct tg3_napi *tnapi = dev_id;
5129         struct tg3 *tp = tnapi->tp;
5130         struct tg3_hw_status *sblk = tnapi->hw_status;
5131         unsigned int handled = 1;
5132
5133         /* In INTx mode, it is possible for the interrupt to arrive at
5134          * the CPU before the status block posted prior to the interrupt.
5135          * Reading the PCI State register will confirm whether the
5136          * interrupt is ours and will flush the status block.
5137          */
5138         if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
5139                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5140                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5141                         handled = 0;
5142                         goto out;
5143                 }
5144         }
5145
5146         /*
5147          * writing any value to intr-mbox-0 clears PCI INTA# and
5148          * chip-internal interrupt pending events.
5149          * writing non-zero to intr-mbox-0 additional tells the
5150          * NIC to stop sending us irqs, engaging "in-intr-handler"
5151          * event coalescing.
5152          *
5153          * Flush the mailbox to de-assert the IRQ immediately to prevent
5154          * spurious interrupts.  The flush impacts performance but
5155          * excessive spurious interrupts can be worse in some cases.
5156          */
5157         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5158
5159         /*
5160          * In a shared interrupt configuration, sometimes other devices'
5161          * interrupts will scream.  We record the current status tag here
5162          * so that the above check can report that the screaming interrupts
5163          * are unhandled.  Eventually they will be silenced.
5164          */
5165         tnapi->last_irq_tag = sblk->status_tag;
5166
5167         if (tg3_irq_sync(tp))
5168                 goto out;
5169
5170         prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5171
5172         napi_schedule(&tnapi->napi);
5173
5174 out:
5175         return IRQ_RETVAL(handled);
5176 }
5177
5178 /* ISR for interrupt test */
5179 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
5180 {
5181         struct tg3_napi *tnapi = dev_id;
5182         struct tg3 *tp = tnapi->tp;
5183         struct tg3_hw_status *sblk = tnapi->hw_status;
5184
5185         if ((sblk->status & SD_STATUS_UPDATED) ||
5186             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5187                 tg3_disable_ints(tp);
5188                 return IRQ_RETVAL(1);
5189         }
5190         return IRQ_RETVAL(0);
5191 }
5192
5193 static int tg3_init_hw(struct tg3 *, int);
5194 static int tg3_halt(struct tg3 *, int, int);
5195
5196 /* Restart hardware after configuration changes, self-test, etc.
5197  * Invoked with tp->lock held.
5198  */
5199 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
5200         __releases(tp->lock)
5201         __acquires(tp->lock)
5202 {
5203         int err;
5204
5205         err = tg3_init_hw(tp, reset_phy);
5206         if (err) {
5207                 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
5208                        "aborting.\n", tp->dev->name);
5209                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5210                 tg3_full_unlock(tp);
5211                 del_timer_sync(&tp->timer);
5212                 tp->irq_sync = 0;
5213                 tg3_napi_enable(tp);
5214                 dev_close(tp->dev);
5215                 tg3_full_lock(tp, 0);
5216         }
5217         return err;
5218 }
5219
5220 #ifdef CONFIG_NET_POLL_CONTROLLER
5221 static void tg3_poll_controller(struct net_device *dev)
5222 {
5223         int i;
5224         struct tg3 *tp = netdev_priv(dev);
5225
5226         for (i = 0; i < tp->irq_cnt; i++)
5227                 tg3_interrupt(tp->napi[i].irq_vec, dev);
5228 }
5229 #endif
5230
5231 static void tg3_reset_task(struct work_struct *work)
5232 {
5233         struct tg3 *tp = container_of(work, struct tg3, reset_task);
5234         int err;
5235         unsigned int restart_timer;
5236
5237         tg3_full_lock(tp, 0);
5238
5239         if (!netif_running(tp->dev)) {
5240                 tg3_full_unlock(tp);
5241                 return;
5242         }
5243
5244         tg3_full_unlock(tp);
5245
5246         tg3_phy_stop(tp);
5247
5248         tg3_netif_stop(tp);
5249
5250         tg3_full_lock(tp, 1);
5251
5252         restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
5253         tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
5254
5255         if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
5256                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
5257                 tp->write32_rx_mbox = tg3_write_flush_reg32;
5258                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
5259                 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
5260         }
5261
5262         tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
5263         err = tg3_init_hw(tp, 1);
5264         if (err)
5265                 goto out;
5266
5267         tg3_netif_start(tp);
5268
5269         if (restart_timer)
5270                 mod_timer(&tp->timer, jiffies + 1);
5271
5272 out:
5273         tg3_full_unlock(tp);
5274
5275         if (!err)
5276                 tg3_phy_start(tp);
5277 }
5278
5279 static void tg3_dump_short_state(struct tg3 *tp)
5280 {
5281         printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5282                tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
5283         printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5284                tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
5285 }
5286
5287 static void tg3_tx_timeout(struct net_device *dev)
5288 {
5289         struct tg3 *tp = netdev_priv(dev);
5290
5291         if (netif_msg_tx_err(tp)) {
5292                 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
5293                        dev->name);
5294                 tg3_dump_short_state(tp);
5295         }
5296
5297         schedule_work(&tp->reset_task);
5298 }
5299
5300 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5301 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5302 {
5303         u32 base = (u32) mapping & 0xffffffff;
5304
5305         return ((base > 0xffffdcc0) &&
5306                 (base + len + 8 < base));
5307 }
5308
5309 /* Test for DMA addresses > 40-bit */
5310 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5311                                           int len)
5312 {
5313 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
5314         if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
5315                 return (((u64) mapping + len) > DMA_BIT_MASK(40));
5316         return 0;
5317 #else
5318         return 0;
5319 #endif
5320 }
5321
5322 static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32);
5323
5324 /* Workaround 4GB and 40-bit hardware DMA bugs. */
5325 static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
5326                                        struct sk_buff *skb, u32 last_plus_one,
5327                                        u32 *start, u32 base_flags, u32 mss)
5328 {
5329         struct tg3 *tp = tnapi->tp;
5330         struct sk_buff *new_skb;
5331         dma_addr_t new_addr = 0;
5332         u32 entry = *start;
5333         int i, ret = 0;
5334
5335         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5336                 new_skb = skb_copy(skb, GFP_ATOMIC);
5337         else {
5338                 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5339
5340                 new_skb = skb_copy_expand(skb,
5341                                           skb_headroom(skb) + more_headroom,
5342                                           skb_tailroom(skb), GFP_ATOMIC);
5343         }
5344
5345         if (!new_skb) {
5346                 ret = -1;
5347         } else {
5348                 /* New SKB is guaranteed to be linear. */
5349                 entry = *start;
5350                 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
5351                                           PCI_DMA_TODEVICE);
5352                 /* Make sure the mapping succeeded */
5353                 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
5354                         ret = -1;
5355                         dev_kfree_skb(new_skb);
5356                         new_skb = NULL;
5357
5358                 /* Make sure new skb does not cross any 4G boundaries.
5359                  * Drop the packet if it does.
5360                  */
5361                 } else if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5362                             tg3_4g_overflow_test(new_addr, new_skb->len)) {
5363                         pci_unmap_single(tp->pdev, new_addr, new_skb->len,
5364                                          PCI_DMA_TODEVICE);
5365                         ret = -1;
5366                         dev_kfree_skb(new_skb);
5367                         new_skb = NULL;
5368                 } else {
5369                         tg3_set_txd(tnapi, entry, new_addr, new_skb->len,
5370                                     base_flags, 1 | (mss << 1));
5371                         *start = NEXT_TX(entry);
5372                 }
5373         }
5374
5375         /* Now clean up the sw ring entries. */
5376         i = 0;
5377         while (entry != last_plus_one) {
5378                 int len;
5379
5380                 if (i == 0)
5381                         len = skb_headlen(skb);
5382                 else
5383                         len = skb_shinfo(skb)->frags[i-1].size;
5384
5385                 pci_unmap_single(tp->pdev,
5386                                  pci_unmap_addr(&tnapi->tx_buffers[entry],
5387                                                 mapping),
5388                                  len, PCI_DMA_TODEVICE);
5389                 if (i == 0) {
5390                         tnapi->tx_buffers[entry].skb = new_skb;
5391                         pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5392                                            new_addr);
5393                 } else {
5394                         tnapi->tx_buffers[entry].skb = NULL;
5395                 }
5396                 entry = NEXT_TX(entry);
5397                 i++;
5398         }
5399
5400         dev_kfree_skb(skb);
5401
5402         return ret;
5403 }
5404
5405 static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
5406                         dma_addr_t mapping, int len, u32 flags,
5407                         u32 mss_and_is_end)
5408 {
5409         struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
5410         int is_end = (mss_and_is_end & 0x1);
5411         u32 mss = (mss_and_is_end >> 1);
5412         u32 vlan_tag = 0;
5413
5414         if (is_end)
5415                 flags |= TXD_FLAG_END;
5416         if (flags & TXD_FLAG_VLAN) {
5417                 vlan_tag = flags >> 16;
5418                 flags &= 0xffff;
5419         }
5420         vlan_tag |= (mss << TXD_MSS_SHIFT);
5421
5422         txd->addr_hi = ((u64) mapping >> 32);
5423         txd->addr_lo = ((u64) mapping & 0xffffffff);
5424         txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5425         txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5426 }
5427
5428 /* hard_start_xmit for devices that don't have any bugs and
5429  * support TG3_FLG2_HW_TSO_2 and TG3_FLG2_HW_TSO_3 only.
5430  */
5431 static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5432                                   struct net_device *dev)
5433 {
5434         struct tg3 *tp = netdev_priv(dev);
5435         u32 len, entry, base_flags, mss;
5436         dma_addr_t mapping;
5437         struct tg3_napi *tnapi;
5438         struct netdev_queue *txq;
5439         unsigned int i, last;
5440
5441
5442         txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5443         tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5444         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
5445                 tnapi++;
5446
5447         /* We are running in BH disabled context with netif_tx_lock
5448          * and TX reclaim runs via tp->napi.poll inside of a software
5449          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5450          * no IRQ context deadlocks to worry about either.  Rejoice!
5451          */
5452         if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5453                 if (!netif_tx_queue_stopped(txq)) {
5454                         netif_tx_stop_queue(txq);
5455
5456                         /* This is a hard error, log it. */
5457                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5458                                "queue awake!\n", dev->name);
5459                 }
5460                 return NETDEV_TX_BUSY;
5461         }
5462
5463         entry = tnapi->tx_prod;
5464         base_flags = 0;
5465         mss = 0;
5466         if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5467                 int tcp_opt_len, ip_tcp_len;
5468                 u32 hdrlen;
5469
5470                 if (skb_header_cloned(skb) &&
5471                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5472                         dev_kfree_skb(skb);
5473                         goto out_unlock;
5474                 }
5475
5476                 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
5477                         hdrlen = skb_headlen(skb) - ETH_HLEN;
5478                 else {
5479                         struct iphdr *iph = ip_hdr(skb);
5480
5481                         tcp_opt_len = tcp_optlen(skb);
5482                         ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5483
5484                         iph->check = 0;
5485                         iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
5486                         hdrlen = ip_tcp_len + tcp_opt_len;
5487                 }
5488
5489                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5490                         mss |= (hdrlen & 0xc) << 12;
5491                         if (hdrlen & 0x10)
5492                                 base_flags |= 0x00000010;
5493                         base_flags |= (hdrlen & 0x3e0) << 5;
5494                 } else
5495                         mss |= hdrlen << 9;
5496
5497                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5498                                TXD_FLAG_CPU_POST_DMA);
5499
5500                 tcp_hdr(skb)->check = 0;
5501
5502         }
5503         else if (skb->ip_summed == CHECKSUM_PARTIAL)
5504                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5505 #if TG3_VLAN_TAG_USED
5506         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5507                 base_flags |= (TXD_FLAG_VLAN |
5508                                (vlan_tx_tag_get(skb) << 16));
5509 #endif
5510
5511         len = skb_headlen(skb);
5512
5513         /* Queue skb data, a.k.a. the main skb fragment. */
5514         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5515         if (pci_dma_mapping_error(tp->pdev, mapping)) {
5516                 dev_kfree_skb(skb);
5517                 goto out_unlock;
5518         }
5519
5520         tnapi->tx_buffers[entry].skb = skb;
5521         pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
5522
5523         if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
5524             !mss && skb->len > ETH_DATA_LEN)
5525                 base_flags |= TXD_FLAG_JMB_PKT;
5526
5527         tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5528                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5529
5530         entry = NEXT_TX(entry);
5531
5532         /* Now loop through additional data fragments, and queue them. */
5533         if (skb_shinfo(skb)->nr_frags > 0) {
5534                 last = skb_shinfo(skb)->nr_frags - 1;
5535                 for (i = 0; i <= last; i++) {
5536                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5537
5538                         len = frag->size;
5539                         mapping = pci_map_page(tp->pdev,
5540                                                frag->page,
5541                                                frag->page_offset,
5542                                                len, PCI_DMA_TODEVICE);
5543                         if (pci_dma_mapping_error(tp->pdev, mapping))
5544                                 goto dma_error;
5545
5546                         tnapi->tx_buffers[entry].skb = NULL;
5547                         pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5548                                            mapping);
5549
5550                         tg3_set_txd(tnapi, entry, mapping, len,
5551                                     base_flags, (i == last) | (mss << 1));
5552
5553                         entry = NEXT_TX(entry);
5554                 }
5555         }
5556
5557         /* Packets are ready, update Tx producer idx local and on card. */
5558         tw32_tx_mbox(tnapi->prodmbox, entry);
5559
5560         tnapi->tx_prod = entry;
5561         if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5562                 netif_tx_stop_queue(txq);
5563                 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5564                         netif_tx_wake_queue(txq);
5565         }
5566
5567 out_unlock:
5568         mmiowb();
5569
5570         return NETDEV_TX_OK;
5571
5572 dma_error:
5573         last = i;
5574         entry = tnapi->tx_prod;
5575         tnapi->tx_buffers[entry].skb = NULL;
5576         pci_unmap_single(tp->pdev,
5577                          pci_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5578                          skb_headlen(skb),
5579                          PCI_DMA_TODEVICE);
5580         for (i = 0; i <= last; i++) {
5581                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5582                 entry = NEXT_TX(entry);
5583
5584                 pci_unmap_page(tp->pdev,
5585                                pci_unmap_addr(&tnapi->tx_buffers[entry],
5586                                               mapping),
5587                                frag->size, PCI_DMA_TODEVICE);
5588         }
5589
5590         dev_kfree_skb(skb);
5591         return NETDEV_TX_OK;
5592 }
5593
5594 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *,
5595                                           struct net_device *);
5596
5597 /* Use GSO to workaround a rare TSO bug that may be triggered when the
5598  * TSO header is greater than 80 bytes.
5599  */
5600 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5601 {
5602         struct sk_buff *segs, *nskb;
5603         u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
5604
5605         /* Estimate the number of fragments in the worst case */
5606         if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
5607                 netif_stop_queue(tp->dev);
5608                 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
5609                         return NETDEV_TX_BUSY;
5610
5611                 netif_wake_queue(tp->dev);
5612         }
5613
5614         segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
5615         if (IS_ERR(segs))
5616                 goto tg3_tso_bug_end;
5617
5618         do {
5619                 nskb = segs;
5620                 segs = segs->next;
5621                 nskb->next = NULL;
5622                 tg3_start_xmit_dma_bug(nskb, tp->dev);
5623         } while (segs);
5624
5625 tg3_tso_bug_end:
5626         dev_kfree_skb(skb);
5627
5628         return NETDEV_TX_OK;
5629 }
5630
5631 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5632  * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5633  */
5634 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
5635                                           struct net_device *dev)
5636 {
5637         struct tg3 *tp = netdev_priv(dev);
5638         u32 len, entry, base_flags, mss;
5639         int would_hit_hwbug;
5640         dma_addr_t mapping;
5641         struct tg3_napi *tnapi;
5642         struct netdev_queue *txq;
5643         unsigned int i, last;
5644
5645
5646         txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5647         tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5648         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
5649                 tnapi++;
5650
5651         /* We are running in BH disabled context with netif_tx_lock
5652          * and TX reclaim runs via tp->napi.poll inside of a software
5653          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5654          * no IRQ context deadlocks to worry about either.  Rejoice!
5655          */
5656         if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5657                 if (!netif_tx_queue_stopped(txq)) {
5658                         netif_tx_stop_queue(txq);
5659
5660                         /* This is a hard error, log it. */
5661                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5662                                "queue awake!\n", dev->name);
5663                 }
5664                 return NETDEV_TX_BUSY;
5665         }
5666
5667         entry = tnapi->tx_prod;
5668         base_flags = 0;
5669         if (skb->ip_summed == CHECKSUM_PARTIAL)
5670                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5671
5672         if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5673                 struct iphdr *iph;
5674                 u32 tcp_opt_len, ip_tcp_len, hdr_len;
5675
5676                 if (skb_header_cloned(skb) &&
5677                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5678                         dev_kfree_skb(skb);
5679                         goto out_unlock;
5680                 }
5681
5682                 tcp_opt_len = tcp_optlen(skb);
5683                 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5684
5685                 hdr_len = ip_tcp_len + tcp_opt_len;
5686                 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
5687                              (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
5688                         return (tg3_tso_bug(tp, skb));
5689
5690                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5691                                TXD_FLAG_CPU_POST_DMA);
5692
5693                 iph = ip_hdr(skb);
5694                 iph->check = 0;
5695                 iph->tot_len = htons(mss + hdr_len);
5696                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
5697                         tcp_hdr(skb)->check = 0;
5698                         base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
5699                 } else
5700                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5701                                                                  iph->daddr, 0,
5702                                                                  IPPROTO_TCP,
5703                                                                  0);
5704
5705                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5706                         mss |= (hdr_len & 0xc) << 12;
5707                         if (hdr_len & 0x10)
5708                                 base_flags |= 0x00000010;
5709                         base_flags |= (hdr_len & 0x3e0) << 5;
5710                 } else if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)
5711                         mss |= hdr_len << 9;
5712                 else if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_1) ||
5713                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5714                         if (tcp_opt_len || iph->ihl > 5) {
5715                                 int tsflags;
5716
5717                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5718                                 mss |= (tsflags << 11);
5719                         }
5720                 } else {
5721                         if (tcp_opt_len || iph->ihl > 5) {
5722                                 int tsflags;
5723
5724                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5725                                 base_flags |= tsflags << 12;
5726                         }
5727                 }
5728         }
5729 #if TG3_VLAN_TAG_USED
5730         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5731                 base_flags |= (TXD_FLAG_VLAN |
5732                                (vlan_tx_tag_get(skb) << 16));
5733 #endif
5734
5735         if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
5736             !mss && skb->len > ETH_DATA_LEN)
5737                 base_flags |= TXD_FLAG_JMB_PKT;
5738
5739         len = skb_headlen(skb);
5740
5741         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5742         if (pci_dma_mapping_error(tp->pdev, mapping)) {
5743                 dev_kfree_skb(skb);
5744                 goto out_unlock;
5745         }
5746
5747         tnapi->tx_buffers[entry].skb = skb;
5748         pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
5749
5750         would_hit_hwbug = 0;
5751
5752         if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) && len <= 8)
5753                 would_hit_hwbug = 1;
5754
5755         if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5756             tg3_4g_overflow_test(mapping, len))
5757                 would_hit_hwbug = 1;
5758
5759         if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5760             tg3_40bit_overflow_test(tp, mapping, len))
5761                 would_hit_hwbug = 1;
5762
5763         if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
5764                 would_hit_hwbug = 1;
5765
5766         tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5767                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5768
5769         entry = NEXT_TX(entry);
5770
5771         /* Now loop through additional data fragments, and queue them. */
5772         if (skb_shinfo(skb)->nr_frags > 0) {
5773                 last = skb_shinfo(skb)->nr_frags - 1;
5774                 for (i = 0; i <= last; i++) {
5775                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5776
5777                         len = frag->size;
5778                         mapping = pci_map_page(tp->pdev,
5779                                                frag->page,
5780                                                frag->page_offset,
5781                                                len, PCI_DMA_TODEVICE);
5782
5783                         tnapi->tx_buffers[entry].skb = NULL;
5784                         pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5785                                            mapping);
5786                         if (pci_dma_mapping_error(tp->pdev, mapping))
5787                                 goto dma_error;
5788
5789                         if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) &&
5790                             len <= 8)
5791                                 would_hit_hwbug = 1;
5792
5793                         if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5794                             tg3_4g_overflow_test(mapping, len))
5795                                 would_hit_hwbug = 1;
5796
5797                         if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5798                             tg3_40bit_overflow_test(tp, mapping, len))
5799                                 would_hit_hwbug = 1;
5800
5801                         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5802                                 tg3_set_txd(tnapi, entry, mapping, len,
5803                                             base_flags, (i == last)|(mss << 1));
5804                         else
5805                                 tg3_set_txd(tnapi, entry, mapping, len,
5806                                             base_flags, (i == last));
5807
5808                         entry = NEXT_TX(entry);
5809                 }
5810         }
5811
5812         if (would_hit_hwbug) {
5813                 u32 last_plus_one = entry;
5814                 u32 start;
5815
5816                 start = entry - 1 - skb_shinfo(skb)->nr_frags;
5817                 start &= (TG3_TX_RING_SIZE - 1);
5818
5819                 /* If the workaround fails due to memory/mapping
5820                  * failure, silently drop this packet.
5821                  */
5822                 if (tigon3_dma_hwbug_workaround(tnapi, skb, last_plus_one,
5823                                                 &start, base_flags, mss))
5824                         goto out_unlock;
5825
5826                 entry = start;
5827         }
5828
5829         /* Packets are ready, update Tx producer idx local and on card. */
5830         tw32_tx_mbox(tnapi->prodmbox, entry);
5831
5832         tnapi->tx_prod = entry;
5833         if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5834                 netif_tx_stop_queue(txq);
5835                 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5836                         netif_tx_wake_queue(txq);
5837         }
5838
5839 out_unlock:
5840         mmiowb();
5841
5842         return NETDEV_TX_OK;
5843
5844 dma_error:
5845         last = i;
5846         entry = tnapi->tx_prod;
5847         tnapi->tx_buffers[entry].skb = NULL;
5848         pci_unmap_single(tp->pdev,
5849                          pci_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5850                          skb_headlen(skb),
5851                          PCI_DMA_TODEVICE);
5852         for (i = 0; i <= last; i++) {
5853                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5854                 entry = NEXT_TX(entry);
5855
5856                 pci_unmap_page(tp->pdev,
5857                                pci_unmap_addr(&tnapi->tx_buffers[entry],
5858                                               mapping),
5859                                frag->size, PCI_DMA_TODEVICE);
5860         }
5861
5862         dev_kfree_skb(skb);
5863         return NETDEV_TX_OK;
5864 }
5865
5866 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
5867                                int new_mtu)
5868 {
5869         dev->mtu = new_mtu;
5870
5871         if (new_mtu > ETH_DATA_LEN) {
5872                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
5873                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
5874                         ethtool_op_set_tso(dev, 0);
5875                 }
5876                 else
5877                         tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
5878         } else {
5879                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
5880                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
5881                 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
5882         }
5883 }
5884
5885 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
5886 {
5887         struct tg3 *tp = netdev_priv(dev);
5888         int err;
5889
5890         if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
5891                 return -EINVAL;
5892
5893         if (!netif_running(dev)) {
5894                 /* We'll just catch it later when the
5895                  * device is up'd.
5896                  */
5897                 tg3_set_mtu(dev, tp, new_mtu);
5898                 return 0;
5899         }
5900
5901         tg3_phy_stop(tp);
5902
5903         tg3_netif_stop(tp);
5904
5905         tg3_full_lock(tp, 1);
5906
5907         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5908
5909         tg3_set_mtu(dev, tp, new_mtu);
5910
5911         err = tg3_restart_hw(tp, 0);
5912
5913         if (!err)
5914                 tg3_netif_start(tp);
5915
5916         tg3_full_unlock(tp);
5917
5918         if (!err)
5919                 tg3_phy_start(tp);
5920
5921         return err;
5922 }
5923
5924 static void tg3_rx_prodring_free(struct tg3 *tp,
5925                                  struct tg3_rx_prodring_set *tpr)
5926 {
5927         int i;
5928
5929         if (tpr != &tp->prodring[0]) {
5930                 for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx;
5931                      i = (i + 1) % TG3_RX_RING_SIZE)
5932                         tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
5933                                         tp->rx_pkt_map_sz);
5934
5935                 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
5936                         for (i = tpr->rx_jmb_cons_idx;
5937                              i != tpr->rx_jmb_prod_idx;
5938                              i = (i + 1) % TG3_RX_JUMBO_RING_SIZE) {
5939                                 tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
5940                                                 TG3_RX_JMB_MAP_SZ);
5941                         }
5942                 }
5943
5944                 return;
5945         }
5946
5947         for (i = 0; i < TG3_RX_RING_SIZE; i++)
5948                 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
5949                                 tp->rx_pkt_map_sz);
5950
5951         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
5952                 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++)
5953                         tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
5954                                         TG3_RX_JMB_MAP_SZ);
5955         }
5956 }
5957
5958 /* Initialize tx/rx rings for packet processing.
5959  *
5960  * The chip has been shut down and the driver detached from
5961  * the networking, so no interrupts or new tx packets will
5962  * end up in the driver.  tp->{tx,}lock are held and thus
5963  * we may not sleep.
5964  */
5965 static int tg3_rx_prodring_alloc(struct tg3 *tp,
5966                                  struct tg3_rx_prodring_set *tpr)
5967 {
5968         u32 i, rx_pkt_dma_sz;
5969
5970         tpr->rx_std_cons_idx = 0;
5971         tpr->rx_std_prod_idx = 0;
5972         tpr->rx_jmb_cons_idx = 0;
5973         tpr->rx_jmb_prod_idx = 0;
5974
5975         if (tpr != &tp->prodring[0]) {
5976                 memset(&tpr->rx_std_buffers[0], 0, TG3_RX_STD_BUFF_RING_SIZE);
5977                 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE)
5978                         memset(&tpr->rx_jmb_buffers[0], 0,
5979                                TG3_RX_JMB_BUFF_RING_SIZE);
5980                 goto done;
5981         }
5982
5983         /* Zero out all descriptors. */
5984         memset(tpr->rx_std, 0, TG3_RX_RING_BYTES);
5985
5986         rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
5987         if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
5988             tp->dev->mtu > ETH_DATA_LEN)
5989                 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
5990         tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
5991
5992         /* Initialize invariants of the rings, we only set this
5993          * stuff once.  This works because the card does not
5994          * write into the rx buffer posting rings.
5995          */
5996         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5997                 struct tg3_rx_buffer_desc *rxd;
5998
5999                 rxd = &tpr->rx_std[i];
6000                 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
6001                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
6002                 rxd->opaque = (RXD_OPAQUE_RING_STD |
6003                                (i << RXD_OPAQUE_INDEX_SHIFT));
6004         }
6005
6006         /* Now allocate fresh SKBs for each rx ring. */
6007         for (i = 0; i < tp->rx_pending; i++) {
6008                 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_STD, i) < 0) {
6009                         printk(KERN_WARNING PFX
6010                                "%s: Using a smaller RX standard ring, "
6011                                "only %d out of %d buffers were allocated "
6012                                "successfully.\n",
6013                                tp->dev->name, i, tp->rx_pending);
6014                         if (i == 0)
6015                                 goto initfail;
6016                         tp->rx_pending = i;
6017                         break;
6018                 }
6019         }
6020
6021         if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE))
6022                 goto done;
6023
6024         memset(tpr->rx_jmb, 0, TG3_RX_JUMBO_RING_BYTES);
6025
6026         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
6027                 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
6028                         struct tg3_rx_buffer_desc *rxd;
6029
6030                         rxd = &tpr->rx_jmb[i].std;
6031                         rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
6032                         rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
6033                                 RXD_FLAG_JUMBO;
6034                         rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
6035                                (i << RXD_OPAQUE_INDEX_SHIFT));
6036                 }
6037
6038                 for (i = 0; i < tp->rx_jumbo_pending; i++) {
6039                         if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_JUMBO,
6040                                              i) < 0) {
6041                                 printk(KERN_WARNING PFX
6042                                        "%s: Using a smaller RX jumbo ring, "
6043                                        "only %d out of %d buffers were "
6044                                        "allocated successfully.\n",
6045                                        tp->dev->name, i, tp->rx_jumbo_pending);
6046                                 if (i == 0)
6047                                         goto initfail;
6048                                 tp->rx_jumbo_pending = i;
6049                                 break;
6050                         }
6051                 }
6052         }
6053
6054 done:
6055         return 0;
6056
6057 initfail:
6058         tg3_rx_prodring_free(tp, tpr);
6059         return -ENOMEM;
6060 }
6061
6062 static void tg3_rx_prodring_fini(struct tg3 *tp,
6063                                  struct tg3_rx_prodring_set *tpr)
6064 {
6065         kfree(tpr->rx_std_buffers);
6066         tpr->rx_std_buffers = NULL;
6067         kfree(tpr->rx_jmb_buffers);
6068         tpr->rx_jmb_buffers = NULL;
6069         if (tpr->rx_std) {
6070                 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
6071                                     tpr->rx_std, tpr->rx_std_mapping);
6072                 tpr->rx_std = NULL;
6073         }
6074         if (tpr->rx_jmb) {
6075                 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
6076                                     tpr->rx_jmb, tpr->rx_jmb_mapping);
6077                 tpr->rx_jmb = NULL;
6078         }
6079 }
6080
6081 static int tg3_rx_prodring_init(struct tg3 *tp,
6082                                 struct tg3_rx_prodring_set *tpr)
6083 {
6084         tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE, GFP_KERNEL);
6085         if (!tpr->rx_std_buffers)
6086                 return -ENOMEM;
6087
6088         tpr->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
6089                                            &tpr->rx_std_mapping);
6090         if (!tpr->rx_std)
6091                 goto err_out;
6092
6093         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
6094                 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE,
6095                                               GFP_KERNEL);
6096                 if (!tpr->rx_jmb_buffers)
6097                         goto err_out;
6098
6099                 tpr->rx_jmb = pci_alloc_consistent(tp->pdev,
6100                                                    TG3_RX_JUMBO_RING_BYTES,
6101                                                    &tpr->rx_jmb_mapping);
6102                 if (!tpr->rx_jmb)
6103                         goto err_out;
6104         }
6105
6106         return 0;
6107
6108 err_out:
6109         tg3_rx_prodring_fini(tp, tpr);
6110         return -ENOMEM;
6111 }
6112
6113 /* Free up pending packets in all rx/tx rings.
6114  *
6115  * The chip has been shut down and the driver detached from
6116  * the networking, so no interrupts or new tx packets will
6117  * end up in the driver.  tp->{tx,}lock is not held and we are not
6118  * in an interrupt context and thus may sleep.
6119  */
6120 static void tg3_free_rings(struct tg3 *tp)
6121 {
6122         int i, j;
6123
6124         for (j = 0; j < tp->irq_cnt; j++) {
6125                 struct tg3_napi *tnapi = &tp->napi[j];
6126
6127                 if (!tnapi->tx_buffers)
6128                         continue;
6129
6130                 for (i = 0; i < TG3_TX_RING_SIZE; ) {
6131                         struct ring_info *txp;
6132                         struct sk_buff *skb;
6133                         unsigned int k;
6134
6135                         txp = &tnapi->tx_buffers[i];
6136                         skb = txp->skb;
6137
6138                         if (skb == NULL) {
6139                                 i++;
6140                                 continue;
6141                         }
6142
6143                         pci_unmap_single(tp->pdev,
6144                                          pci_unmap_addr(txp, mapping),
6145                                          skb_headlen(skb),
6146                                          PCI_DMA_TODEVICE);
6147                         txp->skb = NULL;
6148
6149                         i++;
6150
6151                         for (k = 0; k < skb_shinfo(skb)->nr_frags; k++) {
6152                                 txp = &tnapi->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
6153                                 pci_unmap_page(tp->pdev,
6154                                                pci_unmap_addr(txp, mapping),
6155                                                skb_shinfo(skb)->frags[k].size,
6156                                                PCI_DMA_TODEVICE);
6157                                 i++;
6158                         }
6159
6160                         dev_kfree_skb_any(skb);
6161                 }
6162
6163                 if (tp->irq_cnt == 1 || j != tp->irq_cnt - 1)
6164                         tg3_rx_prodring_free(tp, &tp->prodring[j]);
6165         }
6166 }
6167
6168 /* Initialize tx/rx rings for packet processing.
6169  *
6170  * The chip has been shut down and the driver detached from
6171  * the networking, so no interrupts or new tx packets will
6172  * end up in the driver.  tp->{tx,}lock are held and thus
6173  * we may not sleep.
6174  */
6175 static int tg3_init_rings(struct tg3 *tp)
6176 {
6177         int i;
6178
6179         /* Free up all the SKBs. */
6180         tg3_free_rings(tp);
6181
6182         for (i = 0; i < tp->irq_cnt; i++) {
6183                 struct tg3_napi *tnapi = &tp->napi[i];
6184
6185                 tnapi->last_tag = 0;
6186                 tnapi->last_irq_tag = 0;
6187                 tnapi->hw_status->status = 0;
6188                 tnapi->hw_status->status_tag = 0;
6189                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6190
6191                 tnapi->tx_prod = 0;
6192                 tnapi->tx_cons = 0;
6193                 if (tnapi->tx_ring)
6194                         memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
6195
6196                 tnapi->rx_rcb_ptr = 0;
6197                 if (tnapi->rx_rcb)
6198                         memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6199
6200                 if ((tp->irq_cnt == 1 || i != tp->irq_cnt - 1) &&
6201                         tg3_rx_prodring_alloc(tp, &tp->prodring[i]))
6202                         return -ENOMEM;
6203         }
6204
6205         return 0;
6206 }
6207
6208 /*
6209  * Must not be invoked with interrupt sources disabled and
6210  * the hardware shutdown down.
6211  */
6212 static void tg3_free_consistent(struct tg3 *tp)
6213 {
6214         int i;
6215
6216         for (i = 0; i < tp->irq_cnt; i++) {
6217                 struct tg3_napi *tnapi = &tp->napi[i];
6218
6219                 if (tnapi->tx_ring) {
6220                         pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
6221                                 tnapi->tx_ring, tnapi->tx_desc_mapping);
6222                         tnapi->tx_ring = NULL;
6223                 }
6224
6225                 kfree(tnapi->tx_buffers);
6226                 tnapi->tx_buffers = NULL;
6227
6228                 if (tnapi->rx_rcb) {
6229                         pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
6230                                             tnapi->rx_rcb,
6231                                             tnapi->rx_rcb_mapping);
6232                         tnapi->rx_rcb = NULL;
6233                 }
6234
6235                 if (tnapi->hw_status) {
6236                         pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
6237                                             tnapi->hw_status,
6238                                             tnapi->status_mapping);
6239                         tnapi->hw_status = NULL;
6240                 }
6241         }
6242
6243         if (tp->hw_stats) {
6244                 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
6245                                     tp->hw_stats, tp->stats_mapping);
6246                 tp->hw_stats = NULL;
6247         }
6248
6249         for (i = 0; i < (tp->irq_cnt == 1 ? 1 : tp->irq_cnt - 1); i++)
6250                 tg3_rx_prodring_fini(tp, &tp->prodring[i]);
6251 }
6252
6253 /*
6254  * Must not be invoked with interrupt sources disabled and
6255  * the hardware shutdown down.  Can sleep.
6256  */
6257 static int tg3_alloc_consistent(struct tg3 *tp)
6258 {
6259         int i;
6260
6261         for (i = 0; i < (tp->irq_cnt == 1 ? 1 : tp->irq_cnt - 1); i++) {
6262                 if (tg3_rx_prodring_init(tp, &tp->prodring[i]))
6263                         goto err_out;
6264         }
6265
6266         tp->hw_stats = pci_alloc_consistent(tp->pdev,
6267                                             sizeof(struct tg3_hw_stats),
6268                                             &tp->stats_mapping);
6269         if (!tp->hw_stats)
6270                 goto err_out;
6271
6272         memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6273
6274         for (i = 0; i < tp->irq_cnt; i++) {
6275                 struct tg3_napi *tnapi = &tp->napi[i];
6276                 struct tg3_hw_status *sblk;
6277
6278                 tnapi->hw_status = pci_alloc_consistent(tp->pdev,
6279                                                         TG3_HW_STATUS_SIZE,
6280                                                         &tnapi->status_mapping);
6281                 if (!tnapi->hw_status)
6282                         goto err_out;
6283
6284                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6285                 sblk = tnapi->hw_status;
6286
6287                 /* If multivector TSS is enabled, vector 0 does not handle
6288                  * tx interrupts.  Don't allocate any resources for it.
6289                  */
6290                 if ((!i && !(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) ||
6291                     (i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))) {
6292                         tnapi->tx_buffers = kzalloc(sizeof(struct ring_info) *
6293                                                     TG3_TX_RING_SIZE,
6294                                                     GFP_KERNEL);
6295                         if (!tnapi->tx_buffers)
6296                                 goto err_out;
6297
6298                         tnapi->tx_ring = pci_alloc_consistent(tp->pdev,
6299                                                               TG3_TX_RING_BYTES,
6300                                                        &tnapi->tx_desc_mapping);
6301                         if (!tnapi->tx_ring)
6302                                 goto err_out;
6303                 }
6304
6305                 /*
6306                  * When RSS is enabled, the status block format changes
6307                  * slightly.  The "rx_jumbo_consumer", "reserved",
6308                  * and "rx_mini_consumer" members get mapped to the
6309                  * other three rx return ring producer indexes.
6310                  */
6311                 switch (i) {
6312                 default:
6313                         tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
6314                         break;
6315                 case 2:
6316                         tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer;
6317                         break;
6318                 case 3:
6319                         tnapi->rx_rcb_prod_idx = &sblk->reserved;
6320                         break;
6321                 case 4:
6322                         tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer;
6323                         break;
6324                 }
6325
6326                 if (tp->irq_cnt == 1)
6327                         tnapi->prodring = &tp->prodring[0];
6328                 else if (i)
6329                         tnapi->prodring = &tp->prodring[i - 1];
6330
6331                 /*
6332                  * If multivector RSS is enabled, vector 0 does not handle
6333                  * rx or tx interrupts.  Don't allocate any resources for it.
6334                  */
6335                 if (!i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS))
6336                         continue;
6337
6338                 tnapi->rx_rcb = pci_alloc_consistent(tp->pdev,
6339                                                      TG3_RX_RCB_RING_BYTES(tp),
6340                                                      &tnapi->rx_rcb_mapping);
6341                 if (!tnapi->rx_rcb)
6342                         goto err_out;
6343
6344                 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6345         }
6346
6347         return 0;
6348
6349 err_out:
6350         tg3_free_consistent(tp);
6351         return -ENOMEM;
6352 }
6353
6354 #define MAX_WAIT_CNT 1000
6355
6356 /* To stop a block, clear the enable bit and poll till it
6357  * clears.  tp->lock is held.
6358  */
6359 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
6360 {
6361         unsigned int i;
6362         u32 val;
6363
6364         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6365                 switch (ofs) {
6366                 case RCVLSC_MODE:
6367                 case DMAC_MODE:
6368                 case MBFREE_MODE:
6369                 case BUFMGR_MODE:
6370                 case MEMARB_MODE:
6371                         /* We can't enable/disable these bits of the
6372                          * 5705/5750, just say success.
6373                          */
6374                         return 0;
6375
6376                 default:
6377                         break;
6378                 }
6379         }
6380
6381         val = tr32(ofs);
6382         val &= ~enable_bit;
6383         tw32_f(ofs, val);
6384
6385         for (i = 0; i < MAX_WAIT_CNT; i++) {
6386                 udelay(100);
6387                 val = tr32(ofs);
6388                 if ((val & enable_bit) == 0)
6389                         break;
6390         }
6391
6392         if (i == MAX_WAIT_CNT && !silent) {
6393                 printk(KERN_ERR PFX "tg3_stop_block timed out, "
6394                        "ofs=%lx enable_bit=%x\n",
6395                        ofs, enable_bit);
6396                 return -ENODEV;
6397         }
6398
6399         return 0;
6400 }
6401
6402 /* tp->lock is held. */
6403 static int tg3_abort_hw(struct tg3 *tp, int silent)
6404 {
6405         int i, err;
6406
6407         tg3_disable_ints(tp);
6408
6409         tp->rx_mode &= ~RX_MODE_ENABLE;
6410         tw32_f(MAC_RX_MODE, tp->rx_mode);
6411         udelay(10);
6412
6413         err  = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
6414         err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
6415         err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
6416         err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
6417         err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
6418         err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
6419
6420         err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
6421         err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
6422         err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
6423         err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
6424         err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
6425         err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
6426         err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
6427
6428         tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
6429         tw32_f(MAC_MODE, tp->mac_mode);
6430         udelay(40);
6431
6432         tp->tx_mode &= ~TX_MODE_ENABLE;
6433         tw32_f(MAC_TX_MODE, tp->tx_mode);
6434
6435         for (i = 0; i < MAX_WAIT_CNT; i++) {
6436                 udelay(100);
6437                 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
6438                         break;
6439         }
6440         if (i >= MAX_WAIT_CNT) {
6441                 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
6442                        "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
6443                        tp->dev->name, tr32(MAC_TX_MODE));
6444                 err |= -ENODEV;
6445         }
6446
6447         err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
6448         err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
6449         err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
6450
6451         tw32(FTQ_RESET, 0xffffffff);
6452         tw32(FTQ_RESET, 0x00000000);
6453
6454         err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
6455         err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
6456
6457         for (i = 0; i < tp->irq_cnt; i++) {
6458                 struct tg3_napi *tnapi = &tp->napi[i];
6459                 if (tnapi->hw_status)
6460                         memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6461         }
6462         if (tp->hw_stats)
6463                 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6464
6465         return err;
6466 }
6467
6468 static void tg3_ape_send_event(struct tg3 *tp, u32 event)
6469 {
6470         int i;
6471         u32 apedata;
6472
6473         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
6474         if (apedata != APE_SEG_SIG_MAGIC)
6475                 return;
6476
6477         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
6478         if (!(apedata & APE_FW_STATUS_READY))
6479                 return;
6480
6481         /* Wait for up to 1 millisecond for APE to service previous event. */
6482         for (i = 0; i < 10; i++) {
6483                 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
6484                         return;
6485
6486                 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
6487
6488                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6489                         tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
6490                                         event | APE_EVENT_STATUS_EVENT_PENDING);
6491
6492                 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
6493
6494                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6495                         break;
6496
6497                 udelay(100);
6498         }
6499
6500         if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6501                 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
6502 }
6503
6504 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
6505 {
6506         u32 event;
6507         u32 apedata;
6508
6509         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
6510                 return;
6511
6512         switch (kind) {
6513                 case RESET_KIND_INIT:
6514                         tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
6515                                         APE_HOST_SEG_SIG_MAGIC);
6516                         tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
6517                                         APE_HOST_SEG_LEN_MAGIC);
6518                         apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
6519                         tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
6520                         tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
6521                                         APE_HOST_DRIVER_ID_MAGIC);
6522                         tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
6523                                         APE_HOST_BEHAV_NO_PHYLOCK);
6524
6525                         event = APE_EVENT_STATUS_STATE_START;
6526                         break;
6527                 case RESET_KIND_SHUTDOWN:
6528                         /* With the interface we are currently using,
6529                          * APE does not track driver state.  Wiping
6530                          * out the HOST SEGMENT SIGNATURE forces
6531                          * the APE to assume OS absent status.
6532                          */
6533                         tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
6534
6535                         event = APE_EVENT_STATUS_STATE_UNLOAD;
6536                         break;
6537                 case RESET_KIND_SUSPEND:
6538                         event = APE_EVENT_STATUS_STATE_SUSPEND;
6539                         break;
6540                 default:
6541                         return;
6542         }
6543
6544         event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
6545
6546         tg3_ape_send_event(tp, event);
6547 }
6548
6549 /* tp->lock is held. */
6550 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
6551 {
6552         tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
6553                       NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
6554
6555         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6556                 switch (kind) {
6557                 case RESET_KIND_INIT:
6558                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6559                                       DRV_STATE_START);
6560                         break;
6561
6562                 case RESET_KIND_SHUTDOWN:
6563                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6564                                       DRV_STATE_UNLOAD);
6565                         break;
6566
6567                 case RESET_KIND_SUSPEND:
6568                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6569                                       DRV_STATE_SUSPEND);
6570                         break;
6571
6572                 default:
6573                         break;
6574                 }
6575         }
6576
6577         if (kind == RESET_KIND_INIT ||
6578             kind == RESET_KIND_SUSPEND)
6579                 tg3_ape_driver_state_change(tp, kind);
6580 }
6581
6582 /* tp->lock is held. */
6583 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
6584 {
6585         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6586                 switch (kind) {
6587                 case RESET_KIND_INIT:
6588                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6589                                       DRV_STATE_START_DONE);
6590                         break;
6591
6592                 case RESET_KIND_SHUTDOWN:
6593                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6594                                       DRV_STATE_UNLOAD_DONE);
6595                         break;
6596
6597                 default:
6598                         break;
6599                 }
6600         }
6601
6602         if (kind == RESET_KIND_SHUTDOWN)
6603                 tg3_ape_driver_state_change(tp, kind);
6604 }
6605
6606 /* tp->lock is held. */
6607 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
6608 {
6609         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6610                 switch (kind) {
6611                 case RESET_KIND_INIT:
6612                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6613                                       DRV_STATE_START);
6614                         break;
6615
6616                 case RESET_KIND_SHUTDOWN:
6617                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6618                                       DRV_STATE_UNLOAD);
6619                         break;
6620
6621                 case RESET_KIND_SUSPEND:
6622                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6623                                       DRV_STATE_SUSPEND);
6624                         break;
6625
6626                 default:
6627                         break;
6628                 }
6629         }
6630 }
6631
6632 static int tg3_poll_fw(struct tg3 *tp)
6633 {
6634         int i;
6635         u32 val;
6636
6637         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6638                 /* Wait up to 20ms for init done. */
6639                 for (i = 0; i < 200; i++) {
6640                         if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
6641                                 return 0;
6642                         udelay(100);
6643                 }
6644                 return -ENODEV;
6645         }
6646
6647         /* Wait for firmware initialization to complete. */
6648         for (i = 0; i < 100000; i++) {
6649                 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
6650                 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
6651                         break;
6652                 udelay(10);
6653         }
6654
6655         /* Chip might not be fitted with firmware.  Some Sun onboard
6656          * parts are configured like that.  So don't signal the timeout
6657          * of the above loop as an error, but do report the lack of
6658          * running firmware once.
6659          */
6660         if (i >= 100000 &&
6661             !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
6662                 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
6663
6664                 printk(KERN_INFO PFX "%s: No firmware running.\n",
6665                        tp->dev->name);
6666         }
6667
6668         return 0;
6669 }
6670
6671 /* Save PCI command register before chip reset */
6672 static void tg3_save_pci_state(struct tg3 *tp)
6673 {
6674         pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
6675 }
6676
6677 /* Restore PCI state after chip reset */
6678 static void tg3_restore_pci_state(struct tg3 *tp)
6679 {
6680         u32 val;
6681
6682         /* Re-enable indirect register accesses. */
6683         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
6684                                tp->misc_host_ctrl);
6685
6686         /* Set MAX PCI retry to zero. */
6687         val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
6688         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6689             (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
6690                 val |= PCISTATE_RETRY_SAME_DMA;
6691         /* Allow reads and writes to the APE register and memory space. */
6692         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
6693                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6694                        PCISTATE_ALLOW_APE_SHMEM_WR;
6695         pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
6696
6697         pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
6698
6699         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
6700                 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6701                         pcie_set_readrq(tp->pdev, 4096);
6702                 else {
6703                         pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
6704                                               tp->pci_cacheline_sz);
6705                         pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
6706                                               tp->pci_lat_timer);
6707                 }
6708         }
6709
6710         /* Make sure PCI-X relaxed ordering bit is clear. */
6711         if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
6712                 u16 pcix_cmd;
6713
6714                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6715                                      &pcix_cmd);
6716                 pcix_cmd &= ~PCI_X_CMD_ERO;
6717                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6718                                       pcix_cmd);
6719         }
6720
6721         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
6722
6723                 /* Chip reset on 5780 will reset MSI enable bit,
6724                  * so need to restore it.
6725                  */
6726                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6727                         u16 ctrl;
6728
6729                         pci_read_config_word(tp->pdev,
6730                                              tp->msi_cap + PCI_MSI_FLAGS,
6731                                              &ctrl);
6732                         pci_write_config_word(tp->pdev,
6733                                               tp->msi_cap + PCI_MSI_FLAGS,
6734                                               ctrl | PCI_MSI_FLAGS_ENABLE);
6735                         val = tr32(MSGINT_MODE);
6736                         tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
6737                 }
6738         }
6739 }
6740
6741 static void tg3_stop_fw(struct tg3 *);
6742
6743 /* tp->lock is held. */
6744 static int tg3_chip_reset(struct tg3 *tp)
6745 {
6746         u32 val;
6747         void (*write_op)(struct tg3 *, u32, u32);
6748         int i, err;
6749
6750         tg3_nvram_lock(tp);
6751
6752         tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
6753
6754         /* No matching tg3_nvram_unlock() after this because
6755          * chip reset below will undo the nvram lock.
6756          */
6757         tp->nvram_lock_cnt = 0;
6758
6759         /* GRC_MISC_CFG core clock reset will clear the memory
6760          * enable bit in PCI register 4 and the MSI enable bit
6761          * on some chips, so we save relevant registers here.
6762          */
6763         tg3_save_pci_state(tp);
6764
6765         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
6766             (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
6767                 tw32(GRC_FASTBOOT_PC, 0);
6768
6769         /*
6770          * We must avoid the readl() that normally takes place.
6771          * It locks machines, causes machine checks, and other
6772          * fun things.  So, temporarily disable the 5701
6773          * hardware workaround, while we do the reset.
6774          */
6775         write_op = tp->write32;
6776         if (write_op == tg3_write_flush_reg32)
6777                 tp->write32 = tg3_write32;
6778
6779         /* Prevent the irq handler from reading or writing PCI registers
6780          * during chip reset when the memory enable bit in the PCI command
6781          * register may be cleared.  The chip does not generate interrupt
6782          * at this time, but the irq handler may still be called due to irq
6783          * sharing or irqpoll.
6784          */
6785         tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
6786         for (i = 0; i < tp->irq_cnt; i++) {
6787                 struct tg3_napi *tnapi = &tp->napi[i];
6788                 if (tnapi->hw_status) {
6789                         tnapi->hw_status->status = 0;
6790                         tnapi->hw_status->status_tag = 0;
6791                 }
6792                 tnapi->last_tag = 0;
6793                 tnapi->last_irq_tag = 0;
6794         }
6795         smp_mb();
6796
6797         for (i = 0; i < tp->irq_cnt; i++)
6798                 synchronize_irq(tp->napi[i].irq_vec);
6799
6800         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6801                 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
6802                 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
6803         }
6804
6805         /* do the reset */
6806         val = GRC_MISC_CFG_CORECLK_RESET;
6807
6808         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
6809                 if (tr32(0x7e2c) == 0x60) {
6810                         tw32(0x7e2c, 0x20);
6811                 }
6812                 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6813                         tw32(GRC_MISC_CFG, (1 << 29));
6814                         val |= (1 << 29);
6815                 }
6816         }
6817
6818         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6819                 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
6820                 tw32(GRC_VCPU_EXT_CTRL,
6821                      tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
6822         }
6823
6824         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6825                 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
6826         tw32(GRC_MISC_CFG, val);
6827
6828         /* restore 5701 hardware bug workaround write method */
6829         tp->write32 = write_op;
6830
6831         /* Unfortunately, we have to delay before the PCI read back.
6832          * Some 575X chips even will not respond to a PCI cfg access
6833          * when the reset command is given to the chip.
6834          *
6835          * How do these hardware designers expect things to work
6836          * properly if the PCI write is posted for a long period
6837          * of time?  It is always necessary to have some method by
6838          * which a register read back can occur to push the write
6839          * out which does the reset.
6840          *
6841          * For most tg3 variants the trick below was working.
6842          * Ho hum...
6843          */
6844         udelay(120);
6845
6846         /* Flush PCI posted writes.  The normal MMIO registers
6847          * are inaccessible at this time so this is the only
6848          * way to make this reliably (actually, this is no longer
6849          * the case, see above).  I tried to use indirect
6850          * register read/write but this upset some 5701 variants.
6851          */
6852         pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
6853
6854         udelay(120);
6855
6856         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
6857                 u16 val16;
6858
6859                 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
6860                         int i;
6861                         u32 cfg_val;
6862
6863                         /* Wait for link training to complete.  */
6864                         for (i = 0; i < 5000; i++)
6865                                 udelay(100);
6866
6867                         pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
6868                         pci_write_config_dword(tp->pdev, 0xc4,
6869                                                cfg_val | (1 << 15));
6870                 }
6871
6872                 /* Clear the "no snoop" and "relaxed ordering" bits. */
6873                 pci_read_config_word(tp->pdev,
6874                                      tp->pcie_cap + PCI_EXP_DEVCTL,
6875                                      &val16);
6876                 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
6877                            PCI_EXP_DEVCTL_NOSNOOP_EN);
6878                 /*
6879                  * Older PCIe devices only support the 128 byte
6880                  * MPS setting.  Enforce the restriction.
6881                  */
6882                 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
6883                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784))
6884                         val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
6885                 pci_write_config_word(tp->pdev,
6886                                       tp->pcie_cap + PCI_EXP_DEVCTL,
6887                                       val16);
6888
6889                 pcie_set_readrq(tp->pdev, 4096);
6890
6891                 /* Clear error status */
6892                 pci_write_config_word(tp->pdev,
6893                                       tp->pcie_cap + PCI_EXP_DEVSTA,
6894                                       PCI_EXP_DEVSTA_CED |
6895                                       PCI_EXP_DEVSTA_NFED |
6896                                       PCI_EXP_DEVSTA_FED |
6897                                       PCI_EXP_DEVSTA_URD);
6898         }
6899
6900         tg3_restore_pci_state(tp);
6901
6902         tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
6903
6904         val = 0;
6905         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
6906                 val = tr32(MEMARB_MODE);
6907         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
6908
6909         if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
6910                 tg3_stop_fw(tp);
6911                 tw32(0x5000, 0x400);
6912         }
6913
6914         tw32(GRC_MODE, tp->grc_mode);
6915
6916         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
6917                 val = tr32(0xc4);
6918
6919                 tw32(0xc4, val | (1 << 15));
6920         }
6921
6922         if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
6923             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6924                 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
6925                 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
6926                         tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
6927                 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6928         }
6929
6930         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6931                 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
6932                 tw32_f(MAC_MODE, tp->mac_mode);
6933         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
6934                 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
6935                 tw32_f(MAC_MODE, tp->mac_mode);
6936         } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
6937                 tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
6938                 if (tp->mac_mode & MAC_MODE_APE_TX_EN)
6939                         tp->mac_mode |= MAC_MODE_TDE_ENABLE;
6940                 tw32_f(MAC_MODE, tp->mac_mode);
6941         } else
6942                 tw32_f(MAC_MODE, 0);
6943         udelay(40);
6944
6945         tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
6946
6947         err = tg3_poll_fw(tp);
6948         if (err)
6949                 return err;
6950
6951         tg3_mdio_start(tp);
6952
6953         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6954                 u8 phy_addr;
6955
6956                 phy_addr = tp->phy_addr;
6957                 tp->phy_addr = TG3_PHY_PCIE_ADDR;
6958
6959                 tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR,
6960                              TG3_PCIEPHY_TXB_BLK << TG3_PCIEPHY_BLOCK_SHIFT);
6961                 val = TG3_PCIEPHY_TX0CTRL1_TXOCM | TG3_PCIEPHY_TX0CTRL1_RDCTL |
6962                       TG3_PCIEPHY_TX0CTRL1_TXCMV | TG3_PCIEPHY_TX0CTRL1_TKSEL |
6963                       TG3_PCIEPHY_TX0CTRL1_NB_EN;
6964                 tg3_writephy(tp, TG3_PCIEPHY_TX0CTRL1, val);
6965                 udelay(10);
6966
6967                 tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR,
6968                              TG3_PCIEPHY_XGXS_BLK1 << TG3_PCIEPHY_BLOCK_SHIFT);
6969                 val = TG3_PCIEPHY_PWRMGMT4_LOWPWR_EN |
6970                       TG3_PCIEPHY_PWRMGMT4_L1PLLPD_EN;
6971                 tg3_writephy(tp, TG3_PCIEPHY_PWRMGMT4, val);
6972                 udelay(10);
6973
6974                 tp->phy_addr = phy_addr;
6975         }
6976
6977         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
6978             tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
6979             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
6980             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
6981             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765) {
6982                 val = tr32(0x7c00);
6983
6984                 tw32(0x7c00, val | (1 << 25));
6985         }
6986
6987         /* Reprobe ASF enable state.  */
6988         tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
6989         tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
6990         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
6991         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
6992                 u32 nic_cfg;
6993
6994                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
6995                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
6996                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
6997                         tp->last_event_jiffies = jiffies;
6998                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
6999                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
7000                 }
7001         }
7002
7003         return 0;
7004 }
7005
7006 /* tp->lock is held. */
7007 static void tg3_stop_fw(struct tg3 *tp)
7008 {
7009         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
7010            !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7011                 /* Wait for RX cpu to ACK the previous event. */
7012                 tg3_wait_for_event_ack(tp);
7013
7014                 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
7015
7016                 tg3_generate_fw_event(tp);
7017
7018                 /* Wait for RX cpu to ACK this event. */
7019                 tg3_wait_for_event_ack(tp);
7020         }
7021 }
7022
7023 /* tp->lock is held. */
7024 static int tg3_halt(struct tg3 *tp, int kind, int silent)
7025 {
7026         int err;
7027
7028         tg3_stop_fw(tp);
7029
7030         tg3_write_sig_pre_reset(tp, kind);
7031
7032         tg3_abort_hw(tp, silent);
7033         err = tg3_chip_reset(tp);
7034
7035         __tg3_set_mac_addr(tp, 0);
7036
7037         tg3_write_sig_legacy(tp, kind);
7038         tg3_write_sig_post_reset(tp, kind);
7039
7040         if (err)
7041                 return err;
7042
7043         return 0;
7044 }
7045
7046 #define RX_CPU_SCRATCH_BASE     0x30000
7047 #define RX_CPU_SCRATCH_SIZE     0x04000
7048 #define TX_CPU_SCRATCH_BASE     0x34000
7049 #define TX_CPU_SCRATCH_SIZE     0x04000
7050
7051 /* tp->lock is held. */
7052 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
7053 {
7054         int i;
7055
7056         BUG_ON(offset == TX_CPU_BASE &&
7057             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
7058
7059         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7060                 u32 val = tr32(GRC_VCPU_EXT_CTRL);
7061
7062                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
7063                 return 0;
7064         }
7065         if (offset == RX_CPU_BASE) {
7066                 for (i = 0; i < 10000; i++) {
7067                         tw32(offset + CPU_STATE, 0xffffffff);
7068                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
7069                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7070                                 break;
7071                 }
7072
7073                 tw32(offset + CPU_STATE, 0xffffffff);
7074                 tw32_f(offset + CPU_MODE,  CPU_MODE_HALT);
7075                 udelay(10);
7076         } else {
7077                 for (i = 0; i < 10000; i++) {
7078                         tw32(offset + CPU_STATE, 0xffffffff);
7079                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
7080                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7081                                 break;
7082                 }
7083         }
7084
7085         if (i >= 10000) {
7086                 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
7087                        "and %s CPU\n",
7088                        tp->dev->name,
7089                        (offset == RX_CPU_BASE ? "RX" : "TX"));
7090                 return -ENODEV;
7091         }
7092
7093         /* Clear firmware's nvram arbitration. */
7094         if (tp->tg3_flags & TG3_FLAG_NVRAM)
7095                 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
7096         return 0;
7097 }
7098
7099 struct fw_info {
7100         unsigned int fw_base;
7101         unsigned int fw_len;
7102         const __be32 *fw_data;
7103 };
7104
7105 /* tp->lock is held. */
7106 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
7107                                  int cpu_scratch_size, struct fw_info *info)
7108 {
7109         int err, lock_err, i;
7110         void (*write_op)(struct tg3 *, u32, u32);
7111
7112         if (cpu_base == TX_CPU_BASE &&
7113             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7114                 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
7115                        "TX cpu firmware on %s which is 5705.\n",
7116                        tp->dev->name);
7117                 return -EINVAL;
7118         }
7119
7120         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7121                 write_op = tg3_write_mem;
7122         else
7123                 write_op = tg3_write_indirect_reg32;
7124
7125         /* It is possible that bootcode is still loading at this point.
7126          * Get the nvram lock first before halting the cpu.
7127          */
7128         lock_err = tg3_nvram_lock(tp);
7129         err = tg3_halt_cpu(tp, cpu_base);
7130         if (!lock_err)
7131                 tg3_nvram_unlock(tp);
7132         if (err)
7133                 goto out;
7134
7135         for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
7136                 write_op(tp, cpu_scratch_base + i, 0);
7137         tw32(cpu_base + CPU_STATE, 0xffffffff);
7138         tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
7139         for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
7140                 write_op(tp, (cpu_scratch_base +
7141                               (info->fw_base & 0xffff) +
7142                               (i * sizeof(u32))),
7143                               be32_to_cpu(info->fw_data[i]));
7144
7145         err = 0;
7146
7147 out:
7148         return err;
7149 }
7150
7151 /* tp->lock is held. */
7152 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
7153 {
7154         struct fw_info info;
7155         const __be32 *fw_data;
7156         int err, i;
7157
7158         fw_data = (void *)tp->fw->data;
7159
7160         /* Firmware blob starts with version numbers, followed by
7161            start address and length. We are setting complete length.
7162            length = end_address_of_bss - start_address_of_text.
7163            Remainder is the blob to be loaded contiguously
7164            from start address. */
7165
7166         info.fw_base = be32_to_cpu(fw_data[1]);
7167         info.fw_len = tp->fw->size - 12;
7168         info.fw_data = &fw_data[3];
7169
7170         err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
7171                                     RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
7172                                     &info);
7173         if (err)
7174                 return err;
7175
7176         err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
7177                                     TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
7178                                     &info);
7179         if (err)
7180                 return err;
7181
7182         /* Now startup only the RX cpu. */
7183         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7184         tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
7185
7186         for (i = 0; i < 5; i++) {
7187                 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
7188                         break;
7189                 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7190                 tw32(RX_CPU_BASE + CPU_MODE,  CPU_MODE_HALT);
7191                 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
7192                 udelay(1000);
7193         }
7194         if (i >= 5) {
7195                 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
7196                        "to set RX CPU PC, is %08x should be %08x\n",
7197                        tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
7198                        info.fw_base);
7199                 return -ENODEV;
7200         }
7201         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7202         tw32_f(RX_CPU_BASE + CPU_MODE,  0x00000000);
7203
7204         return 0;
7205 }
7206
7207 /* 5705 needs a special version of the TSO firmware.  */
7208
7209 /* tp->lock is held. */
7210 static int tg3_load_tso_firmware(struct tg3 *tp)
7211 {
7212         struct fw_info info;
7213         const __be32 *fw_data;
7214         unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
7215         int err, i;
7216
7217         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7218                 return 0;
7219
7220         fw_data = (void *)tp->fw->data;
7221
7222         /* Firmware blob starts with version numbers, followed by
7223            start address and length. We are setting complete length.
7224            length = end_address_of_bss - start_address_of_text.
7225            Remainder is the blob to be loaded contiguously
7226            from start address. */
7227
7228         info.fw_base = be32_to_cpu(fw_data[1]);
7229         cpu_scratch_size = tp->fw_len;
7230         info.fw_len = tp->fw->size - 12;
7231         info.fw_data = &fw_data[3];
7232
7233         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7234                 cpu_base = RX_CPU_BASE;
7235                 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
7236         } else {
7237                 cpu_base = TX_CPU_BASE;
7238                 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
7239                 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
7240         }
7241
7242         err = tg3_load_firmware_cpu(tp, cpu_base,
7243                                     cpu_scratch_base, cpu_scratch_size,
7244                                     &info);
7245         if (err)
7246                 return err;
7247
7248         /* Now startup the cpu. */
7249         tw32(cpu_base + CPU_STATE, 0xffffffff);
7250         tw32_f(cpu_base + CPU_PC, info.fw_base);
7251
7252         for (i = 0; i < 5; i++) {
7253                 if (tr32(cpu_base + CPU_PC) == info.fw_base)
7254                         break;
7255                 tw32(cpu_base + CPU_STATE, 0xffffffff);
7256                 tw32(cpu_base + CPU_MODE,  CPU_MODE_HALT);
7257                 tw32_f(cpu_base + CPU_PC, info.fw_base);
7258                 udelay(1000);
7259         }
7260         if (i >= 5) {
7261                 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
7262                        "to set CPU PC, is %08x should be %08x\n",
7263                        tp->dev->name, tr32(cpu_base + CPU_PC),
7264                        info.fw_base);
7265                 return -ENODEV;
7266         }
7267         tw32(cpu_base + CPU_STATE, 0xffffffff);
7268         tw32_f(cpu_base + CPU_MODE,  0x00000000);
7269         return 0;
7270 }
7271
7272
7273 static int tg3_set_mac_addr(struct net_device *dev, void *p)
7274 {
7275         struct tg3 *tp = netdev_priv(dev);
7276         struct sockaddr *addr = p;
7277         int err = 0, skip_mac_1 = 0;
7278
7279         if (!is_valid_ether_addr(addr->sa_data))
7280                 return -EINVAL;
7281
7282         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7283
7284         if (!netif_running(dev))
7285                 return 0;
7286
7287         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
7288                 u32 addr0_high, addr0_low, addr1_high, addr1_low;
7289
7290                 addr0_high = tr32(MAC_ADDR_0_HIGH);
7291                 addr0_low = tr32(MAC_ADDR_0_LOW);
7292                 addr1_high = tr32(MAC_ADDR_1_HIGH);
7293                 addr1_low = tr32(MAC_ADDR_1_LOW);
7294
7295                 /* Skip MAC addr 1 if ASF is using it. */
7296                 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
7297                     !(addr1_high == 0 && addr1_low == 0))
7298                         skip_mac_1 = 1;
7299         }
7300         spin_lock_bh(&tp->lock);
7301         __tg3_set_mac_addr(tp, skip_mac_1);
7302         spin_unlock_bh(&tp->lock);
7303
7304         return err;
7305 }
7306
7307 /* tp->lock is held. */
7308 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
7309                            dma_addr_t mapping, u32 maxlen_flags,
7310                            u32 nic_addr)
7311 {
7312         tg3_write_mem(tp,
7313                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
7314                       ((u64) mapping >> 32));
7315         tg3_write_mem(tp,
7316                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
7317                       ((u64) mapping & 0xffffffff));
7318         tg3_write_mem(tp,
7319                       (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
7320                        maxlen_flags);
7321
7322         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7323                 tg3_write_mem(tp,
7324                               (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
7325                               nic_addr);
7326 }
7327
7328 static void __tg3_set_rx_mode(struct net_device *);
7329 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
7330 {
7331         int i;
7332
7333         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) {
7334                 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
7335                 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
7336                 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
7337         } else {
7338                 tw32(HOSTCC_TXCOL_TICKS, 0);
7339                 tw32(HOSTCC_TXMAX_FRAMES, 0);
7340                 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
7341         }
7342
7343         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
7344                 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
7345                 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
7346                 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
7347         } else {
7348                 tw32(HOSTCC_RXCOL_TICKS, 0);
7349                 tw32(HOSTCC_RXMAX_FRAMES, 0);
7350                 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
7351         }
7352
7353         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7354                 u32 val = ec->stats_block_coalesce_usecs;
7355
7356                 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
7357                 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
7358
7359                 if (!netif_carrier_ok(tp->dev))
7360                         val = 0;
7361
7362                 tw32(HOSTCC_STAT_COAL_TICKS, val);
7363         }
7364
7365         for (i = 0; i < tp->irq_cnt - 1; i++) {
7366                 u32 reg;
7367
7368                 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
7369                 tw32(reg, ec->rx_coalesce_usecs);
7370                 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
7371                 tw32(reg, ec->rx_max_coalesced_frames);
7372                 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
7373                 tw32(reg, ec->rx_max_coalesced_frames_irq);
7374
7375                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7376                         reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
7377                         tw32(reg, ec->tx_coalesce_usecs);
7378                         reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
7379                         tw32(reg, ec->tx_max_coalesced_frames);
7380                         reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
7381                         tw32(reg, ec->tx_max_coalesced_frames_irq);
7382                 }
7383         }
7384
7385         for (; i < tp->irq_max - 1; i++) {
7386                 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
7387                 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
7388                 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7389
7390                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7391                         tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
7392                         tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
7393                         tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7394                 }
7395         }
7396 }
7397
7398 /* tp->lock is held. */
7399 static void tg3_rings_reset(struct tg3 *tp)
7400 {
7401         int i;
7402         u32 stblk, txrcb, rxrcb, limit;
7403         struct tg3_napi *tnapi = &tp->napi[0];
7404
7405         /* Disable all transmit rings but the first. */
7406         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7407                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
7408         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7409                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
7410         else
7411                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7412
7413         for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7414              txrcb < limit; txrcb += TG3_BDINFO_SIZE)
7415                 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
7416                               BDINFO_FLAGS_DISABLED);
7417
7418
7419         /* Disable all receive return rings but the first. */
7420         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
7421                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
7422         else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7423                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
7424         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
7425                  GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7426                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
7427         else
7428                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7429
7430         for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7431              rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
7432                 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
7433                               BDINFO_FLAGS_DISABLED);
7434
7435         /* Disable interrupts */
7436         tw32_mailbox_f(tp->napi[0].int_mbox, 1);
7437
7438         /* Zero mailbox registers. */
7439         if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) {
7440                 for (i = 1; i < TG3_IRQ_MAX_VECS; i++) {
7441                         tp->napi[i].tx_prod = 0;
7442                         tp->napi[i].tx_cons = 0;
7443                         tw32_mailbox(tp->napi[i].prodmbox, 0);
7444                         tw32_rx_mbox(tp->napi[i].consmbox, 0);
7445                         tw32_mailbox_f(tp->napi[i].int_mbox, 1);
7446                 }
7447         } else {
7448                 tp->napi[0].tx_prod = 0;
7449                 tp->napi[0].tx_cons = 0;
7450                 tw32_mailbox(tp->napi[0].prodmbox, 0);
7451                 tw32_rx_mbox(tp->napi[0].consmbox, 0);
7452         }
7453
7454         /* Make sure the NIC-based send BD rings are disabled. */
7455         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7456                 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
7457                 for (i = 0; i < 16; i++)
7458                         tw32_tx_mbox(mbox + i * 8, 0);
7459         }
7460
7461         txrcb = NIC_SRAM_SEND_RCB;
7462         rxrcb = NIC_SRAM_RCV_RET_RCB;
7463
7464         /* Clear status block in ram. */
7465         memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7466
7467         /* Set status block DMA address */
7468         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7469              ((u64) tnapi->status_mapping >> 32));
7470         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7471              ((u64) tnapi->status_mapping & 0xffffffff));
7472
7473         if (tnapi->tx_ring) {
7474                 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7475                                (TG3_TX_RING_SIZE <<
7476                                 BDINFO_FLAGS_MAXLEN_SHIFT),
7477                                NIC_SRAM_TX_BUFFER_DESC);
7478                 txrcb += TG3_BDINFO_SIZE;
7479         }
7480
7481         if (tnapi->rx_rcb) {
7482                 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7483                                (TG3_RX_RCB_RING_SIZE(tp) <<
7484                                 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7485                 rxrcb += TG3_BDINFO_SIZE;
7486         }
7487
7488         stblk = HOSTCC_STATBLCK_RING1;
7489
7490         for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
7491                 u64 mapping = (u64)tnapi->status_mapping;
7492                 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
7493                 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
7494
7495                 /* Clear status block in ram. */
7496                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7497
7498                 if (tnapi->tx_ring) {
7499                         tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7500                                        (TG3_TX_RING_SIZE <<
7501                                         BDINFO_FLAGS_MAXLEN_SHIFT),
7502                                        NIC_SRAM_TX_BUFFER_DESC);
7503                         txrcb += TG3_BDINFO_SIZE;
7504                 }
7505
7506                 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7507                                (TG3_RX_RCB_RING_SIZE(tp) <<
7508                                 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7509
7510                 stblk += 8;
7511                 rxrcb += TG3_BDINFO_SIZE;
7512         }
7513 }
7514
7515 /* tp->lock is held. */
7516 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
7517 {
7518         u32 val, rdmac_mode;
7519         int i, err, limit;
7520         struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
7521
7522         tg3_disable_ints(tp);
7523
7524         tg3_stop_fw(tp);
7525
7526         tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
7527
7528         if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
7529                 tg3_abort_hw(tp, 1);
7530         }
7531
7532         if (reset_phy &&
7533             !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB))
7534                 tg3_phy_reset(tp);
7535
7536         err = tg3_chip_reset(tp);
7537         if (err)
7538                 return err;
7539
7540         tg3_write_sig_legacy(tp, RESET_KIND_INIT);
7541
7542         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
7543                 val = tr32(TG3_CPMU_CTRL);
7544                 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
7545                 tw32(TG3_CPMU_CTRL, val);
7546
7547                 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7548                 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7549                 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7550                 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7551
7552                 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
7553                 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
7554                 val |= CPMU_LNK_AWARE_MACCLK_6_25;
7555                 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
7556
7557                 val = tr32(TG3_CPMU_HST_ACC);
7558                 val &= ~CPMU_HST_ACC_MACCLK_MASK;
7559                 val |= CPMU_HST_ACC_MACCLK_6_25;
7560                 tw32(TG3_CPMU_HST_ACC, val);
7561         }
7562
7563         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7564                 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
7565                 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
7566                        PCIE_PWR_MGMT_L1_THRESH_4MS;
7567                 tw32(PCIE_PWR_MGMT_THRESH, val);
7568
7569                 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
7570                 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
7571
7572                 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
7573
7574                 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
7575                 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
7576         }
7577
7578         if (tp->tg3_flags3 & TG3_FLG3_L1PLLPD_EN) {
7579                 u32 grc_mode = tr32(GRC_MODE);
7580
7581                 /* Access the lower 1K of PL PCIE block registers. */
7582                 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
7583                 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
7584
7585                 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1);
7586                 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1,
7587                      val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN);
7588
7589                 tw32(GRC_MODE, grc_mode);
7590         }
7591
7592         /* This works around an issue with Athlon chipsets on
7593          * B3 tigon3 silicon.  This bit has no effect on any
7594          * other revision.  But do not set this on PCI Express
7595          * chips and don't even touch the clocks if the CPMU is present.
7596          */
7597         if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
7598                 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
7599                         tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
7600                 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7601         }
7602
7603         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
7604             (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
7605                 val = tr32(TG3PCI_PCISTATE);
7606                 val |= PCISTATE_RETRY_SAME_DMA;
7607                 tw32(TG3PCI_PCISTATE, val);
7608         }
7609
7610         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7611                 /* Allow reads and writes to the
7612                  * APE register and memory space.
7613                  */
7614                 val = tr32(TG3PCI_PCISTATE);
7615                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
7616                        PCISTATE_ALLOW_APE_SHMEM_WR;
7617                 tw32(TG3PCI_PCISTATE, val);
7618         }
7619
7620         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
7621                 /* Enable some hw fixes.  */
7622                 val = tr32(TG3PCI_MSI_DATA);
7623                 val |= (1 << 26) | (1 << 28) | (1 << 29);
7624                 tw32(TG3PCI_MSI_DATA, val);
7625         }
7626
7627         /* Descriptor ring init may make accesses to the
7628          * NIC SRAM area to setup the TX descriptors, so we
7629          * can only do this after the hardware has been
7630          * successfully reset.
7631          */
7632         err = tg3_init_rings(tp);
7633         if (err)
7634                 return err;
7635
7636         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7637             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
7638                 val = tr32(TG3PCI_DMA_RW_CTRL) &
7639                       ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
7640                 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
7641         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
7642                    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
7643                 /* This value is determined during the probe time DMA
7644                  * engine test, tg3_test_dma.
7645                  */
7646                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
7647         }
7648
7649         tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
7650                           GRC_MODE_4X_NIC_SEND_RINGS |
7651                           GRC_MODE_NO_TX_PHDR_CSUM |
7652                           GRC_MODE_NO_RX_PHDR_CSUM);
7653         tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
7654
7655         /* Pseudo-header checksum is done by hardware logic and not
7656          * the offload processers, so make the chip do the pseudo-
7657          * header checksums on receive.  For transmit it is more
7658          * convenient to do the pseudo-header checksum in software
7659          * as Linux does that on transmit for us in all cases.
7660          */
7661         tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
7662
7663         tw32(GRC_MODE,
7664              tp->grc_mode |
7665              (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
7666
7667         /* Setup the timer prescalar register.  Clock is always 66Mhz. */
7668         val = tr32(GRC_MISC_CFG);
7669         val &= ~0xff;
7670         val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
7671         tw32(GRC_MISC_CFG, val);
7672
7673         /* Initialize MBUF/DESC pool. */
7674         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7675                 /* Do nothing.  */
7676         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
7677                 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
7678                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
7679                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
7680                 else
7681                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
7682                 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
7683                 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
7684         }
7685         else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7686                 int fw_len;
7687
7688                 fw_len = tp->fw_len;
7689                 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
7690                 tw32(BUFMGR_MB_POOL_ADDR,
7691                      NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
7692                 tw32(BUFMGR_MB_POOL_SIZE,
7693                      NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
7694         }
7695
7696         if (tp->dev->mtu <= ETH_DATA_LEN) {
7697                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7698                      tp->bufmgr_config.mbuf_read_dma_low_water);
7699                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7700                      tp->bufmgr_config.mbuf_mac_rx_low_water);
7701                 tw32(BUFMGR_MB_HIGH_WATER,
7702                      tp->bufmgr_config.mbuf_high_water);
7703         } else {
7704                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7705                      tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
7706                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7707                      tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
7708                 tw32(BUFMGR_MB_HIGH_WATER,
7709                      tp->bufmgr_config.mbuf_high_water_jumbo);
7710         }
7711         tw32(BUFMGR_DMA_LOW_WATER,
7712              tp->bufmgr_config.dma_low_water);
7713         tw32(BUFMGR_DMA_HIGH_WATER,
7714              tp->bufmgr_config.dma_high_water);
7715
7716         tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
7717         for (i = 0; i < 2000; i++) {
7718                 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
7719                         break;
7720                 udelay(10);
7721         }
7722         if (i >= 2000) {
7723                 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
7724                        tp->dev->name);
7725                 return -ENODEV;
7726         }
7727
7728         /* Setup replenish threshold. */
7729         val = tp->rx_pending / 8;
7730         if (val == 0)
7731                 val = 1;
7732         else if (val > tp->rx_std_max_post)
7733                 val = tp->rx_std_max_post;
7734         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7735                 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
7736                         tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
7737
7738                 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
7739                         val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
7740         }
7741
7742         tw32(RCVBDI_STD_THRESH, val);
7743
7744         /* Initialize TG3_BDINFO's at:
7745          *  RCVDBDI_STD_BD:     standard eth size rx ring
7746          *  RCVDBDI_JUMBO_BD:   jumbo frame rx ring
7747          *  RCVDBDI_MINI_BD:    small frame rx ring (??? does not work)
7748          *
7749          * like so:
7750          *  TG3_BDINFO_HOST_ADDR:       high/low parts of DMA address of ring
7751          *  TG3_BDINFO_MAXLEN_FLAGS:    (rx max buffer size << 16) |
7752          *                              ring attribute flags
7753          *  TG3_BDINFO_NIC_ADDR:        location of descriptors in nic SRAM
7754          *
7755          * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
7756          * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
7757          *
7758          * The size of each ring is fixed in the firmware, but the location is
7759          * configurable.
7760          */
7761         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7762              ((u64) tpr->rx_std_mapping >> 32));
7763         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7764              ((u64) tpr->rx_std_mapping & 0xffffffff));
7765         if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
7766                 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
7767                      NIC_SRAM_RX_BUFFER_DESC);
7768
7769         /* Disable the mini ring */
7770         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7771                 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
7772                      BDINFO_FLAGS_DISABLED);
7773
7774         /* Program the jumbo buffer descriptor ring control
7775          * blocks on those devices that have them.
7776          */
7777         if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
7778             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
7779                 /* Setup replenish threshold. */
7780                 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
7781
7782                 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
7783                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7784                              ((u64) tpr->rx_jmb_mapping >> 32));
7785                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7786                              ((u64) tpr->rx_jmb_mapping & 0xffffffff));
7787                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7788                              (RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT) |
7789                              BDINFO_FLAGS_USE_EXT_RECV);
7790                         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717)
7791                                 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
7792                                      NIC_SRAM_RX_JUMBO_BUFFER_DESC);
7793                 } else {
7794                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7795                              BDINFO_FLAGS_DISABLED);
7796                 }
7797
7798                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7799                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7800                         val = (RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT) |
7801                               (RX_STD_MAX_SIZE << 2);
7802                 else
7803                         val = RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT;
7804         } else
7805                 val = RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT;
7806
7807         tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
7808
7809         tpr->rx_std_prod_idx = tp->rx_pending;
7810         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);
7811
7812         tpr->rx_jmb_prod_idx = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
7813                           tp->rx_jumbo_pending : 0;
7814         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
7815
7816         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7817             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
7818                 tw32(STD_REPLENISH_LWM, 32);
7819                 tw32(JMB_REPLENISH_LWM, 16);
7820         }
7821
7822         tg3_rings_reset(tp);
7823
7824         /* Initialize MAC address and backoff seed. */
7825         __tg3_set_mac_addr(tp, 0);
7826
7827         /* MTU + ethernet header + FCS + optional VLAN tag */
7828         tw32(MAC_RX_MTU_SIZE,
7829              tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
7830
7831         /* The slot time is changed by tg3_setup_phy if we
7832          * run at gigabit with half duplex.
7833          */
7834         tw32(MAC_TX_LENGTHS,
7835              (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
7836              (6 << TX_LENGTHS_IPG_SHIFT) |
7837              (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
7838
7839         /* Receive rules. */
7840         tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
7841         tw32(RCVLPC_CONFIG, 0x0181);
7842
7843         /* Calculate RDMAC_MODE setting early, we need it to determine
7844          * the RCVLPC_STATE_ENABLE mask.
7845          */
7846         rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
7847                       RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
7848                       RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
7849                       RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
7850                       RDMAC_MODE_LNGREAD_ENAB);
7851
7852         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
7853             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7854             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7855                 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
7856                               RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
7857                               RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
7858
7859         /* If statement applies to 5705 and 5750 PCI devices only */
7860         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7861              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7862             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
7863                 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
7864                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7865                         rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
7866                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7867                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
7868                         rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7869                 }
7870         }
7871
7872         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
7873                 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7874
7875         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7876                 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
7877
7878         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
7879             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7880             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7881                 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
7882
7883         /* Receive/send statistics. */
7884         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7885                 val = tr32(RCVLPC_STATS_ENABLE);
7886                 val &= ~RCVLPC_STATSENAB_DACK_FIX;
7887                 tw32(RCVLPC_STATS_ENABLE, val);
7888         } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
7889                    (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
7890                 val = tr32(RCVLPC_STATS_ENABLE);
7891                 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
7892                 tw32(RCVLPC_STATS_ENABLE, val);
7893         } else {
7894                 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
7895         }
7896         tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
7897         tw32(SNDDATAI_STATSENAB, 0xffffff);
7898         tw32(SNDDATAI_STATSCTRL,
7899              (SNDDATAI_SCTRL_ENABLE |
7900               SNDDATAI_SCTRL_FASTUPD));
7901
7902         /* Setup host coalescing engine. */
7903         tw32(HOSTCC_MODE, 0);
7904         for (i = 0; i < 2000; i++) {
7905                 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
7906                         break;
7907                 udelay(10);
7908         }
7909
7910         __tg3_set_coalesce(tp, &tp->coal);
7911
7912         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7913                 /* Status/statistics block address.  See tg3_timer,
7914                  * the tg3_periodic_fetch_stats call there, and
7915                  * tg3_get_stats to see how this works for 5705/5750 chips.
7916                  */
7917                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7918                      ((u64) tp->stats_mapping >> 32));
7919                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7920                      ((u64) tp->stats_mapping & 0xffffffff));
7921                 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
7922
7923                 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
7924
7925                 /* Clear statistics and status block memory areas */
7926                 for (i = NIC_SRAM_STATS_BLK;
7927                      i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
7928                      i += sizeof(u32)) {
7929                         tg3_write_mem(tp, i, 0);
7930                         udelay(40);
7931                 }
7932         }
7933
7934         tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
7935
7936         tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
7937         tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
7938         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7939                 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
7940
7941         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
7942                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
7943                 /* reset to prevent losing 1st rx packet intermittently */
7944                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7945                 udelay(10);
7946         }
7947
7948         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7949                 tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
7950         else
7951                 tp->mac_mode = 0;
7952         tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
7953                 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
7954         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7955             !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7956             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
7957                 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
7958         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
7959         udelay(40);
7960
7961         /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
7962          * If TG3_FLG2_IS_NIC is zero, we should read the
7963          * register to preserve the GPIO settings for LOMs. The GPIOs,
7964          * whether used as inputs or outputs, are set by boot code after
7965          * reset.
7966          */
7967         if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
7968                 u32 gpio_mask;
7969
7970                 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
7971                             GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
7972                             GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
7973
7974                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
7975                         gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
7976                                      GRC_LCLCTRL_GPIO_OUTPUT3;
7977
7978                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
7979                         gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
7980
7981                 tp->grc_local_ctrl &= ~gpio_mask;
7982                 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
7983
7984                 /* GPIO1 must be driven high for eeprom write protect */
7985                 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
7986                         tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
7987                                                GRC_LCLCTRL_GPIO_OUTPUT1);
7988         }
7989         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7990         udelay(100);
7991
7992         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX) {
7993                 val = tr32(MSGINT_MODE);
7994                 val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE;
7995                 tw32(MSGINT_MODE, val);
7996         }
7997
7998         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7999                 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
8000                 udelay(40);
8001         }
8002
8003         val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
8004                WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
8005                WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
8006                WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
8007                WDMAC_MODE_LNGREAD_ENAB);
8008
8009         /* If statement applies to 5705 and 5750 PCI devices only */
8010         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
8011              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
8012             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
8013                 if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
8014                     (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
8015                      tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
8016                         /* nothing */
8017                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
8018                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
8019                            !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
8020                         val |= WDMAC_MODE_RX_ACCEL;
8021                 }
8022         }
8023
8024         /* Enable host coalescing bug fix */
8025         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
8026                 val |= WDMAC_MODE_STATUS_TAG_FIX;
8027
8028         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
8029                 val |= WDMAC_MODE_BURST_ALL_DATA;
8030
8031         tw32_f(WDMAC_MODE, val);
8032         udelay(40);
8033
8034         if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
8035                 u16 pcix_cmd;
8036
8037                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8038                                      &pcix_cmd);
8039                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
8040                         pcix_cmd &= ~PCI_X_CMD_MAX_READ;
8041                         pcix_cmd |= PCI_X_CMD_READ_2K;
8042                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
8043                         pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
8044                         pcix_cmd |= PCI_X_CMD_READ_2K;
8045                 }
8046                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8047                                       pcix_cmd);
8048         }
8049
8050         tw32_f(RDMAC_MODE, rdmac_mode);
8051         udelay(40);
8052
8053         tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
8054         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8055                 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
8056
8057         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
8058                 tw32(SNDDATAC_MODE,
8059                      SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
8060         else
8061                 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
8062
8063         tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
8064         tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
8065         tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
8066         tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
8067         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
8068                 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
8069         val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
8070         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
8071                 val |= SNDBDI_MODE_MULTI_TXQ_EN;
8072         tw32(SNDBDI_MODE, val);
8073         tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
8074
8075         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8076                 err = tg3_load_5701_a0_firmware_fix(tp);
8077                 if (err)
8078                         return err;
8079         }
8080
8081         if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
8082                 err = tg3_load_tso_firmware(tp);
8083                 if (err)
8084                         return err;
8085         }
8086
8087         tp->tx_mode = TX_MODE_ENABLE;
8088         tw32_f(MAC_TX_MODE, tp->tx_mode);
8089         udelay(100);
8090
8091         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) {
8092                 u32 reg = MAC_RSS_INDIR_TBL_0;
8093                 u8 *ent = (u8 *)&val;
8094
8095                 /* Setup the indirection table */
8096                 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
8097                         int idx = i % sizeof(val);
8098
8099                         ent[idx] = i % (tp->irq_cnt - 1);
8100                         if (idx == sizeof(val) - 1) {
8101                                 tw32(reg, val);
8102                                 reg += 4;
8103                         }
8104                 }
8105
8106                 /* Setup the "secret" hash key. */
8107                 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
8108                 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
8109                 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
8110                 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
8111                 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
8112                 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
8113                 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
8114                 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
8115                 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
8116                 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
8117         }
8118
8119         tp->rx_mode = RX_MODE_ENABLE;
8120         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
8121                 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
8122
8123         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)
8124                 tp->rx_mode |= RX_MODE_RSS_ENABLE |
8125                                RX_MODE_RSS_ITBL_HASH_BITS_7 |
8126                                RX_MODE_RSS_IPV6_HASH_EN |
8127                                RX_MODE_RSS_TCP_IPV6_HASH_EN |
8128                                RX_MODE_RSS_IPV4_HASH_EN |
8129                                RX_MODE_RSS_TCP_IPV4_HASH_EN;
8130
8131         tw32_f(MAC_RX_MODE, tp->rx_mode);
8132         udelay(10);
8133
8134         tw32(MAC_LED_CTRL, tp->led_ctrl);
8135
8136         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
8137         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
8138                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8139                 udelay(10);
8140         }
8141         tw32_f(MAC_RX_MODE, tp->rx_mode);
8142         udelay(10);
8143
8144         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
8145                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
8146                         !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
8147                         /* Set drive transmission level to 1.2V  */
8148                         /* only if the signal pre-emphasis bit is not set  */
8149                         val = tr32(MAC_SERDES_CFG);
8150                         val &= 0xfffff000;
8151                         val |= 0x880;
8152                         tw32(MAC_SERDES_CFG, val);
8153                 }
8154                 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
8155                         tw32(MAC_SERDES_CFG, 0x616000);
8156         }
8157
8158         /* Prevent chip from dropping frames when flow control
8159          * is enabled.
8160          */
8161         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
8162                 val = 1;
8163         else
8164                 val = 2;
8165         tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val);
8166
8167         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
8168             (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
8169                 /* Use hardware link auto-negotiation */
8170                 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
8171         }
8172
8173         if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
8174             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
8175                 u32 tmp;
8176
8177                 tmp = tr32(SERDES_RX_CTRL);
8178                 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
8179                 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
8180                 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
8181                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8182         }
8183
8184         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
8185                 if (tp->link_config.phy_is_low_power) {
8186                         tp->link_config.phy_is_low_power = 0;
8187                         tp->link_config.speed = tp->link_config.orig_speed;
8188                         tp->link_config.duplex = tp->link_config.orig_duplex;
8189                         tp->link_config.autoneg = tp->link_config.orig_autoneg;
8190                 }
8191
8192                 err = tg3_setup_phy(tp, 0);
8193                 if (err)
8194                         return err;
8195
8196                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8197                     !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)) {
8198                         u32 tmp;
8199
8200                         /* Clear CRC stats. */
8201                         if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
8202                                 tg3_writephy(tp, MII_TG3_TEST1,
8203                                              tmp | MII_TG3_TEST1_CRC_EN);
8204                                 tg3_readphy(tp, 0x14, &tmp);
8205                         }
8206                 }
8207         }
8208
8209         __tg3_set_rx_mode(tp->dev);
8210
8211         /* Initialize receive rules. */
8212         tw32(MAC_RCV_RULE_0,  0xc2000000 & RCV_RULE_DISABLE_MASK);
8213         tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
8214         tw32(MAC_RCV_RULE_1,  0x86000004 & RCV_RULE_DISABLE_MASK);
8215         tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
8216
8217         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
8218             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
8219                 limit = 8;
8220         else
8221                 limit = 16;
8222         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
8223                 limit -= 4;
8224         switch (limit) {
8225         case 16:
8226                 tw32(MAC_RCV_RULE_15,  0); tw32(MAC_RCV_VALUE_15,  0);
8227         case 15:
8228                 tw32(MAC_RCV_RULE_14,  0); tw32(MAC_RCV_VALUE_14,  0);
8229         case 14:
8230                 tw32(MAC_RCV_RULE_13,  0); tw32(MAC_RCV_VALUE_13,  0);
8231         case 13:
8232                 tw32(MAC_RCV_RULE_12,  0); tw32(MAC_RCV_VALUE_12,  0);
8233         case 12:
8234                 tw32(MAC_RCV_RULE_11,  0); tw32(MAC_RCV_VALUE_11,  0);
8235         case 11:
8236                 tw32(MAC_RCV_RULE_10,  0); tw32(MAC_RCV_VALUE_10,  0);
8237         case 10:
8238                 tw32(MAC_RCV_RULE_9,  0); tw32(MAC_RCV_VALUE_9,  0);
8239         case 9:
8240                 tw32(MAC_RCV_RULE_8,  0); tw32(MAC_RCV_VALUE_8,  0);
8241         case 8:
8242                 tw32(MAC_RCV_RULE_7,  0); tw32(MAC_RCV_VALUE_7,  0);
8243         case 7:
8244                 tw32(MAC_RCV_RULE_6,  0); tw32(MAC_RCV_VALUE_6,  0);
8245         case 6:
8246                 tw32(MAC_RCV_RULE_5,  0); tw32(MAC_RCV_VALUE_5,  0);
8247         case 5:
8248                 tw32(MAC_RCV_RULE_4,  0); tw32(MAC_RCV_VALUE_4,  0);
8249         case 4:
8250                 /* tw32(MAC_RCV_RULE_3,  0); tw32(MAC_RCV_VALUE_3,  0); */
8251         case 3:
8252                 /* tw32(MAC_RCV_RULE_2,  0); tw32(MAC_RCV_VALUE_2,  0); */
8253         case 2:
8254         case 1:
8255
8256         default:
8257                 break;
8258         }
8259
8260         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
8261                 /* Write our heartbeat update interval to APE. */
8262                 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
8263                                 APE_HOST_HEARTBEAT_INT_DISABLE);
8264
8265         tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
8266
8267         return 0;
8268 }
8269
8270 /* Called at device open time to get the chip ready for
8271  * packet processing.  Invoked with tp->lock held.
8272  */
8273 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
8274 {
8275         tg3_switch_clocks(tp);
8276
8277         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
8278
8279         return tg3_reset_hw(tp, reset_phy);
8280 }
8281
8282 #define TG3_STAT_ADD32(PSTAT, REG) \
8283 do {    u32 __val = tr32(REG); \
8284         (PSTAT)->low += __val; \
8285         if ((PSTAT)->low < __val) \
8286                 (PSTAT)->high += 1; \
8287 } while (0)
8288
8289 static void tg3_periodic_fetch_stats(struct tg3 *tp)
8290 {
8291         struct tg3_hw_stats *sp = tp->hw_stats;
8292
8293         if (!netif_carrier_ok(tp->dev))
8294                 return;
8295
8296         TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
8297         TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
8298         TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
8299         TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
8300         TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
8301         TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
8302         TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
8303         TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
8304         TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
8305         TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
8306         TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
8307         TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
8308         TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
8309
8310         TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
8311         TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
8312         TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
8313         TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
8314         TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
8315         TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
8316         TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
8317         TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
8318         TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
8319         TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
8320         TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
8321         TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
8322         TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
8323         TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
8324
8325         TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
8326         TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
8327         TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
8328 }
8329
8330 static void tg3_timer(unsigned long __opaque)
8331 {
8332         struct tg3 *tp = (struct tg3 *) __opaque;
8333
8334         if (tp->irq_sync)
8335                 goto restart_timer;
8336
8337         spin_lock(&tp->lock);
8338
8339         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8340                 /* All of this garbage is because when using non-tagged
8341                  * IRQ status the mailbox/status_block protocol the chip
8342                  * uses with the cpu is race prone.
8343                  */
8344                 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
8345                         tw32(GRC_LOCAL_CTRL,
8346                              tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
8347                 } else {
8348                         tw32(HOSTCC_MODE, tp->coalesce_mode |
8349                              HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
8350                 }
8351
8352                 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
8353                         tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
8354                         spin_unlock(&tp->lock);
8355                         schedule_work(&tp->reset_task);
8356                         return;
8357                 }
8358         }
8359
8360         /* This part only runs once per second. */
8361         if (!--tp->timer_counter) {
8362                 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
8363                         tg3_periodic_fetch_stats(tp);
8364
8365                 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
8366                         u32 mac_stat;
8367                         int phy_event;
8368
8369                         mac_stat = tr32(MAC_STATUS);
8370
8371                         phy_event = 0;
8372                         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
8373                                 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
8374                                         phy_event = 1;
8375                         } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
8376                                 phy_event = 1;
8377
8378                         if (phy_event)
8379                                 tg3_setup_phy(tp, 0);
8380                 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
8381                         u32 mac_stat = tr32(MAC_STATUS);
8382                         int need_setup = 0;
8383
8384                         if (netif_carrier_ok(tp->dev) &&
8385                             (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
8386                                 need_setup = 1;
8387                         }
8388                         if (! netif_carrier_ok(tp->dev) &&
8389                             (mac_stat & (MAC_STATUS_PCS_SYNCED |
8390                                          MAC_STATUS_SIGNAL_DET))) {
8391                                 need_setup = 1;
8392                         }
8393                         if (need_setup) {
8394                                 if (!tp->serdes_counter) {
8395                                         tw32_f(MAC_MODE,
8396                                              (tp->mac_mode &
8397                                               ~MAC_MODE_PORT_MODE_MASK));
8398                                         udelay(40);
8399                                         tw32_f(MAC_MODE, tp->mac_mode);
8400                                         udelay(40);
8401                                 }
8402                                 tg3_setup_phy(tp, 0);
8403                         }
8404                 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
8405                         tg3_serdes_parallel_detect(tp);
8406
8407                 tp->timer_counter = tp->timer_multiplier;
8408         }
8409
8410         /* Heartbeat is only sent once every 2 seconds.
8411          *
8412          * The heartbeat is to tell the ASF firmware that the host
8413          * driver is still alive.  In the event that the OS crashes,
8414          * ASF needs to reset the hardware to free up the FIFO space
8415          * that may be filled with rx packets destined for the host.
8416          * If the FIFO is full, ASF will no longer function properly.
8417          *
8418          * Unintended resets have been reported on real time kernels
8419          * where the timer doesn't run on time.  Netpoll will also have
8420          * same problem.
8421          *
8422          * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
8423          * to check the ring condition when the heartbeat is expiring
8424          * before doing the reset.  This will prevent most unintended
8425          * resets.
8426          */
8427         if (!--tp->asf_counter) {
8428                 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
8429                     !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
8430                         tg3_wait_for_event_ack(tp);
8431
8432                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
8433                                       FWCMD_NICDRV_ALIVE3);
8434                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
8435                         /* 5 seconds timeout */
8436                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
8437
8438                         tg3_generate_fw_event(tp);
8439                 }
8440                 tp->asf_counter = tp->asf_multiplier;
8441         }
8442
8443         spin_unlock(&tp->lock);
8444
8445 restart_timer:
8446         tp->timer.expires = jiffies + tp->timer_offset;
8447         add_timer(&tp->timer);
8448 }
8449
8450 static int tg3_request_irq(struct tg3 *tp, int irq_num)
8451 {
8452         irq_handler_t fn;
8453         unsigned long flags;
8454         char *name;
8455         struct tg3_napi *tnapi = &tp->napi[irq_num];
8456
8457         if (tp->irq_cnt == 1)
8458                 name = tp->dev->name;
8459         else {
8460                 name = &tnapi->irq_lbl[0];
8461                 snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
8462                 name[IFNAMSIZ-1] = 0;
8463         }
8464
8465         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8466                 fn = tg3_msi;
8467                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
8468                         fn = tg3_msi_1shot;
8469                 flags = IRQF_SAMPLE_RANDOM;
8470         } else {
8471                 fn = tg3_interrupt;
8472                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8473                         fn = tg3_interrupt_tagged;
8474                 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
8475         }
8476
8477         return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
8478 }
8479
8480 static int tg3_test_interrupt(struct tg3 *tp)
8481 {
8482         struct tg3_napi *tnapi = &tp->napi[0];
8483         struct net_device *dev = tp->dev;
8484         int err, i, intr_ok = 0;
8485         u32 val;
8486
8487         if (!netif_running(dev))
8488                 return -ENODEV;
8489
8490         tg3_disable_ints(tp);
8491
8492         free_irq(tnapi->irq_vec, tnapi);
8493
8494         /*
8495          * Turn off MSI one shot mode.  Otherwise this test has no
8496          * observable way to know whether the interrupt was delivered.
8497          */
8498         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
8499              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) &&
8500             (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8501                 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
8502                 tw32(MSGINT_MODE, val);
8503         }
8504
8505         err = request_irq(tnapi->irq_vec, tg3_test_isr,
8506                           IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi);
8507         if (err)
8508                 return err;
8509
8510         tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
8511         tg3_enable_ints(tp);
8512
8513         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8514                tnapi->coal_now);
8515
8516         for (i = 0; i < 5; i++) {
8517                 u32 int_mbox, misc_host_ctrl;
8518
8519                 int_mbox = tr32_mailbox(tnapi->int_mbox);
8520                 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
8521
8522                 if ((int_mbox != 0) ||
8523                     (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
8524                         intr_ok = 1;
8525                         break;
8526                 }
8527
8528                 msleep(10);
8529         }
8530
8531         tg3_disable_ints(tp);
8532
8533         free_irq(tnapi->irq_vec, tnapi);
8534
8535         err = tg3_request_irq(tp, 0);
8536
8537         if (err)
8538                 return err;
8539
8540         if (intr_ok) {
8541                 /* Reenable MSI one shot mode. */
8542                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
8543                      GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) &&
8544                     (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8545                         val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
8546                         tw32(MSGINT_MODE, val);
8547                 }
8548                 return 0;
8549         }
8550
8551         return -EIO;
8552 }
8553
8554 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
8555  * successfully restored
8556  */
8557 static int tg3_test_msi(struct tg3 *tp)
8558 {
8559         int err;
8560         u16 pci_cmd;
8561
8562         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
8563                 return 0;
8564
8565         /* Turn off SERR reporting in case MSI terminates with Master
8566          * Abort.
8567          */
8568         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
8569         pci_write_config_word(tp->pdev, PCI_COMMAND,
8570                               pci_cmd & ~PCI_COMMAND_SERR);
8571
8572         err = tg3_test_interrupt(tp);
8573
8574         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
8575
8576         if (!err)
8577                 return 0;
8578
8579         /* other failures */
8580         if (err != -EIO)
8581                 return err;
8582
8583         /* MSI test failed, go back to INTx mode */
8584         printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
8585                "switching to INTx mode. Please report this failure to "
8586                "the PCI maintainer and include system chipset information.\n",
8587                        tp->dev->name);
8588
8589         free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8590
8591         pci_disable_msi(tp->pdev);
8592
8593         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8594
8595         err = tg3_request_irq(tp, 0);
8596         if (err)
8597                 return err;
8598
8599         /* Need to reset the chip because the MSI cycle may have terminated
8600          * with Master Abort.
8601          */
8602         tg3_full_lock(tp, 1);
8603
8604         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8605         err = tg3_init_hw(tp, 1);
8606
8607         tg3_full_unlock(tp);
8608
8609         if (err)
8610                 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8611
8612         return err;
8613 }
8614
8615 static int tg3_request_firmware(struct tg3 *tp)
8616 {
8617         const __be32 *fw_data;
8618
8619         if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
8620                 printk(KERN_ERR "%s: Failed to load firmware \"%s\"\n",
8621                        tp->dev->name, tp->fw_needed);
8622                 return -ENOENT;
8623         }
8624
8625         fw_data = (void *)tp->fw->data;
8626
8627         /* Firmware blob starts with version numbers, followed by
8628          * start address and _full_ length including BSS sections
8629          * (which must be longer than the actual data, of course
8630          */
8631
8632         tp->fw_len = be32_to_cpu(fw_data[2]);   /* includes bss */
8633         if (tp->fw_len < (tp->fw->size - 12)) {
8634                 printk(KERN_ERR "%s: bogus length %d in \"%s\"\n",
8635                        tp->dev->name, tp->fw_len, tp->fw_needed);
8636                 release_firmware(tp->fw);
8637                 tp->fw = NULL;
8638                 return -EINVAL;
8639         }
8640
8641         /* We no longer need firmware; we have it. */
8642         tp->fw_needed = NULL;
8643         return 0;
8644 }
8645
8646 static bool tg3_enable_msix(struct tg3 *tp)
8647 {
8648         int i, rc, cpus = num_online_cpus();
8649         struct msix_entry msix_ent[tp->irq_max];
8650
8651         if (cpus == 1)
8652                 /* Just fallback to the simpler MSI mode. */
8653                 return false;
8654
8655         /*
8656          * We want as many rx rings enabled as there are cpus.
8657          * The first MSIX vector only deals with link interrupts, etc,
8658          * so we add one to the number of vectors we are requesting.
8659          */
8660         tp->irq_cnt = min_t(unsigned, cpus + 1, tp->irq_max);
8661
8662         for (i = 0; i < tp->irq_max; i++) {
8663                 msix_ent[i].entry  = i;
8664                 msix_ent[i].vector = 0;
8665         }
8666
8667         rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
8668         if (rc != 0) {
8669                 if (rc < TG3_RSS_MIN_NUM_MSIX_VECS)
8670                         return false;
8671                 if (pci_enable_msix(tp->pdev, msix_ent, rc))
8672                         return false;
8673                 printk(KERN_NOTICE
8674                        "%s: Requested %d MSI-X vectors, received %d\n",
8675                        tp->dev->name, tp->irq_cnt, rc);
8676                 tp->irq_cnt = rc;
8677         }
8678
8679         tp->tg3_flags3 |= TG3_FLG3_ENABLE_RSS;
8680
8681         for (i = 0; i < tp->irq_max; i++)
8682                 tp->napi[i].irq_vec = msix_ent[i].vector;
8683
8684         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
8685                 tp->tg3_flags3 |= TG3_FLG3_ENABLE_TSS;
8686                 tp->dev->real_num_tx_queues = tp->irq_cnt - 1;
8687         } else
8688                 tp->dev->real_num_tx_queues = 1;
8689
8690         return true;
8691 }
8692
8693 static void tg3_ints_init(struct tg3 *tp)
8694 {
8695         if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI_OR_MSIX) &&
8696             !(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8697                 /* All MSI supporting chips should support tagged
8698                  * status.  Assert that this is the case.
8699                  */
8700                 printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
8701                        "Not using MSI.\n", tp->dev->name);
8702                 goto defcfg;
8703         }
8704
8705         if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) && tg3_enable_msix(tp))
8706                 tp->tg3_flags2 |= TG3_FLG2_USING_MSIX;
8707         else if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) &&
8708                  pci_enable_msi(tp->pdev) == 0)
8709                 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
8710
8711         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8712                 u32 msi_mode = tr32(MSGINT_MODE);
8713                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8714                         msi_mode |= MSGINT_MODE_MULTIVEC_EN;
8715                 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
8716         }
8717 defcfg:
8718         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
8719                 tp->irq_cnt = 1;
8720                 tp->napi[0].irq_vec = tp->pdev->irq;
8721                 tp->dev->real_num_tx_queues = 1;
8722         }
8723 }
8724
8725 static void tg3_ints_fini(struct tg3 *tp)
8726 {
8727         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8728                 pci_disable_msix(tp->pdev);
8729         else if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
8730                 pci_disable_msi(tp->pdev);
8731         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI_OR_MSIX;
8732         tp->tg3_flags3 &= ~TG3_FLG3_ENABLE_RSS;
8733 }
8734
8735 static int tg3_open(struct net_device *dev)
8736 {
8737         struct tg3 *tp = netdev_priv(dev);
8738         int i, err;
8739
8740         if (tp->fw_needed) {
8741                 err = tg3_request_firmware(tp);
8742                 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8743                         if (err)
8744                                 return err;
8745                 } else if (err) {
8746                         printk(KERN_WARNING "%s: TSO capability disabled.\n",
8747                                tp->dev->name);
8748                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
8749                 } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8750                         printk(KERN_NOTICE "%s: TSO capability restored.\n",
8751                                tp->dev->name);
8752                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
8753                 }
8754         }
8755
8756         netif_carrier_off(tp->dev);
8757
8758         err = tg3_set_power_state(tp, PCI_D0);
8759         if (err)
8760                 return err;
8761
8762         tg3_full_lock(tp, 0);
8763
8764         tg3_disable_ints(tp);
8765         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8766
8767         tg3_full_unlock(tp);
8768
8769         /*
8770          * Setup interrupts first so we know how
8771          * many NAPI resources to allocate
8772          */
8773         tg3_ints_init(tp);
8774
8775         /* The placement of this call is tied
8776          * to the setup and use of Host TX descriptors.
8777          */
8778         err = tg3_alloc_consistent(tp);
8779         if (err)
8780                 goto err_out1;
8781
8782         tg3_napi_enable(tp);
8783
8784         for (i = 0; i < tp->irq_cnt; i++) {
8785                 struct tg3_napi *tnapi = &tp->napi[i];
8786                 err = tg3_request_irq(tp, i);
8787                 if (err) {
8788                         for (i--; i >= 0; i--)
8789                                 free_irq(tnapi->irq_vec, tnapi);
8790                         break;
8791                 }
8792         }
8793
8794         if (err)
8795                 goto err_out2;
8796
8797         tg3_full_lock(tp, 0);
8798
8799         err = tg3_init_hw(tp, 1);
8800         if (err) {
8801                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8802                 tg3_free_rings(tp);
8803         } else {
8804                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8805                         tp->timer_offset = HZ;
8806                 else
8807                         tp->timer_offset = HZ / 10;
8808
8809                 BUG_ON(tp->timer_offset > HZ);
8810                 tp->timer_counter = tp->timer_multiplier =
8811                         (HZ / tp->timer_offset);
8812                 tp->asf_counter = tp->asf_multiplier =
8813                         ((HZ / tp->timer_offset) * 2);
8814
8815                 init_timer(&tp->timer);
8816                 tp->timer.expires = jiffies + tp->timer_offset;
8817                 tp->timer.data = (unsigned long) tp;
8818                 tp->timer.function = tg3_timer;
8819         }
8820
8821         tg3_full_unlock(tp);
8822
8823         if (err)
8824                 goto err_out3;
8825
8826         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8827                 err = tg3_test_msi(tp);
8828
8829                 if (err) {
8830                         tg3_full_lock(tp, 0);
8831                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8832                         tg3_free_rings(tp);
8833                         tg3_full_unlock(tp);
8834
8835                         goto err_out2;
8836                 }
8837
8838                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
8839                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765 &&
8840                     (tp->tg3_flags2 & TG3_FLG2_USING_MSI) &&
8841                     (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)) {
8842                         u32 val = tr32(PCIE_TRANSACTION_CFG);
8843
8844                         tw32(PCIE_TRANSACTION_CFG,
8845                              val | PCIE_TRANS_CFG_1SHOT_MSI);
8846                 }
8847         }
8848
8849         tg3_phy_start(tp);
8850
8851         tg3_full_lock(tp, 0);
8852
8853         add_timer(&tp->timer);
8854         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
8855         tg3_enable_ints(tp);
8856
8857         tg3_full_unlock(tp);
8858
8859         netif_tx_start_all_queues(dev);
8860
8861         return 0;
8862
8863 err_out3:
8864         for (i = tp->irq_cnt - 1; i >= 0; i--) {
8865                 struct tg3_napi *tnapi = &tp->napi[i];
8866                 free_irq(tnapi->irq_vec, tnapi);
8867         }
8868
8869 err_out2:
8870         tg3_napi_disable(tp);
8871         tg3_free_consistent(tp);
8872
8873 err_out1:
8874         tg3_ints_fini(tp);
8875         return err;
8876 }
8877
8878 #if 0
8879 /*static*/ void tg3_dump_state(struct tg3 *tp)
8880 {
8881         u32 val32, val32_2, val32_3, val32_4, val32_5;
8882         u16 val16;
8883         int i;
8884         struct tg3_hw_status *sblk = tp->napi[0]->hw_status;
8885
8886         pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
8887         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
8888         printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
8889                val16, val32);
8890
8891         /* MAC block */
8892         printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
8893                tr32(MAC_MODE), tr32(MAC_STATUS));
8894         printk("       MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
8895                tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
8896         printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
8897                tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
8898         printk("       MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
8899                tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
8900
8901         /* Send data initiator control block */
8902         printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
8903                tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
8904         printk("       SNDDATAI_STATSCTRL[%08x]\n",
8905                tr32(SNDDATAI_STATSCTRL));
8906
8907         /* Send data completion control block */
8908         printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
8909
8910         /* Send BD ring selector block */
8911         printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
8912                tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
8913
8914         /* Send BD initiator control block */
8915         printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
8916                tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
8917
8918         /* Send BD completion control block */
8919         printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
8920
8921         /* Receive list placement control block */
8922         printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
8923                tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
8924         printk("       RCVLPC_STATSCTRL[%08x]\n",
8925                tr32(RCVLPC_STATSCTRL));
8926
8927         /* Receive data and receive BD initiator control block */
8928         printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
8929                tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
8930
8931         /* Receive data completion control block */
8932         printk("DEBUG: RCVDCC_MODE[%08x]\n",
8933                tr32(RCVDCC_MODE));
8934
8935         /* Receive BD initiator control block */
8936         printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
8937                tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
8938
8939         /* Receive BD completion control block */
8940         printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
8941                tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
8942
8943         /* Receive list selector control block */
8944         printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
8945                tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
8946
8947         /* Mbuf cluster free block */
8948         printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
8949                tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
8950
8951         /* Host coalescing control block */
8952         printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
8953                tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
8954         printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
8955                tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8956                tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8957         printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
8958                tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8959                tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8960         printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
8961                tr32(HOSTCC_STATS_BLK_NIC_ADDR));
8962         printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
8963                tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
8964
8965         /* Memory arbiter control block */
8966         printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
8967                tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
8968
8969         /* Buffer manager control block */
8970         printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
8971                tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
8972         printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
8973                tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
8974         printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
8975                "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
8976                tr32(BUFMGR_DMA_DESC_POOL_ADDR),
8977                tr32(BUFMGR_DMA_DESC_POOL_SIZE));
8978
8979         /* Read DMA control block */
8980         printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
8981                tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
8982
8983         /* Write DMA control block */
8984         printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
8985                tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
8986
8987         /* DMA completion block */
8988         printk("DEBUG: DMAC_MODE[%08x]\n",
8989                tr32(DMAC_MODE));
8990
8991         /* GRC block */
8992         printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
8993                tr32(GRC_MODE), tr32(GRC_MISC_CFG));
8994         printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
8995                tr32(GRC_LOCAL_CTRL));
8996
8997         /* TG3_BDINFOs */
8998         printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
8999                tr32(RCVDBDI_JUMBO_BD + 0x0),
9000                tr32(RCVDBDI_JUMBO_BD + 0x4),
9001                tr32(RCVDBDI_JUMBO_BD + 0x8),
9002                tr32(RCVDBDI_JUMBO_BD + 0xc));
9003         printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
9004                tr32(RCVDBDI_STD_BD + 0x0),
9005                tr32(RCVDBDI_STD_BD + 0x4),
9006                tr32(RCVDBDI_STD_BD + 0x8),
9007                tr32(RCVDBDI_STD_BD + 0xc));
9008         printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
9009                tr32(RCVDBDI_MINI_BD + 0x0),
9010                tr32(RCVDBDI_MINI_BD + 0x4),
9011                tr32(RCVDBDI_MINI_BD + 0x8),
9012                tr32(RCVDBDI_MINI_BD + 0xc));
9013
9014         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
9015         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
9016         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
9017         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
9018         printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
9019                val32, val32_2, val32_3, val32_4);
9020
9021         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
9022         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
9023         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
9024         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
9025         printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
9026                val32, val32_2, val32_3, val32_4);
9027
9028         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
9029         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
9030         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
9031         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
9032         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
9033         printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
9034                val32, val32_2, val32_3, val32_4, val32_5);
9035
9036         /* SW status block */
9037         printk(KERN_DEBUG
9038          "Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
9039                sblk->status,
9040                sblk->status_tag,
9041                sblk->rx_jumbo_consumer,
9042                sblk->rx_consumer,
9043                sblk->rx_mini_consumer,
9044                sblk->idx[0].rx_producer,
9045                sblk->idx[0].tx_consumer);
9046
9047         /* SW statistics block */
9048         printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
9049                ((u32 *)tp->hw_stats)[0],
9050                ((u32 *)tp->hw_stats)[1],
9051                ((u32 *)tp->hw_stats)[2],
9052                ((u32 *)tp->hw_stats)[3]);
9053
9054         /* Mailboxes */
9055         printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
9056                tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
9057                tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
9058                tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
9059                tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
9060
9061         /* NIC side send descriptors. */
9062         for (i = 0; i < 6; i++) {
9063                 unsigned long txd;
9064
9065                 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
9066                         + (i * sizeof(struct tg3_tx_buffer_desc));
9067                 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
9068                        i,
9069                        readl(txd + 0x0), readl(txd + 0x4),
9070                        readl(txd + 0x8), readl(txd + 0xc));
9071         }
9072
9073         /* NIC side RX descriptors. */
9074         for (i = 0; i < 6; i++) {
9075                 unsigned long rxd;
9076
9077                 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
9078                         + (i * sizeof(struct tg3_rx_buffer_desc));
9079                 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
9080                        i,
9081                        readl(rxd + 0x0), readl(rxd + 0x4),
9082                        readl(rxd + 0x8), readl(rxd + 0xc));
9083                 rxd += (4 * sizeof(u32));
9084                 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
9085                        i,
9086                        readl(rxd + 0x0), readl(rxd + 0x4),
9087                        readl(rxd + 0x8), readl(rxd + 0xc));
9088         }
9089
9090         for (i = 0; i < 6; i++) {
9091                 unsigned long rxd;
9092
9093                 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
9094                         + (i * sizeof(struct tg3_rx_buffer_desc));
9095                 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
9096                        i,
9097                        readl(rxd + 0x0), readl(rxd + 0x4),
9098                        readl(rxd + 0x8), readl(rxd + 0xc));
9099                 rxd += (4 * sizeof(u32));
9100                 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
9101                        i,
9102                        readl(rxd + 0x0), readl(rxd + 0x4),
9103                        readl(rxd + 0x8), readl(rxd + 0xc));
9104         }
9105 }
9106 #endif
9107
9108 static struct net_device_stats *tg3_get_stats(struct net_device *);
9109 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
9110
9111 static int tg3_close(struct net_device *dev)
9112 {
9113         int i;
9114         struct tg3 *tp = netdev_priv(dev);
9115
9116         tg3_napi_disable(tp);
9117         cancel_work_sync(&tp->reset_task);
9118
9119         netif_tx_stop_all_queues(dev);
9120
9121         del_timer_sync(&tp->timer);
9122
9123         tg3_phy_stop(tp);
9124
9125         tg3_full_lock(tp, 1);
9126 #if 0
9127         tg3_dump_state(tp);
9128 #endif
9129
9130         tg3_disable_ints(tp);
9131
9132         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9133         tg3_free_rings(tp);
9134         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
9135
9136         tg3_full_unlock(tp);
9137
9138         for (i = tp->irq_cnt - 1; i >= 0; i--) {
9139                 struct tg3_napi *tnapi = &tp->napi[i];
9140                 free_irq(tnapi->irq_vec, tnapi);
9141         }
9142
9143         tg3_ints_fini(tp);
9144
9145         memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
9146                sizeof(tp->net_stats_prev));
9147         memcpy(&tp->estats_prev, tg3_get_estats(tp),
9148                sizeof(tp->estats_prev));
9149
9150         tg3_free_consistent(tp);
9151
9152         tg3_set_power_state(tp, PCI_D3hot);
9153
9154         netif_carrier_off(tp->dev);
9155
9156         return 0;
9157 }
9158
9159 static inline unsigned long get_stat64(tg3_stat64_t *val)
9160 {
9161         unsigned long ret;
9162
9163 #if (BITS_PER_LONG == 32)
9164         ret = val->low;
9165 #else
9166         ret = ((u64)val->high << 32) | ((u64)val->low);
9167 #endif
9168         return ret;
9169 }
9170
9171 static inline u64 get_estat64(tg3_stat64_t *val)
9172 {
9173        return ((u64)val->high << 32) | ((u64)val->low);
9174 }
9175
9176 static unsigned long calc_crc_errors(struct tg3 *tp)
9177 {
9178         struct tg3_hw_stats *hw_stats = tp->hw_stats;
9179
9180         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
9181             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
9182              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
9183                 u32 val;
9184
9185                 spin_lock_bh(&tp->lock);
9186                 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
9187                         tg3_writephy(tp, MII_TG3_TEST1,
9188                                      val | MII_TG3_TEST1_CRC_EN);
9189                         tg3_readphy(tp, 0x14, &val);
9190                 } else
9191                         val = 0;
9192                 spin_unlock_bh(&tp->lock);
9193
9194                 tp->phy_crc_errors += val;
9195
9196                 return tp->phy_crc_errors;
9197         }
9198
9199         return get_stat64(&hw_stats->rx_fcs_errors);
9200 }
9201
9202 #define ESTAT_ADD(member) \
9203         estats->member =        old_estats->member + \
9204                                 get_estat64(&hw_stats->member)
9205
9206 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
9207 {
9208         struct tg3_ethtool_stats *estats = &tp->estats;
9209         struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
9210         struct tg3_hw_stats *hw_stats = tp->hw_stats;
9211
9212         if (!hw_stats)
9213                 return old_estats;
9214
9215         ESTAT_ADD(rx_octets);
9216         ESTAT_ADD(rx_fragments);
9217         ESTAT_ADD(rx_ucast_packets);
9218         ESTAT_ADD(rx_mcast_packets);
9219         ESTAT_ADD(rx_bcast_packets);
9220         ESTAT_ADD(rx_fcs_errors);
9221         ESTAT_ADD(rx_align_errors);
9222         ESTAT_ADD(rx_xon_pause_rcvd);
9223         ESTAT_ADD(rx_xoff_pause_rcvd);
9224         ESTAT_ADD(rx_mac_ctrl_rcvd);
9225         ESTAT_ADD(rx_xoff_entered);
9226         ESTAT_ADD(rx_frame_too_long_errors);
9227         ESTAT_ADD(rx_jabbers);
9228         ESTAT_ADD(rx_undersize_packets);
9229         ESTAT_ADD(rx_in_length_errors);
9230         ESTAT_ADD(rx_out_length_errors);
9231         ESTAT_ADD(rx_64_or_less_octet_packets);
9232         ESTAT_ADD(rx_65_to_127_octet_packets);
9233         ESTAT_ADD(rx_128_to_255_octet_packets);
9234         ESTAT_ADD(rx_256_to_511_octet_packets);
9235         ESTAT_ADD(rx_512_to_1023_octet_packets);
9236         ESTAT_ADD(rx_1024_to_1522_octet_packets);
9237         ESTAT_ADD(rx_1523_to_2047_octet_packets);
9238         ESTAT_ADD(rx_2048_to_4095_octet_packets);
9239         ESTAT_ADD(rx_4096_to_8191_octet_packets);
9240         ESTAT_ADD(rx_8192_to_9022_octet_packets);
9241
9242         ESTAT_ADD(tx_octets);
9243         ESTAT_ADD(tx_collisions);
9244         ESTAT_ADD(tx_xon_sent);
9245         ESTAT_ADD(tx_xoff_sent);
9246         ESTAT_ADD(tx_flow_control);
9247         ESTAT_ADD(tx_mac_errors);
9248         ESTAT_ADD(tx_single_collisions);
9249         ESTAT_ADD(tx_mult_collisions);
9250         ESTAT_ADD(tx_deferred);
9251         ESTAT_ADD(tx_excessive_collisions);
9252         ESTAT_ADD(tx_late_collisions);
9253         ESTAT_ADD(tx_collide_2times);
9254         ESTAT_ADD(tx_collide_3times);
9255         ESTAT_ADD(tx_collide_4times);
9256         ESTAT_ADD(tx_collide_5times);
9257         ESTAT_ADD(tx_collide_6times);
9258         ESTAT_ADD(tx_collide_7times);
9259         ESTAT_ADD(tx_collide_8times);
9260         ESTAT_ADD(tx_collide_9times);
9261         ESTAT_ADD(tx_collide_10times);
9262         ESTAT_ADD(tx_collide_11times);
9263         ESTAT_ADD(tx_collide_12times);
9264         ESTAT_ADD(tx_collide_13times);
9265         ESTAT_ADD(tx_collide_14times);
9266         ESTAT_ADD(tx_collide_15times);
9267         ESTAT_ADD(tx_ucast_packets);
9268         ESTAT_ADD(tx_mcast_packets);
9269         ESTAT_ADD(tx_bcast_packets);
9270         ESTAT_ADD(tx_carrier_sense_errors);
9271         ESTAT_ADD(tx_discards);
9272         ESTAT_ADD(tx_errors);
9273
9274         ESTAT_ADD(dma_writeq_full);
9275         ESTAT_ADD(dma_write_prioq_full);
9276         ESTAT_ADD(rxbds_empty);
9277         ESTAT_ADD(rx_discards);
9278         ESTAT_ADD(rx_errors);
9279         ESTAT_ADD(rx_threshold_hit);
9280
9281         ESTAT_ADD(dma_readq_full);
9282         ESTAT_ADD(dma_read_prioq_full);
9283         ESTAT_ADD(tx_comp_queue_full);
9284
9285         ESTAT_ADD(ring_set_send_prod_index);
9286         ESTAT_ADD(ring_status_update);
9287         ESTAT_ADD(nic_irqs);
9288         ESTAT_ADD(nic_avoided_irqs);
9289         ESTAT_ADD(nic_tx_threshold_hit);
9290
9291         return estats;
9292 }
9293
9294 static struct net_device_stats *tg3_get_stats(struct net_device *dev)
9295 {
9296         struct tg3 *tp = netdev_priv(dev);
9297         struct net_device_stats *stats = &tp->net_stats;
9298         struct net_device_stats *old_stats = &tp->net_stats_prev;
9299         struct tg3_hw_stats *hw_stats = tp->hw_stats;
9300
9301         if (!hw_stats)
9302                 return old_stats;
9303
9304         stats->rx_packets = old_stats->rx_packets +
9305                 get_stat64(&hw_stats->rx_ucast_packets) +
9306                 get_stat64(&hw_stats->rx_mcast_packets) +
9307                 get_stat64(&hw_stats->rx_bcast_packets);
9308
9309         stats->tx_packets = old_stats->tx_packets +
9310                 get_stat64(&hw_stats->tx_ucast_packets) +
9311                 get_stat64(&hw_stats->tx_mcast_packets) +
9312                 get_stat64(&hw_stats->tx_bcast_packets);
9313
9314         stats->rx_bytes = old_stats->rx_bytes +
9315                 get_stat64(&hw_stats->rx_octets);
9316         stats->tx_bytes = old_stats->tx_bytes +
9317                 get_stat64(&hw_stats->tx_octets);
9318
9319         stats->rx_errors = old_stats->rx_errors +
9320                 get_stat64(&hw_stats->rx_errors);
9321         stats->tx_errors = old_stats->tx_errors +
9322                 get_stat64(&hw_stats->tx_errors) +
9323                 get_stat64(&hw_stats->tx_mac_errors) +
9324                 get_stat64(&hw_stats->tx_carrier_sense_errors) +
9325                 get_stat64(&hw_stats->tx_discards);
9326
9327         stats->multicast = old_stats->multicast +
9328                 get_stat64(&hw_stats->rx_mcast_packets);
9329         stats->collisions = old_stats->collisions +
9330                 get_stat64(&hw_stats->tx_collisions);
9331
9332         stats->rx_length_errors = old_stats->rx_length_errors +
9333                 get_stat64(&hw_stats->rx_frame_too_long_errors) +
9334                 get_stat64(&hw_stats->rx_undersize_packets);
9335
9336         stats->rx_over_errors = old_stats->rx_over_errors +
9337                 get_stat64(&hw_stats->rxbds_empty);
9338         stats->rx_frame_errors = old_stats->rx_frame_errors +
9339                 get_stat64(&hw_stats->rx_align_errors);
9340         stats->tx_aborted_errors = old_stats->tx_aborted_errors +
9341                 get_stat64(&hw_stats->tx_discards);
9342         stats->tx_carrier_errors = old_stats->tx_carrier_errors +
9343                 get_stat64(&hw_stats->tx_carrier_sense_errors);
9344
9345         stats->rx_crc_errors = old_stats->rx_crc_errors +
9346                 calc_crc_errors(tp);
9347
9348         stats->rx_missed_errors = old_stats->rx_missed_errors +
9349                 get_stat64(&hw_stats->rx_discards);
9350
9351         return stats;
9352 }
9353
9354 static inline u32 calc_crc(unsigned char *buf, int len)
9355 {
9356         u32 reg;
9357         u32 tmp;
9358         int j, k;
9359
9360         reg = 0xffffffff;
9361
9362         for (j = 0; j < len; j++) {
9363                 reg ^= buf[j];
9364
9365                 for (k = 0; k < 8; k++) {
9366                         tmp = reg & 0x01;
9367
9368                         reg >>= 1;
9369
9370                         if (tmp) {
9371                                 reg ^= 0xedb88320;
9372                         }
9373                 }
9374         }
9375
9376         return ~reg;
9377 }
9378
9379 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
9380 {
9381         /* accept or reject all multicast frames */
9382         tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
9383         tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
9384         tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
9385         tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
9386 }
9387
9388 static void __tg3_set_rx_mode(struct net_device *dev)
9389 {
9390         struct tg3 *tp = netdev_priv(dev);
9391         u32 rx_mode;
9392
9393         rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
9394                                   RX_MODE_KEEP_VLAN_TAG);
9395
9396         /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9397          * flag clear.
9398          */
9399 #if TG3_VLAN_TAG_USED
9400         if (!tp->vlgrp &&
9401             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9402                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9403 #else
9404         /* By definition, VLAN is disabled always in this
9405          * case.
9406          */
9407         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9408                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9409 #endif
9410
9411         if (dev->flags & IFF_PROMISC) {
9412                 /* Promiscuous mode. */
9413                 rx_mode |= RX_MODE_PROMISC;
9414         } else if (dev->flags & IFF_ALLMULTI) {
9415                 /* Accept all multicast. */
9416                 tg3_set_multi (tp, 1);
9417         } else if (dev->mc_count < 1) {
9418                 /* Reject all multicast. */
9419                 tg3_set_multi (tp, 0);
9420         } else {
9421                 /* Accept one or more multicast(s). */
9422                 struct dev_mc_list *mclist;
9423                 unsigned int i;
9424                 u32 mc_filter[4] = { 0, };
9425                 u32 regidx;
9426                 u32 bit;
9427                 u32 crc;
9428
9429                 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
9430                      i++, mclist = mclist->next) {
9431
9432                         crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
9433                         bit = ~crc & 0x7f;
9434                         regidx = (bit & 0x60) >> 5;
9435                         bit &= 0x1f;
9436                         mc_filter[regidx] |= (1 << bit);
9437                 }
9438
9439                 tw32(MAC_HASH_REG_0, mc_filter[0]);
9440                 tw32(MAC_HASH_REG_1, mc_filter[1]);
9441                 tw32(MAC_HASH_REG_2, mc_filter[2]);
9442                 tw32(MAC_HASH_REG_3, mc_filter[3]);
9443         }
9444
9445         if (rx_mode != tp->rx_mode) {
9446                 tp->rx_mode = rx_mode;
9447                 tw32_f(MAC_RX_MODE, rx_mode);
9448                 udelay(10);
9449         }
9450 }
9451
9452 static void tg3_set_rx_mode(struct net_device *dev)
9453 {
9454         struct tg3 *tp = netdev_priv(dev);
9455
9456         if (!netif_running(dev))
9457                 return;
9458
9459         tg3_full_lock(tp, 0);
9460         __tg3_set_rx_mode(dev);
9461         tg3_full_unlock(tp);
9462 }
9463
9464 #define TG3_REGDUMP_LEN         (32 * 1024)
9465
9466 static int tg3_get_regs_len(struct net_device *dev)
9467 {
9468         return TG3_REGDUMP_LEN;
9469 }
9470
9471 static void tg3_get_regs(struct net_device *dev,
9472                 struct ethtool_regs *regs, void *_p)
9473 {
9474         u32 *p = _p;
9475         struct tg3 *tp = netdev_priv(dev);
9476         u8 *orig_p = _p;
9477         int i;
9478
9479         regs->version = 0;
9480
9481         memset(p, 0, TG3_REGDUMP_LEN);
9482
9483         if (tp->link_config.phy_is_low_power)
9484                 return;
9485
9486         tg3_full_lock(tp, 0);
9487
9488 #define __GET_REG32(reg)        (*(p)++ = tr32(reg))
9489 #define GET_REG32_LOOP(base,len)                \
9490 do {    p = (u32 *)(orig_p + (base));           \
9491         for (i = 0; i < len; i += 4)            \
9492                 __GET_REG32((base) + i);        \
9493 } while (0)
9494 #define GET_REG32_1(reg)                        \
9495 do {    p = (u32 *)(orig_p + (reg));            \
9496         __GET_REG32((reg));                     \
9497 } while (0)
9498
9499         GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
9500         GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
9501         GET_REG32_LOOP(MAC_MODE, 0x4f0);
9502         GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
9503         GET_REG32_1(SNDDATAC_MODE);
9504         GET_REG32_LOOP(SNDBDS_MODE, 0x80);
9505         GET_REG32_LOOP(SNDBDI_MODE, 0x48);
9506         GET_REG32_1(SNDBDC_MODE);
9507         GET_REG32_LOOP(RCVLPC_MODE, 0x20);
9508         GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
9509         GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
9510         GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
9511         GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
9512         GET_REG32_1(RCVDCC_MODE);
9513         GET_REG32_LOOP(RCVBDI_MODE, 0x20);
9514         GET_REG32_LOOP(RCVCC_MODE, 0x14);
9515         GET_REG32_LOOP(RCVLSC_MODE, 0x08);
9516         GET_REG32_1(MBFREE_MODE);
9517         GET_REG32_LOOP(HOSTCC_MODE, 0x100);
9518         GET_REG32_LOOP(MEMARB_MODE, 0x10);
9519         GET_REG32_LOOP(BUFMGR_MODE, 0x58);
9520         GET_REG32_LOOP(RDMAC_MODE, 0x08);
9521         GET_REG32_LOOP(WDMAC_MODE, 0x08);
9522         GET_REG32_1(RX_CPU_MODE);
9523         GET_REG32_1(RX_CPU_STATE);
9524         GET_REG32_1(RX_CPU_PGMCTR);
9525         GET_REG32_1(RX_CPU_HWBKPT);
9526         GET_REG32_1(TX_CPU_MODE);
9527         GET_REG32_1(TX_CPU_STATE);
9528         GET_REG32_1(TX_CPU_PGMCTR);
9529         GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
9530         GET_REG32_LOOP(FTQ_RESET, 0x120);
9531         GET_REG32_LOOP(MSGINT_MODE, 0x0c);
9532         GET_REG32_1(DMAC_MODE);
9533         GET_REG32_LOOP(GRC_MODE, 0x4c);
9534         if (tp->tg3_flags & TG3_FLAG_NVRAM)
9535                 GET_REG32_LOOP(NVRAM_CMD, 0x24);
9536
9537 #undef __GET_REG32
9538 #undef GET_REG32_LOOP
9539 #undef GET_REG32_1
9540
9541         tg3_full_unlock(tp);
9542 }
9543
9544 static int tg3_get_eeprom_len(struct net_device *dev)
9545 {
9546         struct tg3 *tp = netdev_priv(dev);
9547
9548         return tp->nvram_size;
9549 }
9550
9551 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9552 {
9553         struct tg3 *tp = netdev_priv(dev);
9554         int ret;
9555         u8  *pd;
9556         u32 i, offset, len, b_offset, b_count;
9557         __be32 val;
9558
9559         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9560                 return -EINVAL;
9561
9562         if (tp->link_config.phy_is_low_power)
9563                 return -EAGAIN;
9564
9565         offset = eeprom->offset;
9566         len = eeprom->len;
9567         eeprom->len = 0;
9568
9569         eeprom->magic = TG3_EEPROM_MAGIC;
9570
9571         if (offset & 3) {
9572                 /* adjustments to start on required 4 byte boundary */
9573                 b_offset = offset & 3;
9574                 b_count = 4 - b_offset;
9575                 if (b_count > len) {
9576                         /* i.e. offset=1 len=2 */
9577                         b_count = len;
9578                 }
9579                 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
9580                 if (ret)
9581                         return ret;
9582                 memcpy(data, ((char*)&val) + b_offset, b_count);
9583                 len -= b_count;
9584                 offset += b_count;
9585                 eeprom->len += b_count;
9586         }
9587
9588         /* read bytes upto the last 4 byte boundary */
9589         pd = &data[eeprom->len];
9590         for (i = 0; i < (len - (len & 3)); i += 4) {
9591                 ret = tg3_nvram_read_be32(tp, offset + i, &val);
9592                 if (ret) {
9593                         eeprom->len += i;
9594                         return ret;
9595                 }
9596                 memcpy(pd + i, &val, 4);
9597         }
9598         eeprom->len += i;
9599
9600         if (len & 3) {
9601                 /* read last bytes not ending on 4 byte boundary */
9602                 pd = &data[eeprom->len];
9603                 b_count = len & 3;
9604                 b_offset = offset + len - b_count;
9605                 ret = tg3_nvram_read_be32(tp, b_offset, &val);
9606                 if (ret)
9607                         return ret;
9608                 memcpy(pd, &val, b_count);
9609                 eeprom->len += b_count;
9610         }
9611         return 0;
9612 }
9613
9614 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
9615
9616 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9617 {
9618         struct tg3 *tp = netdev_priv(dev);
9619         int ret;
9620         u32 offset, len, b_offset, odd_len;
9621         u8 *buf;
9622         __be32 start, end;
9623
9624         if (tp->link_config.phy_is_low_power)
9625                 return -EAGAIN;
9626
9627         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
9628             eeprom->magic != TG3_EEPROM_MAGIC)
9629                 return -EINVAL;
9630
9631         offset = eeprom->offset;
9632         len = eeprom->len;
9633
9634         if ((b_offset = (offset & 3))) {
9635                 /* adjustments to start on required 4 byte boundary */
9636                 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
9637                 if (ret)
9638                         return ret;
9639                 len += b_offset;
9640                 offset &= ~3;
9641                 if (len < 4)
9642                         len = 4;
9643         }
9644
9645         odd_len = 0;
9646         if (len & 3) {
9647                 /* adjustments to end on required 4 byte boundary */
9648                 odd_len = 1;
9649                 len = (len + 3) & ~3;
9650                 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
9651                 if (ret)
9652                         return ret;
9653         }
9654
9655         buf = data;
9656         if (b_offset || odd_len) {
9657                 buf = kmalloc(len, GFP_KERNEL);
9658                 if (!buf)
9659                         return -ENOMEM;
9660                 if (b_offset)
9661                         memcpy(buf, &start, 4);
9662                 if (odd_len)
9663                         memcpy(buf+len-4, &end, 4);
9664                 memcpy(buf + b_offset, data, eeprom->len);
9665         }
9666
9667         ret = tg3_nvram_write_block(tp, offset, len, buf);
9668
9669         if (buf != data)
9670                 kfree(buf);
9671
9672         return ret;
9673 }
9674
9675 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9676 {
9677         struct tg3 *tp = netdev_priv(dev);
9678
9679         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9680                 struct phy_device *phydev;
9681                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9682                         return -EAGAIN;
9683                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9684                 return phy_ethtool_gset(phydev, cmd);
9685         }
9686
9687         cmd->supported = (SUPPORTED_Autoneg);
9688
9689         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
9690                 cmd->supported |= (SUPPORTED_1000baseT_Half |
9691                                    SUPPORTED_1000baseT_Full);
9692
9693         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
9694                 cmd->supported |= (SUPPORTED_100baseT_Half |
9695                                   SUPPORTED_100baseT_Full |
9696                                   SUPPORTED_10baseT_Half |
9697                                   SUPPORTED_10baseT_Full |
9698                                   SUPPORTED_TP);
9699                 cmd->port = PORT_TP;
9700         } else {
9701                 cmd->supported |= SUPPORTED_FIBRE;
9702                 cmd->port = PORT_FIBRE;
9703         }
9704
9705         cmd->advertising = tp->link_config.advertising;
9706         if (netif_running(dev)) {
9707                 cmd->speed = tp->link_config.active_speed;
9708                 cmd->duplex = tp->link_config.active_duplex;
9709         }
9710         cmd->phy_address = tp->phy_addr;
9711         cmd->transceiver = XCVR_INTERNAL;
9712         cmd->autoneg = tp->link_config.autoneg;
9713         cmd->maxtxpkt = 0;
9714         cmd->maxrxpkt = 0;
9715         return 0;
9716 }
9717
9718 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9719 {
9720         struct tg3 *tp = netdev_priv(dev);
9721
9722         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9723                 struct phy_device *phydev;
9724                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9725                         return -EAGAIN;
9726                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9727                 return phy_ethtool_sset(phydev, cmd);
9728         }
9729
9730         if (cmd->autoneg != AUTONEG_ENABLE &&
9731             cmd->autoneg != AUTONEG_DISABLE)
9732                 return -EINVAL;
9733
9734         if (cmd->autoneg == AUTONEG_DISABLE &&
9735             cmd->duplex != DUPLEX_FULL &&
9736             cmd->duplex != DUPLEX_HALF)
9737                 return -EINVAL;
9738
9739         if (cmd->autoneg == AUTONEG_ENABLE) {
9740                 u32 mask = ADVERTISED_Autoneg |
9741                            ADVERTISED_Pause |
9742                            ADVERTISED_Asym_Pause;
9743
9744                 if (!(tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
9745                         mask |= ADVERTISED_1000baseT_Half |
9746                                 ADVERTISED_1000baseT_Full;
9747
9748                 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
9749                         mask |= ADVERTISED_100baseT_Half |
9750                                 ADVERTISED_100baseT_Full |
9751                                 ADVERTISED_10baseT_Half |
9752                                 ADVERTISED_10baseT_Full |
9753                                 ADVERTISED_TP;
9754                 else
9755                         mask |= ADVERTISED_FIBRE;
9756
9757                 if (cmd->advertising & ~mask)
9758                         return -EINVAL;
9759
9760                 mask &= (ADVERTISED_1000baseT_Half |
9761                          ADVERTISED_1000baseT_Full |
9762                          ADVERTISED_100baseT_Half |
9763                          ADVERTISED_100baseT_Full |
9764                          ADVERTISED_10baseT_Half |
9765                          ADVERTISED_10baseT_Full);
9766
9767                 cmd->advertising &= mask;
9768         } else {
9769                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
9770                         if (cmd->speed != SPEED_1000)
9771                                 return -EINVAL;
9772
9773                         if (cmd->duplex != DUPLEX_FULL)
9774                                 return -EINVAL;
9775                 } else {
9776                         if (cmd->speed != SPEED_100 &&
9777                             cmd->speed != SPEED_10)
9778                                 return -EINVAL;
9779                 }
9780         }
9781
9782         tg3_full_lock(tp, 0);
9783
9784         tp->link_config.autoneg = cmd->autoneg;
9785         if (cmd->autoneg == AUTONEG_ENABLE) {
9786                 tp->link_config.advertising = (cmd->advertising |
9787                                               ADVERTISED_Autoneg);
9788                 tp->link_config.speed = SPEED_INVALID;
9789                 tp->link_config.duplex = DUPLEX_INVALID;
9790         } else {
9791                 tp->link_config.advertising = 0;
9792                 tp->link_config.speed = cmd->speed;
9793                 tp->link_config.duplex = cmd->duplex;
9794         }
9795
9796         tp->link_config.orig_speed = tp->link_config.speed;
9797         tp->link_config.orig_duplex = tp->link_config.duplex;
9798         tp->link_config.orig_autoneg = tp->link_config.autoneg;
9799
9800         if (netif_running(dev))
9801                 tg3_setup_phy(tp, 1);
9802
9803         tg3_full_unlock(tp);
9804
9805         return 0;
9806 }
9807
9808 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
9809 {
9810         struct tg3 *tp = netdev_priv(dev);
9811
9812         strcpy(info->driver, DRV_MODULE_NAME);
9813         strcpy(info->version, DRV_MODULE_VERSION);
9814         strcpy(info->fw_version, tp->fw_ver);
9815         strcpy(info->bus_info, pci_name(tp->pdev));
9816 }
9817
9818 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9819 {
9820         struct tg3 *tp = netdev_priv(dev);
9821
9822         if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
9823             device_can_wakeup(&tp->pdev->dev))
9824                 wol->supported = WAKE_MAGIC;
9825         else
9826                 wol->supported = 0;
9827         wol->wolopts = 0;
9828         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
9829             device_can_wakeup(&tp->pdev->dev))
9830                 wol->wolopts = WAKE_MAGIC;
9831         memset(&wol->sopass, 0, sizeof(wol->sopass));
9832 }
9833
9834 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9835 {
9836         struct tg3 *tp = netdev_priv(dev);
9837         struct device *dp = &tp->pdev->dev;
9838
9839         if (wol->wolopts & ~WAKE_MAGIC)
9840                 return -EINVAL;
9841         if ((wol->wolopts & WAKE_MAGIC) &&
9842             !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
9843                 return -EINVAL;
9844
9845         spin_lock_bh(&tp->lock);
9846         if (wol->wolopts & WAKE_MAGIC) {
9847                 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
9848                 device_set_wakeup_enable(dp, true);
9849         } else {
9850                 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
9851                 device_set_wakeup_enable(dp, false);
9852         }
9853         spin_unlock_bh(&tp->lock);
9854
9855         return 0;
9856 }
9857
9858 static u32 tg3_get_msglevel(struct net_device *dev)
9859 {
9860         struct tg3 *tp = netdev_priv(dev);
9861         return tp->msg_enable;
9862 }
9863
9864 static void tg3_set_msglevel(struct net_device *dev, u32 value)
9865 {
9866         struct tg3 *tp = netdev_priv(dev);
9867         tp->msg_enable = value;
9868 }
9869
9870 static int tg3_set_tso(struct net_device *dev, u32 value)
9871 {
9872         struct tg3 *tp = netdev_priv(dev);
9873
9874         if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
9875                 if (value)
9876                         return -EINVAL;
9877                 return 0;
9878         }
9879         if ((dev->features & NETIF_F_IPV6_CSUM) &&
9880             ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
9881              (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3))) {
9882                 if (value) {
9883                         dev->features |= NETIF_F_TSO6;
9884                         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
9885                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9886                             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
9887                              GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
9888                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
9889                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9890                                 dev->features |= NETIF_F_TSO_ECN;
9891                 } else
9892                         dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
9893         }
9894         return ethtool_op_set_tso(dev, value);
9895 }
9896
9897 static int tg3_nway_reset(struct net_device *dev)
9898 {
9899         struct tg3 *tp = netdev_priv(dev);
9900         int r;
9901
9902         if (!netif_running(dev))
9903                 return -EAGAIN;
9904
9905         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9906                 return -EINVAL;
9907
9908         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9909                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9910                         return -EAGAIN;
9911                 r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
9912         } else {
9913                 u32 bmcr;
9914
9915                 spin_lock_bh(&tp->lock);
9916                 r = -EINVAL;
9917                 tg3_readphy(tp, MII_BMCR, &bmcr);
9918                 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
9919                     ((bmcr & BMCR_ANENABLE) ||
9920                      (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
9921                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
9922                                                    BMCR_ANENABLE);
9923                         r = 0;
9924                 }
9925                 spin_unlock_bh(&tp->lock);
9926         }
9927
9928         return r;
9929 }
9930
9931 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9932 {
9933         struct tg3 *tp = netdev_priv(dev);
9934
9935         ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
9936         ering->rx_mini_max_pending = 0;
9937         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9938                 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
9939         else
9940                 ering->rx_jumbo_max_pending = 0;
9941
9942         ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
9943
9944         ering->rx_pending = tp->rx_pending;
9945         ering->rx_mini_pending = 0;
9946         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9947                 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
9948         else
9949                 ering->rx_jumbo_pending = 0;
9950
9951         ering->tx_pending = tp->napi[0].tx_pending;
9952 }
9953
9954 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9955 {
9956         struct tg3 *tp = netdev_priv(dev);
9957         int i, irq_sync = 0, err = 0;
9958
9959         if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
9960             (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
9961             (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
9962             (ering->tx_pending <= MAX_SKB_FRAGS) ||
9963             ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
9964              (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
9965                 return -EINVAL;
9966
9967         if (netif_running(dev)) {
9968                 tg3_phy_stop(tp);
9969                 tg3_netif_stop(tp);
9970                 irq_sync = 1;
9971         }
9972
9973         tg3_full_lock(tp, irq_sync);
9974
9975         tp->rx_pending = ering->rx_pending;
9976
9977         if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
9978             tp->rx_pending > 63)
9979                 tp->rx_pending = 63;
9980         tp->rx_jumbo_pending = ering->rx_jumbo_pending;
9981
9982         for (i = 0; i < TG3_IRQ_MAX_VECS; i++)
9983                 tp->napi[i].tx_pending = ering->tx_pending;
9984
9985         if (netif_running(dev)) {
9986                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9987                 err = tg3_restart_hw(tp, 1);
9988                 if (!err)
9989                         tg3_netif_start(tp);
9990         }
9991
9992         tg3_full_unlock(tp);
9993
9994         if (irq_sync && !err)
9995                 tg3_phy_start(tp);
9996
9997         return err;
9998 }
9999
10000 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
10001 {
10002         struct tg3 *tp = netdev_priv(dev);
10003
10004         epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
10005
10006         if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
10007                 epause->rx_pause = 1;
10008         else
10009                 epause->rx_pause = 0;
10010
10011         if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
10012                 epause->tx_pause = 1;
10013         else
10014                 epause->tx_pause = 0;
10015 }
10016
10017 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
10018 {
10019         struct tg3 *tp = netdev_priv(dev);
10020         int err = 0;
10021
10022         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
10023                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
10024                         return -EAGAIN;
10025
10026                 if (epause->autoneg) {
10027                         u32 newadv;
10028                         struct phy_device *phydev;
10029
10030                         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
10031
10032                         if (epause->rx_pause) {
10033                                 if (epause->tx_pause)
10034                                         newadv = ADVERTISED_Pause;
10035                                 else
10036                                         newadv = ADVERTISED_Pause |
10037                                                  ADVERTISED_Asym_Pause;
10038                         } else if (epause->tx_pause) {
10039                                 newadv = ADVERTISED_Asym_Pause;
10040                         } else
10041                                 newadv = 0;
10042
10043                         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
10044                                 u32 oldadv = phydev->advertising &
10045                                              (ADVERTISED_Pause |
10046                                               ADVERTISED_Asym_Pause);
10047                                 if (oldadv != newadv) {
10048                                         phydev->advertising &=
10049                                                 ~(ADVERTISED_Pause |
10050                                                   ADVERTISED_Asym_Pause);
10051                                         phydev->advertising |= newadv;
10052                                         err = phy_start_aneg(phydev);
10053                                 }
10054                         } else {
10055                                 tp->link_config.advertising &=
10056                                                 ~(ADVERTISED_Pause |
10057                                                   ADVERTISED_Asym_Pause);
10058                                 tp->link_config.advertising |= newadv;
10059                         }
10060                 } else {
10061                         if (epause->rx_pause)
10062                                 tp->link_config.flowctrl |= FLOW_CTRL_RX;
10063                         else
10064                                 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
10065
10066                         if (epause->tx_pause)
10067                                 tp->link_config.flowctrl |= FLOW_CTRL_TX;
10068                         else
10069                                 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
10070
10071                         if (netif_running(dev))
10072                                 tg3_setup_flow_control(tp, 0, 0);
10073                 }
10074         } else {
10075                 int irq_sync = 0;
10076
10077                 if (netif_running(dev)) {
10078                         tg3_netif_stop(tp);
10079                         irq_sync = 1;
10080                 }
10081
10082                 tg3_full_lock(tp, irq_sync);
10083
10084                 if (epause->autoneg)
10085                         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
10086                 else
10087                         tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
10088                 if (epause->rx_pause)
10089                         tp->link_config.flowctrl |= FLOW_CTRL_RX;
10090                 else
10091                         tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
10092                 if (epause->tx_pause)
10093                         tp->link_config.flowctrl |= FLOW_CTRL_TX;
10094                 else
10095                         tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
10096
10097                 if (netif_running(dev)) {
10098                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10099                         err = tg3_restart_hw(tp, 1);
10100                         if (!err)
10101                                 tg3_netif_start(tp);
10102                 }
10103
10104                 tg3_full_unlock(tp);
10105         }
10106
10107         return err;
10108 }
10109
10110 static u32 tg3_get_rx_csum(struct net_device *dev)
10111 {
10112         struct tg3 *tp = netdev_priv(dev);
10113         return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
10114 }
10115
10116 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
10117 {
10118         struct tg3 *tp = netdev_priv(dev);
10119
10120         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10121                 if (data != 0)
10122                         return -EINVAL;
10123                 return 0;
10124         }
10125
10126         spin_lock_bh(&tp->lock);
10127         if (data)
10128                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
10129         else
10130                 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
10131         spin_unlock_bh(&tp->lock);
10132
10133         return 0;
10134 }
10135
10136 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
10137 {
10138         struct tg3 *tp = netdev_priv(dev);
10139
10140         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10141                 if (data != 0)
10142                         return -EINVAL;
10143                 return 0;
10144         }
10145
10146         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10147                 ethtool_op_set_tx_ipv6_csum(dev, data);
10148         else
10149                 ethtool_op_set_tx_csum(dev, data);
10150
10151         return 0;
10152 }
10153
10154 static int tg3_get_sset_count (struct net_device *dev, int sset)
10155 {
10156         switch (sset) {
10157         case ETH_SS_TEST:
10158                 return TG3_NUM_TEST;
10159         case ETH_SS_STATS:
10160                 return TG3_NUM_STATS;
10161         default:
10162                 return -EOPNOTSUPP;
10163         }
10164 }
10165
10166 static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
10167 {
10168         switch (stringset) {
10169         case ETH_SS_STATS:
10170                 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
10171                 break;
10172         case ETH_SS_TEST:
10173                 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
10174                 break;
10175         default:
10176                 WARN_ON(1);     /* we need a WARN() */
10177                 break;
10178         }
10179 }
10180
10181 static int tg3_phys_id(struct net_device *dev, u32 data)
10182 {
10183         struct tg3 *tp = netdev_priv(dev);
10184         int i;
10185
10186         if (!netif_running(tp->dev))
10187                 return -EAGAIN;
10188
10189         if (data == 0)
10190                 data = UINT_MAX / 2;
10191
10192         for (i = 0; i < (data * 2); i++) {
10193                 if ((i % 2) == 0)
10194                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10195                                            LED_CTRL_1000MBPS_ON |
10196                                            LED_CTRL_100MBPS_ON |
10197                                            LED_CTRL_10MBPS_ON |
10198                                            LED_CTRL_TRAFFIC_OVERRIDE |
10199                                            LED_CTRL_TRAFFIC_BLINK |
10200                                            LED_CTRL_TRAFFIC_LED);
10201
10202                 else
10203                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10204                                            LED_CTRL_TRAFFIC_OVERRIDE);
10205
10206                 if (msleep_interruptible(500))
10207                         break;
10208         }
10209         tw32(MAC_LED_CTRL, tp->led_ctrl);
10210         return 0;
10211 }
10212
10213 static void tg3_get_ethtool_stats (struct net_device *dev,
10214                                    struct ethtool_stats *estats, u64 *tmp_stats)
10215 {
10216         struct tg3 *tp = netdev_priv(dev);
10217         memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
10218 }
10219
10220 #define NVRAM_TEST_SIZE 0x100
10221 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE   0x14
10222 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE   0x18
10223 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE   0x1c
10224 #define NVRAM_SELFBOOT_HW_SIZE 0x20
10225 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
10226
10227 static int tg3_test_nvram(struct tg3 *tp)
10228 {
10229         u32 csum, magic;
10230         __be32 *buf;
10231         int i, j, k, err = 0, size;
10232
10233         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
10234                 return 0;
10235
10236         if (tg3_nvram_read(tp, 0, &magic) != 0)
10237                 return -EIO;
10238
10239         if (magic == TG3_EEPROM_MAGIC)
10240                 size = NVRAM_TEST_SIZE;
10241         else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
10242                 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
10243                     TG3_EEPROM_SB_FORMAT_1) {
10244                         switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
10245                         case TG3_EEPROM_SB_REVISION_0:
10246                                 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
10247                                 break;
10248                         case TG3_EEPROM_SB_REVISION_2:
10249                                 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
10250                                 break;
10251                         case TG3_EEPROM_SB_REVISION_3:
10252                                 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
10253                                 break;
10254                         default:
10255                                 return 0;
10256                         }
10257                 } else
10258                         return 0;
10259         } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
10260                 size = NVRAM_SELFBOOT_HW_SIZE;
10261         else
10262                 return -EIO;
10263
10264         buf = kmalloc(size, GFP_KERNEL);
10265         if (buf == NULL)
10266                 return -ENOMEM;
10267
10268         err = -EIO;
10269         for (i = 0, j = 0; i < size; i += 4, j++) {
10270                 err = tg3_nvram_read_be32(tp, i, &buf[j]);
10271                 if (err)
10272                         break;
10273         }
10274         if (i < size)
10275                 goto out;
10276
10277         /* Selfboot format */
10278         magic = be32_to_cpu(buf[0]);
10279         if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
10280             TG3_EEPROM_MAGIC_FW) {
10281                 u8 *buf8 = (u8 *) buf, csum8 = 0;
10282
10283                 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
10284                     TG3_EEPROM_SB_REVISION_2) {
10285                         /* For rev 2, the csum doesn't include the MBA. */
10286                         for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
10287                                 csum8 += buf8[i];
10288                         for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
10289                                 csum8 += buf8[i];
10290                 } else {
10291                         for (i = 0; i < size; i++)
10292                                 csum8 += buf8[i];
10293                 }
10294
10295                 if (csum8 == 0) {
10296                         err = 0;
10297                         goto out;
10298                 }
10299
10300                 err = -EIO;
10301                 goto out;
10302         }
10303
10304         if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
10305             TG3_EEPROM_MAGIC_HW) {
10306                 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
10307                 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
10308                 u8 *buf8 = (u8 *) buf;
10309
10310                 /* Separate the parity bits and the data bytes.  */
10311                 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
10312                         if ((i == 0) || (i == 8)) {
10313                                 int l;
10314                                 u8 msk;
10315
10316                                 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
10317                                         parity[k++] = buf8[i] & msk;
10318                                 i++;
10319                         }
10320                         else if (i == 16) {
10321                                 int l;
10322                                 u8 msk;
10323
10324                                 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
10325                                         parity[k++] = buf8[i] & msk;
10326                                 i++;
10327
10328                                 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
10329                                         parity[k++] = buf8[i] & msk;
10330                                 i++;
10331                         }
10332                         data[j++] = buf8[i];
10333                 }
10334
10335                 err = -EIO;
10336                 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
10337                         u8 hw8 = hweight8(data[i]);
10338
10339                         if ((hw8 & 0x1) && parity[i])
10340                                 goto out;
10341                         else if (!(hw8 & 0x1) && !parity[i])
10342                                 goto out;
10343                 }
10344                 err = 0;
10345                 goto out;
10346         }
10347
10348         /* Bootstrap checksum at offset 0x10 */
10349         csum = calc_crc((unsigned char *) buf, 0x10);
10350         if (csum != be32_to_cpu(buf[0x10/4]))
10351                 goto out;
10352
10353         /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
10354         csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
10355         if (csum != be32_to_cpu(buf[0xfc/4]))
10356                 goto out;
10357
10358         err = 0;
10359
10360 out:
10361         kfree(buf);
10362         return err;
10363 }
10364
10365 #define TG3_SERDES_TIMEOUT_SEC  2
10366 #define TG3_COPPER_TIMEOUT_SEC  6
10367
10368 static int tg3_test_link(struct tg3 *tp)
10369 {
10370         int i, max;
10371
10372         if (!netif_running(tp->dev))
10373                 return -ENODEV;
10374
10375         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
10376                 max = TG3_SERDES_TIMEOUT_SEC;
10377         else
10378                 max = TG3_COPPER_TIMEOUT_SEC;
10379
10380         for (i = 0; i < max; i++) {
10381                 if (netif_carrier_ok(tp->dev))
10382                         return 0;
10383
10384                 if (msleep_interruptible(1000))
10385                         break;
10386         }
10387
10388         return -EIO;
10389 }
10390
10391 /* Only test the commonly used registers */
10392 static int tg3_test_registers(struct tg3 *tp)
10393 {
10394         int i, is_5705, is_5750;
10395         u32 offset, read_mask, write_mask, val, save_val, read_val;
10396         static struct {
10397                 u16 offset;
10398                 u16 flags;
10399 #define TG3_FL_5705     0x1
10400 #define TG3_FL_NOT_5705 0x2
10401 #define TG3_FL_NOT_5788 0x4
10402 #define TG3_FL_NOT_5750 0x8
10403                 u32 read_mask;
10404                 u32 write_mask;
10405         } reg_tbl[] = {
10406                 /* MAC Control Registers */
10407                 { MAC_MODE, TG3_FL_NOT_5705,
10408                         0x00000000, 0x00ef6f8c },
10409                 { MAC_MODE, TG3_FL_5705,
10410                         0x00000000, 0x01ef6b8c },
10411                 { MAC_STATUS, TG3_FL_NOT_5705,
10412                         0x03800107, 0x00000000 },
10413                 { MAC_STATUS, TG3_FL_5705,
10414                         0x03800100, 0x00000000 },
10415                 { MAC_ADDR_0_HIGH, 0x0000,
10416                         0x00000000, 0x0000ffff },
10417                 { MAC_ADDR_0_LOW, 0x0000,
10418                         0x00000000, 0xffffffff },
10419                 { MAC_RX_MTU_SIZE, 0x0000,
10420                         0x00000000, 0x0000ffff },
10421                 { MAC_TX_MODE, 0x0000,
10422                         0x00000000, 0x00000070 },
10423                 { MAC_TX_LENGTHS, 0x0000,
10424                         0x00000000, 0x00003fff },
10425                 { MAC_RX_MODE, TG3_FL_NOT_5705,
10426                         0x00000000, 0x000007fc },
10427                 { MAC_RX_MODE, TG3_FL_5705,
10428                         0x00000000, 0x000007dc },
10429                 { MAC_HASH_REG_0, 0x0000,
10430                         0x00000000, 0xffffffff },
10431                 { MAC_HASH_REG_1, 0x0000,
10432                         0x00000000, 0xffffffff },
10433                 { MAC_HASH_REG_2, 0x0000,
10434                         0x00000000, 0xffffffff },
10435                 { MAC_HASH_REG_3, 0x0000,
10436                         0x00000000, 0xffffffff },
10437
10438                 /* Receive Data and Receive BD Initiator Control Registers. */
10439                 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
10440                         0x00000000, 0xffffffff },
10441                 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
10442                         0x00000000, 0xffffffff },
10443                 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
10444                         0x00000000, 0x00000003 },
10445                 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
10446                         0x00000000, 0xffffffff },
10447                 { RCVDBDI_STD_BD+0, 0x0000,
10448                         0x00000000, 0xffffffff },
10449                 { RCVDBDI_STD_BD+4, 0x0000,
10450                         0x00000000, 0xffffffff },
10451                 { RCVDBDI_STD_BD+8, 0x0000,
10452                         0x00000000, 0xffff0002 },
10453                 { RCVDBDI_STD_BD+0xc, 0x0000,
10454                         0x00000000, 0xffffffff },
10455
10456                 /* Receive BD Initiator Control Registers. */
10457                 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
10458                         0x00000000, 0xffffffff },
10459                 { RCVBDI_STD_THRESH, TG3_FL_5705,
10460                         0x00000000, 0x000003ff },
10461                 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
10462                         0x00000000, 0xffffffff },
10463
10464                 /* Host Coalescing Control Registers. */
10465                 { HOSTCC_MODE, TG3_FL_NOT_5705,
10466                         0x00000000, 0x00000004 },
10467                 { HOSTCC_MODE, TG3_FL_5705,
10468                         0x00000000, 0x000000f6 },
10469                 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
10470                         0x00000000, 0xffffffff },
10471                 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
10472                         0x00000000, 0x000003ff },
10473                 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
10474                         0x00000000, 0xffffffff },
10475                 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
10476                         0x00000000, 0x000003ff },
10477                 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
10478                         0x00000000, 0xffffffff },
10479                 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10480                         0x00000000, 0x000000ff },
10481                 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
10482                         0x00000000, 0xffffffff },
10483                 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10484                         0x00000000, 0x000000ff },
10485                 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
10486                         0x00000000, 0xffffffff },
10487                 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
10488                         0x00000000, 0xffffffff },
10489                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10490                         0x00000000, 0xffffffff },
10491                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10492                         0x00000000, 0x000000ff },
10493                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10494                         0x00000000, 0xffffffff },
10495                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10496                         0x00000000, 0x000000ff },
10497                 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
10498                         0x00000000, 0xffffffff },
10499                 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
10500                         0x00000000, 0xffffffff },
10501                 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
10502                         0x00000000, 0xffffffff },
10503                 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
10504                         0x00000000, 0xffffffff },
10505                 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
10506                         0x00000000, 0xffffffff },
10507                 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
10508                         0xffffffff, 0x00000000 },
10509                 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
10510                         0xffffffff, 0x00000000 },
10511
10512                 /* Buffer Manager Control Registers. */
10513                 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
10514                         0x00000000, 0x007fff80 },
10515                 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
10516                         0x00000000, 0x007fffff },
10517                 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
10518                         0x00000000, 0x0000003f },
10519                 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
10520                         0x00000000, 0x000001ff },
10521                 { BUFMGR_MB_HIGH_WATER, 0x0000,
10522                         0x00000000, 0x000001ff },
10523                 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
10524                         0xffffffff, 0x00000000 },
10525                 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
10526                         0xffffffff, 0x00000000 },
10527
10528                 /* Mailbox Registers */
10529                 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
10530                         0x00000000, 0x000001ff },
10531                 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
10532                         0x00000000, 0x000001ff },
10533                 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
10534                         0x00000000, 0x000007ff },
10535                 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
10536                         0x00000000, 0x000001ff },
10537
10538                 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
10539         };
10540
10541         is_5705 = is_5750 = 0;
10542         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10543                 is_5705 = 1;
10544                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10545                         is_5750 = 1;
10546         }
10547
10548         for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
10549                 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
10550                         continue;
10551
10552                 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
10553                         continue;
10554
10555                 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10556                     (reg_tbl[i].flags & TG3_FL_NOT_5788))
10557                         continue;
10558
10559                 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
10560                         continue;
10561
10562                 offset = (u32) reg_tbl[i].offset;
10563                 read_mask = reg_tbl[i].read_mask;
10564                 write_mask = reg_tbl[i].write_mask;
10565
10566                 /* Save the original register content */
10567                 save_val = tr32(offset);
10568
10569                 /* Determine the read-only value. */
10570                 read_val = save_val & read_mask;
10571
10572                 /* Write zero to the register, then make sure the read-only bits
10573                  * are not changed and the read/write bits are all zeros.
10574                  */
10575                 tw32(offset, 0);
10576
10577                 val = tr32(offset);
10578
10579                 /* Test the read-only and read/write bits. */
10580                 if (((val & read_mask) != read_val) || (val & write_mask))
10581                         goto out;
10582
10583                 /* Write ones to all the bits defined by RdMask and WrMask, then
10584                  * make sure the read-only bits are not changed and the
10585                  * read/write bits are all ones.
10586                  */
10587                 tw32(offset, read_mask | write_mask);
10588
10589                 val = tr32(offset);
10590
10591                 /* Test the read-only bits. */
10592                 if ((val & read_mask) != read_val)
10593                         goto out;
10594
10595                 /* Test the read/write bits. */
10596                 if ((val & write_mask) != write_mask)
10597                         goto out;
10598
10599                 tw32(offset, save_val);
10600         }
10601
10602         return 0;
10603
10604 out:
10605         if (netif_msg_hw(tp))
10606                 printk(KERN_ERR PFX "Register test failed at offset %x\n",
10607                        offset);
10608         tw32(offset, save_val);
10609         return -EIO;
10610 }
10611
10612 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
10613 {
10614         static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
10615         int i;
10616         u32 j;
10617
10618         for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
10619                 for (j = 0; j < len; j += 4) {
10620                         u32 val;
10621
10622                         tg3_write_mem(tp, offset + j, test_pattern[i]);
10623                         tg3_read_mem(tp, offset + j, &val);
10624                         if (val != test_pattern[i])
10625                                 return -EIO;
10626                 }
10627         }
10628         return 0;
10629 }
10630
10631 static int tg3_test_memory(struct tg3 *tp)
10632 {
10633         static struct mem_entry {
10634                 u32 offset;
10635                 u32 len;
10636         } mem_tbl_570x[] = {
10637                 { 0x00000000, 0x00b50},
10638                 { 0x00002000, 0x1c000},
10639                 { 0xffffffff, 0x00000}
10640         }, mem_tbl_5705[] = {
10641                 { 0x00000100, 0x0000c},
10642                 { 0x00000200, 0x00008},
10643                 { 0x00004000, 0x00800},
10644                 { 0x00006000, 0x01000},
10645                 { 0x00008000, 0x02000},
10646                 { 0x00010000, 0x0e000},
10647                 { 0xffffffff, 0x00000}
10648         }, mem_tbl_5755[] = {
10649                 { 0x00000200, 0x00008},
10650                 { 0x00004000, 0x00800},
10651                 { 0x00006000, 0x00800},
10652                 { 0x00008000, 0x02000},
10653                 { 0x00010000, 0x0c000},
10654                 { 0xffffffff, 0x00000}
10655         }, mem_tbl_5906[] = {
10656                 { 0x00000200, 0x00008},
10657                 { 0x00004000, 0x00400},
10658                 { 0x00006000, 0x00400},
10659                 { 0x00008000, 0x01000},
10660                 { 0x00010000, 0x01000},
10661                 { 0xffffffff, 0x00000}
10662         }, mem_tbl_5717[] = {
10663                 { 0x00000200, 0x00008},
10664                 { 0x00010000, 0x0a000},
10665                 { 0x00020000, 0x13c00},
10666                 { 0xffffffff, 0x00000}
10667         }, mem_tbl_57765[] = {
10668                 { 0x00000200, 0x00008},
10669                 { 0x00004000, 0x00800},
10670                 { 0x00006000, 0x09800},
10671                 { 0x00010000, 0x0a000},
10672                 { 0xffffffff, 0x00000}
10673         };
10674         struct mem_entry *mem_tbl;
10675         int err = 0;
10676         int i;
10677
10678         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
10679                 mem_tbl = mem_tbl_5717;
10680         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
10681                 mem_tbl = mem_tbl_57765;
10682         else if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10683                 mem_tbl = mem_tbl_5755;
10684         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10685                 mem_tbl = mem_tbl_5906;
10686         else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
10687                 mem_tbl = mem_tbl_5705;
10688         else
10689                 mem_tbl = mem_tbl_570x;
10690
10691         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
10692                 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
10693                     mem_tbl[i].len)) != 0)
10694                         break;
10695         }
10696
10697         return err;
10698 }
10699
10700 #define TG3_MAC_LOOPBACK        0
10701 #define TG3_PHY_LOOPBACK        1
10702
10703 static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
10704 {
10705         u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
10706         u32 desc_idx, coal_now;
10707         struct sk_buff *skb, *rx_skb;
10708         u8 *tx_data;
10709         dma_addr_t map;
10710         int num_pkts, tx_len, rx_len, i, err;
10711         struct tg3_rx_buffer_desc *desc;
10712         struct tg3_napi *tnapi, *rnapi;
10713         struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
10714
10715         if (tp->irq_cnt > 1) {
10716                 tnapi = &tp->napi[1];
10717                 rnapi = &tp->napi[1];
10718         } else {
10719                 tnapi = &tp->napi[0];
10720                 rnapi = &tp->napi[0];
10721         }
10722         coal_now = tnapi->coal_now | rnapi->coal_now;
10723
10724         if (loopback_mode == TG3_MAC_LOOPBACK) {
10725                 /* HW errata - mac loopback fails in some cases on 5780.
10726                  * Normal traffic and PHY loopback are not affected by
10727                  * errata.
10728                  */
10729                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
10730                         return 0;
10731
10732                 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
10733                            MAC_MODE_PORT_INT_LPBACK;
10734                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10735                         mac_mode |= MAC_MODE_LINK_POLARITY;
10736                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
10737                         mac_mode |= MAC_MODE_PORT_MODE_MII;
10738                 else
10739                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
10740                 tw32(MAC_MODE, mac_mode);
10741         } else if (loopback_mode == TG3_PHY_LOOPBACK) {
10742                 u32 val;
10743
10744                 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10745                         tg3_phy_fet_toggle_apd(tp, false);
10746                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
10747                 } else
10748                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
10749
10750                 tg3_phy_toggle_automdix(tp, 0);
10751
10752                 tg3_writephy(tp, MII_BMCR, val);
10753                 udelay(40);
10754
10755                 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
10756                 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10757                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10758                                 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x1800);
10759                         mac_mode |= MAC_MODE_PORT_MODE_MII;
10760                 } else
10761                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
10762
10763                 /* reset to prevent losing 1st rx packet intermittently */
10764                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
10765                         tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10766                         udelay(10);
10767                         tw32_f(MAC_RX_MODE, tp->rx_mode);
10768                 }
10769                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
10770                         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)
10771                                 mac_mode &= ~MAC_MODE_LINK_POLARITY;
10772                         else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411)
10773                                 mac_mode |= MAC_MODE_LINK_POLARITY;
10774                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
10775                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
10776                 }
10777                 tw32(MAC_MODE, mac_mode);
10778         }
10779         else
10780                 return -EINVAL;
10781
10782         err = -EIO;
10783
10784         tx_len = 1514;
10785         skb = netdev_alloc_skb(tp->dev, tx_len);
10786         if (!skb)
10787                 return -ENOMEM;
10788
10789         tx_data = skb_put(skb, tx_len);
10790         memcpy(tx_data, tp->dev->dev_addr, 6);
10791         memset(tx_data + 6, 0x0, 8);
10792
10793         tw32(MAC_RX_MTU_SIZE, tx_len + 4);
10794
10795         for (i = 14; i < tx_len; i++)
10796                 tx_data[i] = (u8) (i & 0xff);
10797
10798         map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
10799         if (pci_dma_mapping_error(tp->pdev, map)) {
10800                 dev_kfree_skb(skb);
10801                 return -EIO;
10802         }
10803
10804         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10805                rnapi->coal_now);
10806
10807         udelay(10);
10808
10809         rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
10810
10811         num_pkts = 0;
10812
10813         tg3_set_txd(tnapi, tnapi->tx_prod, map, tx_len, 0, 1);
10814
10815         tnapi->tx_prod++;
10816         num_pkts++;
10817
10818         tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
10819         tr32_mailbox(tnapi->prodmbox);
10820
10821         udelay(10);
10822
10823         /* 350 usec to allow enough time on some 10/100 Mbps devices.  */
10824         for (i = 0; i < 35; i++) {
10825                 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10826                        coal_now);
10827
10828                 udelay(10);
10829
10830                 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
10831                 rx_idx = rnapi->hw_status->idx[0].rx_producer;
10832                 if ((tx_idx == tnapi->tx_prod) &&
10833                     (rx_idx == (rx_start_idx + num_pkts)))
10834                         break;
10835         }
10836
10837         pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
10838         dev_kfree_skb(skb);
10839
10840         if (tx_idx != tnapi->tx_prod)
10841                 goto out;
10842
10843         if (rx_idx != rx_start_idx + num_pkts)
10844                 goto out;
10845
10846         desc = &rnapi->rx_rcb[rx_start_idx];
10847         desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
10848         opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
10849         if (opaque_key != RXD_OPAQUE_RING_STD)
10850                 goto out;
10851
10852         if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
10853             (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
10854                 goto out;
10855
10856         rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
10857         if (rx_len != tx_len)
10858                 goto out;
10859
10860         rx_skb = tpr->rx_std_buffers[desc_idx].skb;
10861
10862         map = pci_unmap_addr(&tpr->rx_std_buffers[desc_idx], mapping);
10863         pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
10864
10865         for (i = 14; i < tx_len; i++) {
10866                 if (*(rx_skb->data + i) != (u8) (i & 0xff))
10867                         goto out;
10868         }
10869         err = 0;
10870
10871         /* tg3_free_rings will unmap and free the rx_skb */
10872 out:
10873         return err;
10874 }
10875
10876 #define TG3_MAC_LOOPBACK_FAILED         1
10877 #define TG3_PHY_LOOPBACK_FAILED         2
10878 #define TG3_LOOPBACK_FAILED             (TG3_MAC_LOOPBACK_FAILED |      \
10879                                          TG3_PHY_LOOPBACK_FAILED)
10880
10881 static int tg3_test_loopback(struct tg3 *tp)
10882 {
10883         int err = 0;
10884         u32 cpmuctrl = 0;
10885
10886         if (!netif_running(tp->dev))
10887                 return TG3_LOOPBACK_FAILED;
10888
10889         err = tg3_reset_hw(tp, 1);
10890         if (err)
10891                 return TG3_LOOPBACK_FAILED;
10892
10893         /* Turn off gphy autopowerdown. */
10894         if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10895                 tg3_phy_toggle_apd(tp, false);
10896
10897         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
10898                 int i;
10899                 u32 status;
10900
10901                 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
10902
10903                 /* Wait for up to 40 microseconds to acquire lock. */
10904                 for (i = 0; i < 4; i++) {
10905                         status = tr32(TG3_CPMU_MUTEX_GNT);
10906                         if (status == CPMU_MUTEX_GNT_DRIVER)
10907                                 break;
10908                         udelay(10);
10909                 }
10910
10911                 if (status != CPMU_MUTEX_GNT_DRIVER)
10912                         return TG3_LOOPBACK_FAILED;
10913
10914                 /* Turn off link-based power management. */
10915                 cpmuctrl = tr32(TG3_CPMU_CTRL);
10916                 tw32(TG3_CPMU_CTRL,
10917                      cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
10918                                   CPMU_CTRL_LINK_AWARE_MODE));
10919         }
10920
10921         if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
10922                 err |= TG3_MAC_LOOPBACK_FAILED;
10923
10924         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
10925                 tw32(TG3_CPMU_CTRL, cpmuctrl);
10926
10927                 /* Release the mutex */
10928                 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
10929         }
10930
10931         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
10932             !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
10933                 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
10934                         err |= TG3_PHY_LOOPBACK_FAILED;
10935         }
10936
10937         /* Re-enable gphy autopowerdown. */
10938         if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10939                 tg3_phy_toggle_apd(tp, true);
10940
10941         return err;
10942 }
10943
10944 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
10945                           u64 *data)
10946 {
10947         struct tg3 *tp = netdev_priv(dev);
10948
10949         if (tp->link_config.phy_is_low_power)
10950                 tg3_set_power_state(tp, PCI_D0);
10951
10952         memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
10953
10954         if (tg3_test_nvram(tp) != 0) {
10955                 etest->flags |= ETH_TEST_FL_FAILED;
10956                 data[0] = 1;
10957         }
10958         if (tg3_test_link(tp) != 0) {
10959                 etest->flags |= ETH_TEST_FL_FAILED;
10960                 data[1] = 1;
10961         }
10962         if (etest->flags & ETH_TEST_FL_OFFLINE) {
10963                 int err, err2 = 0, irq_sync = 0;
10964
10965                 if (netif_running(dev)) {
10966                         tg3_phy_stop(tp);
10967                         tg3_netif_stop(tp);
10968                         irq_sync = 1;
10969                 }
10970
10971                 tg3_full_lock(tp, irq_sync);
10972
10973                 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
10974                 err = tg3_nvram_lock(tp);
10975                 tg3_halt_cpu(tp, RX_CPU_BASE);
10976                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10977                         tg3_halt_cpu(tp, TX_CPU_BASE);
10978                 if (!err)
10979                         tg3_nvram_unlock(tp);
10980
10981                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
10982                         tg3_phy_reset(tp);
10983
10984                 if (tg3_test_registers(tp) != 0) {
10985                         etest->flags |= ETH_TEST_FL_FAILED;
10986                         data[2] = 1;
10987                 }
10988                 if (tg3_test_memory(tp) != 0) {
10989                         etest->flags |= ETH_TEST_FL_FAILED;
10990                         data[3] = 1;
10991                 }
10992                 if ((data[4] = tg3_test_loopback(tp)) != 0)
10993                         etest->flags |= ETH_TEST_FL_FAILED;
10994
10995                 tg3_full_unlock(tp);
10996
10997                 if (tg3_test_interrupt(tp) != 0) {
10998                         etest->flags |= ETH_TEST_FL_FAILED;
10999                         data[5] = 1;
11000                 }
11001
11002                 tg3_full_lock(tp, 0);
11003
11004                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11005                 if (netif_running(dev)) {
11006                         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
11007                         err2 = tg3_restart_hw(tp, 1);
11008                         if (!err2)
11009                                 tg3_netif_start(tp);
11010                 }
11011
11012                 tg3_full_unlock(tp);
11013
11014                 if (irq_sync && !err2)
11015                         tg3_phy_start(tp);
11016         }
11017         if (tp->link_config.phy_is_low_power)
11018                 tg3_set_power_state(tp, PCI_D3hot);
11019
11020 }
11021
11022 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
11023 {
11024         struct mii_ioctl_data *data = if_mii(ifr);
11025         struct tg3 *tp = netdev_priv(dev);
11026         int err;
11027
11028         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
11029                 struct phy_device *phydev;
11030                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
11031                         return -EAGAIN;
11032                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
11033                 return phy_mii_ioctl(phydev, data, cmd);
11034         }
11035
11036         switch(cmd) {
11037         case SIOCGMIIPHY:
11038                 data->phy_id = tp->phy_addr;
11039
11040                 /* fallthru */
11041         case SIOCGMIIREG: {
11042                 u32 mii_regval;
11043
11044                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
11045                         break;                  /* We have no PHY */
11046
11047                 if (tp->link_config.phy_is_low_power)
11048                         return -EAGAIN;
11049
11050                 spin_lock_bh(&tp->lock);
11051                 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
11052                 spin_unlock_bh(&tp->lock);
11053
11054                 data->val_out = mii_regval;
11055
11056                 return err;
11057         }
11058
11059         case SIOCSMIIREG:
11060                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
11061                         break;                  /* We have no PHY */
11062
11063                 if (tp->link_config.phy_is_low_power)
11064                         return -EAGAIN;
11065
11066                 spin_lock_bh(&tp->lock);
11067                 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
11068                 spin_unlock_bh(&tp->lock);
11069
11070                 return err;
11071
11072         default:
11073                 /* do nothing */
11074                 break;
11075         }
11076         return -EOPNOTSUPP;
11077 }
11078
11079 #if TG3_VLAN_TAG_USED
11080 static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
11081 {
11082         struct tg3 *tp = netdev_priv(dev);
11083
11084         if (!netif_running(dev)) {
11085                 tp->vlgrp = grp;
11086                 return;
11087         }
11088
11089         tg3_netif_stop(tp);
11090
11091         tg3_full_lock(tp, 0);
11092
11093         tp->vlgrp = grp;
11094
11095         /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
11096         __tg3_set_rx_mode(dev);
11097
11098         tg3_netif_start(tp);
11099
11100         tg3_full_unlock(tp);
11101 }
11102 #endif
11103
11104 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11105 {
11106         struct tg3 *tp = netdev_priv(dev);
11107
11108         memcpy(ec, &tp->coal, sizeof(*ec));
11109         return 0;
11110 }
11111
11112 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11113 {
11114         struct tg3 *tp = netdev_priv(dev);
11115         u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
11116         u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
11117
11118         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
11119                 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
11120                 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
11121                 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
11122                 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
11123         }
11124
11125         if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
11126             (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
11127             (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
11128             (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
11129             (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
11130             (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
11131             (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
11132             (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
11133             (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
11134             (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
11135                 return -EINVAL;
11136
11137         /* No rx interrupts will be generated if both are zero */
11138         if ((ec->rx_coalesce_usecs == 0) &&
11139             (ec->rx_max_coalesced_frames == 0))
11140                 return -EINVAL;
11141
11142         /* No tx interrupts will be generated if both are zero */
11143         if ((ec->tx_coalesce_usecs == 0) &&
11144             (ec->tx_max_coalesced_frames == 0))
11145                 return -EINVAL;
11146
11147         /* Only copy relevant parameters, ignore all others. */
11148         tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
11149         tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
11150         tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
11151         tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
11152         tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
11153         tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
11154         tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
11155         tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
11156         tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
11157
11158         if (netif_running(dev)) {
11159                 tg3_full_lock(tp, 0);
11160                 __tg3_set_coalesce(tp, &tp->coal);
11161                 tg3_full_unlock(tp);
11162         }
11163         return 0;
11164 }
11165
11166 static const struct ethtool_ops tg3_ethtool_ops = {
11167         .get_settings           = tg3_get_settings,
11168         .set_settings           = tg3_set_settings,
11169         .get_drvinfo            = tg3_get_drvinfo,
11170         .get_regs_len           = tg3_get_regs_len,
11171         .get_regs               = tg3_get_regs,
11172         .get_wol                = tg3_get_wol,
11173         .set_wol                = tg3_set_wol,
11174         .get_msglevel           = tg3_get_msglevel,
11175         .set_msglevel           = tg3_set_msglevel,
11176         .nway_reset             = tg3_nway_reset,
11177         .get_link               = ethtool_op_get_link,
11178         .get_eeprom_len         = tg3_get_eeprom_len,
11179         .get_eeprom             = tg3_get_eeprom,
11180         .set_eeprom             = tg3_set_eeprom,
11181         .get_ringparam          = tg3_get_ringparam,
11182         .set_ringparam          = tg3_set_ringparam,
11183         .get_pauseparam         = tg3_get_pauseparam,
11184         .set_pauseparam         = tg3_set_pauseparam,
11185         .get_rx_csum            = tg3_get_rx_csum,
11186         .set_rx_csum            = tg3_set_rx_csum,
11187         .set_tx_csum            = tg3_set_tx_csum,
11188         .set_sg                 = ethtool_op_set_sg,
11189         .set_tso                = tg3_set_tso,
11190         .self_test              = tg3_self_test,
11191         .get_strings            = tg3_get_strings,
11192         .phys_id                = tg3_phys_id,
11193         .get_ethtool_stats      = tg3_get_ethtool_stats,
11194         .get_coalesce           = tg3_get_coalesce,
11195         .set_coalesce           = tg3_set_coalesce,
11196         .get_sset_count         = tg3_get_sset_count,
11197 };
11198
11199 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
11200 {
11201         u32 cursize, val, magic;
11202
11203         tp->nvram_size = EEPROM_CHIP_SIZE;
11204
11205         if (tg3_nvram_read(tp, 0, &magic) != 0)
11206                 return;
11207
11208         if ((magic != TG3_EEPROM_MAGIC) &&
11209             ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
11210             ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
11211                 return;
11212
11213         /*
11214          * Size the chip by reading offsets at increasing powers of two.
11215          * When we encounter our validation signature, we know the addressing
11216          * has wrapped around, and thus have our chip size.
11217          */
11218         cursize = 0x10;
11219
11220         while (cursize < tp->nvram_size) {
11221                 if (tg3_nvram_read(tp, cursize, &val) != 0)
11222                         return;
11223
11224                 if (val == magic)
11225                         break;
11226
11227                 cursize <<= 1;
11228         }
11229
11230         tp->nvram_size = cursize;
11231 }
11232
11233 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
11234 {
11235         u32 val;
11236
11237         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
11238             tg3_nvram_read(tp, 0, &val) != 0)
11239                 return;
11240
11241         /* Selfboot format */
11242         if (val != TG3_EEPROM_MAGIC) {
11243                 tg3_get_eeprom_size(tp);
11244                 return;
11245         }
11246
11247         if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
11248                 if (val != 0) {
11249                         /* This is confusing.  We want to operate on the
11250                          * 16-bit value at offset 0xf2.  The tg3_nvram_read()
11251                          * call will read from NVRAM and byteswap the data
11252                          * according to the byteswapping settings for all
11253                          * other register accesses.  This ensures the data we
11254                          * want will always reside in the lower 16-bits.
11255                          * However, the data in NVRAM is in LE format, which
11256                          * means the data from the NVRAM read will always be
11257                          * opposite the endianness of the CPU.  The 16-bit
11258                          * byteswap then brings the data to CPU endianness.
11259                          */
11260                         tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
11261                         return;
11262                 }
11263         }
11264         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11265 }
11266
11267 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
11268 {
11269         u32 nvcfg1;
11270
11271         nvcfg1 = tr32(NVRAM_CFG1);
11272         if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
11273                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11274         } else {
11275                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11276                 tw32(NVRAM_CFG1, nvcfg1);
11277         }
11278
11279         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
11280             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
11281                 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
11282                 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
11283                         tp->nvram_jedecnum = JEDEC_ATMEL;
11284                         tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11285                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11286                         break;
11287                 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
11288                         tp->nvram_jedecnum = JEDEC_ATMEL;
11289                         tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
11290                         break;
11291                 case FLASH_VENDOR_ATMEL_EEPROM:
11292                         tp->nvram_jedecnum = JEDEC_ATMEL;
11293                         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11294                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11295                         break;
11296                 case FLASH_VENDOR_ST:
11297                         tp->nvram_jedecnum = JEDEC_ST;
11298                         tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
11299                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11300                         break;
11301                 case FLASH_VENDOR_SAIFUN:
11302                         tp->nvram_jedecnum = JEDEC_SAIFUN;
11303                         tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
11304                         break;
11305                 case FLASH_VENDOR_SST_SMALL:
11306                 case FLASH_VENDOR_SST_LARGE:
11307                         tp->nvram_jedecnum = JEDEC_SST;
11308                         tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
11309                         break;
11310                 }
11311         } else {
11312                 tp->nvram_jedecnum = JEDEC_ATMEL;
11313                 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11314                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11315         }
11316 }
11317
11318 static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
11319 {
11320         switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
11321         case FLASH_5752PAGE_SIZE_256:
11322                 tp->nvram_pagesize = 256;
11323                 break;
11324         case FLASH_5752PAGE_SIZE_512:
11325                 tp->nvram_pagesize = 512;
11326                 break;
11327         case FLASH_5752PAGE_SIZE_1K:
11328                 tp->nvram_pagesize = 1024;
11329                 break;
11330         case FLASH_5752PAGE_SIZE_2K:
11331                 tp->nvram_pagesize = 2048;
11332                 break;
11333         case FLASH_5752PAGE_SIZE_4K:
11334                 tp->nvram_pagesize = 4096;
11335                 break;
11336         case FLASH_5752PAGE_SIZE_264:
11337                 tp->nvram_pagesize = 264;
11338                 break;
11339         case FLASH_5752PAGE_SIZE_528:
11340                 tp->nvram_pagesize = 528;
11341                 break;
11342         }
11343 }
11344
11345 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
11346 {
11347         u32 nvcfg1;
11348
11349         nvcfg1 = tr32(NVRAM_CFG1);
11350
11351         /* NVRAM protection for TPM */
11352         if (nvcfg1 & (1 << 27))
11353                 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11354
11355         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11356         case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
11357         case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
11358                 tp->nvram_jedecnum = JEDEC_ATMEL;
11359                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11360                 break;
11361         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11362                 tp->nvram_jedecnum = JEDEC_ATMEL;
11363                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11364                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11365                 break;
11366         case FLASH_5752VENDOR_ST_M45PE10:
11367         case FLASH_5752VENDOR_ST_M45PE20:
11368         case FLASH_5752VENDOR_ST_M45PE40:
11369                 tp->nvram_jedecnum = JEDEC_ST;
11370                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11371                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11372                 break;
11373         }
11374
11375         if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
11376                 tg3_nvram_get_pagesize(tp, nvcfg1);
11377         } else {
11378                 /* For eeprom, set pagesize to maximum eeprom size */
11379                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11380
11381                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11382                 tw32(NVRAM_CFG1, nvcfg1);
11383         }
11384 }
11385
11386 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
11387 {
11388         u32 nvcfg1, protect = 0;
11389
11390         nvcfg1 = tr32(NVRAM_CFG1);
11391
11392         /* NVRAM protection for TPM */
11393         if (nvcfg1 & (1 << 27)) {
11394                 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11395                 protect = 1;
11396         }
11397
11398         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11399         switch (nvcfg1) {
11400         case FLASH_5755VENDOR_ATMEL_FLASH_1:
11401         case FLASH_5755VENDOR_ATMEL_FLASH_2:
11402         case FLASH_5755VENDOR_ATMEL_FLASH_3:
11403         case FLASH_5755VENDOR_ATMEL_FLASH_5:
11404                 tp->nvram_jedecnum = JEDEC_ATMEL;
11405                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11406                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11407                 tp->nvram_pagesize = 264;
11408                 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
11409                     nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
11410                         tp->nvram_size = (protect ? 0x3e200 :
11411                                           TG3_NVRAM_SIZE_512KB);
11412                 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
11413                         tp->nvram_size = (protect ? 0x1f200 :
11414                                           TG3_NVRAM_SIZE_256KB);
11415                 else
11416                         tp->nvram_size = (protect ? 0x1f200 :
11417                                           TG3_NVRAM_SIZE_128KB);
11418                 break;
11419         case FLASH_5752VENDOR_ST_M45PE10:
11420         case FLASH_5752VENDOR_ST_M45PE20:
11421         case FLASH_5752VENDOR_ST_M45PE40:
11422                 tp->nvram_jedecnum = JEDEC_ST;
11423                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11424                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11425                 tp->nvram_pagesize = 256;
11426                 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
11427                         tp->nvram_size = (protect ?
11428                                           TG3_NVRAM_SIZE_64KB :
11429                                           TG3_NVRAM_SIZE_128KB);
11430                 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
11431                         tp->nvram_size = (protect ?
11432                                           TG3_NVRAM_SIZE_64KB :
11433                                           TG3_NVRAM_SIZE_256KB);
11434                 else
11435                         tp->nvram_size = (protect ?
11436                                           TG3_NVRAM_SIZE_128KB :
11437                                           TG3_NVRAM_SIZE_512KB);
11438                 break;
11439         }
11440 }
11441
11442 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
11443 {
11444         u32 nvcfg1;
11445
11446         nvcfg1 = tr32(NVRAM_CFG1);
11447
11448         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11449         case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
11450         case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11451         case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
11452         case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11453                 tp->nvram_jedecnum = JEDEC_ATMEL;
11454                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11455                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11456
11457                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11458                 tw32(NVRAM_CFG1, nvcfg1);
11459                 break;
11460         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11461         case FLASH_5755VENDOR_ATMEL_FLASH_1:
11462         case FLASH_5755VENDOR_ATMEL_FLASH_2:
11463         case FLASH_5755VENDOR_ATMEL_FLASH_3:
11464                 tp->nvram_jedecnum = JEDEC_ATMEL;
11465                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11466                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11467                 tp->nvram_pagesize = 264;
11468                 break;
11469         case FLASH_5752VENDOR_ST_M45PE10:
11470         case FLASH_5752VENDOR_ST_M45PE20:
11471         case FLASH_5752VENDOR_ST_M45PE40:
11472                 tp->nvram_jedecnum = JEDEC_ST;
11473                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11474                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11475                 tp->nvram_pagesize = 256;
11476                 break;
11477         }
11478 }
11479
11480 static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
11481 {
11482         u32 nvcfg1, protect = 0;
11483
11484         nvcfg1 = tr32(NVRAM_CFG1);
11485
11486         /* NVRAM protection for TPM */
11487         if (nvcfg1 & (1 << 27)) {
11488                 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11489                 protect = 1;
11490         }
11491
11492         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11493         switch (nvcfg1) {
11494         case FLASH_5761VENDOR_ATMEL_ADB021D:
11495         case FLASH_5761VENDOR_ATMEL_ADB041D:
11496         case FLASH_5761VENDOR_ATMEL_ADB081D:
11497         case FLASH_5761VENDOR_ATMEL_ADB161D:
11498         case FLASH_5761VENDOR_ATMEL_MDB021D:
11499         case FLASH_5761VENDOR_ATMEL_MDB041D:
11500         case FLASH_5761VENDOR_ATMEL_MDB081D:
11501         case FLASH_5761VENDOR_ATMEL_MDB161D:
11502                 tp->nvram_jedecnum = JEDEC_ATMEL;
11503                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11504                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11505                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11506                 tp->nvram_pagesize = 256;
11507                 break;
11508         case FLASH_5761VENDOR_ST_A_M45PE20:
11509         case FLASH_5761VENDOR_ST_A_M45PE40:
11510         case FLASH_5761VENDOR_ST_A_M45PE80:
11511         case FLASH_5761VENDOR_ST_A_M45PE16:
11512         case FLASH_5761VENDOR_ST_M_M45PE20:
11513         case FLASH_5761VENDOR_ST_M_M45PE40:
11514         case FLASH_5761VENDOR_ST_M_M45PE80:
11515         case FLASH_5761VENDOR_ST_M_M45PE16:
11516                 tp->nvram_jedecnum = JEDEC_ST;
11517                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11518                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11519                 tp->nvram_pagesize = 256;
11520                 break;
11521         }
11522
11523         if (protect) {
11524                 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
11525         } else {
11526                 switch (nvcfg1) {
11527                 case FLASH_5761VENDOR_ATMEL_ADB161D:
11528                 case FLASH_5761VENDOR_ATMEL_MDB161D:
11529                 case FLASH_5761VENDOR_ST_A_M45PE16:
11530                 case FLASH_5761VENDOR_ST_M_M45PE16:
11531                         tp->nvram_size = TG3_NVRAM_SIZE_2MB;
11532                         break;
11533                 case FLASH_5761VENDOR_ATMEL_ADB081D:
11534                 case FLASH_5761VENDOR_ATMEL_MDB081D:
11535                 case FLASH_5761VENDOR_ST_A_M45PE80:
11536                 case FLASH_5761VENDOR_ST_M_M45PE80:
11537                         tp->nvram_size = TG3_NVRAM_SIZE_1MB;
11538                         break;
11539                 case FLASH_5761VENDOR_ATMEL_ADB041D:
11540                 case FLASH_5761VENDOR_ATMEL_MDB041D:
11541                 case FLASH_5761VENDOR_ST_A_M45PE40:
11542                 case FLASH_5761VENDOR_ST_M_M45PE40:
11543                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11544                         break;
11545                 case FLASH_5761VENDOR_ATMEL_ADB021D:
11546                 case FLASH_5761VENDOR_ATMEL_MDB021D:
11547                 case FLASH_5761VENDOR_ST_A_M45PE20:
11548                 case FLASH_5761VENDOR_ST_M_M45PE20:
11549                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11550                         break;
11551                 }
11552         }
11553 }
11554
11555 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
11556 {
11557         tp->nvram_jedecnum = JEDEC_ATMEL;
11558         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11559         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11560 }
11561
11562 static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
11563 {
11564         u32 nvcfg1;
11565
11566         nvcfg1 = tr32(NVRAM_CFG1);
11567
11568         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11569         case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11570         case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11571                 tp->nvram_jedecnum = JEDEC_ATMEL;
11572                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11573                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11574
11575                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11576                 tw32(NVRAM_CFG1, nvcfg1);
11577                 return;
11578         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11579         case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11580         case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11581         case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11582         case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11583         case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11584         case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11585                 tp->nvram_jedecnum = JEDEC_ATMEL;
11586                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11587                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11588
11589                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11590                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11591                 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11592                 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11593                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11594                         break;
11595                 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11596                 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11597                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11598                         break;
11599                 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11600                 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11601                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11602                         break;
11603                 }
11604                 break;
11605         case FLASH_5752VENDOR_ST_M45PE10:
11606         case FLASH_5752VENDOR_ST_M45PE20:
11607         case FLASH_5752VENDOR_ST_M45PE40:
11608                 tp->nvram_jedecnum = JEDEC_ST;
11609                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11610                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11611
11612                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11613                 case FLASH_5752VENDOR_ST_M45PE10:
11614                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11615                         break;
11616                 case FLASH_5752VENDOR_ST_M45PE20:
11617                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11618                         break;
11619                 case FLASH_5752VENDOR_ST_M45PE40:
11620                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11621                         break;
11622                 }
11623                 break;
11624         default:
11625                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11626                 return;
11627         }
11628
11629         tg3_nvram_get_pagesize(tp, nvcfg1);
11630         if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11631                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11632 }
11633
11634
11635 static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp)
11636 {
11637         u32 nvcfg1;
11638
11639         nvcfg1 = tr32(NVRAM_CFG1);
11640
11641         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11642         case FLASH_5717VENDOR_ATMEL_EEPROM:
11643         case FLASH_5717VENDOR_MICRO_EEPROM:
11644                 tp->nvram_jedecnum = JEDEC_ATMEL;
11645                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11646                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11647
11648                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11649                 tw32(NVRAM_CFG1, nvcfg1);
11650                 return;
11651         case FLASH_5717VENDOR_ATMEL_MDB011D:
11652         case FLASH_5717VENDOR_ATMEL_ADB011B:
11653         case FLASH_5717VENDOR_ATMEL_ADB011D:
11654         case FLASH_5717VENDOR_ATMEL_MDB021D:
11655         case FLASH_5717VENDOR_ATMEL_ADB021B:
11656         case FLASH_5717VENDOR_ATMEL_ADB021D:
11657         case FLASH_5717VENDOR_ATMEL_45USPT:
11658                 tp->nvram_jedecnum = JEDEC_ATMEL;
11659                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11660                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11661
11662                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11663                 case FLASH_5717VENDOR_ATMEL_MDB021D:
11664                 case FLASH_5717VENDOR_ATMEL_ADB021B:
11665                 case FLASH_5717VENDOR_ATMEL_ADB021D:
11666                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11667                         break;
11668                 default:
11669                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11670                         break;
11671                 }
11672                 break;
11673         case FLASH_5717VENDOR_ST_M_M25PE10:
11674         case FLASH_5717VENDOR_ST_A_M25PE10:
11675         case FLASH_5717VENDOR_ST_M_M45PE10:
11676         case FLASH_5717VENDOR_ST_A_M45PE10:
11677         case FLASH_5717VENDOR_ST_M_M25PE20:
11678         case FLASH_5717VENDOR_ST_A_M25PE20:
11679         case FLASH_5717VENDOR_ST_M_M45PE20:
11680         case FLASH_5717VENDOR_ST_A_M45PE20:
11681         case FLASH_5717VENDOR_ST_25USPT:
11682         case FLASH_5717VENDOR_ST_45USPT:
11683                 tp->nvram_jedecnum = JEDEC_ST;
11684                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11685                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11686
11687                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11688                 case FLASH_5717VENDOR_ST_M_M25PE20:
11689                 case FLASH_5717VENDOR_ST_A_M25PE20:
11690                 case FLASH_5717VENDOR_ST_M_M45PE20:
11691                 case FLASH_5717VENDOR_ST_A_M45PE20:
11692                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11693                         break;
11694                 default:
11695                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11696                         break;
11697                 }
11698                 break;
11699         default:
11700                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11701                 return;
11702         }
11703
11704         tg3_nvram_get_pagesize(tp, nvcfg1);
11705         if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11706                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11707 }
11708
11709 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
11710 static void __devinit tg3_nvram_init(struct tg3 *tp)
11711 {
11712         tw32_f(GRC_EEPROM_ADDR,
11713              (EEPROM_ADDR_FSM_RESET |
11714               (EEPROM_DEFAULT_CLOCK_PERIOD <<
11715                EEPROM_ADDR_CLKPERD_SHIFT)));
11716
11717         msleep(1);
11718
11719         /* Enable seeprom accesses. */
11720         tw32_f(GRC_LOCAL_CTRL,
11721              tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
11722         udelay(100);
11723
11724         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11725             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
11726                 tp->tg3_flags |= TG3_FLAG_NVRAM;
11727
11728                 if (tg3_nvram_lock(tp)) {
11729                         printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
11730                                "tg3_nvram_init failed.\n", tp->dev->name);
11731                         return;
11732                 }
11733                 tg3_enable_nvram_access(tp);
11734
11735                 tp->nvram_size = 0;
11736
11737                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
11738                         tg3_get_5752_nvram_info(tp);
11739                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
11740                         tg3_get_5755_nvram_info(tp);
11741                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
11742                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11743                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11744                         tg3_get_5787_nvram_info(tp);
11745                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
11746                         tg3_get_5761_nvram_info(tp);
11747                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11748                         tg3_get_5906_nvram_info(tp);
11749                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
11750                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
11751                         tg3_get_57780_nvram_info(tp);
11752                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
11753                         tg3_get_5717_nvram_info(tp);
11754                 else
11755                         tg3_get_nvram_info(tp);
11756
11757                 if (tp->nvram_size == 0)
11758                         tg3_get_nvram_size(tp);
11759
11760                 tg3_disable_nvram_access(tp);
11761                 tg3_nvram_unlock(tp);
11762
11763         } else {
11764                 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
11765
11766                 tg3_get_eeprom_size(tp);
11767         }
11768 }
11769
11770 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
11771                                     u32 offset, u32 len, u8 *buf)
11772 {
11773         int i, j, rc = 0;
11774         u32 val;
11775
11776         for (i = 0; i < len; i += 4) {
11777                 u32 addr;
11778                 __be32 data;
11779
11780                 addr = offset + i;
11781
11782                 memcpy(&data, buf + i, 4);
11783
11784                 /*
11785                  * The SEEPROM interface expects the data to always be opposite
11786                  * the native endian format.  We accomplish this by reversing
11787                  * all the operations that would have been performed on the
11788                  * data from a call to tg3_nvram_read_be32().
11789                  */
11790                 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
11791
11792                 val = tr32(GRC_EEPROM_ADDR);
11793                 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
11794
11795                 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
11796                         EEPROM_ADDR_READ);
11797                 tw32(GRC_EEPROM_ADDR, val |
11798                         (0 << EEPROM_ADDR_DEVID_SHIFT) |
11799                         (addr & EEPROM_ADDR_ADDR_MASK) |
11800                         EEPROM_ADDR_START |
11801                         EEPROM_ADDR_WRITE);
11802
11803                 for (j = 0; j < 1000; j++) {
11804                         val = tr32(GRC_EEPROM_ADDR);
11805
11806                         if (val & EEPROM_ADDR_COMPLETE)
11807                                 break;
11808                         msleep(1);
11809                 }
11810                 if (!(val & EEPROM_ADDR_COMPLETE)) {
11811                         rc = -EBUSY;
11812                         break;
11813                 }
11814         }
11815
11816         return rc;
11817 }
11818
11819 /* offset and length are dword aligned */
11820 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
11821                 u8 *buf)
11822 {
11823         int ret = 0;
11824         u32 pagesize = tp->nvram_pagesize;
11825         u32 pagemask = pagesize - 1;
11826         u32 nvram_cmd;
11827         u8 *tmp;
11828
11829         tmp = kmalloc(pagesize, GFP_KERNEL);
11830         if (tmp == NULL)
11831                 return -ENOMEM;
11832
11833         while (len) {
11834                 int j;
11835                 u32 phy_addr, page_off, size;
11836
11837                 phy_addr = offset & ~pagemask;
11838
11839                 for (j = 0; j < pagesize; j += 4) {
11840                         ret = tg3_nvram_read_be32(tp, phy_addr + j,
11841                                                   (__be32 *) (tmp + j));
11842                         if (ret)
11843                                 break;
11844                 }
11845                 if (ret)
11846                         break;
11847
11848                 page_off = offset & pagemask;
11849                 size = pagesize;
11850                 if (len < size)
11851                         size = len;
11852
11853                 len -= size;
11854
11855                 memcpy(tmp + page_off, buf, size);
11856
11857                 offset = offset + (pagesize - page_off);
11858
11859                 tg3_enable_nvram_access(tp);
11860
11861                 /*
11862                  * Before we can erase the flash page, we need
11863                  * to issue a special "write enable" command.
11864                  */
11865                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11866
11867                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11868                         break;
11869
11870                 /* Erase the target page */
11871                 tw32(NVRAM_ADDR, phy_addr);
11872
11873                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
11874                         NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
11875
11876                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11877                         break;
11878
11879                 /* Issue another write enable to start the write. */
11880                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11881
11882                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11883                         break;
11884
11885                 for (j = 0; j < pagesize; j += 4) {
11886                         __be32 data;
11887
11888                         data = *((__be32 *) (tmp + j));
11889
11890                         tw32(NVRAM_WRDATA, be32_to_cpu(data));
11891
11892                         tw32(NVRAM_ADDR, phy_addr + j);
11893
11894                         nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
11895                                 NVRAM_CMD_WR;
11896
11897                         if (j == 0)
11898                                 nvram_cmd |= NVRAM_CMD_FIRST;
11899                         else if (j == (pagesize - 4))
11900                                 nvram_cmd |= NVRAM_CMD_LAST;
11901
11902                         if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11903                                 break;
11904                 }
11905                 if (ret)
11906                         break;
11907         }
11908
11909         nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11910         tg3_nvram_exec_cmd(tp, nvram_cmd);
11911
11912         kfree(tmp);
11913
11914         return ret;
11915 }
11916
11917 /* offset and length are dword aligned */
11918 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
11919                 u8 *buf)
11920 {
11921         int i, ret = 0;
11922
11923         for (i = 0; i < len; i += 4, offset += 4) {
11924                 u32 page_off, phy_addr, nvram_cmd;
11925                 __be32 data;
11926
11927                 memcpy(&data, buf + i, 4);
11928                 tw32(NVRAM_WRDATA, be32_to_cpu(data));
11929
11930                 page_off = offset % tp->nvram_pagesize;
11931
11932                 phy_addr = tg3_nvram_phys_addr(tp, offset);
11933
11934                 tw32(NVRAM_ADDR, phy_addr);
11935
11936                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
11937
11938                 if ((page_off == 0) || (i == 0))
11939                         nvram_cmd |= NVRAM_CMD_FIRST;
11940                 if (page_off == (tp->nvram_pagesize - 4))
11941                         nvram_cmd |= NVRAM_CMD_LAST;
11942
11943                 if (i == (len - 4))
11944                         nvram_cmd |= NVRAM_CMD_LAST;
11945
11946                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
11947                     !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
11948                     (tp->nvram_jedecnum == JEDEC_ST) &&
11949                     (nvram_cmd & NVRAM_CMD_FIRST)) {
11950
11951                         if ((ret = tg3_nvram_exec_cmd(tp,
11952                                 NVRAM_CMD_WREN | NVRAM_CMD_GO |
11953                                 NVRAM_CMD_DONE)))
11954
11955                                 break;
11956                 }
11957                 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11958                         /* We always do complete word writes to eeprom. */
11959                         nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
11960                 }
11961
11962                 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11963                         break;
11964         }
11965         return ret;
11966 }
11967
11968 /* offset and length are dword aligned */
11969 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
11970 {
11971         int ret;
11972
11973         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
11974                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
11975                        ~GRC_LCLCTRL_GPIO_OUTPUT1);
11976                 udelay(40);
11977         }
11978
11979         if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
11980                 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
11981         }
11982         else {
11983                 u32 grc_mode;
11984
11985                 ret = tg3_nvram_lock(tp);
11986                 if (ret)
11987                         return ret;
11988
11989                 tg3_enable_nvram_access(tp);
11990                 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
11991                     !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM))
11992                         tw32(NVRAM_WRITE1, 0x406);
11993
11994                 grc_mode = tr32(GRC_MODE);
11995                 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
11996
11997                 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
11998                         !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11999
12000                         ret = tg3_nvram_write_block_buffered(tp, offset, len,
12001                                 buf);
12002                 }
12003                 else {
12004                         ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
12005                                 buf);
12006                 }
12007
12008                 grc_mode = tr32(GRC_MODE);
12009                 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
12010
12011                 tg3_disable_nvram_access(tp);
12012                 tg3_nvram_unlock(tp);
12013         }
12014
12015         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
12016                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
12017                 udelay(40);
12018         }
12019
12020         return ret;
12021 }
12022
12023 struct subsys_tbl_ent {
12024         u16 subsys_vendor, subsys_devid;
12025         u32 phy_id;
12026 };
12027
12028 static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
12029         /* Broadcom boards. */
12030         { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
12031         { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
12032         { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
12033         { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 },              /* BCM95700A9 */
12034         { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
12035         { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
12036         { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 },              /* BCM95701A7 */
12037         { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
12038         { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
12039         { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
12040         { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
12041
12042         /* 3com boards. */
12043         { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
12044         { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
12045         { PCI_VENDOR_ID_3COM, 0x1004, 0 },              /* 3C996SX */
12046         { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
12047         { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
12048
12049         /* DELL boards. */
12050         { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
12051         { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
12052         { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
12053         { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
12054
12055         /* Compaq boards. */
12056         { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
12057         { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
12058         { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 },              /* CHANGELING */
12059         { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
12060         { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
12061
12062         /* IBM boards. */
12063         { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
12064 };
12065
12066 static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
12067 {
12068         int i;
12069
12070         for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
12071                 if ((subsys_id_to_phy_id[i].subsys_vendor ==
12072                      tp->pdev->subsystem_vendor) &&
12073                     (subsys_id_to_phy_id[i].subsys_devid ==
12074                      tp->pdev->subsystem_device))
12075                         return &subsys_id_to_phy_id[i];
12076         }
12077         return NULL;
12078 }
12079
12080 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
12081 {
12082         u32 val;
12083         u16 pmcsr;
12084
12085         /* On some early chips the SRAM cannot be accessed in D3hot state,
12086          * so need make sure we're in D0.
12087          */
12088         pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
12089         pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
12090         pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
12091         msleep(1);
12092
12093         /* Make sure register accesses (indirect or otherwise)
12094          * will function correctly.
12095          */
12096         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12097                                tp->misc_host_ctrl);
12098
12099         /* The memory arbiter has to be enabled in order for SRAM accesses
12100          * to succeed.  Normally on powerup the tg3 chip firmware will make
12101          * sure it is enabled, but other entities such as system netboot
12102          * code might disable it.
12103          */
12104         val = tr32(MEMARB_MODE);
12105         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
12106
12107         tp->phy_id = PHY_ID_INVALID;
12108         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12109
12110         /* Assume an onboard device and WOL capable by default.  */
12111         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
12112
12113         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12114                 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
12115                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12116                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12117                 }
12118                 val = tr32(VCPU_CFGSHDW);
12119                 if (val & VCPU_CFGSHDW_ASPM_DBNC)
12120                         tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
12121                 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
12122                     (val & VCPU_CFGSHDW_WOL_MAGPKT))
12123                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12124                 goto done;
12125         }
12126
12127         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
12128         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
12129                 u32 nic_cfg, led_cfg;
12130                 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
12131                 int eeprom_phy_serdes = 0;
12132
12133                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
12134                 tp->nic_sram_data_cfg = nic_cfg;
12135
12136                 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
12137                 ver >>= NIC_SRAM_DATA_VER_SHIFT;
12138                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
12139                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
12140                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
12141                     (ver > 0) && (ver < 0x100))
12142                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
12143
12144                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
12145                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
12146
12147                 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
12148                     NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
12149                         eeprom_phy_serdes = 1;
12150
12151                 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
12152                 if (nic_phy_id != 0) {
12153                         u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
12154                         u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
12155
12156                         eeprom_phy_id  = (id1 >> 16) << 10;
12157                         eeprom_phy_id |= (id2 & 0xfc00) << 16;
12158                         eeprom_phy_id |= (id2 & 0x03ff) <<  0;
12159                 } else
12160                         eeprom_phy_id = 0;
12161
12162                 tp->phy_id = eeprom_phy_id;
12163                 if (eeprom_phy_serdes) {
12164                         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
12165                                 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
12166                         else
12167                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12168                 }
12169
12170                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
12171                         led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
12172                                     SHASTA_EXT_LED_MODE_MASK);
12173                 else
12174                         led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
12175
12176                 switch (led_cfg) {
12177                 default:
12178                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
12179                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12180                         break;
12181
12182                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
12183                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12184                         break;
12185
12186                 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
12187                         tp->led_ctrl = LED_CTRL_MODE_MAC;
12188
12189                         /* Default to PHY_1_MODE if 0 (MAC_MODE) is
12190                          * read on some older 5700/5701 bootcode.
12191                          */
12192                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
12193                             ASIC_REV_5700 ||
12194                             GET_ASIC_REV(tp->pci_chip_rev_id) ==
12195                             ASIC_REV_5701)
12196                                 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12197
12198                         break;
12199
12200                 case SHASTA_EXT_LED_SHARED:
12201                         tp->led_ctrl = LED_CTRL_MODE_SHARED;
12202                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
12203                             tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
12204                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12205                                                  LED_CTRL_MODE_PHY_2);
12206                         break;
12207
12208                 case SHASTA_EXT_LED_MAC:
12209                         tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
12210                         break;
12211
12212                 case SHASTA_EXT_LED_COMBO:
12213                         tp->led_ctrl = LED_CTRL_MODE_COMBO;
12214                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
12215                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12216                                                  LED_CTRL_MODE_PHY_2);
12217                         break;
12218
12219                 }
12220
12221                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12222                      GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
12223                     tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
12224                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12225
12226                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
12227                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12228
12229                 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
12230                         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
12231                         if ((tp->pdev->subsystem_vendor ==
12232                              PCI_VENDOR_ID_ARIMA) &&
12233                             (tp->pdev->subsystem_device == 0x205a ||
12234                              tp->pdev->subsystem_device == 0x2063))
12235                                 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12236                 } else {
12237                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12238                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12239                 }
12240
12241                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
12242                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
12243                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
12244                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
12245                 }
12246
12247                 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
12248                         (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
12249                         tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
12250
12251                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
12252                     !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
12253                         tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
12254
12255                 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
12256                     (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
12257                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12258
12259                 if (cfg2 & (1 << 17))
12260                         tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
12261
12262                 /* serdes signal pre-emphasis in register 0x590 set by */
12263                 /* bootcode if bit 18 is set */
12264                 if (cfg2 & (1 << 18))
12265                         tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
12266
12267                 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12268                       GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
12269                     (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
12270                         tp->tg3_flags3 |= TG3_FLG3_PHY_ENABLE_APD;
12271
12272                 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12273                         u32 cfg3;
12274
12275                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
12276                         if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
12277                                 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
12278                 }
12279
12280                 if (cfg4 & NIC_SRAM_RGMII_STD_IBND_DISABLE)
12281                         tp->tg3_flags3 |= TG3_FLG3_RGMII_STD_IBND_DISABLE;
12282                 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
12283                         tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
12284                 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
12285                         tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
12286         }
12287 done:
12288         device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
12289         device_set_wakeup_enable(&tp->pdev->dev,
12290                                  tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
12291 }
12292
12293 static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
12294 {
12295         int i;
12296         u32 val;
12297
12298         tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
12299         tw32(OTP_CTRL, cmd);
12300
12301         /* Wait for up to 1 ms for command to execute. */
12302         for (i = 0; i < 100; i++) {
12303                 val = tr32(OTP_STATUS);
12304                 if (val & OTP_STATUS_CMD_DONE)
12305                         break;
12306                 udelay(10);
12307         }
12308
12309         return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
12310 }
12311
12312 /* Read the gphy configuration from the OTP region of the chip.  The gphy
12313  * configuration is a 32-bit value that straddles the alignment boundary.
12314  * We do two 32-bit reads and then shift and merge the results.
12315  */
12316 static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
12317 {
12318         u32 bhalf_otp, thalf_otp;
12319
12320         tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
12321
12322         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
12323                 return 0;
12324
12325         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
12326
12327         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12328                 return 0;
12329
12330         thalf_otp = tr32(OTP_READ_DATA);
12331
12332         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
12333
12334         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12335                 return 0;
12336
12337         bhalf_otp = tr32(OTP_READ_DATA);
12338
12339         return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
12340 }
12341
12342 static int __devinit tg3_phy_probe(struct tg3 *tp)
12343 {
12344         u32 hw_phy_id_1, hw_phy_id_2;
12345         u32 hw_phy_id, hw_phy_id_masked;
12346         int err;
12347
12348         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
12349                 return tg3_phy_init(tp);
12350
12351         /* Reading the PHY ID register can conflict with ASF
12352          * firmware access to the PHY hardware.
12353          */
12354         err = 0;
12355         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12356             (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
12357                 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
12358         } else {
12359                 /* Now read the physical PHY_ID from the chip and verify
12360                  * that it is sane.  If it doesn't look good, we fall back
12361                  * to either the hard-coded table based PHY_ID and failing
12362                  * that the value found in the eeprom area.
12363                  */
12364                 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
12365                 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
12366
12367                 hw_phy_id  = (hw_phy_id_1 & 0xffff) << 10;
12368                 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
12369                 hw_phy_id |= (hw_phy_id_2 & 0x03ff) <<  0;
12370
12371                 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
12372         }
12373
12374         if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
12375                 tp->phy_id = hw_phy_id;
12376                 if (hw_phy_id_masked == PHY_ID_BCM8002)
12377                         tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12378                 else
12379                         tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
12380         } else {
12381                 if (tp->phy_id != PHY_ID_INVALID) {
12382                         /* Do nothing, phy ID already set up in
12383                          * tg3_get_eeprom_hw_cfg().
12384                          */
12385                 } else {
12386                         struct subsys_tbl_ent *p;
12387
12388                         /* No eeprom signature?  Try the hardcoded
12389                          * subsys device table.
12390                          */
12391                         p = lookup_by_subsys(tp);
12392                         if (!p)
12393                                 return -ENODEV;
12394
12395                         tp->phy_id = p->phy_id;
12396                         if (!tp->phy_id ||
12397                             tp->phy_id == PHY_ID_BCM8002)
12398                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12399                 }
12400         }
12401
12402         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
12403             !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
12404             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
12405                 u32 bmsr, adv_reg, tg3_ctrl, mask;
12406
12407                 tg3_readphy(tp, MII_BMSR, &bmsr);
12408                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
12409                     (bmsr & BMSR_LSTATUS))
12410                         goto skip_phy_reset;
12411
12412                 err = tg3_phy_reset(tp);
12413                 if (err)
12414                         return err;
12415
12416                 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
12417                            ADVERTISE_100HALF | ADVERTISE_100FULL |
12418                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
12419                 tg3_ctrl = 0;
12420                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
12421                         tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
12422                                     MII_TG3_CTRL_ADV_1000_FULL);
12423                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12424                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
12425                                 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
12426                                              MII_TG3_CTRL_ENABLE_AS_MASTER);
12427                 }
12428
12429                 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
12430                         ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
12431                         ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
12432                 if (!tg3_copper_is_advertising_all(tp, mask)) {
12433                         tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12434
12435                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
12436                                 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12437
12438                         tg3_writephy(tp, MII_BMCR,
12439                                      BMCR_ANENABLE | BMCR_ANRESTART);
12440                 }
12441                 tg3_phy_set_wirespeed(tp);
12442
12443                 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12444                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
12445                         tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12446         }
12447
12448 skip_phy_reset:
12449         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
12450                 err = tg3_init_5401phy_dsp(tp);
12451                 if (err)
12452                         return err;
12453         }
12454
12455         if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
12456                 err = tg3_init_5401phy_dsp(tp);
12457         }
12458
12459         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
12460                 tp->link_config.advertising =
12461                         (ADVERTISED_1000baseT_Half |
12462                          ADVERTISED_1000baseT_Full |
12463                          ADVERTISED_Autoneg |
12464                          ADVERTISED_FIBRE);
12465         if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
12466                 tp->link_config.advertising &=
12467                         ~(ADVERTISED_1000baseT_Half |
12468                           ADVERTISED_1000baseT_Full);
12469
12470         return err;
12471 }
12472
12473 static void __devinit tg3_read_partno(struct tg3 *tp)
12474 {
12475         unsigned char vpd_data[TG3_NVM_VPD_LEN];   /* in little-endian format */
12476         unsigned int i;
12477         u32 magic;
12478
12479         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
12480             tg3_nvram_read(tp, 0x0, &magic))
12481                 goto out_not_found;
12482
12483         if (magic == TG3_EEPROM_MAGIC) {
12484                 for (i = 0; i < TG3_NVM_VPD_LEN; i += 4) {
12485                         u32 tmp;
12486
12487                         /* The data is in little-endian format in NVRAM.
12488                          * Use the big-endian read routines to preserve
12489                          * the byte order as it exists in NVRAM.
12490                          */
12491                         if (tg3_nvram_read_be32(tp, TG3_NVM_VPD_OFF + i, &tmp))
12492                                 goto out_not_found;
12493
12494                         memcpy(&vpd_data[i], &tmp, sizeof(tmp));
12495                 }
12496         } else {
12497                 ssize_t cnt;
12498                 unsigned int pos = 0, i = 0;
12499
12500                 for (; pos < TG3_NVM_VPD_LEN && i < 3; i++, pos += cnt) {
12501                         cnt = pci_read_vpd(tp->pdev, pos,
12502                                            TG3_NVM_VPD_LEN - pos,
12503                                            &vpd_data[pos]);
12504                         if (cnt == -ETIMEDOUT || -EINTR)
12505                                 cnt = 0;
12506                         else if (cnt < 0)
12507                                 goto out_not_found;
12508                 }
12509                 if (pos != TG3_NVM_VPD_LEN)
12510                         goto out_not_found;
12511         }
12512
12513         /* Now parse and find the part number. */
12514         for (i = 0; i < TG3_NVM_VPD_LEN - 2; ) {
12515                 unsigned char val = vpd_data[i];
12516                 unsigned int block_end;
12517
12518                 if (val == 0x82 || val == 0x91) {
12519                         i = (i + 3 +
12520                              (vpd_data[i + 1] +
12521                               (vpd_data[i + 2] << 8)));
12522                         continue;
12523                 }
12524
12525                 if (val != 0x90)
12526                         goto out_not_found;
12527
12528                 block_end = (i + 3 +
12529                              (vpd_data[i + 1] +
12530                               (vpd_data[i + 2] << 8)));
12531                 i += 3;
12532
12533                 if (block_end > TG3_NVM_VPD_LEN)
12534                         goto out_not_found;
12535
12536                 while (i < (block_end - 2)) {
12537                         if (vpd_data[i + 0] == 'P' &&
12538                             vpd_data[i + 1] == 'N') {
12539                                 int partno_len = vpd_data[i + 2];
12540
12541                                 i += 3;
12542                                 if (partno_len > TG3_BPN_SIZE ||
12543                                     (partno_len + i) > TG3_NVM_VPD_LEN)
12544                                         goto out_not_found;
12545
12546                                 memcpy(tp->board_part_number,
12547                                        &vpd_data[i], partno_len);
12548
12549                                 /* Success. */
12550                                 return;
12551                         }
12552                         i += 3 + vpd_data[i + 2];
12553                 }
12554
12555                 /* Part number not found. */
12556                 goto out_not_found;
12557         }
12558
12559 out_not_found:
12560         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12561                 strcpy(tp->board_part_number, "BCM95906");
12562         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12563                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
12564                 strcpy(tp->board_part_number, "BCM57780");
12565         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12566                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
12567                 strcpy(tp->board_part_number, "BCM57760");
12568         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12569                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
12570                 strcpy(tp->board_part_number, "BCM57790");
12571         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12572                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
12573                 strcpy(tp->board_part_number, "BCM57788");
12574         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
12575                 strcpy(tp->board_part_number, "BCM57765");
12576         else
12577                 strcpy(tp->board_part_number, "none");
12578 }
12579
12580 static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
12581 {
12582         u32 val;
12583
12584         if (tg3_nvram_read(tp, offset, &val) ||
12585             (val & 0xfc000000) != 0x0c000000 ||
12586             tg3_nvram_read(tp, offset + 4, &val) ||
12587             val != 0)
12588                 return 0;
12589
12590         return 1;
12591 }
12592
12593 static void __devinit tg3_read_bc_ver(struct tg3 *tp)
12594 {
12595         u32 val, offset, start, ver_offset;
12596         int i;
12597         bool newver = false;
12598
12599         if (tg3_nvram_read(tp, 0xc, &offset) ||
12600             tg3_nvram_read(tp, 0x4, &start))
12601                 return;
12602
12603         offset = tg3_nvram_logical_addr(tp, offset);
12604
12605         if (tg3_nvram_read(tp, offset, &val))
12606                 return;
12607
12608         if ((val & 0xfc000000) == 0x0c000000) {
12609                 if (tg3_nvram_read(tp, offset + 4, &val))
12610                         return;
12611
12612                 if (val == 0)
12613                         newver = true;
12614         }
12615
12616         if (newver) {
12617                 if (tg3_nvram_read(tp, offset + 8, &ver_offset))
12618                         return;
12619
12620                 offset = offset + ver_offset - start;
12621                 for (i = 0; i < 16; i += 4) {
12622                         __be32 v;
12623                         if (tg3_nvram_read_be32(tp, offset + i, &v))
12624                                 return;
12625
12626                         memcpy(tp->fw_ver + i, &v, sizeof(v));
12627                 }
12628         } else {
12629                 u32 major, minor;
12630
12631                 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
12632                         return;
12633
12634                 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
12635                         TG3_NVM_BCVER_MAJSFT;
12636                 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
12637                 snprintf(&tp->fw_ver[0], 32, "v%d.%02d", major, minor);
12638         }
12639 }
12640
12641 static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
12642 {
12643         u32 val, major, minor;
12644
12645         /* Use native endian representation */
12646         if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
12647                 return;
12648
12649         major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
12650                 TG3_NVM_HWSB_CFG1_MAJSFT;
12651         minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
12652                 TG3_NVM_HWSB_CFG1_MINSFT;
12653
12654         snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
12655 }
12656
12657 static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
12658 {
12659         u32 offset, major, minor, build;
12660
12661         tp->fw_ver[0] = 's';
12662         tp->fw_ver[1] = 'b';
12663         tp->fw_ver[2] = '\0';
12664
12665         if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
12666                 return;
12667
12668         switch (val & TG3_EEPROM_SB_REVISION_MASK) {
12669         case TG3_EEPROM_SB_REVISION_0:
12670                 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
12671                 break;
12672         case TG3_EEPROM_SB_REVISION_2:
12673                 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
12674                 break;
12675         case TG3_EEPROM_SB_REVISION_3:
12676                 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
12677                 break;
12678         default:
12679                 return;
12680         }
12681
12682         if (tg3_nvram_read(tp, offset, &val))
12683                 return;
12684
12685         build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
12686                 TG3_EEPROM_SB_EDH_BLD_SHFT;
12687         major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
12688                 TG3_EEPROM_SB_EDH_MAJ_SHFT;
12689         minor =  val & TG3_EEPROM_SB_EDH_MIN_MASK;
12690
12691         if (minor > 99 || build > 26)
12692                 return;
12693
12694         snprintf(&tp->fw_ver[2], 30, " v%d.%02d", major, minor);
12695
12696         if (build > 0) {
12697                 tp->fw_ver[8] = 'a' + build - 1;
12698                 tp->fw_ver[9] = '\0';
12699         }
12700 }
12701
12702 static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
12703 {
12704         u32 val, offset, start;
12705         int i, vlen;
12706
12707         for (offset = TG3_NVM_DIR_START;
12708              offset < TG3_NVM_DIR_END;
12709              offset += TG3_NVM_DIRENT_SIZE) {
12710                 if (tg3_nvram_read(tp, offset, &val))
12711                         return;
12712
12713                 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
12714                         break;
12715         }
12716
12717         if (offset == TG3_NVM_DIR_END)
12718                 return;
12719
12720         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
12721                 start = 0x08000000;
12722         else if (tg3_nvram_read(tp, offset - 4, &start))
12723                 return;
12724
12725         if (tg3_nvram_read(tp, offset + 4, &offset) ||
12726             !tg3_fw_img_is_valid(tp, offset) ||
12727             tg3_nvram_read(tp, offset + 8, &val))
12728                 return;
12729
12730         offset += val - start;
12731
12732         vlen = strlen(tp->fw_ver);
12733
12734         tp->fw_ver[vlen++] = ',';
12735         tp->fw_ver[vlen++] = ' ';
12736
12737         for (i = 0; i < 4; i++) {
12738                 __be32 v;
12739                 if (tg3_nvram_read_be32(tp, offset, &v))
12740                         return;
12741
12742                 offset += sizeof(v);
12743
12744                 if (vlen > TG3_VER_SIZE - sizeof(v)) {
12745                         memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
12746                         break;
12747                 }
12748
12749                 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
12750                 vlen += sizeof(v);
12751         }
12752 }
12753
12754 static void __devinit tg3_read_dash_ver(struct tg3 *tp)
12755 {
12756         int vlen;
12757         u32 apedata;
12758
12759         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) ||
12760             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
12761                 return;
12762
12763         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
12764         if (apedata != APE_SEG_SIG_MAGIC)
12765                 return;
12766
12767         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
12768         if (!(apedata & APE_FW_STATUS_READY))
12769                 return;
12770
12771         apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
12772
12773         vlen = strlen(tp->fw_ver);
12774
12775         snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " DASH v%d.%d.%d.%d",
12776                  (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
12777                  (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
12778                  (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
12779                  (apedata & APE_FW_VERSION_BLDMSK));
12780 }
12781
12782 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
12783 {
12784         u32 val;
12785
12786         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) {
12787                 tp->fw_ver[0] = 's';
12788                 tp->fw_ver[1] = 'b';
12789                 tp->fw_ver[2] = '\0';
12790
12791                 return;
12792         }
12793
12794         if (tg3_nvram_read(tp, 0, &val))
12795                 return;
12796
12797         if (val == TG3_EEPROM_MAGIC)
12798                 tg3_read_bc_ver(tp);
12799         else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
12800                 tg3_read_sb_ver(tp, val);
12801         else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
12802                 tg3_read_hwsb_ver(tp);
12803         else
12804                 return;
12805
12806         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12807              (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
12808                 return;
12809
12810         tg3_read_mgmtfw_ver(tp);
12811
12812         tp->fw_ver[TG3_VER_SIZE - 1] = 0;
12813 }
12814
12815 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
12816
12817 static int __devinit tg3_get_invariants(struct tg3 *tp)
12818 {
12819         static struct pci_device_id write_reorder_chipsets[] = {
12820                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12821                              PCI_DEVICE_ID_AMD_FE_GATE_700C) },
12822                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12823                              PCI_DEVICE_ID_AMD_8131_BRIDGE) },
12824                 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
12825                              PCI_DEVICE_ID_VIA_8385_0) },
12826                 { },
12827         };
12828         u32 misc_ctrl_reg;
12829         u32 pci_state_reg, grc_misc_cfg;
12830         u32 val;
12831         u16 pci_cmd;
12832         int err;
12833
12834         /* Force memory write invalidate off.  If we leave it on,
12835          * then on 5700_BX chips we have to enable a workaround.
12836          * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
12837          * to match the cacheline size.  The Broadcom driver have this
12838          * workaround but turns MWI off all the times so never uses
12839          * it.  This seems to suggest that the workaround is insufficient.
12840          */
12841         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12842         pci_cmd &= ~PCI_COMMAND_INVALIDATE;
12843         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12844
12845         /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
12846          * has the register indirect write enable bit set before
12847          * we try to access any of the MMIO registers.  It is also
12848          * critical that the PCI-X hw workaround situation is decided
12849          * before that as well.
12850          */
12851         pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12852                               &misc_ctrl_reg);
12853
12854         tp->pci_chip_rev_id = (misc_ctrl_reg >>
12855                                MISC_HOST_CTRL_CHIPREV_SHIFT);
12856         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
12857                 u32 prod_id_asic_rev;
12858
12859                 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
12860                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
12861                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5724)
12862                         pci_read_config_dword(tp->pdev,
12863                                               TG3PCI_GEN2_PRODID_ASICREV,
12864                                               &prod_id_asic_rev);
12865                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 ||
12866                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 ||
12867                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||
12868                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||
12869                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
12870                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
12871                         pci_read_config_dword(tp->pdev,
12872                                               TG3PCI_GEN15_PRODID_ASICREV,
12873                                               &prod_id_asic_rev);
12874                 else
12875                         pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
12876                                               &prod_id_asic_rev);
12877
12878                 tp->pci_chip_rev_id = prod_id_asic_rev;
12879         }
12880
12881         /* Wrong chip ID in 5752 A0. This code can be removed later
12882          * as A0 is not in production.
12883          */
12884         if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
12885                 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
12886
12887         /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
12888          * we need to disable memory and use config. cycles
12889          * only to access all registers. The 5702/03 chips
12890          * can mistakenly decode the special cycles from the
12891          * ICH chipsets as memory write cycles, causing corruption
12892          * of register and memory space. Only certain ICH bridges
12893          * will drive special cycles with non-zero data during the
12894          * address phase which can fall within the 5703's address
12895          * range. This is not an ICH bug as the PCI spec allows
12896          * non-zero address during special cycles. However, only
12897          * these ICH bridges are known to drive non-zero addresses
12898          * during special cycles.
12899          *
12900          * Since special cycles do not cross PCI bridges, we only
12901          * enable this workaround if the 5703 is on the secondary
12902          * bus of these ICH bridges.
12903          */
12904         if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
12905             (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
12906                 static struct tg3_dev_id {
12907                         u32     vendor;
12908                         u32     device;
12909                         u32     rev;
12910                 } ich_chipsets[] = {
12911                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
12912                           PCI_ANY_ID },
12913                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
12914                           PCI_ANY_ID },
12915                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
12916                           0xa },
12917                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
12918                           PCI_ANY_ID },
12919                         { },
12920                 };
12921                 struct tg3_dev_id *pci_id = &ich_chipsets[0];
12922                 struct pci_dev *bridge = NULL;
12923
12924                 while (pci_id->vendor != 0) {
12925                         bridge = pci_get_device(pci_id->vendor, pci_id->device,
12926                                                 bridge);
12927                         if (!bridge) {
12928                                 pci_id++;
12929                                 continue;
12930                         }
12931                         if (pci_id->rev != PCI_ANY_ID) {
12932                                 if (bridge->revision > pci_id->rev)
12933                                         continue;
12934                         }
12935                         if (bridge->subordinate &&
12936                             (bridge->subordinate->number ==
12937                              tp->pdev->bus->number)) {
12938
12939                                 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
12940                                 pci_dev_put(bridge);
12941                                 break;
12942                         }
12943                 }
12944         }
12945
12946         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
12947                 static struct tg3_dev_id {
12948                         u32     vendor;
12949                         u32     device;
12950                 } bridge_chipsets[] = {
12951                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
12952                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
12953                         { },
12954                 };
12955                 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
12956                 struct pci_dev *bridge = NULL;
12957
12958                 while (pci_id->vendor != 0) {
12959                         bridge = pci_get_device(pci_id->vendor,
12960                                                 pci_id->device,
12961                                                 bridge);
12962                         if (!bridge) {
12963                                 pci_id++;
12964                                 continue;
12965                         }
12966                         if (bridge->subordinate &&
12967                             (bridge->subordinate->number <=
12968                              tp->pdev->bus->number) &&
12969                             (bridge->subordinate->subordinate >=
12970                              tp->pdev->bus->number)) {
12971                                 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
12972                                 pci_dev_put(bridge);
12973                                 break;
12974                         }
12975                 }
12976         }
12977
12978         /* The EPB bridge inside 5714, 5715, and 5780 cannot support
12979          * DMA addresses > 40-bit. This bridge may have other additional
12980          * 57xx devices behind it in some 4-port NIC designs for example.
12981          * Any tg3 device found behind the bridge will also need the 40-bit
12982          * DMA workaround.
12983          */
12984         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
12985             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
12986                 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
12987                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
12988                 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
12989         }
12990         else {
12991                 struct pci_dev *bridge = NULL;
12992
12993                 do {
12994                         bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
12995                                                 PCI_DEVICE_ID_SERVERWORKS_EPB,
12996                                                 bridge);
12997                         if (bridge && bridge->subordinate &&
12998                             (bridge->subordinate->number <=
12999                              tp->pdev->bus->number) &&
13000                             (bridge->subordinate->subordinate >=
13001                              tp->pdev->bus->number)) {
13002                                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
13003                                 pci_dev_put(bridge);
13004                                 break;
13005                         }
13006                 } while (bridge);
13007         }
13008
13009         /* Initialize misc host control in PCI block. */
13010         tp->misc_host_ctrl |= (misc_ctrl_reg &
13011                                MISC_HOST_CTRL_CHIPREV);
13012         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13013                                tp->misc_host_ctrl);
13014
13015         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
13016             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
13017             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
13018                 tp->pdev_peer = tg3_find_peer(tp);
13019
13020         /* Intentionally exclude ASIC_REV_5906 */
13021         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13022             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13023             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13024             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13025             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13026             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13027             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13028             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13029                 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
13030
13031         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13032             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13033             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
13034             (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13035             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13036                 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
13037
13038         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
13039             (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
13040                 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
13041
13042         /* 5700 B0 chips do not support checksumming correctly due
13043          * to hardware bugs.
13044          */
13045         if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
13046                 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
13047         else {
13048                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
13049                 tp->dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
13050                 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
13051                         tp->dev->features |= NETIF_F_IPV6_CSUM;
13052         }
13053
13054         /* Determine TSO capabilities */
13055         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13056             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13057                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_3;
13058         else if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13059                  GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13060                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
13061         else if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
13062                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
13063                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 &&
13064                     tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
13065                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
13066         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13067                    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13068                    tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
13069                 tp->tg3_flags2 |= TG3_FLG2_TSO_BUG;
13070                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
13071                         tp->fw_needed = FIRMWARE_TG3TSO5;
13072                 else
13073                         tp->fw_needed = FIRMWARE_TG3TSO;
13074         }
13075
13076         tp->irq_max = 1;
13077
13078         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
13079                 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
13080                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
13081                     GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
13082                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
13083                      tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
13084                      tp->pdev_peer == tp->pdev))
13085                         tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
13086
13087                 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13088                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13089                         tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
13090                 }
13091
13092                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13093                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
13094                         tp->tg3_flags |= TG3_FLAG_SUPPORT_MSIX;
13095                         tp->irq_max = TG3_IRQ_MAX_VECS;
13096                 }
13097         }
13098
13099         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13100             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13101                 tp->tg3_flags3 |= TG3_FLG3_SHORT_DMA_BUG;
13102         else if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS)) {
13103                 tp->tg3_flags3 |= TG3_FLG3_4G_DMA_BNDRY_BUG;
13104                 tp->tg3_flags3 |= TG3_FLG3_40BIT_DMA_LIMIT_BUG;
13105         }
13106
13107         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13108             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13109                 tp->tg3_flags3 |= TG3_FLG3_USE_JUMBO_BDFLAG;
13110
13111         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
13112              (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
13113                  (tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG))
13114                 tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE;
13115
13116         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13117                               &pci_state_reg);
13118
13119         tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
13120         if (tp->pcie_cap != 0) {
13121                 u16 lnkctl;
13122
13123                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
13124
13125                 pcie_set_readrq(tp->pdev, 4096);
13126
13127                 pci_read_config_word(tp->pdev,
13128                                      tp->pcie_cap + PCI_EXP_LNKCTL,
13129                                      &lnkctl);
13130                 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
13131                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13132                                 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
13133                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13134                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13135                             tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
13136                             tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
13137                                 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
13138                 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5717_A0) {
13139                         tp->tg3_flags3 |= TG3_FLG3_L1PLLPD_EN;
13140                 }
13141         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
13142                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
13143         } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
13144                    (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13145                 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
13146                 if (!tp->pcix_cap) {
13147                         printk(KERN_ERR PFX "Cannot find PCI-X "
13148                                             "capability, aborting.\n");
13149                         return -EIO;
13150                 }
13151
13152                 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
13153                         tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
13154         }
13155
13156         /* If we have an AMD 762 or VIA K8T800 chipset, write
13157          * reordering to the mailbox registers done by the host
13158          * controller can cause major troubles.  We read back from
13159          * every mailbox register write to force the writes to be
13160          * posted to the chip in order.
13161          */
13162         if (pci_dev_present(write_reorder_chipsets) &&
13163             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13164                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
13165
13166         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
13167                              &tp->pci_cacheline_sz);
13168         pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13169                              &tp->pci_lat_timer);
13170         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13171             tp->pci_lat_timer < 64) {
13172                 tp->pci_lat_timer = 64;
13173                 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13174                                       tp->pci_lat_timer);
13175         }
13176
13177         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
13178                 /* 5700 BX chips need to have their TX producer index
13179                  * mailboxes written twice to workaround a bug.
13180                  */
13181                 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
13182
13183                 /* If we are in PCI-X mode, enable register write workaround.
13184                  *
13185                  * The workaround is to use indirect register accesses
13186                  * for all chip writes not to mailbox registers.
13187                  */
13188                 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
13189                         u32 pm_reg;
13190
13191                         tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13192
13193                         /* The chip can have it's power management PCI config
13194                          * space registers clobbered due to this bug.
13195                          * So explicitly force the chip into D0 here.
13196                          */
13197                         pci_read_config_dword(tp->pdev,
13198                                               tp->pm_cap + PCI_PM_CTRL,
13199                                               &pm_reg);
13200                         pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
13201                         pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
13202                         pci_write_config_dword(tp->pdev,
13203                                                tp->pm_cap + PCI_PM_CTRL,
13204                                                pm_reg);
13205
13206                         /* Also, force SERR#/PERR# in PCI command. */
13207                         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13208                         pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
13209                         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13210                 }
13211         }
13212
13213         if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
13214                 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
13215         if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
13216                 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
13217
13218         /* Chip-specific fixup from Broadcom driver */
13219         if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
13220             (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
13221                 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
13222                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
13223         }
13224
13225         /* Default fast path register access methods */
13226         tp->read32 = tg3_read32;
13227         tp->write32 = tg3_write32;
13228         tp->read32_mbox = tg3_read32;
13229         tp->write32_mbox = tg3_write32;
13230         tp->write32_tx_mbox = tg3_write32;
13231         tp->write32_rx_mbox = tg3_write32;
13232
13233         /* Various workaround register access methods */
13234         if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
13235                 tp->write32 = tg3_write_indirect_reg32;
13236         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
13237                  ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
13238                   tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
13239                 /*
13240                  * Back to back register writes can cause problems on these
13241                  * chips, the workaround is to read back all reg writes
13242                  * except those to mailbox regs.
13243                  *
13244                  * See tg3_write_indirect_reg32().
13245                  */
13246                 tp->write32 = tg3_write_flush_reg32;
13247         }
13248
13249         if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
13250             (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
13251                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
13252                 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
13253                         tp->write32_rx_mbox = tg3_write_flush_reg32;
13254         }
13255
13256         if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
13257                 tp->read32 = tg3_read_indirect_reg32;
13258                 tp->write32 = tg3_write_indirect_reg32;
13259                 tp->read32_mbox = tg3_read_indirect_mbox;
13260                 tp->write32_mbox = tg3_write_indirect_mbox;
13261                 tp->write32_tx_mbox = tg3_write_indirect_mbox;
13262                 tp->write32_rx_mbox = tg3_write_indirect_mbox;
13263
13264                 iounmap(tp->regs);
13265                 tp->regs = NULL;
13266
13267                 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13268                 pci_cmd &= ~PCI_COMMAND_MEMORY;
13269                 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13270         }
13271         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13272                 tp->read32_mbox = tg3_read32_mbox_5906;
13273                 tp->write32_mbox = tg3_write32_mbox_5906;
13274                 tp->write32_tx_mbox = tg3_write32_mbox_5906;
13275                 tp->write32_rx_mbox = tg3_write32_mbox_5906;
13276         }
13277
13278         if (tp->write32 == tg3_write_indirect_reg32 ||
13279             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13280              (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13281               GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
13282                 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
13283
13284         /* Get eeprom hw config before calling tg3_set_power_state().
13285          * In particular, the TG3_FLG2_IS_NIC flag must be
13286          * determined before calling tg3_set_power_state() so that
13287          * we know whether or not to switch out of Vaux power.
13288          * When the flag is set, it means that GPIO1 is used for eeprom
13289          * write protect and also implies that it is a LOM where GPIOs
13290          * are not used to switch power.
13291          */
13292         tg3_get_eeprom_hw_cfg(tp);
13293
13294         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
13295                 /* Allow reads and writes to the
13296                  * APE register and memory space.
13297                  */
13298                 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
13299                                  PCISTATE_ALLOW_APE_SHMEM_WR;
13300                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
13301                                        pci_state_reg);
13302         }
13303
13304         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13305             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13306             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13307             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13308             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13309             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13310                 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
13311
13312         /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
13313          * GPIO1 driven high will bring 5700's external PHY out of reset.
13314          * It is also used as eeprom write protect on LOMs.
13315          */
13316         tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
13317         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13318             (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
13319                 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
13320                                        GRC_LCLCTRL_GPIO_OUTPUT1);
13321         /* Unused GPIO3 must be driven as output on 5752 because there
13322          * are no pull-up resistors on unused GPIO pins.
13323          */
13324         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
13325                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
13326
13327         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13328             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
13329                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13330
13331         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
13332             tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
13333                 /* Turn off the debug UART. */
13334                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13335                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
13336                         /* Keep VMain power. */
13337                         tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
13338                                               GRC_LCLCTRL_GPIO_OUTPUT0;
13339         }
13340
13341         /* Force the chip into D0. */
13342         err = tg3_set_power_state(tp, PCI_D0);
13343         if (err) {
13344                 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
13345                        pci_name(tp->pdev));
13346                 return err;
13347         }
13348
13349         /* Derive initial jumbo mode from MTU assigned in
13350          * ether_setup() via the alloc_etherdev() call
13351          */
13352         if (tp->dev->mtu > ETH_DATA_LEN &&
13353             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13354                 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
13355
13356         /* Determine WakeOnLan speed to use. */
13357         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13358             tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
13359             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
13360             tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
13361                 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
13362         } else {
13363                 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
13364         }
13365
13366         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13367                 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
13368
13369         /* A few boards don't want Ethernet@WireSpeed phy feature */
13370         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13371             ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
13372              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
13373              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
13374             (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) ||
13375             (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
13376                 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
13377
13378         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
13379             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
13380                 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
13381         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
13382                 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
13383
13384         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
13385             !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
13386             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
13387             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 &&
13388             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
13389             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765) {
13390                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13391                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13392                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13393                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
13394                         if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
13395                             tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
13396                                 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
13397                         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
13398                                 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
13399                 } else
13400                         tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
13401         }
13402
13403         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13404             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
13405                 tp->phy_otp = tg3_read_otp_phycfg(tp);
13406                 if (tp->phy_otp == 0)
13407                         tp->phy_otp = TG3_OTP_DEFAULT;
13408         }
13409
13410         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
13411                 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
13412         else
13413                 tp->mi_mode = MAC_MI_MODE_BASE;
13414
13415         tp->coalesce_mode = 0;
13416         if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
13417             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
13418                 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
13419
13420         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13421             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
13422                 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
13423
13424         err = tg3_mdio_init(tp);
13425         if (err)
13426                 return err;
13427
13428         /* Initialize data/descriptor byte/word swapping. */
13429         val = tr32(GRC_MODE);
13430         val &= GRC_MODE_HOST_STACKUP;
13431         tw32(GRC_MODE, val | tp->grc_mode);
13432
13433         tg3_switch_clocks(tp);
13434
13435         /* Clear this out for sanity. */
13436         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
13437
13438         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13439                               &pci_state_reg);
13440         if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
13441             (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
13442                 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
13443
13444                 if (chiprevid == CHIPREV_ID_5701_A0 ||
13445                     chiprevid == CHIPREV_ID_5701_B0 ||
13446                     chiprevid == CHIPREV_ID_5701_B2 ||
13447                     chiprevid == CHIPREV_ID_5701_B5) {
13448                         void __iomem *sram_base;
13449
13450                         /* Write some dummy words into the SRAM status block
13451                          * area, see if it reads back correctly.  If the return
13452                          * value is bad, force enable the PCIX workaround.
13453                          */
13454                         sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
13455
13456                         writel(0x00000000, sram_base);
13457                         writel(0x00000000, sram_base + 4);
13458                         writel(0xffffffff, sram_base + 4);
13459                         if (readl(sram_base) != 0x00000000)
13460                                 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13461                 }
13462         }
13463
13464         udelay(50);
13465         tg3_nvram_init(tp);
13466
13467         grc_misc_cfg = tr32(GRC_MISC_CFG);
13468         grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
13469
13470         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13471             (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
13472              grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
13473                 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
13474
13475         if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
13476             (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
13477                 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
13478         if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
13479                 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
13480                                       HOSTCC_MODE_CLRTICK_TXBD);
13481
13482                 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
13483                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13484                                        tp->misc_host_ctrl);
13485         }
13486
13487         /* Preserve the APE MAC_MODE bits */
13488         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
13489                 tp->mac_mode = tr32(MAC_MODE) |
13490                                MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
13491         else
13492                 tp->mac_mode = TG3_DEF_MAC_MODE;
13493
13494         /* these are limited to 10/100 only */
13495         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13496              (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
13497             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13498              tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13499              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
13500               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
13501               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
13502             (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13503              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
13504               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
13505               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
13506             tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
13507             (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
13508                 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
13509
13510         err = tg3_phy_probe(tp);
13511         if (err) {
13512                 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
13513                        pci_name(tp->pdev), err);
13514                 /* ... but do not return immediately ... */
13515                 tg3_mdio_fini(tp);
13516         }
13517
13518         tg3_read_partno(tp);
13519         tg3_read_fw_ver(tp);
13520
13521         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
13522                 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
13523         } else {
13524                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13525                         tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
13526                 else
13527                         tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
13528         }
13529
13530         /* 5700 {AX,BX} chips have a broken status block link
13531          * change bit implementation, so we must use the
13532          * status register in those cases.
13533          */
13534         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13535                 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
13536         else
13537                 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
13538
13539         /* The led_ctrl is set during tg3_phy_probe, here we might
13540          * have to force the link status polling mechanism based
13541          * upon subsystem IDs.
13542          */
13543         if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
13544             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13545             !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
13546                 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
13547                                   TG3_FLAG_USE_LINKCHG_REG);
13548         }
13549
13550         /* For all SERDES we poll the MAC status register. */
13551         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
13552                 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
13553         else
13554                 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
13555
13556         tp->rx_offset = NET_IP_ALIGN;
13557         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13558             (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
13559                 tp->rx_offset = 0;
13560
13561         tp->rx_std_max_post = TG3_RX_RING_SIZE;
13562
13563         /* Increment the rx prod index on the rx std ring by at most
13564          * 8 for these chips to workaround hw errata.
13565          */
13566         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13567             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13568             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
13569                 tp->rx_std_max_post = 8;
13570
13571         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
13572                 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
13573                                      PCIE_PWR_MGMT_L1_THRESH_MSK;
13574
13575         return err;
13576 }
13577
13578 #ifdef CONFIG_SPARC
13579 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
13580 {
13581         struct net_device *dev = tp->dev;
13582         struct pci_dev *pdev = tp->pdev;
13583         struct device_node *dp = pci_device_to_OF_node(pdev);
13584         const unsigned char *addr;
13585         int len;
13586
13587         addr = of_get_property(dp, "local-mac-address", &len);
13588         if (addr && len == 6) {
13589                 memcpy(dev->dev_addr, addr, 6);
13590                 memcpy(dev->perm_addr, dev->dev_addr, 6);
13591                 return 0;
13592         }
13593         return -ENODEV;
13594 }
13595
13596 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
13597 {
13598         struct net_device *dev = tp->dev;
13599
13600         memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
13601         memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
13602         return 0;
13603 }
13604 #endif
13605
13606 static int __devinit tg3_get_device_address(struct tg3 *tp)
13607 {
13608         struct net_device *dev = tp->dev;
13609         u32 hi, lo, mac_offset;
13610         int addr_ok = 0;
13611
13612 #ifdef CONFIG_SPARC
13613         if (!tg3_get_macaddr_sparc(tp))
13614                 return 0;
13615 #endif
13616
13617         mac_offset = 0x7c;
13618         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
13619             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13620                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
13621                         mac_offset = 0xcc;
13622                 if (tg3_nvram_lock(tp))
13623                         tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
13624                 else
13625                         tg3_nvram_unlock(tp);
13626         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
13627                 if (tr32(TG3_CPMU_STATUS) & TG3_CPMU_STATUS_PCIE_FUNC)
13628                         mac_offset = 0xcc;
13629         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13630                 mac_offset = 0x10;
13631
13632         /* First try to get it from MAC address mailbox. */
13633         tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
13634         if ((hi >> 16) == 0x484b) {
13635                 dev->dev_addr[0] = (hi >>  8) & 0xff;
13636                 dev->dev_addr[1] = (hi >>  0) & 0xff;
13637
13638                 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
13639                 dev->dev_addr[2] = (lo >> 24) & 0xff;
13640                 dev->dev_addr[3] = (lo >> 16) & 0xff;
13641                 dev->dev_addr[4] = (lo >>  8) & 0xff;
13642                 dev->dev_addr[5] = (lo >>  0) & 0xff;
13643
13644                 /* Some old bootcode may report a 0 MAC address in SRAM */
13645                 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
13646         }
13647         if (!addr_ok) {
13648                 /* Next, try NVRAM. */
13649                 if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) &&
13650                     !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
13651                     !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
13652                         memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
13653                         memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
13654                 }
13655                 /* Finally just fetch it out of the MAC control regs. */
13656                 else {
13657                         hi = tr32(MAC_ADDR_0_HIGH);
13658                         lo = tr32(MAC_ADDR_0_LOW);
13659
13660                         dev->dev_addr[5] = lo & 0xff;
13661                         dev->dev_addr[4] = (lo >> 8) & 0xff;
13662                         dev->dev_addr[3] = (lo >> 16) & 0xff;
13663                         dev->dev_addr[2] = (lo >> 24) & 0xff;
13664                         dev->dev_addr[1] = hi & 0xff;
13665                         dev->dev_addr[0] = (hi >> 8) & 0xff;
13666                 }
13667         }
13668
13669         if (!is_valid_ether_addr(&dev->dev_addr[0])) {
13670 #ifdef CONFIG_SPARC
13671                 if (!tg3_get_default_macaddr_sparc(tp))
13672                         return 0;
13673 #endif
13674                 return -EINVAL;
13675         }
13676         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
13677         return 0;
13678 }
13679
13680 #define BOUNDARY_SINGLE_CACHELINE       1
13681 #define BOUNDARY_MULTI_CACHELINE        2
13682
13683 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
13684 {
13685         int cacheline_size;
13686         u8 byte;
13687         int goal;
13688
13689         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
13690         if (byte == 0)
13691                 cacheline_size = 1024;
13692         else
13693                 cacheline_size = (int) byte * 4;
13694
13695         /* On 5703 and later chips, the boundary bits have no
13696          * effect.
13697          */
13698         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13699             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13700             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13701                 goto out;
13702
13703 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
13704         goal = BOUNDARY_MULTI_CACHELINE;
13705 #else
13706 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
13707         goal = BOUNDARY_SINGLE_CACHELINE;
13708 #else
13709         goal = 0;
13710 #endif
13711 #endif
13712
13713         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13714             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
13715                 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
13716                 goto out;
13717         }
13718
13719         if (!goal)
13720                 goto out;
13721
13722         /* PCI controllers on most RISC systems tend to disconnect
13723          * when a device tries to burst across a cache-line boundary.
13724          * Therefore, letting tg3 do so just wastes PCI bandwidth.
13725          *
13726          * Unfortunately, for PCI-E there are only limited
13727          * write-side controls for this, and thus for reads
13728          * we will still get the disconnects.  We'll also waste
13729          * these PCI cycles for both read and write for chips
13730          * other than 5700 and 5701 which do not implement the
13731          * boundary bits.
13732          */
13733         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13734             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
13735                 switch (cacheline_size) {
13736                 case 16:
13737                 case 32:
13738                 case 64:
13739                 case 128:
13740                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13741                                 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
13742                                         DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
13743                         } else {
13744                                 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13745                                         DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13746                         }
13747                         break;
13748
13749                 case 256:
13750                         val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
13751                                 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
13752                         break;
13753
13754                 default:
13755                         val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13756                                 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13757                         break;
13758                 }
13759         } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13760                 switch (cacheline_size) {
13761                 case 16:
13762                 case 32:
13763                 case 64:
13764                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13765                                 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13766                                 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
13767                                 break;
13768                         }
13769                         /* fallthrough */
13770                 case 128:
13771                 default:
13772                         val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13773                         val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
13774                         break;
13775                 }
13776         } else {
13777                 switch (cacheline_size) {
13778                 case 16:
13779                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13780                                 val |= (DMA_RWCTRL_READ_BNDRY_16 |
13781                                         DMA_RWCTRL_WRITE_BNDRY_16);
13782                                 break;
13783                         }
13784                         /* fallthrough */
13785                 case 32:
13786                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13787                                 val |= (DMA_RWCTRL_READ_BNDRY_32 |
13788                                         DMA_RWCTRL_WRITE_BNDRY_32);
13789                                 break;
13790                         }
13791                         /* fallthrough */
13792                 case 64:
13793                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13794                                 val |= (DMA_RWCTRL_READ_BNDRY_64 |
13795                                         DMA_RWCTRL_WRITE_BNDRY_64);
13796                                 break;
13797                         }
13798                         /* fallthrough */
13799                 case 128:
13800                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13801                                 val |= (DMA_RWCTRL_READ_BNDRY_128 |
13802                                         DMA_RWCTRL_WRITE_BNDRY_128);
13803                                 break;
13804                         }
13805                         /* fallthrough */
13806                 case 256:
13807                         val |= (DMA_RWCTRL_READ_BNDRY_256 |
13808                                 DMA_RWCTRL_WRITE_BNDRY_256);
13809                         break;
13810                 case 512:
13811                         val |= (DMA_RWCTRL_READ_BNDRY_512 |
13812                                 DMA_RWCTRL_WRITE_BNDRY_512);
13813                         break;
13814                 case 1024:
13815                 default:
13816                         val |= (DMA_RWCTRL_READ_BNDRY_1024 |
13817                                 DMA_RWCTRL_WRITE_BNDRY_1024);
13818                         break;
13819                 }
13820         }
13821
13822 out:
13823         return val;
13824 }
13825
13826 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
13827 {
13828         struct tg3_internal_buffer_desc test_desc;
13829         u32 sram_dma_descs;
13830         int i, ret;
13831
13832         sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
13833
13834         tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
13835         tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
13836         tw32(RDMAC_STATUS, 0);
13837         tw32(WDMAC_STATUS, 0);
13838
13839         tw32(BUFMGR_MODE, 0);
13840         tw32(FTQ_RESET, 0);
13841
13842         test_desc.addr_hi = ((u64) buf_dma) >> 32;
13843         test_desc.addr_lo = buf_dma & 0xffffffff;
13844         test_desc.nic_mbuf = 0x00002100;
13845         test_desc.len = size;
13846
13847         /*
13848          * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
13849          * the *second* time the tg3 driver was getting loaded after an
13850          * initial scan.
13851          *
13852          * Broadcom tells me:
13853          *   ...the DMA engine is connected to the GRC block and a DMA
13854          *   reset may affect the GRC block in some unpredictable way...
13855          *   The behavior of resets to individual blocks has not been tested.
13856          *
13857          * Broadcom noted the GRC reset will also reset all sub-components.
13858          */
13859         if (to_device) {
13860                 test_desc.cqid_sqid = (13 << 8) | 2;
13861
13862                 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
13863                 udelay(40);
13864         } else {
13865                 test_desc.cqid_sqid = (16 << 8) | 7;
13866
13867                 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
13868                 udelay(40);
13869         }
13870         test_desc.flags = 0x00000005;
13871
13872         for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
13873                 u32 val;
13874
13875                 val = *(((u32 *)&test_desc) + i);
13876                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
13877                                        sram_dma_descs + (i * sizeof(u32)));
13878                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
13879         }
13880         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
13881
13882         if (to_device) {
13883                 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
13884         } else {
13885                 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
13886         }
13887
13888         ret = -ENODEV;
13889         for (i = 0; i < 40; i++) {
13890                 u32 val;
13891
13892                 if (to_device)
13893                         val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
13894                 else
13895                         val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
13896                 if ((val & 0xffff) == sram_dma_descs) {
13897                         ret = 0;
13898                         break;
13899                 }
13900
13901                 udelay(100);
13902         }
13903
13904         return ret;
13905 }
13906
13907 #define TEST_BUFFER_SIZE        0x2000
13908
13909 static int __devinit tg3_test_dma(struct tg3 *tp)
13910 {
13911         dma_addr_t buf_dma;
13912         u32 *buf, saved_dma_rwctrl;
13913         int ret = 0;
13914
13915         buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
13916         if (!buf) {
13917                 ret = -ENOMEM;
13918                 goto out_nofree;
13919         }
13920
13921         tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
13922                           (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
13923
13924         tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
13925
13926         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13927             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13928                 goto out;
13929
13930         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13931                 /* DMA read watermark not used on PCIE */
13932                 tp->dma_rwctrl |= 0x00180000;
13933         } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
13934                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
13935                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
13936                         tp->dma_rwctrl |= 0x003f0000;
13937                 else
13938                         tp->dma_rwctrl |= 0x003f000f;
13939         } else {
13940                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13941                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
13942                         u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
13943                         u32 read_water = 0x7;
13944
13945                         /* If the 5704 is behind the EPB bridge, we can
13946                          * do the less restrictive ONE_DMA workaround for
13947                          * better performance.
13948                          */
13949                         if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
13950                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13951                                 tp->dma_rwctrl |= 0x8000;
13952                         else if (ccval == 0x6 || ccval == 0x7)
13953                                 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
13954
13955                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
13956                                 read_water = 4;
13957                         /* Set bit 23 to enable PCIX hw bug fix */
13958                         tp->dma_rwctrl |=
13959                                 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
13960                                 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
13961                                 (1 << 23);
13962                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
13963                         /* 5780 always in PCIX mode */
13964                         tp->dma_rwctrl |= 0x00144000;
13965                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
13966                         /* 5714 always in PCIX mode */
13967                         tp->dma_rwctrl |= 0x00148000;
13968                 } else {
13969                         tp->dma_rwctrl |= 0x001b000f;
13970                 }
13971         }
13972
13973         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13974             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13975                 tp->dma_rwctrl &= 0xfffffff0;
13976
13977         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13978             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
13979                 /* Remove this if it causes problems for some boards. */
13980                 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
13981
13982                 /* On 5700/5701 chips, we need to set this bit.
13983                  * Otherwise the chip will issue cacheline transactions
13984                  * to streamable DMA memory with not all the byte
13985                  * enables turned on.  This is an error on several
13986                  * RISC PCI controllers, in particular sparc64.
13987                  *
13988                  * On 5703/5704 chips, this bit has been reassigned
13989                  * a different meaning.  In particular, it is used
13990                  * on those chips to enable a PCI-X workaround.
13991                  */
13992                 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
13993         }
13994
13995         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13996
13997 #if 0
13998         /* Unneeded, already done by tg3_get_invariants.  */
13999         tg3_switch_clocks(tp);
14000 #endif
14001
14002         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
14003             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
14004                 goto out;
14005
14006         /* It is best to perform DMA test with maximum write burst size
14007          * to expose the 5700/5701 write DMA bug.
14008          */
14009         saved_dma_rwctrl = tp->dma_rwctrl;
14010         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14011         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14012
14013         while (1) {
14014                 u32 *p = buf, i;
14015
14016                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
14017                         p[i] = i;
14018
14019                 /* Send the buffer to the chip. */
14020                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
14021                 if (ret) {
14022                         printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
14023                         break;
14024                 }
14025
14026 #if 0
14027                 /* validate data reached card RAM correctly. */
14028                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14029                         u32 val;
14030                         tg3_read_mem(tp, 0x2100 + (i*4), &val);
14031                         if (le32_to_cpu(val) != p[i]) {
14032                                 printk(KERN_ERR "  tg3_test_dma()  Card buffer corrupted on write! (%d != %d)\n", val, i);
14033                                 /* ret = -ENODEV here? */
14034                         }
14035                         p[i] = 0;
14036                 }
14037 #endif
14038                 /* Now read it back. */
14039                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
14040                 if (ret) {
14041                         printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
14042
14043                         break;
14044                 }
14045
14046                 /* Verify it. */
14047                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14048                         if (p[i] == i)
14049                                 continue;
14050
14051                         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14052                             DMA_RWCTRL_WRITE_BNDRY_16) {
14053                                 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14054                                 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14055                                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14056                                 break;
14057                         } else {
14058                                 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
14059                                 ret = -ENODEV;
14060                                 goto out;
14061                         }
14062                 }
14063
14064                 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
14065                         /* Success. */
14066                         ret = 0;
14067                         break;
14068                 }
14069         }
14070         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14071             DMA_RWCTRL_WRITE_BNDRY_16) {
14072                 static struct pci_device_id dma_wait_state_chipsets[] = {
14073                         { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
14074                                      PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
14075                         { },
14076                 };
14077
14078                 /* DMA test passed without adjusting DMA boundary,
14079                  * now look for chipsets that are known to expose the
14080                  * DMA bug without failing the test.
14081                  */
14082                 if (pci_dev_present(dma_wait_state_chipsets)) {
14083                         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14084                         tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14085                 }
14086                 else
14087                         /* Safe to use the calculated DMA boundary. */
14088                         tp->dma_rwctrl = saved_dma_rwctrl;
14089
14090                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14091         }
14092
14093 out:
14094         pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
14095 out_nofree:
14096         return ret;
14097 }
14098
14099 static void __devinit tg3_init_link_config(struct tg3 *tp)
14100 {
14101         tp->link_config.advertising =
14102                 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
14103                  ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
14104                  ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
14105                  ADVERTISED_Autoneg | ADVERTISED_MII);
14106         tp->link_config.speed = SPEED_INVALID;
14107         tp->link_config.duplex = DUPLEX_INVALID;
14108         tp->link_config.autoneg = AUTONEG_ENABLE;
14109         tp->link_config.active_speed = SPEED_INVALID;
14110         tp->link_config.active_duplex = DUPLEX_INVALID;
14111         tp->link_config.phy_is_low_power = 0;
14112         tp->link_config.orig_speed = SPEED_INVALID;
14113         tp->link_config.orig_duplex = DUPLEX_INVALID;
14114         tp->link_config.orig_autoneg = AUTONEG_INVALID;
14115 }
14116
14117 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
14118 {
14119         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
14120             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
14121                 tp->bufmgr_config.mbuf_read_dma_low_water =
14122                         DEFAULT_MB_RDMA_LOW_WATER_5705;
14123                 tp->bufmgr_config.mbuf_mac_rx_low_water =
14124                         DEFAULT_MB_MACRX_LOW_WATER_57765;
14125                 tp->bufmgr_config.mbuf_high_water =
14126                         DEFAULT_MB_HIGH_WATER_57765;
14127
14128                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14129                         DEFAULT_MB_RDMA_LOW_WATER_5705;
14130                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14131                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765;
14132                 tp->bufmgr_config.mbuf_high_water_jumbo =
14133                         DEFAULT_MB_HIGH_WATER_JUMBO_57765;
14134         } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
14135                 tp->bufmgr_config.mbuf_read_dma_low_water =
14136                         DEFAULT_MB_RDMA_LOW_WATER_5705;
14137                 tp->bufmgr_config.mbuf_mac_rx_low_water =
14138                         DEFAULT_MB_MACRX_LOW_WATER_5705;
14139                 tp->bufmgr_config.mbuf_high_water =
14140                         DEFAULT_MB_HIGH_WATER_5705;
14141                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
14142                         tp->bufmgr_config.mbuf_mac_rx_low_water =
14143                                 DEFAULT_MB_MACRX_LOW_WATER_5906;
14144                         tp->bufmgr_config.mbuf_high_water =
14145                                 DEFAULT_MB_HIGH_WATER_5906;
14146                 }
14147
14148                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14149                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
14150                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14151                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
14152                 tp->bufmgr_config.mbuf_high_water_jumbo =
14153                         DEFAULT_MB_HIGH_WATER_JUMBO_5780;
14154         } else {
14155                 tp->bufmgr_config.mbuf_read_dma_low_water =
14156                         DEFAULT_MB_RDMA_LOW_WATER;
14157                 tp->bufmgr_config.mbuf_mac_rx_low_water =
14158                         DEFAULT_MB_MACRX_LOW_WATER;
14159                 tp->bufmgr_config.mbuf_high_water =
14160                         DEFAULT_MB_HIGH_WATER;
14161
14162                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14163                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
14164                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14165                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
14166                 tp->bufmgr_config.mbuf_high_water_jumbo =
14167                         DEFAULT_MB_HIGH_WATER_JUMBO;
14168         }
14169
14170         tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
14171         tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
14172 }
14173
14174 static char * __devinit tg3_phy_string(struct tg3 *tp)
14175 {
14176         switch (tp->phy_id & PHY_ID_MASK) {
14177         case PHY_ID_BCM5400:    return "5400";
14178         case PHY_ID_BCM5401:    return "5401";
14179         case PHY_ID_BCM5411:    return "5411";
14180         case PHY_ID_BCM5701:    return "5701";
14181         case PHY_ID_BCM5703:    return "5703";
14182         case PHY_ID_BCM5704:    return "5704";
14183         case PHY_ID_BCM5705:    return "5705";
14184         case PHY_ID_BCM5750:    return "5750";
14185         case PHY_ID_BCM5752:    return "5752";
14186         case PHY_ID_BCM5714:    return "5714";
14187         case PHY_ID_BCM5780:    return "5780";
14188         case PHY_ID_BCM5755:    return "5755";
14189         case PHY_ID_BCM5787:    return "5787";
14190         case PHY_ID_BCM5784:    return "5784";
14191         case PHY_ID_BCM5756:    return "5722/5756";
14192         case PHY_ID_BCM5906:    return "5906";
14193         case PHY_ID_BCM5761:    return "5761";
14194         case PHY_ID_BCM5718C:   return "5718C";
14195         case PHY_ID_BCM5718S:   return "5718S";
14196         case PHY_ID_BCM8002:    return "8002/serdes";
14197         case 0:                 return "serdes";
14198         default:                return "unknown";
14199         }
14200 }
14201
14202 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
14203 {
14204         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
14205                 strcpy(str, "PCI Express");
14206                 return str;
14207         } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
14208                 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
14209
14210                 strcpy(str, "PCIX:");
14211
14212                 if ((clock_ctrl == 7) ||
14213                     ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
14214                      GRC_MISC_CFG_BOARD_ID_5704CIOBE))
14215                         strcat(str, "133MHz");
14216                 else if (clock_ctrl == 0)
14217                         strcat(str, "33MHz");
14218                 else if (clock_ctrl == 2)
14219                         strcat(str, "50MHz");
14220                 else if (clock_ctrl == 4)
14221                         strcat(str, "66MHz");
14222                 else if (clock_ctrl == 6)
14223                         strcat(str, "100MHz");
14224         } else {
14225                 strcpy(str, "PCI:");
14226                 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
14227                         strcat(str, "66MHz");
14228                 else
14229                         strcat(str, "33MHz");
14230         }
14231         if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
14232                 strcat(str, ":32-bit");
14233         else
14234                 strcat(str, ":64-bit");
14235         return str;
14236 }
14237
14238 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
14239 {
14240         struct pci_dev *peer;
14241         unsigned int func, devnr = tp->pdev->devfn & ~7;
14242
14243         for (func = 0; func < 8; func++) {
14244                 peer = pci_get_slot(tp->pdev->bus, devnr | func);
14245                 if (peer && peer != tp->pdev)
14246                         break;
14247                 pci_dev_put(peer);
14248         }
14249         /* 5704 can be configured in single-port mode, set peer to
14250          * tp->pdev in that case.
14251          */
14252         if (!peer) {
14253                 peer = tp->pdev;
14254                 return peer;
14255         }
14256
14257         /*
14258          * We don't need to keep the refcount elevated; there's no way
14259          * to remove one half of this device without removing the other
14260          */
14261         pci_dev_put(peer);
14262
14263         return peer;
14264 }
14265
14266 static void __devinit tg3_init_coal(struct tg3 *tp)
14267 {
14268         struct ethtool_coalesce *ec = &tp->coal;
14269
14270         memset(ec, 0, sizeof(*ec));
14271         ec->cmd = ETHTOOL_GCOALESCE;
14272         ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
14273         ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
14274         ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
14275         ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
14276         ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
14277         ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
14278         ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
14279         ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
14280         ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
14281
14282         if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
14283                                  HOSTCC_MODE_CLRTICK_TXBD)) {
14284                 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
14285                 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
14286                 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
14287                 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
14288         }
14289
14290         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
14291                 ec->rx_coalesce_usecs_irq = 0;
14292                 ec->tx_coalesce_usecs_irq = 0;
14293                 ec->stats_block_coalesce_usecs = 0;
14294         }
14295 }
14296
14297 static const struct net_device_ops tg3_netdev_ops = {
14298         .ndo_open               = tg3_open,
14299         .ndo_stop               = tg3_close,
14300         .ndo_start_xmit         = tg3_start_xmit,
14301         .ndo_get_stats          = tg3_get_stats,
14302         .ndo_validate_addr      = eth_validate_addr,
14303         .ndo_set_multicast_list = tg3_set_rx_mode,
14304         .ndo_set_mac_address    = tg3_set_mac_addr,
14305         .ndo_do_ioctl           = tg3_ioctl,
14306         .ndo_tx_timeout         = tg3_tx_timeout,
14307         .ndo_change_mtu         = tg3_change_mtu,
14308 #if TG3_VLAN_TAG_USED
14309         .ndo_vlan_rx_register   = tg3_vlan_rx_register,
14310 #endif
14311 #ifdef CONFIG_NET_POLL_CONTROLLER
14312         .ndo_poll_controller    = tg3_poll_controller,
14313 #endif
14314 };
14315
14316 static const struct net_device_ops tg3_netdev_ops_dma_bug = {
14317         .ndo_open               = tg3_open,
14318         .ndo_stop               = tg3_close,
14319         .ndo_start_xmit         = tg3_start_xmit_dma_bug,
14320         .ndo_get_stats          = tg3_get_stats,
14321         .ndo_validate_addr      = eth_validate_addr,
14322         .ndo_set_multicast_list = tg3_set_rx_mode,
14323         .ndo_set_mac_address    = tg3_set_mac_addr,
14324         .ndo_do_ioctl           = tg3_ioctl,
14325         .ndo_tx_timeout         = tg3_tx_timeout,
14326         .ndo_change_mtu         = tg3_change_mtu,
14327 #if TG3_VLAN_TAG_USED
14328         .ndo_vlan_rx_register   = tg3_vlan_rx_register,
14329 #endif
14330 #ifdef CONFIG_NET_POLL_CONTROLLER
14331         .ndo_poll_controller    = tg3_poll_controller,
14332 #endif
14333 };
14334
14335 static int __devinit tg3_init_one(struct pci_dev *pdev,
14336                                   const struct pci_device_id *ent)
14337 {
14338         static int tg3_version_printed = 0;
14339         struct net_device *dev;
14340         struct tg3 *tp;
14341         int i, err, pm_cap;
14342         u32 sndmbx, rcvmbx, intmbx;
14343         char str[40];
14344         u64 dma_mask, persist_dma_mask;
14345
14346         if (tg3_version_printed++ == 0)
14347                 printk(KERN_INFO "%s", version);
14348
14349         err = pci_enable_device(pdev);
14350         if (err) {
14351                 printk(KERN_ERR PFX "Cannot enable PCI device, "
14352                        "aborting.\n");
14353                 return err;
14354         }
14355
14356         err = pci_request_regions(pdev, DRV_MODULE_NAME);
14357         if (err) {
14358                 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
14359                        "aborting.\n");
14360                 goto err_out_disable_pdev;
14361         }
14362
14363         pci_set_master(pdev);
14364
14365         /* Find power-management capability. */
14366         pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
14367         if (pm_cap == 0) {
14368                 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
14369                        "aborting.\n");
14370                 err = -EIO;
14371                 goto err_out_free_res;
14372         }
14373
14374         dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
14375         if (!dev) {
14376                 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
14377                 err = -ENOMEM;
14378                 goto err_out_free_res;
14379         }
14380
14381         SET_NETDEV_DEV(dev, &pdev->dev);
14382
14383 #if TG3_VLAN_TAG_USED
14384         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
14385 #endif
14386
14387         tp = netdev_priv(dev);
14388         tp->pdev = pdev;
14389         tp->dev = dev;
14390         tp->pm_cap = pm_cap;
14391         tp->rx_mode = TG3_DEF_RX_MODE;
14392         tp->tx_mode = TG3_DEF_TX_MODE;
14393
14394         if (tg3_debug > 0)
14395                 tp->msg_enable = tg3_debug;
14396         else
14397                 tp->msg_enable = TG3_DEF_MSG_ENABLE;
14398
14399         /* The word/byte swap controls here control register access byte
14400          * swapping.  DMA data byte swapping is controlled in the GRC_MODE
14401          * setting below.
14402          */
14403         tp->misc_host_ctrl =
14404                 MISC_HOST_CTRL_MASK_PCI_INT |
14405                 MISC_HOST_CTRL_WORD_SWAP |
14406                 MISC_HOST_CTRL_INDIR_ACCESS |
14407                 MISC_HOST_CTRL_PCISTATE_RW;
14408
14409         /* The NONFRM (non-frame) byte/word swap controls take effect
14410          * on descriptor entries, anything which isn't packet data.
14411          *
14412          * The StrongARM chips on the board (one for tx, one for rx)
14413          * are running in big-endian mode.
14414          */
14415         tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
14416                         GRC_MODE_WSWAP_NONFRM_DATA);
14417 #ifdef __BIG_ENDIAN
14418         tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
14419 #endif
14420         spin_lock_init(&tp->lock);
14421         spin_lock_init(&tp->indirect_lock);
14422         INIT_WORK(&tp->reset_task, tg3_reset_task);
14423
14424         tp->regs = pci_ioremap_bar(pdev, BAR_0);
14425         if (!tp->regs) {
14426                 printk(KERN_ERR PFX "Cannot map device registers, "
14427                        "aborting.\n");
14428                 err = -ENOMEM;
14429                 goto err_out_free_dev;
14430         }
14431
14432         tg3_init_link_config(tp);
14433
14434         tp->rx_pending = TG3_DEF_RX_RING_PENDING;
14435         tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
14436
14437         dev->ethtool_ops = &tg3_ethtool_ops;
14438         dev->watchdog_timeo = TG3_TX_TIMEOUT;
14439         dev->irq = pdev->irq;
14440
14441         err = tg3_get_invariants(tp);
14442         if (err) {
14443                 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
14444                        "aborting.\n");
14445                 goto err_out_iounmap;
14446         }
14447
14448         if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
14449             tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
14450                 dev->netdev_ops = &tg3_netdev_ops;
14451         else
14452                 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
14453
14454
14455         /* The EPB bridge inside 5714, 5715, and 5780 and any
14456          * device behind the EPB cannot support DMA addresses > 40-bit.
14457          * On 64-bit systems with IOMMU, use 40-bit dma_mask.
14458          * On 64-bit systems without IOMMU, use 64-bit dma_mask and
14459          * do DMA address check in tg3_start_xmit().
14460          */
14461         if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
14462                 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
14463         else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
14464                 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
14465 #ifdef CONFIG_HIGHMEM
14466                 dma_mask = DMA_BIT_MASK(64);
14467 #endif
14468         } else
14469                 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
14470
14471         /* Configure DMA attributes. */
14472         if (dma_mask > DMA_BIT_MASK(32)) {
14473                 err = pci_set_dma_mask(pdev, dma_mask);
14474                 if (!err) {
14475                         dev->features |= NETIF_F_HIGHDMA;
14476                         err = pci_set_consistent_dma_mask(pdev,
14477                                                           persist_dma_mask);
14478                         if (err < 0) {
14479                                 printk(KERN_ERR PFX "Unable to obtain 64 bit "
14480                                        "DMA for consistent allocations\n");
14481                                 goto err_out_iounmap;
14482                         }
14483                 }
14484         }
14485         if (err || dma_mask == DMA_BIT_MASK(32)) {
14486                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
14487                 if (err) {
14488                         printk(KERN_ERR PFX "No usable DMA configuration, "
14489                                "aborting.\n");
14490                         goto err_out_iounmap;
14491                 }
14492         }
14493
14494         tg3_init_bufmgr_config(tp);
14495
14496         /* Selectively allow TSO based on operating conditions */
14497         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
14498             (tp->fw_needed && !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)))
14499                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
14500         else {
14501                 tp->tg3_flags2 &= ~(TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG);
14502                 tp->fw_needed = NULL;
14503         }
14504
14505         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
14506                 tp->fw_needed = FIRMWARE_TG3;
14507
14508         /* TSO is on by default on chips that support hardware TSO.
14509          * Firmware TSO on older chips gives lower performance, so it
14510          * is off by default, but can be enabled using ethtool.
14511          */
14512         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) &&
14513             (dev->features & NETIF_F_IP_CSUM))
14514                 dev->features |= NETIF_F_TSO;
14515
14516         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
14517             (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3)) {
14518                 if (dev->features & NETIF_F_IPV6_CSUM)
14519                         dev->features |= NETIF_F_TSO6;
14520                 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
14521                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
14522                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
14523                      GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
14524                         GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
14525                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
14526                         dev->features |= NETIF_F_TSO_ECN;
14527         }
14528
14529         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
14530             !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
14531             !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
14532                 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
14533                 tp->rx_pending = 63;
14534         }
14535
14536         err = tg3_get_device_address(tp);
14537         if (err) {
14538                 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
14539                        "aborting.\n");
14540                 goto err_out_iounmap;
14541         }
14542
14543         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
14544                 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
14545                 if (!tp->aperegs) {
14546                         printk(KERN_ERR PFX "Cannot map APE registers, "
14547                                "aborting.\n");
14548                         err = -ENOMEM;
14549                         goto err_out_iounmap;
14550                 }
14551
14552                 tg3_ape_lock_init(tp);
14553
14554                 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
14555                         tg3_read_dash_ver(tp);
14556         }
14557
14558         /*
14559          * Reset chip in case UNDI or EFI driver did not shutdown
14560          * DMA self test will enable WDMAC and we'll see (spurious)
14561          * pending DMA on the PCI bus at that point.
14562          */
14563         if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
14564             (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
14565                 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
14566                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14567         }
14568
14569         err = tg3_test_dma(tp);
14570         if (err) {
14571                 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
14572                 goto err_out_apeunmap;
14573         }
14574
14575         /* flow control autonegotiation is default behavior */
14576         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
14577         tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
14578
14579         intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
14580         rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
14581         sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
14582         for (i = 0; i < TG3_IRQ_MAX_VECS; i++) {
14583                 struct tg3_napi *tnapi = &tp->napi[i];
14584
14585                 tnapi->tp = tp;
14586                 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
14587
14588                 tnapi->int_mbox = intmbx;
14589                 if (i < 4)
14590                         intmbx += 0x8;
14591                 else
14592                         intmbx += 0x4;
14593
14594                 tnapi->consmbox = rcvmbx;
14595                 tnapi->prodmbox = sndmbx;
14596
14597                 if (i) {
14598                         tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
14599                         netif_napi_add(dev, &tnapi->napi, tg3_poll_msix, 64);
14600                 } else {
14601                         tnapi->coal_now = HOSTCC_MODE_NOW;
14602                         netif_napi_add(dev, &tnapi->napi, tg3_poll, 64);
14603                 }
14604
14605                 if (!(tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX))
14606                         break;
14607
14608                 /*
14609                  * If we support MSIX, we'll be using RSS.  If we're using
14610                  * RSS, the first vector only handles link interrupts and the
14611                  * remaining vectors handle rx and tx interrupts.  Reuse the
14612                  * mailbox values for the next iteration.  The values we setup
14613                  * above are still useful for the single vectored mode.
14614                  */
14615                 if (!i)
14616                         continue;
14617
14618                 rcvmbx += 0x8;
14619
14620                 if (sndmbx & 0x4)
14621                         sndmbx -= 0x4;
14622                 else
14623                         sndmbx += 0xc;
14624         }
14625
14626         tg3_init_coal(tp);
14627
14628         pci_set_drvdata(pdev, dev);
14629
14630         err = register_netdev(dev);
14631         if (err) {
14632                 printk(KERN_ERR PFX "Cannot register net device, "
14633                        "aborting.\n");
14634                 goto err_out_apeunmap;
14635         }
14636
14637         printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
14638                dev->name,
14639                tp->board_part_number,
14640                tp->pci_chip_rev_id,
14641                tg3_bus_string(tp, str),
14642                dev->dev_addr);
14643
14644         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
14645                 struct phy_device *phydev;
14646                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
14647                 printk(KERN_INFO
14648                        "%s: attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
14649                        tp->dev->name, phydev->drv->name,
14650                        dev_name(&phydev->dev));
14651         } else
14652                 printk(KERN_INFO
14653                        "%s: attached PHY is %s (%s Ethernet) (WireSpeed[%d])\n",
14654                        tp->dev->name, tg3_phy_string(tp),
14655                        ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
14656                         ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
14657                          "10/100/1000Base-T")),
14658                        (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0);
14659
14660         printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
14661                dev->name,
14662                (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
14663                (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
14664                (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
14665                (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
14666                (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
14667         printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
14668                dev->name, tp->dma_rwctrl,
14669                (pdev->dma_mask == DMA_BIT_MASK(32)) ? 32 :
14670                 (((u64) pdev->dma_mask == DMA_BIT_MASK(40)) ? 40 : 64));
14671
14672         return 0;
14673
14674 err_out_apeunmap:
14675         if (tp->aperegs) {
14676                 iounmap(tp->aperegs);
14677                 tp->aperegs = NULL;
14678         }
14679
14680 err_out_iounmap:
14681         if (tp->regs) {
14682                 iounmap(tp->regs);
14683                 tp->regs = NULL;
14684         }
14685
14686 err_out_free_dev:
14687         free_netdev(dev);
14688
14689 err_out_free_res:
14690         pci_release_regions(pdev);
14691
14692 err_out_disable_pdev:
14693         pci_disable_device(pdev);
14694         pci_set_drvdata(pdev, NULL);
14695         return err;
14696 }
14697
14698 static void __devexit tg3_remove_one(struct pci_dev *pdev)
14699 {
14700         struct net_device *dev = pci_get_drvdata(pdev);
14701
14702         if (dev) {
14703                 struct tg3 *tp = netdev_priv(dev);
14704
14705                 if (tp->fw)
14706                         release_firmware(tp->fw);
14707
14708                 flush_scheduled_work();
14709
14710                 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
14711                         tg3_phy_fini(tp);
14712                         tg3_mdio_fini(tp);
14713                 }
14714
14715                 unregister_netdev(dev);
14716                 if (tp->aperegs) {
14717                         iounmap(tp->aperegs);
14718                         tp->aperegs = NULL;
14719                 }
14720                 if (tp->regs) {
14721                         iounmap(tp->regs);
14722                         tp->regs = NULL;
14723                 }
14724                 free_netdev(dev);
14725                 pci_release_regions(pdev);
14726                 pci_disable_device(pdev);
14727                 pci_set_drvdata(pdev, NULL);
14728         }
14729 }
14730
14731 static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
14732 {
14733         struct net_device *dev = pci_get_drvdata(pdev);
14734         struct tg3 *tp = netdev_priv(dev);
14735         pci_power_t target_state;
14736         int err;
14737
14738         /* PCI register 4 needs to be saved whether netif_running() or not.
14739          * MSI address and data need to be saved if using MSI and
14740          * netif_running().
14741          */
14742         pci_save_state(pdev);
14743
14744         if (!netif_running(dev))
14745                 return 0;
14746
14747         flush_scheduled_work();
14748         tg3_phy_stop(tp);
14749         tg3_netif_stop(tp);
14750
14751         del_timer_sync(&tp->timer);
14752
14753         tg3_full_lock(tp, 1);
14754         tg3_disable_ints(tp);
14755         tg3_full_unlock(tp);
14756
14757         netif_device_detach(dev);
14758
14759         tg3_full_lock(tp, 0);
14760         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14761         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
14762         tg3_full_unlock(tp);
14763
14764         target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
14765
14766         err = tg3_set_power_state(tp, target_state);
14767         if (err) {
14768                 int err2;
14769
14770                 tg3_full_lock(tp, 0);
14771
14772                 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
14773                 err2 = tg3_restart_hw(tp, 1);
14774                 if (err2)
14775                         goto out;
14776
14777                 tp->timer.expires = jiffies + tp->timer_offset;
14778                 add_timer(&tp->timer);
14779
14780                 netif_device_attach(dev);
14781                 tg3_netif_start(tp);
14782
14783 out:
14784                 tg3_full_unlock(tp);
14785
14786                 if (!err2)
14787                         tg3_phy_start(tp);
14788         }
14789
14790         return err;
14791 }
14792
14793 static int tg3_resume(struct pci_dev *pdev)
14794 {
14795         struct net_device *dev = pci_get_drvdata(pdev);
14796         struct tg3 *tp = netdev_priv(dev);
14797         int err;
14798
14799         pci_restore_state(tp->pdev);
14800
14801         if (!netif_running(dev))
14802                 return 0;
14803
14804         err = tg3_set_power_state(tp, PCI_D0);
14805         if (err)
14806                 return err;
14807
14808         netif_device_attach(dev);
14809
14810         tg3_full_lock(tp, 0);
14811
14812         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
14813         err = tg3_restart_hw(tp, 1);
14814         if (err)
14815                 goto out;
14816
14817         tp->timer.expires = jiffies + tp->timer_offset;
14818         add_timer(&tp->timer);
14819
14820         tg3_netif_start(tp);
14821
14822 out:
14823         tg3_full_unlock(tp);
14824
14825         if (!err)
14826                 tg3_phy_start(tp);
14827
14828         return err;
14829 }
14830
14831 static struct pci_driver tg3_driver = {
14832         .name           = DRV_MODULE_NAME,
14833         .id_table       = tg3_pci_tbl,
14834         .probe          = tg3_init_one,
14835         .remove         = __devexit_p(tg3_remove_one),
14836         .suspend        = tg3_suspend,
14837         .resume         = tg3_resume
14838 };
14839
14840 static int __init tg3_init(void)
14841 {
14842         return pci_register_driver(&tg3_driver);
14843 }
14844
14845 static void __exit tg3_cleanup(void)
14846 {
14847         pci_unregister_driver(&tg3_driver);
14848 }
14849
14850 module_init(tg3_init);
14851 module_exit(tg3_cleanup);