SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/net/tg3.c

   1 /*
   2  * tg3.c: Broadcom Tigon3 ethernet driver.
   3  *
   4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
   5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
   6  * Copyright (C) 2004 Sun Microsystems Inc.
   7  * Copyright (C) 2005-2009 Broadcom Corporation.
   8  *
   9  * Firmware is:
  10  *      Derived from proprietary unpublished source code,
  11  *      Copyright (C) 2000-2003 Broadcom Corporation.
  12  *
  13  *      Permission is hereby granted for the distribution of this firmware
  14  *      data in hexadecimal or equivalent format, provided this copyright
  15  *      notice is accompanying it.
  16  */
  17
  18
  19 #include <linux/module.h>
  20 #include <linux/moduleparam.h>
  21 #include <linux/kernel.h>
  22 #include <linux/types.h>
  23 #include <linux/compiler.h>
  24 #include <linux/slab.h>
  25 #include <linux/delay.h>
  26 #include <linux/in.h>
  27 #include <linux/init.h>
  28 #include <linux/ioport.h>
  29 #include <linux/pci.h>
  30 #include <linux/netdevice.h>
  31 #include <linux/etherdevice.h>
  32 #include <linux/skbuff.h>
  33 #include <linux/ethtool.h>
  34 #include <linux/mii.h>
  35 #include <linux/phy.h>
  36 #include <linux/brcmphy.h>
  37 #include <linux/if_vlan.h>
  38 #include <linux/ip.h>
  39 #include <linux/tcp.h>
  40 #include <linux/workqueue.h>
  41 #include <linux/prefetch.h>
  42 #include <linux/dma-mapping.h>
  43 #include <linux/firmware.h>
  44
  45 #include <net/checksum.h>
  46 #include <net/ip.h>
  47
  48 #include <asm/system.h>
  49 #include <asm/io.h>
  50 #include <asm/byteorder.h>
  51 #include <asm/uaccess.h>
  52
  53 #ifdef CONFIG_SPARC
  54 #include <asm/idprom.h>
  55 #include <asm/prom.h>
  56 #endif
  57
  58 #define BAR_0   0
  59 #define BAR_2   2
  60
  61 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  62 #define TG3_VLAN_TAG_USED 1
  63 #else
  64 #define TG3_VLAN_TAG_USED 0
  65 #endif
  66
  67 #include "tg3.h"
  68
  69 #define DRV_MODULE_NAME         "tg3"
  70 #define PFX DRV_MODULE_NAME     ": "
  71 #define DRV_MODULE_VERSION      "3.102"
  72 #define DRV_MODULE_RELDATE      "September 1, 2009"
  73
  74 #define TG3_DEF_MAC_MODE        0
  75 #define TG3_DEF_RX_MODE         0
  76 #define TG3_DEF_TX_MODE         0
  77 #define TG3_DEF_MSG_ENABLE        \
  78         (NETIF_MSG_DRV          | \
  79          NETIF_MSG_PROBE        | \
  80          NETIF_MSG_LINK         | \
  81          NETIF_MSG_TIMER        | \
  82          NETIF_MSG_IFDOWN       | \
  83          NETIF_MSG_IFUP         | \
  84          NETIF_MSG_RX_ERR       | \
  85          NETIF_MSG_TX_ERR)
  86
  87 /* length of time before we decide the hardware is borked,
  88  * and dev->tx_timeout() should be called to fix the problem
  89  */
  90 #define TG3_TX_TIMEOUT                  (5 * HZ)
  91
  92 /* hardware minimum and maximum for a single frame's data payload */
  93 #define TG3_MIN_MTU                     60
  94 #define TG3_MAX_MTU(tp) \
  95         ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
  96
  97 /* These numbers seem to be hard coded in the NIC firmware somehow.
  98  * You can't change the ring sizes, but you can change where you place
  99  * them in the NIC onboard memory.
 100  */
 101 #define TG3_RX_RING_SIZE                512
 102 #define TG3_DEF_RX_RING_PENDING         200
 103 #define TG3_RX_JUMBO_RING_SIZE          256
 104 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
 105 #define TG3_RSS_INDIR_TBL_SIZE 128
 106
 107 /* Do not place this n-ring entries value into the tp struct itself,
 108  * we really want to expose these constants to GCC so that modulo et
 109  * al.  operations are done with shifts and masks instead of with
 110  * hw multiply/modulo instructions.  Another solution would be to
 111  * replace things like '% foo' with '& (foo - 1)'.
 112  */
 113 #define TG3_RX_RCB_RING_SIZE(tp)        \
 114         (((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) && \
 115           !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) ? 1024 : 512)
 116
 117 #define TG3_TX_RING_SIZE                512
 118 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
 119
 120 #define TG3_RX_RING_BYTES       (sizeof(struct tg3_rx_buffer_desc) * \
 121                                  TG3_RX_RING_SIZE)
 122 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_ext_rx_buffer_desc) * \
 123                                  TG3_RX_JUMBO_RING_SIZE)
 124 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
 125                                  TG3_RX_RCB_RING_SIZE(tp))
 126 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
 127                                  TG3_TX_RING_SIZE)
 128 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
 129
 130 #define TG3_DMA_BYTE_ENAB               64
 131
 132 #define TG3_RX_STD_DMA_SZ               1536
 133 #define TG3_RX_JMB_DMA_SZ               9046
 134
 135 #define TG3_RX_DMA_TO_MAP_SZ(x)         ((x) + TG3_DMA_BYTE_ENAB)
 136
 137 #define TG3_RX_STD_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
 138 #define TG3_RX_JMB_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
 139
 140 /* minimum number of free TX descriptors required to wake up TX process */
 141 #define TG3_TX_WAKEUP_THRESH(tnapi)             ((tnapi)->tx_pending / 4)
 142
 143 #define TG3_RAW_IP_ALIGN 2
 144
 145 /* number of ETHTOOL_GSTATS u64's */
 146 #define TG3_NUM_STATS           (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
 147
 148 #define TG3_NUM_TEST            6
 149
 150 #define FIRMWARE_TG3            "tigon/tg3.bin"
 151 #define FIRMWARE_TG3TSO         "tigon/tg3_tso.bin"
 152 #define FIRMWARE_TG3TSO5        "tigon/tg3_tso5.bin"
 153
 154 static char version[] __devinitdata =
 155         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
 156
 157 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
 158 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
 159 MODULE_LICENSE("GPL");
 160 MODULE_VERSION(DRV_MODULE_VERSION);
 161 MODULE_FIRMWARE(FIRMWARE_TG3);
 162 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
 163 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
 164
 165 #define TG3_RSS_MIN_NUM_MSIX_VECS       2
 166
 167 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
 168 module_param(tg3_debug, int, 0);
 169 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
 170
 171 static struct pci_device_id tg3_pci_tbl[] = {
 172         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
 173         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
 174         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
 175         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
 176         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
 177         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
 178         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
 179         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
 180         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
 181         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
 182         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
 183         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
 184         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
 185         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
 186         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
 187         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
 188         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
 189         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
 190         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
 191         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
 192         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
 193         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
 194         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
 195         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
 196         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
 197         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
 198         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
 199         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
 200         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
 201         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
 202         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
 203         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
 204         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
 205         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
 206         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
 207         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
 208         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
 209         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
 210         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
 211         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
 212         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
 213         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
 214         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
 215         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
 216         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
 217         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
 218         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
 219         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
 220         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
 221         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
 222         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
 223         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
 224         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
 225         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
 226         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
 227         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
 228         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
 229         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
 230         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
 231         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
 232         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
 233         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
 234         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
 235         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
 236         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
 237         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
 238         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
 239         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
 240         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
 241         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
 242         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
 243         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
 244         {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
 245         {}
 246 };
 247
 248 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
 249
 250 static const struct {
 251         const char string[ETH_GSTRING_LEN];
 252 } ethtool_stats_keys[TG3_NUM_STATS] = {
 253         { "rx_octets" },
 254         { "rx_fragments" },
 255         { "rx_ucast_packets" },
 256         { "rx_mcast_packets" },
 257         { "rx_bcast_packets" },
 258         { "rx_fcs_errors" },
 259         { "rx_align_errors" },
 260         { "rx_xon_pause_rcvd" },
 261         { "rx_xoff_pause_rcvd" },
 262         { "rx_mac_ctrl_rcvd" },
 263         { "rx_xoff_entered" },
 264         { "rx_frame_too_long_errors" },
 265         { "rx_jabbers" },
 266         { "rx_undersize_packets" },
 267         { "rx_in_length_errors" },
 268         { "rx_out_length_errors" },
 269         { "rx_64_or_less_octet_packets" },
 270         { "rx_65_to_127_octet_packets" },
 271         { "rx_128_to_255_octet_packets" },
 272         { "rx_256_to_511_octet_packets" },
 273         { "rx_512_to_1023_octet_packets" },
 274         { "rx_1024_to_1522_octet_packets" },
 275         { "rx_1523_to_2047_octet_packets" },
 276         { "rx_2048_to_4095_octet_packets" },
 277         { "rx_4096_to_8191_octet_packets" },
 278         { "rx_8192_to_9022_octet_packets" },
 279
 280         { "tx_octets" },
 281         { "tx_collisions" },
 282
 283         { "tx_xon_sent" },
 284         { "tx_xoff_sent" },
 285         { "tx_flow_control" },
 286         { "tx_mac_errors" },
 287         { "tx_single_collisions" },
 288         { "tx_mult_collisions" },
 289         { "tx_deferred" },
 290         { "tx_excessive_collisions" },
 291         { "tx_late_collisions" },
 292         { "tx_collide_2times" },
 293         { "tx_collide_3times" },
 294         { "tx_collide_4times" },
 295         { "tx_collide_5times" },
 296         { "tx_collide_6times" },
 297         { "tx_collide_7times" },
 298         { "tx_collide_8times" },
 299         { "tx_collide_9times" },
 300         { "tx_collide_10times" },
 301         { "tx_collide_11times" },
 302         { "tx_collide_12times" },
 303         { "tx_collide_13times" },
 304         { "tx_collide_14times" },
 305         { "tx_collide_15times" },
 306         { "tx_ucast_packets" },
 307         { "tx_mcast_packets" },
 308         { "tx_bcast_packets" },
 309         { "tx_carrier_sense_errors" },
 310         { "tx_discards" },
 311         { "tx_errors" },
 312
 313         { "dma_writeq_full" },
 314         { "dma_write_prioq_full" },
 315         { "rxbds_empty" },
 316         { "rx_discards" },
 317         { "rx_errors" },
 318         { "rx_threshold_hit" },
 319
 320         { "dma_readq_full" },
 321         { "dma_read_prioq_full" },
 322         { "tx_comp_queue_full" },
 323
 324         { "ring_set_send_prod_index" },
 325         { "ring_status_update" },
 326         { "nic_irqs" },
 327         { "nic_avoided_irqs" },
 328         { "nic_tx_threshold_hit" }
 329 };
 330
 331 static const struct {
 332         const char string[ETH_GSTRING_LEN];
 333 } ethtool_test_keys[TG3_NUM_TEST] = {
 334         { "nvram test     (online) " },
 335         { "link test      (online) " },
 336         { "register test  (offline)" },
 337         { "memory test    (offline)" },
 338         { "loopback test  (offline)" },
 339         { "interrupt test (offline)" },
 340 };
 341
 342 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
 343 {
 344         writel(val, tp->regs + off);
 345 }
 346
 347 static u32 tg3_read32(struct tg3 *tp, u32 off)
 348 {
 349         return (readl(tp->regs + off));
 350 }
 351
 352 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
 353 {
 354         writel(val, tp->aperegs + off);
 355 }
 356
 357 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
 358 {
 359         return (readl(tp->aperegs + off));
 360 }
 361
 362 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
 363 {
 364         unsigned long flags;
 365
 366         spin_lock_irqsave(&tp->indirect_lock, flags);
 367         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 368         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 369         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 370 }
 371
 372 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
 373 {
 374         writel(val, tp->regs + off);
 375         readl(tp->regs + off);
 376 }
 377
 378 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
 379 {
 380         unsigned long flags;
 381         u32 val;
 382
 383         spin_lock_irqsave(&tp->indirect_lock, flags);
 384         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 385         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 386         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 387         return val;
 388 }
 389
 390 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
 391 {
 392         unsigned long flags;
 393
 394         if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
 395                 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
 396                                        TG3_64BIT_REG_LOW, val);
 397                 return;
 398         }
 399         if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
 400                 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
 401                                        TG3_64BIT_REG_LOW, val);
 402                 return;
 403         }
 404
 405         spin_lock_irqsave(&tp->indirect_lock, flags);
 406         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 407         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 408         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 409
 410         /* In indirect mode when disabling interrupts, we also need
 411          * to clear the interrupt bit in the GRC local ctrl register.
 412          */
 413         if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
 414             (val == 0x1)) {
 415                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
 416                                        tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
 417         }
 418 }
 419
 420 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
 421 {
 422         unsigned long flags;
 423         u32 val;
 424
 425         spin_lock_irqsave(&tp->indirect_lock, flags);
 426         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 427         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 428         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 429         return val;
 430 }
 431
 432 /* usec_wait specifies the wait time in usec when writing to certain registers
 433  * where it is unsafe to read back the register without some delay.
 434  * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
 435  * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
 436  */
 437 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
 438 {
 439         if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
 440             (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 441                 /* Non-posted methods */
 442                 tp->write32(tp, off, val);
 443         else {
 444                 /* Posted method */
 445                 tg3_write32(tp, off, val);
 446                 if (usec_wait)
 447                         udelay(usec_wait);
 448                 tp->read32(tp, off);
 449         }
 450         /* Wait again after the read for the posted method to guarantee that
 451          * the wait time is met.
 452          */
 453         if (usec_wait)
 454                 udelay(usec_wait);
 455 }
 456
 457 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
 458 {
 459         tp->write32_mbox(tp, off, val);
 460         if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
 461             !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 462                 tp->read32_mbox(tp, off);
 463 }
 464
 465 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
 466 {
 467         void __iomem *mbox = tp->regs + off;
 468         writel(val, mbox);
 469         if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
 470                 writel(val, mbox);
 471         if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
 472                 readl(mbox);
 473 }
 474
 475 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
 476 {
 477         return (readl(tp->regs + off + GRCMBOX_BASE));
 478 }
 479
 480 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
 481 {
 482         writel(val, tp->regs + off + GRCMBOX_BASE);
 483 }
 484
 485 #define tw32_mailbox(reg, val)  tp->write32_mbox(tp, reg, val)
 486 #define tw32_mailbox_f(reg, val)        tw32_mailbox_flush(tp, (reg), (val))
 487 #define tw32_rx_mbox(reg, val)  tp->write32_rx_mbox(tp, reg, val)
 488 #define tw32_tx_mbox(reg, val)  tp->write32_tx_mbox(tp, reg, val)
 489 #define tr32_mailbox(reg)       tp->read32_mbox(tp, reg)
 490
 491 #define tw32(reg,val)           tp->write32(tp, reg, val)
 492 #define tw32_f(reg,val)         _tw32_flush(tp,(reg),(val), 0)
 493 #define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
 494 #define tr32(reg)               tp->read32(tp, reg)
 495
 496 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
 497 {
 498         unsigned long flags;
 499
 500         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 501             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
 502                 return;
 503
 504         spin_lock_irqsave(&tp->indirect_lock, flags);
 505         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 506                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 507                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 508
 509                 /* Always leave this as zero. */
 510                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 511         } else {
 512                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 513                 tw32_f(TG3PCI_MEM_WIN_DATA, val);
 514
 515                 /* Always leave this as zero. */
 516                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 517         }
 518         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 519 }
 520
 521 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
 522 {
 523         unsigned long flags;
 524
 525         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 526             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
 527                 *val = 0;
 528                 return;
 529         }
 530
 531         spin_lock_irqsave(&tp->indirect_lock, flags);
 532         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 533                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 534                 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 535
 536                 /* Always leave this as zero. */
 537                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 538         } else {
 539                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 540                 *val = tr32(TG3PCI_MEM_WIN_DATA);
 541
 542                 /* Always leave this as zero. */
 543                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 544         }
 545         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 546 }
 547
 548 static void tg3_ape_lock_init(struct tg3 *tp)
 549 {
 550         int i;
 551
 552         /* Make sure the driver hasn't any stale locks. */
 553         for (i = 0; i < 8; i++)
 554                 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + 4 * i,
 555                                 APE_LOCK_GRANT_DRIVER);
 556 }
 557
 558 static int tg3_ape_lock(struct tg3 *tp, int locknum)
 559 {
 560         int i, off;
 561         int ret = 0;
 562         u32 status;
 563
 564         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 565                 return 0;
 566
 567         switch (locknum) {
 568                 case TG3_APE_LOCK_GRC:
 569                 case TG3_APE_LOCK_MEM:
 570                         break;
 571                 default:
 572                         return -EINVAL;
 573         }
 574
 575         off = 4 * locknum;
 576
 577         tg3_ape_write32(tp, TG3_APE_LOCK_REQ + off, APE_LOCK_REQ_DRIVER);
 578
 579         /* Wait for up to 1 millisecond to acquire lock. */
 580         for (i = 0; i < 100; i++) {
 581                 status = tg3_ape_read32(tp, TG3_APE_LOCK_GRANT + off);
 582                 if (status == APE_LOCK_GRANT_DRIVER)
 583                         break;
 584                 udelay(10);
 585         }
 586
 587         if (status != APE_LOCK_GRANT_DRIVER) {
 588                 /* Revoke the lock request. */
 589                 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off,
 590                                 APE_LOCK_GRANT_DRIVER);
 591
 592                 ret = -EBUSY;
 593         }
 594
 595         return ret;
 596 }
 597
 598 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
 599 {
 600         int off;
 601
 602         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 603                 return;
 604
 605         switch (locknum) {
 606                 case TG3_APE_LOCK_GRC:
 607                 case TG3_APE_LOCK_MEM:
 608                         break;
 609                 default:
 610                         return;
 611         }
 612
 613         off = 4 * locknum;
 614         tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, APE_LOCK_GRANT_DRIVER);
 615 }
 616
 617 static void tg3_disable_ints(struct tg3 *tp)
 618 {
 619         int i;
 620
 621         tw32(TG3PCI_MISC_HOST_CTRL,
 622              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
 623         for (i = 0; i < tp->irq_max; i++)
 624                 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
 625 }
 626
 627 static void tg3_enable_ints(struct tg3 *tp)
 628 {
 629         int i;
 630         u32 coal_now = 0;
 631
 632         tp->irq_sync = 0;
 633         wmb();
 634
 635         tw32(TG3PCI_MISC_HOST_CTRL,
 636              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
 637
 638         for (i = 0; i < tp->irq_cnt; i++) {
 639                 struct tg3_napi *tnapi = &tp->napi[i];
 640                 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
 641                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
 642                         tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
 643
 644                 coal_now |= tnapi->coal_now;
 645         }
 646
 647         /* Force an initial interrupt */
 648         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 649             (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
 650                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
 651         else
 652                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 653                      HOSTCC_MODE_ENABLE | coal_now);
 654 }
 655
 656 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
 657 {
 658         struct tg3 *tp = tnapi->tp;
 659         struct tg3_hw_status *sblk = tnapi->hw_status;
 660         unsigned int work_exists = 0;
 661
 662         /* check for phy events */
 663         if (!(tp->tg3_flags &
 664               (TG3_FLAG_USE_LINKCHG_REG |
 665                TG3_FLAG_POLL_SERDES))) {
 666                 if (sblk->status & SD_STATUS_LINK_CHG)
 667                         work_exists = 1;
 668         }
 669         /* check for RX/TX work to do */
 670         if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
 671             *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
 672                 work_exists = 1;
 673
 674         return work_exists;
 675 }
 676
 677 /* tg3_int_reenable
 678  *  similar to tg3_enable_ints, but it accurately determines whether there
 679  *  is new work pending and can return without flushing the PIO write
 680  *  which reenables interrupts
 681  */
 682 static void tg3_int_reenable(struct tg3_napi *tnapi)
 683 {
 684         struct tg3 *tp = tnapi->tp;
 685
 686         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
 687         mmiowb();
 688
 689         /* When doing tagged status, this work check is unnecessary.
 690          * The last_tag we write above tells the chip which piece of
 691          * work we've completed.
 692          */
 693         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 694             tg3_has_work(tnapi))
 695                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 696                      HOSTCC_MODE_ENABLE | tnapi->coal_now);
 697 }
 698
 699 static void tg3_napi_disable(struct tg3 *tp)
 700 {
 701         int i;
 702
 703         for (i = tp->irq_cnt - 1; i >= 0; i--)
 704                 napi_disable(&tp->napi[i].napi);
 705 }
 706
 707 static void tg3_napi_enable(struct tg3 *tp)
 708 {
 709         int i;
 710
 711         for (i = 0; i < tp->irq_cnt; i++)
 712                 napi_enable(&tp->napi[i].napi);
 713 }
 714
 715 static inline void tg3_netif_stop(struct tg3 *tp)
 716 {
 717         tp->dev->trans_start = jiffies; /* prevent tx timeout */
 718         tg3_napi_disable(tp);
 719         netif_tx_disable(tp->dev);
 720 }
 721
 722 static inline void tg3_netif_start(struct tg3 *tp)
 723 {
 724         /* NOTE: unconditional netif_tx_wake_all_queues is only
 725          * appropriate so long as all callers are assured to
 726          * have free tx slots (such as after tg3_init_hw)
 727          */
 728         netif_tx_wake_all_queues(tp->dev);
 729
 730         tg3_napi_enable(tp);
 731         tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
 732         tg3_enable_ints(tp);
 733 }
 734
 735 static void tg3_switch_clocks(struct tg3 *tp)
 736 {
 737         u32 clock_ctrl;
 738         u32 orig_clock_ctrl;
 739
 740         if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
 741             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
 742                 return;
 743
 744         clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
 745
 746         orig_clock_ctrl = clock_ctrl;
 747         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
 748                        CLOCK_CTRL_CLKRUN_OENABLE |
 749                        0x1f);
 750         tp->pci_clock_ctrl = clock_ctrl;
 751
 752         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
 753                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
 754                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
 755                                     clock_ctrl | CLOCK_CTRL_625_CORE, 40);
 756                 }
 757         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
 758                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 759                             clock_ctrl |
 760                             (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
 761                             40);
 762                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 763                             clock_ctrl | (CLOCK_CTRL_ALTCLK),
 764                             40);
 765         }
 766         tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
 767 }
 768
 769 #define PHY_BUSY_LOOPS  5000
 770
 771 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
 772 {
 773         u32 frame_val;
 774         unsigned int loops;
 775         int ret;
 776
 777         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 778                 tw32_f(MAC_MI_MODE,
 779                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 780                 udelay(80);
 781         }
 782
 783         *val = 0x0;
 784
 785         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
 786                       MI_COM_PHY_ADDR_MASK);
 787         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 788                       MI_COM_REG_ADDR_MASK);
 789         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
 790
 791         tw32_f(MAC_MI_COM, frame_val);
 792
 793         loops = PHY_BUSY_LOOPS;
 794         while (loops != 0) {
 795                 udelay(10);
 796                 frame_val = tr32(MAC_MI_COM);
 797
 798                 if ((frame_val & MI_COM_BUSY) == 0) {
 799                         udelay(5);
 800                         frame_val = tr32(MAC_MI_COM);
 801                         break;
 802                 }
 803                 loops -= 1;
 804         }
 805
 806         ret = -EBUSY;
 807         if (loops != 0) {
 808                 *val = frame_val & MI_COM_DATA_MASK;
 809                 ret = 0;
 810         }
 811
 812         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 813                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 814                 udelay(80);
 815         }
 816
 817         return ret;
 818 }
 819
 820 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
 821 {
 822         u32 frame_val;
 823         unsigned int loops;
 824         int ret;
 825
 826         if ((tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
 827             (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
 828                 return 0;
 829
 830         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 831                 tw32_f(MAC_MI_MODE,
 832                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 833                 udelay(80);
 834         }
 835
 836         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
 837                       MI_COM_PHY_ADDR_MASK);
 838         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 839                       MI_COM_REG_ADDR_MASK);
 840         frame_val |= (val & MI_COM_DATA_MASK);
 841         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
 842
 843         tw32_f(MAC_MI_COM, frame_val);
 844
 845         loops = PHY_BUSY_LOOPS;
 846         while (loops != 0) {
 847                 udelay(10);
 848                 frame_val = tr32(MAC_MI_COM);
 849                 if ((frame_val & MI_COM_BUSY) == 0) {
 850                         udelay(5);
 851                         frame_val = tr32(MAC_MI_COM);
 852                         break;
 853                 }
 854                 loops -= 1;
 855         }
 856
 857         ret = -EBUSY;
 858         if (loops != 0)
 859                 ret = 0;
 860
 861         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 862                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 863                 udelay(80);
 864         }
 865
 866         return ret;
 867 }
 868
 869 static int tg3_bmcr_reset(struct tg3 *tp)
 870 {
 871         u32 phy_control;
 872         int limit, err;
 873
 874         /* OK, reset it, and poll the BMCR_RESET bit until it
 875          * clears or we time out.
 876          */
 877         phy_control = BMCR_RESET;
 878         err = tg3_writephy(tp, MII_BMCR, phy_control);
 879         if (err != 0)
 880                 return -EBUSY;
 881
 882         limit = 5000;
 883         while (limit--) {
 884                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
 885                 if (err != 0)
 886                         return -EBUSY;
 887
 888                 if ((phy_control & BMCR_RESET) == 0) {
 889                         udelay(40);
 890                         break;
 891                 }
 892                 udelay(10);
 893         }
 894         if (limit < 0)
 895                 return -EBUSY;
 896
 897         return 0;
 898 }
 899
 900 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
 901 {
 902         struct tg3 *tp = bp->priv;
 903         u32 val;
 904
 905         spin_lock_bh(&tp->lock);
 906
 907         if (tg3_readphy(tp, reg, &val))
 908                 val = -EIO;
 909
 910         spin_unlock_bh(&tp->lock);
 911
 912         return val;
 913 }
 914
 915 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
 916 {
 917         struct tg3 *tp = bp->priv;
 918         u32 ret = 0;
 919
 920         spin_lock_bh(&tp->lock);
 921
 922         if (tg3_writephy(tp, reg, val))
 923                 ret = -EIO;
 924
 925         spin_unlock_bh(&tp->lock);
 926
 927         return ret;
 928 }
 929
 930 static int tg3_mdio_reset(struct mii_bus *bp)
 931 {
 932         return 0;
 933 }
 934
 935 static void tg3_mdio_config_5785(struct tg3 *tp)
 936 {
 937         u32 val;
 938         struct phy_device *phydev;
 939
 940         phydev = tp->mdio_bus->phy_map[PHY_ADDR];
 941         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
 942         case TG3_PHY_ID_BCM50610:
 943                 val = MAC_PHYCFG2_50610_LED_MODES;
 944                 break;
 945         case TG3_PHY_ID_BCMAC131:
 946                 val = MAC_PHYCFG2_AC131_LED_MODES;
 947                 break;
 948         case TG3_PHY_ID_RTL8211C:
 949                 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
 950                 break;
 951         case TG3_PHY_ID_RTL8201E:
 952                 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
 953                 break;
 954         default:
 955                 return;
 956         }
 957
 958         if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
 959                 tw32(MAC_PHYCFG2, val);
 960
 961                 val = tr32(MAC_PHYCFG1);
 962                 val &= ~(MAC_PHYCFG1_RGMII_INT |
 963                          MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
 964                 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
 965                 tw32(MAC_PHYCFG1, val);
 966
 967                 return;
 968         }
 969
 970         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE))
 971                 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
 972                        MAC_PHYCFG2_FMODE_MASK_MASK |
 973                        MAC_PHYCFG2_GMODE_MASK_MASK |
 974                        MAC_PHYCFG2_ACT_MASK_MASK   |
 975                        MAC_PHYCFG2_QUAL_MASK_MASK |
 976                        MAC_PHYCFG2_INBAND_ENABLE;
 977
 978         tw32(MAC_PHYCFG2, val);
 979
 980         val = tr32(MAC_PHYCFG1);
 981         val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
 982                  MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
 983         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
 984                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
 985                         val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
 986                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
 987                         val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
 988         }
 989         val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
 990                MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
 991         tw32(MAC_PHYCFG1, val);
 992
 993         val = tr32(MAC_EXT_RGMII_MODE);
 994         val &= ~(MAC_RGMII_MODE_RX_INT_B |
 995                  MAC_RGMII_MODE_RX_QUALITY |
 996                  MAC_RGMII_MODE_RX_ACTIVITY |
 997                  MAC_RGMII_MODE_RX_ENG_DET |
 998                  MAC_RGMII_MODE_TX_ENABLE |
 999                  MAC_RGMII_MODE_TX_LOWPWR |
1000                  MAC_RGMII_MODE_TX_RESET);
1001         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
1002                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1003                         val |= MAC_RGMII_MODE_RX_INT_B |
1004                                MAC_RGMII_MODE_RX_QUALITY |
1005                                MAC_RGMII_MODE_RX_ACTIVITY |
1006                                MAC_RGMII_MODE_RX_ENG_DET;
1007                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1008                         val |= MAC_RGMII_MODE_TX_ENABLE |
1009                                MAC_RGMII_MODE_TX_LOWPWR |
1010                                MAC_RGMII_MODE_TX_RESET;
1011         }
1012         tw32(MAC_EXT_RGMII_MODE, val);
1013 }
1014
1015 static void tg3_mdio_start(struct tg3 *tp)
1016 {
1017         tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1018         tw32_f(MAC_MI_MODE, tp->mi_mode);
1019         udelay(80);
1020
1021         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
1022                 u32 funcnum, is_serdes;
1023
1024                 funcnum = tr32(TG3_CPMU_STATUS) & TG3_CPMU_STATUS_PCIE_FUNC;
1025                 if (funcnum)
1026                         tp->phy_addr = 2;
1027                 else
1028                         tp->phy_addr = 1;
1029
1030                 is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1031                 if (is_serdes)
1032                         tp->phy_addr += 7;
1033         } else
1034                 tp->phy_addr = PHY_ADDR;
1035
1036         if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
1037             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1038                 tg3_mdio_config_5785(tp);
1039 }
1040
1041 static int tg3_mdio_init(struct tg3 *tp)
1042 {
1043         int i;
1044         u32 reg;
1045         struct phy_device *phydev;
1046
1047         tg3_mdio_start(tp);
1048
1049         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1050             (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1051                 return 0;
1052
1053         tp->mdio_bus = mdiobus_alloc();
1054         if (tp->mdio_bus == NULL)
1055                 return -ENOMEM;
1056
1057         tp->mdio_bus->name     = "tg3 mdio bus";
1058         snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1059                  (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1060         tp->mdio_bus->priv     = tp;
1061         tp->mdio_bus->parent   = &tp->pdev->dev;
1062         tp->mdio_bus->read     = &tg3_mdio_read;
1063         tp->mdio_bus->write    = &tg3_mdio_write;
1064         tp->mdio_bus->reset    = &tg3_mdio_reset;
1065         tp->mdio_bus->phy_mask = ~(1 << PHY_ADDR);
1066         tp->mdio_bus->irq      = &tp->mdio_irq[0];
1067
1068         for (i = 0; i < PHY_MAX_ADDR; i++)
1069                 tp->mdio_bus->irq[i] = PHY_POLL;
1070
1071         /* The bus registration will look for all the PHYs on the mdio bus.
1072          * Unfortunately, it does not ensure the PHY is powered up before
1073          * accessing the PHY ID registers.  A chip reset is the
1074          * quickest way to bring the device back to an operational state..
1075          */
1076         if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1077                 tg3_bmcr_reset(tp);
1078
1079         i = mdiobus_register(tp->mdio_bus);
1080         if (i) {
1081                 printk(KERN_WARNING "%s: mdiobus_reg failed (0x%x)\n",
1082                         tp->dev->name, i);
1083                 mdiobus_free(tp->mdio_bus);
1084                 return i;
1085         }
1086
1087         phydev = tp->mdio_bus->phy_map[PHY_ADDR];
1088
1089         if (!phydev || !phydev->drv) {
1090                 printk(KERN_WARNING "%s: No PHY devices\n", tp->dev->name);
1091                 mdiobus_unregister(tp->mdio_bus);
1092                 mdiobus_free(tp->mdio_bus);
1093                 return -ENODEV;
1094         }
1095
1096         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1097         case TG3_PHY_ID_BCM57780:
1098                 phydev->interface = PHY_INTERFACE_MODE_GMII;
1099                 break;
1100         case TG3_PHY_ID_BCM50610:
1101                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)
1102                         phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1103                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1104                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1105                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1106                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1107                 /* fallthru */
1108         case TG3_PHY_ID_RTL8211C:
1109                 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1110                 break;
1111         case TG3_PHY_ID_RTL8201E:
1112         case TG3_PHY_ID_BCMAC131:
1113                 phydev->interface = PHY_INTERFACE_MODE_MII;
1114                 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
1115                 break;
1116         }
1117
1118         tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1119
1120         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1121                 tg3_mdio_config_5785(tp);
1122
1123         return 0;
1124 }
1125
1126 static void tg3_mdio_fini(struct tg3 *tp)
1127 {
1128         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1129                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
1130                 mdiobus_unregister(tp->mdio_bus);
1131                 mdiobus_free(tp->mdio_bus);
1132         }
1133 }
1134
1135 /* tp->lock is held. */
1136 static inline void tg3_generate_fw_event(struct tg3 *tp)
1137 {
1138         u32 val;
1139
1140         val = tr32(GRC_RX_CPU_EVENT);
1141         val |= GRC_RX_CPU_DRIVER_EVENT;
1142         tw32_f(GRC_RX_CPU_EVENT, val);
1143
1144         tp->last_event_jiffies = jiffies;
1145 }
1146
1147 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1148
1149 /* tp->lock is held. */
1150 static void tg3_wait_for_event_ack(struct tg3 *tp)
1151 {
1152         int i;
1153         unsigned int delay_cnt;
1154         long time_remain;
1155
1156         /* If enough time has passed, no wait is necessary. */
1157         time_remain = (long)(tp->last_event_jiffies + 1 +
1158                       usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1159                       (long)jiffies;
1160         if (time_remain < 0)
1161                 return;
1162
1163         /* Check if we can shorten the wait time. */
1164         delay_cnt = jiffies_to_usecs(time_remain);
1165         if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1166                 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1167         delay_cnt = (delay_cnt >> 3) + 1;
1168
1169         for (i = 0; i < delay_cnt; i++) {
1170                 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1171                         break;
1172                 udelay(8);
1173         }
1174 }
1175
1176 /* tp->lock is held. */
1177 static void tg3_ump_link_report(struct tg3 *tp)
1178 {
1179         u32 reg;
1180         u32 val;
1181
1182         if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1183             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
1184                 return;
1185
1186         tg3_wait_for_event_ack(tp);
1187
1188         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1189
1190         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1191
1192         val = 0;
1193         if (!tg3_readphy(tp, MII_BMCR, &reg))
1194                 val = reg << 16;
1195         if (!tg3_readphy(tp, MII_BMSR, &reg))
1196                 val |= (reg & 0xffff);
1197         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1198
1199         val = 0;
1200         if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1201                 val = reg << 16;
1202         if (!tg3_readphy(tp, MII_LPA, &reg))
1203                 val |= (reg & 0xffff);
1204         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1205
1206         val = 0;
1207         if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
1208                 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1209                         val = reg << 16;
1210                 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1211                         val |= (reg & 0xffff);
1212         }
1213         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1214
1215         if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1216                 val = reg << 16;
1217         else
1218                 val = 0;
1219         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1220
1221         tg3_generate_fw_event(tp);
1222 }
1223
1224 static void tg3_link_report(struct tg3 *tp)
1225 {
1226         if (!netif_carrier_ok(tp->dev)) {
1227                 if (netif_msg_link(tp))
1228                         printk(KERN_INFO PFX "%s: Link is down.\n",
1229                                tp->dev->name);
1230                 tg3_ump_link_report(tp);
1231         } else if (netif_msg_link(tp)) {
1232                 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1233                        tp->dev->name,
1234                        (tp->link_config.active_speed == SPEED_1000 ?
1235                         1000 :
1236                         (tp->link_config.active_speed == SPEED_100 ?
1237                          100 : 10)),
1238                        (tp->link_config.active_duplex == DUPLEX_FULL ?
1239                         "full" : "half"));
1240
1241                 printk(KERN_INFO PFX
1242                        "%s: Flow control is %s for TX and %s for RX.\n",
1243                        tp->dev->name,
1244                        (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1245                        "on" : "off",
1246                        (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1247                        "on" : "off");
1248                 tg3_ump_link_report(tp);
1249         }
1250 }
1251
1252 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1253 {
1254         u16 miireg;
1255
1256         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1257                 miireg = ADVERTISE_PAUSE_CAP;
1258         else if (flow_ctrl & FLOW_CTRL_TX)
1259                 miireg = ADVERTISE_PAUSE_ASYM;
1260         else if (flow_ctrl & FLOW_CTRL_RX)
1261                 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1262         else
1263                 miireg = 0;
1264
1265         return miireg;
1266 }
1267
1268 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1269 {
1270         u16 miireg;
1271
1272         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1273                 miireg = ADVERTISE_1000XPAUSE;
1274         else if (flow_ctrl & FLOW_CTRL_TX)
1275                 miireg = ADVERTISE_1000XPSE_ASYM;
1276         else if (flow_ctrl & FLOW_CTRL_RX)
1277                 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1278         else
1279                 miireg = 0;
1280
1281         return miireg;
1282 }
1283
1284 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1285 {
1286         u8 cap = 0;
1287
1288         if (lcladv & ADVERTISE_1000XPAUSE) {
1289                 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1290                         if (rmtadv & LPA_1000XPAUSE)
1291                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1292                         else if (rmtadv & LPA_1000XPAUSE_ASYM)
1293                                 cap = FLOW_CTRL_RX;
1294                 } else {
1295                         if (rmtadv & LPA_1000XPAUSE)
1296                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1297                 }
1298         } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1299                 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1300                         cap = FLOW_CTRL_TX;
1301         }
1302
1303         return cap;
1304 }
1305
1306 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1307 {
1308         u8 autoneg;
1309         u8 flowctrl = 0;
1310         u32 old_rx_mode = tp->rx_mode;
1311         u32 old_tx_mode = tp->tx_mode;
1312
1313         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
1314                 autoneg = tp->mdio_bus->phy_map[PHY_ADDR]->autoneg;
1315         else
1316                 autoneg = tp->link_config.autoneg;
1317
1318         if (autoneg == AUTONEG_ENABLE &&
1319             (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1320                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1321                         flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1322                 else
1323                         flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1324         } else
1325                 flowctrl = tp->link_config.flowctrl;
1326
1327         tp->link_config.active_flowctrl = flowctrl;
1328
1329         if (flowctrl & FLOW_CTRL_RX)
1330                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1331         else
1332                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1333
1334         if (old_rx_mode != tp->rx_mode)
1335                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1336
1337         if (flowctrl & FLOW_CTRL_TX)
1338                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1339         else
1340                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1341
1342         if (old_tx_mode != tp->tx_mode)
1343                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1344 }
1345
1346 static void tg3_adjust_link(struct net_device *dev)
1347 {
1348         u8 oldflowctrl, linkmesg = 0;
1349         u32 mac_mode, lcl_adv, rmt_adv;
1350         struct tg3 *tp = netdev_priv(dev);
1351         struct phy_device *phydev = tp->mdio_bus->phy_map[PHY_ADDR];
1352
1353         spin_lock_bh(&tp->lock);
1354
1355         mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1356                                     MAC_MODE_HALF_DUPLEX);
1357
1358         oldflowctrl = tp->link_config.active_flowctrl;
1359
1360         if (phydev->link) {
1361                 lcl_adv = 0;
1362                 rmt_adv = 0;
1363
1364                 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1365                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1366                 else
1367                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
1368
1369                 if (phydev->duplex == DUPLEX_HALF)
1370                         mac_mode |= MAC_MODE_HALF_DUPLEX;
1371                 else {
1372                         lcl_adv = tg3_advert_flowctrl_1000T(
1373                                   tp->link_config.flowctrl);
1374
1375                         if (phydev->pause)
1376                                 rmt_adv = LPA_PAUSE_CAP;
1377                         if (phydev->asym_pause)
1378                                 rmt_adv |= LPA_PAUSE_ASYM;
1379                 }
1380
1381                 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1382         } else
1383                 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1384
1385         if (mac_mode != tp->mac_mode) {
1386                 tp->mac_mode = mac_mode;
1387                 tw32_f(MAC_MODE, tp->mac_mode);
1388                 udelay(40);
1389         }
1390
1391         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1392                 if (phydev->speed == SPEED_10)
1393                         tw32(MAC_MI_STAT,
1394                              MAC_MI_STAT_10MBPS_MODE |
1395                              MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1396                 else
1397                         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1398         }
1399
1400         if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1401                 tw32(MAC_TX_LENGTHS,
1402                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1403                       (6 << TX_LENGTHS_IPG_SHIFT) |
1404                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1405         else
1406                 tw32(MAC_TX_LENGTHS,
1407                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1408                       (6 << TX_LENGTHS_IPG_SHIFT) |
1409                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1410
1411         if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1412             (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1413             phydev->speed != tp->link_config.active_speed ||
1414             phydev->duplex != tp->link_config.active_duplex ||
1415             oldflowctrl != tp->link_config.active_flowctrl)
1416             linkmesg = 1;
1417
1418         tp->link_config.active_speed = phydev->speed;
1419         tp->link_config.active_duplex = phydev->duplex;
1420
1421         spin_unlock_bh(&tp->lock);
1422
1423         if (linkmesg)
1424                 tg3_link_report(tp);
1425 }
1426
1427 static int tg3_phy_init(struct tg3 *tp)
1428 {
1429         struct phy_device *phydev;
1430
1431         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
1432                 return 0;
1433
1434         /* Bring the PHY back to a known state. */
1435         tg3_bmcr_reset(tp);
1436
1437         phydev = tp->mdio_bus->phy_map[PHY_ADDR];
1438
1439         /* Attach the MAC to the PHY. */
1440         phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1441                              phydev->dev_flags, phydev->interface);
1442         if (IS_ERR(phydev)) {
1443                 printk(KERN_ERR "%s: Could not attach to PHY\n", tp->dev->name);
1444                 return PTR_ERR(phydev);
1445         }
1446
1447         /* Mask with MAC supported features. */
1448         switch (phydev->interface) {
1449         case PHY_INTERFACE_MODE_GMII:
1450         case PHY_INTERFACE_MODE_RGMII:
1451                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1452                         phydev->supported &= (PHY_GBIT_FEATURES |
1453                                               SUPPORTED_Pause |
1454                                               SUPPORTED_Asym_Pause);
1455                         break;
1456                 }
1457                 /* fallthru */
1458         case PHY_INTERFACE_MODE_MII:
1459                 phydev->supported &= (PHY_BASIC_FEATURES |
1460                                       SUPPORTED_Pause |
1461                                       SUPPORTED_Asym_Pause);
1462                 break;
1463         default:
1464                 phy_disconnect(tp->mdio_bus->phy_map[PHY_ADDR]);
1465                 return -EINVAL;
1466         }
1467
1468         tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED;
1469
1470         phydev->advertising = phydev->supported;
1471
1472         return 0;
1473 }
1474
1475 static void tg3_phy_start(struct tg3 *tp)
1476 {
1477         struct phy_device *phydev;
1478
1479         if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1480                 return;
1481
1482         phydev = tp->mdio_bus->phy_map[PHY_ADDR];
1483
1484         if (tp->link_config.phy_is_low_power) {
1485                 tp->link_config.phy_is_low_power = 0;
1486                 phydev->speed = tp->link_config.orig_speed;
1487                 phydev->duplex = tp->link_config.orig_duplex;
1488                 phydev->autoneg = tp->link_config.orig_autoneg;
1489                 phydev->advertising = tp->link_config.orig_advertising;
1490         }
1491
1492         phy_start(phydev);
1493
1494         phy_start_aneg(phydev);
1495 }
1496
1497 static void tg3_phy_stop(struct tg3 *tp)
1498 {
1499         if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1500                 return;
1501
1502         phy_stop(tp->mdio_bus->phy_map[PHY_ADDR]);
1503 }
1504
1505 static void tg3_phy_fini(struct tg3 *tp)
1506 {
1507         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
1508                 phy_disconnect(tp->mdio_bus->phy_map[PHY_ADDR]);
1509                 tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED;
1510         }
1511 }
1512
1513 static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1514 {
1515         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1516         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1517 }
1518
1519 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1520 {
1521         u32 phytest;
1522
1523         if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1524                 u32 phy;
1525
1526                 tg3_writephy(tp, MII_TG3_FET_TEST,
1527                              phytest | MII_TG3_FET_SHADOW_EN);
1528                 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1529                         if (enable)
1530                                 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1531                         else
1532                                 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1533                         tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1534                 }
1535                 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1536         }
1537 }
1538
1539 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1540 {
1541         u32 reg;
1542
1543         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
1544                 return;
1545
1546         if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1547                 tg3_phy_fet_toggle_apd(tp, enable);
1548                 return;
1549         }
1550
1551         reg = MII_TG3_MISC_SHDW_WREN |
1552               MII_TG3_MISC_SHDW_SCR5_SEL |
1553               MII_TG3_MISC_SHDW_SCR5_LPED |
1554               MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1555               MII_TG3_MISC_SHDW_SCR5_SDTL |
1556               MII_TG3_MISC_SHDW_SCR5_C125OE;
1557         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1558                 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1559
1560         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1561
1562
1563         reg = MII_TG3_MISC_SHDW_WREN |
1564               MII_TG3_MISC_SHDW_APD_SEL |
1565               MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1566         if (enable)
1567                 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1568
1569         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1570 }
1571
1572 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1573 {
1574         u32 phy;
1575
1576         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1577             (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1578                 return;
1579
1580         if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1581                 u32 ephy;
1582
1583                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1584                         u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1585
1586                         tg3_writephy(tp, MII_TG3_FET_TEST,
1587                                      ephy | MII_TG3_FET_SHADOW_EN);
1588                         if (!tg3_readphy(tp, reg, &phy)) {
1589                                 if (enable)
1590                                         phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1591                                 else
1592                                         phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1593                                 tg3_writephy(tp, reg, phy);
1594                         }
1595                         tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
1596                 }
1597         } else {
1598                 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1599                       MII_TG3_AUXCTL_SHDWSEL_MISC;
1600                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1601                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1602                         if (enable)
1603                                 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1604                         else
1605                                 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1606                         phy |= MII_TG3_AUXCTL_MISC_WREN;
1607                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1608                 }
1609         }
1610 }
1611
1612 static void tg3_phy_set_wirespeed(struct tg3 *tp)
1613 {
1614         u32 val;
1615
1616         if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
1617                 return;
1618
1619         if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1620             !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1621                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1622                              (val | (1 << 15) | (1 << 4)));
1623 }
1624
1625 static void tg3_phy_apply_otp(struct tg3 *tp)
1626 {
1627         u32 otp, phy;
1628
1629         if (!tp->phy_otp)
1630                 return;
1631
1632         otp = tp->phy_otp;
1633
1634         /* Enable SM_DSP clock and tx 6dB coding. */
1635         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1636               MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1637               MII_TG3_AUXCTL_ACTL_TX_6DB;
1638         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1639
1640         phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1641         phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1642         tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1643
1644         phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1645               ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1646         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1647
1648         phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1649         phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1650         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1651
1652         phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1653         tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1654
1655         phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1656         tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1657
1658         phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1659               ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1660         tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1661
1662         /* Turn off SM_DSP clock. */
1663         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1664               MII_TG3_AUXCTL_ACTL_TX_6DB;
1665         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1666 }
1667
1668 static int tg3_wait_macro_done(struct tg3 *tp)
1669 {
1670         int limit = 100;
1671
1672         while (limit--) {
1673                 u32 tmp32;
1674
1675                 if (!tg3_readphy(tp, 0x16, &tmp32)) {
1676                         if ((tmp32 & 0x1000) == 0)
1677                                 break;
1678                 }
1679         }
1680         if (limit < 0)
1681                 return -EBUSY;
1682
1683         return 0;
1684 }
1685
1686 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1687 {
1688         static const u32 test_pat[4][6] = {
1689         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1690         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1691         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1692         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1693         };
1694         int chan;
1695
1696         for (chan = 0; chan < 4; chan++) {
1697                 int i;
1698
1699                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1700                              (chan * 0x2000) | 0x0200);
1701                 tg3_writephy(tp, 0x16, 0x0002);
1702
1703                 for (i = 0; i < 6; i++)
1704                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1705                                      test_pat[chan][i]);
1706
1707                 tg3_writephy(tp, 0x16, 0x0202);
1708                 if (tg3_wait_macro_done(tp)) {
1709                         *resetp = 1;
1710                         return -EBUSY;
1711                 }
1712
1713                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1714                              (chan * 0x2000) | 0x0200);
1715                 tg3_writephy(tp, 0x16, 0x0082);
1716                 if (tg3_wait_macro_done(tp)) {
1717                         *resetp = 1;
1718                         return -EBUSY;
1719                 }
1720
1721                 tg3_writephy(tp, 0x16, 0x0802);
1722                 if (tg3_wait_macro_done(tp)) {
1723                         *resetp = 1;
1724                         return -EBUSY;
1725                 }
1726
1727                 for (i = 0; i < 6; i += 2) {
1728                         u32 low, high;
1729
1730                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1731                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1732                             tg3_wait_macro_done(tp)) {
1733                                 *resetp = 1;
1734                                 return -EBUSY;
1735                         }
1736                         low &= 0x7fff;
1737                         high &= 0x000f;
1738                         if (low != test_pat[chan][i] ||
1739                             high != test_pat[chan][i+1]) {
1740                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1741                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1742                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1743
1744                                 return -EBUSY;
1745                         }
1746                 }
1747         }
1748
1749         return 0;
1750 }
1751
1752 static int tg3_phy_reset_chanpat(struct tg3 *tp)
1753 {
1754         int chan;
1755
1756         for (chan = 0; chan < 4; chan++) {
1757                 int i;
1758
1759                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1760                              (chan * 0x2000) | 0x0200);
1761                 tg3_writephy(tp, 0x16, 0x0002);
1762                 for (i = 0; i < 6; i++)
1763                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1764                 tg3_writephy(tp, 0x16, 0x0202);
1765                 if (tg3_wait_macro_done(tp))
1766                         return -EBUSY;
1767         }
1768
1769         return 0;
1770 }
1771
1772 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1773 {
1774         u32 reg32, phy9_orig;
1775         int retries, do_phy_reset, err;
1776
1777         retries = 10;
1778         do_phy_reset = 1;
1779         do {
1780                 if (do_phy_reset) {
1781                         err = tg3_bmcr_reset(tp);
1782                         if (err)
1783                                 return err;
1784                         do_phy_reset = 0;
1785                 }
1786
1787                 /* Disable transmitter and interrupt.  */
1788                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1789                         continue;
1790
1791                 reg32 |= 0x3000;
1792                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1793
1794                 /* Set full-duplex, 1000 mbps.  */
1795                 tg3_writephy(tp, MII_BMCR,
1796                              BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1797
1798                 /* Set to master mode.  */
1799                 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1800                         continue;
1801
1802                 tg3_writephy(tp, MII_TG3_CTRL,
1803                              (MII_TG3_CTRL_AS_MASTER |
1804                               MII_TG3_CTRL_ENABLE_AS_MASTER));
1805
1806                 /* Enable SM_DSP_CLOCK and 6dB.  */
1807                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1808
1809                 /* Block the PHY control access.  */
1810                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1811                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
1812
1813                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1814                 if (!err)
1815                         break;
1816         } while (--retries);
1817
1818         err = tg3_phy_reset_chanpat(tp);
1819         if (err)
1820                 return err;
1821
1822         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1823         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
1824
1825         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1826         tg3_writephy(tp, 0x16, 0x0000);
1827
1828         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1829             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1830                 /* Set Extended packet length bit for jumbo frames */
1831                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1832         }
1833         else {
1834                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1835         }
1836
1837         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1838
1839         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1840                 reg32 &= ~0x3000;
1841                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1842         } else if (!err)
1843                 err = -EBUSY;
1844
1845         return err;
1846 }
1847
1848 /* This will reset the tigon3 PHY if there is no valid
1849  * link unless the FORCE argument is non-zero.
1850  */
1851 static int tg3_phy_reset(struct tg3 *tp)
1852 {
1853         u32 cpmuctrl;
1854         u32 phy_status;
1855         int err;
1856
1857         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1858                 u32 val;
1859
1860                 val = tr32(GRC_MISC_CFG);
1861                 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1862                 udelay(40);
1863         }
1864         err  = tg3_readphy(tp, MII_BMSR, &phy_status);
1865         err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1866         if (err != 0)
1867                 return -EBUSY;
1868
1869         if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1870                 netif_carrier_off(tp->dev);
1871                 tg3_link_report(tp);
1872         }
1873
1874         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1875             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1876             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1877                 err = tg3_phy_reset_5703_4_5(tp);
1878                 if (err)
1879                         return err;
1880                 goto out;
1881         }
1882
1883         cpmuctrl = 0;
1884         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1885             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1886                 cpmuctrl = tr32(TG3_CPMU_CTRL);
1887                 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1888                         tw32(TG3_CPMU_CTRL,
1889                              cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1890         }
1891
1892         err = tg3_bmcr_reset(tp);
1893         if (err)
1894                 return err;
1895
1896         if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1897                 u32 phy;
1898
1899                 phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1900                 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
1901
1902                 tw32(TG3_CPMU_CTRL, cpmuctrl);
1903         }
1904
1905         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
1906             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
1907                 u32 val;
1908
1909                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1910                 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1911                     CPMU_LSPD_1000MB_MACCLK_12_5) {
1912                         val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1913                         udelay(40);
1914                         tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1915                 }
1916         }
1917
1918         tg3_phy_apply_otp(tp);
1919
1920         if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
1921                 tg3_phy_toggle_apd(tp, true);
1922         else
1923                 tg3_phy_toggle_apd(tp, false);
1924
1925 out:
1926         if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1927                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1928                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1929                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1930                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1931                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1932                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1933         }
1934         if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1935                 tg3_writephy(tp, 0x1c, 0x8d68);
1936                 tg3_writephy(tp, 0x1c, 0x8d68);
1937         }
1938         if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1939                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1940                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1941                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1942                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1943                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1944                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1945                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1946                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1947         }
1948         else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1949                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1950                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1951                 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1952                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1953                         tg3_writephy(tp, MII_TG3_TEST1,
1954                                      MII_TG3_TEST1_TRIM_EN | 0x4);
1955                 } else
1956                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
1957                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1958         }
1959         /* Set Extended packet length bit (bit 14) on all chips that */
1960         /* support jumbo frames */
1961         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1962                 /* Cannot do read-modify-write on 5401 */
1963                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1964         } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1965                 u32 phy_reg;
1966
1967                 /* Set bit 14 with read-modify-write to preserve other bits */
1968                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1969                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1970                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1971         }
1972
1973         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1974          * jumbo frames transmission.
1975          */
1976         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1977                 u32 phy_reg;
1978
1979                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
1980                     tg3_writephy(tp, MII_TG3_EXT_CTRL,
1981                                  phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1982         }
1983
1984         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1985                 /* adjust output voltage */
1986                 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
1987         }
1988
1989         tg3_phy_toggle_automdix(tp, 1);
1990         tg3_phy_set_wirespeed(tp);
1991         return 0;
1992 }
1993
1994 static void tg3_frob_aux_power(struct tg3 *tp)
1995 {
1996         struct tg3 *tp_peer = tp;
1997
1998         if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
1999                 return;
2000
2001         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2002             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
2003             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
2004                 struct net_device *dev_peer;
2005
2006                 dev_peer = pci_get_drvdata(tp->pdev_peer);
2007                 /* remove_one() may have been run on the peer. */
2008                 if (!dev_peer)
2009                         tp_peer = tp;
2010                 else
2011                         tp_peer = netdev_priv(dev_peer);
2012         }
2013
2014         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2015             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
2016             (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2017             (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
2018                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2019                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2020                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2021                                     (GRC_LCLCTRL_GPIO_OE0 |
2022                                      GRC_LCLCTRL_GPIO_OE1 |
2023                                      GRC_LCLCTRL_GPIO_OE2 |
2024                                      GRC_LCLCTRL_GPIO_OUTPUT0 |
2025                                      GRC_LCLCTRL_GPIO_OUTPUT1),
2026                                     100);
2027                 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2028                            tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2029                         /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2030                         u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2031                                              GRC_LCLCTRL_GPIO_OE1 |
2032                                              GRC_LCLCTRL_GPIO_OE2 |
2033                                              GRC_LCLCTRL_GPIO_OUTPUT0 |
2034                                              GRC_LCLCTRL_GPIO_OUTPUT1 |
2035                                              tp->grc_local_ctrl;
2036                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2037
2038                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2039                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2040
2041                         grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2042                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2043                 } else {
2044                         u32 no_gpio2;
2045                         u32 grc_local_ctrl = 0;
2046
2047                         if (tp_peer != tp &&
2048                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2049                                 return;
2050
2051                         /* Workaround to prevent overdrawing Amps. */
2052                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2053                             ASIC_REV_5714) {
2054                                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2055                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2056                                             grc_local_ctrl, 100);
2057                         }
2058
2059                         /* On 5753 and variants, GPIO2 cannot be used. */
2060                         no_gpio2 = tp->nic_sram_data_cfg &
2061                                     NIC_SRAM_DATA_CFG_NO_GPIO2;
2062
2063                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2064                                          GRC_LCLCTRL_GPIO_OE1 |
2065                                          GRC_LCLCTRL_GPIO_OE2 |
2066                                          GRC_LCLCTRL_GPIO_OUTPUT1 |
2067                                          GRC_LCLCTRL_GPIO_OUTPUT2;
2068                         if (no_gpio2) {
2069                                 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2070                                                     GRC_LCLCTRL_GPIO_OUTPUT2);
2071                         }
2072                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2073                                                     grc_local_ctrl, 100);
2074
2075                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2076
2077                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2078                                                     grc_local_ctrl, 100);
2079
2080                         if (!no_gpio2) {
2081                                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2082                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2083                                             grc_local_ctrl, 100);
2084                         }
2085                 }
2086         } else {
2087                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2088                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2089                         if (tp_peer != tp &&
2090                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2091                                 return;
2092
2093                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2094                                     (GRC_LCLCTRL_GPIO_OE1 |
2095                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2096
2097                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2098                                     GRC_LCLCTRL_GPIO_OE1, 100);
2099
2100                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2101                                     (GRC_LCLCTRL_GPIO_OE1 |
2102                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2103                 }
2104         }
2105 }
2106
2107 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2108 {
2109         if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2110                 return 1;
2111         else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) {
2112                 if (speed != SPEED_10)
2113                         return 1;
2114         } else if (speed == SPEED_10)
2115                 return 1;
2116
2117         return 0;
2118 }
2119
2120 static int tg3_setup_phy(struct tg3 *, int);
2121
2122 #define RESET_KIND_SHUTDOWN     0
2123 #define RESET_KIND_INIT         1
2124 #define RESET_KIND_SUSPEND      2
2125
2126 static void tg3_write_sig_post_reset(struct tg3 *, int);
2127 static int tg3_halt_cpu(struct tg3 *, u32);
2128
2129 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2130 {
2131         u32 val;
2132
2133         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2134                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2135                         u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2136                         u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2137
2138                         sg_dig_ctrl |=
2139                                 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2140                         tw32(SG_DIG_CTRL, sg_dig_ctrl);
2141                         tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2142                 }
2143                 return;
2144         }
2145
2146         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2147                 tg3_bmcr_reset(tp);
2148                 val = tr32(GRC_MISC_CFG);
2149                 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2150                 udelay(40);
2151                 return;
2152         } else if (do_low_power) {
2153                 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2154                              MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2155
2156                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2157                              MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2158                              MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2159                              MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2160                              MII_TG3_AUXCTL_PCTL_VREG_11V);
2161         }
2162
2163         /* The PHY should not be powered down on some chips because
2164          * of bugs.
2165          */
2166         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2167             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2168             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2169              (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
2170                 return;
2171
2172         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2173             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2174                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2175                 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2176                 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2177                 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2178         }
2179
2180         tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2181 }
2182
2183 /* tp->lock is held. */
2184 static int tg3_nvram_lock(struct tg3 *tp)
2185 {
2186         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2187                 int i;
2188
2189                 if (tp->nvram_lock_cnt == 0) {
2190                         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2191                         for (i = 0; i < 8000; i++) {
2192                                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2193                                         break;
2194                                 udelay(20);
2195                         }
2196                         if (i == 8000) {
2197                                 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2198                                 return -ENODEV;
2199                         }
2200                 }
2201                 tp->nvram_lock_cnt++;
2202         }
2203         return 0;
2204 }
2205
2206 /* tp->lock is held. */
2207 static void tg3_nvram_unlock(struct tg3 *tp)
2208 {
2209         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2210                 if (tp->nvram_lock_cnt > 0)
2211                         tp->nvram_lock_cnt--;
2212                 if (tp->nvram_lock_cnt == 0)
2213                         tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2214         }
2215 }
2216
2217 /* tp->lock is held. */
2218 static void tg3_enable_nvram_access(struct tg3 *tp)
2219 {
2220         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2221             !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
2222                 u32 nvaccess = tr32(NVRAM_ACCESS);
2223
2224                 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2225         }
2226 }
2227
2228 /* tp->lock is held. */
2229 static void tg3_disable_nvram_access(struct tg3 *tp)
2230 {
2231         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2232             !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
2233                 u32 nvaccess = tr32(NVRAM_ACCESS);
2234
2235                 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2236         }
2237 }
2238
2239 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2240                                         u32 offset, u32 *val)
2241 {
2242         u32 tmp;
2243         int i;
2244
2245         if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2246                 return -EINVAL;
2247
2248         tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2249                                         EEPROM_ADDR_DEVID_MASK |
2250                                         EEPROM_ADDR_READ);
2251         tw32(GRC_EEPROM_ADDR,
2252              tmp |
2253              (0 << EEPROM_ADDR_DEVID_SHIFT) |
2254              ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2255               EEPROM_ADDR_ADDR_MASK) |
2256              EEPROM_ADDR_READ | EEPROM_ADDR_START);
2257
2258         for (i = 0; i < 1000; i++) {
2259                 tmp = tr32(GRC_EEPROM_ADDR);
2260
2261                 if (tmp & EEPROM_ADDR_COMPLETE)
2262                         break;
2263                 msleep(1);
2264         }
2265         if (!(tmp & EEPROM_ADDR_COMPLETE))
2266                 return -EBUSY;
2267
2268         tmp = tr32(GRC_EEPROM_DATA);
2269
2270         /*
2271          * The data will always be opposite the native endian
2272          * format.  Perform a blind byteswap to compensate.
2273          */
2274         *val = swab32(tmp);
2275
2276         return 0;
2277 }
2278
2279 #define NVRAM_CMD_TIMEOUT 10000
2280
2281 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2282 {
2283         int i;
2284
2285         tw32(NVRAM_CMD, nvram_cmd);
2286         for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2287                 udelay(10);
2288                 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2289                         udelay(10);
2290                         break;
2291                 }
2292         }
2293
2294         if (i == NVRAM_CMD_TIMEOUT)
2295                 return -EBUSY;
2296
2297         return 0;
2298 }
2299
2300 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2301 {
2302         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2303             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2304             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2305            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2306             (tp->nvram_jedecnum == JEDEC_ATMEL))
2307
2308                 addr = ((addr / tp->nvram_pagesize) <<
2309                         ATMEL_AT45DB0X1B_PAGE_POS) +
2310                        (addr % tp->nvram_pagesize);
2311
2312         return addr;
2313 }
2314
2315 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2316 {
2317         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2318             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2319             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2320            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2321             (tp->nvram_jedecnum == JEDEC_ATMEL))
2322
2323                 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2324                         tp->nvram_pagesize) +
2325                        (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2326
2327         return addr;
2328 }
2329
2330 /* NOTE: Data read in from NVRAM is byteswapped according to
2331  * the byteswapping settings for all other register accesses.
2332  * tg3 devices are BE devices, so on a BE machine, the data
2333  * returned will be exactly as it is seen in NVRAM.  On a LE
2334  * machine, the 32-bit value will be byteswapped.
2335  */
2336 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2337 {
2338         int ret;
2339
2340         if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2341                 return tg3_nvram_read_using_eeprom(tp, offset, val);
2342
2343         offset = tg3_nvram_phys_addr(tp, offset);
2344
2345         if (offset > NVRAM_ADDR_MSK)
2346                 return -EINVAL;
2347
2348         ret = tg3_nvram_lock(tp);
2349         if (ret)
2350                 return ret;
2351
2352         tg3_enable_nvram_access(tp);
2353
2354         tw32(NVRAM_ADDR, offset);
2355         ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2356                 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2357
2358         if (ret == 0)
2359                 *val = tr32(NVRAM_RDDATA);
2360
2361         tg3_disable_nvram_access(tp);
2362
2363         tg3_nvram_unlock(tp);
2364
2365         return ret;
2366 }
2367
2368 /* Ensures NVRAM data is in bytestream format. */
2369 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
2370 {
2371         u32 v;
2372         int res = tg3_nvram_read(tp, offset, &v);
2373         if (!res)
2374                 *val = cpu_to_be32(v);
2375         return res;
2376 }
2377
2378 /* tp->lock is held. */
2379 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2380 {
2381         u32 addr_high, addr_low;
2382         int i;
2383
2384         addr_high = ((tp->dev->dev_addr[0] << 8) |
2385                      tp->dev->dev_addr[1]);
2386         addr_low = ((tp->dev->dev_addr[2] << 24) |
2387                     (tp->dev->dev_addr[3] << 16) |
2388                     (tp->dev->dev_addr[4] <<  8) |
2389                     (tp->dev->dev_addr[5] <<  0));
2390         for (i = 0; i < 4; i++) {
2391                 if (i == 1 && skip_mac_1)
2392                         continue;
2393                 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2394                 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2395         }
2396
2397         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2398             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2399                 for (i = 0; i < 12; i++) {
2400                         tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2401                         tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2402                 }
2403         }
2404
2405         addr_high = (tp->dev->dev_addr[0] +
2406                      tp->dev->dev_addr[1] +
2407                      tp->dev->dev_addr[2] +
2408                      tp->dev->dev_addr[3] +
2409                      tp->dev->dev_addr[4] +
2410                      tp->dev->dev_addr[5]) &
2411                 TX_BACKOFF_SEED_MASK;
2412         tw32(MAC_TX_BACKOFF_SEED, addr_high);
2413 }
2414
2415 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
2416 {
2417         u32 misc_host_ctrl;
2418         bool device_should_wake, do_low_power;
2419
2420         /* Make sure register accesses (indirect or otherwise)
2421          * will function correctly.
2422          */
2423         pci_write_config_dword(tp->pdev,
2424                                TG3PCI_MISC_HOST_CTRL,
2425                                tp->misc_host_ctrl);
2426
2427         switch (state) {
2428         case PCI_D0:
2429                 pci_enable_wake(tp->pdev, state, false);
2430                 pci_set_power_state(tp->pdev, PCI_D0);
2431
2432                 /* Switch out of Vaux if it is a NIC */
2433                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
2434                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
2435
2436                 return 0;
2437
2438         case PCI_D1:
2439         case PCI_D2:
2440         case PCI_D3hot:
2441                 break;
2442
2443         default:
2444                 printk(KERN_ERR PFX "%s: Invalid power state (D%d) requested\n",
2445                         tp->dev->name, state);
2446                 return -EINVAL;
2447         }
2448
2449         /* Restore the CLKREQ setting. */
2450         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2451                 u16 lnkctl;
2452
2453                 pci_read_config_word(tp->pdev,
2454                                      tp->pcie_cap + PCI_EXP_LNKCTL,
2455                                      &lnkctl);
2456                 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2457                 pci_write_config_word(tp->pdev,
2458                                       tp->pcie_cap + PCI_EXP_LNKCTL,
2459                                       lnkctl);
2460         }
2461
2462         misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2463         tw32(TG3PCI_MISC_HOST_CTRL,
2464              misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2465
2466         device_should_wake = pci_pme_capable(tp->pdev, state) &&
2467                              device_may_wakeup(&tp->pdev->dev) &&
2468                              (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2469
2470         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
2471                 do_low_power = false;
2472                 if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) &&
2473                     !tp->link_config.phy_is_low_power) {
2474                         struct phy_device *phydev;
2475                         u32 phyid, advertising;
2476
2477                         phydev = tp->mdio_bus->phy_map[PHY_ADDR];
2478
2479                         tp->link_config.phy_is_low_power = 1;
2480
2481                         tp->link_config.orig_speed = phydev->speed;
2482                         tp->link_config.orig_duplex = phydev->duplex;
2483                         tp->link_config.orig_autoneg = phydev->autoneg;
2484                         tp->link_config.orig_advertising = phydev->advertising;
2485
2486                         advertising = ADVERTISED_TP |
2487                                       ADVERTISED_Pause |
2488                                       ADVERTISED_Autoneg |
2489                                       ADVERTISED_10baseT_Half;
2490
2491                         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2492                             device_should_wake) {
2493                                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2494                                         advertising |=
2495                                                 ADVERTISED_100baseT_Half |
2496                                                 ADVERTISED_100baseT_Full |
2497                                                 ADVERTISED_10baseT_Full;
2498                                 else
2499                                         advertising |= ADVERTISED_10baseT_Full;
2500                         }
2501
2502                         phydev->advertising = advertising;
2503
2504                         phy_start_aneg(phydev);
2505
2506                         phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2507                         if (phyid != TG3_PHY_ID_BCMAC131) {
2508                                 phyid &= TG3_PHY_OUI_MASK;
2509                                 if (phyid == TG3_PHY_OUI_1 ||
2510                                     phyid == TG3_PHY_OUI_2 ||
2511                                     phyid == TG3_PHY_OUI_3)
2512                                         do_low_power = true;
2513                         }
2514                 }
2515         } else {
2516                 do_low_power = true;
2517
2518                 if (tp->link_config.phy_is_low_power == 0) {
2519                         tp->link_config.phy_is_low_power = 1;
2520                         tp->link_config.orig_speed = tp->link_config.speed;
2521                         tp->link_config.orig_duplex = tp->link_config.duplex;
2522                         tp->link_config.orig_autoneg = tp->link_config.autoneg;
2523                 }
2524
2525                 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
2526                         tp->link_config.speed = SPEED_10;
2527                         tp->link_config.duplex = DUPLEX_HALF;
2528                         tp->link_config.autoneg = AUTONEG_ENABLE;
2529                         tg3_setup_phy(tp, 0);
2530                 }
2531         }
2532
2533         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2534                 u32 val;
2535
2536                 val = tr32(GRC_VCPU_EXT_CTRL);
2537                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2538         } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2539                 int i;
2540                 u32 val;
2541
2542                 for (i = 0; i < 200; i++) {
2543                         tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2544                         if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2545                                 break;
2546                         msleep(1);
2547                 }
2548         }
2549         if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2550                 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2551                                                      WOL_DRV_STATE_SHUTDOWN |
2552                                                      WOL_DRV_WOL |
2553                                                      WOL_SET_MAGIC_PKT);
2554
2555         if (device_should_wake) {
2556                 u32 mac_mode;
2557
2558                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
2559                         if (do_low_power) {
2560                                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2561                                 udelay(40);
2562                         }
2563
2564                         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
2565                                 mac_mode = MAC_MODE_PORT_MODE_GMII;
2566                         else
2567                                 mac_mode = MAC_MODE_PORT_MODE_MII;
2568
2569                         mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2570                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2571                             ASIC_REV_5700) {
2572                                 u32 speed = (tp->tg3_flags &
2573                                              TG3_FLAG_WOL_SPEED_100MB) ?
2574                                              SPEED_100 : SPEED_10;
2575                                 if (tg3_5700_link_polarity(tp, speed))
2576                                         mac_mode |= MAC_MODE_LINK_POLARITY;
2577                                 else
2578                                         mac_mode &= ~MAC_MODE_LINK_POLARITY;
2579                         }
2580                 } else {
2581                         mac_mode = MAC_MODE_PORT_MODE_TBI;
2582                 }
2583
2584                 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
2585                         tw32(MAC_LED_CTRL, tp->led_ctrl);
2586
2587                 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2588                 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2589                     !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2590                     ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2591                      (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2592                         mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
2593
2594                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2595                         mac_mode |= tp->mac_mode &
2596                                     (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2597                         if (mac_mode & MAC_MODE_APE_TX_EN)
2598                                 mac_mode |= MAC_MODE_TDE_ENABLE;
2599                 }
2600
2601                 tw32_f(MAC_MODE, mac_mode);
2602                 udelay(100);
2603
2604                 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2605                 udelay(10);
2606         }
2607
2608         if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2609             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2610              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2611                 u32 base_val;
2612
2613                 base_val = tp->pci_clock_ctrl;
2614                 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2615                              CLOCK_CTRL_TXCLK_DISABLE);
2616
2617                 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2618                             CLOCK_CTRL_PWRDOWN_PLL133, 40);
2619         } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
2620                    (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
2621                    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
2622                 /* do nothing */
2623         } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2624                      (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2625                 u32 newbits1, newbits2;
2626
2627                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2628                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2629                         newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2630                                     CLOCK_CTRL_TXCLK_DISABLE |
2631                                     CLOCK_CTRL_ALTCLK);
2632                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2633                 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2634                         newbits1 = CLOCK_CTRL_625_CORE;
2635                         newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2636                 } else {
2637                         newbits1 = CLOCK_CTRL_ALTCLK;
2638                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2639                 }
2640
2641                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2642                             40);
2643
2644                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2645                             40);
2646
2647                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2648                         u32 newbits3;
2649
2650                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2651                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2652                                 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2653                                             CLOCK_CTRL_TXCLK_DISABLE |
2654                                             CLOCK_CTRL_44MHZ_CORE);
2655                         } else {
2656                                 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2657                         }
2658
2659                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
2660                                     tp->pci_clock_ctrl | newbits3, 40);
2661                 }
2662         }
2663
2664         if (!(device_should_wake) &&
2665             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
2666                 tg3_power_down_phy(tp, do_low_power);
2667
2668         tg3_frob_aux_power(tp);
2669
2670         /* Workaround for unstable PLL clock */
2671         if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2672             (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2673                 u32 val = tr32(0x7d00);
2674
2675                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2676                 tw32(0x7d00, val);
2677                 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2678                         int err;
2679
2680                         err = tg3_nvram_lock(tp);
2681                         tg3_halt_cpu(tp, RX_CPU_BASE);
2682                         if (!err)
2683                                 tg3_nvram_unlock(tp);
2684                 }
2685         }
2686
2687         tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2688
2689         if (device_should_wake)
2690                 pci_enable_wake(tp->pdev, state, true);
2691
2692         /* Finally, set the new power state. */
2693         pci_set_power_state(tp->pdev, state);
2694
2695         return 0;
2696 }
2697
2698 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2699 {
2700         switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2701         case MII_TG3_AUX_STAT_10HALF:
2702                 *speed = SPEED_10;
2703                 *duplex = DUPLEX_HALF;
2704                 break;
2705
2706         case MII_TG3_AUX_STAT_10FULL:
2707                 *speed = SPEED_10;
2708                 *duplex = DUPLEX_FULL;
2709                 break;
2710
2711         case MII_TG3_AUX_STAT_100HALF:
2712                 *speed = SPEED_100;
2713                 *duplex = DUPLEX_HALF;
2714                 break;
2715
2716         case MII_TG3_AUX_STAT_100FULL:
2717                 *speed = SPEED_100;
2718                 *duplex = DUPLEX_FULL;
2719                 break;
2720
2721         case MII_TG3_AUX_STAT_1000HALF:
2722                 *speed = SPEED_1000;
2723                 *duplex = DUPLEX_HALF;
2724                 break;
2725
2726         case MII_TG3_AUX_STAT_1000FULL:
2727                 *speed = SPEED_1000;
2728                 *duplex = DUPLEX_FULL;
2729                 break;
2730
2731         default:
2732                 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
2733                         *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2734                                  SPEED_10;
2735                         *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2736                                   DUPLEX_HALF;
2737                         break;
2738                 }
2739                 *speed = SPEED_INVALID;
2740                 *duplex = DUPLEX_INVALID;
2741                 break;
2742         }
2743 }
2744
2745 static void tg3_phy_copper_begin(struct tg3 *tp)
2746 {
2747         u32 new_adv;
2748         int i;
2749
2750         if (tp->link_config.phy_is_low_power) {
2751                 /* Entering low power mode.  Disable gigabit and
2752                  * 100baseT advertisements.
2753                  */
2754                 tg3_writephy(tp, MII_TG3_CTRL, 0);
2755
2756                 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2757                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2758                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2759                         new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2760
2761                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2762         } else if (tp->link_config.speed == SPEED_INVALID) {
2763                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2764                         tp->link_config.advertising &=
2765                                 ~(ADVERTISED_1000baseT_Half |
2766                                   ADVERTISED_1000baseT_Full);
2767
2768                 new_adv = ADVERTISE_CSMA;
2769                 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2770                         new_adv |= ADVERTISE_10HALF;
2771                 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2772                         new_adv |= ADVERTISE_10FULL;
2773                 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2774                         new_adv |= ADVERTISE_100HALF;
2775                 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2776                         new_adv |= ADVERTISE_100FULL;
2777
2778                 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2779
2780                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2781
2782                 if (tp->link_config.advertising &
2783                     (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2784                         new_adv = 0;
2785                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2786                                 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2787                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2788                                 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2789                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
2790                             (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2791                              tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2792                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2793                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2794                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2795                 } else {
2796                         tg3_writephy(tp, MII_TG3_CTRL, 0);
2797                 }
2798         } else {
2799                 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2800                 new_adv |= ADVERTISE_CSMA;
2801
2802                 /* Asking for a specific link mode. */
2803                 if (tp->link_config.speed == SPEED_1000) {
2804                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2805
2806                         if (tp->link_config.duplex == DUPLEX_FULL)
2807                                 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2808                         else
2809                                 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2810                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2811                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2812                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2813                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2814                 } else {
2815                         if (tp->link_config.speed == SPEED_100) {
2816                                 if (tp->link_config.duplex == DUPLEX_FULL)
2817                                         new_adv |= ADVERTISE_100FULL;
2818                                 else
2819                                         new_adv |= ADVERTISE_100HALF;
2820                         } else {
2821                                 if (tp->link_config.duplex == DUPLEX_FULL)
2822                                         new_adv |= ADVERTISE_10FULL;
2823                                 else
2824                                         new_adv |= ADVERTISE_10HALF;
2825                         }
2826                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2827
2828                         new_adv = 0;
2829                 }
2830
2831                 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2832         }
2833
2834         if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2835             tp->link_config.speed != SPEED_INVALID) {
2836                 u32 bmcr, orig_bmcr;
2837
2838                 tp->link_config.active_speed = tp->link_config.speed;
2839                 tp->link_config.active_duplex = tp->link_config.duplex;
2840
2841                 bmcr = 0;
2842                 switch (tp->link_config.speed) {
2843                 default:
2844                 case SPEED_10:
2845                         break;
2846
2847                 case SPEED_100:
2848                         bmcr |= BMCR_SPEED100;
2849                         break;
2850
2851                 case SPEED_1000:
2852                         bmcr |= TG3_BMCR_SPEED1000;
2853                         break;
2854                 }
2855
2856                 if (tp->link_config.duplex == DUPLEX_FULL)
2857                         bmcr |= BMCR_FULLDPLX;
2858
2859                 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2860                     (bmcr != orig_bmcr)) {
2861                         tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2862                         for (i = 0; i < 1500; i++) {
2863                                 u32 tmp;
2864
2865                                 udelay(10);
2866                                 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2867                                     tg3_readphy(tp, MII_BMSR, &tmp))
2868                                         continue;
2869                                 if (!(tmp & BMSR_LSTATUS)) {
2870                                         udelay(40);
2871                                         break;
2872                                 }
2873                         }
2874                         tg3_writephy(tp, MII_BMCR, bmcr);
2875                         udelay(40);
2876                 }
2877         } else {
2878                 tg3_writephy(tp, MII_BMCR,
2879                              BMCR_ANENABLE | BMCR_ANRESTART);
2880         }
2881 }
2882
2883 static int tg3_init_5401phy_dsp(struct tg3 *tp)
2884 {
2885         int err;
2886
2887         /* Turn off tap power management. */
2888         /* Set Extended packet length bit */
2889         err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2890
2891         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
2892         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
2893
2894         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
2895         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
2896
2897         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2898         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
2899
2900         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2901         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
2902
2903         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2904         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
2905
2906         udelay(40);
2907
2908         return err;
2909 }
2910
2911 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
2912 {
2913         u32 adv_reg, all_mask = 0;
2914
2915         if (mask & ADVERTISED_10baseT_Half)
2916                 all_mask |= ADVERTISE_10HALF;
2917         if (mask & ADVERTISED_10baseT_Full)
2918                 all_mask |= ADVERTISE_10FULL;
2919         if (mask & ADVERTISED_100baseT_Half)
2920                 all_mask |= ADVERTISE_100HALF;
2921         if (mask & ADVERTISED_100baseT_Full)
2922                 all_mask |= ADVERTISE_100FULL;
2923
2924         if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
2925                 return 0;
2926
2927         if ((adv_reg & all_mask) != all_mask)
2928                 return 0;
2929         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
2930                 u32 tg3_ctrl;
2931
2932                 all_mask = 0;
2933                 if (mask & ADVERTISED_1000baseT_Half)
2934                         all_mask |= ADVERTISE_1000HALF;
2935                 if (mask & ADVERTISED_1000baseT_Full)
2936                         all_mask |= ADVERTISE_1000FULL;
2937
2938                 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
2939                         return 0;
2940
2941                 if ((tg3_ctrl & all_mask) != all_mask)
2942                         return 0;
2943         }
2944         return 1;
2945 }
2946
2947 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
2948 {
2949         u32 curadv, reqadv;
2950
2951         if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
2952                 return 1;
2953
2954         curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2955         reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2956
2957         if (tp->link_config.active_duplex == DUPLEX_FULL) {
2958                 if (curadv != reqadv)
2959                         return 0;
2960
2961                 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
2962                         tg3_readphy(tp, MII_LPA, rmtadv);
2963         } else {
2964                 /* Reprogram the advertisement register, even if it
2965                  * does not affect the current link.  If the link
2966                  * gets renegotiated in the future, we can save an
2967                  * additional renegotiation cycle by advertising
2968                  * it correctly in the first place.
2969                  */
2970                 if (curadv != reqadv) {
2971                         *lcladv &= ~(ADVERTISE_PAUSE_CAP |
2972                                      ADVERTISE_PAUSE_ASYM);
2973                         tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
2974                 }
2975         }
2976
2977         return 1;
2978 }
2979
2980 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
2981 {
2982         int current_link_up;
2983         u32 bmsr, dummy;
2984         u32 lcl_adv, rmt_adv;
2985         u16 current_speed;
2986         u8 current_duplex;
2987         int i, err;
2988
2989         tw32(MAC_EVENT, 0);
2990
2991         tw32_f(MAC_STATUS,
2992              (MAC_STATUS_SYNC_CHANGED |
2993               MAC_STATUS_CFG_CHANGED |
2994               MAC_STATUS_MI_COMPLETION |
2995               MAC_STATUS_LNKSTATE_CHANGED));
2996         udelay(40);
2997
2998         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
2999                 tw32_f(MAC_MI_MODE,
3000                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
3001                 udelay(80);
3002         }
3003
3004         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
3005
3006         /* Some third-party PHYs need to be reset on link going
3007          * down.
3008          */
3009         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3010              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
3011              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
3012             netif_carrier_ok(tp->dev)) {
3013                 tg3_readphy(tp, MII_BMSR, &bmsr);
3014                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3015                     !(bmsr & BMSR_LSTATUS))
3016                         force_reset = 1;
3017         }
3018         if (force_reset)
3019                 tg3_phy_reset(tp);
3020
3021         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
3022                 tg3_readphy(tp, MII_BMSR, &bmsr);
3023                 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
3024                     !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
3025                         bmsr = 0;
3026
3027                 if (!(bmsr & BMSR_LSTATUS)) {
3028                         err = tg3_init_5401phy_dsp(tp);
3029                         if (err)
3030                                 return err;
3031
3032                         tg3_readphy(tp, MII_BMSR, &bmsr);
3033                         for (i = 0; i < 1000; i++) {
3034                                 udelay(10);
3035                                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3036                                     (bmsr & BMSR_LSTATUS)) {
3037                                         udelay(40);
3038                                         break;
3039                                 }
3040                         }
3041
3042                         if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
3043                             !(bmsr & BMSR_LSTATUS) &&
3044                             tp->link_config.active_speed == SPEED_1000) {
3045                                 err = tg3_phy_reset(tp);
3046                                 if (!err)
3047                                         err = tg3_init_5401phy_dsp(tp);
3048                                 if (err)
3049                                         return err;
3050                         }
3051                 }
3052         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3053                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3054                 /* 5701 {A0,B0} CRC bug workaround */
3055                 tg3_writephy(tp, 0x15, 0x0a75);
3056                 tg3_writephy(tp, 0x1c, 0x8c68);
3057                 tg3_writephy(tp, 0x1c, 0x8d68);
3058                 tg3_writephy(tp, 0x1c, 0x8c68);
3059         }
3060
3061         /* Clear pending interrupts... */
3062         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3063         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3064
3065         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
3066                 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
3067         else if (!(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
3068                 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3069
3070         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3071             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3072                 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3073                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
3074                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3075                 else
3076                         tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3077         }
3078
3079         current_link_up = 0;
3080         current_speed = SPEED_INVALID;
3081         current_duplex = DUPLEX_INVALID;
3082
3083         if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
3084                 u32 val;
3085
3086                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3087                 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3088                 if (!(val & (1 << 10))) {
3089                         val |= (1 << 10);
3090                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3091                         goto relink;
3092                 }
3093         }
3094
3095         bmsr = 0;
3096         for (i = 0; i < 100; i++) {
3097                 tg3_readphy(tp, MII_BMSR, &bmsr);
3098                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3099                     (bmsr & BMSR_LSTATUS))
3100                         break;
3101                 udelay(40);
3102         }
3103
3104         if (bmsr & BMSR_LSTATUS) {
3105                 u32 aux_stat, bmcr;
3106
3107                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3108                 for (i = 0; i < 2000; i++) {
3109                         udelay(10);
3110                         if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3111                             aux_stat)
3112                                 break;
3113                 }
3114
3115                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3116                                              &current_speed,
3117                                              &current_duplex);
3118
3119                 bmcr = 0;
3120                 for (i = 0; i < 200; i++) {
3121                         tg3_readphy(tp, MII_BMCR, &bmcr);
3122                         if (tg3_readphy(tp, MII_BMCR, &bmcr))
3123                                 continue;
3124                         if (bmcr && bmcr != 0x7fff)
3125                                 break;
3126                         udelay(10);
3127                 }
3128
3129                 lcl_adv = 0;
3130                 rmt_adv = 0;
3131
3132                 tp->link_config.active_speed = current_speed;
3133                 tp->link_config.active_duplex = current_duplex;
3134
3135                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3136                         if ((bmcr & BMCR_ANENABLE) &&
3137                             tg3_copper_is_advertising_all(tp,
3138                                                 tp->link_config.advertising)) {
3139                                 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3140                                                                   &rmt_adv))
3141                                         current_link_up = 1;
3142                         }
3143                 } else {
3144                         if (!(bmcr & BMCR_ANENABLE) &&
3145                             tp->link_config.speed == current_speed &&
3146                             tp->link_config.duplex == current_duplex &&
3147                             tp->link_config.flowctrl ==
3148                             tp->link_config.active_flowctrl) {
3149                                 current_link_up = 1;
3150                         }
3151                 }
3152
3153                 if (current_link_up == 1 &&
3154                     tp->link_config.active_duplex == DUPLEX_FULL)
3155                         tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
3156         }
3157
3158 relink:
3159         if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
3160                 u32 tmp;
3161
3162                 tg3_phy_copper_begin(tp);
3163
3164                 tg3_readphy(tp, MII_BMSR, &tmp);
3165                 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
3166                     (tmp & BMSR_LSTATUS))
3167                         current_link_up = 1;
3168         }
3169
3170         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3171         if (current_link_up == 1) {
3172                 if (tp->link_config.active_speed == SPEED_100 ||
3173                     tp->link_config.active_speed == SPEED_10)
3174                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3175                 else
3176                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3177         } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)
3178                 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3179         else
3180                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3181
3182         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3183         if (tp->link_config.active_duplex == DUPLEX_HALF)
3184                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3185
3186         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
3187                 if (current_link_up == 1 &&
3188                     tg3_5700_link_polarity(tp, tp->link_config.active_speed))
3189                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
3190                 else
3191                         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
3192         }
3193
3194         /* ??? Without this setting Netgear GA302T PHY does not
3195          * ??? send/receive packets...
3196          */
3197         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
3198             tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3199                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3200                 tw32_f(MAC_MI_MODE, tp->mi_mode);
3201                 udelay(80);
3202         }
3203
3204         tw32_f(MAC_MODE, tp->mac_mode);
3205         udelay(40);
3206
3207         if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3208                 /* Polled via timer. */
3209                 tw32_f(MAC_EVENT, 0);
3210         } else {
3211                 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3212         }
3213         udelay(40);
3214
3215         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3216             current_link_up == 1 &&
3217             tp->link_config.active_speed == SPEED_1000 &&
3218             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3219              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3220                 udelay(120);
3221                 tw32_f(MAC_STATUS,
3222                      (MAC_STATUS_SYNC_CHANGED |
3223                       MAC_STATUS_CFG_CHANGED));
3224                 udelay(40);
3225                 tg3_write_mem(tp,
3226                               NIC_SRAM_FIRMWARE_MBOX,
3227                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3228         }
3229
3230         /* Prevent send BD corruption. */
3231         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3232                 u16 oldlnkctl, newlnkctl;
3233
3234                 pci_read_config_word(tp->pdev,
3235                                      tp->pcie_cap + PCI_EXP_LNKCTL,
3236                                      &oldlnkctl);
3237                 if (tp->link_config.active_speed == SPEED_100 ||
3238                     tp->link_config.active_speed == SPEED_10)
3239                         newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3240                 else
3241                         newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3242                 if (newlnkctl != oldlnkctl)
3243                         pci_write_config_word(tp->pdev,
3244                                               tp->pcie_cap + PCI_EXP_LNKCTL,
3245                                               newlnkctl);
3246         } else if (tp->tg3_flags3 & TG3_FLG3_TOGGLE_10_100_L1PLLPD) {
3247                 u32 newreg, oldreg = tr32(TG3_PCIE_LNKCTL);
3248                 if (tp->link_config.active_speed == SPEED_100 ||
3249                     tp->link_config.active_speed == SPEED_10)
3250                         newreg = oldreg & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
3251                 else
3252                         newreg = oldreg | TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
3253                 if (newreg != oldreg)
3254                         tw32(TG3_PCIE_LNKCTL, newreg);
3255         }
3256
3257         if (current_link_up != netif_carrier_ok(tp->dev)) {
3258                 if (current_link_up)
3259                         netif_carrier_on(tp->dev);
3260                 else
3261                         netif_carrier_off(tp->dev);
3262                 tg3_link_report(tp);
3263         }
3264
3265         return 0;
3266 }
3267
3268 struct tg3_fiber_aneginfo {
3269         int state;
3270 #define ANEG_STATE_UNKNOWN              0
3271 #define ANEG_STATE_AN_ENABLE            1
3272 #define ANEG_STATE_RESTART_INIT         2
3273 #define ANEG_STATE_RESTART              3
3274 #define ANEG_STATE_DISABLE_LINK_OK      4
3275 #define ANEG_STATE_ABILITY_DETECT_INIT  5
3276 #define ANEG_STATE_ABILITY_DETECT       6
3277 #define ANEG_STATE_ACK_DETECT_INIT      7
3278 #define ANEG_STATE_ACK_DETECT           8
3279 #define ANEG_STATE_COMPLETE_ACK_INIT    9
3280 #define ANEG_STATE_COMPLETE_ACK         10
3281 #define ANEG_STATE_IDLE_DETECT_INIT     11
3282 #define ANEG_STATE_IDLE_DETECT          12
3283 #define ANEG_STATE_LINK_OK              13
3284 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
3285 #define ANEG_STATE_NEXT_PAGE_WAIT       15
3286
3287         u32 flags;
3288 #define MR_AN_ENABLE            0x00000001
3289 #define MR_RESTART_AN           0x00000002
3290 #define MR_AN_COMPLETE          0x00000004
3291 #define MR_PAGE_RX              0x00000008
3292 #define MR_NP_LOADED            0x00000010
3293 #define MR_TOGGLE_TX            0x00000020
3294 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
3295 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
3296 #define MR_LP_ADV_SYM_PAUSE     0x00000100
3297 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
3298 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3299 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3300 #define MR_LP_ADV_NEXT_PAGE     0x00001000
3301 #define MR_TOGGLE_RX            0x00002000
3302 #define MR_NP_RX                0x00004000
3303
3304 #define MR_LINK_OK              0x80000000
3305
3306         unsigned long link_time, cur_time;
3307
3308         u32 ability_match_cfg;
3309         int ability_match_count;
3310
3311         char ability_match, idle_match, ack_match;
3312
3313         u32 txconfig, rxconfig;
3314 #define ANEG_CFG_NP             0x00000080
3315 #define ANEG_CFG_ACK            0x00000040
3316 #define ANEG_CFG_RF2            0x00000020
3317 #define ANEG_CFG_RF1            0x00000010
3318 #define ANEG_CFG_PS2            0x00000001
3319 #define ANEG_CFG_PS1            0x00008000
3320 #define ANEG_CFG_HD             0x00004000
3321 #define ANEG_CFG_FD             0x00002000
3322 #define ANEG_CFG_INVAL          0x00001f06
3323
3324 };
3325 #define ANEG_OK         0
3326 #define ANEG_DONE       1
3327 #define ANEG_TIMER_ENAB 2
3328 #define ANEG_FAILED     -1
3329
3330 #define ANEG_STATE_SETTLE_TIME  10000
3331
3332 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3333                                    struct tg3_fiber_aneginfo *ap)
3334 {
3335         u16 flowctrl;
3336         unsigned long delta;
3337         u32 rx_cfg_reg;
3338         int ret;
3339
3340         if (ap->state == ANEG_STATE_UNKNOWN) {
3341                 ap->rxconfig = 0;
3342                 ap->link_time = 0;
3343                 ap->cur_time = 0;
3344                 ap->ability_match_cfg = 0;
3345                 ap->ability_match_count = 0;
3346                 ap->ability_match = 0;
3347                 ap->idle_match = 0;
3348                 ap->ack_match = 0;
3349         }
3350         ap->cur_time++;
3351
3352         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3353                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3354
3355                 if (rx_cfg_reg != ap->ability_match_cfg) {
3356                         ap->ability_match_cfg = rx_cfg_reg;
3357                         ap->ability_match = 0;
3358                         ap->ability_match_count = 0;
3359                 } else {
3360                         if (++ap->ability_match_count > 1) {
3361                                 ap->ability_match = 1;
3362                                 ap->ability_match_cfg = rx_cfg_reg;
3363                         }
3364                 }
3365                 if (rx_cfg_reg & ANEG_CFG_ACK)
3366                         ap->ack_match = 1;
3367                 else
3368                         ap->ack_match = 0;
3369
3370                 ap->idle_match = 0;
3371         } else {
3372                 ap->idle_match = 1;
3373                 ap->ability_match_cfg = 0;
3374                 ap->ability_match_count = 0;
3375                 ap->ability_match = 0;
3376                 ap->ack_match = 0;
3377
3378                 rx_cfg_reg = 0;
3379         }
3380
3381         ap->rxconfig = rx_cfg_reg;
3382         ret = ANEG_OK;
3383
3384         switch(ap->state) {
3385         case ANEG_STATE_UNKNOWN:
3386                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3387                         ap->state = ANEG_STATE_AN_ENABLE;
3388
3389                 /* fallthru */
3390         case ANEG_STATE_AN_ENABLE:
3391                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3392                 if (ap->flags & MR_AN_ENABLE) {
3393                         ap->link_time = 0;
3394                         ap->cur_time = 0;
3395                         ap->ability_match_cfg = 0;
3396                         ap->ability_match_count = 0;
3397                         ap->ability_match = 0;
3398                         ap->idle_match = 0;
3399                         ap->ack_match = 0;
3400
3401                         ap->state = ANEG_STATE_RESTART_INIT;
3402                 } else {
3403                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
3404                 }
3405                 break;
3406
3407         case ANEG_STATE_RESTART_INIT:
3408                 ap->link_time = ap->cur_time;
3409                 ap->flags &= ~(MR_NP_LOADED);
3410                 ap->txconfig = 0;
3411                 tw32(MAC_TX_AUTO_NEG, 0);
3412                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3413                 tw32_f(MAC_MODE, tp->mac_mode);
3414                 udelay(40);
3415
3416                 ret = ANEG_TIMER_ENAB;
3417                 ap->state = ANEG_STATE_RESTART;
3418
3419                 /* fallthru */
3420         case ANEG_STATE_RESTART:
3421                 delta = ap->cur_time - ap->link_time;
3422                 if (delta > ANEG_STATE_SETTLE_TIME) {
3423                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3424                 } else {
3425                         ret = ANEG_TIMER_ENAB;
3426                 }
3427                 break;
3428
3429         case ANEG_STATE_DISABLE_LINK_OK:
3430                 ret = ANEG_DONE;
3431                 break;
3432
3433         case ANEG_STATE_ABILITY_DETECT_INIT:
3434                 ap->flags &= ~(MR_TOGGLE_TX);
3435                 ap->txconfig = ANEG_CFG_FD;
3436                 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3437                 if (flowctrl & ADVERTISE_1000XPAUSE)
3438                         ap->txconfig |= ANEG_CFG_PS1;
3439                 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3440                         ap->txconfig |= ANEG_CFG_PS2;
3441                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3442                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3443                 tw32_f(MAC_MODE, tp->mac_mode);
3444                 udelay(40);
3445
3446                 ap->state = ANEG_STATE_ABILITY_DETECT;
3447                 break;
3448
3449         case ANEG_STATE_ABILITY_DETECT:
3450                 if (ap->ability_match != 0 && ap->rxconfig != 0) {
3451                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
3452                 }
3453                 break;
3454
3455         case ANEG_STATE_ACK_DETECT_INIT:
3456                 ap->txconfig |= ANEG_CFG_ACK;
3457                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3458                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3459                 tw32_f(MAC_MODE, tp->mac_mode);
3460                 udelay(40);
3461
3462                 ap->state = ANEG_STATE_ACK_DETECT;
3463
3464                 /* fallthru */
3465         case ANEG_STATE_ACK_DETECT:
3466                 if (ap->ack_match != 0) {
3467                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3468                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3469                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3470                         } else {
3471                                 ap->state = ANEG_STATE_AN_ENABLE;
3472                         }
3473                 } else if (ap->ability_match != 0 &&
3474                            ap->rxconfig == 0) {
3475                         ap->state = ANEG_STATE_AN_ENABLE;
3476                 }
3477                 break;
3478
3479         case ANEG_STATE_COMPLETE_ACK_INIT:
3480                 if (ap->rxconfig & ANEG_CFG_INVAL) {
3481                         ret = ANEG_FAILED;
3482                         break;
3483                 }
3484                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3485                                MR_LP_ADV_HALF_DUPLEX |
3486                                MR_LP_ADV_SYM_PAUSE |
3487                                MR_LP_ADV_ASYM_PAUSE |
3488                                MR_LP_ADV_REMOTE_FAULT1 |
3489                                MR_LP_ADV_REMOTE_FAULT2 |
3490                                MR_LP_ADV_NEXT_PAGE |
3491                                MR_TOGGLE_RX |
3492                                MR_NP_RX);
3493                 if (ap->rxconfig & ANEG_CFG_FD)
3494                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3495                 if (ap->rxconfig & ANEG_CFG_HD)
3496                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3497                 if (ap->rxconfig & ANEG_CFG_PS1)
3498                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
3499                 if (ap->rxconfig & ANEG_CFG_PS2)
3500                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3501                 if (ap->rxconfig & ANEG_CFG_RF1)
3502                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3503                 if (ap->rxconfig & ANEG_CFG_RF2)
3504                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3505                 if (ap->rxconfig & ANEG_CFG_NP)
3506                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
3507
3508                 ap->link_time = ap->cur_time;
3509
3510                 ap->flags ^= (MR_TOGGLE_TX);
3511                 if (ap->rxconfig & 0x0008)
3512                         ap->flags |= MR_TOGGLE_RX;
3513                 if (ap->rxconfig & ANEG_CFG_NP)
3514                         ap->flags |= MR_NP_RX;
3515                 ap->flags |= MR_PAGE_RX;
3516
3517                 ap->state = ANEG_STATE_COMPLETE_ACK;
3518                 ret = ANEG_TIMER_ENAB;
3519                 break;
3520
3521         case ANEG_STATE_COMPLETE_ACK:
3522                 if (ap->ability_match != 0 &&
3523                     ap->rxconfig == 0) {
3524                         ap->state = ANEG_STATE_AN_ENABLE;
3525                         break;
3526                 }
3527                 delta = ap->cur_time - ap->link_time;
3528                 if (delta > ANEG_STATE_SETTLE_TIME) {
3529                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3530                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3531                         } else {
3532                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3533                                     !(ap->flags & MR_NP_RX)) {
3534                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3535                                 } else {
3536                                         ret = ANEG_FAILED;
3537                                 }
3538                         }
3539                 }
3540                 break;
3541
3542         case ANEG_STATE_IDLE_DETECT_INIT:
3543                 ap->link_time = ap->cur_time;
3544                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3545                 tw32_f(MAC_MODE, tp->mac_mode);
3546                 udelay(40);
3547
3548                 ap->state = ANEG_STATE_IDLE_DETECT;
3549                 ret = ANEG_TIMER_ENAB;
3550                 break;
3551
3552         case ANEG_STATE_IDLE_DETECT:
3553                 if (ap->ability_match != 0 &&
3554                     ap->rxconfig == 0) {
3555                         ap->state = ANEG_STATE_AN_ENABLE;
3556                         break;
3557                 }
3558                 delta = ap->cur_time - ap->link_time;
3559                 if (delta > ANEG_STATE_SETTLE_TIME) {
3560                         /* XXX another gem from the Broadcom driver :( */
3561                         ap->state = ANEG_STATE_LINK_OK;
3562                 }
3563                 break;
3564
3565         case ANEG_STATE_LINK_OK:
3566                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3567                 ret = ANEG_DONE;
3568                 break;
3569
3570         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3571                 /* ??? unimplemented */
3572                 break;
3573
3574         case ANEG_STATE_NEXT_PAGE_WAIT:
3575                 /* ??? unimplemented */
3576                 break;
3577
3578         default:
3579                 ret = ANEG_FAILED;
3580                 break;
3581         }
3582
3583         return ret;
3584 }
3585
3586 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
3587 {
3588         int res = 0;
3589         struct tg3_fiber_aneginfo aninfo;
3590         int status = ANEG_FAILED;
3591         unsigned int tick;
3592         u32 tmp;
3593
3594         tw32_f(MAC_TX_AUTO_NEG, 0);
3595
3596         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3597         tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3598         udelay(40);
3599
3600         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3601         udelay(40);
3602
3603         memset(&aninfo, 0, sizeof(aninfo));
3604         aninfo.flags |= MR_AN_ENABLE;
3605         aninfo.state = ANEG_STATE_UNKNOWN;
3606         aninfo.cur_time = 0;
3607         tick = 0;
3608         while (++tick < 195000) {
3609                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3610                 if (status == ANEG_DONE || status == ANEG_FAILED)
3611                         break;
3612
3613                 udelay(1);
3614         }
3615
3616         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3617         tw32_f(MAC_MODE, tp->mac_mode);
3618         udelay(40);
3619
3620         *txflags = aninfo.txconfig;
3621         *rxflags = aninfo.flags;
3622
3623         if (status == ANEG_DONE &&
3624             (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3625                              MR_LP_ADV_FULL_DUPLEX)))
3626                 res = 1;
3627
3628         return res;
3629 }
3630
3631 static void tg3_init_bcm8002(struct tg3 *tp)
3632 {
3633         u32 mac_status = tr32(MAC_STATUS);
3634         int i;
3635
3636         /* Reset when initting first time or we have a link. */
3637         if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3638             !(mac_status & MAC_STATUS_PCS_SYNCED))
3639                 return;
3640
3641         /* Set PLL lock range. */
3642         tg3_writephy(tp, 0x16, 0x8007);
3643
3644         /* SW reset */
3645         tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3646
3647         /* Wait for reset to complete. */
3648         /* XXX schedule_timeout() ... */
3649         for (i = 0; i < 500; i++)
3650                 udelay(10);
3651
3652         /* Config mode; select PMA/Ch 1 regs. */
3653         tg3_writephy(tp, 0x10, 0x8411);
3654
3655         /* Enable auto-lock and comdet, select txclk for tx. */
3656         tg3_writephy(tp, 0x11, 0x0a10);
3657
3658         tg3_writephy(tp, 0x18, 0x00a0);
3659         tg3_writephy(tp, 0x16, 0x41ff);
3660
3661         /* Assert and deassert POR. */
3662         tg3_writephy(tp, 0x13, 0x0400);
3663         udelay(40);
3664         tg3_writephy(tp, 0x13, 0x0000);
3665
3666         tg3_writephy(tp, 0x11, 0x0a50);
3667         udelay(40);
3668         tg3_writephy(tp, 0x11, 0x0a10);
3669
3670         /* Wait for signal to stabilize */
3671         /* XXX schedule_timeout() ... */
3672         for (i = 0; i < 15000; i++)
3673                 udelay(10);
3674
3675         /* Deselect the channel register so we can read the PHYID
3676          * later.
3677          */
3678         tg3_writephy(tp, 0x10, 0x8011);
3679 }
3680
3681 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3682 {
3683         u16 flowctrl;
3684         u32 sg_dig_ctrl, sg_dig_status;
3685         u32 serdes_cfg, expected_sg_dig_ctrl;
3686         int workaround, port_a;
3687         int current_link_up;
3688
3689         serdes_cfg = 0;
3690         expected_sg_dig_ctrl = 0;
3691         workaround = 0;
3692         port_a = 1;
3693         current_link_up = 0;
3694
3695         if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3696             tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3697                 workaround = 1;
3698                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3699                         port_a = 0;
3700
3701                 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3702                 /* preserve bits 20-23 for voltage regulator */
3703                 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3704         }
3705
3706         sg_dig_ctrl = tr32(SG_DIG_CTRL);
3707
3708         if (tp->link_config.autoneg != AUTONEG_ENABLE) {
3709                 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
3710                         if (workaround) {
3711                                 u32 val = serdes_cfg;
3712
3713                                 if (port_a)
3714                                         val |= 0xc010000;
3715                                 else
3716                                         val |= 0x4010000;
3717                                 tw32_f(MAC_SERDES_CFG, val);
3718                         }
3719
3720                         tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3721                 }
3722                 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3723                         tg3_setup_flow_control(tp, 0, 0);
3724                         current_link_up = 1;
3725                 }
3726                 goto out;
3727         }
3728
3729         /* Want auto-negotiation.  */
3730         expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
3731
3732         flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3733         if (flowctrl & ADVERTISE_1000XPAUSE)
3734                 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3735         if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3736                 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
3737
3738         if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3739                 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
3740                     tp->serdes_counter &&
3741                     ((mac_status & (MAC_STATUS_PCS_SYNCED |
3742                                     MAC_STATUS_RCVD_CFG)) ==
3743                      MAC_STATUS_PCS_SYNCED)) {
3744                         tp->serdes_counter--;
3745                         current_link_up = 1;
3746                         goto out;
3747                 }
3748 restart_autoneg:
3749                 if (workaround)
3750                         tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
3751                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
3752                 udelay(5);
3753                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3754
3755                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3756                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3757         } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3758                                  MAC_STATUS_SIGNAL_DET)) {
3759                 sg_dig_status = tr32(SG_DIG_STATUS);
3760                 mac_status = tr32(MAC_STATUS);
3761
3762                 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
3763                     (mac_status & MAC_STATUS_PCS_SYNCED)) {
3764                         u32 local_adv = 0, remote_adv = 0;
3765
3766                         if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3767                                 local_adv |= ADVERTISE_1000XPAUSE;
3768                         if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3769                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3770
3771                         if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
3772                                 remote_adv |= LPA_1000XPAUSE;
3773                         if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
3774                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3775
3776                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3777                         current_link_up = 1;
3778                         tp->serdes_counter = 0;
3779                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3780                 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3781                         if (tp->serdes_counter)
3782                                 tp->serdes_counter--;
3783                         else {
3784                                 if (workaround) {
3785                                         u32 val = serdes_cfg;
3786
3787                                         if (port_a)
3788                                                 val |= 0xc010000;
3789                                         else
3790                                                 val |= 0x4010000;
3791
3792                                         tw32_f(MAC_SERDES_CFG, val);
3793                                 }
3794
3795                                 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3796                                 udelay(40);
3797
3798                                 /* Link parallel detection - link is up */
3799                                 /* only if we have PCS_SYNC and not */
3800                                 /* receiving config code words */
3801                                 mac_status = tr32(MAC_STATUS);
3802                                 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3803                                     !(mac_status & MAC_STATUS_RCVD_CFG)) {
3804                                         tg3_setup_flow_control(tp, 0, 0);
3805                                         current_link_up = 1;
3806                                         tp->tg3_flags2 |=
3807                                                 TG3_FLG2_PARALLEL_DETECT;
3808                                         tp->serdes_counter =
3809                                                 SERDES_PARALLEL_DET_TIMEOUT;
3810                                 } else
3811                                         goto restart_autoneg;
3812                         }
3813                 }
3814         } else {
3815                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3816                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3817         }
3818
3819 out:
3820         return current_link_up;
3821 }
3822
3823 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3824 {
3825         int current_link_up = 0;
3826
3827         if (!(mac_status & MAC_STATUS_PCS_SYNCED))
3828                 goto out;
3829
3830         if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3831                 u32 txflags, rxflags;
3832                 int i;
3833
3834                 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3835                         u32 local_adv = 0, remote_adv = 0;
3836
3837                         if (txflags & ANEG_CFG_PS1)
3838                                 local_adv |= ADVERTISE_1000XPAUSE;
3839                         if (txflags & ANEG_CFG_PS2)
3840                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3841
3842                         if (rxflags & MR_LP_ADV_SYM_PAUSE)
3843                                 remote_adv |= LPA_1000XPAUSE;
3844                         if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3845                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3846
3847                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3848
3849                         current_link_up = 1;
3850                 }
3851                 for (i = 0; i < 30; i++) {
3852                         udelay(20);
3853                         tw32_f(MAC_STATUS,
3854                                (MAC_STATUS_SYNC_CHANGED |
3855                                 MAC_STATUS_CFG_CHANGED));
3856                         udelay(40);
3857                         if ((tr32(MAC_STATUS) &
3858                              (MAC_STATUS_SYNC_CHANGED |
3859                               MAC_STATUS_CFG_CHANGED)) == 0)
3860                                 break;
3861                 }
3862
3863                 mac_status = tr32(MAC_STATUS);
3864                 if (current_link_up == 0 &&
3865                     (mac_status & MAC_STATUS_PCS_SYNCED) &&
3866                     !(mac_status & MAC_STATUS_RCVD_CFG))
3867                         current_link_up = 1;
3868         } else {
3869                 tg3_setup_flow_control(tp, 0, 0);
3870
3871                 /* Forcing 1000FD link up. */
3872                 current_link_up = 1;
3873
3874                 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3875                 udelay(40);
3876
3877                 tw32_f(MAC_MODE, tp->mac_mode);
3878                 udelay(40);
3879         }
3880
3881 out:
3882         return current_link_up;
3883 }
3884
3885 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3886 {
3887         u32 orig_pause_cfg;
3888         u16 orig_active_speed;
3889         u8 orig_active_duplex;
3890         u32 mac_status;
3891         int current_link_up;
3892         int i;
3893
3894         orig_pause_cfg = tp->link_config.active_flowctrl;
3895         orig_active_speed = tp->link_config.active_speed;
3896         orig_active_duplex = tp->link_config.active_duplex;
3897
3898         if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3899             netif_carrier_ok(tp->dev) &&
3900             (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3901                 mac_status = tr32(MAC_STATUS);
3902                 mac_status &= (MAC_STATUS_PCS_SYNCED |
3903                                MAC_STATUS_SIGNAL_DET |
3904                                MAC_STATUS_CFG_CHANGED |
3905                                MAC_STATUS_RCVD_CFG);
3906                 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3907                                    MAC_STATUS_SIGNAL_DET)) {
3908                         tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3909                                             MAC_STATUS_CFG_CHANGED));
3910                         return 0;
3911                 }
3912         }
3913
3914         tw32_f(MAC_TX_AUTO_NEG, 0);
3915
3916         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3917         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3918         tw32_f(MAC_MODE, tp->mac_mode);
3919         udelay(40);
3920
3921         if (tp->phy_id == PHY_ID_BCM8002)
3922                 tg3_init_bcm8002(tp);
3923
3924         /* Enable link change event even when serdes polling.  */
3925         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3926         udelay(40);
3927
3928         current_link_up = 0;
3929         mac_status = tr32(MAC_STATUS);
3930
3931         if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
3932                 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
3933         else
3934                 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
3935
3936         tp->napi[0].hw_status->status =
3937                 (SD_STATUS_UPDATED |
3938                  (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
3939
3940         for (i = 0; i < 100; i++) {
3941                 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3942                                     MAC_STATUS_CFG_CHANGED));
3943                 udelay(5);
3944                 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3945                                          MAC_STATUS_CFG_CHANGED |
3946                                          MAC_STATUS_LNKSTATE_CHANGED)) == 0)
3947                         break;
3948         }
3949
3950         mac_status = tr32(MAC_STATUS);
3951         if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
3952                 current_link_up = 0;
3953                 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
3954                     tp->serdes_counter == 0) {
3955                         tw32_f(MAC_MODE, (tp->mac_mode |
3956                                           MAC_MODE_SEND_CONFIGS));
3957                         udelay(1);
3958                         tw32_f(MAC_MODE, tp->mac_mode);
3959                 }
3960         }
3961
3962         if (current_link_up == 1) {
3963                 tp->link_config.active_speed = SPEED_1000;
3964                 tp->link_config.active_duplex = DUPLEX_FULL;
3965                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3966                                     LED_CTRL_LNKLED_OVERRIDE |
3967                                     LED_CTRL_1000MBPS_ON));
3968         } else {
3969                 tp->link_config.active_speed = SPEED_INVALID;
3970                 tp->link_config.active_duplex = DUPLEX_INVALID;
3971                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3972                                     LED_CTRL_LNKLED_OVERRIDE |
3973                                     LED_CTRL_TRAFFIC_OVERRIDE));
3974         }
3975
3976         if (current_link_up != netif_carrier_ok(tp->dev)) {
3977                 if (current_link_up)
3978                         netif_carrier_on(tp->dev);
3979                 else
3980                         netif_carrier_off(tp->dev);
3981                 tg3_link_report(tp);
3982         } else {
3983                 u32 now_pause_cfg = tp->link_config.active_flowctrl;
3984                 if (orig_pause_cfg != now_pause_cfg ||
3985                     orig_active_speed != tp->link_config.active_speed ||
3986                     orig_active_duplex != tp->link_config.active_duplex)
3987                         tg3_link_report(tp);
3988         }
3989
3990         return 0;
3991 }
3992
3993 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
3994 {
3995         int current_link_up, err = 0;
3996         u32 bmsr, bmcr;
3997         u16 current_speed;
3998         u8 current_duplex;
3999         u32 local_adv, remote_adv;
4000
4001         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4002         tw32_f(MAC_MODE, tp->mac_mode);
4003         udelay(40);
4004
4005         tw32(MAC_EVENT, 0);
4006
4007         tw32_f(MAC_STATUS,
4008              (MAC_STATUS_SYNC_CHANGED |
4009               MAC_STATUS_CFG_CHANGED |
4010               MAC_STATUS_MI_COMPLETION |
4011               MAC_STATUS_LNKSTATE_CHANGED));
4012         udelay(40);
4013
4014         if (force_reset)
4015                 tg3_phy_reset(tp);
4016
4017         current_link_up = 0;
4018         current_speed = SPEED_INVALID;
4019         current_duplex = DUPLEX_INVALID;
4020
4021         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4022         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4023         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
4024                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4025                         bmsr |= BMSR_LSTATUS;
4026                 else
4027                         bmsr &= ~BMSR_LSTATUS;
4028         }
4029
4030         err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4031
4032         if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
4033             (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4034                 /* do nothing, just check for link up at the end */
4035         } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4036                 u32 adv, new_adv;
4037
4038                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4039                 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4040                                   ADVERTISE_1000XPAUSE |
4041                                   ADVERTISE_1000XPSE_ASYM |
4042                                   ADVERTISE_SLCT);
4043
4044                 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4045
4046                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4047                         new_adv |= ADVERTISE_1000XHALF;
4048                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4049                         new_adv |= ADVERTISE_1000XFULL;
4050
4051                 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4052                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
4053                         bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4054                         tg3_writephy(tp, MII_BMCR, bmcr);
4055
4056                         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4057                         tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
4058                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4059
4060                         return err;
4061                 }
4062         } else {
4063                 u32 new_bmcr;
4064
4065                 bmcr &= ~BMCR_SPEED1000;
4066                 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4067
4068                 if (tp->link_config.duplex == DUPLEX_FULL)
4069                         new_bmcr |= BMCR_FULLDPLX;
4070
4071                 if (new_bmcr != bmcr) {
4072                         /* BMCR_SPEED1000 is a reserved bit that needs
4073                          * to be set on write.
4074                          */
4075                         new_bmcr |= BMCR_SPEED1000;
4076
4077                         /* Force a linkdown */
4078                         if (netif_carrier_ok(tp->dev)) {
4079                                 u32 adv;
4080
4081                                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4082                                 adv &= ~(ADVERTISE_1000XFULL |
4083                                          ADVERTISE_1000XHALF |
4084                                          ADVERTISE_SLCT);
4085                                 tg3_writephy(tp, MII_ADVERTISE, adv);
4086                                 tg3_writephy(tp, MII_BMCR, bmcr |
4087                                                            BMCR_ANRESTART |
4088                                                            BMCR_ANENABLE);
4089                                 udelay(10);
4090                                 netif_carrier_off(tp->dev);
4091                         }
4092                         tg3_writephy(tp, MII_BMCR, new_bmcr);
4093                         bmcr = new_bmcr;
4094                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4095                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4096                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4097                             ASIC_REV_5714) {
4098                                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4099                                         bmsr |= BMSR_LSTATUS;
4100                                 else
4101                                         bmsr &= ~BMSR_LSTATUS;
4102                         }
4103                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4104                 }
4105         }
4106
4107         if (bmsr & BMSR_LSTATUS) {
4108                 current_speed = SPEED_1000;
4109                 current_link_up = 1;
4110                 if (bmcr & BMCR_FULLDPLX)
4111                         current_duplex = DUPLEX_FULL;
4112                 else
4113                         current_duplex = DUPLEX_HALF;
4114
4115                 local_adv = 0;
4116                 remote_adv = 0;
4117
4118                 if (bmcr & BMCR_ANENABLE) {
4119                         u32 common;
4120
4121                         err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4122                         err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4123                         common = local_adv & remote_adv;
4124                         if (common & (ADVERTISE_1000XHALF |
4125                                       ADVERTISE_1000XFULL)) {
4126                                 if (common & ADVERTISE_1000XFULL)
4127                                         current_duplex = DUPLEX_FULL;
4128                                 else
4129                                         current_duplex = DUPLEX_HALF;
4130                         }
4131                         else
4132                                 current_link_up = 0;
4133                 }
4134         }
4135
4136         if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4137                 tg3_setup_flow_control(tp, local_adv, remote_adv);
4138
4139         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4140         if (tp->link_config.active_duplex == DUPLEX_HALF)
4141                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4142
4143         tw32_f(MAC_MODE, tp->mac_mode);
4144         udelay(40);
4145
4146         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4147
4148         tp->link_config.active_speed = current_speed;
4149         tp->link_config.active_duplex = current_duplex;
4150
4151         if (current_link_up != netif_carrier_ok(tp->dev)) {
4152                 if (current_link_up)
4153                         netif_carrier_on(tp->dev);
4154                 else {
4155                         netif_carrier_off(tp->dev);
4156                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4157                 }
4158                 tg3_link_report(tp);
4159         }
4160         return err;
4161 }
4162
4163 static void tg3_serdes_parallel_detect(struct tg3 *tp)
4164 {
4165         if (tp->serdes_counter) {
4166                 /* Give autoneg time to complete. */
4167                 tp->serdes_counter--;
4168                 return;
4169         }
4170         if (!netif_carrier_ok(tp->dev) &&
4171             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4172                 u32 bmcr;
4173
4174                 tg3_readphy(tp, MII_BMCR, &bmcr);
4175                 if (bmcr & BMCR_ANENABLE) {
4176                         u32 phy1, phy2;
4177
4178                         /* Select shadow register 0x1f */
4179                         tg3_writephy(tp, 0x1c, 0x7c00);
4180                         tg3_readphy(tp, 0x1c, &phy1);
4181
4182                         /* Select expansion interrupt status register */
4183                         tg3_writephy(tp, 0x17, 0x0f01);
4184                         tg3_readphy(tp, 0x15, &phy2);
4185                         tg3_readphy(tp, 0x15, &phy2);
4186
4187                         if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4188                                 /* We have signal detect and not receiving
4189                                  * config code words, link is up by parallel
4190                                  * detection.
4191                                  */
4192
4193                                 bmcr &= ~BMCR_ANENABLE;
4194                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4195                                 tg3_writephy(tp, MII_BMCR, bmcr);
4196                                 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
4197                         }
4198                 }
4199         }
4200         else if (netif_carrier_ok(tp->dev) &&
4201                  (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4202                  (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4203                 u32 phy2;
4204
4205                 /* Select expansion interrupt status register */
4206                 tg3_writephy(tp, 0x17, 0x0f01);
4207                 tg3_readphy(tp, 0x15, &phy2);
4208                 if (phy2 & 0x20) {
4209                         u32 bmcr;
4210
4211                         /* Config code words received, turn on autoneg. */
4212                         tg3_readphy(tp, MII_BMCR, &bmcr);
4213                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4214
4215                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4216
4217                 }
4218         }
4219 }
4220
4221 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4222 {
4223         int err;
4224
4225         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4226                 err = tg3_setup_fiber_phy(tp, force_reset);
4227         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
4228                 err = tg3_setup_fiber_mii_phy(tp, force_reset);
4229         } else {
4230                 err = tg3_setup_copper_phy(tp, force_reset);
4231         }
4232
4233         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
4234                 u32 val, scale;
4235
4236                 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4237                 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4238                         scale = 65;
4239                 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4240                         scale = 6;
4241                 else
4242                         scale = 12;
4243
4244                 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4245                 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4246                 tw32(GRC_MISC_CFG, val);
4247         }
4248
4249         if (tp->link_config.active_speed == SPEED_1000 &&
4250             tp->link_config.active_duplex == DUPLEX_HALF)
4251                 tw32(MAC_TX_LENGTHS,
4252                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4253                       (6 << TX_LENGTHS_IPG_SHIFT) |
4254                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4255         else
4256                 tw32(MAC_TX_LENGTHS,
4257                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4258                       (6 << TX_LENGTHS_IPG_SHIFT) |
4259                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4260
4261         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4262                 if (netif_carrier_ok(tp->dev)) {
4263                         tw32(HOSTCC_STAT_COAL_TICKS,
4264                              tp->coal.stats_block_coalesce_usecs);
4265                 } else {
4266                         tw32(HOSTCC_STAT_COAL_TICKS, 0);
4267                 }
4268         }
4269
4270         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4271                 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4272                 if (!netif_carrier_ok(tp->dev))
4273                         val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4274                               tp->pwrmgmt_thresh;
4275                 else
4276                         val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4277                 tw32(PCIE_PWR_MGMT_THRESH, val);
4278         }
4279
4280         return err;
4281 }
4282
4283 /* This is called whenever we suspect that the system chipset is re-
4284  * ordering the sequence of MMIO to the tx send mailbox. The symptom
4285  * is bogus tx completions. We try to recover by setting the
4286  * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4287  * in the workqueue.
4288  */
4289 static void tg3_tx_recover(struct tg3 *tp)
4290 {
4291         BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4292                tp->write32_tx_mbox == tg3_write_indirect_mbox);
4293
4294         printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
4295                "mapped I/O cycles to the network device, attempting to "
4296                "recover. Please report the problem to the driver maintainer "
4297                "and include system chipset information.\n", tp->dev->name);
4298
4299         spin_lock(&tp->lock);
4300         tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
4301         spin_unlock(&tp->lock);
4302 }
4303
4304 static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
4305 {
4306         smp_mb();
4307         return tnapi->tx_pending -
4308                ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
4309 }
4310
4311 /* Tigon3 never reports partial packet sends.  So we do not
4312  * need special logic to handle SKBs that have not had all
4313  * of their frags sent yet, like SunGEM does.
4314  */
4315 static void tg3_tx(struct tg3_napi *tnapi)
4316 {
4317         struct tg3 *tp = tnapi->tp;
4318         u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
4319         u32 sw_idx = tnapi->tx_cons;
4320         struct netdev_queue *txq;
4321         int index = tnapi - tp->napi;
4322
4323         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
4324                 index--;
4325
4326         txq = netdev_get_tx_queue(tp->dev, index);
4327
4328         while (sw_idx != hw_idx) {
4329                 struct tx_ring_info *ri = &tnapi->tx_buffers[sw_idx];
4330                 struct sk_buff *skb = ri->skb;
4331                 int i, tx_bug = 0;
4332
4333                 if (unlikely(skb == NULL)) {
4334                         tg3_tx_recover(tp);
4335                         return;
4336                 }
4337
4338                 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
4339
4340                 ri->skb = NULL;
4341
4342                 sw_idx = NEXT_TX(sw_idx);
4343
4344                 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
4345                         ri = &tnapi->tx_buffers[sw_idx];
4346                         if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4347                                 tx_bug = 1;
4348                         sw_idx = NEXT_TX(sw_idx);
4349                 }
4350
4351                 dev_kfree_skb(skb);
4352
4353                 if (unlikely(tx_bug)) {
4354                         tg3_tx_recover(tp);
4355                         return;
4356                 }
4357         }
4358
4359         tnapi->tx_cons = sw_idx;
4360
4361         /* Need to make the tx_cons update visible to tg3_start_xmit()
4362          * before checking for netif_queue_stopped().  Without the
4363          * memory barrier, there is a small possibility that tg3_start_xmit()
4364          * will miss it and cause the queue to be stopped forever.
4365          */
4366         smp_mb();
4367
4368         if (unlikely(netif_tx_queue_stopped(txq) &&
4369                      (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
4370                 __netif_tx_lock(txq, smp_processor_id());
4371                 if (netif_tx_queue_stopped(txq) &&
4372                     (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
4373                         netif_tx_wake_queue(txq);
4374                 __netif_tx_unlock(txq);
4375         }
4376 }
4377
4378 /* Returns size of skb allocated or < 0 on error.
4379  *
4380  * We only need to fill in the address because the other members
4381  * of the RX descriptor are invariant, see tg3_init_rings.
4382  *
4383  * Note the purposeful assymetry of cpu vs. chip accesses.  For
4384  * posting buffers we only dirty the first cache line of the RX
4385  * descriptor (containing the address).  Whereas for the RX status
4386  * buffers the cpu only reads the last cacheline of the RX descriptor
4387  * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4388  */
4389 static int tg3_alloc_rx_skb(struct tg3_napi *tnapi, u32 opaque_key,
4390                             int src_idx, u32 dest_idx_unmasked)
4391 {
4392         struct tg3 *tp = tnapi->tp;
4393         struct tg3_rx_buffer_desc *desc;
4394         struct ring_info *map, *src_map;
4395         struct sk_buff *skb;
4396         dma_addr_t mapping;
4397         int skb_size, dest_idx;
4398         struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
4399
4400         src_map = NULL;
4401         switch (opaque_key) {
4402         case RXD_OPAQUE_RING_STD:
4403                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4404                 desc = &tpr->rx_std[dest_idx];
4405                 map = &tpr->rx_std_buffers[dest_idx];
4406                 if (src_idx >= 0)
4407                         src_map = &tpr->rx_std_buffers[src_idx];
4408                 skb_size = tp->rx_pkt_map_sz;
4409                 break;
4410
4411         case RXD_OPAQUE_RING_JUMBO:
4412                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4413                 desc = &tpr->rx_jmb[dest_idx].std;
4414                 map = &tpr->rx_jmb_buffers[dest_idx];
4415                 if (src_idx >= 0)
4416                         src_map = &tpr->rx_jmb_buffers[src_idx];
4417                 skb_size = TG3_RX_JMB_MAP_SZ;
4418                 break;
4419
4420         default:
4421                 return -EINVAL;
4422         }
4423
4424         /* Do not overwrite any of the map or rp information
4425          * until we are sure we can commit to a new buffer.
4426          *
4427          * Callers depend upon this behavior and assume that
4428          * we leave everything unchanged if we fail.
4429          */
4430         skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
4431         if (skb == NULL)
4432                 return -ENOMEM;
4433
4434         skb_reserve(skb, tp->rx_offset);
4435
4436         mapping = pci_map_single(tp->pdev, skb->data, skb_size,
4437                                  PCI_DMA_FROMDEVICE);
4438
4439         map->skb = skb;
4440         pci_unmap_addr_set(map, mapping, mapping);
4441
4442         if (src_map != NULL)
4443                 src_map->skb = NULL;
4444
4445         desc->addr_hi = ((u64)mapping >> 32);
4446         desc->addr_lo = ((u64)mapping & 0xffffffff);
4447
4448         return skb_size;
4449 }
4450
4451 /* We only need to move over in the address because the other
4452  * members of the RX descriptor are invariant.  See notes above
4453  * tg3_alloc_rx_skb for full details.
4454  */
4455 static void tg3_recycle_rx(struct tg3_napi *tnapi, u32 opaque_key,
4456                            int src_idx, u32 dest_idx_unmasked)
4457 {
4458         struct tg3 *tp = tnapi->tp;
4459         struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4460         struct ring_info *src_map, *dest_map;
4461         int dest_idx;
4462         struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
4463
4464         switch (opaque_key) {
4465         case RXD_OPAQUE_RING_STD:
4466                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4467                 dest_desc = &tpr->rx_std[dest_idx];
4468                 dest_map = &tpr->rx_std_buffers[dest_idx];
4469                 src_desc = &tpr->rx_std[src_idx];
4470                 src_map = &tpr->rx_std_buffers[src_idx];
4471                 break;
4472
4473         case RXD_OPAQUE_RING_JUMBO:
4474                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4475                 dest_desc = &tpr->rx_jmb[dest_idx].std;
4476                 dest_map = &tpr->rx_jmb_buffers[dest_idx];
4477                 src_desc = &tpr->rx_jmb[src_idx].std;
4478                 src_map = &tpr->rx_jmb_buffers[src_idx];
4479                 break;
4480
4481         default:
4482                 return;
4483         }
4484
4485         dest_map->skb = src_map->skb;
4486         pci_unmap_addr_set(dest_map, mapping,
4487                            pci_unmap_addr(src_map, mapping));
4488         dest_desc->addr_hi = src_desc->addr_hi;
4489         dest_desc->addr_lo = src_desc->addr_lo;
4490
4491         src_map->skb = NULL;
4492 }
4493
4494 /* The RX ring scheme is composed of multiple rings which post fresh
4495  * buffers to the chip, and one special ring the chip uses to report
4496  * status back to the host.
4497  *
4498  * The special ring reports the status of received packets to the
4499  * host.  The chip does not write into the original descriptor the
4500  * RX buffer was obtained from.  The chip simply takes the original
4501  * descriptor as provided by the host, updates the status and length
4502  * field, then writes this into the next status ring entry.
4503  *
4504  * Each ring the host uses to post buffers to the chip is described
4505  * by a TG3_BDINFO entry in the chips SRAM area.  When a packet arrives,
4506  * it is first placed into the on-chip ram.  When the packet's length
4507  * is known, it walks down the TG3_BDINFO entries to select the ring.
4508  * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4509  * which is within the range of the new packet's length is chosen.
4510  *
4511  * The "separate ring for rx status" scheme may sound queer, but it makes
4512  * sense from a cache coherency perspective.  If only the host writes
4513  * to the buffer post rings, and only the chip writes to the rx status
4514  * rings, then cache lines never move beyond shared-modified state.
4515  * If both the host and chip were to write into the same ring, cache line
4516  * eviction could occur since both entities want it in an exclusive state.
4517  */
4518 static int tg3_rx(struct tg3_napi *tnapi, int budget)
4519 {
4520         struct tg3 *tp = tnapi->tp;
4521         u32 work_mask, rx_std_posted = 0;
4522         u32 sw_idx = tnapi->rx_rcb_ptr;
4523         u16 hw_idx;
4524         int received;
4525         struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
4526
4527         hw_idx = *(tnapi->rx_rcb_prod_idx);
4528         /*
4529          * We need to order the read of hw_idx and the read of
4530          * the opaque cookie.
4531          */
4532         rmb();
4533         work_mask = 0;
4534         received = 0;
4535         while (sw_idx != hw_idx && budget > 0) {
4536                 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
4537                 unsigned int len;
4538                 struct sk_buff *skb;
4539                 dma_addr_t dma_addr;
4540                 u32 opaque_key, desc_idx, *post_ptr;
4541
4542                 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4543                 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4544                 if (opaque_key == RXD_OPAQUE_RING_STD) {
4545                         struct ring_info *ri = &tpr->rx_std_buffers[desc_idx];
4546                         dma_addr = pci_unmap_addr(ri, mapping);
4547                         skb = ri->skb;
4548                         post_ptr = &tpr->rx_std_ptr;
4549                         rx_std_posted++;
4550                 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4551                         struct ring_info *ri = &tpr->rx_jmb_buffers[desc_idx];
4552                         dma_addr = pci_unmap_addr(ri, mapping);
4553                         skb = ri->skb;
4554                         post_ptr = &tpr->rx_jmb_ptr;
4555                 } else
4556                         goto next_pkt_nopost;
4557
4558                 work_mask |= opaque_key;
4559
4560                 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4561                     (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4562                 drop_it:
4563                         tg3_recycle_rx(tnapi, opaque_key,
4564                                        desc_idx, *post_ptr);
4565                 drop_it_no_recycle:
4566                         /* Other statistics kept track of by card. */
4567                         tp->net_stats.rx_dropped++;
4568                         goto next_pkt;
4569                 }
4570
4571                 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4572                       ETH_FCS_LEN;
4573
4574                 if (len > RX_COPY_THRESHOLD
4575                         && tp->rx_offset == NET_IP_ALIGN
4576                         /* rx_offset will likely not equal NET_IP_ALIGN
4577                          * if this is a 5701 card running in PCI-X mode
4578                          * [see tg3_get_invariants()]
4579                          */
4580                 ) {
4581                         int skb_size;
4582
4583                         skb_size = tg3_alloc_rx_skb(tnapi, opaque_key,
4584                                                     desc_idx, *post_ptr);
4585                         if (skb_size < 0)
4586                                 goto drop_it;
4587
4588                         pci_unmap_single(tp->pdev, dma_addr, skb_size,
4589                                          PCI_DMA_FROMDEVICE);
4590
4591                         skb_put(skb, len);
4592                 } else {
4593                         struct sk_buff *copy_skb;
4594
4595                         tg3_recycle_rx(tnapi, opaque_key,
4596                                        desc_idx, *post_ptr);
4597
4598                         copy_skb = netdev_alloc_skb(tp->dev,
4599                                                     len + TG3_RAW_IP_ALIGN);
4600                         if (copy_skb == NULL)
4601                                 goto drop_it_no_recycle;
4602
4603                         skb_reserve(copy_skb, TG3_RAW_IP_ALIGN);
4604                         skb_put(copy_skb, len);
4605                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4606                         skb_copy_from_linear_data(skb, copy_skb->data, len);
4607                         pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4608
4609                         /* We'll reuse the original ring buffer. */
4610                         skb = copy_skb;
4611                 }
4612
4613                 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4614                     (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4615                     (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4616                       >> RXD_TCPCSUM_SHIFT) == 0xffff))
4617                         skb->ip_summed = CHECKSUM_UNNECESSARY;
4618                 else
4619                         skb->ip_summed = CHECKSUM_NONE;
4620
4621                 skb->protocol = eth_type_trans(skb, tp->dev);
4622
4623                 if (len > (tp->dev->mtu + ETH_HLEN) &&
4624                     skb->protocol != htons(ETH_P_8021Q)) {
4625                         dev_kfree_skb(skb);
4626                         goto next_pkt;
4627                 }
4628
4629 #if TG3_VLAN_TAG_USED
4630                 if (tp->vlgrp != NULL &&
4631                     desc->type_flags & RXD_FLAG_VLAN) {
4632                         vlan_gro_receive(&tnapi->napi, tp->vlgrp,
4633                                          desc->err_vlan & RXD_VLAN_MASK, skb);
4634                 } else
4635 #endif
4636                         napi_gro_receive(&tnapi->napi, skb);
4637
4638                 received++;
4639                 budget--;
4640
4641 next_pkt:
4642                 (*post_ptr)++;
4643
4644                 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4645                         u32 idx = *post_ptr % TG3_RX_RING_SIZE;
4646
4647                         tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX +
4648                                      TG3_64BIT_REG_LOW, idx);
4649                         work_mask &= ~RXD_OPAQUE_RING_STD;
4650                         rx_std_posted = 0;
4651                 }
4652 next_pkt_nopost:
4653                 sw_idx++;
4654                 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
4655
4656                 /* Refresh hw_idx to see if there is new work */
4657                 if (sw_idx == hw_idx) {
4658                         hw_idx = *(tnapi->rx_rcb_prod_idx);
4659                         rmb();
4660                 }
4661         }
4662
4663         /* ACK the status ring. */
4664         tnapi->rx_rcb_ptr = sw_idx;
4665         tw32_rx_mbox(tnapi->consmbox, sw_idx);
4666
4667         /* Refill RX ring(s). */
4668         if (work_mask & RXD_OPAQUE_RING_STD) {
4669                 sw_idx = tpr->rx_std_ptr % TG3_RX_RING_SIZE;
4670                 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
4671                              sw_idx);
4672         }
4673         if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4674                 sw_idx = tpr->rx_jmb_ptr % TG3_RX_JUMBO_RING_SIZE;
4675                 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
4676                              sw_idx);
4677         }
4678         mmiowb();
4679
4680         return received;
4681 }
4682
4683 static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
4684 {
4685         struct tg3 *tp = tnapi->tp;
4686         struct tg3_hw_status *sblk = tnapi->hw_status;
4687
4688         /* handle link change and other phy events */
4689         if (!(tp->tg3_flags &
4690               (TG3_FLAG_USE_LINKCHG_REG |
4691                TG3_FLAG_POLL_SERDES))) {
4692                 if (sblk->status & SD_STATUS_LINK_CHG) {
4693                         sblk->status = SD_STATUS_UPDATED |
4694                                 (sblk->status & ~SD_STATUS_LINK_CHG);
4695                         spin_lock(&tp->lock);
4696                         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4697                                 tw32_f(MAC_STATUS,
4698                                      (MAC_STATUS_SYNC_CHANGED |
4699                                       MAC_STATUS_CFG_CHANGED |
4700                                       MAC_STATUS_MI_COMPLETION |
4701                                       MAC_STATUS_LNKSTATE_CHANGED));
4702                                 udelay(40);
4703                         } else
4704                                 tg3_setup_phy(tp, 0);
4705                         spin_unlock(&tp->lock);
4706                 }
4707         }
4708
4709         /* run TX completion thread */
4710         if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
4711                 tg3_tx(tnapi);
4712                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4713                         return work_done;
4714         }
4715
4716         /* run RX thread, within the bounds set by NAPI.
4717          * All RX "locking" is done by ensuring outside
4718          * code synchronizes with tg3->napi.poll()
4719          */
4720         if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
4721                 work_done += tg3_rx(tnapi, budget - work_done);
4722
4723         return work_done;
4724 }
4725
4726 static int tg3_poll(struct napi_struct *napi, int budget)
4727 {
4728         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
4729         struct tg3 *tp = tnapi->tp;
4730         int work_done = 0;
4731         struct tg3_hw_status *sblk = tnapi->hw_status;
4732
4733         while (1) {
4734                 work_done = tg3_poll_work(tnapi, work_done, budget);
4735
4736                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4737                         goto tx_recovery;
4738
4739                 if (unlikely(work_done >= budget))
4740                         break;
4741
4742                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
4743                         /* tp->last_tag is used in tg3_int_reenable() below
4744                          * to tell the hw how much work has been processed,
4745                          * so we must read it before checking for more work.
4746                          */
4747                         tnapi->last_tag = sblk->status_tag;
4748                         tnapi->last_irq_tag = tnapi->last_tag;
4749                         rmb();
4750                 } else
4751                         sblk->status &= ~SD_STATUS_UPDATED;
4752
4753                 if (likely(!tg3_has_work(tnapi))) {
4754                         napi_complete(napi);
4755                         tg3_int_reenable(tnapi);
4756                         break;
4757                 }
4758         }
4759
4760         return work_done;
4761
4762 tx_recovery:
4763         /* work_done is guaranteed to be less than budget. */
4764         napi_complete(napi);
4765         schedule_work(&tp->reset_task);
4766         return work_done;
4767 }
4768
4769 static void tg3_irq_quiesce(struct tg3 *tp)
4770 {
4771         int i;
4772
4773         BUG_ON(tp->irq_sync);
4774
4775         tp->irq_sync = 1;
4776         smp_mb();
4777
4778         for (i = 0; i < tp->irq_cnt; i++)
4779                 synchronize_irq(tp->napi[i].irq_vec);
4780 }
4781
4782 static inline int tg3_irq_sync(struct tg3 *tp)
4783 {
4784         return tp->irq_sync;
4785 }
4786
4787 /* Fully shutdown all tg3 driver activity elsewhere in the system.
4788  * If irq_sync is non-zero, then the IRQ handler must be synchronized
4789  * with as well.  Most of the time, this is not necessary except when
4790  * shutting down the device.
4791  */
4792 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
4793 {
4794         spin_lock_bh(&tp->lock);
4795         if (irq_sync)
4796                 tg3_irq_quiesce(tp);
4797 }
4798
4799 static inline void tg3_full_unlock(struct tg3 *tp)
4800 {
4801         spin_unlock_bh(&tp->lock);
4802 }
4803
4804 /* One-shot MSI handler - Chip automatically disables interrupt
4805  * after sending MSI so driver doesn't have to do it.
4806  */
4807 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
4808 {
4809         struct tg3_napi *tnapi = dev_id;
4810         struct tg3 *tp = tnapi->tp;
4811
4812         prefetch(tnapi->hw_status);
4813         if (tnapi->rx_rcb)
4814                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
4815
4816         if (likely(!tg3_irq_sync(tp)))
4817                 napi_schedule(&tnapi->napi);
4818
4819         return IRQ_HANDLED;
4820 }
4821
4822 /* MSI ISR - No need to check for interrupt sharing and no need to
4823  * flush status block and interrupt mailbox. PCI ordering rules
4824  * guarantee that MSI will arrive after the status block.
4825  */
4826 static irqreturn_t tg3_msi(int irq, void *dev_id)
4827 {
4828         struct tg3_napi *tnapi = dev_id;
4829         struct tg3 *tp = tnapi->tp;
4830
4831         prefetch(tnapi->hw_status);
4832         if (tnapi->rx_rcb)
4833                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
4834         /*
4835          * Writing any value to intr-mbox-0 clears PCI INTA# and
4836          * chip-internal interrupt pending events.
4837          * Writing non-zero to intr-mbox-0 additional tells the
4838          * NIC to stop sending us irqs, engaging "in-intr-handler"
4839          * event coalescing.
4840          */
4841         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4842         if (likely(!tg3_irq_sync(tp)))
4843                 napi_schedule(&tnapi->napi);
4844
4845         return IRQ_RETVAL(1);
4846 }
4847
4848 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
4849 {
4850         struct tg3_napi *tnapi = dev_id;
4851         struct tg3 *tp = tnapi->tp;
4852         struct tg3_hw_status *sblk = tnapi->hw_status;
4853         unsigned int handled = 1;
4854
4855         /* In INTx mode, it is possible for the interrupt to arrive at
4856          * the CPU before the status block posted prior to the interrupt.
4857          * Reading the PCI State register will confirm whether the
4858          * interrupt is ours and will flush the status block.
4859          */
4860         if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
4861                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4862                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4863                         handled = 0;
4864                         goto out;
4865                 }
4866         }
4867
4868         /*
4869          * Writing any value to intr-mbox-0 clears PCI INTA# and
4870          * chip-internal interrupt pending events.
4871          * Writing non-zero to intr-mbox-0 additional tells the
4872          * NIC to stop sending us irqs, engaging "in-intr-handler"
4873          * event coalescing.
4874          *
4875          * Flush the mailbox to de-assert the IRQ immediately to prevent
4876          * spurious interrupts.  The flush impacts performance but
4877          * excessive spurious interrupts can be worse in some cases.
4878          */
4879         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4880         if (tg3_irq_sync(tp))
4881                 goto out;
4882         sblk->status &= ~SD_STATUS_UPDATED;
4883         if (likely(tg3_has_work(tnapi))) {
4884                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
4885                 napi_schedule(&tnapi->napi);
4886         } else {
4887                 /* No work, shared interrupt perhaps?  re-enable
4888                  * interrupts, and flush that PCI write
4889                  */
4890                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
4891                                0x00000000);
4892         }
4893 out:
4894         return IRQ_RETVAL(handled);
4895 }
4896
4897 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
4898 {
4899         struct tg3_napi *tnapi = dev_id;
4900         struct tg3 *tp = tnapi->tp;
4901         struct tg3_hw_status *sblk = tnapi->hw_status;
4902         unsigned int handled = 1;
4903
4904         /* In INTx mode, it is possible for the interrupt to arrive at
4905          * the CPU before the status block posted prior to the interrupt.
4906          * Reading the PCI State register will confirm whether the
4907          * interrupt is ours and will flush the status block.
4908          */
4909         if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
4910                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4911                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4912                         handled = 0;
4913                         goto out;
4914                 }
4915         }
4916
4917         /*
4918          * writing any value to intr-mbox-0 clears PCI INTA# and
4919          * chip-internal interrupt pending events.
4920          * writing non-zero to intr-mbox-0 additional tells the
4921          * NIC to stop sending us irqs, engaging "in-intr-handler"
4922          * event coalescing.
4923          *
4924          * Flush the mailbox to de-assert the IRQ immediately to prevent
4925          * spurious interrupts.  The flush impacts performance but
4926          * excessive spurious interrupts can be worse in some cases.
4927          */
4928         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4929
4930         /*
4931          * In a shared interrupt configuration, sometimes other devices'
4932          * interrupts will scream.  We record the current status tag here
4933          * so that the above check can report that the screaming interrupts
4934          * are unhandled.  Eventually they will be silenced.
4935          */
4936         tnapi->last_irq_tag = sblk->status_tag;
4937
4938         if (tg3_irq_sync(tp))
4939                 goto out;
4940
4941         prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
4942
4943         napi_schedule(&tnapi->napi);
4944
4945 out:
4946         return IRQ_RETVAL(handled);
4947 }
4948
4949 /* ISR for interrupt test */
4950 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
4951 {
4952         struct tg3_napi *tnapi = dev_id;
4953         struct tg3 *tp = tnapi->tp;
4954         struct tg3_hw_status *sblk = tnapi->hw_status;
4955
4956         if ((sblk->status & SD_STATUS_UPDATED) ||
4957             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4958                 tg3_disable_ints(tp);
4959                 return IRQ_RETVAL(1);
4960         }
4961         return IRQ_RETVAL(0);
4962 }
4963
4964 static int tg3_init_hw(struct tg3 *, int);
4965 static int tg3_halt(struct tg3 *, int, int);
4966
4967 /* Restart hardware after configuration changes, self-test, etc.
4968  * Invoked with tp->lock held.
4969  */
4970 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
4971         __releases(tp->lock)
4972         __acquires(tp->lock)
4973 {
4974         int err;
4975
4976         err = tg3_init_hw(tp, reset_phy);
4977         if (err) {
4978                 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
4979                        "aborting.\n", tp->dev->name);
4980                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
4981                 tg3_full_unlock(tp);
4982                 del_timer_sync(&tp->timer);
4983                 tp->irq_sync = 0;
4984                 tg3_napi_enable(tp);
4985                 dev_close(tp->dev);
4986                 tg3_full_lock(tp, 0);
4987         }
4988         return err;
4989 }
4990
4991 #ifdef CONFIG_NET_POLL_CONTROLLER
4992 static void tg3_poll_controller(struct net_device *dev)
4993 {
4994         int i;
4995         struct tg3 *tp = netdev_priv(dev);
4996
4997         for (i = 0; i < tp->irq_cnt; i++)
4998                 tg3_interrupt(tp->napi[i].irq_vec, dev);
4999 }
5000 #endif
5001
5002 static void tg3_reset_task(struct work_struct *work)
5003 {
5004         struct tg3 *tp = container_of(work, struct tg3, reset_task);
5005         int err;
5006         unsigned int restart_timer;
5007
5008         tg3_full_lock(tp, 0);
5009
5010         if (!netif_running(tp->dev)) {
5011                 tg3_full_unlock(tp);
5012                 return;
5013         }
5014
5015         tg3_full_unlock(tp);
5016
5017         tg3_phy_stop(tp);
5018
5019         tg3_netif_stop(tp);
5020
5021         tg3_full_lock(tp, 1);
5022
5023         restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
5024         tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
5025
5026         if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
5027                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
5028                 tp->write32_rx_mbox = tg3_write_flush_reg32;
5029                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
5030                 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
5031         }
5032
5033         tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
5034         err = tg3_init_hw(tp, 1);
5035         if (err)
5036                 goto out;
5037
5038         tg3_netif_start(tp);
5039
5040         if (restart_timer)
5041                 mod_timer(&tp->timer, jiffies + 1);
5042
5043 out:
5044         tg3_full_unlock(tp);
5045
5046         if (!err)
5047                 tg3_phy_start(tp);
5048 }
5049
5050 static void tg3_dump_short_state(struct tg3 *tp)
5051 {
5052         printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5053                tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
5054         printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5055                tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
5056 }
5057
5058 static void tg3_tx_timeout(struct net_device *dev)
5059 {
5060         struct tg3 *tp = netdev_priv(dev);
5061
5062         if (netif_msg_tx_err(tp)) {
5063                 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
5064                        dev->name);
5065                 tg3_dump_short_state(tp);
5066         }
5067
5068         schedule_work(&tp->reset_task);
5069 }
5070
5071 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5072 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5073 {
5074         u32 base = (u32) mapping & 0xffffffff;
5075
5076         return ((base > 0xffffdcc0) &&
5077                 (base + len + 8 < base));
5078 }
5079
5080 /* Test for DMA addresses > 40-bit */
5081 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5082                                           int len)
5083 {
5084 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
5085         if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
5086                 return (((u64) mapping + len) > DMA_BIT_MASK(40));
5087         return 0;
5088 #else
5089         return 0;
5090 #endif
5091 }
5092
5093 static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32);
5094
5095 /* Workaround 4GB and 40-bit hardware DMA bugs. */
5096 static int tigon3_dma_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
5097                                        u32 last_plus_one, u32 *start,
5098                                        u32 base_flags, u32 mss)
5099 {
5100         struct tg3_napi *tnapi = &tp->napi[0];
5101         struct sk_buff *new_skb;
5102         dma_addr_t new_addr = 0;
5103         u32 entry = *start;
5104         int i, ret = 0;
5105
5106         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5107                 new_skb = skb_copy(skb, GFP_ATOMIC);
5108         else {
5109                 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5110
5111                 new_skb = skb_copy_expand(skb,
5112                                           skb_headroom(skb) + more_headroom,
5113                                           skb_tailroom(skb), GFP_ATOMIC);
5114         }
5115
5116         if (!new_skb) {
5117                 ret = -1;
5118         } else {
5119                 /* New SKB is guaranteed to be linear. */
5120                 entry = *start;
5121                 ret = skb_dma_map(&tp->pdev->dev, new_skb, DMA_TO_DEVICE);
5122                 new_addr = skb_shinfo(new_skb)->dma_head;
5123
5124                 /* Make sure new skb does not cross any 4G boundaries.
5125                  * Drop the packet if it does.
5126                  */
5127                 if (ret || tg3_4g_overflow_test(new_addr, new_skb->len)) {
5128                         if (!ret)
5129                                 skb_dma_unmap(&tp->pdev->dev, new_skb,
5130                                               DMA_TO_DEVICE);
5131                         ret = -1;
5132                         dev_kfree_skb(new_skb);
5133                         new_skb = NULL;
5134                 } else {
5135                         tg3_set_txd(tnapi, entry, new_addr, new_skb->len,
5136                                     base_flags, 1 | (mss << 1));
5137                         *start = NEXT_TX(entry);
5138                 }
5139         }
5140
5141         /* Now clean up the sw ring entries. */
5142         i = 0;
5143         while (entry != last_plus_one) {
5144                 if (i == 0)
5145                         tnapi->tx_buffers[entry].skb = new_skb;
5146                 else
5147                         tnapi->tx_buffers[entry].skb = NULL;
5148                 entry = NEXT_TX(entry);
5149                 i++;
5150         }
5151
5152         skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
5153         dev_kfree_skb(skb);
5154
5155         return ret;
5156 }
5157
5158 static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
5159                         dma_addr_t mapping, int len, u32 flags,
5160                         u32 mss_and_is_end)
5161 {
5162         struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
5163         int is_end = (mss_and_is_end & 0x1);
5164         u32 mss = (mss_and_is_end >> 1);
5165         u32 vlan_tag = 0;
5166
5167         if (is_end)
5168                 flags |= TXD_FLAG_END;
5169         if (flags & TXD_FLAG_VLAN) {
5170                 vlan_tag = flags >> 16;
5171                 flags &= 0xffff;
5172         }
5173         vlan_tag |= (mss << TXD_MSS_SHIFT);
5174
5175         txd->addr_hi = ((u64) mapping >> 32);
5176         txd->addr_lo = ((u64) mapping & 0xffffffff);
5177         txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5178         txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5179 }
5180
5181 /* hard_start_xmit for devices that don't have any bugs and
5182  * support TG3_FLG2_HW_TSO_2 only.
5183  */
5184 static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5185                                   struct net_device *dev)
5186 {
5187         struct tg3 *tp = netdev_priv(dev);
5188         u32 len, entry, base_flags, mss;
5189         struct skb_shared_info *sp;
5190         dma_addr_t mapping;
5191         struct tg3_napi *tnapi;
5192         struct netdev_queue *txq;
5193
5194         txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5195         tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5196         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
5197                 tnapi++;
5198
5199         /* We are running in BH disabled context with netif_tx_lock
5200          * and TX reclaim runs via tp->napi.poll inside of a software
5201          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5202          * no IRQ context deadlocks to worry about either.  Rejoice!
5203          */
5204         if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5205                 if (!netif_tx_queue_stopped(txq)) {
5206                         netif_tx_stop_queue(txq);
5207
5208                         /* This is a hard error, log it. */
5209                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5210                                "queue awake!\n", dev->name);
5211                 }
5212                 return NETDEV_TX_BUSY;
5213         }
5214
5215         entry = tnapi->tx_prod;
5216         base_flags = 0;
5217         mss = 0;
5218         if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5219                 int tcp_opt_len, ip_tcp_len;
5220                 u32 hdrlen;
5221
5222                 if (skb_header_cloned(skb) &&
5223                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5224                         dev_kfree_skb(skb);
5225                         goto out_unlock;
5226                 }
5227
5228                 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
5229                         hdrlen = skb_headlen(skb) - ETH_HLEN;
5230                 else {
5231                         struct iphdr *iph = ip_hdr(skb);
5232
5233                         tcp_opt_len = tcp_optlen(skb);
5234                         ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5235
5236                         iph->check = 0;
5237                         iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
5238                         hdrlen = ip_tcp_len + tcp_opt_len;
5239                 }
5240
5241                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
5242                         mss |= (hdrlen & 0xc) << 12;
5243                         if (hdrlen & 0x10)
5244                                 base_flags |= 0x00000010;
5245                         base_flags |= (hdrlen & 0x3e0) << 5;
5246                 } else
5247                         mss |= hdrlen << 9;
5248
5249                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5250                                TXD_FLAG_CPU_POST_DMA);
5251
5252                 tcp_hdr(skb)->check = 0;
5253
5254         }
5255         else if (skb->ip_summed == CHECKSUM_PARTIAL)
5256                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5257 #if TG3_VLAN_TAG_USED
5258         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5259                 base_flags |= (TXD_FLAG_VLAN |
5260                                (vlan_tx_tag_get(skb) << 16));
5261 #endif
5262
5263         if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
5264                 dev_kfree_skb(skb);
5265                 goto out_unlock;
5266         }
5267
5268         sp = skb_shinfo(skb);
5269
5270         mapping = sp->dma_head;
5271
5272         tnapi->tx_buffers[entry].skb = skb;
5273
5274         len = skb_headlen(skb);
5275
5276         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
5277             !mss && skb->len > ETH_DATA_LEN)
5278                 base_flags |= TXD_FLAG_JMB_PKT;
5279
5280         tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5281                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5282
5283         entry = NEXT_TX(entry);
5284
5285         /* Now loop through additional data fragments, and queue them. */
5286         if (skb_shinfo(skb)->nr_frags > 0) {
5287                 unsigned int i, last;
5288
5289                 last = skb_shinfo(skb)->nr_frags - 1;
5290                 for (i = 0; i <= last; i++) {
5291                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5292
5293                         len = frag->size;
5294                         mapping = sp->dma_maps[i];
5295                         tnapi->tx_buffers[entry].skb = NULL;
5296
5297                         tg3_set_txd(tnapi, entry, mapping, len,
5298                                     base_flags, (i == last) | (mss << 1));
5299
5300                         entry = NEXT_TX(entry);
5301                 }
5302         }
5303
5304         /* Packets are ready, update Tx producer idx local and on card. */
5305         tw32_tx_mbox(tnapi->prodmbox, entry);
5306
5307         tnapi->tx_prod = entry;
5308         if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5309                 netif_tx_stop_queue(txq);
5310                 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5311                         netif_tx_wake_queue(txq);
5312         }
5313
5314 out_unlock:
5315         mmiowb();
5316
5317         return NETDEV_TX_OK;
5318 }
5319
5320 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *,
5321                                           struct net_device *);
5322
5323 /* Use GSO to workaround a rare TSO bug that may be triggered when the
5324  * TSO header is greater than 80 bytes.
5325  */
5326 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5327 {
5328         struct sk_buff *segs, *nskb;
5329         u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
5330
5331         /* Estimate the number of fragments in the worst case */
5332         if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
5333                 netif_stop_queue(tp->dev);
5334                 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
5335                         return NETDEV_TX_BUSY;
5336
5337                 netif_wake_queue(tp->dev);
5338         }
5339
5340         segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
5341         if (IS_ERR(segs))
5342                 goto tg3_tso_bug_end;
5343
5344         do {
5345                 nskb = segs;
5346                 segs = segs->next;
5347                 nskb->next = NULL;
5348                 tg3_start_xmit_dma_bug(nskb, tp->dev);
5349         } while (segs);
5350
5351 tg3_tso_bug_end:
5352         dev_kfree_skb(skb);
5353
5354         return NETDEV_TX_OK;
5355 }
5356
5357 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5358  * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5359  */
5360 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
5361                                           struct net_device *dev)
5362 {
5363         struct tg3 *tp = netdev_priv(dev);
5364         u32 len, entry, base_flags, mss;
5365         struct skb_shared_info *sp;
5366         int would_hit_hwbug;
5367         dma_addr_t mapping;
5368         struct tg3_napi *tnapi = &tp->napi[0];
5369
5370         len = skb_headlen(skb);
5371
5372         /* We are running in BH disabled context with netif_tx_lock
5373          * and TX reclaim runs via tp->napi.poll inside of a software
5374          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5375          * no IRQ context deadlocks to worry about either.  Rejoice!
5376          */
5377         if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5378                 if (!netif_queue_stopped(dev)) {
5379                         netif_stop_queue(dev);
5380
5381                         /* This is a hard error, log it. */
5382                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5383                                "queue awake!\n", dev->name);
5384                 }
5385                 return NETDEV_TX_BUSY;
5386         }
5387
5388         entry = tnapi->tx_prod;
5389         base_flags = 0;
5390         if (skb->ip_summed == CHECKSUM_PARTIAL)
5391                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5392         mss = 0;
5393         if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5394                 struct iphdr *iph;
5395                 int tcp_opt_len, ip_tcp_len, hdr_len;
5396
5397                 if (skb_header_cloned(skb) &&
5398                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5399                         dev_kfree_skb(skb);
5400                         goto out_unlock;
5401                 }
5402
5403                 tcp_opt_len = tcp_optlen(skb);
5404                 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5405
5406                 hdr_len = ip_tcp_len + tcp_opt_len;
5407                 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
5408                              (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
5409                         return (tg3_tso_bug(tp, skb));
5410
5411                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5412                                TXD_FLAG_CPU_POST_DMA);
5413
5414                 iph = ip_hdr(skb);
5415                 iph->check = 0;
5416                 iph->tot_len = htons(mss + hdr_len);
5417                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
5418                         tcp_hdr(skb)->check = 0;
5419                         base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
5420                 } else
5421                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5422                                                                  iph->daddr, 0,
5423                                                                  IPPROTO_TCP,
5424                                                                  0);
5425
5426                 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
5427                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
5428                         if (tcp_opt_len || iph->ihl > 5) {
5429                                 int tsflags;
5430
5431                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5432                                 mss |= (tsflags << 11);
5433                         }
5434                 } else {
5435                         if (tcp_opt_len || iph->ihl > 5) {
5436                                 int tsflags;
5437
5438                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5439                                 base_flags |= tsflags << 12;
5440                         }
5441                 }
5442         }
5443 #if TG3_VLAN_TAG_USED
5444         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5445                 base_flags |= (TXD_FLAG_VLAN |
5446                                (vlan_tx_tag_get(skb) << 16));
5447 #endif
5448
5449         if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
5450                 dev_kfree_skb(skb);
5451                 goto out_unlock;
5452         }
5453
5454         sp = skb_shinfo(skb);
5455
5456         mapping = sp->dma_head;
5457
5458         tnapi->tx_buffers[entry].skb = skb;
5459
5460         would_hit_hwbug = 0;
5461
5462         if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
5463                 would_hit_hwbug = 1;
5464         else if (tg3_4g_overflow_test(mapping, len))
5465                 would_hit_hwbug = 1;
5466
5467         tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5468                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5469
5470         entry = NEXT_TX(entry);
5471
5472         /* Now loop through additional data fragments, and queue them. */
5473         if (skb_shinfo(skb)->nr_frags > 0) {
5474                 unsigned int i, last;
5475
5476                 last = skb_shinfo(skb)->nr_frags - 1;
5477                 for (i = 0; i <= last; i++) {
5478                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5479
5480                         len = frag->size;
5481                         mapping = sp->dma_maps[i];
5482
5483                         tnapi->tx_buffers[entry].skb = NULL;
5484
5485                         if (tg3_4g_overflow_test(mapping, len))
5486                                 would_hit_hwbug = 1;
5487
5488                         if (tg3_40bit_overflow_test(tp, mapping, len))
5489                                 would_hit_hwbug = 1;
5490
5491                         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5492                                 tg3_set_txd(tnapi, entry, mapping, len,
5493                                             base_flags, (i == last)|(mss << 1));
5494                         else
5495                                 tg3_set_txd(tnapi, entry, mapping, len,
5496                                             base_flags, (i == last));
5497
5498                         entry = NEXT_TX(entry);
5499                 }
5500         }
5501
5502         if (would_hit_hwbug) {
5503                 u32 last_plus_one = entry;
5504                 u32 start;
5505
5506                 start = entry - 1 - skb_shinfo(skb)->nr_frags;
5507                 start &= (TG3_TX_RING_SIZE - 1);
5508
5509                 /* If the workaround fails due to memory/mapping
5510                  * failure, silently drop this packet.
5511                  */
5512                 if (tigon3_dma_hwbug_workaround(tp, skb, last_plus_one,
5513                                                 &start, base_flags, mss))
5514                         goto out_unlock;
5515
5516                 entry = start;
5517         }
5518
5519         /* Packets are ready, update Tx producer idx local and on card. */
5520         tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, entry);
5521
5522         tnapi->tx_prod = entry;
5523         if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5524                 netif_stop_queue(dev);
5525                 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5526                         netif_wake_queue(tp->dev);
5527         }
5528
5529 out_unlock:
5530         mmiowb();
5531
5532         return NETDEV_TX_OK;
5533 }
5534
5535 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
5536                                int new_mtu)
5537 {
5538         dev->mtu = new_mtu;
5539
5540         if (new_mtu > ETH_DATA_LEN) {
5541                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
5542                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
5543                         ethtool_op_set_tso(dev, 0);
5544                 }
5545                 else
5546                         tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
5547         } else {
5548                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
5549                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
5550                 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
5551         }
5552 }
5553
5554 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
5555 {
5556         struct tg3 *tp = netdev_priv(dev);
5557         int err;
5558
5559         if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
5560                 return -EINVAL;
5561
5562         if (!netif_running(dev)) {
5563                 /* We'll just catch it later when the
5564                  * device is up'd.
5565                  */
5566                 tg3_set_mtu(dev, tp, new_mtu);
5567                 return 0;
5568         }
5569
5570         tg3_phy_stop(tp);
5571
5572         tg3_netif_stop(tp);
5573
5574         tg3_full_lock(tp, 1);
5575
5576         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5577
5578         tg3_set_mtu(dev, tp, new_mtu);
5579
5580         err = tg3_restart_hw(tp, 0);
5581
5582         if (!err)
5583                 tg3_netif_start(tp);
5584
5585         tg3_full_unlock(tp);
5586
5587         if (!err)
5588                 tg3_phy_start(tp);
5589
5590         return err;
5591 }
5592
5593 static void tg3_rx_prodring_free(struct tg3 *tp,
5594                                  struct tg3_rx_prodring_set *tpr)
5595 {
5596         int i;
5597         struct ring_info *rxp;
5598
5599         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5600                 rxp = &tpr->rx_std_buffers[i];
5601
5602                 if (rxp->skb == NULL)
5603                         continue;
5604
5605                 pci_unmap_single(tp->pdev,
5606                                  pci_unmap_addr(rxp, mapping),
5607                                  tp->rx_pkt_map_sz,
5608                                  PCI_DMA_FROMDEVICE);
5609                 dev_kfree_skb_any(rxp->skb);
5610                 rxp->skb = NULL;
5611         }
5612
5613         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
5614                 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
5615                         rxp = &tpr->rx_jmb_buffers[i];
5616
5617                         if (rxp->skb == NULL)
5618                                 continue;
5619
5620                         pci_unmap_single(tp->pdev,
5621                                          pci_unmap_addr(rxp, mapping),
5622                                          TG3_RX_JMB_MAP_SZ,
5623                                          PCI_DMA_FROMDEVICE);
5624                         dev_kfree_skb_any(rxp->skb);
5625                         rxp->skb = NULL;
5626                 }
5627         }
5628 }
5629
5630 /* Initialize tx/rx rings for packet processing.
5631  *
5632  * The chip has been shut down and the driver detached from
5633  * the networking, so no interrupts or new tx packets will
5634  * end up in the driver.  tp->{tx,}lock are held and thus
5635  * we may not sleep.
5636  */
5637 static int tg3_rx_prodring_alloc(struct tg3 *tp,
5638                                  struct tg3_rx_prodring_set *tpr)
5639 {
5640         u32 i, rx_pkt_dma_sz;
5641         struct tg3_napi *tnapi = &tp->napi[0];
5642
5643         /* Zero out all descriptors. */
5644         memset(tpr->rx_std, 0, TG3_RX_RING_BYTES);
5645
5646         rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
5647         if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
5648             tp->dev->mtu > ETH_DATA_LEN)
5649                 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
5650         tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
5651
5652         /* Initialize invariants of the rings, we only set this
5653          * stuff once.  This works because the card does not
5654          * write into the rx buffer posting rings.
5655          */
5656         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5657                 struct tg3_rx_buffer_desc *rxd;
5658
5659                 rxd = &tpr->rx_std[i];
5660                 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
5661                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
5662                 rxd->opaque = (RXD_OPAQUE_RING_STD |
5663                                (i << RXD_OPAQUE_INDEX_SHIFT));
5664         }
5665
5666         /* Now allocate fresh SKBs for each rx ring. */
5667         for (i = 0; i < tp->rx_pending; i++) {
5668                 if (tg3_alloc_rx_skb(tnapi, RXD_OPAQUE_RING_STD, -1, i) < 0) {
5669                         printk(KERN_WARNING PFX
5670                                "%s: Using a smaller RX standard ring, "
5671                                "only %d out of %d buffers were allocated "
5672                                "successfully.\n",
5673                                tp->dev->name, i, tp->rx_pending);
5674                         if (i == 0)
5675                                 goto initfail;
5676                         tp->rx_pending = i;
5677                         break;
5678                 }
5679         }
5680
5681         if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE))
5682                 goto done;
5683
5684         memset(tpr->rx_jmb, 0, TG3_RX_JUMBO_RING_BYTES);
5685
5686         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
5687                 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
5688                         struct tg3_rx_buffer_desc *rxd;
5689
5690                         rxd = &tpr->rx_jmb[i].std;
5691                         rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
5692                         rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
5693                                 RXD_FLAG_JUMBO;
5694                         rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
5695                                (i << RXD_OPAQUE_INDEX_SHIFT));
5696                 }
5697
5698                 for (i = 0; i < tp->rx_jumbo_pending; i++) {
5699                         if (tg3_alloc_rx_skb(tnapi, RXD_OPAQUE_RING_JUMBO,
5700                                              -1, i) < 0) {
5701                                 printk(KERN_WARNING PFX
5702                                        "%s: Using a smaller RX jumbo ring, "
5703                                        "only %d out of %d buffers were "
5704                                        "allocated successfully.\n",
5705                                        tp->dev->name, i, tp->rx_jumbo_pending);
5706                                 if (i == 0)
5707                                         goto initfail;
5708                                 tp->rx_jumbo_pending = i;
5709                                 break;
5710                         }
5711                 }
5712         }
5713
5714 done:
5715         return 0;
5716
5717 initfail:
5718         tg3_rx_prodring_free(tp, tpr);
5719         return -ENOMEM;
5720 }
5721
5722 static void tg3_rx_prodring_fini(struct tg3 *tp,
5723                                  struct tg3_rx_prodring_set *tpr)
5724 {
5725         kfree(tpr->rx_std_buffers);
5726         tpr->rx_std_buffers = NULL;
5727         kfree(tpr->rx_jmb_buffers);
5728         tpr->rx_jmb_buffers = NULL;
5729         if (tpr->rx_std) {
5730                 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
5731                                     tpr->rx_std, tpr->rx_std_mapping);
5732                 tpr->rx_std = NULL;
5733         }
5734         if (tpr->rx_jmb) {
5735                 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
5736                                     tpr->rx_jmb, tpr->rx_jmb_mapping);
5737                 tpr->rx_jmb = NULL;
5738         }
5739 }
5740
5741 static int tg3_rx_prodring_init(struct tg3 *tp,
5742                                 struct tg3_rx_prodring_set *tpr)
5743 {
5744         tpr->rx_std_buffers = kzalloc(sizeof(struct ring_info) *
5745                                       TG3_RX_RING_SIZE, GFP_KERNEL);
5746         if (!tpr->rx_std_buffers)
5747                 return -ENOMEM;
5748
5749         tpr->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
5750                                            &tpr->rx_std_mapping);
5751         if (!tpr->rx_std)
5752                 goto err_out;
5753
5754         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
5755                 tpr->rx_jmb_buffers = kzalloc(sizeof(struct ring_info) *
5756                                               TG3_RX_JUMBO_RING_SIZE,
5757                                               GFP_KERNEL);
5758                 if (!tpr->rx_jmb_buffers)
5759                         goto err_out;
5760
5761                 tpr->rx_jmb = pci_alloc_consistent(tp->pdev,
5762                                                    TG3_RX_JUMBO_RING_BYTES,
5763                                                    &tpr->rx_jmb_mapping);
5764                 if (!tpr->rx_jmb)
5765                         goto err_out;
5766         }
5767
5768         return 0;
5769
5770 err_out:
5771         tg3_rx_prodring_fini(tp, tpr);
5772         return -ENOMEM;
5773 }
5774
5775 /* Free up pending packets in all rx/tx rings.
5776  *
5777  * The chip has been shut down and the driver detached from
5778  * the networking, so no interrupts or new tx packets will
5779  * end up in the driver.  tp->{tx,}lock is not held and we are not
5780  * in an interrupt context and thus may sleep.
5781  */
5782 static void tg3_free_rings(struct tg3 *tp)
5783 {
5784         int i, j;
5785
5786         for (j = 0; j < tp->irq_cnt; j++) {
5787                 struct tg3_napi *tnapi = &tp->napi[j];
5788
5789                 if (!tnapi->tx_buffers)
5790                         continue;
5791
5792                 for (i = 0; i < TG3_TX_RING_SIZE; ) {
5793                         struct tx_ring_info *txp;
5794                         struct sk_buff *skb;
5795
5796                         txp = &tnapi->tx_buffers[i];
5797                         skb = txp->skb;
5798
5799                         if (skb == NULL) {
5800                                 i++;
5801                                 continue;
5802                         }
5803
5804                         skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
5805
5806                         txp->skb = NULL;
5807
5808                         i += skb_shinfo(skb)->nr_frags + 1;
5809
5810                         dev_kfree_skb_any(skb);
5811                 }
5812         }
5813
5814         tg3_rx_prodring_free(tp, &tp->prodring[0]);
5815 }
5816
5817 /* Initialize tx/rx rings for packet processing.
5818  *
5819  * The chip has been shut down and the driver detached from
5820  * the networking, so no interrupts or new tx packets will
5821  * end up in the driver.  tp->{tx,}lock are held and thus
5822  * we may not sleep.
5823  */
5824 static int tg3_init_rings(struct tg3 *tp)
5825 {
5826         int i;
5827
5828         /* Free up all the SKBs. */
5829         tg3_free_rings(tp);
5830
5831         for (i = 0; i < tp->irq_cnt; i++) {
5832                 struct tg3_napi *tnapi = &tp->napi[i];
5833
5834                 tnapi->last_tag = 0;
5835                 tnapi->last_irq_tag = 0;
5836                 tnapi->hw_status->status = 0;
5837                 tnapi->hw_status->status_tag = 0;
5838                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
5839
5840                 tnapi->tx_prod = 0;
5841                 tnapi->tx_cons = 0;
5842                 if (tnapi->tx_ring)
5843                         memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
5844
5845                 tnapi->rx_rcb_ptr = 0;
5846                 if (tnapi->rx_rcb)
5847                         memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
5848         }
5849
5850         return tg3_rx_prodring_alloc(tp, &tp->prodring[0]);
5851 }
5852
5853 /*
5854  * Must not be invoked with interrupt sources disabled and
5855  * the hardware shutdown down.
5856  */
5857 static void tg3_free_consistent(struct tg3 *tp)
5858 {
5859         int i;
5860
5861         for (i = 0; i < tp->irq_cnt; i++) {
5862                 struct tg3_napi *tnapi = &tp->napi[i];
5863
5864                 if (tnapi->tx_ring) {
5865                         pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
5866                                 tnapi->tx_ring, tnapi->tx_desc_mapping);
5867                         tnapi->tx_ring = NULL;
5868                 }
5869
5870                 kfree(tnapi->tx_buffers);
5871                 tnapi->tx_buffers = NULL;
5872
5873                 if (tnapi->rx_rcb) {
5874                         pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
5875                                             tnapi->rx_rcb,
5876                                             tnapi->rx_rcb_mapping);
5877                         tnapi->rx_rcb = NULL;
5878                 }
5879
5880                 if (tnapi->hw_status) {
5881                         pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
5882                                             tnapi->hw_status,
5883                                             tnapi->status_mapping);
5884                         tnapi->hw_status = NULL;
5885                 }
5886         }
5887
5888         if (tp->hw_stats) {
5889                 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
5890                                     tp->hw_stats, tp->stats_mapping);
5891                 tp->hw_stats = NULL;
5892         }
5893
5894         tg3_rx_prodring_fini(tp, &tp->prodring[0]);
5895 }
5896
5897 /*
5898  * Must not be invoked with interrupt sources disabled and
5899  * the hardware shutdown down.  Can sleep.
5900  */
5901 static int tg3_alloc_consistent(struct tg3 *tp)
5902 {
5903         int i;
5904
5905         if (tg3_rx_prodring_init(tp, &tp->prodring[0]))
5906                 return -ENOMEM;
5907
5908         tp->hw_stats = pci_alloc_consistent(tp->pdev,
5909                                             sizeof(struct tg3_hw_stats),
5910                                             &tp->stats_mapping);
5911         if (!tp->hw_stats)
5912                 goto err_out;
5913
5914         memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
5915
5916         for (i = 0; i < tp->irq_cnt; i++) {
5917                 struct tg3_napi *tnapi = &tp->napi[i];
5918                 struct tg3_hw_status *sblk;
5919
5920                 tnapi->hw_status = pci_alloc_consistent(tp->pdev,
5921                                                         TG3_HW_STATUS_SIZE,
5922                                                         &tnapi->status_mapping);
5923                 if (!tnapi->hw_status)
5924                         goto err_out;
5925
5926                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
5927                 sblk = tnapi->hw_status;
5928
5929                 /*
5930                  * When RSS is enabled, the status block format changes
5931                  * slightly.  The "rx_jumbo_consumer", "reserved",
5932                  * and "rx_mini_consumer" members get mapped to the
5933                  * other three rx return ring producer indexes.
5934                  */
5935                 switch (i) {
5936                 default:
5937                         tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
5938                         break;
5939                 case 2:
5940                         tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer;
5941                         break;
5942                 case 3:
5943                         tnapi->rx_rcb_prod_idx = &sblk->reserved;
5944                         break;
5945                 case 4:
5946                         tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer;
5947                         break;
5948                 }
5949
5950                 /*
5951                  * If multivector RSS is enabled, vector 0 does not handle
5952                  * rx or tx interrupts.  Don't allocate any resources for it.
5953                  */
5954                 if (!i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS))
5955                         continue;
5956
5957                 tnapi->rx_rcb = pci_alloc_consistent(tp->pdev,
5958                                                      TG3_RX_RCB_RING_BYTES(tp),
5959                                                      &tnapi->rx_rcb_mapping);
5960                 if (!tnapi->rx_rcb)
5961                         goto err_out;
5962
5963                 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
5964
5965                 tnapi->tx_buffers = kzalloc(sizeof(struct tx_ring_info) *
5966                                             TG3_TX_RING_SIZE, GFP_KERNEL);
5967                 if (!tnapi->tx_buffers)
5968                         goto err_out;
5969
5970                 tnapi->tx_ring = pci_alloc_consistent(tp->pdev,
5971                                                       TG3_TX_RING_BYTES,
5972                                                       &tnapi->tx_desc_mapping);
5973                 if (!tnapi->tx_ring)
5974                         goto err_out;
5975         }
5976
5977         return 0;
5978
5979 err_out:
5980         tg3_free_consistent(tp);
5981         return -ENOMEM;
5982 }
5983
5984 #define MAX_WAIT_CNT 1000
5985
5986 /* To stop a block, clear the enable bit and poll till it
5987  * clears.  tp->lock is held.
5988  */
5989 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
5990 {
5991         unsigned int i;
5992         u32 val;
5993
5994         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
5995                 switch (ofs) {
5996                 case RCVLSC_MODE:
5997                 case DMAC_MODE:
5998                 case MBFREE_MODE:
5999                 case BUFMGR_MODE:
6000                 case MEMARB_MODE:
6001                         /* We can't enable/disable these bits of the
6002                          * 5705/5750, just say success.
6003                          */
6004                         return 0;
6005
6006                 default:
6007                         break;
6008                 }
6009         }
6010
6011         val = tr32(ofs);
6012         val &= ~enable_bit;
6013         tw32_f(ofs, val);
6014
6015         for (i = 0; i < MAX_WAIT_CNT; i++) {
6016                 udelay(100);
6017                 val = tr32(ofs);
6018                 if ((val & enable_bit) == 0)
6019                         break;
6020         }
6021
6022         if (i == MAX_WAIT_CNT && !silent) {
6023                 printk(KERN_ERR PFX "tg3_stop_block timed out, "
6024                        "ofs=%lx enable_bit=%x\n",
6025                        ofs, enable_bit);
6026                 return -ENODEV;
6027         }
6028
6029         return 0;
6030 }
6031
6032 /* tp->lock is held. */
6033 static int tg3_abort_hw(struct tg3 *tp, int silent)
6034 {
6035         int i, err;
6036
6037         tg3_disable_ints(tp);
6038
6039         tp->rx_mode &= ~RX_MODE_ENABLE;
6040         tw32_f(MAC_RX_MODE, tp->rx_mode);
6041         udelay(10);
6042
6043         err  = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
6044         err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
6045         err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
6046         err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
6047         err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
6048         err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
6049
6050         err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
6051         err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
6052         err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
6053         err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
6054         err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
6055         err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
6056         err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
6057
6058         tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
6059         tw32_f(MAC_MODE, tp->mac_mode);
6060         udelay(40);
6061
6062         tp->tx_mode &= ~TX_MODE_ENABLE;
6063         tw32_f(MAC_TX_MODE, tp->tx_mode);
6064
6065         for (i = 0; i < MAX_WAIT_CNT; i++) {
6066                 udelay(100);
6067                 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
6068                         break;
6069         }
6070         if (i >= MAX_WAIT_CNT) {
6071                 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
6072                        "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
6073                        tp->dev->name, tr32(MAC_TX_MODE));
6074                 err |= -ENODEV;
6075         }
6076
6077         err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
6078         err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
6079         err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
6080
6081         tw32(FTQ_RESET, 0xffffffff);
6082         tw32(FTQ_RESET, 0x00000000);
6083
6084         err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
6085         err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
6086
6087         for (i = 0; i < tp->irq_cnt; i++) {
6088                 struct tg3_napi *tnapi = &tp->napi[i];
6089                 if (tnapi->hw_status)
6090                         memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6091         }
6092         if (tp->hw_stats)
6093                 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6094
6095         return err;
6096 }
6097
6098 static void tg3_ape_send_event(struct tg3 *tp, u32 event)
6099 {
6100         int i;
6101         u32 apedata;
6102
6103         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
6104         if (apedata != APE_SEG_SIG_MAGIC)
6105                 return;
6106
6107         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
6108         if (!(apedata & APE_FW_STATUS_READY))
6109                 return;
6110
6111         /* Wait for up to 1 millisecond for APE to service previous event. */
6112         for (i = 0; i < 10; i++) {
6113                 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
6114                         return;
6115
6116                 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
6117
6118                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6119                         tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
6120                                         event | APE_EVENT_STATUS_EVENT_PENDING);
6121
6122                 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
6123
6124                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6125                         break;
6126
6127                 udelay(100);
6128         }
6129
6130         if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6131                 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
6132 }
6133
6134 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
6135 {
6136         u32 event;
6137         u32 apedata;
6138
6139         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
6140                 return;
6141
6142         switch (kind) {
6143                 case RESET_KIND_INIT:
6144                         tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
6145                                         APE_HOST_SEG_SIG_MAGIC);
6146                         tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
6147                                         APE_HOST_SEG_LEN_MAGIC);
6148                         apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
6149                         tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
6150                         tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
6151                                         APE_HOST_DRIVER_ID_MAGIC);
6152                         tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
6153                                         APE_HOST_BEHAV_NO_PHYLOCK);
6154
6155                         event = APE_EVENT_STATUS_STATE_START;
6156                         break;
6157                 case RESET_KIND_SHUTDOWN:
6158                         /* With the interface we are currently using,
6159                          * APE does not track driver state.  Wiping
6160                          * out the HOST SEGMENT SIGNATURE forces
6161                          * the APE to assume OS absent status.
6162                          */
6163                         tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
6164
6165                         event = APE_EVENT_STATUS_STATE_UNLOAD;
6166                         break;
6167                 case RESET_KIND_SUSPEND:
6168                         event = APE_EVENT_STATUS_STATE_SUSPEND;
6169                         break;
6170                 default:
6171                         return;
6172         }
6173
6174         event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
6175
6176         tg3_ape_send_event(tp, event);
6177 }
6178
6179 /* tp->lock is held. */
6180 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
6181 {
6182         tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
6183                       NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
6184
6185         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6186                 switch (kind) {
6187                 case RESET_KIND_INIT:
6188                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6189                                       DRV_STATE_START);
6190                         break;
6191
6192                 case RESET_KIND_SHUTDOWN:
6193                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6194                                       DRV_STATE_UNLOAD);
6195                         break;
6196
6197                 case RESET_KIND_SUSPEND:
6198                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6199                                       DRV_STATE_SUSPEND);
6200                         break;
6201
6202                 default:
6203                         break;
6204                 }
6205         }
6206
6207         if (kind == RESET_KIND_INIT ||
6208             kind == RESET_KIND_SUSPEND)
6209                 tg3_ape_driver_state_change(tp, kind);
6210 }
6211
6212 /* tp->lock is held. */
6213 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
6214 {
6215         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6216                 switch (kind) {
6217                 case RESET_KIND_INIT:
6218                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6219                                       DRV_STATE_START_DONE);
6220                         break;
6221
6222                 case RESET_KIND_SHUTDOWN:
6223                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6224                                       DRV_STATE_UNLOAD_DONE);
6225                         break;
6226
6227                 default:
6228                         break;
6229                 }
6230         }
6231
6232         if (kind == RESET_KIND_SHUTDOWN)
6233                 tg3_ape_driver_state_change(tp, kind);
6234 }
6235
6236 /* tp->lock is held. */
6237 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
6238 {
6239         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6240                 switch (kind) {
6241                 case RESET_KIND_INIT:
6242                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6243                                       DRV_STATE_START);
6244                         break;
6245
6246                 case RESET_KIND_SHUTDOWN:
6247                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6248                                       DRV_STATE_UNLOAD);
6249                         break;
6250
6251                 case RESET_KIND_SUSPEND:
6252                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6253                                       DRV_STATE_SUSPEND);
6254                         break;
6255
6256                 default:
6257                         break;
6258                 }
6259         }
6260 }
6261
6262 static int tg3_poll_fw(struct tg3 *tp)
6263 {
6264         int i;
6265         u32 val;
6266
6267         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6268                 /* Wait up to 20ms for init done. */
6269                 for (i = 0; i < 200; i++) {
6270                         if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
6271                                 return 0;
6272                         udelay(100);
6273                 }
6274                 return -ENODEV;
6275         }
6276
6277         /* Wait for firmware initialization to complete. */
6278         for (i = 0; i < 100000; i++) {
6279                 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
6280                 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
6281                         break;
6282                 udelay(10);
6283         }
6284
6285         /* Chip might not be fitted with firmware.  Some Sun onboard
6286          * parts are configured like that.  So don't signal the timeout
6287          * of the above loop as an error, but do report the lack of
6288          * running firmware once.
6289          */
6290         if (i >= 100000 &&
6291             !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
6292                 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
6293
6294                 printk(KERN_INFO PFX "%s: No firmware running.\n",
6295                        tp->dev->name);
6296         }
6297
6298         return 0;
6299 }
6300
6301 /* Save PCI command register before chip reset */
6302 static void tg3_save_pci_state(struct tg3 *tp)
6303 {
6304         pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
6305 }
6306
6307 /* Restore PCI state after chip reset */
6308 static void tg3_restore_pci_state(struct tg3 *tp)
6309 {
6310         u32 val;
6311
6312         /* Re-enable indirect register accesses. */
6313         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
6314                                tp->misc_host_ctrl);
6315
6316         /* Set MAX PCI retry to zero. */
6317         val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
6318         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6319             (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
6320                 val |= PCISTATE_RETRY_SAME_DMA;
6321         /* Allow reads and writes to the APE register and memory space. */
6322         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
6323                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6324                        PCISTATE_ALLOW_APE_SHMEM_WR;
6325         pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
6326
6327         pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
6328
6329         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
6330                 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6331                         pcie_set_readrq(tp->pdev, 4096);
6332                 else {
6333                         pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
6334                                               tp->pci_cacheline_sz);
6335                         pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
6336                                               tp->pci_lat_timer);
6337                 }
6338         }
6339
6340         /* Make sure PCI-X relaxed ordering bit is clear. */
6341         if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
6342                 u16 pcix_cmd;
6343
6344                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6345                                      &pcix_cmd);
6346                 pcix_cmd &= ~PCI_X_CMD_ERO;
6347                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6348                                       pcix_cmd);
6349         }
6350
6351         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
6352
6353                 /* Chip reset on 5780 will reset MSI enable bit,
6354                  * so need to restore it.
6355                  */
6356                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6357                         u16 ctrl;
6358
6359                         pci_read_config_word(tp->pdev,
6360                                              tp->msi_cap + PCI_MSI_FLAGS,
6361                                              &ctrl);
6362                         pci_write_config_word(tp->pdev,
6363                                               tp->msi_cap + PCI_MSI_FLAGS,
6364                                               ctrl | PCI_MSI_FLAGS_ENABLE);
6365                         val = tr32(MSGINT_MODE);
6366                         tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
6367                 }
6368         }
6369 }
6370
6371 static void tg3_stop_fw(struct tg3 *);
6372
6373 /* tp->lock is held. */
6374 static int tg3_chip_reset(struct tg3 *tp)
6375 {
6376         u32 val;
6377         void (*write_op)(struct tg3 *, u32, u32);
6378         int i, err;
6379
6380         tg3_nvram_lock(tp);
6381
6382         tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
6383
6384         /* No matching tg3_nvram_unlock() after this because
6385          * chip reset below will undo the nvram lock.
6386          */
6387         tp->nvram_lock_cnt = 0;
6388
6389         /* GRC_MISC_CFG core clock reset will clear the memory
6390          * enable bit in PCI register 4 and the MSI enable bit
6391          * on some chips, so we save relevant registers here.
6392          */
6393         tg3_save_pci_state(tp);
6394
6395         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
6396             (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
6397                 tw32(GRC_FASTBOOT_PC, 0);
6398
6399         /*
6400          * We must avoid the readl() that normally takes place.
6401          * It locks machines, causes machine checks, and other
6402          * fun things.  So, temporarily disable the 5701
6403          * hardware workaround, while we do the reset.
6404          */
6405         write_op = tp->write32;
6406         if (write_op == tg3_write_flush_reg32)
6407                 tp->write32 = tg3_write32;
6408
6409         /* Prevent the irq handler from reading or writing PCI registers
6410          * during chip reset when the memory enable bit in the PCI command
6411          * register may be cleared.  The chip does not generate interrupt
6412          * at this time, but the irq handler may still be called due to irq
6413          * sharing or irqpoll.
6414          */
6415         tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
6416         for (i = 0; i < tp->irq_cnt; i++) {
6417                 struct tg3_napi *tnapi = &tp->napi[i];
6418                 if (tnapi->hw_status) {
6419                         tnapi->hw_status->status = 0;
6420                         tnapi->hw_status->status_tag = 0;
6421                 }
6422                 tnapi->last_tag = 0;
6423                 tnapi->last_irq_tag = 0;
6424         }
6425         smp_mb();
6426
6427         for (i = 0; i < tp->irq_cnt; i++)
6428                 synchronize_irq(tp->napi[i].irq_vec);
6429
6430         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6431                 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
6432                 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
6433         }
6434
6435         /* do the reset */
6436         val = GRC_MISC_CFG_CORECLK_RESET;
6437
6438         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
6439                 if (tr32(0x7e2c) == 0x60) {
6440                         tw32(0x7e2c, 0x20);
6441                 }
6442                 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6443                         tw32(GRC_MISC_CFG, (1 << 29));
6444                         val |= (1 << 29);
6445                 }
6446         }
6447
6448         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6449                 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
6450                 tw32(GRC_VCPU_EXT_CTRL,
6451                      tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
6452         }
6453
6454         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6455                 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
6456         tw32(GRC_MISC_CFG, val);
6457
6458         /* restore 5701 hardware bug workaround write method */
6459         tp->write32 = write_op;
6460
6461         /* Unfortunately, we have to delay before the PCI read back.
6462          * Some 575X chips even will not respond to a PCI cfg access
6463          * when the reset command is given to the chip.
6464          *
6465          * How do these hardware designers expect things to work
6466          * properly if the PCI write is posted for a long period
6467          * of time?  It is always necessary to have some method by
6468          * which a register read back can occur to push the write
6469          * out which does the reset.
6470          *
6471          * For most tg3 variants the trick below was working.
6472          * Ho hum...
6473          */
6474         udelay(120);
6475
6476         /* Flush PCI posted writes.  The normal MMIO registers
6477          * are inaccessible at this time so this is the only
6478          * way to make this reliably (actually, this is no longer
6479          * the case, see above).  I tried to use indirect
6480          * register read/write but this upset some 5701 variants.
6481          */
6482         pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
6483
6484         udelay(120);
6485
6486         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
6487                 u16 val16;
6488
6489                 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
6490                         int i;
6491                         u32 cfg_val;
6492
6493                         /* Wait for link training to complete.  */
6494                         for (i = 0; i < 5000; i++)
6495                                 udelay(100);
6496
6497                         pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
6498                         pci_write_config_dword(tp->pdev, 0xc4,
6499                                                cfg_val | (1 << 15));
6500                 }
6501
6502                 /* Clear the "no snoop" and "relaxed ordering" bits. */
6503                 pci_read_config_word(tp->pdev,
6504                                      tp->pcie_cap + PCI_EXP_DEVCTL,
6505                                      &val16);
6506                 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
6507                            PCI_EXP_DEVCTL_NOSNOOP_EN);
6508                 /*
6509                  * Older PCIe devices only support the 128 byte
6510                  * MPS setting.  Enforce the restriction.
6511                  */
6512                 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
6513                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784))
6514                         val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
6515                 pci_write_config_word(tp->pdev,
6516                                       tp->pcie_cap + PCI_EXP_DEVCTL,
6517                                       val16);
6518
6519                 pcie_set_readrq(tp->pdev, 4096);
6520
6521                 /* Clear error status */
6522                 pci_write_config_word(tp->pdev,
6523                                       tp->pcie_cap + PCI_EXP_DEVSTA,
6524                                       PCI_EXP_DEVSTA_CED |
6525                                       PCI_EXP_DEVSTA_NFED |
6526                                       PCI_EXP_DEVSTA_FED |
6527                                       PCI_EXP_DEVSTA_URD);
6528         }
6529
6530         tg3_restore_pci_state(tp);
6531
6532         tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
6533
6534         val = 0;
6535         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
6536                 val = tr32(MEMARB_MODE);
6537         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
6538
6539         if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
6540                 tg3_stop_fw(tp);
6541                 tw32(0x5000, 0x400);
6542         }
6543
6544         tw32(GRC_MODE, tp->grc_mode);
6545
6546         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
6547                 val = tr32(0xc4);
6548
6549                 tw32(0xc4, val | (1 << 15));
6550         }
6551
6552         if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
6553             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6554                 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
6555                 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
6556                         tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
6557                 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6558         }
6559
6560         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6561                 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
6562                 tw32_f(MAC_MODE, tp->mac_mode);
6563         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
6564                 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
6565                 tw32_f(MAC_MODE, tp->mac_mode);
6566         } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
6567                 tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
6568                 if (tp->mac_mode & MAC_MODE_APE_TX_EN)
6569                         tp->mac_mode |= MAC_MODE_TDE_ENABLE;
6570                 tw32_f(MAC_MODE, tp->mac_mode);
6571         } else
6572                 tw32_f(MAC_MODE, 0);
6573         udelay(40);
6574
6575         tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
6576
6577         err = tg3_poll_fw(tp);
6578         if (err)
6579                 return err;
6580
6581         tg3_mdio_start(tp);
6582
6583         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
6584             tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
6585             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
6586             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) {
6587                 val = tr32(0x7c00);
6588
6589                 tw32(0x7c00, val | (1 << 25));
6590         }
6591
6592         /* Reprobe ASF enable state.  */
6593         tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
6594         tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
6595         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
6596         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
6597                 u32 nic_cfg;
6598
6599                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
6600                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
6601                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
6602                         tp->last_event_jiffies = jiffies;
6603                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
6604                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
6605                 }
6606         }
6607
6608         return 0;
6609 }
6610
6611 /* tp->lock is held. */
6612 static void tg3_stop_fw(struct tg3 *tp)
6613 {
6614         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
6615            !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
6616                 /* Wait for RX cpu to ACK the previous event. */
6617                 tg3_wait_for_event_ack(tp);
6618
6619                 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
6620
6621                 tg3_generate_fw_event(tp);
6622
6623                 /* Wait for RX cpu to ACK this event. */
6624                 tg3_wait_for_event_ack(tp);
6625         }
6626 }
6627
6628 /* tp->lock is held. */
6629 static int tg3_halt(struct tg3 *tp, int kind, int silent)
6630 {
6631         int err;
6632
6633         tg3_stop_fw(tp);
6634
6635         tg3_write_sig_pre_reset(tp, kind);
6636
6637         tg3_abort_hw(tp, silent);
6638         err = tg3_chip_reset(tp);
6639
6640         __tg3_set_mac_addr(tp, 0);
6641
6642         tg3_write_sig_legacy(tp, kind);
6643         tg3_write_sig_post_reset(tp, kind);
6644
6645         if (err)
6646                 return err;
6647
6648         return 0;
6649 }
6650
6651 #define RX_CPU_SCRATCH_BASE     0x30000
6652 #define RX_CPU_SCRATCH_SIZE     0x04000
6653 #define TX_CPU_SCRATCH_BASE     0x34000
6654 #define TX_CPU_SCRATCH_SIZE     0x04000
6655
6656 /* tp->lock is held. */
6657 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
6658 {
6659         int i;
6660
6661         BUG_ON(offset == TX_CPU_BASE &&
6662             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
6663
6664         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6665                 u32 val = tr32(GRC_VCPU_EXT_CTRL);
6666
6667                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
6668                 return 0;
6669         }
6670         if (offset == RX_CPU_BASE) {
6671                 for (i = 0; i < 10000; i++) {
6672                         tw32(offset + CPU_STATE, 0xffffffff);
6673                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
6674                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6675                                 break;
6676                 }
6677
6678                 tw32(offset + CPU_STATE, 0xffffffff);
6679                 tw32_f(offset + CPU_MODE,  CPU_MODE_HALT);
6680                 udelay(10);
6681         } else {
6682                 for (i = 0; i < 10000; i++) {
6683                         tw32(offset + CPU_STATE, 0xffffffff);
6684                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
6685                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6686                                 break;
6687                 }
6688         }
6689
6690         if (i >= 10000) {
6691                 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
6692                        "and %s CPU\n",
6693                        tp->dev->name,
6694                        (offset == RX_CPU_BASE ? "RX" : "TX"));
6695                 return -ENODEV;
6696         }
6697
6698         /* Clear firmware's nvram arbitration. */
6699         if (tp->tg3_flags & TG3_FLAG_NVRAM)
6700                 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
6701         return 0;
6702 }
6703
6704 struct fw_info {
6705         unsigned int fw_base;
6706         unsigned int fw_len;
6707         const __be32 *fw_data;
6708 };
6709
6710 /* tp->lock is held. */
6711 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
6712                                  int cpu_scratch_size, struct fw_info *info)
6713 {
6714         int err, lock_err, i;
6715         void (*write_op)(struct tg3 *, u32, u32);
6716
6717         if (cpu_base == TX_CPU_BASE &&
6718             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6719                 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
6720                        "TX cpu firmware on %s which is 5705.\n",
6721                        tp->dev->name);
6722                 return -EINVAL;
6723         }
6724
6725         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6726                 write_op = tg3_write_mem;
6727         else
6728                 write_op = tg3_write_indirect_reg32;
6729
6730         /* It is possible that bootcode is still loading at this point.
6731          * Get the nvram lock first before halting the cpu.
6732          */
6733         lock_err = tg3_nvram_lock(tp);
6734         err = tg3_halt_cpu(tp, cpu_base);
6735         if (!lock_err)
6736                 tg3_nvram_unlock(tp);
6737         if (err)
6738                 goto out;
6739
6740         for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
6741                 write_op(tp, cpu_scratch_base + i, 0);
6742         tw32(cpu_base + CPU_STATE, 0xffffffff);
6743         tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
6744         for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
6745                 write_op(tp, (cpu_scratch_base +
6746                               (info->fw_base & 0xffff) +
6747                               (i * sizeof(u32))),
6748                               be32_to_cpu(info->fw_data[i]));
6749
6750         err = 0;
6751
6752 out:
6753         return err;
6754 }
6755
6756 /* tp->lock is held. */
6757 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
6758 {
6759         struct fw_info info;
6760         const __be32 *fw_data;
6761         int err, i;
6762
6763         fw_data = (void *)tp->fw->data;
6764
6765         /* Firmware blob starts with version numbers, followed by
6766            start address and length. We are setting complete length.
6767            length = end_address_of_bss - start_address_of_text.
6768            Remainder is the blob to be loaded contiguously
6769            from start address. */
6770
6771         info.fw_base = be32_to_cpu(fw_data[1]);
6772         info.fw_len = tp->fw->size - 12;
6773         info.fw_data = &fw_data[3];
6774
6775         err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
6776                                     RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
6777                                     &info);
6778         if (err)
6779                 return err;
6780
6781         err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
6782                                     TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
6783                                     &info);
6784         if (err)
6785                 return err;
6786
6787         /* Now startup only the RX cpu. */
6788         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6789         tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
6790
6791         for (i = 0; i < 5; i++) {
6792                 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
6793                         break;
6794                 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6795                 tw32(RX_CPU_BASE + CPU_MODE,  CPU_MODE_HALT);
6796                 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
6797                 udelay(1000);
6798         }
6799         if (i >= 5) {
6800                 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
6801                        "to set RX CPU PC, is %08x should be %08x\n",
6802                        tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
6803                        info.fw_base);
6804                 return -ENODEV;
6805         }
6806         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6807         tw32_f(RX_CPU_BASE + CPU_MODE,  0x00000000);
6808
6809         return 0;
6810 }
6811
6812 /* 5705 needs a special version of the TSO firmware.  */
6813
6814 /* tp->lock is held. */
6815 static int tg3_load_tso_firmware(struct tg3 *tp)
6816 {
6817         struct fw_info info;
6818         const __be32 *fw_data;
6819         unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
6820         int err, i;
6821
6822         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6823                 return 0;
6824
6825         fw_data = (void *)tp->fw->data;
6826
6827         /* Firmware blob starts with version numbers, followed by
6828            start address and length. We are setting complete length.
6829            length = end_address_of_bss - start_address_of_text.
6830            Remainder is the blob to be loaded contiguously
6831            from start address. */
6832
6833         info.fw_base = be32_to_cpu(fw_data[1]);
6834         cpu_scratch_size = tp->fw_len;
6835         info.fw_len = tp->fw->size - 12;
6836         info.fw_data = &fw_data[3];
6837
6838         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6839                 cpu_base = RX_CPU_BASE;
6840                 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
6841         } else {
6842                 cpu_base = TX_CPU_BASE;
6843                 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
6844                 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
6845         }
6846
6847         err = tg3_load_firmware_cpu(tp, cpu_base,
6848                                     cpu_scratch_base, cpu_scratch_size,
6849                                     &info);
6850         if (err)
6851                 return err;
6852
6853         /* Now startup the cpu. */
6854         tw32(cpu_base + CPU_STATE, 0xffffffff);
6855         tw32_f(cpu_base + CPU_PC, info.fw_base);
6856
6857         for (i = 0; i < 5; i++) {
6858                 if (tr32(cpu_base + CPU_PC) == info.fw_base)
6859                         break;
6860                 tw32(cpu_base + CPU_STATE, 0xffffffff);
6861                 tw32(cpu_base + CPU_MODE,  CPU_MODE_HALT);
6862                 tw32_f(cpu_base + CPU_PC, info.fw_base);
6863                 udelay(1000);
6864         }
6865         if (i >= 5) {
6866                 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
6867                        "to set CPU PC, is %08x should be %08x\n",
6868                        tp->dev->name, tr32(cpu_base + CPU_PC),
6869                        info.fw_base);
6870                 return -ENODEV;
6871         }
6872         tw32(cpu_base + CPU_STATE, 0xffffffff);
6873         tw32_f(cpu_base + CPU_MODE,  0x00000000);
6874         return 0;
6875 }
6876
6877
6878 static int tg3_set_mac_addr(struct net_device *dev, void *p)
6879 {
6880         struct tg3 *tp = netdev_priv(dev);
6881         struct sockaddr *addr = p;
6882         int err = 0, skip_mac_1 = 0;
6883
6884         if (!is_valid_ether_addr(addr->sa_data))
6885                 return -EINVAL;
6886
6887         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
6888
6889         if (!netif_running(dev))
6890                 return 0;
6891
6892         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6893                 u32 addr0_high, addr0_low, addr1_high, addr1_low;
6894
6895                 addr0_high = tr32(MAC_ADDR_0_HIGH);
6896                 addr0_low = tr32(MAC_ADDR_0_LOW);
6897                 addr1_high = tr32(MAC_ADDR_1_HIGH);
6898                 addr1_low = tr32(MAC_ADDR_1_LOW);
6899
6900                 /* Skip MAC addr 1 if ASF is using it. */
6901                 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
6902                     !(addr1_high == 0 && addr1_low == 0))
6903                         skip_mac_1 = 1;
6904         }
6905         spin_lock_bh(&tp->lock);
6906         __tg3_set_mac_addr(tp, skip_mac_1);
6907         spin_unlock_bh(&tp->lock);
6908
6909         return err;
6910 }
6911
6912 /* tp->lock is held. */
6913 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
6914                            dma_addr_t mapping, u32 maxlen_flags,
6915                            u32 nic_addr)
6916 {
6917         tg3_write_mem(tp,
6918                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
6919                       ((u64) mapping >> 32));
6920         tg3_write_mem(tp,
6921                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
6922                       ((u64) mapping & 0xffffffff));
6923         tg3_write_mem(tp,
6924                       (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
6925                        maxlen_flags);
6926
6927         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6928                 tg3_write_mem(tp,
6929                               (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
6930                               nic_addr);
6931 }
6932
6933 static void __tg3_set_rx_mode(struct net_device *);
6934 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
6935 {
6936         int i;
6937
6938         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
6939                 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
6940                 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
6941                 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
6942
6943                 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
6944                 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
6945                 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
6946         } else {
6947                 tw32(HOSTCC_TXCOL_TICKS, 0);
6948                 tw32(HOSTCC_TXMAX_FRAMES, 0);
6949                 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
6950
6951                 tw32(HOSTCC_RXCOL_TICKS, 0);
6952                 tw32(HOSTCC_RXMAX_FRAMES, 0);
6953                 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
6954         }
6955
6956         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6957                 u32 val = ec->stats_block_coalesce_usecs;
6958
6959                 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
6960                 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
6961
6962                 if (!netif_carrier_ok(tp->dev))
6963                         val = 0;
6964
6965                 tw32(HOSTCC_STAT_COAL_TICKS, val);
6966         }
6967
6968         for (i = 0; i < tp->irq_cnt - 1; i++) {
6969                 u32 reg;
6970
6971                 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
6972                 tw32(reg, ec->rx_coalesce_usecs);
6973                 reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
6974                 tw32(reg, ec->tx_coalesce_usecs);
6975                 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
6976                 tw32(reg, ec->rx_max_coalesced_frames);
6977                 reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
6978                 tw32(reg, ec->tx_max_coalesced_frames);
6979                 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
6980                 tw32(reg, ec->rx_max_coalesced_frames_irq);
6981                 reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
6982                 tw32(reg, ec->tx_max_coalesced_frames_irq);
6983         }
6984
6985         for (; i < tp->irq_max - 1; i++) {
6986                 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
6987                 tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
6988                 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
6989                 tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
6990                 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
6991                 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
6992         }
6993 }
6994
6995 /* tp->lock is held. */
6996 static void tg3_rings_reset(struct tg3 *tp)
6997 {
6998         int i;
6999         u32 stblk, txrcb, rxrcb, limit;
7000         struct tg3_napi *tnapi = &tp->napi[0];
7001
7002         /* Disable all transmit rings but the first. */
7003         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7004                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
7005         else
7006                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7007
7008         for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7009              txrcb < limit; txrcb += TG3_BDINFO_SIZE)
7010                 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
7011                               BDINFO_FLAGS_DISABLED);
7012
7013
7014         /* Disable all receive return rings but the first. */
7015         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
7016                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
7017         else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7018                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
7019         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
7020                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
7021         else
7022                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7023
7024         for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7025              rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
7026                 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
7027                               BDINFO_FLAGS_DISABLED);
7028
7029         /* Disable interrupts */
7030         tw32_mailbox_f(tp->napi[0].int_mbox, 1);
7031
7032         /* Zero mailbox registers. */
7033         if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) {
7034                 for (i = 1; i < TG3_IRQ_MAX_VECS; i++) {
7035                         tp->napi[i].tx_prod = 0;
7036                         tp->napi[i].tx_cons = 0;
7037                         tw32_mailbox(tp->napi[i].prodmbox, 0);
7038                         tw32_rx_mbox(tp->napi[i].consmbox, 0);
7039                         tw32_mailbox_f(tp->napi[i].int_mbox, 1);
7040                 }
7041         } else {
7042                 tp->napi[0].tx_prod = 0;
7043                 tp->napi[0].tx_cons = 0;
7044                 tw32_mailbox(tp->napi[0].prodmbox, 0);
7045                 tw32_rx_mbox(tp->napi[0].consmbox, 0);
7046         }
7047
7048         /* Make sure the NIC-based send BD rings are disabled. */
7049         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7050                 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
7051                 for (i = 0; i < 16; i++)
7052                         tw32_tx_mbox(mbox + i * 8, 0);
7053         }
7054
7055         txrcb = NIC_SRAM_SEND_RCB;
7056         rxrcb = NIC_SRAM_RCV_RET_RCB;
7057
7058         /* Clear status block in ram. */
7059         memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7060
7061         /* Set status block DMA address */
7062         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7063              ((u64) tnapi->status_mapping >> 32));
7064         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7065              ((u64) tnapi->status_mapping & 0xffffffff));
7066
7067         if (tnapi->tx_ring) {
7068                 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7069                                (TG3_TX_RING_SIZE <<
7070                                 BDINFO_FLAGS_MAXLEN_SHIFT),
7071                                NIC_SRAM_TX_BUFFER_DESC);
7072                 txrcb += TG3_BDINFO_SIZE;
7073         }
7074
7075         if (tnapi->rx_rcb) {
7076                 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7077                                (TG3_RX_RCB_RING_SIZE(tp) <<
7078                                 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7079                 rxrcb += TG3_BDINFO_SIZE;
7080         }
7081
7082         stblk = HOSTCC_STATBLCK_RING1;
7083
7084         for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
7085                 u64 mapping = (u64)tnapi->status_mapping;
7086                 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
7087                 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
7088
7089                 /* Clear status block in ram. */
7090                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7091
7092                 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7093                                (TG3_TX_RING_SIZE <<
7094                                 BDINFO_FLAGS_MAXLEN_SHIFT),
7095                                NIC_SRAM_TX_BUFFER_DESC);
7096
7097                 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7098                                (TG3_RX_RCB_RING_SIZE(tp) <<
7099                                 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7100
7101                 stblk += 8;
7102                 txrcb += TG3_BDINFO_SIZE;
7103                 rxrcb += TG3_BDINFO_SIZE;
7104         }
7105 }
7106
7107 /* tp->lock is held. */
7108 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
7109 {
7110         u32 val, rdmac_mode;
7111         int i, err, limit;
7112         struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
7113
7114         tg3_disable_ints(tp);
7115
7116         tg3_stop_fw(tp);
7117
7118         tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
7119
7120         if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
7121                 tg3_abort_hw(tp, 1);
7122         }
7123
7124         if (reset_phy &&
7125             !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB))
7126                 tg3_phy_reset(tp);
7127
7128         err = tg3_chip_reset(tp);
7129         if (err)
7130                 return err;
7131
7132         tg3_write_sig_legacy(tp, RESET_KIND_INIT);
7133
7134         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
7135                 val = tr32(TG3_CPMU_CTRL);
7136                 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
7137                 tw32(TG3_CPMU_CTRL, val);
7138
7139                 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7140                 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7141                 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7142                 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7143
7144                 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
7145                 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
7146                 val |= CPMU_LNK_AWARE_MACCLK_6_25;
7147                 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
7148
7149                 val = tr32(TG3_CPMU_HST_ACC);
7150                 val &= ~CPMU_HST_ACC_MACCLK_MASK;
7151                 val |= CPMU_HST_ACC_MACCLK_6_25;
7152                 tw32(TG3_CPMU_HST_ACC, val);
7153         }
7154
7155         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7156                 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
7157                 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
7158                        PCIE_PWR_MGMT_L1_THRESH_4MS;
7159                 tw32(PCIE_PWR_MGMT_THRESH, val);
7160
7161                 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
7162                 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
7163
7164                 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
7165         }
7166
7167         if (tp->tg3_flags3 & TG3_FLG3_TOGGLE_10_100_L1PLLPD) {
7168                 val = tr32(TG3_PCIE_LNKCTL);
7169                 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG)
7170                         val |= TG3_PCIE_LNKCTL_L1_PLL_PD_DIS;
7171                 else
7172                         val &= ~TG3_PCIE_LNKCTL_L1_PLL_PD_DIS;
7173                 tw32(TG3_PCIE_LNKCTL, val);
7174         }
7175
7176         /* This works around an issue with Athlon chipsets on
7177          * B3 tigon3 silicon.  This bit has no effect on any
7178          * other revision.  But do not set this on PCI Express
7179          * chips and don't even touch the clocks if the CPMU is present.
7180          */
7181         if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
7182                 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
7183                         tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
7184                 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7185         }
7186
7187         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
7188             (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
7189                 val = tr32(TG3PCI_PCISTATE);
7190                 val |= PCISTATE_RETRY_SAME_DMA;
7191                 tw32(TG3PCI_PCISTATE, val);
7192         }
7193
7194         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7195                 /* Allow reads and writes to the
7196                  * APE register and memory space.
7197                  */
7198                 val = tr32(TG3PCI_PCISTATE);
7199                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
7200                        PCISTATE_ALLOW_APE_SHMEM_WR;
7201                 tw32(TG3PCI_PCISTATE, val);
7202         }
7203
7204         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
7205                 /* Enable some hw fixes.  */
7206                 val = tr32(TG3PCI_MSI_DATA);
7207                 val |= (1 << 26) | (1 << 28) | (1 << 29);
7208                 tw32(TG3PCI_MSI_DATA, val);
7209         }
7210
7211         /* Descriptor ring init may make accesses to the
7212          * NIC SRAM area to setup the TX descriptors, so we
7213          * can only do this after the hardware has been
7214          * successfully reset.
7215          */
7216         err = tg3_init_rings(tp);
7217         if (err)
7218                 return err;
7219
7220         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
7221             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761 &&
7222             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) {
7223                 /* This value is determined during the probe time DMA
7224                  * engine test, tg3_test_dma.
7225                  */
7226                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
7227         }
7228
7229         tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
7230                           GRC_MODE_4X_NIC_SEND_RINGS |
7231                           GRC_MODE_NO_TX_PHDR_CSUM |
7232                           GRC_MODE_NO_RX_PHDR_CSUM);
7233         tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
7234
7235         /* Pseudo-header checksum is done by hardware logic and not
7236          * the offload processers, so make the chip do the pseudo-
7237          * header checksums on receive.  For transmit it is more
7238          * convenient to do the pseudo-header checksum in software
7239          * as Linux does that on transmit for us in all cases.
7240          */
7241         tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
7242
7243         tw32(GRC_MODE,
7244              tp->grc_mode |
7245              (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
7246
7247         /* Setup the timer prescalar register.  Clock is always 66Mhz. */
7248         val = tr32(GRC_MISC_CFG);
7249         val &= ~0xff;
7250         val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
7251         tw32(GRC_MISC_CFG, val);
7252
7253         /* Initialize MBUF/DESC pool. */
7254         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7255                 /* Do nothing.  */
7256         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
7257                 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
7258                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
7259                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
7260                 else
7261                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
7262                 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
7263                 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
7264         }
7265         else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7266                 int fw_len;
7267
7268                 fw_len = tp->fw_len;
7269                 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
7270                 tw32(BUFMGR_MB_POOL_ADDR,
7271                      NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
7272                 tw32(BUFMGR_MB_POOL_SIZE,
7273                      NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
7274         }
7275
7276         if (tp->dev->mtu <= ETH_DATA_LEN) {
7277                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7278                      tp->bufmgr_config.mbuf_read_dma_low_water);
7279                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7280                      tp->bufmgr_config.mbuf_mac_rx_low_water);
7281                 tw32(BUFMGR_MB_HIGH_WATER,
7282                      tp->bufmgr_config.mbuf_high_water);
7283         } else {
7284                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7285                      tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
7286                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7287                      tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
7288                 tw32(BUFMGR_MB_HIGH_WATER,
7289                      tp->bufmgr_config.mbuf_high_water_jumbo);
7290         }
7291         tw32(BUFMGR_DMA_LOW_WATER,
7292              tp->bufmgr_config.dma_low_water);
7293         tw32(BUFMGR_DMA_HIGH_WATER,
7294              tp->bufmgr_config.dma_high_water);
7295
7296         tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
7297         for (i = 0; i < 2000; i++) {
7298                 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
7299                         break;
7300                 udelay(10);
7301         }
7302         if (i >= 2000) {
7303                 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
7304                        tp->dev->name);
7305                 return -ENODEV;
7306         }
7307
7308         /* Setup replenish threshold. */
7309         val = tp->rx_pending / 8;
7310         if (val == 0)
7311                 val = 1;
7312         else if (val > tp->rx_std_max_post)
7313                 val = tp->rx_std_max_post;
7314         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7315                 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
7316                         tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
7317
7318                 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
7319                         val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
7320         }
7321
7322         tw32(RCVBDI_STD_THRESH, val);
7323
7324         /* Initialize TG3_BDINFO's at:
7325          *  RCVDBDI_STD_BD:     standard eth size rx ring
7326          *  RCVDBDI_JUMBO_BD:   jumbo frame rx ring
7327          *  RCVDBDI_MINI_BD:    small frame rx ring (??? does not work)
7328          *
7329          * like so:
7330          *  TG3_BDINFO_HOST_ADDR:       high/low parts of DMA address of ring
7331          *  TG3_BDINFO_MAXLEN_FLAGS:    (rx max buffer size << 16) |
7332          *                              ring attribute flags
7333          *  TG3_BDINFO_NIC_ADDR:        location of descriptors in nic SRAM
7334          *
7335          * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
7336          * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
7337          *
7338          * The size of each ring is fixed in the firmware, but the location is
7339          * configurable.
7340          */
7341         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7342              ((u64) tpr->rx_std_mapping >> 32));
7343         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7344              ((u64) tpr->rx_std_mapping & 0xffffffff));
7345         tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
7346              NIC_SRAM_RX_BUFFER_DESC);
7347
7348         /* Disable the mini ring */
7349         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7350                 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
7351                      BDINFO_FLAGS_DISABLED);
7352
7353         /* Program the jumbo buffer descriptor ring control
7354          * blocks on those devices that have them.
7355          */
7356         if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
7357             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
7358                 /* Setup replenish threshold. */
7359                 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
7360
7361                 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
7362                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7363                              ((u64) tpr->rx_jmb_mapping >> 32));
7364                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7365                              ((u64) tpr->rx_jmb_mapping & 0xffffffff));
7366                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7367                              (RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT) |
7368                              BDINFO_FLAGS_USE_EXT_RECV);
7369                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
7370                              NIC_SRAM_RX_JUMBO_BUFFER_DESC);
7371                 } else {
7372                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7373                              BDINFO_FLAGS_DISABLED);
7374                 }
7375
7376                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
7377                         val = (RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT) |
7378                               (RX_STD_MAX_SIZE << 2);
7379                 else
7380                         val = RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT;
7381         } else
7382                 val = RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT;
7383
7384         tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
7385
7386         tpr->rx_std_ptr = tp->rx_pending;
7387         tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
7388                      tpr->rx_std_ptr);
7389
7390         tpr->rx_jmb_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
7391                           tp->rx_jumbo_pending : 0;
7392         tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
7393                      tpr->rx_jmb_ptr);
7394
7395         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
7396                 tw32(STD_REPLENISH_LWM, 32);
7397                 tw32(JMB_REPLENISH_LWM, 16);
7398         }
7399
7400         tg3_rings_reset(tp);
7401
7402         /* Initialize MAC address and backoff seed. */
7403         __tg3_set_mac_addr(tp, 0);
7404
7405         /* MTU + ethernet header + FCS + optional VLAN tag */
7406         tw32(MAC_RX_MTU_SIZE,
7407              tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
7408
7409         /* The slot time is changed by tg3_setup_phy if we
7410          * run at gigabit with half duplex.
7411          */
7412         tw32(MAC_TX_LENGTHS,
7413              (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
7414              (6 << TX_LENGTHS_IPG_SHIFT) |
7415              (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
7416
7417         /* Receive rules. */
7418         tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
7419         tw32(RCVLPC_CONFIG, 0x0181);
7420
7421         /* Calculate RDMAC_MODE setting early, we need it to determine
7422          * the RCVLPC_STATE_ENABLE mask.
7423          */
7424         rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
7425                       RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
7426                       RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
7427                       RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
7428                       RDMAC_MODE_LNGREAD_ENAB);
7429
7430         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
7431             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7432             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7433                 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
7434                               RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
7435                               RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
7436
7437         /* If statement applies to 5705 and 5750 PCI devices only */
7438         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7439              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7440             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
7441                 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
7442                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7443                         rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
7444                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7445                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
7446                         rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7447                 }
7448         }
7449
7450         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
7451                 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7452
7453         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7454                 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
7455
7456         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7457             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7458                 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
7459
7460         /* Receive/send statistics. */
7461         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7462                 val = tr32(RCVLPC_STATS_ENABLE);
7463                 val &= ~RCVLPC_STATSENAB_DACK_FIX;
7464                 tw32(RCVLPC_STATS_ENABLE, val);
7465         } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
7466                    (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
7467                 val = tr32(RCVLPC_STATS_ENABLE);
7468                 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
7469                 tw32(RCVLPC_STATS_ENABLE, val);
7470         } else {
7471                 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
7472         }
7473         tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
7474         tw32(SNDDATAI_STATSENAB, 0xffffff);
7475         tw32(SNDDATAI_STATSCTRL,
7476              (SNDDATAI_SCTRL_ENABLE |
7477               SNDDATAI_SCTRL_FASTUPD));
7478
7479         /* Setup host coalescing engine. */
7480         tw32(HOSTCC_MODE, 0);
7481         for (i = 0; i < 2000; i++) {
7482                 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
7483                         break;
7484                 udelay(10);
7485         }
7486
7487         __tg3_set_coalesce(tp, &tp->coal);
7488
7489         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7490                 /* Status/statistics block address.  See tg3_timer,
7491                  * the tg3_periodic_fetch_stats call there, and
7492                  * tg3_get_stats to see how this works for 5705/5750 chips.
7493                  */
7494                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7495                      ((u64) tp->stats_mapping >> 32));
7496                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7497                      ((u64) tp->stats_mapping & 0xffffffff));
7498                 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
7499
7500                 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
7501
7502                 /* Clear statistics and status block memory areas */
7503                 for (i = NIC_SRAM_STATS_BLK;
7504                      i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
7505                      i += sizeof(u32)) {
7506                         tg3_write_mem(tp, i, 0);
7507                         udelay(40);
7508                 }
7509         }
7510
7511         tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
7512
7513         tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
7514         tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
7515         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7516                 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
7517
7518         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
7519                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
7520                 /* reset to prevent losing 1st rx packet intermittently */
7521                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7522                 udelay(10);
7523         }
7524
7525         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7526                 tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
7527         else
7528                 tp->mac_mode = 0;
7529         tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
7530                 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
7531         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7532             !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7533             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
7534                 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
7535         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
7536         udelay(40);
7537
7538         /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
7539          * If TG3_FLG2_IS_NIC is zero, we should read the
7540          * register to preserve the GPIO settings for LOMs. The GPIOs,
7541          * whether used as inputs or outputs, are set by boot code after
7542          * reset.
7543          */
7544         if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
7545                 u32 gpio_mask;
7546
7547                 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
7548                             GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
7549                             GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
7550
7551                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
7552                         gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
7553                                      GRC_LCLCTRL_GPIO_OUTPUT3;
7554
7555                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
7556                         gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
7557
7558                 tp->grc_local_ctrl &= ~gpio_mask;
7559                 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
7560
7561                 /* GPIO1 must be driven high for eeprom write protect */
7562                 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
7563                         tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
7564                                                GRC_LCLCTRL_GPIO_OUTPUT1);
7565         }
7566         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7567         udelay(100);
7568
7569         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX) {
7570                 val = tr32(MSGINT_MODE);
7571                 val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE;
7572                 tw32(MSGINT_MODE, val);
7573         }
7574
7575         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7576                 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
7577                 udelay(40);
7578         }
7579
7580         val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
7581                WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
7582                WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
7583                WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
7584                WDMAC_MODE_LNGREAD_ENAB);
7585
7586         /* If statement applies to 5705 and 5750 PCI devices only */
7587         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7588              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7589             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
7590                 if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
7591                     (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
7592                      tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
7593                         /* nothing */
7594                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7595                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
7596                            !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
7597                         val |= WDMAC_MODE_RX_ACCEL;
7598                 }
7599         }
7600
7601         /* Enable host coalescing bug fix */
7602         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
7603                 val |= WDMAC_MODE_STATUS_TAG_FIX;
7604
7605         tw32_f(WDMAC_MODE, val);
7606         udelay(40);
7607
7608         if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
7609                 u16 pcix_cmd;
7610
7611                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7612                                      &pcix_cmd);
7613                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
7614                         pcix_cmd &= ~PCI_X_CMD_MAX_READ;
7615                         pcix_cmd |= PCI_X_CMD_READ_2K;
7616                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
7617                         pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
7618                         pcix_cmd |= PCI_X_CMD_READ_2K;
7619                 }
7620                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7621                                       pcix_cmd);
7622         }
7623
7624         tw32_f(RDMAC_MODE, rdmac_mode);
7625         udelay(40);
7626
7627         tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
7628         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7629                 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
7630
7631         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
7632                 tw32(SNDDATAC_MODE,
7633                      SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
7634         else
7635                 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
7636
7637         tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
7638         tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
7639         tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
7640         tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
7641         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7642                 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
7643         val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
7644         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
7645                 val |= SNDBDI_MODE_MULTI_TXQ_EN;
7646         tw32(SNDBDI_MODE, val);
7647         tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
7648
7649         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
7650                 err = tg3_load_5701_a0_firmware_fix(tp);
7651                 if (err)
7652                         return err;
7653         }
7654
7655         if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7656                 err = tg3_load_tso_firmware(tp);
7657                 if (err)
7658                         return err;
7659         }
7660
7661         tp->tx_mode = TX_MODE_ENABLE;
7662         tw32_f(MAC_TX_MODE, tp->tx_mode);
7663         udelay(100);
7664
7665         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) {
7666                 u32 reg = MAC_RSS_INDIR_TBL_0;
7667                 u8 *ent = (u8 *)&val;
7668
7669                 /* Setup the indirection table */
7670                 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
7671                         int idx = i % sizeof(val);
7672
7673                         ent[idx] = i % (tp->irq_cnt - 1);
7674                         if (idx == sizeof(val) - 1) {
7675                                 tw32(reg, val);
7676                                 reg += 4;
7677                         }
7678                 }
7679
7680                 /* Setup the "secret" hash key. */
7681                 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
7682                 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
7683                 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
7684                 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
7685                 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
7686                 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
7687                 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
7688                 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
7689                 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
7690                 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
7691         }
7692
7693         tp->rx_mode = RX_MODE_ENABLE;
7694         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
7695                 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
7696
7697         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)
7698                 tp->rx_mode |= RX_MODE_RSS_ENABLE |
7699                                RX_MODE_RSS_ITBL_HASH_BITS_7 |
7700                                RX_MODE_RSS_IPV6_HASH_EN |
7701                                RX_MODE_RSS_TCP_IPV6_HASH_EN |
7702                                RX_MODE_RSS_IPV4_HASH_EN |
7703                                RX_MODE_RSS_TCP_IPV4_HASH_EN;
7704
7705         tw32_f(MAC_RX_MODE, tp->rx_mode);
7706         udelay(10);
7707
7708         tw32(MAC_LED_CTRL, tp->led_ctrl);
7709
7710         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
7711         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7712                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7713                 udelay(10);
7714         }
7715         tw32_f(MAC_RX_MODE, tp->rx_mode);
7716         udelay(10);
7717
7718         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7719                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
7720                         !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
7721                         /* Set drive transmission level to 1.2V  */
7722                         /* only if the signal pre-emphasis bit is not set  */
7723                         val = tr32(MAC_SERDES_CFG);
7724                         val &= 0xfffff000;
7725                         val |= 0x880;
7726                         tw32(MAC_SERDES_CFG, val);
7727                 }
7728                 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
7729                         tw32(MAC_SERDES_CFG, 0x616000);
7730         }
7731
7732         /* Prevent chip from dropping frames when flow control
7733          * is enabled.
7734          */
7735         tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
7736
7737         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
7738             (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
7739                 /* Use hardware link auto-negotiation */
7740                 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
7741         }
7742
7743         if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
7744             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
7745                 u32 tmp;
7746
7747                 tmp = tr32(SERDES_RX_CTRL);
7748                 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
7749                 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
7750                 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
7751                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7752         }
7753
7754         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
7755                 if (tp->link_config.phy_is_low_power) {
7756                         tp->link_config.phy_is_low_power = 0;
7757                         tp->link_config.speed = tp->link_config.orig_speed;
7758                         tp->link_config.duplex = tp->link_config.orig_duplex;
7759                         tp->link_config.autoneg = tp->link_config.orig_autoneg;
7760                 }
7761
7762                 err = tg3_setup_phy(tp, 0);
7763                 if (err)
7764                         return err;
7765
7766                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7767                     !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)) {
7768                         u32 tmp;
7769
7770                         /* Clear CRC stats. */
7771                         if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
7772                                 tg3_writephy(tp, MII_TG3_TEST1,
7773                                              tmp | MII_TG3_TEST1_CRC_EN);
7774                                 tg3_readphy(tp, 0x14, &tmp);
7775                         }
7776                 }
7777         }
7778
7779         __tg3_set_rx_mode(tp->dev);
7780
7781         /* Initialize receive rules. */
7782         tw32(MAC_RCV_RULE_0,  0xc2000000 & RCV_RULE_DISABLE_MASK);
7783         tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
7784         tw32(MAC_RCV_RULE_1,  0x86000004 & RCV_RULE_DISABLE_MASK);
7785         tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
7786
7787         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7788             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
7789                 limit = 8;
7790         else
7791                 limit = 16;
7792         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
7793                 limit -= 4;
7794         switch (limit) {
7795         case 16:
7796                 tw32(MAC_RCV_RULE_15,  0); tw32(MAC_RCV_VALUE_15,  0);
7797         case 15:
7798                 tw32(MAC_RCV_RULE_14,  0); tw32(MAC_RCV_VALUE_14,  0);
7799         case 14:
7800                 tw32(MAC_RCV_RULE_13,  0); tw32(MAC_RCV_VALUE_13,  0);
7801         case 13:
7802                 tw32(MAC_RCV_RULE_12,  0); tw32(MAC_RCV_VALUE_12,  0);
7803         case 12:
7804                 tw32(MAC_RCV_RULE_11,  0); tw32(MAC_RCV_VALUE_11,  0);
7805         case 11:
7806                 tw32(MAC_RCV_RULE_10,  0); tw32(MAC_RCV_VALUE_10,  0);
7807         case 10:
7808                 tw32(MAC_RCV_RULE_9,  0); tw32(MAC_RCV_VALUE_9,  0);
7809         case 9:
7810                 tw32(MAC_RCV_RULE_8,  0); tw32(MAC_RCV_VALUE_8,  0);
7811         case 8:
7812                 tw32(MAC_RCV_RULE_7,  0); tw32(MAC_RCV_VALUE_7,  0);
7813         case 7:
7814                 tw32(MAC_RCV_RULE_6,  0); tw32(MAC_RCV_VALUE_6,  0);
7815         case 6:
7816                 tw32(MAC_RCV_RULE_5,  0); tw32(MAC_RCV_VALUE_5,  0);
7817         case 5:
7818                 tw32(MAC_RCV_RULE_4,  0); tw32(MAC_RCV_VALUE_4,  0);
7819         case 4:
7820                 /* tw32(MAC_RCV_RULE_3,  0); tw32(MAC_RCV_VALUE_3,  0); */
7821         case 3:
7822                 /* tw32(MAC_RCV_RULE_2,  0); tw32(MAC_RCV_VALUE_2,  0); */
7823         case 2:
7824         case 1:
7825
7826         default:
7827                 break;
7828         }
7829
7830         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7831                 /* Write our heartbeat update interval to APE. */
7832                 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
7833                                 APE_HOST_HEARTBEAT_INT_DISABLE);
7834
7835         tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
7836
7837         return 0;
7838 }
7839
7840 /* Called at device open time to get the chip ready for
7841  * packet processing.  Invoked with tp->lock held.
7842  */
7843 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
7844 {
7845         tg3_switch_clocks(tp);
7846
7847         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
7848
7849         return tg3_reset_hw(tp, reset_phy);
7850 }
7851
7852 #define TG3_STAT_ADD32(PSTAT, REG) \
7853 do {    u32 __val = tr32(REG); \
7854         (PSTAT)->low += __val; \
7855         if ((PSTAT)->low < __val) \
7856                 (PSTAT)->high += 1; \
7857 } while (0)
7858
7859 static void tg3_periodic_fetch_stats(struct tg3 *tp)
7860 {
7861         struct tg3_hw_stats *sp = tp->hw_stats;
7862
7863         if (!netif_carrier_ok(tp->dev))
7864                 return;
7865
7866         TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
7867         TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
7868         TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
7869         TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
7870         TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
7871         TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
7872         TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
7873         TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
7874         TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
7875         TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
7876         TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
7877         TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
7878         TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
7879
7880         TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
7881         TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
7882         TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
7883         TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
7884         TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
7885         TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
7886         TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
7887         TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
7888         TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
7889         TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
7890         TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
7891         TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
7892         TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
7893         TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
7894
7895         TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
7896         TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
7897         TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
7898 }
7899
7900 static void tg3_timer(unsigned long __opaque)
7901 {
7902         struct tg3 *tp = (struct tg3 *) __opaque;
7903
7904         if (tp->irq_sync)
7905                 goto restart_timer;
7906
7907         spin_lock(&tp->lock);
7908
7909         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7910                 /* All of this garbage is because when using non-tagged
7911                  * IRQ status the mailbox/status_block protocol the chip
7912                  * uses with the cpu is race prone.
7913                  */
7914                 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
7915                         tw32(GRC_LOCAL_CTRL,
7916                              tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
7917                 } else {
7918                         tw32(HOSTCC_MODE, tp->coalesce_mode |
7919                              HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
7920                 }
7921
7922                 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
7923                         tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
7924                         spin_unlock(&tp->lock);
7925                         schedule_work(&tp->reset_task);
7926                         return;
7927                 }
7928         }
7929
7930         /* This part only runs once per second. */
7931         if (!--tp->timer_counter) {
7932                 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7933                         tg3_periodic_fetch_stats(tp);
7934
7935                 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
7936                         u32 mac_stat;
7937                         int phy_event;
7938
7939                         mac_stat = tr32(MAC_STATUS);
7940
7941                         phy_event = 0;
7942                         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
7943                                 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
7944                                         phy_event = 1;
7945                         } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
7946                                 phy_event = 1;
7947
7948                         if (phy_event)
7949                                 tg3_setup_phy(tp, 0);
7950                 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
7951                         u32 mac_stat = tr32(MAC_STATUS);
7952                         int need_setup = 0;
7953
7954                         if (netif_carrier_ok(tp->dev) &&
7955                             (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
7956                                 need_setup = 1;
7957                         }
7958                         if (! netif_carrier_ok(tp->dev) &&
7959                             (mac_stat & (MAC_STATUS_PCS_SYNCED |
7960                                          MAC_STATUS_SIGNAL_DET))) {
7961                                 need_setup = 1;
7962                         }
7963                         if (need_setup) {
7964                                 if (!tp->serdes_counter) {
7965                                         tw32_f(MAC_MODE,
7966                                              (tp->mac_mode &
7967                                               ~MAC_MODE_PORT_MODE_MASK));
7968                                         udelay(40);
7969                                         tw32_f(MAC_MODE, tp->mac_mode);
7970                                         udelay(40);
7971                                 }
7972                                 tg3_setup_phy(tp, 0);
7973                         }
7974                 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
7975                         tg3_serdes_parallel_detect(tp);
7976
7977                 tp->timer_counter = tp->timer_multiplier;
7978         }
7979
7980         /* Heartbeat is only sent once every 2 seconds.
7981          *
7982          * The heartbeat is to tell the ASF firmware that the host
7983          * driver is still alive.  In the event that the OS crashes,
7984          * ASF needs to reset the hardware to free up the FIFO space
7985          * that may be filled with rx packets destined for the host.
7986          * If the FIFO is full, ASF will no longer function properly.
7987          *
7988          * Unintended resets have been reported on real time kernels
7989          * where the timer doesn't run on time.  Netpoll will also have
7990          * same problem.
7991          *
7992          * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
7993          * to check the ring condition when the heartbeat is expiring
7994          * before doing the reset.  This will prevent most unintended
7995          * resets.
7996          */
7997         if (!--tp->asf_counter) {
7998                 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
7999                     !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
8000                         tg3_wait_for_event_ack(tp);
8001
8002                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
8003                                       FWCMD_NICDRV_ALIVE3);
8004                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
8005                         /* 5 seconds timeout */
8006                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
8007
8008                         tg3_generate_fw_event(tp);
8009                 }
8010                 tp->asf_counter = tp->asf_multiplier;
8011         }
8012
8013         spin_unlock(&tp->lock);
8014
8015 restart_timer:
8016         tp->timer.expires = jiffies + tp->timer_offset;
8017         add_timer(&tp->timer);
8018 }
8019
8020 static int tg3_request_irq(struct tg3 *tp, int irq_num)
8021 {
8022         irq_handler_t fn;
8023         unsigned long flags;
8024         char *name;
8025         struct tg3_napi *tnapi = &tp->napi[irq_num];
8026
8027         if (tp->irq_cnt == 1)
8028                 name = tp->dev->name;
8029         else {
8030                 name = &tnapi->irq_lbl[0];
8031                 snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
8032                 name[IFNAMSIZ-1] = 0;
8033         }
8034
8035         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8036                 fn = tg3_msi;
8037                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
8038                         fn = tg3_msi_1shot;
8039                 flags = IRQF_SAMPLE_RANDOM;
8040         } else {
8041                 fn = tg3_interrupt;
8042                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8043                         fn = tg3_interrupt_tagged;
8044                 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
8045         }
8046
8047         return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
8048 }
8049
8050 static int tg3_test_interrupt(struct tg3 *tp)
8051 {
8052         struct tg3_napi *tnapi = &tp->napi[0];
8053         struct net_device *dev = tp->dev;
8054         int err, i, intr_ok = 0;
8055         u32 val;
8056
8057         if (!netif_running(dev))
8058                 return -ENODEV;
8059
8060         tg3_disable_ints(tp);
8061
8062         free_irq(tnapi->irq_vec, tnapi);
8063
8064         /*
8065          * Turn off MSI one shot mode.  Otherwise this test has no
8066          * observable way to know whether the interrupt was delivered.
8067          */
8068         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
8069             (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8070                 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
8071                 tw32(MSGINT_MODE, val);
8072         }
8073
8074         err = request_irq(tnapi->irq_vec, tg3_test_isr,
8075                           IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi);
8076         if (err)
8077                 return err;
8078
8079         tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
8080         tg3_enable_ints(tp);
8081
8082         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8083                tnapi->coal_now);
8084
8085         for (i = 0; i < 5; i++) {
8086                 u32 int_mbox, misc_host_ctrl;
8087
8088                 int_mbox = tr32_mailbox(tnapi->int_mbox);
8089                 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
8090
8091                 if ((int_mbox != 0) ||
8092                     (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
8093                         intr_ok = 1;
8094                         break;
8095                 }
8096
8097                 msleep(10);
8098         }
8099
8100         tg3_disable_ints(tp);
8101
8102         free_irq(tnapi->irq_vec, tnapi);
8103
8104         err = tg3_request_irq(tp, 0);
8105
8106         if (err)
8107                 return err;
8108
8109         if (intr_ok) {
8110                 /* Reenable MSI one shot mode. */
8111                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
8112                     (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8113                         val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
8114                         tw32(MSGINT_MODE, val);
8115                 }
8116                 return 0;
8117         }
8118
8119         return -EIO;
8120 }
8121
8122 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
8123  * successfully restored
8124  */
8125 static int tg3_test_msi(struct tg3 *tp)
8126 {
8127         int err;
8128         u16 pci_cmd;
8129
8130         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
8131                 return 0;
8132
8133         /* Turn off SERR reporting in case MSI terminates with Master
8134          * Abort.
8135          */
8136         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
8137         pci_write_config_word(tp->pdev, PCI_COMMAND,
8138                               pci_cmd & ~PCI_COMMAND_SERR);
8139
8140         err = tg3_test_interrupt(tp);
8141
8142         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
8143
8144         if (!err)
8145                 return 0;
8146
8147         /* other failures */
8148         if (err != -EIO)
8149                 return err;
8150
8151         /* MSI test failed, go back to INTx mode */
8152         printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
8153                "switching to INTx mode. Please report this failure to "
8154                "the PCI maintainer and include system chipset information.\n",
8155                        tp->dev->name);
8156
8157         free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8158
8159         pci_disable_msi(tp->pdev);
8160
8161         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8162
8163         err = tg3_request_irq(tp, 0);
8164         if (err)
8165                 return err;
8166
8167         /* Need to reset the chip because the MSI cycle may have terminated
8168          * with Master Abort.
8169          */
8170         tg3_full_lock(tp, 1);
8171
8172         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8173         err = tg3_init_hw(tp, 1);
8174
8175         tg3_full_unlock(tp);
8176
8177         if (err)
8178                 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8179
8180         return err;
8181 }
8182
8183 static int tg3_request_firmware(struct tg3 *tp)
8184 {
8185         const __be32 *fw_data;
8186
8187         if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
8188                 printk(KERN_ERR "%s: Failed to load firmware \"%s\"\n",
8189                        tp->dev->name, tp->fw_needed);
8190                 return -ENOENT;
8191         }
8192
8193         fw_data = (void *)tp->fw->data;
8194
8195         /* Firmware blob starts with version numbers, followed by
8196          * start address and _full_ length including BSS sections
8197          * (which must be longer than the actual data, of course
8198          */
8199
8200         tp->fw_len = be32_to_cpu(fw_data[2]);   /* includes bss */
8201         if (tp->fw_len < (tp->fw->size - 12)) {
8202                 printk(KERN_ERR "%s: bogus length %d in \"%s\"\n",
8203                        tp->dev->name, tp->fw_len, tp->fw_needed);
8204                 release_firmware(tp->fw);
8205                 tp->fw = NULL;
8206                 return -EINVAL;
8207         }
8208
8209         /* We no longer need firmware; we have it. */
8210         tp->fw_needed = NULL;
8211         return 0;
8212 }
8213
8214 static bool tg3_enable_msix(struct tg3 *tp)
8215 {
8216         int i, rc, cpus = num_online_cpus();
8217         struct msix_entry msix_ent[tp->irq_max];
8218
8219         if (cpus == 1)
8220                 /* Just fallback to the simpler MSI mode. */
8221                 return false;
8222
8223         /*
8224          * We want as many rx rings enabled as there are cpus.
8225          * The first MSIX vector only deals with link interrupts, etc,
8226          * so we add one to the number of vectors we are requesting.
8227          */
8228         tp->irq_cnt = min_t(unsigned, cpus + 1, tp->irq_max);
8229
8230         for (i = 0; i < tp->irq_max; i++) {
8231                 msix_ent[i].entry  = i;
8232                 msix_ent[i].vector = 0;
8233         }
8234
8235         rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
8236         if (rc != 0) {
8237                 if (rc < TG3_RSS_MIN_NUM_MSIX_VECS)
8238                         return false;
8239                 if (pci_enable_msix(tp->pdev, msix_ent, rc))
8240                         return false;
8241                 printk(KERN_NOTICE
8242                        "%s: Requested %d MSI-X vectors, received %d\n",
8243                        tp->dev->name, tp->irq_cnt, rc);
8244                 tp->irq_cnt = rc;
8245         }
8246
8247         tp->tg3_flags3 |= TG3_FLG3_ENABLE_RSS;
8248
8249         for (i = 0; i < tp->irq_max; i++)
8250                 tp->napi[i].irq_vec = msix_ent[i].vector;
8251
8252         tp->dev->real_num_tx_queues = tp->irq_cnt - 1;
8253
8254         return true;
8255 }
8256
8257 static void tg3_ints_init(struct tg3 *tp)
8258 {
8259         if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI_OR_MSIX) &&
8260             !(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8261                 /* All MSI supporting chips should support tagged
8262                  * status.  Assert that this is the case.
8263                  */
8264                 printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
8265                        "Not using MSI.\n", tp->dev->name);
8266                 goto defcfg;
8267         }
8268
8269         if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) && tg3_enable_msix(tp))
8270                 tp->tg3_flags2 |= TG3_FLG2_USING_MSIX;
8271         else if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) &&
8272                  pci_enable_msi(tp->pdev) == 0)
8273                 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
8274
8275         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8276                 u32 msi_mode = tr32(MSGINT_MODE);
8277                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8278                         msi_mode |= MSGINT_MODE_MULTIVEC_EN;
8279                 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
8280         }
8281 defcfg:
8282         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
8283                 tp->irq_cnt = 1;
8284                 tp->napi[0].irq_vec = tp->pdev->irq;
8285                 tp->dev->real_num_tx_queues = 1;
8286         }
8287 }
8288
8289 static void tg3_ints_fini(struct tg3 *tp)
8290 {
8291         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8292                 pci_disable_msix(tp->pdev);
8293         else if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
8294                 pci_disable_msi(tp->pdev);
8295         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI_OR_MSIX;
8296         tp->tg3_flags3 &= ~TG3_FLG3_ENABLE_RSS;
8297 }
8298
8299 static int tg3_open(struct net_device *dev)
8300 {
8301         struct tg3 *tp = netdev_priv(dev);
8302         int i, err;
8303
8304         if (tp->fw_needed) {
8305                 err = tg3_request_firmware(tp);
8306                 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8307                         if (err)
8308                                 return err;
8309                 } else if (err) {
8310                         printk(KERN_WARNING "%s: TSO capability disabled.\n",
8311                                tp->dev->name);
8312                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
8313                 } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8314                         printk(KERN_NOTICE "%s: TSO capability restored.\n",
8315                                tp->dev->name);
8316                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
8317                 }
8318         }
8319
8320         netif_carrier_off(tp->dev);
8321
8322         err = tg3_set_power_state(tp, PCI_D0);
8323         if (err)
8324                 return err;
8325
8326         tg3_full_lock(tp, 0);
8327
8328         tg3_disable_ints(tp);
8329         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8330
8331         tg3_full_unlock(tp);
8332
8333         /*
8334          * Setup interrupts first so we know how
8335          * many NAPI resources to allocate
8336          */
8337         tg3_ints_init(tp);
8338
8339         /* The placement of this call is tied
8340          * to the setup and use of Host TX descriptors.
8341          */
8342         err = tg3_alloc_consistent(tp);
8343         if (err)
8344                 goto err_out1;
8345
8346         tg3_napi_enable(tp);
8347
8348         for (i = 0; i < tp->irq_cnt; i++) {
8349                 struct tg3_napi *tnapi = &tp->napi[i];
8350                 err = tg3_request_irq(tp, i);
8351                 if (err) {
8352                         for (i--; i >= 0; i--)
8353                                 free_irq(tnapi->irq_vec, tnapi);
8354                         break;
8355                 }
8356         }
8357
8358         if (err)
8359                 goto err_out2;
8360
8361         tg3_full_lock(tp, 0);
8362
8363         err = tg3_init_hw(tp, 1);
8364         if (err) {
8365                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8366                 tg3_free_rings(tp);
8367         } else {
8368                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8369                         tp->timer_offset = HZ;
8370                 else
8371                         tp->timer_offset = HZ / 10;
8372
8373                 BUG_ON(tp->timer_offset > HZ);
8374                 tp->timer_counter = tp->timer_multiplier =
8375                         (HZ / tp->timer_offset);
8376                 tp->asf_counter = tp->asf_multiplier =
8377                         ((HZ / tp->timer_offset) * 2);
8378
8379                 init_timer(&tp->timer);
8380                 tp->timer.expires = jiffies + tp->timer_offset;
8381                 tp->timer.data = (unsigned long) tp;
8382                 tp->timer.function = tg3_timer;
8383         }
8384
8385         tg3_full_unlock(tp);
8386
8387         if (err)
8388                 goto err_out3;
8389
8390         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8391                 err = tg3_test_msi(tp);
8392
8393                 if (err) {
8394                         tg3_full_lock(tp, 0);
8395                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8396                         tg3_free_rings(tp);
8397                         tg3_full_unlock(tp);
8398
8399                         goto err_out2;
8400                 }
8401
8402                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
8403                     (tp->tg3_flags2 & TG3_FLG2_USING_MSI) &&
8404                     (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)) {
8405                         u32 val = tr32(PCIE_TRANSACTION_CFG);
8406
8407                         tw32(PCIE_TRANSACTION_CFG,
8408                              val | PCIE_TRANS_CFG_1SHOT_MSI);
8409                 }
8410         }
8411
8412         tg3_phy_start(tp);
8413
8414         tg3_full_lock(tp, 0);
8415
8416         add_timer(&tp->timer);
8417         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
8418         tg3_enable_ints(tp);
8419
8420         tg3_full_unlock(tp);
8421
8422         netif_tx_start_all_queues(dev);
8423
8424         return 0;
8425
8426 err_out3:
8427         for (i = tp->irq_cnt - 1; i >= 0; i--) {
8428                 struct tg3_napi *tnapi = &tp->napi[i];
8429                 free_irq(tnapi->irq_vec, tnapi);
8430         }
8431
8432 err_out2:
8433         tg3_napi_disable(tp);
8434         tg3_free_consistent(tp);
8435
8436 err_out1:
8437         tg3_ints_fini(tp);
8438         return err;
8439 }
8440
8441 #if 0
8442 /*static*/ void tg3_dump_state(struct tg3 *tp)
8443 {
8444         u32 val32, val32_2, val32_3, val32_4, val32_5;
8445         u16 val16;
8446         int i;
8447         struct tg3_hw_status *sblk = tp->napi[0]->hw_status;
8448
8449         pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
8450         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
8451         printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
8452                val16, val32);
8453
8454         /* MAC block */
8455         printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
8456                tr32(MAC_MODE), tr32(MAC_STATUS));
8457         printk("       MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
8458                tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
8459         printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
8460                tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
8461         printk("       MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
8462                tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
8463
8464         /* Send data initiator control block */
8465         printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
8466                tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
8467         printk("       SNDDATAI_STATSCTRL[%08x]\n",
8468                tr32(SNDDATAI_STATSCTRL));
8469
8470         /* Send data completion control block */
8471         printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
8472
8473         /* Send BD ring selector block */
8474         printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
8475                tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
8476
8477         /* Send BD initiator control block */
8478         printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
8479                tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
8480
8481         /* Send BD completion control block */
8482         printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
8483
8484         /* Receive list placement control block */
8485         printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
8486                tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
8487         printk("       RCVLPC_STATSCTRL[%08x]\n",
8488                tr32(RCVLPC_STATSCTRL));
8489
8490         /* Receive data and receive BD initiator control block */
8491         printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
8492                tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
8493
8494         /* Receive data completion control block */
8495         printk("DEBUG: RCVDCC_MODE[%08x]\n",
8496                tr32(RCVDCC_MODE));
8497
8498         /* Receive BD initiator control block */
8499         printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
8500                tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
8501
8502         /* Receive BD completion control block */
8503         printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
8504                tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
8505
8506         /* Receive list selector control block */
8507         printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
8508                tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
8509
8510         /* Mbuf cluster free block */
8511         printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
8512                tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
8513
8514         /* Host coalescing control block */
8515         printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
8516                tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
8517         printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
8518                tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8519                tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8520         printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
8521                tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8522                tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8523         printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
8524                tr32(HOSTCC_STATS_BLK_NIC_ADDR));
8525         printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
8526                tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
8527
8528         /* Memory arbiter control block */
8529         printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
8530                tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
8531
8532         /* Buffer manager control block */
8533         printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
8534                tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
8535         printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
8536                tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
8537         printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
8538                "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
8539                tr32(BUFMGR_DMA_DESC_POOL_ADDR),
8540                tr32(BUFMGR_DMA_DESC_POOL_SIZE));
8541
8542         /* Read DMA control block */
8543         printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
8544                tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
8545
8546         /* Write DMA control block */
8547         printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
8548                tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
8549
8550         /* DMA completion block */
8551         printk("DEBUG: DMAC_MODE[%08x]\n",
8552                tr32(DMAC_MODE));
8553
8554         /* GRC block */
8555         printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
8556                tr32(GRC_MODE), tr32(GRC_MISC_CFG));
8557         printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
8558                tr32(GRC_LOCAL_CTRL));
8559
8560         /* TG3_BDINFOs */
8561         printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
8562                tr32(RCVDBDI_JUMBO_BD + 0x0),
8563                tr32(RCVDBDI_JUMBO_BD + 0x4),
8564                tr32(RCVDBDI_JUMBO_BD + 0x8),
8565                tr32(RCVDBDI_JUMBO_BD + 0xc));
8566         printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
8567                tr32(RCVDBDI_STD_BD + 0x0),
8568                tr32(RCVDBDI_STD_BD + 0x4),
8569                tr32(RCVDBDI_STD_BD + 0x8),
8570                tr32(RCVDBDI_STD_BD + 0xc));
8571         printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
8572                tr32(RCVDBDI_MINI_BD + 0x0),
8573                tr32(RCVDBDI_MINI_BD + 0x4),
8574                tr32(RCVDBDI_MINI_BD + 0x8),
8575                tr32(RCVDBDI_MINI_BD + 0xc));
8576
8577         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
8578         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
8579         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
8580         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
8581         printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
8582                val32, val32_2, val32_3, val32_4);
8583
8584         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
8585         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
8586         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
8587         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
8588         printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
8589                val32, val32_2, val32_3, val32_4);
8590
8591         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
8592         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
8593         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
8594         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
8595         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
8596         printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
8597                val32, val32_2, val32_3, val32_4, val32_5);
8598
8599         /* SW status block */
8600         printk(KERN_DEBUG
8601          "Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
8602                sblk->status,
8603                sblk->status_tag,
8604                sblk->rx_jumbo_consumer,
8605                sblk->rx_consumer,
8606                sblk->rx_mini_consumer,
8607                sblk->idx[0].rx_producer,
8608                sblk->idx[0].tx_consumer);
8609
8610         /* SW statistics block */
8611         printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
8612                ((u32 *)tp->hw_stats)[0],
8613                ((u32 *)tp->hw_stats)[1],
8614                ((u32 *)tp->hw_stats)[2],
8615                ((u32 *)tp->hw_stats)[3]);
8616
8617         /* Mailboxes */
8618         printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
8619                tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
8620                tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
8621                tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
8622                tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
8623
8624         /* NIC side send descriptors. */
8625         for (i = 0; i < 6; i++) {
8626                 unsigned long txd;
8627
8628                 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
8629                         + (i * sizeof(struct tg3_tx_buffer_desc));
8630                 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
8631                        i,
8632                        readl(txd + 0x0), readl(txd + 0x4),
8633                        readl(txd + 0x8), readl(txd + 0xc));
8634         }
8635
8636         /* NIC side RX descriptors. */
8637         for (i = 0; i < 6; i++) {
8638                 unsigned long rxd;
8639
8640                 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
8641                         + (i * sizeof(struct tg3_rx_buffer_desc));
8642                 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
8643                        i,
8644                        readl(rxd + 0x0), readl(rxd + 0x4),
8645                        readl(rxd + 0x8), readl(rxd + 0xc));
8646                 rxd += (4 * sizeof(u32));
8647                 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
8648                        i,
8649                        readl(rxd + 0x0), readl(rxd + 0x4),
8650                        readl(rxd + 0x8), readl(rxd + 0xc));
8651         }
8652
8653         for (i = 0; i < 6; i++) {
8654                 unsigned long rxd;
8655
8656                 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
8657                         + (i * sizeof(struct tg3_rx_buffer_desc));
8658                 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
8659                        i,
8660                        readl(rxd + 0x0), readl(rxd + 0x4),
8661                        readl(rxd + 0x8), readl(rxd + 0xc));
8662                 rxd += (4 * sizeof(u32));
8663                 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
8664                        i,
8665                        readl(rxd + 0x0), readl(rxd + 0x4),
8666                        readl(rxd + 0x8), readl(rxd + 0xc));
8667         }
8668 }
8669 #endif
8670
8671 static struct net_device_stats *tg3_get_stats(struct net_device *);
8672 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
8673
8674 static int tg3_close(struct net_device *dev)
8675 {
8676         int i;
8677         struct tg3 *tp = netdev_priv(dev);
8678
8679         tg3_napi_disable(tp);
8680         cancel_work_sync(&tp->reset_task);
8681
8682         netif_tx_stop_all_queues(dev);
8683
8684         del_timer_sync(&tp->timer);
8685
8686         tg3_phy_stop(tp);
8687
8688         tg3_full_lock(tp, 1);
8689 #if 0
8690         tg3_dump_state(tp);
8691 #endif
8692
8693         tg3_disable_ints(tp);
8694
8695         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8696         tg3_free_rings(tp);
8697         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8698
8699         tg3_full_unlock(tp);
8700
8701         for (i = tp->irq_cnt - 1; i >= 0; i--) {
8702                 struct tg3_napi *tnapi = &tp->napi[i];
8703                 free_irq(tnapi->irq_vec, tnapi);
8704         }
8705
8706         tg3_ints_fini(tp);
8707
8708         memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
8709                sizeof(tp->net_stats_prev));
8710         memcpy(&tp->estats_prev, tg3_get_estats(tp),
8711                sizeof(tp->estats_prev));
8712
8713         tg3_free_consistent(tp);
8714
8715         tg3_set_power_state(tp, PCI_D3hot);
8716
8717         netif_carrier_off(tp->dev);
8718
8719         return 0;
8720 }
8721
8722 static inline unsigned long get_stat64(tg3_stat64_t *val)
8723 {
8724         unsigned long ret;
8725
8726 #if (BITS_PER_LONG == 32)
8727         ret = val->low;
8728 #else
8729         ret = ((u64)val->high << 32) | ((u64)val->low);
8730 #endif
8731         return ret;
8732 }
8733
8734 static inline u64 get_estat64(tg3_stat64_t *val)
8735 {
8736        return ((u64)val->high << 32) | ((u64)val->low);
8737 }
8738
8739 static unsigned long calc_crc_errors(struct tg3 *tp)
8740 {
8741         struct tg3_hw_stats *hw_stats = tp->hw_stats;
8742
8743         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8744             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
8745              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
8746                 u32 val;
8747
8748                 spin_lock_bh(&tp->lock);
8749                 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
8750                         tg3_writephy(tp, MII_TG3_TEST1,
8751                                      val | MII_TG3_TEST1_CRC_EN);
8752                         tg3_readphy(tp, 0x14, &val);
8753                 } else
8754                         val = 0;
8755                 spin_unlock_bh(&tp->lock);
8756
8757                 tp->phy_crc_errors += val;
8758
8759                 return tp->phy_crc_errors;
8760         }
8761
8762         return get_stat64(&hw_stats->rx_fcs_errors);
8763 }
8764
8765 #define ESTAT_ADD(member) \
8766         estats->member =        old_estats->member + \
8767                                 get_estat64(&hw_stats->member)
8768
8769 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
8770 {
8771         struct tg3_ethtool_stats *estats = &tp->estats;
8772         struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
8773         struct tg3_hw_stats *hw_stats = tp->hw_stats;
8774
8775         if (!hw_stats)
8776                 return old_estats;
8777
8778         ESTAT_ADD(rx_octets);
8779         ESTAT_ADD(rx_fragments);
8780         ESTAT_ADD(rx_ucast_packets);
8781         ESTAT_ADD(rx_mcast_packets);
8782         ESTAT_ADD(rx_bcast_packets);
8783         ESTAT_ADD(rx_fcs_errors);
8784         ESTAT_ADD(rx_align_errors);
8785         ESTAT_ADD(rx_xon_pause_rcvd);
8786         ESTAT_ADD(rx_xoff_pause_rcvd);
8787         ESTAT_ADD(rx_mac_ctrl_rcvd);
8788         ESTAT_ADD(rx_xoff_entered);
8789         ESTAT_ADD(rx_frame_too_long_errors);
8790         ESTAT_ADD(rx_jabbers);
8791         ESTAT_ADD(rx_undersize_packets);
8792         ESTAT_ADD(rx_in_length_errors);
8793         ESTAT_ADD(rx_out_length_errors);
8794         ESTAT_ADD(rx_64_or_less_octet_packets);
8795         ESTAT_ADD(rx_65_to_127_octet_packets);
8796         ESTAT_ADD(rx_128_to_255_octet_packets);
8797         ESTAT_ADD(rx_256_to_511_octet_packets);
8798         ESTAT_ADD(rx_512_to_1023_octet_packets);
8799         ESTAT_ADD(rx_1024_to_1522_octet_packets);
8800         ESTAT_ADD(rx_1523_to_2047_octet_packets);
8801         ESTAT_ADD(rx_2048_to_4095_octet_packets);
8802         ESTAT_ADD(rx_4096_to_8191_octet_packets);
8803         ESTAT_ADD(rx_8192_to_9022_octet_packets);
8804
8805         ESTAT_ADD(tx_octets);
8806         ESTAT_ADD(tx_collisions);
8807         ESTAT_ADD(tx_xon_sent);
8808         ESTAT_ADD(tx_xoff_sent);
8809         ESTAT_ADD(tx_flow_control);
8810         ESTAT_ADD(tx_mac_errors);
8811         ESTAT_ADD(tx_single_collisions);
8812         ESTAT_ADD(tx_mult_collisions);
8813         ESTAT_ADD(tx_deferred);
8814         ESTAT_ADD(tx_excessive_collisions);
8815         ESTAT_ADD(tx_late_collisions);
8816         ESTAT_ADD(tx_collide_2times);
8817         ESTAT_ADD(tx_collide_3times);
8818         ESTAT_ADD(tx_collide_4times);
8819         ESTAT_ADD(tx_collide_5times);
8820         ESTAT_ADD(tx_collide_6times);
8821         ESTAT_ADD(tx_collide_7times);
8822         ESTAT_ADD(tx_collide_8times);
8823         ESTAT_ADD(tx_collide_9times);
8824         ESTAT_ADD(tx_collide_10times);
8825         ESTAT_ADD(tx_collide_11times);
8826         ESTAT_ADD(tx_collide_12times);
8827         ESTAT_ADD(tx_collide_13times);
8828         ESTAT_ADD(tx_collide_14times);
8829         ESTAT_ADD(tx_collide_15times);
8830         ESTAT_ADD(tx_ucast_packets);
8831         ESTAT_ADD(tx_mcast_packets);
8832         ESTAT_ADD(tx_bcast_packets);
8833         ESTAT_ADD(tx_carrier_sense_errors);
8834         ESTAT_ADD(tx_discards);
8835         ESTAT_ADD(tx_errors);
8836
8837         ESTAT_ADD(dma_writeq_full);
8838         ESTAT_ADD(dma_write_prioq_full);
8839         ESTAT_ADD(rxbds_empty);
8840         ESTAT_ADD(rx_discards);
8841         ESTAT_ADD(rx_errors);
8842         ESTAT_ADD(rx_threshold_hit);
8843
8844         ESTAT_ADD(dma_readq_full);
8845         ESTAT_ADD(dma_read_prioq_full);
8846         ESTAT_ADD(tx_comp_queue_full);
8847
8848         ESTAT_ADD(ring_set_send_prod_index);
8849         ESTAT_ADD(ring_status_update);
8850         ESTAT_ADD(nic_irqs);
8851         ESTAT_ADD(nic_avoided_irqs);
8852         ESTAT_ADD(nic_tx_threshold_hit);
8853
8854         return estats;
8855 }
8856
8857 static struct net_device_stats *tg3_get_stats(struct net_device *dev)
8858 {
8859         struct tg3 *tp = netdev_priv(dev);
8860         struct net_device_stats *stats = &tp->net_stats;
8861         struct net_device_stats *old_stats = &tp->net_stats_prev;
8862         struct tg3_hw_stats *hw_stats = tp->hw_stats;
8863
8864         if (!hw_stats)
8865                 return old_stats;
8866
8867         stats->rx_packets = old_stats->rx_packets +
8868                 get_stat64(&hw_stats->rx_ucast_packets) +
8869                 get_stat64(&hw_stats->rx_mcast_packets) +
8870                 get_stat64(&hw_stats->rx_bcast_packets);
8871
8872         stats->tx_packets = old_stats->tx_packets +
8873                 get_stat64(&hw_stats->tx_ucast_packets) +
8874                 get_stat64(&hw_stats->tx_mcast_packets) +
8875                 get_stat64(&hw_stats->tx_bcast_packets);
8876
8877         stats->rx_bytes = old_stats->rx_bytes +
8878                 get_stat64(&hw_stats->rx_octets);
8879         stats->tx_bytes = old_stats->tx_bytes +
8880                 get_stat64(&hw_stats->tx_octets);
8881
8882         stats->rx_errors = old_stats->rx_errors +
8883                 get_stat64(&hw_stats->rx_errors);
8884         stats->tx_errors = old_stats->tx_errors +
8885                 get_stat64(&hw_stats->tx_errors) +
8886                 get_stat64(&hw_stats->tx_mac_errors) +
8887                 get_stat64(&hw_stats->tx_carrier_sense_errors) +
8888                 get_stat64(&hw_stats->tx_discards);
8889
8890         stats->multicast = old_stats->multicast +
8891                 get_stat64(&hw_stats->rx_mcast_packets);
8892         stats->collisions = old_stats->collisions +
8893                 get_stat64(&hw_stats->tx_collisions);
8894
8895         stats->rx_length_errors = old_stats->rx_length_errors +
8896                 get_stat64(&hw_stats->rx_frame_too_long_errors) +
8897                 get_stat64(&hw_stats->rx_undersize_packets);
8898
8899         stats->rx_over_errors = old_stats->rx_over_errors +
8900                 get_stat64(&hw_stats->rxbds_empty);
8901         stats->rx_frame_errors = old_stats->rx_frame_errors +
8902                 get_stat64(&hw_stats->rx_align_errors);
8903         stats->tx_aborted_errors = old_stats->tx_aborted_errors +
8904                 get_stat64(&hw_stats->tx_discards);
8905         stats->tx_carrier_errors = old_stats->tx_carrier_errors +
8906                 get_stat64(&hw_stats->tx_carrier_sense_errors);
8907
8908         stats->rx_crc_errors = old_stats->rx_crc_errors +
8909                 calc_crc_errors(tp);
8910
8911         stats->rx_missed_errors = old_stats->rx_missed_errors +
8912                 get_stat64(&hw_stats->rx_discards);
8913
8914         return stats;
8915 }
8916
8917 static inline u32 calc_crc(unsigned char *buf, int len)
8918 {
8919         u32 reg;
8920         u32 tmp;
8921         int j, k;
8922
8923         reg = 0xffffffff;
8924
8925         for (j = 0; j < len; j++) {
8926                 reg ^= buf[j];
8927
8928                 for (k = 0; k < 8; k++) {
8929                         tmp = reg & 0x01;
8930
8931                         reg >>= 1;
8932
8933                         if (tmp) {
8934                                 reg ^= 0xedb88320;
8935                         }
8936                 }
8937         }
8938
8939         return ~reg;
8940 }
8941
8942 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
8943 {
8944         /* accept or reject all multicast frames */
8945         tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
8946         tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
8947         tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
8948         tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
8949 }
8950
8951 static void __tg3_set_rx_mode(struct net_device *dev)
8952 {
8953         struct tg3 *tp = netdev_priv(dev);
8954         u32 rx_mode;
8955
8956         rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
8957                                   RX_MODE_KEEP_VLAN_TAG);
8958
8959         /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
8960          * flag clear.
8961          */
8962 #if TG3_VLAN_TAG_USED
8963         if (!tp->vlgrp &&
8964             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
8965                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
8966 #else
8967         /* By definition, VLAN is disabled always in this
8968          * case.
8969          */
8970         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
8971                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
8972 #endif
8973
8974         if (dev->flags & IFF_PROMISC) {
8975                 /* Promiscuous mode. */
8976                 rx_mode |= RX_MODE_PROMISC;
8977         } else if (dev->flags & IFF_ALLMULTI) {
8978                 /* Accept all multicast. */
8979                 tg3_set_multi (tp, 1);
8980         } else if (dev->mc_count < 1) {
8981                 /* Reject all multicast. */
8982                 tg3_set_multi (tp, 0);
8983         } else {
8984                 /* Accept one or more multicast(s). */
8985                 struct dev_mc_list *mclist;
8986                 unsigned int i;
8987                 u32 mc_filter[4] = { 0, };
8988                 u32 regidx;
8989                 u32 bit;
8990                 u32 crc;
8991
8992                 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
8993                      i++, mclist = mclist->next) {
8994
8995                         crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
8996                         bit = ~crc & 0x7f;
8997                         regidx = (bit & 0x60) >> 5;
8998                         bit &= 0x1f;
8999                         mc_filter[regidx] |= (1 << bit);
9000                 }
9001
9002                 tw32(MAC_HASH_REG_0, mc_filter[0]);
9003                 tw32(MAC_HASH_REG_1, mc_filter[1]);
9004                 tw32(MAC_HASH_REG_2, mc_filter[2]);
9005                 tw32(MAC_HASH_REG_3, mc_filter[3]);
9006         }
9007
9008         if (rx_mode != tp->rx_mode) {
9009                 tp->rx_mode = rx_mode;
9010                 tw32_f(MAC_RX_MODE, rx_mode);
9011                 udelay(10);
9012         }
9013 }
9014
9015 static void tg3_set_rx_mode(struct net_device *dev)
9016 {
9017         struct tg3 *tp = netdev_priv(dev);
9018
9019         if (!netif_running(dev))
9020                 return;
9021
9022         tg3_full_lock(tp, 0);
9023         __tg3_set_rx_mode(dev);
9024         tg3_full_unlock(tp);
9025 }
9026
9027 #define TG3_REGDUMP_LEN         (32 * 1024)
9028
9029 static int tg3_get_regs_len(struct net_device *dev)
9030 {
9031         return TG3_REGDUMP_LEN;
9032 }
9033
9034 static void tg3_get_regs(struct net_device *dev,
9035                 struct ethtool_regs *regs, void *_p)
9036 {
9037         u32 *p = _p;
9038         struct tg3 *tp = netdev_priv(dev);
9039         u8 *orig_p = _p;
9040         int i;
9041
9042         regs->version = 0;
9043
9044         memset(p, 0, TG3_REGDUMP_LEN);
9045
9046         if (tp->link_config.phy_is_low_power)
9047                 return;
9048
9049         tg3_full_lock(tp, 0);
9050
9051 #define __GET_REG32(reg)        (*(p)++ = tr32(reg))
9052 #define GET_REG32_LOOP(base,len)                \
9053 do {    p = (u32 *)(orig_p + (base));           \
9054         for (i = 0; i < len; i += 4)            \
9055                 __GET_REG32((base) + i);        \
9056 } while (0)
9057 #define GET_REG32_1(reg)                        \
9058 do {    p = (u32 *)(orig_p + (reg));            \
9059         __GET_REG32((reg));                     \
9060 } while (0)
9061
9062         GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
9063         GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
9064         GET_REG32_LOOP(MAC_MODE, 0x4f0);
9065         GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
9066         GET_REG32_1(SNDDATAC_MODE);
9067         GET_REG32_LOOP(SNDBDS_MODE, 0x80);
9068         GET_REG32_LOOP(SNDBDI_MODE, 0x48);
9069         GET_REG32_1(SNDBDC_MODE);
9070         GET_REG32_LOOP(RCVLPC_MODE, 0x20);
9071         GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
9072         GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
9073         GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
9074         GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
9075         GET_REG32_1(RCVDCC_MODE);
9076         GET_REG32_LOOP(RCVBDI_MODE, 0x20);
9077         GET_REG32_LOOP(RCVCC_MODE, 0x14);
9078         GET_REG32_LOOP(RCVLSC_MODE, 0x08);
9079         GET_REG32_1(MBFREE_MODE);
9080         GET_REG32_LOOP(HOSTCC_MODE, 0x100);
9081         GET_REG32_LOOP(MEMARB_MODE, 0x10);
9082         GET_REG32_LOOP(BUFMGR_MODE, 0x58);
9083         GET_REG32_LOOP(RDMAC_MODE, 0x08);
9084         GET_REG32_LOOP(WDMAC_MODE, 0x08);
9085         GET_REG32_1(RX_CPU_MODE);
9086         GET_REG32_1(RX_CPU_STATE);
9087         GET_REG32_1(RX_CPU_PGMCTR);
9088         GET_REG32_1(RX_CPU_HWBKPT);
9089         GET_REG32_1(TX_CPU_MODE);
9090         GET_REG32_1(TX_CPU_STATE);
9091         GET_REG32_1(TX_CPU_PGMCTR);
9092         GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
9093         GET_REG32_LOOP(FTQ_RESET, 0x120);
9094         GET_REG32_LOOP(MSGINT_MODE, 0x0c);
9095         GET_REG32_1(DMAC_MODE);
9096         GET_REG32_LOOP(GRC_MODE, 0x4c);
9097         if (tp->tg3_flags & TG3_FLAG_NVRAM)
9098                 GET_REG32_LOOP(NVRAM_CMD, 0x24);
9099
9100 #undef __GET_REG32
9101 #undef GET_REG32_LOOP
9102 #undef GET_REG32_1
9103
9104         tg3_full_unlock(tp);
9105 }
9106
9107 static int tg3_get_eeprom_len(struct net_device *dev)
9108 {
9109         struct tg3 *tp = netdev_priv(dev);
9110
9111         return tp->nvram_size;
9112 }
9113
9114 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9115 {
9116         struct tg3 *tp = netdev_priv(dev);
9117         int ret;
9118         u8  *pd;
9119         u32 i, offset, len, b_offset, b_count;
9120         __be32 val;
9121
9122         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9123                 return -EINVAL;
9124
9125         if (tp->link_config.phy_is_low_power)
9126                 return -EAGAIN;
9127
9128         offset = eeprom->offset;
9129         len = eeprom->len;
9130         eeprom->len = 0;
9131
9132         eeprom->magic = TG3_EEPROM_MAGIC;
9133
9134         if (offset & 3) {
9135                 /* adjustments to start on required 4 byte boundary */
9136                 b_offset = offset & 3;
9137                 b_count = 4 - b_offset;
9138                 if (b_count > len) {
9139                         /* i.e. offset=1 len=2 */
9140                         b_count = len;
9141                 }
9142                 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
9143                 if (ret)
9144                         return ret;
9145                 memcpy(data, ((char*)&val) + b_offset, b_count);
9146                 len -= b_count;
9147                 offset += b_count;
9148                 eeprom->len += b_count;
9149         }
9150
9151         /* read bytes upto the last 4 byte boundary */
9152         pd = &data[eeprom->len];
9153         for (i = 0; i < (len - (len & 3)); i += 4) {
9154                 ret = tg3_nvram_read_be32(tp, offset + i, &val);
9155                 if (ret) {
9156                         eeprom->len += i;
9157                         return ret;
9158                 }
9159                 memcpy(pd + i, &val, 4);
9160         }
9161         eeprom->len += i;
9162
9163         if (len & 3) {
9164                 /* read last bytes not ending on 4 byte boundary */
9165                 pd = &data[eeprom->len];
9166                 b_count = len & 3;
9167                 b_offset = offset + len - b_count;
9168                 ret = tg3_nvram_read_be32(tp, b_offset, &val);
9169                 if (ret)
9170                         return ret;
9171                 memcpy(pd, &val, b_count);
9172                 eeprom->len += b_count;
9173         }
9174         return 0;
9175 }
9176
9177 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
9178
9179 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9180 {
9181         struct tg3 *tp = netdev_priv(dev);
9182         int ret;
9183         u32 offset, len, b_offset, odd_len;
9184         u8 *buf;
9185         __be32 start, end;
9186
9187         if (tp->link_config.phy_is_low_power)
9188                 return -EAGAIN;
9189
9190         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
9191             eeprom->magic != TG3_EEPROM_MAGIC)
9192                 return -EINVAL;
9193
9194         offset = eeprom->offset;
9195         len = eeprom->len;
9196
9197         if ((b_offset = (offset & 3))) {
9198                 /* adjustments to start on required 4 byte boundary */
9199                 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
9200                 if (ret)
9201                         return ret;
9202                 len += b_offset;
9203                 offset &= ~3;
9204                 if (len < 4)
9205                         len = 4;
9206         }
9207
9208         odd_len = 0;
9209         if (len & 3) {
9210                 /* adjustments to end on required 4 byte boundary */
9211                 odd_len = 1;
9212                 len = (len + 3) & ~3;
9213                 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
9214                 if (ret)
9215                         return ret;
9216         }
9217
9218         buf = data;
9219         if (b_offset || odd_len) {
9220                 buf = kmalloc(len, GFP_KERNEL);
9221                 if (!buf)
9222                         return -ENOMEM;
9223                 if (b_offset)
9224                         memcpy(buf, &start, 4);
9225                 if (odd_len)
9226                         memcpy(buf+len-4, &end, 4);
9227                 memcpy(buf + b_offset, data, eeprom->len);
9228         }
9229
9230         ret = tg3_nvram_write_block(tp, offset, len, buf);
9231
9232         if (buf != data)
9233                 kfree(buf);
9234
9235         return ret;
9236 }
9237
9238 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9239 {
9240         struct tg3 *tp = netdev_priv(dev);
9241
9242         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9243                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9244                         return -EAGAIN;
9245                 return phy_ethtool_gset(tp->mdio_bus->phy_map[PHY_ADDR], cmd);
9246         }
9247
9248         cmd->supported = (SUPPORTED_Autoneg);
9249
9250         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
9251                 cmd->supported |= (SUPPORTED_1000baseT_Half |
9252                                    SUPPORTED_1000baseT_Full);
9253
9254         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
9255                 cmd->supported |= (SUPPORTED_100baseT_Half |
9256                                   SUPPORTED_100baseT_Full |
9257                                   SUPPORTED_10baseT_Half |
9258                                   SUPPORTED_10baseT_Full |
9259                                   SUPPORTED_TP);
9260                 cmd->port = PORT_TP;
9261         } else {
9262                 cmd->supported |= SUPPORTED_FIBRE;
9263                 cmd->port = PORT_FIBRE;
9264         }
9265
9266         cmd->advertising = tp->link_config.advertising;
9267         if (netif_running(dev)) {
9268                 cmd->speed = tp->link_config.active_speed;
9269                 cmd->duplex = tp->link_config.active_duplex;
9270         }
9271         cmd->phy_address = tp->phy_addr;
9272         cmd->transceiver = XCVR_INTERNAL;
9273         cmd->autoneg = tp->link_config.autoneg;
9274         cmd->maxtxpkt = 0;
9275         cmd->maxrxpkt = 0;
9276         return 0;
9277 }
9278
9279 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9280 {
9281         struct tg3 *tp = netdev_priv(dev);
9282
9283         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9284                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9285                         return -EAGAIN;
9286                 return phy_ethtool_sset(tp->mdio_bus->phy_map[PHY_ADDR], cmd);
9287         }
9288
9289         if (cmd->autoneg != AUTONEG_ENABLE &&
9290             cmd->autoneg != AUTONEG_DISABLE)
9291                 return -EINVAL;
9292
9293         if (cmd->autoneg == AUTONEG_DISABLE &&
9294             cmd->duplex != DUPLEX_FULL &&
9295             cmd->duplex != DUPLEX_HALF)
9296                 return -EINVAL;
9297
9298         if (cmd->autoneg == AUTONEG_ENABLE) {
9299                 u32 mask = ADVERTISED_Autoneg |
9300                            ADVERTISED_Pause |
9301                            ADVERTISED_Asym_Pause;
9302
9303                 if (!(tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
9304                         mask |= ADVERTISED_1000baseT_Half |
9305                                 ADVERTISED_1000baseT_Full;
9306
9307                 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
9308                         mask |= ADVERTISED_100baseT_Half |
9309                                 ADVERTISED_100baseT_Full |
9310                                 ADVERTISED_10baseT_Half |
9311                                 ADVERTISED_10baseT_Full |
9312                                 ADVERTISED_TP;
9313                 else
9314                         mask |= ADVERTISED_FIBRE;
9315
9316                 if (cmd->advertising & ~mask)
9317                         return -EINVAL;
9318
9319                 mask &= (ADVERTISED_1000baseT_Half |
9320                          ADVERTISED_1000baseT_Full |
9321                          ADVERTISED_100baseT_Half |
9322                          ADVERTISED_100baseT_Full |
9323                          ADVERTISED_10baseT_Half |
9324                          ADVERTISED_10baseT_Full);
9325
9326                 cmd->advertising &= mask;
9327         } else {
9328                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
9329                         if (cmd->speed != SPEED_1000)
9330                                 return -EINVAL;
9331
9332                         if (cmd->duplex != DUPLEX_FULL)
9333                                 return -EINVAL;
9334                 } else {
9335                         if (cmd->speed != SPEED_100 &&
9336                             cmd->speed != SPEED_10)
9337                                 return -EINVAL;
9338                 }
9339         }
9340
9341         tg3_full_lock(tp, 0);
9342
9343         tp->link_config.autoneg = cmd->autoneg;
9344         if (cmd->autoneg == AUTONEG_ENABLE) {
9345                 tp->link_config.advertising = (cmd->advertising |
9346                                               ADVERTISED_Autoneg);
9347                 tp->link_config.speed = SPEED_INVALID;
9348                 tp->link_config.duplex = DUPLEX_INVALID;
9349         } else {
9350                 tp->link_config.advertising = 0;
9351                 tp->link_config.speed = cmd->speed;
9352                 tp->link_config.duplex = cmd->duplex;
9353         }
9354
9355         tp->link_config.orig_speed = tp->link_config.speed;
9356         tp->link_config.orig_duplex = tp->link_config.duplex;
9357         tp->link_config.orig_autoneg = tp->link_config.autoneg;
9358
9359         if (netif_running(dev))
9360                 tg3_setup_phy(tp, 1);
9361
9362         tg3_full_unlock(tp);
9363
9364         return 0;
9365 }
9366
9367 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
9368 {
9369         struct tg3 *tp = netdev_priv(dev);
9370
9371         strcpy(info->driver, DRV_MODULE_NAME);
9372         strcpy(info->version, DRV_MODULE_VERSION);
9373         strcpy(info->fw_version, tp->fw_ver);
9374         strcpy(info->bus_info, pci_name(tp->pdev));
9375 }
9376
9377 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9378 {
9379         struct tg3 *tp = netdev_priv(dev);
9380
9381         if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
9382             device_can_wakeup(&tp->pdev->dev))
9383                 wol->supported = WAKE_MAGIC;
9384         else
9385                 wol->supported = 0;
9386         wol->wolopts = 0;
9387         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
9388             device_can_wakeup(&tp->pdev->dev))
9389                 wol->wolopts = WAKE_MAGIC;
9390         memset(&wol->sopass, 0, sizeof(wol->sopass));
9391 }
9392
9393 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9394 {
9395         struct tg3 *tp = netdev_priv(dev);
9396         struct device *dp = &tp->pdev->dev;
9397
9398         if (wol->wolopts & ~WAKE_MAGIC)
9399                 return -EINVAL;
9400         if ((wol->wolopts & WAKE_MAGIC) &&
9401             !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
9402                 return -EINVAL;
9403
9404         spin_lock_bh(&tp->lock);
9405         if (wol->wolopts & WAKE_MAGIC) {
9406                 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
9407                 device_set_wakeup_enable(dp, true);
9408         } else {
9409                 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
9410                 device_set_wakeup_enable(dp, false);
9411         }
9412         spin_unlock_bh(&tp->lock);
9413
9414         return 0;
9415 }
9416
9417 static u32 tg3_get_msglevel(struct net_device *dev)
9418 {
9419         struct tg3 *tp = netdev_priv(dev);
9420         return tp->msg_enable;
9421 }
9422
9423 static void tg3_set_msglevel(struct net_device *dev, u32 value)
9424 {
9425         struct tg3 *tp = netdev_priv(dev);
9426         tp->msg_enable = value;
9427 }
9428
9429 static int tg3_set_tso(struct net_device *dev, u32 value)
9430 {
9431         struct tg3 *tp = netdev_priv(dev);
9432
9433         if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
9434                 if (value)
9435                         return -EINVAL;
9436                 return 0;
9437         }
9438         if ((dev->features & NETIF_F_IPV6_CSUM) &&
9439             (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)) {
9440                 if (value) {
9441                         dev->features |= NETIF_F_TSO6;
9442                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9443                             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
9444                              GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
9445                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
9446                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
9447                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
9448                                 dev->features |= NETIF_F_TSO_ECN;
9449                 } else
9450                         dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
9451         }
9452         return ethtool_op_set_tso(dev, value);
9453 }
9454
9455 static int tg3_nway_reset(struct net_device *dev)
9456 {
9457         struct tg3 *tp = netdev_priv(dev);
9458         int r;
9459
9460         if (!netif_running(dev))
9461                 return -EAGAIN;
9462
9463         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9464                 return -EINVAL;
9465
9466         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9467                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9468                         return -EAGAIN;
9469                 r = phy_start_aneg(tp->mdio_bus->phy_map[PHY_ADDR]);
9470         } else {
9471                 u32 bmcr;
9472
9473                 spin_lock_bh(&tp->lock);
9474                 r = -EINVAL;
9475                 tg3_readphy(tp, MII_BMCR, &bmcr);
9476                 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
9477                     ((bmcr & BMCR_ANENABLE) ||
9478                      (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
9479                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
9480                                                    BMCR_ANENABLE);
9481                         r = 0;
9482                 }
9483                 spin_unlock_bh(&tp->lock);
9484         }
9485
9486         return r;
9487 }
9488
9489 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9490 {
9491         struct tg3 *tp = netdev_priv(dev);
9492
9493         ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
9494         ering->rx_mini_max_pending = 0;
9495         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9496                 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
9497         else
9498                 ering->rx_jumbo_max_pending = 0;
9499
9500         ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
9501
9502         ering->rx_pending = tp->rx_pending;
9503         ering->rx_mini_pending = 0;
9504         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9505                 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
9506         else
9507                 ering->rx_jumbo_pending = 0;
9508
9509         ering->tx_pending = tp->napi[0].tx_pending;
9510 }
9511
9512 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9513 {
9514         struct tg3 *tp = netdev_priv(dev);
9515         int i, irq_sync = 0, err = 0;
9516
9517         if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
9518             (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
9519             (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
9520             (ering->tx_pending <= MAX_SKB_FRAGS) ||
9521             ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
9522              (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
9523                 return -EINVAL;
9524
9525         if (netif_running(dev)) {
9526                 tg3_phy_stop(tp);
9527                 tg3_netif_stop(tp);
9528                 irq_sync = 1;
9529         }
9530
9531         tg3_full_lock(tp, irq_sync);
9532
9533         tp->rx_pending = ering->rx_pending;
9534
9535         if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
9536             tp->rx_pending > 63)
9537                 tp->rx_pending = 63;
9538         tp->rx_jumbo_pending = ering->rx_jumbo_pending;
9539
9540         for (i = 0; i < TG3_IRQ_MAX_VECS; i++)
9541                 tp->napi[i].tx_pending = ering->tx_pending;
9542
9543         if (netif_running(dev)) {
9544                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9545                 err = tg3_restart_hw(tp, 1);
9546                 if (!err)
9547                         tg3_netif_start(tp);
9548         }
9549
9550         tg3_full_unlock(tp);
9551
9552         if (irq_sync && !err)
9553                 tg3_phy_start(tp);
9554
9555         return err;
9556 }
9557
9558 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9559 {
9560         struct tg3 *tp = netdev_priv(dev);
9561
9562         epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
9563
9564         if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
9565                 epause->rx_pause = 1;
9566         else
9567                 epause->rx_pause = 0;
9568
9569         if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
9570                 epause->tx_pause = 1;
9571         else
9572                 epause->tx_pause = 0;
9573 }
9574
9575 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9576 {
9577         struct tg3 *tp = netdev_priv(dev);
9578         int err = 0;
9579
9580         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9581                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9582                         return -EAGAIN;
9583
9584                 if (epause->autoneg) {
9585                         u32 newadv;
9586                         struct phy_device *phydev;
9587
9588                         phydev = tp->mdio_bus->phy_map[PHY_ADDR];
9589
9590                         if (epause->rx_pause) {
9591                                 if (epause->tx_pause)
9592                                         newadv = ADVERTISED_Pause;
9593                                 else
9594                                         newadv = ADVERTISED_Pause |
9595                                                  ADVERTISED_Asym_Pause;
9596                         } else if (epause->tx_pause) {
9597                                 newadv = ADVERTISED_Asym_Pause;
9598                         } else
9599                                 newadv = 0;
9600
9601                         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
9602                                 u32 oldadv = phydev->advertising &
9603                                              (ADVERTISED_Pause |
9604                                               ADVERTISED_Asym_Pause);
9605                                 if (oldadv != newadv) {
9606                                         phydev->advertising &=
9607                                                 ~(ADVERTISED_Pause |
9608                                                   ADVERTISED_Asym_Pause);
9609                                         phydev->advertising |= newadv;
9610                                         err = phy_start_aneg(phydev);
9611                                 }
9612                         } else {
9613                                 tp->link_config.advertising &=
9614                                                 ~(ADVERTISED_Pause |
9615                                                   ADVERTISED_Asym_Pause);
9616                                 tp->link_config.advertising |= newadv;
9617                         }
9618                 } else {
9619                         if (epause->rx_pause)
9620                                 tp->link_config.flowctrl |= FLOW_CTRL_RX;
9621                         else
9622                                 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
9623
9624                         if (epause->tx_pause)
9625                                 tp->link_config.flowctrl |= FLOW_CTRL_TX;
9626                         else
9627                                 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
9628
9629                         if (netif_running(dev))
9630                                 tg3_setup_flow_control(tp, 0, 0);
9631                 }
9632         } else {
9633                 int irq_sync = 0;
9634
9635                 if (netif_running(dev)) {
9636                         tg3_netif_stop(tp);
9637                         irq_sync = 1;
9638                 }
9639
9640                 tg3_full_lock(tp, irq_sync);
9641
9642                 if (epause->autoneg)
9643                         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
9644                 else
9645                         tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
9646                 if (epause->rx_pause)
9647                         tp->link_config.flowctrl |= FLOW_CTRL_RX;
9648                 else
9649                         tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
9650                 if (epause->tx_pause)
9651                         tp->link_config.flowctrl |= FLOW_CTRL_TX;
9652                 else
9653                         tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
9654
9655                 if (netif_running(dev)) {
9656                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9657                         err = tg3_restart_hw(tp, 1);
9658                         if (!err)
9659                                 tg3_netif_start(tp);
9660                 }
9661
9662                 tg3_full_unlock(tp);
9663         }
9664
9665         return err;
9666 }
9667
9668 static u32 tg3_get_rx_csum(struct net_device *dev)
9669 {
9670         struct tg3 *tp = netdev_priv(dev);
9671         return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
9672 }
9673
9674 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
9675 {
9676         struct tg3 *tp = netdev_priv(dev);
9677
9678         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9679                 if (data != 0)
9680                         return -EINVAL;
9681                 return 0;
9682         }
9683
9684         spin_lock_bh(&tp->lock);
9685         if (data)
9686                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
9687         else
9688                 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
9689         spin_unlock_bh(&tp->lock);
9690
9691         return 0;
9692 }
9693
9694 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
9695 {
9696         struct tg3 *tp = netdev_priv(dev);
9697
9698         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9699                 if (data != 0)
9700                         return -EINVAL;
9701                 return 0;
9702         }
9703
9704         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
9705                 ethtool_op_set_tx_ipv6_csum(dev, data);
9706         else
9707                 ethtool_op_set_tx_csum(dev, data);
9708
9709         return 0;
9710 }
9711
9712 static int tg3_get_sset_count (struct net_device *dev, int sset)
9713 {
9714         switch (sset) {
9715         case ETH_SS_TEST:
9716                 return TG3_NUM_TEST;
9717         case ETH_SS_STATS:
9718                 return TG3_NUM_STATS;
9719         default:
9720                 return -EOPNOTSUPP;
9721         }
9722 }
9723
9724 static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
9725 {
9726         switch (stringset) {
9727         case ETH_SS_STATS:
9728                 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
9729                 break;
9730         case ETH_SS_TEST:
9731                 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
9732                 break;
9733         default:
9734                 WARN_ON(1);     /* we need a WARN() */
9735                 break;
9736         }
9737 }
9738
9739 static int tg3_phys_id(struct net_device *dev, u32 data)
9740 {
9741         struct tg3 *tp = netdev_priv(dev);
9742         int i;
9743
9744         if (!netif_running(tp->dev))
9745                 return -EAGAIN;
9746
9747         if (data == 0)
9748                 data = UINT_MAX / 2;
9749
9750         for (i = 0; i < (data * 2); i++) {
9751                 if ((i % 2) == 0)
9752                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9753                                            LED_CTRL_1000MBPS_ON |
9754                                            LED_CTRL_100MBPS_ON |
9755                                            LED_CTRL_10MBPS_ON |
9756                                            LED_CTRL_TRAFFIC_OVERRIDE |
9757                                            LED_CTRL_TRAFFIC_BLINK |
9758                                            LED_CTRL_TRAFFIC_LED);
9759
9760                 else
9761                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9762                                            LED_CTRL_TRAFFIC_OVERRIDE);
9763
9764                 if (msleep_interruptible(500))
9765                         break;
9766         }
9767         tw32(MAC_LED_CTRL, tp->led_ctrl);
9768         return 0;
9769 }
9770
9771 static void tg3_get_ethtool_stats (struct net_device *dev,
9772                                    struct ethtool_stats *estats, u64 *tmp_stats)
9773 {
9774         struct tg3 *tp = netdev_priv(dev);
9775         memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
9776 }
9777
9778 #define NVRAM_TEST_SIZE 0x100
9779 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE   0x14
9780 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE   0x18
9781 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE   0x1c
9782 #define NVRAM_SELFBOOT_HW_SIZE 0x20
9783 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
9784
9785 static int tg3_test_nvram(struct tg3 *tp)
9786 {
9787         u32 csum, magic;
9788         __be32 *buf;
9789         int i, j, k, err = 0, size;
9790
9791         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9792                 return 0;
9793
9794         if (tg3_nvram_read(tp, 0, &magic) != 0)
9795                 return -EIO;
9796
9797         if (magic == TG3_EEPROM_MAGIC)
9798                 size = NVRAM_TEST_SIZE;
9799         else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
9800                 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
9801                     TG3_EEPROM_SB_FORMAT_1) {
9802                         switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
9803                         case TG3_EEPROM_SB_REVISION_0:
9804                                 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
9805                                 break;
9806                         case TG3_EEPROM_SB_REVISION_2:
9807                                 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
9808                                 break;
9809                         case TG3_EEPROM_SB_REVISION_3:
9810                                 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
9811                                 break;
9812                         default:
9813                                 return 0;
9814                         }
9815                 } else
9816                         return 0;
9817         } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
9818                 size = NVRAM_SELFBOOT_HW_SIZE;
9819         else
9820                 return -EIO;
9821
9822         buf = kmalloc(size, GFP_KERNEL);
9823         if (buf == NULL)
9824                 return -ENOMEM;
9825
9826         err = -EIO;
9827         for (i = 0, j = 0; i < size; i += 4, j++) {
9828                 err = tg3_nvram_read_be32(tp, i, &buf[j]);
9829                 if (err)
9830                         break;
9831         }
9832         if (i < size)
9833                 goto out;
9834
9835         /* Selfboot format */
9836         magic = be32_to_cpu(buf[0]);
9837         if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
9838             TG3_EEPROM_MAGIC_FW) {
9839                 u8 *buf8 = (u8 *) buf, csum8 = 0;
9840
9841                 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
9842                     TG3_EEPROM_SB_REVISION_2) {
9843                         /* For rev 2, the csum doesn't include the MBA. */
9844                         for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
9845                                 csum8 += buf8[i];
9846                         for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
9847                                 csum8 += buf8[i];
9848                 } else {
9849                         for (i = 0; i < size; i++)
9850                                 csum8 += buf8[i];
9851                 }
9852
9853                 if (csum8 == 0) {
9854                         err = 0;
9855                         goto out;
9856                 }
9857
9858                 err = -EIO;
9859                 goto out;
9860         }
9861
9862         if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
9863             TG3_EEPROM_MAGIC_HW) {
9864                 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
9865                 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
9866                 u8 *buf8 = (u8 *) buf;
9867
9868                 /* Separate the parity bits and the data bytes.  */
9869                 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
9870                         if ((i == 0) || (i == 8)) {
9871                                 int l;
9872                                 u8 msk;
9873
9874                                 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
9875                                         parity[k++] = buf8[i] & msk;
9876                                 i++;
9877                         }
9878                         else if (i == 16) {
9879                                 int l;
9880                                 u8 msk;
9881
9882                                 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
9883                                         parity[k++] = buf8[i] & msk;
9884                                 i++;
9885
9886                                 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
9887                                         parity[k++] = buf8[i] & msk;
9888                                 i++;
9889                         }
9890                         data[j++] = buf8[i];
9891                 }
9892
9893                 err = -EIO;
9894                 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
9895                         u8 hw8 = hweight8(data[i]);
9896
9897                         if ((hw8 & 0x1) && parity[i])
9898                                 goto out;
9899                         else if (!(hw8 & 0x1) && !parity[i])
9900                                 goto out;
9901                 }
9902                 err = 0;
9903                 goto out;
9904         }
9905
9906         /* Bootstrap checksum at offset 0x10 */
9907         csum = calc_crc((unsigned char *) buf, 0x10);
9908         if (csum != be32_to_cpu(buf[0x10/4]))
9909                 goto out;
9910
9911         /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
9912         csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
9913         if (csum != be32_to_cpu(buf[0xfc/4]))
9914                 goto out;
9915
9916         err = 0;
9917
9918 out:
9919         kfree(buf);
9920         return err;
9921 }
9922
9923 #define TG3_SERDES_TIMEOUT_SEC  2
9924 #define TG3_COPPER_TIMEOUT_SEC  6
9925
9926 static int tg3_test_link(struct tg3 *tp)
9927 {
9928         int i, max;
9929
9930         if (!netif_running(tp->dev))
9931                 return -ENODEV;
9932
9933         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
9934                 max = TG3_SERDES_TIMEOUT_SEC;
9935         else
9936                 max = TG3_COPPER_TIMEOUT_SEC;
9937
9938         for (i = 0; i < max; i++) {
9939                 if (netif_carrier_ok(tp->dev))
9940                         return 0;
9941
9942                 if (msleep_interruptible(1000))
9943                         break;
9944         }
9945
9946         return -EIO;
9947 }
9948
9949 /* Only test the commonly used registers */
9950 static int tg3_test_registers(struct tg3 *tp)
9951 {
9952         int i, is_5705, is_5750;
9953         u32 offset, read_mask, write_mask, val, save_val, read_val;
9954         static struct {
9955                 u16 offset;
9956                 u16 flags;
9957 #define TG3_FL_5705     0x1
9958 #define TG3_FL_NOT_5705 0x2
9959 #define TG3_FL_NOT_5788 0x4
9960 #define TG3_FL_NOT_5750 0x8
9961                 u32 read_mask;
9962                 u32 write_mask;
9963         } reg_tbl[] = {
9964                 /* MAC Control Registers */
9965                 { MAC_MODE, TG3_FL_NOT_5705,
9966                         0x00000000, 0x00ef6f8c },
9967                 { MAC_MODE, TG3_FL_5705,
9968                         0x00000000, 0x01ef6b8c },
9969                 { MAC_STATUS, TG3_FL_NOT_5705,
9970                         0x03800107, 0x00000000 },
9971                 { MAC_STATUS, TG3_FL_5705,
9972                         0x03800100, 0x00000000 },
9973                 { MAC_ADDR_0_HIGH, 0x0000,
9974                         0x00000000, 0x0000ffff },
9975                 { MAC_ADDR_0_LOW, 0x0000,
9976                         0x00000000, 0xffffffff },
9977                 { MAC_RX_MTU_SIZE, 0x0000,
9978                         0x00000000, 0x0000ffff },
9979                 { MAC_TX_MODE, 0x0000,
9980                         0x00000000, 0x00000070 },
9981                 { MAC_TX_LENGTHS, 0x0000,
9982                         0x00000000, 0x00003fff },
9983                 { MAC_RX_MODE, TG3_FL_NOT_5705,
9984                         0x00000000, 0x000007fc },
9985                 { MAC_RX_MODE, TG3_FL_5705,
9986                         0x00000000, 0x000007dc },
9987                 { MAC_HASH_REG_0, 0x0000,
9988                         0x00000000, 0xffffffff },
9989                 { MAC_HASH_REG_1, 0x0000,
9990                         0x00000000, 0xffffffff },
9991                 { MAC_HASH_REG_2, 0x0000,
9992                         0x00000000, 0xffffffff },
9993                 { MAC_HASH_REG_3, 0x0000,
9994                         0x00000000, 0xffffffff },
9995
9996                 /* Receive Data and Receive BD Initiator Control Registers. */
9997                 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
9998                         0x00000000, 0xffffffff },
9999                 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
10000                         0x00000000, 0xffffffff },
10001                 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
10002                         0x00000000, 0x00000003 },
10003                 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
10004                         0x00000000, 0xffffffff },
10005                 { RCVDBDI_STD_BD+0, 0x0000,
10006                         0x00000000, 0xffffffff },
10007                 { RCVDBDI_STD_BD+4, 0x0000,
10008                         0x00000000, 0xffffffff },
10009                 { RCVDBDI_STD_BD+8, 0x0000,
10010                         0x00000000, 0xffff0002 },
10011                 { RCVDBDI_STD_BD+0xc, 0x0000,
10012                         0x00000000, 0xffffffff },
10013
10014                 /* Receive BD Initiator Control Registers. */
10015                 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
10016                         0x00000000, 0xffffffff },
10017                 { RCVBDI_STD_THRESH, TG3_FL_5705,
10018                         0x00000000, 0x000003ff },
10019                 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
10020                         0x00000000, 0xffffffff },
10021
10022                 /* Host Coalescing Control Registers. */
10023                 { HOSTCC_MODE, TG3_FL_NOT_5705,
10024                         0x00000000, 0x00000004 },
10025                 { HOSTCC_MODE, TG3_FL_5705,
10026                         0x00000000, 0x000000f6 },
10027                 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
10028                         0x00000000, 0xffffffff },
10029                 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
10030                         0x00000000, 0x000003ff },
10031                 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
10032                         0x00000000, 0xffffffff },
10033                 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
10034                         0x00000000, 0x000003ff },
10035                 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
10036                         0x00000000, 0xffffffff },
10037                 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10038                         0x00000000, 0x000000ff },
10039                 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
10040                         0x00000000, 0xffffffff },
10041                 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10042                         0x00000000, 0x000000ff },
10043                 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
10044                         0x00000000, 0xffffffff },
10045                 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
10046                         0x00000000, 0xffffffff },
10047                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10048                         0x00000000, 0xffffffff },
10049                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10050                         0x00000000, 0x000000ff },
10051                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10052                         0x00000000, 0xffffffff },
10053                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10054                         0x00000000, 0x000000ff },
10055                 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
10056                         0x00000000, 0xffffffff },
10057                 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
10058                         0x00000000, 0xffffffff },
10059                 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
10060                         0x00000000, 0xffffffff },
10061                 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
10062                         0x00000000, 0xffffffff },
10063                 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
10064                         0x00000000, 0xffffffff },
10065                 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
10066                         0xffffffff, 0x00000000 },
10067                 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
10068                         0xffffffff, 0x00000000 },
10069
10070                 /* Buffer Manager Control Registers. */
10071                 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
10072                         0x00000000, 0x007fff80 },
10073                 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
10074                         0x00000000, 0x007fffff },
10075                 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
10076                         0x00000000, 0x0000003f },
10077                 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
10078                         0x00000000, 0x000001ff },
10079                 { BUFMGR_MB_HIGH_WATER, 0x0000,
10080                         0x00000000, 0x000001ff },
10081                 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
10082                         0xffffffff, 0x00000000 },
10083                 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
10084                         0xffffffff, 0x00000000 },
10085
10086                 /* Mailbox Registers */
10087                 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
10088                         0x00000000, 0x000001ff },
10089                 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
10090                         0x00000000, 0x000001ff },
10091                 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
10092                         0x00000000, 0x000007ff },
10093                 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
10094                         0x00000000, 0x000001ff },
10095
10096                 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
10097         };
10098
10099         is_5705 = is_5750 = 0;
10100         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10101                 is_5705 = 1;
10102                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10103                         is_5750 = 1;
10104         }
10105
10106         for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
10107                 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
10108                         continue;
10109
10110                 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
10111                         continue;
10112
10113                 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10114                     (reg_tbl[i].flags & TG3_FL_NOT_5788))
10115                         continue;
10116
10117                 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
10118                         continue;
10119
10120                 offset = (u32) reg_tbl[i].offset;
10121                 read_mask = reg_tbl[i].read_mask;
10122                 write_mask = reg_tbl[i].write_mask;
10123
10124                 /* Save the original register content */
10125                 save_val = tr32(offset);
10126
10127                 /* Determine the read-only value. */
10128                 read_val = save_val & read_mask;
10129
10130                 /* Write zero to the register, then make sure the read-only bits
10131                  * are not changed and the read/write bits are all zeros.
10132                  */
10133                 tw32(offset, 0);
10134
10135                 val = tr32(offset);
10136
10137                 /* Test the read-only and read/write bits. */
10138                 if (((val & read_mask) != read_val) || (val & write_mask))
10139                         goto out;
10140
10141                 /* Write ones to all the bits defined by RdMask and WrMask, then
10142                  * make sure the read-only bits are not changed and the
10143                  * read/write bits are all ones.
10144                  */
10145                 tw32(offset, read_mask | write_mask);
10146
10147                 val = tr32(offset);
10148
10149                 /* Test the read-only bits. */
10150                 if ((val & read_mask) != read_val)
10151                         goto out;
10152
10153                 /* Test the read/write bits. */
10154                 if ((val & write_mask) != write_mask)
10155                         goto out;
10156
10157                 tw32(offset, save_val);
10158         }
10159
10160         return 0;
10161
10162 out:
10163         if (netif_msg_hw(tp))
10164                 printk(KERN_ERR PFX "Register test failed at offset %x\n",
10165                        offset);
10166         tw32(offset, save_val);
10167         return -EIO;
10168 }
10169
10170 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
10171 {
10172         static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
10173         int i;
10174         u32 j;
10175
10176         for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
10177                 for (j = 0; j < len; j += 4) {
10178                         u32 val;
10179
10180                         tg3_write_mem(tp, offset + j, test_pattern[i]);
10181                         tg3_read_mem(tp, offset + j, &val);
10182                         if (val != test_pattern[i])
10183                                 return -EIO;
10184                 }
10185         }
10186         return 0;
10187 }
10188
10189 static int tg3_test_memory(struct tg3 *tp)
10190 {
10191         static struct mem_entry {
10192                 u32 offset;
10193                 u32 len;
10194         } mem_tbl_570x[] = {
10195                 { 0x00000000, 0x00b50},
10196                 { 0x00002000, 0x1c000},
10197                 { 0xffffffff, 0x00000}
10198         }, mem_tbl_5705[] = {
10199                 { 0x00000100, 0x0000c},
10200                 { 0x00000200, 0x00008},
10201                 { 0x00004000, 0x00800},
10202                 { 0x00006000, 0x01000},
10203                 { 0x00008000, 0x02000},
10204                 { 0x00010000, 0x0e000},
10205                 { 0xffffffff, 0x00000}
10206         }, mem_tbl_5755[] = {
10207                 { 0x00000200, 0x00008},
10208                 { 0x00004000, 0x00800},
10209                 { 0x00006000, 0x00800},
10210                 { 0x00008000, 0x02000},
10211                 { 0x00010000, 0x0c000},
10212                 { 0xffffffff, 0x00000}
10213         }, mem_tbl_5906[] = {
10214                 { 0x00000200, 0x00008},
10215                 { 0x00004000, 0x00400},
10216                 { 0x00006000, 0x00400},
10217                 { 0x00008000, 0x01000},
10218                 { 0x00010000, 0x01000},
10219                 { 0xffffffff, 0x00000}
10220         };
10221         struct mem_entry *mem_tbl;
10222         int err = 0;
10223         int i;
10224
10225         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10226                 mem_tbl = mem_tbl_5755;
10227         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10228                 mem_tbl = mem_tbl_5906;
10229         else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
10230                 mem_tbl = mem_tbl_5705;
10231         else
10232                 mem_tbl = mem_tbl_570x;
10233
10234         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
10235                 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
10236                     mem_tbl[i].len)) != 0)
10237                         break;
10238         }
10239
10240         return err;
10241 }
10242
10243 #define TG3_MAC_LOOPBACK        0
10244 #define TG3_PHY_LOOPBACK        1
10245
10246 static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
10247 {
10248         u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
10249         u32 desc_idx, coal_now;
10250         struct sk_buff *skb, *rx_skb;
10251         u8 *tx_data;
10252         dma_addr_t map;
10253         int num_pkts, tx_len, rx_len, i, err;
10254         struct tg3_rx_buffer_desc *desc;
10255         struct tg3_napi *tnapi, *rnapi;
10256         struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
10257
10258         if (tp->irq_cnt > 1) {
10259                 tnapi = &tp->napi[1];
10260                 rnapi = &tp->napi[1];
10261         } else {
10262                 tnapi = &tp->napi[0];
10263                 rnapi = &tp->napi[0];
10264         }
10265         coal_now = tnapi->coal_now | rnapi->coal_now;
10266
10267         if (loopback_mode == TG3_MAC_LOOPBACK) {
10268                 /* HW errata - mac loopback fails in some cases on 5780.
10269                  * Normal traffic and PHY loopback are not affected by
10270                  * errata.
10271                  */
10272                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
10273                         return 0;
10274
10275                 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
10276                            MAC_MODE_PORT_INT_LPBACK;
10277                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10278                         mac_mode |= MAC_MODE_LINK_POLARITY;
10279                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
10280                         mac_mode |= MAC_MODE_PORT_MODE_MII;
10281                 else
10282                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
10283                 tw32(MAC_MODE, mac_mode);
10284         } else if (loopback_mode == TG3_PHY_LOOPBACK) {
10285                 u32 val;
10286
10287                 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10288                         tg3_phy_fet_toggle_apd(tp, false);
10289                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
10290                 } else
10291                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
10292
10293                 tg3_phy_toggle_automdix(tp, 0);
10294
10295                 tg3_writephy(tp, MII_BMCR, val);
10296                 udelay(40);
10297
10298                 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
10299                 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10300                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10301                                 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x1800);
10302                         mac_mode |= MAC_MODE_PORT_MODE_MII;
10303                 } else
10304                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
10305
10306                 /* reset to prevent losing 1st rx packet intermittently */
10307                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
10308                         tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10309                         udelay(10);
10310                         tw32_f(MAC_RX_MODE, tp->rx_mode);
10311                 }
10312                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
10313                         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)
10314                                 mac_mode &= ~MAC_MODE_LINK_POLARITY;
10315                         else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411)
10316                                 mac_mode |= MAC_MODE_LINK_POLARITY;
10317                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
10318                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
10319                 }
10320                 tw32(MAC_MODE, mac_mode);
10321         }
10322         else
10323                 return -EINVAL;
10324
10325         err = -EIO;
10326
10327         tx_len = 1514;
10328         skb = netdev_alloc_skb(tp->dev, tx_len);
10329         if (!skb)
10330                 return -ENOMEM;
10331
10332         tx_data = skb_put(skb, tx_len);
10333         memcpy(tx_data, tp->dev->dev_addr, 6);
10334         memset(tx_data + 6, 0x0, 8);
10335
10336         tw32(MAC_RX_MTU_SIZE, tx_len + 4);
10337
10338         for (i = 14; i < tx_len; i++)
10339                 tx_data[i] = (u8) (i & 0xff);
10340
10341         map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
10342
10343         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10344                rnapi->coal_now);
10345
10346         udelay(10);
10347
10348         rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
10349
10350         num_pkts = 0;
10351
10352         tg3_set_txd(tnapi, tnapi->tx_prod, map, tx_len, 0, 1);
10353
10354         tnapi->tx_prod++;
10355         num_pkts++;
10356
10357         tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
10358         tr32_mailbox(tnapi->prodmbox);
10359
10360         udelay(10);
10361
10362         /* 250 usec to allow enough time on some 10/100 Mbps devices.  */
10363         for (i = 0; i < 25; i++) {
10364                 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10365                        coal_now);
10366
10367                 udelay(10);
10368
10369                 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
10370                 rx_idx = rnapi->hw_status->idx[0].rx_producer;
10371                 if ((tx_idx == tnapi->tx_prod) &&
10372                     (rx_idx == (rx_start_idx + num_pkts)))
10373                         break;
10374         }
10375
10376         pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
10377         dev_kfree_skb(skb);
10378
10379         if (tx_idx != tnapi->tx_prod)
10380                 goto out;
10381
10382         if (rx_idx != rx_start_idx + num_pkts)
10383                 goto out;
10384
10385         desc = &rnapi->rx_rcb[rx_start_idx];
10386         desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
10387         opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
10388         if (opaque_key != RXD_OPAQUE_RING_STD)
10389                 goto out;
10390
10391         if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
10392             (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
10393                 goto out;
10394
10395         rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
10396         if (rx_len != tx_len)
10397                 goto out;
10398
10399         rx_skb = tpr->rx_std_buffers[desc_idx].skb;
10400
10401         map = pci_unmap_addr(&tpr->rx_std_buffers[desc_idx], mapping);
10402         pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
10403
10404         for (i = 14; i < tx_len; i++) {
10405                 if (*(rx_skb->data + i) != (u8) (i & 0xff))
10406                         goto out;
10407         }
10408         err = 0;
10409
10410         /* tg3_free_rings will unmap and free the rx_skb */
10411 out:
10412         return err;
10413 }
10414
10415 #define TG3_MAC_LOOPBACK_FAILED         1
10416 #define TG3_PHY_LOOPBACK_FAILED         2
10417 #define TG3_LOOPBACK_FAILED             (TG3_MAC_LOOPBACK_FAILED |      \
10418                                          TG3_PHY_LOOPBACK_FAILED)
10419
10420 static int tg3_test_loopback(struct tg3 *tp)
10421 {
10422         int err = 0;
10423         u32 cpmuctrl = 0;
10424
10425         if (!netif_running(tp->dev))
10426                 return TG3_LOOPBACK_FAILED;
10427
10428         err = tg3_reset_hw(tp, 1);
10429         if (err)
10430                 return TG3_LOOPBACK_FAILED;
10431
10432         /* Turn off gphy autopowerdown. */
10433         if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10434                 tg3_phy_toggle_apd(tp, false);
10435
10436         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
10437                 int i;
10438                 u32 status;
10439
10440                 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
10441
10442                 /* Wait for up to 40 microseconds to acquire lock. */
10443                 for (i = 0; i < 4; i++) {
10444                         status = tr32(TG3_CPMU_MUTEX_GNT);
10445                         if (status == CPMU_MUTEX_GNT_DRIVER)
10446                                 break;
10447                         udelay(10);
10448                 }
10449
10450                 if (status != CPMU_MUTEX_GNT_DRIVER)
10451                         return TG3_LOOPBACK_FAILED;
10452
10453                 /* Turn off link-based power management. */
10454                 cpmuctrl = tr32(TG3_CPMU_CTRL);
10455                 tw32(TG3_CPMU_CTRL,
10456                      cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
10457                                   CPMU_CTRL_LINK_AWARE_MODE));
10458         }
10459
10460         if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
10461                 err |= TG3_MAC_LOOPBACK_FAILED;
10462
10463         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
10464                 tw32(TG3_CPMU_CTRL, cpmuctrl);
10465
10466                 /* Release the mutex */
10467                 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
10468         }
10469
10470         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
10471             !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
10472                 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
10473                         err |= TG3_PHY_LOOPBACK_FAILED;
10474         }
10475
10476         /* Re-enable gphy autopowerdown. */
10477         if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10478                 tg3_phy_toggle_apd(tp, true);
10479
10480         return err;
10481 }
10482
10483 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
10484                           u64 *data)
10485 {
10486         struct tg3 *tp = netdev_priv(dev);
10487
10488         if (tp->link_config.phy_is_low_power)
10489                 tg3_set_power_state(tp, PCI_D0);
10490
10491         memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
10492
10493         if (tg3_test_nvram(tp) != 0) {
10494                 etest->flags |= ETH_TEST_FL_FAILED;
10495                 data[0] = 1;
10496         }
10497         if (tg3_test_link(tp) != 0) {
10498                 etest->flags |= ETH_TEST_FL_FAILED;
10499                 data[1] = 1;
10500         }
10501         if (etest->flags & ETH_TEST_FL_OFFLINE) {
10502                 int err, err2 = 0, irq_sync = 0;
10503
10504                 if (netif_running(dev)) {
10505                         tg3_phy_stop(tp);
10506                         tg3_netif_stop(tp);
10507                         irq_sync = 1;
10508                 }
10509
10510                 tg3_full_lock(tp, irq_sync);
10511
10512                 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
10513                 err = tg3_nvram_lock(tp);
10514                 tg3_halt_cpu(tp, RX_CPU_BASE);
10515                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10516                         tg3_halt_cpu(tp, TX_CPU_BASE);
10517                 if (!err)
10518                         tg3_nvram_unlock(tp);
10519
10520                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
10521                         tg3_phy_reset(tp);
10522
10523                 if (tg3_test_registers(tp) != 0) {
10524                         etest->flags |= ETH_TEST_FL_FAILED;
10525                         data[2] = 1;
10526                 }
10527                 if (tg3_test_memory(tp) != 0) {
10528                         etest->flags |= ETH_TEST_FL_FAILED;
10529                         data[3] = 1;
10530                 }
10531                 if ((data[4] = tg3_test_loopback(tp)) != 0)
10532                         etest->flags |= ETH_TEST_FL_FAILED;
10533
10534                 tg3_full_unlock(tp);
10535
10536                 if (tg3_test_interrupt(tp) != 0) {
10537                         etest->flags |= ETH_TEST_FL_FAILED;
10538                         data[5] = 1;
10539                 }
10540
10541                 tg3_full_lock(tp, 0);
10542
10543                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10544                 if (netif_running(dev)) {
10545                         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
10546                         err2 = tg3_restart_hw(tp, 1);
10547                         if (!err2)
10548                                 tg3_netif_start(tp);
10549                 }
10550
10551                 tg3_full_unlock(tp);
10552
10553                 if (irq_sync && !err2)
10554                         tg3_phy_start(tp);
10555         }
10556         if (tp->link_config.phy_is_low_power)
10557                 tg3_set_power_state(tp, PCI_D3hot);
10558
10559 }
10560
10561 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
10562 {
10563         struct mii_ioctl_data *data = if_mii(ifr);
10564         struct tg3 *tp = netdev_priv(dev);
10565         int err;
10566
10567         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
10568                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
10569                         return -EAGAIN;
10570                 return phy_mii_ioctl(tp->mdio_bus->phy_map[PHY_ADDR], data, cmd);
10571         }
10572
10573         switch(cmd) {
10574         case SIOCGMIIPHY:
10575                 data->phy_id = tp->phy_addr;
10576
10577                 /* fallthru */
10578         case SIOCGMIIREG: {
10579                 u32 mii_regval;
10580
10581                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10582                         break;                  /* We have no PHY */
10583
10584                 if (tp->link_config.phy_is_low_power)
10585                         return -EAGAIN;
10586
10587                 spin_lock_bh(&tp->lock);
10588                 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
10589                 spin_unlock_bh(&tp->lock);
10590
10591                 data->val_out = mii_regval;
10592
10593                 return err;
10594         }
10595
10596         case SIOCSMIIREG:
10597                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10598                         break;                  /* We have no PHY */
10599
10600                 if (tp->link_config.phy_is_low_power)
10601                         return -EAGAIN;
10602
10603                 spin_lock_bh(&tp->lock);
10604                 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
10605                 spin_unlock_bh(&tp->lock);
10606
10607                 return err;
10608
10609         default:
10610                 /* do nothing */
10611                 break;
10612         }
10613         return -EOPNOTSUPP;
10614 }
10615
10616 #if TG3_VLAN_TAG_USED
10617 static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
10618 {
10619         struct tg3 *tp = netdev_priv(dev);
10620
10621         if (!netif_running(dev)) {
10622                 tp->vlgrp = grp;
10623                 return;
10624         }
10625
10626         tg3_netif_stop(tp);
10627
10628         tg3_full_lock(tp, 0);
10629
10630         tp->vlgrp = grp;
10631
10632         /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
10633         __tg3_set_rx_mode(dev);
10634
10635         tg3_netif_start(tp);
10636
10637         tg3_full_unlock(tp);
10638 }
10639 #endif
10640
10641 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10642 {
10643         struct tg3 *tp = netdev_priv(dev);
10644
10645         memcpy(ec, &tp->coal, sizeof(*ec));
10646         return 0;
10647 }
10648
10649 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10650 {
10651         struct tg3 *tp = netdev_priv(dev);
10652         u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
10653         u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
10654
10655         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
10656                 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
10657                 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
10658                 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
10659                 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
10660         }
10661
10662         if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
10663             (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
10664             (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
10665             (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
10666             (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
10667             (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
10668             (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
10669             (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
10670             (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
10671             (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
10672                 return -EINVAL;
10673
10674         /* No rx interrupts will be generated if both are zero */
10675         if ((ec->rx_coalesce_usecs == 0) &&
10676             (ec->rx_max_coalesced_frames == 0))
10677                 return -EINVAL;
10678
10679         /* No tx interrupts will be generated if both are zero */
10680         if ((ec->tx_coalesce_usecs == 0) &&
10681             (ec->tx_max_coalesced_frames == 0))
10682                 return -EINVAL;
10683
10684         /* Only copy relevant parameters, ignore all others. */
10685         tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
10686         tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
10687         tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
10688         tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
10689         tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
10690         tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
10691         tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
10692         tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
10693         tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
10694
10695         if (netif_running(dev)) {
10696                 tg3_full_lock(tp, 0);
10697                 __tg3_set_coalesce(tp, &tp->coal);
10698                 tg3_full_unlock(tp);
10699         }
10700         return 0;
10701 }
10702
10703 static const struct ethtool_ops tg3_ethtool_ops = {
10704         .get_settings           = tg3_get_settings,
10705         .set_settings           = tg3_set_settings,
10706         .get_drvinfo            = tg3_get_drvinfo,
10707         .get_regs_len           = tg3_get_regs_len,
10708         .get_regs               = tg3_get_regs,
10709         .get_wol                = tg3_get_wol,
10710         .set_wol                = tg3_set_wol,
10711         .get_msglevel           = tg3_get_msglevel,
10712         .set_msglevel           = tg3_set_msglevel,
10713         .nway_reset             = tg3_nway_reset,
10714         .get_link               = ethtool_op_get_link,
10715         .get_eeprom_len         = tg3_get_eeprom_len,
10716         .get_eeprom             = tg3_get_eeprom,
10717         .set_eeprom             = tg3_set_eeprom,
10718         .get_ringparam          = tg3_get_ringparam,
10719         .set_ringparam          = tg3_set_ringparam,
10720         .get_pauseparam         = tg3_get_pauseparam,
10721         .set_pauseparam         = tg3_set_pauseparam,
10722         .get_rx_csum            = tg3_get_rx_csum,
10723         .set_rx_csum            = tg3_set_rx_csum,
10724         .set_tx_csum            = tg3_set_tx_csum,
10725         .set_sg                 = ethtool_op_set_sg,
10726         .set_tso                = tg3_set_tso,
10727         .self_test              = tg3_self_test,
10728         .get_strings            = tg3_get_strings,
10729         .phys_id                = tg3_phys_id,
10730         .get_ethtool_stats      = tg3_get_ethtool_stats,
10731         .get_coalesce           = tg3_get_coalesce,
10732         .set_coalesce           = tg3_set_coalesce,
10733         .get_sset_count         = tg3_get_sset_count,
10734 };
10735
10736 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
10737 {
10738         u32 cursize, val, magic;
10739
10740         tp->nvram_size = EEPROM_CHIP_SIZE;
10741
10742         if (tg3_nvram_read(tp, 0, &magic) != 0)
10743                 return;
10744
10745         if ((magic != TG3_EEPROM_MAGIC) &&
10746             ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
10747             ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
10748                 return;
10749
10750         /*
10751          * Size the chip by reading offsets at increasing powers of two.
10752          * When we encounter our validation signature, we know the addressing
10753          * has wrapped around, and thus have our chip size.
10754          */
10755         cursize = 0x10;
10756
10757         while (cursize < tp->nvram_size) {
10758                 if (tg3_nvram_read(tp, cursize, &val) != 0)
10759                         return;
10760
10761                 if (val == magic)
10762                         break;
10763
10764                 cursize <<= 1;
10765         }
10766
10767         tp->nvram_size = cursize;
10768 }
10769
10770 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
10771 {
10772         u32 val;
10773
10774         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
10775             tg3_nvram_read(tp, 0, &val) != 0)
10776                 return;
10777
10778         /* Selfboot format */
10779         if (val != TG3_EEPROM_MAGIC) {
10780                 tg3_get_eeprom_size(tp);
10781                 return;
10782         }
10783
10784         if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
10785                 if (val != 0) {
10786                         /* This is confusing.  We want to operate on the
10787                          * 16-bit value at offset 0xf2.  The tg3_nvram_read()
10788                          * call will read from NVRAM and byteswap the data
10789                          * according to the byteswapping settings for all
10790                          * other register accesses.  This ensures the data we
10791                          * want will always reside in the lower 16-bits.
10792                          * However, the data in NVRAM is in LE format, which
10793                          * means the data from the NVRAM read will always be
10794                          * opposite the endianness of the CPU.  The 16-bit
10795                          * byteswap then brings the data to CPU endianness.
10796                          */
10797                         tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
10798                         return;
10799                 }
10800         }
10801         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10802 }
10803
10804 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
10805 {
10806         u32 nvcfg1;
10807
10808         nvcfg1 = tr32(NVRAM_CFG1);
10809         if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
10810                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10811         } else {
10812                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10813                 tw32(NVRAM_CFG1, nvcfg1);
10814         }
10815
10816         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
10817             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
10818                 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
10819                 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
10820                         tp->nvram_jedecnum = JEDEC_ATMEL;
10821                         tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10822                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10823                         break;
10824                 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
10825                         tp->nvram_jedecnum = JEDEC_ATMEL;
10826                         tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
10827                         break;
10828                 case FLASH_VENDOR_ATMEL_EEPROM:
10829                         tp->nvram_jedecnum = JEDEC_ATMEL;
10830                         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10831                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10832                         break;
10833                 case FLASH_VENDOR_ST:
10834                         tp->nvram_jedecnum = JEDEC_ST;
10835                         tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
10836                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10837                         break;
10838                 case FLASH_VENDOR_SAIFUN:
10839                         tp->nvram_jedecnum = JEDEC_SAIFUN;
10840                         tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
10841                         break;
10842                 case FLASH_VENDOR_SST_SMALL:
10843                 case FLASH_VENDOR_SST_LARGE:
10844                         tp->nvram_jedecnum = JEDEC_SST;
10845                         tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
10846                         break;
10847                 }
10848         } else {
10849                 tp->nvram_jedecnum = JEDEC_ATMEL;
10850                 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10851                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10852         }
10853 }
10854
10855 static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
10856 {
10857         switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
10858         case FLASH_5752PAGE_SIZE_256:
10859                 tp->nvram_pagesize = 256;
10860                 break;
10861         case FLASH_5752PAGE_SIZE_512:
10862                 tp->nvram_pagesize = 512;
10863                 break;
10864         case FLASH_5752PAGE_SIZE_1K:
10865                 tp->nvram_pagesize = 1024;
10866                 break;
10867         case FLASH_5752PAGE_SIZE_2K:
10868                 tp->nvram_pagesize = 2048;
10869                 break;
10870         case FLASH_5752PAGE_SIZE_4K:
10871                 tp->nvram_pagesize = 4096;
10872                 break;
10873         case FLASH_5752PAGE_SIZE_264:
10874                 tp->nvram_pagesize = 264;
10875                 break;
10876         case FLASH_5752PAGE_SIZE_528:
10877                 tp->nvram_pagesize = 528;
10878                 break;
10879         }
10880 }
10881
10882 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
10883 {
10884         u32 nvcfg1;
10885
10886         nvcfg1 = tr32(NVRAM_CFG1);
10887
10888         /* NVRAM protection for TPM */
10889         if (nvcfg1 & (1 << 27))
10890                 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10891
10892         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10893         case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
10894         case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
10895                 tp->nvram_jedecnum = JEDEC_ATMEL;
10896                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10897                 break;
10898         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10899                 tp->nvram_jedecnum = JEDEC_ATMEL;
10900                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10901                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10902                 break;
10903         case FLASH_5752VENDOR_ST_M45PE10:
10904         case FLASH_5752VENDOR_ST_M45PE20:
10905         case FLASH_5752VENDOR_ST_M45PE40:
10906                 tp->nvram_jedecnum = JEDEC_ST;
10907                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10908                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10909                 break;
10910         }
10911
10912         if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
10913                 tg3_nvram_get_pagesize(tp, nvcfg1);
10914         } else {
10915                 /* For eeprom, set pagesize to maximum eeprom size */
10916                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10917
10918                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10919                 tw32(NVRAM_CFG1, nvcfg1);
10920         }
10921 }
10922
10923 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
10924 {
10925         u32 nvcfg1, protect = 0;
10926
10927         nvcfg1 = tr32(NVRAM_CFG1);
10928
10929         /* NVRAM protection for TPM */
10930         if (nvcfg1 & (1 << 27)) {
10931                 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10932                 protect = 1;
10933         }
10934
10935         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
10936         switch (nvcfg1) {
10937         case FLASH_5755VENDOR_ATMEL_FLASH_1:
10938         case FLASH_5755VENDOR_ATMEL_FLASH_2:
10939         case FLASH_5755VENDOR_ATMEL_FLASH_3:
10940         case FLASH_5755VENDOR_ATMEL_FLASH_5:
10941                 tp->nvram_jedecnum = JEDEC_ATMEL;
10942                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10943                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10944                 tp->nvram_pagesize = 264;
10945                 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
10946                     nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
10947                         tp->nvram_size = (protect ? 0x3e200 :
10948                                           TG3_NVRAM_SIZE_512KB);
10949                 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
10950                         tp->nvram_size = (protect ? 0x1f200 :
10951                                           TG3_NVRAM_SIZE_256KB);
10952                 else
10953                         tp->nvram_size = (protect ? 0x1f200 :
10954                                           TG3_NVRAM_SIZE_128KB);
10955                 break;
10956         case FLASH_5752VENDOR_ST_M45PE10:
10957         case FLASH_5752VENDOR_ST_M45PE20:
10958         case FLASH_5752VENDOR_ST_M45PE40:
10959                 tp->nvram_jedecnum = JEDEC_ST;
10960                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10961                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10962                 tp->nvram_pagesize = 256;
10963                 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
10964                         tp->nvram_size = (protect ?
10965                                           TG3_NVRAM_SIZE_64KB :
10966                                           TG3_NVRAM_SIZE_128KB);
10967                 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
10968                         tp->nvram_size = (protect ?
10969                                           TG3_NVRAM_SIZE_64KB :
10970                                           TG3_NVRAM_SIZE_256KB);
10971                 else
10972                         tp->nvram_size = (protect ?
10973                                           TG3_NVRAM_SIZE_128KB :
10974                                           TG3_NVRAM_SIZE_512KB);
10975                 break;
10976         }
10977 }
10978
10979 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
10980 {
10981         u32 nvcfg1;
10982
10983         nvcfg1 = tr32(NVRAM_CFG1);
10984
10985         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10986         case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
10987         case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
10988         case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
10989         case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
10990                 tp->nvram_jedecnum = JEDEC_ATMEL;
10991                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10992                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10993
10994                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10995                 tw32(NVRAM_CFG1, nvcfg1);
10996                 break;
10997         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10998         case FLASH_5755VENDOR_ATMEL_FLASH_1:
10999         case FLASH_5755VENDOR_ATMEL_FLASH_2:
11000         case FLASH_5755VENDOR_ATMEL_FLASH_3:
11001                 tp->nvram_jedecnum = JEDEC_ATMEL;
11002                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11003                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11004                 tp->nvram_pagesize = 264;
11005                 break;
11006         case FLASH_5752VENDOR_ST_M45PE10:
11007         case FLASH_5752VENDOR_ST_M45PE20:
11008         case FLASH_5752VENDOR_ST_M45PE40:
11009                 tp->nvram_jedecnum = JEDEC_ST;
11010                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11011                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11012                 tp->nvram_pagesize = 256;
11013                 break;
11014         }
11015 }
11016
11017 static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
11018 {
11019         u32 nvcfg1, protect = 0;
11020
11021         nvcfg1 = tr32(NVRAM_CFG1);
11022
11023         /* NVRAM protection for TPM */
11024         if (nvcfg1 & (1 << 27)) {
11025                 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
11026                 protect = 1;
11027         }
11028
11029         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11030         switch (nvcfg1) {
11031         case FLASH_5761VENDOR_ATMEL_ADB021D:
11032         case FLASH_5761VENDOR_ATMEL_ADB041D:
11033         case FLASH_5761VENDOR_ATMEL_ADB081D:
11034         case FLASH_5761VENDOR_ATMEL_ADB161D:
11035         case FLASH_5761VENDOR_ATMEL_MDB021D:
11036         case FLASH_5761VENDOR_ATMEL_MDB041D:
11037         case FLASH_5761VENDOR_ATMEL_MDB081D:
11038         case FLASH_5761VENDOR_ATMEL_MDB161D:
11039                 tp->nvram_jedecnum = JEDEC_ATMEL;
11040                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11041                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11042                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11043                 tp->nvram_pagesize = 256;
11044                 break;
11045         case FLASH_5761VENDOR_ST_A_M45PE20:
11046         case FLASH_5761VENDOR_ST_A_M45PE40:
11047         case FLASH_5761VENDOR_ST_A_M45PE80:
11048         case FLASH_5761VENDOR_ST_A_M45PE16:
11049         case FLASH_5761VENDOR_ST_M_M45PE20:
11050         case FLASH_5761VENDOR_ST_M_M45PE40:
11051         case FLASH_5761VENDOR_ST_M_M45PE80:
11052         case FLASH_5761VENDOR_ST_M_M45PE16:
11053                 tp->nvram_jedecnum = JEDEC_ST;
11054                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11055                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11056                 tp->nvram_pagesize = 256;
11057                 break;
11058         }
11059
11060         if (protect) {
11061                 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
11062         } else {
11063                 switch (nvcfg1) {
11064                 case FLASH_5761VENDOR_ATMEL_ADB161D:
11065                 case FLASH_5761VENDOR_ATMEL_MDB161D:
11066                 case FLASH_5761VENDOR_ST_A_M45PE16:
11067                 case FLASH_5761VENDOR_ST_M_M45PE16:
11068                         tp->nvram_size = TG3_NVRAM_SIZE_2MB;
11069                         break;
11070                 case FLASH_5761VENDOR_ATMEL_ADB081D:
11071                 case FLASH_5761VENDOR_ATMEL_MDB081D:
11072                 case FLASH_5761VENDOR_ST_A_M45PE80:
11073                 case FLASH_5761VENDOR_ST_M_M45PE80:
11074                         tp->nvram_size = TG3_NVRAM_SIZE_1MB;
11075                         break;
11076                 case FLASH_5761VENDOR_ATMEL_ADB041D:
11077                 case FLASH_5761VENDOR_ATMEL_MDB041D:
11078                 case FLASH_5761VENDOR_ST_A_M45PE40:
11079                 case FLASH_5761VENDOR_ST_M_M45PE40:
11080                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11081                         break;
11082                 case FLASH_5761VENDOR_ATMEL_ADB021D:
11083                 case FLASH_5761VENDOR_ATMEL_MDB021D:
11084                 case FLASH_5761VENDOR_ST_A_M45PE20:
11085                 case FLASH_5761VENDOR_ST_M_M45PE20:
11086                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11087                         break;
11088                 }
11089         }
11090 }
11091
11092 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
11093 {
11094         tp->nvram_jedecnum = JEDEC_ATMEL;
11095         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11096         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11097 }
11098
11099 static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
11100 {
11101         u32 nvcfg1;
11102
11103         nvcfg1 = tr32(NVRAM_CFG1);
11104
11105         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11106         case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11107         case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11108                 tp->nvram_jedecnum = JEDEC_ATMEL;
11109                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11110                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11111
11112                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11113                 tw32(NVRAM_CFG1, nvcfg1);
11114                 return;
11115         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11116         case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11117         case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11118         case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11119         case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11120         case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11121         case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11122                 tp->nvram_jedecnum = JEDEC_ATMEL;
11123                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11124                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11125
11126                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11127                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11128                 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11129                 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11130                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11131                         break;
11132                 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11133                 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11134                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11135                         break;
11136                 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11137                 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11138                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11139                         break;
11140                 }
11141                 break;
11142         case FLASH_5752VENDOR_ST_M45PE10:
11143         case FLASH_5752VENDOR_ST_M45PE20:
11144         case FLASH_5752VENDOR_ST_M45PE40:
11145                 tp->nvram_jedecnum = JEDEC_ST;
11146                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11147                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11148
11149                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11150                 case FLASH_5752VENDOR_ST_M45PE10:
11151                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11152                         break;
11153                 case FLASH_5752VENDOR_ST_M45PE20:
11154                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11155                         break;
11156                 case FLASH_5752VENDOR_ST_M45PE40:
11157                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11158                         break;
11159                 }
11160                 break;
11161         default:
11162                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11163                 return;
11164         }
11165
11166         tg3_nvram_get_pagesize(tp, nvcfg1);
11167         if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11168                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11169 }
11170
11171
11172 static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp)
11173 {
11174         u32 nvcfg1;
11175
11176         nvcfg1 = tr32(NVRAM_CFG1);
11177
11178         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11179         case FLASH_5717VENDOR_ATMEL_EEPROM:
11180         case FLASH_5717VENDOR_MICRO_EEPROM:
11181                 tp->nvram_jedecnum = JEDEC_ATMEL;
11182                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11183                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11184
11185                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11186                 tw32(NVRAM_CFG1, nvcfg1);
11187                 return;
11188         case FLASH_5717VENDOR_ATMEL_MDB011D:
11189         case FLASH_5717VENDOR_ATMEL_ADB011B:
11190         case FLASH_5717VENDOR_ATMEL_ADB011D:
11191         case FLASH_5717VENDOR_ATMEL_MDB021D:
11192         case FLASH_5717VENDOR_ATMEL_ADB021B:
11193         case FLASH_5717VENDOR_ATMEL_ADB021D:
11194         case FLASH_5717VENDOR_ATMEL_45USPT:
11195                 tp->nvram_jedecnum = JEDEC_ATMEL;
11196                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11197                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11198
11199                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11200                 case FLASH_5717VENDOR_ATMEL_MDB021D:
11201                 case FLASH_5717VENDOR_ATMEL_ADB021B:
11202                 case FLASH_5717VENDOR_ATMEL_ADB021D:
11203                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11204                         break;
11205                 default:
11206                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11207                         break;
11208                 }
11209                 break;
11210         case FLASH_5717VENDOR_ST_M_M25PE10:
11211         case FLASH_5717VENDOR_ST_A_M25PE10:
11212         case FLASH_5717VENDOR_ST_M_M45PE10:
11213         case FLASH_5717VENDOR_ST_A_M45PE10:
11214         case FLASH_5717VENDOR_ST_M_M25PE20:
11215         case FLASH_5717VENDOR_ST_A_M25PE20:
11216         case FLASH_5717VENDOR_ST_M_M45PE20:
11217         case FLASH_5717VENDOR_ST_A_M45PE20:
11218         case FLASH_5717VENDOR_ST_25USPT:
11219         case FLASH_5717VENDOR_ST_45USPT:
11220                 tp->nvram_jedecnum = JEDEC_ST;
11221                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11222                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11223
11224                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11225                 case FLASH_5717VENDOR_ST_M_M25PE20:
11226                 case FLASH_5717VENDOR_ST_A_M25PE20:
11227                 case FLASH_5717VENDOR_ST_M_M45PE20:
11228                 case FLASH_5717VENDOR_ST_A_M45PE20:
11229                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11230                         break;
11231                 default:
11232                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11233                         break;
11234                 }
11235                 break;
11236         default:
11237                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11238                 return;
11239         }
11240
11241         tg3_nvram_get_pagesize(tp, nvcfg1);
11242         if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11243                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11244 }
11245
11246 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
11247 static void __devinit tg3_nvram_init(struct tg3 *tp)
11248 {
11249         tw32_f(GRC_EEPROM_ADDR,
11250              (EEPROM_ADDR_FSM_RESET |
11251               (EEPROM_DEFAULT_CLOCK_PERIOD <<
11252                EEPROM_ADDR_CLKPERD_SHIFT)));
11253
11254         msleep(1);
11255
11256         /* Enable seeprom accesses. */
11257         tw32_f(GRC_LOCAL_CTRL,
11258              tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
11259         udelay(100);
11260
11261         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11262             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
11263                 tp->tg3_flags |= TG3_FLAG_NVRAM;
11264
11265                 if (tg3_nvram_lock(tp)) {
11266                         printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
11267                                "tg3_nvram_init failed.\n", tp->dev->name);
11268                         return;
11269                 }
11270                 tg3_enable_nvram_access(tp);
11271
11272                 tp->nvram_size = 0;
11273
11274                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
11275                         tg3_get_5752_nvram_info(tp);
11276                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
11277                         tg3_get_5755_nvram_info(tp);
11278                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
11279                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11280                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11281                         tg3_get_5787_nvram_info(tp);
11282                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
11283                         tg3_get_5761_nvram_info(tp);
11284                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11285                         tg3_get_5906_nvram_info(tp);
11286                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
11287                         tg3_get_57780_nvram_info(tp);
11288                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
11289                         tg3_get_5717_nvram_info(tp);
11290                 else
11291                         tg3_get_nvram_info(tp);
11292
11293                 if (tp->nvram_size == 0)
11294                         tg3_get_nvram_size(tp);
11295
11296                 tg3_disable_nvram_access(tp);
11297                 tg3_nvram_unlock(tp);
11298
11299         } else {
11300                 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
11301
11302                 tg3_get_eeprom_size(tp);
11303         }
11304 }
11305
11306 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
11307                                     u32 offset, u32 len, u8 *buf)
11308 {
11309         int i, j, rc = 0;
11310         u32 val;
11311
11312         for (i = 0; i < len; i += 4) {
11313                 u32 addr;
11314                 __be32 data;
11315
11316                 addr = offset + i;
11317
11318                 memcpy(&data, buf + i, 4);
11319
11320                 /*
11321                  * The SEEPROM interface expects the data to always be opposite
11322                  * the native endian format.  We accomplish this by reversing
11323                  * all the operations that would have been performed on the
11324                  * data from a call to tg3_nvram_read_be32().
11325                  */
11326                 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
11327
11328                 val = tr32(GRC_EEPROM_ADDR);
11329                 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
11330
11331                 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
11332                         EEPROM_ADDR_READ);
11333                 tw32(GRC_EEPROM_ADDR, val |
11334                         (0 << EEPROM_ADDR_DEVID_SHIFT) |
11335                         (addr & EEPROM_ADDR_ADDR_MASK) |
11336                         EEPROM_ADDR_START |
11337                         EEPROM_ADDR_WRITE);
11338
11339                 for (j = 0; j < 1000; j++) {
11340                         val = tr32(GRC_EEPROM_ADDR);
11341
11342                         if (val & EEPROM_ADDR_COMPLETE)
11343                                 break;
11344                         msleep(1);
11345                 }
11346                 if (!(val & EEPROM_ADDR_COMPLETE)) {
11347                         rc = -EBUSY;
11348                         break;
11349                 }
11350         }
11351
11352         return rc;
11353 }
11354
11355 /* offset and length are dword aligned */
11356 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
11357                 u8 *buf)
11358 {
11359         int ret = 0;
11360         u32 pagesize = tp->nvram_pagesize;
11361         u32 pagemask = pagesize - 1;
11362         u32 nvram_cmd;
11363         u8 *tmp;
11364
11365         tmp = kmalloc(pagesize, GFP_KERNEL);
11366         if (tmp == NULL)
11367                 return -ENOMEM;
11368
11369         while (len) {
11370                 int j;
11371                 u32 phy_addr, page_off, size;
11372
11373                 phy_addr = offset & ~pagemask;
11374
11375                 for (j = 0; j < pagesize; j += 4) {
11376                         ret = tg3_nvram_read_be32(tp, phy_addr + j,
11377                                                   (__be32 *) (tmp + j));
11378                         if (ret)
11379                                 break;
11380                 }
11381                 if (ret)
11382                         break;
11383
11384                 page_off = offset & pagemask;
11385                 size = pagesize;
11386                 if (len < size)
11387                         size = len;
11388
11389                 len -= size;
11390
11391                 memcpy(tmp + page_off, buf, size);
11392
11393                 offset = offset + (pagesize - page_off);
11394
11395                 tg3_enable_nvram_access(tp);
11396
11397                 /*
11398                  * Before we can erase the flash page, we need
11399                  * to issue a special "write enable" command.
11400                  */
11401                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11402
11403                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11404                         break;
11405
11406                 /* Erase the target page */
11407                 tw32(NVRAM_ADDR, phy_addr);
11408
11409                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
11410                         NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
11411
11412                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11413                         break;
11414
11415                 /* Issue another write enable to start the write. */
11416                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11417
11418                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11419                         break;
11420
11421                 for (j = 0; j < pagesize; j += 4) {
11422                         __be32 data;
11423
11424                         data = *((__be32 *) (tmp + j));
11425
11426                         tw32(NVRAM_WRDATA, be32_to_cpu(data));
11427
11428                         tw32(NVRAM_ADDR, phy_addr + j);
11429
11430                         nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
11431                                 NVRAM_CMD_WR;
11432
11433                         if (j == 0)
11434                                 nvram_cmd |= NVRAM_CMD_FIRST;
11435                         else if (j == (pagesize - 4))
11436                                 nvram_cmd |= NVRAM_CMD_LAST;
11437
11438                         if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11439                                 break;
11440                 }
11441                 if (ret)
11442                         break;
11443         }
11444
11445         nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11446         tg3_nvram_exec_cmd(tp, nvram_cmd);
11447
11448         kfree(tmp);
11449
11450         return ret;
11451 }
11452
11453 /* offset and length are dword aligned */
11454 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
11455                 u8 *buf)
11456 {
11457         int i, ret = 0;
11458
11459         for (i = 0; i < len; i += 4, offset += 4) {
11460                 u32 page_off, phy_addr, nvram_cmd;
11461                 __be32 data;
11462
11463                 memcpy(&data, buf + i, 4);
11464                 tw32(NVRAM_WRDATA, be32_to_cpu(data));
11465
11466                 page_off = offset % tp->nvram_pagesize;
11467
11468                 phy_addr = tg3_nvram_phys_addr(tp, offset);
11469
11470                 tw32(NVRAM_ADDR, phy_addr);
11471
11472                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
11473
11474                 if ((page_off == 0) || (i == 0))
11475                         nvram_cmd |= NVRAM_CMD_FIRST;
11476                 if (page_off == (tp->nvram_pagesize - 4))
11477                         nvram_cmd |= NVRAM_CMD_LAST;
11478
11479                 if (i == (len - 4))
11480                         nvram_cmd |= NVRAM_CMD_LAST;
11481
11482                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
11483                     !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
11484                     (tp->nvram_jedecnum == JEDEC_ST) &&
11485                     (nvram_cmd & NVRAM_CMD_FIRST)) {
11486
11487                         if ((ret = tg3_nvram_exec_cmd(tp,
11488                                 NVRAM_CMD_WREN | NVRAM_CMD_GO |
11489                                 NVRAM_CMD_DONE)))
11490
11491                                 break;
11492                 }
11493                 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11494                         /* We always do complete word writes to eeprom. */
11495                         nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
11496                 }
11497
11498                 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11499                         break;
11500         }
11501         return ret;
11502 }
11503
11504 /* offset and length are dword aligned */
11505 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
11506 {
11507         int ret;
11508
11509         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
11510                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
11511                        ~GRC_LCLCTRL_GPIO_OUTPUT1);
11512                 udelay(40);
11513         }
11514
11515         if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
11516                 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
11517         }
11518         else {
11519                 u32 grc_mode;
11520
11521                 ret = tg3_nvram_lock(tp);
11522                 if (ret)
11523                         return ret;
11524
11525                 tg3_enable_nvram_access(tp);
11526                 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
11527                     !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
11528                         tw32(NVRAM_WRITE1, 0x406);
11529
11530                 grc_mode = tr32(GRC_MODE);
11531                 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
11532
11533                 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
11534                         !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11535
11536                         ret = tg3_nvram_write_block_buffered(tp, offset, len,
11537                                 buf);
11538                 }
11539                 else {
11540                         ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
11541                                 buf);
11542                 }
11543
11544                 grc_mode = tr32(GRC_MODE);
11545                 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
11546
11547                 tg3_disable_nvram_access(tp);
11548                 tg3_nvram_unlock(tp);
11549         }
11550
11551         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
11552                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
11553                 udelay(40);
11554         }
11555
11556         return ret;
11557 }
11558
11559 struct subsys_tbl_ent {
11560         u16 subsys_vendor, subsys_devid;
11561         u32 phy_id;
11562 };
11563
11564 static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
11565         /* Broadcom boards. */
11566         { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
11567         { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
11568         { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
11569         { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 },              /* BCM95700A9 */
11570         { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
11571         { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
11572         { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 },              /* BCM95701A7 */
11573         { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
11574         { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
11575         { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
11576         { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
11577
11578         /* 3com boards. */
11579         { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
11580         { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
11581         { PCI_VENDOR_ID_3COM, 0x1004, 0 },              /* 3C996SX */
11582         { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
11583         { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
11584
11585         /* DELL boards. */
11586         { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
11587         { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
11588         { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
11589         { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
11590
11591         /* Compaq boards. */
11592         { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
11593         { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
11594         { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 },              /* CHANGELING */
11595         { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
11596         { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
11597
11598         /* IBM boards. */
11599         { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
11600 };
11601
11602 static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
11603 {
11604         int i;
11605
11606         for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
11607                 if ((subsys_id_to_phy_id[i].subsys_vendor ==
11608                      tp->pdev->subsystem_vendor) &&
11609                     (subsys_id_to_phy_id[i].subsys_devid ==
11610                      tp->pdev->subsystem_device))
11611                         return &subsys_id_to_phy_id[i];
11612         }
11613         return NULL;
11614 }
11615
11616 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
11617 {
11618         u32 val;
11619         u16 pmcsr;
11620
11621         /* On some early chips the SRAM cannot be accessed in D3hot state,
11622          * so need make sure we're in D0.
11623          */
11624         pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
11625         pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
11626         pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
11627         msleep(1);
11628
11629         /* Make sure register accesses (indirect or otherwise)
11630          * will function correctly.
11631          */
11632         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11633                                tp->misc_host_ctrl);
11634
11635         /* The memory arbiter has to be enabled in order for SRAM accesses
11636          * to succeed.  Normally on powerup the tg3 chip firmware will make
11637          * sure it is enabled, but other entities such as system netboot
11638          * code might disable it.
11639          */
11640         val = tr32(MEMARB_MODE);
11641         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
11642
11643         tp->phy_id = PHY_ID_INVALID;
11644         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11645
11646         /* Assume an onboard device and WOL capable by default.  */
11647         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
11648
11649         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
11650                 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
11651                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11652                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
11653                 }
11654                 val = tr32(VCPU_CFGSHDW);
11655                 if (val & VCPU_CFGSHDW_ASPM_DBNC)
11656                         tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
11657                 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
11658                     (val & VCPU_CFGSHDW_WOL_MAGPKT))
11659                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
11660                 goto done;
11661         }
11662
11663         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
11664         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
11665                 u32 nic_cfg, led_cfg;
11666                 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
11667                 int eeprom_phy_serdes = 0;
11668
11669                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
11670                 tp->nic_sram_data_cfg = nic_cfg;
11671
11672                 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
11673                 ver >>= NIC_SRAM_DATA_VER_SHIFT;
11674                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
11675                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
11676                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
11677                     (ver > 0) && (ver < 0x100))
11678                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
11679
11680                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11681                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
11682
11683                 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
11684                     NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
11685                         eeprom_phy_serdes = 1;
11686
11687                 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
11688                 if (nic_phy_id != 0) {
11689                         u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
11690                         u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
11691
11692                         eeprom_phy_id  = (id1 >> 16) << 10;
11693                         eeprom_phy_id |= (id2 & 0xfc00) << 16;
11694                         eeprom_phy_id |= (id2 & 0x03ff) <<  0;
11695                 } else
11696                         eeprom_phy_id = 0;
11697
11698                 tp->phy_id = eeprom_phy_id;
11699                 if (eeprom_phy_serdes) {
11700                         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
11701                                 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
11702                         else
11703                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11704                 }
11705
11706                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
11707                         led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
11708                                     SHASTA_EXT_LED_MODE_MASK);
11709                 else
11710                         led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
11711
11712                 switch (led_cfg) {
11713                 default:
11714                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
11715                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11716                         break;
11717
11718                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
11719                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11720                         break;
11721
11722                 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
11723                         tp->led_ctrl = LED_CTRL_MODE_MAC;
11724
11725                         /* Default to PHY_1_MODE if 0 (MAC_MODE) is
11726                          * read on some older 5700/5701 bootcode.
11727                          */
11728                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
11729                             ASIC_REV_5700 ||
11730                             GET_ASIC_REV(tp->pci_chip_rev_id) ==
11731                             ASIC_REV_5701)
11732                                 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11733
11734                         break;
11735
11736                 case SHASTA_EXT_LED_SHARED:
11737                         tp->led_ctrl = LED_CTRL_MODE_SHARED;
11738                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
11739                             tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
11740                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11741                                                  LED_CTRL_MODE_PHY_2);
11742                         break;
11743
11744                 case SHASTA_EXT_LED_MAC:
11745                         tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
11746                         break;
11747
11748                 case SHASTA_EXT_LED_COMBO:
11749                         tp->led_ctrl = LED_CTRL_MODE_COMBO;
11750                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
11751                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11752                                                  LED_CTRL_MODE_PHY_2);
11753                         break;
11754
11755                 }
11756
11757                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11758                      GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
11759                     tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
11760                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11761
11762                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
11763                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11764
11765                 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
11766                         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
11767                         if ((tp->pdev->subsystem_vendor ==
11768                              PCI_VENDOR_ID_ARIMA) &&
11769                             (tp->pdev->subsystem_device == 0x205a ||
11770                              tp->pdev->subsystem_device == 0x2063))
11771                                 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11772                 } else {
11773                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11774                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
11775                 }
11776
11777                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
11778                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
11779                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
11780                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
11781                 }
11782
11783                 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
11784                         (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
11785                         tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
11786
11787                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
11788                     !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
11789                         tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
11790
11791                 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
11792                     (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
11793                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
11794
11795                 if (cfg2 & (1 << 17))
11796                         tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
11797
11798                 /* serdes signal pre-emphasis in register 0x590 set by */
11799                 /* bootcode if bit 18 is set */
11800                 if (cfg2 & (1 << 18))
11801                         tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
11802
11803                 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
11804                       GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
11805                     (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
11806                         tp->tg3_flags3 |= TG3_FLG3_PHY_ENABLE_APD;
11807
11808                 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11809                         u32 cfg3;
11810
11811                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
11812                         if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
11813                                 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
11814                 }
11815
11816                 if (cfg4 & NIC_SRAM_RGMII_STD_IBND_DISABLE)
11817                         tp->tg3_flags3 |= TG3_FLG3_RGMII_STD_IBND_DISABLE;
11818                 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
11819                         tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
11820                 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
11821                         tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
11822         }
11823 done:
11824         device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
11825         device_set_wakeup_enable(&tp->pdev->dev,
11826                                  tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
11827 }
11828
11829 static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
11830 {
11831         int i;
11832         u32 val;
11833
11834         tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
11835         tw32(OTP_CTRL, cmd);
11836
11837         /* Wait for up to 1 ms for command to execute. */
11838         for (i = 0; i < 100; i++) {
11839                 val = tr32(OTP_STATUS);
11840                 if (val & OTP_STATUS_CMD_DONE)
11841                         break;
11842                 udelay(10);
11843         }
11844
11845         return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
11846 }
11847
11848 /* Read the gphy configuration from the OTP region of the chip.  The gphy
11849  * configuration is a 32-bit value that straddles the alignment boundary.
11850  * We do two 32-bit reads and then shift and merge the results.
11851  */
11852 static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
11853 {
11854         u32 bhalf_otp, thalf_otp;
11855
11856         tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
11857
11858         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
11859                 return 0;
11860
11861         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
11862
11863         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
11864                 return 0;
11865
11866         thalf_otp = tr32(OTP_READ_DATA);
11867
11868         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
11869
11870         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
11871                 return 0;
11872
11873         bhalf_otp = tr32(OTP_READ_DATA);
11874
11875         return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
11876 }
11877
11878 static int __devinit tg3_phy_probe(struct tg3 *tp)
11879 {
11880         u32 hw_phy_id_1, hw_phy_id_2;
11881         u32 hw_phy_id, hw_phy_id_masked;
11882         int err;
11883
11884         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
11885                 return tg3_phy_init(tp);
11886
11887         /* Reading the PHY ID register can conflict with ASF
11888          * firmware access to the PHY hardware.
11889          */
11890         err = 0;
11891         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
11892             (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
11893                 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
11894         } else {
11895                 /* Now read the physical PHY_ID from the chip and verify
11896                  * that it is sane.  If it doesn't look good, we fall back
11897                  * to either the hard-coded table based PHY_ID and failing
11898                  * that the value found in the eeprom area.
11899                  */
11900                 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
11901                 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
11902
11903                 hw_phy_id  = (hw_phy_id_1 & 0xffff) << 10;
11904                 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
11905                 hw_phy_id |= (hw_phy_id_2 & 0x03ff) <<  0;
11906
11907                 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
11908         }
11909
11910         if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
11911                 tp->phy_id = hw_phy_id;
11912                 if (hw_phy_id_masked == PHY_ID_BCM8002)
11913                         tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11914                 else
11915                         tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
11916         } else {
11917                 if (tp->phy_id != PHY_ID_INVALID) {
11918                         /* Do nothing, phy ID already set up in
11919                          * tg3_get_eeprom_hw_cfg().
11920                          */
11921                 } else {
11922                         struct subsys_tbl_ent *p;
11923
11924                         /* No eeprom signature?  Try the hardcoded
11925                          * subsys device table.
11926                          */
11927                         p = lookup_by_subsys(tp);
11928                         if (!p)
11929                                 return -ENODEV;
11930
11931                         tp->phy_id = p->phy_id;
11932                         if (!tp->phy_id ||
11933                             tp->phy_id == PHY_ID_BCM8002)
11934                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11935                 }
11936         }
11937
11938         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
11939             !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
11940             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
11941                 u32 bmsr, adv_reg, tg3_ctrl, mask;
11942
11943                 tg3_readphy(tp, MII_BMSR, &bmsr);
11944                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
11945                     (bmsr & BMSR_LSTATUS))
11946                         goto skip_phy_reset;
11947
11948                 err = tg3_phy_reset(tp);
11949                 if (err)
11950                         return err;
11951
11952                 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
11953                            ADVERTISE_100HALF | ADVERTISE_100FULL |
11954                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
11955                 tg3_ctrl = 0;
11956                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
11957                         tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
11958                                     MII_TG3_CTRL_ADV_1000_FULL);
11959                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
11960                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
11961                                 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
11962                                              MII_TG3_CTRL_ENABLE_AS_MASTER);
11963                 }
11964
11965                 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
11966                         ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
11967                         ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
11968                 if (!tg3_copper_is_advertising_all(tp, mask)) {
11969                         tg3_writephy(tp, MII_ADVERTISE, adv_reg);
11970
11971                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
11972                                 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
11973
11974                         tg3_writephy(tp, MII_BMCR,
11975                                      BMCR_ANENABLE | BMCR_ANRESTART);
11976                 }
11977                 tg3_phy_set_wirespeed(tp);
11978
11979                 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
11980                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
11981                         tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
11982         }
11983
11984 skip_phy_reset:
11985         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
11986                 err = tg3_init_5401phy_dsp(tp);
11987                 if (err)
11988                         return err;
11989         }
11990
11991         if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
11992                 err = tg3_init_5401phy_dsp(tp);
11993         }
11994
11995         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
11996                 tp->link_config.advertising =
11997                         (ADVERTISED_1000baseT_Half |
11998                          ADVERTISED_1000baseT_Full |
11999                          ADVERTISED_Autoneg |
12000                          ADVERTISED_FIBRE);
12001         if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
12002                 tp->link_config.advertising &=
12003                         ~(ADVERTISED_1000baseT_Half |
12004                           ADVERTISED_1000baseT_Full);
12005
12006         return err;
12007 }
12008
12009 static void __devinit tg3_read_partno(struct tg3 *tp)
12010 {
12011         unsigned char vpd_data[256];   /* in little-endian format */
12012         unsigned int i;
12013         u32 magic;
12014
12015         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
12016             tg3_nvram_read(tp, 0x0, &magic))
12017                 goto out_not_found;
12018
12019         if (magic == TG3_EEPROM_MAGIC) {
12020                 for (i = 0; i < 256; i += 4) {
12021                         u32 tmp;
12022
12023                         /* The data is in little-endian format in NVRAM.
12024                          * Use the big-endian read routines to preserve
12025                          * the byte order as it exists in NVRAM.
12026                          */
12027                         if (tg3_nvram_read_be32(tp, 0x100 + i, &tmp))
12028                                 goto out_not_found;
12029
12030                         memcpy(&vpd_data[i], &tmp, sizeof(tmp));
12031                 }
12032         } else {
12033                 int vpd_cap;
12034
12035                 vpd_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_VPD);
12036                 for (i = 0; i < 256; i += 4) {
12037                         u32 tmp, j = 0;
12038                         __le32 v;
12039                         u16 tmp16;
12040
12041                         pci_write_config_word(tp->pdev, vpd_cap + PCI_VPD_ADDR,
12042                                               i);
12043                         while (j++ < 100) {
12044                                 pci_read_config_word(tp->pdev, vpd_cap +
12045                                                      PCI_VPD_ADDR, &tmp16);
12046                                 if (tmp16 & 0x8000)
12047                                         break;
12048                                 msleep(1);
12049                         }
12050                         if (!(tmp16 & 0x8000))
12051                                 goto out_not_found;
12052
12053                         pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA,
12054                                               &tmp);
12055                         v = cpu_to_le32(tmp);
12056                         memcpy(&vpd_data[i], &v, sizeof(v));
12057                 }
12058         }
12059
12060         /* Now parse and find the part number. */
12061         for (i = 0; i < 254; ) {
12062                 unsigned char val = vpd_data[i];
12063                 unsigned int block_end;
12064
12065                 if (val == 0x82 || val == 0x91) {
12066                         i = (i + 3 +
12067                              (vpd_data[i + 1] +
12068                               (vpd_data[i + 2] << 8)));
12069                         continue;
12070                 }
12071
12072                 if (val != 0x90)
12073                         goto out_not_found;
12074
12075                 block_end = (i + 3 +
12076                              (vpd_data[i + 1] +
12077                               (vpd_data[i + 2] << 8)));
12078                 i += 3;
12079
12080                 if (block_end > 256)
12081                         goto out_not_found;
12082
12083                 while (i < (block_end - 2)) {
12084                         if (vpd_data[i + 0] == 'P' &&
12085                             vpd_data[i + 1] == 'N') {
12086                                 int partno_len = vpd_data[i + 2];
12087
12088                                 i += 3;
12089                                 if (partno_len > 24 || (partno_len + i) > 256)
12090                                         goto out_not_found;
12091
12092                                 memcpy(tp->board_part_number,
12093                                        &vpd_data[i], partno_len);
12094
12095                                 /* Success. */
12096                                 return;
12097                         }
12098                         i += 3 + vpd_data[i + 2];
12099                 }
12100
12101                 /* Part number not found. */
12102                 goto out_not_found;
12103         }
12104
12105 out_not_found:
12106         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12107                 strcpy(tp->board_part_number, "BCM95906");
12108         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12109                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
12110                 strcpy(tp->board_part_number, "BCM57780");
12111         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12112                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
12113                 strcpy(tp->board_part_number, "BCM57760");
12114         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12115                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
12116                 strcpy(tp->board_part_number, "BCM57790");
12117         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12118                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
12119                 strcpy(tp->board_part_number, "BCM57788");
12120         else
12121                 strcpy(tp->board_part_number, "none");
12122 }
12123
12124 static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
12125 {
12126         u32 val;
12127
12128         if (tg3_nvram_read(tp, offset, &val) ||
12129             (val & 0xfc000000) != 0x0c000000 ||
12130             tg3_nvram_read(tp, offset + 4, &val) ||
12131             val != 0)
12132                 return 0;
12133
12134         return 1;
12135 }
12136
12137 static void __devinit tg3_read_bc_ver(struct tg3 *tp)
12138 {
12139         u32 val, offset, start, ver_offset;
12140         int i;
12141         bool newver = false;
12142
12143         if (tg3_nvram_read(tp, 0xc, &offset) ||
12144             tg3_nvram_read(tp, 0x4, &start))
12145                 return;
12146
12147         offset = tg3_nvram_logical_addr(tp, offset);
12148
12149         if (tg3_nvram_read(tp, offset, &val))
12150                 return;
12151
12152         if ((val & 0xfc000000) == 0x0c000000) {
12153                 if (tg3_nvram_read(tp, offset + 4, &val))
12154                         return;
12155
12156                 if (val == 0)
12157                         newver = true;
12158         }
12159
12160         if (newver) {
12161                 if (tg3_nvram_read(tp, offset + 8, &ver_offset))
12162                         return;
12163
12164                 offset = offset + ver_offset - start;
12165                 for (i = 0; i < 16; i += 4) {
12166                         __be32 v;
12167                         if (tg3_nvram_read_be32(tp, offset + i, &v))
12168                                 return;
12169
12170                         memcpy(tp->fw_ver + i, &v, sizeof(v));
12171                 }
12172         } else {
12173                 u32 major, minor;
12174
12175                 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
12176                         return;
12177
12178                 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
12179                         TG3_NVM_BCVER_MAJSFT;
12180                 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
12181                 snprintf(&tp->fw_ver[0], 32, "v%d.%02d", major, minor);
12182         }
12183 }
12184
12185 static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
12186 {
12187         u32 val, major, minor;
12188
12189         /* Use native endian representation */
12190         if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
12191                 return;
12192
12193         major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
12194                 TG3_NVM_HWSB_CFG1_MAJSFT;
12195         minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
12196                 TG3_NVM_HWSB_CFG1_MINSFT;
12197
12198         snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
12199 }
12200
12201 static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
12202 {
12203         u32 offset, major, minor, build;
12204
12205         tp->fw_ver[0] = 's';
12206         tp->fw_ver[1] = 'b';
12207         tp->fw_ver[2] = '\0';
12208
12209         if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
12210                 return;
12211
12212         switch (val & TG3_EEPROM_SB_REVISION_MASK) {
12213         case TG3_EEPROM_SB_REVISION_0:
12214                 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
12215                 break;
12216         case TG3_EEPROM_SB_REVISION_2:
12217                 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
12218                 break;
12219         case TG3_EEPROM_SB_REVISION_3:
12220                 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
12221                 break;
12222         default:
12223                 return;
12224         }
12225
12226         if (tg3_nvram_read(tp, offset, &val))
12227                 return;
12228
12229         build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
12230                 TG3_EEPROM_SB_EDH_BLD_SHFT;
12231         major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
12232                 TG3_EEPROM_SB_EDH_MAJ_SHFT;
12233         minor =  val & TG3_EEPROM_SB_EDH_MIN_MASK;
12234
12235         if (minor > 99 || build > 26)
12236                 return;
12237
12238         snprintf(&tp->fw_ver[2], 30, " v%d.%02d", major, minor);
12239
12240         if (build > 0) {
12241                 tp->fw_ver[8] = 'a' + build - 1;
12242                 tp->fw_ver[9] = '\0';
12243         }
12244 }
12245
12246 static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
12247 {
12248         u32 val, offset, start;
12249         int i, vlen;
12250
12251         for (offset = TG3_NVM_DIR_START;
12252              offset < TG3_NVM_DIR_END;
12253              offset += TG3_NVM_DIRENT_SIZE) {
12254                 if (tg3_nvram_read(tp, offset, &val))
12255                         return;
12256
12257                 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
12258                         break;
12259         }
12260
12261         if (offset == TG3_NVM_DIR_END)
12262                 return;
12263
12264         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
12265                 start = 0x08000000;
12266         else if (tg3_nvram_read(tp, offset - 4, &start))
12267                 return;
12268
12269         if (tg3_nvram_read(tp, offset + 4, &offset) ||
12270             !tg3_fw_img_is_valid(tp, offset) ||
12271             tg3_nvram_read(tp, offset + 8, &val))
12272                 return;
12273
12274         offset += val - start;
12275
12276         vlen = strlen(tp->fw_ver);
12277
12278         tp->fw_ver[vlen++] = ',';
12279         tp->fw_ver[vlen++] = ' ';
12280
12281         for (i = 0; i < 4; i++) {
12282                 __be32 v;
12283                 if (tg3_nvram_read_be32(tp, offset, &v))
12284                         return;
12285
12286                 offset += sizeof(v);
12287
12288                 if (vlen > TG3_VER_SIZE - sizeof(v)) {
12289                         memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
12290                         break;
12291                 }
12292
12293                 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
12294                 vlen += sizeof(v);
12295         }
12296 }
12297
12298 static void __devinit tg3_read_dash_ver(struct tg3 *tp)
12299 {
12300         int vlen;
12301         u32 apedata;
12302
12303         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) ||
12304             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
12305                 return;
12306
12307         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
12308         if (apedata != APE_SEG_SIG_MAGIC)
12309                 return;
12310
12311         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
12312         if (!(apedata & APE_FW_STATUS_READY))
12313                 return;
12314
12315         apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
12316
12317         vlen = strlen(tp->fw_ver);
12318
12319         snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " DASH v%d.%d.%d.%d",
12320                  (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
12321                  (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
12322                  (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
12323                  (apedata & APE_FW_VERSION_BLDMSK));
12324 }
12325
12326 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
12327 {
12328         u32 val;
12329
12330         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) {
12331                 tp->fw_ver[0] = 's';
12332                 tp->fw_ver[1] = 'b';
12333                 tp->fw_ver[2] = '\0';
12334
12335                 return;
12336         }
12337
12338         if (tg3_nvram_read(tp, 0, &val))
12339                 return;
12340
12341         if (val == TG3_EEPROM_MAGIC)
12342                 tg3_read_bc_ver(tp);
12343         else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
12344                 tg3_read_sb_ver(tp, val);
12345         else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
12346                 tg3_read_hwsb_ver(tp);
12347         else
12348                 return;
12349
12350         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12351              (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
12352                 return;
12353
12354         tg3_read_mgmtfw_ver(tp);
12355
12356         tp->fw_ver[TG3_VER_SIZE - 1] = 0;
12357 }
12358
12359 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
12360
12361 static int __devinit tg3_get_invariants(struct tg3 *tp)
12362 {
12363         static struct pci_device_id write_reorder_chipsets[] = {
12364                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12365                              PCI_DEVICE_ID_AMD_FE_GATE_700C) },
12366                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12367                              PCI_DEVICE_ID_AMD_8131_BRIDGE) },
12368                 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
12369                              PCI_DEVICE_ID_VIA_8385_0) },
12370                 { },
12371         };
12372         u32 misc_ctrl_reg;
12373         u32 pci_state_reg, grc_misc_cfg;
12374         u32 val;
12375         u16 pci_cmd;
12376         int err;
12377
12378         /* Force memory write invalidate off.  If we leave it on,
12379          * then on 5700_BX chips we have to enable a workaround.
12380          * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
12381          * to match the cacheline size.  The Broadcom driver have this
12382          * workaround but turns MWI off all the times so never uses
12383          * it.  This seems to suggest that the workaround is insufficient.
12384          */
12385         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12386         pci_cmd &= ~PCI_COMMAND_INVALIDATE;
12387         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12388
12389         /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
12390          * has the register indirect write enable bit set before
12391          * we try to access any of the MMIO registers.  It is also
12392          * critical that the PCI-X hw workaround situation is decided
12393          * before that as well.
12394          */
12395         pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12396                               &misc_ctrl_reg);
12397
12398         tp->pci_chip_rev_id = (misc_ctrl_reg >>
12399                                MISC_HOST_CTRL_CHIPREV_SHIFT);
12400         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
12401                 u32 prod_id_asic_rev;
12402
12403                 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717C ||
12404                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717S ||
12405                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718C ||
12406                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718S)
12407                         pci_read_config_dword(tp->pdev,
12408                                               TG3PCI_GEN2_PRODID_ASICREV,
12409                                               &prod_id_asic_rev);
12410                 else
12411                         pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
12412                                               &prod_id_asic_rev);
12413
12414                 tp->pci_chip_rev_id = prod_id_asic_rev;
12415         }
12416
12417         /* Wrong chip ID in 5752 A0. This code can be removed later
12418          * as A0 is not in production.
12419          */
12420         if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
12421                 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
12422
12423         /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
12424          * we need to disable memory and use config. cycles
12425          * only to access all registers. The 5702/03 chips
12426          * can mistakenly decode the special cycles from the
12427          * ICH chipsets as memory write cycles, causing corruption
12428          * of register and memory space. Only certain ICH bridges
12429          * will drive special cycles with non-zero data during the
12430          * address phase which can fall within the 5703's address
12431          * range. This is not an ICH bug as the PCI spec allows
12432          * non-zero address during special cycles. However, only
12433          * these ICH bridges are known to drive non-zero addresses
12434          * during special cycles.
12435          *
12436          * Since special cycles do not cross PCI bridges, we only
12437          * enable this workaround if the 5703 is on the secondary
12438          * bus of these ICH bridges.
12439          */
12440         if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
12441             (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
12442                 static struct tg3_dev_id {
12443                         u32     vendor;
12444                         u32     device;
12445                         u32     rev;
12446                 } ich_chipsets[] = {
12447                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
12448                           PCI_ANY_ID },
12449                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
12450                           PCI_ANY_ID },
12451                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
12452                           0xa },
12453                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
12454                           PCI_ANY_ID },
12455                         { },
12456                 };
12457                 struct tg3_dev_id *pci_id = &ich_chipsets[0];
12458                 struct pci_dev *bridge = NULL;
12459
12460                 while (pci_id->vendor != 0) {
12461                         bridge = pci_get_device(pci_id->vendor, pci_id->device,
12462                                                 bridge);
12463                         if (!bridge) {
12464                                 pci_id++;
12465                                 continue;
12466                         }
12467                         if (pci_id->rev != PCI_ANY_ID) {
12468                                 if (bridge->revision > pci_id->rev)
12469                                         continue;
12470                         }
12471                         if (bridge->subordinate &&
12472                             (bridge->subordinate->number ==
12473                              tp->pdev->bus->number)) {
12474
12475                                 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
12476                                 pci_dev_put(bridge);
12477                                 break;
12478                         }
12479                 }
12480         }
12481
12482         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
12483                 static struct tg3_dev_id {
12484                         u32     vendor;
12485                         u32     device;
12486                 } bridge_chipsets[] = {
12487                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
12488                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
12489                         { },
12490                 };
12491                 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
12492                 struct pci_dev *bridge = NULL;
12493
12494                 while (pci_id->vendor != 0) {
12495                         bridge = pci_get_device(pci_id->vendor,
12496                                                 pci_id->device,
12497                                                 bridge);
12498                         if (!bridge) {
12499                                 pci_id++;
12500                                 continue;
12501                         }
12502                         if (bridge->subordinate &&
12503                             (bridge->subordinate->number <=
12504                              tp->pdev->bus->number) &&
12505                             (bridge->subordinate->subordinate >=
12506                              tp->pdev->bus->number)) {
12507                                 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
12508                                 pci_dev_put(bridge);
12509                                 break;
12510                         }
12511                 }
12512         }
12513
12514         /* The EPB bridge inside 5714, 5715, and 5780 cannot support
12515          * DMA addresses > 40-bit. This bridge may have other additional
12516          * 57xx devices behind it in some 4-port NIC designs for example.
12517          * Any tg3 device found behind the bridge will also need the 40-bit
12518          * DMA workaround.
12519          */
12520         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
12521             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
12522                 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
12523                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
12524                 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
12525         }
12526         else {
12527                 struct pci_dev *bridge = NULL;
12528
12529                 do {
12530                         bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
12531                                                 PCI_DEVICE_ID_SERVERWORKS_EPB,
12532                                                 bridge);
12533                         if (bridge && bridge->subordinate &&
12534                             (bridge->subordinate->number <=
12535                              tp->pdev->bus->number) &&
12536                             (bridge->subordinate->subordinate >=
12537                              tp->pdev->bus->number)) {
12538                                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
12539                                 pci_dev_put(bridge);
12540                                 break;
12541                         }
12542                 } while (bridge);
12543         }
12544
12545         /* Initialize misc host control in PCI block. */
12546         tp->misc_host_ctrl |= (misc_ctrl_reg &
12547                                MISC_HOST_CTRL_CHIPREV);
12548         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12549                                tp->misc_host_ctrl);
12550
12551         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
12552             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
12553             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
12554                 tp->pdev_peer = tg3_find_peer(tp);
12555
12556         /* Intentionally exclude ASIC_REV_5906 */
12557         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12558             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
12559             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12560             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12561             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12562             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
12563             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
12564                 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
12565
12566         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
12567             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
12568             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
12569             (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
12570             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
12571                 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
12572
12573         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
12574             (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
12575                 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
12576
12577         /* 5700 B0 chips do not support checksumming correctly due
12578          * to hardware bugs.
12579          */
12580         if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
12581                 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
12582         else {
12583                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
12584                 tp->dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
12585                 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
12586                         tp->dev->features |= NETIF_F_IPV6_CSUM;
12587         }
12588
12589         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
12590                 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
12591                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
12592                     GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
12593                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
12594                      tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
12595                      tp->pdev_peer == tp->pdev))
12596                         tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
12597
12598                 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
12599                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12600                         tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
12601                         tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
12602                 } else {
12603                         tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
12604                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
12605                                 ASIC_REV_5750 &&
12606                             tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
12607                                 tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
12608                 }
12609         }
12610
12611         tp->irq_max = 1;
12612
12613 #ifdef TG3_NAPI
12614         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
12615                 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSIX;
12616                 tp->irq_max = TG3_IRQ_MAX_VECS;
12617         }
12618 #endif
12619
12620         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
12621              (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
12622             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
12623                 tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE;
12624
12625         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
12626                               &pci_state_reg);
12627
12628         tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
12629         if (tp->pcie_cap != 0) {
12630                 u16 lnkctl;
12631
12632                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
12633
12634                 pcie_set_readrq(tp->pdev, 4096);
12635
12636                 pci_read_config_word(tp->pdev,
12637                                      tp->pcie_cap + PCI_EXP_LNKCTL,
12638                                      &lnkctl);
12639                 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
12640                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12641                                 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
12642                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12643                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12644                             tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
12645                             tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
12646                                 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
12647                 }
12648         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
12649                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
12650         } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
12651                    (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
12652                 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
12653                 if (!tp->pcix_cap) {
12654                         printk(KERN_ERR PFX "Cannot find PCI-X "
12655                                             "capability, aborting.\n");
12656                         return -EIO;
12657                 }
12658
12659                 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
12660                         tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
12661         }
12662
12663         /* If we have an AMD 762 or VIA K8T800 chipset, write
12664          * reordering to the mailbox registers done by the host
12665          * controller can cause major troubles.  We read back from
12666          * every mailbox register write to force the writes to be
12667          * posted to the chip in order.
12668          */
12669         if (pci_dev_present(write_reorder_chipsets) &&
12670             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
12671                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
12672
12673         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
12674                              &tp->pci_cacheline_sz);
12675         pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
12676                              &tp->pci_lat_timer);
12677         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
12678             tp->pci_lat_timer < 64) {
12679                 tp->pci_lat_timer = 64;
12680                 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
12681                                       tp->pci_lat_timer);
12682         }
12683
12684         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
12685                 /* 5700 BX chips need to have their TX producer index
12686                  * mailboxes written twice to workaround a bug.
12687                  */
12688                 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
12689
12690                 /* If we are in PCI-X mode, enable register write workaround.
12691                  *
12692                  * The workaround is to use indirect register accesses
12693                  * for all chip writes not to mailbox registers.
12694                  */
12695                 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
12696                         u32 pm_reg;
12697
12698                         tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
12699
12700                         /* The chip can have it's power management PCI config
12701                          * space registers clobbered due to this bug.
12702                          * So explicitly force the chip into D0 here.
12703                          */
12704                         pci_read_config_dword(tp->pdev,
12705                                               tp->pm_cap + PCI_PM_CTRL,
12706                                               &pm_reg);
12707                         pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
12708                         pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
12709                         pci_write_config_dword(tp->pdev,
12710                                                tp->pm_cap + PCI_PM_CTRL,
12711                                                pm_reg);
12712
12713                         /* Also, force SERR#/PERR# in PCI command. */
12714                         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12715                         pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
12716                         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12717                 }
12718         }
12719
12720         if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
12721                 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
12722         if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
12723                 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
12724
12725         /* Chip-specific fixup from Broadcom driver */
12726         if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
12727             (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
12728                 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
12729                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
12730         }
12731
12732         /* Default fast path register access methods */
12733         tp->read32 = tg3_read32;
12734         tp->write32 = tg3_write32;
12735         tp->read32_mbox = tg3_read32;
12736         tp->write32_mbox = tg3_write32;
12737         tp->write32_tx_mbox = tg3_write32;
12738         tp->write32_rx_mbox = tg3_write32;
12739
12740         /* Various workaround register access methods */
12741         if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
12742                 tp->write32 = tg3_write_indirect_reg32;
12743         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
12744                  ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
12745                   tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
12746                 /*
12747                  * Back to back register writes can cause problems on these
12748                  * chips, the workaround is to read back all reg writes
12749                  * except those to mailbox regs.
12750                  *
12751                  * See tg3_write_indirect_reg32().
12752                  */
12753                 tp->write32 = tg3_write_flush_reg32;
12754         }
12755
12756         if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
12757             (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
12758                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
12759                 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
12760                         tp->write32_rx_mbox = tg3_write_flush_reg32;
12761         }
12762
12763         if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
12764                 tp->read32 = tg3_read_indirect_reg32;
12765                 tp->write32 = tg3_write_indirect_reg32;
12766                 tp->read32_mbox = tg3_read_indirect_mbox;
12767                 tp->write32_mbox = tg3_write_indirect_mbox;
12768                 tp->write32_tx_mbox = tg3_write_indirect_mbox;
12769                 tp->write32_rx_mbox = tg3_write_indirect_mbox;
12770
12771                 iounmap(tp->regs);
12772                 tp->regs = NULL;
12773
12774                 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12775                 pci_cmd &= ~PCI_COMMAND_MEMORY;
12776                 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12777         }
12778         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12779                 tp->read32_mbox = tg3_read32_mbox_5906;
12780                 tp->write32_mbox = tg3_write32_mbox_5906;
12781                 tp->write32_tx_mbox = tg3_write32_mbox_5906;
12782                 tp->write32_rx_mbox = tg3_write32_mbox_5906;
12783         }
12784
12785         if (tp->write32 == tg3_write_indirect_reg32 ||
12786             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
12787              (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12788               GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
12789                 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
12790
12791         /* Get eeprom hw config before calling tg3_set_power_state().
12792          * In particular, the TG3_FLG2_IS_NIC flag must be
12793          * determined before calling tg3_set_power_state() so that
12794          * we know whether or not to switch out of Vaux power.
12795          * When the flag is set, it means that GPIO1 is used for eeprom
12796          * write protect and also implies that it is a LOM where GPIOs
12797          * are not used to switch power.
12798          */
12799         tg3_get_eeprom_hw_cfg(tp);
12800
12801         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
12802                 /* Allow reads and writes to the
12803                  * APE register and memory space.
12804                  */
12805                 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
12806                                  PCISTATE_ALLOW_APE_SHMEM_WR;
12807                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
12808                                        pci_state_reg);
12809         }
12810
12811         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12812             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12813             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12814             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
12815             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
12816                 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
12817
12818         /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
12819          * GPIO1 driven high will bring 5700's external PHY out of reset.
12820          * It is also used as eeprom write protect on LOMs.
12821          */
12822         tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
12823         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
12824             (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
12825                 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
12826                                        GRC_LCLCTRL_GPIO_OUTPUT1);
12827         /* Unused GPIO3 must be driven as output on 5752 because there
12828          * are no pull-up resistors on unused GPIO pins.
12829          */
12830         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
12831                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
12832
12833         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12834             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
12835                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
12836
12837         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
12838             tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
12839                 /* Turn off the debug UART. */
12840                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
12841                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
12842                         /* Keep VMain power. */
12843                         tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
12844                                               GRC_LCLCTRL_GPIO_OUTPUT0;
12845         }
12846
12847         /* Force the chip into D0. */
12848         err = tg3_set_power_state(tp, PCI_D0);
12849         if (err) {
12850                 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
12851                        pci_name(tp->pdev));
12852                 return err;
12853         }
12854
12855         /* Derive initial jumbo mode from MTU assigned in
12856          * ether_setup() via the alloc_etherdev() call
12857          */
12858         if (tp->dev->mtu > ETH_DATA_LEN &&
12859             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
12860                 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
12861
12862         /* Determine WakeOnLan speed to use. */
12863         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12864             tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12865             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
12866             tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
12867                 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
12868         } else {
12869                 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
12870         }
12871
12872         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12873                 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
12874
12875         /* A few boards don't want Ethernet@WireSpeed phy feature */
12876         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
12877             ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
12878              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
12879              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
12880             (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) ||
12881             (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
12882                 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
12883
12884         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
12885             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
12886                 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
12887         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
12888                 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
12889
12890         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
12891             !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
12892             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
12893             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 &&
12894             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) {
12895                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12896                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
12897                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12898                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
12899                         if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
12900                             tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
12901                                 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
12902                         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
12903                                 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
12904                 } else
12905                         tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
12906         }
12907
12908         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12909             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
12910                 tp->phy_otp = tg3_read_otp_phycfg(tp);
12911                 if (tp->phy_otp == 0)
12912                         tp->phy_otp = TG3_OTP_DEFAULT;
12913         }
12914
12915         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
12916                 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
12917         else
12918                 tp->mi_mode = MAC_MI_MODE_BASE;
12919
12920         tp->coalesce_mode = 0;
12921         if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
12922             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
12923                 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
12924
12925         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12926             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
12927                 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
12928
12929         if ((tp->pci_chip_rev_id == CHIPREV_ID_57780_A1 &&
12930              tr32(RCVLPC_STATS_ENABLE) & RCVLPC_STATSENAB_ASF_FIX) ||
12931             tp->pci_chip_rev_id == CHIPREV_ID_57780_A0)
12932                 tp->tg3_flags3 |= TG3_FLG3_TOGGLE_10_100_L1PLLPD;
12933
12934         err = tg3_mdio_init(tp);
12935         if (err)
12936                 return err;
12937
12938         /* Initialize data/descriptor byte/word swapping. */
12939         val = tr32(GRC_MODE);
12940         val &= GRC_MODE_HOST_STACKUP;
12941         tw32(GRC_MODE, val | tp->grc_mode);
12942
12943         tg3_switch_clocks(tp);
12944
12945         /* Clear this out for sanity. */
12946         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
12947
12948         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
12949                               &pci_state_reg);
12950         if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
12951             (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
12952                 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
12953
12954                 if (chiprevid == CHIPREV_ID_5701_A0 ||
12955                     chiprevid == CHIPREV_ID_5701_B0 ||
12956                     chiprevid == CHIPREV_ID_5701_B2 ||
12957                     chiprevid == CHIPREV_ID_5701_B5) {
12958                         void __iomem *sram_base;
12959
12960                         /* Write some dummy words into the SRAM status block
12961                          * area, see if it reads back correctly.  If the return
12962                          * value is bad, force enable the PCIX workaround.
12963                          */
12964                         sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
12965
12966                         writel(0x00000000, sram_base);
12967                         writel(0x00000000, sram_base + 4);
12968                         writel(0xffffffff, sram_base + 4);
12969                         if (readl(sram_base) != 0x00000000)
12970                                 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
12971                 }
12972         }
12973
12974         udelay(50);
12975         tg3_nvram_init(tp);
12976
12977         grc_misc_cfg = tr32(GRC_MISC_CFG);
12978         grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
12979
12980         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
12981             (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
12982              grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
12983                 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
12984
12985         if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
12986             (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
12987                 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
12988         if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
12989                 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
12990                                       HOSTCC_MODE_CLRTICK_TXBD);
12991
12992                 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
12993                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12994                                        tp->misc_host_ctrl);
12995         }
12996
12997         /* Preserve the APE MAC_MODE bits */
12998         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
12999                 tp->mac_mode = tr32(MAC_MODE) |
13000                                MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
13001         else
13002                 tp->mac_mode = TG3_DEF_MAC_MODE;
13003
13004         /* these are limited to 10/100 only */
13005         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13006              (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
13007             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13008              tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13009              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
13010               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
13011               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
13012             (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13013              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
13014               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
13015               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
13016             tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
13017             (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
13018                 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
13019
13020         err = tg3_phy_probe(tp);
13021         if (err) {
13022                 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
13023                        pci_name(tp->pdev), err);
13024                 /* ... but do not return immediately ... */
13025                 tg3_mdio_fini(tp);
13026         }
13027
13028         tg3_read_partno(tp);
13029         tg3_read_fw_ver(tp);
13030
13031         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
13032                 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
13033         } else {
13034                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13035                         tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
13036                 else
13037                         tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
13038         }
13039
13040         /* 5700 {AX,BX} chips have a broken status block link
13041          * change bit implementation, so we must use the
13042          * status register in those cases.
13043          */
13044         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13045                 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
13046         else
13047                 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
13048
13049         /* The led_ctrl is set during tg3_phy_probe, here we might
13050          * have to force the link status polling mechanism based
13051          * upon subsystem IDs.
13052          */
13053         if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
13054             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13055             !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
13056                 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
13057                                   TG3_FLAG_USE_LINKCHG_REG);
13058         }
13059
13060         /* For all SERDES we poll the MAC status register. */
13061         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
13062                 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
13063         else
13064                 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
13065
13066         tp->rx_offset = NET_IP_ALIGN;
13067         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13068             (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
13069                 tp->rx_offset = 0;
13070
13071         tp->rx_std_max_post = TG3_RX_RING_SIZE;
13072
13073         /* Increment the rx prod index on the rx std ring by at most
13074          * 8 for these chips to workaround hw errata.
13075          */
13076         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13077             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13078             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
13079                 tp->rx_std_max_post = 8;
13080
13081         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
13082                 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
13083                                      PCIE_PWR_MGMT_L1_THRESH_MSK;
13084
13085         return err;
13086 }
13087
13088 #ifdef CONFIG_SPARC
13089 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
13090 {
13091         struct net_device *dev = tp->dev;
13092         struct pci_dev *pdev = tp->pdev;
13093         struct device_node *dp = pci_device_to_OF_node(pdev);
13094         const unsigned char *addr;
13095         int len;
13096
13097         addr = of_get_property(dp, "local-mac-address", &len);
13098         if (addr && len == 6) {
13099                 memcpy(dev->dev_addr, addr, 6);
13100                 memcpy(dev->perm_addr, dev->dev_addr, 6);
13101                 return 0;
13102         }
13103         return -ENODEV;
13104 }
13105
13106 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
13107 {
13108         struct net_device *dev = tp->dev;
13109
13110         memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
13111         memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
13112         return 0;
13113 }
13114 #endif
13115
13116 static int __devinit tg3_get_device_address(struct tg3 *tp)
13117 {
13118         struct net_device *dev = tp->dev;
13119         u32 hi, lo, mac_offset;
13120         int addr_ok = 0;
13121
13122 #ifdef CONFIG_SPARC
13123         if (!tg3_get_macaddr_sparc(tp))
13124                 return 0;
13125 #endif
13126
13127         mac_offset = 0x7c;
13128         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
13129             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13130                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
13131                         mac_offset = 0xcc;
13132                 if (tg3_nvram_lock(tp))
13133                         tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
13134                 else
13135                         tg3_nvram_unlock(tp);
13136         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
13137                 if (tr32(TG3_CPMU_STATUS) & TG3_CPMU_STATUS_PCIE_FUNC)
13138                         mac_offset = 0xcc;
13139         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13140                 mac_offset = 0x10;
13141
13142         /* First try to get it from MAC address mailbox. */
13143         tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
13144         if ((hi >> 16) == 0x484b) {
13145                 dev->dev_addr[0] = (hi >>  8) & 0xff;
13146                 dev->dev_addr[1] = (hi >>  0) & 0xff;
13147
13148                 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
13149                 dev->dev_addr[2] = (lo >> 24) & 0xff;
13150                 dev->dev_addr[3] = (lo >> 16) & 0xff;
13151                 dev->dev_addr[4] = (lo >>  8) & 0xff;
13152                 dev->dev_addr[5] = (lo >>  0) & 0xff;
13153
13154                 /* Some old bootcode may report a 0 MAC address in SRAM */
13155                 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
13156         }
13157         if (!addr_ok) {
13158                 /* Next, try NVRAM. */
13159                 if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) &&
13160                     !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
13161                     !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
13162                         memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
13163                         memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
13164                 }
13165                 /* Finally just fetch it out of the MAC control regs. */
13166                 else {
13167                         hi = tr32(MAC_ADDR_0_HIGH);
13168                         lo = tr32(MAC_ADDR_0_LOW);
13169
13170                         dev->dev_addr[5] = lo & 0xff;
13171                         dev->dev_addr[4] = (lo >> 8) & 0xff;
13172                         dev->dev_addr[3] = (lo >> 16) & 0xff;
13173                         dev->dev_addr[2] = (lo >> 24) & 0xff;
13174                         dev->dev_addr[1] = hi & 0xff;
13175                         dev->dev_addr[0] = (hi >> 8) & 0xff;
13176                 }
13177         }
13178
13179         if (!is_valid_ether_addr(&dev->dev_addr[0])) {
13180 #ifdef CONFIG_SPARC
13181                 if (!tg3_get_default_macaddr_sparc(tp))
13182                         return 0;
13183 #endif
13184                 return -EINVAL;
13185         }
13186         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
13187         return 0;
13188 }
13189
13190 #define BOUNDARY_SINGLE_CACHELINE       1
13191 #define BOUNDARY_MULTI_CACHELINE        2
13192
13193 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
13194 {
13195         int cacheline_size;
13196         u8 byte;
13197         int goal;
13198
13199         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
13200         if (byte == 0)
13201                 cacheline_size = 1024;
13202         else
13203                 cacheline_size = (int) byte * 4;
13204
13205         /* On 5703 and later chips, the boundary bits have no
13206          * effect.
13207          */
13208         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13209             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13210             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13211                 goto out;
13212
13213 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
13214         goal = BOUNDARY_MULTI_CACHELINE;
13215 #else
13216 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
13217         goal = BOUNDARY_SINGLE_CACHELINE;
13218 #else
13219         goal = 0;
13220 #endif
13221 #endif
13222
13223         if (!goal)
13224                 goto out;
13225
13226         /* PCI controllers on most RISC systems tend to disconnect
13227          * when a device tries to burst across a cache-line boundary.
13228          * Therefore, letting tg3 do so just wastes PCI bandwidth.
13229          *
13230          * Unfortunately, for PCI-E there are only limited
13231          * write-side controls for this, and thus for reads
13232          * we will still get the disconnects.  We'll also waste
13233          * these PCI cycles for both read and write for chips
13234          * other than 5700 and 5701 which do not implement the
13235          * boundary bits.
13236          */
13237         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13238             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
13239                 switch (cacheline_size) {
13240                 case 16:
13241                 case 32:
13242                 case 64:
13243                 case 128:
13244                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13245                                 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
13246                                         DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
13247                         } else {
13248                                 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13249                                         DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13250                         }
13251                         break;
13252
13253                 case 256:
13254                         val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
13255                                 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
13256                         break;
13257
13258                 default:
13259                         val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13260                                 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13261                         break;
13262                 }
13263         } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13264                 switch (cacheline_size) {
13265                 case 16:
13266                 case 32:
13267                 case 64:
13268                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13269                                 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13270                                 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
13271                                 break;
13272                         }
13273                         /* fallthrough */
13274                 case 128:
13275                 default:
13276                         val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13277                         val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
13278                         break;
13279                 }
13280         } else {
13281                 switch (cacheline_size) {
13282                 case 16:
13283                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13284                                 val |= (DMA_RWCTRL_READ_BNDRY_16 |
13285                                         DMA_RWCTRL_WRITE_BNDRY_16);
13286                                 break;
13287                         }
13288                         /* fallthrough */
13289                 case 32:
13290                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13291                                 val |= (DMA_RWCTRL_READ_BNDRY_32 |
13292                                         DMA_RWCTRL_WRITE_BNDRY_32);
13293                                 break;
13294                         }
13295                         /* fallthrough */
13296                 case 64:
13297                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13298                                 val |= (DMA_RWCTRL_READ_BNDRY_64 |
13299                                         DMA_RWCTRL_WRITE_BNDRY_64);
13300                                 break;
13301                         }
13302                         /* fallthrough */
13303                 case 128:
13304                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13305                                 val |= (DMA_RWCTRL_READ_BNDRY_128 |
13306                                         DMA_RWCTRL_WRITE_BNDRY_128);
13307                                 break;
13308                         }
13309                         /* fallthrough */
13310                 case 256:
13311                         val |= (DMA_RWCTRL_READ_BNDRY_256 |
13312                                 DMA_RWCTRL_WRITE_BNDRY_256);
13313                         break;
13314                 case 512:
13315                         val |= (DMA_RWCTRL_READ_BNDRY_512 |
13316                                 DMA_RWCTRL_WRITE_BNDRY_512);
13317                         break;
13318                 case 1024:
13319                 default:
13320                         val |= (DMA_RWCTRL_READ_BNDRY_1024 |
13321                                 DMA_RWCTRL_WRITE_BNDRY_1024);
13322                         break;
13323                 }
13324         }
13325
13326 out:
13327         return val;
13328 }
13329
13330 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
13331 {
13332         struct tg3_internal_buffer_desc test_desc;
13333         u32 sram_dma_descs;
13334         int i, ret;
13335
13336         sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
13337
13338         tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
13339         tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
13340         tw32(RDMAC_STATUS, 0);
13341         tw32(WDMAC_STATUS, 0);
13342
13343         tw32(BUFMGR_MODE, 0);
13344         tw32(FTQ_RESET, 0);
13345
13346         test_desc.addr_hi = ((u64) buf_dma) >> 32;
13347         test_desc.addr_lo = buf_dma & 0xffffffff;
13348         test_desc.nic_mbuf = 0x00002100;
13349         test_desc.len = size;
13350
13351         /*
13352          * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
13353          * the *second* time the tg3 driver was getting loaded after an
13354          * initial scan.
13355          *
13356          * Broadcom tells me:
13357          *   ...the DMA engine is connected to the GRC block and a DMA
13358          *   reset may affect the GRC block in some unpredictable way...
13359          *   The behavior of resets to individual blocks has not been tested.
13360          *
13361          * Broadcom noted the GRC reset will also reset all sub-components.
13362          */
13363         if (to_device) {
13364                 test_desc.cqid_sqid = (13 << 8) | 2;
13365
13366                 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
13367                 udelay(40);
13368         } else {
13369                 test_desc.cqid_sqid = (16 << 8) | 7;
13370
13371                 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
13372                 udelay(40);
13373         }
13374         test_desc.flags = 0x00000005;
13375
13376         for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
13377                 u32 val;
13378
13379                 val = *(((u32 *)&test_desc) + i);
13380                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
13381                                        sram_dma_descs + (i * sizeof(u32)));
13382                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
13383         }
13384         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
13385
13386         if (to_device) {
13387                 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
13388         } else {
13389                 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
13390         }
13391
13392         ret = -ENODEV;
13393         for (i = 0; i < 40; i++) {
13394                 u32 val;
13395
13396                 if (to_device)
13397                         val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
13398                 else
13399                         val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
13400                 if ((val & 0xffff) == sram_dma_descs) {
13401                         ret = 0;
13402                         break;
13403                 }
13404
13405                 udelay(100);
13406         }
13407
13408         return ret;
13409 }
13410
13411 #define TEST_BUFFER_SIZE        0x2000
13412
13413 static int __devinit tg3_test_dma(struct tg3 *tp)
13414 {
13415         dma_addr_t buf_dma;
13416         u32 *buf, saved_dma_rwctrl;
13417         int ret;
13418
13419         buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
13420         if (!buf) {
13421                 ret = -ENOMEM;
13422                 goto out_nofree;
13423         }
13424
13425         tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
13426                           (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
13427
13428         tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
13429
13430         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13431                 /* DMA read watermark not used on PCIE */
13432                 tp->dma_rwctrl |= 0x00180000;
13433         } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
13434                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
13435                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
13436                         tp->dma_rwctrl |= 0x003f0000;
13437                 else
13438                         tp->dma_rwctrl |= 0x003f000f;
13439         } else {
13440                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13441                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
13442                         u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
13443                         u32 read_water = 0x7;
13444
13445                         /* If the 5704 is behind the EPB bridge, we can
13446                          * do the less restrictive ONE_DMA workaround for
13447                          * better performance.
13448                          */
13449                         if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
13450                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13451                                 tp->dma_rwctrl |= 0x8000;
13452                         else if (ccval == 0x6 || ccval == 0x7)
13453                                 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
13454
13455                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
13456                                 read_water = 4;
13457                         /* Set bit 23 to enable PCIX hw bug fix */
13458                         tp->dma_rwctrl |=
13459                                 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
13460                                 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
13461                                 (1 << 23);
13462                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
13463                         /* 5780 always in PCIX mode */
13464                         tp->dma_rwctrl |= 0x00144000;
13465                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
13466                         /* 5714 always in PCIX mode */
13467                         tp->dma_rwctrl |= 0x00148000;
13468                 } else {
13469                         tp->dma_rwctrl |= 0x001b000f;
13470                 }
13471         }
13472
13473         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13474             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13475                 tp->dma_rwctrl &= 0xfffffff0;
13476
13477         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13478             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
13479                 /* Remove this if it causes problems for some boards. */
13480                 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
13481
13482                 /* On 5700/5701 chips, we need to set this bit.
13483                  * Otherwise the chip will issue cacheline transactions
13484                  * to streamable DMA memory with not all the byte
13485                  * enables turned on.  This is an error on several
13486                  * RISC PCI controllers, in particular sparc64.
13487                  *
13488                  * On 5703/5704 chips, this bit has been reassigned
13489                  * a different meaning.  In particular, it is used
13490                  * on those chips to enable a PCI-X workaround.
13491                  */
13492                 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
13493         }
13494
13495         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13496
13497 #if 0
13498         /* Unneeded, already done by tg3_get_invariants.  */
13499         tg3_switch_clocks(tp);
13500 #endif
13501
13502         ret = 0;
13503         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13504             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
13505                 goto out;
13506
13507         /* It is best to perform DMA test with maximum write burst size
13508          * to expose the 5700/5701 write DMA bug.
13509          */
13510         saved_dma_rwctrl = tp->dma_rwctrl;
13511         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13512         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13513
13514         while (1) {
13515                 u32 *p = buf, i;
13516
13517                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
13518                         p[i] = i;
13519
13520                 /* Send the buffer to the chip. */
13521                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
13522                 if (ret) {
13523                         printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
13524                         break;
13525                 }
13526
13527 #if 0
13528                 /* validate data reached card RAM correctly. */
13529                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
13530                         u32 val;
13531                         tg3_read_mem(tp, 0x2100 + (i*4), &val);
13532                         if (le32_to_cpu(val) != p[i]) {
13533                                 printk(KERN_ERR "  tg3_test_dma()  Card buffer corrupted on write! (%d != %d)\n", val, i);
13534                                 /* ret = -ENODEV here? */
13535                         }
13536                         p[i] = 0;
13537                 }
13538 #endif
13539                 /* Now read it back. */
13540                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
13541                 if (ret) {
13542                         printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
13543
13544                         break;
13545                 }
13546
13547                 /* Verify it. */
13548                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
13549                         if (p[i] == i)
13550                                 continue;
13551
13552                         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
13553                             DMA_RWCTRL_WRITE_BNDRY_16) {
13554                                 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13555                                 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
13556                                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13557                                 break;
13558                         } else {
13559                                 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
13560                                 ret = -ENODEV;
13561                                 goto out;
13562                         }
13563                 }
13564
13565                 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
13566                         /* Success. */
13567                         ret = 0;
13568                         break;
13569                 }
13570         }
13571         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
13572             DMA_RWCTRL_WRITE_BNDRY_16) {
13573                 static struct pci_device_id dma_wait_state_chipsets[] = {
13574                         { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
13575                                      PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
13576                         { },
13577                 };
13578
13579                 /* DMA test passed without adjusting DMA boundary,
13580                  * now look for chipsets that are known to expose the
13581                  * DMA bug without failing the test.
13582                  */
13583                 if (pci_dev_present(dma_wait_state_chipsets)) {
13584                         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13585                         tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
13586                 }
13587                 else
13588                         /* Safe to use the calculated DMA boundary. */
13589                         tp->dma_rwctrl = saved_dma_rwctrl;
13590
13591                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13592         }
13593
13594 out:
13595         pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
13596 out_nofree:
13597         return ret;
13598 }
13599
13600 static void __devinit tg3_init_link_config(struct tg3 *tp)
13601 {
13602         tp->link_config.advertising =
13603                 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
13604                  ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
13605                  ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
13606                  ADVERTISED_Autoneg | ADVERTISED_MII);
13607         tp->link_config.speed = SPEED_INVALID;
13608         tp->link_config.duplex = DUPLEX_INVALID;
13609         tp->link_config.autoneg = AUTONEG_ENABLE;
13610         tp->link_config.active_speed = SPEED_INVALID;
13611         tp->link_config.active_duplex = DUPLEX_INVALID;
13612         tp->link_config.phy_is_low_power = 0;
13613         tp->link_config.orig_speed = SPEED_INVALID;
13614         tp->link_config.orig_duplex = DUPLEX_INVALID;
13615         tp->link_config.orig_autoneg = AUTONEG_INVALID;
13616 }
13617
13618 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
13619 {
13620         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS &&
13621             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) {
13622                 tp->bufmgr_config.mbuf_read_dma_low_water =
13623                         DEFAULT_MB_RDMA_LOW_WATER_5705;
13624                 tp->bufmgr_config.mbuf_mac_rx_low_water =
13625                         DEFAULT_MB_MACRX_LOW_WATER_5705;
13626                 tp->bufmgr_config.mbuf_high_water =
13627                         DEFAULT_MB_HIGH_WATER_5705;
13628                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13629                         tp->bufmgr_config.mbuf_mac_rx_low_water =
13630                                 DEFAULT_MB_MACRX_LOW_WATER_5906;
13631                         tp->bufmgr_config.mbuf_high_water =
13632                                 DEFAULT_MB_HIGH_WATER_5906;
13633                 }
13634
13635                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
13636                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
13637                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
13638                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
13639                 tp->bufmgr_config.mbuf_high_water_jumbo =
13640                         DEFAULT_MB_HIGH_WATER_JUMBO_5780;
13641         } else {
13642                 tp->bufmgr_config.mbuf_read_dma_low_water =
13643                         DEFAULT_MB_RDMA_LOW_WATER;
13644                 tp->bufmgr_config.mbuf_mac_rx_low_water =
13645                         DEFAULT_MB_MACRX_LOW_WATER;
13646                 tp->bufmgr_config.mbuf_high_water =
13647                         DEFAULT_MB_HIGH_WATER;
13648
13649                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
13650                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
13651                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
13652                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
13653                 tp->bufmgr_config.mbuf_high_water_jumbo =
13654                         DEFAULT_MB_HIGH_WATER_JUMBO;
13655         }
13656
13657         tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
13658         tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
13659 }
13660
13661 static char * __devinit tg3_phy_string(struct tg3 *tp)
13662 {
13663         switch (tp->phy_id & PHY_ID_MASK) {
13664         case PHY_ID_BCM5400:    return "5400";
13665         case PHY_ID_BCM5401:    return "5401";
13666         case PHY_ID_BCM5411:    return "5411";
13667         case PHY_ID_BCM5701:    return "5701";
13668         case PHY_ID_BCM5703:    return "5703";
13669         case PHY_ID_BCM5704:    return "5704";
13670         case PHY_ID_BCM5705:    return "5705";
13671         case PHY_ID_BCM5750:    return "5750";
13672         case PHY_ID_BCM5752:    return "5752";
13673         case PHY_ID_BCM5714:    return "5714";
13674         case PHY_ID_BCM5780:    return "5780";
13675         case PHY_ID_BCM5755:    return "5755";
13676         case PHY_ID_BCM5787:    return "5787";
13677         case PHY_ID_BCM5784:    return "5784";
13678         case PHY_ID_BCM5756:    return "5722/5756";
13679         case PHY_ID_BCM5906:    return "5906";
13680         case PHY_ID_BCM5761:    return "5761";
13681         case PHY_ID_BCM8002:    return "8002/serdes";
13682         case 0:                 return "serdes";
13683         default:                return "unknown";
13684         }
13685 }
13686
13687 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
13688 {
13689         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13690                 strcpy(str, "PCI Express");
13691                 return str;
13692         } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
13693                 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
13694
13695                 strcpy(str, "PCIX:");
13696
13697                 if ((clock_ctrl == 7) ||
13698                     ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
13699                      GRC_MISC_CFG_BOARD_ID_5704CIOBE))
13700                         strcat(str, "133MHz");
13701                 else if (clock_ctrl == 0)
13702                         strcat(str, "33MHz");
13703                 else if (clock_ctrl == 2)
13704                         strcat(str, "50MHz");
13705                 else if (clock_ctrl == 4)
13706                         strcat(str, "66MHz");
13707                 else if (clock_ctrl == 6)
13708                         strcat(str, "100MHz");
13709         } else {
13710                 strcpy(str, "PCI:");
13711                 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
13712                         strcat(str, "66MHz");
13713                 else
13714                         strcat(str, "33MHz");
13715         }
13716         if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
13717                 strcat(str, ":32-bit");
13718         else
13719                 strcat(str, ":64-bit");
13720         return str;
13721 }
13722
13723 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
13724 {
13725         struct pci_dev *peer;
13726         unsigned int func, devnr = tp->pdev->devfn & ~7;
13727
13728         for (func = 0; func < 8; func++) {
13729                 peer = pci_get_slot(tp->pdev->bus, devnr | func);
13730                 if (peer && peer != tp->pdev)
13731                         break;
13732                 pci_dev_put(peer);
13733         }
13734         /* 5704 can be configured in single-port mode, set peer to
13735          * tp->pdev in that case.
13736          */
13737         if (!peer) {
13738                 peer = tp->pdev;
13739                 return peer;
13740         }
13741
13742         /*
13743          * We don't need to keep the refcount elevated; there's no way
13744          * to remove one half of this device without removing the other
13745          */
13746         pci_dev_put(peer);
13747
13748         return peer;
13749 }
13750
13751 static void __devinit tg3_init_coal(struct tg3 *tp)
13752 {
13753         struct ethtool_coalesce *ec = &tp->coal;
13754
13755         memset(ec, 0, sizeof(*ec));
13756         ec->cmd = ETHTOOL_GCOALESCE;
13757         ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
13758         ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
13759         ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
13760         ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
13761         ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
13762         ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
13763         ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
13764         ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
13765         ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
13766
13767         if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
13768                                  HOSTCC_MODE_CLRTICK_TXBD)) {
13769                 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
13770                 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
13771                 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
13772                 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
13773         }
13774
13775         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
13776                 ec->rx_coalesce_usecs_irq = 0;
13777                 ec->tx_coalesce_usecs_irq = 0;
13778                 ec->stats_block_coalesce_usecs = 0;
13779         }
13780 }
13781
13782 static const struct net_device_ops tg3_netdev_ops = {
13783         .ndo_open               = tg3_open,
13784         .ndo_stop               = tg3_close,
13785         .ndo_start_xmit         = tg3_start_xmit,
13786         .ndo_get_stats          = tg3_get_stats,
13787         .ndo_validate_addr      = eth_validate_addr,
13788         .ndo_set_multicast_list = tg3_set_rx_mode,
13789         .ndo_set_mac_address    = tg3_set_mac_addr,
13790         .ndo_do_ioctl           = tg3_ioctl,
13791         .ndo_tx_timeout         = tg3_tx_timeout,
13792         .ndo_change_mtu         = tg3_change_mtu,
13793 #if TG3_VLAN_TAG_USED
13794         .ndo_vlan_rx_register   = tg3_vlan_rx_register,
13795 #endif
13796 #ifdef CONFIG_NET_POLL_CONTROLLER
13797         .ndo_poll_controller    = tg3_poll_controller,
13798 #endif
13799 };
13800
13801 static const struct net_device_ops tg3_netdev_ops_dma_bug = {
13802         .ndo_open               = tg3_open,
13803         .ndo_stop               = tg3_close,
13804         .ndo_start_xmit         = tg3_start_xmit_dma_bug,
13805         .ndo_get_stats          = tg3_get_stats,
13806         .ndo_validate_addr      = eth_validate_addr,
13807         .ndo_set_multicast_list = tg3_set_rx_mode,
13808         .ndo_set_mac_address    = tg3_set_mac_addr,
13809         .ndo_do_ioctl           = tg3_ioctl,
13810         .ndo_tx_timeout         = tg3_tx_timeout,
13811         .ndo_change_mtu         = tg3_change_mtu,
13812 #if TG3_VLAN_TAG_USED
13813         .ndo_vlan_rx_register   = tg3_vlan_rx_register,
13814 #endif
13815 #ifdef CONFIG_NET_POLL_CONTROLLER
13816         .ndo_poll_controller    = tg3_poll_controller,
13817 #endif
13818 };
13819
13820 static int __devinit tg3_init_one(struct pci_dev *pdev,
13821                                   const struct pci_device_id *ent)
13822 {
13823         static int tg3_version_printed = 0;
13824         struct net_device *dev;
13825         struct tg3 *tp;
13826         int i, err, pm_cap;
13827         u32 sndmbx, rcvmbx, intmbx;
13828         char str[40];
13829         u64 dma_mask, persist_dma_mask;
13830
13831         if (tg3_version_printed++ == 0)
13832                 printk(KERN_INFO "%s", version);
13833
13834         err = pci_enable_device(pdev);
13835         if (err) {
13836                 printk(KERN_ERR PFX "Cannot enable PCI device, "
13837                        "aborting.\n");
13838                 return err;
13839         }
13840
13841         err = pci_request_regions(pdev, DRV_MODULE_NAME);
13842         if (err) {
13843                 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
13844                        "aborting.\n");
13845                 goto err_out_disable_pdev;
13846         }
13847
13848         pci_set_master(pdev);
13849
13850         /* Find power-management capability. */
13851         pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
13852         if (pm_cap == 0) {
13853                 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
13854                        "aborting.\n");
13855                 err = -EIO;
13856                 goto err_out_free_res;
13857         }
13858
13859         dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
13860         if (!dev) {
13861                 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
13862                 err = -ENOMEM;
13863                 goto err_out_free_res;
13864         }
13865
13866         SET_NETDEV_DEV(dev, &pdev->dev);
13867
13868 #if TG3_VLAN_TAG_USED
13869         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
13870 #endif
13871
13872         tp = netdev_priv(dev);
13873         tp->pdev = pdev;
13874         tp->dev = dev;
13875         tp->pm_cap = pm_cap;
13876         tp->rx_mode = TG3_DEF_RX_MODE;
13877         tp->tx_mode = TG3_DEF_TX_MODE;
13878
13879         if (tg3_debug > 0)
13880                 tp->msg_enable = tg3_debug;
13881         else
13882                 tp->msg_enable = TG3_DEF_MSG_ENABLE;
13883
13884         /* The word/byte swap controls here control register access byte
13885          * swapping.  DMA data byte swapping is controlled in the GRC_MODE
13886          * setting below.
13887          */
13888         tp->misc_host_ctrl =
13889                 MISC_HOST_CTRL_MASK_PCI_INT |
13890                 MISC_HOST_CTRL_WORD_SWAP |
13891                 MISC_HOST_CTRL_INDIR_ACCESS |
13892                 MISC_HOST_CTRL_PCISTATE_RW;
13893
13894         /* The NONFRM (non-frame) byte/word swap controls take effect
13895          * on descriptor entries, anything which isn't packet data.
13896          *
13897          * The StrongARM chips on the board (one for tx, one for rx)
13898          * are running in big-endian mode.
13899          */
13900         tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
13901                         GRC_MODE_WSWAP_NONFRM_DATA);
13902 #ifdef __BIG_ENDIAN
13903         tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
13904 #endif
13905         spin_lock_init(&tp->lock);
13906         spin_lock_init(&tp->indirect_lock);
13907         INIT_WORK(&tp->reset_task, tg3_reset_task);
13908
13909         tp->regs = pci_ioremap_bar(pdev, BAR_0);
13910         if (!tp->regs) {
13911                 printk(KERN_ERR PFX "Cannot map device registers, "
13912                        "aborting.\n");
13913                 err = -ENOMEM;
13914                 goto err_out_free_dev;
13915         }
13916
13917         tg3_init_link_config(tp);
13918
13919         tp->rx_pending = TG3_DEF_RX_RING_PENDING;
13920         tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
13921
13922         intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
13923         rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
13924         sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
13925         for (i = 0; i < TG3_IRQ_MAX_VECS; i++) {
13926                 struct tg3_napi *tnapi = &tp->napi[i];
13927
13928                 tnapi->tp = tp;
13929                 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
13930
13931                 tnapi->int_mbox = intmbx;
13932                 if (i < 4)
13933                         intmbx += 0x8;
13934                 else
13935                         intmbx += 0x4;
13936
13937                 tnapi->consmbox = rcvmbx;
13938                 tnapi->prodmbox = sndmbx;
13939
13940                 if (i)
13941                         tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
13942                 else
13943                         tnapi->coal_now = HOSTCC_MODE_NOW;
13944
13945                 if (!(tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX))
13946                         break;
13947
13948                 /*
13949                  * If we support MSIX, we'll be using RSS.  If we're using
13950                  * RSS, the first vector only handles link interrupts and the
13951                  * remaining vectors handle rx and tx interrupts.  Reuse the
13952                  * mailbox values for the next iteration.  The values we setup
13953                  * above are still useful for the single vectored mode.
13954                  */
13955                 if (!i)
13956                         continue;
13957
13958                 rcvmbx += 0x8;
13959
13960                 if (sndmbx & 0x4)
13961                         sndmbx -= 0x4;
13962                 else
13963                         sndmbx += 0xc;
13964         }
13965
13966         netif_napi_add(dev, &tp->napi[0].napi, tg3_poll, 64);
13967         dev->ethtool_ops = &tg3_ethtool_ops;
13968         dev->watchdog_timeo = TG3_TX_TIMEOUT;
13969         dev->irq = pdev->irq;
13970
13971         err = tg3_get_invariants(tp);
13972         if (err) {
13973                 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
13974                        "aborting.\n");
13975                 goto err_out_iounmap;
13976         }
13977
13978         if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13979             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13980                 dev->netdev_ops = &tg3_netdev_ops;
13981         else
13982                 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
13983
13984
13985         /* The EPB bridge inside 5714, 5715, and 5780 and any
13986          * device behind the EPB cannot support DMA addresses > 40-bit.
13987          * On 64-bit systems with IOMMU, use 40-bit dma_mask.
13988          * On 64-bit systems without IOMMU, use 64-bit dma_mask and
13989          * do DMA address check in tg3_start_xmit().
13990          */
13991         if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
13992                 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
13993         else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
13994                 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
13995 #ifdef CONFIG_HIGHMEM
13996                 dma_mask = DMA_BIT_MASK(64);
13997 #endif
13998         } else
13999                 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
14000
14001         /* Configure DMA attributes. */
14002         if (dma_mask > DMA_BIT_MASK(32)) {
14003                 err = pci_set_dma_mask(pdev, dma_mask);
14004                 if (!err) {
14005                         dev->features |= NETIF_F_HIGHDMA;
14006                         err = pci_set_consistent_dma_mask(pdev,
14007                                                           persist_dma_mask);
14008                         if (err < 0) {
14009                                 printk(KERN_ERR PFX "Unable to obtain 64 bit "
14010                                        "DMA for consistent allocations\n");
14011                                 goto err_out_iounmap;
14012                         }
14013                 }
14014         }
14015         if (err || dma_mask == DMA_BIT_MASK(32)) {
14016                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
14017                 if (err) {
14018                         printk(KERN_ERR PFX "No usable DMA configuration, "
14019                                "aborting.\n");
14020                         goto err_out_iounmap;
14021                 }
14022         }
14023
14024         tg3_init_bufmgr_config(tp);
14025
14026         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
14027                 tp->fw_needed = FIRMWARE_TG3;
14028
14029         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
14030                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
14031         }
14032         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
14033             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
14034             tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
14035             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
14036             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
14037                 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
14038         } else {
14039                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG;
14040                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
14041                         tp->fw_needed = FIRMWARE_TG3TSO5;
14042                 else
14043                         tp->fw_needed = FIRMWARE_TG3TSO;
14044         }
14045
14046         /* TSO is on by default on chips that support hardware TSO.
14047          * Firmware TSO on older chips gives lower performance, so it
14048          * is off by default, but can be enabled using ethtool.
14049          */
14050         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
14051                 if (dev->features & NETIF_F_IP_CSUM)
14052                         dev->features |= NETIF_F_TSO;
14053                 if ((dev->features & NETIF_F_IPV6_CSUM) &&
14054                     (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2))
14055                         dev->features |= NETIF_F_TSO6;
14056                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
14057                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
14058                      GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
14059                         GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
14060                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
14061                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
14062                         dev->features |= NETIF_F_TSO_ECN;
14063         }
14064
14065
14066         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
14067             !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
14068             !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
14069                 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
14070                 tp->rx_pending = 63;
14071         }
14072
14073         err = tg3_get_device_address(tp);
14074         if (err) {
14075                 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
14076                        "aborting.\n");
14077                 goto err_out_fw;
14078         }
14079
14080         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
14081                 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
14082                 if (!tp->aperegs) {
14083                         printk(KERN_ERR PFX "Cannot map APE registers, "
14084                                "aborting.\n");
14085                         err = -ENOMEM;
14086                         goto err_out_fw;
14087                 }
14088
14089                 tg3_ape_lock_init(tp);
14090
14091                 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
14092                         tg3_read_dash_ver(tp);
14093         }
14094
14095         /*
14096          * Reset chip in case UNDI or EFI driver did not shutdown
14097          * DMA self test will enable WDMAC and we'll see (spurious)
14098          * pending DMA on the PCI bus at that point.
14099          */
14100         if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
14101             (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
14102                 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
14103                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14104         }
14105
14106         err = tg3_test_dma(tp);
14107         if (err) {
14108                 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
14109                 goto err_out_apeunmap;
14110         }
14111
14112         /* flow control autonegotiation is default behavior */
14113         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
14114         tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
14115
14116         tg3_init_coal(tp);
14117
14118         pci_set_drvdata(pdev, dev);
14119
14120         err = register_netdev(dev);
14121         if (err) {
14122                 printk(KERN_ERR PFX "Cannot register net device, "
14123                        "aborting.\n");
14124                 goto err_out_apeunmap;
14125         }
14126
14127         printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
14128                dev->name,
14129                tp->board_part_number,
14130                tp->pci_chip_rev_id,
14131                tg3_bus_string(tp, str),
14132                dev->dev_addr);
14133
14134         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
14135                 printk(KERN_INFO
14136                        "%s: attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
14137                        tp->dev->name,
14138                        tp->mdio_bus->phy_map[PHY_ADDR]->drv->name,
14139                        dev_name(&tp->mdio_bus->phy_map[PHY_ADDR]->dev));
14140         else
14141                 printk(KERN_INFO
14142                        "%s: attached PHY is %s (%s Ethernet) (WireSpeed[%d])\n",
14143                        tp->dev->name, tg3_phy_string(tp),
14144                        ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
14145                         ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
14146                          "10/100/1000Base-T")),
14147                        (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0);
14148
14149         printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
14150                dev->name,
14151                (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
14152                (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
14153                (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
14154                (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
14155                (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
14156         printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
14157                dev->name, tp->dma_rwctrl,
14158                (pdev->dma_mask == DMA_BIT_MASK(32)) ? 32 :
14159                 (((u64) pdev->dma_mask == DMA_BIT_MASK(40)) ? 40 : 64));
14160
14161         return 0;
14162
14163 err_out_apeunmap:
14164         if (tp->aperegs) {
14165                 iounmap(tp->aperegs);
14166                 tp->aperegs = NULL;
14167         }
14168
14169 err_out_fw:
14170         if (tp->fw)
14171                 release_firmware(tp->fw);
14172
14173 err_out_iounmap:
14174         if (tp->regs) {
14175                 iounmap(tp->regs);
14176                 tp->regs = NULL;
14177         }
14178
14179 err_out_free_dev:
14180         free_netdev(dev);
14181
14182 err_out_free_res:
14183         pci_release_regions(pdev);
14184
14185 err_out_disable_pdev:
14186         pci_disable_device(pdev);
14187         pci_set_drvdata(pdev, NULL);
14188         return err;
14189 }
14190
14191 static void __devexit tg3_remove_one(struct pci_dev *pdev)
14192 {
14193         struct net_device *dev = pci_get_drvdata(pdev);
14194
14195         if (dev) {
14196                 struct tg3 *tp = netdev_priv(dev);
14197
14198                 if (tp->fw)
14199                         release_firmware(tp->fw);
14200
14201                 flush_scheduled_work();
14202
14203                 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
14204                         tg3_phy_fini(tp);
14205                         tg3_mdio_fini(tp);
14206                 }
14207
14208                 unregister_netdev(dev);
14209                 if (tp->aperegs) {
14210                         iounmap(tp->aperegs);
14211                         tp->aperegs = NULL;
14212                 }
14213                 if (tp->regs) {
14214                         iounmap(tp->regs);
14215                         tp->regs = NULL;
14216                 }
14217                 free_netdev(dev);
14218                 pci_release_regions(pdev);
14219                 pci_disable_device(pdev);
14220                 pci_set_drvdata(pdev, NULL);
14221         }
14222 }
14223
14224 static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
14225 {
14226         struct net_device *dev = pci_get_drvdata(pdev);
14227         struct tg3 *tp = netdev_priv(dev);
14228         pci_power_t target_state;
14229         int err;
14230
14231         /* PCI register 4 needs to be saved whether netif_running() or not.
14232          * MSI address and data need to be saved if using MSI and
14233          * netif_running().
14234          */
14235         pci_save_state(pdev);
14236
14237         if (!netif_running(dev))
14238                 return 0;
14239
14240         flush_scheduled_work();
14241         tg3_phy_stop(tp);
14242         tg3_netif_stop(tp);
14243
14244         del_timer_sync(&tp->timer);
14245
14246         tg3_full_lock(tp, 1);
14247         tg3_disable_ints(tp);
14248         tg3_full_unlock(tp);
14249
14250         netif_device_detach(dev);
14251
14252         tg3_full_lock(tp, 0);
14253         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14254         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
14255         tg3_full_unlock(tp);
14256
14257         target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
14258
14259         err = tg3_set_power_state(tp, target_state);
14260         if (err) {
14261                 int err2;
14262
14263                 tg3_full_lock(tp, 0);
14264
14265                 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
14266                 err2 = tg3_restart_hw(tp, 1);
14267                 if (err2)
14268                         goto out;
14269
14270                 tp->timer.expires = jiffies + tp->timer_offset;
14271                 add_timer(&tp->timer);
14272
14273                 netif_device_attach(dev);
14274                 tg3_netif_start(tp);
14275
14276 out:
14277                 tg3_full_unlock(tp);
14278
14279                 if (!err2)
14280                         tg3_phy_start(tp);
14281         }
14282
14283         return err;
14284 }
14285
14286 static int tg3_resume(struct pci_dev *pdev)
14287 {
14288         struct net_device *dev = pci_get_drvdata(pdev);
14289         struct tg3 *tp = netdev_priv(dev);
14290         int err;
14291
14292         pci_restore_state(tp->pdev);
14293
14294         if (!netif_running(dev))
14295                 return 0;
14296
14297         err = tg3_set_power_state(tp, PCI_D0);
14298         if (err)
14299                 return err;
14300
14301         netif_device_attach(dev);
14302
14303         tg3_full_lock(tp, 0);
14304
14305         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
14306         err = tg3_restart_hw(tp, 1);
14307         if (err)
14308                 goto out;
14309
14310         tp->timer.expires = jiffies + tp->timer_offset;
14311         add_timer(&tp->timer);
14312
14313         tg3_netif_start(tp);
14314
14315 out:
14316         tg3_full_unlock(tp);
14317
14318         if (!err)
14319                 tg3_phy_start(tp);
14320
14321         return err;
14322 }
14323
14324 static struct pci_driver tg3_driver = {
14325         .name           = DRV_MODULE_NAME,
14326         .id_table       = tg3_pci_tbl,
14327         .probe          = tg3_init_one,
14328         .remove         = __devexit_p(tg3_remove_one),
14329         .suspend        = tg3_suspend,
14330         .resume         = tg3_resume
14331 };
14332
14333 static int __init tg3_init(void)
14334 {
14335         return pci_register_driver(&tg3_driver);
14336 }
14337
14338 static void __exit tg3_cleanup(void)
14339 {
14340         pci_unregister_driver(&tg3_driver);
14341 }
14342
14343 module_init(tg3_init);
14344 module_exit(tg3_cleanup);