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   1 /*
   2  * tg3.c: Broadcom Tigon3 ethernet driver.
   3  *
   4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
   5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
   6  * Copyright (C) 2004 Sun Microsystems Inc.
   7  * Copyright (C) 2005-2007 Broadcom Corporation.
   8  *
   9  * Firmware is:
  10  *      Derived from proprietary unpublished source code,
  11  *      Copyright (C) 2000-2003 Broadcom Corporation.
  12  *
  13  *      Permission is hereby granted for the distribution of this firmware
  14  *      data in hexadecimal or equivalent format, provided this copyright
  15  *      notice is accompanying it.
  16  */
  17
  18
  19 #include <linux/module.h>
  20 #include <linux/moduleparam.h>
  21 #include <linux/kernel.h>
  22 #include <linux/types.h>
  23 #include <linux/compiler.h>
  24 #include <linux/slab.h>
  25 #include <linux/delay.h>
  26 #include <linux/in.h>
  27 #include <linux/init.h>
  28 #include <linux/ioport.h>
  29 #include <linux/pci.h>
  30 #include <linux/netdevice.h>
  31 #include <linux/etherdevice.h>
  32 #include <linux/skbuff.h>
  33 #include <linux/ethtool.h>
  34 #include <linux/mii.h>
  35 #include <linux/if_vlan.h>
  36 #include <linux/ip.h>
  37 #include <linux/tcp.h>
  38 #include <linux/workqueue.h>
  39 #include <linux/prefetch.h>
  40 #include <linux/dma-mapping.h>
  41
  42 #include <net/checksum.h>
  43 #include <net/ip.h>
  44
  45 #include <asm/system.h>
  46 #include <asm/io.h>
  47 #include <asm/byteorder.h>
  48 #include <asm/uaccess.h>
  49
  50 #ifdef CONFIG_SPARC64
  51 #include <asm/idprom.h>
  52 #include <asm/oplib.h>
  53 #include <asm/pbm.h>
  54 #endif
  55
  56 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  57 #define TG3_VLAN_TAG_USED 1
  58 #else
  59 #define TG3_VLAN_TAG_USED 0
  60 #endif
  61
  62 #define TG3_TSO_SUPPORT 1
  63
  64 #include "tg3.h"
  65
  66 #define DRV_MODULE_NAME         "tg3"
  67 #define PFX DRV_MODULE_NAME     ": "
  68 #define DRV_MODULE_VERSION      "3.75"
  69 #define DRV_MODULE_RELDATE      "March 23, 2007"
  70
  71 #define TG3_DEF_MAC_MODE        0
  72 #define TG3_DEF_RX_MODE         0
  73 #define TG3_DEF_TX_MODE         0
  74 #define TG3_DEF_MSG_ENABLE        \
  75         (NETIF_MSG_DRV          | \
  76          NETIF_MSG_PROBE        | \
  77          NETIF_MSG_LINK         | \
  78          NETIF_MSG_TIMER        | \
  79          NETIF_MSG_IFDOWN       | \
  80          NETIF_MSG_IFUP         | \
  81          NETIF_MSG_RX_ERR       | \
  82          NETIF_MSG_TX_ERR)
  83
  84 /* length of time before we decide the hardware is borked,
  85  * and dev->tx_timeout() should be called to fix the problem
  86  */
  87 #define TG3_TX_TIMEOUT                  (5 * HZ)
  88
  89 /* hardware minimum and maximum for a single frame's data payload */
  90 #define TG3_MIN_MTU                     60
  91 #define TG3_MAX_MTU(tp) \
  92         ((tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) ? 9000 : 1500)
  93
  94 /* These numbers seem to be hard coded in the NIC firmware somehow.
  95  * You can't change the ring sizes, but you can change where you place
  96  * them in the NIC onboard memory.
  97  */
  98 #define TG3_RX_RING_SIZE                512
  99 #define TG3_DEF_RX_RING_PENDING         200
 100 #define TG3_RX_JUMBO_RING_SIZE          256
 101 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
 102
 103 /* Do not place this n-ring entries value into the tp struct itself,
 104  * we really want to expose these constants to GCC so that modulo et
 105  * al.  operations are done with shifts and masks instead of with
 106  * hw multiply/modulo instructions.  Another solution would be to
 107  * replace things like '% foo' with '& (foo - 1)'.
 108  */
 109 #define TG3_RX_RCB_RING_SIZE(tp)        \
 110         ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ?  512 : 1024)
 111
 112 #define TG3_TX_RING_SIZE                512
 113 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
 114
 115 #define TG3_RX_RING_BYTES       (sizeof(struct tg3_rx_buffer_desc) * \
 116                                  TG3_RX_RING_SIZE)
 117 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
 118                                  TG3_RX_JUMBO_RING_SIZE)
 119 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
 120                                    TG3_RX_RCB_RING_SIZE(tp))
 121 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
 122                                  TG3_TX_RING_SIZE)
 123 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
 124
 125 #define RX_PKT_BUF_SZ           (1536 + tp->rx_offset + 64)
 126 #define RX_JUMBO_PKT_BUF_SZ     (9046 + tp->rx_offset + 64)
 127
 128 /* minimum number of free TX descriptors required to wake up TX process */
 129 #define TG3_TX_WAKEUP_THRESH(tp)                ((tp)->tx_pending / 4)
 130
 131 /* number of ETHTOOL_GSTATS u64's */
 132 #define TG3_NUM_STATS           (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
 133
 134 #define TG3_NUM_TEST            6
 135
 136 static char version[] __devinitdata =
 137         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
 138
 139 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
 140 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
 141 MODULE_LICENSE("GPL");
 142 MODULE_VERSION(DRV_MODULE_VERSION);
 143
 144 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
 145 module_param(tg3_debug, int, 0);
 146 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
 147
 148 static struct pci_device_id tg3_pci_tbl[] = {
 149         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
 150         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
 151         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
 152         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
 153         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
 154         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
 155         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
 156         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
 157         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
 158         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
 159         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
 160         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
 161         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
 162         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
 163         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
 164         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
 165         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
 166         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
 167         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
 168         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
 169         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
 170         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
 171         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
 172         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
 173         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
 174         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
 175         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
 176         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
 177         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
 178         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
 179         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
 180         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
 181         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
 182         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
 183         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
 184         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
 185         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
 186         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
 187         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
 188         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
 189         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
 190         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
 191         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
 192         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
 193         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
 194         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
 195         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
 196         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
 197         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
 198         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
 199         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
 200         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
 201         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
 202         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
 203         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
 204         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
 205         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
 206         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
 207         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
 208         {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
 209         {}
 210 };
 211
 212 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
 213
 214 static const struct {
 215         const char string[ETH_GSTRING_LEN];
 216 } ethtool_stats_keys[TG3_NUM_STATS] = {
 217         { "rx_octets" },
 218         { "rx_fragments" },
 219         { "rx_ucast_packets" },
 220         { "rx_mcast_packets" },
 221         { "rx_bcast_packets" },
 222         { "rx_fcs_errors" },
 223         { "rx_align_errors" },
 224         { "rx_xon_pause_rcvd" },
 225         { "rx_xoff_pause_rcvd" },
 226         { "rx_mac_ctrl_rcvd" },
 227         { "rx_xoff_entered" },
 228         { "rx_frame_too_long_errors" },
 229         { "rx_jabbers" },
 230         { "rx_undersize_packets" },
 231         { "rx_in_length_errors" },
 232         { "rx_out_length_errors" },
 233         { "rx_64_or_less_octet_packets" },
 234         { "rx_65_to_127_octet_packets" },
 235         { "rx_128_to_255_octet_packets" },
 236         { "rx_256_to_511_octet_packets" },
 237         { "rx_512_to_1023_octet_packets" },
 238         { "rx_1024_to_1522_octet_packets" },
 239         { "rx_1523_to_2047_octet_packets" },
 240         { "rx_2048_to_4095_octet_packets" },
 241         { "rx_4096_to_8191_octet_packets" },
 242         { "rx_8192_to_9022_octet_packets" },
 243
 244         { "tx_octets" },
 245         { "tx_collisions" },
 246
 247         { "tx_xon_sent" },
 248         { "tx_xoff_sent" },
 249         { "tx_flow_control" },
 250         { "tx_mac_errors" },
 251         { "tx_single_collisions" },
 252         { "tx_mult_collisions" },
 253         { "tx_deferred" },
 254         { "tx_excessive_collisions" },
 255         { "tx_late_collisions" },
 256         { "tx_collide_2times" },
 257         { "tx_collide_3times" },
 258         { "tx_collide_4times" },
 259         { "tx_collide_5times" },
 260         { "tx_collide_6times" },
 261         { "tx_collide_7times" },
 262         { "tx_collide_8times" },
 263         { "tx_collide_9times" },
 264         { "tx_collide_10times" },
 265         { "tx_collide_11times" },
 266         { "tx_collide_12times" },
 267         { "tx_collide_13times" },
 268         { "tx_collide_14times" },
 269         { "tx_collide_15times" },
 270         { "tx_ucast_packets" },
 271         { "tx_mcast_packets" },
 272         { "tx_bcast_packets" },
 273         { "tx_carrier_sense_errors" },
 274         { "tx_discards" },
 275         { "tx_errors" },
 276
 277         { "dma_writeq_full" },
 278         { "dma_write_prioq_full" },
 279         { "rxbds_empty" },
 280         { "rx_discards" },
 281         { "rx_errors" },
 282         { "rx_threshold_hit" },
 283
 284         { "dma_readq_full" },
 285         { "dma_read_prioq_full" },
 286         { "tx_comp_queue_full" },
 287
 288         { "ring_set_send_prod_index" },
 289         { "ring_status_update" },
 290         { "nic_irqs" },
 291         { "nic_avoided_irqs" },
 292         { "nic_tx_threshold_hit" }
 293 };
 294
 295 static const struct {
 296         const char string[ETH_GSTRING_LEN];
 297 } ethtool_test_keys[TG3_NUM_TEST] = {
 298         { "nvram test     (online) " },
 299         { "link test      (online) " },
 300         { "register test  (offline)" },
 301         { "memory test    (offline)" },
 302         { "loopback test  (offline)" },
 303         { "interrupt test (offline)" },
 304 };
 305
 306 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
 307 {
 308         writel(val, tp->regs + off);
 309 }
 310
 311 static u32 tg3_read32(struct tg3 *tp, u32 off)
 312 {
 313         return (readl(tp->regs + off));
 314 }
 315
 316 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
 317 {
 318         unsigned long flags;
 319
 320         spin_lock_irqsave(&tp->indirect_lock, flags);
 321         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 322         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 323         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 324 }
 325
 326 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
 327 {
 328         writel(val, tp->regs + off);
 329         readl(tp->regs + off);
 330 }
 331
 332 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
 333 {
 334         unsigned long flags;
 335         u32 val;
 336
 337         spin_lock_irqsave(&tp->indirect_lock, flags);
 338         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 339         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 340         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 341         return val;
 342 }
 343
 344 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
 345 {
 346         unsigned long flags;
 347
 348         if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
 349                 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
 350                                        TG3_64BIT_REG_LOW, val);
 351                 return;
 352         }
 353         if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
 354                 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
 355                                        TG3_64BIT_REG_LOW, val);
 356                 return;
 357         }
 358
 359         spin_lock_irqsave(&tp->indirect_lock, flags);
 360         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 361         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 362         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 363
 364         /* In indirect mode when disabling interrupts, we also need
 365          * to clear the interrupt bit in the GRC local ctrl register.
 366          */
 367         if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
 368             (val == 0x1)) {
 369                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
 370                                        tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
 371         }
 372 }
 373
 374 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
 375 {
 376         unsigned long flags;
 377         u32 val;
 378
 379         spin_lock_irqsave(&tp->indirect_lock, flags);
 380         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 381         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 382         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 383         return val;
 384 }
 385
 386 /* usec_wait specifies the wait time in usec when writing to certain registers
 387  * where it is unsafe to read back the register without some delay.
 388  * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
 389  * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
 390  */
 391 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
 392 {
 393         if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
 394             (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 395                 /* Non-posted methods */
 396                 tp->write32(tp, off, val);
 397         else {
 398                 /* Posted method */
 399                 tg3_write32(tp, off, val);
 400                 if (usec_wait)
 401                         udelay(usec_wait);
 402                 tp->read32(tp, off);
 403         }
 404         /* Wait again after the read for the posted method to guarantee that
 405          * the wait time is met.
 406          */
 407         if (usec_wait)
 408                 udelay(usec_wait);
 409 }
 410
 411 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
 412 {
 413         tp->write32_mbox(tp, off, val);
 414         if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
 415             !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 416                 tp->read32_mbox(tp, off);
 417 }
 418
 419 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
 420 {
 421         void __iomem *mbox = tp->regs + off;
 422         writel(val, mbox);
 423         if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
 424                 writel(val, mbox);
 425         if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
 426                 readl(mbox);
 427 }
 428
 429 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
 430 {
 431         return (readl(tp->regs + off + GRCMBOX_BASE));
 432 }
 433
 434 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
 435 {
 436         writel(val, tp->regs + off + GRCMBOX_BASE);
 437 }
 438
 439 #define tw32_mailbox(reg, val)  tp->write32_mbox(tp, reg, val)
 440 #define tw32_mailbox_f(reg, val)        tw32_mailbox_flush(tp, (reg), (val))
 441 #define tw32_rx_mbox(reg, val)  tp->write32_rx_mbox(tp, reg, val)
 442 #define tw32_tx_mbox(reg, val)  tp->write32_tx_mbox(tp, reg, val)
 443 #define tr32_mailbox(reg)       tp->read32_mbox(tp, reg)
 444
 445 #define tw32(reg,val)           tp->write32(tp, reg, val)
 446 #define tw32_f(reg,val)         _tw32_flush(tp,(reg),(val), 0)
 447 #define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
 448 #define tr32(reg)               tp->read32(tp, reg)
 449
 450 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
 451 {
 452         unsigned long flags;
 453
 454         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 455             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
 456                 return;
 457
 458         spin_lock_irqsave(&tp->indirect_lock, flags);
 459         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 460                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 461                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 462
 463                 /* Always leave this as zero. */
 464                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 465         } else {
 466                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 467                 tw32_f(TG3PCI_MEM_WIN_DATA, val);
 468
 469                 /* Always leave this as zero. */
 470                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 471         }
 472         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 473 }
 474
 475 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
 476 {
 477         unsigned long flags;
 478
 479         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 480             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
 481                 *val = 0;
 482                 return;
 483         }
 484
 485         spin_lock_irqsave(&tp->indirect_lock, flags);
 486         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 487                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 488                 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 489
 490                 /* Always leave this as zero. */
 491                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 492         } else {
 493                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 494                 *val = tr32(TG3PCI_MEM_WIN_DATA);
 495
 496                 /* Always leave this as zero. */
 497                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 498         }
 499         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 500 }
 501
 502 static void tg3_disable_ints(struct tg3 *tp)
 503 {
 504         tw32(TG3PCI_MISC_HOST_CTRL,
 505              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
 506         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
 507 }
 508
 509 static inline void tg3_cond_int(struct tg3 *tp)
 510 {
 511         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 512             (tp->hw_status->status & SD_STATUS_UPDATED))
 513                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
 514         else
 515                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 516                      (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
 517 }
 518
 519 static void tg3_enable_ints(struct tg3 *tp)
 520 {
 521         tp->irq_sync = 0;
 522         wmb();
 523
 524         tw32(TG3PCI_MISC_HOST_CTRL,
 525              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
 526         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
 527                        (tp->last_tag << 24));
 528         if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
 529                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
 530                                (tp->last_tag << 24));
 531         tg3_cond_int(tp);
 532 }
 533
 534 static inline unsigned int tg3_has_work(struct tg3 *tp)
 535 {
 536         struct tg3_hw_status *sblk = tp->hw_status;
 537         unsigned int work_exists = 0;
 538
 539         /* check for phy events */
 540         if (!(tp->tg3_flags &
 541               (TG3_FLAG_USE_LINKCHG_REG |
 542                TG3_FLAG_POLL_SERDES))) {
 543                 if (sblk->status & SD_STATUS_LINK_CHG)
 544                         work_exists = 1;
 545         }
 546         /* check for RX/TX work to do */
 547         if (sblk->idx[0].tx_consumer != tp->tx_cons ||
 548             sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
 549                 work_exists = 1;
 550
 551         return work_exists;
 552 }
 553
 554 /* tg3_restart_ints
 555  *  similar to tg3_enable_ints, but it accurately determines whether there
 556  *  is new work pending and can return without flushing the PIO write
 557  *  which reenables interrupts
 558  */
 559 static void tg3_restart_ints(struct tg3 *tp)
 560 {
 561         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
 562                      tp->last_tag << 24);
 563         mmiowb();
 564
 565         /* When doing tagged status, this work check is unnecessary.
 566          * The last_tag we write above tells the chip which piece of
 567          * work we've completed.
 568          */
 569         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 570             tg3_has_work(tp))
 571                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 572                      (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
 573 }
 574
 575 static inline void tg3_netif_stop(struct tg3 *tp)
 576 {
 577         tp->dev->trans_start = jiffies; /* prevent tx timeout */
 578         netif_poll_disable(tp->dev);
 579         netif_tx_disable(tp->dev);
 580 }
 581
 582 static inline void tg3_netif_start(struct tg3 *tp)
 583 {
 584         netif_wake_queue(tp->dev);
 585         /* NOTE: unconditional netif_wake_queue is only appropriate
 586          * so long as all callers are assured to have free tx slots
 587          * (such as after tg3_init_hw)
 588          */
 589         netif_poll_enable(tp->dev);
 590         tp->hw_status->status |= SD_STATUS_UPDATED;
 591         tg3_enable_ints(tp);
 592 }
 593
 594 static void tg3_switch_clocks(struct tg3 *tp)
 595 {
 596         u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
 597         u32 orig_clock_ctrl;
 598
 599         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
 600                 return;
 601
 602         orig_clock_ctrl = clock_ctrl;
 603         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
 604                        CLOCK_CTRL_CLKRUN_OENABLE |
 605                        0x1f);
 606         tp->pci_clock_ctrl = clock_ctrl;
 607
 608         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
 609                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
 610                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
 611                                     clock_ctrl | CLOCK_CTRL_625_CORE, 40);
 612                 }
 613         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
 614                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 615                             clock_ctrl |
 616                             (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
 617                             40);
 618                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 619                             clock_ctrl | (CLOCK_CTRL_ALTCLK),
 620                             40);
 621         }
 622         tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
 623 }
 624
 625 #define PHY_BUSY_LOOPS  5000
 626
 627 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
 628 {
 629         u32 frame_val;
 630         unsigned int loops;
 631         int ret;
 632
 633         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 634                 tw32_f(MAC_MI_MODE,
 635                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 636                 udelay(80);
 637         }
 638
 639         *val = 0x0;
 640
 641         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
 642                       MI_COM_PHY_ADDR_MASK);
 643         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 644                       MI_COM_REG_ADDR_MASK);
 645         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
 646
 647         tw32_f(MAC_MI_COM, frame_val);
 648
 649         loops = PHY_BUSY_LOOPS;
 650         while (loops != 0) {
 651                 udelay(10);
 652                 frame_val = tr32(MAC_MI_COM);
 653
 654                 if ((frame_val & MI_COM_BUSY) == 0) {
 655                         udelay(5);
 656                         frame_val = tr32(MAC_MI_COM);
 657                         break;
 658                 }
 659                 loops -= 1;
 660         }
 661
 662         ret = -EBUSY;
 663         if (loops != 0) {
 664                 *val = frame_val & MI_COM_DATA_MASK;
 665                 ret = 0;
 666         }
 667
 668         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 669                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 670                 udelay(80);
 671         }
 672
 673         return ret;
 674 }
 675
 676 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
 677 {
 678         u32 frame_val;
 679         unsigned int loops;
 680         int ret;
 681
 682         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
 683             (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
 684                 return 0;
 685
 686         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 687                 tw32_f(MAC_MI_MODE,
 688                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 689                 udelay(80);
 690         }
 691
 692         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
 693                       MI_COM_PHY_ADDR_MASK);
 694         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 695                       MI_COM_REG_ADDR_MASK);
 696         frame_val |= (val & MI_COM_DATA_MASK);
 697         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
 698
 699         tw32_f(MAC_MI_COM, frame_val);
 700
 701         loops = PHY_BUSY_LOOPS;
 702         while (loops != 0) {
 703                 udelay(10);
 704                 frame_val = tr32(MAC_MI_COM);
 705                 if ((frame_val & MI_COM_BUSY) == 0) {
 706                         udelay(5);
 707                         frame_val = tr32(MAC_MI_COM);
 708                         break;
 709                 }
 710                 loops -= 1;
 711         }
 712
 713         ret = -EBUSY;
 714         if (loops != 0)
 715                 ret = 0;
 716
 717         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 718                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 719                 udelay(80);
 720         }
 721
 722         return ret;
 723 }
 724
 725 static void tg3_phy_set_wirespeed(struct tg3 *tp)
 726 {
 727         u32 val;
 728
 729         if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
 730                 return;
 731
 732         if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
 733             !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
 734                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
 735                              (val | (1 << 15) | (1 << 4)));
 736 }
 737
 738 static int tg3_bmcr_reset(struct tg3 *tp)
 739 {
 740         u32 phy_control;
 741         int limit, err;
 742
 743         /* OK, reset it, and poll the BMCR_RESET bit until it
 744          * clears or we time out.
 745          */
 746         phy_control = BMCR_RESET;
 747         err = tg3_writephy(tp, MII_BMCR, phy_control);
 748         if (err != 0)
 749                 return -EBUSY;
 750
 751         limit = 5000;
 752         while (limit--) {
 753                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
 754                 if (err != 0)
 755                         return -EBUSY;
 756
 757                 if ((phy_control & BMCR_RESET) == 0) {
 758                         udelay(40);
 759                         break;
 760                 }
 761                 udelay(10);
 762         }
 763         if (limit <= 0)
 764                 return -EBUSY;
 765
 766         return 0;
 767 }
 768
 769 static int tg3_wait_macro_done(struct tg3 *tp)
 770 {
 771         int limit = 100;
 772
 773         while (limit--) {
 774                 u32 tmp32;
 775
 776                 if (!tg3_readphy(tp, 0x16, &tmp32)) {
 777                         if ((tmp32 & 0x1000) == 0)
 778                                 break;
 779                 }
 780         }
 781         if (limit <= 0)
 782                 return -EBUSY;
 783
 784         return 0;
 785 }
 786
 787 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
 788 {
 789         static const u32 test_pat[4][6] = {
 790         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
 791         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
 792         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
 793         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
 794         };
 795         int chan;
 796
 797         for (chan = 0; chan < 4; chan++) {
 798                 int i;
 799
 800                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
 801                              (chan * 0x2000) | 0x0200);
 802                 tg3_writephy(tp, 0x16, 0x0002);
 803
 804                 for (i = 0; i < 6; i++)
 805                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
 806                                      test_pat[chan][i]);
 807
 808                 tg3_writephy(tp, 0x16, 0x0202);
 809                 if (tg3_wait_macro_done(tp)) {
 810                         *resetp = 1;
 811                         return -EBUSY;
 812                 }
 813
 814                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
 815                              (chan * 0x2000) | 0x0200);
 816                 tg3_writephy(tp, 0x16, 0x0082);
 817                 if (tg3_wait_macro_done(tp)) {
 818                         *resetp = 1;
 819                         return -EBUSY;
 820                 }
 821
 822                 tg3_writephy(tp, 0x16, 0x0802);
 823                 if (tg3_wait_macro_done(tp)) {
 824                         *resetp = 1;
 825                         return -EBUSY;
 826                 }
 827
 828                 for (i = 0; i < 6; i += 2) {
 829                         u32 low, high;
 830
 831                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
 832                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
 833                             tg3_wait_macro_done(tp)) {
 834                                 *resetp = 1;
 835                                 return -EBUSY;
 836                         }
 837                         low &= 0x7fff;
 838                         high &= 0x000f;
 839                         if (low != test_pat[chan][i] ||
 840                             high != test_pat[chan][i+1]) {
 841                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
 842                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
 843                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
 844
 845                                 return -EBUSY;
 846                         }
 847                 }
 848         }
 849
 850         return 0;
 851 }
 852
 853 static int tg3_phy_reset_chanpat(struct tg3 *tp)
 854 {
 855         int chan;
 856
 857         for (chan = 0; chan < 4; chan++) {
 858                 int i;
 859
 860                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
 861                              (chan * 0x2000) | 0x0200);
 862                 tg3_writephy(tp, 0x16, 0x0002);
 863                 for (i = 0; i < 6; i++)
 864                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
 865                 tg3_writephy(tp, 0x16, 0x0202);
 866                 if (tg3_wait_macro_done(tp))
 867                         return -EBUSY;
 868         }
 869
 870         return 0;
 871 }
 872
 873 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
 874 {
 875         u32 reg32, phy9_orig;
 876         int retries, do_phy_reset, err;
 877
 878         retries = 10;
 879         do_phy_reset = 1;
 880         do {
 881                 if (do_phy_reset) {
 882                         err = tg3_bmcr_reset(tp);
 883                         if (err)
 884                                 return err;
 885                         do_phy_reset = 0;
 886                 }
 887
 888                 /* Disable transmitter and interrupt.  */
 889                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
 890                         continue;
 891
 892                 reg32 |= 0x3000;
 893                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
 894
 895                 /* Set full-duplex, 1000 mbps.  */
 896                 tg3_writephy(tp, MII_BMCR,
 897                              BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
 898
 899                 /* Set to master mode.  */
 900                 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
 901                         continue;
 902
 903                 tg3_writephy(tp, MII_TG3_CTRL,
 904                              (MII_TG3_CTRL_AS_MASTER |
 905                               MII_TG3_CTRL_ENABLE_AS_MASTER));
 906
 907                 /* Enable SM_DSP_CLOCK and 6dB.  */
 908                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
 909
 910                 /* Block the PHY control access.  */
 911                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
 912                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
 913
 914                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
 915                 if (!err)
 916                         break;
 917         } while (--retries);
 918
 919         err = tg3_phy_reset_chanpat(tp);
 920         if (err)
 921                 return err;
 922
 923         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
 924         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
 925
 926         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
 927         tg3_writephy(tp, 0x16, 0x0000);
 928
 929         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
 930             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
 931                 /* Set Extended packet length bit for jumbo frames */
 932                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
 933         }
 934         else {
 935                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
 936         }
 937
 938         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
 939
 940         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
 941                 reg32 &= ~0x3000;
 942                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
 943         } else if (!err)
 944                 err = -EBUSY;
 945
 946         return err;
 947 }
 948
 949 static void tg3_link_report(struct tg3 *);
 950
 951 /* This will reset the tigon3 PHY if there is no valid
 952  * link unless the FORCE argument is non-zero.
 953  */
 954 static int tg3_phy_reset(struct tg3 *tp)
 955 {
 956         u32 phy_status;
 957         int err;
 958
 959         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
 960                 u32 val;
 961
 962                 val = tr32(GRC_MISC_CFG);
 963                 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
 964                 udelay(40);
 965         }
 966         err  = tg3_readphy(tp, MII_BMSR, &phy_status);
 967         err |= tg3_readphy(tp, MII_BMSR, &phy_status);
 968         if (err != 0)
 969                 return -EBUSY;
 970
 971         if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
 972                 netif_carrier_off(tp->dev);
 973                 tg3_link_report(tp);
 974         }
 975
 976         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
 977             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
 978             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
 979                 err = tg3_phy_reset_5703_4_5(tp);
 980                 if (err)
 981                         return err;
 982                 goto out;
 983         }
 984
 985         err = tg3_bmcr_reset(tp);
 986         if (err)
 987                 return err;
 988
 989 out:
 990         if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
 991                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
 992                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
 993                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
 994                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
 995                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
 996                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
 997         }
 998         if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
 999                 tg3_writephy(tp, 0x1c, 0x8d68);
1000                 tg3_writephy(tp, 0x1c, 0x8d68);
1001         }
1002         if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1003                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1004                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1005                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1006                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1007                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1008                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1009                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1010                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1011         }
1012         else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1013                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1014                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1015                 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1016                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1017                         tg3_writephy(tp, MII_TG3_TEST1,
1018                                      MII_TG3_TEST1_TRIM_EN | 0x4);
1019                 } else
1020                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
1021                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1022         }
1023         /* Set Extended packet length bit (bit 14) on all chips that */
1024         /* support jumbo frames */
1025         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1026                 /* Cannot do read-modify-write on 5401 */
1027                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1028         } else if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1029                 u32 phy_reg;
1030
1031                 /* Set bit 14 with read-modify-write to preserve other bits */
1032                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1033                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1034                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1035         }
1036
1037         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1038          * jumbo frames transmission.
1039          */
1040         if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1041                 u32 phy_reg;
1042
1043                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
1044                     tg3_writephy(tp, MII_TG3_EXT_CTRL,
1045                                  phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1046         }
1047
1048         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1049                 u32 phy_reg;
1050
1051                 /* adjust output voltage */
1052                 tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x12);
1053
1054                 if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &phy_reg)) {
1055                         u32 phy_reg2;
1056
1057                         tg3_writephy(tp, MII_TG3_EPHY_TEST,
1058                                      phy_reg | MII_TG3_EPHY_SHADOW_EN);
1059                         /* Enable auto-MDIX */
1060                         if (!tg3_readphy(tp, 0x10, &phy_reg2))
1061                                 tg3_writephy(tp, 0x10, phy_reg2 | 0x4000);
1062                         tg3_writephy(tp, MII_TG3_EPHY_TEST, phy_reg);
1063                 }
1064         }
1065
1066         tg3_phy_set_wirespeed(tp);
1067         return 0;
1068 }
1069
1070 static void tg3_frob_aux_power(struct tg3 *tp)
1071 {
1072         struct tg3 *tp_peer = tp;
1073
1074         if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
1075                 return;
1076
1077         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
1078             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
1079                 struct net_device *dev_peer;
1080
1081                 dev_peer = pci_get_drvdata(tp->pdev_peer);
1082                 /* remove_one() may have been run on the peer. */
1083                 if (!dev_peer)
1084                         tp_peer = tp;
1085                 else
1086                         tp_peer = netdev_priv(dev_peer);
1087         }
1088
1089         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1090             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
1091             (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1092             (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
1093                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1094                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1095                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1096                                     (GRC_LCLCTRL_GPIO_OE0 |
1097                                      GRC_LCLCTRL_GPIO_OE1 |
1098                                      GRC_LCLCTRL_GPIO_OE2 |
1099                                      GRC_LCLCTRL_GPIO_OUTPUT0 |
1100                                      GRC_LCLCTRL_GPIO_OUTPUT1),
1101                                     100);
1102                 } else {
1103                         u32 no_gpio2;
1104                         u32 grc_local_ctrl = 0;
1105
1106                         if (tp_peer != tp &&
1107                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1108                                 return;
1109
1110                         /* Workaround to prevent overdrawing Amps. */
1111                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
1112                             ASIC_REV_5714) {
1113                                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
1114                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1115                                             grc_local_ctrl, 100);
1116                         }
1117
1118                         /* On 5753 and variants, GPIO2 cannot be used. */
1119                         no_gpio2 = tp->nic_sram_data_cfg &
1120                                     NIC_SRAM_DATA_CFG_NO_GPIO2;
1121
1122                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
1123                                          GRC_LCLCTRL_GPIO_OE1 |
1124                                          GRC_LCLCTRL_GPIO_OE2 |
1125                                          GRC_LCLCTRL_GPIO_OUTPUT1 |
1126                                          GRC_LCLCTRL_GPIO_OUTPUT2;
1127                         if (no_gpio2) {
1128                                 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
1129                                                     GRC_LCLCTRL_GPIO_OUTPUT2);
1130                         }
1131                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1132                                                     grc_local_ctrl, 100);
1133
1134                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
1135
1136                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1137                                                     grc_local_ctrl, 100);
1138
1139                         if (!no_gpio2) {
1140                                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
1141                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1142                                             grc_local_ctrl, 100);
1143                         }
1144                 }
1145         } else {
1146                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
1147                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
1148                         if (tp_peer != tp &&
1149                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1150                                 return;
1151
1152                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1153                                     (GRC_LCLCTRL_GPIO_OE1 |
1154                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1155
1156                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1157                                     GRC_LCLCTRL_GPIO_OE1, 100);
1158
1159                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1160                                     (GRC_LCLCTRL_GPIO_OE1 |
1161                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1162                 }
1163         }
1164 }
1165
1166 static int tg3_setup_phy(struct tg3 *, int);
1167
1168 #define RESET_KIND_SHUTDOWN     0
1169 #define RESET_KIND_INIT         1
1170 #define RESET_KIND_SUSPEND      2
1171
1172 static void tg3_write_sig_post_reset(struct tg3 *, int);
1173 static int tg3_halt_cpu(struct tg3 *, u32);
1174 static int tg3_nvram_lock(struct tg3 *);
1175 static void tg3_nvram_unlock(struct tg3 *);
1176
1177 static void tg3_power_down_phy(struct tg3 *tp)
1178 {
1179         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
1180                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1181                         u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
1182                         u32 serdes_cfg = tr32(MAC_SERDES_CFG);
1183
1184                         sg_dig_ctrl |=
1185                                 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
1186                         tw32(SG_DIG_CTRL, sg_dig_ctrl);
1187                         tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
1188                 }
1189                 return;
1190         }
1191
1192         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1193                 u32 val;
1194
1195                 tg3_bmcr_reset(tp);
1196                 val = tr32(GRC_MISC_CFG);
1197                 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
1198                 udelay(40);
1199                 return;
1200         } else {
1201                 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1202                              MII_TG3_EXT_CTRL_FORCE_LED_OFF);
1203                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x01b2);
1204         }
1205
1206         /* The PHY should not be powered down on some chips because
1207          * of bugs.
1208          */
1209         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1210             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1211             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
1212              (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
1213                 return;
1214         tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
1215 }
1216
1217 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
1218 {
1219         u32 misc_host_ctrl;
1220         u16 power_control, power_caps;
1221         int pm = tp->pm_cap;
1222
1223         /* Make sure register accesses (indirect or otherwise)
1224          * will function correctly.
1225          */
1226         pci_write_config_dword(tp->pdev,
1227                                TG3PCI_MISC_HOST_CTRL,
1228                                tp->misc_host_ctrl);
1229
1230         pci_read_config_word(tp->pdev,
1231                              pm + PCI_PM_CTRL,
1232                              &power_control);
1233         power_control |= PCI_PM_CTRL_PME_STATUS;
1234         power_control &= ~(PCI_PM_CTRL_STATE_MASK);
1235         switch (state) {
1236         case PCI_D0:
1237                 power_control |= 0;
1238                 pci_write_config_word(tp->pdev,
1239                                       pm + PCI_PM_CTRL,
1240                                       power_control);
1241                 udelay(100);    /* Delay after power state change */
1242
1243                 /* Switch out of Vaux if it is a NIC */
1244                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
1245                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
1246
1247                 return 0;
1248
1249         case PCI_D1:
1250                 power_control |= 1;
1251                 break;
1252
1253         case PCI_D2:
1254                 power_control |= 2;
1255                 break;
1256
1257         case PCI_D3hot:
1258                 power_control |= 3;
1259                 break;
1260
1261         default:
1262                 printk(KERN_WARNING PFX "%s: Invalid power state (%d) "
1263                        "requested.\n",
1264                        tp->dev->name, state);
1265                 return -EINVAL;
1266         };
1267
1268         power_control |= PCI_PM_CTRL_PME_ENABLE;
1269
1270         misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
1271         tw32(TG3PCI_MISC_HOST_CTRL,
1272              misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
1273
1274         if (tp->link_config.phy_is_low_power == 0) {
1275                 tp->link_config.phy_is_low_power = 1;
1276                 tp->link_config.orig_speed = tp->link_config.speed;
1277                 tp->link_config.orig_duplex = tp->link_config.duplex;
1278                 tp->link_config.orig_autoneg = tp->link_config.autoneg;
1279         }
1280
1281         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
1282                 tp->link_config.speed = SPEED_10;
1283                 tp->link_config.duplex = DUPLEX_HALF;
1284                 tp->link_config.autoneg = AUTONEG_ENABLE;
1285                 tg3_setup_phy(tp, 0);
1286         }
1287
1288         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1289                 u32 val;
1290
1291                 val = tr32(GRC_VCPU_EXT_CTRL);
1292                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
1293         } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
1294                 int i;
1295                 u32 val;
1296
1297                 for (i = 0; i < 200; i++) {
1298                         tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
1299                         if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
1300                                 break;
1301                         msleep(1);
1302                 }
1303         }
1304         tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
1305                                              WOL_DRV_STATE_SHUTDOWN |
1306                                              WOL_DRV_WOL | WOL_SET_MAGIC_PKT);
1307
1308         pci_read_config_word(tp->pdev, pm + PCI_PM_PMC, &power_caps);
1309
1310         if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE) {
1311                 u32 mac_mode;
1312
1313                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
1314                         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
1315                         udelay(40);
1316
1317                         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
1318                                 mac_mode = MAC_MODE_PORT_MODE_GMII;
1319                         else
1320                                 mac_mode = MAC_MODE_PORT_MODE_MII;
1321
1322                         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 ||
1323                             !(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB))
1324                                 mac_mode |= MAC_MODE_LINK_POLARITY;
1325                 } else {
1326                         mac_mode = MAC_MODE_PORT_MODE_TBI;
1327                 }
1328
1329                 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
1330                         tw32(MAC_LED_CTRL, tp->led_ctrl);
1331
1332                 if (((power_caps & PCI_PM_CAP_PME_D3cold) &&
1333                      (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)))
1334                         mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
1335
1336                 tw32_f(MAC_MODE, mac_mode);
1337                 udelay(100);
1338
1339                 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
1340                 udelay(10);
1341         }
1342
1343         if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
1344             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1345              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
1346                 u32 base_val;
1347
1348                 base_val = tp->pci_clock_ctrl;
1349                 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
1350                              CLOCK_CTRL_TXCLK_DISABLE);
1351
1352                 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
1353                             CLOCK_CTRL_PWRDOWN_PLL133, 40);
1354         } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1355                    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
1356                 /* do nothing */
1357         } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
1358                      (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
1359                 u32 newbits1, newbits2;
1360
1361                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1362                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1363                         newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
1364                                     CLOCK_CTRL_TXCLK_DISABLE |
1365                                     CLOCK_CTRL_ALTCLK);
1366                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1367                 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
1368                         newbits1 = CLOCK_CTRL_625_CORE;
1369                         newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
1370                 } else {
1371                         newbits1 = CLOCK_CTRL_ALTCLK;
1372                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1373                 }
1374
1375                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
1376                             40);
1377
1378                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
1379                             40);
1380
1381                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
1382                         u32 newbits3;
1383
1384                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1385                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1386                                 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
1387                                             CLOCK_CTRL_TXCLK_DISABLE |
1388                                             CLOCK_CTRL_44MHZ_CORE);
1389                         } else {
1390                                 newbits3 = CLOCK_CTRL_44MHZ_CORE;
1391                         }
1392
1393                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
1394                                     tp->pci_clock_ctrl | newbits3, 40);
1395                 }
1396         }
1397
1398         if (!(tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
1399             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1400                 tg3_power_down_phy(tp);
1401
1402         tg3_frob_aux_power(tp);
1403
1404         /* Workaround for unstable PLL clock */
1405         if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
1406             (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
1407                 u32 val = tr32(0x7d00);
1408
1409                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
1410                 tw32(0x7d00, val);
1411                 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
1412                         int err;
1413
1414                         err = tg3_nvram_lock(tp);
1415                         tg3_halt_cpu(tp, RX_CPU_BASE);
1416                         if (!err)
1417                                 tg3_nvram_unlock(tp);
1418                 }
1419         }
1420
1421         tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
1422
1423         /* Finally, set the new power state. */
1424         pci_write_config_word(tp->pdev, pm + PCI_PM_CTRL, power_control);
1425         udelay(100);    /* Delay after power state change */
1426
1427         return 0;
1428 }
1429
1430 static void tg3_link_report(struct tg3 *tp)
1431 {
1432         if (!netif_carrier_ok(tp->dev)) {
1433                 if (netif_msg_link(tp))
1434                         printk(KERN_INFO PFX "%s: Link is down.\n",
1435                                tp->dev->name);
1436         } else if (netif_msg_link(tp)) {
1437                 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1438                        tp->dev->name,
1439                        (tp->link_config.active_speed == SPEED_1000 ?
1440                         1000 :
1441                         (tp->link_config.active_speed == SPEED_100 ?
1442                          100 : 10)),
1443                        (tp->link_config.active_duplex == DUPLEX_FULL ?
1444                         "full" : "half"));
1445
1446                 printk(KERN_INFO PFX "%s: Flow control is %s for TX and "
1447                        "%s for RX.\n",
1448                        tp->dev->name,
1449                        (tp->tg3_flags & TG3_FLAG_TX_PAUSE) ? "on" : "off",
1450                        (tp->tg3_flags & TG3_FLAG_RX_PAUSE) ? "on" : "off");
1451         }
1452 }
1453
1454 static void tg3_setup_flow_control(struct tg3 *tp, u32 local_adv, u32 remote_adv)
1455 {
1456         u32 new_tg3_flags = 0;
1457         u32 old_rx_mode = tp->rx_mode;
1458         u32 old_tx_mode = tp->tx_mode;
1459
1460         if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) {
1461
1462                 /* Convert 1000BaseX flow control bits to 1000BaseT
1463                  * bits before resolving flow control.
1464                  */
1465                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
1466                         local_adv &= ~(ADVERTISE_PAUSE_CAP |
1467                                        ADVERTISE_PAUSE_ASYM);
1468                         remote_adv &= ~(LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
1469
1470                         if (local_adv & ADVERTISE_1000XPAUSE)
1471                                 local_adv |= ADVERTISE_PAUSE_CAP;
1472                         if (local_adv & ADVERTISE_1000XPSE_ASYM)
1473                                 local_adv |= ADVERTISE_PAUSE_ASYM;
1474                         if (remote_adv & LPA_1000XPAUSE)
1475                                 remote_adv |= LPA_PAUSE_CAP;
1476                         if (remote_adv & LPA_1000XPAUSE_ASYM)
1477                                 remote_adv |= LPA_PAUSE_ASYM;
1478                 }
1479
1480                 if (local_adv & ADVERTISE_PAUSE_CAP) {
1481                         if (local_adv & ADVERTISE_PAUSE_ASYM) {
1482                                 if (remote_adv & LPA_PAUSE_CAP)
1483                                         new_tg3_flags |=
1484                                                 (TG3_FLAG_RX_PAUSE |
1485                                                 TG3_FLAG_TX_PAUSE);
1486                                 else if (remote_adv & LPA_PAUSE_ASYM)
1487                                         new_tg3_flags |=
1488                                                 (TG3_FLAG_RX_PAUSE);
1489                         } else {
1490                                 if (remote_adv & LPA_PAUSE_CAP)
1491                                         new_tg3_flags |=
1492                                                 (TG3_FLAG_RX_PAUSE |
1493                                                 TG3_FLAG_TX_PAUSE);
1494                         }
1495                 } else if (local_adv & ADVERTISE_PAUSE_ASYM) {
1496                         if ((remote_adv & LPA_PAUSE_CAP) &&
1497                         (remote_adv & LPA_PAUSE_ASYM))
1498                                 new_tg3_flags |= TG3_FLAG_TX_PAUSE;
1499                 }
1500
1501                 tp->tg3_flags &= ~(TG3_FLAG_RX_PAUSE | TG3_FLAG_TX_PAUSE);
1502                 tp->tg3_flags |= new_tg3_flags;
1503         } else {
1504                 new_tg3_flags = tp->tg3_flags;
1505         }
1506
1507         if (new_tg3_flags & TG3_FLAG_RX_PAUSE)
1508                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1509         else
1510                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1511
1512         if (old_rx_mode != tp->rx_mode) {
1513                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1514         }
1515
1516         if (new_tg3_flags & TG3_FLAG_TX_PAUSE)
1517                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1518         else
1519                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1520
1521         if (old_tx_mode != tp->tx_mode) {
1522                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1523         }
1524 }
1525
1526 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
1527 {
1528         switch (val & MII_TG3_AUX_STAT_SPDMASK) {
1529         case MII_TG3_AUX_STAT_10HALF:
1530                 *speed = SPEED_10;
1531                 *duplex = DUPLEX_HALF;
1532                 break;
1533
1534         case MII_TG3_AUX_STAT_10FULL:
1535                 *speed = SPEED_10;
1536                 *duplex = DUPLEX_FULL;
1537                 break;
1538
1539         case MII_TG3_AUX_STAT_100HALF:
1540                 *speed = SPEED_100;
1541                 *duplex = DUPLEX_HALF;
1542                 break;
1543
1544         case MII_TG3_AUX_STAT_100FULL:
1545                 *speed = SPEED_100;
1546                 *duplex = DUPLEX_FULL;
1547                 break;
1548
1549         case MII_TG3_AUX_STAT_1000HALF:
1550                 *speed = SPEED_1000;
1551                 *duplex = DUPLEX_HALF;
1552                 break;
1553
1554         case MII_TG3_AUX_STAT_1000FULL:
1555                 *speed = SPEED_1000;
1556                 *duplex = DUPLEX_FULL;
1557                 break;
1558
1559         default:
1560                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1561                         *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
1562                                  SPEED_10;
1563                         *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
1564                                   DUPLEX_HALF;
1565                         break;
1566                 }
1567                 *speed = SPEED_INVALID;
1568                 *duplex = DUPLEX_INVALID;
1569                 break;
1570         };
1571 }
1572
1573 static void tg3_phy_copper_begin(struct tg3 *tp)
1574 {
1575         u32 new_adv;
1576         int i;
1577
1578         if (tp->link_config.phy_is_low_power) {
1579                 /* Entering low power mode.  Disable gigabit and
1580                  * 100baseT advertisements.
1581                  */
1582                 tg3_writephy(tp, MII_TG3_CTRL, 0);
1583
1584                 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
1585                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1586                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
1587                         new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
1588
1589                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1590         } else if (tp->link_config.speed == SPEED_INVALID) {
1591                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
1592                         tp->link_config.advertising &=
1593                                 ~(ADVERTISED_1000baseT_Half |
1594                                   ADVERTISED_1000baseT_Full);
1595
1596                 new_adv = (ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1597                 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
1598                         new_adv |= ADVERTISE_10HALF;
1599                 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
1600                         new_adv |= ADVERTISE_10FULL;
1601                 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
1602                         new_adv |= ADVERTISE_100HALF;
1603                 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
1604                         new_adv |= ADVERTISE_100FULL;
1605                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1606
1607                 if (tp->link_config.advertising &
1608                     (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
1609                         new_adv = 0;
1610                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
1611                                 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
1612                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
1613                                 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
1614                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
1615                             (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1616                              tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
1617                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1618                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
1619                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1620                 } else {
1621                         tg3_writephy(tp, MII_TG3_CTRL, 0);
1622                 }
1623         } else {
1624                 /* Asking for a specific link mode. */
1625                 if (tp->link_config.speed == SPEED_1000) {
1626                         new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1627                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
1628
1629                         if (tp->link_config.duplex == DUPLEX_FULL)
1630                                 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
1631                         else
1632                                 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
1633                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1634                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
1635                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1636                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
1637                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1638                 } else {
1639                         tg3_writephy(tp, MII_TG3_CTRL, 0);
1640
1641                         new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1642                         if (tp->link_config.speed == SPEED_100) {
1643                                 if (tp->link_config.duplex == DUPLEX_FULL)
1644                                         new_adv |= ADVERTISE_100FULL;
1645                                 else
1646                                         new_adv |= ADVERTISE_100HALF;
1647                         } else {
1648                                 if (tp->link_config.duplex == DUPLEX_FULL)
1649                                         new_adv |= ADVERTISE_10FULL;
1650                                 else
1651                                         new_adv |= ADVERTISE_10HALF;
1652                         }
1653                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
1654                 }
1655         }
1656
1657         if (tp->link_config.autoneg == AUTONEG_DISABLE &&
1658             tp->link_config.speed != SPEED_INVALID) {
1659                 u32 bmcr, orig_bmcr;
1660
1661                 tp->link_config.active_speed = tp->link_config.speed;
1662                 tp->link_config.active_duplex = tp->link_config.duplex;
1663
1664                 bmcr = 0;
1665                 switch (tp->link_config.speed) {
1666                 default:
1667                 case SPEED_10:
1668                         break;
1669
1670                 case SPEED_100:
1671                         bmcr |= BMCR_SPEED100;
1672                         break;
1673
1674                 case SPEED_1000:
1675                         bmcr |= TG3_BMCR_SPEED1000;
1676                         break;
1677                 };
1678
1679                 if (tp->link_config.duplex == DUPLEX_FULL)
1680                         bmcr |= BMCR_FULLDPLX;
1681
1682                 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
1683                     (bmcr != orig_bmcr)) {
1684                         tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
1685                         for (i = 0; i < 1500; i++) {
1686                                 u32 tmp;
1687
1688                                 udelay(10);
1689                                 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
1690                                     tg3_readphy(tp, MII_BMSR, &tmp))
1691                                         continue;
1692                                 if (!(tmp & BMSR_LSTATUS)) {
1693                                         udelay(40);
1694                                         break;
1695                                 }
1696                         }
1697                         tg3_writephy(tp, MII_BMCR, bmcr);
1698                         udelay(40);
1699                 }
1700         } else {
1701                 tg3_writephy(tp, MII_BMCR,
1702                              BMCR_ANENABLE | BMCR_ANRESTART);
1703         }
1704 }
1705
1706 static int tg3_init_5401phy_dsp(struct tg3 *tp)
1707 {
1708         int err;
1709
1710         /* Turn off tap power management. */
1711         /* Set Extended packet length bit */
1712         err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1713
1714         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
1715         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
1716
1717         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
1718         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
1719
1720         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
1721         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
1722
1723         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
1724         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
1725
1726         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1727         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
1728
1729         udelay(40);
1730
1731         return err;
1732 }
1733
1734 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
1735 {
1736         u32 adv_reg, all_mask = 0;
1737
1738         if (mask & ADVERTISED_10baseT_Half)
1739                 all_mask |= ADVERTISE_10HALF;
1740         if (mask & ADVERTISED_10baseT_Full)
1741                 all_mask |= ADVERTISE_10FULL;
1742         if (mask & ADVERTISED_100baseT_Half)
1743                 all_mask |= ADVERTISE_100HALF;
1744         if (mask & ADVERTISED_100baseT_Full)
1745                 all_mask |= ADVERTISE_100FULL;
1746
1747         if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
1748                 return 0;
1749
1750         if ((adv_reg & all_mask) != all_mask)
1751                 return 0;
1752         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1753                 u32 tg3_ctrl;
1754
1755                 all_mask = 0;
1756                 if (mask & ADVERTISED_1000baseT_Half)
1757                         all_mask |= ADVERTISE_1000HALF;
1758                 if (mask & ADVERTISED_1000baseT_Full)
1759                         all_mask |= ADVERTISE_1000FULL;
1760
1761                 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
1762                         return 0;
1763
1764                 if ((tg3_ctrl & all_mask) != all_mask)
1765                         return 0;
1766         }
1767         return 1;
1768 }
1769
1770 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
1771 {
1772         int current_link_up;
1773         u32 bmsr, dummy;
1774         u16 current_speed;
1775         u8 current_duplex;
1776         int i, err;
1777
1778         tw32(MAC_EVENT, 0);
1779
1780         tw32_f(MAC_STATUS,
1781              (MAC_STATUS_SYNC_CHANGED |
1782               MAC_STATUS_CFG_CHANGED |
1783               MAC_STATUS_MI_COMPLETION |
1784               MAC_STATUS_LNKSTATE_CHANGED));
1785         udelay(40);
1786
1787         tp->mi_mode = MAC_MI_MODE_BASE;
1788         tw32_f(MAC_MI_MODE, tp->mi_mode);
1789         udelay(80);
1790
1791         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
1792
1793         /* Some third-party PHYs need to be reset on link going
1794          * down.
1795          */
1796         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1797              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1798              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
1799             netif_carrier_ok(tp->dev)) {
1800                 tg3_readphy(tp, MII_BMSR, &bmsr);
1801                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1802                     !(bmsr & BMSR_LSTATUS))
1803                         force_reset = 1;
1804         }
1805         if (force_reset)
1806                 tg3_phy_reset(tp);
1807
1808         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1809                 tg3_readphy(tp, MII_BMSR, &bmsr);
1810                 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
1811                     !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
1812                         bmsr = 0;
1813
1814                 if (!(bmsr & BMSR_LSTATUS)) {
1815                         err = tg3_init_5401phy_dsp(tp);
1816                         if (err)
1817                                 return err;
1818
1819                         tg3_readphy(tp, MII_BMSR, &bmsr);
1820                         for (i = 0; i < 1000; i++) {
1821                                 udelay(10);
1822                                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1823                                     (bmsr & BMSR_LSTATUS)) {
1824                                         udelay(40);
1825                                         break;
1826                                 }
1827                         }
1828
1829                         if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
1830                             !(bmsr & BMSR_LSTATUS) &&
1831                             tp->link_config.active_speed == SPEED_1000) {
1832                                 err = tg3_phy_reset(tp);
1833                                 if (!err)
1834                                         err = tg3_init_5401phy_dsp(tp);
1835                                 if (err)
1836                                         return err;
1837                         }
1838                 }
1839         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1840                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
1841                 /* 5701 {A0,B0} CRC bug workaround */
1842                 tg3_writephy(tp, 0x15, 0x0a75);
1843                 tg3_writephy(tp, 0x1c, 0x8c68);
1844                 tg3_writephy(tp, 0x1c, 0x8d68);
1845                 tg3_writephy(tp, 0x1c, 0x8c68);
1846         }
1847
1848         /* Clear pending interrupts... */
1849         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
1850         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
1851
1852         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
1853                 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
1854         else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
1855                 tg3_writephy(tp, MII_TG3_IMASK, ~0);
1856
1857         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1858             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1859                 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
1860                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
1861                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
1862                 else
1863                         tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
1864         }
1865
1866         current_link_up = 0;
1867         current_speed = SPEED_INVALID;
1868         current_duplex = DUPLEX_INVALID;
1869
1870         if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
1871                 u32 val;
1872
1873                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
1874                 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
1875                 if (!(val & (1 << 10))) {
1876                         val |= (1 << 10);
1877                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
1878                         goto relink;
1879                 }
1880         }
1881
1882         bmsr = 0;
1883         for (i = 0; i < 100; i++) {
1884                 tg3_readphy(tp, MII_BMSR, &bmsr);
1885                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1886                     (bmsr & BMSR_LSTATUS))
1887                         break;
1888                 udelay(40);
1889         }
1890
1891         if (bmsr & BMSR_LSTATUS) {
1892                 u32 aux_stat, bmcr;
1893
1894                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
1895                 for (i = 0; i < 2000; i++) {
1896                         udelay(10);
1897                         if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
1898                             aux_stat)
1899                                 break;
1900                 }
1901
1902                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
1903                                              &current_speed,
1904                                              &current_duplex);
1905
1906                 bmcr = 0;
1907                 for (i = 0; i < 200; i++) {
1908                         tg3_readphy(tp, MII_BMCR, &bmcr);
1909                         if (tg3_readphy(tp, MII_BMCR, &bmcr))
1910                                 continue;
1911                         if (bmcr && bmcr != 0x7fff)
1912                                 break;
1913                         udelay(10);
1914                 }
1915
1916                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
1917                         if (bmcr & BMCR_ANENABLE) {
1918                                 current_link_up = 1;
1919
1920                                 /* Force autoneg restart if we are exiting
1921                                  * low power mode.
1922                                  */
1923                                 if (!tg3_copper_is_advertising_all(tp,
1924                                                 tp->link_config.advertising))
1925                                         current_link_up = 0;
1926                         } else {
1927                                 current_link_up = 0;
1928                         }
1929                 } else {
1930                         if (!(bmcr & BMCR_ANENABLE) &&
1931                             tp->link_config.speed == current_speed &&
1932                             tp->link_config.duplex == current_duplex) {
1933                                 current_link_up = 1;
1934                         } else {
1935                                 current_link_up = 0;
1936                         }
1937                 }
1938
1939                 tp->link_config.active_speed = current_speed;
1940                 tp->link_config.active_duplex = current_duplex;
1941         }
1942
1943         if (current_link_up == 1 &&
1944             (tp->link_config.active_duplex == DUPLEX_FULL) &&
1945             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
1946                 u32 local_adv, remote_adv;
1947
1948                 if (tg3_readphy(tp, MII_ADVERTISE, &local_adv))
1949                         local_adv = 0;
1950                 local_adv &= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
1951
1952                 if (tg3_readphy(tp, MII_LPA, &remote_adv))
1953                         remote_adv = 0;
1954
1955                 remote_adv &= (LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
1956
1957                 /* If we are not advertising full pause capability,
1958                  * something is wrong.  Bring the link down and reconfigure.
1959                  */
1960                 if (local_adv != ADVERTISE_PAUSE_CAP) {
1961                         current_link_up = 0;
1962                 } else {
1963                         tg3_setup_flow_control(tp, local_adv, remote_adv);
1964                 }
1965         }
1966 relink:
1967         if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
1968                 u32 tmp;
1969
1970                 tg3_phy_copper_begin(tp);
1971
1972                 tg3_readphy(tp, MII_BMSR, &tmp);
1973                 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
1974                     (tmp & BMSR_LSTATUS))
1975                         current_link_up = 1;
1976         }
1977
1978         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
1979         if (current_link_up == 1) {
1980                 if (tp->link_config.active_speed == SPEED_100 ||
1981                     tp->link_config.active_speed == SPEED_10)
1982                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
1983                 else
1984                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
1985         } else
1986                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
1987
1988         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
1989         if (tp->link_config.active_duplex == DUPLEX_HALF)
1990                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
1991
1992         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
1993         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
1994                 if ((tp->led_ctrl == LED_CTRL_MODE_PHY_2) ||
1995                     (current_link_up == 1 &&
1996                      tp->link_config.active_speed == SPEED_10))
1997                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1998         } else {
1999                 if (current_link_up == 1)
2000                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
2001         }
2002
2003         /* ??? Without this setting Netgear GA302T PHY does not
2004          * ??? send/receive packets...
2005          */
2006         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
2007             tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
2008                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
2009                 tw32_f(MAC_MI_MODE, tp->mi_mode);
2010                 udelay(80);
2011         }
2012
2013         tw32_f(MAC_MODE, tp->mac_mode);
2014         udelay(40);
2015
2016         if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
2017                 /* Polled via timer. */
2018                 tw32_f(MAC_EVENT, 0);
2019         } else {
2020                 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2021         }
2022         udelay(40);
2023
2024         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
2025             current_link_up == 1 &&
2026             tp->link_config.active_speed == SPEED_1000 &&
2027             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
2028              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
2029                 udelay(120);
2030                 tw32_f(MAC_STATUS,
2031                      (MAC_STATUS_SYNC_CHANGED |
2032                       MAC_STATUS_CFG_CHANGED));
2033                 udelay(40);
2034                 tg3_write_mem(tp,
2035                               NIC_SRAM_FIRMWARE_MBOX,
2036                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
2037         }
2038
2039         if (current_link_up != netif_carrier_ok(tp->dev)) {
2040                 if (current_link_up)
2041                         netif_carrier_on(tp->dev);
2042                 else
2043                         netif_carrier_off(tp->dev);
2044                 tg3_link_report(tp);
2045         }
2046
2047         return 0;
2048 }
2049
2050 struct tg3_fiber_aneginfo {
2051         int state;
2052 #define ANEG_STATE_UNKNOWN              0
2053 #define ANEG_STATE_AN_ENABLE            1
2054 #define ANEG_STATE_RESTART_INIT         2
2055 #define ANEG_STATE_RESTART              3
2056 #define ANEG_STATE_DISABLE_LINK_OK      4
2057 #define ANEG_STATE_ABILITY_DETECT_INIT  5
2058 #define ANEG_STATE_ABILITY_DETECT       6
2059 #define ANEG_STATE_ACK_DETECT_INIT      7
2060 #define ANEG_STATE_ACK_DETECT           8
2061 #define ANEG_STATE_COMPLETE_ACK_INIT    9
2062 #define ANEG_STATE_COMPLETE_ACK         10
2063 #define ANEG_STATE_IDLE_DETECT_INIT     11
2064 #define ANEG_STATE_IDLE_DETECT          12
2065 #define ANEG_STATE_LINK_OK              13
2066 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
2067 #define ANEG_STATE_NEXT_PAGE_WAIT       15
2068
2069         u32 flags;
2070 #define MR_AN_ENABLE            0x00000001
2071 #define MR_RESTART_AN           0x00000002
2072 #define MR_AN_COMPLETE          0x00000004
2073 #define MR_PAGE_RX              0x00000008
2074 #define MR_NP_LOADED            0x00000010
2075 #define MR_TOGGLE_TX            0x00000020
2076 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
2077 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
2078 #define MR_LP_ADV_SYM_PAUSE     0x00000100
2079 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
2080 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
2081 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
2082 #define MR_LP_ADV_NEXT_PAGE     0x00001000
2083 #define MR_TOGGLE_RX            0x00002000
2084 #define MR_NP_RX                0x00004000
2085
2086 #define MR_LINK_OK              0x80000000
2087
2088         unsigned long link_time, cur_time;
2089
2090         u32 ability_match_cfg;
2091         int ability_match_count;
2092
2093         char ability_match, idle_match, ack_match;
2094
2095         u32 txconfig, rxconfig;
2096 #define ANEG_CFG_NP             0x00000080
2097 #define ANEG_CFG_ACK            0x00000040
2098 #define ANEG_CFG_RF2            0x00000020
2099 #define ANEG_CFG_RF1            0x00000010
2100 #define ANEG_CFG_PS2            0x00000001
2101 #define ANEG_CFG_PS1            0x00008000
2102 #define ANEG_CFG_HD             0x00004000
2103 #define ANEG_CFG_FD             0x00002000
2104 #define ANEG_CFG_INVAL          0x00001f06
2105
2106 };
2107 #define ANEG_OK         0
2108 #define ANEG_DONE       1
2109 #define ANEG_TIMER_ENAB 2
2110 #define ANEG_FAILED     -1
2111
2112 #define ANEG_STATE_SETTLE_TIME  10000
2113
2114 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
2115                                    struct tg3_fiber_aneginfo *ap)
2116 {
2117         unsigned long delta;
2118         u32 rx_cfg_reg;
2119         int ret;
2120
2121         if (ap->state == ANEG_STATE_UNKNOWN) {
2122                 ap->rxconfig = 0;
2123                 ap->link_time = 0;
2124                 ap->cur_time = 0;
2125                 ap->ability_match_cfg = 0;
2126                 ap->ability_match_count = 0;
2127                 ap->ability_match = 0;
2128                 ap->idle_match = 0;
2129                 ap->ack_match = 0;
2130         }
2131         ap->cur_time++;
2132
2133         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
2134                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
2135
2136                 if (rx_cfg_reg != ap->ability_match_cfg) {
2137                         ap->ability_match_cfg = rx_cfg_reg;
2138                         ap->ability_match = 0;
2139                         ap->ability_match_count = 0;
2140                 } else {
2141                         if (++ap->ability_match_count > 1) {
2142                                 ap->ability_match = 1;
2143                                 ap->ability_match_cfg = rx_cfg_reg;
2144                         }
2145                 }
2146                 if (rx_cfg_reg & ANEG_CFG_ACK)
2147                         ap->ack_match = 1;
2148                 else
2149                         ap->ack_match = 0;
2150
2151                 ap->idle_match = 0;
2152         } else {
2153                 ap->idle_match = 1;
2154                 ap->ability_match_cfg = 0;
2155                 ap->ability_match_count = 0;
2156                 ap->ability_match = 0;
2157                 ap->ack_match = 0;
2158
2159                 rx_cfg_reg = 0;
2160         }
2161
2162         ap->rxconfig = rx_cfg_reg;
2163         ret = ANEG_OK;
2164
2165         switch(ap->state) {
2166         case ANEG_STATE_UNKNOWN:
2167                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
2168                         ap->state = ANEG_STATE_AN_ENABLE;
2169
2170                 /* fallthru */
2171         case ANEG_STATE_AN_ENABLE:
2172                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
2173                 if (ap->flags & MR_AN_ENABLE) {
2174                         ap->link_time = 0;
2175                         ap->cur_time = 0;
2176                         ap->ability_match_cfg = 0;
2177                         ap->ability_match_count = 0;
2178                         ap->ability_match = 0;
2179                         ap->idle_match = 0;
2180                         ap->ack_match = 0;
2181
2182                         ap->state = ANEG_STATE_RESTART_INIT;
2183                 } else {
2184                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
2185                 }
2186                 break;
2187
2188         case ANEG_STATE_RESTART_INIT:
2189                 ap->link_time = ap->cur_time;
2190                 ap->flags &= ~(MR_NP_LOADED);
2191                 ap->txconfig = 0;
2192                 tw32(MAC_TX_AUTO_NEG, 0);
2193                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2194                 tw32_f(MAC_MODE, tp->mac_mode);
2195                 udelay(40);
2196
2197                 ret = ANEG_TIMER_ENAB;
2198                 ap->state = ANEG_STATE_RESTART;
2199
2200                 /* fallthru */
2201         case ANEG_STATE_RESTART:
2202                 delta = ap->cur_time - ap->link_time;
2203                 if (delta > ANEG_STATE_SETTLE_TIME) {
2204                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
2205                 } else {
2206                         ret = ANEG_TIMER_ENAB;
2207                 }
2208                 break;
2209
2210         case ANEG_STATE_DISABLE_LINK_OK:
2211                 ret = ANEG_DONE;
2212                 break;
2213
2214         case ANEG_STATE_ABILITY_DETECT_INIT:
2215                 ap->flags &= ~(MR_TOGGLE_TX);
2216                 ap->txconfig = (ANEG_CFG_FD | ANEG_CFG_PS1);
2217                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2218                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2219                 tw32_f(MAC_MODE, tp->mac_mode);
2220                 udelay(40);
2221
2222                 ap->state = ANEG_STATE_ABILITY_DETECT;
2223                 break;
2224
2225         case ANEG_STATE_ABILITY_DETECT:
2226                 if (ap->ability_match != 0 && ap->rxconfig != 0) {
2227                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
2228                 }
2229                 break;
2230
2231         case ANEG_STATE_ACK_DETECT_INIT:
2232                 ap->txconfig |= ANEG_CFG_ACK;
2233                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2234                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2235                 tw32_f(MAC_MODE, tp->mac_mode);
2236                 udelay(40);
2237
2238                 ap->state = ANEG_STATE_ACK_DETECT;
2239
2240                 /* fallthru */
2241         case ANEG_STATE_ACK_DETECT:
2242                 if (ap->ack_match != 0) {
2243                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
2244                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
2245                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
2246                         } else {
2247                                 ap->state = ANEG_STATE_AN_ENABLE;
2248                         }
2249                 } else if (ap->ability_match != 0 &&
2250                            ap->rxconfig == 0) {
2251                         ap->state = ANEG_STATE_AN_ENABLE;
2252                 }
2253                 break;
2254
2255         case ANEG_STATE_COMPLETE_ACK_INIT:
2256                 if (ap->rxconfig & ANEG_CFG_INVAL) {
2257                         ret = ANEG_FAILED;
2258                         break;
2259                 }
2260                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
2261                                MR_LP_ADV_HALF_DUPLEX |
2262                                MR_LP_ADV_SYM_PAUSE |
2263                                MR_LP_ADV_ASYM_PAUSE |
2264                                MR_LP_ADV_REMOTE_FAULT1 |
2265                                MR_LP_ADV_REMOTE_FAULT2 |
2266                                MR_LP_ADV_NEXT_PAGE |
2267                                MR_TOGGLE_RX |
2268                                MR_NP_RX);
2269                 if (ap->rxconfig & ANEG_CFG_FD)
2270                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
2271                 if (ap->rxconfig & ANEG_CFG_HD)
2272                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
2273                 if (ap->rxconfig & ANEG_CFG_PS1)
2274                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
2275                 if (ap->rxconfig & ANEG_CFG_PS2)
2276                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
2277                 if (ap->rxconfig & ANEG_CFG_RF1)
2278                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
2279                 if (ap->rxconfig & ANEG_CFG_RF2)
2280                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
2281                 if (ap->rxconfig & ANEG_CFG_NP)
2282                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
2283
2284                 ap->link_time = ap->cur_time;
2285
2286                 ap->flags ^= (MR_TOGGLE_TX);
2287                 if (ap->rxconfig & 0x0008)
2288                         ap->flags |= MR_TOGGLE_RX;
2289                 if (ap->rxconfig & ANEG_CFG_NP)
2290                         ap->flags |= MR_NP_RX;
2291                 ap->flags |= MR_PAGE_RX;
2292
2293                 ap->state = ANEG_STATE_COMPLETE_ACK;
2294                 ret = ANEG_TIMER_ENAB;
2295                 break;
2296
2297         case ANEG_STATE_COMPLETE_ACK:
2298                 if (ap->ability_match != 0 &&
2299                     ap->rxconfig == 0) {
2300                         ap->state = ANEG_STATE_AN_ENABLE;
2301                         break;
2302                 }
2303                 delta = ap->cur_time - ap->link_time;
2304                 if (delta > ANEG_STATE_SETTLE_TIME) {
2305                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
2306                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2307                         } else {
2308                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
2309                                     !(ap->flags & MR_NP_RX)) {
2310                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2311                                 } else {
2312                                         ret = ANEG_FAILED;
2313                                 }
2314                         }
2315                 }
2316                 break;
2317
2318         case ANEG_STATE_IDLE_DETECT_INIT:
2319                 ap->link_time = ap->cur_time;
2320                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2321                 tw32_f(MAC_MODE, tp->mac_mode);
2322                 udelay(40);
2323
2324                 ap->state = ANEG_STATE_IDLE_DETECT;
2325                 ret = ANEG_TIMER_ENAB;
2326                 break;
2327
2328         case ANEG_STATE_IDLE_DETECT:
2329                 if (ap->ability_match != 0 &&
2330                     ap->rxconfig == 0) {
2331                         ap->state = ANEG_STATE_AN_ENABLE;
2332                         break;
2333                 }
2334                 delta = ap->cur_time - ap->link_time;
2335                 if (delta > ANEG_STATE_SETTLE_TIME) {
2336                         /* XXX another gem from the Broadcom driver :( */
2337                         ap->state = ANEG_STATE_LINK_OK;
2338                 }
2339                 break;
2340
2341         case ANEG_STATE_LINK_OK:
2342                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
2343                 ret = ANEG_DONE;
2344                 break;
2345
2346         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
2347                 /* ??? unimplemented */
2348                 break;
2349
2350         case ANEG_STATE_NEXT_PAGE_WAIT:
2351                 /* ??? unimplemented */
2352                 break;
2353
2354         default:
2355                 ret = ANEG_FAILED;
2356                 break;
2357         };
2358
2359         return ret;
2360 }
2361
2362 static int fiber_autoneg(struct tg3 *tp, u32 *flags)
2363 {
2364         int res = 0;
2365         struct tg3_fiber_aneginfo aninfo;
2366         int status = ANEG_FAILED;
2367         unsigned int tick;
2368         u32 tmp;
2369
2370         tw32_f(MAC_TX_AUTO_NEG, 0);
2371
2372         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
2373         tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
2374         udelay(40);
2375
2376         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
2377         udelay(40);
2378
2379         memset(&aninfo, 0, sizeof(aninfo));
2380         aninfo.flags |= MR_AN_ENABLE;
2381         aninfo.state = ANEG_STATE_UNKNOWN;
2382         aninfo.cur_time = 0;
2383         tick = 0;
2384         while (++tick < 195000) {
2385                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
2386                 if (status == ANEG_DONE || status == ANEG_FAILED)
2387                         break;
2388
2389                 udelay(1);
2390         }
2391
2392         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2393         tw32_f(MAC_MODE, tp->mac_mode);
2394         udelay(40);
2395
2396         *flags = aninfo.flags;
2397
2398         if (status == ANEG_DONE &&
2399             (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
2400                              MR_LP_ADV_FULL_DUPLEX)))
2401                 res = 1;
2402
2403         return res;
2404 }
2405
2406 static void tg3_init_bcm8002(struct tg3 *tp)
2407 {
2408         u32 mac_status = tr32(MAC_STATUS);
2409         int i;
2410
2411         /* Reset when initting first time or we have a link. */
2412         if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
2413             !(mac_status & MAC_STATUS_PCS_SYNCED))
2414                 return;
2415
2416         /* Set PLL lock range. */
2417         tg3_writephy(tp, 0x16, 0x8007);
2418
2419         /* SW reset */
2420         tg3_writephy(tp, MII_BMCR, BMCR_RESET);
2421
2422         /* Wait for reset to complete. */
2423         /* XXX schedule_timeout() ... */
2424         for (i = 0; i < 500; i++)
2425                 udelay(10);
2426
2427         /* Config mode; select PMA/Ch 1 regs. */
2428         tg3_writephy(tp, 0x10, 0x8411);
2429
2430         /* Enable auto-lock and comdet, select txclk for tx. */
2431         tg3_writephy(tp, 0x11, 0x0a10);
2432
2433         tg3_writephy(tp, 0x18, 0x00a0);
2434         tg3_writephy(tp, 0x16, 0x41ff);
2435
2436         /* Assert and deassert POR. */
2437         tg3_writephy(tp, 0x13, 0x0400);
2438         udelay(40);
2439         tg3_writephy(tp, 0x13, 0x0000);
2440
2441         tg3_writephy(tp, 0x11, 0x0a50);
2442         udelay(40);
2443         tg3_writephy(tp, 0x11, 0x0a10);
2444
2445         /* Wait for signal to stabilize */
2446         /* XXX schedule_timeout() ... */
2447         for (i = 0; i < 15000; i++)
2448                 udelay(10);
2449
2450         /* Deselect the channel register so we can read the PHYID
2451          * later.
2452          */
2453         tg3_writephy(tp, 0x10, 0x8011);
2454 }
2455
2456 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
2457 {
2458         u32 sg_dig_ctrl, sg_dig_status;
2459         u32 serdes_cfg, expected_sg_dig_ctrl;
2460         int workaround, port_a;
2461         int current_link_up;
2462
2463         serdes_cfg = 0;
2464         expected_sg_dig_ctrl = 0;
2465         workaround = 0;
2466         port_a = 1;
2467         current_link_up = 0;
2468
2469         if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
2470             tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
2471                 workaround = 1;
2472                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
2473                         port_a = 0;
2474
2475                 /* preserve bits 0-11,13,14 for signal pre-emphasis */
2476                 /* preserve bits 20-23 for voltage regulator */
2477                 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
2478         }
2479
2480         sg_dig_ctrl = tr32(SG_DIG_CTRL);
2481
2482         if (tp->link_config.autoneg != AUTONEG_ENABLE) {
2483                 if (sg_dig_ctrl & (1 << 31)) {
2484                         if (workaround) {
2485                                 u32 val = serdes_cfg;
2486
2487                                 if (port_a)
2488                                         val |= 0xc010000;
2489                                 else
2490                                         val |= 0x4010000;
2491                                 tw32_f(MAC_SERDES_CFG, val);
2492                         }
2493                         tw32_f(SG_DIG_CTRL, 0x01388400);
2494                 }
2495                 if (mac_status & MAC_STATUS_PCS_SYNCED) {
2496                         tg3_setup_flow_control(tp, 0, 0);
2497                         current_link_up = 1;
2498                 }
2499                 goto out;
2500         }
2501
2502         /* Want auto-negotiation.  */
2503         expected_sg_dig_ctrl = 0x81388400;
2504
2505         /* Pause capability */
2506         expected_sg_dig_ctrl |= (1 << 11);
2507
2508         /* Asymettric pause */
2509         expected_sg_dig_ctrl |= (1 << 12);
2510
2511         if (sg_dig_ctrl != expected_sg_dig_ctrl) {
2512                 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
2513                     tp->serdes_counter &&
2514                     ((mac_status & (MAC_STATUS_PCS_SYNCED |
2515                                     MAC_STATUS_RCVD_CFG)) ==
2516                      MAC_STATUS_PCS_SYNCED)) {
2517                         tp->serdes_counter--;
2518                         current_link_up = 1;
2519                         goto out;
2520                 }
2521 restart_autoneg:
2522                 if (workaround)
2523                         tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
2524                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | (1 << 30));
2525                 udelay(5);
2526                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
2527
2528                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
2529                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2530         } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
2531                                  MAC_STATUS_SIGNAL_DET)) {
2532                 sg_dig_status = tr32(SG_DIG_STATUS);
2533                 mac_status = tr32(MAC_STATUS);
2534
2535                 if ((sg_dig_status & (1 << 1)) &&
2536                     (mac_status & MAC_STATUS_PCS_SYNCED)) {
2537                         u32 local_adv, remote_adv;
2538
2539                         local_adv = ADVERTISE_PAUSE_CAP;
2540                         remote_adv = 0;
2541                         if (sg_dig_status & (1 << 19))
2542                                 remote_adv |= LPA_PAUSE_CAP;
2543                         if (sg_dig_status & (1 << 20))
2544                                 remote_adv |= LPA_PAUSE_ASYM;
2545
2546                         tg3_setup_flow_control(tp, local_adv, remote_adv);
2547                         current_link_up = 1;
2548                         tp->serdes_counter = 0;
2549                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2550                 } else if (!(sg_dig_status & (1 << 1))) {
2551                         if (tp->serdes_counter)
2552                                 tp->serdes_counter--;
2553                         else {
2554                                 if (workaround) {
2555                                         u32 val = serdes_cfg;
2556
2557                                         if (port_a)
2558                                                 val |= 0xc010000;
2559                                         else
2560                                                 val |= 0x4010000;
2561
2562                                         tw32_f(MAC_SERDES_CFG, val);
2563                                 }
2564
2565                                 tw32_f(SG_DIG_CTRL, 0x01388400);
2566                                 udelay(40);
2567
2568                                 /* Link parallel detection - link is up */
2569                                 /* only if we have PCS_SYNC and not */
2570                                 /* receiving config code words */
2571                                 mac_status = tr32(MAC_STATUS);
2572                                 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
2573                                     !(mac_status & MAC_STATUS_RCVD_CFG)) {
2574                                         tg3_setup_flow_control(tp, 0, 0);
2575                                         current_link_up = 1;
2576                                         tp->tg3_flags2 |=
2577                                                 TG3_FLG2_PARALLEL_DETECT;
2578                                         tp->serdes_counter =
2579                                                 SERDES_PARALLEL_DET_TIMEOUT;
2580                                 } else
2581                                         goto restart_autoneg;
2582                         }
2583                 }
2584         } else {
2585                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
2586                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2587         }
2588
2589 out:
2590         return current_link_up;
2591 }
2592
2593 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
2594 {
2595         int current_link_up = 0;
2596
2597         if (!(mac_status & MAC_STATUS_PCS_SYNCED)) {
2598                 tp->tg3_flags &= ~TG3_FLAG_GOT_SERDES_FLOWCTL;
2599                 goto out;
2600         }
2601
2602         if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2603                 u32 flags;
2604                 int i;
2605
2606                 if (fiber_autoneg(tp, &flags)) {
2607                         u32 local_adv, remote_adv;
2608
2609                         local_adv = ADVERTISE_PAUSE_CAP;
2610                         remote_adv = 0;
2611                         if (flags & MR_LP_ADV_SYM_PAUSE)
2612                                 remote_adv |= LPA_PAUSE_CAP;
2613                         if (flags & MR_LP_ADV_ASYM_PAUSE)
2614                                 remote_adv |= LPA_PAUSE_ASYM;
2615
2616                         tg3_setup_flow_control(tp, local_adv, remote_adv);
2617
2618                         tp->tg3_flags |= TG3_FLAG_GOT_SERDES_FLOWCTL;
2619                         current_link_up = 1;
2620                 }
2621                 for (i = 0; i < 30; i++) {
2622                         udelay(20);
2623                         tw32_f(MAC_STATUS,
2624                                (MAC_STATUS_SYNC_CHANGED |
2625                                 MAC_STATUS_CFG_CHANGED));
2626                         udelay(40);
2627                         if ((tr32(MAC_STATUS) &
2628                              (MAC_STATUS_SYNC_CHANGED |
2629                               MAC_STATUS_CFG_CHANGED)) == 0)
2630                                 break;
2631                 }
2632
2633                 mac_status = tr32(MAC_STATUS);
2634                 if (current_link_up == 0 &&
2635                     (mac_status & MAC_STATUS_PCS_SYNCED) &&
2636                     !(mac_status & MAC_STATUS_RCVD_CFG))
2637                         current_link_up = 1;
2638         } else {
2639                 /* Forcing 1000FD link up. */
2640                 current_link_up = 1;
2641                 tp->tg3_flags |= TG3_FLAG_GOT_SERDES_FLOWCTL;
2642
2643                 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
2644                 udelay(40);
2645         }
2646
2647 out:
2648         return current_link_up;
2649 }
2650
2651 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
2652 {
2653         u32 orig_pause_cfg;
2654         u16 orig_active_speed;
2655         u8 orig_active_duplex;
2656         u32 mac_status;
2657         int current_link_up;
2658         int i;
2659
2660         orig_pause_cfg =
2661                 (tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
2662                                   TG3_FLAG_TX_PAUSE));
2663         orig_active_speed = tp->link_config.active_speed;
2664         orig_active_duplex = tp->link_config.active_duplex;
2665
2666         if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
2667             netif_carrier_ok(tp->dev) &&
2668             (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
2669                 mac_status = tr32(MAC_STATUS);
2670                 mac_status &= (MAC_STATUS_PCS_SYNCED |
2671                                MAC_STATUS_SIGNAL_DET |
2672                                MAC_STATUS_CFG_CHANGED |
2673                                MAC_STATUS_RCVD_CFG);
2674                 if (mac_status == (MAC_STATUS_PCS_SYNCED |
2675                                    MAC_STATUS_SIGNAL_DET)) {
2676                         tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2677                                             MAC_STATUS_CFG_CHANGED));
2678                         return 0;
2679                 }
2680         }
2681
2682         tw32_f(MAC_TX_AUTO_NEG, 0);
2683
2684         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
2685         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
2686         tw32_f(MAC_MODE, tp->mac_mode);
2687         udelay(40);
2688
2689         if (tp->phy_id == PHY_ID_BCM8002)
2690                 tg3_init_bcm8002(tp);
2691
2692         /* Enable link change event even when serdes polling.  */
2693         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2694         udelay(40);
2695
2696         current_link_up = 0;
2697         mac_status = tr32(MAC_STATUS);
2698
2699         if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
2700                 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
2701         else
2702                 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
2703
2704         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
2705         tw32_f(MAC_MODE, tp->mac_mode);
2706         udelay(40);
2707
2708         tp->hw_status->status =
2709                 (SD_STATUS_UPDATED |
2710                  (tp->hw_status->status & ~SD_STATUS_LINK_CHG));
2711
2712         for (i = 0; i < 100; i++) {
2713                 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2714                                     MAC_STATUS_CFG_CHANGED));
2715                 udelay(5);
2716                 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
2717                                          MAC_STATUS_CFG_CHANGED |
2718                                          MAC_STATUS_LNKSTATE_CHANGED)) == 0)
2719                         break;
2720         }
2721
2722         mac_status = tr32(MAC_STATUS);
2723         if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
2724                 current_link_up = 0;
2725                 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
2726                     tp->serdes_counter == 0) {
2727                         tw32_f(MAC_MODE, (tp->mac_mode |
2728                                           MAC_MODE_SEND_CONFIGS));
2729                         udelay(1);
2730                         tw32_f(MAC_MODE, tp->mac_mode);
2731                 }
2732         }
2733
2734         if (current_link_up == 1) {
2735                 tp->link_config.active_speed = SPEED_1000;
2736                 tp->link_config.active_duplex = DUPLEX_FULL;
2737                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
2738                                     LED_CTRL_LNKLED_OVERRIDE |
2739                                     LED_CTRL_1000MBPS_ON));
2740         } else {
2741                 tp->link_config.active_speed = SPEED_INVALID;
2742                 tp->link_config.active_duplex = DUPLEX_INVALID;
2743                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
2744                                     LED_CTRL_LNKLED_OVERRIDE |
2745                                     LED_CTRL_TRAFFIC_OVERRIDE));
2746         }
2747
2748         if (current_link_up != netif_carrier_ok(tp->dev)) {
2749                 if (current_link_up)
2750                         netif_carrier_on(tp->dev);
2751                 else
2752                         netif_carrier_off(tp->dev);
2753                 tg3_link_report(tp);
2754         } else {
2755                 u32 now_pause_cfg =
2756                         tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
2757                                          TG3_FLAG_TX_PAUSE);
2758                 if (orig_pause_cfg != now_pause_cfg ||
2759                     orig_active_speed != tp->link_config.active_speed ||
2760                     orig_active_duplex != tp->link_config.active_duplex)
2761                         tg3_link_report(tp);
2762         }
2763
2764         return 0;
2765 }
2766
2767 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
2768 {
2769         int current_link_up, err = 0;
2770         u32 bmsr, bmcr;
2771         u16 current_speed;
2772         u8 current_duplex;
2773
2774         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2775         tw32_f(MAC_MODE, tp->mac_mode);
2776         udelay(40);
2777
2778         tw32(MAC_EVENT, 0);
2779
2780         tw32_f(MAC_STATUS,
2781              (MAC_STATUS_SYNC_CHANGED |
2782               MAC_STATUS_CFG_CHANGED |
2783               MAC_STATUS_MI_COMPLETION |
2784               MAC_STATUS_LNKSTATE_CHANGED));
2785         udelay(40);
2786
2787         if (force_reset)
2788                 tg3_phy_reset(tp);
2789
2790         current_link_up = 0;
2791         current_speed = SPEED_INVALID;
2792         current_duplex = DUPLEX_INVALID;
2793
2794         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2795         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2796         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
2797                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
2798                         bmsr |= BMSR_LSTATUS;
2799                 else
2800                         bmsr &= ~BMSR_LSTATUS;
2801         }
2802
2803         err |= tg3_readphy(tp, MII_BMCR, &bmcr);
2804
2805         if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
2806             (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
2807                 /* do nothing, just check for link up at the end */
2808         } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2809                 u32 adv, new_adv;
2810
2811                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
2812                 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
2813                                   ADVERTISE_1000XPAUSE |
2814                                   ADVERTISE_1000XPSE_ASYM |
2815                                   ADVERTISE_SLCT);
2816
2817                 /* Always advertise symmetric PAUSE just like copper */
2818                 new_adv |= ADVERTISE_1000XPAUSE;
2819
2820                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2821                         new_adv |= ADVERTISE_1000XHALF;
2822                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2823                         new_adv |= ADVERTISE_1000XFULL;
2824
2825                 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
2826                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2827                         bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
2828                         tg3_writephy(tp, MII_BMCR, bmcr);
2829
2830                         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2831                         tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
2832                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2833
2834                         return err;
2835                 }
2836         } else {
2837                 u32 new_bmcr;
2838
2839                 bmcr &= ~BMCR_SPEED1000;
2840                 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
2841
2842                 if (tp->link_config.duplex == DUPLEX_FULL)
2843                         new_bmcr |= BMCR_FULLDPLX;
2844
2845                 if (new_bmcr != bmcr) {
2846                         /* BMCR_SPEED1000 is a reserved bit that needs
2847                          * to be set on write.
2848                          */
2849                         new_bmcr |= BMCR_SPEED1000;
2850
2851                         /* Force a linkdown */
2852                         if (netif_carrier_ok(tp->dev)) {
2853                                 u32 adv;
2854
2855                                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
2856                                 adv &= ~(ADVERTISE_1000XFULL |
2857                                          ADVERTISE_1000XHALF |
2858                                          ADVERTISE_SLCT);
2859                                 tg3_writephy(tp, MII_ADVERTISE, adv);
2860                                 tg3_writephy(tp, MII_BMCR, bmcr |
2861                                                            BMCR_ANRESTART |
2862                                                            BMCR_ANENABLE);
2863                                 udelay(10);
2864                                 netif_carrier_off(tp->dev);
2865                         }
2866                         tg3_writephy(tp, MII_BMCR, new_bmcr);
2867                         bmcr = new_bmcr;
2868                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2869                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2870                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2871                             ASIC_REV_5714) {
2872                                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
2873                                         bmsr |= BMSR_LSTATUS;
2874                                 else
2875                                         bmsr &= ~BMSR_LSTATUS;
2876                         }
2877                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2878                 }
2879         }
2880
2881         if (bmsr & BMSR_LSTATUS) {
2882                 current_speed = SPEED_1000;
2883                 current_link_up = 1;
2884                 if (bmcr & BMCR_FULLDPLX)
2885                         current_duplex = DUPLEX_FULL;
2886                 else
2887                         current_duplex = DUPLEX_HALF;
2888
2889                 if (bmcr & BMCR_ANENABLE) {
2890                         u32 local_adv, remote_adv, common;
2891
2892                         err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
2893                         err |= tg3_readphy(tp, MII_LPA, &remote_adv);
2894                         common = local_adv & remote_adv;
2895                         if (common & (ADVERTISE_1000XHALF |
2896                                       ADVERTISE_1000XFULL)) {
2897                                 if (common & ADVERTISE_1000XFULL)
2898                                         current_duplex = DUPLEX_FULL;
2899                                 else
2900                                         current_duplex = DUPLEX_HALF;
2901
2902                                 tg3_setup_flow_control(tp, local_adv,
2903                                                        remote_adv);
2904                         }
2905                         else
2906                                 current_link_up = 0;
2907                 }
2908         }
2909
2910         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
2911         if (tp->link_config.active_duplex == DUPLEX_HALF)
2912                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
2913
2914         tw32_f(MAC_MODE, tp->mac_mode);
2915         udelay(40);
2916
2917         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2918
2919         tp->link_config.active_speed = current_speed;
2920         tp->link_config.active_duplex = current_duplex;
2921
2922         if (current_link_up != netif_carrier_ok(tp->dev)) {
2923                 if (current_link_up)
2924                         netif_carrier_on(tp->dev);
2925                 else {
2926                         netif_carrier_off(tp->dev);
2927                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2928                 }
2929                 tg3_link_report(tp);
2930         }
2931         return err;
2932 }
2933
2934 static void tg3_serdes_parallel_detect(struct tg3 *tp)
2935 {
2936         if (tp->serdes_counter) {
2937                 /* Give autoneg time to complete. */
2938                 tp->serdes_counter--;
2939                 return;
2940         }
2941         if (!netif_carrier_ok(tp->dev) &&
2942             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
2943                 u32 bmcr;
2944
2945                 tg3_readphy(tp, MII_BMCR, &bmcr);
2946                 if (bmcr & BMCR_ANENABLE) {
2947                         u32 phy1, phy2;
2948
2949                         /* Select shadow register 0x1f */
2950                         tg3_writephy(tp, 0x1c, 0x7c00);
2951                         tg3_readphy(tp, 0x1c, &phy1);
2952
2953                         /* Select expansion interrupt status register */
2954                         tg3_writephy(tp, 0x17, 0x0f01);
2955                         tg3_readphy(tp, 0x15, &phy2);
2956                         tg3_readphy(tp, 0x15, &phy2);
2957
2958                         if ((phy1 & 0x10) && !(phy2 & 0x20)) {
2959                                 /* We have signal detect and not receiving
2960                                  * config code words, link is up by parallel
2961                                  * detection.
2962                                  */
2963
2964                                 bmcr &= ~BMCR_ANENABLE;
2965                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
2966                                 tg3_writephy(tp, MII_BMCR, bmcr);
2967                                 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
2968                         }
2969                 }
2970         }
2971         else if (netif_carrier_ok(tp->dev) &&
2972                  (tp->link_config.autoneg == AUTONEG_ENABLE) &&
2973                  (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
2974                 u32 phy2;
2975
2976                 /* Select expansion interrupt status register */
2977                 tg3_writephy(tp, 0x17, 0x0f01);
2978                 tg3_readphy(tp, 0x15, &phy2);
2979                 if (phy2 & 0x20) {
2980                         u32 bmcr;
2981
2982                         /* Config code words received, turn on autoneg. */
2983                         tg3_readphy(tp, MII_BMCR, &bmcr);
2984                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
2985
2986                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2987
2988                 }
2989         }
2990 }
2991
2992 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
2993 {
2994         int err;
2995
2996         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2997                 err = tg3_setup_fiber_phy(tp, force_reset);
2998         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
2999                 err = tg3_setup_fiber_mii_phy(tp, force_reset);
3000         } else {
3001                 err = tg3_setup_copper_phy(tp, force_reset);
3002         }
3003
3004         if (tp->link_config.active_speed == SPEED_1000 &&
3005             tp->link_config.active_duplex == DUPLEX_HALF)
3006                 tw32(MAC_TX_LENGTHS,
3007                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
3008                       (6 << TX_LENGTHS_IPG_SHIFT) |
3009                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
3010         else
3011                 tw32(MAC_TX_LENGTHS,
3012                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
3013                       (6 << TX_LENGTHS_IPG_SHIFT) |
3014                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
3015
3016         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
3017                 if (netif_carrier_ok(tp->dev)) {
3018                         tw32(HOSTCC_STAT_COAL_TICKS,
3019                              tp->coal.stats_block_coalesce_usecs);
3020                 } else {
3021                         tw32(HOSTCC_STAT_COAL_TICKS, 0);
3022                 }
3023         }
3024
3025         return err;
3026 }
3027
3028 /* This is called whenever we suspect that the system chipset is re-
3029  * ordering the sequence of MMIO to the tx send mailbox. The symptom
3030  * is bogus tx completions. We try to recover by setting the
3031  * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
3032  * in the workqueue.
3033  */
3034 static void tg3_tx_recover(struct tg3 *tp)
3035 {
3036         BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
3037                tp->write32_tx_mbox == tg3_write_indirect_mbox);
3038
3039         printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
3040                "mapped I/O cycles to the network device, attempting to "
3041                "recover. Please report the problem to the driver maintainer "
3042                "and include system chipset information.\n", tp->dev->name);
3043
3044         spin_lock(&tp->lock);
3045         tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
3046         spin_unlock(&tp->lock);
3047 }
3048
3049 static inline u32 tg3_tx_avail(struct tg3 *tp)
3050 {
3051         smp_mb();
3052         return (tp->tx_pending -
3053                 ((tp->tx_prod - tp->tx_cons) & (TG3_TX_RING_SIZE - 1)));
3054 }
3055
3056 /* Tigon3 never reports partial packet sends.  So we do not
3057  * need special logic to handle SKBs that have not had all
3058  * of their frags sent yet, like SunGEM does.
3059  */
3060 static void tg3_tx(struct tg3 *tp)
3061 {
3062         u32 hw_idx = tp->hw_status->idx[0].tx_consumer;
3063         u32 sw_idx = tp->tx_cons;
3064
3065         while (sw_idx != hw_idx) {
3066                 struct tx_ring_info *ri = &tp->tx_buffers[sw_idx];
3067                 struct sk_buff *skb = ri->skb;
3068                 int i, tx_bug = 0;
3069
3070                 if (unlikely(skb == NULL)) {
3071                         tg3_tx_recover(tp);
3072                         return;
3073                 }
3074
3075                 pci_unmap_single(tp->pdev,
3076                                  pci_unmap_addr(ri, mapping),
3077                                  skb_headlen(skb),
3078                                  PCI_DMA_TODEVICE);
3079
3080                 ri->skb = NULL;
3081
3082                 sw_idx = NEXT_TX(sw_idx);
3083
3084                 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
3085                         ri = &tp->tx_buffers[sw_idx];
3086                         if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
3087                                 tx_bug = 1;
3088
3089                         pci_unmap_page(tp->pdev,
3090                                        pci_unmap_addr(ri, mapping),
3091                                        skb_shinfo(skb)->frags[i].size,
3092                                        PCI_DMA_TODEVICE);
3093
3094                         sw_idx = NEXT_TX(sw_idx);
3095                 }
3096
3097                 dev_kfree_skb(skb);
3098
3099                 if (unlikely(tx_bug)) {
3100                         tg3_tx_recover(tp);
3101                         return;
3102                 }
3103         }
3104
3105         tp->tx_cons = sw_idx;
3106
3107         /* Need to make the tx_cons update visible to tg3_start_xmit()
3108          * before checking for netif_queue_stopped().  Without the
3109          * memory barrier, there is a small possibility that tg3_start_xmit()
3110          * will miss it and cause the queue to be stopped forever.
3111          */
3112         smp_mb();
3113
3114         if (unlikely(netif_queue_stopped(tp->dev) &&
3115                      (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))) {
3116                 netif_tx_lock(tp->dev);
3117                 if (netif_queue_stopped(tp->dev) &&
3118                     (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))
3119                         netif_wake_queue(tp->dev);
3120                 netif_tx_unlock(tp->dev);
3121         }
3122 }
3123
3124 /* Returns size of skb allocated or < 0 on error.
3125  *
3126  * We only need to fill in the address because the other members
3127  * of the RX descriptor are invariant, see tg3_init_rings.
3128  *
3129  * Note the purposeful assymetry of cpu vs. chip accesses.  For
3130  * posting buffers we only dirty the first cache line of the RX
3131  * descriptor (containing the address).  Whereas for the RX status
3132  * buffers the cpu only reads the last cacheline of the RX descriptor
3133  * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
3134  */
3135 static int tg3_alloc_rx_skb(struct tg3 *tp, u32 opaque_key,
3136                             int src_idx, u32 dest_idx_unmasked)
3137 {
3138         struct tg3_rx_buffer_desc *desc;
3139         struct ring_info *map, *src_map;
3140         struct sk_buff *skb;
3141         dma_addr_t mapping;
3142         int skb_size, dest_idx;
3143
3144         src_map = NULL;
3145         switch (opaque_key) {
3146         case RXD_OPAQUE_RING_STD:
3147                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
3148                 desc = &tp->rx_std[dest_idx];
3149                 map = &tp->rx_std_buffers[dest_idx];
3150                 if (src_idx >= 0)
3151                         src_map = &tp->rx_std_buffers[src_idx];
3152                 skb_size = tp->rx_pkt_buf_sz;
3153                 break;
3154
3155         case RXD_OPAQUE_RING_JUMBO:
3156                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
3157                 desc = &tp->rx_jumbo[dest_idx];
3158                 map = &tp->rx_jumbo_buffers[dest_idx];
3159                 if (src_idx >= 0)
3160                         src_map = &tp->rx_jumbo_buffers[src_idx];
3161                 skb_size = RX_JUMBO_PKT_BUF_SZ;
3162                 break;
3163
3164         default:
3165                 return -EINVAL;
3166         };
3167
3168         /* Do not overwrite any of the map or rp information
3169          * until we are sure we can commit to a new buffer.
3170          *
3171          * Callers depend upon this behavior and assume that
3172          * we leave everything unchanged if we fail.
3173          */
3174         skb = netdev_alloc_skb(tp->dev, skb_size);
3175         if (skb == NULL)
3176                 return -ENOMEM;
3177
3178         skb_reserve(skb, tp->rx_offset);
3179
3180         mapping = pci_map_single(tp->pdev, skb->data,
3181                                  skb_size - tp->rx_offset,
3182                                  PCI_DMA_FROMDEVICE);
3183
3184         map->skb = skb;
3185         pci_unmap_addr_set(map, mapping, mapping);
3186
3187         if (src_map != NULL)
3188                 src_map->skb = NULL;
3189
3190         desc->addr_hi = ((u64)mapping >> 32);
3191         desc->addr_lo = ((u64)mapping & 0xffffffff);
3192
3193         return skb_size;
3194 }
3195
3196 /* We only need to move over in the address because the other
3197  * members of the RX descriptor are invariant.  See notes above
3198  * tg3_alloc_rx_skb for full details.
3199  */
3200 static void tg3_recycle_rx(struct tg3 *tp, u32 opaque_key,
3201                            int src_idx, u32 dest_idx_unmasked)
3202 {
3203         struct tg3_rx_buffer_desc *src_desc, *dest_desc;
3204         struct ring_info *src_map, *dest_map;
3205         int dest_idx;
3206
3207         switch (opaque_key) {
3208         case RXD_OPAQUE_RING_STD:
3209                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
3210                 dest_desc = &tp->rx_std[dest_idx];
3211                 dest_map = &tp->rx_std_buffers[dest_idx];
3212                 src_desc = &tp->rx_std[src_idx];
3213                 src_map = &tp->rx_std_buffers[src_idx];
3214                 break;
3215
3216         case RXD_OPAQUE_RING_JUMBO:
3217                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
3218                 dest_desc = &tp->rx_jumbo[dest_idx];
3219                 dest_map = &tp->rx_jumbo_buffers[dest_idx];
3220                 src_desc = &tp->rx_jumbo[src_idx];
3221                 src_map = &tp->rx_jumbo_buffers[src_idx];
3222                 break;
3223
3224         default:
3225                 return;
3226         };
3227
3228         dest_map->skb = src_map->skb;
3229         pci_unmap_addr_set(dest_map, mapping,
3230                            pci_unmap_addr(src_map, mapping));
3231         dest_desc->addr_hi = src_desc->addr_hi;
3232         dest_desc->addr_lo = src_desc->addr_lo;
3233
3234         src_map->skb = NULL;
3235 }
3236
3237 #if TG3_VLAN_TAG_USED
3238 static int tg3_vlan_rx(struct tg3 *tp, struct sk_buff *skb, u16 vlan_tag)
3239 {
3240         return vlan_hwaccel_receive_skb(skb, tp->vlgrp, vlan_tag);
3241 }
3242 #endif
3243
3244 /* The RX ring scheme is composed of multiple rings which post fresh
3245  * buffers to the chip, and one special ring the chip uses to report
3246  * status back to the host.
3247  *
3248  * The special ring reports the status of received packets to the
3249  * host.  The chip does not write into the original descriptor the
3250  * RX buffer was obtained from.  The chip simply takes the original
3251  * descriptor as provided by the host, updates the status and length
3252  * field, then writes this into the next status ring entry.
3253  *
3254  * Each ring the host uses to post buffers to the chip is described
3255  * by a TG3_BDINFO entry in the chips SRAM area.  When a packet arrives,
3256  * it is first placed into the on-chip ram.  When the packet's length
3257  * is known, it walks down the TG3_BDINFO entries to select the ring.
3258  * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
3259  * which is within the range of the new packet's length is chosen.
3260  *
3261  * The "separate ring for rx status" scheme may sound queer, but it makes
3262  * sense from a cache coherency perspective.  If only the host writes
3263  * to the buffer post rings, and only the chip writes to the rx status
3264  * rings, then cache lines never move beyond shared-modified state.
3265  * If both the host and chip were to write into the same ring, cache line
3266  * eviction could occur since both entities want it in an exclusive state.
3267  */
3268 static int tg3_rx(struct tg3 *tp, int budget)
3269 {
3270         u32 work_mask, rx_std_posted = 0;
3271         u32 sw_idx = tp->rx_rcb_ptr;
3272         u16 hw_idx;
3273         int received;
3274
3275         hw_idx = tp->hw_status->idx[0].rx_producer;
3276         /*
3277          * We need to order the read of hw_idx and the read of
3278          * the opaque cookie.
3279          */
3280         rmb();
3281         work_mask = 0;
3282         received = 0;
3283         while (sw_idx != hw_idx && budget > 0) {
3284                 struct tg3_rx_buffer_desc *desc = &tp->rx_rcb[sw_idx];
3285                 unsigned int len;
3286                 struct sk_buff *skb;
3287                 dma_addr_t dma_addr;
3288                 u32 opaque_key, desc_idx, *post_ptr;
3289
3290                 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
3291                 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
3292                 if (opaque_key == RXD_OPAQUE_RING_STD) {
3293                         dma_addr = pci_unmap_addr(&tp->rx_std_buffers[desc_idx],
3294                                                   mapping);
3295                         skb = tp->rx_std_buffers[desc_idx].skb;
3296                         post_ptr = &tp->rx_std_ptr;
3297                         rx_std_posted++;
3298                 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
3299                         dma_addr = pci_unmap_addr(&tp->rx_jumbo_buffers[desc_idx],
3300                                                   mapping);
3301                         skb = tp->rx_jumbo_buffers[desc_idx].skb;
3302                         post_ptr = &tp->rx_jumbo_ptr;
3303                 }
3304                 else {
3305                         goto next_pkt_nopost;
3306                 }
3307
3308                 work_mask |= opaque_key;
3309
3310                 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
3311                     (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
3312                 drop_it:
3313                         tg3_recycle_rx(tp, opaque_key,
3314                                        desc_idx, *post_ptr);
3315                 drop_it_no_recycle:
3316                         /* Other statistics kept track of by card. */
3317                         tp->net_stats.rx_dropped++;
3318                         goto next_pkt;
3319                 }
3320
3321                 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4; /* omit crc */
3322
3323                 if (len > RX_COPY_THRESHOLD
3324                         && tp->rx_offset == 2
3325                         /* rx_offset != 2 iff this is a 5701 card running
3326                          * in PCI-X mode [see tg3_get_invariants()] */
3327                 ) {
3328                         int skb_size;
3329
3330                         skb_size = tg3_alloc_rx_skb(tp, opaque_key,
3331                                                     desc_idx, *post_ptr);
3332                         if (skb_size < 0)
3333                                 goto drop_it;
3334
3335                         pci_unmap_single(tp->pdev, dma_addr,
3336                                          skb_size - tp->rx_offset,
3337                                          PCI_DMA_FROMDEVICE);
3338
3339                         skb_put(skb, len);
3340                 } else {
3341                         struct sk_buff *copy_skb;
3342
3343                         tg3_recycle_rx(tp, opaque_key,
3344                                        desc_idx, *post_ptr);
3345
3346                         copy_skb = netdev_alloc_skb(tp->dev, len + 2);
3347                         if (copy_skb == NULL)
3348                                 goto drop_it_no_recycle;
3349
3350                         skb_reserve(copy_skb, 2);
3351                         skb_put(copy_skb, len);
3352                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
3353                         memcpy(copy_skb->data, skb->data, len);
3354                         pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
3355
3356                         /* We'll reuse the original ring buffer. */
3357                         skb = copy_skb;
3358                 }
3359
3360                 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
3361                     (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
3362                     (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
3363                       >> RXD_TCPCSUM_SHIFT) == 0xffff))
3364                         skb->ip_summed = CHECKSUM_UNNECESSARY;
3365                 else
3366                         skb->ip_summed = CHECKSUM_NONE;
3367
3368                 skb->protocol = eth_type_trans(skb, tp->dev);
3369 #if TG3_VLAN_TAG_USED
3370                 if (tp->vlgrp != NULL &&
3371                     desc->type_flags & RXD_FLAG_VLAN) {
3372                         tg3_vlan_rx(tp, skb,
3373                                     desc->err_vlan & RXD_VLAN_MASK);
3374                 } else
3375 #endif
3376                         netif_receive_skb(skb);
3377
3378                 tp->dev->last_rx = jiffies;
3379                 received++;
3380                 budget--;
3381
3382 next_pkt:
3383                 (*post_ptr)++;
3384
3385                 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
3386                         u32 idx = *post_ptr % TG3_RX_RING_SIZE;
3387
3388                         tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX +
3389                                      TG3_64BIT_REG_LOW, idx);
3390                         work_mask &= ~RXD_OPAQUE_RING_STD;
3391                         rx_std_posted = 0;
3392                 }
3393 next_pkt_nopost:
3394                 sw_idx++;
3395                 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
3396
3397                 /* Refresh hw_idx to see if there is new work */
3398                 if (sw_idx == hw_idx) {
3399                         hw_idx = tp->hw_status->idx[0].rx_producer;
3400                         rmb();
3401                 }
3402         }
3403
3404         /* ACK the status ring. */
3405         tp->rx_rcb_ptr = sw_idx;
3406         tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, sw_idx);
3407
3408         /* Refill RX ring(s). */
3409         if (work_mask & RXD_OPAQUE_RING_STD) {
3410                 sw_idx = tp->rx_std_ptr % TG3_RX_RING_SIZE;
3411                 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
3412                              sw_idx);
3413         }
3414         if (work_mask & RXD_OPAQUE_RING_JUMBO) {
3415                 sw_idx = tp->rx_jumbo_ptr % TG3_RX_JUMBO_RING_SIZE;
3416                 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
3417                              sw_idx);
3418         }
3419         mmiowb();
3420
3421         return received;
3422 }
3423
3424 static int tg3_poll(struct net_device *netdev, int *budget)
3425 {
3426         struct tg3 *tp = netdev_priv(netdev);
3427         struct tg3_hw_status *sblk = tp->hw_status;
3428         int done;
3429
3430         /* handle link change and other phy events */
3431         if (!(tp->tg3_flags &
3432               (TG3_FLAG_USE_LINKCHG_REG |
3433                TG3_FLAG_POLL_SERDES))) {
3434                 if (sblk->status & SD_STATUS_LINK_CHG) {
3435                         sblk->status = SD_STATUS_UPDATED |
3436                                 (sblk->status & ~SD_STATUS_LINK_CHG);
3437                         spin_lock(&tp->lock);
3438                         tg3_setup_phy(tp, 0);
3439                         spin_unlock(&tp->lock);
3440                 }
3441         }
3442
3443         /* run TX completion thread */
3444         if (sblk->idx[0].tx_consumer != tp->tx_cons) {
3445                 tg3_tx(tp);
3446                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING)) {
3447                         netif_rx_complete(netdev);
3448                         schedule_work(&tp->reset_task);
3449                         return 0;
3450                 }
3451         }
3452
3453         /* run RX thread, within the bounds set by NAPI.
3454          * All RX "locking" is done by ensuring outside
3455          * code synchronizes with dev->poll()
3456          */
3457         if (sblk->idx[0].rx_producer != tp->rx_rcb_ptr) {
3458                 int orig_budget = *budget;
3459                 int work_done;
3460
3461                 if (orig_budget > netdev->quota)
3462                         orig_budget = netdev->quota;
3463
3464                 work_done = tg3_rx(tp, orig_budget);
3465
3466                 *budget -= work_done;
3467                 netdev->quota -= work_done;
3468         }
3469
3470         if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
3471                 tp->last_tag = sblk->status_tag;
3472                 rmb();
3473         } else
3474                 sblk->status &= ~SD_STATUS_UPDATED;
3475
3476         /* if no more work, tell net stack and NIC we're done */
3477         done = !tg3_has_work(tp);
3478         if (done) {
3479                 netif_rx_complete(netdev);
3480                 tg3_restart_ints(tp);
3481         }
3482
3483         return (done ? 0 : 1);
3484 }
3485
3486 static void tg3_irq_quiesce(struct tg3 *tp)
3487 {
3488         BUG_ON(tp->irq_sync);
3489
3490         tp->irq_sync = 1;
3491         smp_mb();
3492
3493         synchronize_irq(tp->pdev->irq);
3494 }
3495
3496 static inline int tg3_irq_sync(struct tg3 *tp)
3497 {
3498         return tp->irq_sync;
3499 }
3500
3501 /* Fully shutdown all tg3 driver activity elsewhere in the system.
3502  * If irq_sync is non-zero, then the IRQ handler must be synchronized
3503  * with as well.  Most of the time, this is not necessary except when
3504  * shutting down the device.
3505  */
3506 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
3507 {
3508         if (irq_sync)
3509                 tg3_irq_quiesce(tp);
3510         spin_lock_bh(&tp->lock);
3511 }
3512
3513 static inline void tg3_full_unlock(struct tg3 *tp)
3514 {
3515         spin_unlock_bh(&tp->lock);
3516 }
3517
3518 /* One-shot MSI handler - Chip automatically disables interrupt
3519  * after sending MSI so driver doesn't have to do it.
3520  */
3521 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
3522 {
3523         struct net_device *dev = dev_id;
3524         struct tg3 *tp = netdev_priv(dev);
3525
3526         prefetch(tp->hw_status);
3527         prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3528
3529         if (likely(!tg3_irq_sync(tp)))
3530                 netif_rx_schedule(dev);         /* schedule NAPI poll */
3531
3532         return IRQ_HANDLED;
3533 }
3534
3535 /* MSI ISR - No need to check for interrupt sharing and no need to
3536  * flush status block and interrupt mailbox. PCI ordering rules
3537  * guarantee that MSI will arrive after the status block.
3538  */
3539 static irqreturn_t tg3_msi(int irq, void *dev_id)
3540 {
3541         struct net_device *dev = dev_id;
3542         struct tg3 *tp = netdev_priv(dev);
3543
3544         prefetch(tp->hw_status);
3545         prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3546         /*
3547          * Writing any value to intr-mbox-0 clears PCI INTA# and
3548          * chip-internal interrupt pending events.
3549          * Writing non-zero to intr-mbox-0 additional tells the
3550          * NIC to stop sending us irqs, engaging "in-intr-handler"
3551          * event coalescing.
3552          */
3553         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
3554         if (likely(!tg3_irq_sync(tp)))
3555                 netif_rx_schedule(dev);         /* schedule NAPI poll */
3556
3557         return IRQ_RETVAL(1);
3558 }
3559
3560 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
3561 {
3562         struct net_device *dev = dev_id;
3563         struct tg3 *tp = netdev_priv(dev);
3564         struct tg3_hw_status *sblk = tp->hw_status;
3565         unsigned int handled = 1;
3566
3567         /* In INTx mode, it is possible for the interrupt to arrive at
3568          * the CPU before the status block posted prior to the interrupt.
3569          * Reading the PCI State register will confirm whether the
3570          * interrupt is ours and will flush the status block.
3571          */
3572         if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
3573                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
3574                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3575                         handled = 0;
3576                         goto out;
3577                 }
3578         }
3579
3580         /*
3581          * Writing any value to intr-mbox-0 clears PCI INTA# and
3582          * chip-internal interrupt pending events.
3583          * Writing non-zero to intr-mbox-0 additional tells the
3584          * NIC to stop sending us irqs, engaging "in-intr-handler"
3585          * event coalescing.
3586          */
3587         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
3588         if (tg3_irq_sync(tp))
3589                 goto out;
3590         sblk->status &= ~SD_STATUS_UPDATED;
3591         if (likely(tg3_has_work(tp))) {
3592                 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3593                 netif_rx_schedule(dev);         /* schedule NAPI poll */
3594         } else {
3595                 /* No work, shared interrupt perhaps?  re-enable
3596                  * interrupts, and flush that PCI write
3597                  */
3598                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3599                                0x00000000);
3600         }
3601 out:
3602         return IRQ_RETVAL(handled);
3603 }
3604
3605 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
3606 {
3607         struct net_device *dev = dev_id;
3608         struct tg3 *tp = netdev_priv(dev);
3609         struct tg3_hw_status *sblk = tp->hw_status;
3610         unsigned int handled = 1;
3611
3612         /* In INTx mode, it is possible for the interrupt to arrive at
3613          * the CPU before the status block posted prior to the interrupt.
3614          * Reading the PCI State register will confirm whether the
3615          * interrupt is ours and will flush the status block.
3616          */
3617         if (unlikely(sblk->status_tag == tp->last_tag)) {
3618                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
3619                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3620                         handled = 0;
3621                         goto out;
3622                 }
3623         }
3624
3625         /*
3626          * writing any value to intr-mbox-0 clears PCI INTA# and
3627          * chip-internal interrupt pending events.
3628          * writing non-zero to intr-mbox-0 additional tells the
3629          * NIC to stop sending us irqs, engaging "in-intr-handler"
3630          * event coalescing.
3631          */
3632         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
3633         if (tg3_irq_sync(tp))
3634                 goto out;
3635         if (netif_rx_schedule_prep(dev)) {
3636                 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3637                 /* Update last_tag to mark that this status has been
3638                  * seen. Because interrupt may be shared, we may be
3639                  * racing with tg3_poll(), so only update last_tag
3640                  * if tg3_poll() is not scheduled.
3641                  */
3642                 tp->last_tag = sblk->status_tag;
3643                 __netif_rx_schedule(dev);
3644         }
3645 out:
3646         return IRQ_RETVAL(handled);
3647 }
3648
3649 /* ISR for interrupt test */
3650 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
3651 {
3652         struct net_device *dev = dev_id;
3653         struct tg3 *tp = netdev_priv(dev);
3654         struct tg3_hw_status *sblk = tp->hw_status;
3655
3656         if ((sblk->status & SD_STATUS_UPDATED) ||
3657             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3658                 tg3_disable_ints(tp);
3659                 return IRQ_RETVAL(1);
3660         }
3661         return IRQ_RETVAL(0);
3662 }
3663
3664 static int tg3_init_hw(struct tg3 *, int);
3665 static int tg3_halt(struct tg3 *, int, int);
3666
3667 /* Restart hardware after configuration changes, self-test, etc.
3668  * Invoked with tp->lock held.
3669  */
3670 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
3671 {
3672         int err;
3673
3674         err = tg3_init_hw(tp, reset_phy);
3675         if (err) {
3676                 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
3677                        "aborting.\n", tp->dev->name);
3678                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
3679                 tg3_full_unlock(tp);
3680                 del_timer_sync(&tp->timer);
3681                 tp->irq_sync = 0;
3682                 netif_poll_enable(tp->dev);
3683                 dev_close(tp->dev);
3684                 tg3_full_lock(tp, 0);
3685         }
3686         return err;
3687 }
3688
3689 #ifdef CONFIG_NET_POLL_CONTROLLER
3690 static void tg3_poll_controller(struct net_device *dev)
3691 {
3692         struct tg3 *tp = netdev_priv(dev);
3693
3694         tg3_interrupt(tp->pdev->irq, dev);
3695 }
3696 #endif
3697
3698 static void tg3_reset_task(struct work_struct *work)
3699 {
3700         struct tg3 *tp = container_of(work, struct tg3, reset_task);
3701         unsigned int restart_timer;
3702
3703         tg3_full_lock(tp, 0);
3704         tp->tg3_flags |= TG3_FLAG_IN_RESET_TASK;
3705
3706         if (!netif_running(tp->dev)) {
3707                 tp->tg3_flags &= ~TG3_FLAG_IN_RESET_TASK;
3708                 tg3_full_unlock(tp);
3709                 return;
3710         }
3711
3712         tg3_full_unlock(tp);
3713
3714         tg3_netif_stop(tp);
3715
3716         tg3_full_lock(tp, 1);
3717
3718         restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
3719         tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
3720
3721         if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
3722                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
3723                 tp->write32_rx_mbox = tg3_write_flush_reg32;
3724                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
3725                 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
3726         }
3727
3728         tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
3729         if (tg3_init_hw(tp, 1))
3730                 goto out;
3731
3732         tg3_netif_start(tp);
3733
3734         if (restart_timer)
3735                 mod_timer(&tp->timer, jiffies + 1);
3736
3737 out:
3738         tp->tg3_flags &= ~TG3_FLAG_IN_RESET_TASK;
3739
3740         tg3_full_unlock(tp);
3741 }
3742
3743 static void tg3_dump_short_state(struct tg3 *tp)
3744 {
3745         printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
3746                tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
3747         printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
3748                tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
3749 }
3750
3751 static void tg3_tx_timeout(struct net_device *dev)
3752 {
3753         struct tg3 *tp = netdev_priv(dev);
3754
3755         if (netif_msg_tx_err(tp)) {
3756                 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
3757                        dev->name);
3758                 tg3_dump_short_state(tp);
3759         }
3760
3761         schedule_work(&tp->reset_task);
3762 }
3763
3764 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
3765 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
3766 {
3767         u32 base = (u32) mapping & 0xffffffff;
3768
3769         return ((base > 0xffffdcc0) &&
3770                 (base + len + 8 < base));
3771 }
3772
3773 /* Test for DMA addresses > 40-bit */
3774 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
3775                                           int len)
3776 {
3777 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
3778         if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
3779                 return (((u64) mapping + len) > DMA_40BIT_MASK);
3780         return 0;
3781 #else
3782         return 0;
3783 #endif
3784 }
3785
3786 static void tg3_set_txd(struct tg3 *, int, dma_addr_t, int, u32, u32);
3787
3788 /* Workaround 4GB and 40-bit hardware DMA bugs. */
3789 static int tigon3_dma_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
3790                                        u32 last_plus_one, u32 *start,
3791                                        u32 base_flags, u32 mss)
3792 {
3793         struct sk_buff *new_skb = skb_copy(skb, GFP_ATOMIC);
3794         dma_addr_t new_addr = 0;
3795         u32 entry = *start;
3796         int i, ret = 0;
3797
3798         if (!new_skb) {
3799                 ret = -1;
3800         } else {
3801                 /* New SKB is guaranteed to be linear. */
3802                 entry = *start;
3803                 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
3804                                           PCI_DMA_TODEVICE);
3805                 /* Make sure new skb does not cross any 4G boundaries.
3806                  * Drop the packet if it does.
3807                  */
3808                 if (tg3_4g_overflow_test(new_addr, new_skb->len)) {
3809                         ret = -1;
3810                         dev_kfree_skb(new_skb);
3811                         new_skb = NULL;
3812                 } else {
3813                         tg3_set_txd(tp, entry, new_addr, new_skb->len,
3814                                     base_flags, 1 | (mss << 1));
3815                         *start = NEXT_TX(entry);
3816                 }
3817         }
3818
3819         /* Now clean up the sw ring entries. */
3820         i = 0;
3821         while (entry != last_plus_one) {
3822                 int len;
3823
3824                 if (i == 0)
3825                         len = skb_headlen(skb);
3826                 else
3827                         len = skb_shinfo(skb)->frags[i-1].size;
3828                 pci_unmap_single(tp->pdev,
3829                                  pci_unmap_addr(&tp->tx_buffers[entry], mapping),
3830                                  len, PCI_DMA_TODEVICE);
3831                 if (i == 0) {
3832                         tp->tx_buffers[entry].skb = new_skb;
3833                         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, new_addr);
3834                 } else {
3835                         tp->tx_buffers[entry].skb = NULL;
3836                 }
3837                 entry = NEXT_TX(entry);
3838                 i++;
3839         }
3840
3841         dev_kfree_skb(skb);
3842
3843         return ret;
3844 }
3845
3846 static void tg3_set_txd(struct tg3 *tp, int entry,
3847                         dma_addr_t mapping, int len, u32 flags,
3848                         u32 mss_and_is_end)
3849 {
3850         struct tg3_tx_buffer_desc *txd = &tp->tx_ring[entry];
3851         int is_end = (mss_and_is_end & 0x1);
3852         u32 mss = (mss_and_is_end >> 1);
3853         u32 vlan_tag = 0;
3854
3855         if (is_end)
3856                 flags |= TXD_FLAG_END;
3857         if (flags & TXD_FLAG_VLAN) {
3858                 vlan_tag = flags >> 16;
3859                 flags &= 0xffff;
3860         }
3861         vlan_tag |= (mss << TXD_MSS_SHIFT);
3862
3863         txd->addr_hi = ((u64) mapping >> 32);
3864         txd->addr_lo = ((u64) mapping & 0xffffffff);
3865         txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
3866         txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
3867 }
3868
3869 /* hard_start_xmit for devices that don't have any bugs and
3870  * support TG3_FLG2_HW_TSO_2 only.
3871  */
3872 static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
3873 {
3874         struct tg3 *tp = netdev_priv(dev);
3875         dma_addr_t mapping;
3876         u32 len, entry, base_flags, mss;
3877
3878         len = skb_headlen(skb);
3879
3880         /* We are running in BH disabled context with netif_tx_lock
3881          * and TX reclaim runs via tp->poll inside of a software
3882          * interrupt.  Furthermore, IRQ processing runs lockless so we have
3883          * no IRQ context deadlocks to worry about either.  Rejoice!
3884          */
3885         if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
3886                 if (!netif_queue_stopped(dev)) {
3887                         netif_stop_queue(dev);
3888
3889                         /* This is a hard error, log it. */
3890                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
3891                                "queue awake!\n", dev->name);
3892                 }
3893                 return NETDEV_TX_BUSY;
3894         }
3895
3896         entry = tp->tx_prod;
3897         base_flags = 0;
3898         mss = 0;
3899         if (skb->len > (tp->dev->mtu + ETH_HLEN) &&
3900             (mss = skb_shinfo(skb)->gso_size) != 0) {
3901                 int tcp_opt_len, ip_tcp_len;
3902
3903                 if (skb_header_cloned(skb) &&
3904                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
3905                         dev_kfree_skb(skb);
3906                         goto out_unlock;
3907                 }
3908
3909                 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
3910                         mss |= (skb_headlen(skb) - ETH_HLEN) << 9;
3911                 else {
3912                         struct iphdr *iph = ip_hdr(skb);
3913
3914                         tcp_opt_len = ((skb->h.th->doff - 5) * 4);
3915                         ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
3916
3917                         iph->check = 0;
3918                         iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
3919                         mss |= (ip_tcp_len + tcp_opt_len) << 9;
3920                 }
3921
3922                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
3923                                TXD_FLAG_CPU_POST_DMA);
3924
3925                 skb->h.th->check = 0;
3926
3927         }
3928         else if (skb->ip_summed == CHECKSUM_PARTIAL)
3929                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
3930 #if TG3_VLAN_TAG_USED
3931         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
3932                 base_flags |= (TXD_FLAG_VLAN |
3933                                (vlan_tx_tag_get(skb) << 16));
3934 #endif
3935
3936         /* Queue skb data, a.k.a. the main skb fragment. */
3937         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
3938
3939         tp->tx_buffers[entry].skb = skb;
3940         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
3941
3942         tg3_set_txd(tp, entry, mapping, len, base_flags,
3943                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
3944
3945         entry = NEXT_TX(entry);
3946
3947         /* Now loop through additional data fragments, and queue them. */
3948         if (skb_shinfo(skb)->nr_frags > 0) {
3949                 unsigned int i, last;
3950
3951                 last = skb_shinfo(skb)->nr_frags - 1;
3952                 for (i = 0; i <= last; i++) {
3953                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3954
3955                         len = frag->size;
3956                         mapping = pci_map_page(tp->pdev,
3957                                                frag->page,
3958                                                frag->page_offset,
3959                                                len, PCI_DMA_TODEVICE);
3960
3961                         tp->tx_buffers[entry].skb = NULL;
3962                         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
3963
3964                         tg3_set_txd(tp, entry, mapping, len,
3965                                     base_flags, (i == last) | (mss << 1));
3966
3967                         entry = NEXT_TX(entry);
3968                 }
3969         }
3970
3971         /* Packets are ready, update Tx producer idx local and on card. */
3972         tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
3973
3974         tp->tx_prod = entry;
3975         if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
3976                 netif_stop_queue(dev);
3977                 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
3978                         netif_wake_queue(tp->dev);
3979         }
3980
3981 out_unlock:
3982         mmiowb();
3983
3984         dev->trans_start = jiffies;
3985
3986         return NETDEV_TX_OK;
3987 }
3988
3989 static int tg3_start_xmit_dma_bug(struct sk_buff *, struct net_device *);
3990
3991 /* Use GSO to workaround a rare TSO bug that may be triggered when the
3992  * TSO header is greater than 80 bytes.
3993  */
3994 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
3995 {
3996         struct sk_buff *segs, *nskb;
3997
3998         /* Estimate the number of fragments in the worst case */
3999         if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))) {
4000                 netif_stop_queue(tp->dev);
4001                 if (tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))
4002                         return NETDEV_TX_BUSY;
4003
4004                 netif_wake_queue(tp->dev);
4005         }
4006
4007         segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
4008         if (unlikely(IS_ERR(segs)))
4009                 goto tg3_tso_bug_end;
4010
4011         do {
4012                 nskb = segs;
4013                 segs = segs->next;
4014                 nskb->next = NULL;
4015                 tg3_start_xmit_dma_bug(nskb, tp->dev);
4016         } while (segs);
4017
4018 tg3_tso_bug_end:
4019         dev_kfree_skb(skb);
4020
4021         return NETDEV_TX_OK;
4022 }
4023
4024 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
4025  * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
4026  */
4027 static int tg3_start_xmit_dma_bug(struct sk_buff *skb, struct net_device *dev)
4028 {
4029         struct tg3 *tp = netdev_priv(dev);
4030         dma_addr_t mapping;
4031         u32 len, entry, base_flags, mss;
4032         int would_hit_hwbug;
4033
4034         len = skb_headlen(skb);
4035
4036         /* We are running in BH disabled context with netif_tx_lock
4037          * and TX reclaim runs via tp->poll inside of a software
4038          * interrupt.  Furthermore, IRQ processing runs lockless so we have
4039          * no IRQ context deadlocks to worry about either.  Rejoice!
4040          */
4041         if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
4042                 if (!netif_queue_stopped(dev)) {
4043                         netif_stop_queue(dev);
4044
4045                         /* This is a hard error, log it. */
4046                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
4047                                "queue awake!\n", dev->name);
4048                 }
4049                 return NETDEV_TX_BUSY;
4050         }
4051
4052         entry = tp->tx_prod;
4053         base_flags = 0;
4054         if (skb->ip_summed == CHECKSUM_PARTIAL)
4055                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
4056         mss = 0;
4057         if (skb->len > (tp->dev->mtu + ETH_HLEN) &&
4058             (mss = skb_shinfo(skb)->gso_size) != 0) {
4059                 struct iphdr *iph;
4060                 int tcp_opt_len, ip_tcp_len, hdr_len;
4061
4062                 if (skb_header_cloned(skb) &&
4063                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
4064                         dev_kfree_skb(skb);
4065                         goto out_unlock;
4066                 }
4067
4068                 tcp_opt_len = ((skb->h.th->doff - 5) * 4);
4069                 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
4070
4071                 hdr_len = ip_tcp_len + tcp_opt_len;
4072                 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
4073                              (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
4074                         return (tg3_tso_bug(tp, skb));
4075
4076                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
4077                                TXD_FLAG_CPU_POST_DMA);
4078
4079                 iph = ip_hdr(skb);
4080                 iph->check = 0;
4081                 iph->tot_len = htons(mss + hdr_len);
4082                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
4083                         skb->h.th->check = 0;
4084                         base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
4085                 }
4086                 else {
4087                         skb->h.th->check = ~csum_tcpudp_magic(iph->saddr,
4088                                                               iph->daddr, 0,
4089                                                               IPPROTO_TCP, 0);
4090                 }
4091
4092                 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
4093                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
4094                         if (tcp_opt_len || iph->ihl > 5) {
4095                                 int tsflags;
4096
4097                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
4098                                 mss |= (tsflags << 11);
4099                         }
4100                 } else {
4101                         if (tcp_opt_len || iph->ihl > 5) {
4102                                 int tsflags;
4103
4104                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
4105                                 base_flags |= tsflags << 12;
4106                         }
4107                 }
4108         }
4109 #if TG3_VLAN_TAG_USED
4110         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
4111                 base_flags |= (TXD_FLAG_VLAN |
4112                                (vlan_tx_tag_get(skb) << 16));
4113 #endif
4114
4115         /* Queue skb data, a.k.a. the main skb fragment. */
4116         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
4117
4118         tp->tx_buffers[entry].skb = skb;
4119         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4120
4121         would_hit_hwbug = 0;
4122
4123         if (tg3_4g_overflow_test(mapping, len))
4124                 would_hit_hwbug = 1;
4125
4126         tg3_set_txd(tp, entry, mapping, len, base_flags,
4127                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
4128
4129         entry = NEXT_TX(entry);
4130
4131         /* Now loop through additional data fragments, and queue them. */
4132         if (skb_shinfo(skb)->nr_frags > 0) {
4133                 unsigned int i, last;
4134
4135                 last = skb_shinfo(skb)->nr_frags - 1;
4136                 for (i = 0; i <= last; i++) {
4137                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4138
4139                         len = frag->size;
4140                         mapping = pci_map_page(tp->pdev,
4141                                                frag->page,
4142                                                frag->page_offset,
4143                                                len, PCI_DMA_TODEVICE);
4144
4145                         tp->tx_buffers[entry].skb = NULL;
4146                         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4147
4148                         if (tg3_4g_overflow_test(mapping, len))
4149                                 would_hit_hwbug = 1;
4150
4151                         if (tg3_40bit_overflow_test(tp, mapping, len))
4152                                 would_hit_hwbug = 1;
4153
4154                         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
4155                                 tg3_set_txd(tp, entry, mapping, len,
4156                                             base_flags, (i == last)|(mss << 1));
4157                         else
4158                                 tg3_set_txd(tp, entry, mapping, len,
4159                                             base_flags, (i == last));
4160
4161                         entry = NEXT_TX(entry);
4162                 }
4163         }
4164
4165         if (would_hit_hwbug) {
4166                 u32 last_plus_one = entry;
4167                 u32 start;
4168
4169                 start = entry - 1 - skb_shinfo(skb)->nr_frags;
4170                 start &= (TG3_TX_RING_SIZE - 1);
4171
4172                 /* If the workaround fails due to memory/mapping
4173                  * failure, silently drop this packet.
4174                  */
4175                 if (tigon3_dma_hwbug_workaround(tp, skb, last_plus_one,
4176                                                 &start, base_flags, mss))
4177                         goto out_unlock;
4178
4179                 entry = start;
4180         }
4181
4182         /* Packets are ready, update Tx producer idx local and on card. */
4183         tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
4184
4185         tp->tx_prod = entry;
4186         if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
4187                 netif_stop_queue(dev);
4188                 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
4189                         netif_wake_queue(tp->dev);
4190         }
4191
4192 out_unlock:
4193         mmiowb();
4194
4195         dev->trans_start = jiffies;
4196
4197         return NETDEV_TX_OK;
4198 }
4199
4200 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
4201                                int new_mtu)
4202 {
4203         dev->mtu = new_mtu;
4204
4205         if (new_mtu > ETH_DATA_LEN) {
4206                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
4207                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
4208                         ethtool_op_set_tso(dev, 0);
4209                 }
4210                 else
4211                         tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
4212         } else {
4213                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
4214                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
4215                 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
4216         }
4217 }
4218
4219 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
4220 {
4221         struct tg3 *tp = netdev_priv(dev);
4222         int err;
4223
4224         if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
4225                 return -EINVAL;
4226
4227         if (!netif_running(dev)) {
4228                 /* We'll just catch it later when the
4229                  * device is up'd.
4230                  */
4231                 tg3_set_mtu(dev, tp, new_mtu);
4232                 return 0;
4233         }
4234
4235         tg3_netif_stop(tp);
4236
4237         tg3_full_lock(tp, 1);
4238
4239         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
4240
4241         tg3_set_mtu(dev, tp, new_mtu);
4242
4243         err = tg3_restart_hw(tp, 0);
4244
4245         if (!err)
4246                 tg3_netif_start(tp);
4247
4248         tg3_full_unlock(tp);
4249
4250         return err;
4251 }
4252
4253 /* Free up pending packets in all rx/tx rings.
4254  *
4255  * The chip has been shut down and the driver detached from
4256  * the networking, so no interrupts or new tx packets will
4257  * end up in the driver.  tp->{tx,}lock is not held and we are not
4258  * in an interrupt context and thus may sleep.
4259  */
4260 static void tg3_free_rings(struct tg3 *tp)
4261 {
4262         struct ring_info *rxp;
4263         int i;
4264
4265         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
4266                 rxp = &tp->rx_std_buffers[i];
4267
4268                 if (rxp->skb == NULL)
4269                         continue;
4270                 pci_unmap_single(tp->pdev,
4271                                  pci_unmap_addr(rxp, mapping),
4272                                  tp->rx_pkt_buf_sz - tp->rx_offset,
4273                                  PCI_DMA_FROMDEVICE);
4274                 dev_kfree_skb_any(rxp->skb);
4275                 rxp->skb = NULL;
4276         }
4277
4278         for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
4279                 rxp = &tp->rx_jumbo_buffers[i];
4280
4281                 if (rxp->skb == NULL)
4282                         continue;
4283                 pci_unmap_single(tp->pdev,
4284                                  pci_unmap_addr(rxp, mapping),
4285                                  RX_JUMBO_PKT_BUF_SZ - tp->rx_offset,
4286                                  PCI_DMA_FROMDEVICE);
4287                 dev_kfree_skb_any(rxp->skb);
4288                 rxp->skb = NULL;
4289         }
4290
4291         for (i = 0; i < TG3_TX_RING_SIZE; ) {
4292                 struct tx_ring_info *txp;
4293                 struct sk_buff *skb;
4294                 int j;
4295
4296                 txp = &tp->tx_buffers[i];
4297                 skb = txp->skb;
4298
4299                 if (skb == NULL) {
4300                         i++;
4301                         continue;
4302                 }
4303
4304                 pci_unmap_single(tp->pdev,
4305                                  pci_unmap_addr(txp, mapping),
4306                                  skb_headlen(skb),
4307                                  PCI_DMA_TODEVICE);
4308                 txp->skb = NULL;
4309
4310                 i++;
4311
4312                 for (j = 0; j < skb_shinfo(skb)->nr_frags; j++) {
4313                         txp = &tp->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
4314                         pci_unmap_page(tp->pdev,
4315                                        pci_unmap_addr(txp, mapping),
4316                                        skb_shinfo(skb)->frags[j].size,
4317                                        PCI_DMA_TODEVICE);
4318                         i++;
4319                 }
4320
4321                 dev_kfree_skb_any(skb);
4322         }
4323 }
4324
4325 /* Initialize tx/rx rings for packet processing.
4326  *
4327  * The chip has been shut down and the driver detached from
4328  * the networking, so no interrupts or new tx packets will
4329  * end up in the driver.  tp->{tx,}lock are held and thus
4330  * we may not sleep.
4331  */
4332 static int tg3_init_rings(struct tg3 *tp)
4333 {
4334         u32 i;
4335
4336         /* Free up all the SKBs. */
4337         tg3_free_rings(tp);
4338
4339         /* Zero out all descriptors. */
4340         memset(tp->rx_std, 0, TG3_RX_RING_BYTES);
4341         memset(tp->rx_jumbo, 0, TG3_RX_JUMBO_RING_BYTES);
4342         memset(tp->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
4343         memset(tp->tx_ring, 0, TG3_TX_RING_BYTES);
4344
4345         tp->rx_pkt_buf_sz = RX_PKT_BUF_SZ;
4346         if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
4347             (tp->dev->mtu > ETH_DATA_LEN))
4348                 tp->rx_pkt_buf_sz = RX_JUMBO_PKT_BUF_SZ;
4349
4350         /* Initialize invariants of the rings, we only set this
4351          * stuff once.  This works because the card does not
4352          * write into the rx buffer posting rings.
4353          */
4354         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
4355                 struct tg3_rx_buffer_desc *rxd;
4356
4357                 rxd = &tp->rx_std[i];
4358                 rxd->idx_len = (tp->rx_pkt_buf_sz - tp->rx_offset - 64)
4359                         << RXD_LEN_SHIFT;
4360                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
4361                 rxd->opaque = (RXD_OPAQUE_RING_STD |
4362                                (i << RXD_OPAQUE_INDEX_SHIFT));
4363         }
4364
4365         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
4366                 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
4367                         struct tg3_rx_buffer_desc *rxd;
4368
4369                         rxd = &tp->rx_jumbo[i];
4370                         rxd->idx_len = (RX_JUMBO_PKT_BUF_SZ - tp->rx_offset - 64)
4371                                 << RXD_LEN_SHIFT;
4372                         rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
4373                                 RXD_FLAG_JUMBO;
4374                         rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
4375                                (i << RXD_OPAQUE_INDEX_SHIFT));
4376                 }
4377         }
4378
4379         /* Now allocate fresh SKBs for each rx ring. */
4380         for (i = 0; i < tp->rx_pending; i++) {
4381                 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_STD, -1, i) < 0) {
4382                         printk(KERN_WARNING PFX
4383                                "%s: Using a smaller RX standard ring, "
4384                                "only %d out of %d buffers were allocated "
4385                                "successfully.\n",
4386                                tp->dev->name, i, tp->rx_pending);
4387                         if (i == 0)
4388                                 return -ENOMEM;
4389                         tp->rx_pending = i;
4390                         break;
4391                 }
4392         }
4393
4394         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
4395                 for (i = 0; i < tp->rx_jumbo_pending; i++) {
4396                         if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_JUMBO,
4397                                              -1, i) < 0) {
4398                                 printk(KERN_WARNING PFX
4399                                        "%s: Using a smaller RX jumbo ring, "
4400                                        "only %d out of %d buffers were "
4401                                        "allocated successfully.\n",
4402                                        tp->dev->name, i, tp->rx_jumbo_pending);
4403                                 if (i == 0) {
4404                                         tg3_free_rings(tp);
4405                                         return -ENOMEM;
4406                                 }
4407                                 tp->rx_jumbo_pending = i;
4408                                 break;
4409                         }
4410                 }
4411         }
4412         return 0;
4413 }
4414
4415 /*
4416  * Must not be invoked with interrupt sources disabled and
4417  * the hardware shutdown down.
4418  */
4419 static void tg3_free_consistent(struct tg3 *tp)
4420 {
4421         kfree(tp->rx_std_buffers);
4422         tp->rx_std_buffers = NULL;
4423         if (tp->rx_std) {
4424                 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
4425                                     tp->rx_std, tp->rx_std_mapping);
4426                 tp->rx_std = NULL;
4427         }
4428         if (tp->rx_jumbo) {
4429                 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
4430                                     tp->rx_jumbo, tp->rx_jumbo_mapping);
4431                 tp->rx_jumbo = NULL;
4432         }
4433         if (tp->rx_rcb) {
4434                 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
4435                                     tp->rx_rcb, tp->rx_rcb_mapping);
4436                 tp->rx_rcb = NULL;
4437         }
4438         if (tp->tx_ring) {
4439                 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
4440                         tp->tx_ring, tp->tx_desc_mapping);
4441                 tp->tx_ring = NULL;
4442         }
4443         if (tp->hw_status) {
4444                 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
4445                                     tp->hw_status, tp->status_mapping);
4446                 tp->hw_status = NULL;
4447         }
4448         if (tp->hw_stats) {
4449                 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
4450                                     tp->hw_stats, tp->stats_mapping);
4451                 tp->hw_stats = NULL;
4452         }
4453 }
4454
4455 /*
4456  * Must not be invoked with interrupt sources disabled and
4457  * the hardware shutdown down.  Can sleep.
4458  */
4459 static int tg3_alloc_consistent(struct tg3 *tp)
4460 {
4461         tp->rx_std_buffers = kzalloc((sizeof(struct ring_info) *
4462                                       (TG3_RX_RING_SIZE +
4463                                        TG3_RX_JUMBO_RING_SIZE)) +
4464                                      (sizeof(struct tx_ring_info) *
4465                                       TG3_TX_RING_SIZE),
4466                                      GFP_KERNEL);
4467         if (!tp->rx_std_buffers)
4468                 return -ENOMEM;
4469
4470         tp->rx_jumbo_buffers = &tp->rx_std_buffers[TG3_RX_RING_SIZE];
4471         tp->tx_buffers = (struct tx_ring_info *)
4472                 &tp->rx_jumbo_buffers[TG3_RX_JUMBO_RING_SIZE];
4473
4474         tp->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
4475                                           &tp->rx_std_mapping);
4476         if (!tp->rx_std)
4477                 goto err_out;
4478
4479         tp->rx_jumbo = pci_alloc_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
4480                                             &tp->rx_jumbo_mapping);
4481
4482         if (!tp->rx_jumbo)
4483                 goto err_out;
4484
4485         tp->rx_rcb = pci_alloc_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
4486                                           &tp->rx_rcb_mapping);
4487         if (!tp->rx_rcb)
4488                 goto err_out;
4489
4490         tp->tx_ring = pci_alloc_consistent(tp->pdev, TG3_TX_RING_BYTES,
4491                                            &tp->tx_desc_mapping);
4492         if (!tp->tx_ring)
4493                 goto err_out;
4494
4495         tp->hw_status = pci_alloc_consistent(tp->pdev,
4496                                              TG3_HW_STATUS_SIZE,
4497                                              &tp->status_mapping);
4498         if (!tp->hw_status)
4499                 goto err_out;
4500
4501         tp->hw_stats = pci_alloc_consistent(tp->pdev,
4502                                             sizeof(struct tg3_hw_stats),
4503                                             &tp->stats_mapping);
4504         if (!tp->hw_stats)
4505                 goto err_out;
4506
4507         memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
4508         memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
4509
4510         return 0;
4511
4512 err_out:
4513         tg3_free_consistent(tp);
4514         return -ENOMEM;
4515 }
4516
4517 #define MAX_WAIT_CNT 1000
4518
4519 /* To stop a block, clear the enable bit and poll till it
4520  * clears.  tp->lock is held.
4521  */
4522 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
4523 {
4524         unsigned int i;
4525         u32 val;
4526
4527         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
4528                 switch (ofs) {
4529                 case RCVLSC_MODE:
4530                 case DMAC_MODE:
4531                 case MBFREE_MODE:
4532                 case BUFMGR_MODE:
4533                 case MEMARB_MODE:
4534                         /* We can't enable/disable these bits of the
4535                          * 5705/5750, just say success.
4536                          */
4537                         return 0;
4538
4539                 default:
4540                         break;
4541                 };
4542         }
4543
4544         val = tr32(ofs);
4545         val &= ~enable_bit;
4546         tw32_f(ofs, val);
4547
4548         for (i = 0; i < MAX_WAIT_CNT; i++) {
4549                 udelay(100);
4550                 val = tr32(ofs);
4551                 if ((val & enable_bit) == 0)
4552                         break;
4553         }
4554
4555         if (i == MAX_WAIT_CNT && !silent) {
4556                 printk(KERN_ERR PFX "tg3_stop_block timed out, "
4557                        "ofs=%lx enable_bit=%x\n",
4558                        ofs, enable_bit);
4559                 return -ENODEV;
4560         }
4561
4562         return 0;
4563 }
4564
4565 /* tp->lock is held. */
4566 static int tg3_abort_hw(struct tg3 *tp, int silent)
4567 {
4568         int i, err;
4569
4570         tg3_disable_ints(tp);
4571
4572         tp->rx_mode &= ~RX_MODE_ENABLE;
4573         tw32_f(MAC_RX_MODE, tp->rx_mode);
4574         udelay(10);
4575
4576         err  = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
4577         err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
4578         err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
4579         err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
4580         err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
4581         err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
4582
4583         err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
4584         err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
4585         err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
4586         err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
4587         err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
4588         err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
4589         err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
4590
4591         tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
4592         tw32_f(MAC_MODE, tp->mac_mode);
4593         udelay(40);
4594
4595         tp->tx_mode &= ~TX_MODE_ENABLE;
4596         tw32_f(MAC_TX_MODE, tp->tx_mode);
4597
4598         for (i = 0; i < MAX_WAIT_CNT; i++) {
4599                 udelay(100);
4600                 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
4601                         break;
4602         }
4603         if (i >= MAX_WAIT_CNT) {
4604                 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
4605                        "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
4606                        tp->dev->name, tr32(MAC_TX_MODE));
4607                 err |= -ENODEV;
4608         }
4609
4610         err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
4611         err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
4612         err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
4613
4614         tw32(FTQ_RESET, 0xffffffff);
4615         tw32(FTQ_RESET, 0x00000000);
4616
4617         err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
4618         err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
4619
4620         if (tp->hw_status)
4621                 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
4622         if (tp->hw_stats)
4623                 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
4624
4625         return err;
4626 }
4627
4628 /* tp->lock is held. */
4629 static int tg3_nvram_lock(struct tg3 *tp)
4630 {
4631         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
4632                 int i;
4633
4634                 if (tp->nvram_lock_cnt == 0) {
4635                         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
4636                         for (i = 0; i < 8000; i++) {
4637                                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
4638                                         break;
4639                                 udelay(20);
4640                         }
4641                         if (i == 8000) {
4642                                 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
4643                                 return -ENODEV;
4644                         }
4645                 }
4646                 tp->nvram_lock_cnt++;
4647         }
4648         return 0;
4649 }
4650
4651 /* tp->lock is held. */
4652 static void tg3_nvram_unlock(struct tg3 *tp)
4653 {
4654         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
4655                 if (tp->nvram_lock_cnt > 0)
4656                         tp->nvram_lock_cnt--;
4657                 if (tp->nvram_lock_cnt == 0)
4658                         tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
4659         }
4660 }
4661
4662 /* tp->lock is held. */
4663 static void tg3_enable_nvram_access(struct tg3 *tp)
4664 {
4665         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
4666             !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
4667                 u32 nvaccess = tr32(NVRAM_ACCESS);
4668
4669                 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
4670         }
4671 }
4672
4673 /* tp->lock is held. */
4674 static void tg3_disable_nvram_access(struct tg3 *tp)
4675 {
4676         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
4677             !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
4678                 u32 nvaccess = tr32(NVRAM_ACCESS);
4679
4680                 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
4681         }
4682 }
4683
4684 /* tp->lock is held. */
4685 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
4686 {
4687         tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
4688                       NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
4689
4690         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
4691                 switch (kind) {
4692                 case RESET_KIND_INIT:
4693                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4694                                       DRV_STATE_START);
4695                         break;
4696
4697                 case RESET_KIND_SHUTDOWN:
4698                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4699                                       DRV_STATE_UNLOAD);
4700                         break;
4701
4702                 case RESET_KIND_SUSPEND:
4703                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4704                                       DRV_STATE_SUSPEND);
4705                         break;
4706
4707                 default:
4708                         break;
4709                 };
4710         }
4711 }
4712
4713 /* tp->lock is held. */
4714 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
4715 {
4716         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
4717                 switch (kind) {
4718                 case RESET_KIND_INIT:
4719                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4720                                       DRV_STATE_START_DONE);
4721                         break;
4722
4723                 case RESET_KIND_SHUTDOWN:
4724                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4725                                       DRV_STATE_UNLOAD_DONE);
4726                         break;
4727
4728                 default:
4729                         break;
4730                 };
4731         }
4732 }
4733
4734 /* tp->lock is held. */
4735 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
4736 {
4737         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
4738                 switch (kind) {
4739                 case RESET_KIND_INIT:
4740                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4741                                       DRV_STATE_START);
4742                         break;
4743
4744                 case RESET_KIND_SHUTDOWN:
4745                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4746                                       DRV_STATE_UNLOAD);
4747                         break;
4748
4749                 case RESET_KIND_SUSPEND:
4750                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4751                                       DRV_STATE_SUSPEND);
4752                         break;
4753
4754                 default:
4755                         break;
4756                 };
4757         }
4758 }
4759
4760 static int tg3_poll_fw(struct tg3 *tp)
4761 {
4762         int i;
4763         u32 val;
4764
4765         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
4766                 /* Wait up to 20ms for init done. */
4767                 for (i = 0; i < 200; i++) {
4768                         if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
4769                                 return 0;
4770                         udelay(100);
4771                 }
4772                 return -ENODEV;
4773         }
4774
4775         /* Wait for firmware initialization to complete. */
4776         for (i = 0; i < 100000; i++) {
4777                 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
4778                 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
4779                         break;
4780                 udelay(10);
4781         }
4782
4783         /* Chip might not be fitted with firmware.  Some Sun onboard
4784          * parts are configured like that.  So don't signal the timeout
4785          * of the above loop as an error, but do report the lack of
4786          * running firmware once.
4787          */
4788         if (i >= 100000 &&
4789             !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
4790                 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
4791
4792                 printk(KERN_INFO PFX "%s: No firmware running.\n",
4793                        tp->dev->name);
4794         }
4795
4796         return 0;
4797 }
4798
4799 static void tg3_stop_fw(struct tg3 *);
4800
4801 /* tp->lock is held. */
4802 static int tg3_chip_reset(struct tg3 *tp)
4803 {
4804         u32 val;
4805         void (*write_op)(struct tg3 *, u32, u32);
4806         int err;
4807
4808         tg3_nvram_lock(tp);
4809
4810         /* No matching tg3_nvram_unlock() after this because
4811          * chip reset below will undo the nvram lock.
4812          */
4813         tp->nvram_lock_cnt = 0;
4814
4815         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
4816             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
4817             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
4818                 tw32(GRC_FASTBOOT_PC, 0);
4819
4820         /*
4821          * We must avoid the readl() that normally takes place.
4822          * It locks machines, causes machine checks, and other
4823          * fun things.  So, temporarily disable the 5701
4824          * hardware workaround, while we do the reset.
4825          */
4826         write_op = tp->write32;
4827         if (write_op == tg3_write_flush_reg32)
4828                 tp->write32 = tg3_write32;
4829
4830         /* Prevent the irq handler from reading or writing PCI registers
4831          * during chip reset when the memory enable bit in the PCI command
4832          * register may be cleared.  The chip does not generate interrupt
4833          * at this time, but the irq handler may still be called due to irq
4834          * sharing or irqpoll.
4835          */
4836         tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
4837         if (tp->hw_status) {
4838                 tp->hw_status->status = 0;
4839                 tp->hw_status->status_tag = 0;
4840         }
4841         tp->last_tag = 0;
4842         smp_mb();
4843         synchronize_irq(tp->pdev->irq);
4844
4845         /* do the reset */
4846         val = GRC_MISC_CFG_CORECLK_RESET;
4847
4848         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
4849                 if (tr32(0x7e2c) == 0x60) {
4850                         tw32(0x7e2c, 0x20);
4851                 }
4852                 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
4853                         tw32(GRC_MISC_CFG, (1 << 29));
4854                         val |= (1 << 29);
4855                 }
4856         }
4857
4858         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
4859                 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
4860                 tw32(GRC_VCPU_EXT_CTRL,
4861                      tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
4862         }
4863
4864         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
4865                 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
4866         tw32(GRC_MISC_CFG, val);
4867
4868         /* restore 5701 hardware bug workaround write method */
4869         tp->write32 = write_op;
4870
4871         /* Unfortunately, we have to delay before the PCI read back.
4872          * Some 575X chips even will not respond to a PCI cfg access
4873          * when the reset command is given to the chip.
4874          *
4875          * How do these hardware designers expect things to work
4876          * properly if the PCI write is posted for a long period
4877          * of time?  It is always necessary to have some method by
4878          * which a register read back can occur to push the write
4879          * out which does the reset.
4880          *
4881          * For most tg3 variants the trick below was working.
4882          * Ho hum...
4883          */
4884         udelay(120);
4885
4886         /* Flush PCI posted writes.  The normal MMIO registers
4887          * are inaccessible at this time so this is the only
4888          * way to make this reliably (actually, this is no longer
4889          * the case, see above).  I tried to use indirect
4890          * register read/write but this upset some 5701 variants.
4891          */
4892         pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
4893
4894         udelay(120);
4895
4896         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
4897                 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
4898                         int i;
4899                         u32 cfg_val;
4900
4901                         /* Wait for link training to complete.  */
4902                         for (i = 0; i < 5000; i++)
4903                                 udelay(100);
4904
4905                         pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
4906                         pci_write_config_dword(tp->pdev, 0xc4,
4907                                                cfg_val | (1 << 15));
4908                 }
4909                 /* Set PCIE max payload size and clear error status.  */
4910                 pci_write_config_dword(tp->pdev, 0xd8, 0xf5000);
4911         }
4912
4913         /* Re-enable indirect register accesses. */
4914         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
4915                                tp->misc_host_ctrl);
4916
4917         /* Set MAX PCI retry to zero. */
4918         val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
4919         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
4920             (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
4921                 val |= PCISTATE_RETRY_SAME_DMA;
4922         pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
4923
4924         pci_restore_state(tp->pdev);
4925
4926         tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
4927
4928         /* Make sure PCI-X relaxed ordering bit is clear. */
4929         pci_read_config_dword(tp->pdev, TG3PCI_X_CAPS, &val);
4930         val &= ~PCIX_CAPS_RELAXED_ORDERING;
4931         pci_write_config_dword(tp->pdev, TG3PCI_X_CAPS, val);
4932
4933         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
4934                 u32 val;
4935
4936                 /* Chip reset on 5780 will reset MSI enable bit,
4937                  * so need to restore it.
4938                  */
4939                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
4940                         u16 ctrl;
4941
4942                         pci_read_config_word(tp->pdev,
4943                                              tp->msi_cap + PCI_MSI_FLAGS,
4944                                              &ctrl);
4945                         pci_write_config_word(tp->pdev,
4946                                               tp->msi_cap + PCI_MSI_FLAGS,
4947                                               ctrl | PCI_MSI_FLAGS_ENABLE);
4948                         val = tr32(MSGINT_MODE);
4949                         tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
4950                 }
4951
4952                 val = tr32(MEMARB_MODE);
4953                 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
4954
4955         } else
4956                 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
4957
4958         if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
4959                 tg3_stop_fw(tp);
4960                 tw32(0x5000, 0x400);
4961         }
4962
4963         tw32(GRC_MODE, tp->grc_mode);
4964
4965         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
4966                 u32 val = tr32(0xc4);
4967
4968                 tw32(0xc4, val | (1 << 15));
4969         }
4970
4971         if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
4972             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
4973                 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
4974                 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
4975                         tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
4976                 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
4977         }
4978
4979         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4980                 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
4981                 tw32_f(MAC_MODE, tp->mac_mode);
4982         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
4983                 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
4984                 tw32_f(MAC_MODE, tp->mac_mode);
4985         } else
4986                 tw32_f(MAC_MODE, 0);
4987         udelay(40);
4988
4989         err = tg3_poll_fw(tp);
4990         if (err)
4991                 return err;
4992
4993         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
4994             tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
4995                 u32 val = tr32(0x7c00);
4996
4997                 tw32(0x7c00, val | (1 << 25));
4998         }
4999
5000         /* Reprobe ASF enable state.  */
5001         tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
5002         tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
5003         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
5004         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
5005                 u32 nic_cfg;
5006
5007                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
5008                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
5009                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
5010                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
5011                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
5012                 }
5013         }
5014
5015         return 0;
5016 }
5017
5018 /* tp->lock is held. */
5019 static void tg3_stop_fw(struct tg3 *tp)
5020 {
5021         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
5022                 u32 val;
5023                 int i;
5024
5025                 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
5026                 val = tr32(GRC_RX_CPU_EVENT);
5027                 val |= (1 << 14);
5028                 tw32(GRC_RX_CPU_EVENT, val);
5029
5030                 /* Wait for RX cpu to ACK the event.  */
5031                 for (i = 0; i < 100; i++) {
5032                         if (!(tr32(GRC_RX_CPU_EVENT) & (1 << 14)))
5033                                 break;
5034                         udelay(1);
5035                 }
5036         }
5037 }
5038
5039 /* tp->lock is held. */
5040 static int tg3_halt(struct tg3 *tp, int kind, int silent)
5041 {
5042         int err;
5043
5044         tg3_stop_fw(tp);
5045
5046         tg3_write_sig_pre_reset(tp, kind);
5047
5048         tg3_abort_hw(tp, silent);
5049         err = tg3_chip_reset(tp);
5050
5051         tg3_write_sig_legacy(tp, kind);
5052         tg3_write_sig_post_reset(tp, kind);
5053
5054         if (err)
5055                 return err;
5056
5057         return 0;
5058 }
5059
5060 #define TG3_FW_RELEASE_MAJOR    0x0
5061 #define TG3_FW_RELASE_MINOR     0x0
5062 #define TG3_FW_RELEASE_FIX      0x0
5063 #define TG3_FW_START_ADDR       0x08000000
5064 #define TG3_FW_TEXT_ADDR        0x08000000
5065 #define TG3_FW_TEXT_LEN         0x9c0
5066 #define TG3_FW_RODATA_ADDR      0x080009c0
5067 #define TG3_FW_RODATA_LEN       0x60
5068 #define TG3_FW_DATA_ADDR        0x08000a40
5069 #define TG3_FW_DATA_LEN         0x20
5070 #define TG3_FW_SBSS_ADDR        0x08000a60
5071 #define TG3_FW_SBSS_LEN         0xc
5072 #define TG3_FW_BSS_ADDR         0x08000a70
5073 #define TG3_FW_BSS_LEN          0x10
5074
5075 static const u32 tg3FwText[(TG3_FW_TEXT_LEN / sizeof(u32)) + 1] = {
5076         0x00000000, 0x10000003, 0x00000000, 0x0000000d, 0x0000000d, 0x3c1d0800,
5077         0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100000, 0x0e000018, 0x00000000,
5078         0x0000000d, 0x3c1d0800, 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100034,
5079         0x0e00021c, 0x00000000, 0x0000000d, 0x00000000, 0x00000000, 0x00000000,
5080         0x27bdffe0, 0x3c1cc000, 0xafbf0018, 0xaf80680c, 0x0e00004c, 0x241b2105,
5081         0x97850000, 0x97870002, 0x9782002c, 0x9783002e, 0x3c040800, 0x248409c0,
5082         0xafa00014, 0x00021400, 0x00621825, 0x00052c00, 0xafa30010, 0x8f860010,
5083         0x00e52825, 0x0e000060, 0x24070102, 0x3c02ac00, 0x34420100, 0x3c03ac01,
5084         0x34630100, 0xaf820490, 0x3c02ffff, 0xaf820494, 0xaf830498, 0xaf82049c,
5085         0x24020001, 0xaf825ce0, 0x0e00003f, 0xaf825d00, 0x0e000140, 0x00000000,
5086         0x8fbf0018, 0x03e00008, 0x27bd0020, 0x2402ffff, 0xaf825404, 0x8f835400,
5087         0x34630400, 0xaf835400, 0xaf825404, 0x3c020800, 0x24420034, 0xaf82541c,
5088         0x03e00008, 0xaf805400, 0x00000000, 0x00000000, 0x3c020800, 0x34423000,
5089         0x3c030800, 0x34633000, 0x3c040800, 0x348437ff, 0x3c010800, 0xac220a64,
5090         0x24020040, 0x3c010800, 0xac220a68, 0x3c010800, 0xac200a60, 0xac600000,
5091         0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
5092         0x00804821, 0x8faa0010, 0x3c020800, 0x8c420a60, 0x3c040800, 0x8c840a68,
5093         0x8fab0014, 0x24430001, 0x0044102b, 0x3c010800, 0xac230a60, 0x14400003,
5094         0x00004021, 0x3c010800, 0xac200a60, 0x3c020800, 0x8c420a60, 0x3c030800,
5095         0x8c630a64, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
5096         0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020800, 0x8c420a60,
5097         0x3c030800, 0x8c630a64, 0x8f84680c, 0x00021140, 0x00431021, 0xac440008,
5098         0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
5099         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5100         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5101         0, 0, 0, 0, 0, 0,
5102         0x02000008, 0x00000000, 0x0a0001e3, 0x3c0a0001, 0x0a0001e3, 0x3c0a0002,
5103         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5104         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5105         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5106         0x0a0001e3, 0x3c0a0007, 0x0a0001e3, 0x3c0a0008, 0x0a0001e3, 0x3c0a0009,
5107         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000b,
5108         0x0a0001e3, 0x3c0a000c, 0x0a0001e3, 0x3c0a000d, 0x0a0001e3, 0x00000000,
5109         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000e, 0x0a0001e3, 0x00000000,
5110         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5111         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5112         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a0013, 0x0a0001e3, 0x3c0a0014,
5113         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5114         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5115         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5116         0x27bdffe0, 0x00001821, 0x00001021, 0xafbf0018, 0xafb10014, 0xafb00010,
5117         0x3c010800, 0x00220821, 0xac200a70, 0x3c010800, 0x00220821, 0xac200a74,
5118         0x3c010800, 0x00220821, 0xac200a78, 0x24630001, 0x1860fff5, 0x2442000c,
5119         0x24110001, 0x8f906810, 0x32020004, 0x14400005, 0x24040001, 0x3c020800,
5120         0x8c420a78, 0x18400003, 0x00002021, 0x0e000182, 0x00000000, 0x32020001,
5121         0x10400003, 0x00000000, 0x0e000169, 0x00000000, 0x0a000153, 0xaf915028,
5122         0x8fbf0018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020, 0x3c050800,
5123         0x8ca50a70, 0x3c060800, 0x8cc60a80, 0x3c070800, 0x8ce70a78, 0x27bdffe0,
5124         0x3c040800, 0x248409d0, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014,
5125         0x0e00017b, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x24020001,
5126         0x8f836810, 0x00821004, 0x00021027, 0x00621824, 0x03e00008, 0xaf836810,
5127         0x27bdffd8, 0xafbf0024, 0x1080002e, 0xafb00020, 0x8f825cec, 0xafa20018,
5128         0x8f825cec, 0x3c100800, 0x26100a78, 0xafa2001c, 0x34028000, 0xaf825cec,
5129         0x8e020000, 0x18400016, 0x00000000, 0x3c020800, 0x94420a74, 0x8fa3001c,
5130         0x000221c0, 0xac830004, 0x8fa2001c, 0x3c010800, 0x0e000201, 0xac220a74,
5131         0x10400005, 0x00000000, 0x8e020000, 0x24420001, 0x0a0001df, 0xae020000,
5132         0x3c020800, 0x8c420a70, 0x00021c02, 0x000321c0, 0x0a0001c5, 0xafa2001c,
5133         0x0e000201, 0x00000000, 0x1040001f, 0x00000000, 0x8e020000, 0x8fa3001c,
5134         0x24420001, 0x3c010800, 0xac230a70, 0x3c010800, 0xac230a74, 0x0a0001df,
5135         0xae020000, 0x3c100800, 0x26100a78, 0x8e020000, 0x18400028, 0x00000000,
5136         0x0e000201, 0x00000000, 0x14400024, 0x00000000, 0x8e020000, 0x3c030800,
5137         0x8c630a70, 0x2442ffff, 0xafa3001c, 0x18400006, 0xae020000, 0x00031402,
5138         0x000221c0, 0x8c820004, 0x3c010800, 0xac220a70, 0x97a2001e, 0x2442ff00,
5139         0x2c420300, 0x1440000b, 0x24024000, 0x3c040800, 0x248409dc, 0xafa00010,
5140         0xafa00014, 0x8fa6001c, 0x24050008, 0x0e000060, 0x00003821, 0x0a0001df,
5141         0x00000000, 0xaf825cf8, 0x3c020800, 0x8c420a40, 0x8fa3001c, 0x24420001,
5142         0xaf835cf8, 0x3c010800, 0xac220a40, 0x8fbf0024, 0x8fb00020, 0x03e00008,
5143         0x27bd0028, 0x27bdffe0, 0x3c040800, 0x248409e8, 0x00002821, 0x00003021,
5144         0x00003821, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x8fbf0018,
5145         0x03e00008, 0x27bd0020, 0x8f82680c, 0x8f85680c, 0x00021827, 0x0003182b,
5146         0x00031823, 0x00431024, 0x00441021, 0x00a2282b, 0x10a00006, 0x00000000,
5147         0x00401821, 0x8f82680c, 0x0043102b, 0x1440fffd, 0x00000000, 0x03e00008,
5148         0x00000000, 0x3c040800, 0x8c840000, 0x3c030800, 0x8c630a40, 0x0064102b,
5149         0x54400002, 0x00831023, 0x00641023, 0x2c420008, 0x03e00008, 0x38420001,
5150         0x27bdffe0, 0x00802821, 0x3c040800, 0x24840a00, 0x00003021, 0x00003821,
5151         0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x0a000216, 0x00000000,
5152         0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000, 0x27bdffe0, 0x3c1cc000,
5153         0xafbf0018, 0x0e00004c, 0xaf80680c, 0x3c040800, 0x24840a10, 0x03802821,
5154         0x00003021, 0x00003821, 0xafa00010, 0x0e000060, 0xafa00014, 0x2402ffff,
5155         0xaf825404, 0x3c0200aa, 0x0e000234, 0xaf825434, 0x8fbf0018, 0x03e00008,
5156         0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe8, 0xafb00010,
5157         0x24100001, 0xafbf0014, 0x3c01c003, 0xac200000, 0x8f826810, 0x30422000,
5158         0x10400003, 0x00000000, 0x0e000246, 0x00000000, 0x0a00023a, 0xaf905428,
5159         0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x27bdfff8, 0x8f845d0c,
5160         0x3c0200ff, 0x3c030800, 0x8c630a50, 0x3442fff8, 0x00821024, 0x1043001e,
5161         0x3c0500ff, 0x34a5fff8, 0x3c06c003, 0x3c074000, 0x00851824, 0x8c620010,
5162         0x3c010800, 0xac230a50, 0x30420008, 0x10400005, 0x00871025, 0x8cc20000,
5163         0x24420001, 0xacc20000, 0x00871025, 0xaf825d0c, 0x8fa20000, 0x24420001,
5164         0xafa20000, 0x8fa20000, 0x8fa20000, 0x24420001, 0xafa20000, 0x8fa20000,
5165         0x8f845d0c, 0x3c030800, 0x8c630a50, 0x00851024, 0x1443ffe8, 0x00851824,
5166         0x27bd0008, 0x03e00008, 0x00000000, 0x00000000, 0x00000000
5167 };
5168
5169 static const u32 tg3FwRodata[(TG3_FW_RODATA_LEN / sizeof(u32)) + 1] = {
5170         0x35373031, 0x726c7341, 0x00000000, 0x00000000, 0x53774576, 0x656e7430,
5171         0x00000000, 0x726c7045, 0x76656e74, 0x31000000, 0x556e6b6e, 0x45766e74,
5172         0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
5173         0x00000000, 0x00000000, 0x4d61696e, 0x43707542, 0x00000000, 0x00000000,
5174         0x00000000
5175 };
5176
5177 #if 0 /* All zeros, don't eat up space with it. */
5178 u32 tg3FwData[(TG3_FW_DATA_LEN / sizeof(u32)) + 1] = {
5179         0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5180         0x00000000, 0x00000000, 0x00000000, 0x00000000
5181 };
5182 #endif
5183
5184 #define RX_CPU_SCRATCH_BASE     0x30000
5185 #define RX_CPU_SCRATCH_SIZE     0x04000
5186 #define TX_CPU_SCRATCH_BASE     0x34000
5187 #define TX_CPU_SCRATCH_SIZE     0x04000
5188
5189 /* tp->lock is held. */
5190 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
5191 {
5192         int i;
5193
5194         BUG_ON(offset == TX_CPU_BASE &&
5195             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
5196
5197         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
5198                 u32 val = tr32(GRC_VCPU_EXT_CTRL);
5199
5200                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
5201                 return 0;
5202         }
5203         if (offset == RX_CPU_BASE) {
5204                 for (i = 0; i < 10000; i++) {
5205                         tw32(offset + CPU_STATE, 0xffffffff);
5206                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
5207                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
5208                                 break;
5209                 }
5210
5211                 tw32(offset + CPU_STATE, 0xffffffff);
5212                 tw32_f(offset + CPU_MODE,  CPU_MODE_HALT);
5213                 udelay(10);
5214         } else {
5215                 for (i = 0; i < 10000; i++) {
5216                         tw32(offset + CPU_STATE, 0xffffffff);
5217                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
5218                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
5219                                 break;
5220                 }
5221         }
5222
5223         if (i >= 10000) {
5224                 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
5225                        "and %s CPU\n",
5226                        tp->dev->name,
5227                        (offset == RX_CPU_BASE ? "RX" : "TX"));
5228                 return -ENODEV;
5229         }
5230
5231         /* Clear firmware's nvram arbitration. */
5232         if (tp->tg3_flags & TG3_FLAG_NVRAM)
5233                 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
5234         return 0;
5235 }
5236
5237 struct fw_info {
5238         unsigned int text_base;
5239         unsigned int text_len;
5240         const u32 *text_data;
5241         unsigned int rodata_base;
5242         unsigned int rodata_len;
5243         const u32 *rodata_data;
5244         unsigned int data_base;
5245         unsigned int data_len;
5246         const u32 *data_data;
5247 };
5248
5249 /* tp->lock is held. */
5250 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
5251                                  int cpu_scratch_size, struct fw_info *info)
5252 {
5253         int err, lock_err, i;
5254         void (*write_op)(struct tg3 *, u32, u32);
5255
5256         if (cpu_base == TX_CPU_BASE &&
5257             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5258                 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
5259                        "TX cpu firmware on %s which is 5705.\n",
5260                        tp->dev->name);
5261                 return -EINVAL;
5262         }
5263
5264         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
5265                 write_op = tg3_write_mem;
5266         else
5267                 write_op = tg3_write_indirect_reg32;
5268
5269         /* It is possible that bootcode is still loading at this point.
5270          * Get the nvram lock first before halting the cpu.
5271          */
5272         lock_err = tg3_nvram_lock(tp);
5273         err = tg3_halt_cpu(tp, cpu_base);
5274         if (!lock_err)
5275                 tg3_nvram_unlock(tp);
5276         if (err)
5277                 goto out;
5278
5279         for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
5280                 write_op(tp, cpu_scratch_base + i, 0);
5281         tw32(cpu_base + CPU_STATE, 0xffffffff);
5282         tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
5283         for (i = 0; i < (info->text_len / sizeof(u32)); i++)
5284                 write_op(tp, (cpu_scratch_base +
5285                               (info->text_base & 0xffff) +
5286                               (i * sizeof(u32))),
5287                          (info->text_data ?
5288                           info->text_data[i] : 0));
5289         for (i = 0; i < (info->rodata_len / sizeof(u32)); i++)
5290                 write_op(tp, (cpu_scratch_base +
5291                               (info->rodata_base & 0xffff) +
5292                               (i * sizeof(u32))),
5293                          (info->rodata_data ?
5294                           info->rodata_data[i] : 0));
5295         for (i = 0; i < (info->data_len / sizeof(u32)); i++)
5296                 write_op(tp, (cpu_scratch_base +
5297                               (info->data_base & 0xffff) +
5298                               (i * sizeof(u32))),
5299                          (info->data_data ?
5300                           info->data_data[i] : 0));
5301
5302         err = 0;
5303
5304 out:
5305         return err;
5306 }
5307
5308 /* tp->lock is held. */
5309 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
5310 {
5311         struct fw_info info;
5312         int err, i;
5313
5314         info.text_base = TG3_FW_TEXT_ADDR;
5315         info.text_len = TG3_FW_TEXT_LEN;
5316         info.text_data = &tg3FwText[0];
5317         info.rodata_base = TG3_FW_RODATA_ADDR;
5318         info.rodata_len = TG3_FW_RODATA_LEN;
5319         info.rodata_data = &tg3FwRodata[0];
5320         info.data_base = TG3_FW_DATA_ADDR;
5321         info.data_len = TG3_FW_DATA_LEN;
5322         info.data_data = NULL;
5323
5324         err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
5325                                     RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
5326                                     &info);
5327         if (err)
5328                 return err;
5329
5330         err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
5331                                     TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
5332                                     &info);
5333         if (err)
5334                 return err;
5335
5336         /* Now startup only the RX cpu. */
5337         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5338         tw32_f(RX_CPU_BASE + CPU_PC,    TG3_FW_TEXT_ADDR);
5339
5340         for (i = 0; i < 5; i++) {
5341                 if (tr32(RX_CPU_BASE + CPU_PC) == TG3_FW_TEXT_ADDR)
5342                         break;
5343                 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5344                 tw32(RX_CPU_BASE + CPU_MODE,  CPU_MODE_HALT);
5345                 tw32_f(RX_CPU_BASE + CPU_PC,    TG3_FW_TEXT_ADDR);
5346                 udelay(1000);
5347         }
5348         if (i >= 5) {
5349                 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
5350                        "to set RX CPU PC, is %08x should be %08x\n",
5351                        tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
5352                        TG3_FW_TEXT_ADDR);
5353                 return -ENODEV;
5354         }
5355         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5356         tw32_f(RX_CPU_BASE + CPU_MODE,  0x00000000);
5357
5358         return 0;
5359 }
5360
5361
5362 #define TG3_TSO_FW_RELEASE_MAJOR        0x1
5363 #define TG3_TSO_FW_RELASE_MINOR         0x6
5364 #define TG3_TSO_FW_RELEASE_FIX          0x0
5365 #define TG3_TSO_FW_START_ADDR           0x08000000
5366 #define TG3_TSO_FW_TEXT_ADDR            0x08000000
5367 #define TG3_TSO_FW_TEXT_LEN             0x1aa0
5368 #define TG3_TSO_FW_RODATA_ADDR          0x08001aa0
5369 #define TG3_TSO_FW_RODATA_LEN           0x60
5370 #define TG3_TSO_FW_DATA_ADDR            0x08001b20
5371 #define TG3_TSO_FW_DATA_LEN             0x30
5372 #define TG3_TSO_FW_SBSS_ADDR            0x08001b50
5373 #define TG3_TSO_FW_SBSS_LEN             0x2c
5374 #define TG3_TSO_FW_BSS_ADDR             0x08001b80
5375 #define TG3_TSO_FW_BSS_LEN              0x894
5376
5377 static const u32 tg3TsoFwText[(TG3_TSO_FW_TEXT_LEN / 4) + 1] = {
5378         0x0e000003, 0x00000000, 0x08001b24, 0x00000000, 0x10000003, 0x00000000,
5379         0x0000000d, 0x0000000d, 0x3c1d0800, 0x37bd4000, 0x03a0f021, 0x3c100800,
5380         0x26100000, 0x0e000010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
5381         0xafbf0018, 0x0e0005d8, 0x34840002, 0x0e000668, 0x00000000, 0x3c030800,
5382         0x90631b68, 0x24020002, 0x3c040800, 0x24841aac, 0x14620003, 0x24050001,
5383         0x3c040800, 0x24841aa0, 0x24060006, 0x00003821, 0xafa00010, 0x0e00067c,
5384         0xafa00014, 0x8f625c50, 0x34420001, 0xaf625c50, 0x8f625c90, 0x34420001,
5385         0xaf625c90, 0x2402ffff, 0x0e000034, 0xaf625404, 0x8fbf0018, 0x03e00008,
5386         0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c,
5387         0xafb20018, 0xafb10014, 0x0e00005b, 0xafb00010, 0x24120002, 0x24110001,
5388         0x8f706820, 0x32020100, 0x10400003, 0x00000000, 0x0e0000bb, 0x00000000,
5389         0x8f706820, 0x32022000, 0x10400004, 0x32020001, 0x0e0001f0, 0x24040001,
5390         0x32020001, 0x10400003, 0x00000000, 0x0e0000a3, 0x00000000, 0x3c020800,
5391         0x90421b98, 0x14520003, 0x00000000, 0x0e0004c0, 0x00000000, 0x0a00003c,
5392         0xaf715028, 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008,
5393         0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ac0, 0x00002821, 0x00003021,
5394         0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x3c040800,
5395         0x248423d8, 0xa4800000, 0x3c010800, 0xa0201b98, 0x3c010800, 0xac201b9c,
5396         0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
5397         0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bbc, 0x8f624434, 0x3c010800,
5398         0xac221b88, 0x8f624438, 0x3c010800, 0xac221b8c, 0x8f624410, 0xac80f7a8,
5399         0x3c010800, 0xac201b84, 0x3c010800, 0xac2023e0, 0x3c010800, 0xac2023c8,
5400         0x3c010800, 0xac2023cc, 0x3c010800, 0xac202400, 0x3c010800, 0xac221b90,
5401         0x8f620068, 0x24030007, 0x00021702, 0x10430005, 0x00000000, 0x8f620068,
5402         0x00021702, 0x14400004, 0x24020001, 0x3c010800, 0x0a000097, 0xac20240c,
5403         0xac820034, 0x3c040800, 0x24841acc, 0x3c050800, 0x8ca5240c, 0x00003021,
5404         0x00003821, 0xafa00010, 0x0e00067c, 0xafa00014, 0x8fbf0018, 0x03e00008,
5405         0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ad8, 0x00002821, 0x00003021,
5406         0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x0e00005b,
5407         0x00000000, 0x0e0000b4, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5408         0x24020001, 0x8f636820, 0x00821004, 0x00021027, 0x00621824, 0x03e00008,
5409         0xaf636820, 0x27bdffd0, 0xafbf002c, 0xafb60028, 0xafb50024, 0xafb40020,
5410         0xafb3001c, 0xafb20018, 0xafb10014, 0xafb00010, 0x8f675c5c, 0x3c030800,
5411         0x24631bbc, 0x8c620000, 0x14470005, 0x3c0200ff, 0x3c020800, 0x90421b98,
5412         0x14400119, 0x3c0200ff, 0x3442fff8, 0x00e28824, 0xac670000, 0x00111902,
5413         0x306300ff, 0x30e20003, 0x000211c0, 0x00622825, 0x00a04021, 0x00071602,
5414         0x3c030800, 0x90631b98, 0x3044000f, 0x14600036, 0x00804821, 0x24020001,
5415         0x3c010800, 0xa0221b98, 0x00051100, 0x00821025, 0x3c010800, 0xac201b9c,
5416         0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
5417         0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bb0, 0x3c010800, 0xac201bb4,
5418         0x3c010800, 0xa42223d8, 0x9622000c, 0x30437fff, 0x3c010800, 0xa4222410,
5419         0x30428000, 0x3c010800, 0xa4231bc6, 0x10400005, 0x24020001, 0x3c010800,
5420         0xac2223f4, 0x0a000102, 0x2406003e, 0x24060036, 0x3c010800, 0xac2023f4,
5421         0x9622000a, 0x3c030800, 0x94631bc6, 0x3c010800, 0xac2023f0, 0x3c010800,
5422         0xac2023f8, 0x00021302, 0x00021080, 0x00c21021, 0x00621821, 0x3c010800,
5423         0xa42223d0, 0x3c010800, 0x0a000115, 0xa4231b96, 0x9622000c, 0x3c010800,
5424         0xa42223ec, 0x3c040800, 0x24841b9c, 0x8c820000, 0x00021100, 0x3c010800,
5425         0x00220821, 0xac311bc8, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
5426         0xac271bcc, 0x8c820000, 0x25030001, 0x306601ff, 0x00021100, 0x3c010800,
5427         0x00220821, 0xac261bd0, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
5428         0xac291bd4, 0x96230008, 0x3c020800, 0x8c421bac, 0x00432821, 0x3c010800,
5429         0xac251bac, 0x9622000a, 0x30420004, 0x14400018, 0x00061100, 0x8f630c14,
5430         0x3063000f, 0x2c620002, 0x1440000b, 0x3c02c000, 0x8f630c14, 0x3c020800,
5431         0x8c421b40, 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002,
5432         0x1040fff7, 0x3c02c000, 0x00e21825, 0xaf635c5c, 0x8f625c50, 0x30420002,
5433         0x10400014, 0x00000000, 0x0a000147, 0x00000000, 0x3c030800, 0x8c631b80,
5434         0x3c040800, 0x94841b94, 0x01221025, 0x3c010800, 0xa42223da, 0x24020001,
5435         0x3c010800, 0xac221bb8, 0x24630001, 0x0085202a, 0x3c010800, 0x10800003,
5436         0xac231b80, 0x3c010800, 0xa4251b94, 0x3c060800, 0x24c61b9c, 0x8cc20000,
5437         0x24420001, 0xacc20000, 0x28420080, 0x14400005, 0x00000000, 0x0e000656,
5438         0x24040002, 0x0a0001e6, 0x00000000, 0x3c020800, 0x8c421bb8, 0x10400078,
5439         0x24020001, 0x3c050800, 0x90a51b98, 0x14a20072, 0x00000000, 0x3c150800,
5440         0x96b51b96, 0x3c040800, 0x8c841bac, 0x32a3ffff, 0x0083102a, 0x1440006c,
5441         0x00000000, 0x14830003, 0x00000000, 0x3c010800, 0xac2523f0, 0x1060005c,
5442         0x00009021, 0x24d60004, 0x0060a021, 0x24d30014, 0x8ec20000, 0x00028100,
5443         0x3c110800, 0x02308821, 0x0e000625, 0x8e311bc8, 0x00402821, 0x10a00054,
5444         0x00000000, 0x9628000a, 0x31020040, 0x10400005, 0x2407180c, 0x8e22000c,
5445         0x2407188c, 0x00021400, 0xaca20018, 0x3c030800, 0x00701821, 0x8c631bd0,
5446         0x3c020800, 0x00501021, 0x8c421bd4, 0x00031d00, 0x00021400, 0x00621825,
5447         0xaca30014, 0x8ec30004, 0x96220008, 0x00432023, 0x3242ffff, 0x3083ffff,
5448         0x00431021, 0x0282102a, 0x14400002, 0x02b23023, 0x00803021, 0x8e620000,
5449         0x30c4ffff, 0x00441021, 0xae620000, 0x8e220000, 0xaca20000, 0x8e220004,
5450         0x8e63fff4, 0x00431021, 0xaca20004, 0xa4a6000e, 0x8e62fff4, 0x00441021,
5451         0xae62fff4, 0x96230008, 0x0043102a, 0x14400005, 0x02469021, 0x8e62fff0,
5452         0xae60fff4, 0x24420001, 0xae62fff0, 0xaca00008, 0x3242ffff, 0x14540008,
5453         0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x24020905, 0xa4a2000c,
5454         0x0a0001cb, 0x34e70020, 0xa4a2000c, 0x3c020800, 0x8c4223f0, 0x10400003,
5455         0x3c024b65, 0x0a0001d3, 0x34427654, 0x3c02b49a, 0x344289ab, 0xaca2001c,
5456         0x30e2ffff, 0xaca20010, 0x0e0005a2, 0x00a02021, 0x3242ffff, 0x0054102b,
5457         0x1440ffa9, 0x00000000, 0x24020002, 0x3c010800, 0x0a0001e6, 0xa0221b98,
5458         0x8ec2083c, 0x24420001, 0x0a0001e6, 0xaec2083c, 0x0e0004c0, 0x00000000,
5459         0x8fbf002c, 0x8fb60028, 0x8fb50024, 0x8fb40020, 0x8fb3001c, 0x8fb20018,
5460         0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0030, 0x27bdffd0, 0xafbf0028,
5461         0xafb30024, 0xafb20020, 0xafb1001c, 0xafb00018, 0x8f725c9c, 0x3c0200ff,
5462         0x3442fff8, 0x3c070800, 0x24e71bb4, 0x02428824, 0x9623000e, 0x8ce20000,
5463         0x00431021, 0xace20000, 0x8e220010, 0x30420020, 0x14400011, 0x00809821,
5464         0x0e00063b, 0x02202021, 0x3c02c000, 0x02421825, 0xaf635c9c, 0x8f625c90,
5465         0x30420002, 0x1040011e, 0x00000000, 0xaf635c9c, 0x8f625c90, 0x30420002,
5466         0x10400119, 0x00000000, 0x0a00020d, 0x00000000, 0x8e240008, 0x8e230014,
5467         0x00041402, 0x000231c0, 0x00031502, 0x304201ff, 0x2442ffff, 0x3042007f,
5468         0x00031942, 0x30637800, 0x00021100, 0x24424000, 0x00624821, 0x9522000a,
5469         0x3084ffff, 0x30420008, 0x104000b0, 0x000429c0, 0x3c020800, 0x8c422400,
5470         0x14400024, 0x24c50008, 0x94c20014, 0x3c010800, 0xa42223d0, 0x8cc40010,
5471         0x00041402, 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42423d4, 0x94c2000e,
5472         0x3083ffff, 0x00431023, 0x3c010800, 0xac222408, 0x94c2001a, 0x3c010800,
5473         0xac262400, 0x3c010800, 0xac322404, 0x3c010800, 0xac2223fc, 0x3c02c000,
5474         0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e5, 0x00000000,
5475         0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e0, 0x00000000, 0x0a000246,
5476         0x00000000, 0x94c2000e, 0x3c030800, 0x946323d4, 0x00434023, 0x3103ffff,
5477         0x2c620008, 0x1040001c, 0x00000000, 0x94c20014, 0x24420028, 0x00a22821,
5478         0x00031042, 0x1840000b, 0x00002021, 0x24e60848, 0x00403821, 0x94a30000,
5479         0x8cc20000, 0x24840001, 0x00431021, 0xacc20000, 0x0087102a, 0x1440fff9,
5480         0x24a50002, 0x31020001, 0x1040001f, 0x3c024000, 0x3c040800, 0x248423fc,
5481         0xa0a00001, 0x94a30000, 0x8c820000, 0x00431021, 0x0a000285, 0xac820000,
5482         0x8f626800, 0x3c030010, 0x00431024, 0x10400009, 0x00000000, 0x94c2001a,
5483         0x3c030800, 0x8c6323fc, 0x00431021, 0x3c010800, 0xac2223fc, 0x0a000286,
5484         0x3c024000, 0x94c2001a, 0x94c4001c, 0x3c030800, 0x8c6323fc, 0x00441023,
5485         0x00621821, 0x3c010800, 0xac2323fc, 0x3c024000, 0x02421825, 0xaf635c9c,
5486         0x8f625c90, 0x30420002, 0x1440fffc, 0x00000000, 0x9522000a, 0x30420010,
5487         0x1040009b, 0x00000000, 0x3c030800, 0x946323d4, 0x3c070800, 0x24e72400,
5488         0x8ce40000, 0x8f626800, 0x24630030, 0x00832821, 0x3c030010, 0x00431024,
5489         0x1440000a, 0x00000000, 0x94a20004, 0x3c040800, 0x8c842408, 0x3c030800,
5490         0x8c6323fc, 0x00441023, 0x00621821, 0x3c010800, 0xac2323fc, 0x3c040800,
5491         0x8c8423fc, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402, 0x00822021,
5492         0x00041027, 0xa4a20006, 0x3c030800, 0x8c632404, 0x3c0200ff, 0x3442fff8,
5493         0x00628824, 0x96220008, 0x24050001, 0x24034000, 0x000231c0, 0x00801021,
5494         0xa4c2001a, 0xa4c0001c, 0xace00000, 0x3c010800, 0xac251b60, 0xaf635cb8,
5495         0x8f625cb0, 0x30420002, 0x10400003, 0x00000000, 0x3c010800, 0xac201b60,
5496         0x8e220008, 0xaf625cb8, 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000,
5497         0x3c010800, 0xac201b60, 0x3c020800, 0x8c421b60, 0x1040ffec, 0x00000000,
5498         0x3c040800, 0x0e00063b, 0x8c842404, 0x0a00032a, 0x00000000, 0x3c030800,
5499         0x90631b98, 0x24020002, 0x14620003, 0x3c034b65, 0x0a0002e1, 0x00008021,
5500         0x8e22001c, 0x34637654, 0x10430002, 0x24100002, 0x24100001, 0x00c02021,
5501         0x0e000350, 0x02003021, 0x24020003, 0x3c010800, 0xa0221b98, 0x24020002,
5502         0x1202000a, 0x24020001, 0x3c030800, 0x8c6323f0, 0x10620006, 0x00000000,
5503         0x3c020800, 0x944223d8, 0x00021400, 0x0a00031f, 0xae220014, 0x3c040800,
5504         0x248423da, 0x94820000, 0x00021400, 0xae220014, 0x3c020800, 0x8c421bbc,
5505         0x3c03c000, 0x3c010800, 0xa0201b98, 0x00431025, 0xaf625c5c, 0x8f625c50,
5506         0x30420002, 0x10400009, 0x00000000, 0x2484f7e2, 0x8c820000, 0x00431025,
5507         0xaf625c5c, 0x8f625c50, 0x30420002, 0x1440fffa, 0x00000000, 0x3c020800,
5508         0x24421b84, 0x8c430000, 0x24630001, 0xac430000, 0x8f630c14, 0x3063000f,
5509         0x2c620002, 0x1440000c, 0x3c024000, 0x8f630c14, 0x3c020800, 0x8c421b40,
5510         0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7,
5511         0x00000000, 0x3c024000, 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002,
5512         0x1440fffc, 0x00000000, 0x12600003, 0x00000000, 0x0e0004c0, 0x00000000,
5513         0x8fbf0028, 0x8fb30024, 0x8fb20020, 0x8fb1001c, 0x8fb00018, 0x03e00008,
5514         0x27bd0030, 0x8f634450, 0x3c040800, 0x24841b88, 0x8c820000, 0x00031c02,
5515         0x0043102b, 0x14400007, 0x3c038000, 0x8c840004, 0x8f624450, 0x00021c02,
5516         0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
5517         0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3c024000,
5518         0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00000000,
5519         0x03e00008, 0x00000000, 0x27bdffe0, 0x00805821, 0x14c00011, 0x256e0008,
5520         0x3c020800, 0x8c4223f4, 0x10400007, 0x24020016, 0x3c010800, 0xa42223d2,
5521         0x2402002a, 0x3c010800, 0x0a000364, 0xa42223d4, 0x8d670010, 0x00071402,
5522         0x3c010800, 0xa42223d2, 0x3c010800, 0xa42723d4, 0x3c040800, 0x948423d4,
5523         0x3c030800, 0x946323d2, 0x95cf0006, 0x3c020800, 0x944223d0, 0x00832023,
5524         0x01e2c023, 0x3065ffff, 0x24a20028, 0x01c24821, 0x3082ffff, 0x14c0001a,
5525         0x01226021, 0x9582000c, 0x3042003f, 0x3c010800, 0xa42223d6, 0x95820004,
5526         0x95830006, 0x3c010800, 0xac2023e4, 0x3c010800, 0xac2023e8, 0x00021400,
5527         0x00431025, 0x3c010800, 0xac221bc0, 0x95220004, 0x3c010800, 0xa4221bc4,
5528         0x95230002, 0x01e51023, 0x0043102a, 0x10400010, 0x24020001, 0x3c010800,
5529         0x0a000398, 0xac2223f8, 0x3c030800, 0x8c6323e8, 0x3c020800, 0x94421bc4,
5530         0x00431021, 0xa5220004, 0x3c020800, 0x94421bc0, 0xa5820004, 0x3c020800,
5531         0x8c421bc0, 0xa5820006, 0x3c020800, 0x8c4223f0, 0x3c0d0800, 0x8dad23e4,
5532         0x3c0a0800, 0x144000e5, 0x8d4a23e8, 0x3c020800, 0x94421bc4, 0x004a1821,
5533         0x3063ffff, 0x0062182b, 0x24020002, 0x10c2000d, 0x01435023, 0x3c020800,
5534         0x944223d6, 0x30420009, 0x10400008, 0x00000000, 0x9582000c, 0x3042fff6,
5535         0xa582000c, 0x3c020800, 0x944223d6, 0x30420009, 0x01a26823, 0x3c020800,
5536         0x8c4223f8, 0x1040004a, 0x01203821, 0x3c020800, 0x944223d2, 0x00004021,
5537         0xa520000a, 0x01e21023, 0xa5220002, 0x3082ffff, 0x00021042, 0x18400008,
5538         0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021, 0x0103102a,
5539         0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061402,
5540         0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021, 0x2527000c,
5541         0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004, 0x1440fffb,
5542         0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023, 0x01803821,
5543         0x3082ffff, 0xa4e00010, 0x00621821, 0x00021042, 0x18400010, 0x00c33021,
5544         0x00404821, 0x94e20000, 0x24e70002, 0x00c23021, 0x30e2007f, 0x14400006,
5545         0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80, 0x00625824, 0x25670008,
5546         0x0109102a, 0x1440fff3, 0x00000000, 0x30820001, 0x10400005, 0x00061c02,
5547         0xa0e00001, 0x94e20000, 0x00c23021, 0x00061c02, 0x30c2ffff, 0x00623021,
5548         0x00061402, 0x00c23021, 0x0a00047d, 0x30c6ffff, 0x24020002, 0x14c20081,
5549         0x00000000, 0x3c020800, 0x8c42240c, 0x14400007, 0x00000000, 0x3c020800,
5550         0x944223d2, 0x95230002, 0x01e21023, 0x10620077, 0x00000000, 0x3c020800,
5551         0x944223d2, 0x01e21023, 0xa5220002, 0x3c020800, 0x8c42240c, 0x1040001a,
5552         0x31e3ffff, 0x8dc70010, 0x3c020800, 0x94421b96, 0x00e04021, 0x00072c02,
5553         0x00aa2021, 0x00431023, 0x00823823, 0x00072402, 0x30e2ffff, 0x00823821,
5554         0x00071027, 0xa522000a, 0x3102ffff, 0x3c040800, 0x948423d4, 0x00453023,
5555         0x00e02821, 0x00641823, 0x006d1821, 0x00c33021, 0x00061c02, 0x30c2ffff,
5556         0x0a00047d, 0x00623021, 0x01203821, 0x00004021, 0x3082ffff, 0x00021042,
5557         0x18400008, 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021,
5558         0x0103102a, 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021,
5559         0x00061402, 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021,
5560         0x2527000c, 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004,
5561         0x1440fffb, 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023,
5562         0x01803821, 0x3082ffff, 0xa4e00010, 0x3c040800, 0x948423d4, 0x00621821,
5563         0x00c33021, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061c02, 0x3c020800,
5564         0x944223d0, 0x00c34821, 0x00441023, 0x00021fc2, 0x00431021, 0x00021043,
5565         0x18400010, 0x00003021, 0x00402021, 0x94e20000, 0x24e70002, 0x00c23021,
5566         0x30e2007f, 0x14400006, 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80,
5567         0x00625824, 0x25670008, 0x0104102a, 0x1440fff3, 0x00000000, 0x3c020800,
5568         0x944223ec, 0x00c23021, 0x3122ffff, 0x00c23021, 0x00061c02, 0x30c2ffff,
5569         0x00623021, 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010,
5570         0xadc00014, 0x0a00049d, 0xadc00000, 0x8dc70010, 0x00e04021, 0x11400007,
5571         0x00072c02, 0x00aa3021, 0x00061402, 0x30c3ffff, 0x00433021, 0x00061402,
5572         0x00c22821, 0x00051027, 0xa522000a, 0x3c030800, 0x946323d4, 0x3102ffff,
5573         0x01e21021, 0x00433023, 0x00cd3021, 0x00061c02, 0x30c2ffff, 0x00623021,
5574         0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010, 0x3102ffff,
5575         0x00051c00, 0x00431025, 0xadc20010, 0x3c020800, 0x8c4223f4, 0x10400005,
5576         0x2de205eb, 0x14400002, 0x25e2fff2, 0x34028870, 0xa5c20034, 0x3c030800,
5577         0x246323e8, 0x8c620000, 0x24420001, 0xac620000, 0x3c040800, 0x8c8423e4,
5578         0x3c020800, 0x8c421bc0, 0x3303ffff, 0x00832021, 0x00431821, 0x0062102b,
5579         0x3c010800, 0xac2423e4, 0x10400003, 0x2482ffff, 0x3c010800, 0xac2223e4,
5580         0x3c010800, 0xac231bc0, 0x03e00008, 0x27bd0020, 0x27bdffb8, 0x3c050800,
5581         0x24a51b96, 0xafbf0044, 0xafbe0040, 0xafb7003c, 0xafb60038, 0xafb50034,
5582         0xafb40030, 0xafb3002c, 0xafb20028, 0xafb10024, 0xafb00020, 0x94a90000,
5583         0x3c020800, 0x944223d0, 0x3c030800, 0x8c631bb0, 0x3c040800, 0x8c841bac,
5584         0x01221023, 0x0064182a, 0xa7a9001e, 0x106000be, 0xa7a20016, 0x24be0022,
5585         0x97b6001e, 0x24b3001a, 0x24b70016, 0x8fc20000, 0x14400008, 0x00000000,
5586         0x8fc2fff8, 0x97a30016, 0x8fc4fff4, 0x00431021, 0x0082202a, 0x148000b0,
5587         0x00000000, 0x97d50818, 0x32a2ffff, 0x104000a3, 0x00009021, 0x0040a021,
5588         0x00008821, 0x0e000625, 0x00000000, 0x00403021, 0x14c00007, 0x00000000,
5589         0x3c020800, 0x8c4223dc, 0x24420001, 0x3c010800, 0x0a000596, 0xac2223dc,
5590         0x3c100800, 0x02118021, 0x8e101bc8, 0x9608000a, 0x31020040, 0x10400005,
5591         0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x31020080,
5592         0x54400001, 0x34e70010, 0x3c020800, 0x00511021, 0x8c421bd0, 0x3c030800,
5593         0x00711821, 0x8c631bd4, 0x00021500, 0x00031c00, 0x00431025, 0xacc20014,
5594         0x96040008, 0x3242ffff, 0x00821021, 0x0282102a, 0x14400002, 0x02b22823,
5595         0x00802821, 0x8e020000, 0x02459021, 0xacc20000, 0x8e020004, 0x00c02021,
5596         0x26310010, 0xac820004, 0x30e2ffff, 0xac800008, 0xa485000e, 0xac820010,
5597         0x24020305, 0x0e0005a2, 0xa482000c, 0x3242ffff, 0x0054102b, 0x1440ffc5,
5598         0x3242ffff, 0x0a00058e, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
5599         0x10400067, 0x00000000, 0x8e62fff0, 0x00028900, 0x3c100800, 0x02118021,
5600         0x0e000625, 0x8e101bc8, 0x00403021, 0x14c00005, 0x00000000, 0x8e62082c,
5601         0x24420001, 0x0a000596, 0xae62082c, 0x9608000a, 0x31020040, 0x10400005,
5602         0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x3c020800,
5603         0x00511021, 0x8c421bd0, 0x3c030800, 0x00711821, 0x8c631bd4, 0x00021500,
5604         0x00031c00, 0x00431025, 0xacc20014, 0x8e63fff4, 0x96020008, 0x00432023,
5605         0x3242ffff, 0x3083ffff, 0x00431021, 0x02c2102a, 0x10400003, 0x00802821,
5606         0x97a9001e, 0x01322823, 0x8e620000, 0x30a4ffff, 0x00441021, 0xae620000,
5607         0xa4c5000e, 0x8e020000, 0xacc20000, 0x8e020004, 0x8e63fff4, 0x00431021,
5608         0xacc20004, 0x8e63fff4, 0x96020008, 0x00641821, 0x0062102a, 0x14400006,
5609         0x02459021, 0x8e62fff0, 0xae60fff4, 0x24420001, 0x0a000571, 0xae62fff0,
5610         0xae63fff4, 0xacc00008, 0x3242ffff, 0x10560003, 0x31020004, 0x10400006,
5611         0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x34e70020, 0x24020905,
5612         0xa4c2000c, 0x8ee30000, 0x8ee20004, 0x14620007, 0x3c02b49a, 0x8ee20860,
5613         0x54400001, 0x34e70400, 0x3c024b65, 0x0a000588, 0x34427654, 0x344289ab,
5614         0xacc2001c, 0x30e2ffff, 0xacc20010, 0x0e0005a2, 0x00c02021, 0x3242ffff,
5615         0x0056102b, 0x1440ff9b, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
5616         0x1440ff48, 0x00000000, 0x8fbf0044, 0x8fbe0040, 0x8fb7003c, 0x8fb60038,
5617         0x8fb50034, 0x8fb40030, 0x8fb3002c, 0x8fb20028, 0x8fb10024, 0x8fb00020,
5618         0x03e00008, 0x27bd0048, 0x27bdffe8, 0xafbf0014, 0xafb00010, 0x8f624450,
5619         0x8f634410, 0x0a0005b1, 0x00808021, 0x8f626820, 0x30422000, 0x10400003,
5620         0x00000000, 0x0e0001f0, 0x00002021, 0x8f624450, 0x8f634410, 0x3042ffff,
5621         0x0043102b, 0x1440fff5, 0x00000000, 0x8f630c14, 0x3063000f, 0x2c620002,
5622         0x1440000b, 0x00000000, 0x8f630c14, 0x3c020800, 0x8c421b40, 0x3063000f,
5623         0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7, 0x00000000,
5624         0xaf705c18, 0x8f625c10, 0x30420002, 0x10400009, 0x00000000, 0x8f626820,
5625         0x30422000, 0x1040fff8, 0x00000000, 0x0e0001f0, 0x00002021, 0x0a0005c4,
5626         0x00000000, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000,
5627         0x00000000, 0x00000000, 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010,
5628         0xaf60680c, 0x8f626804, 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50,
5629         0x3c010800, 0xac221b54, 0x24020b78, 0x3c010800, 0xac221b64, 0x34630002,
5630         0xaf634000, 0x0e000605, 0x00808021, 0x3c010800, 0xa0221b68, 0x304200ff,
5631         0x24030002, 0x14430005, 0x00000000, 0x3c020800, 0x8c421b54, 0x0a0005f8,
5632         0xac5000c0, 0x3c020800, 0x8c421b54, 0xac5000bc, 0x8f624434, 0x8f634438,
5633         0x8f644410, 0x3c010800, 0xac221b5c, 0x3c010800, 0xac231b6c, 0x3c010800,
5634         0xac241b58, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x3c040800,
5635         0x8c870000, 0x3c03aa55, 0x3463aa55, 0x3c06c003, 0xac830000, 0x8cc20000,
5636         0x14430007, 0x24050002, 0x3c0355aa, 0x346355aa, 0xac830000, 0x8cc20000,
5637         0x50430001, 0x24050001, 0x3c020800, 0xac470000, 0x03e00008, 0x00a01021,
5638         0x27bdfff8, 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe,
5639         0x00000000, 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008,
5640         0x27bd0008, 0x8f634450, 0x3c020800, 0x8c421b5c, 0x00031c02, 0x0043102b,
5641         0x14400008, 0x3c038000, 0x3c040800, 0x8c841b6c, 0x8f624450, 0x00021c02,
5642         0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
5643         0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff,
5644         0x2442e000, 0x2c422001, 0x14400003, 0x3c024000, 0x0a000648, 0x2402ffff,
5645         0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021,
5646         0x03e00008, 0x00000000, 0x8f624450, 0x3c030800, 0x8c631b58, 0x0a000651,
5647         0x3042ffff, 0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000,
5648         0x03e00008, 0x00000000, 0x27bdffe0, 0x00802821, 0x3c040800, 0x24841af0,
5649         0x00003021, 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014,
5650         0x0a000660, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000,
5651         0x00000000, 0x00000000, 0x3c020800, 0x34423000, 0x3c030800, 0x34633000,
5652         0x3c040800, 0x348437ff, 0x3c010800, 0xac221b74, 0x24020040, 0x3c010800,
5653         0xac221b78, 0x3c010800, 0xac201b70, 0xac600000, 0x24630004, 0x0083102b,
5654         0x5040fffd, 0xac600000, 0x03e00008, 0x00000000, 0x00804821, 0x8faa0010,
5655         0x3c020800, 0x8c421b70, 0x3c040800, 0x8c841b78, 0x8fab0014, 0x24430001,
5656         0x0044102b, 0x3c010800, 0xac231b70, 0x14400003, 0x00004021, 0x3c010800,
5657         0xac201b70, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74, 0x91240000,
5658         0x00021140, 0x00431021, 0x00481021, 0x25080001, 0xa0440000, 0x29020008,
5659         0x1440fff4, 0x25290001, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74,
5660         0x8f64680c, 0x00021140, 0x00431021, 0xac440008, 0xac45000c, 0xac460010,
5661         0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c, 0x00000000, 0x00000000,
5662 };
5663
5664 static const u32 tg3TsoFwRodata[] = {
5665         0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
5666         0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x496e0000, 0x73746b6f,
5667         0x66662a2a, 0x00000000, 0x53774576, 0x656e7430, 0x00000000, 0x00000000,
5668         0x00000000, 0x00000000, 0x66617461, 0x6c457272, 0x00000000, 0x00000000,
5669         0x00000000,
5670 };
5671
5672 static const u32 tg3TsoFwData[] = {
5673         0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x362e3000, 0x00000000,
5674         0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5675         0x00000000,
5676 };
5677
5678 /* 5705 needs a special version of the TSO firmware.  */
5679 #define TG3_TSO5_FW_RELEASE_MAJOR       0x1
5680 #define TG3_TSO5_FW_RELASE_MINOR        0x2
5681 #define TG3_TSO5_FW_RELEASE_FIX         0x0
5682 #define TG3_TSO5_FW_START_ADDR          0x00010000
5683 #define TG3_TSO5_FW_TEXT_ADDR           0x00010000
5684 #define TG3_TSO5_FW_TEXT_LEN            0xe90
5685 #define TG3_TSO5_FW_RODATA_ADDR         0x00010e90
5686 #define TG3_TSO5_FW_RODATA_LEN          0x50
5687 #define TG3_TSO5_FW_DATA_ADDR           0x00010f00
5688 #define TG3_TSO5_FW_DATA_LEN            0x20
5689 #define TG3_TSO5_FW_SBSS_ADDR           0x00010f20
5690 #define TG3_TSO5_FW_SBSS_LEN            0x28
5691 #define TG3_TSO5_FW_BSS_ADDR            0x00010f50
5692 #define TG3_TSO5_FW_BSS_LEN             0x88
5693
5694 static const u32 tg3Tso5FwText[(TG3_TSO5_FW_TEXT_LEN / 4) + 1] = {
5695         0x0c004003, 0x00000000, 0x00010f04, 0x00000000, 0x10000003, 0x00000000,
5696         0x0000000d, 0x0000000d, 0x3c1d0001, 0x37bde000, 0x03a0f021, 0x3c100001,
5697         0x26100000, 0x0c004010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
5698         0xafbf0018, 0x0c0042e8, 0x34840002, 0x0c004364, 0x00000000, 0x3c030001,
5699         0x90630f34, 0x24020002, 0x3c040001, 0x24840e9c, 0x14620003, 0x24050001,
5700         0x3c040001, 0x24840e90, 0x24060002, 0x00003821, 0xafa00010, 0x0c004378,
5701         0xafa00014, 0x0c00402c, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5702         0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c, 0xafb20018, 0xafb10014,
5703         0x0c0042d4, 0xafb00010, 0x3c128000, 0x24110001, 0x8f706810, 0x32020400,
5704         0x10400007, 0x00000000, 0x8f641008, 0x00921024, 0x14400003, 0x00000000,
5705         0x0c004064, 0x00000000, 0x3c020001, 0x90420f56, 0x10510003, 0x32020200,
5706         0x1040fff1, 0x00000000, 0x0c0041b4, 0x00000000, 0x08004034, 0x00000000,
5707         0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020,
5708         0x27bdffe0, 0x3c040001, 0x24840eb0, 0x00002821, 0x00003021, 0x00003821,
5709         0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0000d021, 0x24020130,
5710         0xaf625000, 0x3c010001, 0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018,
5711         0x03e00008, 0x27bd0020, 0x00000000, 0x00000000, 0x3c030001, 0x24630f60,
5712         0x90620000, 0x27bdfff0, 0x14400003, 0x0080c021, 0x08004073, 0x00004821,
5713         0x3c022000, 0x03021024, 0x10400003, 0x24090002, 0x08004073, 0xa0600000,
5714         0x24090001, 0x00181040, 0x30431f80, 0x346f8008, 0x1520004b, 0x25eb0028,
5715         0x3c040001, 0x00832021, 0x8c848010, 0x3c050001, 0x24a50f7a, 0x00041402,
5716         0xa0a20000, 0x3c010001, 0xa0240f7b, 0x3c020001, 0x00431021, 0x94428014,
5717         0x3c010001, 0xa0220f7c, 0x3c0c0001, 0x01836021, 0x8d8c8018, 0x304200ff,
5718         0x24420008, 0x000220c3, 0x24020001, 0x3c010001, 0xa0220f60, 0x0124102b,
5719         0x1040000c, 0x00003821, 0x24a6000e, 0x01602821, 0x8ca20000, 0x8ca30004,
5720         0x24a50008, 0x24e70001, 0xacc20000, 0xacc30004, 0x00e4102b, 0x1440fff8,
5721         0x24c60008, 0x00003821, 0x3c080001, 0x25080f7b, 0x91060000, 0x3c020001,
5722         0x90420f7c, 0x2503000d, 0x00c32821, 0x00461023, 0x00021fc2, 0x00431021,
5723         0x00021043, 0x1840000c, 0x00002021, 0x91020001, 0x00461023, 0x00021fc2,
5724         0x00431021, 0x00021843, 0x94a20000, 0x24e70001, 0x00822021, 0x00e3102a,
5725         0x1440fffb, 0x24a50002, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
5726         0x00822021, 0x3c02ffff, 0x01821024, 0x3083ffff, 0x00431025, 0x3c010001,
5727         0x080040fa, 0xac220f80, 0x3c050001, 0x24a50f7c, 0x90a20000, 0x3c0c0001,
5728         0x01836021, 0x8d8c8018, 0x000220c2, 0x1080000e, 0x00003821, 0x01603021,
5729         0x24a5000c, 0x8ca20000, 0x8ca30004, 0x24a50008, 0x24e70001, 0xacc20000,
5730         0xacc30004, 0x00e4102b, 0x1440fff8, 0x24c60008, 0x3c050001, 0x24a50f7c,
5731         0x90a20000, 0x30430007, 0x24020004, 0x10620011, 0x28620005, 0x10400005,
5732         0x24020002, 0x10620008, 0x000710c0, 0x080040fa, 0x00000000, 0x24020006,
5733         0x1062000e, 0x000710c0, 0x080040fa, 0x00000000, 0x00a21821, 0x9463000c,
5734         0x004b1021, 0x080040fa, 0xa4430000, 0x000710c0, 0x00a21821, 0x8c63000c,
5735         0x004b1021, 0x080040fa, 0xac430000, 0x00a21821, 0x8c63000c, 0x004b2021,
5736         0x00a21021, 0xac830000, 0x94420010, 0xa4820004, 0x95e70006, 0x3c020001,
5737         0x90420f7c, 0x3c030001, 0x90630f7a, 0x00e2c823, 0x3c020001, 0x90420f7b,
5738         0x24630028, 0x01e34021, 0x24420028, 0x15200012, 0x01e23021, 0x94c2000c,
5739         0x3c010001, 0xa4220f78, 0x94c20004, 0x94c30006, 0x3c010001, 0xa4200f76,
5740         0x3c010001, 0xa4200f72, 0x00021400, 0x00431025, 0x3c010001, 0xac220f6c,
5741         0x95020004, 0x3c010001, 0x08004124, 0xa4220f70, 0x3c020001, 0x94420f70,
5742         0x3c030001, 0x94630f72, 0x00431021, 0xa5020004, 0x3c020001, 0x94420f6c,
5743         0xa4c20004, 0x3c020001, 0x8c420f6c, 0xa4c20006, 0x3c040001, 0x94840f72,
5744         0x3c020001, 0x94420f70, 0x3c0a0001, 0x954a0f76, 0x00441821, 0x3063ffff,
5745         0x0062182a, 0x24020002, 0x1122000b, 0x00832023, 0x3c030001, 0x94630f78,
5746         0x30620009, 0x10400006, 0x3062fff6, 0xa4c2000c, 0x3c020001, 0x94420f78,
5747         0x30420009, 0x01425023, 0x24020001, 0x1122001b, 0x29220002, 0x50400005,
5748         0x24020002, 0x11200007, 0x31a2ffff, 0x08004197, 0x00000000, 0x1122001d,
5749         0x24020016, 0x08004197, 0x31a2ffff, 0x3c0e0001, 0x95ce0f80, 0x10800005,
5750         0x01806821, 0x01c42021, 0x00041c02, 0x3082ffff, 0x00627021, 0x000e1027,
5751         0xa502000a, 0x3c030001, 0x90630f7b, 0x31a2ffff, 0x00e21021, 0x0800418d,
5752         0x00432023, 0x3c020001, 0x94420f80, 0x00442021, 0x00041c02, 0x3082ffff,
5753         0x00622021, 0x00807021, 0x00041027, 0x08004185, 0xa502000a, 0x3c050001,
5754         0x24a50f7a, 0x90a30000, 0x14620002, 0x24e2fff2, 0xa5e20034, 0x90a20000,
5755         0x00e21023, 0xa5020002, 0x3c030001, 0x94630f80, 0x3c020001, 0x94420f5a,
5756         0x30e5ffff, 0x00641821, 0x00451023, 0x00622023, 0x00041c02, 0x3082ffff,
5757         0x00622021, 0x00041027, 0xa502000a, 0x3c030001, 0x90630f7c, 0x24620001,
5758         0x14a20005, 0x00807021, 0x01631021, 0x90420000, 0x08004185, 0x00026200,
5759         0x24620002, 0x14a20003, 0x306200fe, 0x004b1021, 0x944c0000, 0x3c020001,
5760         0x94420f82, 0x3183ffff, 0x3c040001, 0x90840f7b, 0x00431021, 0x00e21021,
5761         0x00442023, 0x008a2021, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
5762         0x00822021, 0x00806821, 0x00041027, 0xa4c20010, 0x31a2ffff, 0x000e1c00,
5763         0x00431025, 0x3c040001, 0x24840f72, 0xade20010, 0x94820000, 0x3c050001,
5764         0x94a50f76, 0x3c030001, 0x8c630f6c, 0x24420001, 0x00b92821, 0xa4820000,
5765         0x3322ffff, 0x00622021, 0x0083182b, 0x3c010001, 0xa4250f76, 0x10600003,
5766         0x24a2ffff, 0x3c010001, 0xa4220f76, 0x3c024000, 0x03021025, 0x3c010001,
5767         0xac240f6c, 0xaf621008, 0x03e00008, 0x27bd0010, 0x3c030001, 0x90630f56,
5768         0x27bdffe8, 0x24020001, 0xafbf0014, 0x10620026, 0xafb00010, 0x8f620cf4,
5769         0x2442ffff, 0x3042007f, 0x00021100, 0x8c434000, 0x3c010001, 0xac230f64,
5770         0x8c434008, 0x24444000, 0x8c5c4004, 0x30620040, 0x14400002, 0x24020088,
5771         0x24020008, 0x3c010001, 0xa4220f68, 0x30620004, 0x10400005, 0x24020001,
5772         0x3c010001, 0xa0220f57, 0x080041d5, 0x00031402, 0x3c010001, 0xa0200f57,
5773         0x00031402, 0x3c010001, 0xa4220f54, 0x9483000c, 0x24020001, 0x3c010001,
5774         0xa4200f50, 0x3c010001, 0xa0220f56, 0x3c010001, 0xa4230f62, 0x24020001,
5775         0x1342001e, 0x00000000, 0x13400005, 0x24020003, 0x13420067, 0x00000000,
5776         0x080042cf, 0x00000000, 0x3c020001, 0x94420f62, 0x241a0001, 0x3c010001,
5777         0xa4200f5e, 0x3c010001, 0xa4200f52, 0x304407ff, 0x00021bc2, 0x00031823,
5778         0x3063003e, 0x34630036, 0x00021242, 0x3042003c, 0x00621821, 0x3c010001,
5779         0xa4240f58, 0x00832021, 0x24630030, 0x3c010001, 0xa4240f5a, 0x3c010001,
5780         0xa4230f5c, 0x3c060001, 0x24c60f52, 0x94c50000, 0x94c30002, 0x3c040001,
5781         0x94840f5a, 0x00651021, 0x0044102a, 0x10400013, 0x3c108000, 0x00a31021,
5782         0xa4c20000, 0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008,
5783         0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4,
5784         0x00501024, 0x104000b7, 0x00000000, 0x0800420f, 0x00000000, 0x3c030001,
5785         0x94630f50, 0x00851023, 0xa4c40000, 0x00621821, 0x3042ffff, 0x3c010001,
5786         0xa4230f50, 0xaf620ce8, 0x3c020001, 0x94420f68, 0x34420024, 0xaf620cec,
5787         0x94c30002, 0x3c020001, 0x94420f50, 0x14620012, 0x3c028000, 0x3c108000,
5788         0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008, 0x00901024,
5789         0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024,
5790         0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003, 0xaf620cf4, 0x3c108000,
5791         0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000,
5792         0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003,
5793         0x3c070001, 0x24e70f50, 0x94e20000, 0x03821021, 0xaf620ce0, 0x3c020001,
5794         0x8c420f64, 0xaf620ce4, 0x3c050001, 0x94a50f54, 0x94e30000, 0x3c040001,
5795         0x94840f58, 0x3c020001, 0x94420f5e, 0x00a32823, 0x00822023, 0x30a6ffff,
5796         0x3083ffff, 0x00c3102b, 0x14400043, 0x00000000, 0x3c020001, 0x94420f5c,
5797         0x00021400, 0x00621025, 0xaf620ce8, 0x94e20000, 0x3c030001, 0x94630f54,
5798         0x00441021, 0xa4e20000, 0x3042ffff, 0x14430021, 0x3c020008, 0x3c020001,
5799         0x90420f57, 0x10400006, 0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624,
5800         0x0800427c, 0x0000d021, 0x3c020001, 0x94420f68, 0x3c030008, 0x34630624,
5801         0x00431025, 0xaf620cec, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
5802         0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
5803         0x00000000, 0x8f620cf4, 0x00501024, 0x10400015, 0x00000000, 0x08004283,
5804         0x00000000, 0x3c030001, 0x94630f68, 0x34420624, 0x3c108000, 0x00621825,
5805         0x3c028000, 0xaf630cec, 0xaf620cf4, 0x8f641008, 0x00901024, 0x14400003,
5806         0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7,
5807         0x00000000, 0x3c010001, 0x080042cf, 0xa4200f5e, 0x3c020001, 0x94420f5c,
5808         0x00021400, 0x00c21025, 0xaf620ce8, 0x3c020001, 0x90420f57, 0x10400009,
5809         0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624, 0x0000d021, 0x00431025,
5810         0xaf620cec, 0x080042c1, 0x3c108000, 0x3c020001, 0x94420f68, 0x3c030008,
5811         0x34630604, 0x00431025, 0xaf620cec, 0x3c020001, 0x94420f5e, 0x00451021,
5812         0x3c010001, 0xa4220f5e, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
5813         0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
5814         0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x8fbf0014,
5815         0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000, 0x27bdffe0, 0x3c040001,
5816         0x24840ec0, 0x00002821, 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010,
5817         0x0c004378, 0xafa00014, 0x0000d021, 0x24020130, 0xaf625000, 0x3c010001,
5818         0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5819         0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010, 0xaf60680c, 0x8f626804,
5820         0x34420082, 0xaf626804, 0x8f634000, 0x24020b50, 0x3c010001, 0xac220f20,
5821         0x24020b78, 0x3c010001, 0xac220f30, 0x34630002, 0xaf634000, 0x0c004315,
5822         0x00808021, 0x3c010001, 0xa0220f34, 0x304200ff, 0x24030002, 0x14430005,
5823         0x00000000, 0x3c020001, 0x8c420f20, 0x08004308, 0xac5000c0, 0x3c020001,
5824         0x8c420f20, 0xac5000bc, 0x8f624434, 0x8f634438, 0x8f644410, 0x3c010001,
5825         0xac220f28, 0x3c010001, 0xac230f38, 0x3c010001, 0xac240f24, 0x8fbf0014,
5826         0x8fb00010, 0x03e00008, 0x27bd0018, 0x03e00008, 0x24020001, 0x27bdfff8,
5827         0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe, 0x00000000,
5828         0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008, 0x27bd0008,
5829         0x8f634450, 0x3c020001, 0x8c420f28, 0x00031c02, 0x0043102b, 0x14400008,
5830         0x3c038000, 0x3c040001, 0x8c840f38, 0x8f624450, 0x00021c02, 0x0083102b,
5831         0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024, 0x1440fffd,
5832         0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff, 0x2442e000,
5833         0x2c422001, 0x14400003, 0x3c024000, 0x08004347, 0x2402ffff, 0x00822025,
5834         0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021, 0x03e00008,
5835         0x00000000, 0x8f624450, 0x3c030001, 0x8c630f24, 0x08004350, 0x3042ffff,
5836         0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000, 0x03e00008,
5837         0x00000000, 0x27bdffe0, 0x00802821, 0x3c040001, 0x24840ed0, 0x00003021,
5838         0x00003821, 0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0800435f,
5839         0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x3c020001, 0x3442d600,
5840         0x3c030001, 0x3463d600, 0x3c040001, 0x3484ddff, 0x3c010001, 0xac220f40,
5841         0x24020040, 0x3c010001, 0xac220f44, 0x3c010001, 0xac200f3c, 0xac600000,
5842         0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
5843         0x00804821, 0x8faa0010, 0x3c020001, 0x8c420f3c, 0x3c040001, 0x8c840f44,
5844         0x8fab0014, 0x24430001, 0x0044102b, 0x3c010001, 0xac230f3c, 0x14400003,
5845         0x00004021, 0x3c010001, 0xac200f3c, 0x3c020001, 0x8c420f3c, 0x3c030001,
5846         0x8c630f40, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
5847         0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020001, 0x8c420f3c,
5848         0x3c030001, 0x8c630f40, 0x8f64680c, 0x00021140, 0x00431021, 0xac440008,
5849         0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
5850         0x00000000, 0x00000000, 0x00000000,
5851 };
5852
5853 static const u32 tg3Tso5FwRodata[(TG3_TSO5_FW_RODATA_LEN / 4) + 1] = {
5854         0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
5855         0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x00000000, 0x00000000,
5856         0x73746b6f, 0x66666c64, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
5857         0x00000000, 0x00000000, 0x00000000,
5858 };
5859
5860 static const u32 tg3Tso5FwData[(TG3_TSO5_FW_DATA_LEN / 4) + 1] = {
5861         0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x322e3000, 0x00000000,
5862         0x00000000, 0x00000000, 0x00000000,
5863 };
5864
5865 /* tp->lock is held. */
5866 static int tg3_load_tso_firmware(struct tg3 *tp)
5867 {
5868         struct fw_info info;
5869         unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
5870         int err, i;
5871
5872         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5873                 return 0;
5874
5875         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5876                 info.text_base = TG3_TSO5_FW_TEXT_ADDR;
5877                 info.text_len = TG3_TSO5_FW_TEXT_LEN;
5878                 info.text_data = &tg3Tso5FwText[0];
5879                 info.rodata_base = TG3_TSO5_FW_RODATA_ADDR;
5880                 info.rodata_len = TG3_TSO5_FW_RODATA_LEN;
5881                 info.rodata_data = &tg3Tso5FwRodata[0];
5882                 info.data_base = TG3_TSO5_FW_DATA_ADDR;
5883                 info.data_len = TG3_TSO5_FW_DATA_LEN;
5884                 info.data_data = &tg3Tso5FwData[0];
5885                 cpu_base = RX_CPU_BASE;
5886                 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
5887                 cpu_scratch_size = (info.text_len +
5888                                     info.rodata_len +
5889                                     info.data_len +
5890                                     TG3_TSO5_FW_SBSS_LEN +
5891                                     TG3_TSO5_FW_BSS_LEN);
5892         } else {
5893                 info.text_base = TG3_TSO_FW_TEXT_ADDR;
5894                 info.text_len = TG3_TSO_FW_TEXT_LEN;
5895                 info.text_data = &tg3TsoFwText[0];
5896                 info.rodata_base = TG3_TSO_FW_RODATA_ADDR;
5897                 info.rodata_len = TG3_TSO_FW_RODATA_LEN;
5898                 info.rodata_data = &tg3TsoFwRodata[0];
5899                 info.data_base = TG3_TSO_FW_DATA_ADDR;
5900                 info.data_len = TG3_TSO_FW_DATA_LEN;
5901                 info.data_data = &tg3TsoFwData[0];
5902                 cpu_base = TX_CPU_BASE;
5903                 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
5904                 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
5905         }
5906
5907         err = tg3_load_firmware_cpu(tp, cpu_base,
5908                                     cpu_scratch_base, cpu_scratch_size,
5909                                     &info);
5910         if (err)
5911                 return err;
5912
5913         /* Now startup the cpu. */
5914         tw32(cpu_base + CPU_STATE, 0xffffffff);
5915         tw32_f(cpu_base + CPU_PC,    info.text_base);
5916
5917         for (i = 0; i < 5; i++) {
5918                 if (tr32(cpu_base + CPU_PC) == info.text_base)
5919                         break;
5920                 tw32(cpu_base + CPU_STATE, 0xffffffff);
5921                 tw32(cpu_base + CPU_MODE,  CPU_MODE_HALT);
5922                 tw32_f(cpu_base + CPU_PC,    info.text_base);
5923                 udelay(1000);
5924         }
5925         if (i >= 5) {
5926                 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
5927                        "to set CPU PC, is %08x should be %08x\n",
5928                        tp->dev->name, tr32(cpu_base + CPU_PC),
5929                        info.text_base);
5930                 return -ENODEV;
5931         }
5932         tw32(cpu_base + CPU_STATE, 0xffffffff);
5933         tw32_f(cpu_base + CPU_MODE,  0x00000000);
5934         return 0;
5935 }
5936
5937
5938 /* tp->lock is held. */
5939 static void __tg3_set_mac_addr(struct tg3 *tp)
5940 {
5941         u32 addr_high, addr_low;
5942         int i;
5943
5944         addr_high = ((tp->dev->dev_addr[0] << 8) |
5945                      tp->dev->dev_addr[1]);
5946         addr_low = ((tp->dev->dev_addr[2] << 24) |
5947                     (tp->dev->dev_addr[3] << 16) |
5948                     (tp->dev->dev_addr[4] <<  8) |
5949                     (tp->dev->dev_addr[5] <<  0));
5950         for (i = 0; i < 4; i++) {
5951                 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
5952                 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
5953         }
5954
5955         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
5956             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
5957                 for (i = 0; i < 12; i++) {
5958                         tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
5959                         tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
5960                 }
5961         }
5962
5963         addr_high = (tp->dev->dev_addr[0] +
5964                      tp->dev->dev_addr[1] +
5965                      tp->dev->dev_addr[2] +
5966                      tp->dev->dev_addr[3] +
5967                      tp->dev->dev_addr[4] +
5968                      tp->dev->dev_addr[5]) &
5969                 TX_BACKOFF_SEED_MASK;
5970         tw32(MAC_TX_BACKOFF_SEED, addr_high);
5971 }
5972
5973 static int tg3_set_mac_addr(struct net_device *dev, void *p)
5974 {
5975         struct tg3 *tp = netdev_priv(dev);
5976         struct sockaddr *addr = p;
5977         int err = 0;
5978
5979         if (!is_valid_ether_addr(addr->sa_data))
5980                 return -EINVAL;
5981
5982         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
5983
5984         if (!netif_running(dev))
5985                 return 0;
5986
5987         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
5988                 /* Reset chip so that ASF can re-init any MAC addresses it
5989                  * needs.
5990                  */
5991                 tg3_netif_stop(tp);
5992                 tg3_full_lock(tp, 1);
5993
5994                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5995                 err = tg3_restart_hw(tp, 0);
5996                 if (!err)
5997                         tg3_netif_start(tp);
5998                 tg3_full_unlock(tp);
5999         } else {
6000                 spin_lock_bh(&tp->lock);
6001                 __tg3_set_mac_addr(tp);
6002                 spin_unlock_bh(&tp->lock);
6003         }
6004
6005         return err;
6006 }
6007
6008 /* tp->lock is held. */
6009 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
6010                            dma_addr_t mapping, u32 maxlen_flags,
6011                            u32 nic_addr)
6012 {
6013         tg3_write_mem(tp,
6014                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
6015                       ((u64) mapping >> 32));
6016         tg3_write_mem(tp,
6017                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
6018                       ((u64) mapping & 0xffffffff));
6019         tg3_write_mem(tp,
6020                       (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
6021                        maxlen_flags);
6022
6023         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6024                 tg3_write_mem(tp,
6025                               (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
6026                               nic_addr);
6027 }
6028
6029 static void __tg3_set_rx_mode(struct net_device *);
6030 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
6031 {
6032         tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
6033         tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
6034         tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
6035         tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
6036         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6037                 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
6038                 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
6039         }
6040         tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
6041         tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
6042         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6043                 u32 val = ec->stats_block_coalesce_usecs;
6044
6045                 if (!netif_carrier_ok(tp->dev))
6046                         val = 0;
6047
6048                 tw32(HOSTCC_STAT_COAL_TICKS, val);
6049         }
6050 }
6051
6052 /* tp->lock is held. */
6053 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
6054 {
6055         u32 val, rdmac_mode;
6056         int i, err, limit;
6057
6058         tg3_disable_ints(tp);
6059
6060         tg3_stop_fw(tp);
6061
6062         tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
6063
6064         if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
6065                 tg3_abort_hw(tp, 1);
6066         }
6067
6068         if (reset_phy)
6069                 tg3_phy_reset(tp);
6070
6071         err = tg3_chip_reset(tp);
6072         if (err)
6073                 return err;
6074
6075         tg3_write_sig_legacy(tp, RESET_KIND_INIT);
6076
6077         /* This works around an issue with Athlon chipsets on
6078          * B3 tigon3 silicon.  This bit has no effect on any
6079          * other revision.  But do not set this on PCI Express
6080          * chips.
6081          */
6082         if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
6083                 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
6084         tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6085
6086         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6087             (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
6088                 val = tr32(TG3PCI_PCISTATE);
6089                 val |= PCISTATE_RETRY_SAME_DMA;
6090                 tw32(TG3PCI_PCISTATE, val);
6091         }
6092
6093         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
6094                 /* Enable some hw fixes.  */
6095                 val = tr32(TG3PCI_MSI_DATA);
6096                 val |= (1 << 26) | (1 << 28) | (1 << 29);
6097                 tw32(TG3PCI_MSI_DATA, val);
6098         }
6099
6100         /* Descriptor ring init may make accesses to the
6101          * NIC SRAM area to setup the TX descriptors, so we
6102          * can only do this after the hardware has been
6103          * successfully reset.
6104          */
6105         err = tg3_init_rings(tp);
6106         if (err)
6107                 return err;
6108
6109         /* This value is determined during the probe time DMA
6110          * engine test, tg3_test_dma.
6111          */
6112         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
6113
6114         tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
6115                           GRC_MODE_4X_NIC_SEND_RINGS |
6116                           GRC_MODE_NO_TX_PHDR_CSUM |
6117                           GRC_MODE_NO_RX_PHDR_CSUM);
6118         tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
6119
6120         /* Pseudo-header checksum is done by hardware logic and not
6121          * the offload processers, so make the chip do the pseudo-
6122          * header checksums on receive.  For transmit it is more
6123          * convenient to do the pseudo-header checksum in software
6124          * as Linux does that on transmit for us in all cases.
6125          */
6126         tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
6127
6128         tw32(GRC_MODE,
6129              tp->grc_mode |
6130              (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
6131
6132         /* Setup the timer prescalar register.  Clock is always 66Mhz. */
6133         val = tr32(GRC_MISC_CFG);
6134         val &= ~0xff;
6135         val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
6136         tw32(GRC_MISC_CFG, val);
6137
6138         /* Initialize MBUF/DESC pool. */
6139         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
6140                 /* Do nothing.  */
6141         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
6142                 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
6143                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
6144                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
6145                 else
6146                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
6147                 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
6148                 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
6149         }
6150         else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
6151                 int fw_len;
6152
6153                 fw_len = (TG3_TSO5_FW_TEXT_LEN +
6154                           TG3_TSO5_FW_RODATA_LEN +
6155                           TG3_TSO5_FW_DATA_LEN +
6156                           TG3_TSO5_FW_SBSS_LEN +
6157                           TG3_TSO5_FW_BSS_LEN);
6158                 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
6159                 tw32(BUFMGR_MB_POOL_ADDR,
6160                      NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
6161                 tw32(BUFMGR_MB_POOL_SIZE,
6162                      NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
6163         }
6164
6165         if (tp->dev->mtu <= ETH_DATA_LEN) {
6166                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
6167                      tp->bufmgr_config.mbuf_read_dma_low_water);
6168                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
6169                      tp->bufmgr_config.mbuf_mac_rx_low_water);
6170                 tw32(BUFMGR_MB_HIGH_WATER,
6171                      tp->bufmgr_config.mbuf_high_water);
6172         } else {
6173                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
6174                      tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
6175                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
6176                      tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
6177                 tw32(BUFMGR_MB_HIGH_WATER,
6178                      tp->bufmgr_config.mbuf_high_water_jumbo);
6179         }
6180         tw32(BUFMGR_DMA_LOW_WATER,
6181              tp->bufmgr_config.dma_low_water);
6182         tw32(BUFMGR_DMA_HIGH_WATER,
6183              tp->bufmgr_config.dma_high_water);
6184
6185         tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
6186         for (i = 0; i < 2000; i++) {
6187                 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
6188                         break;
6189                 udelay(10);
6190         }
6191         if (i >= 2000) {
6192                 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
6193                        tp->dev->name);
6194                 return -ENODEV;
6195         }
6196
6197         /* Setup replenish threshold. */
6198         val = tp->rx_pending / 8;
6199         if (val == 0)
6200                 val = 1;
6201         else if (val > tp->rx_std_max_post)
6202                 val = tp->rx_std_max_post;
6203         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6204                 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
6205                         tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
6206
6207                 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
6208                         val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
6209         }
6210
6211         tw32(RCVBDI_STD_THRESH, val);
6212
6213         /* Initialize TG3_BDINFO's at:
6214          *  RCVDBDI_STD_BD:     standard eth size rx ring
6215          *  RCVDBDI_JUMBO_BD:   jumbo frame rx ring
6216          *  RCVDBDI_MINI_BD:    small frame rx ring (??? does not work)
6217          *
6218          * like so:
6219          *  TG3_BDINFO_HOST_ADDR:       high/low parts of DMA address of ring
6220          *  TG3_BDINFO_MAXLEN_FLAGS:    (rx max buffer size << 16) |
6221          *                              ring attribute flags
6222          *  TG3_BDINFO_NIC_ADDR:        location of descriptors in nic SRAM
6223          *
6224          * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
6225          * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
6226          *
6227          * The size of each ring is fixed in the firmware, but the location is
6228          * configurable.
6229          */
6230         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
6231              ((u64) tp->rx_std_mapping >> 32));
6232         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
6233              ((u64) tp->rx_std_mapping & 0xffffffff));
6234         tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
6235              NIC_SRAM_RX_BUFFER_DESC);
6236
6237         /* Don't even try to program the JUMBO/MINI buffer descriptor
6238          * configs on 5705.
6239          */
6240         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6241                 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
6242                      RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT);
6243         } else {
6244                 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
6245                      RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
6246
6247                 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
6248                      BDINFO_FLAGS_DISABLED);
6249
6250                 /* Setup replenish threshold. */
6251                 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
6252
6253                 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
6254                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
6255                              ((u64) tp->rx_jumbo_mapping >> 32));
6256                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
6257                              ((u64) tp->rx_jumbo_mapping & 0xffffffff));
6258                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
6259                              RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
6260                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
6261                              NIC_SRAM_RX_JUMBO_BUFFER_DESC);
6262                 } else {
6263                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
6264                              BDINFO_FLAGS_DISABLED);
6265                 }
6266
6267         }
6268
6269         /* There is only one send ring on 5705/5750, no need to explicitly
6270          * disable the others.
6271          */
6272         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6273                 /* Clear out send RCB ring in SRAM. */
6274                 for (i = NIC_SRAM_SEND_RCB; i < NIC_SRAM_RCV_RET_RCB; i += TG3_BDINFO_SIZE)
6275                         tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
6276                                       BDINFO_FLAGS_DISABLED);
6277         }
6278
6279         tp->tx_prod = 0;
6280         tp->tx_cons = 0;
6281         tw32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
6282         tw32_tx_mbox(MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
6283
6284         tg3_set_bdinfo(tp, NIC_SRAM_SEND_RCB,
6285                        tp->tx_desc_mapping,
6286                        (TG3_TX_RING_SIZE <<
6287                         BDINFO_FLAGS_MAXLEN_SHIFT),
6288                        NIC_SRAM_TX_BUFFER_DESC);
6289
6290         /* There is only one receive return ring on 5705/5750, no need
6291          * to explicitly disable the others.
6292          */
6293         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6294                 for (i = NIC_SRAM_RCV_RET_RCB; i < NIC_SRAM_STATS_BLK;
6295                      i += TG3_BDINFO_SIZE) {
6296                         tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
6297                                       BDINFO_FLAGS_DISABLED);
6298                 }
6299         }
6300
6301         tp->rx_rcb_ptr = 0;
6302         tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, 0);
6303
6304         tg3_set_bdinfo(tp, NIC_SRAM_RCV_RET_RCB,
6305                        tp->rx_rcb_mapping,
6306                        (TG3_RX_RCB_RING_SIZE(tp) <<
6307                         BDINFO_FLAGS_MAXLEN_SHIFT),
6308                        0);
6309
6310         tp->rx_std_ptr = tp->rx_pending;
6311         tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
6312                      tp->rx_std_ptr);
6313
6314         tp->rx_jumbo_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
6315                                                 tp->rx_jumbo_pending : 0;
6316         tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
6317                      tp->rx_jumbo_ptr);
6318
6319         /* Initialize MAC address and backoff seed. */
6320         __tg3_set_mac_addr(tp);
6321
6322         /* MTU + ethernet header + FCS + optional VLAN tag */
6323         tw32(MAC_RX_MTU_SIZE, tp->dev->mtu + ETH_HLEN + 8);
6324
6325         /* The slot time is changed by tg3_setup_phy if we
6326          * run at gigabit with half duplex.
6327          */
6328         tw32(MAC_TX_LENGTHS,
6329              (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
6330              (6 << TX_LENGTHS_IPG_SHIFT) |
6331              (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
6332
6333         /* Receive rules. */
6334         tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
6335         tw32(RCVLPC_CONFIG, 0x0181);
6336
6337         /* Calculate RDMAC_MODE setting early, we need it to determine
6338          * the RCVLPC_STATE_ENABLE mask.
6339          */
6340         rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
6341                       RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
6342                       RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
6343                       RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
6344                       RDMAC_MODE_LNGREAD_ENAB);
6345
6346         /* If statement applies to 5705 and 5750 PCI devices only */
6347         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
6348              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
6349             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
6350                 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
6351                     (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
6352                      tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
6353                         rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
6354                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
6355                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
6356                         rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
6357                 }
6358         }
6359
6360         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6361                 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
6362
6363         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6364                 rdmac_mode |= (1 << 27);
6365
6366         /* Receive/send statistics. */
6367         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
6368                 val = tr32(RCVLPC_STATS_ENABLE);
6369                 val &= ~RCVLPC_STATSENAB_DACK_FIX;
6370                 tw32(RCVLPC_STATS_ENABLE, val);
6371         } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
6372                    (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
6373                 val = tr32(RCVLPC_STATS_ENABLE);
6374                 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
6375                 tw32(RCVLPC_STATS_ENABLE, val);
6376         } else {
6377                 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
6378         }
6379         tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
6380         tw32(SNDDATAI_STATSENAB, 0xffffff);
6381         tw32(SNDDATAI_STATSCTRL,
6382              (SNDDATAI_SCTRL_ENABLE |
6383               SNDDATAI_SCTRL_FASTUPD));
6384
6385         /* Setup host coalescing engine. */
6386         tw32(HOSTCC_MODE, 0);
6387         for (i = 0; i < 2000; i++) {
6388                 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
6389                         break;
6390                 udelay(10);
6391         }
6392
6393         __tg3_set_coalesce(tp, &tp->coal);
6394
6395         /* set status block DMA address */
6396         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
6397              ((u64) tp->status_mapping >> 32));
6398         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
6399              ((u64) tp->status_mapping & 0xffffffff));
6400
6401         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6402                 /* Status/statistics block address.  See tg3_timer,
6403                  * the tg3_periodic_fetch_stats call there, and
6404                  * tg3_get_stats to see how this works for 5705/5750 chips.
6405                  */
6406                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
6407                      ((u64) tp->stats_mapping >> 32));
6408                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
6409                      ((u64) tp->stats_mapping & 0xffffffff));
6410                 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
6411                 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
6412         }
6413
6414         tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
6415
6416         tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
6417         tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
6418         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6419                 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
6420
6421         /* Clear statistics/status block in chip, and status block in ram. */
6422         for (i = NIC_SRAM_STATS_BLK;
6423              i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
6424              i += sizeof(u32)) {
6425                 tg3_write_mem(tp, i, 0);
6426                 udelay(40);
6427         }
6428         memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
6429
6430         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
6431                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
6432                 /* reset to prevent losing 1st rx packet intermittently */
6433                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
6434                 udelay(10);
6435         }
6436
6437         tp->mac_mode = MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
6438                 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
6439         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
6440         udelay(40);
6441
6442         /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
6443          * If TG3_FLG2_IS_NIC is zero, we should read the
6444          * register to preserve the GPIO settings for LOMs. The GPIOs,
6445          * whether used as inputs or outputs, are set by boot code after
6446          * reset.
6447          */
6448         if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
6449                 u32 gpio_mask;
6450
6451                 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
6452                             GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
6453                             GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
6454
6455                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
6456                         gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
6457                                      GRC_LCLCTRL_GPIO_OUTPUT3;
6458
6459                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
6460                         gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
6461
6462                 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
6463
6464                 /* GPIO1 must be driven high for eeprom write protect */
6465                 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
6466                         tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
6467                                                GRC_LCLCTRL_GPIO_OUTPUT1);
6468         }
6469         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
6470         udelay(100);
6471
6472         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0);
6473         tp->last_tag = 0;
6474
6475         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6476                 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
6477                 udelay(40);
6478         }
6479
6480         val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
6481                WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
6482                WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
6483                WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
6484                WDMAC_MODE_LNGREAD_ENAB);
6485
6486         /* If statement applies to 5705 and 5750 PCI devices only */
6487         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
6488              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
6489             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
6490                 if ((tp->tg3_flags & TG3_FLG2_TSO_CAPABLE) &&
6491                     (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
6492                      tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
6493                         /* nothing */
6494                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
6495                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
6496                            !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
6497                         val |= WDMAC_MODE_RX_ACCEL;
6498                 }
6499         }
6500
6501         /* Enable host coalescing bug fix */
6502         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) ||
6503             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787))
6504                 val |= (1 << 29);
6505
6506         tw32_f(WDMAC_MODE, val);
6507         udelay(40);
6508
6509         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) {
6510                 val = tr32(TG3PCI_X_CAPS);
6511                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
6512                         val &= ~PCIX_CAPS_BURST_MASK;
6513                         val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
6514                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
6515                         val &= ~(PCIX_CAPS_SPLIT_MASK | PCIX_CAPS_BURST_MASK);
6516                         val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
6517                 }
6518                 tw32(TG3PCI_X_CAPS, val);
6519         }
6520
6521         tw32_f(RDMAC_MODE, rdmac_mode);
6522         udelay(40);
6523
6524         tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
6525         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6526                 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
6527         tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
6528         tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
6529         tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
6530         tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
6531         tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
6532         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6533                 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
6534         tw32(SNDBDI_MODE, SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE);
6535         tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
6536
6537         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
6538                 err = tg3_load_5701_a0_firmware_fix(tp);
6539                 if (err)
6540                         return err;
6541         }
6542
6543         if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
6544                 err = tg3_load_tso_firmware(tp);
6545                 if (err)
6546                         return err;
6547         }
6548
6549         tp->tx_mode = TX_MODE_ENABLE;
6550         tw32_f(MAC_TX_MODE, tp->tx_mode);
6551         udelay(100);
6552
6553         tp->rx_mode = RX_MODE_ENABLE;
6554         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
6555                 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
6556
6557         tw32_f(MAC_RX_MODE, tp->rx_mode);
6558         udelay(10);
6559
6560         if (tp->link_config.phy_is_low_power) {
6561                 tp->link_config.phy_is_low_power = 0;
6562                 tp->link_config.speed = tp->link_config.orig_speed;
6563                 tp->link_config.duplex = tp->link_config.orig_duplex;
6564                 tp->link_config.autoneg = tp->link_config.orig_autoneg;
6565         }
6566
6567         tp->mi_mode = MAC_MI_MODE_BASE;
6568         tw32_f(MAC_MI_MODE, tp->mi_mode);
6569         udelay(80);
6570
6571         tw32(MAC_LED_CTRL, tp->led_ctrl);
6572
6573         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
6574         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6575                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
6576                 udelay(10);
6577         }
6578         tw32_f(MAC_RX_MODE, tp->rx_mode);
6579         udelay(10);
6580
6581         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6582                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
6583                         !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
6584                         /* Set drive transmission level to 1.2V  */
6585                         /* only if the signal pre-emphasis bit is not set  */
6586                         val = tr32(MAC_SERDES_CFG);
6587                         val &= 0xfffff000;
6588                         val |= 0x880;
6589                         tw32(MAC_SERDES_CFG, val);
6590                 }
6591                 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
6592                         tw32(MAC_SERDES_CFG, 0x616000);
6593         }
6594
6595         /* Prevent chip from dropping frames when flow control
6596          * is enabled.
6597          */
6598         tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
6599
6600         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
6601             (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
6602                 /* Use hardware link auto-negotiation */
6603                 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
6604         }
6605
6606         if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
6607             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
6608                 u32 tmp;
6609
6610                 tmp = tr32(SERDES_RX_CTRL);
6611                 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
6612                 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
6613                 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
6614                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
6615         }
6616
6617         err = tg3_setup_phy(tp, 0);
6618         if (err)
6619                 return err;
6620
6621         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
6622             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906) {
6623                 u32 tmp;
6624
6625                 /* Clear CRC stats. */
6626                 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
6627                         tg3_writephy(tp, MII_TG3_TEST1,
6628                                      tmp | MII_TG3_TEST1_CRC_EN);
6629                         tg3_readphy(tp, 0x14, &tmp);
6630                 }
6631         }
6632
6633         __tg3_set_rx_mode(tp->dev);
6634
6635         /* Initialize receive rules. */
6636         tw32(MAC_RCV_RULE_0,  0xc2000000 & RCV_RULE_DISABLE_MASK);
6637         tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
6638         tw32(MAC_RCV_RULE_1,  0x86000004 & RCV_RULE_DISABLE_MASK);
6639         tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
6640
6641         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
6642             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
6643                 limit = 8;
6644         else
6645                 limit = 16;
6646         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
6647                 limit -= 4;
6648         switch (limit) {
6649         case 16:
6650                 tw32(MAC_RCV_RULE_15,  0); tw32(MAC_RCV_VALUE_15,  0);
6651         case 15:
6652                 tw32(MAC_RCV_RULE_14,  0); tw32(MAC_RCV_VALUE_14,  0);
6653         case 14:
6654                 tw32(MAC_RCV_RULE_13,  0); tw32(MAC_RCV_VALUE_13,  0);
6655         case 13:
6656                 tw32(MAC_RCV_RULE_12,  0); tw32(MAC_RCV_VALUE_12,  0);
6657         case 12:
6658                 tw32(MAC_RCV_RULE_11,  0); tw32(MAC_RCV_VALUE_11,  0);
6659         case 11:
6660                 tw32(MAC_RCV_RULE_10,  0); tw32(MAC_RCV_VALUE_10,  0);
6661         case 10:
6662                 tw32(MAC_RCV_RULE_9,  0); tw32(MAC_RCV_VALUE_9,  0);
6663         case 9:
6664                 tw32(MAC_RCV_RULE_8,  0); tw32(MAC_RCV_VALUE_8,  0);
6665         case 8:
6666                 tw32(MAC_RCV_RULE_7,  0); tw32(MAC_RCV_VALUE_7,  0);
6667         case 7:
6668                 tw32(MAC_RCV_RULE_6,  0); tw32(MAC_RCV_VALUE_6,  0);
6669         case 6:
6670                 tw32(MAC_RCV_RULE_5,  0); tw32(MAC_RCV_VALUE_5,  0);
6671         case 5:
6672                 tw32(MAC_RCV_RULE_4,  0); tw32(MAC_RCV_VALUE_4,  0);
6673         case 4:
6674                 /* tw32(MAC_RCV_RULE_3,  0); tw32(MAC_RCV_VALUE_3,  0); */
6675         case 3:
6676                 /* tw32(MAC_RCV_RULE_2,  0); tw32(MAC_RCV_VALUE_2,  0); */
6677         case 2:
6678         case 1:
6679
6680         default:
6681                 break;
6682         };
6683
6684         tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
6685
6686         return 0;
6687 }
6688
6689 /* Called at device open time to get the chip ready for
6690  * packet processing.  Invoked with tp->lock held.
6691  */
6692 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
6693 {
6694         int err;
6695
6696         /* Force the chip into D0. */
6697         err = tg3_set_power_state(tp, PCI_D0);
6698         if (err)
6699                 goto out;
6700
6701         tg3_switch_clocks(tp);
6702
6703         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
6704
6705         err = tg3_reset_hw(tp, reset_phy);
6706
6707 out:
6708         return err;
6709 }
6710
6711 #define TG3_STAT_ADD32(PSTAT, REG) \
6712 do {    u32 __val = tr32(REG); \
6713         (PSTAT)->low += __val; \
6714         if ((PSTAT)->low < __val) \
6715                 (PSTAT)->high += 1; \
6716 } while (0)
6717
6718 static void tg3_periodic_fetch_stats(struct tg3 *tp)
6719 {
6720         struct tg3_hw_stats *sp = tp->hw_stats;
6721
6722         if (!netif_carrier_ok(tp->dev))
6723                 return;
6724
6725         TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
6726         TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
6727         TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
6728         TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
6729         TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
6730         TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
6731         TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
6732         TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
6733         TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
6734         TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
6735         TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
6736         TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
6737         TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
6738
6739         TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
6740         TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
6741         TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
6742         TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
6743         TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
6744         TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
6745         TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
6746         TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
6747         TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
6748         TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
6749         TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
6750         TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
6751         TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
6752         TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
6753
6754         TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
6755         TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
6756         TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
6757 }
6758
6759 static void tg3_timer(unsigned long __opaque)
6760 {
6761         struct tg3 *tp = (struct tg3 *) __opaque;
6762
6763         if (tp->irq_sync)
6764                 goto restart_timer;
6765
6766         spin_lock(&tp->lock);
6767
6768         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
6769                 /* All of this garbage is because when using non-tagged
6770                  * IRQ status the mailbox/status_block protocol the chip
6771                  * uses with the cpu is race prone.
6772                  */
6773                 if (tp->hw_status->status & SD_STATUS_UPDATED) {
6774                         tw32(GRC_LOCAL_CTRL,
6775                              tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
6776                 } else {
6777                         tw32(HOSTCC_MODE, tp->coalesce_mode |
6778                              (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
6779                 }
6780
6781                 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
6782                         tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
6783                         spin_unlock(&tp->lock);
6784                         schedule_work(&tp->reset_task);
6785                         return;
6786                 }
6787         }
6788
6789         /* This part only runs once per second. */
6790         if (!--tp->timer_counter) {
6791                 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6792                         tg3_periodic_fetch_stats(tp);
6793
6794                 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
6795                         u32 mac_stat;
6796                         int phy_event;
6797
6798                         mac_stat = tr32(MAC_STATUS);
6799
6800                         phy_event = 0;
6801                         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
6802                                 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
6803                                         phy_event = 1;
6804                         } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
6805                                 phy_event = 1;
6806
6807                         if (phy_event)
6808                                 tg3_setup_phy(tp, 0);
6809                 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
6810                         u32 mac_stat = tr32(MAC_STATUS);
6811                         int need_setup = 0;
6812
6813                         if (netif_carrier_ok(tp->dev) &&
6814                             (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
6815                                 need_setup = 1;
6816                         }
6817                         if (! netif_carrier_ok(tp->dev) &&
6818                             (mac_stat & (MAC_STATUS_PCS_SYNCED |
6819                                          MAC_STATUS_SIGNAL_DET))) {
6820                                 need_setup = 1;
6821                         }
6822                         if (need_setup) {
6823                                 if (!tp->serdes_counter) {
6824                                         tw32_f(MAC_MODE,
6825                                              (tp->mac_mode &
6826                                               ~MAC_MODE_PORT_MODE_MASK));
6827                                         udelay(40);
6828                                         tw32_f(MAC_MODE, tp->mac_mode);
6829                                         udelay(40);
6830                                 }
6831                                 tg3_setup_phy(tp, 0);
6832                         }
6833                 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
6834                         tg3_serdes_parallel_detect(tp);
6835
6836                 tp->timer_counter = tp->timer_multiplier;
6837         }
6838
6839         /* Heartbeat is only sent once every 2 seconds.
6840          *
6841          * The heartbeat is to tell the ASF firmware that the host
6842          * driver is still alive.  In the event that the OS crashes,
6843          * ASF needs to reset the hardware to free up the FIFO space
6844          * that may be filled with rx packets destined for the host.
6845          * If the FIFO is full, ASF will no longer function properly.
6846          *
6847          * Unintended resets have been reported on real time kernels
6848          * where the timer doesn't run on time.  Netpoll will also have
6849          * same problem.
6850          *
6851          * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
6852          * to check the ring condition when the heartbeat is expiring
6853          * before doing the reset.  This will prevent most unintended
6854          * resets.
6855          */
6856         if (!--tp->asf_counter) {
6857                 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6858                         u32 val;
6859
6860                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
6861                                       FWCMD_NICDRV_ALIVE3);
6862                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
6863                         /* 5 seconds timeout */
6864                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
6865                         val = tr32(GRC_RX_CPU_EVENT);
6866                         val |= (1 << 14);
6867                         tw32(GRC_RX_CPU_EVENT, val);
6868                 }
6869                 tp->asf_counter = tp->asf_multiplier;
6870         }
6871
6872         spin_unlock(&tp->lock);
6873
6874 restart_timer:
6875         tp->timer.expires = jiffies + tp->timer_offset;
6876         add_timer(&tp->timer);
6877 }
6878
6879 static int tg3_request_irq(struct tg3 *tp)
6880 {
6881         irq_handler_t fn;
6882         unsigned long flags;
6883         struct net_device *dev = tp->dev;
6884
6885         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6886                 fn = tg3_msi;
6887                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
6888                         fn = tg3_msi_1shot;
6889                 flags = IRQF_SAMPLE_RANDOM;
6890         } else {
6891                 fn = tg3_interrupt;
6892                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
6893                         fn = tg3_interrupt_tagged;
6894                 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
6895         }
6896         return (request_irq(tp->pdev->irq, fn, flags, dev->name, dev));
6897 }
6898
6899 static int tg3_test_interrupt(struct tg3 *tp)
6900 {
6901         struct net_device *dev = tp->dev;
6902         int err, i, intr_ok = 0;
6903
6904         if (!netif_running(dev))
6905                 return -ENODEV;
6906
6907         tg3_disable_ints(tp);
6908
6909         free_irq(tp->pdev->irq, dev);
6910
6911         err = request_irq(tp->pdev->irq, tg3_test_isr,
6912                           IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, dev);
6913         if (err)
6914                 return err;
6915
6916         tp->hw_status->status &= ~SD_STATUS_UPDATED;
6917         tg3_enable_ints(tp);
6918
6919         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
6920                HOSTCC_MODE_NOW);
6921
6922         for (i = 0; i < 5; i++) {
6923                 u32 int_mbox, misc_host_ctrl;
6924
6925                 int_mbox = tr32_mailbox(MAILBOX_INTERRUPT_0 +
6926                                         TG3_64BIT_REG_LOW);
6927                 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
6928
6929                 if ((int_mbox != 0) ||
6930                     (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
6931                         intr_ok = 1;
6932                         break;
6933                 }
6934
6935                 msleep(10);
6936         }
6937
6938         tg3_disable_ints(tp);
6939
6940         free_irq(tp->pdev->irq, dev);
6941
6942         err = tg3_request_irq(tp);
6943
6944         if (err)
6945                 return err;
6946
6947         if (intr_ok)
6948                 return 0;
6949
6950         return -EIO;
6951 }
6952
6953 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
6954  * successfully restored
6955  */
6956 static int tg3_test_msi(struct tg3 *tp)
6957 {
6958         struct net_device *dev = tp->dev;
6959         int err;
6960         u16 pci_cmd;
6961
6962         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
6963                 return 0;
6964
6965         /* Turn off SERR reporting in case MSI terminates with Master
6966          * Abort.
6967          */
6968         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
6969         pci_write_config_word(tp->pdev, PCI_COMMAND,
6970                               pci_cmd & ~PCI_COMMAND_SERR);
6971
6972         err = tg3_test_interrupt(tp);
6973
6974         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
6975
6976         if (!err)
6977                 return 0;
6978
6979         /* other failures */
6980         if (err != -EIO)
6981                 return err;
6982
6983         /* MSI test failed, go back to INTx mode */
6984         printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
6985                "switching to INTx mode. Please report this failure to "
6986                "the PCI maintainer and include system chipset information.\n",
6987                        tp->dev->name);
6988
6989         free_irq(tp->pdev->irq, dev);
6990         pci_disable_msi(tp->pdev);
6991
6992         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
6993
6994         err = tg3_request_irq(tp);
6995         if (err)
6996                 return err;
6997
6998         /* Need to reset the chip because the MSI cycle may have terminated
6999          * with Master Abort.
7000          */
7001         tg3_full_lock(tp, 1);
7002
7003         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7004         err = tg3_init_hw(tp, 1);
7005
7006         tg3_full_unlock(tp);
7007
7008         if (err)
7009                 free_irq(tp->pdev->irq, dev);
7010
7011         return err;
7012 }
7013
7014 static int tg3_open(struct net_device *dev)
7015 {
7016         struct tg3 *tp = netdev_priv(dev);
7017         int err;
7018
7019         netif_carrier_off(tp->dev);
7020
7021         tg3_full_lock(tp, 0);
7022
7023         err = tg3_set_power_state(tp, PCI_D0);
7024         if (err) {
7025                 tg3_full_unlock(tp);
7026                 return err;
7027         }
7028
7029         tg3_disable_ints(tp);
7030         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
7031
7032         tg3_full_unlock(tp);
7033
7034         /* The placement of this call is tied
7035          * to the setup and use of Host TX descriptors.
7036          */
7037         err = tg3_alloc_consistent(tp);
7038         if (err)
7039                 return err;
7040
7041         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
7042             (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5750_AX) &&
7043             (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5750_BX) &&
7044             !((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) &&
7045               (tp->pdev_peer == tp->pdev))) {
7046                 /* All MSI supporting chips should support tagged
7047                  * status.  Assert that this is the case.
7048                  */
7049                 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7050                         printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
7051                                "Not using MSI.\n", tp->dev->name);
7052                 } else if (pci_enable_msi(tp->pdev) == 0) {
7053                         u32 msi_mode;
7054
7055                         msi_mode = tr32(MSGINT_MODE);
7056                         tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
7057                         tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
7058                 }
7059         }
7060         err = tg3_request_irq(tp);
7061
7062         if (err) {
7063                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7064                         pci_disable_msi(tp->pdev);
7065                         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7066                 }
7067                 tg3_free_consistent(tp);
7068                 return err;
7069         }
7070
7071         tg3_full_lock(tp, 0);
7072
7073         err = tg3_init_hw(tp, 1);
7074         if (err) {
7075                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7076                 tg3_free_rings(tp);
7077         } else {
7078                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
7079                         tp->timer_offset = HZ;
7080                 else
7081                         tp->timer_offset = HZ / 10;
7082
7083                 BUG_ON(tp->timer_offset > HZ);
7084                 tp->timer_counter = tp->timer_multiplier =
7085                         (HZ / tp->timer_offset);
7086                 tp->asf_counter = tp->asf_multiplier =
7087                         ((HZ / tp->timer_offset) * 2);
7088
7089                 init_timer(&tp->timer);
7090                 tp->timer.expires = jiffies + tp->timer_offset;
7091                 tp->timer.data = (unsigned long) tp;
7092                 tp->timer.function = tg3_timer;
7093         }
7094
7095         tg3_full_unlock(tp);
7096
7097         if (err) {
7098                 free_irq(tp->pdev->irq, dev);
7099                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7100                         pci_disable_msi(tp->pdev);
7101                         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7102                 }
7103                 tg3_free_consistent(tp);
7104                 return err;
7105         }
7106
7107         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7108                 err = tg3_test_msi(tp);
7109
7110                 if (err) {
7111                         tg3_full_lock(tp, 0);
7112
7113                         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7114                                 pci_disable_msi(tp->pdev);
7115                                 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7116                         }
7117                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7118                         tg3_free_rings(tp);
7119                         tg3_free_consistent(tp);
7120
7121                         tg3_full_unlock(tp);
7122
7123                         return err;
7124                 }
7125
7126                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7127                         if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI) {
7128                                 u32 val = tr32(PCIE_TRANSACTION_CFG);
7129
7130                                 tw32(PCIE_TRANSACTION_CFG,
7131                                      val | PCIE_TRANS_CFG_1SHOT_MSI);
7132                         }
7133                 }
7134         }
7135
7136         tg3_full_lock(tp, 0);
7137
7138         add_timer(&tp->timer);
7139         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
7140         tg3_enable_ints(tp);
7141
7142         tg3_full_unlock(tp);
7143
7144         netif_start_queue(dev);
7145
7146         return 0;
7147 }
7148
7149 #if 0
7150 /*static*/ void tg3_dump_state(struct tg3 *tp)
7151 {
7152         u32 val32, val32_2, val32_3, val32_4, val32_5;
7153         u16 val16;
7154         int i;
7155
7156         pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
7157         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
7158         printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
7159                val16, val32);
7160
7161         /* MAC block */
7162         printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
7163                tr32(MAC_MODE), tr32(MAC_STATUS));
7164         printk("       MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
7165                tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
7166         printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
7167                tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
7168         printk("       MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
7169                tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
7170
7171         /* Send data initiator control block */
7172         printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
7173                tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
7174         printk("       SNDDATAI_STATSCTRL[%08x]\n",
7175                tr32(SNDDATAI_STATSCTRL));
7176
7177         /* Send data completion control block */
7178         printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
7179
7180         /* Send BD ring selector block */
7181         printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
7182                tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
7183
7184         /* Send BD initiator control block */
7185         printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
7186                tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
7187
7188         /* Send BD completion control block */
7189         printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
7190
7191         /* Receive list placement control block */
7192         printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
7193                tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
7194         printk("       RCVLPC_STATSCTRL[%08x]\n",
7195                tr32(RCVLPC_STATSCTRL));
7196
7197         /* Receive data and receive BD initiator control block */
7198         printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
7199                tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
7200
7201         /* Receive data completion control block */
7202         printk("DEBUG: RCVDCC_MODE[%08x]\n",
7203                tr32(RCVDCC_MODE));
7204
7205         /* Receive BD initiator control block */
7206         printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
7207                tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
7208
7209         /* Receive BD completion control block */
7210         printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
7211                tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
7212
7213         /* Receive list selector control block */
7214         printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
7215                tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
7216
7217         /* Mbuf cluster free block */
7218         printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
7219                tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
7220
7221         /* Host coalescing control block */
7222         printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
7223                tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
7224         printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
7225                tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
7226                tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
7227         printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
7228                tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
7229                tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
7230         printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
7231                tr32(HOSTCC_STATS_BLK_NIC_ADDR));
7232         printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
7233                tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
7234
7235         /* Memory arbiter control block */
7236         printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
7237                tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
7238
7239         /* Buffer manager control block */
7240         printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
7241                tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
7242         printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
7243                tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
7244         printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
7245                "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
7246                tr32(BUFMGR_DMA_DESC_POOL_ADDR),
7247                tr32(BUFMGR_DMA_DESC_POOL_SIZE));
7248
7249         /* Read DMA control block */
7250         printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
7251                tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
7252
7253         /* Write DMA control block */
7254         printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
7255                tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
7256
7257         /* DMA completion block */
7258         printk("DEBUG: DMAC_MODE[%08x]\n",
7259                tr32(DMAC_MODE));
7260
7261         /* GRC block */
7262         printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
7263                tr32(GRC_MODE), tr32(GRC_MISC_CFG));
7264         printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
7265                tr32(GRC_LOCAL_CTRL));
7266
7267         /* TG3_BDINFOs */
7268         printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
7269                tr32(RCVDBDI_JUMBO_BD + 0x0),
7270                tr32(RCVDBDI_JUMBO_BD + 0x4),
7271                tr32(RCVDBDI_JUMBO_BD + 0x8),
7272                tr32(RCVDBDI_JUMBO_BD + 0xc));
7273         printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
7274                tr32(RCVDBDI_STD_BD + 0x0),
7275                tr32(RCVDBDI_STD_BD + 0x4),
7276                tr32(RCVDBDI_STD_BD + 0x8),
7277                tr32(RCVDBDI_STD_BD + 0xc));
7278         printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
7279                tr32(RCVDBDI_MINI_BD + 0x0),
7280                tr32(RCVDBDI_MINI_BD + 0x4),
7281                tr32(RCVDBDI_MINI_BD + 0x8),
7282                tr32(RCVDBDI_MINI_BD + 0xc));
7283
7284         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
7285         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
7286         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
7287         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
7288         printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
7289                val32, val32_2, val32_3, val32_4);
7290
7291         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
7292         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
7293         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
7294         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
7295         printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
7296                val32, val32_2, val32_3, val32_4);
7297
7298         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
7299         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
7300         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
7301         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
7302         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
7303         printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
7304                val32, val32_2, val32_3, val32_4, val32_5);
7305
7306         /* SW status block */
7307         printk("DEBUG: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
7308                tp->hw_status->status,
7309                tp->hw_status->status_tag,
7310                tp->hw_status->rx_jumbo_consumer,
7311                tp->hw_status->rx_consumer,
7312                tp->hw_status->rx_mini_consumer,
7313                tp->hw_status->idx[0].rx_producer,
7314                tp->hw_status->idx[0].tx_consumer);
7315
7316         /* SW statistics block */
7317         printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
7318                ((u32 *)tp->hw_stats)[0],
7319                ((u32 *)tp->hw_stats)[1],
7320                ((u32 *)tp->hw_stats)[2],
7321                ((u32 *)tp->hw_stats)[3]);
7322
7323         /* Mailboxes */
7324         printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
7325                tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
7326                tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
7327                tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
7328                tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
7329
7330         /* NIC side send descriptors. */
7331         for (i = 0; i < 6; i++) {
7332                 unsigned long txd;
7333
7334                 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
7335                         + (i * sizeof(struct tg3_tx_buffer_desc));
7336                 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
7337                        i,
7338                        readl(txd + 0x0), readl(txd + 0x4),
7339                        readl(txd + 0x8), readl(txd + 0xc));
7340         }
7341
7342         /* NIC side RX descriptors. */
7343         for (i = 0; i < 6; i++) {
7344                 unsigned long rxd;
7345
7346                 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
7347                         + (i * sizeof(struct tg3_rx_buffer_desc));
7348                 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
7349                        i,
7350                        readl(rxd + 0x0), readl(rxd + 0x4),
7351                        readl(rxd + 0x8), readl(rxd + 0xc));
7352                 rxd += (4 * sizeof(u32));
7353                 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
7354                        i,
7355                        readl(rxd + 0x0), readl(rxd + 0x4),
7356                        readl(rxd + 0x8), readl(rxd + 0xc));
7357         }
7358
7359         for (i = 0; i < 6; i++) {
7360                 unsigned long rxd;
7361
7362                 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
7363                         + (i * sizeof(struct tg3_rx_buffer_desc));
7364                 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
7365                        i,
7366                        readl(rxd + 0x0), readl(rxd + 0x4),
7367                        readl(rxd + 0x8), readl(rxd + 0xc));
7368                 rxd += (4 * sizeof(u32));
7369                 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
7370                        i,
7371                        readl(rxd + 0x0), readl(rxd + 0x4),
7372                        readl(rxd + 0x8), readl(rxd + 0xc));
7373         }
7374 }
7375 #endif
7376
7377 static struct net_device_stats *tg3_get_stats(struct net_device *);
7378 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
7379
7380 static int tg3_close(struct net_device *dev)
7381 {
7382         struct tg3 *tp = netdev_priv(dev);
7383
7384         /* Calling flush_scheduled_work() may deadlock because
7385          * linkwatch_event() may be on the workqueue and it will try to get
7386          * the rtnl_lock which we are holding.
7387          */
7388         while (tp->tg3_flags & TG3_FLAG_IN_RESET_TASK)
7389                 msleep(1);
7390
7391         netif_stop_queue(dev);
7392
7393         del_timer_sync(&tp->timer);
7394
7395         tg3_full_lock(tp, 1);
7396 #if 0
7397         tg3_dump_state(tp);
7398 #endif
7399
7400         tg3_disable_ints(tp);
7401
7402         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7403         tg3_free_rings(tp);
7404         tp->tg3_flags &=
7405                 ~(TG3_FLAG_INIT_COMPLETE |
7406                   TG3_FLAG_GOT_SERDES_FLOWCTL);
7407
7408         tg3_full_unlock(tp);
7409
7410         free_irq(tp->pdev->irq, dev);
7411         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7412                 pci_disable_msi(tp->pdev);
7413                 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7414         }
7415
7416         memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
7417                sizeof(tp->net_stats_prev));
7418         memcpy(&tp->estats_prev, tg3_get_estats(tp),
7419                sizeof(tp->estats_prev));
7420
7421         tg3_free_consistent(tp);
7422
7423         tg3_set_power_state(tp, PCI_D3hot);
7424
7425         netif_carrier_off(tp->dev);
7426
7427         return 0;
7428 }
7429
7430 static inline unsigned long get_stat64(tg3_stat64_t *val)
7431 {
7432         unsigned long ret;
7433
7434 #if (BITS_PER_LONG == 32)
7435         ret = val->low;
7436 #else
7437         ret = ((u64)val->high << 32) | ((u64)val->low);
7438 #endif
7439         return ret;
7440 }
7441
7442 static unsigned long calc_crc_errors(struct tg3 *tp)
7443 {
7444         struct tg3_hw_stats *hw_stats = tp->hw_stats;
7445
7446         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7447             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
7448              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
7449                 u32 val;
7450
7451                 spin_lock_bh(&tp->lock);
7452                 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
7453                         tg3_writephy(tp, MII_TG3_TEST1,
7454                                      val | MII_TG3_TEST1_CRC_EN);
7455                         tg3_readphy(tp, 0x14, &val);
7456                 } else
7457                         val = 0;
7458                 spin_unlock_bh(&tp->lock);
7459
7460                 tp->phy_crc_errors += val;
7461
7462                 return tp->phy_crc_errors;
7463         }
7464
7465         return get_stat64(&hw_stats->rx_fcs_errors);
7466 }
7467
7468 #define ESTAT_ADD(member) \
7469         estats->member =        old_estats->member + \
7470                                 get_stat64(&hw_stats->member)
7471
7472 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
7473 {
7474         struct tg3_ethtool_stats *estats = &tp->estats;
7475         struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
7476         struct tg3_hw_stats *hw_stats = tp->hw_stats;
7477
7478         if (!hw_stats)
7479                 return old_estats;
7480
7481         ESTAT_ADD(rx_octets);
7482         ESTAT_ADD(rx_fragments);
7483         ESTAT_ADD(rx_ucast_packets);
7484         ESTAT_ADD(rx_mcast_packets);
7485         ESTAT_ADD(rx_bcast_packets);
7486         ESTAT_ADD(rx_fcs_errors);
7487         ESTAT_ADD(rx_align_errors);
7488         ESTAT_ADD(rx_xon_pause_rcvd);
7489         ESTAT_ADD(rx_xoff_pause_rcvd);
7490         ESTAT_ADD(rx_mac_ctrl_rcvd);
7491         ESTAT_ADD(rx_xoff_entered);
7492         ESTAT_ADD(rx_frame_too_long_errors);
7493         ESTAT_ADD(rx_jabbers);
7494         ESTAT_ADD(rx_undersize_packets);
7495         ESTAT_ADD(rx_in_length_errors);
7496         ESTAT_ADD(rx_out_length_errors);
7497         ESTAT_ADD(rx_64_or_less_octet_packets);
7498         ESTAT_ADD(rx_65_to_127_octet_packets);
7499         ESTAT_ADD(rx_128_to_255_octet_packets);
7500         ESTAT_ADD(rx_256_to_511_octet_packets);
7501         ESTAT_ADD(rx_512_to_1023_octet_packets);
7502         ESTAT_ADD(rx_1024_to_1522_octet_packets);
7503         ESTAT_ADD(rx_1523_to_2047_octet_packets);
7504         ESTAT_ADD(rx_2048_to_4095_octet_packets);
7505         ESTAT_ADD(rx_4096_to_8191_octet_packets);
7506         ESTAT_ADD(rx_8192_to_9022_octet_packets);
7507
7508         ESTAT_ADD(tx_octets);
7509         ESTAT_ADD(tx_collisions);
7510         ESTAT_ADD(tx_xon_sent);
7511         ESTAT_ADD(tx_xoff_sent);
7512         ESTAT_ADD(tx_flow_control);
7513         ESTAT_ADD(tx_mac_errors);
7514         ESTAT_ADD(tx_single_collisions);
7515         ESTAT_ADD(tx_mult_collisions);
7516         ESTAT_ADD(tx_deferred);
7517         ESTAT_ADD(tx_excessive_collisions);
7518         ESTAT_ADD(tx_late_collisions);
7519         ESTAT_ADD(tx_collide_2times);
7520         ESTAT_ADD(tx_collide_3times);
7521         ESTAT_ADD(tx_collide_4times);
7522         ESTAT_ADD(tx_collide_5times);
7523         ESTAT_ADD(tx_collide_6times);
7524         ESTAT_ADD(tx_collide_7times);
7525         ESTAT_ADD(tx_collide_8times);
7526         ESTAT_ADD(tx_collide_9times);
7527         ESTAT_ADD(tx_collide_10times);
7528         ESTAT_ADD(tx_collide_11times);
7529         ESTAT_ADD(tx_collide_12times);
7530         ESTAT_ADD(tx_collide_13times);
7531         ESTAT_ADD(tx_collide_14times);
7532         ESTAT_ADD(tx_collide_15times);
7533         ESTAT_ADD(tx_ucast_packets);
7534         ESTAT_ADD(tx_mcast_packets);
7535         ESTAT_ADD(tx_bcast_packets);
7536         ESTAT_ADD(tx_carrier_sense_errors);
7537         ESTAT_ADD(tx_discards);
7538         ESTAT_ADD(tx_errors);
7539
7540         ESTAT_ADD(dma_writeq_full);
7541         ESTAT_ADD(dma_write_prioq_full);
7542         ESTAT_ADD(rxbds_empty);
7543         ESTAT_ADD(rx_discards);
7544         ESTAT_ADD(rx_errors);
7545         ESTAT_ADD(rx_threshold_hit);
7546
7547         ESTAT_ADD(dma_readq_full);
7548         ESTAT_ADD(dma_read_prioq_full);
7549         ESTAT_ADD(tx_comp_queue_full);
7550
7551         ESTAT_ADD(ring_set_send_prod_index);
7552         ESTAT_ADD(ring_status_update);
7553         ESTAT_ADD(nic_irqs);
7554         ESTAT_ADD(nic_avoided_irqs);
7555         ESTAT_ADD(nic_tx_threshold_hit);
7556
7557         return estats;
7558 }
7559
7560 static struct net_device_stats *tg3_get_stats(struct net_device *dev)
7561 {
7562         struct tg3 *tp = netdev_priv(dev);
7563         struct net_device_stats *stats = &tp->net_stats;
7564         struct net_device_stats *old_stats = &tp->net_stats_prev;
7565         struct tg3_hw_stats *hw_stats = tp->hw_stats;
7566
7567         if (!hw_stats)
7568                 return old_stats;
7569
7570         stats->rx_packets = old_stats->rx_packets +
7571                 get_stat64(&hw_stats->rx_ucast_packets) +
7572                 get_stat64(&hw_stats->rx_mcast_packets) +
7573                 get_stat64(&hw_stats->rx_bcast_packets);
7574
7575         stats->tx_packets = old_stats->tx_packets +
7576                 get_stat64(&hw_stats->tx_ucast_packets) +
7577                 get_stat64(&hw_stats->tx_mcast_packets) +
7578                 get_stat64(&hw_stats->tx_bcast_packets);
7579
7580         stats->rx_bytes = old_stats->rx_bytes +
7581                 get_stat64(&hw_stats->rx_octets);
7582         stats->tx_bytes = old_stats->tx_bytes +
7583                 get_stat64(&hw_stats->tx_octets);
7584
7585         stats->rx_errors = old_stats->rx_errors +
7586                 get_stat64(&hw_stats->rx_errors);
7587         stats->tx_errors = old_stats->tx_errors +
7588                 get_stat64(&hw_stats->tx_errors) +
7589                 get_stat64(&hw_stats->tx_mac_errors) +
7590                 get_stat64(&hw_stats->tx_carrier_sense_errors) +
7591                 get_stat64(&hw_stats->tx_discards);
7592
7593         stats->multicast = old_stats->multicast +
7594                 get_stat64(&hw_stats->rx_mcast_packets);
7595         stats->collisions = old_stats->collisions +
7596                 get_stat64(&hw_stats->tx_collisions);
7597
7598         stats->rx_length_errors = old_stats->rx_length_errors +
7599                 get_stat64(&hw_stats->rx_frame_too_long_errors) +
7600                 get_stat64(&hw_stats->rx_undersize_packets);
7601
7602         stats->rx_over_errors = old_stats->rx_over_errors +
7603                 get_stat64(&hw_stats->rxbds_empty);
7604         stats->rx_frame_errors = old_stats->rx_frame_errors +
7605                 get_stat64(&hw_stats->rx_align_errors);
7606         stats->tx_aborted_errors = old_stats->tx_aborted_errors +
7607                 get_stat64(&hw_stats->tx_discards);
7608         stats->tx_carrier_errors = old_stats->tx_carrier_errors +
7609                 get_stat64(&hw_stats->tx_carrier_sense_errors);
7610
7611         stats->rx_crc_errors = old_stats->rx_crc_errors +
7612                 calc_crc_errors(tp);
7613
7614         stats->rx_missed_errors = old_stats->rx_missed_errors +
7615                 get_stat64(&hw_stats->rx_discards);
7616
7617         return stats;
7618 }
7619
7620 static inline u32 calc_crc(unsigned char *buf, int len)
7621 {
7622         u32 reg;
7623         u32 tmp;
7624         int j, k;
7625
7626         reg = 0xffffffff;
7627
7628         for (j = 0; j < len; j++) {
7629                 reg ^= buf[j];
7630
7631                 for (k = 0; k < 8; k++) {
7632                         tmp = reg & 0x01;
7633
7634                         reg >>= 1;
7635
7636                         if (tmp) {
7637                                 reg ^= 0xedb88320;
7638                         }
7639                 }
7640         }
7641
7642         return ~reg;
7643 }
7644
7645 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
7646 {
7647         /* accept or reject all multicast frames */
7648         tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
7649         tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
7650         tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
7651         tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
7652 }
7653
7654 static void __tg3_set_rx_mode(struct net_device *dev)
7655 {
7656         struct tg3 *tp = netdev_priv(dev);
7657         u32 rx_mode;
7658
7659         rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
7660                                   RX_MODE_KEEP_VLAN_TAG);
7661
7662         /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
7663          * flag clear.
7664          */
7665 #if TG3_VLAN_TAG_USED
7666         if (!tp->vlgrp &&
7667             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
7668                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
7669 #else
7670         /* By definition, VLAN is disabled always in this
7671          * case.
7672          */
7673         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
7674                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
7675 #endif
7676
7677         if (dev->flags & IFF_PROMISC) {
7678                 /* Promiscuous mode. */
7679                 rx_mode |= RX_MODE_PROMISC;
7680         } else if (dev->flags & IFF_ALLMULTI) {
7681                 /* Accept all multicast. */
7682                 tg3_set_multi (tp, 1);
7683         } else if (dev->mc_count < 1) {
7684                 /* Reject all multicast. */
7685                 tg3_set_multi (tp, 0);
7686         } else {
7687                 /* Accept one or more multicast(s). */
7688                 struct dev_mc_list *mclist;
7689                 unsigned int i;
7690                 u32 mc_filter[4] = { 0, };
7691                 u32 regidx;
7692                 u32 bit;
7693                 u32 crc;
7694
7695                 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
7696                      i++, mclist = mclist->next) {
7697
7698                         crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
7699                         bit = ~crc & 0x7f;
7700                         regidx = (bit & 0x60) >> 5;
7701                         bit &= 0x1f;
7702                         mc_filter[regidx] |= (1 << bit);
7703                 }
7704
7705                 tw32(MAC_HASH_REG_0, mc_filter[0]);
7706                 tw32(MAC_HASH_REG_1, mc_filter[1]);
7707                 tw32(MAC_HASH_REG_2, mc_filter[2]);
7708                 tw32(MAC_HASH_REG_3, mc_filter[3]);
7709         }
7710
7711         if (rx_mode != tp->rx_mode) {
7712                 tp->rx_mode = rx_mode;
7713                 tw32_f(MAC_RX_MODE, rx_mode);
7714                 udelay(10);
7715         }
7716 }
7717
7718 static void tg3_set_rx_mode(struct net_device *dev)
7719 {
7720         struct tg3 *tp = netdev_priv(dev);
7721
7722         if (!netif_running(dev))
7723                 return;
7724
7725         tg3_full_lock(tp, 0);
7726         __tg3_set_rx_mode(dev);
7727         tg3_full_unlock(tp);
7728 }
7729
7730 #define TG3_REGDUMP_LEN         (32 * 1024)
7731
7732 static int tg3_get_regs_len(struct net_device *dev)
7733 {
7734         return TG3_REGDUMP_LEN;
7735 }
7736
7737 static void tg3_get_regs(struct net_device *dev,
7738                 struct ethtool_regs *regs, void *_p)
7739 {
7740         u32 *p = _p;
7741         struct tg3 *tp = netdev_priv(dev);
7742         u8 *orig_p = _p;
7743         int i;
7744
7745         regs->version = 0;
7746
7747         memset(p, 0, TG3_REGDUMP_LEN);
7748
7749         if (tp->link_config.phy_is_low_power)
7750                 return;
7751
7752         tg3_full_lock(tp, 0);
7753
7754 #define __GET_REG32(reg)        (*(p)++ = tr32(reg))
7755 #define GET_REG32_LOOP(base,len)                \
7756 do {    p = (u32 *)(orig_p + (base));           \
7757         for (i = 0; i < len; i += 4)            \
7758                 __GET_REG32((base) + i);        \
7759 } while (0)
7760 #define GET_REG32_1(reg)                        \
7761 do {    p = (u32 *)(orig_p + (reg));            \
7762         __GET_REG32((reg));                     \
7763 } while (0)
7764
7765         GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
7766         GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
7767         GET_REG32_LOOP(MAC_MODE, 0x4f0);
7768         GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
7769         GET_REG32_1(SNDDATAC_MODE);
7770         GET_REG32_LOOP(SNDBDS_MODE, 0x80);
7771         GET_REG32_LOOP(SNDBDI_MODE, 0x48);
7772         GET_REG32_1(SNDBDC_MODE);
7773         GET_REG32_LOOP(RCVLPC_MODE, 0x20);
7774         GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
7775         GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
7776         GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
7777         GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
7778         GET_REG32_1(RCVDCC_MODE);
7779         GET_REG32_LOOP(RCVBDI_MODE, 0x20);
7780         GET_REG32_LOOP(RCVCC_MODE, 0x14);
7781         GET_REG32_LOOP(RCVLSC_MODE, 0x08);
7782         GET_REG32_1(MBFREE_MODE);
7783         GET_REG32_LOOP(HOSTCC_MODE, 0x100);
7784         GET_REG32_LOOP(MEMARB_MODE, 0x10);
7785         GET_REG32_LOOP(BUFMGR_MODE, 0x58);
7786         GET_REG32_LOOP(RDMAC_MODE, 0x08);
7787         GET_REG32_LOOP(WDMAC_MODE, 0x08);
7788         GET_REG32_1(RX_CPU_MODE);
7789         GET_REG32_1(RX_CPU_STATE);
7790         GET_REG32_1(RX_CPU_PGMCTR);
7791         GET_REG32_1(RX_CPU_HWBKPT);
7792         GET_REG32_1(TX_CPU_MODE);
7793         GET_REG32_1(TX_CPU_STATE);
7794         GET_REG32_1(TX_CPU_PGMCTR);
7795         GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
7796         GET_REG32_LOOP(FTQ_RESET, 0x120);
7797         GET_REG32_LOOP(MSGINT_MODE, 0x0c);
7798         GET_REG32_1(DMAC_MODE);
7799         GET_REG32_LOOP(GRC_MODE, 0x4c);
7800         if (tp->tg3_flags & TG3_FLAG_NVRAM)
7801                 GET_REG32_LOOP(NVRAM_CMD, 0x24);
7802
7803 #undef __GET_REG32
7804 #undef GET_REG32_LOOP
7805 #undef GET_REG32_1
7806
7807         tg3_full_unlock(tp);
7808 }
7809
7810 static int tg3_get_eeprom_len(struct net_device *dev)
7811 {
7812         struct tg3 *tp = netdev_priv(dev);
7813
7814         return tp->nvram_size;
7815 }
7816
7817 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val);
7818 static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val);
7819
7820 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
7821 {
7822         struct tg3 *tp = netdev_priv(dev);
7823         int ret;
7824         u8  *pd;
7825         u32 i, offset, len, val, b_offset, b_count;
7826
7827         if (tp->link_config.phy_is_low_power)
7828                 return -EAGAIN;
7829
7830         offset = eeprom->offset;
7831         len = eeprom->len;
7832         eeprom->len = 0;
7833
7834         eeprom->magic = TG3_EEPROM_MAGIC;
7835
7836         if (offset & 3) {
7837                 /* adjustments to start on required 4 byte boundary */
7838                 b_offset = offset & 3;
7839                 b_count = 4 - b_offset;
7840                 if (b_count > len) {
7841                         /* i.e. offset=1 len=2 */
7842                         b_count = len;
7843                 }
7844                 ret = tg3_nvram_read(tp, offset-b_offset, &val);
7845                 if (ret)
7846                         return ret;
7847                 val = cpu_to_le32(val);
7848                 memcpy(data, ((char*)&val) + b_offset, b_count);
7849                 len -= b_count;
7850                 offset += b_count;
7851                 eeprom->len += b_count;
7852         }
7853
7854         /* read bytes upto the last 4 byte boundary */
7855         pd = &data[eeprom->len];
7856         for (i = 0; i < (len - (len & 3)); i += 4) {
7857                 ret = tg3_nvram_read(tp, offset + i, &val);
7858                 if (ret) {
7859                         eeprom->len += i;
7860                         return ret;
7861                 }
7862                 val = cpu_to_le32(val);
7863                 memcpy(pd + i, &val, 4);
7864         }
7865         eeprom->len += i;
7866
7867         if (len & 3) {
7868                 /* read last bytes not ending on 4 byte boundary */
7869                 pd = &data[eeprom->len];
7870                 b_count = len & 3;
7871                 b_offset = offset + len - b_count;
7872                 ret = tg3_nvram_read(tp, b_offset, &val);
7873                 if (ret)
7874                         return ret;
7875                 val = cpu_to_le32(val);
7876                 memcpy(pd, ((char*)&val), b_count);
7877                 eeprom->len += b_count;
7878         }
7879         return 0;
7880 }
7881
7882 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
7883
7884 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
7885 {
7886         struct tg3 *tp = netdev_priv(dev);
7887         int ret;
7888         u32 offset, len, b_offset, odd_len, start, end;
7889         u8 *buf;
7890
7891         if (tp->link_config.phy_is_low_power)
7892                 return -EAGAIN;
7893
7894         if (eeprom->magic != TG3_EEPROM_MAGIC)
7895                 return -EINVAL;
7896
7897         offset = eeprom->offset;
7898         len = eeprom->len;
7899
7900         if ((b_offset = (offset & 3))) {
7901                 /* adjustments to start on required 4 byte boundary */
7902                 ret = tg3_nvram_read(tp, offset-b_offset, &start);
7903                 if (ret)
7904                         return ret;
7905                 start = cpu_to_le32(start);
7906                 len += b_offset;
7907                 offset &= ~3;
7908                 if (len < 4)
7909                         len = 4;
7910         }
7911
7912         odd_len = 0;
7913         if (len & 3) {
7914                 /* adjustments to end on required 4 byte boundary */
7915                 odd_len = 1;
7916                 len = (len + 3) & ~3;
7917                 ret = tg3_nvram_read(tp, offset+len-4, &end);
7918                 if (ret)
7919                         return ret;
7920                 end = cpu_to_le32(end);
7921         }
7922
7923         buf = data;
7924         if (b_offset || odd_len) {
7925                 buf = kmalloc(len, GFP_KERNEL);
7926                 if (buf == 0)
7927                         return -ENOMEM;
7928                 if (b_offset)
7929                         memcpy(buf, &start, 4);
7930                 if (odd_len)
7931                         memcpy(buf+len-4, &end, 4);
7932                 memcpy(buf + b_offset, data, eeprom->len);
7933         }
7934
7935         ret = tg3_nvram_write_block(tp, offset, len, buf);
7936
7937         if (buf != data)
7938                 kfree(buf);
7939
7940         return ret;
7941 }
7942
7943 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
7944 {
7945         struct tg3 *tp = netdev_priv(dev);
7946
7947         cmd->supported = (SUPPORTED_Autoneg);
7948
7949         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
7950                 cmd->supported |= (SUPPORTED_1000baseT_Half |
7951                                    SUPPORTED_1000baseT_Full);
7952
7953         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
7954                 cmd->supported |= (SUPPORTED_100baseT_Half |
7955                                   SUPPORTED_100baseT_Full |
7956                                   SUPPORTED_10baseT_Half |
7957                                   SUPPORTED_10baseT_Full |
7958                                   SUPPORTED_MII);
7959                 cmd->port = PORT_TP;
7960         } else {
7961                 cmd->supported |= SUPPORTED_FIBRE;
7962                 cmd->port = PORT_FIBRE;
7963         }
7964
7965         cmd->advertising = tp->link_config.advertising;
7966         if (netif_running(dev)) {
7967                 cmd->speed = tp->link_config.active_speed;
7968                 cmd->duplex = tp->link_config.active_duplex;
7969         }
7970         cmd->phy_address = PHY_ADDR;
7971         cmd->transceiver = 0;
7972         cmd->autoneg = tp->link_config.autoneg;
7973         cmd->maxtxpkt = 0;
7974         cmd->maxrxpkt = 0;
7975         return 0;
7976 }
7977
7978 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
7979 {
7980         struct tg3 *tp = netdev_priv(dev);
7981
7982         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
7983                 /* These are the only valid advertisement bits allowed.  */
7984                 if (cmd->autoneg == AUTONEG_ENABLE &&
7985                     (cmd->advertising & ~(ADVERTISED_1000baseT_Half |
7986                                           ADVERTISED_1000baseT_Full |
7987                                           ADVERTISED_Autoneg |
7988                                           ADVERTISED_FIBRE)))
7989                         return -EINVAL;
7990                 /* Fiber can only do SPEED_1000.  */
7991                 else if ((cmd->autoneg != AUTONEG_ENABLE) &&
7992                          (cmd->speed != SPEED_1000))
7993                         return -EINVAL;
7994         /* Copper cannot force SPEED_1000.  */
7995         } else if ((cmd->autoneg != AUTONEG_ENABLE) &&
7996                    (cmd->speed == SPEED_1000))
7997                 return -EINVAL;
7998         else if ((cmd->speed == SPEED_1000) &&
7999                  (tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
8000                 return -EINVAL;
8001
8002         tg3_full_lock(tp, 0);
8003
8004         tp->link_config.autoneg = cmd->autoneg;
8005         if (cmd->autoneg == AUTONEG_ENABLE) {
8006                 tp->link_config.advertising = cmd->advertising;
8007                 tp->link_config.speed = SPEED_INVALID;
8008                 tp->link_config.duplex = DUPLEX_INVALID;
8009         } else {
8010                 tp->link_config.advertising = 0;
8011                 tp->link_config.speed = cmd->speed;
8012                 tp->link_config.duplex = cmd->duplex;
8013         }
8014
8015         tp->link_config.orig_speed = tp->link_config.speed;
8016         tp->link_config.orig_duplex = tp->link_config.duplex;
8017         tp->link_config.orig_autoneg = tp->link_config.autoneg;
8018
8019         if (netif_running(dev))
8020                 tg3_setup_phy(tp, 1);
8021
8022         tg3_full_unlock(tp);
8023
8024         return 0;
8025 }
8026
8027 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
8028 {
8029         struct tg3 *tp = netdev_priv(dev);
8030
8031         strcpy(info->driver, DRV_MODULE_NAME);
8032         strcpy(info->version, DRV_MODULE_VERSION);
8033         strcpy(info->fw_version, tp->fw_ver);
8034         strcpy(info->bus_info, pci_name(tp->pdev));
8035 }
8036
8037 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8038 {
8039         struct tg3 *tp = netdev_priv(dev);
8040
8041         wol->supported = WAKE_MAGIC;
8042         wol->wolopts = 0;
8043         if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)
8044                 wol->wolopts = WAKE_MAGIC;
8045         memset(&wol->sopass, 0, sizeof(wol->sopass));
8046 }
8047
8048 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8049 {
8050         struct tg3 *tp = netdev_priv(dev);
8051
8052         if (wol->wolopts & ~WAKE_MAGIC)
8053                 return -EINVAL;
8054         if ((wol->wolopts & WAKE_MAGIC) &&
8055             tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
8056             !(tp->tg3_flags & TG3_FLAG_SERDES_WOL_CAP))
8057                 return -EINVAL;
8058
8059         spin_lock_bh(&tp->lock);
8060         if (wol->wolopts & WAKE_MAGIC)
8061                 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
8062         else
8063                 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
8064         spin_unlock_bh(&tp->lock);
8065
8066         return 0;
8067 }
8068
8069 static u32 tg3_get_msglevel(struct net_device *dev)
8070 {
8071         struct tg3 *tp = netdev_priv(dev);
8072         return tp->msg_enable;
8073 }
8074
8075 static void tg3_set_msglevel(struct net_device *dev, u32 value)
8076 {
8077         struct tg3 *tp = netdev_priv(dev);
8078         tp->msg_enable = value;
8079 }
8080
8081 static int tg3_set_tso(struct net_device *dev, u32 value)
8082 {
8083         struct tg3 *tp = netdev_priv(dev);
8084
8085         if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8086                 if (value)
8087                         return -EINVAL;
8088                 return 0;
8089         }
8090         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) &&
8091             (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)) {
8092                 if (value)
8093                         dev->features |= NETIF_F_TSO6;
8094                 else
8095                         dev->features &= ~NETIF_F_TSO6;
8096         }
8097         return ethtool_op_set_tso(dev, value);
8098 }
8099
8100 static int tg3_nway_reset(struct net_device *dev)
8101 {
8102         struct tg3 *tp = netdev_priv(dev);
8103         u32 bmcr;
8104         int r;
8105
8106         if (!netif_running(dev))
8107                 return -EAGAIN;
8108
8109         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
8110                 return -EINVAL;
8111
8112         spin_lock_bh(&tp->lock);
8113         r = -EINVAL;
8114         tg3_readphy(tp, MII_BMCR, &bmcr);
8115         if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
8116             ((bmcr & BMCR_ANENABLE) ||
8117              (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
8118                 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
8119                                            BMCR_ANENABLE);
8120                 r = 0;
8121         }
8122         spin_unlock_bh(&tp->lock);
8123
8124         return r;
8125 }
8126
8127 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
8128 {
8129         struct tg3 *tp = netdev_priv(dev);
8130
8131         ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
8132         ering->rx_mini_max_pending = 0;
8133         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
8134                 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
8135         else
8136                 ering->rx_jumbo_max_pending = 0;
8137
8138         ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
8139
8140         ering->rx_pending = tp->rx_pending;
8141         ering->rx_mini_pending = 0;
8142         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
8143                 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
8144         else
8145                 ering->rx_jumbo_pending = 0;
8146
8147         ering->tx_pending = tp->tx_pending;
8148 }
8149
8150 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
8151 {
8152         struct tg3 *tp = netdev_priv(dev);
8153         int irq_sync = 0, err = 0;
8154
8155         if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
8156             (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
8157             (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
8158             (ering->tx_pending <= MAX_SKB_FRAGS) ||
8159             ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
8160              (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
8161                 return -EINVAL;
8162
8163         if (netif_running(dev)) {
8164                 tg3_netif_stop(tp);
8165                 irq_sync = 1;
8166         }
8167
8168         tg3_full_lock(tp, irq_sync);
8169
8170         tp->rx_pending = ering->rx_pending;
8171
8172         if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
8173             tp->rx_pending > 63)
8174                 tp->rx_pending = 63;
8175         tp->rx_jumbo_pending = ering->rx_jumbo_pending;
8176         tp->tx_pending = ering->tx_pending;
8177
8178         if (netif_running(dev)) {
8179                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8180                 err = tg3_restart_hw(tp, 1);
8181                 if (!err)
8182                         tg3_netif_start(tp);
8183         }
8184
8185         tg3_full_unlock(tp);
8186
8187         return err;
8188 }
8189
8190 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
8191 {
8192         struct tg3 *tp = netdev_priv(dev);
8193
8194         epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
8195         epause->rx_pause = (tp->tg3_flags & TG3_FLAG_RX_PAUSE) != 0;
8196         epause->tx_pause = (tp->tg3_flags & TG3_FLAG_TX_PAUSE) != 0;
8197 }
8198
8199 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
8200 {
8201         struct tg3 *tp = netdev_priv(dev);
8202         int irq_sync = 0, err = 0;
8203
8204         if (netif_running(dev)) {
8205                 tg3_netif_stop(tp);
8206                 irq_sync = 1;
8207         }
8208
8209         tg3_full_lock(tp, irq_sync);
8210
8211         if (epause->autoneg)
8212                 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
8213         else
8214                 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
8215         if (epause->rx_pause)
8216                 tp->tg3_flags |= TG3_FLAG_RX_PAUSE;
8217         else
8218                 tp->tg3_flags &= ~TG3_FLAG_RX_PAUSE;
8219         if (epause->tx_pause)
8220                 tp->tg3_flags |= TG3_FLAG_TX_PAUSE;
8221         else
8222                 tp->tg3_flags &= ~TG3_FLAG_TX_PAUSE;
8223
8224         if (netif_running(dev)) {
8225                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8226                 err = tg3_restart_hw(tp, 1);
8227                 if (!err)
8228                         tg3_netif_start(tp);
8229         }
8230
8231         tg3_full_unlock(tp);
8232
8233         return err;
8234 }
8235
8236 static u32 tg3_get_rx_csum(struct net_device *dev)
8237 {
8238         struct tg3 *tp = netdev_priv(dev);
8239         return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
8240 }
8241
8242 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
8243 {
8244         struct tg3 *tp = netdev_priv(dev);
8245
8246         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
8247                 if (data != 0)
8248                         return -EINVAL;
8249                 return 0;
8250         }
8251
8252         spin_lock_bh(&tp->lock);
8253         if (data)
8254                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
8255         else
8256                 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
8257         spin_unlock_bh(&tp->lock);
8258
8259         return 0;
8260 }
8261
8262 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
8263 {
8264         struct tg3 *tp = netdev_priv(dev);
8265
8266         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
8267                 if (data != 0)
8268                         return -EINVAL;
8269                 return 0;
8270         }
8271
8272         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
8273             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
8274                 ethtool_op_set_tx_hw_csum(dev, data);
8275         else
8276                 ethtool_op_set_tx_csum(dev, data);
8277
8278         return 0;
8279 }
8280
8281 static int tg3_get_stats_count (struct net_device *dev)
8282 {
8283         return TG3_NUM_STATS;
8284 }
8285
8286 static int tg3_get_test_count (struct net_device *dev)
8287 {
8288         return TG3_NUM_TEST;
8289 }
8290
8291 static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
8292 {
8293         switch (stringset) {
8294         case ETH_SS_STATS:
8295                 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
8296                 break;
8297         case ETH_SS_TEST:
8298                 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
8299                 break;
8300         default:
8301                 WARN_ON(1);     /* we need a WARN() */
8302                 break;
8303         }
8304 }
8305
8306 static int tg3_phys_id(struct net_device *dev, u32 data)
8307 {
8308         struct tg3 *tp = netdev_priv(dev);
8309         int i;
8310
8311         if (!netif_running(tp->dev))
8312                 return -EAGAIN;
8313
8314         if (data == 0)
8315                 data = 2;
8316
8317         for (i = 0; i < (data * 2); i++) {
8318                 if ((i % 2) == 0)
8319                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
8320                                            LED_CTRL_1000MBPS_ON |
8321                                            LED_CTRL_100MBPS_ON |
8322                                            LED_CTRL_10MBPS_ON |
8323                                            LED_CTRL_TRAFFIC_OVERRIDE |
8324                                            LED_CTRL_TRAFFIC_BLINK |
8325                                            LED_CTRL_TRAFFIC_LED);
8326
8327                 else
8328                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
8329                                            LED_CTRL_TRAFFIC_OVERRIDE);
8330
8331                 if (msleep_interruptible(500))
8332                         break;
8333         }
8334         tw32(MAC_LED_CTRL, tp->led_ctrl);
8335         return 0;
8336 }
8337
8338 static void tg3_get_ethtool_stats (struct net_device *dev,
8339                                    struct ethtool_stats *estats, u64 *tmp_stats)
8340 {
8341         struct tg3 *tp = netdev_priv(dev);
8342         memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
8343 }
8344
8345 #define NVRAM_TEST_SIZE 0x100
8346 #define NVRAM_SELFBOOT_FORMAT1_SIZE 0x14
8347 #define NVRAM_SELFBOOT_HW_SIZE 0x20
8348 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
8349
8350 static int tg3_test_nvram(struct tg3 *tp)
8351 {
8352         u32 *buf, csum, magic;
8353         int i, j, err = 0, size;
8354
8355         if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
8356                 return -EIO;
8357
8358         if (magic == TG3_EEPROM_MAGIC)
8359                 size = NVRAM_TEST_SIZE;
8360         else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
8361                 if ((magic & 0xe00000) == 0x200000)
8362                         size = NVRAM_SELFBOOT_FORMAT1_SIZE;
8363                 else
8364                         return 0;
8365         } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
8366                 size = NVRAM_SELFBOOT_HW_SIZE;
8367         else
8368                 return -EIO;
8369
8370         buf = kmalloc(size, GFP_KERNEL);
8371         if (buf == NULL)
8372                 return -ENOMEM;
8373
8374         err = -EIO;
8375         for (i = 0, j = 0; i < size; i += 4, j++) {
8376                 u32 val;
8377
8378                 if ((err = tg3_nvram_read(tp, i, &val)) != 0)
8379                         break;
8380                 buf[j] = cpu_to_le32(val);
8381         }
8382         if (i < size)
8383                 goto out;
8384
8385         /* Selfboot format */
8386         if ((cpu_to_be32(buf[0]) & TG3_EEPROM_MAGIC_FW_MSK) ==
8387             TG3_EEPROM_MAGIC_FW) {
8388                 u8 *buf8 = (u8 *) buf, csum8 = 0;
8389
8390                 for (i = 0; i < size; i++)
8391                         csum8 += buf8[i];
8392
8393                 if (csum8 == 0) {
8394                         err = 0;
8395                         goto out;
8396                 }
8397
8398                 err = -EIO;
8399                 goto out;
8400         }
8401
8402         if ((cpu_to_be32(buf[0]) & TG3_EEPROM_MAGIC_HW_MSK) ==
8403             TG3_EEPROM_MAGIC_HW) {
8404                 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
8405                 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
8406                 u8 *buf8 = (u8 *) buf;
8407                 int j, k;
8408
8409                 /* Separate the parity bits and the data bytes.  */
8410                 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
8411                         if ((i == 0) || (i == 8)) {
8412                                 int l;
8413                                 u8 msk;
8414
8415                                 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
8416                                         parity[k++] = buf8[i] & msk;
8417                                 i++;
8418                         }
8419                         else if (i == 16) {
8420                                 int l;
8421                                 u8 msk;
8422
8423                                 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
8424                                         parity[k++] = buf8[i] & msk;
8425                                 i++;
8426
8427                                 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
8428                                         parity[k++] = buf8[i] & msk;
8429                                 i++;
8430                         }
8431                         data[j++] = buf8[i];
8432                 }
8433
8434                 err = -EIO;
8435                 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
8436                         u8 hw8 = hweight8(data[i]);
8437
8438                         if ((hw8 & 0x1) && parity[i])
8439                                 goto out;
8440                         else if (!(hw8 & 0x1) && !parity[i])
8441                                 goto out;
8442                 }
8443                 err = 0;
8444                 goto out;
8445         }
8446
8447         /* Bootstrap checksum at offset 0x10 */
8448         csum = calc_crc((unsigned char *) buf, 0x10);
8449         if(csum != cpu_to_le32(buf[0x10/4]))
8450                 goto out;
8451
8452         /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
8453         csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
8454         if (csum != cpu_to_le32(buf[0xfc/4]))
8455                  goto out;
8456
8457         err = 0;
8458
8459 out:
8460         kfree(buf);
8461         return err;
8462 }
8463
8464 #define TG3_SERDES_TIMEOUT_SEC  2
8465 #define TG3_COPPER_TIMEOUT_SEC  6
8466
8467 static int tg3_test_link(struct tg3 *tp)
8468 {
8469         int i, max;
8470
8471         if (!netif_running(tp->dev))
8472                 return -ENODEV;
8473
8474         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
8475                 max = TG3_SERDES_TIMEOUT_SEC;
8476         else
8477                 max = TG3_COPPER_TIMEOUT_SEC;
8478
8479         for (i = 0; i < max; i++) {
8480                 if (netif_carrier_ok(tp->dev))
8481                         return 0;
8482
8483                 if (msleep_interruptible(1000))
8484                         break;
8485         }
8486
8487         return -EIO;
8488 }
8489
8490 /* Only test the commonly used registers */
8491 static int tg3_test_registers(struct tg3 *tp)
8492 {
8493         int i, is_5705, is_5750;
8494         u32 offset, read_mask, write_mask, val, save_val, read_val;
8495         static struct {
8496                 u16 offset;
8497                 u16 flags;
8498 #define TG3_FL_5705     0x1
8499 #define TG3_FL_NOT_5705 0x2
8500 #define TG3_FL_NOT_5788 0x4
8501 #define TG3_FL_NOT_5750 0x8
8502                 u32 read_mask;
8503                 u32 write_mask;
8504         } reg_tbl[] = {
8505                 /* MAC Control Registers */
8506                 { MAC_MODE, TG3_FL_NOT_5705,
8507                         0x00000000, 0x00ef6f8c },
8508                 { MAC_MODE, TG3_FL_5705,
8509                         0x00000000, 0x01ef6b8c },
8510                 { MAC_STATUS, TG3_FL_NOT_5705,
8511                         0x03800107, 0x00000000 },
8512                 { MAC_STATUS, TG3_FL_5705,
8513                         0x03800100, 0x00000000 },
8514                 { MAC_ADDR_0_HIGH, 0x0000,
8515                         0x00000000, 0x0000ffff },
8516                 { MAC_ADDR_0_LOW, 0x0000,
8517                         0x00000000, 0xffffffff },
8518                 { MAC_RX_MTU_SIZE, 0x0000,
8519                         0x00000000, 0x0000ffff },
8520                 { MAC_TX_MODE, 0x0000,
8521                         0x00000000, 0x00000070 },
8522                 { MAC_TX_LENGTHS, 0x0000,
8523                         0x00000000, 0x00003fff },
8524                 { MAC_RX_MODE, TG3_FL_NOT_5705,
8525                         0x00000000, 0x000007fc },
8526                 { MAC_RX_MODE, TG3_FL_5705,
8527                         0x00000000, 0x000007dc },
8528                 { MAC_HASH_REG_0, 0x0000,
8529                         0x00000000, 0xffffffff },
8530                 { MAC_HASH_REG_1, 0x0000,
8531                         0x00000000, 0xffffffff },
8532                 { MAC_HASH_REG_2, 0x0000,
8533                         0x00000000, 0xffffffff },
8534                 { MAC_HASH_REG_3, 0x0000,
8535                         0x00000000, 0xffffffff },
8536
8537                 /* Receive Data and Receive BD Initiator Control Registers. */
8538                 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
8539                         0x00000000, 0xffffffff },
8540                 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
8541                         0x00000000, 0xffffffff },
8542                 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
8543                         0x00000000, 0x00000003 },
8544                 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
8545                         0x00000000, 0xffffffff },
8546                 { RCVDBDI_STD_BD+0, 0x0000,
8547                         0x00000000, 0xffffffff },
8548                 { RCVDBDI_STD_BD+4, 0x0000,
8549                         0x00000000, 0xffffffff },
8550                 { RCVDBDI_STD_BD+8, 0x0000,
8551                         0x00000000, 0xffff0002 },
8552                 { RCVDBDI_STD_BD+0xc, 0x0000,
8553                         0x00000000, 0xffffffff },
8554
8555                 /* Receive BD Initiator Control Registers. */
8556                 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
8557                         0x00000000, 0xffffffff },
8558                 { RCVBDI_STD_THRESH, TG3_FL_5705,
8559                         0x00000000, 0x000003ff },
8560                 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
8561                         0x00000000, 0xffffffff },
8562
8563                 /* Host Coalescing Control Registers. */
8564                 { HOSTCC_MODE, TG3_FL_NOT_5705,
8565                         0x00000000, 0x00000004 },
8566                 { HOSTCC_MODE, TG3_FL_5705,
8567                         0x00000000, 0x000000f6 },
8568                 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
8569                         0x00000000, 0xffffffff },
8570                 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
8571                         0x00000000, 0x000003ff },
8572                 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
8573                         0x00000000, 0xffffffff },
8574                 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
8575                         0x00000000, 0x000003ff },
8576                 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
8577                         0x00000000, 0xffffffff },
8578                 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
8579                         0x00000000, 0x000000ff },
8580                 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
8581                         0x00000000, 0xffffffff },
8582                 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
8583                         0x00000000, 0x000000ff },
8584                 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
8585                         0x00000000, 0xffffffff },
8586                 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
8587                         0x00000000, 0xffffffff },
8588                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
8589                         0x00000000, 0xffffffff },
8590                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
8591                         0x00000000, 0x000000ff },
8592                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
8593                         0x00000000, 0xffffffff },
8594                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
8595                         0x00000000, 0x000000ff },
8596                 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
8597                         0x00000000, 0xffffffff },
8598                 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
8599                         0x00000000, 0xffffffff },
8600                 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
8601                         0x00000000, 0xffffffff },
8602                 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
8603                         0x00000000, 0xffffffff },
8604                 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
8605                         0x00000000, 0xffffffff },
8606                 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
8607                         0xffffffff, 0x00000000 },
8608                 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
8609                         0xffffffff, 0x00000000 },
8610
8611                 /* Buffer Manager Control Registers. */
8612                 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
8613                         0x00000000, 0x007fff80 },
8614                 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
8615                         0x00000000, 0x007fffff },
8616                 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
8617                         0x00000000, 0x0000003f },
8618                 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
8619                         0x00000000, 0x000001ff },
8620                 { BUFMGR_MB_HIGH_WATER, 0x0000,
8621                         0x00000000, 0x000001ff },
8622                 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
8623                         0xffffffff, 0x00000000 },
8624                 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
8625                         0xffffffff, 0x00000000 },
8626
8627                 /* Mailbox Registers */
8628                 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
8629                         0x00000000, 0x000001ff },
8630                 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
8631                         0x00000000, 0x000001ff },
8632                 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
8633                         0x00000000, 0x000007ff },
8634                 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
8635                         0x00000000, 0x000001ff },
8636
8637                 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
8638         };
8639
8640         is_5705 = is_5750 = 0;
8641         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
8642                 is_5705 = 1;
8643                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
8644                         is_5750 = 1;
8645         }
8646
8647         for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
8648                 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
8649                         continue;
8650
8651                 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
8652                         continue;
8653
8654                 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
8655                     (reg_tbl[i].flags & TG3_FL_NOT_5788))
8656                         continue;
8657
8658                 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
8659                         continue;
8660
8661                 offset = (u32) reg_tbl[i].offset;
8662                 read_mask = reg_tbl[i].read_mask;
8663                 write_mask = reg_tbl[i].write_mask;
8664
8665                 /* Save the original register content */
8666                 save_val = tr32(offset);
8667
8668                 /* Determine the read-only value. */
8669                 read_val = save_val & read_mask;
8670
8671                 /* Write zero to the register, then make sure the read-only bits
8672                  * are not changed and the read/write bits are all zeros.
8673                  */
8674                 tw32(offset, 0);
8675
8676                 val = tr32(offset);
8677
8678                 /* Test the read-only and read/write bits. */
8679                 if (((val & read_mask) != read_val) || (val & write_mask))
8680                         goto out;
8681
8682                 /* Write ones to all the bits defined by RdMask and WrMask, then
8683                  * make sure the read-only bits are not changed and the
8684                  * read/write bits are all ones.
8685                  */
8686                 tw32(offset, read_mask | write_mask);
8687
8688                 val = tr32(offset);
8689
8690                 /* Test the read-only bits. */
8691                 if ((val & read_mask) != read_val)
8692                         goto out;
8693
8694                 /* Test the read/write bits. */
8695                 if ((val & write_mask) != write_mask)
8696                         goto out;
8697
8698                 tw32(offset, save_val);
8699         }
8700
8701         return 0;
8702
8703 out:
8704         if (netif_msg_hw(tp))
8705                 printk(KERN_ERR PFX "Register test failed at offset %x\n",
8706                        offset);
8707         tw32(offset, save_val);
8708         return -EIO;
8709 }
8710
8711 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
8712 {
8713         static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
8714         int i;
8715         u32 j;
8716
8717         for (i = 0; i < sizeof(test_pattern)/sizeof(u32); i++) {
8718                 for (j = 0; j < len; j += 4) {
8719                         u32 val;
8720
8721                         tg3_write_mem(tp, offset + j, test_pattern[i]);
8722                         tg3_read_mem(tp, offset + j, &val);
8723                         if (val != test_pattern[i])
8724                                 return -EIO;
8725                 }
8726         }
8727         return 0;
8728 }
8729
8730 static int tg3_test_memory(struct tg3 *tp)
8731 {
8732         static struct mem_entry {
8733                 u32 offset;
8734                 u32 len;
8735         } mem_tbl_570x[] = {
8736                 { 0x00000000, 0x00b50},
8737                 { 0x00002000, 0x1c000},
8738                 { 0xffffffff, 0x00000}
8739         }, mem_tbl_5705[] = {
8740                 { 0x00000100, 0x0000c},
8741                 { 0x00000200, 0x00008},
8742                 { 0x00004000, 0x00800},
8743                 { 0x00006000, 0x01000},
8744                 { 0x00008000, 0x02000},
8745                 { 0x00010000, 0x0e000},
8746                 { 0xffffffff, 0x00000}
8747         }, mem_tbl_5755[] = {
8748                 { 0x00000200, 0x00008},
8749                 { 0x00004000, 0x00800},
8750                 { 0x00006000, 0x00800},
8751                 { 0x00008000, 0x02000},
8752                 { 0x00010000, 0x0c000},
8753                 { 0xffffffff, 0x00000}
8754         }, mem_tbl_5906[] = {
8755                 { 0x00000200, 0x00008},
8756                 { 0x00004000, 0x00400},
8757                 { 0x00006000, 0x00400},
8758                 { 0x00008000, 0x01000},
8759                 { 0x00010000, 0x01000},
8760                 { 0xffffffff, 0x00000}
8761         };
8762         struct mem_entry *mem_tbl;
8763         int err = 0;
8764         int i;
8765
8766         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
8767                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
8768                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
8769                         mem_tbl = mem_tbl_5755;
8770                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
8771                         mem_tbl = mem_tbl_5906;
8772                 else
8773                         mem_tbl = mem_tbl_5705;
8774         } else
8775                 mem_tbl = mem_tbl_570x;
8776
8777         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
8778                 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
8779                     mem_tbl[i].len)) != 0)
8780                         break;
8781         }
8782
8783         return err;
8784 }
8785
8786 #define TG3_MAC_LOOPBACK        0
8787 #define TG3_PHY_LOOPBACK        1
8788
8789 static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
8790 {
8791         u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
8792         u32 desc_idx;
8793         struct sk_buff *skb, *rx_skb;
8794         u8 *tx_data;
8795         dma_addr_t map;
8796         int num_pkts, tx_len, rx_len, i, err;
8797         struct tg3_rx_buffer_desc *desc;
8798
8799         if (loopback_mode == TG3_MAC_LOOPBACK) {
8800                 /* HW errata - mac loopback fails in some cases on 5780.
8801                  * Normal traffic and PHY loopback are not affected by
8802                  * errata.
8803                  */
8804                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
8805                         return 0;
8806
8807                 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
8808                            MAC_MODE_PORT_INT_LPBACK | MAC_MODE_LINK_POLARITY;
8809                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
8810                         mac_mode |= MAC_MODE_PORT_MODE_MII;
8811                 else
8812                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
8813                 tw32(MAC_MODE, mac_mode);
8814         } else if (loopback_mode == TG3_PHY_LOOPBACK) {
8815                 u32 val;
8816
8817                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
8818                         u32 phytest;
8819
8820                         if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &phytest)) {
8821                                 u32 phy;
8822
8823                                 tg3_writephy(tp, MII_TG3_EPHY_TEST,
8824                                              phytest | MII_TG3_EPHY_SHADOW_EN);
8825                                 if (!tg3_readphy(tp, 0x1b, &phy))
8826                                         tg3_writephy(tp, 0x1b, phy & ~0x20);
8827                                 if (!tg3_readphy(tp, 0x10, &phy))
8828                                         tg3_writephy(tp, 0x10, phy & ~0x4000);
8829                                 tg3_writephy(tp, MII_TG3_EPHY_TEST, phytest);
8830                         }
8831                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
8832                 } else
8833                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
8834
8835                 tg3_writephy(tp, MII_BMCR, val);
8836                 udelay(40);
8837
8838                 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
8839                            MAC_MODE_LINK_POLARITY;
8840                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
8841                         tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x1800);
8842                         mac_mode |= MAC_MODE_PORT_MODE_MII;
8843                 } else
8844                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
8845
8846                 /* reset to prevent losing 1st rx packet intermittently */
8847                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
8848                         tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8849                         udelay(10);
8850                         tw32_f(MAC_RX_MODE, tp->rx_mode);
8851                 }
8852                 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
8853                         mac_mode &= ~MAC_MODE_LINK_POLARITY;
8854                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
8855                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
8856                 }
8857                 tw32(MAC_MODE, mac_mode);
8858         }
8859         else
8860                 return -EINVAL;
8861
8862         err = -EIO;
8863
8864         tx_len = 1514;
8865         skb = netdev_alloc_skb(tp->dev, tx_len);
8866         if (!skb)
8867                 return -ENOMEM;
8868
8869         tx_data = skb_put(skb, tx_len);
8870         memcpy(tx_data, tp->dev->dev_addr, 6);
8871         memset(tx_data + 6, 0x0, 8);
8872
8873         tw32(MAC_RX_MTU_SIZE, tx_len + 4);
8874
8875         for (i = 14; i < tx_len; i++)
8876                 tx_data[i] = (u8) (i & 0xff);
8877
8878         map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
8879
8880         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8881              HOSTCC_MODE_NOW);
8882
8883         udelay(10);
8884
8885         rx_start_idx = tp->hw_status->idx[0].rx_producer;
8886
8887         num_pkts = 0;
8888
8889         tg3_set_txd(tp, tp->tx_prod, map, tx_len, 0, 1);
8890
8891         tp->tx_prod++;
8892         num_pkts++;
8893
8894         tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW,
8895                      tp->tx_prod);
8896         tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW);
8897
8898         udelay(10);
8899
8900         /* 250 usec to allow enough time on some 10/100 Mbps devices.  */
8901         for (i = 0; i < 25; i++) {
8902                 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8903                        HOSTCC_MODE_NOW);
8904
8905                 udelay(10);
8906
8907                 tx_idx = tp->hw_status->idx[0].tx_consumer;
8908                 rx_idx = tp->hw_status->idx[0].rx_producer;
8909                 if ((tx_idx == tp->tx_prod) &&
8910                     (rx_idx == (rx_start_idx + num_pkts)))
8911                         break;
8912         }
8913
8914         pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
8915         dev_kfree_skb(skb);
8916
8917         if (tx_idx != tp->tx_prod)
8918                 goto out;
8919
8920         if (rx_idx != rx_start_idx + num_pkts)
8921                 goto out;
8922
8923         desc = &tp->rx_rcb[rx_start_idx];
8924         desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
8925         opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
8926         if (opaque_key != RXD_OPAQUE_RING_STD)
8927                 goto out;
8928
8929         if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
8930             (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
8931                 goto out;
8932
8933         rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
8934         if (rx_len != tx_len)
8935                 goto out;
8936
8937         rx_skb = tp->rx_std_buffers[desc_idx].skb;
8938
8939         map = pci_unmap_addr(&tp->rx_std_buffers[desc_idx], mapping);
8940         pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
8941
8942         for (i = 14; i < tx_len; i++) {
8943                 if (*(rx_skb->data + i) != (u8) (i & 0xff))
8944                         goto out;
8945         }
8946         err = 0;
8947
8948         /* tg3_free_rings will unmap and free the rx_skb */
8949 out:
8950         return err;
8951 }
8952
8953 #define TG3_MAC_LOOPBACK_FAILED         1
8954 #define TG3_PHY_LOOPBACK_FAILED         2
8955 #define TG3_LOOPBACK_FAILED             (TG3_MAC_LOOPBACK_FAILED |      \
8956                                          TG3_PHY_LOOPBACK_FAILED)
8957
8958 static int tg3_test_loopback(struct tg3 *tp)
8959 {
8960         int err = 0;
8961
8962         if (!netif_running(tp->dev))
8963                 return TG3_LOOPBACK_FAILED;
8964
8965         err = tg3_reset_hw(tp, 1);
8966         if (err)
8967                 return TG3_LOOPBACK_FAILED;
8968
8969         if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
8970                 err |= TG3_MAC_LOOPBACK_FAILED;
8971         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
8972                 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
8973                         err |= TG3_PHY_LOOPBACK_FAILED;
8974         }
8975
8976         return err;
8977 }
8978
8979 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
8980                           u64 *data)
8981 {
8982         struct tg3 *tp = netdev_priv(dev);
8983
8984         if (tp->link_config.phy_is_low_power)
8985                 tg3_set_power_state(tp, PCI_D0);
8986
8987         memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
8988
8989         if (tg3_test_nvram(tp) != 0) {
8990                 etest->flags |= ETH_TEST_FL_FAILED;
8991                 data[0] = 1;
8992         }
8993         if (tg3_test_link(tp) != 0) {
8994                 etest->flags |= ETH_TEST_FL_FAILED;
8995                 data[1] = 1;
8996         }
8997         if (etest->flags & ETH_TEST_FL_OFFLINE) {
8998                 int err, irq_sync = 0;
8999
9000                 if (netif_running(dev)) {
9001                         tg3_netif_stop(tp);
9002                         irq_sync = 1;
9003                 }
9004
9005                 tg3_full_lock(tp, irq_sync);
9006
9007                 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
9008                 err = tg3_nvram_lock(tp);
9009                 tg3_halt_cpu(tp, RX_CPU_BASE);
9010                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
9011                         tg3_halt_cpu(tp, TX_CPU_BASE);
9012                 if (!err)
9013                         tg3_nvram_unlock(tp);
9014
9015                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
9016                         tg3_phy_reset(tp);
9017
9018                 if (tg3_test_registers(tp) != 0) {
9019                         etest->flags |= ETH_TEST_FL_FAILED;
9020                         data[2] = 1;
9021                 }
9022                 if (tg3_test_memory(tp) != 0) {
9023                         etest->flags |= ETH_TEST_FL_FAILED;
9024                         data[3] = 1;
9025                 }
9026                 if ((data[4] = tg3_test_loopback(tp)) != 0)
9027                         etest->flags |= ETH_TEST_FL_FAILED;
9028
9029                 tg3_full_unlock(tp);
9030
9031                 if (tg3_test_interrupt(tp) != 0) {
9032                         etest->flags |= ETH_TEST_FL_FAILED;
9033                         data[5] = 1;
9034                 }
9035
9036                 tg3_full_lock(tp, 0);
9037
9038                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9039                 if (netif_running(dev)) {
9040                         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
9041                         if (!tg3_restart_hw(tp, 1))
9042                                 tg3_netif_start(tp);
9043                 }
9044
9045                 tg3_full_unlock(tp);
9046         }
9047         if (tp->link_config.phy_is_low_power)
9048                 tg3_set_power_state(tp, PCI_D3hot);
9049
9050 }
9051
9052 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
9053 {
9054         struct mii_ioctl_data *data = if_mii(ifr);
9055         struct tg3 *tp = netdev_priv(dev);
9056         int err;
9057
9058         switch(cmd) {
9059         case SIOCGMIIPHY:
9060                 data->phy_id = PHY_ADDR;
9061
9062                 /* fallthru */
9063         case SIOCGMIIREG: {
9064                 u32 mii_regval;
9065
9066                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9067                         break;                  /* We have no PHY */
9068
9069                 if (tp->link_config.phy_is_low_power)
9070                         return -EAGAIN;
9071
9072                 spin_lock_bh(&tp->lock);
9073                 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
9074                 spin_unlock_bh(&tp->lock);
9075
9076                 data->val_out = mii_regval;
9077
9078                 return err;
9079         }
9080
9081         case SIOCSMIIREG:
9082                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9083                         break;                  /* We have no PHY */
9084
9085                 if (!capable(CAP_NET_ADMIN))
9086                         return -EPERM;
9087
9088                 if (tp->link_config.phy_is_low_power)
9089                         return -EAGAIN;
9090
9091                 spin_lock_bh(&tp->lock);
9092                 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
9093                 spin_unlock_bh(&tp->lock);
9094
9095                 return err;
9096
9097         default:
9098                 /* do nothing */
9099                 break;
9100         }
9101         return -EOPNOTSUPP;
9102 }
9103
9104 #if TG3_VLAN_TAG_USED
9105 static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
9106 {
9107         struct tg3 *tp = netdev_priv(dev);
9108
9109         if (netif_running(dev))
9110                 tg3_netif_stop(tp);
9111
9112         tg3_full_lock(tp, 0);
9113
9114         tp->vlgrp = grp;
9115
9116         /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
9117         __tg3_set_rx_mode(dev);
9118
9119         tg3_full_unlock(tp);
9120
9121         if (netif_running(dev))
9122                 tg3_netif_start(tp);
9123 }
9124
9125 static void tg3_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
9126 {
9127         struct tg3 *tp = netdev_priv(dev);
9128
9129         if (netif_running(dev))
9130                 tg3_netif_stop(tp);
9131
9132         tg3_full_lock(tp, 0);
9133         vlan_group_set_device(tp->vlgrp, vid, NULL);
9134         tg3_full_unlock(tp);
9135
9136         if (netif_running(dev))
9137                 tg3_netif_start(tp);
9138 }
9139 #endif
9140
9141 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
9142 {
9143         struct tg3 *tp = netdev_priv(dev);
9144
9145         memcpy(ec, &tp->coal, sizeof(*ec));
9146         return 0;
9147 }
9148
9149 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
9150 {
9151         struct tg3 *tp = netdev_priv(dev);
9152         u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
9153         u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
9154
9155         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
9156                 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
9157                 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
9158                 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
9159                 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
9160         }
9161
9162         if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
9163             (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
9164             (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
9165             (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
9166             (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
9167             (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
9168             (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
9169             (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
9170             (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
9171             (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
9172                 return -EINVAL;
9173
9174         /* No rx interrupts will be generated if both are zero */
9175         if ((ec->rx_coalesce_usecs == 0) &&
9176             (ec->rx_max_coalesced_frames == 0))
9177                 return -EINVAL;
9178
9179         /* No tx interrupts will be generated if both are zero */
9180         if ((ec->tx_coalesce_usecs == 0) &&
9181             (ec->tx_max_coalesced_frames == 0))
9182                 return -EINVAL;
9183
9184         /* Only copy relevant parameters, ignore all others. */
9185         tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
9186         tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
9187         tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
9188         tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
9189         tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
9190         tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
9191         tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
9192         tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
9193         tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
9194
9195         if (netif_running(dev)) {
9196                 tg3_full_lock(tp, 0);
9197                 __tg3_set_coalesce(tp, &tp->coal);
9198                 tg3_full_unlock(tp);
9199         }
9200         return 0;
9201 }
9202
9203 static const struct ethtool_ops tg3_ethtool_ops = {
9204         .get_settings           = tg3_get_settings,
9205         .set_settings           = tg3_set_settings,
9206         .get_drvinfo            = tg3_get_drvinfo,
9207         .get_regs_len           = tg3_get_regs_len,
9208         .get_regs               = tg3_get_regs,
9209         .get_wol                = tg3_get_wol,
9210         .set_wol                = tg3_set_wol,
9211         .get_msglevel           = tg3_get_msglevel,
9212         .set_msglevel           = tg3_set_msglevel,
9213         .nway_reset             = tg3_nway_reset,
9214         .get_link               = ethtool_op_get_link,
9215         .get_eeprom_len         = tg3_get_eeprom_len,
9216         .get_eeprom             = tg3_get_eeprom,
9217         .set_eeprom             = tg3_set_eeprom,
9218         .get_ringparam          = tg3_get_ringparam,
9219         .set_ringparam          = tg3_set_ringparam,
9220         .get_pauseparam         = tg3_get_pauseparam,
9221         .set_pauseparam         = tg3_set_pauseparam,
9222         .get_rx_csum            = tg3_get_rx_csum,
9223         .set_rx_csum            = tg3_set_rx_csum,
9224         .get_tx_csum            = ethtool_op_get_tx_csum,
9225         .set_tx_csum            = tg3_set_tx_csum,
9226         .get_sg                 = ethtool_op_get_sg,
9227         .set_sg                 = ethtool_op_set_sg,
9228         .get_tso                = ethtool_op_get_tso,
9229         .set_tso                = tg3_set_tso,
9230         .self_test_count        = tg3_get_test_count,
9231         .self_test              = tg3_self_test,
9232         .get_strings            = tg3_get_strings,
9233         .phys_id                = tg3_phys_id,
9234         .get_stats_count        = tg3_get_stats_count,
9235         .get_ethtool_stats      = tg3_get_ethtool_stats,
9236         .get_coalesce           = tg3_get_coalesce,
9237         .set_coalesce           = tg3_set_coalesce,
9238         .get_perm_addr          = ethtool_op_get_perm_addr,
9239 };
9240
9241 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
9242 {
9243         u32 cursize, val, magic;
9244
9245         tp->nvram_size = EEPROM_CHIP_SIZE;
9246
9247         if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
9248                 return;
9249
9250         if ((magic != TG3_EEPROM_MAGIC) &&
9251             ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
9252             ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
9253                 return;
9254
9255         /*
9256          * Size the chip by reading offsets at increasing powers of two.
9257          * When we encounter our validation signature, we know the addressing
9258          * has wrapped around, and thus have our chip size.
9259          */
9260         cursize = 0x10;
9261
9262         while (cursize < tp->nvram_size) {
9263                 if (tg3_nvram_read_swab(tp, cursize, &val) != 0)
9264                         return;
9265
9266                 if (val == magic)
9267                         break;
9268
9269                 cursize <<= 1;
9270         }
9271
9272         tp->nvram_size = cursize;
9273 }
9274
9275 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
9276 {
9277         u32 val;
9278
9279         if (tg3_nvram_read_swab(tp, 0, &val) != 0)
9280                 return;
9281
9282         /* Selfboot format */
9283         if (val != TG3_EEPROM_MAGIC) {
9284                 tg3_get_eeprom_size(tp);
9285                 return;
9286         }
9287
9288         if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
9289                 if (val != 0) {
9290                         tp->nvram_size = (val >> 16) * 1024;
9291                         return;
9292                 }
9293         }
9294         tp->nvram_size = 0x20000;
9295 }
9296
9297 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
9298 {
9299         u32 nvcfg1;
9300
9301         nvcfg1 = tr32(NVRAM_CFG1);
9302         if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
9303                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9304         }
9305         else {
9306                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
9307                 tw32(NVRAM_CFG1, nvcfg1);
9308         }
9309
9310         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
9311             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
9312                 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
9313                         case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
9314                                 tp->nvram_jedecnum = JEDEC_ATMEL;
9315                                 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
9316                                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9317                                 break;
9318                         case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
9319                                 tp->nvram_jedecnum = JEDEC_ATMEL;
9320                                 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
9321                                 break;
9322                         case FLASH_VENDOR_ATMEL_EEPROM:
9323                                 tp->nvram_jedecnum = JEDEC_ATMEL;
9324                                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9325                                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9326                                 break;
9327                         case FLASH_VENDOR_ST:
9328                                 tp->nvram_jedecnum = JEDEC_ST;
9329                                 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
9330                                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9331                                 break;
9332                         case FLASH_VENDOR_SAIFUN:
9333                                 tp->nvram_jedecnum = JEDEC_SAIFUN;
9334                                 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
9335                                 break;
9336                         case FLASH_VENDOR_SST_SMALL:
9337                         case FLASH_VENDOR_SST_LARGE:
9338                                 tp->nvram_jedecnum = JEDEC_SST;
9339                                 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
9340                                 break;
9341                 }
9342         }
9343         else {
9344                 tp->nvram_jedecnum = JEDEC_ATMEL;
9345                 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
9346                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9347         }
9348 }
9349
9350 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
9351 {
9352         u32 nvcfg1;
9353
9354         nvcfg1 = tr32(NVRAM_CFG1);
9355
9356         /* NVRAM protection for TPM */
9357         if (nvcfg1 & (1 << 27))
9358                 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
9359
9360         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
9361                 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
9362                 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
9363                         tp->nvram_jedecnum = JEDEC_ATMEL;
9364                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9365                         break;
9366                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
9367                         tp->nvram_jedecnum = JEDEC_ATMEL;
9368                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9369                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
9370                         break;
9371                 case FLASH_5752VENDOR_ST_M45PE10:
9372                 case FLASH_5752VENDOR_ST_M45PE20:
9373                 case FLASH_5752VENDOR_ST_M45PE40:
9374                         tp->nvram_jedecnum = JEDEC_ST;
9375                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9376                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
9377                         break;
9378         }
9379
9380         if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
9381                 switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
9382                         case FLASH_5752PAGE_SIZE_256:
9383                                 tp->nvram_pagesize = 256;
9384                                 break;
9385                         case FLASH_5752PAGE_SIZE_512:
9386                                 tp->nvram_pagesize = 512;
9387                                 break;
9388                         case FLASH_5752PAGE_SIZE_1K:
9389                                 tp->nvram_pagesize = 1024;
9390                                 break;
9391                         case FLASH_5752PAGE_SIZE_2K:
9392                                 tp->nvram_pagesize = 2048;
9393                                 break;
9394                         case FLASH_5752PAGE_SIZE_4K:
9395                                 tp->nvram_pagesize = 4096;
9396                                 break;
9397                         case FLASH_5752PAGE_SIZE_264:
9398                                 tp->nvram_pagesize = 264;
9399                                 break;
9400                 }
9401         }
9402         else {
9403                 /* For eeprom, set pagesize to maximum eeprom size */
9404                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9405
9406                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
9407                 tw32(NVRAM_CFG1, nvcfg1);
9408         }
9409 }
9410
9411 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
9412 {
9413         u32 nvcfg1;
9414
9415         nvcfg1 = tr32(NVRAM_CFG1);
9416
9417         /* NVRAM protection for TPM */
9418         if (nvcfg1 & (1 << 27))
9419                 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
9420
9421         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
9422                 case FLASH_5755VENDOR_ATMEL_EEPROM_64KHZ:
9423                 case FLASH_5755VENDOR_ATMEL_EEPROM_376KHZ:
9424                         tp->nvram_jedecnum = JEDEC_ATMEL;
9425                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9426                         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9427
9428                         nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
9429                         tw32(NVRAM_CFG1, nvcfg1);
9430                         break;
9431                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
9432                 case FLASH_5755VENDOR_ATMEL_FLASH_1:
9433                 case FLASH_5755VENDOR_ATMEL_FLASH_2:
9434                 case FLASH_5755VENDOR_ATMEL_FLASH_3:
9435                 case FLASH_5755VENDOR_ATMEL_FLASH_4:
9436                         tp->nvram_jedecnum = JEDEC_ATMEL;
9437                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9438                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
9439                         tp->nvram_pagesize = 264;
9440                         break;
9441                 case FLASH_5752VENDOR_ST_M45PE10:
9442                 case FLASH_5752VENDOR_ST_M45PE20:
9443                 case FLASH_5752VENDOR_ST_M45PE40:
9444                         tp->nvram_jedecnum = JEDEC_ST;
9445                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9446                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
9447                         tp->nvram_pagesize = 256;
9448                         break;
9449         }
9450 }
9451
9452 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
9453 {
9454         u32 nvcfg1;
9455
9456         nvcfg1 = tr32(NVRAM_CFG1);
9457
9458         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
9459                 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
9460                 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
9461                 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
9462                 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
9463                         tp->nvram_jedecnum = JEDEC_ATMEL;
9464                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9465                         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9466
9467                         nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
9468                         tw32(NVRAM_CFG1, nvcfg1);
9469                         break;
9470                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
9471                 case FLASH_5755VENDOR_ATMEL_FLASH_1:
9472                 case FLASH_5755VENDOR_ATMEL_FLASH_2:
9473                 case FLASH_5755VENDOR_ATMEL_FLASH_3:
9474                         tp->nvram_jedecnum = JEDEC_ATMEL;
9475                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9476                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
9477                         tp->nvram_pagesize = 264;
9478                         break;
9479                 case FLASH_5752VENDOR_ST_M45PE10:
9480                 case FLASH_5752VENDOR_ST_M45PE20:
9481                 case FLASH_5752VENDOR_ST_M45PE40:
9482                         tp->nvram_jedecnum = JEDEC_ST;
9483                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9484                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
9485                         tp->nvram_pagesize = 256;
9486                         break;
9487         }
9488 }
9489
9490 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
9491 {
9492         tp->nvram_jedecnum = JEDEC_ATMEL;
9493         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9494         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9495 }
9496
9497 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
9498 static void __devinit tg3_nvram_init(struct tg3 *tp)
9499 {
9500         tw32_f(GRC_EEPROM_ADDR,
9501              (EEPROM_ADDR_FSM_RESET |
9502               (EEPROM_DEFAULT_CLOCK_PERIOD <<
9503                EEPROM_ADDR_CLKPERD_SHIFT)));
9504
9505         msleep(1);
9506
9507         /* Enable seeprom accesses. */
9508         tw32_f(GRC_LOCAL_CTRL,
9509              tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
9510         udelay(100);
9511
9512         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
9513             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
9514                 tp->tg3_flags |= TG3_FLAG_NVRAM;
9515
9516                 if (tg3_nvram_lock(tp)) {
9517                         printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
9518                                "tg3_nvram_init failed.\n", tp->dev->name);
9519                         return;
9520                 }
9521                 tg3_enable_nvram_access(tp);
9522
9523                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
9524                         tg3_get_5752_nvram_info(tp);
9525                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
9526                         tg3_get_5755_nvram_info(tp);
9527                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
9528                         tg3_get_5787_nvram_info(tp);
9529                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
9530                         tg3_get_5906_nvram_info(tp);
9531                 else
9532                         tg3_get_nvram_info(tp);
9533
9534                 tg3_get_nvram_size(tp);
9535
9536                 tg3_disable_nvram_access(tp);
9537                 tg3_nvram_unlock(tp);
9538
9539         } else {
9540                 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
9541
9542                 tg3_get_eeprom_size(tp);
9543         }
9544 }
9545
9546 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
9547                                         u32 offset, u32 *val)
9548 {
9549         u32 tmp;
9550         int i;
9551
9552         if (offset > EEPROM_ADDR_ADDR_MASK ||
9553             (offset % 4) != 0)
9554                 return -EINVAL;
9555
9556         tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
9557                                         EEPROM_ADDR_DEVID_MASK |
9558                                         EEPROM_ADDR_READ);
9559         tw32(GRC_EEPROM_ADDR,
9560              tmp |
9561              (0 << EEPROM_ADDR_DEVID_SHIFT) |
9562              ((offset << EEPROM_ADDR_ADDR_SHIFT) &
9563               EEPROM_ADDR_ADDR_MASK) |
9564              EEPROM_ADDR_READ | EEPROM_ADDR_START);
9565
9566         for (i = 0; i < 1000; i++) {
9567                 tmp = tr32(GRC_EEPROM_ADDR);
9568
9569                 if (tmp & EEPROM_ADDR_COMPLETE)
9570                         break;
9571                 msleep(1);
9572         }
9573         if (!(tmp & EEPROM_ADDR_COMPLETE))
9574                 return -EBUSY;
9575
9576         *val = tr32(GRC_EEPROM_DATA);
9577         return 0;
9578 }
9579
9580 #define NVRAM_CMD_TIMEOUT 10000
9581
9582 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
9583 {
9584         int i;
9585
9586         tw32(NVRAM_CMD, nvram_cmd);
9587         for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
9588                 udelay(10);
9589                 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
9590                         udelay(10);
9591                         break;
9592                 }
9593         }
9594         if (i == NVRAM_CMD_TIMEOUT) {
9595                 return -EBUSY;
9596         }
9597         return 0;
9598 }
9599
9600 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
9601 {
9602         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
9603             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
9604             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
9605             (tp->nvram_jedecnum == JEDEC_ATMEL))
9606
9607                 addr = ((addr / tp->nvram_pagesize) <<
9608                         ATMEL_AT45DB0X1B_PAGE_POS) +
9609                        (addr % tp->nvram_pagesize);
9610
9611         return addr;
9612 }
9613
9614 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
9615 {
9616         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
9617             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
9618             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
9619             (tp->nvram_jedecnum == JEDEC_ATMEL))
9620
9621                 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
9622                         tp->nvram_pagesize) +
9623                        (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
9624
9625         return addr;
9626 }
9627
9628 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
9629 {
9630         int ret;
9631
9632         if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
9633                 return tg3_nvram_read_using_eeprom(tp, offset, val);
9634
9635         offset = tg3_nvram_phys_addr(tp, offset);
9636
9637         if (offset > NVRAM_ADDR_MSK)
9638                 return -EINVAL;
9639
9640         ret = tg3_nvram_lock(tp);
9641         if (ret)
9642                 return ret;
9643
9644         tg3_enable_nvram_access(tp);
9645
9646         tw32(NVRAM_ADDR, offset);
9647         ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
9648                 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
9649
9650         if (ret == 0)
9651                 *val = swab32(tr32(NVRAM_RDDATA));
9652
9653         tg3_disable_nvram_access(tp);
9654
9655         tg3_nvram_unlock(tp);
9656
9657         return ret;
9658 }
9659
9660 static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val)
9661 {
9662         int err;
9663         u32 tmp;
9664
9665         err = tg3_nvram_read(tp, offset, &tmp);
9666         *val = swab32(tmp);
9667         return err;
9668 }
9669
9670 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
9671                                     u32 offset, u32 len, u8 *buf)
9672 {
9673         int i, j, rc = 0;
9674         u32 val;
9675
9676         for (i = 0; i < len; i += 4) {
9677                 u32 addr, data;
9678
9679                 addr = offset + i;
9680
9681                 memcpy(&data, buf + i, 4);
9682
9683                 tw32(GRC_EEPROM_DATA, cpu_to_le32(data));
9684
9685                 val = tr32(GRC_EEPROM_ADDR);
9686                 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
9687
9688                 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
9689                         EEPROM_ADDR_READ);
9690                 tw32(GRC_EEPROM_ADDR, val |
9691                         (0 << EEPROM_ADDR_DEVID_SHIFT) |
9692                         (addr & EEPROM_ADDR_ADDR_MASK) |
9693                         EEPROM_ADDR_START |
9694                         EEPROM_ADDR_WRITE);
9695
9696                 for (j = 0; j < 1000; j++) {
9697                         val = tr32(GRC_EEPROM_ADDR);
9698
9699                         if (val & EEPROM_ADDR_COMPLETE)
9700                                 break;
9701                         msleep(1);
9702                 }
9703                 if (!(val & EEPROM_ADDR_COMPLETE)) {
9704                         rc = -EBUSY;
9705                         break;
9706                 }
9707         }
9708
9709         return rc;
9710 }
9711
9712 /* offset and length are dword aligned */
9713 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
9714                 u8 *buf)
9715 {
9716         int ret = 0;
9717         u32 pagesize = tp->nvram_pagesize;
9718         u32 pagemask = pagesize - 1;
9719         u32 nvram_cmd;
9720         u8 *tmp;
9721
9722         tmp = kmalloc(pagesize, GFP_KERNEL);
9723         if (tmp == NULL)
9724                 return -ENOMEM;
9725
9726         while (len) {
9727                 int j;
9728                 u32 phy_addr, page_off, size;
9729
9730                 phy_addr = offset & ~pagemask;
9731
9732                 for (j = 0; j < pagesize; j += 4) {
9733                         if ((ret = tg3_nvram_read(tp, phy_addr + j,
9734                                                 (u32 *) (tmp + j))))
9735                                 break;
9736                 }
9737                 if (ret)
9738                         break;
9739
9740                 page_off = offset & pagemask;
9741                 size = pagesize;
9742                 if (len < size)
9743                         size = len;
9744
9745                 len -= size;
9746
9747                 memcpy(tmp + page_off, buf, size);
9748
9749                 offset = offset + (pagesize - page_off);
9750
9751                 tg3_enable_nvram_access(tp);
9752
9753                 /*
9754                  * Before we can erase the flash page, we need
9755                  * to issue a special "write enable" command.
9756                  */
9757                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
9758
9759                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
9760                         break;
9761
9762                 /* Erase the target page */
9763                 tw32(NVRAM_ADDR, phy_addr);
9764
9765                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
9766                         NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
9767
9768                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
9769                         break;
9770
9771                 /* Issue another write enable to start the write. */
9772                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
9773
9774                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
9775                         break;
9776
9777                 for (j = 0; j < pagesize; j += 4) {
9778                         u32 data;
9779
9780                         data = *((u32 *) (tmp + j));
9781                         tw32(NVRAM_WRDATA, cpu_to_be32(data));
9782
9783                         tw32(NVRAM_ADDR, phy_addr + j);
9784
9785                         nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
9786                                 NVRAM_CMD_WR;
9787
9788                         if (j == 0)
9789                                 nvram_cmd |= NVRAM_CMD_FIRST;
9790                         else if (j == (pagesize - 4))
9791                                 nvram_cmd |= NVRAM_CMD_LAST;
9792
9793                         if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
9794                                 break;
9795                 }
9796                 if (ret)
9797                         break;
9798         }
9799
9800         nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
9801         tg3_nvram_exec_cmd(tp, nvram_cmd);
9802
9803         kfree(tmp);
9804
9805         return ret;
9806 }
9807
9808 /* offset and length are dword aligned */
9809 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
9810                 u8 *buf)
9811 {
9812         int i, ret = 0;
9813
9814         for (i = 0; i < len; i += 4, offset += 4) {
9815                 u32 data, page_off, phy_addr, nvram_cmd;
9816
9817                 memcpy(&data, buf + i, 4);
9818                 tw32(NVRAM_WRDATA, cpu_to_be32(data));
9819
9820                 page_off = offset % tp->nvram_pagesize;
9821
9822                 phy_addr = tg3_nvram_phys_addr(tp, offset);
9823
9824                 tw32(NVRAM_ADDR, phy_addr);
9825
9826                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
9827
9828                 if ((page_off == 0) || (i == 0))
9829                         nvram_cmd |= NVRAM_CMD_FIRST;
9830                 if (page_off == (tp->nvram_pagesize - 4))
9831                         nvram_cmd |= NVRAM_CMD_LAST;
9832
9833                 if (i == (len - 4))
9834                         nvram_cmd |= NVRAM_CMD_LAST;
9835
9836                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752) &&
9837                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5755) &&
9838                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787) &&
9839                     (tp->nvram_jedecnum == JEDEC_ST) &&
9840                     (nvram_cmd & NVRAM_CMD_FIRST)) {
9841
9842                         if ((ret = tg3_nvram_exec_cmd(tp,
9843                                 NVRAM_CMD_WREN | NVRAM_CMD_GO |
9844                                 NVRAM_CMD_DONE)))
9845
9846                                 break;
9847                 }
9848                 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
9849                         /* We always do complete word writes to eeprom. */
9850                         nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
9851                 }
9852
9853                 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
9854                         break;
9855         }
9856         return ret;
9857 }
9858
9859 /* offset and length are dword aligned */
9860 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
9861 {
9862         int ret;
9863
9864         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
9865                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
9866                        ~GRC_LCLCTRL_GPIO_OUTPUT1);
9867                 udelay(40);
9868         }
9869
9870         if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
9871                 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
9872         }
9873         else {
9874                 u32 grc_mode;
9875
9876                 ret = tg3_nvram_lock(tp);
9877                 if (ret)
9878                         return ret;
9879
9880                 tg3_enable_nvram_access(tp);
9881                 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
9882                     !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
9883                         tw32(NVRAM_WRITE1, 0x406);
9884
9885                 grc_mode = tr32(GRC_MODE);
9886                 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
9887
9888                 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
9889                         !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
9890
9891                         ret = tg3_nvram_write_block_buffered(tp, offset, len,
9892                                 buf);
9893                 }
9894                 else {
9895                         ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
9896                                 buf);
9897                 }
9898
9899                 grc_mode = tr32(GRC_MODE);
9900                 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
9901
9902                 tg3_disable_nvram_access(tp);
9903                 tg3_nvram_unlock(tp);
9904         }
9905
9906         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
9907                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
9908                 udelay(40);
9909         }
9910
9911         return ret;
9912 }
9913
9914 struct subsys_tbl_ent {
9915         u16 subsys_vendor, subsys_devid;
9916         u32 phy_id;
9917 };
9918
9919 static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
9920         /* Broadcom boards. */
9921         { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
9922         { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
9923         { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
9924         { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 },              /* BCM95700A9 */
9925         { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
9926         { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
9927         { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 },              /* BCM95701A7 */
9928         { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
9929         { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
9930         { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
9931         { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
9932
9933         /* 3com boards. */
9934         { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
9935         { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
9936         { PCI_VENDOR_ID_3COM, 0x1004, 0 },              /* 3C996SX */
9937         { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
9938         { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
9939
9940         /* DELL boards. */
9941         { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
9942         { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
9943         { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
9944         { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
9945
9946         /* Compaq boards. */
9947         { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
9948         { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
9949         { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 },              /* CHANGELING */
9950         { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
9951         { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
9952
9953         /* IBM boards. */
9954         { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
9955 };
9956
9957 static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
9958 {
9959         int i;
9960
9961         for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
9962                 if ((subsys_id_to_phy_id[i].subsys_vendor ==
9963                      tp->pdev->subsystem_vendor) &&
9964                     (subsys_id_to_phy_id[i].subsys_devid ==
9965                      tp->pdev->subsystem_device))
9966                         return &subsys_id_to_phy_id[i];
9967         }
9968         return NULL;
9969 }
9970
9971 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
9972 {
9973         u32 val;
9974         u16 pmcsr;
9975
9976         /* On some early chips the SRAM cannot be accessed in D3hot state,
9977          * so need make sure we're in D0.
9978          */
9979         pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
9980         pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
9981         pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
9982         msleep(1);
9983
9984         /* Make sure register accesses (indirect or otherwise)
9985          * will function correctly.
9986          */
9987         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
9988                                tp->misc_host_ctrl);
9989
9990         /* The memory arbiter has to be enabled in order for SRAM accesses
9991          * to succeed.  Normally on powerup the tg3 chip firmware will make
9992          * sure it is enabled, but other entities such as system netboot
9993          * code might disable it.
9994          */
9995         val = tr32(MEMARB_MODE);
9996         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
9997
9998         tp->phy_id = PHY_ID_INVALID;
9999         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
10000
10001         /* Assume an onboard device by default.  */
10002         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
10003
10004         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
10005                 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
10006                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
10007                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
10008                 }
10009                 return;
10010         }
10011
10012         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
10013         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
10014                 u32 nic_cfg, led_cfg;
10015                 u32 nic_phy_id, ver, cfg2 = 0, eeprom_phy_id;
10016                 int eeprom_phy_serdes = 0;
10017
10018                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
10019                 tp->nic_sram_data_cfg = nic_cfg;
10020
10021                 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
10022                 ver >>= NIC_SRAM_DATA_VER_SHIFT;
10023                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
10024                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
10025                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
10026                     (ver > 0) && (ver < 0x100))
10027                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
10028
10029                 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
10030                     NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
10031                         eeprom_phy_serdes = 1;
10032
10033                 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
10034                 if (nic_phy_id != 0) {
10035                         u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
10036                         u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
10037
10038                         eeprom_phy_id  = (id1 >> 16) << 10;
10039                         eeprom_phy_id |= (id2 & 0xfc00) << 16;
10040                         eeprom_phy_id |= (id2 & 0x03ff) <<  0;
10041                 } else
10042                         eeprom_phy_id = 0;
10043
10044                 tp->phy_id = eeprom_phy_id;
10045                 if (eeprom_phy_serdes) {
10046                         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
10047                                 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
10048                         else
10049                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
10050                 }
10051
10052                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10053                         led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
10054                                     SHASTA_EXT_LED_MODE_MASK);
10055                 else
10056                         led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
10057
10058                 switch (led_cfg) {
10059                 default:
10060                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
10061                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
10062                         break;
10063
10064                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
10065                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
10066                         break;
10067
10068                 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
10069                         tp->led_ctrl = LED_CTRL_MODE_MAC;
10070
10071                         /* Default to PHY_1_MODE if 0 (MAC_MODE) is
10072                          * read on some older 5700/5701 bootcode.
10073                          */
10074                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
10075                             ASIC_REV_5700 ||
10076                             GET_ASIC_REV(tp->pci_chip_rev_id) ==
10077                             ASIC_REV_5701)
10078                                 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
10079
10080                         break;
10081
10082                 case SHASTA_EXT_LED_SHARED:
10083                         tp->led_ctrl = LED_CTRL_MODE_SHARED;
10084                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
10085                             tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
10086                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
10087                                                  LED_CTRL_MODE_PHY_2);
10088                         break;
10089
10090                 case SHASTA_EXT_LED_MAC:
10091                         tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
10092                         break;
10093
10094                 case SHASTA_EXT_LED_COMBO:
10095                         tp->led_ctrl = LED_CTRL_MODE_COMBO;
10096                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
10097                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
10098                                                  LED_CTRL_MODE_PHY_2);
10099                         break;
10100
10101                 };
10102
10103                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10104                      GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
10105                     tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
10106                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
10107
10108                 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
10109                         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
10110                         if ((tp->pdev->subsystem_vendor ==
10111                              PCI_VENDOR_ID_ARIMA) &&
10112                             (tp->pdev->subsystem_device == 0x205a ||
10113                              tp->pdev->subsystem_device == 0x2063))
10114                                 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
10115                 } else {
10116                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
10117                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
10118                 }
10119
10120                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
10121                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
10122                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10123                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
10124                 }
10125                 if (nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL)
10126                         tp->tg3_flags |= TG3_FLAG_SERDES_WOL_CAP;
10127
10128                 if (cfg2 & (1 << 17))
10129                         tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
10130
10131                 /* serdes signal pre-emphasis in register 0x590 set by */
10132                 /* bootcode if bit 18 is set */
10133                 if (cfg2 & (1 << 18))
10134                         tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
10135         }
10136 }
10137
10138 static int __devinit tg3_phy_probe(struct tg3 *tp)
10139 {
10140         u32 hw_phy_id_1, hw_phy_id_2;
10141         u32 hw_phy_id, hw_phy_id_masked;
10142         int err;
10143
10144         /* Reading the PHY ID register can conflict with ASF
10145          * firwmare access to the PHY hardware.
10146          */
10147         err = 0;
10148         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
10149                 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
10150         } else {
10151                 /* Now read the physical PHY_ID from the chip and verify
10152                  * that it is sane.  If it doesn't look good, we fall back
10153                  * to either the hard-coded table based PHY_ID and failing
10154                  * that the value found in the eeprom area.
10155                  */
10156                 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
10157                 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
10158
10159                 hw_phy_id  = (hw_phy_id_1 & 0xffff) << 10;
10160                 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
10161                 hw_phy_id |= (hw_phy_id_2 & 0x03ff) <<  0;
10162
10163                 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
10164         }
10165
10166         if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
10167                 tp->phy_id = hw_phy_id;
10168                 if (hw_phy_id_masked == PHY_ID_BCM8002)
10169                         tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
10170                 else
10171                         tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
10172         } else {
10173                 if (tp->phy_id != PHY_ID_INVALID) {
10174                         /* Do nothing, phy ID already set up in
10175                          * tg3_get_eeprom_hw_cfg().
10176                          */
10177                 } else {
10178                         struct subsys_tbl_ent *p;
10179
10180                         /* No eeprom signature?  Try the hardcoded
10181                          * subsys device table.
10182                          */
10183                         p = lookup_by_subsys(tp);
10184                         if (!p)
10185                                 return -ENODEV;
10186
10187                         tp->phy_id = p->phy_id;
10188                         if (!tp->phy_id ||
10189                             tp->phy_id == PHY_ID_BCM8002)
10190                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
10191                 }
10192         }
10193
10194         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
10195             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
10196                 u32 bmsr, adv_reg, tg3_ctrl, mask;
10197
10198                 tg3_readphy(tp, MII_BMSR, &bmsr);
10199                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
10200                     (bmsr & BMSR_LSTATUS))
10201                         goto skip_phy_reset;
10202
10203                 err = tg3_phy_reset(tp);
10204                 if (err)
10205                         return err;
10206
10207                 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
10208                            ADVERTISE_100HALF | ADVERTISE_100FULL |
10209                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
10210                 tg3_ctrl = 0;
10211                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
10212                         tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
10213                                     MII_TG3_CTRL_ADV_1000_FULL);
10214                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
10215                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
10216                                 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
10217                                              MII_TG3_CTRL_ENABLE_AS_MASTER);
10218                 }
10219
10220                 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
10221                         ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
10222                         ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
10223                 if (!tg3_copper_is_advertising_all(tp, mask)) {
10224                         tg3_writephy(tp, MII_ADVERTISE, adv_reg);
10225
10226                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
10227                                 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
10228
10229                         tg3_writephy(tp, MII_BMCR,
10230                                      BMCR_ANENABLE | BMCR_ANRESTART);
10231                 }
10232                 tg3_phy_set_wirespeed(tp);
10233
10234                 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
10235                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
10236                         tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
10237         }
10238
10239 skip_phy_reset:
10240         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
10241                 err = tg3_init_5401phy_dsp(tp);
10242                 if (err)
10243                         return err;
10244         }
10245
10246         if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
10247                 err = tg3_init_5401phy_dsp(tp);
10248         }
10249
10250         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
10251                 tp->link_config.advertising =
10252                         (ADVERTISED_1000baseT_Half |
10253                          ADVERTISED_1000baseT_Full |
10254                          ADVERTISED_Autoneg |
10255                          ADVERTISED_FIBRE);
10256         if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
10257                 tp->link_config.advertising &=
10258                         ~(ADVERTISED_1000baseT_Half |
10259                           ADVERTISED_1000baseT_Full);
10260
10261         return err;
10262 }
10263
10264 static void __devinit tg3_read_partno(struct tg3 *tp)
10265 {
10266         unsigned char vpd_data[256];
10267         unsigned int i;
10268         u32 magic;
10269
10270         if (tg3_nvram_read_swab(tp, 0x0, &magic))
10271                 goto out_not_found;
10272
10273         if (magic == TG3_EEPROM_MAGIC) {
10274                 for (i = 0; i < 256; i += 4) {
10275                         u32 tmp;
10276
10277                         if (tg3_nvram_read(tp, 0x100 + i, &tmp))
10278                                 goto out_not_found;
10279
10280                         vpd_data[i + 0] = ((tmp >>  0) & 0xff);
10281                         vpd_data[i + 1] = ((tmp >>  8) & 0xff);
10282                         vpd_data[i + 2] = ((tmp >> 16) & 0xff);
10283                         vpd_data[i + 3] = ((tmp >> 24) & 0xff);
10284                 }
10285         } else {
10286                 int vpd_cap;
10287
10288                 vpd_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_VPD);
10289                 for (i = 0; i < 256; i += 4) {
10290                         u32 tmp, j = 0;
10291                         u16 tmp16;
10292
10293                         pci_write_config_word(tp->pdev, vpd_cap + PCI_VPD_ADDR,
10294                                               i);
10295                         while (j++ < 100) {
10296                                 pci_read_config_word(tp->pdev, vpd_cap +
10297                                                      PCI_VPD_ADDR, &tmp16);
10298                                 if (tmp16 & 0x8000)
10299                                         break;
10300                                 msleep(1);
10301                         }
10302                         if (!(tmp16 & 0x8000))
10303                                 goto out_not_found;
10304
10305                         pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA,
10306                                               &tmp);
10307                         tmp = cpu_to_le32(tmp);
10308                         memcpy(&vpd_data[i], &tmp, 4);
10309                 }
10310         }
10311
10312         /* Now parse and find the part number. */
10313         for (i = 0; i < 254; ) {
10314                 unsigned char val = vpd_data[i];
10315                 unsigned int block_end;
10316
10317                 if (val == 0x82 || val == 0x91) {
10318                         i = (i + 3 +
10319                              (vpd_data[i + 1] +
10320                               (vpd_data[i + 2] << 8)));
10321                         continue;
10322                 }
10323
10324                 if (val != 0x90)
10325                         goto out_not_found;
10326
10327                 block_end = (i + 3 +
10328                              (vpd_data[i + 1] +
10329                               (vpd_data[i + 2] << 8)));
10330                 i += 3;
10331
10332                 if (block_end > 256)
10333                         goto out_not_found;
10334
10335                 while (i < (block_end - 2)) {
10336                         if (vpd_data[i + 0] == 'P' &&
10337                             vpd_data[i + 1] == 'N') {
10338                                 int partno_len = vpd_data[i + 2];
10339
10340                                 i += 3;
10341                                 if (partno_len > 24 || (partno_len + i) > 256)
10342                                         goto out_not_found;
10343
10344                                 memcpy(tp->board_part_number,
10345                                        &vpd_data[i], partno_len);
10346
10347                                 /* Success. */
10348                                 return;
10349                         }
10350                         i += 3 + vpd_data[i + 2];
10351                 }
10352
10353                 /* Part number not found. */
10354                 goto out_not_found;
10355         }
10356
10357 out_not_found:
10358         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10359                 strcpy(tp->board_part_number, "BCM95906");
10360         else
10361                 strcpy(tp->board_part_number, "none");
10362 }
10363
10364 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
10365 {
10366         u32 val, offset, start;
10367
10368         if (tg3_nvram_read_swab(tp, 0, &val))
10369                 return;
10370
10371         if (val != TG3_EEPROM_MAGIC)
10372                 return;
10373
10374         if (tg3_nvram_read_swab(tp, 0xc, &offset) ||
10375             tg3_nvram_read_swab(tp, 0x4, &start))
10376                 return;
10377
10378         offset = tg3_nvram_logical_addr(tp, offset);
10379         if (tg3_nvram_read_swab(tp, offset, &val))
10380                 return;
10381
10382         if ((val & 0xfc000000) == 0x0c000000) {
10383                 u32 ver_offset, addr;
10384                 int i;
10385
10386                 if (tg3_nvram_read_swab(tp, offset + 4, &val) ||
10387                     tg3_nvram_read_swab(tp, offset + 8, &ver_offset))
10388                         return;
10389
10390                 if (val != 0)
10391                         return;
10392
10393                 addr = offset + ver_offset - start;
10394                 for (i = 0; i < 16; i += 4) {
10395                         if (tg3_nvram_read(tp, addr + i, &val))
10396                                 return;
10397
10398                         val = cpu_to_le32(val);
10399                         memcpy(tp->fw_ver + i, &val, 4);
10400                 }
10401         }
10402 }
10403
10404 static int __devinit tg3_get_invariants(struct tg3 *tp)
10405 {
10406         static struct pci_device_id write_reorder_chipsets[] = {
10407                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
10408                              PCI_DEVICE_ID_AMD_FE_GATE_700C) },
10409                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
10410                              PCI_DEVICE_ID_AMD_8131_BRIDGE) },
10411                 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
10412                              PCI_DEVICE_ID_VIA_8385_0) },
10413                 { },
10414         };
10415         u32 misc_ctrl_reg;
10416         u32 cacheline_sz_reg;
10417         u32 pci_state_reg, grc_misc_cfg;
10418         u32 val;
10419         u16 pci_cmd;
10420         int err, pcie_cap;
10421
10422         /* Force memory write invalidate off.  If we leave it on,
10423          * then on 5700_BX chips we have to enable a workaround.
10424          * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
10425          * to match the cacheline size.  The Broadcom driver have this
10426          * workaround but turns MWI off all the times so never uses
10427          * it.  This seems to suggest that the workaround is insufficient.
10428          */
10429         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
10430         pci_cmd &= ~PCI_COMMAND_INVALIDATE;
10431         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
10432
10433         /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
10434          * has the register indirect write enable bit set before
10435          * we try to access any of the MMIO registers.  It is also
10436          * critical that the PCI-X hw workaround situation is decided
10437          * before that as well.
10438          */
10439         pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
10440                               &misc_ctrl_reg);
10441
10442         tp->pci_chip_rev_id = (misc_ctrl_reg >>
10443                                MISC_HOST_CTRL_CHIPREV_SHIFT);
10444
10445         /* Wrong chip ID in 5752 A0. This code can be removed later
10446          * as A0 is not in production.
10447          */
10448         if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
10449                 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
10450
10451         /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
10452          * we need to disable memory and use config. cycles
10453          * only to access all registers. The 5702/03 chips
10454          * can mistakenly decode the special cycles from the
10455          * ICH chipsets as memory write cycles, causing corruption
10456          * of register and memory space. Only certain ICH bridges
10457          * will drive special cycles with non-zero data during the
10458          * address phase which can fall within the 5703's address
10459          * range. This is not an ICH bug as the PCI spec allows
10460          * non-zero address during special cycles. However, only
10461          * these ICH bridges are known to drive non-zero addresses
10462          * during special cycles.
10463          *
10464          * Since special cycles do not cross PCI bridges, we only
10465          * enable this workaround if the 5703 is on the secondary
10466          * bus of these ICH bridges.
10467          */
10468         if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
10469             (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
10470                 static struct tg3_dev_id {
10471                         u32     vendor;
10472                         u32     device;
10473                         u32     rev;
10474                 } ich_chipsets[] = {
10475                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
10476                           PCI_ANY_ID },
10477                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
10478                           PCI_ANY_ID },
10479                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
10480                           0xa },
10481                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
10482                           PCI_ANY_ID },
10483                         { },
10484                 };
10485                 struct tg3_dev_id *pci_id = &ich_chipsets[0];
10486                 struct pci_dev *bridge = NULL;
10487
10488                 while (pci_id->vendor != 0) {
10489                         bridge = pci_get_device(pci_id->vendor, pci_id->device,
10490                                                 bridge);
10491                         if (!bridge) {
10492                                 pci_id++;
10493                                 continue;
10494                         }
10495                         if (pci_id->rev != PCI_ANY_ID) {
10496                                 u8 rev;
10497
10498                                 pci_read_config_byte(bridge, PCI_REVISION_ID,
10499                                                      &rev);
10500                                 if (rev > pci_id->rev)
10501                                         continue;
10502                         }
10503                         if (bridge->subordinate &&
10504                             (bridge->subordinate->number ==
10505                              tp->pdev->bus->number)) {
10506
10507                                 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
10508                                 pci_dev_put(bridge);
10509                                 break;
10510                         }
10511                 }
10512         }
10513
10514         /* The EPB bridge inside 5714, 5715, and 5780 cannot support
10515          * DMA addresses > 40-bit. This bridge may have other additional
10516          * 57xx devices behind it in some 4-port NIC designs for example.
10517          * Any tg3 device found behind the bridge will also need the 40-bit
10518          * DMA workaround.
10519          */
10520         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
10521             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
10522                 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
10523                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
10524                 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
10525         }
10526         else {
10527                 struct pci_dev *bridge = NULL;
10528
10529                 do {
10530                         bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
10531                                                 PCI_DEVICE_ID_SERVERWORKS_EPB,
10532                                                 bridge);
10533                         if (bridge && bridge->subordinate &&
10534                             (bridge->subordinate->number <=
10535                              tp->pdev->bus->number) &&
10536                             (bridge->subordinate->subordinate >=
10537                              tp->pdev->bus->number)) {
10538                                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
10539                                 pci_dev_put(bridge);
10540                                 break;
10541                         }
10542                 } while (bridge);
10543         }
10544
10545         /* Initialize misc host control in PCI block. */
10546         tp->misc_host_ctrl |= (misc_ctrl_reg &
10547                                MISC_HOST_CTRL_CHIPREV);
10548         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
10549                                tp->misc_host_ctrl);
10550
10551         pci_read_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
10552                               &cacheline_sz_reg);
10553
10554         tp->pci_cacheline_sz = (cacheline_sz_reg >>  0) & 0xff;
10555         tp->pci_lat_timer    = (cacheline_sz_reg >>  8) & 0xff;
10556         tp->pci_hdr_type     = (cacheline_sz_reg >> 16) & 0xff;
10557         tp->pci_bist         = (cacheline_sz_reg >> 24) & 0xff;
10558
10559         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
10560             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
10561             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
10562             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
10563             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
10564             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
10565                 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
10566
10567         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
10568             (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
10569                 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
10570
10571         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
10572                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
10573                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
10574                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
10575                         tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
10576                         tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
10577                 } else {
10578                         tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
10579                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
10580                                 ASIC_REV_5750 &&
10581                             tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
10582                                 tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
10583                 }
10584         }
10585
10586         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 &&
10587             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750 &&
10588             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
10589             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5755 &&
10590             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787 &&
10591             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
10592                 tp->tg3_flags2 |= TG3_FLG2_JUMBO_CAPABLE;
10593
10594         pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
10595         if (pcie_cap != 0) {
10596                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
10597                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
10598                         u16 lnkctl;
10599
10600                         pci_read_config_word(tp->pdev,
10601                                              pcie_cap + PCI_EXP_LNKCTL,
10602                                              &lnkctl);
10603                         if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN)
10604                                 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
10605                 }
10606         }
10607
10608         /* If we have an AMD 762 or VIA K8T800 chipset, write
10609          * reordering to the mailbox registers done by the host
10610          * controller can cause major troubles.  We read back from
10611          * every mailbox register write to force the writes to be
10612          * posted to the chip in order.
10613          */
10614         if (pci_dev_present(write_reorder_chipsets) &&
10615             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
10616                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
10617
10618         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
10619             tp->pci_lat_timer < 64) {
10620                 tp->pci_lat_timer = 64;
10621
10622                 cacheline_sz_reg  = ((tp->pci_cacheline_sz & 0xff) <<  0);
10623                 cacheline_sz_reg |= ((tp->pci_lat_timer    & 0xff) <<  8);
10624                 cacheline_sz_reg |= ((tp->pci_hdr_type     & 0xff) << 16);
10625                 cacheline_sz_reg |= ((tp->pci_bist         & 0xff) << 24);
10626
10627                 pci_write_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
10628                                        cacheline_sz_reg);
10629         }
10630
10631         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
10632                               &pci_state_reg);
10633
10634         if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0) {
10635                 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
10636
10637                 /* If this is a 5700 BX chipset, and we are in PCI-X
10638                  * mode, enable register write workaround.
10639                  *
10640                  * The workaround is to use indirect register accesses
10641                  * for all chip writes not to mailbox registers.
10642                  */
10643                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
10644                         u32 pm_reg;
10645                         u16 pci_cmd;
10646
10647                         tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
10648
10649                         /* The chip can have it's power management PCI config
10650                          * space registers clobbered due to this bug.
10651                          * So explicitly force the chip into D0 here.
10652                          */
10653                         pci_read_config_dword(tp->pdev, TG3PCI_PM_CTRL_STAT,
10654                                               &pm_reg);
10655                         pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
10656                         pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
10657                         pci_write_config_dword(tp->pdev, TG3PCI_PM_CTRL_STAT,
10658                                                pm_reg);
10659
10660                         /* Also, force SERR#/PERR# in PCI command. */
10661                         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
10662                         pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
10663                         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
10664                 }
10665         }
10666
10667         /* 5700 BX chips need to have their TX producer index mailboxes
10668          * written twice to workaround a bug.
10669          */
10670         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX)
10671                 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
10672
10673         /* Back to back register writes can cause problems on this chip,
10674          * the workaround is to read back all reg writes except those to
10675          * mailbox regs.  See tg3_write_indirect_reg32().
10676          *
10677          * PCI Express 5750_A0 rev chips need this workaround too.
10678          */
10679         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
10680             ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
10681              tp->pci_chip_rev_id == CHIPREV_ID_5750_A0))
10682                 tp->tg3_flags |= TG3_FLAG_5701_REG_WRITE_BUG;
10683
10684         if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
10685                 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
10686         if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
10687                 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
10688
10689         /* Chip-specific fixup from Broadcom driver */
10690         if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
10691             (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
10692                 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
10693                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
10694         }
10695
10696         /* Default fast path register access methods */
10697         tp->read32 = tg3_read32;
10698         tp->write32 = tg3_write32;
10699         tp->read32_mbox = tg3_read32;
10700         tp->write32_mbox = tg3_write32;
10701         tp->write32_tx_mbox = tg3_write32;
10702         tp->write32_rx_mbox = tg3_write32;
10703
10704         /* Various workaround register access methods */
10705         if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
10706                 tp->write32 = tg3_write_indirect_reg32;
10707         else if (tp->tg3_flags & TG3_FLAG_5701_REG_WRITE_BUG)
10708                 tp->write32 = tg3_write_flush_reg32;
10709
10710         if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
10711             (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
10712                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
10713                 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
10714                         tp->write32_rx_mbox = tg3_write_flush_reg32;
10715         }
10716
10717         if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
10718                 tp->read32 = tg3_read_indirect_reg32;
10719                 tp->write32 = tg3_write_indirect_reg32;
10720                 tp->read32_mbox = tg3_read_indirect_mbox;
10721                 tp->write32_mbox = tg3_write_indirect_mbox;
10722                 tp->write32_tx_mbox = tg3_write_indirect_mbox;
10723                 tp->write32_rx_mbox = tg3_write_indirect_mbox;
10724
10725                 iounmap(tp->regs);
10726                 tp->regs = NULL;
10727
10728                 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
10729                 pci_cmd &= ~PCI_COMMAND_MEMORY;
10730                 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
10731         }
10732         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
10733                 tp->read32_mbox = tg3_read32_mbox_5906;
10734                 tp->write32_mbox = tg3_write32_mbox_5906;
10735                 tp->write32_tx_mbox = tg3_write32_mbox_5906;
10736                 tp->write32_rx_mbox = tg3_write32_mbox_5906;
10737         }
10738
10739         if (tp->write32 == tg3_write_indirect_reg32 ||
10740             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
10741              (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10742               GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
10743                 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
10744
10745         /* Get eeprom hw config before calling tg3_set_power_state().
10746          * In particular, the TG3_FLG2_IS_NIC flag must be
10747          * determined before calling tg3_set_power_state() so that
10748          * we know whether or not to switch out of Vaux power.
10749          * When the flag is set, it means that GPIO1 is used for eeprom
10750          * write protect and also implies that it is a LOM where GPIOs
10751          * are not used to switch power.
10752          */
10753         tg3_get_eeprom_hw_cfg(tp);
10754
10755         /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
10756          * GPIO1 driven high will bring 5700's external PHY out of reset.
10757          * It is also used as eeprom write protect on LOMs.
10758          */
10759         tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
10760         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
10761             (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
10762                 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
10763                                        GRC_LCLCTRL_GPIO_OUTPUT1);
10764         /* Unused GPIO3 must be driven as output on 5752 because there
10765          * are no pull-up resistors on unused GPIO pins.
10766          */
10767         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
10768                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
10769
10770         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
10771                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
10772
10773         /* Force the chip into D0. */
10774         err = tg3_set_power_state(tp, PCI_D0);
10775         if (err) {
10776                 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
10777                        pci_name(tp->pdev));
10778                 return err;
10779         }
10780
10781         /* 5700 B0 chips do not support checksumming correctly due
10782          * to hardware bugs.
10783          */
10784         if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
10785                 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
10786
10787         /* Derive initial jumbo mode from MTU assigned in
10788          * ether_setup() via the alloc_etherdev() call
10789          */
10790         if (tp->dev->mtu > ETH_DATA_LEN &&
10791             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
10792                 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
10793
10794         /* Determine WakeOnLan speed to use. */
10795         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10796             tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
10797             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
10798             tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
10799                 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
10800         } else {
10801                 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
10802         }
10803
10804         /* A few boards don't want Ethernet@WireSpeed phy feature */
10805         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
10806             ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
10807              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
10808              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
10809             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) ||
10810             (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
10811                 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
10812
10813         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
10814             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
10815                 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
10816         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
10817                 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
10818
10819         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10820                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
10821                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787) {
10822                         if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
10823                             tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
10824                                 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
10825                         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
10826                                 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
10827                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
10828                         tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
10829         }
10830
10831         tp->coalesce_mode = 0;
10832         if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
10833             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
10834                 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
10835
10836         /* Initialize MAC MI mode, polling disabled. */
10837         tw32_f(MAC_MI_MODE, tp->mi_mode);
10838         udelay(80);
10839
10840         /* Initialize data/descriptor byte/word swapping. */
10841         val = tr32(GRC_MODE);
10842         val &= GRC_MODE_HOST_STACKUP;
10843         tw32(GRC_MODE, val | tp->grc_mode);
10844
10845         tg3_switch_clocks(tp);
10846
10847         /* Clear this out for sanity. */
10848         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
10849
10850         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
10851                               &pci_state_reg);
10852         if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
10853             (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
10854                 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
10855
10856                 if (chiprevid == CHIPREV_ID_5701_A0 ||
10857                     chiprevid == CHIPREV_ID_5701_B0 ||
10858                     chiprevid == CHIPREV_ID_5701_B2 ||
10859                     chiprevid == CHIPREV_ID_5701_B5) {
10860                         void __iomem *sram_base;
10861
10862                         /* Write some dummy words into the SRAM status block
10863                          * area, see if it reads back correctly.  If the return
10864                          * value is bad, force enable the PCIX workaround.
10865                          */
10866                         sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
10867
10868                         writel(0x00000000, sram_base);
10869                         writel(0x00000000, sram_base + 4);
10870                         writel(0xffffffff, sram_base + 4);
10871                         if (readl(sram_base) != 0x00000000)
10872                                 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
10873                 }
10874         }
10875
10876         udelay(50);
10877         tg3_nvram_init(tp);
10878
10879         grc_misc_cfg = tr32(GRC_MISC_CFG);
10880         grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
10881
10882         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
10883             (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
10884              grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
10885                 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
10886
10887         if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10888             (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
10889                 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
10890         if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
10891                 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
10892                                       HOSTCC_MODE_CLRTICK_TXBD);
10893
10894                 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
10895                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
10896                                        tp->misc_host_ctrl);
10897         }
10898
10899         /* these are limited to 10/100 only */
10900         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
10901              (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
10902             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
10903              tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
10904              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
10905               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
10906               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
10907             (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
10908              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
10909               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
10910               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
10911             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10912                 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
10913
10914         err = tg3_phy_probe(tp);
10915         if (err) {
10916                 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
10917                        pci_name(tp->pdev), err);
10918                 /* ... but do not return immediately ... */
10919         }
10920
10921         tg3_read_partno(tp);
10922         tg3_read_fw_ver(tp);
10923
10924         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
10925                 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
10926         } else {
10927                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
10928                         tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
10929                 else
10930                         tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
10931         }
10932
10933         /* 5700 {AX,BX} chips have a broken status block link
10934          * change bit implementation, so we must use the
10935          * status register in those cases.
10936          */
10937         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
10938                 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
10939         else
10940                 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
10941
10942         /* The led_ctrl is set during tg3_phy_probe, here we might
10943          * have to force the link status polling mechanism based
10944          * upon subsystem IDs.
10945          */
10946         if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
10947             !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
10948                 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
10949                                   TG3_FLAG_USE_LINKCHG_REG);
10950         }
10951
10952         /* For all SERDES we poll the MAC status register. */
10953         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10954                 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
10955         else
10956                 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
10957
10958         /* All chips before 5787 can get confused if TX buffers
10959          * straddle the 4GB address boundary in some cases.
10960          */
10961         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
10962             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
10963             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10964                 tp->dev->hard_start_xmit = tg3_start_xmit;
10965         else
10966                 tp->dev->hard_start_xmit = tg3_start_xmit_dma_bug;
10967
10968         tp->rx_offset = 2;
10969         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
10970             (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
10971                 tp->rx_offset = 0;
10972
10973         tp->rx_std_max_post = TG3_RX_RING_SIZE;
10974
10975         /* Increment the rx prod index on the rx std ring by at most
10976          * 8 for these chips to workaround hw errata.
10977          */
10978         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
10979             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
10980             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
10981                 tp->rx_std_max_post = 8;
10982
10983         /* By default, disable wake-on-lan.  User can change this
10984          * using ETHTOOL_SWOL.
10985          */
10986         tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
10987
10988         return err;
10989 }
10990
10991 #ifdef CONFIG_SPARC64
10992 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
10993 {
10994         struct net_device *dev = tp->dev;
10995         struct pci_dev *pdev = tp->pdev;
10996         struct pcidev_cookie *pcp = pdev->sysdata;
10997
10998         if (pcp != NULL) {
10999                 unsigned char *addr;
11000                 int len;
11001
11002                 addr = of_get_property(pcp->prom_node, "local-mac-address",
11003                                         &len);
11004                 if (addr && len == 6) {
11005                         memcpy(dev->dev_addr, addr, 6);
11006                         memcpy(dev->perm_addr, dev->dev_addr, 6);
11007                         return 0;
11008                 }
11009         }
11010         return -ENODEV;
11011 }
11012
11013 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
11014 {
11015         struct net_device *dev = tp->dev;
11016
11017         memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
11018         memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
11019         return 0;
11020 }
11021 #endif
11022
11023 static int __devinit tg3_get_device_address(struct tg3 *tp)
11024 {
11025         struct net_device *dev = tp->dev;
11026         u32 hi, lo, mac_offset;
11027         int addr_ok = 0;
11028
11029 #ifdef CONFIG_SPARC64
11030         if (!tg3_get_macaddr_sparc(tp))
11031                 return 0;
11032 #endif
11033
11034         mac_offset = 0x7c;
11035         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
11036             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
11037                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
11038                         mac_offset = 0xcc;
11039                 if (tg3_nvram_lock(tp))
11040                         tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
11041                 else
11042                         tg3_nvram_unlock(tp);
11043         }
11044         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11045                 mac_offset = 0x10;
11046
11047         /* First try to get it from MAC address mailbox. */
11048         tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
11049         if ((hi >> 16) == 0x484b) {
11050                 dev->dev_addr[0] = (hi >>  8) & 0xff;
11051                 dev->dev_addr[1] = (hi >>  0) & 0xff;
11052
11053                 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
11054                 dev->dev_addr[2] = (lo >> 24) & 0xff;
11055                 dev->dev_addr[3] = (lo >> 16) & 0xff;
11056                 dev->dev_addr[4] = (lo >>  8) & 0xff;
11057                 dev->dev_addr[5] = (lo >>  0) & 0xff;
11058
11059                 /* Some old bootcode may report a 0 MAC address in SRAM */
11060                 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
11061         }
11062         if (!addr_ok) {
11063                 /* Next, try NVRAM. */
11064                 if (!tg3_nvram_read(tp, mac_offset + 0, &hi) &&
11065                     !tg3_nvram_read(tp, mac_offset + 4, &lo)) {
11066                         dev->dev_addr[0] = ((hi >> 16) & 0xff);
11067                         dev->dev_addr[1] = ((hi >> 24) & 0xff);
11068                         dev->dev_addr[2] = ((lo >>  0) & 0xff);
11069                         dev->dev_addr[3] = ((lo >>  8) & 0xff);
11070                         dev->dev_addr[4] = ((lo >> 16) & 0xff);
11071                         dev->dev_addr[5] = ((lo >> 24) & 0xff);
11072                 }
11073                 /* Finally just fetch it out of the MAC control regs. */
11074                 else {
11075                         hi = tr32(MAC_ADDR_0_HIGH);
11076                         lo = tr32(MAC_ADDR_0_LOW);
11077
11078                         dev->dev_addr[5] = lo & 0xff;
11079                         dev->dev_addr[4] = (lo >> 8) & 0xff;
11080                         dev->dev_addr[3] = (lo >> 16) & 0xff;
11081                         dev->dev_addr[2] = (lo >> 24) & 0xff;
11082                         dev->dev_addr[1] = hi & 0xff;
11083                         dev->dev_addr[0] = (hi >> 8) & 0xff;
11084                 }
11085         }
11086
11087         if (!is_valid_ether_addr(&dev->dev_addr[0])) {
11088 #ifdef CONFIG_SPARC64
11089                 if (!tg3_get_default_macaddr_sparc(tp))
11090                         return 0;
11091 #endif
11092                 return -EINVAL;
11093         }
11094         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
11095         return 0;
11096 }
11097
11098 #define BOUNDARY_SINGLE_CACHELINE       1
11099 #define BOUNDARY_MULTI_CACHELINE        2
11100
11101 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
11102 {
11103         int cacheline_size;
11104         u8 byte;
11105         int goal;
11106
11107         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
11108         if (byte == 0)
11109                 cacheline_size = 1024;
11110         else
11111                 cacheline_size = (int) byte * 4;
11112
11113         /* On 5703 and later chips, the boundary bits have no
11114          * effect.
11115          */
11116         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11117             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
11118             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
11119                 goto out;
11120
11121 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
11122         goal = BOUNDARY_MULTI_CACHELINE;
11123 #else
11124 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
11125         goal = BOUNDARY_SINGLE_CACHELINE;
11126 #else
11127         goal = 0;
11128 #endif
11129 #endif
11130
11131         if (!goal)
11132                 goto out;
11133
11134         /* PCI controllers on most RISC systems tend to disconnect
11135          * when a device tries to burst across a cache-line boundary.
11136          * Therefore, letting tg3 do so just wastes PCI bandwidth.
11137          *
11138          * Unfortunately, for PCI-E there are only limited
11139          * write-side controls for this, and thus for reads
11140          * we will still get the disconnects.  We'll also waste
11141          * these PCI cycles for both read and write for chips
11142          * other than 5700 and 5701 which do not implement the
11143          * boundary bits.
11144          */
11145         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
11146             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
11147                 switch (cacheline_size) {
11148                 case 16:
11149                 case 32:
11150                 case 64:
11151                 case 128:
11152                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
11153                                 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
11154                                         DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
11155                         } else {
11156                                 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
11157                                         DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
11158                         }
11159                         break;
11160
11161                 case 256:
11162                         val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
11163                                 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
11164                         break;
11165
11166                 default:
11167                         val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
11168                                 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
11169                         break;
11170                 };
11171         } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11172                 switch (cacheline_size) {
11173                 case 16:
11174                 case 32:
11175                 case 64:
11176                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
11177                                 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
11178                                 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
11179                                 break;
11180                         }
11181                         /* fallthrough */
11182                 case 128:
11183                 default:
11184                         val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
11185                         val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
11186                         break;
11187                 };
11188         } else {
11189                 switch (cacheline_size) {
11190                 case 16:
11191                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
11192                                 val |= (DMA_RWCTRL_READ_BNDRY_16 |
11193                                         DMA_RWCTRL_WRITE_BNDRY_16);
11194                                 break;
11195                         }
11196                         /* fallthrough */
11197                 case 32:
11198                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
11199                                 val |= (DMA_RWCTRL_READ_BNDRY_32 |
11200                                         DMA_RWCTRL_WRITE_BNDRY_32);
11201                                 break;
11202                         }
11203                         /* fallthrough */
11204                 case 64:
11205                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
11206                                 val |= (DMA_RWCTRL_READ_BNDRY_64 |
11207                                         DMA_RWCTRL_WRITE_BNDRY_64);
11208                                 break;
11209                         }
11210                         /* fallthrough */
11211                 case 128:
11212                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
11213                                 val |= (DMA_RWCTRL_READ_BNDRY_128 |
11214                                         DMA_RWCTRL_WRITE_BNDRY_128);
11215                                 break;
11216                         }
11217                         /* fallthrough */
11218                 case 256:
11219                         val |= (DMA_RWCTRL_READ_BNDRY_256 |
11220                                 DMA_RWCTRL_WRITE_BNDRY_256);
11221                         break;
11222                 case 512:
11223                         val |= (DMA_RWCTRL_READ_BNDRY_512 |
11224                                 DMA_RWCTRL_WRITE_BNDRY_512);
11225                         break;
11226                 case 1024:
11227                 default:
11228                         val |= (DMA_RWCTRL_READ_BNDRY_1024 |
11229                                 DMA_RWCTRL_WRITE_BNDRY_1024);
11230                         break;
11231                 };
11232         }
11233
11234 out:
11235         return val;
11236 }
11237
11238 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
11239 {
11240         struct tg3_internal_buffer_desc test_desc;
11241         u32 sram_dma_descs;
11242         int i, ret;
11243
11244         sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
11245
11246         tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
11247         tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
11248         tw32(RDMAC_STATUS, 0);
11249         tw32(WDMAC_STATUS, 0);
11250
11251         tw32(BUFMGR_MODE, 0);
11252         tw32(FTQ_RESET, 0);
11253
11254         test_desc.addr_hi = ((u64) buf_dma) >> 32;
11255         test_desc.addr_lo = buf_dma & 0xffffffff;
11256         test_desc.nic_mbuf = 0x00002100;
11257         test_desc.len = size;
11258
11259         /*
11260          * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
11261          * the *second* time the tg3 driver was getting loaded after an
11262          * initial scan.
11263          *
11264          * Broadcom tells me:
11265          *   ...the DMA engine is connected to the GRC block and a DMA
11266          *   reset may affect the GRC block in some unpredictable way...
11267          *   The behavior of resets to individual blocks has not been tested.
11268          *
11269          * Broadcom noted the GRC reset will also reset all sub-components.
11270          */
11271         if (to_device) {
11272                 test_desc.cqid_sqid = (13 << 8) | 2;
11273
11274                 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
11275                 udelay(40);
11276         } else {
11277                 test_desc.cqid_sqid = (16 << 8) | 7;
11278
11279                 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
11280                 udelay(40);
11281         }
11282         test_desc.flags = 0x00000005;
11283
11284         for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
11285                 u32 val;
11286
11287                 val = *(((u32 *)&test_desc) + i);
11288                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
11289                                        sram_dma_descs + (i * sizeof(u32)));
11290                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
11291         }
11292         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
11293
11294         if (to_device) {
11295                 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
11296         } else {
11297                 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
11298         }
11299
11300         ret = -ENODEV;
11301         for (i = 0; i < 40; i++) {
11302                 u32 val;
11303
11304                 if (to_device)
11305                         val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
11306                 else
11307                         val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
11308                 if ((val & 0xffff) == sram_dma_descs) {
11309                         ret = 0;
11310                         break;
11311                 }
11312
11313                 udelay(100);
11314         }
11315
11316         return ret;
11317 }
11318
11319 #define TEST_BUFFER_SIZE        0x2000
11320
11321 static int __devinit tg3_test_dma(struct tg3 *tp)
11322 {
11323         dma_addr_t buf_dma;
11324         u32 *buf, saved_dma_rwctrl;
11325         int ret;
11326
11327         buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
11328         if (!buf) {
11329                 ret = -ENOMEM;
11330                 goto out_nofree;
11331         }
11332
11333         tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
11334                           (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
11335
11336         tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
11337
11338         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11339                 /* DMA read watermark not used on PCIE */
11340                 tp->dma_rwctrl |= 0x00180000;
11341         } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
11342                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
11343                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
11344                         tp->dma_rwctrl |= 0x003f0000;
11345                 else
11346                         tp->dma_rwctrl |= 0x003f000f;
11347         } else {
11348                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
11349                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
11350                         u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
11351                         u32 read_water = 0x7;
11352
11353                         /* If the 5704 is behind the EPB bridge, we can
11354                          * do the less restrictive ONE_DMA workaround for
11355                          * better performance.
11356                          */
11357                         if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
11358                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
11359                                 tp->dma_rwctrl |= 0x8000;
11360                         else if (ccval == 0x6 || ccval == 0x7)
11361                                 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
11362
11363                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
11364                                 read_water = 4;
11365                         /* Set bit 23 to enable PCIX hw bug fix */
11366                         tp->dma_rwctrl |=
11367                                 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
11368                                 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
11369                                 (1 << 23);
11370                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
11371                         /* 5780 always in PCIX mode */
11372                         tp->dma_rwctrl |= 0x00144000;
11373                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
11374                         /* 5714 always in PCIX mode */
11375                         tp->dma_rwctrl |= 0x00148000;
11376                 } else {
11377                         tp->dma_rwctrl |= 0x001b000f;
11378                 }
11379         }
11380
11381         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
11382             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
11383                 tp->dma_rwctrl &= 0xfffffff0;
11384
11385         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11386             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
11387                 /* Remove this if it causes problems for some boards. */
11388                 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
11389
11390                 /* On 5700/5701 chips, we need to set this bit.
11391                  * Otherwise the chip will issue cacheline transactions
11392                  * to streamable DMA memory with not all the byte
11393                  * enables turned on.  This is an error on several
11394                  * RISC PCI controllers, in particular sparc64.
11395                  *
11396                  * On 5703/5704 chips, this bit has been reassigned
11397                  * a different meaning.  In particular, it is used
11398                  * on those chips to enable a PCI-X workaround.
11399                  */
11400                 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
11401         }
11402
11403         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
11404
11405 #if 0
11406         /* Unneeded, already done by tg3_get_invariants.  */
11407         tg3_switch_clocks(tp);
11408 #endif
11409
11410         ret = 0;
11411         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11412             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
11413                 goto out;
11414
11415         /* It is best to perform DMA test with maximum write burst size
11416          * to expose the 5700/5701 write DMA bug.
11417          */
11418         saved_dma_rwctrl = tp->dma_rwctrl;
11419         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
11420         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
11421
11422         while (1) {
11423                 u32 *p = buf, i;
11424
11425                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
11426                         p[i] = i;
11427
11428                 /* Send the buffer to the chip. */
11429                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
11430                 if (ret) {
11431                         printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
11432                         break;
11433                 }
11434
11435 #if 0
11436                 /* validate data reached card RAM correctly. */
11437                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
11438                         u32 val;
11439                         tg3_read_mem(tp, 0x2100 + (i*4), &val);
11440                         if (le32_to_cpu(val) != p[i]) {
11441                                 printk(KERN_ERR "  tg3_test_dma()  Card buffer corrupted on write! (%d != %d)\n", val, i);
11442                                 /* ret = -ENODEV here? */
11443                         }
11444                         p[i] = 0;
11445                 }
11446 #endif
11447                 /* Now read it back. */
11448                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
11449                 if (ret) {
11450                         printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
11451
11452                         break;
11453                 }
11454
11455                 /* Verify it. */
11456                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
11457                         if (p[i] == i)
11458                                 continue;
11459
11460                         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
11461                             DMA_RWCTRL_WRITE_BNDRY_16) {
11462                                 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
11463                                 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
11464                                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
11465                                 break;
11466                         } else {
11467                                 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
11468                                 ret = -ENODEV;
11469                                 goto out;
11470                         }
11471                 }
11472
11473                 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
11474                         /* Success. */
11475                         ret = 0;
11476                         break;
11477                 }
11478         }
11479         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
11480             DMA_RWCTRL_WRITE_BNDRY_16) {
11481                 static struct pci_device_id dma_wait_state_chipsets[] = {
11482                         { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
11483                                      PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
11484                         { },
11485                 };
11486
11487                 /* DMA test passed without adjusting DMA boundary,
11488                  * now look for chipsets that are known to expose the
11489                  * DMA bug without failing the test.
11490                  */
11491                 if (pci_dev_present(dma_wait_state_chipsets)) {
11492                         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
11493                         tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
11494                 }
11495                 else
11496                         /* Safe to use the calculated DMA boundary. */
11497                         tp->dma_rwctrl = saved_dma_rwctrl;
11498
11499                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
11500         }
11501
11502 out:
11503         pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
11504 out_nofree:
11505         return ret;
11506 }
11507
11508 static void __devinit tg3_init_link_config(struct tg3 *tp)
11509 {
11510         tp->link_config.advertising =
11511                 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
11512                  ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
11513                  ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
11514                  ADVERTISED_Autoneg | ADVERTISED_MII);
11515         tp->link_config.speed = SPEED_INVALID;
11516         tp->link_config.duplex = DUPLEX_INVALID;
11517         tp->link_config.autoneg = AUTONEG_ENABLE;
11518         tp->link_config.active_speed = SPEED_INVALID;
11519         tp->link_config.active_duplex = DUPLEX_INVALID;
11520         tp->link_config.phy_is_low_power = 0;
11521         tp->link_config.orig_speed = SPEED_INVALID;
11522         tp->link_config.orig_duplex = DUPLEX_INVALID;
11523         tp->link_config.orig_autoneg = AUTONEG_INVALID;
11524 }
11525
11526 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
11527 {
11528         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
11529                 tp->bufmgr_config.mbuf_read_dma_low_water =
11530                         DEFAULT_MB_RDMA_LOW_WATER_5705;
11531                 tp->bufmgr_config.mbuf_mac_rx_low_water =
11532                         DEFAULT_MB_MACRX_LOW_WATER_5705;
11533                 tp->bufmgr_config.mbuf_high_water =
11534                         DEFAULT_MB_HIGH_WATER_5705;
11535                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
11536                         tp->bufmgr_config.mbuf_mac_rx_low_water =
11537                                 DEFAULT_MB_MACRX_LOW_WATER_5906;
11538                         tp->bufmgr_config.mbuf_high_water =
11539                                 DEFAULT_MB_HIGH_WATER_5906;
11540                 }
11541
11542                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
11543                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
11544                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
11545                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
11546                 tp->bufmgr_config.mbuf_high_water_jumbo =
11547                         DEFAULT_MB_HIGH_WATER_JUMBO_5780;
11548         } else {
11549                 tp->bufmgr_config.mbuf_read_dma_low_water =
11550                         DEFAULT_MB_RDMA_LOW_WATER;
11551                 tp->bufmgr_config.mbuf_mac_rx_low_water =
11552                         DEFAULT_MB_MACRX_LOW_WATER;
11553                 tp->bufmgr_config.mbuf_high_water =
11554                         DEFAULT_MB_HIGH_WATER;
11555
11556                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
11557                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
11558                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
11559                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
11560                 tp->bufmgr_config.mbuf_high_water_jumbo =
11561                         DEFAULT_MB_HIGH_WATER_JUMBO;
11562         }
11563
11564         tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
11565         tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
11566 }
11567
11568 static char * __devinit tg3_phy_string(struct tg3 *tp)
11569 {
11570         switch (tp->phy_id & PHY_ID_MASK) {
11571         case PHY_ID_BCM5400:    return "5400";
11572         case PHY_ID_BCM5401:    return "5401";
11573         case PHY_ID_BCM5411:    return "5411";
11574         case PHY_ID_BCM5701:    return "5701";
11575         case PHY_ID_BCM5703:    return "5703";
11576         case PHY_ID_BCM5704:    return "5704";
11577         case PHY_ID_BCM5705:    return "5705";
11578         case PHY_ID_BCM5750:    return "5750";
11579         case PHY_ID_BCM5752:    return "5752";
11580         case PHY_ID_BCM5714:    return "5714";
11581         case PHY_ID_BCM5780:    return "5780";
11582         case PHY_ID_BCM5755:    return "5755";
11583         case PHY_ID_BCM5787:    return "5787";
11584         case PHY_ID_BCM5756:    return "5722/5756";
11585         case PHY_ID_BCM5906:    return "5906";
11586         case PHY_ID_BCM8002:    return "8002/serdes";
11587         case 0:                 return "serdes";
11588         default:                return "unknown";
11589         };
11590 }
11591
11592 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
11593 {
11594         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11595                 strcpy(str, "PCI Express");
11596                 return str;
11597         } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
11598                 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
11599
11600                 strcpy(str, "PCIX:");
11601
11602                 if ((clock_ctrl == 7) ||
11603                     ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
11604                      GRC_MISC_CFG_BOARD_ID_5704CIOBE))
11605                         strcat(str, "133MHz");
11606                 else if (clock_ctrl == 0)
11607                         strcat(str, "33MHz");
11608                 else if (clock_ctrl == 2)
11609                         strcat(str, "50MHz");
11610                 else if (clock_ctrl == 4)
11611                         strcat(str, "66MHz");
11612                 else if (clock_ctrl == 6)
11613                         strcat(str, "100MHz");
11614         } else {
11615                 strcpy(str, "PCI:");
11616                 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
11617                         strcat(str, "66MHz");
11618                 else
11619                         strcat(str, "33MHz");
11620         }
11621         if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
11622                 strcat(str, ":32-bit");
11623         else
11624                 strcat(str, ":64-bit");
11625         return str;
11626 }
11627
11628 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
11629 {
11630         struct pci_dev *peer;
11631         unsigned int func, devnr = tp->pdev->devfn & ~7;
11632
11633         for (func = 0; func < 8; func++) {
11634                 peer = pci_get_slot(tp->pdev->bus, devnr | func);
11635                 if (peer && peer != tp->pdev)
11636                         break;
11637                 pci_dev_put(peer);
11638         }
11639         /* 5704 can be configured in single-port mode, set peer to
11640          * tp->pdev in that case.
11641          */
11642         if (!peer) {
11643                 peer = tp->pdev;
11644                 return peer;
11645         }
11646
11647         /*
11648          * We don't need to keep the refcount elevated; there's no way
11649          * to remove one half of this device without removing the other
11650          */
11651         pci_dev_put(peer);
11652
11653         return peer;
11654 }
11655
11656 static void __devinit tg3_init_coal(struct tg3 *tp)
11657 {
11658         struct ethtool_coalesce *ec = &tp->coal;
11659
11660         memset(ec, 0, sizeof(*ec));
11661         ec->cmd = ETHTOOL_GCOALESCE;
11662         ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
11663         ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
11664         ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
11665         ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
11666         ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
11667         ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
11668         ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
11669         ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
11670         ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
11671
11672         if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
11673                                  HOSTCC_MODE_CLRTICK_TXBD)) {
11674                 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
11675                 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
11676                 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
11677                 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
11678         }
11679
11680         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
11681                 ec->rx_coalesce_usecs_irq = 0;
11682                 ec->tx_coalesce_usecs_irq = 0;
11683                 ec->stats_block_coalesce_usecs = 0;
11684         }
11685 }
11686
11687 static int __devinit tg3_init_one(struct pci_dev *pdev,
11688                                   const struct pci_device_id *ent)
11689 {
11690         static int tg3_version_printed = 0;
11691         unsigned long tg3reg_base, tg3reg_len;
11692         struct net_device *dev;
11693         struct tg3 *tp;
11694         int i, err, pm_cap;
11695         char str[40];
11696         u64 dma_mask, persist_dma_mask;
11697
11698         if (tg3_version_printed++ == 0)
11699                 printk(KERN_INFO "%s", version);
11700
11701         err = pci_enable_device(pdev);
11702         if (err) {
11703                 printk(KERN_ERR PFX "Cannot enable PCI device, "
11704                        "aborting.\n");
11705                 return err;
11706         }
11707
11708         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
11709                 printk(KERN_ERR PFX "Cannot find proper PCI device "
11710                        "base address, aborting.\n");
11711                 err = -ENODEV;
11712                 goto err_out_disable_pdev;
11713         }
11714
11715         err = pci_request_regions(pdev, DRV_MODULE_NAME);
11716         if (err) {
11717                 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
11718                        "aborting.\n");
11719                 goto err_out_disable_pdev;
11720         }
11721
11722         pci_set_master(pdev);
11723
11724         /* Find power-management capability. */
11725         pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
11726         if (pm_cap == 0) {
11727                 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
11728                        "aborting.\n");
11729                 err = -EIO;
11730                 goto err_out_free_res;
11731         }
11732
11733         tg3reg_base = pci_resource_start(pdev, 0);
11734         tg3reg_len = pci_resource_len(pdev, 0);
11735
11736         dev = alloc_etherdev(sizeof(*tp));
11737         if (!dev) {
11738                 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
11739                 err = -ENOMEM;
11740                 goto err_out_free_res;
11741         }
11742
11743         SET_MODULE_OWNER(dev);
11744         SET_NETDEV_DEV(dev, &pdev->dev);
11745
11746 #if TG3_VLAN_TAG_USED
11747         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
11748         dev->vlan_rx_register = tg3_vlan_rx_register;
11749         dev->vlan_rx_kill_vid = tg3_vlan_rx_kill_vid;
11750 #endif
11751
11752         tp = netdev_priv(dev);
11753         tp->pdev = pdev;
11754         tp->dev = dev;
11755         tp->pm_cap = pm_cap;
11756         tp->mac_mode = TG3_DEF_MAC_MODE;
11757         tp->rx_mode = TG3_DEF_RX_MODE;
11758         tp->tx_mode = TG3_DEF_TX_MODE;
11759         tp->mi_mode = MAC_MI_MODE_BASE;
11760         if (tg3_debug > 0)
11761                 tp->msg_enable = tg3_debug;
11762         else
11763                 tp->msg_enable = TG3_DEF_MSG_ENABLE;
11764
11765         /* The word/byte swap controls here control register access byte
11766          * swapping.  DMA data byte swapping is controlled in the GRC_MODE
11767          * setting below.
11768          */
11769         tp->misc_host_ctrl =
11770                 MISC_HOST_CTRL_MASK_PCI_INT |
11771                 MISC_HOST_CTRL_WORD_SWAP |
11772                 MISC_HOST_CTRL_INDIR_ACCESS |
11773                 MISC_HOST_CTRL_PCISTATE_RW;
11774
11775         /* The NONFRM (non-frame) byte/word swap controls take effect
11776          * on descriptor entries, anything which isn't packet data.
11777          *
11778          * The StrongARM chips on the board (one for tx, one for rx)
11779          * are running in big-endian mode.
11780          */
11781         tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
11782                         GRC_MODE_WSWAP_NONFRM_DATA);
11783 #ifdef __BIG_ENDIAN
11784         tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
11785 #endif
11786         spin_lock_init(&tp->lock);
11787         spin_lock_init(&tp->indirect_lock);
11788         INIT_WORK(&tp->reset_task, tg3_reset_task);
11789
11790         tp->regs = ioremap_nocache(tg3reg_base, tg3reg_len);
11791         if (tp->regs == 0UL) {
11792                 printk(KERN_ERR PFX "Cannot map device registers, "
11793                        "aborting.\n");
11794                 err = -ENOMEM;
11795                 goto err_out_free_dev;
11796         }
11797
11798         tg3_init_link_config(tp);
11799
11800         tp->rx_pending = TG3_DEF_RX_RING_PENDING;
11801         tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
11802         tp->tx_pending = TG3_DEF_TX_RING_PENDING;
11803
11804         dev->open = tg3_open;
11805         dev->stop = tg3_close;
11806         dev->get_stats = tg3_get_stats;
11807         dev->set_multicast_list = tg3_set_rx_mode;
11808         dev->set_mac_address = tg3_set_mac_addr;
11809         dev->do_ioctl = tg3_ioctl;
11810         dev->tx_timeout = tg3_tx_timeout;
11811         dev->poll = tg3_poll;
11812         dev->ethtool_ops = &tg3_ethtool_ops;
11813         dev->weight = 64;
11814         dev->watchdog_timeo = TG3_TX_TIMEOUT;
11815         dev->change_mtu = tg3_change_mtu;
11816         dev->irq = pdev->irq;
11817 #ifdef CONFIG_NET_POLL_CONTROLLER
11818         dev->poll_controller = tg3_poll_controller;
11819 #endif
11820
11821         err = tg3_get_invariants(tp);
11822         if (err) {
11823                 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
11824                        "aborting.\n");
11825                 goto err_out_iounmap;
11826         }
11827
11828         /* The EPB bridge inside 5714, 5715, and 5780 and any
11829          * device behind the EPB cannot support DMA addresses > 40-bit.
11830          * On 64-bit systems with IOMMU, use 40-bit dma_mask.
11831          * On 64-bit systems without IOMMU, use 64-bit dma_mask and
11832          * do DMA address check in tg3_start_xmit().
11833          */
11834         if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
11835                 persist_dma_mask = dma_mask = DMA_32BIT_MASK;
11836         else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
11837                 persist_dma_mask = dma_mask = DMA_40BIT_MASK;
11838 #ifdef CONFIG_HIGHMEM
11839                 dma_mask = DMA_64BIT_MASK;
11840 #endif
11841         } else
11842                 persist_dma_mask = dma_mask = DMA_64BIT_MASK;
11843
11844         /* Configure DMA attributes. */
11845         if (dma_mask > DMA_32BIT_MASK) {
11846                 err = pci_set_dma_mask(pdev, dma_mask);
11847                 if (!err) {
11848                         dev->features |= NETIF_F_HIGHDMA;
11849                         err = pci_set_consistent_dma_mask(pdev,
11850                                                           persist_dma_mask);
11851                         if (err < 0) {
11852                                 printk(KERN_ERR PFX "Unable to obtain 64 bit "
11853                                        "DMA for consistent allocations\n");
11854                                 goto err_out_iounmap;
11855                         }
11856                 }
11857         }
11858         if (err || dma_mask == DMA_32BIT_MASK) {
11859                 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
11860                 if (err) {
11861                         printk(KERN_ERR PFX "No usable DMA configuration, "
11862                                "aborting.\n");
11863                         goto err_out_iounmap;
11864                 }
11865         }
11866
11867         tg3_init_bufmgr_config(tp);
11868
11869         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
11870                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
11871         }
11872         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11873             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
11874             tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
11875             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
11876             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
11877                 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
11878         } else {
11879                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG;
11880         }
11881
11882         /* TSO is on by default on chips that support hardware TSO.
11883          * Firmware TSO on older chips gives lower performance, so it
11884          * is off by default, but can be enabled using ethtool.
11885          */
11886         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
11887                 dev->features |= NETIF_F_TSO;
11888                 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) &&
11889                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906))
11890                         dev->features |= NETIF_F_TSO6;
11891         }
11892
11893
11894         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
11895             !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
11896             !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
11897                 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
11898                 tp->rx_pending = 63;
11899         }
11900
11901         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
11902             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714))
11903                 tp->pdev_peer = tg3_find_peer(tp);
11904
11905         err = tg3_get_device_address(tp);
11906         if (err) {
11907                 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
11908                        "aborting.\n");
11909                 goto err_out_iounmap;
11910         }
11911
11912         /*
11913          * Reset chip in case UNDI or EFI driver did not shutdown
11914          * DMA self test will enable WDMAC and we'll see (spurious)
11915          * pending DMA on the PCI bus at that point.
11916          */
11917         if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
11918             (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
11919                 pci_save_state(tp->pdev);
11920                 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
11921                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11922         }
11923
11924         err = tg3_test_dma(tp);
11925         if (err) {
11926                 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
11927                 goto err_out_iounmap;
11928         }
11929
11930         /* Tigon3 can do ipv4 only... and some chips have buggy
11931          * checksumming.
11932          */
11933         if ((tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) == 0) {
11934                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
11935                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
11936                         dev->features |= NETIF_F_HW_CSUM;
11937                 else
11938                         dev->features |= NETIF_F_IP_CSUM;
11939                 dev->features |= NETIF_F_SG;
11940                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
11941         } else
11942                 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
11943
11944         /* flow control autonegotiation is default behavior */
11945         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
11946
11947         tg3_init_coal(tp);
11948
11949         /* Now that we have fully setup the chip, save away a snapshot
11950          * of the PCI config space.  We need to restore this after
11951          * GRC_MISC_CFG core clock resets and some resume events.
11952          */
11953         pci_save_state(tp->pdev);
11954
11955         pci_set_drvdata(pdev, dev);
11956
11957         err = register_netdev(dev);
11958         if (err) {
11959                 printk(KERN_ERR PFX "Cannot register net device, "
11960                        "aborting.\n");
11961                 goto err_out_iounmap;
11962         }
11963
11964         printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x PHY(%s)] (%s) %s Ethernet ",
11965                dev->name,
11966                tp->board_part_number,
11967                tp->pci_chip_rev_id,
11968                tg3_phy_string(tp),
11969                tg3_bus_string(tp, str),
11970                ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
11971                 ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
11972                  "10/100/1000Base-T")));
11973
11974         for (i = 0; i < 6; i++)
11975                 printk("%2.2x%c", dev->dev_addr[i],
11976                        i == 5 ? '\n' : ':');
11977
11978         printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] "
11979                "MIirq[%d] ASF[%d] WireSpeed[%d] TSOcap[%d]\n",
11980                dev->name,
11981                (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
11982                (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
11983                (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
11984                (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
11985                (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0,
11986                (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
11987         printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
11988                dev->name, tp->dma_rwctrl,
11989                (pdev->dma_mask == DMA_32BIT_MASK) ? 32 :
11990                 (((u64) pdev->dma_mask == DMA_40BIT_MASK) ? 40 : 64));
11991
11992         return 0;
11993
11994 err_out_iounmap:
11995         if (tp->regs) {
11996                 iounmap(tp->regs);
11997                 tp->regs = NULL;
11998         }
11999
12000 err_out_free_dev:
12001         free_netdev(dev);
12002
12003 err_out_free_res:
12004         pci_release_regions(pdev);
12005
12006 err_out_disable_pdev:
12007         pci_disable_device(pdev);
12008         pci_set_drvdata(pdev, NULL);
12009         return err;
12010 }
12011
12012 static void __devexit tg3_remove_one(struct pci_dev *pdev)
12013 {
12014         struct net_device *dev = pci_get_drvdata(pdev);
12015
12016         if (dev) {
12017                 struct tg3 *tp = netdev_priv(dev);
12018
12019                 flush_scheduled_work();
12020                 unregister_netdev(dev);
12021                 if (tp->regs) {
12022                         iounmap(tp->regs);
12023                         tp->regs = NULL;
12024                 }
12025                 free_netdev(dev);
12026                 pci_release_regions(pdev);
12027                 pci_disable_device(pdev);
12028                 pci_set_drvdata(pdev, NULL);
12029         }
12030 }
12031
12032 static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
12033 {
12034         struct net_device *dev = pci_get_drvdata(pdev);
12035         struct tg3 *tp = netdev_priv(dev);
12036         int err;
12037
12038         if (!netif_running(dev))
12039                 return 0;
12040
12041         flush_scheduled_work();
12042         tg3_netif_stop(tp);
12043
12044         del_timer_sync(&tp->timer);
12045
12046         tg3_full_lock(tp, 1);
12047         tg3_disable_ints(tp);
12048         tg3_full_unlock(tp);
12049
12050         netif_device_detach(dev);
12051
12052         tg3_full_lock(tp, 0);
12053         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
12054         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
12055         tg3_full_unlock(tp);
12056
12057         /* Save MSI address and data for resume.  */
12058         pci_save_state(pdev);
12059
12060         err = tg3_set_power_state(tp, pci_choose_state(pdev, state));
12061         if (err) {
12062                 tg3_full_lock(tp, 0);
12063
12064                 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
12065                 if (tg3_restart_hw(tp, 1))
12066                         goto out;
12067
12068                 tp->timer.expires = jiffies + tp->timer_offset;
12069                 add_timer(&tp->timer);
12070
12071                 netif_device_attach(dev);
12072                 tg3_netif_start(tp);
12073
12074 out:
12075                 tg3_full_unlock(tp);
12076         }
12077
12078         return err;
12079 }
12080
12081 static int tg3_resume(struct pci_dev *pdev)
12082 {
12083         struct net_device *dev = pci_get_drvdata(pdev);
12084         struct tg3 *tp = netdev_priv(dev);
12085         int err;
12086
12087         if (!netif_running(dev))
12088                 return 0;
12089
12090         pci_restore_state(tp->pdev);
12091
12092         err = tg3_set_power_state(tp, PCI_D0);
12093         if (err)
12094                 return err;
12095
12096         netif_device_attach(dev);
12097
12098         tg3_full_lock(tp, 0);
12099
12100         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
12101         err = tg3_restart_hw(tp, 1);
12102         if (err)
12103                 goto out;
12104
12105         tp->timer.expires = jiffies + tp->timer_offset;
12106         add_timer(&tp->timer);
12107
12108         tg3_netif_start(tp);
12109
12110 out:
12111         tg3_full_unlock(tp);
12112
12113         return err;
12114 }
12115
12116 static struct pci_driver tg3_driver = {
12117         .name           = DRV_MODULE_NAME,
12118         .id_table       = tg3_pci_tbl,
12119         .probe          = tg3_init_one,
12120         .remove         = __devexit_p(tg3_remove_one),
12121         .suspend        = tg3_suspend,
12122         .resume         = tg3_resume
12123 };
12124
12125 static int __init tg3_init(void)
12126 {
12127         return pci_register_driver(&tg3_driver);
12128 }
12129
12130 static void __exit tg3_cleanup(void)
12131 {
12132         pci_unregister_driver(&tg3_driver);
12133 }
12134
12135 module_init(tg3_init);
12136 module_exit(tg3_cleanup);