SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/net/tg3.c

   1 /*
   2  * tg3.c: Broadcom Tigon3 ethernet driver.
   3  *
   4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
   5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
   6  * Copyright (C) 2004 Sun Microsystems Inc.
   7  * Copyright (C) 2005-2010 Broadcom Corporation.
   8  *
   9  * Firmware is:
  10  *      Derived from proprietary unpublished source code,
  11  *      Copyright (C) 2000-2003 Broadcom Corporation.
  12  *
  13  *      Permission is hereby granted for the distribution of this firmware
  14  *      data in hexadecimal or equivalent format, provided this copyright
  15  *      notice is accompanying it.
  16  */
  17
  18
  19 #include <linux/module.h>
  20 #include <linux/moduleparam.h>
  21 #include <linux/kernel.h>
  22 #include <linux/types.h>
  23 #include <linux/compiler.h>
  24 #include <linux/slab.h>
  25 #include <linux/delay.h>
  26 #include <linux/in.h>
  27 #include <linux/init.h>
  28 #include <linux/ioport.h>
  29 #include <linux/pci.h>
  30 #include <linux/netdevice.h>
  31 #include <linux/etherdevice.h>
  32 #include <linux/skbuff.h>
  33 #include <linux/ethtool.h>
  34 #include <linux/mii.h>
  35 #include <linux/phy.h>
  36 #include <linux/brcmphy.h>
  37 #include <linux/if_vlan.h>
  38 #include <linux/ip.h>
  39 #include <linux/tcp.h>
  40 #include <linux/workqueue.h>
  41 #include <linux/prefetch.h>
  42 #include <linux/dma-mapping.h>
  43 #include <linux/firmware.h>
  44
  45 #include <net/checksum.h>
  46 #include <net/ip.h>
  47
  48 #include <asm/system.h>
  49 #include <asm/io.h>
  50 #include <asm/byteorder.h>
  51 #include <asm/uaccess.h>
  52
  53 #ifdef CONFIG_SPARC
  54 #include <asm/idprom.h>
  55 #include <asm/prom.h>
  56 #endif
  57
  58 #define BAR_0   0
  59 #define BAR_2   2
  60
  61 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  62 #define TG3_VLAN_TAG_USED 1
  63 #else
  64 #define TG3_VLAN_TAG_USED 0
  65 #endif
  66
  67 #include "tg3.h"
  68
  69 #define DRV_MODULE_NAME         "tg3"
  70 #define PFX DRV_MODULE_NAME     ": "
  71 #define DRV_MODULE_VERSION      "3.106"
  72 #define DRV_MODULE_RELDATE      "January 12, 2010"
  73
  74 #define TG3_DEF_MAC_MODE        0
  75 #define TG3_DEF_RX_MODE         0
  76 #define TG3_DEF_TX_MODE         0
  77 #define TG3_DEF_MSG_ENABLE        \
  78         (NETIF_MSG_DRV          | \
  79          NETIF_MSG_PROBE        | \
  80          NETIF_MSG_LINK         | \
  81          NETIF_MSG_TIMER        | \
  82          NETIF_MSG_IFDOWN       | \
  83          NETIF_MSG_IFUP         | \
  84          NETIF_MSG_RX_ERR       | \
  85          NETIF_MSG_TX_ERR)
  86
  87 /* length of time before we decide the hardware is borked,
  88  * and dev->tx_timeout() should be called to fix the problem
  89  */
  90 #define TG3_TX_TIMEOUT                  (5 * HZ)
  91
  92 /* hardware minimum and maximum for a single frame's data payload */
  93 #define TG3_MIN_MTU                     60
  94 #define TG3_MAX_MTU(tp) \
  95         ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
  96
  97 /* These numbers seem to be hard coded in the NIC firmware somehow.
  98  * You can't change the ring sizes, but you can change where you place
  99  * them in the NIC onboard memory.
 100  */
 101 #define TG3_RX_RING_SIZE                512
 102 #define TG3_DEF_RX_RING_PENDING         200
 103 #define TG3_RX_JUMBO_RING_SIZE          256
 104 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
 105 #define TG3_RSS_INDIR_TBL_SIZE 128
 106
 107 /* Do not place this n-ring entries value into the tp struct itself,
 108  * we really want to expose these constants to GCC so that modulo et
 109  * al.  operations are done with shifts and masks instead of with
 110  * hw multiply/modulo instructions.  Another solution would be to
 111  * replace things like '% foo' with '& (foo - 1)'.
 112  */
 113 #define TG3_RX_RCB_RING_SIZE(tp)        \
 114         (((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) && \
 115           !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) ? 1024 : 512)
 116
 117 #define TG3_TX_RING_SIZE                512
 118 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
 119
 120 #define TG3_RX_RING_BYTES       (sizeof(struct tg3_rx_buffer_desc) * \
 121                                  TG3_RX_RING_SIZE)
 122 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_ext_rx_buffer_desc) * \
 123                                  TG3_RX_JUMBO_RING_SIZE)
 124 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
 125                                  TG3_RX_RCB_RING_SIZE(tp))
 126 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
 127                                  TG3_TX_RING_SIZE)
 128 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
 129
 130 #define TG3_DMA_BYTE_ENAB               64
 131
 132 #define TG3_RX_STD_DMA_SZ               1536
 133 #define TG3_RX_JMB_DMA_SZ               9046
 134
 135 #define TG3_RX_DMA_TO_MAP_SZ(x)         ((x) + TG3_DMA_BYTE_ENAB)
 136
 137 #define TG3_RX_STD_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
 138 #define TG3_RX_JMB_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
 139
 140 #define TG3_RX_STD_BUFF_RING_SIZE \
 141         (sizeof(struct ring_info) * TG3_RX_RING_SIZE)
 142
 143 #define TG3_RX_JMB_BUFF_RING_SIZE \
 144         (sizeof(struct ring_info) * TG3_RX_JUMBO_RING_SIZE)
 145
 146 /* minimum number of free TX descriptors required to wake up TX process */
 147 #define TG3_TX_WAKEUP_THRESH(tnapi)             ((tnapi)->tx_pending / 4)
 148
 149 #define TG3_RAW_IP_ALIGN 2
 150
 151 /* number of ETHTOOL_GSTATS u64's */
 152 #define TG3_NUM_STATS           (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
 153
 154 #define TG3_NUM_TEST            6
 155
 156 #define FIRMWARE_TG3            "tigon/tg3.bin"
 157 #define FIRMWARE_TG3TSO         "tigon/tg3_tso.bin"
 158 #define FIRMWARE_TG3TSO5        "tigon/tg3_tso5.bin"
 159
 160 static char version[] __devinitdata =
 161         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
 162
 163 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
 164 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
 165 MODULE_LICENSE("GPL");
 166 MODULE_VERSION(DRV_MODULE_VERSION);
 167 MODULE_FIRMWARE(FIRMWARE_TG3);
 168 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
 169 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
 170
 171 #define TG3_RSS_MIN_NUM_MSIX_VECS       2
 172
 173 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
 174 module_param(tg3_debug, int, 0);
 175 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
 176
 177 static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
 178         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
 179         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
 180         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
 181         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
 182         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
 183         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
 184         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
 185         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
 186         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
 187         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
 188         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
 189         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
 190         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
 191         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
 192         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
 193         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
 194         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
 195         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
 196         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
 197         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
 198         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
 199         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
 200         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
 201         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
 202         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
 203         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
 204         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
 205         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
 206         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
 207         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
 208         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
 209         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
 210         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
 211         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
 212         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
 213         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
 214         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
 215         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
 216         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
 217         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
 218         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
 219         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
 220         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
 221         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
 222         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
 223         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
 224         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
 225         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
 226         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
 227         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
 228         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
 229         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
 230         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
 231         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
 232         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
 233         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
 234         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
 235         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
 236         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
 237         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
 238         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
 239         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
 240         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
 241         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
 242         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
 243         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
 244         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
 245         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
 246         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5724)},
 247         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
 248         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
 249         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
 250         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
 251         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791)},
 252         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795)},
 253         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
 254         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
 255         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
 256         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
 257         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
 258         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
 259         {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
 260         {}
 261 };
 262
 263 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
 264
 265 static const struct {
 266         const char string[ETH_GSTRING_LEN];
 267 } ethtool_stats_keys[TG3_NUM_STATS] = {
 268         { "rx_octets" },
 269         { "rx_fragments" },
 270         { "rx_ucast_packets" },
 271         { "rx_mcast_packets" },
 272         { "rx_bcast_packets" },
 273         { "rx_fcs_errors" },
 274         { "rx_align_errors" },
 275         { "rx_xon_pause_rcvd" },
 276         { "rx_xoff_pause_rcvd" },
 277         { "rx_mac_ctrl_rcvd" },
 278         { "rx_xoff_entered" },
 279         { "rx_frame_too_long_errors" },
 280         { "rx_jabbers" },
 281         { "rx_undersize_packets" },
 282         { "rx_in_length_errors" },
 283         { "rx_out_length_errors" },
 284         { "rx_64_or_less_octet_packets" },
 285         { "rx_65_to_127_octet_packets" },
 286         { "rx_128_to_255_octet_packets" },
 287         { "rx_256_to_511_octet_packets" },
 288         { "rx_512_to_1023_octet_packets" },
 289         { "rx_1024_to_1522_octet_packets" },
 290         { "rx_1523_to_2047_octet_packets" },
 291         { "rx_2048_to_4095_octet_packets" },
 292         { "rx_4096_to_8191_octet_packets" },
 293         { "rx_8192_to_9022_octet_packets" },
 294
 295         { "tx_octets" },
 296         { "tx_collisions" },
 297
 298         { "tx_xon_sent" },
 299         { "tx_xoff_sent" },
 300         { "tx_flow_control" },
 301         { "tx_mac_errors" },
 302         { "tx_single_collisions" },
 303         { "tx_mult_collisions" },
 304         { "tx_deferred" },
 305         { "tx_excessive_collisions" },
 306         { "tx_late_collisions" },
 307         { "tx_collide_2times" },
 308         { "tx_collide_3times" },
 309         { "tx_collide_4times" },
 310         { "tx_collide_5times" },
 311         { "tx_collide_6times" },
 312         { "tx_collide_7times" },
 313         { "tx_collide_8times" },
 314         { "tx_collide_9times" },
 315         { "tx_collide_10times" },
 316         { "tx_collide_11times" },
 317         { "tx_collide_12times" },
 318         { "tx_collide_13times" },
 319         { "tx_collide_14times" },
 320         { "tx_collide_15times" },
 321         { "tx_ucast_packets" },
 322         { "tx_mcast_packets" },
 323         { "tx_bcast_packets" },
 324         { "tx_carrier_sense_errors" },
 325         { "tx_discards" },
 326         { "tx_errors" },
 327
 328         { "dma_writeq_full" },
 329         { "dma_write_prioq_full" },
 330         { "rxbds_empty" },
 331         { "rx_discards" },
 332         { "rx_errors" },
 333         { "rx_threshold_hit" },
 334
 335         { "dma_readq_full" },
 336         { "dma_read_prioq_full" },
 337         { "tx_comp_queue_full" },
 338
 339         { "ring_set_send_prod_index" },
 340         { "ring_status_update" },
 341         { "nic_irqs" },
 342         { "nic_avoided_irqs" },
 343         { "nic_tx_threshold_hit" }
 344 };
 345
 346 static const struct {
 347         const char string[ETH_GSTRING_LEN];
 348 } ethtool_test_keys[TG3_NUM_TEST] = {
 349         { "nvram test     (online) " },
 350         { "link test      (online) " },
 351         { "register test  (offline)" },
 352         { "memory test    (offline)" },
 353         { "loopback test  (offline)" },
 354         { "interrupt test (offline)" },
 355 };
 356
 357 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
 358 {
 359         writel(val, tp->regs + off);
 360 }
 361
 362 static u32 tg3_read32(struct tg3 *tp, u32 off)
 363 {
 364         return (readl(tp->regs + off));
 365 }
 366
 367 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
 368 {
 369         writel(val, tp->aperegs + off);
 370 }
 371
 372 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
 373 {
 374         return (readl(tp->aperegs + off));
 375 }
 376
 377 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
 378 {
 379         unsigned long flags;
 380
 381         spin_lock_irqsave(&tp->indirect_lock, flags);
 382         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 383         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 384         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 385 }
 386
 387 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
 388 {
 389         writel(val, tp->regs + off);
 390         readl(tp->regs + off);
 391 }
 392
 393 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
 394 {
 395         unsigned long flags;
 396         u32 val;
 397
 398         spin_lock_irqsave(&tp->indirect_lock, flags);
 399         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 400         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 401         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 402         return val;
 403 }
 404
 405 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
 406 {
 407         unsigned long flags;
 408
 409         if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
 410                 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
 411                                        TG3_64BIT_REG_LOW, val);
 412                 return;
 413         }
 414         if (off == TG3_RX_STD_PROD_IDX_REG) {
 415                 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
 416                                        TG3_64BIT_REG_LOW, val);
 417                 return;
 418         }
 419
 420         spin_lock_irqsave(&tp->indirect_lock, flags);
 421         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 422         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 423         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 424
 425         /* In indirect mode when disabling interrupts, we also need
 426          * to clear the interrupt bit in the GRC local ctrl register.
 427          */
 428         if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
 429             (val == 0x1)) {
 430                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
 431                                        tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
 432         }
 433 }
 434
 435 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
 436 {
 437         unsigned long flags;
 438         u32 val;
 439
 440         spin_lock_irqsave(&tp->indirect_lock, flags);
 441         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 442         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 443         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 444         return val;
 445 }
 446
 447 /* usec_wait specifies the wait time in usec when writing to certain registers
 448  * where it is unsafe to read back the register without some delay.
 449  * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
 450  * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
 451  */
 452 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
 453 {
 454         if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
 455             (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 456                 /* Non-posted methods */
 457                 tp->write32(tp, off, val);
 458         else {
 459                 /* Posted method */
 460                 tg3_write32(tp, off, val);
 461                 if (usec_wait)
 462                         udelay(usec_wait);
 463                 tp->read32(tp, off);
 464         }
 465         /* Wait again after the read for the posted method to guarantee that
 466          * the wait time is met.
 467          */
 468         if (usec_wait)
 469                 udelay(usec_wait);
 470 }
 471
 472 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
 473 {
 474         tp->write32_mbox(tp, off, val);
 475         if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
 476             !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 477                 tp->read32_mbox(tp, off);
 478 }
 479
 480 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
 481 {
 482         void __iomem *mbox = tp->regs + off;
 483         writel(val, mbox);
 484         if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
 485                 writel(val, mbox);
 486         if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
 487                 readl(mbox);
 488 }
 489
 490 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
 491 {
 492         return (readl(tp->regs + off + GRCMBOX_BASE));
 493 }
 494
 495 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
 496 {
 497         writel(val, tp->regs + off + GRCMBOX_BASE);
 498 }
 499
 500 #define tw32_mailbox(reg, val)  tp->write32_mbox(tp, reg, val)
 501 #define tw32_mailbox_f(reg, val)        tw32_mailbox_flush(tp, (reg), (val))
 502 #define tw32_rx_mbox(reg, val)  tp->write32_rx_mbox(tp, reg, val)
 503 #define tw32_tx_mbox(reg, val)  tp->write32_tx_mbox(tp, reg, val)
 504 #define tr32_mailbox(reg)       tp->read32_mbox(tp, reg)
 505
 506 #define tw32(reg,val)           tp->write32(tp, reg, val)
 507 #define tw32_f(reg,val)         _tw32_flush(tp,(reg),(val), 0)
 508 #define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
 509 #define tr32(reg)               tp->read32(tp, reg)
 510
 511 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
 512 {
 513         unsigned long flags;
 514
 515         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 516             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
 517                 return;
 518
 519         spin_lock_irqsave(&tp->indirect_lock, flags);
 520         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 521                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 522                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 523
 524                 /* Always leave this as zero. */
 525                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 526         } else {
 527                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 528                 tw32_f(TG3PCI_MEM_WIN_DATA, val);
 529
 530                 /* Always leave this as zero. */
 531                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 532         }
 533         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 534 }
 535
 536 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
 537 {
 538         unsigned long flags;
 539
 540         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 541             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
 542                 *val = 0;
 543                 return;
 544         }
 545
 546         spin_lock_irqsave(&tp->indirect_lock, flags);
 547         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 548                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 549                 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 550
 551                 /* Always leave this as zero. */
 552                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 553         } else {
 554                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 555                 *val = tr32(TG3PCI_MEM_WIN_DATA);
 556
 557                 /* Always leave this as zero. */
 558                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 559         }
 560         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 561 }
 562
 563 static void tg3_ape_lock_init(struct tg3 *tp)
 564 {
 565         int i;
 566
 567         /* Make sure the driver hasn't any stale locks. */
 568         for (i = 0; i < 8; i++)
 569                 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + 4 * i,
 570                                 APE_LOCK_GRANT_DRIVER);
 571 }
 572
 573 static int tg3_ape_lock(struct tg3 *tp, int locknum)
 574 {
 575         int i, off;
 576         int ret = 0;
 577         u32 status;
 578
 579         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 580                 return 0;
 581
 582         switch (locknum) {
 583                 case TG3_APE_LOCK_GRC:
 584                 case TG3_APE_LOCK_MEM:
 585                         break;
 586                 default:
 587                         return -EINVAL;
 588         }
 589
 590         off = 4 * locknum;
 591
 592         tg3_ape_write32(tp, TG3_APE_LOCK_REQ + off, APE_LOCK_REQ_DRIVER);
 593
 594         /* Wait for up to 1 millisecond to acquire lock. */
 595         for (i = 0; i < 100; i++) {
 596                 status = tg3_ape_read32(tp, TG3_APE_LOCK_GRANT + off);
 597                 if (status == APE_LOCK_GRANT_DRIVER)
 598                         break;
 599                 udelay(10);
 600         }
 601
 602         if (status != APE_LOCK_GRANT_DRIVER) {
 603                 /* Revoke the lock request. */
 604                 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off,
 605                                 APE_LOCK_GRANT_DRIVER);
 606
 607                 ret = -EBUSY;
 608         }
 609
 610         return ret;
 611 }
 612
 613 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
 614 {
 615         int off;
 616
 617         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 618                 return;
 619
 620         switch (locknum) {
 621                 case TG3_APE_LOCK_GRC:
 622                 case TG3_APE_LOCK_MEM:
 623                         break;
 624                 default:
 625                         return;
 626         }
 627
 628         off = 4 * locknum;
 629         tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, APE_LOCK_GRANT_DRIVER);
 630 }
 631
 632 static void tg3_disable_ints(struct tg3 *tp)
 633 {
 634         int i;
 635
 636         tw32(TG3PCI_MISC_HOST_CTRL,
 637              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
 638         for (i = 0; i < tp->irq_max; i++)
 639                 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
 640 }
 641
 642 static void tg3_enable_ints(struct tg3 *tp)
 643 {
 644         int i;
 645         u32 coal_now = 0;
 646
 647         tp->irq_sync = 0;
 648         wmb();
 649
 650         tw32(TG3PCI_MISC_HOST_CTRL,
 651              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
 652
 653         for (i = 0; i < tp->irq_cnt; i++) {
 654                 struct tg3_napi *tnapi = &tp->napi[i];
 655                 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
 656                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
 657                         tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
 658
 659                 coal_now |= tnapi->coal_now;
 660         }
 661
 662         /* Force an initial interrupt */
 663         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 664             (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
 665                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
 666         else
 667                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 668                      HOSTCC_MODE_ENABLE | coal_now);
 669 }
 670
 671 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
 672 {
 673         struct tg3 *tp = tnapi->tp;
 674         struct tg3_hw_status *sblk = tnapi->hw_status;
 675         unsigned int work_exists = 0;
 676
 677         /* check for phy events */
 678         if (!(tp->tg3_flags &
 679               (TG3_FLAG_USE_LINKCHG_REG |
 680                TG3_FLAG_POLL_SERDES))) {
 681                 if (sblk->status & SD_STATUS_LINK_CHG)
 682                         work_exists = 1;
 683         }
 684         /* check for RX/TX work to do */
 685         if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
 686             *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
 687                 work_exists = 1;
 688
 689         return work_exists;
 690 }
 691
 692 /* tg3_int_reenable
 693  *  similar to tg3_enable_ints, but it accurately determines whether there
 694  *  is new work pending and can return without flushing the PIO write
 695  *  which reenables interrupts
 696  */
 697 static void tg3_int_reenable(struct tg3_napi *tnapi)
 698 {
 699         struct tg3 *tp = tnapi->tp;
 700
 701         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
 702         mmiowb();
 703
 704         /* When doing tagged status, this work check is unnecessary.
 705          * The last_tag we write above tells the chip which piece of
 706          * work we've completed.
 707          */
 708         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 709             tg3_has_work(tnapi))
 710                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 711                      HOSTCC_MODE_ENABLE | tnapi->coal_now);
 712 }
 713
 714 static void tg3_napi_disable(struct tg3 *tp)
 715 {
 716         int i;
 717
 718         for (i = tp->irq_cnt - 1; i >= 0; i--)
 719                 napi_disable(&tp->napi[i].napi);
 720 }
 721
 722 static void tg3_napi_enable(struct tg3 *tp)
 723 {
 724         int i;
 725
 726         for (i = 0; i < tp->irq_cnt; i++)
 727                 napi_enable(&tp->napi[i].napi);
 728 }
 729
 730 static inline void tg3_netif_stop(struct tg3 *tp)
 731 {
 732         tp->dev->trans_start = jiffies; /* prevent tx timeout */
 733         tg3_napi_disable(tp);
 734         netif_tx_disable(tp->dev);
 735 }
 736
 737 static inline void tg3_netif_start(struct tg3 *tp)
 738 {
 739         /* NOTE: unconditional netif_tx_wake_all_queues is only
 740          * appropriate so long as all callers are assured to
 741          * have free tx slots (such as after tg3_init_hw)
 742          */
 743         netif_tx_wake_all_queues(tp->dev);
 744
 745         tg3_napi_enable(tp);
 746         tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
 747         tg3_enable_ints(tp);
 748 }
 749
 750 static void tg3_switch_clocks(struct tg3 *tp)
 751 {
 752         u32 clock_ctrl;
 753         u32 orig_clock_ctrl;
 754
 755         if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
 756             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
 757                 return;
 758
 759         clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
 760
 761         orig_clock_ctrl = clock_ctrl;
 762         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
 763                        CLOCK_CTRL_CLKRUN_OENABLE |
 764                        0x1f);
 765         tp->pci_clock_ctrl = clock_ctrl;
 766
 767         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
 768                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
 769                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
 770                                     clock_ctrl | CLOCK_CTRL_625_CORE, 40);
 771                 }
 772         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
 773                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 774                             clock_ctrl |
 775                             (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
 776                             40);
 777                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 778                             clock_ctrl | (CLOCK_CTRL_ALTCLK),
 779                             40);
 780         }
 781         tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
 782 }
 783
 784 #define PHY_BUSY_LOOPS  5000
 785
 786 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
 787 {
 788         u32 frame_val;
 789         unsigned int loops;
 790         int ret;
 791
 792         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 793                 tw32_f(MAC_MI_MODE,
 794                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 795                 udelay(80);
 796         }
 797
 798         *val = 0x0;
 799
 800         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
 801                       MI_COM_PHY_ADDR_MASK);
 802         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 803                       MI_COM_REG_ADDR_MASK);
 804         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
 805
 806         tw32_f(MAC_MI_COM, frame_val);
 807
 808         loops = PHY_BUSY_LOOPS;
 809         while (loops != 0) {
 810                 udelay(10);
 811                 frame_val = tr32(MAC_MI_COM);
 812
 813                 if ((frame_val & MI_COM_BUSY) == 0) {
 814                         udelay(5);
 815                         frame_val = tr32(MAC_MI_COM);
 816                         break;
 817                 }
 818                 loops -= 1;
 819         }
 820
 821         ret = -EBUSY;
 822         if (loops != 0) {
 823                 *val = frame_val & MI_COM_DATA_MASK;
 824                 ret = 0;
 825         }
 826
 827         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 828                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 829                 udelay(80);
 830         }
 831
 832         return ret;
 833 }
 834
 835 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
 836 {
 837         u32 frame_val;
 838         unsigned int loops;
 839         int ret;
 840
 841         if ((tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
 842             (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
 843                 return 0;
 844
 845         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 846                 tw32_f(MAC_MI_MODE,
 847                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 848                 udelay(80);
 849         }
 850
 851         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
 852                       MI_COM_PHY_ADDR_MASK);
 853         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 854                       MI_COM_REG_ADDR_MASK);
 855         frame_val |= (val & MI_COM_DATA_MASK);
 856         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
 857
 858         tw32_f(MAC_MI_COM, frame_val);
 859
 860         loops = PHY_BUSY_LOOPS;
 861         while (loops != 0) {
 862                 udelay(10);
 863                 frame_val = tr32(MAC_MI_COM);
 864                 if ((frame_val & MI_COM_BUSY) == 0) {
 865                         udelay(5);
 866                         frame_val = tr32(MAC_MI_COM);
 867                         break;
 868                 }
 869                 loops -= 1;
 870         }
 871
 872         ret = -EBUSY;
 873         if (loops != 0)
 874                 ret = 0;
 875
 876         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 877                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 878                 udelay(80);
 879         }
 880
 881         return ret;
 882 }
 883
 884 static int tg3_bmcr_reset(struct tg3 *tp)
 885 {
 886         u32 phy_control;
 887         int limit, err;
 888
 889         /* OK, reset it, and poll the BMCR_RESET bit until it
 890          * clears or we time out.
 891          */
 892         phy_control = BMCR_RESET;
 893         err = tg3_writephy(tp, MII_BMCR, phy_control);
 894         if (err != 0)
 895                 return -EBUSY;
 896
 897         limit = 5000;
 898         while (limit--) {
 899                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
 900                 if (err != 0)
 901                         return -EBUSY;
 902
 903                 if ((phy_control & BMCR_RESET) == 0) {
 904                         udelay(40);
 905                         break;
 906                 }
 907                 udelay(10);
 908         }
 909         if (limit < 0)
 910                 return -EBUSY;
 911
 912         return 0;
 913 }
 914
 915 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
 916 {
 917         struct tg3 *tp = bp->priv;
 918         u32 val;
 919
 920         spin_lock_bh(&tp->lock);
 921
 922         if (tg3_readphy(tp, reg, &val))
 923                 val = -EIO;
 924
 925         spin_unlock_bh(&tp->lock);
 926
 927         return val;
 928 }
 929
 930 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
 931 {
 932         struct tg3 *tp = bp->priv;
 933         u32 ret = 0;
 934
 935         spin_lock_bh(&tp->lock);
 936
 937         if (tg3_writephy(tp, reg, val))
 938                 ret = -EIO;
 939
 940         spin_unlock_bh(&tp->lock);
 941
 942         return ret;
 943 }
 944
 945 static int tg3_mdio_reset(struct mii_bus *bp)
 946 {
 947         return 0;
 948 }
 949
 950 static void tg3_mdio_config_5785(struct tg3 *tp)
 951 {
 952         u32 val;
 953         struct phy_device *phydev;
 954
 955         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
 956         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
 957         case TG3_PHY_ID_BCM50610:
 958         case TG3_PHY_ID_BCM50610M:
 959                 val = MAC_PHYCFG2_50610_LED_MODES;
 960                 break;
 961         case TG3_PHY_ID_BCMAC131:
 962                 val = MAC_PHYCFG2_AC131_LED_MODES;
 963                 break;
 964         case TG3_PHY_ID_RTL8211C:
 965                 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
 966                 break;
 967         case TG3_PHY_ID_RTL8201E:
 968                 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
 969                 break;
 970         default:
 971                 return;
 972         }
 973
 974         if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
 975                 tw32(MAC_PHYCFG2, val);
 976
 977                 val = tr32(MAC_PHYCFG1);
 978                 val &= ~(MAC_PHYCFG1_RGMII_INT |
 979                          MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
 980                 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
 981                 tw32(MAC_PHYCFG1, val);
 982
 983                 return;
 984         }
 985
 986         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE))
 987                 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
 988                        MAC_PHYCFG2_FMODE_MASK_MASK |
 989                        MAC_PHYCFG2_GMODE_MASK_MASK |
 990                        MAC_PHYCFG2_ACT_MASK_MASK   |
 991                        MAC_PHYCFG2_QUAL_MASK_MASK |
 992                        MAC_PHYCFG2_INBAND_ENABLE;
 993
 994         tw32(MAC_PHYCFG2, val);
 995
 996         val = tr32(MAC_PHYCFG1);
 997         val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
 998                  MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
 999         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
1000                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1001                         val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
1002                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1003                         val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1004         }
1005         val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1006                MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1007         tw32(MAC_PHYCFG1, val);
1008
1009         val = tr32(MAC_EXT_RGMII_MODE);
1010         val &= ~(MAC_RGMII_MODE_RX_INT_B |
1011                  MAC_RGMII_MODE_RX_QUALITY |
1012                  MAC_RGMII_MODE_RX_ACTIVITY |
1013                  MAC_RGMII_MODE_RX_ENG_DET |
1014                  MAC_RGMII_MODE_TX_ENABLE |
1015                  MAC_RGMII_MODE_TX_LOWPWR |
1016                  MAC_RGMII_MODE_TX_RESET);
1017         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
1018                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1019                         val |= MAC_RGMII_MODE_RX_INT_B |
1020                                MAC_RGMII_MODE_RX_QUALITY |
1021                                MAC_RGMII_MODE_RX_ACTIVITY |
1022                                MAC_RGMII_MODE_RX_ENG_DET;
1023                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1024                         val |= MAC_RGMII_MODE_TX_ENABLE |
1025                                MAC_RGMII_MODE_TX_LOWPWR |
1026                                MAC_RGMII_MODE_TX_RESET;
1027         }
1028         tw32(MAC_EXT_RGMII_MODE, val);
1029 }
1030
1031 static void tg3_mdio_start(struct tg3 *tp)
1032 {
1033         tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1034         tw32_f(MAC_MI_MODE, tp->mi_mode);
1035         udelay(80);
1036
1037         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
1038                 u32 funcnum, is_serdes;
1039
1040                 funcnum = tr32(TG3_CPMU_STATUS) & TG3_CPMU_STATUS_PCIE_FUNC;
1041                 if (funcnum)
1042                         tp->phy_addr = 2;
1043                 else
1044                         tp->phy_addr = 1;
1045
1046                 if (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
1047                         is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1048                 else
1049                         is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1050                                     TG3_CPMU_PHY_STRAP_IS_SERDES;
1051                 if (is_serdes)
1052                         tp->phy_addr += 7;
1053         } else
1054                 tp->phy_addr = TG3_PHY_MII_ADDR;
1055
1056         if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
1057             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1058                 tg3_mdio_config_5785(tp);
1059 }
1060
1061 static int tg3_mdio_init(struct tg3 *tp)
1062 {
1063         int i;
1064         u32 reg;
1065         struct phy_device *phydev;
1066
1067         tg3_mdio_start(tp);
1068
1069         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1070             (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1071                 return 0;
1072
1073         tp->mdio_bus = mdiobus_alloc();
1074         if (tp->mdio_bus == NULL)
1075                 return -ENOMEM;
1076
1077         tp->mdio_bus->name     = "tg3 mdio bus";
1078         snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1079                  (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1080         tp->mdio_bus->priv     = tp;
1081         tp->mdio_bus->parent   = &tp->pdev->dev;
1082         tp->mdio_bus->read     = &tg3_mdio_read;
1083         tp->mdio_bus->write    = &tg3_mdio_write;
1084         tp->mdio_bus->reset    = &tg3_mdio_reset;
1085         tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
1086         tp->mdio_bus->irq      = &tp->mdio_irq[0];
1087
1088         for (i = 0; i < PHY_MAX_ADDR; i++)
1089                 tp->mdio_bus->irq[i] = PHY_POLL;
1090
1091         /* The bus registration will look for all the PHYs on the mdio bus.
1092          * Unfortunately, it does not ensure the PHY is powered up before
1093          * accessing the PHY ID registers.  A chip reset is the
1094          * quickest way to bring the device back to an operational state..
1095          */
1096         if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1097                 tg3_bmcr_reset(tp);
1098
1099         i = mdiobus_register(tp->mdio_bus);
1100         if (i) {
1101                 printk(KERN_WARNING "%s: mdiobus_reg failed (0x%x)\n",
1102                         tp->dev->name, i);
1103                 mdiobus_free(tp->mdio_bus);
1104                 return i;
1105         }
1106
1107         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1108
1109         if (!phydev || !phydev->drv) {
1110                 printk(KERN_WARNING "%s: No PHY devices\n", tp->dev->name);
1111                 mdiobus_unregister(tp->mdio_bus);
1112                 mdiobus_free(tp->mdio_bus);
1113                 return -ENODEV;
1114         }
1115
1116         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1117         case TG3_PHY_ID_BCM57780:
1118                 phydev->interface = PHY_INTERFACE_MODE_GMII;
1119                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1120                 break;
1121         case TG3_PHY_ID_BCM50610:
1122         case TG3_PHY_ID_BCM50610M:
1123                 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
1124                                      PHY_BRCM_RX_REFCLK_UNUSED |
1125                                      PHY_BRCM_DIS_TXCRXC_NOENRGY |
1126                                      PHY_BRCM_AUTO_PWRDWN_ENABLE;
1127                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)
1128                         phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1129                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1130                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1131                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1132                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1133                 /* fallthru */
1134         case TG3_PHY_ID_RTL8211C:
1135                 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1136                 break;
1137         case TG3_PHY_ID_RTL8201E:
1138         case TG3_PHY_ID_BCMAC131:
1139                 phydev->interface = PHY_INTERFACE_MODE_MII;
1140                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1141                 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
1142                 break;
1143         }
1144
1145         tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1146
1147         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1148                 tg3_mdio_config_5785(tp);
1149
1150         return 0;
1151 }
1152
1153 static void tg3_mdio_fini(struct tg3 *tp)
1154 {
1155         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1156                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
1157                 mdiobus_unregister(tp->mdio_bus);
1158                 mdiobus_free(tp->mdio_bus);
1159         }
1160 }
1161
1162 /* tp->lock is held. */
1163 static inline void tg3_generate_fw_event(struct tg3 *tp)
1164 {
1165         u32 val;
1166
1167         val = tr32(GRC_RX_CPU_EVENT);
1168         val |= GRC_RX_CPU_DRIVER_EVENT;
1169         tw32_f(GRC_RX_CPU_EVENT, val);
1170
1171         tp->last_event_jiffies = jiffies;
1172 }
1173
1174 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1175
1176 /* tp->lock is held. */
1177 static void tg3_wait_for_event_ack(struct tg3 *tp)
1178 {
1179         int i;
1180         unsigned int delay_cnt;
1181         long time_remain;
1182
1183         /* If enough time has passed, no wait is necessary. */
1184         time_remain = (long)(tp->last_event_jiffies + 1 +
1185                       usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1186                       (long)jiffies;
1187         if (time_remain < 0)
1188                 return;
1189
1190         /* Check if we can shorten the wait time. */
1191         delay_cnt = jiffies_to_usecs(time_remain);
1192         if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1193                 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1194         delay_cnt = (delay_cnt >> 3) + 1;
1195
1196         for (i = 0; i < delay_cnt; i++) {
1197                 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1198                         break;
1199                 udelay(8);
1200         }
1201 }
1202
1203 /* tp->lock is held. */
1204 static void tg3_ump_link_report(struct tg3 *tp)
1205 {
1206         u32 reg;
1207         u32 val;
1208
1209         if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1210             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
1211                 return;
1212
1213         tg3_wait_for_event_ack(tp);
1214
1215         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1216
1217         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1218
1219         val = 0;
1220         if (!tg3_readphy(tp, MII_BMCR, &reg))
1221                 val = reg << 16;
1222         if (!tg3_readphy(tp, MII_BMSR, &reg))
1223                 val |= (reg & 0xffff);
1224         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1225
1226         val = 0;
1227         if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1228                 val = reg << 16;
1229         if (!tg3_readphy(tp, MII_LPA, &reg))
1230                 val |= (reg & 0xffff);
1231         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1232
1233         val = 0;
1234         if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
1235                 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1236                         val = reg << 16;
1237                 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1238                         val |= (reg & 0xffff);
1239         }
1240         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1241
1242         if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1243                 val = reg << 16;
1244         else
1245                 val = 0;
1246         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1247
1248         tg3_generate_fw_event(tp);
1249 }
1250
1251 static void tg3_link_report(struct tg3 *tp)
1252 {
1253         if (!netif_carrier_ok(tp->dev)) {
1254                 if (netif_msg_link(tp))
1255                         printk(KERN_INFO PFX "%s: Link is down.\n",
1256                                tp->dev->name);
1257                 tg3_ump_link_report(tp);
1258         } else if (netif_msg_link(tp)) {
1259                 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1260                        tp->dev->name,
1261                        (tp->link_config.active_speed == SPEED_1000 ?
1262                         1000 :
1263                         (tp->link_config.active_speed == SPEED_100 ?
1264                          100 : 10)),
1265                        (tp->link_config.active_duplex == DUPLEX_FULL ?
1266                         "full" : "half"));
1267
1268                 printk(KERN_INFO PFX
1269                        "%s: Flow control is %s for TX and %s for RX.\n",
1270                        tp->dev->name,
1271                        (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1272                        "on" : "off",
1273                        (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1274                        "on" : "off");
1275                 tg3_ump_link_report(tp);
1276         }
1277 }
1278
1279 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1280 {
1281         u16 miireg;
1282
1283         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1284                 miireg = ADVERTISE_PAUSE_CAP;
1285         else if (flow_ctrl & FLOW_CTRL_TX)
1286                 miireg = ADVERTISE_PAUSE_ASYM;
1287         else if (flow_ctrl & FLOW_CTRL_RX)
1288                 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1289         else
1290                 miireg = 0;
1291
1292         return miireg;
1293 }
1294
1295 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1296 {
1297         u16 miireg;
1298
1299         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1300                 miireg = ADVERTISE_1000XPAUSE;
1301         else if (flow_ctrl & FLOW_CTRL_TX)
1302                 miireg = ADVERTISE_1000XPSE_ASYM;
1303         else if (flow_ctrl & FLOW_CTRL_RX)
1304                 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1305         else
1306                 miireg = 0;
1307
1308         return miireg;
1309 }
1310
1311 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1312 {
1313         u8 cap = 0;
1314
1315         if (lcladv & ADVERTISE_1000XPAUSE) {
1316                 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1317                         if (rmtadv & LPA_1000XPAUSE)
1318                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1319                         else if (rmtadv & LPA_1000XPAUSE_ASYM)
1320                                 cap = FLOW_CTRL_RX;
1321                 } else {
1322                         if (rmtadv & LPA_1000XPAUSE)
1323                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1324                 }
1325         } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1326                 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1327                         cap = FLOW_CTRL_TX;
1328         }
1329
1330         return cap;
1331 }
1332
1333 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1334 {
1335         u8 autoneg;
1336         u8 flowctrl = 0;
1337         u32 old_rx_mode = tp->rx_mode;
1338         u32 old_tx_mode = tp->tx_mode;
1339
1340         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
1341                 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
1342         else
1343                 autoneg = tp->link_config.autoneg;
1344
1345         if (autoneg == AUTONEG_ENABLE &&
1346             (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1347                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1348                         flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1349                 else
1350                         flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1351         } else
1352                 flowctrl = tp->link_config.flowctrl;
1353
1354         tp->link_config.active_flowctrl = flowctrl;
1355
1356         if (flowctrl & FLOW_CTRL_RX)
1357                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1358         else
1359                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1360
1361         if (old_rx_mode != tp->rx_mode)
1362                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1363
1364         if (flowctrl & FLOW_CTRL_TX)
1365                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1366         else
1367                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1368
1369         if (old_tx_mode != tp->tx_mode)
1370                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1371 }
1372
1373 static void tg3_adjust_link(struct net_device *dev)
1374 {
1375         u8 oldflowctrl, linkmesg = 0;
1376         u32 mac_mode, lcl_adv, rmt_adv;
1377         struct tg3 *tp = netdev_priv(dev);
1378         struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1379
1380         spin_lock_bh(&tp->lock);
1381
1382         mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1383                                     MAC_MODE_HALF_DUPLEX);
1384
1385         oldflowctrl = tp->link_config.active_flowctrl;
1386
1387         if (phydev->link) {
1388                 lcl_adv = 0;
1389                 rmt_adv = 0;
1390
1391                 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1392                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1393                 else if (phydev->speed == SPEED_1000 ||
1394                          GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
1395                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
1396                 else
1397                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1398
1399                 if (phydev->duplex == DUPLEX_HALF)
1400                         mac_mode |= MAC_MODE_HALF_DUPLEX;
1401                 else {
1402                         lcl_adv = tg3_advert_flowctrl_1000T(
1403                                   tp->link_config.flowctrl);
1404
1405                         if (phydev->pause)
1406                                 rmt_adv = LPA_PAUSE_CAP;
1407                         if (phydev->asym_pause)
1408                                 rmt_adv |= LPA_PAUSE_ASYM;
1409                 }
1410
1411                 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1412         } else
1413                 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1414
1415         if (mac_mode != tp->mac_mode) {
1416                 tp->mac_mode = mac_mode;
1417                 tw32_f(MAC_MODE, tp->mac_mode);
1418                 udelay(40);
1419         }
1420
1421         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1422                 if (phydev->speed == SPEED_10)
1423                         tw32(MAC_MI_STAT,
1424                              MAC_MI_STAT_10MBPS_MODE |
1425                              MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1426                 else
1427                         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1428         }
1429
1430         if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1431                 tw32(MAC_TX_LENGTHS,
1432                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1433                       (6 << TX_LENGTHS_IPG_SHIFT) |
1434                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1435         else
1436                 tw32(MAC_TX_LENGTHS,
1437                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1438                       (6 << TX_LENGTHS_IPG_SHIFT) |
1439                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1440
1441         if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1442             (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1443             phydev->speed != tp->link_config.active_speed ||
1444             phydev->duplex != tp->link_config.active_duplex ||
1445             oldflowctrl != tp->link_config.active_flowctrl)
1446             linkmesg = 1;
1447
1448         tp->link_config.active_speed = phydev->speed;
1449         tp->link_config.active_duplex = phydev->duplex;
1450
1451         spin_unlock_bh(&tp->lock);
1452
1453         if (linkmesg)
1454                 tg3_link_report(tp);
1455 }
1456
1457 static int tg3_phy_init(struct tg3 *tp)
1458 {
1459         struct phy_device *phydev;
1460
1461         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
1462                 return 0;
1463
1464         /* Bring the PHY back to a known state. */
1465         tg3_bmcr_reset(tp);
1466
1467         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1468
1469         /* Attach the MAC to the PHY. */
1470         phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1471                              phydev->dev_flags, phydev->interface);
1472         if (IS_ERR(phydev)) {
1473                 printk(KERN_ERR "%s: Could not attach to PHY\n", tp->dev->name);
1474                 return PTR_ERR(phydev);
1475         }
1476
1477         /* Mask with MAC supported features. */
1478         switch (phydev->interface) {
1479         case PHY_INTERFACE_MODE_GMII:
1480         case PHY_INTERFACE_MODE_RGMII:
1481                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1482                         phydev->supported &= (PHY_GBIT_FEATURES |
1483                                               SUPPORTED_Pause |
1484                                               SUPPORTED_Asym_Pause);
1485                         break;
1486                 }
1487                 /* fallthru */
1488         case PHY_INTERFACE_MODE_MII:
1489                 phydev->supported &= (PHY_BASIC_FEATURES |
1490                                       SUPPORTED_Pause |
1491                                       SUPPORTED_Asym_Pause);
1492                 break;
1493         default:
1494                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1495                 return -EINVAL;
1496         }
1497
1498         tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED;
1499
1500         phydev->advertising = phydev->supported;
1501
1502         return 0;
1503 }
1504
1505 static void tg3_phy_start(struct tg3 *tp)
1506 {
1507         struct phy_device *phydev;
1508
1509         if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1510                 return;
1511
1512         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1513
1514         if (tp->link_config.phy_is_low_power) {
1515                 tp->link_config.phy_is_low_power = 0;
1516                 phydev->speed = tp->link_config.orig_speed;
1517                 phydev->duplex = tp->link_config.orig_duplex;
1518                 phydev->autoneg = tp->link_config.orig_autoneg;
1519                 phydev->advertising = tp->link_config.orig_advertising;
1520         }
1521
1522         phy_start(phydev);
1523
1524         phy_start_aneg(phydev);
1525 }
1526
1527 static void tg3_phy_stop(struct tg3 *tp)
1528 {
1529         if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1530                 return;
1531
1532         phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1533 }
1534
1535 static void tg3_phy_fini(struct tg3 *tp)
1536 {
1537         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
1538                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1539                 tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED;
1540         }
1541 }
1542
1543 static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1544 {
1545         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1546         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1547 }
1548
1549 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1550 {
1551         u32 phytest;
1552
1553         if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1554                 u32 phy;
1555
1556                 tg3_writephy(tp, MII_TG3_FET_TEST,
1557                              phytest | MII_TG3_FET_SHADOW_EN);
1558                 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1559                         if (enable)
1560                                 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1561                         else
1562                                 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1563                         tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1564                 }
1565                 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1566         }
1567 }
1568
1569 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1570 {
1571         u32 reg;
1572
1573         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1574                 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
1575              (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
1576                 return;
1577
1578         if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1579                 tg3_phy_fet_toggle_apd(tp, enable);
1580                 return;
1581         }
1582
1583         reg = MII_TG3_MISC_SHDW_WREN |
1584               MII_TG3_MISC_SHDW_SCR5_SEL |
1585               MII_TG3_MISC_SHDW_SCR5_LPED |
1586               MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1587               MII_TG3_MISC_SHDW_SCR5_SDTL |
1588               MII_TG3_MISC_SHDW_SCR5_C125OE;
1589         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1590                 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1591
1592         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1593
1594
1595         reg = MII_TG3_MISC_SHDW_WREN |
1596               MII_TG3_MISC_SHDW_APD_SEL |
1597               MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1598         if (enable)
1599                 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1600
1601         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1602 }
1603
1604 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1605 {
1606         u32 phy;
1607
1608         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1609             (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1610                 return;
1611
1612         if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1613                 u32 ephy;
1614
1615                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1616                         u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1617
1618                         tg3_writephy(tp, MII_TG3_FET_TEST,
1619                                      ephy | MII_TG3_FET_SHADOW_EN);
1620                         if (!tg3_readphy(tp, reg, &phy)) {
1621                                 if (enable)
1622                                         phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1623                                 else
1624                                         phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1625                                 tg3_writephy(tp, reg, phy);
1626                         }
1627                         tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
1628                 }
1629         } else {
1630                 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1631                       MII_TG3_AUXCTL_SHDWSEL_MISC;
1632                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1633                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1634                         if (enable)
1635                                 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1636                         else
1637                                 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1638                         phy |= MII_TG3_AUXCTL_MISC_WREN;
1639                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1640                 }
1641         }
1642 }
1643
1644 static void tg3_phy_set_wirespeed(struct tg3 *tp)
1645 {
1646         u32 val;
1647
1648         if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
1649                 return;
1650
1651         if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1652             !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1653                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1654                              (val | (1 << 15) | (1 << 4)));
1655 }
1656
1657 static void tg3_phy_apply_otp(struct tg3 *tp)
1658 {
1659         u32 otp, phy;
1660
1661         if (!tp->phy_otp)
1662                 return;
1663
1664         otp = tp->phy_otp;
1665
1666         /* Enable SM_DSP clock and tx 6dB coding. */
1667         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1668               MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1669               MII_TG3_AUXCTL_ACTL_TX_6DB;
1670         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1671
1672         phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1673         phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1674         tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1675
1676         phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1677               ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1678         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1679
1680         phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1681         phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1682         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1683
1684         phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1685         tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1686
1687         phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1688         tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1689
1690         phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1691               ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1692         tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1693
1694         /* Turn off SM_DSP clock. */
1695         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1696               MII_TG3_AUXCTL_ACTL_TX_6DB;
1697         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1698 }
1699
1700 static int tg3_wait_macro_done(struct tg3 *tp)
1701 {
1702         int limit = 100;
1703
1704         while (limit--) {
1705                 u32 tmp32;
1706
1707                 if (!tg3_readphy(tp, 0x16, &tmp32)) {
1708                         if ((tmp32 & 0x1000) == 0)
1709                                 break;
1710                 }
1711         }
1712         if (limit < 0)
1713                 return -EBUSY;
1714
1715         return 0;
1716 }
1717
1718 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1719 {
1720         static const u32 test_pat[4][6] = {
1721         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1722         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1723         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1724         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1725         };
1726         int chan;
1727
1728         for (chan = 0; chan < 4; chan++) {
1729                 int i;
1730
1731                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1732                              (chan * 0x2000) | 0x0200);
1733                 tg3_writephy(tp, 0x16, 0x0002);
1734
1735                 for (i = 0; i < 6; i++)
1736                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1737                                      test_pat[chan][i]);
1738
1739                 tg3_writephy(tp, 0x16, 0x0202);
1740                 if (tg3_wait_macro_done(tp)) {
1741                         *resetp = 1;
1742                         return -EBUSY;
1743                 }
1744
1745                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1746                              (chan * 0x2000) | 0x0200);
1747                 tg3_writephy(tp, 0x16, 0x0082);
1748                 if (tg3_wait_macro_done(tp)) {
1749                         *resetp = 1;
1750                         return -EBUSY;
1751                 }
1752
1753                 tg3_writephy(tp, 0x16, 0x0802);
1754                 if (tg3_wait_macro_done(tp)) {
1755                         *resetp = 1;
1756                         return -EBUSY;
1757                 }
1758
1759                 for (i = 0; i < 6; i += 2) {
1760                         u32 low, high;
1761
1762                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1763                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1764                             tg3_wait_macro_done(tp)) {
1765                                 *resetp = 1;
1766                                 return -EBUSY;
1767                         }
1768                         low &= 0x7fff;
1769                         high &= 0x000f;
1770                         if (low != test_pat[chan][i] ||
1771                             high != test_pat[chan][i+1]) {
1772                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1773                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1774                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1775
1776                                 return -EBUSY;
1777                         }
1778                 }
1779         }
1780
1781         return 0;
1782 }
1783
1784 static int tg3_phy_reset_chanpat(struct tg3 *tp)
1785 {
1786         int chan;
1787
1788         for (chan = 0; chan < 4; chan++) {
1789                 int i;
1790
1791                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1792                              (chan * 0x2000) | 0x0200);
1793                 tg3_writephy(tp, 0x16, 0x0002);
1794                 for (i = 0; i < 6; i++)
1795                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1796                 tg3_writephy(tp, 0x16, 0x0202);
1797                 if (tg3_wait_macro_done(tp))
1798                         return -EBUSY;
1799         }
1800
1801         return 0;
1802 }
1803
1804 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1805 {
1806         u32 reg32, phy9_orig;
1807         int retries, do_phy_reset, err;
1808
1809         retries = 10;
1810         do_phy_reset = 1;
1811         do {
1812                 if (do_phy_reset) {
1813                         err = tg3_bmcr_reset(tp);
1814                         if (err)
1815                                 return err;
1816                         do_phy_reset = 0;
1817                 }
1818
1819                 /* Disable transmitter and interrupt.  */
1820                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1821                         continue;
1822
1823                 reg32 |= 0x3000;
1824                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1825
1826                 /* Set full-duplex, 1000 mbps.  */
1827                 tg3_writephy(tp, MII_BMCR,
1828                              BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1829
1830                 /* Set to master mode.  */
1831                 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1832                         continue;
1833
1834                 tg3_writephy(tp, MII_TG3_CTRL,
1835                              (MII_TG3_CTRL_AS_MASTER |
1836                               MII_TG3_CTRL_ENABLE_AS_MASTER));
1837
1838                 /* Enable SM_DSP_CLOCK and 6dB.  */
1839                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1840
1841                 /* Block the PHY control access.  */
1842                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1843                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
1844
1845                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1846                 if (!err)
1847                         break;
1848         } while (--retries);
1849
1850         err = tg3_phy_reset_chanpat(tp);
1851         if (err)
1852                 return err;
1853
1854         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1855         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
1856
1857         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1858         tg3_writephy(tp, 0x16, 0x0000);
1859
1860         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1861             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1862                 /* Set Extended packet length bit for jumbo frames */
1863                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1864         }
1865         else {
1866                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1867         }
1868
1869         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1870
1871         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1872                 reg32 &= ~0x3000;
1873                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1874         } else if (!err)
1875                 err = -EBUSY;
1876
1877         return err;
1878 }
1879
1880 /* This will reset the tigon3 PHY if there is no valid
1881  * link unless the FORCE argument is non-zero.
1882  */
1883 static int tg3_phy_reset(struct tg3 *tp)
1884 {
1885         u32 cpmuctrl;
1886         u32 phy_status;
1887         int err;
1888
1889         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1890                 u32 val;
1891
1892                 val = tr32(GRC_MISC_CFG);
1893                 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1894                 udelay(40);
1895         }
1896         err  = tg3_readphy(tp, MII_BMSR, &phy_status);
1897         err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1898         if (err != 0)
1899                 return -EBUSY;
1900
1901         if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1902                 netif_carrier_off(tp->dev);
1903                 tg3_link_report(tp);
1904         }
1905
1906         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1907             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1908             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1909                 err = tg3_phy_reset_5703_4_5(tp);
1910                 if (err)
1911                         return err;
1912                 goto out;
1913         }
1914
1915         cpmuctrl = 0;
1916         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1917             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1918                 cpmuctrl = tr32(TG3_CPMU_CTRL);
1919                 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1920                         tw32(TG3_CPMU_CTRL,
1921                              cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1922         }
1923
1924         err = tg3_bmcr_reset(tp);
1925         if (err)
1926                 return err;
1927
1928         if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1929                 u32 phy;
1930
1931                 phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1932                 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
1933
1934                 tw32(TG3_CPMU_CTRL, cpmuctrl);
1935         }
1936
1937         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
1938             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
1939                 u32 val;
1940
1941                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1942                 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1943                     CPMU_LSPD_1000MB_MACCLK_12_5) {
1944                         val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1945                         udelay(40);
1946                         tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1947                 }
1948         }
1949
1950         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
1951             (tp->tg3_flags2 & TG3_FLG2_MII_SERDES))
1952                 return 0;
1953
1954         tg3_phy_apply_otp(tp);
1955
1956         if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
1957                 tg3_phy_toggle_apd(tp, true);
1958         else
1959                 tg3_phy_toggle_apd(tp, false);
1960
1961 out:
1962         if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1963                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1964                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1965                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1966                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1967                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1968                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1969         }
1970         if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1971                 tg3_writephy(tp, 0x1c, 0x8d68);
1972                 tg3_writephy(tp, 0x1c, 0x8d68);
1973         }
1974         if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1975                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1976                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1977                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1978                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1979                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1980                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1981                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1982                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1983         }
1984         else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1985                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1986                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1987                 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1988                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1989                         tg3_writephy(tp, MII_TG3_TEST1,
1990                                      MII_TG3_TEST1_TRIM_EN | 0x4);
1991                 } else
1992                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
1993                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1994         }
1995         /* Set Extended packet length bit (bit 14) on all chips that */
1996         /* support jumbo frames */
1997         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1998                 /* Cannot do read-modify-write on 5401 */
1999                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2000         } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2001                 u32 phy_reg;
2002
2003                 /* Set bit 14 with read-modify-write to preserve other bits */
2004                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
2005                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
2006                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
2007         }
2008
2009         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2010          * jumbo frames transmission.
2011          */
2012         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2013                 u32 phy_reg;
2014
2015                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
2016                     tg3_writephy(tp, MII_TG3_EXT_CTRL,
2017                                  phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
2018         }
2019
2020         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2021                 /* adjust output voltage */
2022                 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
2023         }
2024
2025         tg3_phy_toggle_automdix(tp, 1);
2026         tg3_phy_set_wirespeed(tp);
2027         return 0;
2028 }
2029
2030 static void tg3_frob_aux_power(struct tg3 *tp)
2031 {
2032         struct tg3 *tp_peer = tp;
2033
2034         /* The GPIOs do something completely different on 57765. */
2035         if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0 ||
2036             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
2037                 return;
2038
2039         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2040             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
2041             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
2042                 struct net_device *dev_peer;
2043
2044                 dev_peer = pci_get_drvdata(tp->pdev_peer);
2045                 /* remove_one() may have been run on the peer. */
2046                 if (!dev_peer)
2047                         tp_peer = tp;
2048                 else
2049                         tp_peer = netdev_priv(dev_peer);
2050         }
2051
2052         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2053             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
2054             (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2055             (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
2056                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2057                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2058                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2059                                     (GRC_LCLCTRL_GPIO_OE0 |
2060                                      GRC_LCLCTRL_GPIO_OE1 |
2061                                      GRC_LCLCTRL_GPIO_OE2 |
2062                                      GRC_LCLCTRL_GPIO_OUTPUT0 |
2063                                      GRC_LCLCTRL_GPIO_OUTPUT1),
2064                                     100);
2065                 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2066                            tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2067                         /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2068                         u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2069                                              GRC_LCLCTRL_GPIO_OE1 |
2070                                              GRC_LCLCTRL_GPIO_OE2 |
2071                                              GRC_LCLCTRL_GPIO_OUTPUT0 |
2072                                              GRC_LCLCTRL_GPIO_OUTPUT1 |
2073                                              tp->grc_local_ctrl;
2074                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2075
2076                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2077                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2078
2079                         grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2080                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2081                 } else {
2082                         u32 no_gpio2;
2083                         u32 grc_local_ctrl = 0;
2084
2085                         if (tp_peer != tp &&
2086                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2087                                 return;
2088
2089                         /* Workaround to prevent overdrawing Amps. */
2090                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2091                             ASIC_REV_5714) {
2092                                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2093                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2094                                             grc_local_ctrl, 100);
2095                         }
2096
2097                         /* On 5753 and variants, GPIO2 cannot be used. */
2098                         no_gpio2 = tp->nic_sram_data_cfg &
2099                                     NIC_SRAM_DATA_CFG_NO_GPIO2;
2100
2101                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2102                                          GRC_LCLCTRL_GPIO_OE1 |
2103                                          GRC_LCLCTRL_GPIO_OE2 |
2104                                          GRC_LCLCTRL_GPIO_OUTPUT1 |
2105                                          GRC_LCLCTRL_GPIO_OUTPUT2;
2106                         if (no_gpio2) {
2107                                 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2108                                                     GRC_LCLCTRL_GPIO_OUTPUT2);
2109                         }
2110                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2111                                                     grc_local_ctrl, 100);
2112
2113                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2114
2115                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2116                                                     grc_local_ctrl, 100);
2117
2118                         if (!no_gpio2) {
2119                                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2120                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2121                                             grc_local_ctrl, 100);
2122                         }
2123                 }
2124         } else {
2125                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2126                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2127                         if (tp_peer != tp &&
2128                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2129                                 return;
2130
2131                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2132                                     (GRC_LCLCTRL_GPIO_OE1 |
2133                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2134
2135                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2136                                     GRC_LCLCTRL_GPIO_OE1, 100);
2137
2138                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2139                                     (GRC_LCLCTRL_GPIO_OE1 |
2140                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2141                 }
2142         }
2143 }
2144
2145 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2146 {
2147         if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2148                 return 1;
2149         else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) {
2150                 if (speed != SPEED_10)
2151                         return 1;
2152         } else if (speed == SPEED_10)
2153                 return 1;
2154
2155         return 0;
2156 }
2157
2158 static int tg3_setup_phy(struct tg3 *, int);
2159
2160 #define RESET_KIND_SHUTDOWN     0
2161 #define RESET_KIND_INIT         1
2162 #define RESET_KIND_SUSPEND      2
2163
2164 static void tg3_write_sig_post_reset(struct tg3 *, int);
2165 static int tg3_halt_cpu(struct tg3 *, u32);
2166
2167 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2168 {
2169         u32 val;
2170
2171         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2172                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2173                         u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2174                         u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2175
2176                         sg_dig_ctrl |=
2177                                 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2178                         tw32(SG_DIG_CTRL, sg_dig_ctrl);
2179                         tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2180                 }
2181                 return;
2182         }
2183
2184         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2185                 tg3_bmcr_reset(tp);
2186                 val = tr32(GRC_MISC_CFG);
2187                 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2188                 udelay(40);
2189                 return;
2190         } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
2191                 u32 phytest;
2192                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2193                         u32 phy;
2194
2195                         tg3_writephy(tp, MII_ADVERTISE, 0);
2196                         tg3_writephy(tp, MII_BMCR,
2197                                      BMCR_ANENABLE | BMCR_ANRESTART);
2198
2199                         tg3_writephy(tp, MII_TG3_FET_TEST,
2200                                      phytest | MII_TG3_FET_SHADOW_EN);
2201                         if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2202                                 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2203                                 tg3_writephy(tp,
2204                                              MII_TG3_FET_SHDW_AUXMODE4,
2205                                              phy);
2206                         }
2207                         tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2208                 }
2209                 return;
2210         } else if (do_low_power) {
2211                 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2212                              MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2213
2214                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2215                              MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2216                              MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2217                              MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2218                              MII_TG3_AUXCTL_PCTL_VREG_11V);
2219         }
2220
2221         /* The PHY should not be powered down on some chips because
2222          * of bugs.
2223          */
2224         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2225             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2226             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2227              (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
2228                 return;
2229
2230         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2231             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2232                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2233                 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2234                 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2235                 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2236         }
2237
2238         tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2239 }
2240
2241 /* tp->lock is held. */
2242 static int tg3_nvram_lock(struct tg3 *tp)
2243 {
2244         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2245                 int i;
2246
2247                 if (tp->nvram_lock_cnt == 0) {
2248                         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2249                         for (i = 0; i < 8000; i++) {
2250                                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2251                                         break;
2252                                 udelay(20);
2253                         }
2254                         if (i == 8000) {
2255                                 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2256                                 return -ENODEV;
2257                         }
2258                 }
2259                 tp->nvram_lock_cnt++;
2260         }
2261         return 0;
2262 }
2263
2264 /* tp->lock is held. */
2265 static void tg3_nvram_unlock(struct tg3 *tp)
2266 {
2267         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2268                 if (tp->nvram_lock_cnt > 0)
2269                         tp->nvram_lock_cnt--;
2270                 if (tp->nvram_lock_cnt == 0)
2271                         tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2272         }
2273 }
2274
2275 /* tp->lock is held. */
2276 static void tg3_enable_nvram_access(struct tg3 *tp)
2277 {
2278         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2279             !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2280                 u32 nvaccess = tr32(NVRAM_ACCESS);
2281
2282                 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2283         }
2284 }
2285
2286 /* tp->lock is held. */
2287 static void tg3_disable_nvram_access(struct tg3 *tp)
2288 {
2289         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2290             !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2291                 u32 nvaccess = tr32(NVRAM_ACCESS);
2292
2293                 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2294         }
2295 }
2296
2297 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2298                                         u32 offset, u32 *val)
2299 {
2300         u32 tmp;
2301         int i;
2302
2303         if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2304                 return -EINVAL;
2305
2306         tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2307                                         EEPROM_ADDR_DEVID_MASK |
2308                                         EEPROM_ADDR_READ);
2309         tw32(GRC_EEPROM_ADDR,
2310              tmp |
2311              (0 << EEPROM_ADDR_DEVID_SHIFT) |
2312              ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2313               EEPROM_ADDR_ADDR_MASK) |
2314              EEPROM_ADDR_READ | EEPROM_ADDR_START);
2315
2316         for (i = 0; i < 1000; i++) {
2317                 tmp = tr32(GRC_EEPROM_ADDR);
2318
2319                 if (tmp & EEPROM_ADDR_COMPLETE)
2320                         break;
2321                 msleep(1);
2322         }
2323         if (!(tmp & EEPROM_ADDR_COMPLETE))
2324                 return -EBUSY;
2325
2326         tmp = tr32(GRC_EEPROM_DATA);
2327
2328         /*
2329          * The data will always be opposite the native endian
2330          * format.  Perform a blind byteswap to compensate.
2331          */
2332         *val = swab32(tmp);
2333
2334         return 0;
2335 }
2336
2337 #define NVRAM_CMD_TIMEOUT 10000
2338
2339 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2340 {
2341         int i;
2342
2343         tw32(NVRAM_CMD, nvram_cmd);
2344         for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2345                 udelay(10);
2346                 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2347                         udelay(10);
2348                         break;
2349                 }
2350         }
2351
2352         if (i == NVRAM_CMD_TIMEOUT)
2353                 return -EBUSY;
2354
2355         return 0;
2356 }
2357
2358 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2359 {
2360         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2361             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2362             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2363            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2364             (tp->nvram_jedecnum == JEDEC_ATMEL))
2365
2366                 addr = ((addr / tp->nvram_pagesize) <<
2367                         ATMEL_AT45DB0X1B_PAGE_POS) +
2368                        (addr % tp->nvram_pagesize);
2369
2370         return addr;
2371 }
2372
2373 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2374 {
2375         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2376             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2377             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2378            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2379             (tp->nvram_jedecnum == JEDEC_ATMEL))
2380
2381                 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2382                         tp->nvram_pagesize) +
2383                        (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2384
2385         return addr;
2386 }
2387
2388 /* NOTE: Data read in from NVRAM is byteswapped according to
2389  * the byteswapping settings for all other register accesses.
2390  * tg3 devices are BE devices, so on a BE machine, the data
2391  * returned will be exactly as it is seen in NVRAM.  On a LE
2392  * machine, the 32-bit value will be byteswapped.
2393  */
2394 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2395 {
2396         int ret;
2397
2398         if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2399                 return tg3_nvram_read_using_eeprom(tp, offset, val);
2400
2401         offset = tg3_nvram_phys_addr(tp, offset);
2402
2403         if (offset > NVRAM_ADDR_MSK)
2404                 return -EINVAL;
2405
2406         ret = tg3_nvram_lock(tp);
2407         if (ret)
2408                 return ret;
2409
2410         tg3_enable_nvram_access(tp);
2411
2412         tw32(NVRAM_ADDR, offset);
2413         ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2414                 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2415
2416         if (ret == 0)
2417                 *val = tr32(NVRAM_RDDATA);
2418
2419         tg3_disable_nvram_access(tp);
2420
2421         tg3_nvram_unlock(tp);
2422
2423         return ret;
2424 }
2425
2426 /* Ensures NVRAM data is in bytestream format. */
2427 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
2428 {
2429         u32 v;
2430         int res = tg3_nvram_read(tp, offset, &v);
2431         if (!res)
2432                 *val = cpu_to_be32(v);
2433         return res;
2434 }
2435
2436 /* tp->lock is held. */
2437 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2438 {
2439         u32 addr_high, addr_low;
2440         int i;
2441
2442         addr_high = ((tp->dev->dev_addr[0] << 8) |
2443                      tp->dev->dev_addr[1]);
2444         addr_low = ((tp->dev->dev_addr[2] << 24) |
2445                     (tp->dev->dev_addr[3] << 16) |
2446                     (tp->dev->dev_addr[4] <<  8) |
2447                     (tp->dev->dev_addr[5] <<  0));
2448         for (i = 0; i < 4; i++) {
2449                 if (i == 1 && skip_mac_1)
2450                         continue;
2451                 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2452                 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2453         }
2454
2455         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2456             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2457                 for (i = 0; i < 12; i++) {
2458                         tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2459                         tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2460                 }
2461         }
2462
2463         addr_high = (tp->dev->dev_addr[0] +
2464                      tp->dev->dev_addr[1] +
2465                      tp->dev->dev_addr[2] +
2466                      tp->dev->dev_addr[3] +
2467                      tp->dev->dev_addr[4] +
2468                      tp->dev->dev_addr[5]) &
2469                 TX_BACKOFF_SEED_MASK;
2470         tw32(MAC_TX_BACKOFF_SEED, addr_high);
2471 }
2472
2473 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
2474 {
2475         u32 misc_host_ctrl;
2476         bool device_should_wake, do_low_power;
2477
2478         /* Make sure register accesses (indirect or otherwise)
2479          * will function correctly.
2480          */
2481         pci_write_config_dword(tp->pdev,
2482                                TG3PCI_MISC_HOST_CTRL,
2483                                tp->misc_host_ctrl);
2484
2485         switch (state) {
2486         case PCI_D0:
2487                 pci_enable_wake(tp->pdev, state, false);
2488                 pci_set_power_state(tp->pdev, PCI_D0);
2489
2490                 /* Switch out of Vaux if it is a NIC */
2491                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
2492                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
2493
2494                 return 0;
2495
2496         case PCI_D1:
2497         case PCI_D2:
2498         case PCI_D3hot:
2499                 break;
2500
2501         default:
2502                 printk(KERN_ERR PFX "%s: Invalid power state (D%d) requested\n",
2503                         tp->dev->name, state);
2504                 return -EINVAL;
2505         }
2506
2507         /* Restore the CLKREQ setting. */
2508         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2509                 u16 lnkctl;
2510
2511                 pci_read_config_word(tp->pdev,
2512                                      tp->pcie_cap + PCI_EXP_LNKCTL,
2513                                      &lnkctl);
2514                 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2515                 pci_write_config_word(tp->pdev,
2516                                       tp->pcie_cap + PCI_EXP_LNKCTL,
2517                                       lnkctl);
2518         }
2519
2520         misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2521         tw32(TG3PCI_MISC_HOST_CTRL,
2522              misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2523
2524         device_should_wake = pci_pme_capable(tp->pdev, state) &&
2525                              device_may_wakeup(&tp->pdev->dev) &&
2526                              (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2527
2528         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
2529                 do_low_power = false;
2530                 if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) &&
2531                     !tp->link_config.phy_is_low_power) {
2532                         struct phy_device *phydev;
2533                         u32 phyid, advertising;
2534
2535                         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
2536
2537                         tp->link_config.phy_is_low_power = 1;
2538
2539                         tp->link_config.orig_speed = phydev->speed;
2540                         tp->link_config.orig_duplex = phydev->duplex;
2541                         tp->link_config.orig_autoneg = phydev->autoneg;
2542                         tp->link_config.orig_advertising = phydev->advertising;
2543
2544                         advertising = ADVERTISED_TP |
2545                                       ADVERTISED_Pause |
2546                                       ADVERTISED_Autoneg |
2547                                       ADVERTISED_10baseT_Half;
2548
2549                         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2550                             device_should_wake) {
2551                                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2552                                         advertising |=
2553                                                 ADVERTISED_100baseT_Half |
2554                                                 ADVERTISED_100baseT_Full |
2555                                                 ADVERTISED_10baseT_Full;
2556                                 else
2557                                         advertising |= ADVERTISED_10baseT_Full;
2558                         }
2559
2560                         phydev->advertising = advertising;
2561
2562                         phy_start_aneg(phydev);
2563
2564                         phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2565                         if (phyid != TG3_PHY_ID_BCMAC131) {
2566                                 phyid &= TG3_PHY_OUI_MASK;
2567                                 if (phyid == TG3_PHY_OUI_1 ||
2568                                     phyid == TG3_PHY_OUI_2 ||
2569                                     phyid == TG3_PHY_OUI_3)
2570                                         do_low_power = true;
2571                         }
2572                 }
2573         } else {
2574                 do_low_power = true;
2575
2576                 if (tp->link_config.phy_is_low_power == 0) {
2577                         tp->link_config.phy_is_low_power = 1;
2578                         tp->link_config.orig_speed = tp->link_config.speed;
2579                         tp->link_config.orig_duplex = tp->link_config.duplex;
2580                         tp->link_config.orig_autoneg = tp->link_config.autoneg;
2581                 }
2582
2583                 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
2584                         tp->link_config.speed = SPEED_10;
2585                         tp->link_config.duplex = DUPLEX_HALF;
2586                         tp->link_config.autoneg = AUTONEG_ENABLE;
2587                         tg3_setup_phy(tp, 0);
2588                 }
2589         }
2590
2591         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2592                 u32 val;
2593
2594                 val = tr32(GRC_VCPU_EXT_CTRL);
2595                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2596         } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2597                 int i;
2598                 u32 val;
2599
2600                 for (i = 0; i < 200; i++) {
2601                         tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2602                         if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2603                                 break;
2604                         msleep(1);
2605                 }
2606         }
2607         if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2608                 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2609                                                      WOL_DRV_STATE_SHUTDOWN |
2610                                                      WOL_DRV_WOL |
2611                                                      WOL_SET_MAGIC_PKT);
2612
2613         if (device_should_wake) {
2614                 u32 mac_mode;
2615
2616                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
2617                         if (do_low_power) {
2618                                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2619                                 udelay(40);
2620                         }
2621
2622                         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
2623                                 mac_mode = MAC_MODE_PORT_MODE_GMII;
2624                         else
2625                                 mac_mode = MAC_MODE_PORT_MODE_MII;
2626
2627                         mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2628                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2629                             ASIC_REV_5700) {
2630                                 u32 speed = (tp->tg3_flags &
2631                                              TG3_FLAG_WOL_SPEED_100MB) ?
2632                                              SPEED_100 : SPEED_10;
2633                                 if (tg3_5700_link_polarity(tp, speed))
2634                                         mac_mode |= MAC_MODE_LINK_POLARITY;
2635                                 else
2636                                         mac_mode &= ~MAC_MODE_LINK_POLARITY;
2637                         }
2638                 } else {
2639                         mac_mode = MAC_MODE_PORT_MODE_TBI;
2640                 }
2641
2642                 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
2643                         tw32(MAC_LED_CTRL, tp->led_ctrl);
2644
2645                 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2646                 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2647                     !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2648                     ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2649                      (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2650                         mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
2651
2652                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2653                         mac_mode |= tp->mac_mode &
2654                                     (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2655                         if (mac_mode & MAC_MODE_APE_TX_EN)
2656                                 mac_mode |= MAC_MODE_TDE_ENABLE;
2657                 }
2658
2659                 tw32_f(MAC_MODE, mac_mode);
2660                 udelay(100);
2661
2662                 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2663                 udelay(10);
2664         }
2665
2666         if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2667             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2668              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2669                 u32 base_val;
2670
2671                 base_val = tp->pci_clock_ctrl;
2672                 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2673                              CLOCK_CTRL_TXCLK_DISABLE);
2674
2675                 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2676                             CLOCK_CTRL_PWRDOWN_PLL133, 40);
2677         } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
2678                    (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
2679                    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
2680                 /* do nothing */
2681         } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2682                      (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2683                 u32 newbits1, newbits2;
2684
2685                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2686                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2687                         newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2688                                     CLOCK_CTRL_TXCLK_DISABLE |
2689                                     CLOCK_CTRL_ALTCLK);
2690                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2691                 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2692                         newbits1 = CLOCK_CTRL_625_CORE;
2693                         newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2694                 } else {
2695                         newbits1 = CLOCK_CTRL_ALTCLK;
2696                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2697                 }
2698
2699                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2700                             40);
2701
2702                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2703                             40);
2704
2705                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2706                         u32 newbits3;
2707
2708                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2709                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2710                                 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2711                                             CLOCK_CTRL_TXCLK_DISABLE |
2712                                             CLOCK_CTRL_44MHZ_CORE);
2713                         } else {
2714                                 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2715                         }
2716
2717                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
2718                                     tp->pci_clock_ctrl | newbits3, 40);
2719                 }
2720         }
2721
2722         if (!(device_should_wake) &&
2723             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
2724                 tg3_power_down_phy(tp, do_low_power);
2725
2726         tg3_frob_aux_power(tp);
2727
2728         /* Workaround for unstable PLL clock */
2729         if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2730             (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2731                 u32 val = tr32(0x7d00);
2732
2733                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2734                 tw32(0x7d00, val);
2735                 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2736                         int err;
2737
2738                         err = tg3_nvram_lock(tp);
2739                         tg3_halt_cpu(tp, RX_CPU_BASE);
2740                         if (!err)
2741                                 tg3_nvram_unlock(tp);
2742                 }
2743         }
2744
2745         tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2746
2747         if (device_should_wake)
2748                 pci_enable_wake(tp->pdev, state, true);
2749
2750         /* Finally, set the new power state. */
2751         pci_set_power_state(tp->pdev, state);
2752
2753         return 0;
2754 }
2755
2756 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2757 {
2758         switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2759         case MII_TG3_AUX_STAT_10HALF:
2760                 *speed = SPEED_10;
2761                 *duplex = DUPLEX_HALF;
2762                 break;
2763
2764         case MII_TG3_AUX_STAT_10FULL:
2765                 *speed = SPEED_10;
2766                 *duplex = DUPLEX_FULL;
2767                 break;
2768
2769         case MII_TG3_AUX_STAT_100HALF:
2770                 *speed = SPEED_100;
2771                 *duplex = DUPLEX_HALF;
2772                 break;
2773
2774         case MII_TG3_AUX_STAT_100FULL:
2775                 *speed = SPEED_100;
2776                 *duplex = DUPLEX_FULL;
2777                 break;
2778
2779         case MII_TG3_AUX_STAT_1000HALF:
2780                 *speed = SPEED_1000;
2781                 *duplex = DUPLEX_HALF;
2782                 break;
2783
2784         case MII_TG3_AUX_STAT_1000FULL:
2785                 *speed = SPEED_1000;
2786                 *duplex = DUPLEX_FULL;
2787                 break;
2788
2789         default:
2790                 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
2791                         *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2792                                  SPEED_10;
2793                         *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2794                                   DUPLEX_HALF;
2795                         break;
2796                 }
2797                 *speed = SPEED_INVALID;
2798                 *duplex = DUPLEX_INVALID;
2799                 break;
2800         }
2801 }
2802
2803 static void tg3_phy_copper_begin(struct tg3 *tp)
2804 {
2805         u32 new_adv;
2806         int i;
2807
2808         if (tp->link_config.phy_is_low_power) {
2809                 /* Entering low power mode.  Disable gigabit and
2810                  * 100baseT advertisements.
2811                  */
2812                 tg3_writephy(tp, MII_TG3_CTRL, 0);
2813
2814                 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2815                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2816                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2817                         new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2818
2819                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2820         } else if (tp->link_config.speed == SPEED_INVALID) {
2821                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2822                         tp->link_config.advertising &=
2823                                 ~(ADVERTISED_1000baseT_Half |
2824                                   ADVERTISED_1000baseT_Full);
2825
2826                 new_adv = ADVERTISE_CSMA;
2827                 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2828                         new_adv |= ADVERTISE_10HALF;
2829                 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2830                         new_adv |= ADVERTISE_10FULL;
2831                 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2832                         new_adv |= ADVERTISE_100HALF;
2833                 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2834                         new_adv |= ADVERTISE_100FULL;
2835
2836                 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2837
2838                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2839
2840                 if (tp->link_config.advertising &
2841                     (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2842                         new_adv = 0;
2843                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2844                                 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2845                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2846                                 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2847                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
2848                             (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2849                              tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2850                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2851                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2852                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2853                 } else {
2854                         tg3_writephy(tp, MII_TG3_CTRL, 0);
2855                 }
2856         } else {
2857                 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2858                 new_adv |= ADVERTISE_CSMA;
2859
2860                 /* Asking for a specific link mode. */
2861                 if (tp->link_config.speed == SPEED_1000) {
2862                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2863
2864                         if (tp->link_config.duplex == DUPLEX_FULL)
2865                                 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2866                         else
2867                                 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2868                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2869                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2870                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2871                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2872                 } else {
2873                         if (tp->link_config.speed == SPEED_100) {
2874                                 if (tp->link_config.duplex == DUPLEX_FULL)
2875                                         new_adv |= ADVERTISE_100FULL;
2876                                 else
2877                                         new_adv |= ADVERTISE_100HALF;
2878                         } else {
2879                                 if (tp->link_config.duplex == DUPLEX_FULL)
2880                                         new_adv |= ADVERTISE_10FULL;
2881                                 else
2882                                         new_adv |= ADVERTISE_10HALF;
2883                         }
2884                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2885
2886                         new_adv = 0;
2887                 }
2888
2889                 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2890         }
2891
2892         if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2893             tp->link_config.speed != SPEED_INVALID) {
2894                 u32 bmcr, orig_bmcr;
2895
2896                 tp->link_config.active_speed = tp->link_config.speed;
2897                 tp->link_config.active_duplex = tp->link_config.duplex;
2898
2899                 bmcr = 0;
2900                 switch (tp->link_config.speed) {
2901                 default:
2902                 case SPEED_10:
2903                         break;
2904
2905                 case SPEED_100:
2906                         bmcr |= BMCR_SPEED100;
2907                         break;
2908
2909                 case SPEED_1000:
2910                         bmcr |= TG3_BMCR_SPEED1000;
2911                         break;
2912                 }
2913
2914                 if (tp->link_config.duplex == DUPLEX_FULL)
2915                         bmcr |= BMCR_FULLDPLX;
2916
2917                 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2918                     (bmcr != orig_bmcr)) {
2919                         tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2920                         for (i = 0; i < 1500; i++) {
2921                                 u32 tmp;
2922
2923                                 udelay(10);
2924                                 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2925                                     tg3_readphy(tp, MII_BMSR, &tmp))
2926                                         continue;
2927                                 if (!(tmp & BMSR_LSTATUS)) {
2928                                         udelay(40);
2929                                         break;
2930                                 }
2931                         }
2932                         tg3_writephy(tp, MII_BMCR, bmcr);
2933                         udelay(40);
2934                 }
2935         } else {
2936                 tg3_writephy(tp, MII_BMCR,
2937                              BMCR_ANENABLE | BMCR_ANRESTART);
2938         }
2939 }
2940
2941 static int tg3_init_5401phy_dsp(struct tg3 *tp)
2942 {
2943         int err;
2944
2945         /* Turn off tap power management. */
2946         /* Set Extended packet length bit */
2947         err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2948
2949         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
2950         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
2951
2952         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
2953         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
2954
2955         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2956         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
2957
2958         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2959         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
2960
2961         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2962         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
2963
2964         udelay(40);
2965
2966         return err;
2967 }
2968
2969 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
2970 {
2971         u32 adv_reg, all_mask = 0;
2972
2973         if (mask & ADVERTISED_10baseT_Half)
2974                 all_mask |= ADVERTISE_10HALF;
2975         if (mask & ADVERTISED_10baseT_Full)
2976                 all_mask |= ADVERTISE_10FULL;
2977         if (mask & ADVERTISED_100baseT_Half)
2978                 all_mask |= ADVERTISE_100HALF;
2979         if (mask & ADVERTISED_100baseT_Full)
2980                 all_mask |= ADVERTISE_100FULL;
2981
2982         if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
2983                 return 0;
2984
2985         if ((adv_reg & all_mask) != all_mask)
2986                 return 0;
2987         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
2988                 u32 tg3_ctrl;
2989
2990                 all_mask = 0;
2991                 if (mask & ADVERTISED_1000baseT_Half)
2992                         all_mask |= ADVERTISE_1000HALF;
2993                 if (mask & ADVERTISED_1000baseT_Full)
2994                         all_mask |= ADVERTISE_1000FULL;
2995
2996                 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
2997                         return 0;
2998
2999                 if ((tg3_ctrl & all_mask) != all_mask)
3000                         return 0;
3001         }
3002         return 1;
3003 }
3004
3005 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
3006 {
3007         u32 curadv, reqadv;
3008
3009         if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
3010                 return 1;
3011
3012         curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3013         reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
3014
3015         if (tp->link_config.active_duplex == DUPLEX_FULL) {
3016                 if (curadv != reqadv)
3017                         return 0;
3018
3019                 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
3020                         tg3_readphy(tp, MII_LPA, rmtadv);
3021         } else {
3022                 /* Reprogram the advertisement register, even if it
3023                  * does not affect the current link.  If the link
3024                  * gets renegotiated in the future, we can save an
3025                  * additional renegotiation cycle by advertising
3026                  * it correctly in the first place.
3027                  */
3028                 if (curadv != reqadv) {
3029                         *lcladv &= ~(ADVERTISE_PAUSE_CAP |
3030                                      ADVERTISE_PAUSE_ASYM);
3031                         tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
3032                 }
3033         }
3034
3035         return 1;
3036 }
3037
3038 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
3039 {
3040         int current_link_up;
3041         u32 bmsr, dummy;
3042         u32 lcl_adv, rmt_adv;
3043         u16 current_speed;
3044         u8 current_duplex;
3045         int i, err;
3046
3047         tw32(MAC_EVENT, 0);
3048
3049         tw32_f(MAC_STATUS,
3050              (MAC_STATUS_SYNC_CHANGED |
3051               MAC_STATUS_CFG_CHANGED |
3052               MAC_STATUS_MI_COMPLETION |
3053               MAC_STATUS_LNKSTATE_CHANGED));
3054         udelay(40);
3055
3056         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
3057                 tw32_f(MAC_MI_MODE,
3058                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
3059                 udelay(80);
3060         }
3061
3062         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
3063
3064         /* Some third-party PHYs need to be reset on link going
3065          * down.
3066          */
3067         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3068              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
3069              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
3070             netif_carrier_ok(tp->dev)) {
3071                 tg3_readphy(tp, MII_BMSR, &bmsr);
3072                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3073                     !(bmsr & BMSR_LSTATUS))
3074                         force_reset = 1;
3075         }
3076         if (force_reset)
3077                 tg3_phy_reset(tp);
3078
3079         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
3080                 tg3_readphy(tp, MII_BMSR, &bmsr);
3081                 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
3082                     !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
3083                         bmsr = 0;
3084
3085                 if (!(bmsr & BMSR_LSTATUS)) {
3086                         err = tg3_init_5401phy_dsp(tp);
3087                         if (err)
3088                                 return err;
3089
3090                         tg3_readphy(tp, MII_BMSR, &bmsr);
3091                         for (i = 0; i < 1000; i++) {
3092                                 udelay(10);
3093                                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3094                                     (bmsr & BMSR_LSTATUS)) {
3095                                         udelay(40);
3096                                         break;
3097                                 }
3098                         }
3099
3100                         if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
3101                             !(bmsr & BMSR_LSTATUS) &&
3102                             tp->link_config.active_speed == SPEED_1000) {
3103                                 err = tg3_phy_reset(tp);
3104                                 if (!err)
3105                                         err = tg3_init_5401phy_dsp(tp);
3106                                 if (err)
3107                                         return err;
3108                         }
3109                 }
3110         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3111                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3112                 /* 5701 {A0,B0} CRC bug workaround */
3113                 tg3_writephy(tp, 0x15, 0x0a75);
3114                 tg3_writephy(tp, 0x1c, 0x8c68);
3115                 tg3_writephy(tp, 0x1c, 0x8d68);
3116                 tg3_writephy(tp, 0x1c, 0x8c68);
3117         }
3118
3119         /* Clear pending interrupts... */
3120         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3121         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3122
3123         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
3124                 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
3125         else if (!(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
3126                 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3127
3128         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3129             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3130                 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3131                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
3132                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3133                 else
3134                         tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3135         }
3136
3137         current_link_up = 0;
3138         current_speed = SPEED_INVALID;
3139         current_duplex = DUPLEX_INVALID;
3140
3141         if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
3142                 u32 val;
3143
3144                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3145                 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3146                 if (!(val & (1 << 10))) {
3147                         val |= (1 << 10);
3148                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3149                         goto relink;
3150                 }
3151         }
3152
3153         bmsr = 0;
3154         for (i = 0; i < 100; i++) {
3155                 tg3_readphy(tp, MII_BMSR, &bmsr);
3156                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3157                     (bmsr & BMSR_LSTATUS))
3158                         break;
3159                 udelay(40);
3160         }
3161
3162         if (bmsr & BMSR_LSTATUS) {
3163                 u32 aux_stat, bmcr;
3164
3165                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3166                 for (i = 0; i < 2000; i++) {
3167                         udelay(10);
3168                         if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3169                             aux_stat)
3170                                 break;
3171                 }
3172
3173                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3174                                              &current_speed,
3175                                              &current_duplex);
3176
3177                 bmcr = 0;
3178                 for (i = 0; i < 200; i++) {
3179                         tg3_readphy(tp, MII_BMCR, &bmcr);
3180                         if (tg3_readphy(tp, MII_BMCR, &bmcr))
3181                                 continue;
3182                         if (bmcr && bmcr != 0x7fff)
3183                                 break;
3184                         udelay(10);
3185                 }
3186
3187                 lcl_adv = 0;
3188                 rmt_adv = 0;
3189
3190                 tp->link_config.active_speed = current_speed;
3191                 tp->link_config.active_duplex = current_duplex;
3192
3193                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3194                         if ((bmcr & BMCR_ANENABLE) &&
3195                             tg3_copper_is_advertising_all(tp,
3196                                                 tp->link_config.advertising)) {
3197                                 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3198                                                                   &rmt_adv))
3199                                         current_link_up = 1;
3200                         }
3201                 } else {
3202                         if (!(bmcr & BMCR_ANENABLE) &&
3203                             tp->link_config.speed == current_speed &&
3204                             tp->link_config.duplex == current_duplex &&
3205                             tp->link_config.flowctrl ==
3206                             tp->link_config.active_flowctrl) {
3207                                 current_link_up = 1;
3208                         }
3209                 }
3210
3211                 if (current_link_up == 1 &&
3212                     tp->link_config.active_duplex == DUPLEX_FULL)
3213                         tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
3214         }
3215
3216 relink:
3217         if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
3218                 u32 tmp;
3219
3220                 tg3_phy_copper_begin(tp);
3221
3222                 tg3_readphy(tp, MII_BMSR, &tmp);
3223                 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
3224                     (tmp & BMSR_LSTATUS))
3225                         current_link_up = 1;
3226         }
3227
3228         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3229         if (current_link_up == 1) {
3230                 if (tp->link_config.active_speed == SPEED_100 ||
3231                     tp->link_config.active_speed == SPEED_10)
3232                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3233                 else
3234                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3235         } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)
3236                 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3237         else
3238                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3239
3240         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3241         if (tp->link_config.active_duplex == DUPLEX_HALF)
3242                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3243
3244         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
3245                 if (current_link_up == 1 &&
3246                     tg3_5700_link_polarity(tp, tp->link_config.active_speed))
3247                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
3248                 else
3249                         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
3250         }
3251
3252         /* ??? Without this setting Netgear GA302T PHY does not
3253          * ??? send/receive packets...
3254          */
3255         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
3256             tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3257                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3258                 tw32_f(MAC_MI_MODE, tp->mi_mode);
3259                 udelay(80);
3260         }
3261
3262         tw32_f(MAC_MODE, tp->mac_mode);
3263         udelay(40);
3264
3265         if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3266                 /* Polled via timer. */
3267                 tw32_f(MAC_EVENT, 0);
3268         } else {
3269                 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3270         }
3271         udelay(40);
3272
3273         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3274             current_link_up == 1 &&
3275             tp->link_config.active_speed == SPEED_1000 &&
3276             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3277              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3278                 udelay(120);
3279                 tw32_f(MAC_STATUS,
3280                      (MAC_STATUS_SYNC_CHANGED |
3281                       MAC_STATUS_CFG_CHANGED));
3282                 udelay(40);
3283                 tg3_write_mem(tp,
3284                               NIC_SRAM_FIRMWARE_MBOX,
3285                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3286         }
3287
3288         /* Prevent send BD corruption. */
3289         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3290                 u16 oldlnkctl, newlnkctl;
3291
3292                 pci_read_config_word(tp->pdev,
3293                                      tp->pcie_cap + PCI_EXP_LNKCTL,
3294                                      &oldlnkctl);
3295                 if (tp->link_config.active_speed == SPEED_100 ||
3296                     tp->link_config.active_speed == SPEED_10)
3297                         newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3298                 else
3299                         newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3300                 if (newlnkctl != oldlnkctl)
3301                         pci_write_config_word(tp->pdev,
3302                                               tp->pcie_cap + PCI_EXP_LNKCTL,
3303                                               newlnkctl);
3304         }
3305
3306         if (current_link_up != netif_carrier_ok(tp->dev)) {
3307                 if (current_link_up)
3308                         netif_carrier_on(tp->dev);
3309                 else
3310                         netif_carrier_off(tp->dev);
3311                 tg3_link_report(tp);
3312         }
3313
3314         return 0;
3315 }
3316
3317 struct tg3_fiber_aneginfo {
3318         int state;
3319 #define ANEG_STATE_UNKNOWN              0
3320 #define ANEG_STATE_AN_ENABLE            1
3321 #define ANEG_STATE_RESTART_INIT         2
3322 #define ANEG_STATE_RESTART              3
3323 #define ANEG_STATE_DISABLE_LINK_OK      4
3324 #define ANEG_STATE_ABILITY_DETECT_INIT  5
3325 #define ANEG_STATE_ABILITY_DETECT       6
3326 #define ANEG_STATE_ACK_DETECT_INIT      7
3327 #define ANEG_STATE_ACK_DETECT           8
3328 #define ANEG_STATE_COMPLETE_ACK_INIT    9
3329 #define ANEG_STATE_COMPLETE_ACK         10
3330 #define ANEG_STATE_IDLE_DETECT_INIT     11
3331 #define ANEG_STATE_IDLE_DETECT          12
3332 #define ANEG_STATE_LINK_OK              13
3333 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
3334 #define ANEG_STATE_NEXT_PAGE_WAIT       15
3335
3336         u32 flags;
3337 #define MR_AN_ENABLE            0x00000001
3338 #define MR_RESTART_AN           0x00000002
3339 #define MR_AN_COMPLETE          0x00000004
3340 #define MR_PAGE_RX              0x00000008
3341 #define MR_NP_LOADED            0x00000010
3342 #define MR_TOGGLE_TX            0x00000020
3343 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
3344 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
3345 #define MR_LP_ADV_SYM_PAUSE     0x00000100
3346 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
3347 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3348 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3349 #define MR_LP_ADV_NEXT_PAGE     0x00001000
3350 #define MR_TOGGLE_RX            0x00002000
3351 #define MR_NP_RX                0x00004000
3352
3353 #define MR_LINK_OK              0x80000000
3354
3355         unsigned long link_time, cur_time;
3356
3357         u32 ability_match_cfg;
3358         int ability_match_count;
3359
3360         char ability_match, idle_match, ack_match;
3361
3362         u32 txconfig, rxconfig;
3363 #define ANEG_CFG_NP             0x00000080
3364 #define ANEG_CFG_ACK            0x00000040
3365 #define ANEG_CFG_RF2            0x00000020
3366 #define ANEG_CFG_RF1            0x00000010
3367 #define ANEG_CFG_PS2            0x00000001
3368 #define ANEG_CFG_PS1            0x00008000
3369 #define ANEG_CFG_HD             0x00004000
3370 #define ANEG_CFG_FD             0x00002000
3371 #define ANEG_CFG_INVAL          0x00001f06
3372
3373 };
3374 #define ANEG_OK         0
3375 #define ANEG_DONE       1
3376 #define ANEG_TIMER_ENAB 2
3377 #define ANEG_FAILED     -1
3378
3379 #define ANEG_STATE_SETTLE_TIME  10000
3380
3381 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3382                                    struct tg3_fiber_aneginfo *ap)
3383 {
3384         u16 flowctrl;
3385         unsigned long delta;
3386         u32 rx_cfg_reg;
3387         int ret;
3388
3389         if (ap->state == ANEG_STATE_UNKNOWN) {
3390                 ap->rxconfig = 0;
3391                 ap->link_time = 0;
3392                 ap->cur_time = 0;
3393                 ap->ability_match_cfg = 0;
3394                 ap->ability_match_count = 0;
3395                 ap->ability_match = 0;
3396                 ap->idle_match = 0;
3397                 ap->ack_match = 0;
3398         }
3399         ap->cur_time++;
3400
3401         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3402                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3403
3404                 if (rx_cfg_reg != ap->ability_match_cfg) {
3405                         ap->ability_match_cfg = rx_cfg_reg;
3406                         ap->ability_match = 0;
3407                         ap->ability_match_count = 0;
3408                 } else {
3409                         if (++ap->ability_match_count > 1) {
3410                                 ap->ability_match = 1;
3411                                 ap->ability_match_cfg = rx_cfg_reg;
3412                         }
3413                 }
3414                 if (rx_cfg_reg & ANEG_CFG_ACK)
3415                         ap->ack_match = 1;
3416                 else
3417                         ap->ack_match = 0;
3418
3419                 ap->idle_match = 0;
3420         } else {
3421                 ap->idle_match = 1;
3422                 ap->ability_match_cfg = 0;
3423                 ap->ability_match_count = 0;
3424                 ap->ability_match = 0;
3425                 ap->ack_match = 0;
3426
3427                 rx_cfg_reg = 0;
3428         }
3429
3430         ap->rxconfig = rx_cfg_reg;
3431         ret = ANEG_OK;
3432
3433         switch(ap->state) {
3434         case ANEG_STATE_UNKNOWN:
3435                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3436                         ap->state = ANEG_STATE_AN_ENABLE;
3437
3438                 /* fallthru */
3439         case ANEG_STATE_AN_ENABLE:
3440                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3441                 if (ap->flags & MR_AN_ENABLE) {
3442                         ap->link_time = 0;
3443                         ap->cur_time = 0;
3444                         ap->ability_match_cfg = 0;
3445                         ap->ability_match_count = 0;
3446                         ap->ability_match = 0;
3447                         ap->idle_match = 0;
3448                         ap->ack_match = 0;
3449
3450                         ap->state = ANEG_STATE_RESTART_INIT;
3451                 } else {
3452                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
3453                 }
3454                 break;
3455
3456         case ANEG_STATE_RESTART_INIT:
3457                 ap->link_time = ap->cur_time;
3458                 ap->flags &= ~(MR_NP_LOADED);
3459                 ap->txconfig = 0;
3460                 tw32(MAC_TX_AUTO_NEG, 0);
3461                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3462                 tw32_f(MAC_MODE, tp->mac_mode);
3463                 udelay(40);
3464
3465                 ret = ANEG_TIMER_ENAB;
3466                 ap->state = ANEG_STATE_RESTART;
3467
3468                 /* fallthru */
3469         case ANEG_STATE_RESTART:
3470                 delta = ap->cur_time - ap->link_time;
3471                 if (delta > ANEG_STATE_SETTLE_TIME) {
3472                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3473                 } else {
3474                         ret = ANEG_TIMER_ENAB;
3475                 }
3476                 break;
3477
3478         case ANEG_STATE_DISABLE_LINK_OK:
3479                 ret = ANEG_DONE;
3480                 break;
3481
3482         case ANEG_STATE_ABILITY_DETECT_INIT:
3483                 ap->flags &= ~(MR_TOGGLE_TX);
3484                 ap->txconfig = ANEG_CFG_FD;
3485                 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3486                 if (flowctrl & ADVERTISE_1000XPAUSE)
3487                         ap->txconfig |= ANEG_CFG_PS1;
3488                 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3489                         ap->txconfig |= ANEG_CFG_PS2;
3490                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3491                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3492                 tw32_f(MAC_MODE, tp->mac_mode);
3493                 udelay(40);
3494
3495                 ap->state = ANEG_STATE_ABILITY_DETECT;
3496                 break;
3497
3498         case ANEG_STATE_ABILITY_DETECT:
3499                 if (ap->ability_match != 0 && ap->rxconfig != 0) {
3500                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
3501                 }
3502                 break;
3503
3504         case ANEG_STATE_ACK_DETECT_INIT:
3505                 ap->txconfig |= ANEG_CFG_ACK;
3506                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3507                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3508                 tw32_f(MAC_MODE, tp->mac_mode);
3509                 udelay(40);
3510
3511                 ap->state = ANEG_STATE_ACK_DETECT;
3512
3513                 /* fallthru */
3514         case ANEG_STATE_ACK_DETECT:
3515                 if (ap->ack_match != 0) {
3516                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3517                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3518                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3519                         } else {
3520                                 ap->state = ANEG_STATE_AN_ENABLE;
3521                         }
3522                 } else if (ap->ability_match != 0 &&
3523                            ap->rxconfig == 0) {
3524                         ap->state = ANEG_STATE_AN_ENABLE;
3525                 }
3526                 break;
3527
3528         case ANEG_STATE_COMPLETE_ACK_INIT:
3529                 if (ap->rxconfig & ANEG_CFG_INVAL) {
3530                         ret = ANEG_FAILED;
3531                         break;
3532                 }
3533                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3534                                MR_LP_ADV_HALF_DUPLEX |
3535                                MR_LP_ADV_SYM_PAUSE |
3536                                MR_LP_ADV_ASYM_PAUSE |
3537                                MR_LP_ADV_REMOTE_FAULT1 |
3538                                MR_LP_ADV_REMOTE_FAULT2 |
3539                                MR_LP_ADV_NEXT_PAGE |
3540                                MR_TOGGLE_RX |
3541                                MR_NP_RX);
3542                 if (ap->rxconfig & ANEG_CFG_FD)
3543                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3544                 if (ap->rxconfig & ANEG_CFG_HD)
3545                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3546                 if (ap->rxconfig & ANEG_CFG_PS1)
3547                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
3548                 if (ap->rxconfig & ANEG_CFG_PS2)
3549                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3550                 if (ap->rxconfig & ANEG_CFG_RF1)
3551                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3552                 if (ap->rxconfig & ANEG_CFG_RF2)
3553                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3554                 if (ap->rxconfig & ANEG_CFG_NP)
3555                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
3556
3557                 ap->link_time = ap->cur_time;
3558
3559                 ap->flags ^= (MR_TOGGLE_TX);
3560                 if (ap->rxconfig & 0x0008)
3561                         ap->flags |= MR_TOGGLE_RX;
3562                 if (ap->rxconfig & ANEG_CFG_NP)
3563                         ap->flags |= MR_NP_RX;
3564                 ap->flags |= MR_PAGE_RX;
3565
3566                 ap->state = ANEG_STATE_COMPLETE_ACK;
3567                 ret = ANEG_TIMER_ENAB;
3568                 break;
3569
3570         case ANEG_STATE_COMPLETE_ACK:
3571                 if (ap->ability_match != 0 &&
3572                     ap->rxconfig == 0) {
3573                         ap->state = ANEG_STATE_AN_ENABLE;
3574                         break;
3575                 }
3576                 delta = ap->cur_time - ap->link_time;
3577                 if (delta > ANEG_STATE_SETTLE_TIME) {
3578                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3579                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3580                         } else {
3581                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3582                                     !(ap->flags & MR_NP_RX)) {
3583                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3584                                 } else {
3585                                         ret = ANEG_FAILED;
3586                                 }
3587                         }
3588                 }
3589                 break;
3590
3591         case ANEG_STATE_IDLE_DETECT_INIT:
3592                 ap->link_time = ap->cur_time;
3593                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3594                 tw32_f(MAC_MODE, tp->mac_mode);
3595                 udelay(40);
3596
3597                 ap->state = ANEG_STATE_IDLE_DETECT;
3598                 ret = ANEG_TIMER_ENAB;
3599                 break;
3600
3601         case ANEG_STATE_IDLE_DETECT:
3602                 if (ap->ability_match != 0 &&
3603                     ap->rxconfig == 0) {
3604                         ap->state = ANEG_STATE_AN_ENABLE;
3605                         break;
3606                 }
3607                 delta = ap->cur_time - ap->link_time;
3608                 if (delta > ANEG_STATE_SETTLE_TIME) {
3609                         /* XXX another gem from the Broadcom driver :( */
3610                         ap->state = ANEG_STATE_LINK_OK;
3611                 }
3612                 break;
3613
3614         case ANEG_STATE_LINK_OK:
3615                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3616                 ret = ANEG_DONE;
3617                 break;
3618
3619         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3620                 /* ??? unimplemented */
3621                 break;
3622
3623         case ANEG_STATE_NEXT_PAGE_WAIT:
3624                 /* ??? unimplemented */
3625                 break;
3626
3627         default:
3628                 ret = ANEG_FAILED;
3629                 break;
3630         }
3631
3632         return ret;
3633 }
3634
3635 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
3636 {
3637         int res = 0;
3638         struct tg3_fiber_aneginfo aninfo;
3639         int status = ANEG_FAILED;
3640         unsigned int tick;
3641         u32 tmp;
3642
3643         tw32_f(MAC_TX_AUTO_NEG, 0);
3644
3645         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3646         tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3647         udelay(40);
3648
3649         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3650         udelay(40);
3651
3652         memset(&aninfo, 0, sizeof(aninfo));
3653         aninfo.flags |= MR_AN_ENABLE;
3654         aninfo.state = ANEG_STATE_UNKNOWN;
3655         aninfo.cur_time = 0;
3656         tick = 0;
3657         while (++tick < 195000) {
3658                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3659                 if (status == ANEG_DONE || status == ANEG_FAILED)
3660                         break;
3661
3662                 udelay(1);
3663         }
3664
3665         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3666         tw32_f(MAC_MODE, tp->mac_mode);
3667         udelay(40);
3668
3669         *txflags = aninfo.txconfig;
3670         *rxflags = aninfo.flags;
3671
3672         if (status == ANEG_DONE &&
3673             (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3674                              MR_LP_ADV_FULL_DUPLEX)))
3675                 res = 1;
3676
3677         return res;
3678 }
3679
3680 static void tg3_init_bcm8002(struct tg3 *tp)
3681 {
3682         u32 mac_status = tr32(MAC_STATUS);
3683         int i;
3684
3685         /* Reset when initting first time or we have a link. */
3686         if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3687             !(mac_status & MAC_STATUS_PCS_SYNCED))
3688                 return;
3689
3690         /* Set PLL lock range. */
3691         tg3_writephy(tp, 0x16, 0x8007);
3692
3693         /* SW reset */
3694         tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3695
3696         /* Wait for reset to complete. */
3697         /* XXX schedule_timeout() ... */
3698         for (i = 0; i < 500; i++)
3699                 udelay(10);
3700
3701         /* Config mode; select PMA/Ch 1 regs. */
3702         tg3_writephy(tp, 0x10, 0x8411);
3703
3704         /* Enable auto-lock and comdet, select txclk for tx. */
3705         tg3_writephy(tp, 0x11, 0x0a10);
3706
3707         tg3_writephy(tp, 0x18, 0x00a0);
3708         tg3_writephy(tp, 0x16, 0x41ff);
3709
3710         /* Assert and deassert POR. */
3711         tg3_writephy(tp, 0x13, 0x0400);
3712         udelay(40);
3713         tg3_writephy(tp, 0x13, 0x0000);
3714
3715         tg3_writephy(tp, 0x11, 0x0a50);
3716         udelay(40);
3717         tg3_writephy(tp, 0x11, 0x0a10);
3718
3719         /* Wait for signal to stabilize */
3720         /* XXX schedule_timeout() ... */
3721         for (i = 0; i < 15000; i++)
3722                 udelay(10);
3723
3724         /* Deselect the channel register so we can read the PHYID
3725          * later.
3726          */
3727         tg3_writephy(tp, 0x10, 0x8011);
3728 }
3729
3730 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3731 {
3732         u16 flowctrl;
3733         u32 sg_dig_ctrl, sg_dig_status;
3734         u32 serdes_cfg, expected_sg_dig_ctrl;
3735         int workaround, port_a;
3736         int current_link_up;
3737
3738         serdes_cfg = 0;
3739         expected_sg_dig_ctrl = 0;
3740         workaround = 0;
3741         port_a = 1;
3742         current_link_up = 0;
3743
3744         if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3745             tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3746                 workaround = 1;
3747                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3748                         port_a = 0;
3749
3750                 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3751                 /* preserve bits 20-23 for voltage regulator */
3752                 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3753         }
3754
3755         sg_dig_ctrl = tr32(SG_DIG_CTRL);
3756
3757         if (tp->link_config.autoneg != AUTONEG_ENABLE) {
3758                 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
3759                         if (workaround) {
3760                                 u32 val = serdes_cfg;
3761
3762                                 if (port_a)
3763                                         val |= 0xc010000;
3764                                 else
3765                                         val |= 0x4010000;
3766                                 tw32_f(MAC_SERDES_CFG, val);
3767                         }
3768
3769                         tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3770                 }
3771                 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3772                         tg3_setup_flow_control(tp, 0, 0);
3773                         current_link_up = 1;
3774                 }
3775                 goto out;
3776         }
3777
3778         /* Want auto-negotiation.  */
3779         expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
3780
3781         flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3782         if (flowctrl & ADVERTISE_1000XPAUSE)
3783                 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3784         if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3785                 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
3786
3787         if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3788                 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
3789                     tp->serdes_counter &&
3790                     ((mac_status & (MAC_STATUS_PCS_SYNCED |
3791                                     MAC_STATUS_RCVD_CFG)) ==
3792                      MAC_STATUS_PCS_SYNCED)) {
3793                         tp->serdes_counter--;
3794                         current_link_up = 1;
3795                         goto out;
3796                 }
3797 restart_autoneg:
3798                 if (workaround)
3799                         tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
3800                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
3801                 udelay(5);
3802                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3803
3804                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3805                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3806         } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3807                                  MAC_STATUS_SIGNAL_DET)) {
3808                 sg_dig_status = tr32(SG_DIG_STATUS);
3809                 mac_status = tr32(MAC_STATUS);
3810
3811                 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
3812                     (mac_status & MAC_STATUS_PCS_SYNCED)) {
3813                         u32 local_adv = 0, remote_adv = 0;
3814
3815                         if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3816                                 local_adv |= ADVERTISE_1000XPAUSE;
3817                         if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3818                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3819
3820                         if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
3821                                 remote_adv |= LPA_1000XPAUSE;
3822                         if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
3823                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3824
3825                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3826                         current_link_up = 1;
3827                         tp->serdes_counter = 0;
3828                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3829                 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3830                         if (tp->serdes_counter)
3831                                 tp->serdes_counter--;
3832                         else {
3833                                 if (workaround) {
3834                                         u32 val = serdes_cfg;
3835
3836                                         if (port_a)
3837                                                 val |= 0xc010000;
3838                                         else
3839                                                 val |= 0x4010000;
3840
3841                                         tw32_f(MAC_SERDES_CFG, val);
3842                                 }
3843
3844                                 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3845                                 udelay(40);
3846
3847                                 /* Link parallel detection - link is up */
3848                                 /* only if we have PCS_SYNC and not */
3849                                 /* receiving config code words */
3850                                 mac_status = tr32(MAC_STATUS);
3851                                 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3852                                     !(mac_status & MAC_STATUS_RCVD_CFG)) {
3853                                         tg3_setup_flow_control(tp, 0, 0);
3854                                         current_link_up = 1;
3855                                         tp->tg3_flags2 |=
3856                                                 TG3_FLG2_PARALLEL_DETECT;
3857                                         tp->serdes_counter =
3858                                                 SERDES_PARALLEL_DET_TIMEOUT;
3859                                 } else
3860                                         goto restart_autoneg;
3861                         }
3862                 }
3863         } else {
3864                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3865                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3866         }
3867
3868 out:
3869         return current_link_up;
3870 }
3871
3872 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3873 {
3874         int current_link_up = 0;
3875
3876         if (!(mac_status & MAC_STATUS_PCS_SYNCED))
3877                 goto out;
3878
3879         if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3880                 u32 txflags, rxflags;
3881                 int i;
3882
3883                 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3884                         u32 local_adv = 0, remote_adv = 0;
3885
3886                         if (txflags & ANEG_CFG_PS1)
3887                                 local_adv |= ADVERTISE_1000XPAUSE;
3888                         if (txflags & ANEG_CFG_PS2)
3889                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3890
3891                         if (rxflags & MR_LP_ADV_SYM_PAUSE)
3892                                 remote_adv |= LPA_1000XPAUSE;
3893                         if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3894                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3895
3896                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3897
3898                         current_link_up = 1;
3899                 }
3900                 for (i = 0; i < 30; i++) {
3901                         udelay(20);
3902                         tw32_f(MAC_STATUS,
3903                                (MAC_STATUS_SYNC_CHANGED |
3904                                 MAC_STATUS_CFG_CHANGED));
3905                         udelay(40);
3906                         if ((tr32(MAC_STATUS) &
3907                              (MAC_STATUS_SYNC_CHANGED |
3908                               MAC_STATUS_CFG_CHANGED)) == 0)
3909                                 break;
3910                 }
3911
3912                 mac_status = tr32(MAC_STATUS);
3913                 if (current_link_up == 0 &&
3914                     (mac_status & MAC_STATUS_PCS_SYNCED) &&
3915                     !(mac_status & MAC_STATUS_RCVD_CFG))
3916                         current_link_up = 1;
3917         } else {
3918                 tg3_setup_flow_control(tp, 0, 0);
3919
3920                 /* Forcing 1000FD link up. */
3921                 current_link_up = 1;
3922
3923                 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3924                 udelay(40);
3925
3926                 tw32_f(MAC_MODE, tp->mac_mode);
3927                 udelay(40);
3928         }
3929
3930 out:
3931         return current_link_up;
3932 }
3933
3934 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3935 {
3936         u32 orig_pause_cfg;
3937         u16 orig_active_speed;
3938         u8 orig_active_duplex;
3939         u32 mac_status;
3940         int current_link_up;
3941         int i;
3942
3943         orig_pause_cfg = tp->link_config.active_flowctrl;
3944         orig_active_speed = tp->link_config.active_speed;
3945         orig_active_duplex = tp->link_config.active_duplex;
3946
3947         if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3948             netif_carrier_ok(tp->dev) &&
3949             (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3950                 mac_status = tr32(MAC_STATUS);
3951                 mac_status &= (MAC_STATUS_PCS_SYNCED |
3952                                MAC_STATUS_SIGNAL_DET |
3953                                MAC_STATUS_CFG_CHANGED |
3954                                MAC_STATUS_RCVD_CFG);
3955                 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3956                                    MAC_STATUS_SIGNAL_DET)) {
3957                         tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3958                                             MAC_STATUS_CFG_CHANGED));
3959                         return 0;
3960                 }
3961         }
3962
3963         tw32_f(MAC_TX_AUTO_NEG, 0);
3964
3965         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3966         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3967         tw32_f(MAC_MODE, tp->mac_mode);
3968         udelay(40);
3969
3970         if (tp->phy_id == PHY_ID_BCM8002)
3971                 tg3_init_bcm8002(tp);
3972
3973         /* Enable link change event even when serdes polling.  */
3974         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3975         udelay(40);
3976
3977         current_link_up = 0;
3978         mac_status = tr32(MAC_STATUS);
3979
3980         if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
3981                 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
3982         else
3983                 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
3984
3985         tp->napi[0].hw_status->status =
3986                 (SD_STATUS_UPDATED |
3987                  (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
3988
3989         for (i = 0; i < 100; i++) {
3990                 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3991                                     MAC_STATUS_CFG_CHANGED));
3992                 udelay(5);
3993                 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3994                                          MAC_STATUS_CFG_CHANGED |
3995                                          MAC_STATUS_LNKSTATE_CHANGED)) == 0)
3996                         break;
3997         }
3998
3999         mac_status = tr32(MAC_STATUS);
4000         if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
4001                 current_link_up = 0;
4002                 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
4003                     tp->serdes_counter == 0) {
4004                         tw32_f(MAC_MODE, (tp->mac_mode |
4005                                           MAC_MODE_SEND_CONFIGS));
4006                         udelay(1);
4007                         tw32_f(MAC_MODE, tp->mac_mode);
4008                 }
4009         }
4010
4011         if (current_link_up == 1) {
4012                 tp->link_config.active_speed = SPEED_1000;
4013                 tp->link_config.active_duplex = DUPLEX_FULL;
4014                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4015                                     LED_CTRL_LNKLED_OVERRIDE |
4016                                     LED_CTRL_1000MBPS_ON));
4017         } else {
4018                 tp->link_config.active_speed = SPEED_INVALID;
4019                 tp->link_config.active_duplex = DUPLEX_INVALID;
4020                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4021                                     LED_CTRL_LNKLED_OVERRIDE |
4022                                     LED_CTRL_TRAFFIC_OVERRIDE));
4023         }
4024
4025         if (current_link_up != netif_carrier_ok(tp->dev)) {
4026                 if (current_link_up)
4027                         netif_carrier_on(tp->dev);
4028                 else
4029                         netif_carrier_off(tp->dev);
4030                 tg3_link_report(tp);
4031         } else {
4032                 u32 now_pause_cfg = tp->link_config.active_flowctrl;
4033                 if (orig_pause_cfg != now_pause_cfg ||
4034                     orig_active_speed != tp->link_config.active_speed ||
4035                     orig_active_duplex != tp->link_config.active_duplex)
4036                         tg3_link_report(tp);
4037         }
4038
4039         return 0;
4040 }
4041
4042 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
4043 {
4044         int current_link_up, err = 0;
4045         u32 bmsr, bmcr;
4046         u16 current_speed;
4047         u8 current_duplex;
4048         u32 local_adv, remote_adv;
4049
4050         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4051         tw32_f(MAC_MODE, tp->mac_mode);
4052         udelay(40);
4053
4054         tw32(MAC_EVENT, 0);
4055
4056         tw32_f(MAC_STATUS,
4057              (MAC_STATUS_SYNC_CHANGED |
4058               MAC_STATUS_CFG_CHANGED |
4059               MAC_STATUS_MI_COMPLETION |
4060               MAC_STATUS_LNKSTATE_CHANGED));
4061         udelay(40);
4062
4063         if (force_reset)
4064                 tg3_phy_reset(tp);
4065
4066         current_link_up = 0;
4067         current_speed = SPEED_INVALID;
4068         current_duplex = DUPLEX_INVALID;
4069
4070         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4071         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4072         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
4073                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4074                         bmsr |= BMSR_LSTATUS;
4075                 else
4076                         bmsr &= ~BMSR_LSTATUS;
4077         }
4078
4079         err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4080
4081         if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
4082             (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4083                 /* do nothing, just check for link up at the end */
4084         } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4085                 u32 adv, new_adv;
4086
4087                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4088                 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4089                                   ADVERTISE_1000XPAUSE |
4090                                   ADVERTISE_1000XPSE_ASYM |
4091                                   ADVERTISE_SLCT);
4092
4093                 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4094
4095                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4096                         new_adv |= ADVERTISE_1000XHALF;
4097                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4098                         new_adv |= ADVERTISE_1000XFULL;
4099
4100                 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4101                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
4102                         bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4103                         tg3_writephy(tp, MII_BMCR, bmcr);
4104
4105                         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4106                         tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
4107                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4108
4109                         return err;
4110                 }
4111         } else {
4112                 u32 new_bmcr;
4113
4114                 bmcr &= ~BMCR_SPEED1000;
4115                 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4116
4117                 if (tp->link_config.duplex == DUPLEX_FULL)
4118                         new_bmcr |= BMCR_FULLDPLX;
4119
4120                 if (new_bmcr != bmcr) {
4121                         /* BMCR_SPEED1000 is a reserved bit that needs
4122                          * to be set on write.
4123                          */
4124                         new_bmcr |= BMCR_SPEED1000;
4125
4126                         /* Force a linkdown */
4127                         if (netif_carrier_ok(tp->dev)) {
4128                                 u32 adv;
4129
4130                                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4131                                 adv &= ~(ADVERTISE_1000XFULL |
4132                                          ADVERTISE_1000XHALF |
4133                                          ADVERTISE_SLCT);
4134                                 tg3_writephy(tp, MII_ADVERTISE, adv);
4135                                 tg3_writephy(tp, MII_BMCR, bmcr |
4136                                                            BMCR_ANRESTART |
4137                                                            BMCR_ANENABLE);
4138                                 udelay(10);
4139                                 netif_carrier_off(tp->dev);
4140                         }
4141                         tg3_writephy(tp, MII_BMCR, new_bmcr);
4142                         bmcr = new_bmcr;
4143                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4144                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4145                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4146                             ASIC_REV_5714) {
4147                                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4148                                         bmsr |= BMSR_LSTATUS;
4149                                 else
4150                                         bmsr &= ~BMSR_LSTATUS;
4151                         }
4152                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4153                 }
4154         }
4155
4156         if (bmsr & BMSR_LSTATUS) {
4157                 current_speed = SPEED_1000;
4158                 current_link_up = 1;
4159                 if (bmcr & BMCR_FULLDPLX)
4160                         current_duplex = DUPLEX_FULL;
4161                 else
4162                         current_duplex = DUPLEX_HALF;
4163
4164                 local_adv = 0;
4165                 remote_adv = 0;
4166
4167                 if (bmcr & BMCR_ANENABLE) {
4168                         u32 common;
4169
4170                         err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4171                         err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4172                         common = local_adv & remote_adv;
4173                         if (common & (ADVERTISE_1000XHALF |
4174                                       ADVERTISE_1000XFULL)) {
4175                                 if (common & ADVERTISE_1000XFULL)
4176                                         current_duplex = DUPLEX_FULL;
4177                                 else
4178                                         current_duplex = DUPLEX_HALF;
4179                         }
4180                         else
4181                                 current_link_up = 0;
4182                 }
4183         }
4184
4185         if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4186                 tg3_setup_flow_control(tp, local_adv, remote_adv);
4187
4188         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4189         if (tp->link_config.active_duplex == DUPLEX_HALF)
4190                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4191
4192         tw32_f(MAC_MODE, tp->mac_mode);
4193         udelay(40);
4194
4195         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4196
4197         tp->link_config.active_speed = current_speed;
4198         tp->link_config.active_duplex = current_duplex;
4199
4200         if (current_link_up != netif_carrier_ok(tp->dev)) {
4201                 if (current_link_up)
4202                         netif_carrier_on(tp->dev);
4203                 else {
4204                         netif_carrier_off(tp->dev);
4205                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4206                 }
4207                 tg3_link_report(tp);
4208         }
4209         return err;
4210 }
4211
4212 static void tg3_serdes_parallel_detect(struct tg3 *tp)
4213 {
4214         if (tp->serdes_counter) {
4215                 /* Give autoneg time to complete. */
4216                 tp->serdes_counter--;
4217                 return;
4218         }
4219         if (!netif_carrier_ok(tp->dev) &&
4220             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4221                 u32 bmcr;
4222
4223                 tg3_readphy(tp, MII_BMCR, &bmcr);
4224                 if (bmcr & BMCR_ANENABLE) {
4225                         u32 phy1, phy2;
4226
4227                         /* Select shadow register 0x1f */
4228                         tg3_writephy(tp, 0x1c, 0x7c00);
4229                         tg3_readphy(tp, 0x1c, &phy1);
4230
4231                         /* Select expansion interrupt status register */
4232                         tg3_writephy(tp, 0x17, 0x0f01);
4233                         tg3_readphy(tp, 0x15, &phy2);
4234                         tg3_readphy(tp, 0x15, &phy2);
4235
4236                         if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4237                                 /* We have signal detect and not receiving
4238                                  * config code words, link is up by parallel
4239                                  * detection.
4240                                  */
4241
4242                                 bmcr &= ~BMCR_ANENABLE;
4243                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4244                                 tg3_writephy(tp, MII_BMCR, bmcr);
4245                                 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
4246                         }
4247                 }
4248         }
4249         else if (netif_carrier_ok(tp->dev) &&
4250                  (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4251                  (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4252                 u32 phy2;
4253
4254                 /* Select expansion interrupt status register */
4255                 tg3_writephy(tp, 0x17, 0x0f01);
4256                 tg3_readphy(tp, 0x15, &phy2);
4257                 if (phy2 & 0x20) {
4258                         u32 bmcr;
4259
4260                         /* Config code words received, turn on autoneg. */
4261                         tg3_readphy(tp, MII_BMCR, &bmcr);
4262                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4263
4264                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4265
4266                 }
4267         }
4268 }
4269
4270 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4271 {
4272         int err;
4273
4274         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4275                 err = tg3_setup_fiber_phy(tp, force_reset);
4276         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
4277                 err = tg3_setup_fiber_mii_phy(tp, force_reset);
4278         } else {
4279                 err = tg3_setup_copper_phy(tp, force_reset);
4280         }
4281
4282         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
4283                 u32 val, scale;
4284
4285                 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4286                 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4287                         scale = 65;
4288                 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4289                         scale = 6;
4290                 else
4291                         scale = 12;
4292
4293                 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4294                 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4295                 tw32(GRC_MISC_CFG, val);
4296         }
4297
4298         if (tp->link_config.active_speed == SPEED_1000 &&
4299             tp->link_config.active_duplex == DUPLEX_HALF)
4300                 tw32(MAC_TX_LENGTHS,
4301                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4302                       (6 << TX_LENGTHS_IPG_SHIFT) |
4303                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4304         else
4305                 tw32(MAC_TX_LENGTHS,
4306                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4307                       (6 << TX_LENGTHS_IPG_SHIFT) |
4308                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4309
4310         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4311                 if (netif_carrier_ok(tp->dev)) {
4312                         tw32(HOSTCC_STAT_COAL_TICKS,
4313                              tp->coal.stats_block_coalesce_usecs);
4314                 } else {
4315                         tw32(HOSTCC_STAT_COAL_TICKS, 0);
4316                 }
4317         }
4318
4319         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4320                 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4321                 if (!netif_carrier_ok(tp->dev))
4322                         val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4323                               tp->pwrmgmt_thresh;
4324                 else
4325                         val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4326                 tw32(PCIE_PWR_MGMT_THRESH, val);
4327         }
4328
4329         return err;
4330 }
4331
4332 /* This is called whenever we suspect that the system chipset is re-
4333  * ordering the sequence of MMIO to the tx send mailbox. The symptom
4334  * is bogus tx completions. We try to recover by setting the
4335  * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4336  * in the workqueue.
4337  */
4338 static void tg3_tx_recover(struct tg3 *tp)
4339 {
4340         BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4341                tp->write32_tx_mbox == tg3_write_indirect_mbox);
4342
4343         printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
4344                "mapped I/O cycles to the network device, attempting to "
4345                "recover. Please report the problem to the driver maintainer "
4346                "and include system chipset information.\n", tp->dev->name);
4347
4348         spin_lock(&tp->lock);
4349         tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
4350         spin_unlock(&tp->lock);
4351 }
4352
4353 static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
4354 {
4355         smp_mb();
4356         return tnapi->tx_pending -
4357                ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
4358 }
4359
4360 /* Tigon3 never reports partial packet sends.  So we do not
4361  * need special logic to handle SKBs that have not had all
4362  * of their frags sent yet, like SunGEM does.
4363  */
4364 static void tg3_tx(struct tg3_napi *tnapi)
4365 {
4366         struct tg3 *tp = tnapi->tp;
4367         u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
4368         u32 sw_idx = tnapi->tx_cons;
4369         struct netdev_queue *txq;
4370         int index = tnapi - tp->napi;
4371
4372         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
4373                 index--;
4374
4375         txq = netdev_get_tx_queue(tp->dev, index);
4376
4377         while (sw_idx != hw_idx) {
4378                 struct ring_info *ri = &tnapi->tx_buffers[sw_idx];
4379                 struct sk_buff *skb = ri->skb;
4380                 int i, tx_bug = 0;
4381
4382                 if (unlikely(skb == NULL)) {
4383                         tg3_tx_recover(tp);
4384                         return;
4385                 }
4386
4387                 pci_unmap_single(tp->pdev,
4388                                  pci_unmap_addr(ri, mapping),
4389                                  skb_headlen(skb),
4390                                  PCI_DMA_TODEVICE);
4391
4392                 ri->skb = NULL;
4393
4394                 sw_idx = NEXT_TX(sw_idx);
4395
4396                 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
4397                         ri = &tnapi->tx_buffers[sw_idx];
4398                         if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4399                                 tx_bug = 1;
4400
4401                         pci_unmap_page(tp->pdev,
4402                                        pci_unmap_addr(ri, mapping),
4403                                        skb_shinfo(skb)->frags[i].size,
4404                                        PCI_DMA_TODEVICE);
4405                         sw_idx = NEXT_TX(sw_idx);
4406                 }
4407
4408                 dev_kfree_skb(skb);
4409
4410                 if (unlikely(tx_bug)) {
4411                         tg3_tx_recover(tp);
4412                         return;
4413                 }
4414         }
4415
4416         tnapi->tx_cons = sw_idx;
4417
4418         /* Need to make the tx_cons update visible to tg3_start_xmit()
4419          * before checking for netif_queue_stopped().  Without the
4420          * memory barrier, there is a small possibility that tg3_start_xmit()
4421          * will miss it and cause the queue to be stopped forever.
4422          */
4423         smp_mb();
4424
4425         if (unlikely(netif_tx_queue_stopped(txq) &&
4426                      (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
4427                 __netif_tx_lock(txq, smp_processor_id());
4428                 if (netif_tx_queue_stopped(txq) &&
4429                     (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
4430                         netif_tx_wake_queue(txq);
4431                 __netif_tx_unlock(txq);
4432         }
4433 }
4434
4435 static void tg3_rx_skb_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
4436 {
4437         if (!ri->skb)
4438                 return;
4439
4440         pci_unmap_single(tp->pdev, pci_unmap_addr(ri, mapping),
4441                          map_sz, PCI_DMA_FROMDEVICE);
4442         dev_kfree_skb_any(ri->skb);
4443         ri->skb = NULL;
4444 }
4445
4446 /* Returns size of skb allocated or < 0 on error.
4447  *
4448  * We only need to fill in the address because the other members
4449  * of the RX descriptor are invariant, see tg3_init_rings.
4450  *
4451  * Note the purposeful assymetry of cpu vs. chip accesses.  For
4452  * posting buffers we only dirty the first cache line of the RX
4453  * descriptor (containing the address).  Whereas for the RX status
4454  * buffers the cpu only reads the last cacheline of the RX descriptor
4455  * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4456  */
4457 static int tg3_alloc_rx_skb(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
4458                             u32 opaque_key, u32 dest_idx_unmasked)
4459 {
4460         struct tg3_rx_buffer_desc *desc;
4461         struct ring_info *map, *src_map;
4462         struct sk_buff *skb;
4463         dma_addr_t mapping;
4464         int skb_size, dest_idx;
4465
4466         src_map = NULL;
4467         switch (opaque_key) {
4468         case RXD_OPAQUE_RING_STD:
4469                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4470                 desc = &tpr->rx_std[dest_idx];
4471                 map = &tpr->rx_std_buffers[dest_idx];
4472                 skb_size = tp->rx_pkt_map_sz;
4473                 break;
4474
4475         case RXD_OPAQUE_RING_JUMBO:
4476                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4477                 desc = &tpr->rx_jmb[dest_idx].std;
4478                 map = &tpr->rx_jmb_buffers[dest_idx];
4479                 skb_size = TG3_RX_JMB_MAP_SZ;
4480                 break;
4481
4482         default:
4483                 return -EINVAL;
4484         }
4485
4486         /* Do not overwrite any of the map or rp information
4487          * until we are sure we can commit to a new buffer.
4488          *
4489          * Callers depend upon this behavior and assume that
4490          * we leave everything unchanged if we fail.
4491          */
4492         skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
4493         if (skb == NULL)
4494                 return -ENOMEM;
4495
4496         skb_reserve(skb, tp->rx_offset);
4497
4498         mapping = pci_map_single(tp->pdev, skb->data, skb_size,
4499                                  PCI_DMA_FROMDEVICE);
4500         if (pci_dma_mapping_error(tp->pdev, mapping)) {
4501                 dev_kfree_skb(skb);
4502                 return -EIO;
4503         }
4504
4505         map->skb = skb;
4506         pci_unmap_addr_set(map, mapping, mapping);
4507
4508         desc->addr_hi = ((u64)mapping >> 32);
4509         desc->addr_lo = ((u64)mapping & 0xffffffff);
4510
4511         return skb_size;
4512 }
4513
4514 /* We only need to move over in the address because the other
4515  * members of the RX descriptor are invariant.  See notes above
4516  * tg3_alloc_rx_skb for full details.
4517  */
4518 static void tg3_recycle_rx(struct tg3_napi *tnapi,
4519                            struct tg3_rx_prodring_set *dpr,
4520                            u32 opaque_key, int src_idx,
4521                            u32 dest_idx_unmasked)
4522 {
4523         struct tg3 *tp = tnapi->tp;
4524         struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4525         struct ring_info *src_map, *dest_map;
4526         int dest_idx;
4527         struct tg3_rx_prodring_set *spr = &tp->prodring[0];
4528
4529         switch (opaque_key) {
4530         case RXD_OPAQUE_RING_STD:
4531                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4532                 dest_desc = &dpr->rx_std[dest_idx];
4533                 dest_map = &dpr->rx_std_buffers[dest_idx];
4534                 src_desc = &spr->rx_std[src_idx];
4535                 src_map = &spr->rx_std_buffers[src_idx];
4536                 break;
4537
4538         case RXD_OPAQUE_RING_JUMBO:
4539                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4540                 dest_desc = &dpr->rx_jmb[dest_idx].std;
4541                 dest_map = &dpr->rx_jmb_buffers[dest_idx];
4542                 src_desc = &spr->rx_jmb[src_idx].std;
4543                 src_map = &spr->rx_jmb_buffers[src_idx];
4544                 break;
4545
4546         default:
4547                 return;
4548         }
4549
4550         dest_map->skb = src_map->skb;
4551         pci_unmap_addr_set(dest_map, mapping,
4552                            pci_unmap_addr(src_map, mapping));
4553         dest_desc->addr_hi = src_desc->addr_hi;
4554         dest_desc->addr_lo = src_desc->addr_lo;
4555         src_map->skb = NULL;
4556 }
4557
4558 /* The RX ring scheme is composed of multiple rings which post fresh
4559  * buffers to the chip, and one special ring the chip uses to report
4560  * status back to the host.
4561  *
4562  * The special ring reports the status of received packets to the
4563  * host.  The chip does not write into the original descriptor the
4564  * RX buffer was obtained from.  The chip simply takes the original
4565  * descriptor as provided by the host, updates the status and length
4566  * field, then writes this into the next status ring entry.
4567  *
4568  * Each ring the host uses to post buffers to the chip is described
4569  * by a TG3_BDINFO entry in the chips SRAM area.  When a packet arrives,
4570  * it is first placed into the on-chip ram.  When the packet's length
4571  * is known, it walks down the TG3_BDINFO entries to select the ring.
4572  * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4573  * which is within the range of the new packet's length is chosen.
4574  *
4575  * The "separate ring for rx status" scheme may sound queer, but it makes
4576  * sense from a cache coherency perspective.  If only the host writes
4577  * to the buffer post rings, and only the chip writes to the rx status
4578  * rings, then cache lines never move beyond shared-modified state.
4579  * If both the host and chip were to write into the same ring, cache line
4580  * eviction could occur since both entities want it in an exclusive state.
4581  */
4582 static int tg3_rx(struct tg3_napi *tnapi, int budget)
4583 {
4584         struct tg3 *tp = tnapi->tp;
4585         u32 work_mask, rx_std_posted = 0;
4586         u32 std_prod_idx, jmb_prod_idx;
4587         u32 sw_idx = tnapi->rx_rcb_ptr;
4588         u16 hw_idx;
4589         int received;
4590         struct tg3_rx_prodring_set *tpr = tnapi->prodring;
4591
4592         hw_idx = *(tnapi->rx_rcb_prod_idx);
4593         /*
4594          * We need to order the read of hw_idx and the read of
4595          * the opaque cookie.
4596          */
4597         rmb();
4598         work_mask = 0;
4599         received = 0;
4600         std_prod_idx = tpr->rx_std_prod_idx;
4601         jmb_prod_idx = tpr->rx_jmb_prod_idx;
4602         while (sw_idx != hw_idx && budget > 0) {
4603                 struct ring_info *ri;
4604                 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
4605                 unsigned int len;
4606                 struct sk_buff *skb;
4607                 dma_addr_t dma_addr;
4608                 u32 opaque_key, desc_idx, *post_ptr;
4609
4610                 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4611                 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4612                 if (opaque_key == RXD_OPAQUE_RING_STD) {
4613                         ri = &tp->prodring[0].rx_std_buffers[desc_idx];
4614                         dma_addr = pci_unmap_addr(ri, mapping);
4615                         skb = ri->skb;
4616                         post_ptr = &std_prod_idx;
4617                         rx_std_posted++;
4618                 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4619                         ri = &tp->prodring[0].rx_jmb_buffers[desc_idx];
4620                         dma_addr = pci_unmap_addr(ri, mapping);
4621                         skb = ri->skb;
4622                         post_ptr = &jmb_prod_idx;
4623                 } else
4624                         goto next_pkt_nopost;
4625
4626                 work_mask |= opaque_key;
4627
4628                 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4629                     (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4630                 drop_it:
4631                         tg3_recycle_rx(tnapi, tpr, opaque_key,
4632                                        desc_idx, *post_ptr);
4633                 drop_it_no_recycle:
4634                         /* Other statistics kept track of by card. */
4635                         tp->net_stats.rx_dropped++;
4636                         goto next_pkt;
4637                 }
4638
4639                 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4640                       ETH_FCS_LEN;
4641
4642                 if (len > RX_COPY_THRESHOLD &&
4643                     tp->rx_offset == NET_IP_ALIGN) {
4644                     /* rx_offset will likely not equal NET_IP_ALIGN
4645                      * if this is a 5701 card running in PCI-X mode
4646                      * [see tg3_get_invariants()]
4647                      */
4648                         int skb_size;
4649
4650                         skb_size = tg3_alloc_rx_skb(tp, tpr, opaque_key,
4651                                                     *post_ptr);
4652                         if (skb_size < 0)
4653                                 goto drop_it;
4654
4655                         ri->skb = NULL;
4656
4657                         pci_unmap_single(tp->pdev, dma_addr, skb_size,
4658                                          PCI_DMA_FROMDEVICE);
4659
4660                         skb_put(skb, len);
4661                 } else {
4662                         struct sk_buff *copy_skb;
4663
4664                         tg3_recycle_rx(tnapi, tpr, opaque_key,
4665                                        desc_idx, *post_ptr);
4666
4667                         copy_skb = netdev_alloc_skb(tp->dev,
4668                                                     len + TG3_RAW_IP_ALIGN);
4669                         if (copy_skb == NULL)
4670                                 goto drop_it_no_recycle;
4671
4672                         skb_reserve(copy_skb, TG3_RAW_IP_ALIGN);
4673                         skb_put(copy_skb, len);
4674                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4675                         skb_copy_from_linear_data(skb, copy_skb->data, len);
4676                         pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4677
4678                         /* We'll reuse the original ring buffer. */
4679                         skb = copy_skb;
4680                 }
4681
4682                 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4683                     (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4684                     (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4685                       >> RXD_TCPCSUM_SHIFT) == 0xffff))
4686                         skb->ip_summed = CHECKSUM_UNNECESSARY;
4687                 else
4688                         skb->ip_summed = CHECKSUM_NONE;
4689
4690                 skb->protocol = eth_type_trans(skb, tp->dev);
4691
4692                 if (len > (tp->dev->mtu + ETH_HLEN) &&
4693                     skb->protocol != htons(ETH_P_8021Q)) {
4694                         dev_kfree_skb(skb);
4695                         goto next_pkt;
4696                 }
4697
4698 #if TG3_VLAN_TAG_USED
4699                 if (tp->vlgrp != NULL &&
4700                     desc->type_flags & RXD_FLAG_VLAN) {
4701                         vlan_gro_receive(&tnapi->napi, tp->vlgrp,
4702                                          desc->err_vlan & RXD_VLAN_MASK, skb);
4703                 } else
4704 #endif
4705                         napi_gro_receive(&tnapi->napi, skb);
4706
4707                 received++;
4708                 budget--;
4709
4710 next_pkt:
4711                 (*post_ptr)++;
4712
4713                 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4714                         tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4715                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4716                                      tpr->rx_std_prod_idx);
4717                         work_mask &= ~RXD_OPAQUE_RING_STD;
4718                         rx_std_posted = 0;
4719                 }
4720 next_pkt_nopost:
4721                 sw_idx++;
4722                 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
4723
4724                 /* Refresh hw_idx to see if there is new work */
4725                 if (sw_idx == hw_idx) {
4726                         hw_idx = *(tnapi->rx_rcb_prod_idx);
4727                         rmb();
4728                 }
4729         }
4730
4731         /* ACK the status ring. */
4732         tnapi->rx_rcb_ptr = sw_idx;
4733         tw32_rx_mbox(tnapi->consmbox, sw_idx);
4734
4735         /* Refill RX ring(s). */
4736         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) || tnapi == &tp->napi[1]) {
4737                 if (work_mask & RXD_OPAQUE_RING_STD) {
4738                         tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4739                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4740                                      tpr->rx_std_prod_idx);
4741                 }
4742                 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4743                         tpr->rx_jmb_prod_idx = jmb_prod_idx %
4744                                                TG3_RX_JUMBO_RING_SIZE;
4745                         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
4746                                      tpr->rx_jmb_prod_idx);
4747                 }
4748                 mmiowb();
4749         } else if (work_mask) {
4750                 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
4751                  * updated before the producer indices can be updated.
4752                  */
4753                 smp_wmb();
4754
4755                 tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4756                 tpr->rx_jmb_prod_idx = jmb_prod_idx % TG3_RX_JUMBO_RING_SIZE;
4757
4758                 napi_schedule(&tp->napi[1].napi);
4759         }
4760
4761         return received;
4762 }
4763
4764 static void tg3_poll_link(struct tg3 *tp)
4765 {
4766         /* handle link change and other phy events */
4767         if (!(tp->tg3_flags &
4768               (TG3_FLAG_USE_LINKCHG_REG |
4769                TG3_FLAG_POLL_SERDES))) {
4770                 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
4771
4772                 if (sblk->status & SD_STATUS_LINK_CHG) {
4773                         sblk->status = SD_STATUS_UPDATED |
4774                                        (sblk->status & ~SD_STATUS_LINK_CHG);
4775                         spin_lock(&tp->lock);
4776                         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4777                                 tw32_f(MAC_STATUS,
4778                                      (MAC_STATUS_SYNC_CHANGED |
4779                                       MAC_STATUS_CFG_CHANGED |
4780                                       MAC_STATUS_MI_COMPLETION |
4781                                       MAC_STATUS_LNKSTATE_CHANGED));
4782                                 udelay(40);
4783                         } else
4784                                 tg3_setup_phy(tp, 0);
4785                         spin_unlock(&tp->lock);
4786                 }
4787         }
4788 }
4789
4790 static void tg3_rx_prodring_xfer(struct tg3 *tp,
4791                                  struct tg3_rx_prodring_set *dpr,
4792                                  struct tg3_rx_prodring_set *spr)
4793 {
4794         u32 si, di, cpycnt, src_prod_idx;
4795         int i;
4796
4797         while (1) {
4798                 src_prod_idx = spr->rx_std_prod_idx;
4799
4800                 /* Make sure updates to the rx_std_buffers[] entries and the
4801                  * standard producer index are seen in the correct order.
4802                  */
4803                 smp_rmb();
4804
4805                 if (spr->rx_std_cons_idx == src_prod_idx)
4806                         break;
4807
4808                 if (spr->rx_std_cons_idx < src_prod_idx)
4809                         cpycnt = src_prod_idx - spr->rx_std_cons_idx;
4810                 else
4811                         cpycnt = TG3_RX_RING_SIZE - spr->rx_std_cons_idx;
4812
4813                 cpycnt = min(cpycnt, TG3_RX_RING_SIZE - dpr->rx_std_prod_idx);
4814
4815                 si = spr->rx_std_cons_idx;
4816                 di = dpr->rx_std_prod_idx;
4817
4818                 memcpy(&dpr->rx_std_buffers[di],
4819                        &spr->rx_std_buffers[si],
4820                        cpycnt * sizeof(struct ring_info));
4821
4822                 for (i = 0; i < cpycnt; i++, di++, si++) {
4823                         struct tg3_rx_buffer_desc *sbd, *dbd;
4824                         sbd = &spr->rx_std[si];
4825                         dbd = &dpr->rx_std[di];
4826                         dbd->addr_hi = sbd->addr_hi;
4827                         dbd->addr_lo = sbd->addr_lo;
4828                 }
4829
4830                 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) %
4831                                        TG3_RX_RING_SIZE;
4832                 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) %
4833                                        TG3_RX_RING_SIZE;
4834         }
4835
4836         while (1) {
4837                 src_prod_idx = spr->rx_jmb_prod_idx;
4838
4839                 /* Make sure updates to the rx_jmb_buffers[] entries and
4840                  * the jumbo producer index are seen in the correct order.
4841                  */
4842                 smp_rmb();
4843
4844                 if (spr->rx_jmb_cons_idx == src_prod_idx)
4845                         break;
4846
4847                 if (spr->rx_jmb_cons_idx < src_prod_idx)
4848                         cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
4849                 else
4850                         cpycnt = TG3_RX_JUMBO_RING_SIZE - spr->rx_jmb_cons_idx;
4851
4852                 cpycnt = min(cpycnt,
4853                              TG3_RX_JUMBO_RING_SIZE - dpr->rx_jmb_prod_idx);
4854
4855                 si = spr->rx_jmb_cons_idx;
4856                 di = dpr->rx_jmb_prod_idx;
4857
4858                 memcpy(&dpr->rx_jmb_buffers[di],
4859                        &spr->rx_jmb_buffers[si],
4860                        cpycnt * sizeof(struct ring_info));
4861
4862                 for (i = 0; i < cpycnt; i++, di++, si++) {
4863                         struct tg3_rx_buffer_desc *sbd, *dbd;
4864                         sbd = &spr->rx_jmb[si].std;
4865                         dbd = &dpr->rx_jmb[di].std;
4866                         dbd->addr_hi = sbd->addr_hi;
4867                         dbd->addr_lo = sbd->addr_lo;
4868                 }
4869
4870                 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) %
4871                                        TG3_RX_JUMBO_RING_SIZE;
4872                 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) %
4873                                        TG3_RX_JUMBO_RING_SIZE;
4874         }
4875 }
4876
4877 static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
4878 {
4879         struct tg3 *tp = tnapi->tp;
4880
4881         /* run TX completion thread */
4882         if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
4883                 tg3_tx(tnapi);
4884                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4885                         return work_done;
4886         }
4887
4888         /* run RX thread, within the bounds set by NAPI.
4889          * All RX "locking" is done by ensuring outside
4890          * code synchronizes with tg3->napi.poll()
4891          */
4892         if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
4893                 work_done += tg3_rx(tnapi, budget - work_done);
4894
4895         if ((tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) && tnapi == &tp->napi[1]) {
4896                 int i;
4897                 u32 std_prod_idx = tp->prodring[0].rx_std_prod_idx;
4898                 u32 jmb_prod_idx = tp->prodring[0].rx_jmb_prod_idx;
4899
4900                 for (i = 2; i < tp->irq_cnt; i++)
4901                         tg3_rx_prodring_xfer(tp, tnapi->prodring,
4902                                              tp->napi[i].prodring);
4903
4904                 wmb();
4905
4906                 if (std_prod_idx != tp->prodring[0].rx_std_prod_idx) {
4907                         u32 mbox = TG3_RX_STD_PROD_IDX_REG;
4908                         tw32_rx_mbox(mbox, tp->prodring[0].rx_std_prod_idx);
4909                 }
4910
4911                 if (jmb_prod_idx != tp->prodring[0].rx_jmb_prod_idx) {
4912                         u32 mbox = TG3_RX_JMB_PROD_IDX_REG;
4913                         tw32_rx_mbox(mbox, tp->prodring[0].rx_jmb_prod_idx);
4914                 }
4915
4916                 mmiowb();
4917         }
4918
4919         return work_done;
4920 }
4921
4922 static int tg3_poll_msix(struct napi_struct *napi, int budget)
4923 {
4924         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
4925         struct tg3 *tp = tnapi->tp;
4926         int work_done = 0;
4927         struct tg3_hw_status *sblk = tnapi->hw_status;
4928
4929         while (1) {
4930                 work_done = tg3_poll_work(tnapi, work_done, budget);
4931
4932                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4933                         goto tx_recovery;
4934
4935                 if (unlikely(work_done >= budget))
4936                         break;
4937
4938                 /* tp->last_tag is used in tg3_restart_ints() below
4939                  * to tell the hw how much work has been processed,
4940                  * so we must read it before checking for more work.
4941                  */
4942                 tnapi->last_tag = sblk->status_tag;
4943                 tnapi->last_irq_tag = tnapi->last_tag;
4944                 rmb();
4945
4946                 /* check for RX/TX work to do */
4947                 if (sblk->idx[0].tx_consumer == tnapi->tx_cons &&
4948                     *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr) {
4949                         napi_complete(napi);
4950                         /* Reenable interrupts. */
4951                         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
4952                         mmiowb();
4953                         break;
4954                 }
4955         }
4956
4957         return work_done;
4958
4959 tx_recovery:
4960         /* work_done is guaranteed to be less than budget. */
4961         napi_complete(napi);
4962         schedule_work(&tp->reset_task);
4963         return work_done;
4964 }
4965
4966 static int tg3_poll(struct napi_struct *napi, int budget)
4967 {
4968         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
4969         struct tg3 *tp = tnapi->tp;
4970         int work_done = 0;
4971         struct tg3_hw_status *sblk = tnapi->hw_status;
4972
4973         while (1) {
4974                 tg3_poll_link(tp);
4975
4976                 work_done = tg3_poll_work(tnapi, work_done, budget);
4977
4978                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4979                         goto tx_recovery;
4980
4981                 if (unlikely(work_done >= budget))
4982                         break;
4983
4984                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
4985                         /* tp->last_tag is used in tg3_int_reenable() below
4986                          * to tell the hw how much work has been processed,
4987                          * so we must read it before checking for more work.
4988                          */
4989                         tnapi->last_tag = sblk->status_tag;
4990                         tnapi->last_irq_tag = tnapi->last_tag;
4991                         rmb();
4992                 } else
4993                         sblk->status &= ~SD_STATUS_UPDATED;
4994
4995                 if (likely(!tg3_has_work(tnapi))) {
4996                         napi_complete(napi);
4997                         tg3_int_reenable(tnapi);
4998                         break;
4999                 }
5000         }
5001
5002         return work_done;
5003
5004 tx_recovery:
5005         /* work_done is guaranteed to be less than budget. */
5006         napi_complete(napi);
5007         schedule_work(&tp->reset_task);
5008         return work_done;
5009 }
5010
5011 static void tg3_irq_quiesce(struct tg3 *tp)
5012 {
5013         int i;
5014
5015         BUG_ON(tp->irq_sync);
5016
5017         tp->irq_sync = 1;
5018         smp_mb();
5019
5020         for (i = 0; i < tp->irq_cnt; i++)
5021                 synchronize_irq(tp->napi[i].irq_vec);
5022 }
5023
5024 static inline int tg3_irq_sync(struct tg3 *tp)
5025 {
5026         return tp->irq_sync;
5027 }
5028
5029 /* Fully shutdown all tg3 driver activity elsewhere in the system.
5030  * If irq_sync is non-zero, then the IRQ handler must be synchronized
5031  * with as well.  Most of the time, this is not necessary except when
5032  * shutting down the device.
5033  */
5034 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
5035 {
5036         spin_lock_bh(&tp->lock);
5037         if (irq_sync)
5038                 tg3_irq_quiesce(tp);
5039 }
5040
5041 static inline void tg3_full_unlock(struct tg3 *tp)
5042 {
5043         spin_unlock_bh(&tp->lock);
5044 }
5045
5046 /* One-shot MSI handler - Chip automatically disables interrupt
5047  * after sending MSI so driver doesn't have to do it.
5048  */
5049 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
5050 {
5051         struct tg3_napi *tnapi = dev_id;
5052         struct tg3 *tp = tnapi->tp;
5053
5054         prefetch(tnapi->hw_status);
5055         if (tnapi->rx_rcb)
5056                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5057
5058         if (likely(!tg3_irq_sync(tp)))
5059                 napi_schedule(&tnapi->napi);
5060
5061         return IRQ_HANDLED;
5062 }
5063
5064 /* MSI ISR - No need to check for interrupt sharing and no need to
5065  * flush status block and interrupt mailbox. PCI ordering rules
5066  * guarantee that MSI will arrive after the status block.
5067  */
5068 static irqreturn_t tg3_msi(int irq, void *dev_id)
5069 {
5070         struct tg3_napi *tnapi = dev_id;
5071         struct tg3 *tp = tnapi->tp;
5072
5073         prefetch(tnapi->hw_status);
5074         if (tnapi->rx_rcb)
5075                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5076         /*
5077          * Writing any value to intr-mbox-0 clears PCI INTA# and
5078          * chip-internal interrupt pending events.
5079          * Writing non-zero to intr-mbox-0 additional tells the
5080          * NIC to stop sending us irqs, engaging "in-intr-handler"
5081          * event coalescing.
5082          */
5083         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5084         if (likely(!tg3_irq_sync(tp)))
5085                 napi_schedule(&tnapi->napi);
5086
5087         return IRQ_RETVAL(1);
5088 }
5089
5090 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
5091 {
5092         struct tg3_napi *tnapi = dev_id;
5093         struct tg3 *tp = tnapi->tp;
5094         struct tg3_hw_status *sblk = tnapi->hw_status;
5095         unsigned int handled = 1;
5096
5097         /* In INTx mode, it is possible for the interrupt to arrive at
5098          * the CPU before the status block posted prior to the interrupt.
5099          * Reading the PCI State register will confirm whether the
5100          * interrupt is ours and will flush the status block.
5101          */
5102         if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
5103                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5104                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5105                         handled = 0;
5106                         goto out;
5107                 }
5108         }
5109
5110         /*
5111          * Writing any value to intr-mbox-0 clears PCI INTA# and
5112          * chip-internal interrupt pending events.
5113          * Writing non-zero to intr-mbox-0 additional tells the
5114          * NIC to stop sending us irqs, engaging "in-intr-handler"
5115          * event coalescing.
5116          *
5117          * Flush the mailbox to de-assert the IRQ immediately to prevent
5118          * spurious interrupts.  The flush impacts performance but
5119          * excessive spurious interrupts can be worse in some cases.
5120          */
5121         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5122         if (tg3_irq_sync(tp))
5123                 goto out;
5124         sblk->status &= ~SD_STATUS_UPDATED;
5125         if (likely(tg3_has_work(tnapi))) {
5126                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5127                 napi_schedule(&tnapi->napi);
5128         } else {
5129                 /* No work, shared interrupt perhaps?  re-enable
5130                  * interrupts, and flush that PCI write
5131                  */
5132                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
5133                                0x00000000);
5134         }
5135 out:
5136         return IRQ_RETVAL(handled);
5137 }
5138
5139 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
5140 {
5141         struct tg3_napi *tnapi = dev_id;
5142         struct tg3 *tp = tnapi->tp;
5143         struct tg3_hw_status *sblk = tnapi->hw_status;
5144         unsigned int handled = 1;
5145
5146         /* In INTx mode, it is possible for the interrupt to arrive at
5147          * the CPU before the status block posted prior to the interrupt.
5148          * Reading the PCI State register will confirm whether the
5149          * interrupt is ours and will flush the status block.
5150          */
5151         if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
5152                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5153                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5154                         handled = 0;
5155                         goto out;
5156                 }
5157         }
5158
5159         /*
5160          * writing any value to intr-mbox-0 clears PCI INTA# and
5161          * chip-internal interrupt pending events.
5162          * writing non-zero to intr-mbox-0 additional tells the
5163          * NIC to stop sending us irqs, engaging "in-intr-handler"
5164          * event coalescing.
5165          *
5166          * Flush the mailbox to de-assert the IRQ immediately to prevent
5167          * spurious interrupts.  The flush impacts performance but
5168          * excessive spurious interrupts can be worse in some cases.
5169          */
5170         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5171
5172         /*
5173          * In a shared interrupt configuration, sometimes other devices'
5174          * interrupts will scream.  We record the current status tag here
5175          * so that the above check can report that the screaming interrupts
5176          * are unhandled.  Eventually they will be silenced.
5177          */
5178         tnapi->last_irq_tag = sblk->status_tag;
5179
5180         if (tg3_irq_sync(tp))
5181                 goto out;
5182
5183         prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5184
5185         napi_schedule(&tnapi->napi);
5186
5187 out:
5188         return IRQ_RETVAL(handled);
5189 }
5190
5191 /* ISR for interrupt test */
5192 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
5193 {
5194         struct tg3_napi *tnapi = dev_id;
5195         struct tg3 *tp = tnapi->tp;
5196         struct tg3_hw_status *sblk = tnapi->hw_status;
5197
5198         if ((sblk->status & SD_STATUS_UPDATED) ||
5199             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5200                 tg3_disable_ints(tp);
5201                 return IRQ_RETVAL(1);
5202         }
5203         return IRQ_RETVAL(0);
5204 }
5205
5206 static int tg3_init_hw(struct tg3 *, int);
5207 static int tg3_halt(struct tg3 *, int, int);
5208
5209 /* Restart hardware after configuration changes, self-test, etc.
5210  * Invoked with tp->lock held.
5211  */
5212 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
5213         __releases(tp->lock)
5214         __acquires(tp->lock)
5215 {
5216         int err;
5217
5218         err = tg3_init_hw(tp, reset_phy);
5219         if (err) {
5220                 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
5221                        "aborting.\n", tp->dev->name);
5222                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5223                 tg3_full_unlock(tp);
5224                 del_timer_sync(&tp->timer);
5225                 tp->irq_sync = 0;
5226                 tg3_napi_enable(tp);
5227                 dev_close(tp->dev);
5228                 tg3_full_lock(tp, 0);
5229         }
5230         return err;
5231 }
5232
5233 #ifdef CONFIG_NET_POLL_CONTROLLER
5234 static void tg3_poll_controller(struct net_device *dev)
5235 {
5236         int i;
5237         struct tg3 *tp = netdev_priv(dev);
5238
5239         for (i = 0; i < tp->irq_cnt; i++)
5240                 tg3_interrupt(tp->napi[i].irq_vec, dev);
5241 }
5242 #endif
5243
5244 static void tg3_reset_task(struct work_struct *work)
5245 {
5246         struct tg3 *tp = container_of(work, struct tg3, reset_task);
5247         int err;
5248         unsigned int restart_timer;
5249
5250         tg3_full_lock(tp, 0);
5251
5252         if (!netif_running(tp->dev)) {
5253                 tg3_full_unlock(tp);
5254                 return;
5255         }
5256
5257         tg3_full_unlock(tp);
5258
5259         tg3_phy_stop(tp);
5260
5261         tg3_netif_stop(tp);
5262
5263         tg3_full_lock(tp, 1);
5264
5265         restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
5266         tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
5267
5268         if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
5269                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
5270                 tp->write32_rx_mbox = tg3_write_flush_reg32;
5271                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
5272                 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
5273         }
5274
5275         tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
5276         err = tg3_init_hw(tp, 1);
5277         if (err)
5278                 goto out;
5279
5280         tg3_netif_start(tp);
5281
5282         if (restart_timer)
5283                 mod_timer(&tp->timer, jiffies + 1);
5284
5285 out:
5286         tg3_full_unlock(tp);
5287
5288         if (!err)
5289                 tg3_phy_start(tp);
5290 }
5291
5292 static void tg3_dump_short_state(struct tg3 *tp)
5293 {
5294         printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5295                tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
5296         printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5297                tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
5298 }
5299
5300 static void tg3_tx_timeout(struct net_device *dev)
5301 {
5302         struct tg3 *tp = netdev_priv(dev);
5303
5304         if (netif_msg_tx_err(tp)) {
5305                 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
5306                        dev->name);
5307                 tg3_dump_short_state(tp);
5308         }
5309
5310         schedule_work(&tp->reset_task);
5311 }
5312
5313 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5314 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5315 {
5316         u32 base = (u32) mapping & 0xffffffff;
5317
5318         return ((base > 0xffffdcc0) &&
5319                 (base + len + 8 < base));
5320 }
5321
5322 /* Test for DMA addresses > 40-bit */
5323 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5324                                           int len)
5325 {
5326 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
5327         if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
5328                 return (((u64) mapping + len) > DMA_BIT_MASK(40));
5329         return 0;
5330 #else
5331         return 0;
5332 #endif
5333 }
5334
5335 static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32);
5336
5337 /* Workaround 4GB and 40-bit hardware DMA bugs. */
5338 static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
5339                                        struct sk_buff *skb, u32 last_plus_one,
5340                                        u32 *start, u32 base_flags, u32 mss)
5341 {
5342         struct tg3 *tp = tnapi->tp;
5343         struct sk_buff *new_skb;
5344         dma_addr_t new_addr = 0;
5345         u32 entry = *start;
5346         int i, ret = 0;
5347
5348         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5349                 new_skb = skb_copy(skb, GFP_ATOMIC);
5350         else {
5351                 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5352
5353                 new_skb = skb_copy_expand(skb,
5354                                           skb_headroom(skb) + more_headroom,
5355                                           skb_tailroom(skb), GFP_ATOMIC);
5356         }
5357
5358         if (!new_skb) {
5359                 ret = -1;
5360         } else {
5361                 /* New SKB is guaranteed to be linear. */
5362                 entry = *start;
5363                 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
5364                                           PCI_DMA_TODEVICE);
5365                 /* Make sure the mapping succeeded */
5366                 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
5367                         ret = -1;
5368                         dev_kfree_skb(new_skb);
5369                         new_skb = NULL;
5370
5371                 /* Make sure new skb does not cross any 4G boundaries.
5372                  * Drop the packet if it does.
5373                  */
5374                 } else if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5375                             tg3_4g_overflow_test(new_addr, new_skb->len)) {
5376                         pci_unmap_single(tp->pdev, new_addr, new_skb->len,
5377                                          PCI_DMA_TODEVICE);
5378                         ret = -1;
5379                         dev_kfree_skb(new_skb);
5380                         new_skb = NULL;
5381                 } else {
5382                         tg3_set_txd(tnapi, entry, new_addr, new_skb->len,
5383                                     base_flags, 1 | (mss << 1));
5384                         *start = NEXT_TX(entry);
5385                 }
5386         }
5387
5388         /* Now clean up the sw ring entries. */
5389         i = 0;
5390         while (entry != last_plus_one) {
5391                 int len;
5392
5393                 if (i == 0)
5394                         len = skb_headlen(skb);
5395                 else
5396                         len = skb_shinfo(skb)->frags[i-1].size;
5397
5398                 pci_unmap_single(tp->pdev,
5399                                  pci_unmap_addr(&tnapi->tx_buffers[entry],
5400                                                 mapping),
5401                                  len, PCI_DMA_TODEVICE);
5402                 if (i == 0) {
5403                         tnapi->tx_buffers[entry].skb = new_skb;
5404                         pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5405                                            new_addr);
5406                 } else {
5407                         tnapi->tx_buffers[entry].skb = NULL;
5408                 }
5409                 entry = NEXT_TX(entry);
5410                 i++;
5411         }
5412
5413         dev_kfree_skb(skb);
5414
5415         return ret;
5416 }
5417
5418 static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
5419                         dma_addr_t mapping, int len, u32 flags,
5420                         u32 mss_and_is_end)
5421 {
5422         struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
5423         int is_end = (mss_and_is_end & 0x1);
5424         u32 mss = (mss_and_is_end >> 1);
5425         u32 vlan_tag = 0;
5426
5427         if (is_end)
5428                 flags |= TXD_FLAG_END;
5429         if (flags & TXD_FLAG_VLAN) {
5430                 vlan_tag = flags >> 16;
5431                 flags &= 0xffff;
5432         }
5433         vlan_tag |= (mss << TXD_MSS_SHIFT);
5434
5435         txd->addr_hi = ((u64) mapping >> 32);
5436         txd->addr_lo = ((u64) mapping & 0xffffffff);
5437         txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5438         txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5439 }
5440
5441 /* hard_start_xmit for devices that don't have any bugs and
5442  * support TG3_FLG2_HW_TSO_2 and TG3_FLG2_HW_TSO_3 only.
5443  */
5444 static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5445                                   struct net_device *dev)
5446 {
5447         struct tg3 *tp = netdev_priv(dev);
5448         u32 len, entry, base_flags, mss;
5449         dma_addr_t mapping;
5450         struct tg3_napi *tnapi;
5451         struct netdev_queue *txq;
5452         unsigned int i, last;
5453
5454
5455         txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5456         tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5457         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
5458                 tnapi++;
5459
5460         /* We are running in BH disabled context with netif_tx_lock
5461          * and TX reclaim runs via tp->napi.poll inside of a software
5462          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5463          * no IRQ context deadlocks to worry about either.  Rejoice!
5464          */
5465         if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5466                 if (!netif_tx_queue_stopped(txq)) {
5467                         netif_tx_stop_queue(txq);
5468
5469                         /* This is a hard error, log it. */
5470                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5471                                "queue awake!\n", dev->name);
5472                 }
5473                 return NETDEV_TX_BUSY;
5474         }
5475
5476         entry = tnapi->tx_prod;
5477         base_flags = 0;
5478         mss = 0;
5479         if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5480                 int tcp_opt_len, ip_tcp_len;
5481                 u32 hdrlen;
5482
5483                 if (skb_header_cloned(skb) &&
5484                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5485                         dev_kfree_skb(skb);
5486                         goto out_unlock;
5487                 }
5488
5489                 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
5490                         hdrlen = skb_headlen(skb) - ETH_HLEN;
5491                 else {
5492                         struct iphdr *iph = ip_hdr(skb);
5493
5494                         tcp_opt_len = tcp_optlen(skb);
5495                         ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5496
5497                         iph->check = 0;
5498                         iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
5499                         hdrlen = ip_tcp_len + tcp_opt_len;
5500                 }
5501
5502                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5503                         mss |= (hdrlen & 0xc) << 12;
5504                         if (hdrlen & 0x10)
5505                                 base_flags |= 0x00000010;
5506                         base_flags |= (hdrlen & 0x3e0) << 5;
5507                 } else
5508                         mss |= hdrlen << 9;
5509
5510                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5511                                TXD_FLAG_CPU_POST_DMA);
5512
5513                 tcp_hdr(skb)->check = 0;
5514
5515         }
5516         else if (skb->ip_summed == CHECKSUM_PARTIAL)
5517                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5518 #if TG3_VLAN_TAG_USED
5519         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5520                 base_flags |= (TXD_FLAG_VLAN |
5521                                (vlan_tx_tag_get(skb) << 16));
5522 #endif
5523
5524         len = skb_headlen(skb);
5525
5526         /* Queue skb data, a.k.a. the main skb fragment. */
5527         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5528         if (pci_dma_mapping_error(tp->pdev, mapping)) {
5529                 dev_kfree_skb(skb);
5530                 goto out_unlock;
5531         }
5532
5533         tnapi->tx_buffers[entry].skb = skb;
5534         pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
5535
5536         if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
5537             !mss && skb->len > ETH_DATA_LEN)
5538                 base_flags |= TXD_FLAG_JMB_PKT;
5539
5540         tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5541                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5542
5543         entry = NEXT_TX(entry);
5544
5545         /* Now loop through additional data fragments, and queue them. */
5546         if (skb_shinfo(skb)->nr_frags > 0) {
5547                 last = skb_shinfo(skb)->nr_frags - 1;
5548                 for (i = 0; i <= last; i++) {
5549                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5550
5551                         len = frag->size;
5552                         mapping = pci_map_page(tp->pdev,
5553                                                frag->page,
5554                                                frag->page_offset,
5555                                                len, PCI_DMA_TODEVICE);
5556                         if (pci_dma_mapping_error(tp->pdev, mapping))
5557                                 goto dma_error;
5558
5559                         tnapi->tx_buffers[entry].skb = NULL;
5560                         pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5561                                            mapping);
5562
5563                         tg3_set_txd(tnapi, entry, mapping, len,
5564                                     base_flags, (i == last) | (mss << 1));
5565
5566                         entry = NEXT_TX(entry);
5567                 }
5568         }
5569
5570         /* Packets are ready, update Tx producer idx local and on card. */
5571         tw32_tx_mbox(tnapi->prodmbox, entry);
5572
5573         tnapi->tx_prod = entry;
5574         if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5575                 netif_tx_stop_queue(txq);
5576                 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5577                         netif_tx_wake_queue(txq);
5578         }
5579
5580 out_unlock:
5581         mmiowb();
5582
5583         return NETDEV_TX_OK;
5584
5585 dma_error:
5586         last = i;
5587         entry = tnapi->tx_prod;
5588         tnapi->tx_buffers[entry].skb = NULL;
5589         pci_unmap_single(tp->pdev,
5590                          pci_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5591                          skb_headlen(skb),
5592                          PCI_DMA_TODEVICE);
5593         for (i = 0; i <= last; i++) {
5594                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5595                 entry = NEXT_TX(entry);
5596
5597                 pci_unmap_page(tp->pdev,
5598                                pci_unmap_addr(&tnapi->tx_buffers[entry],
5599                                               mapping),
5600                                frag->size, PCI_DMA_TODEVICE);
5601         }
5602
5603         dev_kfree_skb(skb);
5604         return NETDEV_TX_OK;
5605 }
5606
5607 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *,
5608                                           struct net_device *);
5609
5610 /* Use GSO to workaround a rare TSO bug that may be triggered when the
5611  * TSO header is greater than 80 bytes.
5612  */
5613 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5614 {
5615         struct sk_buff *segs, *nskb;
5616         u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
5617
5618         /* Estimate the number of fragments in the worst case */
5619         if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
5620                 netif_stop_queue(tp->dev);
5621                 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
5622                         return NETDEV_TX_BUSY;
5623
5624                 netif_wake_queue(tp->dev);
5625         }
5626
5627         segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
5628         if (IS_ERR(segs))
5629                 goto tg3_tso_bug_end;
5630
5631         do {
5632                 nskb = segs;
5633                 segs = segs->next;
5634                 nskb->next = NULL;
5635                 tg3_start_xmit_dma_bug(nskb, tp->dev);
5636         } while (segs);
5637
5638 tg3_tso_bug_end:
5639         dev_kfree_skb(skb);
5640
5641         return NETDEV_TX_OK;
5642 }
5643
5644 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5645  * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5646  */
5647 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
5648                                           struct net_device *dev)
5649 {
5650         struct tg3 *tp = netdev_priv(dev);
5651         u32 len, entry, base_flags, mss;
5652         int would_hit_hwbug;
5653         dma_addr_t mapping;
5654         struct tg3_napi *tnapi;
5655         struct netdev_queue *txq;
5656         unsigned int i, last;
5657
5658
5659         txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5660         tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5661         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
5662                 tnapi++;
5663
5664         /* We are running in BH disabled context with netif_tx_lock
5665          * and TX reclaim runs via tp->napi.poll inside of a software
5666          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5667          * no IRQ context deadlocks to worry about either.  Rejoice!
5668          */
5669         if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5670                 if (!netif_tx_queue_stopped(txq)) {
5671                         netif_tx_stop_queue(txq);
5672
5673                         /* This is a hard error, log it. */
5674                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5675                                "queue awake!\n", dev->name);
5676                 }
5677                 return NETDEV_TX_BUSY;
5678         }
5679
5680         entry = tnapi->tx_prod;
5681         base_flags = 0;
5682         if (skb->ip_summed == CHECKSUM_PARTIAL)
5683                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5684
5685         if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5686                 struct iphdr *iph;
5687                 u32 tcp_opt_len, ip_tcp_len, hdr_len;
5688
5689                 if (skb_header_cloned(skb) &&
5690                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5691                         dev_kfree_skb(skb);
5692                         goto out_unlock;
5693                 }
5694
5695                 tcp_opt_len = tcp_optlen(skb);
5696                 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5697
5698                 hdr_len = ip_tcp_len + tcp_opt_len;
5699                 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
5700                              (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
5701                         return (tg3_tso_bug(tp, skb));
5702
5703                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5704                                TXD_FLAG_CPU_POST_DMA);
5705
5706                 iph = ip_hdr(skb);
5707                 iph->check = 0;
5708                 iph->tot_len = htons(mss + hdr_len);
5709                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
5710                         tcp_hdr(skb)->check = 0;
5711                         base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
5712                 } else
5713                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5714                                                                  iph->daddr, 0,
5715                                                                  IPPROTO_TCP,
5716                                                                  0);
5717
5718                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5719                         mss |= (hdr_len & 0xc) << 12;
5720                         if (hdr_len & 0x10)
5721                                 base_flags |= 0x00000010;
5722                         base_flags |= (hdr_len & 0x3e0) << 5;
5723                 } else if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)
5724                         mss |= hdr_len << 9;
5725                 else if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_1) ||
5726                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5727                         if (tcp_opt_len || iph->ihl > 5) {
5728                                 int tsflags;
5729
5730                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5731                                 mss |= (tsflags << 11);
5732                         }
5733                 } else {
5734                         if (tcp_opt_len || iph->ihl > 5) {
5735                                 int tsflags;
5736
5737                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5738                                 base_flags |= tsflags << 12;
5739                         }
5740                 }
5741         }
5742 #if TG3_VLAN_TAG_USED
5743         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5744                 base_flags |= (TXD_FLAG_VLAN |
5745                                (vlan_tx_tag_get(skb) << 16));
5746 #endif
5747
5748         if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
5749             !mss && skb->len > ETH_DATA_LEN)
5750                 base_flags |= TXD_FLAG_JMB_PKT;
5751
5752         len = skb_headlen(skb);
5753
5754         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5755         if (pci_dma_mapping_error(tp->pdev, mapping)) {
5756                 dev_kfree_skb(skb);
5757                 goto out_unlock;
5758         }
5759
5760         tnapi->tx_buffers[entry].skb = skb;
5761         pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
5762
5763         would_hit_hwbug = 0;
5764
5765         if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) && len <= 8)
5766                 would_hit_hwbug = 1;
5767
5768         if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5769             tg3_4g_overflow_test(mapping, len))
5770                 would_hit_hwbug = 1;
5771
5772         if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5773             tg3_40bit_overflow_test(tp, mapping, len))
5774                 would_hit_hwbug = 1;
5775
5776         if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
5777                 would_hit_hwbug = 1;
5778
5779         tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5780                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5781
5782         entry = NEXT_TX(entry);
5783
5784         /* Now loop through additional data fragments, and queue them. */
5785         if (skb_shinfo(skb)->nr_frags > 0) {
5786                 last = skb_shinfo(skb)->nr_frags - 1;
5787                 for (i = 0; i <= last; i++) {
5788                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5789
5790                         len = frag->size;
5791                         mapping = pci_map_page(tp->pdev,
5792                                                frag->page,
5793                                                frag->page_offset,
5794                                                len, PCI_DMA_TODEVICE);
5795
5796                         tnapi->tx_buffers[entry].skb = NULL;
5797                         pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5798                                            mapping);
5799                         if (pci_dma_mapping_error(tp->pdev, mapping))
5800                                 goto dma_error;
5801
5802                         if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) &&
5803                             len <= 8)
5804                                 would_hit_hwbug = 1;
5805
5806                         if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5807                             tg3_4g_overflow_test(mapping, len))
5808                                 would_hit_hwbug = 1;
5809
5810                         if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5811                             tg3_40bit_overflow_test(tp, mapping, len))
5812                                 would_hit_hwbug = 1;
5813
5814                         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5815                                 tg3_set_txd(tnapi, entry, mapping, len,
5816                                             base_flags, (i == last)|(mss << 1));
5817                         else
5818                                 tg3_set_txd(tnapi, entry, mapping, len,
5819                                             base_flags, (i == last));
5820
5821                         entry = NEXT_TX(entry);
5822                 }
5823         }
5824
5825         if (would_hit_hwbug) {
5826                 u32 last_plus_one = entry;
5827                 u32 start;
5828
5829                 start = entry - 1 - skb_shinfo(skb)->nr_frags;
5830                 start &= (TG3_TX_RING_SIZE - 1);
5831
5832                 /* If the workaround fails due to memory/mapping
5833                  * failure, silently drop this packet.
5834                  */
5835                 if (tigon3_dma_hwbug_workaround(tnapi, skb, last_plus_one,
5836                                                 &start, base_flags, mss))
5837                         goto out_unlock;
5838
5839                 entry = start;
5840         }
5841
5842         /* Packets are ready, update Tx producer idx local and on card. */
5843         tw32_tx_mbox(tnapi->prodmbox, entry);
5844
5845         tnapi->tx_prod = entry;
5846         if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5847                 netif_tx_stop_queue(txq);
5848                 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5849                         netif_tx_wake_queue(txq);
5850         }
5851
5852 out_unlock:
5853         mmiowb();
5854
5855         return NETDEV_TX_OK;
5856
5857 dma_error:
5858         last = i;
5859         entry = tnapi->tx_prod;
5860         tnapi->tx_buffers[entry].skb = NULL;
5861         pci_unmap_single(tp->pdev,
5862                          pci_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5863                          skb_headlen(skb),
5864                          PCI_DMA_TODEVICE);
5865         for (i = 0; i <= last; i++) {
5866                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5867                 entry = NEXT_TX(entry);
5868
5869                 pci_unmap_page(tp->pdev,
5870                                pci_unmap_addr(&tnapi->tx_buffers[entry],
5871                                               mapping),
5872                                frag->size, PCI_DMA_TODEVICE);
5873         }
5874
5875         dev_kfree_skb(skb);
5876         return NETDEV_TX_OK;
5877 }
5878
5879 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
5880                                int new_mtu)
5881 {
5882         dev->mtu = new_mtu;
5883
5884         if (new_mtu > ETH_DATA_LEN) {
5885                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
5886                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
5887                         ethtool_op_set_tso(dev, 0);
5888                 }
5889                 else
5890                         tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
5891         } else {
5892                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
5893                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
5894                 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
5895         }
5896 }
5897
5898 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
5899 {
5900         struct tg3 *tp = netdev_priv(dev);
5901         int err;
5902
5903         if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
5904                 return -EINVAL;
5905
5906         if (!netif_running(dev)) {
5907                 /* We'll just catch it later when the
5908                  * device is up'd.
5909                  */
5910                 tg3_set_mtu(dev, tp, new_mtu);
5911                 return 0;
5912         }
5913
5914         tg3_phy_stop(tp);
5915
5916         tg3_netif_stop(tp);
5917
5918         tg3_full_lock(tp, 1);
5919
5920         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5921
5922         tg3_set_mtu(dev, tp, new_mtu);
5923
5924         err = tg3_restart_hw(tp, 0);
5925
5926         if (!err)
5927                 tg3_netif_start(tp);
5928
5929         tg3_full_unlock(tp);
5930
5931         if (!err)
5932                 tg3_phy_start(tp);
5933
5934         return err;
5935 }
5936
5937 static void tg3_rx_prodring_free(struct tg3 *tp,
5938                                  struct tg3_rx_prodring_set *tpr)
5939 {
5940         int i;
5941
5942         if (tpr != &tp->prodring[0]) {
5943                 for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx;
5944                      i = (i + 1) % TG3_RX_RING_SIZE)
5945                         tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
5946                                         tp->rx_pkt_map_sz);
5947
5948                 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
5949                         for (i = tpr->rx_jmb_cons_idx;
5950                              i != tpr->rx_jmb_prod_idx;
5951                              i = (i + 1) % TG3_RX_JUMBO_RING_SIZE) {
5952                                 tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
5953                                                 TG3_RX_JMB_MAP_SZ);
5954                         }
5955                 }
5956
5957                 return;
5958         }
5959
5960         for (i = 0; i < TG3_RX_RING_SIZE; i++)
5961                 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
5962                                 tp->rx_pkt_map_sz);
5963
5964         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
5965                 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++)
5966                         tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
5967                                         TG3_RX_JMB_MAP_SZ);
5968         }
5969 }
5970
5971 /* Initialize tx/rx rings for packet processing.
5972  *
5973  * The chip has been shut down and the driver detached from
5974  * the networking, so no interrupts or new tx packets will
5975  * end up in the driver.  tp->{tx,}lock are held and thus
5976  * we may not sleep.
5977  */
5978 static int tg3_rx_prodring_alloc(struct tg3 *tp,
5979                                  struct tg3_rx_prodring_set *tpr)
5980 {
5981         u32 i, rx_pkt_dma_sz;
5982
5983         tpr->rx_std_cons_idx = 0;
5984         tpr->rx_std_prod_idx = 0;
5985         tpr->rx_jmb_cons_idx = 0;
5986         tpr->rx_jmb_prod_idx = 0;
5987
5988         if (tpr != &tp->prodring[0]) {
5989                 memset(&tpr->rx_std_buffers[0], 0, TG3_RX_STD_BUFF_RING_SIZE);
5990                 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE)
5991                         memset(&tpr->rx_jmb_buffers[0], 0,
5992                                TG3_RX_JMB_BUFF_RING_SIZE);
5993                 goto done;
5994         }
5995
5996         /* Zero out all descriptors. */
5997         memset(tpr->rx_std, 0, TG3_RX_RING_BYTES);
5998
5999         rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
6000         if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
6001             tp->dev->mtu > ETH_DATA_LEN)
6002                 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
6003         tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
6004
6005         /* Initialize invariants of the rings, we only set this
6006          * stuff once.  This works because the card does not
6007          * write into the rx buffer posting rings.
6008          */
6009         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
6010                 struct tg3_rx_buffer_desc *rxd;
6011
6012                 rxd = &tpr->rx_std[i];
6013                 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
6014                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
6015                 rxd->opaque = (RXD_OPAQUE_RING_STD |
6016                                (i << RXD_OPAQUE_INDEX_SHIFT));
6017         }
6018
6019         /* Now allocate fresh SKBs for each rx ring. */
6020         for (i = 0; i < tp->rx_pending; i++) {
6021                 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_STD, i) < 0) {
6022                         printk(KERN_WARNING PFX
6023                                "%s: Using a smaller RX standard ring, "
6024                                "only %d out of %d buffers were allocated "
6025                                "successfully.\n",
6026                                tp->dev->name, i, tp->rx_pending);
6027                         if (i == 0)
6028                                 goto initfail;
6029                         tp->rx_pending = i;
6030                         break;
6031                 }
6032         }
6033
6034         if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE))
6035                 goto done;
6036
6037         memset(tpr->rx_jmb, 0, TG3_RX_JUMBO_RING_BYTES);
6038
6039         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
6040                 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
6041                         struct tg3_rx_buffer_desc *rxd;
6042
6043                         rxd = &tpr->rx_jmb[i].std;
6044                         rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
6045                         rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
6046                                 RXD_FLAG_JUMBO;
6047                         rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
6048                                (i << RXD_OPAQUE_INDEX_SHIFT));
6049                 }
6050
6051                 for (i = 0; i < tp->rx_jumbo_pending; i++) {
6052                         if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_JUMBO,
6053                                              i) < 0) {
6054                                 printk(KERN_WARNING PFX
6055                                        "%s: Using a smaller RX jumbo ring, "
6056                                        "only %d out of %d buffers were "
6057                                        "allocated successfully.\n",
6058                                        tp->dev->name, i, tp->rx_jumbo_pending);
6059                                 if (i == 0)
6060                                         goto initfail;
6061                                 tp->rx_jumbo_pending = i;
6062                                 break;
6063                         }
6064                 }
6065         }
6066
6067 done:
6068         return 0;
6069
6070 initfail:
6071         tg3_rx_prodring_free(tp, tpr);
6072         return -ENOMEM;
6073 }
6074
6075 static void tg3_rx_prodring_fini(struct tg3 *tp,
6076                                  struct tg3_rx_prodring_set *tpr)
6077 {
6078         kfree(tpr->rx_std_buffers);
6079         tpr->rx_std_buffers = NULL;
6080         kfree(tpr->rx_jmb_buffers);
6081         tpr->rx_jmb_buffers = NULL;
6082         if (tpr->rx_std) {
6083                 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
6084                                     tpr->rx_std, tpr->rx_std_mapping);
6085                 tpr->rx_std = NULL;
6086         }
6087         if (tpr->rx_jmb) {
6088                 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
6089                                     tpr->rx_jmb, tpr->rx_jmb_mapping);
6090                 tpr->rx_jmb = NULL;
6091         }
6092 }
6093
6094 static int tg3_rx_prodring_init(struct tg3 *tp,
6095                                 struct tg3_rx_prodring_set *tpr)
6096 {
6097         tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE, GFP_KERNEL);
6098         if (!tpr->rx_std_buffers)
6099                 return -ENOMEM;
6100
6101         tpr->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
6102                                            &tpr->rx_std_mapping);
6103         if (!tpr->rx_std)
6104                 goto err_out;
6105
6106         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
6107                 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE,
6108                                               GFP_KERNEL);
6109                 if (!tpr->rx_jmb_buffers)
6110                         goto err_out;
6111
6112                 tpr->rx_jmb = pci_alloc_consistent(tp->pdev,
6113                                                    TG3_RX_JUMBO_RING_BYTES,
6114                                                    &tpr->rx_jmb_mapping);
6115                 if (!tpr->rx_jmb)
6116                         goto err_out;
6117         }
6118
6119         return 0;
6120
6121 err_out:
6122         tg3_rx_prodring_fini(tp, tpr);
6123         return -ENOMEM;
6124 }
6125
6126 /* Free up pending packets in all rx/tx rings.
6127  *
6128  * The chip has been shut down and the driver detached from
6129  * the networking, so no interrupts or new tx packets will
6130  * end up in the driver.  tp->{tx,}lock is not held and we are not
6131  * in an interrupt context and thus may sleep.
6132  */
6133 static void tg3_free_rings(struct tg3 *tp)
6134 {
6135         int i, j;
6136
6137         for (j = 0; j < tp->irq_cnt; j++) {
6138                 struct tg3_napi *tnapi = &tp->napi[j];
6139
6140                 if (!tnapi->tx_buffers)
6141                         continue;
6142
6143                 for (i = 0; i < TG3_TX_RING_SIZE; ) {
6144                         struct ring_info *txp;
6145                         struct sk_buff *skb;
6146                         unsigned int k;
6147
6148                         txp = &tnapi->tx_buffers[i];
6149                         skb = txp->skb;
6150
6151                         if (skb == NULL) {
6152                                 i++;
6153                                 continue;
6154                         }
6155
6156                         pci_unmap_single(tp->pdev,
6157                                          pci_unmap_addr(txp, mapping),
6158                                          skb_headlen(skb),
6159                                          PCI_DMA_TODEVICE);
6160                         txp->skb = NULL;
6161
6162                         i++;
6163
6164                         for (k = 0; k < skb_shinfo(skb)->nr_frags; k++) {
6165                                 txp = &tnapi->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
6166                                 pci_unmap_page(tp->pdev,
6167                                                pci_unmap_addr(txp, mapping),
6168                                                skb_shinfo(skb)->frags[k].size,
6169                                                PCI_DMA_TODEVICE);
6170                                 i++;
6171                         }
6172
6173                         dev_kfree_skb_any(skb);
6174                 }
6175
6176                 if (tp->irq_cnt == 1 || j != tp->irq_cnt - 1)
6177                         tg3_rx_prodring_free(tp, &tp->prodring[j]);
6178         }
6179 }
6180
6181 /* Initialize tx/rx rings for packet processing.
6182  *
6183  * The chip has been shut down and the driver detached from
6184  * the networking, so no interrupts or new tx packets will
6185  * end up in the driver.  tp->{tx,}lock are held and thus
6186  * we may not sleep.
6187  */
6188 static int tg3_init_rings(struct tg3 *tp)
6189 {
6190         int i;
6191
6192         /* Free up all the SKBs. */
6193         tg3_free_rings(tp);
6194
6195         for (i = 0; i < tp->irq_cnt; i++) {
6196                 struct tg3_napi *tnapi = &tp->napi[i];
6197
6198                 tnapi->last_tag = 0;
6199                 tnapi->last_irq_tag = 0;
6200                 tnapi->hw_status->status = 0;
6201                 tnapi->hw_status->status_tag = 0;
6202                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6203
6204                 tnapi->tx_prod = 0;
6205                 tnapi->tx_cons = 0;
6206                 if (tnapi->tx_ring)
6207                         memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
6208
6209                 tnapi->rx_rcb_ptr = 0;
6210                 if (tnapi->rx_rcb)
6211                         memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6212
6213                 if ((tp->irq_cnt == 1 || i != tp->irq_cnt - 1) &&
6214                         tg3_rx_prodring_alloc(tp, &tp->prodring[i]))
6215                         return -ENOMEM;
6216         }
6217
6218         return 0;
6219 }
6220
6221 /*
6222  * Must not be invoked with interrupt sources disabled and
6223  * the hardware shutdown down.
6224  */
6225 static void tg3_free_consistent(struct tg3 *tp)
6226 {
6227         int i;
6228
6229         for (i = 0; i < tp->irq_cnt; i++) {
6230                 struct tg3_napi *tnapi = &tp->napi[i];
6231
6232                 if (tnapi->tx_ring) {
6233                         pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
6234                                 tnapi->tx_ring, tnapi->tx_desc_mapping);
6235                         tnapi->tx_ring = NULL;
6236                 }
6237
6238                 kfree(tnapi->tx_buffers);
6239                 tnapi->tx_buffers = NULL;
6240
6241                 if (tnapi->rx_rcb) {
6242                         pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
6243                                             tnapi->rx_rcb,
6244                                             tnapi->rx_rcb_mapping);
6245                         tnapi->rx_rcb = NULL;
6246                 }
6247
6248                 if (tnapi->hw_status) {
6249                         pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
6250                                             tnapi->hw_status,
6251                                             tnapi->status_mapping);
6252                         tnapi->hw_status = NULL;
6253                 }
6254         }
6255
6256         if (tp->hw_stats) {
6257                 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
6258                                     tp->hw_stats, tp->stats_mapping);
6259                 tp->hw_stats = NULL;
6260         }
6261
6262         for (i = 0; i < (tp->irq_cnt == 1 ? 1 : tp->irq_cnt - 1); i++)
6263                 tg3_rx_prodring_fini(tp, &tp->prodring[i]);
6264 }
6265
6266 /*
6267  * Must not be invoked with interrupt sources disabled and
6268  * the hardware shutdown down.  Can sleep.
6269  */
6270 static int tg3_alloc_consistent(struct tg3 *tp)
6271 {
6272         int i;
6273
6274         for (i = 0; i < (tp->irq_cnt == 1 ? 1 : tp->irq_cnt - 1); i++) {
6275                 if (tg3_rx_prodring_init(tp, &tp->prodring[i]))
6276                         goto err_out;
6277         }
6278
6279         tp->hw_stats = pci_alloc_consistent(tp->pdev,
6280                                             sizeof(struct tg3_hw_stats),
6281                                             &tp->stats_mapping);
6282         if (!tp->hw_stats)
6283                 goto err_out;
6284
6285         memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6286
6287         for (i = 0; i < tp->irq_cnt; i++) {
6288                 struct tg3_napi *tnapi = &tp->napi[i];
6289                 struct tg3_hw_status *sblk;
6290
6291                 tnapi->hw_status = pci_alloc_consistent(tp->pdev,
6292                                                         TG3_HW_STATUS_SIZE,
6293                                                         &tnapi->status_mapping);
6294                 if (!tnapi->hw_status)
6295                         goto err_out;
6296
6297                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6298                 sblk = tnapi->hw_status;
6299
6300                 /* If multivector TSS is enabled, vector 0 does not handle
6301                  * tx interrupts.  Don't allocate any resources for it.
6302                  */
6303                 if ((!i && !(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) ||
6304                     (i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))) {
6305                         tnapi->tx_buffers = kzalloc(sizeof(struct ring_info) *
6306                                                     TG3_TX_RING_SIZE,
6307                                                     GFP_KERNEL);
6308                         if (!tnapi->tx_buffers)
6309                                 goto err_out;
6310
6311                         tnapi->tx_ring = pci_alloc_consistent(tp->pdev,
6312                                                               TG3_TX_RING_BYTES,
6313                                                        &tnapi->tx_desc_mapping);
6314                         if (!tnapi->tx_ring)
6315                                 goto err_out;
6316                 }
6317
6318                 /*
6319                  * When RSS is enabled, the status block format changes
6320                  * slightly.  The "rx_jumbo_consumer", "reserved",
6321                  * and "rx_mini_consumer" members get mapped to the
6322                  * other three rx return ring producer indexes.
6323                  */
6324                 switch (i) {
6325                 default:
6326                         tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
6327                         break;
6328                 case 2:
6329                         tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer;
6330                         break;
6331                 case 3:
6332                         tnapi->rx_rcb_prod_idx = &sblk->reserved;
6333                         break;
6334                 case 4:
6335                         tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer;
6336                         break;
6337                 }
6338
6339                 if (tp->irq_cnt == 1)
6340                         tnapi->prodring = &tp->prodring[0];
6341                 else if (i)
6342                         tnapi->prodring = &tp->prodring[i - 1];
6343
6344                 /*
6345                  * If multivector RSS is enabled, vector 0 does not handle
6346                  * rx or tx interrupts.  Don't allocate any resources for it.
6347                  */
6348                 if (!i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS))
6349                         continue;
6350
6351                 tnapi->rx_rcb = pci_alloc_consistent(tp->pdev,
6352                                                      TG3_RX_RCB_RING_BYTES(tp),
6353                                                      &tnapi->rx_rcb_mapping);
6354                 if (!tnapi->rx_rcb)
6355                         goto err_out;
6356
6357                 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6358         }
6359
6360         return 0;
6361
6362 err_out:
6363         tg3_free_consistent(tp);
6364         return -ENOMEM;
6365 }
6366
6367 #define MAX_WAIT_CNT 1000
6368
6369 /* To stop a block, clear the enable bit and poll till it
6370  * clears.  tp->lock is held.
6371  */
6372 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
6373 {
6374         unsigned int i;
6375         u32 val;
6376
6377         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6378                 switch (ofs) {
6379                 case RCVLSC_MODE:
6380                 case DMAC_MODE:
6381                 case MBFREE_MODE:
6382                 case BUFMGR_MODE:
6383                 case MEMARB_MODE:
6384                         /* We can't enable/disable these bits of the
6385                          * 5705/5750, just say success.
6386                          */
6387                         return 0;
6388
6389                 default:
6390                         break;
6391                 }
6392         }
6393
6394         val = tr32(ofs);
6395         val &= ~enable_bit;
6396         tw32_f(ofs, val);
6397
6398         for (i = 0; i < MAX_WAIT_CNT; i++) {
6399                 udelay(100);
6400                 val = tr32(ofs);
6401                 if ((val & enable_bit) == 0)
6402                         break;
6403         }
6404
6405         if (i == MAX_WAIT_CNT && !silent) {
6406                 printk(KERN_ERR PFX "tg3_stop_block timed out, "
6407                        "ofs=%lx enable_bit=%x\n",
6408                        ofs, enable_bit);
6409                 return -ENODEV;
6410         }
6411
6412         return 0;
6413 }
6414
6415 /* tp->lock is held. */
6416 static int tg3_abort_hw(struct tg3 *tp, int silent)
6417 {
6418         int i, err;
6419
6420         tg3_disable_ints(tp);
6421
6422         tp->rx_mode &= ~RX_MODE_ENABLE;
6423         tw32_f(MAC_RX_MODE, tp->rx_mode);
6424         udelay(10);
6425
6426         err  = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
6427         err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
6428         err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
6429         err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
6430         err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
6431         err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
6432
6433         err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
6434         err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
6435         err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
6436         err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
6437         err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
6438         err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
6439         err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
6440
6441         tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
6442         tw32_f(MAC_MODE, tp->mac_mode);
6443         udelay(40);
6444
6445         tp->tx_mode &= ~TX_MODE_ENABLE;
6446         tw32_f(MAC_TX_MODE, tp->tx_mode);
6447
6448         for (i = 0; i < MAX_WAIT_CNT; i++) {
6449                 udelay(100);
6450                 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
6451                         break;
6452         }
6453         if (i >= MAX_WAIT_CNT) {
6454                 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
6455                        "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
6456                        tp->dev->name, tr32(MAC_TX_MODE));
6457                 err |= -ENODEV;
6458         }
6459
6460         err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
6461         err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
6462         err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
6463
6464         tw32(FTQ_RESET, 0xffffffff);
6465         tw32(FTQ_RESET, 0x00000000);
6466
6467         err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
6468         err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
6469
6470         for (i = 0; i < tp->irq_cnt; i++) {
6471                 struct tg3_napi *tnapi = &tp->napi[i];
6472                 if (tnapi->hw_status)
6473                         memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6474         }
6475         if (tp->hw_stats)
6476                 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6477
6478         return err;
6479 }
6480
6481 static void tg3_ape_send_event(struct tg3 *tp, u32 event)
6482 {
6483         int i;
6484         u32 apedata;
6485
6486         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
6487         if (apedata != APE_SEG_SIG_MAGIC)
6488                 return;
6489
6490         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
6491         if (!(apedata & APE_FW_STATUS_READY))
6492                 return;
6493
6494         /* Wait for up to 1 millisecond for APE to service previous event. */
6495         for (i = 0; i < 10; i++) {
6496                 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
6497                         return;
6498
6499                 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
6500
6501                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6502                         tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
6503                                         event | APE_EVENT_STATUS_EVENT_PENDING);
6504
6505                 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
6506
6507                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6508                         break;
6509
6510                 udelay(100);
6511         }
6512
6513         if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6514                 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
6515 }
6516
6517 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
6518 {
6519         u32 event;
6520         u32 apedata;
6521
6522         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
6523                 return;
6524
6525         switch (kind) {
6526                 case RESET_KIND_INIT:
6527                         tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
6528                                         APE_HOST_SEG_SIG_MAGIC);
6529                         tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
6530                                         APE_HOST_SEG_LEN_MAGIC);
6531                         apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
6532                         tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
6533                         tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
6534                                         APE_HOST_DRIVER_ID_MAGIC);
6535                         tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
6536                                         APE_HOST_BEHAV_NO_PHYLOCK);
6537
6538                         event = APE_EVENT_STATUS_STATE_START;
6539                         break;
6540                 case RESET_KIND_SHUTDOWN:
6541                         /* With the interface we are currently using,
6542                          * APE does not track driver state.  Wiping
6543                          * out the HOST SEGMENT SIGNATURE forces
6544                          * the APE to assume OS absent status.
6545                          */
6546                         tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
6547
6548                         event = APE_EVENT_STATUS_STATE_UNLOAD;
6549                         break;
6550                 case RESET_KIND_SUSPEND:
6551                         event = APE_EVENT_STATUS_STATE_SUSPEND;
6552                         break;
6553                 default:
6554                         return;
6555         }
6556
6557         event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
6558
6559         tg3_ape_send_event(tp, event);
6560 }
6561
6562 /* tp->lock is held. */
6563 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
6564 {
6565         tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
6566                       NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
6567
6568         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6569                 switch (kind) {
6570                 case RESET_KIND_INIT:
6571                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6572                                       DRV_STATE_START);
6573                         break;
6574
6575                 case RESET_KIND_SHUTDOWN:
6576                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6577                                       DRV_STATE_UNLOAD);
6578                         break;
6579
6580                 case RESET_KIND_SUSPEND:
6581                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6582                                       DRV_STATE_SUSPEND);
6583                         break;
6584
6585                 default:
6586                         break;
6587                 }
6588         }
6589
6590         if (kind == RESET_KIND_INIT ||
6591             kind == RESET_KIND_SUSPEND)
6592                 tg3_ape_driver_state_change(tp, kind);
6593 }
6594
6595 /* tp->lock is held. */
6596 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
6597 {
6598         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6599                 switch (kind) {
6600                 case RESET_KIND_INIT:
6601                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6602                                       DRV_STATE_START_DONE);
6603                         break;
6604
6605                 case RESET_KIND_SHUTDOWN:
6606                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6607                                       DRV_STATE_UNLOAD_DONE);
6608                         break;
6609
6610                 default:
6611                         break;
6612                 }
6613         }
6614
6615         if (kind == RESET_KIND_SHUTDOWN)
6616                 tg3_ape_driver_state_change(tp, kind);
6617 }
6618
6619 /* tp->lock is held. */
6620 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
6621 {
6622         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6623                 switch (kind) {
6624                 case RESET_KIND_INIT:
6625                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6626                                       DRV_STATE_START);
6627                         break;
6628
6629                 case RESET_KIND_SHUTDOWN:
6630                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6631                                       DRV_STATE_UNLOAD);
6632                         break;
6633
6634                 case RESET_KIND_SUSPEND:
6635                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6636                                       DRV_STATE_SUSPEND);
6637                         break;
6638
6639                 default:
6640                         break;
6641                 }
6642         }
6643 }
6644
6645 static int tg3_poll_fw(struct tg3 *tp)
6646 {
6647         int i;
6648         u32 val;
6649
6650         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6651                 /* Wait up to 20ms for init done. */
6652                 for (i = 0; i < 200; i++) {
6653                         if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
6654                                 return 0;
6655                         udelay(100);
6656                 }
6657                 return -ENODEV;
6658         }
6659
6660         /* Wait for firmware initialization to complete. */
6661         for (i = 0; i < 100000; i++) {
6662                 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
6663                 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
6664                         break;
6665                 udelay(10);
6666         }
6667
6668         /* Chip might not be fitted with firmware.  Some Sun onboard
6669          * parts are configured like that.  So don't signal the timeout
6670          * of the above loop as an error, but do report the lack of
6671          * running firmware once.
6672          */
6673         if (i >= 100000 &&
6674             !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
6675                 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
6676
6677                 printk(KERN_INFO PFX "%s: No firmware running.\n",
6678                        tp->dev->name);
6679         }
6680
6681         return 0;
6682 }
6683
6684 /* Save PCI command register before chip reset */
6685 static void tg3_save_pci_state(struct tg3 *tp)
6686 {
6687         pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
6688 }
6689
6690 /* Restore PCI state after chip reset */
6691 static void tg3_restore_pci_state(struct tg3 *tp)
6692 {
6693         u32 val;
6694
6695         /* Re-enable indirect register accesses. */
6696         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
6697                                tp->misc_host_ctrl);
6698
6699         /* Set MAX PCI retry to zero. */
6700         val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
6701         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6702             (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
6703                 val |= PCISTATE_RETRY_SAME_DMA;
6704         /* Allow reads and writes to the APE register and memory space. */
6705         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
6706                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6707                        PCISTATE_ALLOW_APE_SHMEM_WR;
6708         pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
6709
6710         pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
6711
6712         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
6713                 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6714                         pcie_set_readrq(tp->pdev, 4096);
6715                 else {
6716                         pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
6717                                               tp->pci_cacheline_sz);
6718                         pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
6719                                               tp->pci_lat_timer);
6720                 }
6721         }
6722
6723         /* Make sure PCI-X relaxed ordering bit is clear. */
6724         if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
6725                 u16 pcix_cmd;
6726
6727                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6728                                      &pcix_cmd);
6729                 pcix_cmd &= ~PCI_X_CMD_ERO;
6730                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6731                                       pcix_cmd);
6732         }
6733
6734         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
6735
6736                 /* Chip reset on 5780 will reset MSI enable bit,
6737                  * so need to restore it.
6738                  */
6739                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6740                         u16 ctrl;
6741
6742                         pci_read_config_word(tp->pdev,
6743                                              tp->msi_cap + PCI_MSI_FLAGS,
6744                                              &ctrl);
6745                         pci_write_config_word(tp->pdev,
6746                                               tp->msi_cap + PCI_MSI_FLAGS,
6747                                               ctrl | PCI_MSI_FLAGS_ENABLE);
6748                         val = tr32(MSGINT_MODE);
6749                         tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
6750                 }
6751         }
6752 }
6753
6754 static void tg3_stop_fw(struct tg3 *);
6755
6756 /* tp->lock is held. */
6757 static int tg3_chip_reset(struct tg3 *tp)
6758 {
6759         u32 val;
6760         void (*write_op)(struct tg3 *, u32, u32);
6761         int i, err;
6762
6763         tg3_nvram_lock(tp);
6764
6765         tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
6766
6767         /* No matching tg3_nvram_unlock() after this because
6768          * chip reset below will undo the nvram lock.
6769          */
6770         tp->nvram_lock_cnt = 0;
6771
6772         /* GRC_MISC_CFG core clock reset will clear the memory
6773          * enable bit in PCI register 4 and the MSI enable bit
6774          * on some chips, so we save relevant registers here.
6775          */
6776         tg3_save_pci_state(tp);
6777
6778         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
6779             (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
6780                 tw32(GRC_FASTBOOT_PC, 0);
6781
6782         /*
6783          * We must avoid the readl() that normally takes place.
6784          * It locks machines, causes machine checks, and other
6785          * fun things.  So, temporarily disable the 5701
6786          * hardware workaround, while we do the reset.
6787          */
6788         write_op = tp->write32;
6789         if (write_op == tg3_write_flush_reg32)
6790                 tp->write32 = tg3_write32;
6791
6792         /* Prevent the irq handler from reading or writing PCI registers
6793          * during chip reset when the memory enable bit in the PCI command
6794          * register may be cleared.  The chip does not generate interrupt
6795          * at this time, but the irq handler may still be called due to irq
6796          * sharing or irqpoll.
6797          */
6798         tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
6799         for (i = 0; i < tp->irq_cnt; i++) {
6800                 struct tg3_napi *tnapi = &tp->napi[i];
6801                 if (tnapi->hw_status) {
6802                         tnapi->hw_status->status = 0;
6803                         tnapi->hw_status->status_tag = 0;
6804                 }
6805                 tnapi->last_tag = 0;
6806                 tnapi->last_irq_tag = 0;
6807         }
6808         smp_mb();
6809
6810         for (i = 0; i < tp->irq_cnt; i++)
6811                 synchronize_irq(tp->napi[i].irq_vec);
6812
6813         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6814                 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
6815                 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
6816         }
6817
6818         /* do the reset */
6819         val = GRC_MISC_CFG_CORECLK_RESET;
6820
6821         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
6822                 if (tr32(0x7e2c) == 0x60) {
6823                         tw32(0x7e2c, 0x20);
6824                 }
6825                 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6826                         tw32(GRC_MISC_CFG, (1 << 29));
6827                         val |= (1 << 29);
6828                 }
6829         }
6830
6831         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6832                 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
6833                 tw32(GRC_VCPU_EXT_CTRL,
6834                      tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
6835         }
6836
6837         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6838                 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
6839         tw32(GRC_MISC_CFG, val);
6840
6841         /* restore 5701 hardware bug workaround write method */
6842         tp->write32 = write_op;
6843
6844         /* Unfortunately, we have to delay before the PCI read back.
6845          * Some 575X chips even will not respond to a PCI cfg access
6846          * when the reset command is given to the chip.
6847          *
6848          * How do these hardware designers expect things to work
6849          * properly if the PCI write is posted for a long period
6850          * of time?  It is always necessary to have some method by
6851          * which a register read back can occur to push the write
6852          * out which does the reset.
6853          *
6854          * For most tg3 variants the trick below was working.
6855          * Ho hum...
6856          */
6857         udelay(120);
6858
6859         /* Flush PCI posted writes.  The normal MMIO registers
6860          * are inaccessible at this time so this is the only
6861          * way to make this reliably (actually, this is no longer
6862          * the case, see above).  I tried to use indirect
6863          * register read/write but this upset some 5701 variants.
6864          */
6865         pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
6866
6867         udelay(120);
6868
6869         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
6870                 u16 val16;
6871
6872                 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
6873                         int i;
6874                         u32 cfg_val;
6875
6876                         /* Wait for link training to complete.  */
6877                         for (i = 0; i < 5000; i++)
6878                                 udelay(100);
6879
6880                         pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
6881                         pci_write_config_dword(tp->pdev, 0xc4,
6882                                                cfg_val | (1 << 15));
6883                 }
6884
6885                 /* Clear the "no snoop" and "relaxed ordering" bits. */
6886                 pci_read_config_word(tp->pdev,
6887                                      tp->pcie_cap + PCI_EXP_DEVCTL,
6888                                      &val16);
6889                 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
6890                            PCI_EXP_DEVCTL_NOSNOOP_EN);
6891                 /*
6892                  * Older PCIe devices only support the 128 byte
6893                  * MPS setting.  Enforce the restriction.
6894                  */
6895                 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
6896                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784))
6897                         val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
6898                 pci_write_config_word(tp->pdev,
6899                                       tp->pcie_cap + PCI_EXP_DEVCTL,
6900                                       val16);
6901
6902                 pcie_set_readrq(tp->pdev, 4096);
6903
6904                 /* Clear error status */
6905                 pci_write_config_word(tp->pdev,
6906                                       tp->pcie_cap + PCI_EXP_DEVSTA,
6907                                       PCI_EXP_DEVSTA_CED |
6908                                       PCI_EXP_DEVSTA_NFED |
6909                                       PCI_EXP_DEVSTA_FED |
6910                                       PCI_EXP_DEVSTA_URD);
6911         }
6912
6913         tg3_restore_pci_state(tp);
6914
6915         tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
6916
6917         val = 0;
6918         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
6919                 val = tr32(MEMARB_MODE);
6920         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
6921
6922         if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
6923                 tg3_stop_fw(tp);
6924                 tw32(0x5000, 0x400);
6925         }
6926
6927         tw32(GRC_MODE, tp->grc_mode);
6928
6929         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
6930                 val = tr32(0xc4);
6931
6932                 tw32(0xc4, val | (1 << 15));
6933         }
6934
6935         if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
6936             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6937                 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
6938                 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
6939                         tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
6940                 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6941         }
6942
6943         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6944                 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
6945                 tw32_f(MAC_MODE, tp->mac_mode);
6946         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
6947                 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
6948                 tw32_f(MAC_MODE, tp->mac_mode);
6949         } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
6950                 tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
6951                 if (tp->mac_mode & MAC_MODE_APE_TX_EN)
6952                         tp->mac_mode |= MAC_MODE_TDE_ENABLE;
6953                 tw32_f(MAC_MODE, tp->mac_mode);
6954         } else
6955                 tw32_f(MAC_MODE, 0);
6956         udelay(40);
6957
6958         tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
6959
6960         err = tg3_poll_fw(tp);
6961         if (err)
6962                 return err;
6963
6964         tg3_mdio_start(tp);
6965
6966         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6967                 u8 phy_addr;
6968
6969                 phy_addr = tp->phy_addr;
6970                 tp->phy_addr = TG3_PHY_PCIE_ADDR;
6971
6972                 tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR,
6973                              TG3_PCIEPHY_TXB_BLK << TG3_PCIEPHY_BLOCK_SHIFT);
6974                 val = TG3_PCIEPHY_TX0CTRL1_TXOCM | TG3_PCIEPHY_TX0CTRL1_RDCTL |
6975                       TG3_PCIEPHY_TX0CTRL1_TXCMV | TG3_PCIEPHY_TX0CTRL1_TKSEL |
6976                       TG3_PCIEPHY_TX0CTRL1_NB_EN;
6977                 tg3_writephy(tp, TG3_PCIEPHY_TX0CTRL1, val);
6978                 udelay(10);
6979
6980                 tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR,
6981                              TG3_PCIEPHY_XGXS_BLK1 << TG3_PCIEPHY_BLOCK_SHIFT);
6982                 val = TG3_PCIEPHY_PWRMGMT4_LOWPWR_EN |
6983                       TG3_PCIEPHY_PWRMGMT4_L1PLLPD_EN;
6984                 tg3_writephy(tp, TG3_PCIEPHY_PWRMGMT4, val);
6985                 udelay(10);
6986
6987                 tp->phy_addr = phy_addr;
6988         }
6989
6990         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
6991             tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
6992             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
6993             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
6994             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765) {
6995                 val = tr32(0x7c00);
6996
6997                 tw32(0x7c00, val | (1 << 25));
6998         }
6999
7000         /* Reprobe ASF enable state.  */
7001         tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
7002         tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
7003         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
7004         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
7005                 u32 nic_cfg;
7006
7007                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
7008                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
7009                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
7010                         tp->last_event_jiffies = jiffies;
7011                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
7012                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
7013                 }
7014         }
7015
7016         return 0;
7017 }
7018
7019 /* tp->lock is held. */
7020 static void tg3_stop_fw(struct tg3 *tp)
7021 {
7022         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
7023            !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7024                 /* Wait for RX cpu to ACK the previous event. */
7025                 tg3_wait_for_event_ack(tp);
7026
7027                 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
7028
7029                 tg3_generate_fw_event(tp);
7030
7031                 /* Wait for RX cpu to ACK this event. */
7032                 tg3_wait_for_event_ack(tp);
7033         }
7034 }
7035
7036 /* tp->lock is held. */
7037 static int tg3_halt(struct tg3 *tp, int kind, int silent)
7038 {
7039         int err;
7040
7041         tg3_stop_fw(tp);
7042
7043         tg3_write_sig_pre_reset(tp, kind);
7044
7045         tg3_abort_hw(tp, silent);
7046         err = tg3_chip_reset(tp);
7047
7048         __tg3_set_mac_addr(tp, 0);
7049
7050         tg3_write_sig_legacy(tp, kind);
7051         tg3_write_sig_post_reset(tp, kind);
7052
7053         if (err)
7054                 return err;
7055
7056         return 0;
7057 }
7058
7059 #define RX_CPU_SCRATCH_BASE     0x30000
7060 #define RX_CPU_SCRATCH_SIZE     0x04000
7061 #define TX_CPU_SCRATCH_BASE     0x34000
7062 #define TX_CPU_SCRATCH_SIZE     0x04000
7063
7064 /* tp->lock is held. */
7065 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
7066 {
7067         int i;
7068
7069         BUG_ON(offset == TX_CPU_BASE &&
7070             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
7071
7072         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7073                 u32 val = tr32(GRC_VCPU_EXT_CTRL);
7074
7075                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
7076                 return 0;
7077         }
7078         if (offset == RX_CPU_BASE) {
7079                 for (i = 0; i < 10000; i++) {
7080                         tw32(offset + CPU_STATE, 0xffffffff);
7081                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
7082                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7083                                 break;
7084                 }
7085
7086                 tw32(offset + CPU_STATE, 0xffffffff);
7087                 tw32_f(offset + CPU_MODE,  CPU_MODE_HALT);
7088                 udelay(10);
7089         } else {
7090                 for (i = 0; i < 10000; i++) {
7091                         tw32(offset + CPU_STATE, 0xffffffff);
7092                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
7093                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7094                                 break;
7095                 }
7096         }
7097
7098         if (i >= 10000) {
7099                 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
7100                        "and %s CPU\n",
7101                        tp->dev->name,
7102                        (offset == RX_CPU_BASE ? "RX" : "TX"));
7103                 return -ENODEV;
7104         }
7105
7106         /* Clear firmware's nvram arbitration. */
7107         if (tp->tg3_flags & TG3_FLAG_NVRAM)
7108                 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
7109         return 0;
7110 }
7111
7112 struct fw_info {
7113         unsigned int fw_base;
7114         unsigned int fw_len;
7115         const __be32 *fw_data;
7116 };
7117
7118 /* tp->lock is held. */
7119 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
7120                                  int cpu_scratch_size, struct fw_info *info)
7121 {
7122         int err, lock_err, i;
7123         void (*write_op)(struct tg3 *, u32, u32);
7124
7125         if (cpu_base == TX_CPU_BASE &&
7126             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7127                 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
7128                        "TX cpu firmware on %s which is 5705.\n",
7129                        tp->dev->name);
7130                 return -EINVAL;
7131         }
7132
7133         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7134                 write_op = tg3_write_mem;
7135         else
7136                 write_op = tg3_write_indirect_reg32;
7137
7138         /* It is possible that bootcode is still loading at this point.
7139          * Get the nvram lock first before halting the cpu.
7140          */
7141         lock_err = tg3_nvram_lock(tp);
7142         err = tg3_halt_cpu(tp, cpu_base);
7143         if (!lock_err)
7144                 tg3_nvram_unlock(tp);
7145         if (err)
7146                 goto out;
7147
7148         for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
7149                 write_op(tp, cpu_scratch_base + i, 0);
7150         tw32(cpu_base + CPU_STATE, 0xffffffff);
7151         tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
7152         for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
7153                 write_op(tp, (cpu_scratch_base +
7154                               (info->fw_base & 0xffff) +
7155                               (i * sizeof(u32))),
7156                               be32_to_cpu(info->fw_data[i]));
7157
7158         err = 0;
7159
7160 out:
7161         return err;
7162 }
7163
7164 /* tp->lock is held. */
7165 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
7166 {
7167         struct fw_info info;
7168         const __be32 *fw_data;
7169         int err, i;
7170
7171         fw_data = (void *)tp->fw->data;
7172
7173         /* Firmware blob starts with version numbers, followed by
7174            start address and length. We are setting complete length.
7175            length = end_address_of_bss - start_address_of_text.
7176            Remainder is the blob to be loaded contiguously
7177            from start address. */
7178
7179         info.fw_base = be32_to_cpu(fw_data[1]);
7180         info.fw_len = tp->fw->size - 12;
7181         info.fw_data = &fw_data[3];
7182
7183         err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
7184                                     RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
7185                                     &info);
7186         if (err)
7187                 return err;
7188
7189         err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
7190                                     TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
7191                                     &info);
7192         if (err)
7193                 return err;
7194
7195         /* Now startup only the RX cpu. */
7196         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7197         tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
7198
7199         for (i = 0; i < 5; i++) {
7200                 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
7201                         break;
7202                 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7203                 tw32(RX_CPU_BASE + CPU_MODE,  CPU_MODE_HALT);
7204                 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
7205                 udelay(1000);
7206         }
7207         if (i >= 5) {
7208                 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
7209                        "to set RX CPU PC, is %08x should be %08x\n",
7210                        tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
7211                        info.fw_base);
7212                 return -ENODEV;
7213         }
7214         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7215         tw32_f(RX_CPU_BASE + CPU_MODE,  0x00000000);
7216
7217         return 0;
7218 }
7219
7220 /* 5705 needs a special version of the TSO firmware.  */
7221
7222 /* tp->lock is held. */
7223 static int tg3_load_tso_firmware(struct tg3 *tp)
7224 {
7225         struct fw_info info;
7226         const __be32 *fw_data;
7227         unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
7228         int err, i;
7229
7230         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7231                 return 0;
7232
7233         fw_data = (void *)tp->fw->data;
7234
7235         /* Firmware blob starts with version numbers, followed by
7236            start address and length. We are setting complete length.
7237            length = end_address_of_bss - start_address_of_text.
7238            Remainder is the blob to be loaded contiguously
7239            from start address. */
7240
7241         info.fw_base = be32_to_cpu(fw_data[1]);
7242         cpu_scratch_size = tp->fw_len;
7243         info.fw_len = tp->fw->size - 12;
7244         info.fw_data = &fw_data[3];
7245
7246         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7247                 cpu_base = RX_CPU_BASE;
7248                 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
7249         } else {
7250                 cpu_base = TX_CPU_BASE;
7251                 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
7252                 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
7253         }
7254
7255         err = tg3_load_firmware_cpu(tp, cpu_base,
7256                                     cpu_scratch_base, cpu_scratch_size,
7257                                     &info);
7258         if (err)
7259                 return err;
7260
7261         /* Now startup the cpu. */
7262         tw32(cpu_base + CPU_STATE, 0xffffffff);
7263         tw32_f(cpu_base + CPU_PC, info.fw_base);
7264
7265         for (i = 0; i < 5; i++) {
7266                 if (tr32(cpu_base + CPU_PC) == info.fw_base)
7267                         break;
7268                 tw32(cpu_base + CPU_STATE, 0xffffffff);
7269                 tw32(cpu_base + CPU_MODE,  CPU_MODE_HALT);
7270                 tw32_f(cpu_base + CPU_PC, info.fw_base);
7271                 udelay(1000);
7272         }
7273         if (i >= 5) {
7274                 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
7275                        "to set CPU PC, is %08x should be %08x\n",
7276                        tp->dev->name, tr32(cpu_base + CPU_PC),
7277                        info.fw_base);
7278                 return -ENODEV;
7279         }
7280         tw32(cpu_base + CPU_STATE, 0xffffffff);
7281         tw32_f(cpu_base + CPU_MODE,  0x00000000);
7282         return 0;
7283 }
7284
7285
7286 static int tg3_set_mac_addr(struct net_device *dev, void *p)
7287 {
7288         struct tg3 *tp = netdev_priv(dev);
7289         struct sockaddr *addr = p;
7290         int err = 0, skip_mac_1 = 0;
7291
7292         if (!is_valid_ether_addr(addr->sa_data))
7293                 return -EINVAL;
7294
7295         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7296
7297         if (!netif_running(dev))
7298                 return 0;
7299
7300         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
7301                 u32 addr0_high, addr0_low, addr1_high, addr1_low;
7302
7303                 addr0_high = tr32(MAC_ADDR_0_HIGH);
7304                 addr0_low = tr32(MAC_ADDR_0_LOW);
7305                 addr1_high = tr32(MAC_ADDR_1_HIGH);
7306                 addr1_low = tr32(MAC_ADDR_1_LOW);
7307
7308                 /* Skip MAC addr 1 if ASF is using it. */
7309                 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
7310                     !(addr1_high == 0 && addr1_low == 0))
7311                         skip_mac_1 = 1;
7312         }
7313         spin_lock_bh(&tp->lock);
7314         __tg3_set_mac_addr(tp, skip_mac_1);
7315         spin_unlock_bh(&tp->lock);
7316
7317         return err;
7318 }
7319
7320 /* tp->lock is held. */
7321 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
7322                            dma_addr_t mapping, u32 maxlen_flags,
7323                            u32 nic_addr)
7324 {
7325         tg3_write_mem(tp,
7326                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
7327                       ((u64) mapping >> 32));
7328         tg3_write_mem(tp,
7329                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
7330                       ((u64) mapping & 0xffffffff));
7331         tg3_write_mem(tp,
7332                       (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
7333                        maxlen_flags);
7334
7335         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7336                 tg3_write_mem(tp,
7337                               (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
7338                               nic_addr);
7339 }
7340
7341 static void __tg3_set_rx_mode(struct net_device *);
7342 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
7343 {
7344         int i;
7345
7346         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) {
7347                 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
7348                 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
7349                 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
7350         } else {
7351                 tw32(HOSTCC_TXCOL_TICKS, 0);
7352                 tw32(HOSTCC_TXMAX_FRAMES, 0);
7353                 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
7354         }
7355
7356         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
7357                 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
7358                 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
7359                 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
7360         } else {
7361                 tw32(HOSTCC_RXCOL_TICKS, 0);
7362                 tw32(HOSTCC_RXMAX_FRAMES, 0);
7363                 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
7364         }
7365
7366         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7367                 u32 val = ec->stats_block_coalesce_usecs;
7368
7369                 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
7370                 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
7371
7372                 if (!netif_carrier_ok(tp->dev))
7373                         val = 0;
7374
7375                 tw32(HOSTCC_STAT_COAL_TICKS, val);
7376         }
7377
7378         for (i = 0; i < tp->irq_cnt - 1; i++) {
7379                 u32 reg;
7380
7381                 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
7382                 tw32(reg, ec->rx_coalesce_usecs);
7383                 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
7384                 tw32(reg, ec->rx_max_coalesced_frames);
7385                 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
7386                 tw32(reg, ec->rx_max_coalesced_frames_irq);
7387
7388                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7389                         reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
7390                         tw32(reg, ec->tx_coalesce_usecs);
7391                         reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
7392                         tw32(reg, ec->tx_max_coalesced_frames);
7393                         reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
7394                         tw32(reg, ec->tx_max_coalesced_frames_irq);
7395                 }
7396         }
7397
7398         for (; i < tp->irq_max - 1; i++) {
7399                 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
7400                 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
7401                 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7402
7403                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7404                         tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
7405                         tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
7406                         tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7407                 }
7408         }
7409 }
7410
7411 /* tp->lock is held. */
7412 static void tg3_rings_reset(struct tg3 *tp)
7413 {
7414         int i;
7415         u32 stblk, txrcb, rxrcb, limit;
7416         struct tg3_napi *tnapi = &tp->napi[0];
7417
7418         /* Disable all transmit rings but the first. */
7419         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7420                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
7421         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7422                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
7423         else
7424                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7425
7426         for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7427              txrcb < limit; txrcb += TG3_BDINFO_SIZE)
7428                 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
7429                               BDINFO_FLAGS_DISABLED);
7430
7431
7432         /* Disable all receive return rings but the first. */
7433         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
7434                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
7435         else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7436                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
7437         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
7438                  GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7439                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
7440         else
7441                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7442
7443         for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7444              rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
7445                 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
7446                               BDINFO_FLAGS_DISABLED);
7447
7448         /* Disable interrupts */
7449         tw32_mailbox_f(tp->napi[0].int_mbox, 1);
7450
7451         /* Zero mailbox registers. */
7452         if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) {
7453                 for (i = 1; i < TG3_IRQ_MAX_VECS; i++) {
7454                         tp->napi[i].tx_prod = 0;
7455                         tp->napi[i].tx_cons = 0;
7456                         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
7457                                 tw32_mailbox(tp->napi[i].prodmbox, 0);
7458                         tw32_rx_mbox(tp->napi[i].consmbox, 0);
7459                         tw32_mailbox_f(tp->napi[i].int_mbox, 1);
7460                 }
7461                 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))
7462                         tw32_mailbox(tp->napi[0].prodmbox, 0);
7463         } else {
7464                 tp->napi[0].tx_prod = 0;
7465                 tp->napi[0].tx_cons = 0;
7466                 tw32_mailbox(tp->napi[0].prodmbox, 0);
7467                 tw32_rx_mbox(tp->napi[0].consmbox, 0);
7468         }
7469
7470         /* Make sure the NIC-based send BD rings are disabled. */
7471         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7472                 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
7473                 for (i = 0; i < 16; i++)
7474                         tw32_tx_mbox(mbox + i * 8, 0);
7475         }
7476
7477         txrcb = NIC_SRAM_SEND_RCB;
7478         rxrcb = NIC_SRAM_RCV_RET_RCB;
7479
7480         /* Clear status block in ram. */
7481         memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7482
7483         /* Set status block DMA address */
7484         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7485              ((u64) tnapi->status_mapping >> 32));
7486         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7487              ((u64) tnapi->status_mapping & 0xffffffff));
7488
7489         if (tnapi->tx_ring) {
7490                 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7491                                (TG3_TX_RING_SIZE <<
7492                                 BDINFO_FLAGS_MAXLEN_SHIFT),
7493                                NIC_SRAM_TX_BUFFER_DESC);
7494                 txrcb += TG3_BDINFO_SIZE;
7495         }
7496
7497         if (tnapi->rx_rcb) {
7498                 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7499                                (TG3_RX_RCB_RING_SIZE(tp) <<
7500                                 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7501                 rxrcb += TG3_BDINFO_SIZE;
7502         }
7503
7504         stblk = HOSTCC_STATBLCK_RING1;
7505
7506         for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
7507                 u64 mapping = (u64)tnapi->status_mapping;
7508                 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
7509                 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
7510
7511                 /* Clear status block in ram. */
7512                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7513
7514                 if (tnapi->tx_ring) {
7515                         tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7516                                        (TG3_TX_RING_SIZE <<
7517                                         BDINFO_FLAGS_MAXLEN_SHIFT),
7518                                        NIC_SRAM_TX_BUFFER_DESC);
7519                         txrcb += TG3_BDINFO_SIZE;
7520                 }
7521
7522                 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7523                                (TG3_RX_RCB_RING_SIZE(tp) <<
7524                                 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7525
7526                 stblk += 8;
7527                 rxrcb += TG3_BDINFO_SIZE;
7528         }
7529 }
7530
7531 /* tp->lock is held. */
7532 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
7533 {
7534         u32 val, rdmac_mode;
7535         int i, err, limit;
7536         struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
7537
7538         tg3_disable_ints(tp);
7539
7540         tg3_stop_fw(tp);
7541
7542         tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
7543
7544         if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
7545                 tg3_abort_hw(tp, 1);
7546         }
7547
7548         if (reset_phy &&
7549             !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB))
7550                 tg3_phy_reset(tp);
7551
7552         err = tg3_chip_reset(tp);
7553         if (err)
7554                 return err;
7555
7556         tg3_write_sig_legacy(tp, RESET_KIND_INIT);
7557
7558         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
7559                 val = tr32(TG3_CPMU_CTRL);
7560                 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
7561                 tw32(TG3_CPMU_CTRL, val);
7562
7563                 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7564                 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7565                 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7566                 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7567
7568                 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
7569                 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
7570                 val |= CPMU_LNK_AWARE_MACCLK_6_25;
7571                 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
7572
7573                 val = tr32(TG3_CPMU_HST_ACC);
7574                 val &= ~CPMU_HST_ACC_MACCLK_MASK;
7575                 val |= CPMU_HST_ACC_MACCLK_6_25;
7576                 tw32(TG3_CPMU_HST_ACC, val);
7577         }
7578
7579         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7580                 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
7581                 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
7582                        PCIE_PWR_MGMT_L1_THRESH_4MS;
7583                 tw32(PCIE_PWR_MGMT_THRESH, val);
7584
7585                 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
7586                 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
7587
7588                 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
7589
7590                 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
7591                 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
7592         }
7593
7594         if (tp->tg3_flags3 & TG3_FLG3_L1PLLPD_EN) {
7595                 u32 grc_mode = tr32(GRC_MODE);
7596
7597                 /* Access the lower 1K of PL PCIE block registers. */
7598                 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
7599                 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
7600
7601                 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1);
7602                 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1,
7603                      val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN);
7604
7605                 tw32(GRC_MODE, grc_mode);
7606         }
7607
7608         /* This works around an issue with Athlon chipsets on
7609          * B3 tigon3 silicon.  This bit has no effect on any
7610          * other revision.  But do not set this on PCI Express
7611          * chips and don't even touch the clocks if the CPMU is present.
7612          */
7613         if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
7614                 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
7615                         tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
7616                 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7617         }
7618
7619         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
7620             (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
7621                 val = tr32(TG3PCI_PCISTATE);
7622                 val |= PCISTATE_RETRY_SAME_DMA;
7623                 tw32(TG3PCI_PCISTATE, val);
7624         }
7625
7626         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7627                 /* Allow reads and writes to the
7628                  * APE register and memory space.
7629                  */
7630                 val = tr32(TG3PCI_PCISTATE);
7631                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
7632                        PCISTATE_ALLOW_APE_SHMEM_WR;
7633                 tw32(TG3PCI_PCISTATE, val);
7634         }
7635
7636         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
7637                 /* Enable some hw fixes.  */
7638                 val = tr32(TG3PCI_MSI_DATA);
7639                 val |= (1 << 26) | (1 << 28) | (1 << 29);
7640                 tw32(TG3PCI_MSI_DATA, val);
7641         }
7642
7643         /* Descriptor ring init may make accesses to the
7644          * NIC SRAM area to setup the TX descriptors, so we
7645          * can only do this after the hardware has been
7646          * successfully reset.
7647          */
7648         err = tg3_init_rings(tp);
7649         if (err)
7650                 return err;
7651
7652         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7653             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
7654                 val = tr32(TG3PCI_DMA_RW_CTRL) &
7655                       ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
7656                 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
7657         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
7658                    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
7659                 /* This value is determined during the probe time DMA
7660                  * engine test, tg3_test_dma.
7661                  */
7662                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
7663         }
7664
7665         tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
7666                           GRC_MODE_4X_NIC_SEND_RINGS |
7667                           GRC_MODE_NO_TX_PHDR_CSUM |
7668                           GRC_MODE_NO_RX_PHDR_CSUM);
7669         tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
7670
7671         /* Pseudo-header checksum is done by hardware logic and not
7672          * the offload processers, so make the chip do the pseudo-
7673          * header checksums on receive.  For transmit it is more
7674          * convenient to do the pseudo-header checksum in software
7675          * as Linux does that on transmit for us in all cases.
7676          */
7677         tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
7678
7679         tw32(GRC_MODE,
7680              tp->grc_mode |
7681              (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
7682
7683         /* Setup the timer prescalar register.  Clock is always 66Mhz. */
7684         val = tr32(GRC_MISC_CFG);
7685         val &= ~0xff;
7686         val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
7687         tw32(GRC_MISC_CFG, val);
7688
7689         /* Initialize MBUF/DESC pool. */
7690         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7691                 /* Do nothing.  */
7692         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
7693                 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
7694                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
7695                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
7696                 else
7697                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
7698                 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
7699                 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
7700         }
7701         else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7702                 int fw_len;
7703
7704                 fw_len = tp->fw_len;
7705                 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
7706                 tw32(BUFMGR_MB_POOL_ADDR,
7707                      NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
7708                 tw32(BUFMGR_MB_POOL_SIZE,
7709                      NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
7710         }
7711
7712         if (tp->dev->mtu <= ETH_DATA_LEN) {
7713                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7714                      tp->bufmgr_config.mbuf_read_dma_low_water);
7715                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7716                      tp->bufmgr_config.mbuf_mac_rx_low_water);
7717                 tw32(BUFMGR_MB_HIGH_WATER,
7718                      tp->bufmgr_config.mbuf_high_water);
7719         } else {
7720                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7721                      tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
7722                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7723                      tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
7724                 tw32(BUFMGR_MB_HIGH_WATER,
7725                      tp->bufmgr_config.mbuf_high_water_jumbo);
7726         }
7727         tw32(BUFMGR_DMA_LOW_WATER,
7728              tp->bufmgr_config.dma_low_water);
7729         tw32(BUFMGR_DMA_HIGH_WATER,
7730              tp->bufmgr_config.dma_high_water);
7731
7732         tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
7733         for (i = 0; i < 2000; i++) {
7734                 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
7735                         break;
7736                 udelay(10);
7737         }
7738         if (i >= 2000) {
7739                 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
7740                        tp->dev->name);
7741                 return -ENODEV;
7742         }
7743
7744         /* Setup replenish threshold. */
7745         val = tp->rx_pending / 8;
7746         if (val == 0)
7747                 val = 1;
7748         else if (val > tp->rx_std_max_post)
7749                 val = tp->rx_std_max_post;
7750         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7751                 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
7752                         tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
7753
7754                 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
7755                         val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
7756         }
7757
7758         tw32(RCVBDI_STD_THRESH, val);
7759
7760         /* Initialize TG3_BDINFO's at:
7761          *  RCVDBDI_STD_BD:     standard eth size rx ring
7762          *  RCVDBDI_JUMBO_BD:   jumbo frame rx ring
7763          *  RCVDBDI_MINI_BD:    small frame rx ring (??? does not work)
7764          *
7765          * like so:
7766          *  TG3_BDINFO_HOST_ADDR:       high/low parts of DMA address of ring
7767          *  TG3_BDINFO_MAXLEN_FLAGS:    (rx max buffer size << 16) |
7768          *                              ring attribute flags
7769          *  TG3_BDINFO_NIC_ADDR:        location of descriptors in nic SRAM
7770          *
7771          * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
7772          * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
7773          *
7774          * The size of each ring is fixed in the firmware, but the location is
7775          * configurable.
7776          */
7777         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7778              ((u64) tpr->rx_std_mapping >> 32));
7779         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7780              ((u64) tpr->rx_std_mapping & 0xffffffff));
7781         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717)
7782                 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
7783                      NIC_SRAM_RX_BUFFER_DESC);
7784
7785         /* Disable the mini ring */
7786         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7787                 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
7788                      BDINFO_FLAGS_DISABLED);
7789
7790         /* Program the jumbo buffer descriptor ring control
7791          * blocks on those devices that have them.
7792          */
7793         if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
7794             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
7795                 /* Setup replenish threshold. */
7796                 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
7797
7798                 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
7799                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7800                              ((u64) tpr->rx_jmb_mapping >> 32));
7801                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7802                              ((u64) tpr->rx_jmb_mapping & 0xffffffff));
7803                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7804                              (RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT) |
7805                              BDINFO_FLAGS_USE_EXT_RECV);
7806                         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717)
7807                                 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
7808                                      NIC_SRAM_RX_JUMBO_BUFFER_DESC);
7809                 } else {
7810                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7811                              BDINFO_FLAGS_DISABLED);
7812                 }
7813
7814                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7815                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7816                         val = (RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT) |
7817                               (RX_STD_MAX_SIZE << 2);
7818                 else
7819                         val = RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT;
7820         } else
7821                 val = RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT;
7822
7823         tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
7824
7825         tpr->rx_std_prod_idx = tp->rx_pending;
7826         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);
7827
7828         tpr->rx_jmb_prod_idx = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
7829                           tp->rx_jumbo_pending : 0;
7830         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
7831
7832         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7833             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
7834                 tw32(STD_REPLENISH_LWM, 32);
7835                 tw32(JMB_REPLENISH_LWM, 16);
7836         }
7837
7838         tg3_rings_reset(tp);
7839
7840         /* Initialize MAC address and backoff seed. */
7841         __tg3_set_mac_addr(tp, 0);
7842
7843         /* MTU + ethernet header + FCS + optional VLAN tag */
7844         tw32(MAC_RX_MTU_SIZE,
7845              tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
7846
7847         /* The slot time is changed by tg3_setup_phy if we
7848          * run at gigabit with half duplex.
7849          */
7850         tw32(MAC_TX_LENGTHS,
7851              (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
7852              (6 << TX_LENGTHS_IPG_SHIFT) |
7853              (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
7854
7855         /* Receive rules. */
7856         tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
7857         tw32(RCVLPC_CONFIG, 0x0181);
7858
7859         /* Calculate RDMAC_MODE setting early, we need it to determine
7860          * the RCVLPC_STATE_ENABLE mask.
7861          */
7862         rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
7863                       RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
7864                       RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
7865                       RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
7866                       RDMAC_MODE_LNGREAD_ENAB);
7867
7868         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
7869             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7870             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7871                 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
7872                               RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
7873                               RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
7874
7875         /* If statement applies to 5705 and 5750 PCI devices only */
7876         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7877              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7878             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
7879                 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
7880                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7881                         rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
7882                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7883                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
7884                         rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7885                 }
7886         }
7887
7888         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
7889                 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7890
7891         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7892                 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
7893
7894         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
7895             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7896             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7897                 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
7898
7899         /* Receive/send statistics. */
7900         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7901                 val = tr32(RCVLPC_STATS_ENABLE);
7902                 val &= ~RCVLPC_STATSENAB_DACK_FIX;
7903                 tw32(RCVLPC_STATS_ENABLE, val);
7904         } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
7905                    (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
7906                 val = tr32(RCVLPC_STATS_ENABLE);
7907                 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
7908                 tw32(RCVLPC_STATS_ENABLE, val);
7909         } else {
7910                 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
7911         }
7912         tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
7913         tw32(SNDDATAI_STATSENAB, 0xffffff);
7914         tw32(SNDDATAI_STATSCTRL,
7915              (SNDDATAI_SCTRL_ENABLE |
7916               SNDDATAI_SCTRL_FASTUPD));
7917
7918         /* Setup host coalescing engine. */
7919         tw32(HOSTCC_MODE, 0);
7920         for (i = 0; i < 2000; i++) {
7921                 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
7922                         break;
7923                 udelay(10);
7924         }
7925
7926         __tg3_set_coalesce(tp, &tp->coal);
7927
7928         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7929                 /* Status/statistics block address.  See tg3_timer,
7930                  * the tg3_periodic_fetch_stats call there, and
7931                  * tg3_get_stats to see how this works for 5705/5750 chips.
7932                  */
7933                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7934                      ((u64) tp->stats_mapping >> 32));
7935                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7936                      ((u64) tp->stats_mapping & 0xffffffff));
7937                 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
7938
7939                 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
7940
7941                 /* Clear statistics and status block memory areas */
7942                 for (i = NIC_SRAM_STATS_BLK;
7943                      i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
7944                      i += sizeof(u32)) {
7945                         tg3_write_mem(tp, i, 0);
7946                         udelay(40);
7947                 }
7948         }
7949
7950         tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
7951
7952         tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
7953         tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
7954         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7955                 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
7956
7957         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
7958                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
7959                 /* reset to prevent losing 1st rx packet intermittently */
7960                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7961                 udelay(10);
7962         }
7963
7964         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7965                 tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
7966         else
7967                 tp->mac_mode = 0;
7968         tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
7969                 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
7970         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7971             !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7972             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
7973                 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
7974         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
7975         udelay(40);
7976
7977         /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
7978          * If TG3_FLG2_IS_NIC is zero, we should read the
7979          * register to preserve the GPIO settings for LOMs. The GPIOs,
7980          * whether used as inputs or outputs, are set by boot code after
7981          * reset.
7982          */
7983         if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
7984                 u32 gpio_mask;
7985
7986                 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
7987                             GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
7988                             GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
7989
7990                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
7991                         gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
7992                                      GRC_LCLCTRL_GPIO_OUTPUT3;
7993
7994                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
7995                         gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
7996
7997                 tp->grc_local_ctrl &= ~gpio_mask;
7998                 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
7999
8000                 /* GPIO1 must be driven high for eeprom write protect */
8001                 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
8002                         tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
8003                                                GRC_LCLCTRL_GPIO_OUTPUT1);
8004         }
8005         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8006         udelay(100);
8007
8008         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX) {
8009                 val = tr32(MSGINT_MODE);
8010                 val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE;
8011                 tw32(MSGINT_MODE, val);
8012         }
8013
8014         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
8015                 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
8016                 udelay(40);
8017         }
8018
8019         val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
8020                WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
8021                WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
8022                WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
8023                WDMAC_MODE_LNGREAD_ENAB);
8024
8025         /* If statement applies to 5705 and 5750 PCI devices only */
8026         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
8027              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
8028             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
8029                 if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
8030                     (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
8031                      tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
8032                         /* nothing */
8033                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
8034                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
8035                            !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
8036                         val |= WDMAC_MODE_RX_ACCEL;
8037                 }
8038         }
8039
8040         /* Enable host coalescing bug fix */
8041         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
8042                 val |= WDMAC_MODE_STATUS_TAG_FIX;
8043
8044         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
8045                 val |= WDMAC_MODE_BURST_ALL_DATA;
8046
8047         tw32_f(WDMAC_MODE, val);
8048         udelay(40);
8049
8050         if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
8051                 u16 pcix_cmd;
8052
8053                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8054                                      &pcix_cmd);
8055                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
8056                         pcix_cmd &= ~PCI_X_CMD_MAX_READ;
8057                         pcix_cmd |= PCI_X_CMD_READ_2K;
8058                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
8059                         pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
8060                         pcix_cmd |= PCI_X_CMD_READ_2K;
8061                 }
8062                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8063                                       pcix_cmd);
8064         }
8065
8066         tw32_f(RDMAC_MODE, rdmac_mode);
8067         udelay(40);
8068
8069         tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
8070         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8071                 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
8072
8073         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
8074                 tw32(SNDDATAC_MODE,
8075                      SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
8076         else
8077                 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
8078
8079         tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
8080         tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
8081         tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
8082         tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
8083         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
8084                 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
8085         val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
8086         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
8087                 val |= SNDBDI_MODE_MULTI_TXQ_EN;
8088         tw32(SNDBDI_MODE, val);
8089         tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
8090
8091         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8092                 err = tg3_load_5701_a0_firmware_fix(tp);
8093                 if (err)
8094                         return err;
8095         }
8096
8097         if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
8098                 err = tg3_load_tso_firmware(tp);
8099                 if (err)
8100                         return err;
8101         }
8102
8103         tp->tx_mode = TX_MODE_ENABLE;
8104         tw32_f(MAC_TX_MODE, tp->tx_mode);
8105         udelay(100);
8106
8107         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) {
8108                 u32 reg = MAC_RSS_INDIR_TBL_0;
8109                 u8 *ent = (u8 *)&val;
8110
8111                 /* Setup the indirection table */
8112                 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
8113                         int idx = i % sizeof(val);
8114
8115                         ent[idx] = i % (tp->irq_cnt - 1);
8116                         if (idx == sizeof(val) - 1) {
8117                                 tw32(reg, val);
8118                                 reg += 4;
8119                         }
8120                 }
8121
8122                 /* Setup the "secret" hash key. */
8123                 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
8124                 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
8125                 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
8126                 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
8127                 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
8128                 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
8129                 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
8130                 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
8131                 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
8132                 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
8133         }
8134
8135         tp->rx_mode = RX_MODE_ENABLE;
8136         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
8137                 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
8138
8139         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)
8140                 tp->rx_mode |= RX_MODE_RSS_ENABLE |
8141                                RX_MODE_RSS_ITBL_HASH_BITS_7 |
8142                                RX_MODE_RSS_IPV6_HASH_EN |
8143                                RX_MODE_RSS_TCP_IPV6_HASH_EN |
8144                                RX_MODE_RSS_IPV4_HASH_EN |
8145                                RX_MODE_RSS_TCP_IPV4_HASH_EN;
8146
8147         tw32_f(MAC_RX_MODE, tp->rx_mode);
8148         udelay(10);
8149
8150         tw32(MAC_LED_CTRL, tp->led_ctrl);
8151
8152         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
8153         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
8154                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8155                 udelay(10);
8156         }
8157         tw32_f(MAC_RX_MODE, tp->rx_mode);
8158         udelay(10);
8159
8160         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
8161                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
8162                         !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
8163                         /* Set drive transmission level to 1.2V  */
8164                         /* only if the signal pre-emphasis bit is not set  */
8165                         val = tr32(MAC_SERDES_CFG);
8166                         val &= 0xfffff000;
8167                         val |= 0x880;
8168                         tw32(MAC_SERDES_CFG, val);
8169                 }
8170                 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
8171                         tw32(MAC_SERDES_CFG, 0x616000);
8172         }
8173
8174         /* Prevent chip from dropping frames when flow control
8175          * is enabled.
8176          */
8177         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
8178                 val = 1;
8179         else
8180                 val = 2;
8181         tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val);
8182
8183         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
8184             (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
8185                 /* Use hardware link auto-negotiation */
8186                 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
8187         }
8188
8189         if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
8190             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
8191                 u32 tmp;
8192
8193                 tmp = tr32(SERDES_RX_CTRL);
8194                 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
8195                 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
8196                 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
8197                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8198         }
8199
8200         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
8201                 if (tp->link_config.phy_is_low_power) {
8202                         tp->link_config.phy_is_low_power = 0;
8203                         tp->link_config.speed = tp->link_config.orig_speed;
8204                         tp->link_config.duplex = tp->link_config.orig_duplex;
8205                         tp->link_config.autoneg = tp->link_config.orig_autoneg;
8206                 }
8207
8208                 err = tg3_setup_phy(tp, 0);
8209                 if (err)
8210                         return err;
8211
8212                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8213                     !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)) {
8214                         u32 tmp;
8215
8216                         /* Clear CRC stats. */
8217                         if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
8218                                 tg3_writephy(tp, MII_TG3_TEST1,
8219                                              tmp | MII_TG3_TEST1_CRC_EN);
8220                                 tg3_readphy(tp, 0x14, &tmp);
8221                         }
8222                 }
8223         }
8224
8225         __tg3_set_rx_mode(tp->dev);
8226
8227         /* Initialize receive rules. */
8228         tw32(MAC_RCV_RULE_0,  0xc2000000 & RCV_RULE_DISABLE_MASK);
8229         tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
8230         tw32(MAC_RCV_RULE_1,  0x86000004 & RCV_RULE_DISABLE_MASK);
8231         tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
8232
8233         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
8234             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
8235                 limit = 8;
8236         else
8237                 limit = 16;
8238         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
8239                 limit -= 4;
8240         switch (limit) {
8241         case 16:
8242                 tw32(MAC_RCV_RULE_15,  0); tw32(MAC_RCV_VALUE_15,  0);
8243         case 15:
8244                 tw32(MAC_RCV_RULE_14,  0); tw32(MAC_RCV_VALUE_14,  0);
8245         case 14:
8246                 tw32(MAC_RCV_RULE_13,  0); tw32(MAC_RCV_VALUE_13,  0);
8247         case 13:
8248                 tw32(MAC_RCV_RULE_12,  0); tw32(MAC_RCV_VALUE_12,  0);
8249         case 12:
8250                 tw32(MAC_RCV_RULE_11,  0); tw32(MAC_RCV_VALUE_11,  0);
8251         case 11:
8252                 tw32(MAC_RCV_RULE_10,  0); tw32(MAC_RCV_VALUE_10,  0);
8253         case 10:
8254                 tw32(MAC_RCV_RULE_9,  0); tw32(MAC_RCV_VALUE_9,  0);
8255         case 9:
8256                 tw32(MAC_RCV_RULE_8,  0); tw32(MAC_RCV_VALUE_8,  0);
8257         case 8:
8258                 tw32(MAC_RCV_RULE_7,  0); tw32(MAC_RCV_VALUE_7,  0);
8259         case 7:
8260                 tw32(MAC_RCV_RULE_6,  0); tw32(MAC_RCV_VALUE_6,  0);
8261         case 6:
8262                 tw32(MAC_RCV_RULE_5,  0); tw32(MAC_RCV_VALUE_5,  0);
8263         case 5:
8264                 tw32(MAC_RCV_RULE_4,  0); tw32(MAC_RCV_VALUE_4,  0);
8265         case 4:
8266                 /* tw32(MAC_RCV_RULE_3,  0); tw32(MAC_RCV_VALUE_3,  0); */
8267         case 3:
8268                 /* tw32(MAC_RCV_RULE_2,  0); tw32(MAC_RCV_VALUE_2,  0); */
8269         case 2:
8270         case 1:
8271
8272         default:
8273                 break;
8274         }
8275
8276         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
8277                 /* Write our heartbeat update interval to APE. */
8278                 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
8279                                 APE_HOST_HEARTBEAT_INT_DISABLE);
8280
8281         tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
8282
8283         return 0;
8284 }
8285
8286 /* Called at device open time to get the chip ready for
8287  * packet processing.  Invoked with tp->lock held.
8288  */
8289 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
8290 {
8291         tg3_switch_clocks(tp);
8292
8293         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
8294
8295         return tg3_reset_hw(tp, reset_phy);
8296 }
8297
8298 #define TG3_STAT_ADD32(PSTAT, REG) \
8299 do {    u32 __val = tr32(REG); \
8300         (PSTAT)->low += __val; \
8301         if ((PSTAT)->low < __val) \
8302                 (PSTAT)->high += 1; \
8303 } while (0)
8304
8305 static void tg3_periodic_fetch_stats(struct tg3 *tp)
8306 {
8307         struct tg3_hw_stats *sp = tp->hw_stats;
8308
8309         if (!netif_carrier_ok(tp->dev))
8310                 return;
8311
8312         TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
8313         TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
8314         TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
8315         TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
8316         TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
8317         TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
8318         TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
8319         TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
8320         TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
8321         TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
8322         TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
8323         TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
8324         TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
8325
8326         TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
8327         TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
8328         TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
8329         TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
8330         TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
8331         TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
8332         TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
8333         TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
8334         TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
8335         TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
8336         TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
8337         TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
8338         TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
8339         TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
8340
8341         TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
8342         TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
8343         TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
8344 }
8345
8346 static void tg3_timer(unsigned long __opaque)
8347 {
8348         struct tg3 *tp = (struct tg3 *) __opaque;
8349
8350         if (tp->irq_sync)
8351                 goto restart_timer;
8352
8353         spin_lock(&tp->lock);
8354
8355         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8356                 /* All of this garbage is because when using non-tagged
8357                  * IRQ status the mailbox/status_block protocol the chip
8358                  * uses with the cpu is race prone.
8359                  */
8360                 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
8361                         tw32(GRC_LOCAL_CTRL,
8362                              tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
8363                 } else {
8364                         tw32(HOSTCC_MODE, tp->coalesce_mode |
8365                              HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
8366                 }
8367
8368                 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
8369                         tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
8370                         spin_unlock(&tp->lock);
8371                         schedule_work(&tp->reset_task);
8372                         return;
8373                 }
8374         }
8375
8376         /* This part only runs once per second. */
8377         if (!--tp->timer_counter) {
8378                 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
8379                         tg3_periodic_fetch_stats(tp);
8380
8381                 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
8382                         u32 mac_stat;
8383                         int phy_event;
8384
8385                         mac_stat = tr32(MAC_STATUS);
8386
8387                         phy_event = 0;
8388                         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
8389                                 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
8390                                         phy_event = 1;
8391                         } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
8392                                 phy_event = 1;
8393
8394                         if (phy_event)
8395                                 tg3_setup_phy(tp, 0);
8396                 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
8397                         u32 mac_stat = tr32(MAC_STATUS);
8398                         int need_setup = 0;
8399
8400                         if (netif_carrier_ok(tp->dev) &&
8401                             (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
8402                                 need_setup = 1;
8403                         }
8404                         if (! netif_carrier_ok(tp->dev) &&
8405                             (mac_stat & (MAC_STATUS_PCS_SYNCED |
8406                                          MAC_STATUS_SIGNAL_DET))) {
8407                                 need_setup = 1;
8408                         }
8409                         if (need_setup) {
8410                                 if (!tp->serdes_counter) {
8411                                         tw32_f(MAC_MODE,
8412                                              (tp->mac_mode &
8413                                               ~MAC_MODE_PORT_MODE_MASK));
8414                                         udelay(40);
8415                                         tw32_f(MAC_MODE, tp->mac_mode);
8416                                         udelay(40);
8417                                 }
8418                                 tg3_setup_phy(tp, 0);
8419                         }
8420                 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
8421                         tg3_serdes_parallel_detect(tp);
8422
8423                 tp->timer_counter = tp->timer_multiplier;
8424         }
8425
8426         /* Heartbeat is only sent once every 2 seconds.
8427          *
8428          * The heartbeat is to tell the ASF firmware that the host
8429          * driver is still alive.  In the event that the OS crashes,
8430          * ASF needs to reset the hardware to free up the FIFO space
8431          * that may be filled with rx packets destined for the host.
8432          * If the FIFO is full, ASF will no longer function properly.
8433          *
8434          * Unintended resets have been reported on real time kernels
8435          * where the timer doesn't run on time.  Netpoll will also have
8436          * same problem.
8437          *
8438          * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
8439          * to check the ring condition when the heartbeat is expiring
8440          * before doing the reset.  This will prevent most unintended
8441          * resets.
8442          */
8443         if (!--tp->asf_counter) {
8444                 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
8445                     !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
8446                         tg3_wait_for_event_ack(tp);
8447
8448                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
8449                                       FWCMD_NICDRV_ALIVE3);
8450                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
8451                         /* 5 seconds timeout */
8452                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
8453
8454                         tg3_generate_fw_event(tp);
8455                 }
8456                 tp->asf_counter = tp->asf_multiplier;
8457         }
8458
8459         spin_unlock(&tp->lock);
8460
8461 restart_timer:
8462         tp->timer.expires = jiffies + tp->timer_offset;
8463         add_timer(&tp->timer);
8464 }
8465
8466 static int tg3_request_irq(struct tg3 *tp, int irq_num)
8467 {
8468         irq_handler_t fn;
8469         unsigned long flags;
8470         char *name;
8471         struct tg3_napi *tnapi = &tp->napi[irq_num];
8472
8473         if (tp->irq_cnt == 1)
8474                 name = tp->dev->name;
8475         else {
8476                 name = &tnapi->irq_lbl[0];
8477                 snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
8478                 name[IFNAMSIZ-1] = 0;
8479         }
8480
8481         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8482                 fn = tg3_msi;
8483                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
8484                         fn = tg3_msi_1shot;
8485                 flags = IRQF_SAMPLE_RANDOM;
8486         } else {
8487                 fn = tg3_interrupt;
8488                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8489                         fn = tg3_interrupt_tagged;
8490                 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
8491         }
8492
8493         return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
8494 }
8495
8496 static int tg3_test_interrupt(struct tg3 *tp)
8497 {
8498         struct tg3_napi *tnapi = &tp->napi[0];
8499         struct net_device *dev = tp->dev;
8500         int err, i, intr_ok = 0;
8501         u32 val;
8502
8503         if (!netif_running(dev))
8504                 return -ENODEV;
8505
8506         tg3_disable_ints(tp);
8507
8508         free_irq(tnapi->irq_vec, tnapi);
8509
8510         /*
8511          * Turn off MSI one shot mode.  Otherwise this test has no
8512          * observable way to know whether the interrupt was delivered.
8513          */
8514         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
8515              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) &&
8516             (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8517                 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
8518                 tw32(MSGINT_MODE, val);
8519         }
8520
8521         err = request_irq(tnapi->irq_vec, tg3_test_isr,
8522                           IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi);
8523         if (err)
8524                 return err;
8525
8526         tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
8527         tg3_enable_ints(tp);
8528
8529         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8530                tnapi->coal_now);
8531
8532         for (i = 0; i < 5; i++) {
8533                 u32 int_mbox, misc_host_ctrl;
8534
8535                 int_mbox = tr32_mailbox(tnapi->int_mbox);
8536                 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
8537
8538                 if ((int_mbox != 0) ||
8539                     (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
8540                         intr_ok = 1;
8541                         break;
8542                 }
8543
8544                 msleep(10);
8545         }
8546
8547         tg3_disable_ints(tp);
8548
8549         free_irq(tnapi->irq_vec, tnapi);
8550
8551         err = tg3_request_irq(tp, 0);
8552
8553         if (err)
8554                 return err;
8555
8556         if (intr_ok) {
8557                 /* Reenable MSI one shot mode. */
8558                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
8559                      GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) &&
8560                     (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8561                         val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
8562                         tw32(MSGINT_MODE, val);
8563                 }
8564                 return 0;
8565         }
8566
8567         return -EIO;
8568 }
8569
8570 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
8571  * successfully restored
8572  */
8573 static int tg3_test_msi(struct tg3 *tp)
8574 {
8575         int err;
8576         u16 pci_cmd;
8577
8578         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
8579                 return 0;
8580
8581         /* Turn off SERR reporting in case MSI terminates with Master
8582          * Abort.
8583          */
8584         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
8585         pci_write_config_word(tp->pdev, PCI_COMMAND,
8586                               pci_cmd & ~PCI_COMMAND_SERR);
8587
8588         err = tg3_test_interrupt(tp);
8589
8590         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
8591
8592         if (!err)
8593                 return 0;
8594
8595         /* other failures */
8596         if (err != -EIO)
8597                 return err;
8598
8599         /* MSI test failed, go back to INTx mode */
8600         printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
8601                "switching to INTx mode. Please report this failure to "
8602                "the PCI maintainer and include system chipset information.\n",
8603                        tp->dev->name);
8604
8605         free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8606
8607         pci_disable_msi(tp->pdev);
8608
8609         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8610
8611         err = tg3_request_irq(tp, 0);
8612         if (err)
8613                 return err;
8614
8615         /* Need to reset the chip because the MSI cycle may have terminated
8616          * with Master Abort.
8617          */
8618         tg3_full_lock(tp, 1);
8619
8620         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8621         err = tg3_init_hw(tp, 1);
8622
8623         tg3_full_unlock(tp);
8624
8625         if (err)
8626                 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8627
8628         return err;
8629 }
8630
8631 static int tg3_request_firmware(struct tg3 *tp)
8632 {
8633         const __be32 *fw_data;
8634
8635         if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
8636                 printk(KERN_ERR "%s: Failed to load firmware \"%s\"\n",
8637                        tp->dev->name, tp->fw_needed);
8638                 return -ENOENT;
8639         }
8640
8641         fw_data = (void *)tp->fw->data;
8642
8643         /* Firmware blob starts with version numbers, followed by
8644          * start address and _full_ length including BSS sections
8645          * (which must be longer than the actual data, of course
8646          */
8647
8648         tp->fw_len = be32_to_cpu(fw_data[2]);   /* includes bss */
8649         if (tp->fw_len < (tp->fw->size - 12)) {
8650                 printk(KERN_ERR "%s: bogus length %d in \"%s\"\n",
8651                        tp->dev->name, tp->fw_len, tp->fw_needed);
8652                 release_firmware(tp->fw);
8653                 tp->fw = NULL;
8654                 return -EINVAL;
8655         }
8656
8657         /* We no longer need firmware; we have it. */
8658         tp->fw_needed = NULL;
8659         return 0;
8660 }
8661
8662 static bool tg3_enable_msix(struct tg3 *tp)
8663 {
8664         int i, rc, cpus = num_online_cpus();
8665         struct msix_entry msix_ent[tp->irq_max];
8666
8667         if (cpus == 1)
8668                 /* Just fallback to the simpler MSI mode. */
8669                 return false;
8670
8671         /*
8672          * We want as many rx rings enabled as there are cpus.
8673          * The first MSIX vector only deals with link interrupts, etc,
8674          * so we add one to the number of vectors we are requesting.
8675          */
8676         tp->irq_cnt = min_t(unsigned, cpus + 1, tp->irq_max);
8677
8678         for (i = 0; i < tp->irq_max; i++) {
8679                 msix_ent[i].entry  = i;
8680                 msix_ent[i].vector = 0;
8681         }
8682
8683         rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
8684         if (rc != 0) {
8685                 if (rc < TG3_RSS_MIN_NUM_MSIX_VECS)
8686                         return false;
8687                 if (pci_enable_msix(tp->pdev, msix_ent, rc))
8688                         return false;
8689                 printk(KERN_NOTICE
8690                        "%s: Requested %d MSI-X vectors, received %d\n",
8691                        tp->dev->name, tp->irq_cnt, rc);
8692                 tp->irq_cnt = rc;
8693         }
8694
8695         tp->tg3_flags3 |= TG3_FLG3_ENABLE_RSS;
8696
8697         for (i = 0; i < tp->irq_max; i++)
8698                 tp->napi[i].irq_vec = msix_ent[i].vector;
8699
8700         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
8701                 tp->tg3_flags3 |= TG3_FLG3_ENABLE_TSS;
8702                 tp->dev->real_num_tx_queues = tp->irq_cnt - 1;
8703         } else
8704                 tp->dev->real_num_tx_queues = 1;
8705
8706         return true;
8707 }
8708
8709 static void tg3_ints_init(struct tg3 *tp)
8710 {
8711         if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI_OR_MSIX) &&
8712             !(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8713                 /* All MSI supporting chips should support tagged
8714                  * status.  Assert that this is the case.
8715                  */
8716                 printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
8717                        "Not using MSI.\n", tp->dev->name);
8718                 goto defcfg;
8719         }
8720
8721         if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) && tg3_enable_msix(tp))
8722                 tp->tg3_flags2 |= TG3_FLG2_USING_MSIX;
8723         else if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) &&
8724                  pci_enable_msi(tp->pdev) == 0)
8725                 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
8726
8727         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8728                 u32 msi_mode = tr32(MSGINT_MODE);
8729                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8730                         msi_mode |= MSGINT_MODE_MULTIVEC_EN;
8731                 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
8732         }
8733 defcfg:
8734         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
8735                 tp->irq_cnt = 1;
8736                 tp->napi[0].irq_vec = tp->pdev->irq;
8737                 tp->dev->real_num_tx_queues = 1;
8738         }
8739 }
8740
8741 static void tg3_ints_fini(struct tg3 *tp)
8742 {
8743         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8744                 pci_disable_msix(tp->pdev);
8745         else if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
8746                 pci_disable_msi(tp->pdev);
8747         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI_OR_MSIX;
8748         tp->tg3_flags3 &= ~TG3_FLG3_ENABLE_RSS;
8749 }
8750
8751 static int tg3_open(struct net_device *dev)
8752 {
8753         struct tg3 *tp = netdev_priv(dev);
8754         int i, err;
8755
8756         if (tp->fw_needed) {
8757                 err = tg3_request_firmware(tp);
8758                 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8759                         if (err)
8760                                 return err;
8761                 } else if (err) {
8762                         printk(KERN_WARNING "%s: TSO capability disabled.\n",
8763                                tp->dev->name);
8764                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
8765                 } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8766                         printk(KERN_NOTICE "%s: TSO capability restored.\n",
8767                                tp->dev->name);
8768                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
8769                 }
8770         }
8771
8772         netif_carrier_off(tp->dev);
8773
8774         err = tg3_set_power_state(tp, PCI_D0);
8775         if (err)
8776                 return err;
8777
8778         tg3_full_lock(tp, 0);
8779
8780         tg3_disable_ints(tp);
8781         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8782
8783         tg3_full_unlock(tp);
8784
8785         /*
8786          * Setup interrupts first so we know how
8787          * many NAPI resources to allocate
8788          */
8789         tg3_ints_init(tp);
8790
8791         /* The placement of this call is tied
8792          * to the setup and use of Host TX descriptors.
8793          */
8794         err = tg3_alloc_consistent(tp);
8795         if (err)
8796                 goto err_out1;
8797
8798         tg3_napi_enable(tp);
8799
8800         for (i = 0; i < tp->irq_cnt; i++) {
8801                 struct tg3_napi *tnapi = &tp->napi[i];
8802                 err = tg3_request_irq(tp, i);
8803                 if (err) {
8804                         for (i--; i >= 0; i--)
8805                                 free_irq(tnapi->irq_vec, tnapi);
8806                         break;
8807                 }
8808         }
8809
8810         if (err)
8811                 goto err_out2;
8812
8813         tg3_full_lock(tp, 0);
8814
8815         err = tg3_init_hw(tp, 1);
8816         if (err) {
8817                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8818                 tg3_free_rings(tp);
8819         } else {
8820                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8821                         tp->timer_offset = HZ;
8822                 else
8823                         tp->timer_offset = HZ / 10;
8824
8825                 BUG_ON(tp->timer_offset > HZ);
8826                 tp->timer_counter = tp->timer_multiplier =
8827                         (HZ / tp->timer_offset);
8828                 tp->asf_counter = tp->asf_multiplier =
8829                         ((HZ / tp->timer_offset) * 2);
8830
8831                 init_timer(&tp->timer);
8832                 tp->timer.expires = jiffies + tp->timer_offset;
8833                 tp->timer.data = (unsigned long) tp;
8834                 tp->timer.function = tg3_timer;
8835         }
8836
8837         tg3_full_unlock(tp);
8838
8839         if (err)
8840                 goto err_out3;
8841
8842         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8843                 err = tg3_test_msi(tp);
8844
8845                 if (err) {
8846                         tg3_full_lock(tp, 0);
8847                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8848                         tg3_free_rings(tp);
8849                         tg3_full_unlock(tp);
8850
8851                         goto err_out2;
8852                 }
8853
8854                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
8855                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765 &&
8856                     (tp->tg3_flags2 & TG3_FLG2_USING_MSI) &&
8857                     (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)) {
8858                         u32 val = tr32(PCIE_TRANSACTION_CFG);
8859
8860                         tw32(PCIE_TRANSACTION_CFG,
8861                              val | PCIE_TRANS_CFG_1SHOT_MSI);
8862                 }
8863         }
8864
8865         tg3_phy_start(tp);
8866
8867         tg3_full_lock(tp, 0);
8868
8869         add_timer(&tp->timer);
8870         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
8871         tg3_enable_ints(tp);
8872
8873         tg3_full_unlock(tp);
8874
8875         netif_tx_start_all_queues(dev);
8876
8877         return 0;
8878
8879 err_out3:
8880         for (i = tp->irq_cnt - 1; i >= 0; i--) {
8881                 struct tg3_napi *tnapi = &tp->napi[i];
8882                 free_irq(tnapi->irq_vec, tnapi);
8883         }
8884
8885 err_out2:
8886         tg3_napi_disable(tp);
8887         tg3_free_consistent(tp);
8888
8889 err_out1:
8890         tg3_ints_fini(tp);
8891         return err;
8892 }
8893
8894 #if 0
8895 /*static*/ void tg3_dump_state(struct tg3 *tp)
8896 {
8897         u32 val32, val32_2, val32_3, val32_4, val32_5;
8898         u16 val16;
8899         int i;
8900         struct tg3_hw_status *sblk = tp->napi[0]->hw_status;
8901
8902         pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
8903         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
8904         printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
8905                val16, val32);
8906
8907         /* MAC block */
8908         printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
8909                tr32(MAC_MODE), tr32(MAC_STATUS));
8910         printk("       MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
8911                tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
8912         printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
8913                tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
8914         printk("       MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
8915                tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
8916
8917         /* Send data initiator control block */
8918         printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
8919                tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
8920         printk("       SNDDATAI_STATSCTRL[%08x]\n",
8921                tr32(SNDDATAI_STATSCTRL));
8922
8923         /* Send data completion control block */
8924         printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
8925
8926         /* Send BD ring selector block */
8927         printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
8928                tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
8929
8930         /* Send BD initiator control block */
8931         printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
8932                tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
8933
8934         /* Send BD completion control block */
8935         printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
8936
8937         /* Receive list placement control block */
8938         printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
8939                tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
8940         printk("       RCVLPC_STATSCTRL[%08x]\n",
8941                tr32(RCVLPC_STATSCTRL));
8942
8943         /* Receive data and receive BD initiator control block */
8944         printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
8945                tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
8946
8947         /* Receive data completion control block */
8948         printk("DEBUG: RCVDCC_MODE[%08x]\n",
8949                tr32(RCVDCC_MODE));
8950
8951         /* Receive BD initiator control block */
8952         printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
8953                tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
8954
8955         /* Receive BD completion control block */
8956         printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
8957                tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
8958
8959         /* Receive list selector control block */
8960         printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
8961                tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
8962
8963         /* Mbuf cluster free block */
8964         printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
8965                tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
8966
8967         /* Host coalescing control block */
8968         printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
8969                tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
8970         printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
8971                tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8972                tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8973         printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
8974                tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8975                tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8976         printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
8977                tr32(HOSTCC_STATS_BLK_NIC_ADDR));
8978         printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
8979                tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
8980
8981         /* Memory arbiter control block */
8982         printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
8983                tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
8984
8985         /* Buffer manager control block */
8986         printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
8987                tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
8988         printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
8989                tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
8990         printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
8991                "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
8992                tr32(BUFMGR_DMA_DESC_POOL_ADDR),
8993                tr32(BUFMGR_DMA_DESC_POOL_SIZE));
8994
8995         /* Read DMA control block */
8996         printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
8997                tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
8998
8999         /* Write DMA control block */
9000         printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
9001                tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
9002
9003         /* DMA completion block */
9004         printk("DEBUG: DMAC_MODE[%08x]\n",
9005                tr32(DMAC_MODE));
9006
9007         /* GRC block */
9008         printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
9009                tr32(GRC_MODE), tr32(GRC_MISC_CFG));
9010         printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
9011                tr32(GRC_LOCAL_CTRL));
9012
9013         /* TG3_BDINFOs */
9014         printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
9015                tr32(RCVDBDI_JUMBO_BD + 0x0),
9016                tr32(RCVDBDI_JUMBO_BD + 0x4),
9017                tr32(RCVDBDI_JUMBO_BD + 0x8),
9018                tr32(RCVDBDI_JUMBO_BD + 0xc));
9019         printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
9020                tr32(RCVDBDI_STD_BD + 0x0),
9021                tr32(RCVDBDI_STD_BD + 0x4),
9022                tr32(RCVDBDI_STD_BD + 0x8),
9023                tr32(RCVDBDI_STD_BD + 0xc));
9024         printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
9025                tr32(RCVDBDI_MINI_BD + 0x0),
9026                tr32(RCVDBDI_MINI_BD + 0x4),
9027                tr32(RCVDBDI_MINI_BD + 0x8),
9028                tr32(RCVDBDI_MINI_BD + 0xc));
9029
9030         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
9031         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
9032         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
9033         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
9034         printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
9035                val32, val32_2, val32_3, val32_4);
9036
9037         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
9038         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
9039         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
9040         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
9041         printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
9042                val32, val32_2, val32_3, val32_4);
9043
9044         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
9045         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
9046         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
9047         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
9048         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
9049         printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
9050                val32, val32_2, val32_3, val32_4, val32_5);
9051
9052         /* SW status block */
9053         printk(KERN_DEBUG
9054          "Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
9055                sblk->status,
9056                sblk->status_tag,
9057                sblk->rx_jumbo_consumer,
9058                sblk->rx_consumer,
9059                sblk->rx_mini_consumer,
9060                sblk->idx[0].rx_producer,
9061                sblk->idx[0].tx_consumer);
9062
9063         /* SW statistics block */
9064         printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
9065                ((u32 *)tp->hw_stats)[0],
9066                ((u32 *)tp->hw_stats)[1],
9067                ((u32 *)tp->hw_stats)[2],
9068                ((u32 *)tp->hw_stats)[3]);
9069
9070         /* Mailboxes */
9071         printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
9072                tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
9073                tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
9074                tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
9075                tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
9076
9077         /* NIC side send descriptors. */
9078         for (i = 0; i < 6; i++) {
9079                 unsigned long txd;
9080
9081                 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
9082                         + (i * sizeof(struct tg3_tx_buffer_desc));
9083                 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
9084                        i,
9085                        readl(txd + 0x0), readl(txd + 0x4),
9086                        readl(txd + 0x8), readl(txd + 0xc));
9087         }
9088
9089         /* NIC side RX descriptors. */
9090         for (i = 0; i < 6; i++) {
9091                 unsigned long rxd;
9092
9093                 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
9094                         + (i * sizeof(struct tg3_rx_buffer_desc));
9095                 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
9096                        i,
9097                        readl(rxd + 0x0), readl(rxd + 0x4),
9098                        readl(rxd + 0x8), readl(rxd + 0xc));
9099                 rxd += (4 * sizeof(u32));
9100                 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
9101                        i,
9102                        readl(rxd + 0x0), readl(rxd + 0x4),
9103                        readl(rxd + 0x8), readl(rxd + 0xc));
9104         }
9105
9106         for (i = 0; i < 6; i++) {
9107                 unsigned long rxd;
9108
9109                 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
9110                         + (i * sizeof(struct tg3_rx_buffer_desc));
9111                 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
9112                        i,
9113                        readl(rxd + 0x0), readl(rxd + 0x4),
9114                        readl(rxd + 0x8), readl(rxd + 0xc));
9115                 rxd += (4 * sizeof(u32));
9116                 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
9117                        i,
9118                        readl(rxd + 0x0), readl(rxd + 0x4),
9119                        readl(rxd + 0x8), readl(rxd + 0xc));
9120         }
9121 }
9122 #endif
9123
9124 static struct net_device_stats *tg3_get_stats(struct net_device *);
9125 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
9126
9127 static int tg3_close(struct net_device *dev)
9128 {
9129         int i;
9130         struct tg3 *tp = netdev_priv(dev);
9131
9132         tg3_napi_disable(tp);
9133         cancel_work_sync(&tp->reset_task);
9134
9135         netif_tx_stop_all_queues(dev);
9136
9137         del_timer_sync(&tp->timer);
9138
9139         tg3_phy_stop(tp);
9140
9141         tg3_full_lock(tp, 1);
9142 #if 0
9143         tg3_dump_state(tp);
9144 #endif
9145
9146         tg3_disable_ints(tp);
9147
9148         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9149         tg3_free_rings(tp);
9150         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
9151
9152         tg3_full_unlock(tp);
9153
9154         for (i = tp->irq_cnt - 1; i >= 0; i--) {
9155                 struct tg3_napi *tnapi = &tp->napi[i];
9156                 free_irq(tnapi->irq_vec, tnapi);
9157         }
9158
9159         tg3_ints_fini(tp);
9160
9161         memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
9162                sizeof(tp->net_stats_prev));
9163         memcpy(&tp->estats_prev, tg3_get_estats(tp),
9164                sizeof(tp->estats_prev));
9165
9166         tg3_free_consistent(tp);
9167
9168         tg3_set_power_state(tp, PCI_D3hot);
9169
9170         netif_carrier_off(tp->dev);
9171
9172         return 0;
9173 }
9174
9175 static inline unsigned long get_stat64(tg3_stat64_t *val)
9176 {
9177         unsigned long ret;
9178
9179 #if (BITS_PER_LONG == 32)
9180         ret = val->low;
9181 #else
9182         ret = ((u64)val->high << 32) | ((u64)val->low);
9183 #endif
9184         return ret;
9185 }
9186
9187 static inline u64 get_estat64(tg3_stat64_t *val)
9188 {
9189        return ((u64)val->high << 32) | ((u64)val->low);
9190 }
9191
9192 static unsigned long calc_crc_errors(struct tg3 *tp)
9193 {
9194         struct tg3_hw_stats *hw_stats = tp->hw_stats;
9195
9196         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
9197             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
9198              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
9199                 u32 val;
9200
9201                 spin_lock_bh(&tp->lock);
9202                 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
9203                         tg3_writephy(tp, MII_TG3_TEST1,
9204                                      val | MII_TG3_TEST1_CRC_EN);
9205                         tg3_readphy(tp, 0x14, &val);
9206                 } else
9207                         val = 0;
9208                 spin_unlock_bh(&tp->lock);
9209
9210                 tp->phy_crc_errors += val;
9211
9212                 return tp->phy_crc_errors;
9213         }
9214
9215         return get_stat64(&hw_stats->rx_fcs_errors);
9216 }
9217
9218 #define ESTAT_ADD(member) \
9219         estats->member =        old_estats->member + \
9220                                 get_estat64(&hw_stats->member)
9221
9222 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
9223 {
9224         struct tg3_ethtool_stats *estats = &tp->estats;
9225         struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
9226         struct tg3_hw_stats *hw_stats = tp->hw_stats;
9227
9228         if (!hw_stats)
9229                 return old_estats;
9230
9231         ESTAT_ADD(rx_octets);
9232         ESTAT_ADD(rx_fragments);
9233         ESTAT_ADD(rx_ucast_packets);
9234         ESTAT_ADD(rx_mcast_packets);
9235         ESTAT_ADD(rx_bcast_packets);
9236         ESTAT_ADD(rx_fcs_errors);
9237         ESTAT_ADD(rx_align_errors);
9238         ESTAT_ADD(rx_xon_pause_rcvd);
9239         ESTAT_ADD(rx_xoff_pause_rcvd);
9240         ESTAT_ADD(rx_mac_ctrl_rcvd);
9241         ESTAT_ADD(rx_xoff_entered);
9242         ESTAT_ADD(rx_frame_too_long_errors);
9243         ESTAT_ADD(rx_jabbers);
9244         ESTAT_ADD(rx_undersize_packets);
9245         ESTAT_ADD(rx_in_length_errors);
9246         ESTAT_ADD(rx_out_length_errors);
9247         ESTAT_ADD(rx_64_or_less_octet_packets);
9248         ESTAT_ADD(rx_65_to_127_octet_packets);
9249         ESTAT_ADD(rx_128_to_255_octet_packets);
9250         ESTAT_ADD(rx_256_to_511_octet_packets);
9251         ESTAT_ADD(rx_512_to_1023_octet_packets);
9252         ESTAT_ADD(rx_1024_to_1522_octet_packets);
9253         ESTAT_ADD(rx_1523_to_2047_octet_packets);
9254         ESTAT_ADD(rx_2048_to_4095_octet_packets);
9255         ESTAT_ADD(rx_4096_to_8191_octet_packets);
9256         ESTAT_ADD(rx_8192_to_9022_octet_packets);
9257
9258         ESTAT_ADD(tx_octets);
9259         ESTAT_ADD(tx_collisions);
9260         ESTAT_ADD(tx_xon_sent);
9261         ESTAT_ADD(tx_xoff_sent);
9262         ESTAT_ADD(tx_flow_control);
9263         ESTAT_ADD(tx_mac_errors);
9264         ESTAT_ADD(tx_single_collisions);
9265         ESTAT_ADD(tx_mult_collisions);
9266         ESTAT_ADD(tx_deferred);
9267         ESTAT_ADD(tx_excessive_collisions);
9268         ESTAT_ADD(tx_late_collisions);
9269         ESTAT_ADD(tx_collide_2times);
9270         ESTAT_ADD(tx_collide_3times);
9271         ESTAT_ADD(tx_collide_4times);
9272         ESTAT_ADD(tx_collide_5times);
9273         ESTAT_ADD(tx_collide_6times);
9274         ESTAT_ADD(tx_collide_7times);
9275         ESTAT_ADD(tx_collide_8times);
9276         ESTAT_ADD(tx_collide_9times);
9277         ESTAT_ADD(tx_collide_10times);
9278         ESTAT_ADD(tx_collide_11times);
9279         ESTAT_ADD(tx_collide_12times);
9280         ESTAT_ADD(tx_collide_13times);
9281         ESTAT_ADD(tx_collide_14times);
9282         ESTAT_ADD(tx_collide_15times);
9283         ESTAT_ADD(tx_ucast_packets);
9284         ESTAT_ADD(tx_mcast_packets);
9285         ESTAT_ADD(tx_bcast_packets);
9286         ESTAT_ADD(tx_carrier_sense_errors);
9287         ESTAT_ADD(tx_discards);
9288         ESTAT_ADD(tx_errors);
9289
9290         ESTAT_ADD(dma_writeq_full);
9291         ESTAT_ADD(dma_write_prioq_full);
9292         ESTAT_ADD(rxbds_empty);
9293         ESTAT_ADD(rx_discards);
9294         ESTAT_ADD(rx_errors);
9295         ESTAT_ADD(rx_threshold_hit);
9296
9297         ESTAT_ADD(dma_readq_full);
9298         ESTAT_ADD(dma_read_prioq_full);
9299         ESTAT_ADD(tx_comp_queue_full);
9300
9301         ESTAT_ADD(ring_set_send_prod_index);
9302         ESTAT_ADD(ring_status_update);
9303         ESTAT_ADD(nic_irqs);
9304         ESTAT_ADD(nic_avoided_irqs);
9305         ESTAT_ADD(nic_tx_threshold_hit);
9306
9307         return estats;
9308 }
9309
9310 static struct net_device_stats *tg3_get_stats(struct net_device *dev)
9311 {
9312         struct tg3 *tp = netdev_priv(dev);
9313         struct net_device_stats *stats = &tp->net_stats;
9314         struct net_device_stats *old_stats = &tp->net_stats_prev;
9315         struct tg3_hw_stats *hw_stats = tp->hw_stats;
9316
9317         if (!hw_stats)
9318                 return old_stats;
9319
9320         stats->rx_packets = old_stats->rx_packets +
9321                 get_stat64(&hw_stats->rx_ucast_packets) +
9322                 get_stat64(&hw_stats->rx_mcast_packets) +
9323                 get_stat64(&hw_stats->rx_bcast_packets);
9324
9325         stats->tx_packets = old_stats->tx_packets +
9326                 get_stat64(&hw_stats->tx_ucast_packets) +
9327                 get_stat64(&hw_stats->tx_mcast_packets) +
9328                 get_stat64(&hw_stats->tx_bcast_packets);
9329
9330         stats->rx_bytes = old_stats->rx_bytes +
9331                 get_stat64(&hw_stats->rx_octets);
9332         stats->tx_bytes = old_stats->tx_bytes +
9333                 get_stat64(&hw_stats->tx_octets);
9334
9335         stats->rx_errors = old_stats->rx_errors +
9336                 get_stat64(&hw_stats->rx_errors);
9337         stats->tx_errors = old_stats->tx_errors +
9338                 get_stat64(&hw_stats->tx_errors) +
9339                 get_stat64(&hw_stats->tx_mac_errors) +
9340                 get_stat64(&hw_stats->tx_carrier_sense_errors) +
9341                 get_stat64(&hw_stats->tx_discards);
9342
9343         stats->multicast = old_stats->multicast +
9344                 get_stat64(&hw_stats->rx_mcast_packets);
9345         stats->collisions = old_stats->collisions +
9346                 get_stat64(&hw_stats->tx_collisions);
9347
9348         stats->rx_length_errors = old_stats->rx_length_errors +
9349                 get_stat64(&hw_stats->rx_frame_too_long_errors) +
9350                 get_stat64(&hw_stats->rx_undersize_packets);
9351
9352         stats->rx_over_errors = old_stats->rx_over_errors +
9353                 get_stat64(&hw_stats->rxbds_empty);
9354         stats->rx_frame_errors = old_stats->rx_frame_errors +
9355                 get_stat64(&hw_stats->rx_align_errors);
9356         stats->tx_aborted_errors = old_stats->tx_aborted_errors +
9357                 get_stat64(&hw_stats->tx_discards);
9358         stats->tx_carrier_errors = old_stats->tx_carrier_errors +
9359                 get_stat64(&hw_stats->tx_carrier_sense_errors);
9360
9361         stats->rx_crc_errors = old_stats->rx_crc_errors +
9362                 calc_crc_errors(tp);
9363
9364         stats->rx_missed_errors = old_stats->rx_missed_errors +
9365                 get_stat64(&hw_stats->rx_discards);
9366
9367         return stats;
9368 }
9369
9370 static inline u32 calc_crc(unsigned char *buf, int len)
9371 {
9372         u32 reg;
9373         u32 tmp;
9374         int j, k;
9375
9376         reg = 0xffffffff;
9377
9378         for (j = 0; j < len; j++) {
9379                 reg ^= buf[j];
9380
9381                 for (k = 0; k < 8; k++) {
9382                         tmp = reg & 0x01;
9383
9384                         reg >>= 1;
9385
9386                         if (tmp) {
9387                                 reg ^= 0xedb88320;
9388                         }
9389                 }
9390         }
9391
9392         return ~reg;
9393 }
9394
9395 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
9396 {
9397         /* accept or reject all multicast frames */
9398         tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
9399         tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
9400         tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
9401         tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
9402 }
9403
9404 static void __tg3_set_rx_mode(struct net_device *dev)
9405 {
9406         struct tg3 *tp = netdev_priv(dev);
9407         u32 rx_mode;
9408
9409         rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
9410                                   RX_MODE_KEEP_VLAN_TAG);
9411
9412         /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9413          * flag clear.
9414          */
9415 #if TG3_VLAN_TAG_USED
9416         if (!tp->vlgrp &&
9417             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9418                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9419 #else
9420         /* By definition, VLAN is disabled always in this
9421          * case.
9422          */
9423         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9424                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9425 #endif
9426
9427         if (dev->flags & IFF_PROMISC) {
9428                 /* Promiscuous mode. */
9429                 rx_mode |= RX_MODE_PROMISC;
9430         } else if (dev->flags & IFF_ALLMULTI) {
9431                 /* Accept all multicast. */
9432                 tg3_set_multi (tp, 1);
9433         } else if (dev->mc_count < 1) {
9434                 /* Reject all multicast. */
9435                 tg3_set_multi (tp, 0);
9436         } else {
9437                 /* Accept one or more multicast(s). */
9438                 struct dev_mc_list *mclist;
9439                 unsigned int i;
9440                 u32 mc_filter[4] = { 0, };
9441                 u32 regidx;
9442                 u32 bit;
9443                 u32 crc;
9444
9445                 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
9446                      i++, mclist = mclist->next) {
9447
9448                         crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
9449                         bit = ~crc & 0x7f;
9450                         regidx = (bit & 0x60) >> 5;
9451                         bit &= 0x1f;
9452                         mc_filter[regidx] |= (1 << bit);
9453                 }
9454
9455                 tw32(MAC_HASH_REG_0, mc_filter[0]);
9456                 tw32(MAC_HASH_REG_1, mc_filter[1]);
9457                 tw32(MAC_HASH_REG_2, mc_filter[2]);
9458                 tw32(MAC_HASH_REG_3, mc_filter[3]);
9459         }
9460
9461         if (rx_mode != tp->rx_mode) {
9462                 tp->rx_mode = rx_mode;
9463                 tw32_f(MAC_RX_MODE, rx_mode);
9464                 udelay(10);
9465         }
9466 }
9467
9468 static void tg3_set_rx_mode(struct net_device *dev)
9469 {
9470         struct tg3 *tp = netdev_priv(dev);
9471
9472         if (!netif_running(dev))
9473                 return;
9474
9475         tg3_full_lock(tp, 0);
9476         __tg3_set_rx_mode(dev);
9477         tg3_full_unlock(tp);
9478 }
9479
9480 #define TG3_REGDUMP_LEN         (32 * 1024)
9481
9482 static int tg3_get_regs_len(struct net_device *dev)
9483 {
9484         return TG3_REGDUMP_LEN;
9485 }
9486
9487 static void tg3_get_regs(struct net_device *dev,
9488                 struct ethtool_regs *regs, void *_p)
9489 {
9490         u32 *p = _p;
9491         struct tg3 *tp = netdev_priv(dev);
9492         u8 *orig_p = _p;
9493         int i;
9494
9495         regs->version = 0;
9496
9497         memset(p, 0, TG3_REGDUMP_LEN);
9498
9499         if (tp->link_config.phy_is_low_power)
9500                 return;
9501
9502         tg3_full_lock(tp, 0);
9503
9504 #define __GET_REG32(reg)        (*(p)++ = tr32(reg))
9505 #define GET_REG32_LOOP(base,len)                \
9506 do {    p = (u32 *)(orig_p + (base));           \
9507         for (i = 0; i < len; i += 4)            \
9508                 __GET_REG32((base) + i);        \
9509 } while (0)
9510 #define GET_REG32_1(reg)                        \
9511 do {    p = (u32 *)(orig_p + (reg));            \
9512         __GET_REG32((reg));                     \
9513 } while (0)
9514
9515         GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
9516         GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
9517         GET_REG32_LOOP(MAC_MODE, 0x4f0);
9518         GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
9519         GET_REG32_1(SNDDATAC_MODE);
9520         GET_REG32_LOOP(SNDBDS_MODE, 0x80);
9521         GET_REG32_LOOP(SNDBDI_MODE, 0x48);
9522         GET_REG32_1(SNDBDC_MODE);
9523         GET_REG32_LOOP(RCVLPC_MODE, 0x20);
9524         GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
9525         GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
9526         GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
9527         GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
9528         GET_REG32_1(RCVDCC_MODE);
9529         GET_REG32_LOOP(RCVBDI_MODE, 0x20);
9530         GET_REG32_LOOP(RCVCC_MODE, 0x14);
9531         GET_REG32_LOOP(RCVLSC_MODE, 0x08);
9532         GET_REG32_1(MBFREE_MODE);
9533         GET_REG32_LOOP(HOSTCC_MODE, 0x100);
9534         GET_REG32_LOOP(MEMARB_MODE, 0x10);
9535         GET_REG32_LOOP(BUFMGR_MODE, 0x58);
9536         GET_REG32_LOOP(RDMAC_MODE, 0x08);
9537         GET_REG32_LOOP(WDMAC_MODE, 0x08);
9538         GET_REG32_1(RX_CPU_MODE);
9539         GET_REG32_1(RX_CPU_STATE);
9540         GET_REG32_1(RX_CPU_PGMCTR);
9541         GET_REG32_1(RX_CPU_HWBKPT);
9542         GET_REG32_1(TX_CPU_MODE);
9543         GET_REG32_1(TX_CPU_STATE);
9544         GET_REG32_1(TX_CPU_PGMCTR);
9545         GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
9546         GET_REG32_LOOP(FTQ_RESET, 0x120);
9547         GET_REG32_LOOP(MSGINT_MODE, 0x0c);
9548         GET_REG32_1(DMAC_MODE);
9549         GET_REG32_LOOP(GRC_MODE, 0x4c);
9550         if (tp->tg3_flags & TG3_FLAG_NVRAM)
9551                 GET_REG32_LOOP(NVRAM_CMD, 0x24);
9552
9553 #undef __GET_REG32
9554 #undef GET_REG32_LOOP
9555 #undef GET_REG32_1
9556
9557         tg3_full_unlock(tp);
9558 }
9559
9560 static int tg3_get_eeprom_len(struct net_device *dev)
9561 {
9562         struct tg3 *tp = netdev_priv(dev);
9563
9564         return tp->nvram_size;
9565 }
9566
9567 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9568 {
9569         struct tg3 *tp = netdev_priv(dev);
9570         int ret;
9571         u8  *pd;
9572         u32 i, offset, len, b_offset, b_count;
9573         __be32 val;
9574
9575         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9576                 return -EINVAL;
9577
9578         if (tp->link_config.phy_is_low_power)
9579                 return -EAGAIN;
9580
9581         offset = eeprom->offset;
9582         len = eeprom->len;
9583         eeprom->len = 0;
9584
9585         eeprom->magic = TG3_EEPROM_MAGIC;
9586
9587         if (offset & 3) {
9588                 /* adjustments to start on required 4 byte boundary */
9589                 b_offset = offset & 3;
9590                 b_count = 4 - b_offset;
9591                 if (b_count > len) {
9592                         /* i.e. offset=1 len=2 */
9593                         b_count = len;
9594                 }
9595                 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
9596                 if (ret)
9597                         return ret;
9598                 memcpy(data, ((char*)&val) + b_offset, b_count);
9599                 len -= b_count;
9600                 offset += b_count;
9601                 eeprom->len += b_count;
9602         }
9603
9604         /* read bytes upto the last 4 byte boundary */
9605         pd = &data[eeprom->len];
9606         for (i = 0; i < (len - (len & 3)); i += 4) {
9607                 ret = tg3_nvram_read_be32(tp, offset + i, &val);
9608                 if (ret) {
9609                         eeprom->len += i;
9610                         return ret;
9611                 }
9612                 memcpy(pd + i, &val, 4);
9613         }
9614         eeprom->len += i;
9615
9616         if (len & 3) {
9617                 /* read last bytes not ending on 4 byte boundary */
9618                 pd = &data[eeprom->len];
9619                 b_count = len & 3;
9620                 b_offset = offset + len - b_count;
9621                 ret = tg3_nvram_read_be32(tp, b_offset, &val);
9622                 if (ret)
9623                         return ret;
9624                 memcpy(pd, &val, b_count);
9625                 eeprom->len += b_count;
9626         }
9627         return 0;
9628 }
9629
9630 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
9631
9632 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9633 {
9634         struct tg3 *tp = netdev_priv(dev);
9635         int ret;
9636         u32 offset, len, b_offset, odd_len;
9637         u8 *buf;
9638         __be32 start, end;
9639
9640         if (tp->link_config.phy_is_low_power)
9641                 return -EAGAIN;
9642
9643         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
9644             eeprom->magic != TG3_EEPROM_MAGIC)
9645                 return -EINVAL;
9646
9647         offset = eeprom->offset;
9648         len = eeprom->len;
9649
9650         if ((b_offset = (offset & 3))) {
9651                 /* adjustments to start on required 4 byte boundary */
9652                 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
9653                 if (ret)
9654                         return ret;
9655                 len += b_offset;
9656                 offset &= ~3;
9657                 if (len < 4)
9658                         len = 4;
9659         }
9660
9661         odd_len = 0;
9662         if (len & 3) {
9663                 /* adjustments to end on required 4 byte boundary */
9664                 odd_len = 1;
9665                 len = (len + 3) & ~3;
9666                 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
9667                 if (ret)
9668                         return ret;
9669         }
9670
9671         buf = data;
9672         if (b_offset || odd_len) {
9673                 buf = kmalloc(len, GFP_KERNEL);
9674                 if (!buf)
9675                         return -ENOMEM;
9676                 if (b_offset)
9677                         memcpy(buf, &start, 4);
9678                 if (odd_len)
9679                         memcpy(buf+len-4, &end, 4);
9680                 memcpy(buf + b_offset, data, eeprom->len);
9681         }
9682
9683         ret = tg3_nvram_write_block(tp, offset, len, buf);
9684
9685         if (buf != data)
9686                 kfree(buf);
9687
9688         return ret;
9689 }
9690
9691 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9692 {
9693         struct tg3 *tp = netdev_priv(dev);
9694
9695         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9696                 struct phy_device *phydev;
9697                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9698                         return -EAGAIN;
9699                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9700                 return phy_ethtool_gset(phydev, cmd);
9701         }
9702
9703         cmd->supported = (SUPPORTED_Autoneg);
9704
9705         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
9706                 cmd->supported |= (SUPPORTED_1000baseT_Half |
9707                                    SUPPORTED_1000baseT_Full);
9708
9709         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
9710                 cmd->supported |= (SUPPORTED_100baseT_Half |
9711                                   SUPPORTED_100baseT_Full |
9712                                   SUPPORTED_10baseT_Half |
9713                                   SUPPORTED_10baseT_Full |
9714                                   SUPPORTED_TP);
9715                 cmd->port = PORT_TP;
9716         } else {
9717                 cmd->supported |= SUPPORTED_FIBRE;
9718                 cmd->port = PORT_FIBRE;
9719         }
9720
9721         cmd->advertising = tp->link_config.advertising;
9722         if (netif_running(dev)) {
9723                 cmd->speed = tp->link_config.active_speed;
9724                 cmd->duplex = tp->link_config.active_duplex;
9725         }
9726         cmd->phy_address = tp->phy_addr;
9727         cmd->transceiver = XCVR_INTERNAL;
9728         cmd->autoneg = tp->link_config.autoneg;
9729         cmd->maxtxpkt = 0;
9730         cmd->maxrxpkt = 0;
9731         return 0;
9732 }
9733
9734 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9735 {
9736         struct tg3 *tp = netdev_priv(dev);
9737
9738         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9739                 struct phy_device *phydev;
9740                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9741                         return -EAGAIN;
9742                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9743                 return phy_ethtool_sset(phydev, cmd);
9744         }
9745
9746         if (cmd->autoneg != AUTONEG_ENABLE &&
9747             cmd->autoneg != AUTONEG_DISABLE)
9748                 return -EINVAL;
9749
9750         if (cmd->autoneg == AUTONEG_DISABLE &&
9751             cmd->duplex != DUPLEX_FULL &&
9752             cmd->duplex != DUPLEX_HALF)
9753                 return -EINVAL;
9754
9755         if (cmd->autoneg == AUTONEG_ENABLE) {
9756                 u32 mask = ADVERTISED_Autoneg |
9757                            ADVERTISED_Pause |
9758                            ADVERTISED_Asym_Pause;
9759
9760                 if (!(tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
9761                         mask |= ADVERTISED_1000baseT_Half |
9762                                 ADVERTISED_1000baseT_Full;
9763
9764                 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
9765                         mask |= ADVERTISED_100baseT_Half |
9766                                 ADVERTISED_100baseT_Full |
9767                                 ADVERTISED_10baseT_Half |
9768                                 ADVERTISED_10baseT_Full |
9769                                 ADVERTISED_TP;
9770                 else
9771                         mask |= ADVERTISED_FIBRE;
9772
9773                 if (cmd->advertising & ~mask)
9774                         return -EINVAL;
9775
9776                 mask &= (ADVERTISED_1000baseT_Half |
9777                          ADVERTISED_1000baseT_Full |
9778                          ADVERTISED_100baseT_Half |
9779                          ADVERTISED_100baseT_Full |
9780                          ADVERTISED_10baseT_Half |
9781                          ADVERTISED_10baseT_Full);
9782
9783                 cmd->advertising &= mask;
9784         } else {
9785                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
9786                         if (cmd->speed != SPEED_1000)
9787                                 return -EINVAL;
9788
9789                         if (cmd->duplex != DUPLEX_FULL)
9790                                 return -EINVAL;
9791                 } else {
9792                         if (cmd->speed != SPEED_100 &&
9793                             cmd->speed != SPEED_10)
9794                                 return -EINVAL;
9795                 }
9796         }
9797
9798         tg3_full_lock(tp, 0);
9799
9800         tp->link_config.autoneg = cmd->autoneg;
9801         if (cmd->autoneg == AUTONEG_ENABLE) {
9802                 tp->link_config.advertising = (cmd->advertising |
9803                                               ADVERTISED_Autoneg);
9804                 tp->link_config.speed = SPEED_INVALID;
9805                 tp->link_config.duplex = DUPLEX_INVALID;
9806         } else {
9807                 tp->link_config.advertising = 0;
9808                 tp->link_config.speed = cmd->speed;
9809                 tp->link_config.duplex = cmd->duplex;
9810         }
9811
9812         tp->link_config.orig_speed = tp->link_config.speed;
9813         tp->link_config.orig_duplex = tp->link_config.duplex;
9814         tp->link_config.orig_autoneg = tp->link_config.autoneg;
9815
9816         if (netif_running(dev))
9817                 tg3_setup_phy(tp, 1);
9818
9819         tg3_full_unlock(tp);
9820
9821         return 0;
9822 }
9823
9824 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
9825 {
9826         struct tg3 *tp = netdev_priv(dev);
9827
9828         strcpy(info->driver, DRV_MODULE_NAME);
9829         strcpy(info->version, DRV_MODULE_VERSION);
9830         strcpy(info->fw_version, tp->fw_ver);
9831         strcpy(info->bus_info, pci_name(tp->pdev));
9832 }
9833
9834 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9835 {
9836         struct tg3 *tp = netdev_priv(dev);
9837
9838         if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
9839             device_can_wakeup(&tp->pdev->dev))
9840                 wol->supported = WAKE_MAGIC;
9841         else
9842                 wol->supported = 0;
9843         wol->wolopts = 0;
9844         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
9845             device_can_wakeup(&tp->pdev->dev))
9846                 wol->wolopts = WAKE_MAGIC;
9847         memset(&wol->sopass, 0, sizeof(wol->sopass));
9848 }
9849
9850 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9851 {
9852         struct tg3 *tp = netdev_priv(dev);
9853         struct device *dp = &tp->pdev->dev;
9854
9855         if (wol->wolopts & ~WAKE_MAGIC)
9856                 return -EINVAL;
9857         if ((wol->wolopts & WAKE_MAGIC) &&
9858             !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
9859                 return -EINVAL;
9860
9861         spin_lock_bh(&tp->lock);
9862         if (wol->wolopts & WAKE_MAGIC) {
9863                 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
9864                 device_set_wakeup_enable(dp, true);
9865         } else {
9866                 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
9867                 device_set_wakeup_enable(dp, false);
9868         }
9869         spin_unlock_bh(&tp->lock);
9870
9871         return 0;
9872 }
9873
9874 static u32 tg3_get_msglevel(struct net_device *dev)
9875 {
9876         struct tg3 *tp = netdev_priv(dev);
9877         return tp->msg_enable;
9878 }
9879
9880 static void tg3_set_msglevel(struct net_device *dev, u32 value)
9881 {
9882         struct tg3 *tp = netdev_priv(dev);
9883         tp->msg_enable = value;
9884 }
9885
9886 static int tg3_set_tso(struct net_device *dev, u32 value)
9887 {
9888         struct tg3 *tp = netdev_priv(dev);
9889
9890         if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
9891                 if (value)
9892                         return -EINVAL;
9893                 return 0;
9894         }
9895         if ((dev->features & NETIF_F_IPV6_CSUM) &&
9896             ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
9897              (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3))) {
9898                 if (value) {
9899                         dev->features |= NETIF_F_TSO6;
9900                         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
9901                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9902                             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
9903                              GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
9904                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
9905                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9906                                 dev->features |= NETIF_F_TSO_ECN;
9907                 } else
9908                         dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
9909         }
9910         return ethtool_op_set_tso(dev, value);
9911 }
9912
9913 static int tg3_nway_reset(struct net_device *dev)
9914 {
9915         struct tg3 *tp = netdev_priv(dev);
9916         int r;
9917
9918         if (!netif_running(dev))
9919                 return -EAGAIN;
9920
9921         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9922                 return -EINVAL;
9923
9924         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9925                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9926                         return -EAGAIN;
9927                 r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
9928         } else {
9929                 u32 bmcr;
9930
9931                 spin_lock_bh(&tp->lock);
9932                 r = -EINVAL;
9933                 tg3_readphy(tp, MII_BMCR, &bmcr);
9934                 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
9935                     ((bmcr & BMCR_ANENABLE) ||
9936                      (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
9937                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
9938                                                    BMCR_ANENABLE);
9939                         r = 0;
9940                 }
9941                 spin_unlock_bh(&tp->lock);
9942         }
9943
9944         return r;
9945 }
9946
9947 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9948 {
9949         struct tg3 *tp = netdev_priv(dev);
9950
9951         ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
9952         ering->rx_mini_max_pending = 0;
9953         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9954                 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
9955         else
9956                 ering->rx_jumbo_max_pending = 0;
9957
9958         ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
9959
9960         ering->rx_pending = tp->rx_pending;
9961         ering->rx_mini_pending = 0;
9962         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9963                 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
9964         else
9965                 ering->rx_jumbo_pending = 0;
9966
9967         ering->tx_pending = tp->napi[0].tx_pending;
9968 }
9969
9970 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9971 {
9972         struct tg3 *tp = netdev_priv(dev);
9973         int i, irq_sync = 0, err = 0;
9974
9975         if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
9976             (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
9977             (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
9978             (ering->tx_pending <= MAX_SKB_FRAGS) ||
9979             ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
9980              (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
9981                 return -EINVAL;
9982
9983         if (netif_running(dev)) {
9984                 tg3_phy_stop(tp);
9985                 tg3_netif_stop(tp);
9986                 irq_sync = 1;
9987         }
9988
9989         tg3_full_lock(tp, irq_sync);
9990
9991         tp->rx_pending = ering->rx_pending;
9992
9993         if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
9994             tp->rx_pending > 63)
9995                 tp->rx_pending = 63;
9996         tp->rx_jumbo_pending = ering->rx_jumbo_pending;
9997
9998         for (i = 0; i < TG3_IRQ_MAX_VECS; i++)
9999                 tp->napi[i].tx_pending = ering->tx_pending;
10000
10001         if (netif_running(dev)) {
10002                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10003                 err = tg3_restart_hw(tp, 1);
10004                 if (!err)
10005                         tg3_netif_start(tp);
10006         }
10007
10008         tg3_full_unlock(tp);
10009
10010         if (irq_sync && !err)
10011                 tg3_phy_start(tp);
10012
10013         return err;
10014 }
10015
10016 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
10017 {
10018         struct tg3 *tp = netdev_priv(dev);
10019
10020         epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
10021
10022         if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
10023                 epause->rx_pause = 1;
10024         else
10025                 epause->rx_pause = 0;
10026
10027         if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
10028                 epause->tx_pause = 1;
10029         else
10030                 epause->tx_pause = 0;
10031 }
10032
10033 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
10034 {
10035         struct tg3 *tp = netdev_priv(dev);
10036         int err = 0;
10037
10038         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
10039                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
10040                         return -EAGAIN;
10041
10042                 if (epause->autoneg) {
10043                         u32 newadv;
10044                         struct phy_device *phydev;
10045
10046                         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
10047
10048                         if (epause->rx_pause) {
10049                                 if (epause->tx_pause)
10050                                         newadv = ADVERTISED_Pause;
10051                                 else
10052                                         newadv = ADVERTISED_Pause |
10053                                                  ADVERTISED_Asym_Pause;
10054                         } else if (epause->tx_pause) {
10055                                 newadv = ADVERTISED_Asym_Pause;
10056                         } else
10057                                 newadv = 0;
10058
10059                         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
10060                                 u32 oldadv = phydev->advertising &
10061                                              (ADVERTISED_Pause |
10062                                               ADVERTISED_Asym_Pause);
10063                                 if (oldadv != newadv) {
10064                                         phydev->advertising &=
10065                                                 ~(ADVERTISED_Pause |
10066                                                   ADVERTISED_Asym_Pause);
10067                                         phydev->advertising |= newadv;
10068                                         err = phy_start_aneg(phydev);
10069                                 }
10070                         } else {
10071                                 tp->link_config.advertising &=
10072                                                 ~(ADVERTISED_Pause |
10073                                                   ADVERTISED_Asym_Pause);
10074                                 tp->link_config.advertising |= newadv;
10075                         }
10076                 } else {
10077                         if (epause->rx_pause)
10078                                 tp->link_config.flowctrl |= FLOW_CTRL_RX;
10079                         else
10080                                 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
10081
10082                         if (epause->tx_pause)
10083                                 tp->link_config.flowctrl |= FLOW_CTRL_TX;
10084                         else
10085                                 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
10086
10087                         if (netif_running(dev))
10088                                 tg3_setup_flow_control(tp, 0, 0);
10089                 }
10090         } else {
10091                 int irq_sync = 0;
10092
10093                 if (netif_running(dev)) {
10094                         tg3_netif_stop(tp);
10095                         irq_sync = 1;
10096                 }
10097
10098                 tg3_full_lock(tp, irq_sync);
10099
10100                 if (epause->autoneg)
10101                         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
10102                 else
10103                         tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
10104                 if (epause->rx_pause)
10105                         tp->link_config.flowctrl |= FLOW_CTRL_RX;
10106                 else
10107                         tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
10108                 if (epause->tx_pause)
10109                         tp->link_config.flowctrl |= FLOW_CTRL_TX;
10110                 else
10111                         tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
10112
10113                 if (netif_running(dev)) {
10114                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10115                         err = tg3_restart_hw(tp, 1);
10116                         if (!err)
10117                                 tg3_netif_start(tp);
10118                 }
10119
10120                 tg3_full_unlock(tp);
10121         }
10122
10123         return err;
10124 }
10125
10126 static u32 tg3_get_rx_csum(struct net_device *dev)
10127 {
10128         struct tg3 *tp = netdev_priv(dev);
10129         return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
10130 }
10131
10132 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
10133 {
10134         struct tg3 *tp = netdev_priv(dev);
10135
10136         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10137                 if (data != 0)
10138                         return -EINVAL;
10139                 return 0;
10140         }
10141
10142         spin_lock_bh(&tp->lock);
10143         if (data)
10144                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
10145         else
10146                 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
10147         spin_unlock_bh(&tp->lock);
10148
10149         return 0;
10150 }
10151
10152 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
10153 {
10154         struct tg3 *tp = netdev_priv(dev);
10155
10156         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10157                 if (data != 0)
10158                         return -EINVAL;
10159                 return 0;
10160         }
10161
10162         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10163                 ethtool_op_set_tx_ipv6_csum(dev, data);
10164         else
10165                 ethtool_op_set_tx_csum(dev, data);
10166
10167         return 0;
10168 }
10169
10170 static int tg3_get_sset_count (struct net_device *dev, int sset)
10171 {
10172         switch (sset) {
10173         case ETH_SS_TEST:
10174                 return TG3_NUM_TEST;
10175         case ETH_SS_STATS:
10176                 return TG3_NUM_STATS;
10177         default:
10178                 return -EOPNOTSUPP;
10179         }
10180 }
10181
10182 static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
10183 {
10184         switch (stringset) {
10185         case ETH_SS_STATS:
10186                 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
10187                 break;
10188         case ETH_SS_TEST:
10189                 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
10190                 break;
10191         default:
10192                 WARN_ON(1);     /* we need a WARN() */
10193                 break;
10194         }
10195 }
10196
10197 static int tg3_phys_id(struct net_device *dev, u32 data)
10198 {
10199         struct tg3 *tp = netdev_priv(dev);
10200         int i;
10201
10202         if (!netif_running(tp->dev))
10203                 return -EAGAIN;
10204
10205         if (data == 0)
10206                 data = UINT_MAX / 2;
10207
10208         for (i = 0; i < (data * 2); i++) {
10209                 if ((i % 2) == 0)
10210                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10211                                            LED_CTRL_1000MBPS_ON |
10212                                            LED_CTRL_100MBPS_ON |
10213                                            LED_CTRL_10MBPS_ON |
10214                                            LED_CTRL_TRAFFIC_OVERRIDE |
10215                                            LED_CTRL_TRAFFIC_BLINK |
10216                                            LED_CTRL_TRAFFIC_LED);
10217
10218                 else
10219                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10220                                            LED_CTRL_TRAFFIC_OVERRIDE);
10221
10222                 if (msleep_interruptible(500))
10223                         break;
10224         }
10225         tw32(MAC_LED_CTRL, tp->led_ctrl);
10226         return 0;
10227 }
10228
10229 static void tg3_get_ethtool_stats (struct net_device *dev,
10230                                    struct ethtool_stats *estats, u64 *tmp_stats)
10231 {
10232         struct tg3 *tp = netdev_priv(dev);
10233         memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
10234 }
10235
10236 #define NVRAM_TEST_SIZE 0x100
10237 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE   0x14
10238 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE   0x18
10239 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE   0x1c
10240 #define NVRAM_SELFBOOT_HW_SIZE 0x20
10241 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
10242
10243 static int tg3_test_nvram(struct tg3 *tp)
10244 {
10245         u32 csum, magic;
10246         __be32 *buf;
10247         int i, j, k, err = 0, size;
10248
10249         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
10250                 return 0;
10251
10252         if (tg3_nvram_read(tp, 0, &magic) != 0)
10253                 return -EIO;
10254
10255         if (magic == TG3_EEPROM_MAGIC)
10256                 size = NVRAM_TEST_SIZE;
10257         else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
10258                 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
10259                     TG3_EEPROM_SB_FORMAT_1) {
10260                         switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
10261                         case TG3_EEPROM_SB_REVISION_0:
10262                                 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
10263                                 break;
10264                         case TG3_EEPROM_SB_REVISION_2:
10265                                 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
10266                                 break;
10267                         case TG3_EEPROM_SB_REVISION_3:
10268                                 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
10269                                 break;
10270                         default:
10271                                 return 0;
10272                         }
10273                 } else
10274                         return 0;
10275         } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
10276                 size = NVRAM_SELFBOOT_HW_SIZE;
10277         else
10278                 return -EIO;
10279
10280         buf = kmalloc(size, GFP_KERNEL);
10281         if (buf == NULL)
10282                 return -ENOMEM;
10283
10284         err = -EIO;
10285         for (i = 0, j = 0; i < size; i += 4, j++) {
10286                 err = tg3_nvram_read_be32(tp, i, &buf[j]);
10287                 if (err)
10288                         break;
10289         }
10290         if (i < size)
10291                 goto out;
10292
10293         /* Selfboot format */
10294         magic = be32_to_cpu(buf[0]);
10295         if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
10296             TG3_EEPROM_MAGIC_FW) {
10297                 u8 *buf8 = (u8 *) buf, csum8 = 0;
10298
10299                 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
10300                     TG3_EEPROM_SB_REVISION_2) {
10301                         /* For rev 2, the csum doesn't include the MBA. */
10302                         for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
10303                                 csum8 += buf8[i];
10304                         for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
10305                                 csum8 += buf8[i];
10306                 } else {
10307                         for (i = 0; i < size; i++)
10308                                 csum8 += buf8[i];
10309                 }
10310
10311                 if (csum8 == 0) {
10312                         err = 0;
10313                         goto out;
10314                 }
10315
10316                 err = -EIO;
10317                 goto out;
10318         }
10319
10320         if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
10321             TG3_EEPROM_MAGIC_HW) {
10322                 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
10323                 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
10324                 u8 *buf8 = (u8 *) buf;
10325
10326                 /* Separate the parity bits and the data bytes.  */
10327                 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
10328                         if ((i == 0) || (i == 8)) {
10329                                 int l;
10330                                 u8 msk;
10331
10332                                 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
10333                                         parity[k++] = buf8[i] & msk;
10334                                 i++;
10335                         }
10336                         else if (i == 16) {
10337                                 int l;
10338                                 u8 msk;
10339
10340                                 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
10341                                         parity[k++] = buf8[i] & msk;
10342                                 i++;
10343
10344                                 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
10345                                         parity[k++] = buf8[i] & msk;
10346                                 i++;
10347                         }
10348                         data[j++] = buf8[i];
10349                 }
10350
10351                 err = -EIO;
10352                 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
10353                         u8 hw8 = hweight8(data[i]);
10354
10355                         if ((hw8 & 0x1) && parity[i])
10356                                 goto out;
10357                         else if (!(hw8 & 0x1) && !parity[i])
10358                                 goto out;
10359                 }
10360                 err = 0;
10361                 goto out;
10362         }
10363
10364         /* Bootstrap checksum at offset 0x10 */
10365         csum = calc_crc((unsigned char *) buf, 0x10);
10366         if (csum != be32_to_cpu(buf[0x10/4]))
10367                 goto out;
10368
10369         /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
10370         csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
10371         if (csum != be32_to_cpu(buf[0xfc/4]))
10372                 goto out;
10373
10374         err = 0;
10375
10376 out:
10377         kfree(buf);
10378         return err;
10379 }
10380
10381 #define TG3_SERDES_TIMEOUT_SEC  2
10382 #define TG3_COPPER_TIMEOUT_SEC  6
10383
10384 static int tg3_test_link(struct tg3 *tp)
10385 {
10386         int i, max;
10387
10388         if (!netif_running(tp->dev))
10389                 return -ENODEV;
10390
10391         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
10392                 max = TG3_SERDES_TIMEOUT_SEC;
10393         else
10394                 max = TG3_COPPER_TIMEOUT_SEC;
10395
10396         for (i = 0; i < max; i++) {
10397                 if (netif_carrier_ok(tp->dev))
10398                         return 0;
10399
10400                 if (msleep_interruptible(1000))
10401                         break;
10402         }
10403
10404         return -EIO;
10405 }
10406
10407 /* Only test the commonly used registers */
10408 static int tg3_test_registers(struct tg3 *tp)
10409 {
10410         int i, is_5705, is_5750;
10411         u32 offset, read_mask, write_mask, val, save_val, read_val;
10412         static struct {
10413                 u16 offset;
10414                 u16 flags;
10415 #define TG3_FL_5705     0x1
10416 #define TG3_FL_NOT_5705 0x2
10417 #define TG3_FL_NOT_5788 0x4
10418 #define TG3_FL_NOT_5750 0x8
10419                 u32 read_mask;
10420                 u32 write_mask;
10421         } reg_tbl[] = {
10422                 /* MAC Control Registers */
10423                 { MAC_MODE, TG3_FL_NOT_5705,
10424                         0x00000000, 0x00ef6f8c },
10425                 { MAC_MODE, TG3_FL_5705,
10426                         0x00000000, 0x01ef6b8c },
10427                 { MAC_STATUS, TG3_FL_NOT_5705,
10428                         0x03800107, 0x00000000 },
10429                 { MAC_STATUS, TG3_FL_5705,
10430                         0x03800100, 0x00000000 },
10431                 { MAC_ADDR_0_HIGH, 0x0000,
10432                         0x00000000, 0x0000ffff },
10433                 { MAC_ADDR_0_LOW, 0x0000,
10434                         0x00000000, 0xffffffff },
10435                 { MAC_RX_MTU_SIZE, 0x0000,
10436                         0x00000000, 0x0000ffff },
10437                 { MAC_TX_MODE, 0x0000,
10438                         0x00000000, 0x00000070 },
10439                 { MAC_TX_LENGTHS, 0x0000,
10440                         0x00000000, 0x00003fff },
10441                 { MAC_RX_MODE, TG3_FL_NOT_5705,
10442                         0x00000000, 0x000007fc },
10443                 { MAC_RX_MODE, TG3_FL_5705,
10444                         0x00000000, 0x000007dc },
10445                 { MAC_HASH_REG_0, 0x0000,
10446                         0x00000000, 0xffffffff },
10447                 { MAC_HASH_REG_1, 0x0000,
10448                         0x00000000, 0xffffffff },
10449                 { MAC_HASH_REG_2, 0x0000,
10450                         0x00000000, 0xffffffff },
10451                 { MAC_HASH_REG_3, 0x0000,
10452                         0x00000000, 0xffffffff },
10453
10454                 /* Receive Data and Receive BD Initiator Control Registers. */
10455                 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
10456                         0x00000000, 0xffffffff },
10457                 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
10458                         0x00000000, 0xffffffff },
10459                 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
10460                         0x00000000, 0x00000003 },
10461                 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
10462                         0x00000000, 0xffffffff },
10463                 { RCVDBDI_STD_BD+0, 0x0000,
10464                         0x00000000, 0xffffffff },
10465                 { RCVDBDI_STD_BD+4, 0x0000,
10466                         0x00000000, 0xffffffff },
10467                 { RCVDBDI_STD_BD+8, 0x0000,
10468                         0x00000000, 0xffff0002 },
10469                 { RCVDBDI_STD_BD+0xc, 0x0000,
10470                         0x00000000, 0xffffffff },
10471
10472                 /* Receive BD Initiator Control Registers. */
10473                 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
10474                         0x00000000, 0xffffffff },
10475                 { RCVBDI_STD_THRESH, TG3_FL_5705,
10476                         0x00000000, 0x000003ff },
10477                 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
10478                         0x00000000, 0xffffffff },
10479
10480                 /* Host Coalescing Control Registers. */
10481                 { HOSTCC_MODE, TG3_FL_NOT_5705,
10482                         0x00000000, 0x00000004 },
10483                 { HOSTCC_MODE, TG3_FL_5705,
10484                         0x00000000, 0x000000f6 },
10485                 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
10486                         0x00000000, 0xffffffff },
10487                 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
10488                         0x00000000, 0x000003ff },
10489                 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
10490                         0x00000000, 0xffffffff },
10491                 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
10492                         0x00000000, 0x000003ff },
10493                 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
10494                         0x00000000, 0xffffffff },
10495                 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10496                         0x00000000, 0x000000ff },
10497                 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
10498                         0x00000000, 0xffffffff },
10499                 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10500                         0x00000000, 0x000000ff },
10501                 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
10502                         0x00000000, 0xffffffff },
10503                 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
10504                         0x00000000, 0xffffffff },
10505                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10506                         0x00000000, 0xffffffff },
10507                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10508                         0x00000000, 0x000000ff },
10509                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10510                         0x00000000, 0xffffffff },
10511                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10512                         0x00000000, 0x000000ff },
10513                 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
10514                         0x00000000, 0xffffffff },
10515                 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
10516                         0x00000000, 0xffffffff },
10517                 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
10518                         0x00000000, 0xffffffff },
10519                 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
10520                         0x00000000, 0xffffffff },
10521                 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
10522                         0x00000000, 0xffffffff },
10523                 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
10524                         0xffffffff, 0x00000000 },
10525                 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
10526                         0xffffffff, 0x00000000 },
10527
10528                 /* Buffer Manager Control Registers. */
10529                 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
10530                         0x00000000, 0x007fff80 },
10531                 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
10532                         0x00000000, 0x007fffff },
10533                 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
10534                         0x00000000, 0x0000003f },
10535                 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
10536                         0x00000000, 0x000001ff },
10537                 { BUFMGR_MB_HIGH_WATER, 0x0000,
10538                         0x00000000, 0x000001ff },
10539                 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
10540                         0xffffffff, 0x00000000 },
10541                 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
10542                         0xffffffff, 0x00000000 },
10543
10544                 /* Mailbox Registers */
10545                 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
10546                         0x00000000, 0x000001ff },
10547                 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
10548                         0x00000000, 0x000001ff },
10549                 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
10550                         0x00000000, 0x000007ff },
10551                 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
10552                         0x00000000, 0x000001ff },
10553
10554                 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
10555         };
10556
10557         is_5705 = is_5750 = 0;
10558         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10559                 is_5705 = 1;
10560                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10561                         is_5750 = 1;
10562         }
10563
10564         for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
10565                 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
10566                         continue;
10567
10568                 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
10569                         continue;
10570
10571                 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10572                     (reg_tbl[i].flags & TG3_FL_NOT_5788))
10573                         continue;
10574
10575                 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
10576                         continue;
10577
10578                 offset = (u32) reg_tbl[i].offset;
10579                 read_mask = reg_tbl[i].read_mask;
10580                 write_mask = reg_tbl[i].write_mask;
10581
10582                 /* Save the original register content */
10583                 save_val = tr32(offset);
10584
10585                 /* Determine the read-only value. */
10586                 read_val = save_val & read_mask;
10587
10588                 /* Write zero to the register, then make sure the read-only bits
10589                  * are not changed and the read/write bits are all zeros.
10590                  */
10591                 tw32(offset, 0);
10592
10593                 val = tr32(offset);
10594
10595                 /* Test the read-only and read/write bits. */
10596                 if (((val & read_mask) != read_val) || (val & write_mask))
10597                         goto out;
10598
10599                 /* Write ones to all the bits defined by RdMask and WrMask, then
10600                  * make sure the read-only bits are not changed and the
10601                  * read/write bits are all ones.
10602                  */
10603                 tw32(offset, read_mask | write_mask);
10604
10605                 val = tr32(offset);
10606
10607                 /* Test the read-only bits. */
10608                 if ((val & read_mask) != read_val)
10609                         goto out;
10610
10611                 /* Test the read/write bits. */
10612                 if ((val & write_mask) != write_mask)
10613                         goto out;
10614
10615                 tw32(offset, save_val);
10616         }
10617
10618         return 0;
10619
10620 out:
10621         if (netif_msg_hw(tp))
10622                 printk(KERN_ERR PFX "Register test failed at offset %x\n",
10623                        offset);
10624         tw32(offset, save_val);
10625         return -EIO;
10626 }
10627
10628 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
10629 {
10630         static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
10631         int i;
10632         u32 j;
10633
10634         for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
10635                 for (j = 0; j < len; j += 4) {
10636                         u32 val;
10637
10638                         tg3_write_mem(tp, offset + j, test_pattern[i]);
10639                         tg3_read_mem(tp, offset + j, &val);
10640                         if (val != test_pattern[i])
10641                                 return -EIO;
10642                 }
10643         }
10644         return 0;
10645 }
10646
10647 static int tg3_test_memory(struct tg3 *tp)
10648 {
10649         static struct mem_entry {
10650                 u32 offset;
10651                 u32 len;
10652         } mem_tbl_570x[] = {
10653                 { 0x00000000, 0x00b50},
10654                 { 0x00002000, 0x1c000},
10655                 { 0xffffffff, 0x00000}
10656         }, mem_tbl_5705[] = {
10657                 { 0x00000100, 0x0000c},
10658                 { 0x00000200, 0x00008},
10659                 { 0x00004000, 0x00800},
10660                 { 0x00006000, 0x01000},
10661                 { 0x00008000, 0x02000},
10662                 { 0x00010000, 0x0e000},
10663                 { 0xffffffff, 0x00000}
10664         }, mem_tbl_5755[] = {
10665                 { 0x00000200, 0x00008},
10666                 { 0x00004000, 0x00800},
10667                 { 0x00006000, 0x00800},
10668                 { 0x00008000, 0x02000},
10669                 { 0x00010000, 0x0c000},
10670                 { 0xffffffff, 0x00000}
10671         }, mem_tbl_5906[] = {
10672                 { 0x00000200, 0x00008},
10673                 { 0x00004000, 0x00400},
10674                 { 0x00006000, 0x00400},
10675                 { 0x00008000, 0x01000},
10676                 { 0x00010000, 0x01000},
10677                 { 0xffffffff, 0x00000}
10678         }, mem_tbl_5717[] = {
10679                 { 0x00000200, 0x00008},
10680                 { 0x00010000, 0x0a000},
10681                 { 0x00020000, 0x13c00},
10682                 { 0xffffffff, 0x00000}
10683         }, mem_tbl_57765[] = {
10684                 { 0x00000200, 0x00008},
10685                 { 0x00004000, 0x00800},
10686                 { 0x00006000, 0x09800},
10687                 { 0x00010000, 0x0a000},
10688                 { 0xffffffff, 0x00000}
10689         };
10690         struct mem_entry *mem_tbl;
10691         int err = 0;
10692         int i;
10693
10694         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
10695                 mem_tbl = mem_tbl_5717;
10696         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
10697                 mem_tbl = mem_tbl_57765;
10698         else if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10699                 mem_tbl = mem_tbl_5755;
10700         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10701                 mem_tbl = mem_tbl_5906;
10702         else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
10703                 mem_tbl = mem_tbl_5705;
10704         else
10705                 mem_tbl = mem_tbl_570x;
10706
10707         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
10708                 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
10709                     mem_tbl[i].len)) != 0)
10710                         break;
10711         }
10712
10713         return err;
10714 }
10715
10716 #define TG3_MAC_LOOPBACK        0
10717 #define TG3_PHY_LOOPBACK        1
10718
10719 static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
10720 {
10721         u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
10722         u32 desc_idx, coal_now;
10723         struct sk_buff *skb, *rx_skb;
10724         u8 *tx_data;
10725         dma_addr_t map;
10726         int num_pkts, tx_len, rx_len, i, err;
10727         struct tg3_rx_buffer_desc *desc;
10728         struct tg3_napi *tnapi, *rnapi;
10729         struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
10730
10731         if (tp->irq_cnt > 1) {
10732                 tnapi = &tp->napi[1];
10733                 rnapi = &tp->napi[1];
10734         } else {
10735                 tnapi = &tp->napi[0];
10736                 rnapi = &tp->napi[0];
10737         }
10738         coal_now = tnapi->coal_now | rnapi->coal_now;
10739
10740         if (loopback_mode == TG3_MAC_LOOPBACK) {
10741                 /* HW errata - mac loopback fails in some cases on 5780.
10742                  * Normal traffic and PHY loopback are not affected by
10743                  * errata.
10744                  */
10745                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
10746                         return 0;
10747
10748                 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
10749                            MAC_MODE_PORT_INT_LPBACK;
10750                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10751                         mac_mode |= MAC_MODE_LINK_POLARITY;
10752                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
10753                         mac_mode |= MAC_MODE_PORT_MODE_MII;
10754                 else
10755                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
10756                 tw32(MAC_MODE, mac_mode);
10757         } else if (loopback_mode == TG3_PHY_LOOPBACK) {
10758                 u32 val;
10759
10760                 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10761                         tg3_phy_fet_toggle_apd(tp, false);
10762                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
10763                 } else
10764                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
10765
10766                 tg3_phy_toggle_automdix(tp, 0);
10767
10768                 tg3_writephy(tp, MII_BMCR, val);
10769                 udelay(40);
10770
10771                 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
10772                 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10773                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10774                                 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x1800);
10775                         mac_mode |= MAC_MODE_PORT_MODE_MII;
10776                 } else
10777                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
10778
10779                 /* reset to prevent losing 1st rx packet intermittently */
10780                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
10781                         tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10782                         udelay(10);
10783                         tw32_f(MAC_RX_MODE, tp->rx_mode);
10784                 }
10785                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
10786                         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)
10787                                 mac_mode &= ~MAC_MODE_LINK_POLARITY;
10788                         else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411)
10789                                 mac_mode |= MAC_MODE_LINK_POLARITY;
10790                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
10791                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
10792                 }
10793                 tw32(MAC_MODE, mac_mode);
10794         }
10795         else
10796                 return -EINVAL;
10797
10798         err = -EIO;
10799
10800         tx_len = 1514;
10801         skb = netdev_alloc_skb(tp->dev, tx_len);
10802         if (!skb)
10803                 return -ENOMEM;
10804
10805         tx_data = skb_put(skb, tx_len);
10806         memcpy(tx_data, tp->dev->dev_addr, 6);
10807         memset(tx_data + 6, 0x0, 8);
10808
10809         tw32(MAC_RX_MTU_SIZE, tx_len + 4);
10810
10811         for (i = 14; i < tx_len; i++)
10812                 tx_data[i] = (u8) (i & 0xff);
10813
10814         map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
10815         if (pci_dma_mapping_error(tp->pdev, map)) {
10816                 dev_kfree_skb(skb);
10817                 return -EIO;
10818         }
10819
10820         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10821                rnapi->coal_now);
10822
10823         udelay(10);
10824
10825         rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
10826
10827         num_pkts = 0;
10828
10829         tg3_set_txd(tnapi, tnapi->tx_prod, map, tx_len, 0, 1);
10830
10831         tnapi->tx_prod++;
10832         num_pkts++;
10833
10834         tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
10835         tr32_mailbox(tnapi->prodmbox);
10836
10837         udelay(10);
10838
10839         /* 350 usec to allow enough time on some 10/100 Mbps devices.  */
10840         for (i = 0; i < 35; i++) {
10841                 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10842                        coal_now);
10843
10844                 udelay(10);
10845
10846                 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
10847                 rx_idx = rnapi->hw_status->idx[0].rx_producer;
10848                 if ((tx_idx == tnapi->tx_prod) &&
10849                     (rx_idx == (rx_start_idx + num_pkts)))
10850                         break;
10851         }
10852
10853         pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
10854         dev_kfree_skb(skb);
10855
10856         if (tx_idx != tnapi->tx_prod)
10857                 goto out;
10858
10859         if (rx_idx != rx_start_idx + num_pkts)
10860                 goto out;
10861
10862         desc = &rnapi->rx_rcb[rx_start_idx];
10863         desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
10864         opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
10865         if (opaque_key != RXD_OPAQUE_RING_STD)
10866                 goto out;
10867
10868         if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
10869             (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
10870                 goto out;
10871
10872         rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
10873         if (rx_len != tx_len)
10874                 goto out;
10875
10876         rx_skb = tpr->rx_std_buffers[desc_idx].skb;
10877
10878         map = pci_unmap_addr(&tpr->rx_std_buffers[desc_idx], mapping);
10879         pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
10880
10881         for (i = 14; i < tx_len; i++) {
10882                 if (*(rx_skb->data + i) != (u8) (i & 0xff))
10883                         goto out;
10884         }
10885         err = 0;
10886
10887         /* tg3_free_rings will unmap and free the rx_skb */
10888 out:
10889         return err;
10890 }
10891
10892 #define TG3_MAC_LOOPBACK_FAILED         1
10893 #define TG3_PHY_LOOPBACK_FAILED         2
10894 #define TG3_LOOPBACK_FAILED             (TG3_MAC_LOOPBACK_FAILED |      \
10895                                          TG3_PHY_LOOPBACK_FAILED)
10896
10897 static int tg3_test_loopback(struct tg3 *tp)
10898 {
10899         int err = 0;
10900         u32 cpmuctrl = 0;
10901
10902         if (!netif_running(tp->dev))
10903                 return TG3_LOOPBACK_FAILED;
10904
10905         err = tg3_reset_hw(tp, 1);
10906         if (err)
10907                 return TG3_LOOPBACK_FAILED;
10908
10909         /* Turn off gphy autopowerdown. */
10910         if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10911                 tg3_phy_toggle_apd(tp, false);
10912
10913         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
10914                 int i;
10915                 u32 status;
10916
10917                 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
10918
10919                 /* Wait for up to 40 microseconds to acquire lock. */
10920                 for (i = 0; i < 4; i++) {
10921                         status = tr32(TG3_CPMU_MUTEX_GNT);
10922                         if (status == CPMU_MUTEX_GNT_DRIVER)
10923                                 break;
10924                         udelay(10);
10925                 }
10926
10927                 if (status != CPMU_MUTEX_GNT_DRIVER)
10928                         return TG3_LOOPBACK_FAILED;
10929
10930                 /* Turn off link-based power management. */
10931                 cpmuctrl = tr32(TG3_CPMU_CTRL);
10932                 tw32(TG3_CPMU_CTRL,
10933                      cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
10934                                   CPMU_CTRL_LINK_AWARE_MODE));
10935         }
10936
10937         if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
10938                 err |= TG3_MAC_LOOPBACK_FAILED;
10939
10940         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
10941                 tw32(TG3_CPMU_CTRL, cpmuctrl);
10942
10943                 /* Release the mutex */
10944                 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
10945         }
10946
10947         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
10948             !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
10949                 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
10950                         err |= TG3_PHY_LOOPBACK_FAILED;
10951         }
10952
10953         /* Re-enable gphy autopowerdown. */
10954         if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10955                 tg3_phy_toggle_apd(tp, true);
10956
10957         return err;
10958 }
10959
10960 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
10961                           u64 *data)
10962 {
10963         struct tg3 *tp = netdev_priv(dev);
10964
10965         if (tp->link_config.phy_is_low_power)
10966                 tg3_set_power_state(tp, PCI_D0);
10967
10968         memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
10969
10970         if (tg3_test_nvram(tp) != 0) {
10971                 etest->flags |= ETH_TEST_FL_FAILED;
10972                 data[0] = 1;
10973         }
10974         if (tg3_test_link(tp) != 0) {
10975                 etest->flags |= ETH_TEST_FL_FAILED;
10976                 data[1] = 1;
10977         }
10978         if (etest->flags & ETH_TEST_FL_OFFLINE) {
10979                 int err, err2 = 0, irq_sync = 0;
10980
10981                 if (netif_running(dev)) {
10982                         tg3_phy_stop(tp);
10983                         tg3_netif_stop(tp);
10984                         irq_sync = 1;
10985                 }
10986
10987                 tg3_full_lock(tp, irq_sync);
10988
10989                 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
10990                 err = tg3_nvram_lock(tp);
10991                 tg3_halt_cpu(tp, RX_CPU_BASE);
10992                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10993                         tg3_halt_cpu(tp, TX_CPU_BASE);
10994                 if (!err)
10995                         tg3_nvram_unlock(tp);
10996
10997                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
10998                         tg3_phy_reset(tp);
10999
11000                 if (tg3_test_registers(tp) != 0) {
11001                         etest->flags |= ETH_TEST_FL_FAILED;
11002                         data[2] = 1;
11003                 }
11004                 if (tg3_test_memory(tp) != 0) {
11005                         etest->flags |= ETH_TEST_FL_FAILED;
11006                         data[3] = 1;
11007                 }
11008                 if ((data[4] = tg3_test_loopback(tp)) != 0)
11009                         etest->flags |= ETH_TEST_FL_FAILED;
11010
11011                 tg3_full_unlock(tp);
11012
11013                 if (tg3_test_interrupt(tp) != 0) {
11014                         etest->flags |= ETH_TEST_FL_FAILED;
11015                         data[5] = 1;
11016                 }
11017
11018                 tg3_full_lock(tp, 0);
11019
11020                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11021                 if (netif_running(dev)) {
11022                         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
11023                         err2 = tg3_restart_hw(tp, 1);
11024                         if (!err2)
11025                                 tg3_netif_start(tp);
11026                 }
11027
11028                 tg3_full_unlock(tp);
11029
11030                 if (irq_sync && !err2)
11031                         tg3_phy_start(tp);
11032         }
11033         if (tp->link_config.phy_is_low_power)
11034                 tg3_set_power_state(tp, PCI_D3hot);
11035
11036 }
11037
11038 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
11039 {
11040         struct mii_ioctl_data *data = if_mii(ifr);
11041         struct tg3 *tp = netdev_priv(dev);
11042         int err;
11043
11044         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
11045                 struct phy_device *phydev;
11046                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
11047                         return -EAGAIN;
11048                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
11049                 return phy_mii_ioctl(phydev, data, cmd);
11050         }
11051
11052         switch(cmd) {
11053         case SIOCGMIIPHY:
11054                 data->phy_id = tp->phy_addr;
11055
11056                 /* fallthru */
11057         case SIOCGMIIREG: {
11058                 u32 mii_regval;
11059
11060                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
11061                         break;                  /* We have no PHY */
11062
11063                 if (tp->link_config.phy_is_low_power)
11064                         return -EAGAIN;
11065
11066                 spin_lock_bh(&tp->lock);
11067                 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
11068                 spin_unlock_bh(&tp->lock);
11069
11070                 data->val_out = mii_regval;
11071
11072                 return err;
11073         }
11074
11075         case SIOCSMIIREG:
11076                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
11077                         break;                  /* We have no PHY */
11078
11079                 if (tp->link_config.phy_is_low_power)
11080                         return -EAGAIN;
11081
11082                 spin_lock_bh(&tp->lock);
11083                 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
11084                 spin_unlock_bh(&tp->lock);
11085
11086                 return err;
11087
11088         default:
11089                 /* do nothing */
11090                 break;
11091         }
11092         return -EOPNOTSUPP;
11093 }
11094
11095 #if TG3_VLAN_TAG_USED
11096 static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
11097 {
11098         struct tg3 *tp = netdev_priv(dev);
11099
11100         if (!netif_running(dev)) {
11101                 tp->vlgrp = grp;
11102                 return;
11103         }
11104
11105         tg3_netif_stop(tp);
11106
11107         tg3_full_lock(tp, 0);
11108
11109         tp->vlgrp = grp;
11110
11111         /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
11112         __tg3_set_rx_mode(dev);
11113
11114         tg3_netif_start(tp);
11115
11116         tg3_full_unlock(tp);
11117 }
11118 #endif
11119
11120 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11121 {
11122         struct tg3 *tp = netdev_priv(dev);
11123
11124         memcpy(ec, &tp->coal, sizeof(*ec));
11125         return 0;
11126 }
11127
11128 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11129 {
11130         struct tg3 *tp = netdev_priv(dev);
11131         u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
11132         u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
11133
11134         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
11135                 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
11136                 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
11137                 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
11138                 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
11139         }
11140
11141         if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
11142             (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
11143             (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
11144             (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
11145             (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
11146             (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
11147             (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
11148             (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
11149             (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
11150             (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
11151                 return -EINVAL;
11152
11153         /* No rx interrupts will be generated if both are zero */
11154         if ((ec->rx_coalesce_usecs == 0) &&
11155             (ec->rx_max_coalesced_frames == 0))
11156                 return -EINVAL;
11157
11158         /* No tx interrupts will be generated if both are zero */
11159         if ((ec->tx_coalesce_usecs == 0) &&
11160             (ec->tx_max_coalesced_frames == 0))
11161                 return -EINVAL;
11162
11163         /* Only copy relevant parameters, ignore all others. */
11164         tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
11165         tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
11166         tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
11167         tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
11168         tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
11169         tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
11170         tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
11171         tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
11172         tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
11173
11174         if (netif_running(dev)) {
11175                 tg3_full_lock(tp, 0);
11176                 __tg3_set_coalesce(tp, &tp->coal);
11177                 tg3_full_unlock(tp);
11178         }
11179         return 0;
11180 }
11181
11182 static const struct ethtool_ops tg3_ethtool_ops = {
11183         .get_settings           = tg3_get_settings,
11184         .set_settings           = tg3_set_settings,
11185         .get_drvinfo            = tg3_get_drvinfo,
11186         .get_regs_len           = tg3_get_regs_len,
11187         .get_regs               = tg3_get_regs,
11188         .get_wol                = tg3_get_wol,
11189         .set_wol                = tg3_set_wol,
11190         .get_msglevel           = tg3_get_msglevel,
11191         .set_msglevel           = tg3_set_msglevel,
11192         .nway_reset             = tg3_nway_reset,
11193         .get_link               = ethtool_op_get_link,
11194         .get_eeprom_len         = tg3_get_eeprom_len,
11195         .get_eeprom             = tg3_get_eeprom,
11196         .set_eeprom             = tg3_set_eeprom,
11197         .get_ringparam          = tg3_get_ringparam,
11198         .set_ringparam          = tg3_set_ringparam,
11199         .get_pauseparam         = tg3_get_pauseparam,
11200         .set_pauseparam         = tg3_set_pauseparam,
11201         .get_rx_csum            = tg3_get_rx_csum,
11202         .set_rx_csum            = tg3_set_rx_csum,
11203         .set_tx_csum            = tg3_set_tx_csum,
11204         .set_sg                 = ethtool_op_set_sg,
11205         .set_tso                = tg3_set_tso,
11206         .self_test              = tg3_self_test,
11207         .get_strings            = tg3_get_strings,
11208         .phys_id                = tg3_phys_id,
11209         .get_ethtool_stats      = tg3_get_ethtool_stats,
11210         .get_coalesce           = tg3_get_coalesce,
11211         .set_coalesce           = tg3_set_coalesce,
11212         .get_sset_count         = tg3_get_sset_count,
11213 };
11214
11215 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
11216 {
11217         u32 cursize, val, magic;
11218
11219         tp->nvram_size = EEPROM_CHIP_SIZE;
11220
11221         if (tg3_nvram_read(tp, 0, &magic) != 0)
11222                 return;
11223
11224         if ((magic != TG3_EEPROM_MAGIC) &&
11225             ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
11226             ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
11227                 return;
11228
11229         /*
11230          * Size the chip by reading offsets at increasing powers of two.
11231          * When we encounter our validation signature, we know the addressing
11232          * has wrapped around, and thus have our chip size.
11233          */
11234         cursize = 0x10;
11235
11236         while (cursize < tp->nvram_size) {
11237                 if (tg3_nvram_read(tp, cursize, &val) != 0)
11238                         return;
11239
11240                 if (val == magic)
11241                         break;
11242
11243                 cursize <<= 1;
11244         }
11245
11246         tp->nvram_size = cursize;
11247 }
11248
11249 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
11250 {
11251         u32 val;
11252
11253         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
11254             tg3_nvram_read(tp, 0, &val) != 0)
11255                 return;
11256
11257         /* Selfboot format */
11258         if (val != TG3_EEPROM_MAGIC) {
11259                 tg3_get_eeprom_size(tp);
11260                 return;
11261         }
11262
11263         if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
11264                 if (val != 0) {
11265                         /* This is confusing.  We want to operate on the
11266                          * 16-bit value at offset 0xf2.  The tg3_nvram_read()
11267                          * call will read from NVRAM and byteswap the data
11268                          * according to the byteswapping settings for all
11269                          * other register accesses.  This ensures the data we
11270                          * want will always reside in the lower 16-bits.
11271                          * However, the data in NVRAM is in LE format, which
11272                          * means the data from the NVRAM read will always be
11273                          * opposite the endianness of the CPU.  The 16-bit
11274                          * byteswap then brings the data to CPU endianness.
11275                          */
11276                         tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
11277                         return;
11278                 }
11279         }
11280         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11281 }
11282
11283 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
11284 {
11285         u32 nvcfg1;
11286
11287         nvcfg1 = tr32(NVRAM_CFG1);
11288         if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
11289                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11290         } else {
11291                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11292                 tw32(NVRAM_CFG1, nvcfg1);
11293         }
11294
11295         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
11296             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
11297                 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
11298                 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
11299                         tp->nvram_jedecnum = JEDEC_ATMEL;
11300                         tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11301                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11302                         break;
11303                 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
11304                         tp->nvram_jedecnum = JEDEC_ATMEL;
11305                         tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
11306                         break;
11307                 case FLASH_VENDOR_ATMEL_EEPROM:
11308                         tp->nvram_jedecnum = JEDEC_ATMEL;
11309                         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11310                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11311                         break;
11312                 case FLASH_VENDOR_ST:
11313                         tp->nvram_jedecnum = JEDEC_ST;
11314                         tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
11315                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11316                         break;
11317                 case FLASH_VENDOR_SAIFUN:
11318                         tp->nvram_jedecnum = JEDEC_SAIFUN;
11319                         tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
11320                         break;
11321                 case FLASH_VENDOR_SST_SMALL:
11322                 case FLASH_VENDOR_SST_LARGE:
11323                         tp->nvram_jedecnum = JEDEC_SST;
11324                         tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
11325                         break;
11326                 }
11327         } else {
11328                 tp->nvram_jedecnum = JEDEC_ATMEL;
11329                 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11330                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11331         }
11332 }
11333
11334 static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
11335 {
11336         switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
11337         case FLASH_5752PAGE_SIZE_256:
11338                 tp->nvram_pagesize = 256;
11339                 break;
11340         case FLASH_5752PAGE_SIZE_512:
11341                 tp->nvram_pagesize = 512;
11342                 break;
11343         case FLASH_5752PAGE_SIZE_1K:
11344                 tp->nvram_pagesize = 1024;
11345                 break;
11346         case FLASH_5752PAGE_SIZE_2K:
11347                 tp->nvram_pagesize = 2048;
11348                 break;
11349         case FLASH_5752PAGE_SIZE_4K:
11350                 tp->nvram_pagesize = 4096;
11351                 break;
11352         case FLASH_5752PAGE_SIZE_264:
11353                 tp->nvram_pagesize = 264;
11354                 break;
11355         case FLASH_5752PAGE_SIZE_528:
11356                 tp->nvram_pagesize = 528;
11357                 break;
11358         }
11359 }
11360
11361 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
11362 {
11363         u32 nvcfg1;
11364
11365         nvcfg1 = tr32(NVRAM_CFG1);
11366
11367         /* NVRAM protection for TPM */
11368         if (nvcfg1 & (1 << 27))
11369                 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11370
11371         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11372         case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
11373         case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
11374                 tp->nvram_jedecnum = JEDEC_ATMEL;
11375                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11376                 break;
11377         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11378                 tp->nvram_jedecnum = JEDEC_ATMEL;
11379                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11380                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11381                 break;
11382         case FLASH_5752VENDOR_ST_M45PE10:
11383         case FLASH_5752VENDOR_ST_M45PE20:
11384         case FLASH_5752VENDOR_ST_M45PE40:
11385                 tp->nvram_jedecnum = JEDEC_ST;
11386                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11387                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11388                 break;
11389         }
11390
11391         if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
11392                 tg3_nvram_get_pagesize(tp, nvcfg1);
11393         } else {
11394                 /* For eeprom, set pagesize to maximum eeprom size */
11395                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11396
11397                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11398                 tw32(NVRAM_CFG1, nvcfg1);
11399         }
11400 }
11401
11402 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
11403 {
11404         u32 nvcfg1, protect = 0;
11405
11406         nvcfg1 = tr32(NVRAM_CFG1);
11407
11408         /* NVRAM protection for TPM */
11409         if (nvcfg1 & (1 << 27)) {
11410                 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11411                 protect = 1;
11412         }
11413
11414         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11415         switch (nvcfg1) {
11416         case FLASH_5755VENDOR_ATMEL_FLASH_1:
11417         case FLASH_5755VENDOR_ATMEL_FLASH_2:
11418         case FLASH_5755VENDOR_ATMEL_FLASH_3:
11419         case FLASH_5755VENDOR_ATMEL_FLASH_5:
11420                 tp->nvram_jedecnum = JEDEC_ATMEL;
11421                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11422                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11423                 tp->nvram_pagesize = 264;
11424                 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
11425                     nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
11426                         tp->nvram_size = (protect ? 0x3e200 :
11427                                           TG3_NVRAM_SIZE_512KB);
11428                 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
11429                         tp->nvram_size = (protect ? 0x1f200 :
11430                                           TG3_NVRAM_SIZE_256KB);
11431                 else
11432                         tp->nvram_size = (protect ? 0x1f200 :
11433                                           TG3_NVRAM_SIZE_128KB);
11434                 break;
11435         case FLASH_5752VENDOR_ST_M45PE10:
11436         case FLASH_5752VENDOR_ST_M45PE20:
11437         case FLASH_5752VENDOR_ST_M45PE40:
11438                 tp->nvram_jedecnum = JEDEC_ST;
11439                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11440                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11441                 tp->nvram_pagesize = 256;
11442                 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
11443                         tp->nvram_size = (protect ?
11444                                           TG3_NVRAM_SIZE_64KB :
11445                                           TG3_NVRAM_SIZE_128KB);
11446                 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
11447                         tp->nvram_size = (protect ?
11448                                           TG3_NVRAM_SIZE_64KB :
11449                                           TG3_NVRAM_SIZE_256KB);
11450                 else
11451                         tp->nvram_size = (protect ?
11452                                           TG3_NVRAM_SIZE_128KB :
11453                                           TG3_NVRAM_SIZE_512KB);
11454                 break;
11455         }
11456 }
11457
11458 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
11459 {
11460         u32 nvcfg1;
11461
11462         nvcfg1 = tr32(NVRAM_CFG1);
11463
11464         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11465         case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
11466         case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11467         case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
11468         case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11469                 tp->nvram_jedecnum = JEDEC_ATMEL;
11470                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11471                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11472
11473                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11474                 tw32(NVRAM_CFG1, nvcfg1);
11475                 break;
11476         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11477         case FLASH_5755VENDOR_ATMEL_FLASH_1:
11478         case FLASH_5755VENDOR_ATMEL_FLASH_2:
11479         case FLASH_5755VENDOR_ATMEL_FLASH_3:
11480                 tp->nvram_jedecnum = JEDEC_ATMEL;
11481                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11482                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11483                 tp->nvram_pagesize = 264;
11484                 break;
11485         case FLASH_5752VENDOR_ST_M45PE10:
11486         case FLASH_5752VENDOR_ST_M45PE20:
11487         case FLASH_5752VENDOR_ST_M45PE40:
11488                 tp->nvram_jedecnum = JEDEC_ST;
11489                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11490                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11491                 tp->nvram_pagesize = 256;
11492                 break;
11493         }
11494 }
11495
11496 static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
11497 {
11498         u32 nvcfg1, protect = 0;
11499
11500         nvcfg1 = tr32(NVRAM_CFG1);
11501
11502         /* NVRAM protection for TPM */
11503         if (nvcfg1 & (1 << 27)) {
11504                 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11505                 protect = 1;
11506         }
11507
11508         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11509         switch (nvcfg1) {
11510         case FLASH_5761VENDOR_ATMEL_ADB021D:
11511         case FLASH_5761VENDOR_ATMEL_ADB041D:
11512         case FLASH_5761VENDOR_ATMEL_ADB081D:
11513         case FLASH_5761VENDOR_ATMEL_ADB161D:
11514         case FLASH_5761VENDOR_ATMEL_MDB021D:
11515         case FLASH_5761VENDOR_ATMEL_MDB041D:
11516         case FLASH_5761VENDOR_ATMEL_MDB081D:
11517         case FLASH_5761VENDOR_ATMEL_MDB161D:
11518                 tp->nvram_jedecnum = JEDEC_ATMEL;
11519                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11520                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11521                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11522                 tp->nvram_pagesize = 256;
11523                 break;
11524         case FLASH_5761VENDOR_ST_A_M45PE20:
11525         case FLASH_5761VENDOR_ST_A_M45PE40:
11526         case FLASH_5761VENDOR_ST_A_M45PE80:
11527         case FLASH_5761VENDOR_ST_A_M45PE16:
11528         case FLASH_5761VENDOR_ST_M_M45PE20:
11529         case FLASH_5761VENDOR_ST_M_M45PE40:
11530         case FLASH_5761VENDOR_ST_M_M45PE80:
11531         case FLASH_5761VENDOR_ST_M_M45PE16:
11532                 tp->nvram_jedecnum = JEDEC_ST;
11533                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11534                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11535                 tp->nvram_pagesize = 256;
11536                 break;
11537         }
11538
11539         if (protect) {
11540                 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
11541         } else {
11542                 switch (nvcfg1) {
11543                 case FLASH_5761VENDOR_ATMEL_ADB161D:
11544                 case FLASH_5761VENDOR_ATMEL_MDB161D:
11545                 case FLASH_5761VENDOR_ST_A_M45PE16:
11546                 case FLASH_5761VENDOR_ST_M_M45PE16:
11547                         tp->nvram_size = TG3_NVRAM_SIZE_2MB;
11548                         break;
11549                 case FLASH_5761VENDOR_ATMEL_ADB081D:
11550                 case FLASH_5761VENDOR_ATMEL_MDB081D:
11551                 case FLASH_5761VENDOR_ST_A_M45PE80:
11552                 case FLASH_5761VENDOR_ST_M_M45PE80:
11553                         tp->nvram_size = TG3_NVRAM_SIZE_1MB;
11554                         break;
11555                 case FLASH_5761VENDOR_ATMEL_ADB041D:
11556                 case FLASH_5761VENDOR_ATMEL_MDB041D:
11557                 case FLASH_5761VENDOR_ST_A_M45PE40:
11558                 case FLASH_5761VENDOR_ST_M_M45PE40:
11559                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11560                         break;
11561                 case FLASH_5761VENDOR_ATMEL_ADB021D:
11562                 case FLASH_5761VENDOR_ATMEL_MDB021D:
11563                 case FLASH_5761VENDOR_ST_A_M45PE20:
11564                 case FLASH_5761VENDOR_ST_M_M45PE20:
11565                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11566                         break;
11567                 }
11568         }
11569 }
11570
11571 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
11572 {
11573         tp->nvram_jedecnum = JEDEC_ATMEL;
11574         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11575         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11576 }
11577
11578 static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
11579 {
11580         u32 nvcfg1;
11581
11582         nvcfg1 = tr32(NVRAM_CFG1);
11583
11584         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11585         case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11586         case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11587                 tp->nvram_jedecnum = JEDEC_ATMEL;
11588                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11589                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11590
11591                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11592                 tw32(NVRAM_CFG1, nvcfg1);
11593                 return;
11594         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11595         case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11596         case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11597         case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11598         case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11599         case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11600         case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11601                 tp->nvram_jedecnum = JEDEC_ATMEL;
11602                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11603                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11604
11605                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11606                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11607                 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11608                 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11609                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11610                         break;
11611                 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11612                 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11613                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11614                         break;
11615                 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11616                 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11617                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11618                         break;
11619                 }
11620                 break;
11621         case FLASH_5752VENDOR_ST_M45PE10:
11622         case FLASH_5752VENDOR_ST_M45PE20:
11623         case FLASH_5752VENDOR_ST_M45PE40:
11624                 tp->nvram_jedecnum = JEDEC_ST;
11625                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11626                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11627
11628                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11629                 case FLASH_5752VENDOR_ST_M45PE10:
11630                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11631                         break;
11632                 case FLASH_5752VENDOR_ST_M45PE20:
11633                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11634                         break;
11635                 case FLASH_5752VENDOR_ST_M45PE40:
11636                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11637                         break;
11638                 }
11639                 break;
11640         default:
11641                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11642                 return;
11643         }
11644
11645         tg3_nvram_get_pagesize(tp, nvcfg1);
11646         if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11647                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11648 }
11649
11650
11651 static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp)
11652 {
11653         u32 nvcfg1;
11654
11655         nvcfg1 = tr32(NVRAM_CFG1);
11656
11657         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11658         case FLASH_5717VENDOR_ATMEL_EEPROM:
11659         case FLASH_5717VENDOR_MICRO_EEPROM:
11660                 tp->nvram_jedecnum = JEDEC_ATMEL;
11661                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11662                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11663
11664                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11665                 tw32(NVRAM_CFG1, nvcfg1);
11666                 return;
11667         case FLASH_5717VENDOR_ATMEL_MDB011D:
11668         case FLASH_5717VENDOR_ATMEL_ADB011B:
11669         case FLASH_5717VENDOR_ATMEL_ADB011D:
11670         case FLASH_5717VENDOR_ATMEL_MDB021D:
11671         case FLASH_5717VENDOR_ATMEL_ADB021B:
11672         case FLASH_5717VENDOR_ATMEL_ADB021D:
11673         case FLASH_5717VENDOR_ATMEL_45USPT:
11674                 tp->nvram_jedecnum = JEDEC_ATMEL;
11675                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11676                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11677
11678                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11679                 case FLASH_5717VENDOR_ATMEL_MDB021D:
11680                 case FLASH_5717VENDOR_ATMEL_ADB021B:
11681                 case FLASH_5717VENDOR_ATMEL_ADB021D:
11682                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11683                         break;
11684                 default:
11685                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11686                         break;
11687                 }
11688                 break;
11689         case FLASH_5717VENDOR_ST_M_M25PE10:
11690         case FLASH_5717VENDOR_ST_A_M25PE10:
11691         case FLASH_5717VENDOR_ST_M_M45PE10:
11692         case FLASH_5717VENDOR_ST_A_M45PE10:
11693         case FLASH_5717VENDOR_ST_M_M25PE20:
11694         case FLASH_5717VENDOR_ST_A_M25PE20:
11695         case FLASH_5717VENDOR_ST_M_M45PE20:
11696         case FLASH_5717VENDOR_ST_A_M45PE20:
11697         case FLASH_5717VENDOR_ST_25USPT:
11698         case FLASH_5717VENDOR_ST_45USPT:
11699                 tp->nvram_jedecnum = JEDEC_ST;
11700                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11701                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11702
11703                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11704                 case FLASH_5717VENDOR_ST_M_M25PE20:
11705                 case FLASH_5717VENDOR_ST_A_M25PE20:
11706                 case FLASH_5717VENDOR_ST_M_M45PE20:
11707                 case FLASH_5717VENDOR_ST_A_M45PE20:
11708                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11709                         break;
11710                 default:
11711                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11712                         break;
11713                 }
11714                 break;
11715         default:
11716                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11717                 return;
11718         }
11719
11720         tg3_nvram_get_pagesize(tp, nvcfg1);
11721         if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11722                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11723 }
11724
11725 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
11726 static void __devinit tg3_nvram_init(struct tg3 *tp)
11727 {
11728         tw32_f(GRC_EEPROM_ADDR,
11729              (EEPROM_ADDR_FSM_RESET |
11730               (EEPROM_DEFAULT_CLOCK_PERIOD <<
11731                EEPROM_ADDR_CLKPERD_SHIFT)));
11732
11733         msleep(1);
11734
11735         /* Enable seeprom accesses. */
11736         tw32_f(GRC_LOCAL_CTRL,
11737              tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
11738         udelay(100);
11739
11740         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11741             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
11742                 tp->tg3_flags |= TG3_FLAG_NVRAM;
11743
11744                 if (tg3_nvram_lock(tp)) {
11745                         printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
11746                                "tg3_nvram_init failed.\n", tp->dev->name);
11747                         return;
11748                 }
11749                 tg3_enable_nvram_access(tp);
11750
11751                 tp->nvram_size = 0;
11752
11753                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
11754                         tg3_get_5752_nvram_info(tp);
11755                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
11756                         tg3_get_5755_nvram_info(tp);
11757                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
11758                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11759                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11760                         tg3_get_5787_nvram_info(tp);
11761                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
11762                         tg3_get_5761_nvram_info(tp);
11763                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11764                         tg3_get_5906_nvram_info(tp);
11765                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
11766                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
11767                         tg3_get_57780_nvram_info(tp);
11768                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
11769                         tg3_get_5717_nvram_info(tp);
11770                 else
11771                         tg3_get_nvram_info(tp);
11772
11773                 if (tp->nvram_size == 0)
11774                         tg3_get_nvram_size(tp);
11775
11776                 tg3_disable_nvram_access(tp);
11777                 tg3_nvram_unlock(tp);
11778
11779         } else {
11780                 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
11781
11782                 tg3_get_eeprom_size(tp);
11783         }
11784 }
11785
11786 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
11787                                     u32 offset, u32 len, u8 *buf)
11788 {
11789         int i, j, rc = 0;
11790         u32 val;
11791
11792         for (i = 0; i < len; i += 4) {
11793                 u32 addr;
11794                 __be32 data;
11795
11796                 addr = offset + i;
11797
11798                 memcpy(&data, buf + i, 4);
11799
11800                 /*
11801                  * The SEEPROM interface expects the data to always be opposite
11802                  * the native endian format.  We accomplish this by reversing
11803                  * all the operations that would have been performed on the
11804                  * data from a call to tg3_nvram_read_be32().
11805                  */
11806                 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
11807
11808                 val = tr32(GRC_EEPROM_ADDR);
11809                 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
11810
11811                 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
11812                         EEPROM_ADDR_READ);
11813                 tw32(GRC_EEPROM_ADDR, val |
11814                         (0 << EEPROM_ADDR_DEVID_SHIFT) |
11815                         (addr & EEPROM_ADDR_ADDR_MASK) |
11816                         EEPROM_ADDR_START |
11817                         EEPROM_ADDR_WRITE);
11818
11819                 for (j = 0; j < 1000; j++) {
11820                         val = tr32(GRC_EEPROM_ADDR);
11821
11822                         if (val & EEPROM_ADDR_COMPLETE)
11823                                 break;
11824                         msleep(1);
11825                 }
11826                 if (!(val & EEPROM_ADDR_COMPLETE)) {
11827                         rc = -EBUSY;
11828                         break;
11829                 }
11830         }
11831
11832         return rc;
11833 }
11834
11835 /* offset and length are dword aligned */
11836 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
11837                 u8 *buf)
11838 {
11839         int ret = 0;
11840         u32 pagesize = tp->nvram_pagesize;
11841         u32 pagemask = pagesize - 1;
11842         u32 nvram_cmd;
11843         u8 *tmp;
11844
11845         tmp = kmalloc(pagesize, GFP_KERNEL);
11846         if (tmp == NULL)
11847                 return -ENOMEM;
11848
11849         while (len) {
11850                 int j;
11851                 u32 phy_addr, page_off, size;
11852
11853                 phy_addr = offset & ~pagemask;
11854
11855                 for (j = 0; j < pagesize; j += 4) {
11856                         ret = tg3_nvram_read_be32(tp, phy_addr + j,
11857                                                   (__be32 *) (tmp + j));
11858                         if (ret)
11859                                 break;
11860                 }
11861                 if (ret)
11862                         break;
11863
11864                 page_off = offset & pagemask;
11865                 size = pagesize;
11866                 if (len < size)
11867                         size = len;
11868
11869                 len -= size;
11870
11871                 memcpy(tmp + page_off, buf, size);
11872
11873                 offset = offset + (pagesize - page_off);
11874
11875                 tg3_enable_nvram_access(tp);
11876
11877                 /*
11878                  * Before we can erase the flash page, we need
11879                  * to issue a special "write enable" command.
11880                  */
11881                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11882
11883                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11884                         break;
11885
11886                 /* Erase the target page */
11887                 tw32(NVRAM_ADDR, phy_addr);
11888
11889                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
11890                         NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
11891
11892                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11893                         break;
11894
11895                 /* Issue another write enable to start the write. */
11896                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11897
11898                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11899                         break;
11900
11901                 for (j = 0; j < pagesize; j += 4) {
11902                         __be32 data;
11903
11904                         data = *((__be32 *) (tmp + j));
11905
11906                         tw32(NVRAM_WRDATA, be32_to_cpu(data));
11907
11908                         tw32(NVRAM_ADDR, phy_addr + j);
11909
11910                         nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
11911                                 NVRAM_CMD_WR;
11912
11913                         if (j == 0)
11914                                 nvram_cmd |= NVRAM_CMD_FIRST;
11915                         else if (j == (pagesize - 4))
11916                                 nvram_cmd |= NVRAM_CMD_LAST;
11917
11918                         if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11919                                 break;
11920                 }
11921                 if (ret)
11922                         break;
11923         }
11924
11925         nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11926         tg3_nvram_exec_cmd(tp, nvram_cmd);
11927
11928         kfree(tmp);
11929
11930         return ret;
11931 }
11932
11933 /* offset and length are dword aligned */
11934 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
11935                 u8 *buf)
11936 {
11937         int i, ret = 0;
11938
11939         for (i = 0; i < len; i += 4, offset += 4) {
11940                 u32 page_off, phy_addr, nvram_cmd;
11941                 __be32 data;
11942
11943                 memcpy(&data, buf + i, 4);
11944                 tw32(NVRAM_WRDATA, be32_to_cpu(data));
11945
11946                 page_off = offset % tp->nvram_pagesize;
11947
11948                 phy_addr = tg3_nvram_phys_addr(tp, offset);
11949
11950                 tw32(NVRAM_ADDR, phy_addr);
11951
11952                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
11953
11954                 if ((page_off == 0) || (i == 0))
11955                         nvram_cmd |= NVRAM_CMD_FIRST;
11956                 if (page_off == (tp->nvram_pagesize - 4))
11957                         nvram_cmd |= NVRAM_CMD_LAST;
11958
11959                 if (i == (len - 4))
11960                         nvram_cmd |= NVRAM_CMD_LAST;
11961
11962                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
11963                     !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
11964                     (tp->nvram_jedecnum == JEDEC_ST) &&
11965                     (nvram_cmd & NVRAM_CMD_FIRST)) {
11966
11967                         if ((ret = tg3_nvram_exec_cmd(tp,
11968                                 NVRAM_CMD_WREN | NVRAM_CMD_GO |
11969                                 NVRAM_CMD_DONE)))
11970
11971                                 break;
11972                 }
11973                 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11974                         /* We always do complete word writes to eeprom. */
11975                         nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
11976                 }
11977
11978                 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11979                         break;
11980         }
11981         return ret;
11982 }
11983
11984 /* offset and length are dword aligned */
11985 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
11986 {
11987         int ret;
11988
11989         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
11990                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
11991                        ~GRC_LCLCTRL_GPIO_OUTPUT1);
11992                 udelay(40);
11993         }
11994
11995         if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
11996                 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
11997         }
11998         else {
11999                 u32 grc_mode;
12000
12001                 ret = tg3_nvram_lock(tp);
12002                 if (ret)
12003                         return ret;
12004
12005                 tg3_enable_nvram_access(tp);
12006                 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
12007                     !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM))
12008                         tw32(NVRAM_WRITE1, 0x406);
12009
12010                 grc_mode = tr32(GRC_MODE);
12011                 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
12012
12013                 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
12014                         !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
12015
12016                         ret = tg3_nvram_write_block_buffered(tp, offset, len,
12017                                 buf);
12018                 }
12019                 else {
12020                         ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
12021                                 buf);
12022                 }
12023
12024                 grc_mode = tr32(GRC_MODE);
12025                 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
12026
12027                 tg3_disable_nvram_access(tp);
12028                 tg3_nvram_unlock(tp);
12029         }
12030
12031         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
12032                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
12033                 udelay(40);
12034         }
12035
12036         return ret;
12037 }
12038
12039 struct subsys_tbl_ent {
12040         u16 subsys_vendor, subsys_devid;
12041         u32 phy_id;
12042 };
12043
12044 static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
12045         /* Broadcom boards. */
12046         { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
12047         { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
12048         { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
12049         { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 },              /* BCM95700A9 */
12050         { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
12051         { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
12052         { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 },              /* BCM95701A7 */
12053         { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
12054         { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
12055         { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
12056         { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
12057
12058         /* 3com boards. */
12059         { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
12060         { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
12061         { PCI_VENDOR_ID_3COM, 0x1004, 0 },              /* 3C996SX */
12062         { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
12063         { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
12064
12065         /* DELL boards. */
12066         { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
12067         { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
12068         { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
12069         { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
12070
12071         /* Compaq boards. */
12072         { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
12073         { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
12074         { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 },              /* CHANGELING */
12075         { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
12076         { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
12077
12078         /* IBM boards. */
12079         { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
12080 };
12081
12082 static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
12083 {
12084         int i;
12085
12086         for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
12087                 if ((subsys_id_to_phy_id[i].subsys_vendor ==
12088                      tp->pdev->subsystem_vendor) &&
12089                     (subsys_id_to_phy_id[i].subsys_devid ==
12090                      tp->pdev->subsystem_device))
12091                         return &subsys_id_to_phy_id[i];
12092         }
12093         return NULL;
12094 }
12095
12096 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
12097 {
12098         u32 val;
12099         u16 pmcsr;
12100
12101         /* On some early chips the SRAM cannot be accessed in D3hot state,
12102          * so need make sure we're in D0.
12103          */
12104         pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
12105         pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
12106         pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
12107         msleep(1);
12108
12109         /* Make sure register accesses (indirect or otherwise)
12110          * will function correctly.
12111          */
12112         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12113                                tp->misc_host_ctrl);
12114
12115         /* The memory arbiter has to be enabled in order for SRAM accesses
12116          * to succeed.  Normally on powerup the tg3 chip firmware will make
12117          * sure it is enabled, but other entities such as system netboot
12118          * code might disable it.
12119          */
12120         val = tr32(MEMARB_MODE);
12121         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
12122
12123         tp->phy_id = PHY_ID_INVALID;
12124         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12125
12126         /* Assume an onboard device and WOL capable by default.  */
12127         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
12128
12129         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12130                 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
12131                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12132                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12133                 }
12134                 val = tr32(VCPU_CFGSHDW);
12135                 if (val & VCPU_CFGSHDW_ASPM_DBNC)
12136                         tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
12137                 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
12138                     (val & VCPU_CFGSHDW_WOL_MAGPKT))
12139                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12140                 goto done;
12141         }
12142
12143         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
12144         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
12145                 u32 nic_cfg, led_cfg;
12146                 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
12147                 int eeprom_phy_serdes = 0;
12148
12149                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
12150                 tp->nic_sram_data_cfg = nic_cfg;
12151
12152                 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
12153                 ver >>= NIC_SRAM_DATA_VER_SHIFT;
12154                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
12155                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
12156                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
12157                     (ver > 0) && (ver < 0x100))
12158                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
12159
12160                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
12161                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
12162
12163                 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
12164                     NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
12165                         eeprom_phy_serdes = 1;
12166
12167                 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
12168                 if (nic_phy_id != 0) {
12169                         u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
12170                         u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
12171
12172                         eeprom_phy_id  = (id1 >> 16) << 10;
12173                         eeprom_phy_id |= (id2 & 0xfc00) << 16;
12174                         eeprom_phy_id |= (id2 & 0x03ff) <<  0;
12175                 } else
12176                         eeprom_phy_id = 0;
12177
12178                 tp->phy_id = eeprom_phy_id;
12179                 if (eeprom_phy_serdes) {
12180                         if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
12181                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
12182                                 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
12183                         else
12184                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12185                 }
12186
12187                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
12188                         led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
12189                                     SHASTA_EXT_LED_MODE_MASK);
12190                 else
12191                         led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
12192
12193                 switch (led_cfg) {
12194                 default:
12195                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
12196                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12197                         break;
12198
12199                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
12200                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12201                         break;
12202
12203                 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
12204                         tp->led_ctrl = LED_CTRL_MODE_MAC;
12205
12206                         /* Default to PHY_1_MODE if 0 (MAC_MODE) is
12207                          * read on some older 5700/5701 bootcode.
12208                          */
12209                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
12210                             ASIC_REV_5700 ||
12211                             GET_ASIC_REV(tp->pci_chip_rev_id) ==
12212                             ASIC_REV_5701)
12213                                 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12214
12215                         break;
12216
12217                 case SHASTA_EXT_LED_SHARED:
12218                         tp->led_ctrl = LED_CTRL_MODE_SHARED;
12219                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
12220                             tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
12221                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12222                                                  LED_CTRL_MODE_PHY_2);
12223                         break;
12224
12225                 case SHASTA_EXT_LED_MAC:
12226                         tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
12227                         break;
12228
12229                 case SHASTA_EXT_LED_COMBO:
12230                         tp->led_ctrl = LED_CTRL_MODE_COMBO;
12231                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
12232                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12233                                                  LED_CTRL_MODE_PHY_2);
12234                         break;
12235
12236                 }
12237
12238                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12239                      GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
12240                     tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
12241                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12242
12243                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
12244                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12245
12246                 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
12247                         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
12248                         if ((tp->pdev->subsystem_vendor ==
12249                              PCI_VENDOR_ID_ARIMA) &&
12250                             (tp->pdev->subsystem_device == 0x205a ||
12251                              tp->pdev->subsystem_device == 0x2063))
12252                                 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12253                 } else {
12254                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12255                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12256                 }
12257
12258                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
12259                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
12260                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
12261                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
12262                 }
12263
12264                 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
12265                         (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
12266                         tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
12267
12268                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
12269                     !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
12270                         tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
12271
12272                 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
12273                     (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
12274                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12275
12276                 if (cfg2 & (1 << 17))
12277                         tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
12278
12279                 /* serdes signal pre-emphasis in register 0x590 set by */
12280                 /* bootcode if bit 18 is set */
12281                 if (cfg2 & (1 << 18))
12282                         tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
12283
12284                 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12285                       GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
12286                     (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
12287                         tp->tg3_flags3 |= TG3_FLG3_PHY_ENABLE_APD;
12288
12289                 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12290                         u32 cfg3;
12291
12292                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
12293                         if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
12294                                 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
12295                 }
12296
12297                 if (cfg4 & NIC_SRAM_RGMII_STD_IBND_DISABLE)
12298                         tp->tg3_flags3 |= TG3_FLG3_RGMII_STD_IBND_DISABLE;
12299                 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
12300                         tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
12301                 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
12302                         tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
12303         }
12304 done:
12305         device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
12306         device_set_wakeup_enable(&tp->pdev->dev,
12307                                  tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
12308 }
12309
12310 static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
12311 {
12312         int i;
12313         u32 val;
12314
12315         tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
12316         tw32(OTP_CTRL, cmd);
12317
12318         /* Wait for up to 1 ms for command to execute. */
12319         for (i = 0; i < 100; i++) {
12320                 val = tr32(OTP_STATUS);
12321                 if (val & OTP_STATUS_CMD_DONE)
12322                         break;
12323                 udelay(10);
12324         }
12325
12326         return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
12327 }
12328
12329 /* Read the gphy configuration from the OTP region of the chip.  The gphy
12330  * configuration is a 32-bit value that straddles the alignment boundary.
12331  * We do two 32-bit reads and then shift and merge the results.
12332  */
12333 static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
12334 {
12335         u32 bhalf_otp, thalf_otp;
12336
12337         tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
12338
12339         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
12340                 return 0;
12341
12342         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
12343
12344         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12345                 return 0;
12346
12347         thalf_otp = tr32(OTP_READ_DATA);
12348
12349         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
12350
12351         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12352                 return 0;
12353
12354         bhalf_otp = tr32(OTP_READ_DATA);
12355
12356         return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
12357 }
12358
12359 static int __devinit tg3_phy_probe(struct tg3 *tp)
12360 {
12361         u32 hw_phy_id_1, hw_phy_id_2;
12362         u32 hw_phy_id, hw_phy_id_masked;
12363         int err;
12364
12365         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
12366                 return tg3_phy_init(tp);
12367
12368         /* Reading the PHY ID register can conflict with ASF
12369          * firmware access to the PHY hardware.
12370          */
12371         err = 0;
12372         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12373             (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
12374                 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
12375         } else {
12376                 /* Now read the physical PHY_ID from the chip and verify
12377                  * that it is sane.  If it doesn't look good, we fall back
12378                  * to either the hard-coded table based PHY_ID and failing
12379                  * that the value found in the eeprom area.
12380                  */
12381                 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
12382                 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
12383
12384                 hw_phy_id  = (hw_phy_id_1 & 0xffff) << 10;
12385                 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
12386                 hw_phy_id |= (hw_phy_id_2 & 0x03ff) <<  0;
12387
12388                 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
12389         }
12390
12391         if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
12392                 tp->phy_id = hw_phy_id;
12393                 if (hw_phy_id_masked == PHY_ID_BCM8002)
12394                         tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12395                 else
12396                         tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
12397         } else {
12398                 if (tp->phy_id != PHY_ID_INVALID) {
12399                         /* Do nothing, phy ID already set up in
12400                          * tg3_get_eeprom_hw_cfg().
12401                          */
12402                 } else {
12403                         struct subsys_tbl_ent *p;
12404
12405                         /* No eeprom signature?  Try the hardcoded
12406                          * subsys device table.
12407                          */
12408                         p = lookup_by_subsys(tp);
12409                         if (!p)
12410                                 return -ENODEV;
12411
12412                         tp->phy_id = p->phy_id;
12413                         if (!tp->phy_id ||
12414                             tp->phy_id == PHY_ID_BCM8002)
12415                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12416                 }
12417         }
12418
12419         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
12420             !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
12421             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
12422                 u32 bmsr, adv_reg, tg3_ctrl, mask;
12423
12424                 tg3_readphy(tp, MII_BMSR, &bmsr);
12425                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
12426                     (bmsr & BMSR_LSTATUS))
12427                         goto skip_phy_reset;
12428
12429                 err = tg3_phy_reset(tp);
12430                 if (err)
12431                         return err;
12432
12433                 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
12434                            ADVERTISE_100HALF | ADVERTISE_100FULL |
12435                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
12436                 tg3_ctrl = 0;
12437                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
12438                         tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
12439                                     MII_TG3_CTRL_ADV_1000_FULL);
12440                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12441                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
12442                                 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
12443                                              MII_TG3_CTRL_ENABLE_AS_MASTER);
12444                 }
12445
12446                 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
12447                         ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
12448                         ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
12449                 if (!tg3_copper_is_advertising_all(tp, mask)) {
12450                         tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12451
12452                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
12453                                 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12454
12455                         tg3_writephy(tp, MII_BMCR,
12456                                      BMCR_ANENABLE | BMCR_ANRESTART);
12457                 }
12458                 tg3_phy_set_wirespeed(tp);
12459
12460                 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12461                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
12462                         tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12463         }
12464
12465 skip_phy_reset:
12466         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
12467                 err = tg3_init_5401phy_dsp(tp);
12468                 if (err)
12469                         return err;
12470         }
12471
12472         if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
12473                 err = tg3_init_5401phy_dsp(tp);
12474         }
12475
12476         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
12477                 tp->link_config.advertising =
12478                         (ADVERTISED_1000baseT_Half |
12479                          ADVERTISED_1000baseT_Full |
12480                          ADVERTISED_Autoneg |
12481                          ADVERTISED_FIBRE);
12482         if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
12483                 tp->link_config.advertising &=
12484                         ~(ADVERTISED_1000baseT_Half |
12485                           ADVERTISED_1000baseT_Full);
12486
12487         return err;
12488 }
12489
12490 static void __devinit tg3_read_partno(struct tg3 *tp)
12491 {
12492         unsigned char vpd_data[TG3_NVM_VPD_LEN];   /* in little-endian format */
12493         unsigned int i;
12494         u32 magic;
12495
12496         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
12497             tg3_nvram_read(tp, 0x0, &magic))
12498                 goto out_not_found;
12499
12500         if (magic == TG3_EEPROM_MAGIC) {
12501                 for (i = 0; i < TG3_NVM_VPD_LEN; i += 4) {
12502                         u32 tmp;
12503
12504                         /* The data is in little-endian format in NVRAM.
12505                          * Use the big-endian read routines to preserve
12506                          * the byte order as it exists in NVRAM.
12507                          */
12508                         if (tg3_nvram_read_be32(tp, TG3_NVM_VPD_OFF + i, &tmp))
12509                                 goto out_not_found;
12510
12511                         memcpy(&vpd_data[i], &tmp, sizeof(tmp));
12512                 }
12513         } else {
12514                 ssize_t cnt;
12515                 unsigned int pos = 0, i = 0;
12516
12517                 for (; pos < TG3_NVM_VPD_LEN && i < 3; i++, pos += cnt) {
12518                         cnt = pci_read_vpd(tp->pdev, pos,
12519                                            TG3_NVM_VPD_LEN - pos,
12520                                            &vpd_data[pos]);
12521                         if (cnt == -ETIMEDOUT || -EINTR)
12522                                 cnt = 0;
12523                         else if (cnt < 0)
12524                                 goto out_not_found;
12525                 }
12526                 if (pos != TG3_NVM_VPD_LEN)
12527                         goto out_not_found;
12528         }
12529
12530         /* Now parse and find the part number. */
12531         for (i = 0; i < TG3_NVM_VPD_LEN - 2; ) {
12532                 unsigned char val = vpd_data[i];
12533                 unsigned int block_end;
12534
12535                 if (val == 0x82 || val == 0x91) {
12536                         i = (i + 3 +
12537                              (vpd_data[i + 1] +
12538                               (vpd_data[i + 2] << 8)));
12539                         continue;
12540                 }
12541
12542                 if (val != 0x90)
12543                         goto out_not_found;
12544
12545                 block_end = (i + 3 +
12546                              (vpd_data[i + 1] +
12547                               (vpd_data[i + 2] << 8)));
12548                 i += 3;
12549
12550                 if (block_end > TG3_NVM_VPD_LEN)
12551                         goto out_not_found;
12552
12553                 while (i < (block_end - 2)) {
12554                         if (vpd_data[i + 0] == 'P' &&
12555                             vpd_data[i + 1] == 'N') {
12556                                 int partno_len = vpd_data[i + 2];
12557
12558                                 i += 3;
12559                                 if (partno_len > TG3_BPN_SIZE ||
12560                                     (partno_len + i) > TG3_NVM_VPD_LEN)
12561                                         goto out_not_found;
12562
12563                                 memcpy(tp->board_part_number,
12564                                        &vpd_data[i], partno_len);
12565
12566                                 /* Success. */
12567                                 return;
12568                         }
12569                         i += 3 + vpd_data[i + 2];
12570                 }
12571
12572                 /* Part number not found. */
12573                 goto out_not_found;
12574         }
12575
12576 out_not_found:
12577         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12578                 strcpy(tp->board_part_number, "BCM95906");
12579         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12580                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
12581                 strcpy(tp->board_part_number, "BCM57780");
12582         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12583                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
12584                 strcpy(tp->board_part_number, "BCM57760");
12585         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12586                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
12587                 strcpy(tp->board_part_number, "BCM57790");
12588         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12589                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
12590                 strcpy(tp->board_part_number, "BCM57788");
12591         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
12592                 strcpy(tp->board_part_number, "BCM57765");
12593         else
12594                 strcpy(tp->board_part_number, "none");
12595 }
12596
12597 static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
12598 {
12599         u32 val;
12600
12601         if (tg3_nvram_read(tp, offset, &val) ||
12602             (val & 0xfc000000) != 0x0c000000 ||
12603             tg3_nvram_read(tp, offset + 4, &val) ||
12604             val != 0)
12605                 return 0;
12606
12607         return 1;
12608 }
12609
12610 static void __devinit tg3_read_bc_ver(struct tg3 *tp)
12611 {
12612         u32 val, offset, start, ver_offset;
12613         int i;
12614         bool newver = false;
12615
12616         if (tg3_nvram_read(tp, 0xc, &offset) ||
12617             tg3_nvram_read(tp, 0x4, &start))
12618                 return;
12619
12620         offset = tg3_nvram_logical_addr(tp, offset);
12621
12622         if (tg3_nvram_read(tp, offset, &val))
12623                 return;
12624
12625         if ((val & 0xfc000000) == 0x0c000000) {
12626                 if (tg3_nvram_read(tp, offset + 4, &val))
12627                         return;
12628
12629                 if (val == 0)
12630                         newver = true;
12631         }
12632
12633         if (newver) {
12634                 if (tg3_nvram_read(tp, offset + 8, &ver_offset))
12635                         return;
12636
12637                 offset = offset + ver_offset - start;
12638                 for (i = 0; i < 16; i += 4) {
12639                         __be32 v;
12640                         if (tg3_nvram_read_be32(tp, offset + i, &v))
12641                                 return;
12642
12643                         memcpy(tp->fw_ver + i, &v, sizeof(v));
12644                 }
12645         } else {
12646                 u32 major, minor;
12647
12648                 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
12649                         return;
12650
12651                 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
12652                         TG3_NVM_BCVER_MAJSFT;
12653                 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
12654                 snprintf(&tp->fw_ver[0], 32, "v%d.%02d", major, minor);
12655         }
12656 }
12657
12658 static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
12659 {
12660         u32 val, major, minor;
12661
12662         /* Use native endian representation */
12663         if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
12664                 return;
12665
12666         major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
12667                 TG3_NVM_HWSB_CFG1_MAJSFT;
12668         minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
12669                 TG3_NVM_HWSB_CFG1_MINSFT;
12670
12671         snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
12672 }
12673
12674 static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
12675 {
12676         u32 offset, major, minor, build;
12677
12678         tp->fw_ver[0] = 's';
12679         tp->fw_ver[1] = 'b';
12680         tp->fw_ver[2] = '\0';
12681
12682         if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
12683                 return;
12684
12685         switch (val & TG3_EEPROM_SB_REVISION_MASK) {
12686         case TG3_EEPROM_SB_REVISION_0:
12687                 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
12688                 break;
12689         case TG3_EEPROM_SB_REVISION_2:
12690                 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
12691                 break;
12692         case TG3_EEPROM_SB_REVISION_3:
12693                 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
12694                 break;
12695         default:
12696                 return;
12697         }
12698
12699         if (tg3_nvram_read(tp, offset, &val))
12700                 return;
12701
12702         build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
12703                 TG3_EEPROM_SB_EDH_BLD_SHFT;
12704         major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
12705                 TG3_EEPROM_SB_EDH_MAJ_SHFT;
12706         minor =  val & TG3_EEPROM_SB_EDH_MIN_MASK;
12707
12708         if (minor > 99 || build > 26)
12709                 return;
12710
12711         snprintf(&tp->fw_ver[2], 30, " v%d.%02d", major, minor);
12712
12713         if (build > 0) {
12714                 tp->fw_ver[8] = 'a' + build - 1;
12715                 tp->fw_ver[9] = '\0';
12716         }
12717 }
12718
12719 static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
12720 {
12721         u32 val, offset, start;
12722         int i, vlen;
12723
12724         for (offset = TG3_NVM_DIR_START;
12725              offset < TG3_NVM_DIR_END;
12726              offset += TG3_NVM_DIRENT_SIZE) {
12727                 if (tg3_nvram_read(tp, offset, &val))
12728                         return;
12729
12730                 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
12731                         break;
12732         }
12733
12734         if (offset == TG3_NVM_DIR_END)
12735                 return;
12736
12737         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
12738                 start = 0x08000000;
12739         else if (tg3_nvram_read(tp, offset - 4, &start))
12740                 return;
12741
12742         if (tg3_nvram_read(tp, offset + 4, &offset) ||
12743             !tg3_fw_img_is_valid(tp, offset) ||
12744             tg3_nvram_read(tp, offset + 8, &val))
12745                 return;
12746
12747         offset += val - start;
12748
12749         vlen = strlen(tp->fw_ver);
12750
12751         tp->fw_ver[vlen++] = ',';
12752         tp->fw_ver[vlen++] = ' ';
12753
12754         for (i = 0; i < 4; i++) {
12755                 __be32 v;
12756                 if (tg3_nvram_read_be32(tp, offset, &v))
12757                         return;
12758
12759                 offset += sizeof(v);
12760
12761                 if (vlen > TG3_VER_SIZE - sizeof(v)) {
12762                         memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
12763                         break;
12764                 }
12765
12766                 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
12767                 vlen += sizeof(v);
12768         }
12769 }
12770
12771 static void __devinit tg3_read_dash_ver(struct tg3 *tp)
12772 {
12773         int vlen;
12774         u32 apedata;
12775
12776         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) ||
12777             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
12778                 return;
12779
12780         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
12781         if (apedata != APE_SEG_SIG_MAGIC)
12782                 return;
12783
12784         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
12785         if (!(apedata & APE_FW_STATUS_READY))
12786                 return;
12787
12788         apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
12789
12790         vlen = strlen(tp->fw_ver);
12791
12792         snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " DASH v%d.%d.%d.%d",
12793                  (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
12794                  (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
12795                  (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
12796                  (apedata & APE_FW_VERSION_BLDMSK));
12797 }
12798
12799 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
12800 {
12801         u32 val;
12802
12803         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) {
12804                 tp->fw_ver[0] = 's';
12805                 tp->fw_ver[1] = 'b';
12806                 tp->fw_ver[2] = '\0';
12807
12808                 return;
12809         }
12810
12811         if (tg3_nvram_read(tp, 0, &val))
12812                 return;
12813
12814         if (val == TG3_EEPROM_MAGIC)
12815                 tg3_read_bc_ver(tp);
12816         else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
12817                 tg3_read_sb_ver(tp, val);
12818         else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
12819                 tg3_read_hwsb_ver(tp);
12820         else
12821                 return;
12822
12823         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12824              (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
12825                 return;
12826
12827         tg3_read_mgmtfw_ver(tp);
12828
12829         tp->fw_ver[TG3_VER_SIZE - 1] = 0;
12830 }
12831
12832 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
12833
12834 static int __devinit tg3_get_invariants(struct tg3 *tp)
12835 {
12836         static struct pci_device_id write_reorder_chipsets[] = {
12837                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12838                              PCI_DEVICE_ID_AMD_FE_GATE_700C) },
12839                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12840                              PCI_DEVICE_ID_AMD_8131_BRIDGE) },
12841                 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
12842                              PCI_DEVICE_ID_VIA_8385_0) },
12843                 { },
12844         };
12845         u32 misc_ctrl_reg;
12846         u32 pci_state_reg, grc_misc_cfg;
12847         u32 val;
12848         u16 pci_cmd;
12849         int err;
12850
12851         /* Force memory write invalidate off.  If we leave it on,
12852          * then on 5700_BX chips we have to enable a workaround.
12853          * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
12854          * to match the cacheline size.  The Broadcom driver have this
12855          * workaround but turns MWI off all the times so never uses
12856          * it.  This seems to suggest that the workaround is insufficient.
12857          */
12858         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12859         pci_cmd &= ~PCI_COMMAND_INVALIDATE;
12860         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12861
12862         /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
12863          * has the register indirect write enable bit set before
12864          * we try to access any of the MMIO registers.  It is also
12865          * critical that the PCI-X hw workaround situation is decided
12866          * before that as well.
12867          */
12868         pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12869                               &misc_ctrl_reg);
12870
12871         tp->pci_chip_rev_id = (misc_ctrl_reg >>
12872                                MISC_HOST_CTRL_CHIPREV_SHIFT);
12873         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
12874                 u32 prod_id_asic_rev;
12875
12876                 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
12877                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
12878                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5724)
12879                         pci_read_config_dword(tp->pdev,
12880                                               TG3PCI_GEN2_PRODID_ASICREV,
12881                                               &prod_id_asic_rev);
12882                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 ||
12883                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 ||
12884                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||
12885                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||
12886                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
12887                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
12888                         pci_read_config_dword(tp->pdev,
12889                                               TG3PCI_GEN15_PRODID_ASICREV,
12890                                               &prod_id_asic_rev);
12891                 else
12892                         pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
12893                                               &prod_id_asic_rev);
12894
12895                 tp->pci_chip_rev_id = prod_id_asic_rev;
12896         }
12897
12898         /* Wrong chip ID in 5752 A0. This code can be removed later
12899          * as A0 is not in production.
12900          */
12901         if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
12902                 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
12903
12904         /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
12905          * we need to disable memory and use config. cycles
12906          * only to access all registers. The 5702/03 chips
12907          * can mistakenly decode the special cycles from the
12908          * ICH chipsets as memory write cycles, causing corruption
12909          * of register and memory space. Only certain ICH bridges
12910          * will drive special cycles with non-zero data during the
12911          * address phase which can fall within the 5703's address
12912          * range. This is not an ICH bug as the PCI spec allows
12913          * non-zero address during special cycles. However, only
12914          * these ICH bridges are known to drive non-zero addresses
12915          * during special cycles.
12916          *
12917          * Since special cycles do not cross PCI bridges, we only
12918          * enable this workaround if the 5703 is on the secondary
12919          * bus of these ICH bridges.
12920          */
12921         if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
12922             (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
12923                 static struct tg3_dev_id {
12924                         u32     vendor;
12925                         u32     device;
12926                         u32     rev;
12927                 } ich_chipsets[] = {
12928                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
12929                           PCI_ANY_ID },
12930                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
12931                           PCI_ANY_ID },
12932                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
12933                           0xa },
12934                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
12935                           PCI_ANY_ID },
12936                         { },
12937                 };
12938                 struct tg3_dev_id *pci_id = &ich_chipsets[0];
12939                 struct pci_dev *bridge = NULL;
12940
12941                 while (pci_id->vendor != 0) {
12942                         bridge = pci_get_device(pci_id->vendor, pci_id->device,
12943                                                 bridge);
12944                         if (!bridge) {
12945                                 pci_id++;
12946                                 continue;
12947                         }
12948                         if (pci_id->rev != PCI_ANY_ID) {
12949                                 if (bridge->revision > pci_id->rev)
12950                                         continue;
12951                         }
12952                         if (bridge->subordinate &&
12953                             (bridge->subordinate->number ==
12954                              tp->pdev->bus->number)) {
12955
12956                                 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
12957                                 pci_dev_put(bridge);
12958                                 break;
12959                         }
12960                 }
12961         }
12962
12963         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
12964                 static struct tg3_dev_id {
12965                         u32     vendor;
12966                         u32     device;
12967                 } bridge_chipsets[] = {
12968                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
12969                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
12970                         { },
12971                 };
12972                 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
12973                 struct pci_dev *bridge = NULL;
12974
12975                 while (pci_id->vendor != 0) {
12976                         bridge = pci_get_device(pci_id->vendor,
12977                                                 pci_id->device,
12978                                                 bridge);
12979                         if (!bridge) {
12980                                 pci_id++;
12981                                 continue;
12982                         }
12983                         if (bridge->subordinate &&
12984                             (bridge->subordinate->number <=
12985                              tp->pdev->bus->number) &&
12986                             (bridge->subordinate->subordinate >=
12987                              tp->pdev->bus->number)) {
12988                                 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
12989                                 pci_dev_put(bridge);
12990                                 break;
12991                         }
12992                 }
12993         }
12994
12995         /* The EPB bridge inside 5714, 5715, and 5780 cannot support
12996          * DMA addresses > 40-bit. This bridge may have other additional
12997          * 57xx devices behind it in some 4-port NIC designs for example.
12998          * Any tg3 device found behind the bridge will also need the 40-bit
12999          * DMA workaround.
13000          */
13001         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
13002             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
13003                 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
13004                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
13005                 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
13006         }
13007         else {
13008                 struct pci_dev *bridge = NULL;
13009
13010                 do {
13011                         bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
13012                                                 PCI_DEVICE_ID_SERVERWORKS_EPB,
13013                                                 bridge);
13014                         if (bridge && bridge->subordinate &&
13015                             (bridge->subordinate->number <=
13016                              tp->pdev->bus->number) &&
13017                             (bridge->subordinate->subordinate >=
13018                              tp->pdev->bus->number)) {
13019                                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
13020                                 pci_dev_put(bridge);
13021                                 break;
13022                         }
13023                 } while (bridge);
13024         }
13025
13026         /* Initialize misc host control in PCI block. */
13027         tp->misc_host_ctrl |= (misc_ctrl_reg &
13028                                MISC_HOST_CTRL_CHIPREV);
13029         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13030                                tp->misc_host_ctrl);
13031
13032         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
13033             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
13034             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
13035                 tp->pdev_peer = tg3_find_peer(tp);
13036
13037         /* Intentionally exclude ASIC_REV_5906 */
13038         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13039             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13040             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13041             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13042             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13043             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13044             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13045             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13046                 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
13047
13048         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13049             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13050             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
13051             (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13052             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13053                 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
13054
13055         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
13056             (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
13057                 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
13058
13059         /* 5700 B0 chips do not support checksumming correctly due
13060          * to hardware bugs.
13061          */
13062         if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
13063                 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
13064         else {
13065                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
13066                 tp->dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
13067                 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
13068                         tp->dev->features |= NETIF_F_IPV6_CSUM;
13069         }
13070
13071         /* Determine TSO capabilities */
13072         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13073             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13074                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_3;
13075         else if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13076                  GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13077                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
13078         else if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
13079                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
13080                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 &&
13081                     tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
13082                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
13083         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13084                    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13085                    tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
13086                 tp->tg3_flags2 |= TG3_FLG2_TSO_BUG;
13087                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
13088                         tp->fw_needed = FIRMWARE_TG3TSO5;
13089                 else
13090                         tp->fw_needed = FIRMWARE_TG3TSO;
13091         }
13092
13093         tp->irq_max = 1;
13094
13095         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
13096                 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
13097                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
13098                     GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
13099                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
13100                      tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
13101                      tp->pdev_peer == tp->pdev))
13102                         tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
13103
13104                 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13105                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13106                         tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
13107                 }
13108
13109                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13110                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
13111                         tp->tg3_flags |= TG3_FLAG_SUPPORT_MSIX;
13112                         tp->irq_max = TG3_IRQ_MAX_VECS;
13113                 }
13114         }
13115
13116         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13117             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13118                 tp->tg3_flags3 |= TG3_FLG3_SHORT_DMA_BUG;
13119         else if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS)) {
13120                 tp->tg3_flags3 |= TG3_FLG3_4G_DMA_BNDRY_BUG;
13121                 tp->tg3_flags3 |= TG3_FLG3_40BIT_DMA_LIMIT_BUG;
13122         }
13123
13124         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13125             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13126                 tp->tg3_flags3 |= TG3_FLG3_USE_JUMBO_BDFLAG;
13127
13128         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
13129              (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
13130                  (tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG))
13131                 tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE;
13132
13133         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13134                               &pci_state_reg);
13135
13136         tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
13137         if (tp->pcie_cap != 0) {
13138                 u16 lnkctl;
13139
13140                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
13141
13142                 pcie_set_readrq(tp->pdev, 4096);
13143
13144                 pci_read_config_word(tp->pdev,
13145                                      tp->pcie_cap + PCI_EXP_LNKCTL,
13146                                      &lnkctl);
13147                 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
13148                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13149                                 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
13150                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13151                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13152                             tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
13153                             tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
13154                                 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
13155                 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5717_A0) {
13156                         tp->tg3_flags3 |= TG3_FLG3_L1PLLPD_EN;
13157                 }
13158         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
13159                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
13160         } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
13161                    (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13162                 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
13163                 if (!tp->pcix_cap) {
13164                         printk(KERN_ERR PFX "Cannot find PCI-X "
13165                                             "capability, aborting.\n");
13166                         return -EIO;
13167                 }
13168
13169                 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
13170                         tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
13171         }
13172
13173         /* If we have an AMD 762 or VIA K8T800 chipset, write
13174          * reordering to the mailbox registers done by the host
13175          * controller can cause major troubles.  We read back from
13176          * every mailbox register write to force the writes to be
13177          * posted to the chip in order.
13178          */
13179         if (pci_dev_present(write_reorder_chipsets) &&
13180             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13181                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
13182
13183         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
13184                              &tp->pci_cacheline_sz);
13185         pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13186                              &tp->pci_lat_timer);
13187         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13188             tp->pci_lat_timer < 64) {
13189                 tp->pci_lat_timer = 64;
13190                 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13191                                       tp->pci_lat_timer);
13192         }
13193
13194         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
13195                 /* 5700 BX chips need to have their TX producer index
13196                  * mailboxes written twice to workaround a bug.
13197                  */
13198                 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
13199
13200                 /* If we are in PCI-X mode, enable register write workaround.
13201                  *
13202                  * The workaround is to use indirect register accesses
13203                  * for all chip writes not to mailbox registers.
13204                  */
13205                 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
13206                         u32 pm_reg;
13207
13208                         tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13209
13210                         /* The chip can have it's power management PCI config
13211                          * space registers clobbered due to this bug.
13212                          * So explicitly force the chip into D0 here.
13213                          */
13214                         pci_read_config_dword(tp->pdev,
13215                                               tp->pm_cap + PCI_PM_CTRL,
13216                                               &pm_reg);
13217                         pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
13218                         pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
13219                         pci_write_config_dword(tp->pdev,
13220                                                tp->pm_cap + PCI_PM_CTRL,
13221                                                pm_reg);
13222
13223                         /* Also, force SERR#/PERR# in PCI command. */
13224                         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13225                         pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
13226                         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13227                 }
13228         }
13229
13230         if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
13231                 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
13232         if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
13233                 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
13234
13235         /* Chip-specific fixup from Broadcom driver */
13236         if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
13237             (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
13238                 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
13239                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
13240         }
13241
13242         /* Default fast path register access methods */
13243         tp->read32 = tg3_read32;
13244         tp->write32 = tg3_write32;
13245         tp->read32_mbox = tg3_read32;
13246         tp->write32_mbox = tg3_write32;
13247         tp->write32_tx_mbox = tg3_write32;
13248         tp->write32_rx_mbox = tg3_write32;
13249
13250         /* Various workaround register access methods */
13251         if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
13252                 tp->write32 = tg3_write_indirect_reg32;
13253         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
13254                  ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
13255                   tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
13256                 /*
13257                  * Back to back register writes can cause problems on these
13258                  * chips, the workaround is to read back all reg writes
13259                  * except those to mailbox regs.
13260                  *
13261                  * See tg3_write_indirect_reg32().
13262                  */
13263                 tp->write32 = tg3_write_flush_reg32;
13264         }
13265
13266         if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
13267             (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
13268                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
13269                 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
13270                         tp->write32_rx_mbox = tg3_write_flush_reg32;
13271         }
13272
13273         if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
13274                 tp->read32 = tg3_read_indirect_reg32;
13275                 tp->write32 = tg3_write_indirect_reg32;
13276                 tp->read32_mbox = tg3_read_indirect_mbox;
13277                 tp->write32_mbox = tg3_write_indirect_mbox;
13278                 tp->write32_tx_mbox = tg3_write_indirect_mbox;
13279                 tp->write32_rx_mbox = tg3_write_indirect_mbox;
13280
13281                 iounmap(tp->regs);
13282                 tp->regs = NULL;
13283
13284                 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13285                 pci_cmd &= ~PCI_COMMAND_MEMORY;
13286                 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13287         }
13288         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13289                 tp->read32_mbox = tg3_read32_mbox_5906;
13290                 tp->write32_mbox = tg3_write32_mbox_5906;
13291                 tp->write32_tx_mbox = tg3_write32_mbox_5906;
13292                 tp->write32_rx_mbox = tg3_write32_mbox_5906;
13293         }
13294
13295         if (tp->write32 == tg3_write_indirect_reg32 ||
13296             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13297              (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13298               GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
13299                 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
13300
13301         /* Get eeprom hw config before calling tg3_set_power_state().
13302          * In particular, the TG3_FLG2_IS_NIC flag must be
13303          * determined before calling tg3_set_power_state() so that
13304          * we know whether or not to switch out of Vaux power.
13305          * When the flag is set, it means that GPIO1 is used for eeprom
13306          * write protect and also implies that it is a LOM where GPIOs
13307          * are not used to switch power.
13308          */
13309         tg3_get_eeprom_hw_cfg(tp);
13310
13311         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
13312                 /* Allow reads and writes to the
13313                  * APE register and memory space.
13314                  */
13315                 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
13316                                  PCISTATE_ALLOW_APE_SHMEM_WR;
13317                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
13318                                        pci_state_reg);
13319         }
13320
13321         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13322             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13323             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13324             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13325             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13326             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13327                 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
13328
13329         /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
13330          * GPIO1 driven high will bring 5700's external PHY out of reset.
13331          * It is also used as eeprom write protect on LOMs.
13332          */
13333         tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
13334         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13335             (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
13336                 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
13337                                        GRC_LCLCTRL_GPIO_OUTPUT1);
13338         /* Unused GPIO3 must be driven as output on 5752 because there
13339          * are no pull-up resistors on unused GPIO pins.
13340          */
13341         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
13342                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
13343
13344         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13345             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13346             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13347                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13348
13349         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
13350             tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
13351                 /* Turn off the debug UART. */
13352                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13353                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
13354                         /* Keep VMain power. */
13355                         tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
13356                                               GRC_LCLCTRL_GPIO_OUTPUT0;
13357         }
13358
13359         /* Force the chip into D0. */
13360         err = tg3_set_power_state(tp, PCI_D0);
13361         if (err) {
13362                 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
13363                        pci_name(tp->pdev));
13364                 return err;
13365         }
13366
13367         /* Derive initial jumbo mode from MTU assigned in
13368          * ether_setup() via the alloc_etherdev() call
13369          */
13370         if (tp->dev->mtu > ETH_DATA_LEN &&
13371             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13372                 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
13373
13374         /* Determine WakeOnLan speed to use. */
13375         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13376             tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
13377             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
13378             tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
13379                 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
13380         } else {
13381                 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
13382         }
13383
13384         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13385                 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
13386
13387         /* A few boards don't want Ethernet@WireSpeed phy feature */
13388         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13389             ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
13390              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
13391              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
13392             (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) ||
13393             (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
13394                 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
13395
13396         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
13397             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
13398                 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
13399         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
13400                 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
13401
13402         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
13403             !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
13404             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
13405             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 &&
13406             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
13407             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765) {
13408                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13409                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13410                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13411                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
13412                         if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
13413                             tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
13414                                 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
13415                         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
13416                                 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
13417                 } else
13418                         tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
13419         }
13420
13421         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13422             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
13423                 tp->phy_otp = tg3_read_otp_phycfg(tp);
13424                 if (tp->phy_otp == 0)
13425                         tp->phy_otp = TG3_OTP_DEFAULT;
13426         }
13427
13428         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
13429                 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
13430         else
13431                 tp->mi_mode = MAC_MI_MODE_BASE;
13432
13433         tp->coalesce_mode = 0;
13434         if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
13435             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
13436                 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
13437
13438         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13439             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
13440                 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
13441
13442         err = tg3_mdio_init(tp);
13443         if (err)
13444                 return err;
13445
13446         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
13447             (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0 ||
13448                  (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
13449                 return -ENOTSUPP;
13450
13451         /* Initialize data/descriptor byte/word swapping. */
13452         val = tr32(GRC_MODE);
13453         val &= GRC_MODE_HOST_STACKUP;
13454         tw32(GRC_MODE, val | tp->grc_mode);
13455
13456         tg3_switch_clocks(tp);
13457
13458         /* Clear this out for sanity. */
13459         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
13460
13461         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13462                               &pci_state_reg);
13463         if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
13464             (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
13465                 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
13466
13467                 if (chiprevid == CHIPREV_ID_5701_A0 ||
13468                     chiprevid == CHIPREV_ID_5701_B0 ||
13469                     chiprevid == CHIPREV_ID_5701_B2 ||
13470                     chiprevid == CHIPREV_ID_5701_B5) {
13471                         void __iomem *sram_base;
13472
13473                         /* Write some dummy words into the SRAM status block
13474                          * area, see if it reads back correctly.  If the return
13475                          * value is bad, force enable the PCIX workaround.
13476                          */
13477                         sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
13478
13479                         writel(0x00000000, sram_base);
13480                         writel(0x00000000, sram_base + 4);
13481                         writel(0xffffffff, sram_base + 4);
13482                         if (readl(sram_base) != 0x00000000)
13483                                 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13484                 }
13485         }
13486
13487         udelay(50);
13488         tg3_nvram_init(tp);
13489
13490         grc_misc_cfg = tr32(GRC_MISC_CFG);
13491         grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
13492
13493         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13494             (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
13495              grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
13496                 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
13497
13498         if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
13499             (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
13500                 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
13501         if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
13502                 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
13503                                       HOSTCC_MODE_CLRTICK_TXBD);
13504
13505                 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
13506                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13507                                        tp->misc_host_ctrl);
13508         }
13509
13510         /* Preserve the APE MAC_MODE bits */
13511         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
13512                 tp->mac_mode = tr32(MAC_MODE) |
13513                                MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
13514         else
13515                 tp->mac_mode = TG3_DEF_MAC_MODE;
13516
13517         /* these are limited to 10/100 only */
13518         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13519              (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
13520             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13521              tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13522              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
13523               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
13524               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
13525             (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13526              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
13527               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
13528               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
13529             tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
13530             (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
13531                 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
13532
13533         err = tg3_phy_probe(tp);
13534         if (err) {
13535                 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
13536                        pci_name(tp->pdev), err);
13537                 /* ... but do not return immediately ... */
13538                 tg3_mdio_fini(tp);
13539         }
13540
13541         tg3_read_partno(tp);
13542         tg3_read_fw_ver(tp);
13543
13544         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
13545                 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
13546         } else {
13547                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13548                         tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
13549                 else
13550                         tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
13551         }
13552
13553         /* 5700 {AX,BX} chips have a broken status block link
13554          * change bit implementation, so we must use the
13555          * status register in those cases.
13556          */
13557         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13558                 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
13559         else
13560                 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
13561
13562         /* The led_ctrl is set during tg3_phy_probe, here we might
13563          * have to force the link status polling mechanism based
13564          * upon subsystem IDs.
13565          */
13566         if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
13567             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13568             !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
13569                 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
13570                                   TG3_FLAG_USE_LINKCHG_REG);
13571         }
13572
13573         /* For all SERDES we poll the MAC status register. */
13574         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
13575                 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
13576         else
13577                 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
13578
13579         tp->rx_offset = NET_IP_ALIGN;
13580         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13581             (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
13582                 tp->rx_offset = 0;
13583
13584         tp->rx_std_max_post = TG3_RX_RING_SIZE;
13585
13586         /* Increment the rx prod index on the rx std ring by at most
13587          * 8 for these chips to workaround hw errata.
13588          */
13589         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13590             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13591             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
13592                 tp->rx_std_max_post = 8;
13593
13594         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
13595                 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
13596                                      PCIE_PWR_MGMT_L1_THRESH_MSK;
13597
13598         return err;
13599 }
13600
13601 #ifdef CONFIG_SPARC
13602 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
13603 {
13604         struct net_device *dev = tp->dev;
13605         struct pci_dev *pdev = tp->pdev;
13606         struct device_node *dp = pci_device_to_OF_node(pdev);
13607         const unsigned char *addr;
13608         int len;
13609
13610         addr = of_get_property(dp, "local-mac-address", &len);
13611         if (addr && len == 6) {
13612                 memcpy(dev->dev_addr, addr, 6);
13613                 memcpy(dev->perm_addr, dev->dev_addr, 6);
13614                 return 0;
13615         }
13616         return -ENODEV;
13617 }
13618
13619 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
13620 {
13621         struct net_device *dev = tp->dev;
13622
13623         memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
13624         memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
13625         return 0;
13626 }
13627 #endif
13628
13629 static int __devinit tg3_get_device_address(struct tg3 *tp)
13630 {
13631         struct net_device *dev = tp->dev;
13632         u32 hi, lo, mac_offset;
13633         int addr_ok = 0;
13634
13635 #ifdef CONFIG_SPARC
13636         if (!tg3_get_macaddr_sparc(tp))
13637                 return 0;
13638 #endif
13639
13640         mac_offset = 0x7c;
13641         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
13642             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13643                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
13644                         mac_offset = 0xcc;
13645                 if (tg3_nvram_lock(tp))
13646                         tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
13647                 else
13648                         tg3_nvram_unlock(tp);
13649         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
13650                 if (tr32(TG3_CPMU_STATUS) & TG3_CPMU_STATUS_PCIE_FUNC)
13651                         mac_offset = 0xcc;
13652         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13653                 mac_offset = 0x10;
13654
13655         /* First try to get it from MAC address mailbox. */
13656         tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
13657         if ((hi >> 16) == 0x484b) {
13658                 dev->dev_addr[0] = (hi >>  8) & 0xff;
13659                 dev->dev_addr[1] = (hi >>  0) & 0xff;
13660
13661                 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
13662                 dev->dev_addr[2] = (lo >> 24) & 0xff;
13663                 dev->dev_addr[3] = (lo >> 16) & 0xff;
13664                 dev->dev_addr[4] = (lo >>  8) & 0xff;
13665                 dev->dev_addr[5] = (lo >>  0) & 0xff;
13666
13667                 /* Some old bootcode may report a 0 MAC address in SRAM */
13668                 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
13669         }
13670         if (!addr_ok) {
13671                 /* Next, try NVRAM. */
13672                 if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) &&
13673                     !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
13674                     !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
13675                         memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
13676                         memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
13677                 }
13678                 /* Finally just fetch it out of the MAC control regs. */
13679                 else {
13680                         hi = tr32(MAC_ADDR_0_HIGH);
13681                         lo = tr32(MAC_ADDR_0_LOW);
13682
13683                         dev->dev_addr[5] = lo & 0xff;
13684                         dev->dev_addr[4] = (lo >> 8) & 0xff;
13685                         dev->dev_addr[3] = (lo >> 16) & 0xff;
13686                         dev->dev_addr[2] = (lo >> 24) & 0xff;
13687                         dev->dev_addr[1] = hi & 0xff;
13688                         dev->dev_addr[0] = (hi >> 8) & 0xff;
13689                 }
13690         }
13691
13692         if (!is_valid_ether_addr(&dev->dev_addr[0])) {
13693 #ifdef CONFIG_SPARC
13694                 if (!tg3_get_default_macaddr_sparc(tp))
13695                         return 0;
13696 #endif
13697                 return -EINVAL;
13698         }
13699         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
13700         return 0;
13701 }
13702
13703 #define BOUNDARY_SINGLE_CACHELINE       1
13704 #define BOUNDARY_MULTI_CACHELINE        2
13705
13706 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
13707 {
13708         int cacheline_size;
13709         u8 byte;
13710         int goal;
13711
13712         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
13713         if (byte == 0)
13714                 cacheline_size = 1024;
13715         else
13716                 cacheline_size = (int) byte * 4;
13717
13718         /* On 5703 and later chips, the boundary bits have no
13719          * effect.
13720          */
13721         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13722             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13723             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13724                 goto out;
13725
13726 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
13727         goal = BOUNDARY_MULTI_CACHELINE;
13728 #else
13729 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
13730         goal = BOUNDARY_SINGLE_CACHELINE;
13731 #else
13732         goal = 0;
13733 #endif
13734 #endif
13735
13736         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13737             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
13738                 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
13739                 goto out;
13740         }
13741
13742         if (!goal)
13743                 goto out;
13744
13745         /* PCI controllers on most RISC systems tend to disconnect
13746          * when a device tries to burst across a cache-line boundary.
13747          * Therefore, letting tg3 do so just wastes PCI bandwidth.
13748          *
13749          * Unfortunately, for PCI-E there are only limited
13750          * write-side controls for this, and thus for reads
13751          * we will still get the disconnects.  We'll also waste
13752          * these PCI cycles for both read and write for chips
13753          * other than 5700 and 5701 which do not implement the
13754          * boundary bits.
13755          */
13756         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13757             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
13758                 switch (cacheline_size) {
13759                 case 16:
13760                 case 32:
13761                 case 64:
13762                 case 128:
13763                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13764                                 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
13765                                         DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
13766                         } else {
13767                                 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13768                                         DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13769                         }
13770                         break;
13771
13772                 case 256:
13773                         val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
13774                                 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
13775                         break;
13776
13777                 default:
13778                         val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13779                                 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13780                         break;
13781                 }
13782         } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13783                 switch (cacheline_size) {
13784                 case 16:
13785                 case 32:
13786                 case 64:
13787                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13788                                 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13789                                 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
13790                                 break;
13791                         }
13792                         /* fallthrough */
13793                 case 128:
13794                 default:
13795                         val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13796                         val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
13797                         break;
13798                 }
13799         } else {
13800                 switch (cacheline_size) {
13801                 case 16:
13802                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13803                                 val |= (DMA_RWCTRL_READ_BNDRY_16 |
13804                                         DMA_RWCTRL_WRITE_BNDRY_16);
13805                                 break;
13806                         }
13807                         /* fallthrough */
13808                 case 32:
13809                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13810                                 val |= (DMA_RWCTRL_READ_BNDRY_32 |
13811                                         DMA_RWCTRL_WRITE_BNDRY_32);
13812                                 break;
13813                         }
13814                         /* fallthrough */
13815                 case 64:
13816                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13817                                 val |= (DMA_RWCTRL_READ_BNDRY_64 |
13818                                         DMA_RWCTRL_WRITE_BNDRY_64);
13819                                 break;
13820                         }
13821                         /* fallthrough */
13822                 case 128:
13823                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13824                                 val |= (DMA_RWCTRL_READ_BNDRY_128 |
13825                                         DMA_RWCTRL_WRITE_BNDRY_128);
13826                                 break;
13827                         }
13828                         /* fallthrough */
13829                 case 256:
13830                         val |= (DMA_RWCTRL_READ_BNDRY_256 |
13831                                 DMA_RWCTRL_WRITE_BNDRY_256);
13832                         break;
13833                 case 512:
13834                         val |= (DMA_RWCTRL_READ_BNDRY_512 |
13835                                 DMA_RWCTRL_WRITE_BNDRY_512);
13836                         break;
13837                 case 1024:
13838                 default:
13839                         val |= (DMA_RWCTRL_READ_BNDRY_1024 |
13840                                 DMA_RWCTRL_WRITE_BNDRY_1024);
13841                         break;
13842                 }
13843         }
13844
13845 out:
13846         return val;
13847 }
13848
13849 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
13850 {
13851         struct tg3_internal_buffer_desc test_desc;
13852         u32 sram_dma_descs;
13853         int i, ret;
13854
13855         sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
13856
13857         tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
13858         tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
13859         tw32(RDMAC_STATUS, 0);
13860         tw32(WDMAC_STATUS, 0);
13861
13862         tw32(BUFMGR_MODE, 0);
13863         tw32(FTQ_RESET, 0);
13864
13865         test_desc.addr_hi = ((u64) buf_dma) >> 32;
13866         test_desc.addr_lo = buf_dma & 0xffffffff;
13867         test_desc.nic_mbuf = 0x00002100;
13868         test_desc.len = size;
13869
13870         /*
13871          * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
13872          * the *second* time the tg3 driver was getting loaded after an
13873          * initial scan.
13874          *
13875          * Broadcom tells me:
13876          *   ...the DMA engine is connected to the GRC block and a DMA
13877          *   reset may affect the GRC block in some unpredictable way...
13878          *   The behavior of resets to individual blocks has not been tested.
13879          *
13880          * Broadcom noted the GRC reset will also reset all sub-components.
13881          */
13882         if (to_device) {
13883                 test_desc.cqid_sqid = (13 << 8) | 2;
13884
13885                 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
13886                 udelay(40);
13887         } else {
13888                 test_desc.cqid_sqid = (16 << 8) | 7;
13889
13890                 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
13891                 udelay(40);
13892         }
13893         test_desc.flags = 0x00000005;
13894
13895         for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
13896                 u32 val;
13897
13898                 val = *(((u32 *)&test_desc) + i);
13899                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
13900                                        sram_dma_descs + (i * sizeof(u32)));
13901                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
13902         }
13903         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
13904
13905         if (to_device) {
13906                 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
13907         } else {
13908                 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
13909         }
13910
13911         ret = -ENODEV;
13912         for (i = 0; i < 40; i++) {
13913                 u32 val;
13914
13915                 if (to_device)
13916                         val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
13917                 else
13918                         val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
13919                 if ((val & 0xffff) == sram_dma_descs) {
13920                         ret = 0;
13921                         break;
13922                 }
13923
13924                 udelay(100);
13925         }
13926
13927         return ret;
13928 }
13929
13930 #define TEST_BUFFER_SIZE        0x2000
13931
13932 static int __devinit tg3_test_dma(struct tg3 *tp)
13933 {
13934         dma_addr_t buf_dma;
13935         u32 *buf, saved_dma_rwctrl;
13936         int ret = 0;
13937
13938         buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
13939         if (!buf) {
13940                 ret = -ENOMEM;
13941                 goto out_nofree;
13942         }
13943
13944         tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
13945                           (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
13946
13947         tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
13948
13949         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13950             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13951                 goto out;
13952
13953         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13954                 /* DMA read watermark not used on PCIE */
13955                 tp->dma_rwctrl |= 0x00180000;
13956         } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
13957                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
13958                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
13959                         tp->dma_rwctrl |= 0x003f0000;
13960                 else
13961                         tp->dma_rwctrl |= 0x003f000f;
13962         } else {
13963                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13964                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
13965                         u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
13966                         u32 read_water = 0x7;
13967
13968                         /* If the 5704 is behind the EPB bridge, we can
13969                          * do the less restrictive ONE_DMA workaround for
13970                          * better performance.
13971                          */
13972                         if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
13973                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13974                                 tp->dma_rwctrl |= 0x8000;
13975                         else if (ccval == 0x6 || ccval == 0x7)
13976                                 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
13977
13978                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
13979                                 read_water = 4;
13980                         /* Set bit 23 to enable PCIX hw bug fix */
13981                         tp->dma_rwctrl |=
13982                                 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
13983                                 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
13984                                 (1 << 23);
13985                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
13986                         /* 5780 always in PCIX mode */
13987                         tp->dma_rwctrl |= 0x00144000;
13988                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
13989                         /* 5714 always in PCIX mode */
13990                         tp->dma_rwctrl |= 0x00148000;
13991                 } else {
13992                         tp->dma_rwctrl |= 0x001b000f;
13993                 }
13994         }
13995
13996         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13997             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13998                 tp->dma_rwctrl &= 0xfffffff0;
13999
14000         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
14001             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
14002                 /* Remove this if it causes problems for some boards. */
14003                 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
14004
14005                 /* On 5700/5701 chips, we need to set this bit.
14006                  * Otherwise the chip will issue cacheline transactions
14007                  * to streamable DMA memory with not all the byte
14008                  * enables turned on.  This is an error on several
14009                  * RISC PCI controllers, in particular sparc64.
14010                  *
14011                  * On 5703/5704 chips, this bit has been reassigned
14012                  * a different meaning.  In particular, it is used
14013                  * on those chips to enable a PCI-X workaround.
14014                  */
14015                 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
14016         }
14017
14018         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14019
14020 #if 0
14021         /* Unneeded, already done by tg3_get_invariants.  */
14022         tg3_switch_clocks(tp);
14023 #endif
14024
14025         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
14026             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
14027                 goto out;
14028
14029         /* It is best to perform DMA test with maximum write burst size
14030          * to expose the 5700/5701 write DMA bug.
14031          */
14032         saved_dma_rwctrl = tp->dma_rwctrl;
14033         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14034         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14035
14036         while (1) {
14037                 u32 *p = buf, i;
14038
14039                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
14040                         p[i] = i;
14041
14042                 /* Send the buffer to the chip. */
14043                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
14044                 if (ret) {
14045                         printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
14046                         break;
14047                 }
14048
14049 #if 0
14050                 /* validate data reached card RAM correctly. */
14051                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14052                         u32 val;
14053                         tg3_read_mem(tp, 0x2100 + (i*4), &val);
14054                         if (le32_to_cpu(val) != p[i]) {
14055                                 printk(KERN_ERR "  tg3_test_dma()  Card buffer corrupted on write! (%d != %d)\n", val, i);
14056                                 /* ret = -ENODEV here? */
14057                         }
14058                         p[i] = 0;
14059                 }
14060 #endif
14061                 /* Now read it back. */
14062                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
14063                 if (ret) {
14064                         printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
14065
14066                         break;
14067                 }
14068
14069                 /* Verify it. */
14070                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14071                         if (p[i] == i)
14072                                 continue;
14073
14074                         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14075                             DMA_RWCTRL_WRITE_BNDRY_16) {
14076                                 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14077                                 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14078                                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14079                                 break;
14080                         } else {
14081                                 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
14082                                 ret = -ENODEV;
14083                                 goto out;
14084                         }
14085                 }
14086
14087                 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
14088                         /* Success. */
14089                         ret = 0;
14090                         break;
14091                 }
14092         }
14093         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14094             DMA_RWCTRL_WRITE_BNDRY_16) {
14095                 static struct pci_device_id dma_wait_state_chipsets[] = {
14096                         { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
14097                                      PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
14098                         { },
14099                 };
14100
14101                 /* DMA test passed without adjusting DMA boundary,
14102                  * now look for chipsets that are known to expose the
14103                  * DMA bug without failing the test.
14104                  */
14105                 if (pci_dev_present(dma_wait_state_chipsets)) {
14106                         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14107                         tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14108                 }
14109                 else
14110                         /* Safe to use the calculated DMA boundary. */
14111                         tp->dma_rwctrl = saved_dma_rwctrl;
14112
14113                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14114         }
14115
14116 out:
14117         pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
14118 out_nofree:
14119         return ret;
14120 }
14121
14122 static void __devinit tg3_init_link_config(struct tg3 *tp)
14123 {
14124         tp->link_config.advertising =
14125                 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
14126                  ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
14127                  ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
14128                  ADVERTISED_Autoneg | ADVERTISED_MII);
14129         tp->link_config.speed = SPEED_INVALID;
14130         tp->link_config.duplex = DUPLEX_INVALID;
14131         tp->link_config.autoneg = AUTONEG_ENABLE;
14132         tp->link_config.active_speed = SPEED_INVALID;
14133         tp->link_config.active_duplex = DUPLEX_INVALID;
14134         tp->link_config.phy_is_low_power = 0;
14135         tp->link_config.orig_speed = SPEED_INVALID;
14136         tp->link_config.orig_duplex = DUPLEX_INVALID;
14137         tp->link_config.orig_autoneg = AUTONEG_INVALID;
14138 }
14139
14140 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
14141 {
14142         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
14143             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
14144                 tp->bufmgr_config.mbuf_read_dma_low_water =
14145                         DEFAULT_MB_RDMA_LOW_WATER_5705;
14146                 tp->bufmgr_config.mbuf_mac_rx_low_water =
14147                         DEFAULT_MB_MACRX_LOW_WATER_57765;
14148                 tp->bufmgr_config.mbuf_high_water =
14149                         DEFAULT_MB_HIGH_WATER_57765;
14150
14151                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14152                         DEFAULT_MB_RDMA_LOW_WATER_5705;
14153                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14154                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765;
14155                 tp->bufmgr_config.mbuf_high_water_jumbo =
14156                         DEFAULT_MB_HIGH_WATER_JUMBO_57765;
14157         } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
14158                 tp->bufmgr_config.mbuf_read_dma_low_water =
14159                         DEFAULT_MB_RDMA_LOW_WATER_5705;
14160                 tp->bufmgr_config.mbuf_mac_rx_low_water =
14161                         DEFAULT_MB_MACRX_LOW_WATER_5705;
14162                 tp->bufmgr_config.mbuf_high_water =
14163                         DEFAULT_MB_HIGH_WATER_5705;
14164                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
14165                         tp->bufmgr_config.mbuf_mac_rx_low_water =
14166                                 DEFAULT_MB_MACRX_LOW_WATER_5906;
14167                         tp->bufmgr_config.mbuf_high_water =
14168                                 DEFAULT_MB_HIGH_WATER_5906;
14169                 }
14170
14171                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14172                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
14173                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14174                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
14175                 tp->bufmgr_config.mbuf_high_water_jumbo =
14176                         DEFAULT_MB_HIGH_WATER_JUMBO_5780;
14177         } else {
14178                 tp->bufmgr_config.mbuf_read_dma_low_water =
14179                         DEFAULT_MB_RDMA_LOW_WATER;
14180                 tp->bufmgr_config.mbuf_mac_rx_low_water =
14181                         DEFAULT_MB_MACRX_LOW_WATER;
14182                 tp->bufmgr_config.mbuf_high_water =
14183                         DEFAULT_MB_HIGH_WATER;
14184
14185                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14186                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
14187                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14188                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
14189                 tp->bufmgr_config.mbuf_high_water_jumbo =
14190                         DEFAULT_MB_HIGH_WATER_JUMBO;
14191         }
14192
14193         tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
14194         tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
14195 }
14196
14197 static char * __devinit tg3_phy_string(struct tg3 *tp)
14198 {
14199         switch (tp->phy_id & PHY_ID_MASK) {
14200         case PHY_ID_BCM5400:    return "5400";
14201         case PHY_ID_BCM5401:    return "5401";
14202         case PHY_ID_BCM5411:    return "5411";
14203         case PHY_ID_BCM5701:    return "5701";
14204         case PHY_ID_BCM5703:    return "5703";
14205         case PHY_ID_BCM5704:    return "5704";
14206         case PHY_ID_BCM5705:    return "5705";
14207         case PHY_ID_BCM5750:    return "5750";
14208         case PHY_ID_BCM5752:    return "5752";
14209         case PHY_ID_BCM5714:    return "5714";
14210         case PHY_ID_BCM5780:    return "5780";
14211         case PHY_ID_BCM5755:    return "5755";
14212         case PHY_ID_BCM5787:    return "5787";
14213         case PHY_ID_BCM5784:    return "5784";
14214         case PHY_ID_BCM5756:    return "5722/5756";
14215         case PHY_ID_BCM5906:    return "5906";
14216         case PHY_ID_BCM5761:    return "5761";
14217         case PHY_ID_BCM5718C:   return "5718C";
14218         case PHY_ID_BCM5718S:   return "5718S";
14219         case PHY_ID_BCM57765:   return "57765";
14220         case PHY_ID_BCM8002:    return "8002/serdes";
14221         case 0:                 return "serdes";
14222         default:                return "unknown";
14223         }
14224 }
14225
14226 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
14227 {
14228         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
14229                 strcpy(str, "PCI Express");
14230                 return str;
14231         } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
14232                 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
14233
14234                 strcpy(str, "PCIX:");
14235
14236                 if ((clock_ctrl == 7) ||
14237                     ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
14238                      GRC_MISC_CFG_BOARD_ID_5704CIOBE))
14239                         strcat(str, "133MHz");
14240                 else if (clock_ctrl == 0)
14241                         strcat(str, "33MHz");
14242                 else if (clock_ctrl == 2)
14243                         strcat(str, "50MHz");
14244                 else if (clock_ctrl == 4)
14245                         strcat(str, "66MHz");
14246                 else if (clock_ctrl == 6)
14247                         strcat(str, "100MHz");
14248         } else {
14249                 strcpy(str, "PCI:");
14250                 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
14251                         strcat(str, "66MHz");
14252                 else
14253                         strcat(str, "33MHz");
14254         }
14255         if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
14256                 strcat(str, ":32-bit");
14257         else
14258                 strcat(str, ":64-bit");
14259         return str;
14260 }
14261
14262 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
14263 {
14264         struct pci_dev *peer;
14265         unsigned int func, devnr = tp->pdev->devfn & ~7;
14266
14267         for (func = 0; func < 8; func++) {
14268                 peer = pci_get_slot(tp->pdev->bus, devnr | func);
14269                 if (peer && peer != tp->pdev)
14270                         break;
14271                 pci_dev_put(peer);
14272         }
14273         /* 5704 can be configured in single-port mode, set peer to
14274          * tp->pdev in that case.
14275          */
14276         if (!peer) {
14277                 peer = tp->pdev;
14278                 return peer;
14279         }
14280
14281         /*
14282          * We don't need to keep the refcount elevated; there's no way
14283          * to remove one half of this device without removing the other
14284          */
14285         pci_dev_put(peer);
14286
14287         return peer;
14288 }
14289
14290 static void __devinit tg3_init_coal(struct tg3 *tp)
14291 {
14292         struct ethtool_coalesce *ec = &tp->coal;
14293
14294         memset(ec, 0, sizeof(*ec));
14295         ec->cmd = ETHTOOL_GCOALESCE;
14296         ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
14297         ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
14298         ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
14299         ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
14300         ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
14301         ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
14302         ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
14303         ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
14304         ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
14305
14306         if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
14307                                  HOSTCC_MODE_CLRTICK_TXBD)) {
14308                 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
14309                 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
14310                 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
14311                 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
14312         }
14313
14314         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
14315                 ec->rx_coalesce_usecs_irq = 0;
14316                 ec->tx_coalesce_usecs_irq = 0;
14317                 ec->stats_block_coalesce_usecs = 0;
14318         }
14319 }
14320
14321 static const struct net_device_ops tg3_netdev_ops = {
14322         .ndo_open               = tg3_open,
14323         .ndo_stop               = tg3_close,
14324         .ndo_start_xmit         = tg3_start_xmit,
14325         .ndo_get_stats          = tg3_get_stats,
14326         .ndo_validate_addr      = eth_validate_addr,
14327         .ndo_set_multicast_list = tg3_set_rx_mode,
14328         .ndo_set_mac_address    = tg3_set_mac_addr,
14329         .ndo_do_ioctl           = tg3_ioctl,
14330         .ndo_tx_timeout         = tg3_tx_timeout,
14331         .ndo_change_mtu         = tg3_change_mtu,
14332 #if TG3_VLAN_TAG_USED
14333         .ndo_vlan_rx_register   = tg3_vlan_rx_register,
14334 #endif
14335 #ifdef CONFIG_NET_POLL_CONTROLLER
14336         .ndo_poll_controller    = tg3_poll_controller,
14337 #endif
14338 };
14339
14340 static const struct net_device_ops tg3_netdev_ops_dma_bug = {
14341         .ndo_open               = tg3_open,
14342         .ndo_stop               = tg3_close,
14343         .ndo_start_xmit         = tg3_start_xmit_dma_bug,
14344         .ndo_get_stats          = tg3_get_stats,
14345         .ndo_validate_addr      = eth_validate_addr,
14346         .ndo_set_multicast_list = tg3_set_rx_mode,
14347         .ndo_set_mac_address    = tg3_set_mac_addr,
14348         .ndo_do_ioctl           = tg3_ioctl,
14349         .ndo_tx_timeout         = tg3_tx_timeout,
14350         .ndo_change_mtu         = tg3_change_mtu,
14351 #if TG3_VLAN_TAG_USED
14352         .ndo_vlan_rx_register   = tg3_vlan_rx_register,
14353 #endif
14354 #ifdef CONFIG_NET_POLL_CONTROLLER
14355         .ndo_poll_controller    = tg3_poll_controller,
14356 #endif
14357 };
14358
14359 static int __devinit tg3_init_one(struct pci_dev *pdev,
14360                                   const struct pci_device_id *ent)
14361 {
14362         static int tg3_version_printed = 0;
14363         struct net_device *dev;
14364         struct tg3 *tp;
14365         int i, err, pm_cap;
14366         u32 sndmbx, rcvmbx, intmbx;
14367         char str[40];
14368         u64 dma_mask, persist_dma_mask;
14369
14370         if (tg3_version_printed++ == 0)
14371                 printk(KERN_INFO "%s", version);
14372
14373         err = pci_enable_device(pdev);
14374         if (err) {
14375                 printk(KERN_ERR PFX "Cannot enable PCI device, "
14376                        "aborting.\n");
14377                 return err;
14378         }
14379
14380         err = pci_request_regions(pdev, DRV_MODULE_NAME);
14381         if (err) {
14382                 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
14383                        "aborting.\n");
14384                 goto err_out_disable_pdev;
14385         }
14386
14387         pci_set_master(pdev);
14388
14389         /* Find power-management capability. */
14390         pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
14391         if (pm_cap == 0) {
14392                 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
14393                        "aborting.\n");
14394                 err = -EIO;
14395                 goto err_out_free_res;
14396         }
14397
14398         dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
14399         if (!dev) {
14400                 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
14401                 err = -ENOMEM;
14402                 goto err_out_free_res;
14403         }
14404
14405         SET_NETDEV_DEV(dev, &pdev->dev);
14406
14407 #if TG3_VLAN_TAG_USED
14408         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
14409 #endif
14410
14411         tp = netdev_priv(dev);
14412         tp->pdev = pdev;
14413         tp->dev = dev;
14414         tp->pm_cap = pm_cap;
14415         tp->rx_mode = TG3_DEF_RX_MODE;
14416         tp->tx_mode = TG3_DEF_TX_MODE;
14417
14418         if (tg3_debug > 0)
14419                 tp->msg_enable = tg3_debug;
14420         else
14421                 tp->msg_enable = TG3_DEF_MSG_ENABLE;
14422
14423         /* The word/byte swap controls here control register access byte
14424          * swapping.  DMA data byte swapping is controlled in the GRC_MODE
14425          * setting below.
14426          */
14427         tp->misc_host_ctrl =
14428                 MISC_HOST_CTRL_MASK_PCI_INT |
14429                 MISC_HOST_CTRL_WORD_SWAP |
14430                 MISC_HOST_CTRL_INDIR_ACCESS |
14431                 MISC_HOST_CTRL_PCISTATE_RW;
14432
14433         /* The NONFRM (non-frame) byte/word swap controls take effect
14434          * on descriptor entries, anything which isn't packet data.
14435          *
14436          * The StrongARM chips on the board (one for tx, one for rx)
14437          * are running in big-endian mode.
14438          */
14439         tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
14440                         GRC_MODE_WSWAP_NONFRM_DATA);
14441 #ifdef __BIG_ENDIAN
14442         tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
14443 #endif
14444         spin_lock_init(&tp->lock);
14445         spin_lock_init(&tp->indirect_lock);
14446         INIT_WORK(&tp->reset_task, tg3_reset_task);
14447
14448         tp->regs = pci_ioremap_bar(pdev, BAR_0);
14449         if (!tp->regs) {
14450                 printk(KERN_ERR PFX "Cannot map device registers, "
14451                        "aborting.\n");
14452                 err = -ENOMEM;
14453                 goto err_out_free_dev;
14454         }
14455
14456         tg3_init_link_config(tp);
14457
14458         tp->rx_pending = TG3_DEF_RX_RING_PENDING;
14459         tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
14460
14461         dev->ethtool_ops = &tg3_ethtool_ops;
14462         dev->watchdog_timeo = TG3_TX_TIMEOUT;
14463         dev->irq = pdev->irq;
14464
14465         err = tg3_get_invariants(tp);
14466         if (err) {
14467                 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
14468                        "aborting.\n");
14469                 goto err_out_iounmap;
14470         }
14471
14472         if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
14473             tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
14474                 dev->netdev_ops = &tg3_netdev_ops;
14475         else
14476                 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
14477
14478
14479         /* The EPB bridge inside 5714, 5715, and 5780 and any
14480          * device behind the EPB cannot support DMA addresses > 40-bit.
14481          * On 64-bit systems with IOMMU, use 40-bit dma_mask.
14482          * On 64-bit systems without IOMMU, use 64-bit dma_mask and
14483          * do DMA address check in tg3_start_xmit().
14484          */
14485         if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
14486                 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
14487         else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
14488                 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
14489 #ifdef CONFIG_HIGHMEM
14490                 dma_mask = DMA_BIT_MASK(64);
14491 #endif
14492         } else
14493                 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
14494
14495         /* Configure DMA attributes. */
14496         if (dma_mask > DMA_BIT_MASK(32)) {
14497                 err = pci_set_dma_mask(pdev, dma_mask);
14498                 if (!err) {
14499                         dev->features |= NETIF_F_HIGHDMA;
14500                         err = pci_set_consistent_dma_mask(pdev,
14501                                                           persist_dma_mask);
14502                         if (err < 0) {
14503                                 printk(KERN_ERR PFX "Unable to obtain 64 bit "
14504                                        "DMA for consistent allocations\n");
14505                                 goto err_out_iounmap;
14506                         }
14507                 }
14508         }
14509         if (err || dma_mask == DMA_BIT_MASK(32)) {
14510                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
14511                 if (err) {
14512                         printk(KERN_ERR PFX "No usable DMA configuration, "
14513                                "aborting.\n");
14514                         goto err_out_iounmap;
14515                 }
14516         }
14517
14518         tg3_init_bufmgr_config(tp);
14519
14520         /* Selectively allow TSO based on operating conditions */
14521         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
14522             (tp->fw_needed && !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)))
14523                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
14524         else {
14525                 tp->tg3_flags2 &= ~(TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG);
14526                 tp->fw_needed = NULL;
14527         }
14528
14529         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
14530                 tp->fw_needed = FIRMWARE_TG3;
14531
14532         /* TSO is on by default on chips that support hardware TSO.
14533          * Firmware TSO on older chips gives lower performance, so it
14534          * is off by default, but can be enabled using ethtool.
14535          */
14536         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) &&
14537             (dev->features & NETIF_F_IP_CSUM))
14538                 dev->features |= NETIF_F_TSO;
14539
14540         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
14541             (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3)) {
14542                 if (dev->features & NETIF_F_IPV6_CSUM)
14543                         dev->features |= NETIF_F_TSO6;
14544                 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
14545                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
14546                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
14547                      GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
14548                         GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
14549                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
14550                         dev->features |= NETIF_F_TSO_ECN;
14551         }
14552
14553         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
14554             !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
14555             !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
14556                 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
14557                 tp->rx_pending = 63;
14558         }
14559
14560         err = tg3_get_device_address(tp);
14561         if (err) {
14562                 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
14563                        "aborting.\n");
14564                 goto err_out_iounmap;
14565         }
14566
14567         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
14568                 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
14569                 if (!tp->aperegs) {
14570                         printk(KERN_ERR PFX "Cannot map APE registers, "
14571                                "aborting.\n");
14572                         err = -ENOMEM;
14573                         goto err_out_iounmap;
14574                 }
14575
14576                 tg3_ape_lock_init(tp);
14577
14578                 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
14579                         tg3_read_dash_ver(tp);
14580         }
14581
14582         /*
14583          * Reset chip in case UNDI or EFI driver did not shutdown
14584          * DMA self test will enable WDMAC and we'll see (spurious)
14585          * pending DMA on the PCI bus at that point.
14586          */
14587         if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
14588             (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
14589                 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
14590                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14591         }
14592
14593         err = tg3_test_dma(tp);
14594         if (err) {
14595                 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
14596                 goto err_out_apeunmap;
14597         }
14598
14599         /* flow control autonegotiation is default behavior */
14600         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
14601         tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
14602
14603         intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
14604         rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
14605         sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
14606         for (i = 0; i < TG3_IRQ_MAX_VECS; i++) {
14607                 struct tg3_napi *tnapi = &tp->napi[i];
14608
14609                 tnapi->tp = tp;
14610                 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
14611
14612                 tnapi->int_mbox = intmbx;
14613                 if (i < 4)
14614                         intmbx += 0x8;
14615                 else
14616                         intmbx += 0x4;
14617
14618                 tnapi->consmbox = rcvmbx;
14619                 tnapi->prodmbox = sndmbx;
14620
14621                 if (i) {
14622                         tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
14623                         netif_napi_add(dev, &tnapi->napi, tg3_poll_msix, 64);
14624                 } else {
14625                         tnapi->coal_now = HOSTCC_MODE_NOW;
14626                         netif_napi_add(dev, &tnapi->napi, tg3_poll, 64);
14627                 }
14628
14629                 if (!(tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX))
14630                         break;
14631
14632                 /*
14633                  * If we support MSIX, we'll be using RSS.  If we're using
14634                  * RSS, the first vector only handles link interrupts and the
14635                  * remaining vectors handle rx and tx interrupts.  Reuse the
14636                  * mailbox values for the next iteration.  The values we setup
14637                  * above are still useful for the single vectored mode.
14638                  */
14639                 if (!i)
14640                         continue;
14641
14642                 rcvmbx += 0x8;
14643
14644                 if (sndmbx & 0x4)
14645                         sndmbx -= 0x4;
14646                 else
14647                         sndmbx += 0xc;
14648         }
14649
14650         tg3_init_coal(tp);
14651
14652         pci_set_drvdata(pdev, dev);
14653
14654         err = register_netdev(dev);
14655         if (err) {
14656                 printk(KERN_ERR PFX "Cannot register net device, "
14657                        "aborting.\n");
14658                 goto err_out_apeunmap;
14659         }
14660
14661         printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
14662                dev->name,
14663                tp->board_part_number,
14664                tp->pci_chip_rev_id,
14665                tg3_bus_string(tp, str),
14666                dev->dev_addr);
14667
14668         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
14669                 struct phy_device *phydev;
14670                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
14671                 printk(KERN_INFO
14672                        "%s: attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
14673                        tp->dev->name, phydev->drv->name,
14674                        dev_name(&phydev->dev));
14675         } else
14676                 printk(KERN_INFO
14677                        "%s: attached PHY is %s (%s Ethernet) (WireSpeed[%d])\n",
14678                        tp->dev->name, tg3_phy_string(tp),
14679                        ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
14680                         ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
14681                          "10/100/1000Base-T")),
14682                        (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0);
14683
14684         printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
14685                dev->name,
14686                (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
14687                (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
14688                (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
14689                (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
14690                (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
14691         printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
14692                dev->name, tp->dma_rwctrl,
14693                (pdev->dma_mask == DMA_BIT_MASK(32)) ? 32 :
14694                 (((u64) pdev->dma_mask == DMA_BIT_MASK(40)) ? 40 : 64));
14695
14696         return 0;
14697
14698 err_out_apeunmap:
14699         if (tp->aperegs) {
14700                 iounmap(tp->aperegs);
14701                 tp->aperegs = NULL;
14702         }
14703
14704 err_out_iounmap:
14705         if (tp->regs) {
14706                 iounmap(tp->regs);
14707                 tp->regs = NULL;
14708         }
14709
14710 err_out_free_dev:
14711         free_netdev(dev);
14712
14713 err_out_free_res:
14714         pci_release_regions(pdev);
14715
14716 err_out_disable_pdev:
14717         pci_disable_device(pdev);
14718         pci_set_drvdata(pdev, NULL);
14719         return err;
14720 }
14721
14722 static void __devexit tg3_remove_one(struct pci_dev *pdev)
14723 {
14724         struct net_device *dev = pci_get_drvdata(pdev);
14725
14726         if (dev) {
14727                 struct tg3 *tp = netdev_priv(dev);
14728
14729                 if (tp->fw)
14730                         release_firmware(tp->fw);
14731
14732                 flush_scheduled_work();
14733
14734                 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
14735                         tg3_phy_fini(tp);
14736                         tg3_mdio_fini(tp);
14737                 }
14738
14739                 unregister_netdev(dev);
14740                 if (tp->aperegs) {
14741                         iounmap(tp->aperegs);
14742                         tp->aperegs = NULL;
14743                 }
14744                 if (tp->regs) {
14745                         iounmap(tp->regs);
14746                         tp->regs = NULL;
14747                 }
14748                 free_netdev(dev);
14749                 pci_release_regions(pdev);
14750                 pci_disable_device(pdev);
14751                 pci_set_drvdata(pdev, NULL);
14752         }
14753 }
14754
14755 static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
14756 {
14757         struct net_device *dev = pci_get_drvdata(pdev);
14758         struct tg3 *tp = netdev_priv(dev);
14759         pci_power_t target_state;
14760         int err;
14761
14762         /* PCI register 4 needs to be saved whether netif_running() or not.
14763          * MSI address and data need to be saved if using MSI and
14764          * netif_running().
14765          */
14766         pci_save_state(pdev);
14767
14768         if (!netif_running(dev))
14769                 return 0;
14770
14771         flush_scheduled_work();
14772         tg3_phy_stop(tp);
14773         tg3_netif_stop(tp);
14774
14775         del_timer_sync(&tp->timer);
14776
14777         tg3_full_lock(tp, 1);
14778         tg3_disable_ints(tp);
14779         tg3_full_unlock(tp);
14780
14781         netif_device_detach(dev);
14782
14783         tg3_full_lock(tp, 0);
14784         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14785         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
14786         tg3_full_unlock(tp);
14787
14788         target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
14789
14790         err = tg3_set_power_state(tp, target_state);
14791         if (err) {
14792                 int err2;
14793
14794                 tg3_full_lock(tp, 0);
14795
14796                 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
14797                 err2 = tg3_restart_hw(tp, 1);
14798                 if (err2)
14799                         goto out;
14800
14801                 tp->timer.expires = jiffies + tp->timer_offset;
14802                 add_timer(&tp->timer);
14803
14804                 netif_device_attach(dev);
14805                 tg3_netif_start(tp);
14806
14807 out:
14808                 tg3_full_unlock(tp);
14809
14810                 if (!err2)
14811                         tg3_phy_start(tp);
14812         }
14813
14814         return err;
14815 }
14816
14817 static int tg3_resume(struct pci_dev *pdev)
14818 {
14819         struct net_device *dev = pci_get_drvdata(pdev);
14820         struct tg3 *tp = netdev_priv(dev);
14821         int err;
14822
14823         pci_restore_state(tp->pdev);
14824
14825         if (!netif_running(dev))
14826                 return 0;
14827
14828         err = tg3_set_power_state(tp, PCI_D0);
14829         if (err)
14830                 return err;
14831
14832         netif_device_attach(dev);
14833
14834         tg3_full_lock(tp, 0);
14835
14836         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
14837         err = tg3_restart_hw(tp, 1);
14838         if (err)
14839                 goto out;
14840
14841         tp->timer.expires = jiffies + tp->timer_offset;
14842         add_timer(&tp->timer);
14843
14844         tg3_netif_start(tp);
14845
14846 out:
14847         tg3_full_unlock(tp);
14848
14849         if (!err)
14850                 tg3_phy_start(tp);
14851
14852         return err;
14853 }
14854
14855 static struct pci_driver tg3_driver = {
14856         .name           = DRV_MODULE_NAME,
14857         .id_table       = tg3_pci_tbl,
14858         .probe          = tg3_init_one,
14859         .remove         = __devexit_p(tg3_remove_one),
14860         .suspend        = tg3_suspend,
14861         .resume         = tg3_resume
14862 };
14863
14864 static int __init tg3_init(void)
14865 {
14866         return pci_register_driver(&tg3_driver);
14867 }
14868
14869 static void __exit tg3_cleanup(void)
14870 {
14871         pci_unregister_driver(&tg3_driver);
14872 }
14873
14874 module_init(tg3_init);
14875 module_exit(tg3_cleanup);