SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/net/tg3.c

   1 /*
   2  * tg3.c: Broadcom Tigon3 ethernet driver.
   3  *
   4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
   5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
   6  * Copyright (C) 2004 Sun Microsystems Inc.
   7  * Copyright (C) 2005-2010 Broadcom Corporation.
   8  *
   9  * Firmware is:
  10  *      Derived from proprietary unpublished source code,
  11  *      Copyright (C) 2000-2003 Broadcom Corporation.
  12  *
  13  *      Permission is hereby granted for the distribution of this firmware
  14  *      data in hexadecimal or equivalent format, provided this copyright
  15  *      notice is accompanying it.
  16  */
  17
  18
  19 #include <linux/module.h>
  20 #include <linux/moduleparam.h>
  21 #include <linux/kernel.h>
  22 #include <linux/types.h>
  23 #include <linux/compiler.h>
  24 #include <linux/slab.h>
  25 #include <linux/delay.h>
  26 #include <linux/in.h>
  27 #include <linux/init.h>
  28 #include <linux/ioport.h>
  29 #include <linux/pci.h>
  30 #include <linux/netdevice.h>
  31 #include <linux/etherdevice.h>
  32 #include <linux/skbuff.h>
  33 #include <linux/ethtool.h>
  34 #include <linux/mii.h>
  35 #include <linux/phy.h>
  36 #include <linux/brcmphy.h>
  37 #include <linux/if_vlan.h>
  38 #include <linux/ip.h>
  39 #include <linux/tcp.h>
  40 #include <linux/workqueue.h>
  41 #include <linux/prefetch.h>
  42 #include <linux/dma-mapping.h>
  43 #include <linux/firmware.h>
  44
  45 #include <net/checksum.h>
  46 #include <net/ip.h>
  47
  48 #include <asm/system.h>
  49 #include <asm/io.h>
  50 #include <asm/byteorder.h>
  51 #include <asm/uaccess.h>
  52
  53 #ifdef CONFIG_SPARC
  54 #include <asm/idprom.h>
  55 #include <asm/prom.h>
  56 #endif
  57
  58 #define BAR_0   0
  59 #define BAR_2   2
  60
  61 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  62 #define TG3_VLAN_TAG_USED 1
  63 #else
  64 #define TG3_VLAN_TAG_USED 0
  65 #endif
  66
  67 #include "tg3.h"
  68
  69 #define DRV_MODULE_NAME         "tg3"
  70 #define PFX DRV_MODULE_NAME     ": "
  71 #define DRV_MODULE_VERSION      "3.106"
  72 #define DRV_MODULE_RELDATE      "January 12, 2010"
  73
  74 #define TG3_DEF_MAC_MODE        0
  75 #define TG3_DEF_RX_MODE         0
  76 #define TG3_DEF_TX_MODE         0
  77 #define TG3_DEF_MSG_ENABLE        \
  78         (NETIF_MSG_DRV          | \
  79          NETIF_MSG_PROBE        | \
  80          NETIF_MSG_LINK         | \
  81          NETIF_MSG_TIMER        | \
  82          NETIF_MSG_IFDOWN       | \
  83          NETIF_MSG_IFUP         | \
  84          NETIF_MSG_RX_ERR       | \
  85          NETIF_MSG_TX_ERR)
  86
  87 /* length of time before we decide the hardware is borked,
  88  * and dev->tx_timeout() should be called to fix the problem
  89  */
  90 #define TG3_TX_TIMEOUT                  (5 * HZ)
  91
  92 /* hardware minimum and maximum for a single frame's data payload */
  93 #define TG3_MIN_MTU                     60
  94 #define TG3_MAX_MTU(tp) \
  95         ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
  96
  97 /* These numbers seem to be hard coded in the NIC firmware somehow.
  98  * You can't change the ring sizes, but you can change where you place
  99  * them in the NIC onboard memory.
 100  */
 101 #define TG3_RX_RING_SIZE                512
 102 #define TG3_DEF_RX_RING_PENDING         200
 103 #define TG3_RX_JUMBO_RING_SIZE          256
 104 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
 105 #define TG3_RSS_INDIR_TBL_SIZE 128
 106
 107 /* Do not place this n-ring entries value into the tp struct itself,
 108  * we really want to expose these constants to GCC so that modulo et
 109  * al.  operations are done with shifts and masks instead of with
 110  * hw multiply/modulo instructions.  Another solution would be to
 111  * replace things like '% foo' with '& (foo - 1)'.
 112  */
 113 #define TG3_RX_RCB_RING_SIZE(tp)        \
 114         (((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) && \
 115           !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) ? 1024 : 512)
 116
 117 #define TG3_TX_RING_SIZE                512
 118 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
 119
 120 #define TG3_RX_RING_BYTES       (sizeof(struct tg3_rx_buffer_desc) * \
 121                                  TG3_RX_RING_SIZE)
 122 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_ext_rx_buffer_desc) * \
 123                                  TG3_RX_JUMBO_RING_SIZE)
 124 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
 125                                  TG3_RX_RCB_RING_SIZE(tp))
 126 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
 127                                  TG3_TX_RING_SIZE)
 128 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
 129
 130 #define TG3_DMA_BYTE_ENAB               64
 131
 132 #define TG3_RX_STD_DMA_SZ               1536
 133 #define TG3_RX_JMB_DMA_SZ               9046
 134
 135 #define TG3_RX_DMA_TO_MAP_SZ(x)         ((x) + TG3_DMA_BYTE_ENAB)
 136
 137 #define TG3_RX_STD_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
 138 #define TG3_RX_JMB_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
 139
 140 #define TG3_RX_STD_BUFF_RING_SIZE \
 141         (sizeof(struct ring_info) * TG3_RX_RING_SIZE)
 142
 143 #define TG3_RX_JMB_BUFF_RING_SIZE \
 144         (sizeof(struct ring_info) * TG3_RX_JUMBO_RING_SIZE)
 145
 146 /* minimum number of free TX descriptors required to wake up TX process */
 147 #define TG3_TX_WAKEUP_THRESH(tnapi)             ((tnapi)->tx_pending / 4)
 148
 149 #define TG3_RAW_IP_ALIGN 2
 150
 151 /* number of ETHTOOL_GSTATS u64's */
 152 #define TG3_NUM_STATS           (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
 153
 154 #define TG3_NUM_TEST            6
 155
 156 #define FIRMWARE_TG3            "tigon/tg3.bin"
 157 #define FIRMWARE_TG3TSO         "tigon/tg3_tso.bin"
 158 #define FIRMWARE_TG3TSO5        "tigon/tg3_tso5.bin"
 159
 160 static char version[] __devinitdata =
 161         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
 162
 163 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
 164 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
 165 MODULE_LICENSE("GPL");
 166 MODULE_VERSION(DRV_MODULE_VERSION);
 167 MODULE_FIRMWARE(FIRMWARE_TG3);
 168 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
 169 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
 170
 171 #define TG3_RSS_MIN_NUM_MSIX_VECS       2
 172
 173 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
 174 module_param(tg3_debug, int, 0);
 175 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
 176
 177 static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
 178         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
 179         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
 180         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
 181         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
 182         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
 183         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
 184         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
 185         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
 186         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
 187         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
 188         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
 189         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
 190         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
 191         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
 192         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
 193         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
 194         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
 195         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
 196         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
 197         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
 198         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
 199         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
 200         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
 201         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
 202         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
 203         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
 204         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
 205         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
 206         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
 207         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
 208         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
 209         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
 210         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
 211         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
 212         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
 213         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
 214         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
 215         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
 216         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
 217         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
 218         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
 219         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
 220         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
 221         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
 222         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
 223         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
 224         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
 225         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
 226         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
 227         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
 228         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
 229         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
 230         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
 231         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
 232         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
 233         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
 234         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
 235         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
 236         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
 237         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
 238         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
 239         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
 240         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
 241         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
 242         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
 243         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
 244         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
 245         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
 246         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5724)},
 247         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
 248         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
 249         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
 250         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
 251         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791)},
 252         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795)},
 253         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
 254         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
 255         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
 256         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
 257         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
 258         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
 259         {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
 260         {}
 261 };
 262
 263 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
 264
 265 static const struct {
 266         const char string[ETH_GSTRING_LEN];
 267 } ethtool_stats_keys[TG3_NUM_STATS] = {
 268         { "rx_octets" },
 269         { "rx_fragments" },
 270         { "rx_ucast_packets" },
 271         { "rx_mcast_packets" },
 272         { "rx_bcast_packets" },
 273         { "rx_fcs_errors" },
 274         { "rx_align_errors" },
 275         { "rx_xon_pause_rcvd" },
 276         { "rx_xoff_pause_rcvd" },
 277         { "rx_mac_ctrl_rcvd" },
 278         { "rx_xoff_entered" },
 279         { "rx_frame_too_long_errors" },
 280         { "rx_jabbers" },
 281         { "rx_undersize_packets" },
 282         { "rx_in_length_errors" },
 283         { "rx_out_length_errors" },
 284         { "rx_64_or_less_octet_packets" },
 285         { "rx_65_to_127_octet_packets" },
 286         { "rx_128_to_255_octet_packets" },
 287         { "rx_256_to_511_octet_packets" },
 288         { "rx_512_to_1023_octet_packets" },
 289         { "rx_1024_to_1522_octet_packets" },
 290         { "rx_1523_to_2047_octet_packets" },
 291         { "rx_2048_to_4095_octet_packets" },
 292         { "rx_4096_to_8191_octet_packets" },
 293         { "rx_8192_to_9022_octet_packets" },
 294
 295         { "tx_octets" },
 296         { "tx_collisions" },
 297
 298         { "tx_xon_sent" },
 299         { "tx_xoff_sent" },
 300         { "tx_flow_control" },
 301         { "tx_mac_errors" },
 302         { "tx_single_collisions" },
 303         { "tx_mult_collisions" },
 304         { "tx_deferred" },
 305         { "tx_excessive_collisions" },
 306         { "tx_late_collisions" },
 307         { "tx_collide_2times" },
 308         { "tx_collide_3times" },
 309         { "tx_collide_4times" },
 310         { "tx_collide_5times" },
 311         { "tx_collide_6times" },
 312         { "tx_collide_7times" },
 313         { "tx_collide_8times" },
 314         { "tx_collide_9times" },
 315         { "tx_collide_10times" },
 316         { "tx_collide_11times" },
 317         { "tx_collide_12times" },
 318         { "tx_collide_13times" },
 319         { "tx_collide_14times" },
 320         { "tx_collide_15times" },
 321         { "tx_ucast_packets" },
 322         { "tx_mcast_packets" },
 323         { "tx_bcast_packets" },
 324         { "tx_carrier_sense_errors" },
 325         { "tx_discards" },
 326         { "tx_errors" },
 327
 328         { "dma_writeq_full" },
 329         { "dma_write_prioq_full" },
 330         { "rxbds_empty" },
 331         { "rx_discards" },
 332         { "rx_errors" },
 333         { "rx_threshold_hit" },
 334
 335         { "dma_readq_full" },
 336         { "dma_read_prioq_full" },
 337         { "tx_comp_queue_full" },
 338
 339         { "ring_set_send_prod_index" },
 340         { "ring_status_update" },
 341         { "nic_irqs" },
 342         { "nic_avoided_irqs" },
 343         { "nic_tx_threshold_hit" }
 344 };
 345
 346 static const struct {
 347         const char string[ETH_GSTRING_LEN];
 348 } ethtool_test_keys[TG3_NUM_TEST] = {
 349         { "nvram test     (online) " },
 350         { "link test      (online) " },
 351         { "register test  (offline)" },
 352         { "memory test    (offline)" },
 353         { "loopback test  (offline)" },
 354         { "interrupt test (offline)" },
 355 };
 356
 357 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
 358 {
 359         writel(val, tp->regs + off);
 360 }
 361
 362 static u32 tg3_read32(struct tg3 *tp, u32 off)
 363 {
 364         return (readl(tp->regs + off));
 365 }
 366
 367 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
 368 {
 369         writel(val, tp->aperegs + off);
 370 }
 371
 372 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
 373 {
 374         return (readl(tp->aperegs + off));
 375 }
 376
 377 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
 378 {
 379         unsigned long flags;
 380
 381         spin_lock_irqsave(&tp->indirect_lock, flags);
 382         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 383         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 384         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 385 }
 386
 387 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
 388 {
 389         writel(val, tp->regs + off);
 390         readl(tp->regs + off);
 391 }
 392
 393 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
 394 {
 395         unsigned long flags;
 396         u32 val;
 397
 398         spin_lock_irqsave(&tp->indirect_lock, flags);
 399         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 400         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 401         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 402         return val;
 403 }
 404
 405 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
 406 {
 407         unsigned long flags;
 408
 409         if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
 410                 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
 411                                        TG3_64BIT_REG_LOW, val);
 412                 return;
 413         }
 414         if (off == TG3_RX_STD_PROD_IDX_REG) {
 415                 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
 416                                        TG3_64BIT_REG_LOW, val);
 417                 return;
 418         }
 419
 420         spin_lock_irqsave(&tp->indirect_lock, flags);
 421         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 422         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 423         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 424
 425         /* In indirect mode when disabling interrupts, we also need
 426          * to clear the interrupt bit in the GRC local ctrl register.
 427          */
 428         if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
 429             (val == 0x1)) {
 430                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
 431                                        tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
 432         }
 433 }
 434
 435 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
 436 {
 437         unsigned long flags;
 438         u32 val;
 439
 440         spin_lock_irqsave(&tp->indirect_lock, flags);
 441         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 442         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 443         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 444         return val;
 445 }
 446
 447 /* usec_wait specifies the wait time in usec when writing to certain registers
 448  * where it is unsafe to read back the register without some delay.
 449  * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
 450  * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
 451  */
 452 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
 453 {
 454         if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
 455             (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 456                 /* Non-posted methods */
 457                 tp->write32(tp, off, val);
 458         else {
 459                 /* Posted method */
 460                 tg3_write32(tp, off, val);
 461                 if (usec_wait)
 462                         udelay(usec_wait);
 463                 tp->read32(tp, off);
 464         }
 465         /* Wait again after the read for the posted method to guarantee that
 466          * the wait time is met.
 467          */
 468         if (usec_wait)
 469                 udelay(usec_wait);
 470 }
 471
 472 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
 473 {
 474         tp->write32_mbox(tp, off, val);
 475         if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
 476             !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 477                 tp->read32_mbox(tp, off);
 478 }
 479
 480 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
 481 {
 482         void __iomem *mbox = tp->regs + off;
 483         writel(val, mbox);
 484         if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
 485                 writel(val, mbox);
 486         if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
 487                 readl(mbox);
 488 }
 489
 490 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
 491 {
 492         return (readl(tp->regs + off + GRCMBOX_BASE));
 493 }
 494
 495 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
 496 {
 497         writel(val, tp->regs + off + GRCMBOX_BASE);
 498 }
 499
 500 #define tw32_mailbox(reg, val)  tp->write32_mbox(tp, reg, val)
 501 #define tw32_mailbox_f(reg, val)        tw32_mailbox_flush(tp, (reg), (val))
 502 #define tw32_rx_mbox(reg, val)  tp->write32_rx_mbox(tp, reg, val)
 503 #define tw32_tx_mbox(reg, val)  tp->write32_tx_mbox(tp, reg, val)
 504 #define tr32_mailbox(reg)       tp->read32_mbox(tp, reg)
 505
 506 #define tw32(reg,val)           tp->write32(tp, reg, val)
 507 #define tw32_f(reg,val)         _tw32_flush(tp,(reg),(val), 0)
 508 #define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
 509 #define tr32(reg)               tp->read32(tp, reg)
 510
 511 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
 512 {
 513         unsigned long flags;
 514
 515         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 516             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
 517                 return;
 518
 519         spin_lock_irqsave(&tp->indirect_lock, flags);
 520         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 521                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 522                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 523
 524                 /* Always leave this as zero. */
 525                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 526         } else {
 527                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 528                 tw32_f(TG3PCI_MEM_WIN_DATA, val);
 529
 530                 /* Always leave this as zero. */
 531                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 532         }
 533         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 534 }
 535
 536 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
 537 {
 538         unsigned long flags;
 539
 540         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 541             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
 542                 *val = 0;
 543                 return;
 544         }
 545
 546         spin_lock_irqsave(&tp->indirect_lock, flags);
 547         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 548                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 549                 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 550
 551                 /* Always leave this as zero. */
 552                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 553         } else {
 554                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 555                 *val = tr32(TG3PCI_MEM_WIN_DATA);
 556
 557                 /* Always leave this as zero. */
 558                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 559         }
 560         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 561 }
 562
 563 static void tg3_ape_lock_init(struct tg3 *tp)
 564 {
 565         int i;
 566
 567         /* Make sure the driver hasn't any stale locks. */
 568         for (i = 0; i < 8; i++)
 569                 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + 4 * i,
 570                                 APE_LOCK_GRANT_DRIVER);
 571 }
 572
 573 static int tg3_ape_lock(struct tg3 *tp, int locknum)
 574 {
 575         int i, off;
 576         int ret = 0;
 577         u32 status;
 578
 579         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 580                 return 0;
 581
 582         switch (locknum) {
 583                 case TG3_APE_LOCK_GRC:
 584                 case TG3_APE_LOCK_MEM:
 585                         break;
 586                 default:
 587                         return -EINVAL;
 588         }
 589
 590         off = 4 * locknum;
 591
 592         tg3_ape_write32(tp, TG3_APE_LOCK_REQ + off, APE_LOCK_REQ_DRIVER);
 593
 594         /* Wait for up to 1 millisecond to acquire lock. */
 595         for (i = 0; i < 100; i++) {
 596                 status = tg3_ape_read32(tp, TG3_APE_LOCK_GRANT + off);
 597                 if (status == APE_LOCK_GRANT_DRIVER)
 598                         break;
 599                 udelay(10);
 600         }
 601
 602         if (status != APE_LOCK_GRANT_DRIVER) {
 603                 /* Revoke the lock request. */
 604                 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off,
 605                                 APE_LOCK_GRANT_DRIVER);
 606
 607                 ret = -EBUSY;
 608         }
 609
 610         return ret;
 611 }
 612
 613 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
 614 {
 615         int off;
 616
 617         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 618                 return;
 619
 620         switch (locknum) {
 621                 case TG3_APE_LOCK_GRC:
 622                 case TG3_APE_LOCK_MEM:
 623                         break;
 624                 default:
 625                         return;
 626         }
 627
 628         off = 4 * locknum;
 629         tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, APE_LOCK_GRANT_DRIVER);
 630 }
 631
 632 static void tg3_disable_ints(struct tg3 *tp)
 633 {
 634         int i;
 635
 636         tw32(TG3PCI_MISC_HOST_CTRL,
 637              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
 638         for (i = 0; i < tp->irq_max; i++)
 639                 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
 640 }
 641
 642 static void tg3_enable_ints(struct tg3 *tp)
 643 {
 644         int i;
 645         u32 coal_now = 0;
 646
 647         tp->irq_sync = 0;
 648         wmb();
 649
 650         tw32(TG3PCI_MISC_HOST_CTRL,
 651              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
 652
 653         for (i = 0; i < tp->irq_cnt; i++) {
 654                 struct tg3_napi *tnapi = &tp->napi[i];
 655                 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
 656                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
 657                         tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
 658
 659                 coal_now |= tnapi->coal_now;
 660         }
 661
 662         /* Force an initial interrupt */
 663         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 664             (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
 665                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
 666         else
 667                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 668                      HOSTCC_MODE_ENABLE | coal_now);
 669 }
 670
 671 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
 672 {
 673         struct tg3 *tp = tnapi->tp;
 674         struct tg3_hw_status *sblk = tnapi->hw_status;
 675         unsigned int work_exists = 0;
 676
 677         /* check for phy events */
 678         if (!(tp->tg3_flags &
 679               (TG3_FLAG_USE_LINKCHG_REG |
 680                TG3_FLAG_POLL_SERDES))) {
 681                 if (sblk->status & SD_STATUS_LINK_CHG)
 682                         work_exists = 1;
 683         }
 684         /* check for RX/TX work to do */
 685         if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
 686             *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
 687                 work_exists = 1;
 688
 689         return work_exists;
 690 }
 691
 692 /* tg3_int_reenable
 693  *  similar to tg3_enable_ints, but it accurately determines whether there
 694  *  is new work pending and can return without flushing the PIO write
 695  *  which reenables interrupts
 696  */
 697 static void tg3_int_reenable(struct tg3_napi *tnapi)
 698 {
 699         struct tg3 *tp = tnapi->tp;
 700
 701         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
 702         mmiowb();
 703
 704         /* When doing tagged status, this work check is unnecessary.
 705          * The last_tag we write above tells the chip which piece of
 706          * work we've completed.
 707          */
 708         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 709             tg3_has_work(tnapi))
 710                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 711                      HOSTCC_MODE_ENABLE | tnapi->coal_now);
 712 }
 713
 714 static void tg3_napi_disable(struct tg3 *tp)
 715 {
 716         int i;
 717
 718         for (i = tp->irq_cnt - 1; i >= 0; i--)
 719                 napi_disable(&tp->napi[i].napi);
 720 }
 721
 722 static void tg3_napi_enable(struct tg3 *tp)
 723 {
 724         int i;
 725
 726         for (i = 0; i < tp->irq_cnt; i++)
 727                 napi_enable(&tp->napi[i].napi);
 728 }
 729
 730 static inline void tg3_netif_stop(struct tg3 *tp)
 731 {
 732         tp->dev->trans_start = jiffies; /* prevent tx timeout */
 733         tg3_napi_disable(tp);
 734         netif_tx_disable(tp->dev);
 735 }
 736
 737 static inline void tg3_netif_start(struct tg3 *tp)
 738 {
 739         /* NOTE: unconditional netif_tx_wake_all_queues is only
 740          * appropriate so long as all callers are assured to
 741          * have free tx slots (such as after tg3_init_hw)
 742          */
 743         netif_tx_wake_all_queues(tp->dev);
 744
 745         tg3_napi_enable(tp);
 746         tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
 747         tg3_enable_ints(tp);
 748 }
 749
 750 static void tg3_switch_clocks(struct tg3 *tp)
 751 {
 752         u32 clock_ctrl;
 753         u32 orig_clock_ctrl;
 754
 755         if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
 756             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
 757                 return;
 758
 759         clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
 760
 761         orig_clock_ctrl = clock_ctrl;
 762         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
 763                        CLOCK_CTRL_CLKRUN_OENABLE |
 764                        0x1f);
 765         tp->pci_clock_ctrl = clock_ctrl;
 766
 767         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
 768                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
 769                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
 770                                     clock_ctrl | CLOCK_CTRL_625_CORE, 40);
 771                 }
 772         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
 773                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 774                             clock_ctrl |
 775                             (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
 776                             40);
 777                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 778                             clock_ctrl | (CLOCK_CTRL_ALTCLK),
 779                             40);
 780         }
 781         tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
 782 }
 783
 784 #define PHY_BUSY_LOOPS  5000
 785
 786 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
 787 {
 788         u32 frame_val;
 789         unsigned int loops;
 790         int ret;
 791
 792         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 793                 tw32_f(MAC_MI_MODE,
 794                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 795                 udelay(80);
 796         }
 797
 798         *val = 0x0;
 799
 800         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
 801                       MI_COM_PHY_ADDR_MASK);
 802         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 803                       MI_COM_REG_ADDR_MASK);
 804         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
 805
 806         tw32_f(MAC_MI_COM, frame_val);
 807
 808         loops = PHY_BUSY_LOOPS;
 809         while (loops != 0) {
 810                 udelay(10);
 811                 frame_val = tr32(MAC_MI_COM);
 812
 813                 if ((frame_val & MI_COM_BUSY) == 0) {
 814                         udelay(5);
 815                         frame_val = tr32(MAC_MI_COM);
 816                         break;
 817                 }
 818                 loops -= 1;
 819         }
 820
 821         ret = -EBUSY;
 822         if (loops != 0) {
 823                 *val = frame_val & MI_COM_DATA_MASK;
 824                 ret = 0;
 825         }
 826
 827         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 828                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 829                 udelay(80);
 830         }
 831
 832         return ret;
 833 }
 834
 835 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
 836 {
 837         u32 frame_val;
 838         unsigned int loops;
 839         int ret;
 840
 841         if ((tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
 842             (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
 843                 return 0;
 844
 845         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 846                 tw32_f(MAC_MI_MODE,
 847                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 848                 udelay(80);
 849         }
 850
 851         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
 852                       MI_COM_PHY_ADDR_MASK);
 853         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 854                       MI_COM_REG_ADDR_MASK);
 855         frame_val |= (val & MI_COM_DATA_MASK);
 856         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
 857
 858         tw32_f(MAC_MI_COM, frame_val);
 859
 860         loops = PHY_BUSY_LOOPS;
 861         while (loops != 0) {
 862                 udelay(10);
 863                 frame_val = tr32(MAC_MI_COM);
 864                 if ((frame_val & MI_COM_BUSY) == 0) {
 865                         udelay(5);
 866                         frame_val = tr32(MAC_MI_COM);
 867                         break;
 868                 }
 869                 loops -= 1;
 870         }
 871
 872         ret = -EBUSY;
 873         if (loops != 0)
 874                 ret = 0;
 875
 876         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 877                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 878                 udelay(80);
 879         }
 880
 881         return ret;
 882 }
 883
 884 static int tg3_bmcr_reset(struct tg3 *tp)
 885 {
 886         u32 phy_control;
 887         int limit, err;
 888
 889         /* OK, reset it, and poll the BMCR_RESET bit until it
 890          * clears or we time out.
 891          */
 892         phy_control = BMCR_RESET;
 893         err = tg3_writephy(tp, MII_BMCR, phy_control);
 894         if (err != 0)
 895                 return -EBUSY;
 896
 897         limit = 5000;
 898         while (limit--) {
 899                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
 900                 if (err != 0)
 901                         return -EBUSY;
 902
 903                 if ((phy_control & BMCR_RESET) == 0) {
 904                         udelay(40);
 905                         break;
 906                 }
 907                 udelay(10);
 908         }
 909         if (limit < 0)
 910                 return -EBUSY;
 911
 912         return 0;
 913 }
 914
 915 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
 916 {
 917         struct tg3 *tp = bp->priv;
 918         u32 val;
 919
 920         spin_lock_bh(&tp->lock);
 921
 922         if (tg3_readphy(tp, reg, &val))
 923                 val = -EIO;
 924
 925         spin_unlock_bh(&tp->lock);
 926
 927         return val;
 928 }
 929
 930 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
 931 {
 932         struct tg3 *tp = bp->priv;
 933         u32 ret = 0;
 934
 935         spin_lock_bh(&tp->lock);
 936
 937         if (tg3_writephy(tp, reg, val))
 938                 ret = -EIO;
 939
 940         spin_unlock_bh(&tp->lock);
 941
 942         return ret;
 943 }
 944
 945 static int tg3_mdio_reset(struct mii_bus *bp)
 946 {
 947         return 0;
 948 }
 949
 950 static void tg3_mdio_config_5785(struct tg3 *tp)
 951 {
 952         u32 val;
 953         struct phy_device *phydev;
 954
 955         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
 956         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
 957         case TG3_PHY_ID_BCM50610:
 958         case TG3_PHY_ID_BCM50610M:
 959                 val = MAC_PHYCFG2_50610_LED_MODES;
 960                 break;
 961         case TG3_PHY_ID_BCMAC131:
 962                 val = MAC_PHYCFG2_AC131_LED_MODES;
 963                 break;
 964         case TG3_PHY_ID_RTL8211C:
 965                 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
 966                 break;
 967         case TG3_PHY_ID_RTL8201E:
 968                 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
 969                 break;
 970         default:
 971                 return;
 972         }
 973
 974         if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
 975                 tw32(MAC_PHYCFG2, val);
 976
 977                 val = tr32(MAC_PHYCFG1);
 978                 val &= ~(MAC_PHYCFG1_RGMII_INT |
 979                          MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
 980                 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
 981                 tw32(MAC_PHYCFG1, val);
 982
 983                 return;
 984         }
 985
 986         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE))
 987                 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
 988                        MAC_PHYCFG2_FMODE_MASK_MASK |
 989                        MAC_PHYCFG2_GMODE_MASK_MASK |
 990                        MAC_PHYCFG2_ACT_MASK_MASK   |
 991                        MAC_PHYCFG2_QUAL_MASK_MASK |
 992                        MAC_PHYCFG2_INBAND_ENABLE;
 993
 994         tw32(MAC_PHYCFG2, val);
 995
 996         val = tr32(MAC_PHYCFG1);
 997         val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
 998                  MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
 999         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
1000                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1001                         val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
1002                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1003                         val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1004         }
1005         val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1006                MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1007         tw32(MAC_PHYCFG1, val);
1008
1009         val = tr32(MAC_EXT_RGMII_MODE);
1010         val &= ~(MAC_RGMII_MODE_RX_INT_B |
1011                  MAC_RGMII_MODE_RX_QUALITY |
1012                  MAC_RGMII_MODE_RX_ACTIVITY |
1013                  MAC_RGMII_MODE_RX_ENG_DET |
1014                  MAC_RGMII_MODE_TX_ENABLE |
1015                  MAC_RGMII_MODE_TX_LOWPWR |
1016                  MAC_RGMII_MODE_TX_RESET);
1017         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
1018                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1019                         val |= MAC_RGMII_MODE_RX_INT_B |
1020                                MAC_RGMII_MODE_RX_QUALITY |
1021                                MAC_RGMII_MODE_RX_ACTIVITY |
1022                                MAC_RGMII_MODE_RX_ENG_DET;
1023                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1024                         val |= MAC_RGMII_MODE_TX_ENABLE |
1025                                MAC_RGMII_MODE_TX_LOWPWR |
1026                                MAC_RGMII_MODE_TX_RESET;
1027         }
1028         tw32(MAC_EXT_RGMII_MODE, val);
1029 }
1030
1031 static void tg3_mdio_start(struct tg3 *tp)
1032 {
1033         tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1034         tw32_f(MAC_MI_MODE, tp->mi_mode);
1035         udelay(80);
1036
1037         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
1038                 u32 funcnum, is_serdes;
1039
1040                 funcnum = tr32(TG3_CPMU_STATUS) & TG3_CPMU_STATUS_PCIE_FUNC;
1041                 if (funcnum)
1042                         tp->phy_addr = 2;
1043                 else
1044                         tp->phy_addr = 1;
1045
1046                 if (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
1047                         is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1048                 else
1049                         is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1050                                     TG3_CPMU_PHY_STRAP_IS_SERDES;
1051                 if (is_serdes)
1052                         tp->phy_addr += 7;
1053         } else
1054                 tp->phy_addr = TG3_PHY_MII_ADDR;
1055
1056         if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
1057             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1058                 tg3_mdio_config_5785(tp);
1059 }
1060
1061 static int tg3_mdio_init(struct tg3 *tp)
1062 {
1063         int i;
1064         u32 reg;
1065         struct phy_device *phydev;
1066
1067         tg3_mdio_start(tp);
1068
1069         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1070             (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1071                 return 0;
1072
1073         tp->mdio_bus = mdiobus_alloc();
1074         if (tp->mdio_bus == NULL)
1075                 return -ENOMEM;
1076
1077         tp->mdio_bus->name     = "tg3 mdio bus";
1078         snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1079                  (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1080         tp->mdio_bus->priv     = tp;
1081         tp->mdio_bus->parent   = &tp->pdev->dev;
1082         tp->mdio_bus->read     = &tg3_mdio_read;
1083         tp->mdio_bus->write    = &tg3_mdio_write;
1084         tp->mdio_bus->reset    = &tg3_mdio_reset;
1085         tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
1086         tp->mdio_bus->irq      = &tp->mdio_irq[0];
1087
1088         for (i = 0; i < PHY_MAX_ADDR; i++)
1089                 tp->mdio_bus->irq[i] = PHY_POLL;
1090
1091         /* The bus registration will look for all the PHYs on the mdio bus.
1092          * Unfortunately, it does not ensure the PHY is powered up before
1093          * accessing the PHY ID registers.  A chip reset is the
1094          * quickest way to bring the device back to an operational state..
1095          */
1096         if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1097                 tg3_bmcr_reset(tp);
1098
1099         i = mdiobus_register(tp->mdio_bus);
1100         if (i) {
1101                 printk(KERN_WARNING "%s: mdiobus_reg failed (0x%x)\n",
1102                         tp->dev->name, i);
1103                 mdiobus_free(tp->mdio_bus);
1104                 return i;
1105         }
1106
1107         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1108
1109         if (!phydev || !phydev->drv) {
1110                 printk(KERN_WARNING "%s: No PHY devices\n", tp->dev->name);
1111                 mdiobus_unregister(tp->mdio_bus);
1112                 mdiobus_free(tp->mdio_bus);
1113                 return -ENODEV;
1114         }
1115
1116         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1117         case TG3_PHY_ID_BCM57780:
1118                 phydev->interface = PHY_INTERFACE_MODE_GMII;
1119                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1120                 break;
1121         case TG3_PHY_ID_BCM50610:
1122         case TG3_PHY_ID_BCM50610M:
1123                 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
1124                                      PHY_BRCM_RX_REFCLK_UNUSED |
1125                                      PHY_BRCM_DIS_TXCRXC_NOENRGY |
1126                                      PHY_BRCM_AUTO_PWRDWN_ENABLE;
1127                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)
1128                         phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1129                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1130                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1131                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1132                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1133                 /* fallthru */
1134         case TG3_PHY_ID_RTL8211C:
1135                 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1136                 break;
1137         case TG3_PHY_ID_RTL8201E:
1138         case TG3_PHY_ID_BCMAC131:
1139                 phydev->interface = PHY_INTERFACE_MODE_MII;
1140                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1141                 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
1142                 break;
1143         }
1144
1145         tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1146
1147         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1148                 tg3_mdio_config_5785(tp);
1149
1150         return 0;
1151 }
1152
1153 static void tg3_mdio_fini(struct tg3 *tp)
1154 {
1155         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1156                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
1157                 mdiobus_unregister(tp->mdio_bus);
1158                 mdiobus_free(tp->mdio_bus);
1159         }
1160 }
1161
1162 /* tp->lock is held. */
1163 static inline void tg3_generate_fw_event(struct tg3 *tp)
1164 {
1165         u32 val;
1166
1167         val = tr32(GRC_RX_CPU_EVENT);
1168         val |= GRC_RX_CPU_DRIVER_EVENT;
1169         tw32_f(GRC_RX_CPU_EVENT, val);
1170
1171         tp->last_event_jiffies = jiffies;
1172 }
1173
1174 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1175
1176 /* tp->lock is held. */
1177 static void tg3_wait_for_event_ack(struct tg3 *tp)
1178 {
1179         int i;
1180         unsigned int delay_cnt;
1181         long time_remain;
1182
1183         /* If enough time has passed, no wait is necessary. */
1184         time_remain = (long)(tp->last_event_jiffies + 1 +
1185                       usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1186                       (long)jiffies;
1187         if (time_remain < 0)
1188                 return;
1189
1190         /* Check if we can shorten the wait time. */
1191         delay_cnt = jiffies_to_usecs(time_remain);
1192         if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1193                 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1194         delay_cnt = (delay_cnt >> 3) + 1;
1195
1196         for (i = 0; i < delay_cnt; i++) {
1197                 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1198                         break;
1199                 udelay(8);
1200         }
1201 }
1202
1203 /* tp->lock is held. */
1204 static void tg3_ump_link_report(struct tg3 *tp)
1205 {
1206         u32 reg;
1207         u32 val;
1208
1209         if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1210             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
1211                 return;
1212
1213         tg3_wait_for_event_ack(tp);
1214
1215         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1216
1217         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1218
1219         val = 0;
1220         if (!tg3_readphy(tp, MII_BMCR, &reg))
1221                 val = reg << 16;
1222         if (!tg3_readphy(tp, MII_BMSR, &reg))
1223                 val |= (reg & 0xffff);
1224         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1225
1226         val = 0;
1227         if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1228                 val = reg << 16;
1229         if (!tg3_readphy(tp, MII_LPA, &reg))
1230                 val |= (reg & 0xffff);
1231         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1232
1233         val = 0;
1234         if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
1235                 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1236                         val = reg << 16;
1237                 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1238                         val |= (reg & 0xffff);
1239         }
1240         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1241
1242         if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1243                 val = reg << 16;
1244         else
1245                 val = 0;
1246         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1247
1248         tg3_generate_fw_event(tp);
1249 }
1250
1251 static void tg3_link_report(struct tg3 *tp)
1252 {
1253         if (!netif_carrier_ok(tp->dev)) {
1254                 if (netif_msg_link(tp))
1255                         printk(KERN_INFO PFX "%s: Link is down.\n",
1256                                tp->dev->name);
1257                 tg3_ump_link_report(tp);
1258         } else if (netif_msg_link(tp)) {
1259                 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1260                        tp->dev->name,
1261                        (tp->link_config.active_speed == SPEED_1000 ?
1262                         1000 :
1263                         (tp->link_config.active_speed == SPEED_100 ?
1264                          100 : 10)),
1265                        (tp->link_config.active_duplex == DUPLEX_FULL ?
1266                         "full" : "half"));
1267
1268                 printk(KERN_INFO PFX
1269                        "%s: Flow control is %s for TX and %s for RX.\n",
1270                        tp->dev->name,
1271                        (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1272                        "on" : "off",
1273                        (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1274                        "on" : "off");
1275                 tg3_ump_link_report(tp);
1276         }
1277 }
1278
1279 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1280 {
1281         u16 miireg;
1282
1283         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1284                 miireg = ADVERTISE_PAUSE_CAP;
1285         else if (flow_ctrl & FLOW_CTRL_TX)
1286                 miireg = ADVERTISE_PAUSE_ASYM;
1287         else if (flow_ctrl & FLOW_CTRL_RX)
1288                 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1289         else
1290                 miireg = 0;
1291
1292         return miireg;
1293 }
1294
1295 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1296 {
1297         u16 miireg;
1298
1299         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1300                 miireg = ADVERTISE_1000XPAUSE;
1301         else if (flow_ctrl & FLOW_CTRL_TX)
1302                 miireg = ADVERTISE_1000XPSE_ASYM;
1303         else if (flow_ctrl & FLOW_CTRL_RX)
1304                 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1305         else
1306                 miireg = 0;
1307
1308         return miireg;
1309 }
1310
1311 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1312 {
1313         u8 cap = 0;
1314
1315         if (lcladv & ADVERTISE_1000XPAUSE) {
1316                 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1317                         if (rmtadv & LPA_1000XPAUSE)
1318                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1319                         else if (rmtadv & LPA_1000XPAUSE_ASYM)
1320                                 cap = FLOW_CTRL_RX;
1321                 } else {
1322                         if (rmtadv & LPA_1000XPAUSE)
1323                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1324                 }
1325         } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1326                 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1327                         cap = FLOW_CTRL_TX;
1328         }
1329
1330         return cap;
1331 }
1332
1333 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1334 {
1335         u8 autoneg;
1336         u8 flowctrl = 0;
1337         u32 old_rx_mode = tp->rx_mode;
1338         u32 old_tx_mode = tp->tx_mode;
1339
1340         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
1341                 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
1342         else
1343                 autoneg = tp->link_config.autoneg;
1344
1345         if (autoneg == AUTONEG_ENABLE &&
1346             (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1347                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1348                         flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1349                 else
1350                         flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1351         } else
1352                 flowctrl = tp->link_config.flowctrl;
1353
1354         tp->link_config.active_flowctrl = flowctrl;
1355
1356         if (flowctrl & FLOW_CTRL_RX)
1357                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1358         else
1359                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1360
1361         if (old_rx_mode != tp->rx_mode)
1362                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1363
1364         if (flowctrl & FLOW_CTRL_TX)
1365                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1366         else
1367                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1368
1369         if (old_tx_mode != tp->tx_mode)
1370                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1371 }
1372
1373 static void tg3_adjust_link(struct net_device *dev)
1374 {
1375         u8 oldflowctrl, linkmesg = 0;
1376         u32 mac_mode, lcl_adv, rmt_adv;
1377         struct tg3 *tp = netdev_priv(dev);
1378         struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1379
1380         spin_lock_bh(&tp->lock);
1381
1382         mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1383                                     MAC_MODE_HALF_DUPLEX);
1384
1385         oldflowctrl = tp->link_config.active_flowctrl;
1386
1387         if (phydev->link) {
1388                 lcl_adv = 0;
1389                 rmt_adv = 0;
1390
1391                 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1392                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1393                 else if (phydev->speed == SPEED_1000 ||
1394                          GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
1395                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
1396                 else
1397                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1398
1399                 if (phydev->duplex == DUPLEX_HALF)
1400                         mac_mode |= MAC_MODE_HALF_DUPLEX;
1401                 else {
1402                         lcl_adv = tg3_advert_flowctrl_1000T(
1403                                   tp->link_config.flowctrl);
1404
1405                         if (phydev->pause)
1406                                 rmt_adv = LPA_PAUSE_CAP;
1407                         if (phydev->asym_pause)
1408                                 rmt_adv |= LPA_PAUSE_ASYM;
1409                 }
1410
1411                 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1412         } else
1413                 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1414
1415         if (mac_mode != tp->mac_mode) {
1416                 tp->mac_mode = mac_mode;
1417                 tw32_f(MAC_MODE, tp->mac_mode);
1418                 udelay(40);
1419         }
1420
1421         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1422                 if (phydev->speed == SPEED_10)
1423                         tw32(MAC_MI_STAT,
1424                              MAC_MI_STAT_10MBPS_MODE |
1425                              MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1426                 else
1427                         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1428         }
1429
1430         if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1431                 tw32(MAC_TX_LENGTHS,
1432                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1433                       (6 << TX_LENGTHS_IPG_SHIFT) |
1434                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1435         else
1436                 tw32(MAC_TX_LENGTHS,
1437                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1438                       (6 << TX_LENGTHS_IPG_SHIFT) |
1439                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1440
1441         if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1442             (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1443             phydev->speed != tp->link_config.active_speed ||
1444             phydev->duplex != tp->link_config.active_duplex ||
1445             oldflowctrl != tp->link_config.active_flowctrl)
1446             linkmesg = 1;
1447
1448         tp->link_config.active_speed = phydev->speed;
1449         tp->link_config.active_duplex = phydev->duplex;
1450
1451         spin_unlock_bh(&tp->lock);
1452
1453         if (linkmesg)
1454                 tg3_link_report(tp);
1455 }
1456
1457 static int tg3_phy_init(struct tg3 *tp)
1458 {
1459         struct phy_device *phydev;
1460
1461         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
1462                 return 0;
1463
1464         /* Bring the PHY back to a known state. */
1465         tg3_bmcr_reset(tp);
1466
1467         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1468
1469         /* Attach the MAC to the PHY. */
1470         phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1471                              phydev->dev_flags, phydev->interface);
1472         if (IS_ERR(phydev)) {
1473                 printk(KERN_ERR "%s: Could not attach to PHY\n", tp->dev->name);
1474                 return PTR_ERR(phydev);
1475         }
1476
1477         /* Mask with MAC supported features. */
1478         switch (phydev->interface) {
1479         case PHY_INTERFACE_MODE_GMII:
1480         case PHY_INTERFACE_MODE_RGMII:
1481                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1482                         phydev->supported &= (PHY_GBIT_FEATURES |
1483                                               SUPPORTED_Pause |
1484                                               SUPPORTED_Asym_Pause);
1485                         break;
1486                 }
1487                 /* fallthru */
1488         case PHY_INTERFACE_MODE_MII:
1489                 phydev->supported &= (PHY_BASIC_FEATURES |
1490                                       SUPPORTED_Pause |
1491                                       SUPPORTED_Asym_Pause);
1492                 break;
1493         default:
1494                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1495                 return -EINVAL;
1496         }
1497
1498         tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED;
1499
1500         phydev->advertising = phydev->supported;
1501
1502         return 0;
1503 }
1504
1505 static void tg3_phy_start(struct tg3 *tp)
1506 {
1507         struct phy_device *phydev;
1508
1509         if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1510                 return;
1511
1512         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1513
1514         if (tp->link_config.phy_is_low_power) {
1515                 tp->link_config.phy_is_low_power = 0;
1516                 phydev->speed = tp->link_config.orig_speed;
1517                 phydev->duplex = tp->link_config.orig_duplex;
1518                 phydev->autoneg = tp->link_config.orig_autoneg;
1519                 phydev->advertising = tp->link_config.orig_advertising;
1520         }
1521
1522         phy_start(phydev);
1523
1524         phy_start_aneg(phydev);
1525 }
1526
1527 static void tg3_phy_stop(struct tg3 *tp)
1528 {
1529         if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1530                 return;
1531
1532         phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1533 }
1534
1535 static void tg3_phy_fini(struct tg3 *tp)
1536 {
1537         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
1538                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1539                 tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED;
1540         }
1541 }
1542
1543 static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1544 {
1545         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1546         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1547 }
1548
1549 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1550 {
1551         u32 phytest;
1552
1553         if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1554                 u32 phy;
1555
1556                 tg3_writephy(tp, MII_TG3_FET_TEST,
1557                              phytest | MII_TG3_FET_SHADOW_EN);
1558                 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1559                         if (enable)
1560                                 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1561                         else
1562                                 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1563                         tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1564                 }
1565                 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1566         }
1567 }
1568
1569 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1570 {
1571         u32 reg;
1572
1573         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1574                 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
1575              (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
1576                 return;
1577
1578         if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1579                 tg3_phy_fet_toggle_apd(tp, enable);
1580                 return;
1581         }
1582
1583         reg = MII_TG3_MISC_SHDW_WREN |
1584               MII_TG3_MISC_SHDW_SCR5_SEL |
1585               MII_TG3_MISC_SHDW_SCR5_LPED |
1586               MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1587               MII_TG3_MISC_SHDW_SCR5_SDTL |
1588               MII_TG3_MISC_SHDW_SCR5_C125OE;
1589         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1590                 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1591
1592         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1593
1594
1595         reg = MII_TG3_MISC_SHDW_WREN |
1596               MII_TG3_MISC_SHDW_APD_SEL |
1597               MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1598         if (enable)
1599                 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1600
1601         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1602 }
1603
1604 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1605 {
1606         u32 phy;
1607
1608         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1609             (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1610                 return;
1611
1612         if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1613                 u32 ephy;
1614
1615                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1616                         u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1617
1618                         tg3_writephy(tp, MII_TG3_FET_TEST,
1619                                      ephy | MII_TG3_FET_SHADOW_EN);
1620                         if (!tg3_readphy(tp, reg, &phy)) {
1621                                 if (enable)
1622                                         phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1623                                 else
1624                                         phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1625                                 tg3_writephy(tp, reg, phy);
1626                         }
1627                         tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
1628                 }
1629         } else {
1630                 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1631                       MII_TG3_AUXCTL_SHDWSEL_MISC;
1632                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1633                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1634                         if (enable)
1635                                 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1636                         else
1637                                 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1638                         phy |= MII_TG3_AUXCTL_MISC_WREN;
1639                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1640                 }
1641         }
1642 }
1643
1644 static void tg3_phy_set_wirespeed(struct tg3 *tp)
1645 {
1646         u32 val;
1647
1648         if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
1649                 return;
1650
1651         if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1652             !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1653                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1654                              (val | (1 << 15) | (1 << 4)));
1655 }
1656
1657 static void tg3_phy_apply_otp(struct tg3 *tp)
1658 {
1659         u32 otp, phy;
1660
1661         if (!tp->phy_otp)
1662                 return;
1663
1664         otp = tp->phy_otp;
1665
1666         /* Enable SM_DSP clock and tx 6dB coding. */
1667         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1668               MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1669               MII_TG3_AUXCTL_ACTL_TX_6DB;
1670         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1671
1672         phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1673         phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1674         tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1675
1676         phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1677               ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1678         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1679
1680         phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1681         phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1682         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1683
1684         phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1685         tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1686
1687         phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1688         tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1689
1690         phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1691               ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1692         tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1693
1694         /* Turn off SM_DSP clock. */
1695         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1696               MII_TG3_AUXCTL_ACTL_TX_6DB;
1697         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1698 }
1699
1700 static int tg3_wait_macro_done(struct tg3 *tp)
1701 {
1702         int limit = 100;
1703
1704         while (limit--) {
1705                 u32 tmp32;
1706
1707                 if (!tg3_readphy(tp, 0x16, &tmp32)) {
1708                         if ((tmp32 & 0x1000) == 0)
1709                                 break;
1710                 }
1711         }
1712         if (limit < 0)
1713                 return -EBUSY;
1714
1715         return 0;
1716 }
1717
1718 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1719 {
1720         static const u32 test_pat[4][6] = {
1721         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1722         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1723         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1724         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1725         };
1726         int chan;
1727
1728         for (chan = 0; chan < 4; chan++) {
1729                 int i;
1730
1731                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1732                              (chan * 0x2000) | 0x0200);
1733                 tg3_writephy(tp, 0x16, 0x0002);
1734
1735                 for (i = 0; i < 6; i++)
1736                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1737                                      test_pat[chan][i]);
1738
1739                 tg3_writephy(tp, 0x16, 0x0202);
1740                 if (tg3_wait_macro_done(tp)) {
1741                         *resetp = 1;
1742                         return -EBUSY;
1743                 }
1744
1745                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1746                              (chan * 0x2000) | 0x0200);
1747                 tg3_writephy(tp, 0x16, 0x0082);
1748                 if (tg3_wait_macro_done(tp)) {
1749                         *resetp = 1;
1750                         return -EBUSY;
1751                 }
1752
1753                 tg3_writephy(tp, 0x16, 0x0802);
1754                 if (tg3_wait_macro_done(tp)) {
1755                         *resetp = 1;
1756                         return -EBUSY;
1757                 }
1758
1759                 for (i = 0; i < 6; i += 2) {
1760                         u32 low, high;
1761
1762                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1763                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1764                             tg3_wait_macro_done(tp)) {
1765                                 *resetp = 1;
1766                                 return -EBUSY;
1767                         }
1768                         low &= 0x7fff;
1769                         high &= 0x000f;
1770                         if (low != test_pat[chan][i] ||
1771                             high != test_pat[chan][i+1]) {
1772                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1773                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1774                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1775
1776                                 return -EBUSY;
1777                         }
1778                 }
1779         }
1780
1781         return 0;
1782 }
1783
1784 static int tg3_phy_reset_chanpat(struct tg3 *tp)
1785 {
1786         int chan;
1787
1788         for (chan = 0; chan < 4; chan++) {
1789                 int i;
1790
1791                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1792                              (chan * 0x2000) | 0x0200);
1793                 tg3_writephy(tp, 0x16, 0x0002);
1794                 for (i = 0; i < 6; i++)
1795                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1796                 tg3_writephy(tp, 0x16, 0x0202);
1797                 if (tg3_wait_macro_done(tp))
1798                         return -EBUSY;
1799         }
1800
1801         return 0;
1802 }
1803
1804 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1805 {
1806         u32 reg32, phy9_orig;
1807         int retries, do_phy_reset, err;
1808
1809         retries = 10;
1810         do_phy_reset = 1;
1811         do {
1812                 if (do_phy_reset) {
1813                         err = tg3_bmcr_reset(tp);
1814                         if (err)
1815                                 return err;
1816                         do_phy_reset = 0;
1817                 }
1818
1819                 /* Disable transmitter and interrupt.  */
1820                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1821                         continue;
1822
1823                 reg32 |= 0x3000;
1824                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1825
1826                 /* Set full-duplex, 1000 mbps.  */
1827                 tg3_writephy(tp, MII_BMCR,
1828                              BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1829
1830                 /* Set to master mode.  */
1831                 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1832                         continue;
1833
1834                 tg3_writephy(tp, MII_TG3_CTRL,
1835                              (MII_TG3_CTRL_AS_MASTER |
1836                               MII_TG3_CTRL_ENABLE_AS_MASTER));
1837
1838                 /* Enable SM_DSP_CLOCK and 6dB.  */
1839                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1840
1841                 /* Block the PHY control access.  */
1842                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1843                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
1844
1845                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1846                 if (!err)
1847                         break;
1848         } while (--retries);
1849
1850         err = tg3_phy_reset_chanpat(tp);
1851         if (err)
1852                 return err;
1853
1854         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1855         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
1856
1857         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1858         tg3_writephy(tp, 0x16, 0x0000);
1859
1860         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1861             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1862                 /* Set Extended packet length bit for jumbo frames */
1863                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1864         }
1865         else {
1866                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1867         }
1868
1869         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1870
1871         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1872                 reg32 &= ~0x3000;
1873                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1874         } else if (!err)
1875                 err = -EBUSY;
1876
1877         return err;
1878 }
1879
1880 /* This will reset the tigon3 PHY if there is no valid
1881  * link unless the FORCE argument is non-zero.
1882  */
1883 static int tg3_phy_reset(struct tg3 *tp)
1884 {
1885         u32 cpmuctrl;
1886         u32 phy_status;
1887         int err;
1888
1889         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1890                 u32 val;
1891
1892                 val = tr32(GRC_MISC_CFG);
1893                 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1894                 udelay(40);
1895         }
1896         err  = tg3_readphy(tp, MII_BMSR, &phy_status);
1897         err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1898         if (err != 0)
1899                 return -EBUSY;
1900
1901         if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1902                 netif_carrier_off(tp->dev);
1903                 tg3_link_report(tp);
1904         }
1905
1906         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1907             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1908             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1909                 err = tg3_phy_reset_5703_4_5(tp);
1910                 if (err)
1911                         return err;
1912                 goto out;
1913         }
1914
1915         cpmuctrl = 0;
1916         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1917             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1918                 cpmuctrl = tr32(TG3_CPMU_CTRL);
1919                 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1920                         tw32(TG3_CPMU_CTRL,
1921                              cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1922         }
1923
1924         err = tg3_bmcr_reset(tp);
1925         if (err)
1926                 return err;
1927
1928         if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1929                 u32 phy;
1930
1931                 phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1932                 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
1933
1934                 tw32(TG3_CPMU_CTRL, cpmuctrl);
1935         }
1936
1937         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
1938             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
1939                 u32 val;
1940
1941                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1942                 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1943                     CPMU_LSPD_1000MB_MACCLK_12_5) {
1944                         val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1945                         udelay(40);
1946                         tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1947                 }
1948         }
1949
1950         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
1951             (tp->tg3_flags2 & TG3_FLG2_MII_SERDES))
1952                 return 0;
1953
1954         tg3_phy_apply_otp(tp);
1955
1956         if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
1957                 tg3_phy_toggle_apd(tp, true);
1958         else
1959                 tg3_phy_toggle_apd(tp, false);
1960
1961 out:
1962         if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1963                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1964                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1965                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1966                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1967                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1968                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1969         }
1970         if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1971                 tg3_writephy(tp, 0x1c, 0x8d68);
1972                 tg3_writephy(tp, 0x1c, 0x8d68);
1973         }
1974         if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1975                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1976                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1977                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1978                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1979                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1980                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1981                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1982                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1983         }
1984         else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1985                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1986                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1987                 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1988                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1989                         tg3_writephy(tp, MII_TG3_TEST1,
1990                                      MII_TG3_TEST1_TRIM_EN | 0x4);
1991                 } else
1992                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
1993                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1994         }
1995         /* Set Extended packet length bit (bit 14) on all chips that */
1996         /* support jumbo frames */
1997         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1998                 /* Cannot do read-modify-write on 5401 */
1999                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2000         } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2001                 u32 phy_reg;
2002
2003                 /* Set bit 14 with read-modify-write to preserve other bits */
2004                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
2005                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
2006                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
2007         }
2008
2009         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2010          * jumbo frames transmission.
2011          */
2012         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2013                 u32 phy_reg;
2014
2015                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
2016                     tg3_writephy(tp, MII_TG3_EXT_CTRL,
2017                                  phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
2018         }
2019
2020         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2021                 /* adjust output voltage */
2022                 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
2023         }
2024
2025         tg3_phy_toggle_automdix(tp, 1);
2026         tg3_phy_set_wirespeed(tp);
2027         return 0;
2028 }
2029
2030 static void tg3_frob_aux_power(struct tg3 *tp)
2031 {
2032         struct tg3 *tp_peer = tp;
2033
2034         /* The GPIOs do something completely different on 57765. */
2035         if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0 ||
2036             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
2037                 return;
2038
2039         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2040             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
2041             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
2042                 struct net_device *dev_peer;
2043
2044                 dev_peer = pci_get_drvdata(tp->pdev_peer);
2045                 /* remove_one() may have been run on the peer. */
2046                 if (!dev_peer)
2047                         tp_peer = tp;
2048                 else
2049                         tp_peer = netdev_priv(dev_peer);
2050         }
2051
2052         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2053             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
2054             (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2055             (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
2056                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2057                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2058                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2059                                     (GRC_LCLCTRL_GPIO_OE0 |
2060                                      GRC_LCLCTRL_GPIO_OE1 |
2061                                      GRC_LCLCTRL_GPIO_OE2 |
2062                                      GRC_LCLCTRL_GPIO_OUTPUT0 |
2063                                      GRC_LCLCTRL_GPIO_OUTPUT1),
2064                                     100);
2065                 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2066                            tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2067                         /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2068                         u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2069                                              GRC_LCLCTRL_GPIO_OE1 |
2070                                              GRC_LCLCTRL_GPIO_OE2 |
2071                                              GRC_LCLCTRL_GPIO_OUTPUT0 |
2072                                              GRC_LCLCTRL_GPIO_OUTPUT1 |
2073                                              tp->grc_local_ctrl;
2074                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2075
2076                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2077                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2078
2079                         grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2080                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2081                 } else {
2082                         u32 no_gpio2;
2083                         u32 grc_local_ctrl = 0;
2084
2085                         if (tp_peer != tp &&
2086                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2087                                 return;
2088
2089                         /* Workaround to prevent overdrawing Amps. */
2090                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2091                             ASIC_REV_5714) {
2092                                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2093                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2094                                             grc_local_ctrl, 100);
2095                         }
2096
2097                         /* On 5753 and variants, GPIO2 cannot be used. */
2098                         no_gpio2 = tp->nic_sram_data_cfg &
2099                                     NIC_SRAM_DATA_CFG_NO_GPIO2;
2100
2101                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2102                                          GRC_LCLCTRL_GPIO_OE1 |
2103                                          GRC_LCLCTRL_GPIO_OE2 |
2104                                          GRC_LCLCTRL_GPIO_OUTPUT1 |
2105                                          GRC_LCLCTRL_GPIO_OUTPUT2;
2106                         if (no_gpio2) {
2107                                 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2108                                                     GRC_LCLCTRL_GPIO_OUTPUT2);
2109                         }
2110                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2111                                                     grc_local_ctrl, 100);
2112
2113                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2114
2115                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2116                                                     grc_local_ctrl, 100);
2117
2118                         if (!no_gpio2) {
2119                                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2120                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2121                                             grc_local_ctrl, 100);
2122                         }
2123                 }
2124         } else {
2125                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2126                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2127                         if (tp_peer != tp &&
2128                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2129                                 return;
2130
2131                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2132                                     (GRC_LCLCTRL_GPIO_OE1 |
2133                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2134
2135                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2136                                     GRC_LCLCTRL_GPIO_OE1, 100);
2137
2138                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2139                                     (GRC_LCLCTRL_GPIO_OE1 |
2140                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2141                 }
2142         }
2143 }
2144
2145 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2146 {
2147         if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2148                 return 1;
2149         else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) {
2150                 if (speed != SPEED_10)
2151                         return 1;
2152         } else if (speed == SPEED_10)
2153                 return 1;
2154
2155         return 0;
2156 }
2157
2158 static int tg3_setup_phy(struct tg3 *, int);
2159
2160 #define RESET_KIND_SHUTDOWN     0
2161 #define RESET_KIND_INIT         1
2162 #define RESET_KIND_SUSPEND      2
2163
2164 static void tg3_write_sig_post_reset(struct tg3 *, int);
2165 static int tg3_halt_cpu(struct tg3 *, u32);
2166
2167 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2168 {
2169         u32 val;
2170
2171         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2172                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2173                         u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2174                         u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2175
2176                         sg_dig_ctrl |=
2177                                 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2178                         tw32(SG_DIG_CTRL, sg_dig_ctrl);
2179                         tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2180                 }
2181                 return;
2182         }
2183
2184         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2185                 tg3_bmcr_reset(tp);
2186                 val = tr32(GRC_MISC_CFG);
2187                 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2188                 udelay(40);
2189                 return;
2190         } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
2191                 u32 phytest;
2192                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2193                         u32 phy;
2194
2195                         tg3_writephy(tp, MII_ADVERTISE, 0);
2196                         tg3_writephy(tp, MII_BMCR,
2197                                      BMCR_ANENABLE | BMCR_ANRESTART);
2198
2199                         tg3_writephy(tp, MII_TG3_FET_TEST,
2200                                      phytest | MII_TG3_FET_SHADOW_EN);
2201                         if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2202                                 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2203                                 tg3_writephy(tp,
2204                                              MII_TG3_FET_SHDW_AUXMODE4,
2205                                              phy);
2206                         }
2207                         tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2208                 }
2209                 return;
2210         } else if (do_low_power) {
2211                 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2212                              MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2213
2214                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2215                              MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2216                              MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2217                              MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2218                              MII_TG3_AUXCTL_PCTL_VREG_11V);
2219         }
2220
2221         /* The PHY should not be powered down on some chips because
2222          * of bugs.
2223          */
2224         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2225             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2226             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2227              (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
2228                 return;
2229
2230         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2231             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2232                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2233                 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2234                 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2235                 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2236         }
2237
2238         tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2239 }
2240
2241 /* tp->lock is held. */
2242 static int tg3_nvram_lock(struct tg3 *tp)
2243 {
2244         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2245                 int i;
2246
2247                 if (tp->nvram_lock_cnt == 0) {
2248                         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2249                         for (i = 0; i < 8000; i++) {
2250                                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2251                                         break;
2252                                 udelay(20);
2253                         }
2254                         if (i == 8000) {
2255                                 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2256                                 return -ENODEV;
2257                         }
2258                 }
2259                 tp->nvram_lock_cnt++;
2260         }
2261         return 0;
2262 }
2263
2264 /* tp->lock is held. */
2265 static void tg3_nvram_unlock(struct tg3 *tp)
2266 {
2267         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2268                 if (tp->nvram_lock_cnt > 0)
2269                         tp->nvram_lock_cnt--;
2270                 if (tp->nvram_lock_cnt == 0)
2271                         tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2272         }
2273 }
2274
2275 /* tp->lock is held. */
2276 static void tg3_enable_nvram_access(struct tg3 *tp)
2277 {
2278         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2279             !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2280                 u32 nvaccess = tr32(NVRAM_ACCESS);
2281
2282                 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2283         }
2284 }
2285
2286 /* tp->lock is held. */
2287 static void tg3_disable_nvram_access(struct tg3 *tp)
2288 {
2289         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2290             !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2291                 u32 nvaccess = tr32(NVRAM_ACCESS);
2292
2293                 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2294         }
2295 }
2296
2297 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2298                                         u32 offset, u32 *val)
2299 {
2300         u32 tmp;
2301         int i;
2302
2303         if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2304                 return -EINVAL;
2305
2306         tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2307                                         EEPROM_ADDR_DEVID_MASK |
2308                                         EEPROM_ADDR_READ);
2309         tw32(GRC_EEPROM_ADDR,
2310              tmp |
2311              (0 << EEPROM_ADDR_DEVID_SHIFT) |
2312              ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2313               EEPROM_ADDR_ADDR_MASK) |
2314              EEPROM_ADDR_READ | EEPROM_ADDR_START);
2315
2316         for (i = 0; i < 1000; i++) {
2317                 tmp = tr32(GRC_EEPROM_ADDR);
2318
2319                 if (tmp & EEPROM_ADDR_COMPLETE)
2320                         break;
2321                 msleep(1);
2322         }
2323         if (!(tmp & EEPROM_ADDR_COMPLETE))
2324                 return -EBUSY;
2325
2326         tmp = tr32(GRC_EEPROM_DATA);
2327
2328         /*
2329          * The data will always be opposite the native endian
2330          * format.  Perform a blind byteswap to compensate.
2331          */
2332         *val = swab32(tmp);
2333
2334         return 0;
2335 }
2336
2337 #define NVRAM_CMD_TIMEOUT 10000
2338
2339 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2340 {
2341         int i;
2342
2343         tw32(NVRAM_CMD, nvram_cmd);
2344         for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2345                 udelay(10);
2346                 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2347                         udelay(10);
2348                         break;
2349                 }
2350         }
2351
2352         if (i == NVRAM_CMD_TIMEOUT)
2353                 return -EBUSY;
2354
2355         return 0;
2356 }
2357
2358 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2359 {
2360         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2361             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2362             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2363            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2364             (tp->nvram_jedecnum == JEDEC_ATMEL))
2365
2366                 addr = ((addr / tp->nvram_pagesize) <<
2367                         ATMEL_AT45DB0X1B_PAGE_POS) +
2368                        (addr % tp->nvram_pagesize);
2369
2370         return addr;
2371 }
2372
2373 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2374 {
2375         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2376             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2377             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2378            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2379             (tp->nvram_jedecnum == JEDEC_ATMEL))
2380
2381                 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2382                         tp->nvram_pagesize) +
2383                        (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2384
2385         return addr;
2386 }
2387
2388 /* NOTE: Data read in from NVRAM is byteswapped according to
2389  * the byteswapping settings for all other register accesses.
2390  * tg3 devices are BE devices, so on a BE machine, the data
2391  * returned will be exactly as it is seen in NVRAM.  On a LE
2392  * machine, the 32-bit value will be byteswapped.
2393  */
2394 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2395 {
2396         int ret;
2397
2398         if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2399                 return tg3_nvram_read_using_eeprom(tp, offset, val);
2400
2401         offset = tg3_nvram_phys_addr(tp, offset);
2402
2403         if (offset > NVRAM_ADDR_MSK)
2404                 return -EINVAL;
2405
2406         ret = tg3_nvram_lock(tp);
2407         if (ret)
2408                 return ret;
2409
2410         tg3_enable_nvram_access(tp);
2411
2412         tw32(NVRAM_ADDR, offset);
2413         ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2414                 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2415
2416         if (ret == 0)
2417                 *val = tr32(NVRAM_RDDATA);
2418
2419         tg3_disable_nvram_access(tp);
2420
2421         tg3_nvram_unlock(tp);
2422
2423         return ret;
2424 }
2425
2426 /* Ensures NVRAM data is in bytestream format. */
2427 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
2428 {
2429         u32 v;
2430         int res = tg3_nvram_read(tp, offset, &v);
2431         if (!res)
2432                 *val = cpu_to_be32(v);
2433         return res;
2434 }
2435
2436 /* tp->lock is held. */
2437 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2438 {
2439         u32 addr_high, addr_low;
2440         int i;
2441
2442         addr_high = ((tp->dev->dev_addr[0] << 8) |
2443                      tp->dev->dev_addr[1]);
2444         addr_low = ((tp->dev->dev_addr[2] << 24) |
2445                     (tp->dev->dev_addr[3] << 16) |
2446                     (tp->dev->dev_addr[4] <<  8) |
2447                     (tp->dev->dev_addr[5] <<  0));
2448         for (i = 0; i < 4; i++) {
2449                 if (i == 1 && skip_mac_1)
2450                         continue;
2451                 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2452                 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2453         }
2454
2455         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2456             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2457                 for (i = 0; i < 12; i++) {
2458                         tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2459                         tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2460                 }
2461         }
2462
2463         addr_high = (tp->dev->dev_addr[0] +
2464                      tp->dev->dev_addr[1] +
2465                      tp->dev->dev_addr[2] +
2466                      tp->dev->dev_addr[3] +
2467                      tp->dev->dev_addr[4] +
2468                      tp->dev->dev_addr[5]) &
2469                 TX_BACKOFF_SEED_MASK;
2470         tw32(MAC_TX_BACKOFF_SEED, addr_high);
2471 }
2472
2473 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
2474 {
2475         u32 misc_host_ctrl;
2476         bool device_should_wake, do_low_power;
2477
2478         /* Make sure register accesses (indirect or otherwise)
2479          * will function correctly.
2480          */
2481         pci_write_config_dword(tp->pdev,
2482                                TG3PCI_MISC_HOST_CTRL,
2483                                tp->misc_host_ctrl);
2484
2485         switch (state) {
2486         case PCI_D0:
2487                 pci_enable_wake(tp->pdev, state, false);
2488                 pci_set_power_state(tp->pdev, PCI_D0);
2489
2490                 /* Switch out of Vaux if it is a NIC */
2491                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
2492                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
2493
2494                 return 0;
2495
2496         case PCI_D1:
2497         case PCI_D2:
2498         case PCI_D3hot:
2499                 break;
2500
2501         default:
2502                 printk(KERN_ERR PFX "%s: Invalid power state (D%d) requested\n",
2503                         tp->dev->name, state);
2504                 return -EINVAL;
2505         }
2506
2507         /* Restore the CLKREQ setting. */
2508         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2509                 u16 lnkctl;
2510
2511                 pci_read_config_word(tp->pdev,
2512                                      tp->pcie_cap + PCI_EXP_LNKCTL,
2513                                      &lnkctl);
2514                 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2515                 pci_write_config_word(tp->pdev,
2516                                       tp->pcie_cap + PCI_EXP_LNKCTL,
2517                                       lnkctl);
2518         }
2519
2520         misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2521         tw32(TG3PCI_MISC_HOST_CTRL,
2522              misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2523
2524         device_should_wake = pci_pme_capable(tp->pdev, state) &&
2525                              device_may_wakeup(&tp->pdev->dev) &&
2526                              (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2527
2528         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
2529                 do_low_power = false;
2530                 if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) &&
2531                     !tp->link_config.phy_is_low_power) {
2532                         struct phy_device *phydev;
2533                         u32 phyid, advertising;
2534
2535                         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
2536
2537                         tp->link_config.phy_is_low_power = 1;
2538
2539                         tp->link_config.orig_speed = phydev->speed;
2540                         tp->link_config.orig_duplex = phydev->duplex;
2541                         tp->link_config.orig_autoneg = phydev->autoneg;
2542                         tp->link_config.orig_advertising = phydev->advertising;
2543
2544                         advertising = ADVERTISED_TP |
2545                                       ADVERTISED_Pause |
2546                                       ADVERTISED_Autoneg |
2547                                       ADVERTISED_10baseT_Half;
2548
2549                         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2550                             device_should_wake) {
2551                                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2552                                         advertising |=
2553                                                 ADVERTISED_100baseT_Half |
2554                                                 ADVERTISED_100baseT_Full |
2555                                                 ADVERTISED_10baseT_Full;
2556                                 else
2557                                         advertising |= ADVERTISED_10baseT_Full;
2558                         }
2559
2560                         phydev->advertising = advertising;
2561
2562                         phy_start_aneg(phydev);
2563
2564                         phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2565                         if (phyid != TG3_PHY_ID_BCMAC131) {
2566                                 phyid &= TG3_PHY_OUI_MASK;
2567                                 if (phyid == TG3_PHY_OUI_1 ||
2568                                     phyid == TG3_PHY_OUI_2 ||
2569                                     phyid == TG3_PHY_OUI_3)
2570                                         do_low_power = true;
2571                         }
2572                 }
2573         } else {
2574                 do_low_power = true;
2575
2576                 if (tp->link_config.phy_is_low_power == 0) {
2577                         tp->link_config.phy_is_low_power = 1;
2578                         tp->link_config.orig_speed = tp->link_config.speed;
2579                         tp->link_config.orig_duplex = tp->link_config.duplex;
2580                         tp->link_config.orig_autoneg = tp->link_config.autoneg;
2581                 }
2582
2583                 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
2584                         tp->link_config.speed = SPEED_10;
2585                         tp->link_config.duplex = DUPLEX_HALF;
2586                         tp->link_config.autoneg = AUTONEG_ENABLE;
2587                         tg3_setup_phy(tp, 0);
2588                 }
2589         }
2590
2591         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2592                 u32 val;
2593
2594                 val = tr32(GRC_VCPU_EXT_CTRL);
2595                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2596         } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2597                 int i;
2598                 u32 val;
2599
2600                 for (i = 0; i < 200; i++) {
2601                         tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2602                         if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2603                                 break;
2604                         msleep(1);
2605                 }
2606         }
2607         if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2608                 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2609                                                      WOL_DRV_STATE_SHUTDOWN |
2610                                                      WOL_DRV_WOL |
2611                                                      WOL_SET_MAGIC_PKT);
2612
2613         if (device_should_wake) {
2614                 u32 mac_mode;
2615
2616                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
2617                         if (do_low_power) {
2618                                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2619                                 udelay(40);
2620                         }
2621
2622                         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
2623                                 mac_mode = MAC_MODE_PORT_MODE_GMII;
2624                         else
2625                                 mac_mode = MAC_MODE_PORT_MODE_MII;
2626
2627                         mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2628                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2629                             ASIC_REV_5700) {
2630                                 u32 speed = (tp->tg3_flags &
2631                                              TG3_FLAG_WOL_SPEED_100MB) ?
2632                                              SPEED_100 : SPEED_10;
2633                                 if (tg3_5700_link_polarity(tp, speed))
2634                                         mac_mode |= MAC_MODE_LINK_POLARITY;
2635                                 else
2636                                         mac_mode &= ~MAC_MODE_LINK_POLARITY;
2637                         }
2638                 } else {
2639                         mac_mode = MAC_MODE_PORT_MODE_TBI;
2640                 }
2641
2642                 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
2643                         tw32(MAC_LED_CTRL, tp->led_ctrl);
2644
2645                 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2646                 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2647                     !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2648                     ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2649                      (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2650                         mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
2651
2652                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2653                         mac_mode |= tp->mac_mode &
2654                                     (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2655                         if (mac_mode & MAC_MODE_APE_TX_EN)
2656                                 mac_mode |= MAC_MODE_TDE_ENABLE;
2657                 }
2658
2659                 tw32_f(MAC_MODE, mac_mode);
2660                 udelay(100);
2661
2662                 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2663                 udelay(10);
2664         }
2665
2666         if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2667             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2668              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2669                 u32 base_val;
2670
2671                 base_val = tp->pci_clock_ctrl;
2672                 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2673                              CLOCK_CTRL_TXCLK_DISABLE);
2674
2675                 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2676                             CLOCK_CTRL_PWRDOWN_PLL133, 40);
2677         } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
2678                    (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
2679                    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
2680                 /* do nothing */
2681         } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2682                      (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2683                 u32 newbits1, newbits2;
2684
2685                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2686                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2687                         newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2688                                     CLOCK_CTRL_TXCLK_DISABLE |
2689                                     CLOCK_CTRL_ALTCLK);
2690                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2691                 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2692                         newbits1 = CLOCK_CTRL_625_CORE;
2693                         newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2694                 } else {
2695                         newbits1 = CLOCK_CTRL_ALTCLK;
2696                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2697                 }
2698
2699                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2700                             40);
2701
2702                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2703                             40);
2704
2705                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2706                         u32 newbits3;
2707
2708                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2709                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2710                                 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2711                                             CLOCK_CTRL_TXCLK_DISABLE |
2712                                             CLOCK_CTRL_44MHZ_CORE);
2713                         } else {
2714                                 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2715                         }
2716
2717                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
2718                                     tp->pci_clock_ctrl | newbits3, 40);
2719                 }
2720         }
2721
2722         if (!(device_should_wake) &&
2723             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
2724                 tg3_power_down_phy(tp, do_low_power);
2725
2726         tg3_frob_aux_power(tp);
2727
2728         /* Workaround for unstable PLL clock */
2729         if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2730             (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2731                 u32 val = tr32(0x7d00);
2732
2733                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2734                 tw32(0x7d00, val);
2735                 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2736                         int err;
2737
2738                         err = tg3_nvram_lock(tp);
2739                         tg3_halt_cpu(tp, RX_CPU_BASE);
2740                         if (!err)
2741                                 tg3_nvram_unlock(tp);
2742                 }
2743         }
2744
2745         tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2746
2747         if (device_should_wake)
2748                 pci_enable_wake(tp->pdev, state, true);
2749
2750         /* Finally, set the new power state. */
2751         pci_set_power_state(tp->pdev, state);
2752
2753         return 0;
2754 }
2755
2756 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2757 {
2758         switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2759         case MII_TG3_AUX_STAT_10HALF:
2760                 *speed = SPEED_10;
2761                 *duplex = DUPLEX_HALF;
2762                 break;
2763
2764         case MII_TG3_AUX_STAT_10FULL:
2765                 *speed = SPEED_10;
2766                 *duplex = DUPLEX_FULL;
2767                 break;
2768
2769         case MII_TG3_AUX_STAT_100HALF:
2770                 *speed = SPEED_100;
2771                 *duplex = DUPLEX_HALF;
2772                 break;
2773
2774         case MII_TG3_AUX_STAT_100FULL:
2775                 *speed = SPEED_100;
2776                 *duplex = DUPLEX_FULL;
2777                 break;
2778
2779         case MII_TG3_AUX_STAT_1000HALF:
2780                 *speed = SPEED_1000;
2781                 *duplex = DUPLEX_HALF;
2782                 break;
2783
2784         case MII_TG3_AUX_STAT_1000FULL:
2785                 *speed = SPEED_1000;
2786                 *duplex = DUPLEX_FULL;
2787                 break;
2788
2789         default:
2790                 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
2791                         *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2792                                  SPEED_10;
2793                         *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2794                                   DUPLEX_HALF;
2795                         break;
2796                 }
2797                 *speed = SPEED_INVALID;
2798                 *duplex = DUPLEX_INVALID;
2799                 break;
2800         }
2801 }
2802
2803 static void tg3_phy_copper_begin(struct tg3 *tp)
2804 {
2805         u32 new_adv;
2806         int i;
2807
2808         if (tp->link_config.phy_is_low_power) {
2809                 /* Entering low power mode.  Disable gigabit and
2810                  * 100baseT advertisements.
2811                  */
2812                 tg3_writephy(tp, MII_TG3_CTRL, 0);
2813
2814                 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2815                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2816                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2817                         new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2818
2819                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2820         } else if (tp->link_config.speed == SPEED_INVALID) {
2821                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2822                         tp->link_config.advertising &=
2823                                 ~(ADVERTISED_1000baseT_Half |
2824                                   ADVERTISED_1000baseT_Full);
2825
2826                 new_adv = ADVERTISE_CSMA;
2827                 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2828                         new_adv |= ADVERTISE_10HALF;
2829                 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2830                         new_adv |= ADVERTISE_10FULL;
2831                 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2832                         new_adv |= ADVERTISE_100HALF;
2833                 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2834                         new_adv |= ADVERTISE_100FULL;
2835
2836                 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2837
2838                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2839
2840                 if (tp->link_config.advertising &
2841                     (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2842                         new_adv = 0;
2843                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2844                                 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2845                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2846                                 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2847                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
2848                             (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2849                              tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2850                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2851                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2852                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2853                 } else {
2854                         tg3_writephy(tp, MII_TG3_CTRL, 0);
2855                 }
2856         } else {
2857                 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2858                 new_adv |= ADVERTISE_CSMA;
2859
2860                 /* Asking for a specific link mode. */
2861                 if (tp->link_config.speed == SPEED_1000) {
2862                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2863
2864                         if (tp->link_config.duplex == DUPLEX_FULL)
2865                                 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2866                         else
2867                                 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2868                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2869                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2870                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2871                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2872                 } else {
2873                         if (tp->link_config.speed == SPEED_100) {
2874                                 if (tp->link_config.duplex == DUPLEX_FULL)
2875                                         new_adv |= ADVERTISE_100FULL;
2876                                 else
2877                                         new_adv |= ADVERTISE_100HALF;
2878                         } else {
2879                                 if (tp->link_config.duplex == DUPLEX_FULL)
2880                                         new_adv |= ADVERTISE_10FULL;
2881                                 else
2882                                         new_adv |= ADVERTISE_10HALF;
2883                         }
2884                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2885
2886                         new_adv = 0;
2887                 }
2888
2889                 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2890         }
2891
2892         if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2893             tp->link_config.speed != SPEED_INVALID) {
2894                 u32 bmcr, orig_bmcr;
2895
2896                 tp->link_config.active_speed = tp->link_config.speed;
2897                 tp->link_config.active_duplex = tp->link_config.duplex;
2898
2899                 bmcr = 0;
2900                 switch (tp->link_config.speed) {
2901                 default:
2902                 case SPEED_10:
2903                         break;
2904
2905                 case SPEED_100:
2906                         bmcr |= BMCR_SPEED100;
2907                         break;
2908
2909                 case SPEED_1000:
2910                         bmcr |= TG3_BMCR_SPEED1000;
2911                         break;
2912                 }
2913
2914                 if (tp->link_config.duplex == DUPLEX_FULL)
2915                         bmcr |= BMCR_FULLDPLX;
2916
2917                 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2918                     (bmcr != orig_bmcr)) {
2919                         tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2920                         for (i = 0; i < 1500; i++) {
2921                                 u32 tmp;
2922
2923                                 udelay(10);
2924                                 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2925                                     tg3_readphy(tp, MII_BMSR, &tmp))
2926                                         continue;
2927                                 if (!(tmp & BMSR_LSTATUS)) {
2928                                         udelay(40);
2929                                         break;
2930                                 }
2931                         }
2932                         tg3_writephy(tp, MII_BMCR, bmcr);
2933                         udelay(40);
2934                 }
2935         } else {
2936                 tg3_writephy(tp, MII_BMCR,
2937                              BMCR_ANENABLE | BMCR_ANRESTART);
2938         }
2939 }
2940
2941 static int tg3_init_5401phy_dsp(struct tg3 *tp)
2942 {
2943         int err;
2944
2945         /* Turn off tap power management. */
2946         /* Set Extended packet length bit */
2947         err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2948
2949         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
2950         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
2951
2952         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
2953         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
2954
2955         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2956         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
2957
2958         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2959         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
2960
2961         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2962         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
2963
2964         udelay(40);
2965
2966         return err;
2967 }
2968
2969 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
2970 {
2971         u32 adv_reg, all_mask = 0;
2972
2973         if (mask & ADVERTISED_10baseT_Half)
2974                 all_mask |= ADVERTISE_10HALF;
2975         if (mask & ADVERTISED_10baseT_Full)
2976                 all_mask |= ADVERTISE_10FULL;
2977         if (mask & ADVERTISED_100baseT_Half)
2978                 all_mask |= ADVERTISE_100HALF;
2979         if (mask & ADVERTISED_100baseT_Full)
2980                 all_mask |= ADVERTISE_100FULL;
2981
2982         if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
2983                 return 0;
2984
2985         if ((adv_reg & all_mask) != all_mask)
2986                 return 0;
2987         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
2988                 u32 tg3_ctrl;
2989
2990                 all_mask = 0;
2991                 if (mask & ADVERTISED_1000baseT_Half)
2992                         all_mask |= ADVERTISE_1000HALF;
2993                 if (mask & ADVERTISED_1000baseT_Full)
2994                         all_mask |= ADVERTISE_1000FULL;
2995
2996                 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
2997                         return 0;
2998
2999                 if ((tg3_ctrl & all_mask) != all_mask)
3000                         return 0;
3001         }
3002         return 1;
3003 }
3004
3005 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
3006 {
3007         u32 curadv, reqadv;
3008
3009         if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
3010                 return 1;
3011
3012         curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3013         reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
3014
3015         if (tp->link_config.active_duplex == DUPLEX_FULL) {
3016                 if (curadv != reqadv)
3017                         return 0;
3018
3019                 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
3020                         tg3_readphy(tp, MII_LPA, rmtadv);
3021         } else {
3022                 /* Reprogram the advertisement register, even if it
3023                  * does not affect the current link.  If the link
3024                  * gets renegotiated in the future, we can save an
3025                  * additional renegotiation cycle by advertising
3026                  * it correctly in the first place.
3027                  */
3028                 if (curadv != reqadv) {
3029                         *lcladv &= ~(ADVERTISE_PAUSE_CAP |
3030                                      ADVERTISE_PAUSE_ASYM);
3031                         tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
3032                 }
3033         }
3034
3035         return 1;
3036 }
3037
3038 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
3039 {
3040         int current_link_up;
3041         u32 bmsr, dummy;
3042         u32 lcl_adv, rmt_adv;
3043         u16 current_speed;
3044         u8 current_duplex;
3045         int i, err;
3046
3047         tw32(MAC_EVENT, 0);
3048
3049         tw32_f(MAC_STATUS,
3050              (MAC_STATUS_SYNC_CHANGED |
3051               MAC_STATUS_CFG_CHANGED |
3052               MAC_STATUS_MI_COMPLETION |
3053               MAC_STATUS_LNKSTATE_CHANGED));
3054         udelay(40);
3055
3056         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
3057                 tw32_f(MAC_MI_MODE,
3058                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
3059                 udelay(80);
3060         }
3061
3062         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
3063
3064         /* Some third-party PHYs need to be reset on link going
3065          * down.
3066          */
3067         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3068              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
3069              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
3070             netif_carrier_ok(tp->dev)) {
3071                 tg3_readphy(tp, MII_BMSR, &bmsr);
3072                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3073                     !(bmsr & BMSR_LSTATUS))
3074                         force_reset = 1;
3075         }
3076         if (force_reset)
3077                 tg3_phy_reset(tp);
3078
3079         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
3080                 tg3_readphy(tp, MII_BMSR, &bmsr);
3081                 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
3082                     !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
3083                         bmsr = 0;
3084
3085                 if (!(bmsr & BMSR_LSTATUS)) {
3086                         err = tg3_init_5401phy_dsp(tp);
3087                         if (err)
3088                                 return err;
3089
3090                         tg3_readphy(tp, MII_BMSR, &bmsr);
3091                         for (i = 0; i < 1000; i++) {
3092                                 udelay(10);
3093                                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3094                                     (bmsr & BMSR_LSTATUS)) {
3095                                         udelay(40);
3096                                         break;
3097                                 }
3098                         }
3099
3100                         if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
3101                             !(bmsr & BMSR_LSTATUS) &&
3102                             tp->link_config.active_speed == SPEED_1000) {
3103                                 err = tg3_phy_reset(tp);
3104                                 if (!err)
3105                                         err = tg3_init_5401phy_dsp(tp);
3106                                 if (err)
3107                                         return err;
3108                         }
3109                 }
3110         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3111                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3112                 /* 5701 {A0,B0} CRC bug workaround */
3113                 tg3_writephy(tp, 0x15, 0x0a75);
3114                 tg3_writephy(tp, 0x1c, 0x8c68);
3115                 tg3_writephy(tp, 0x1c, 0x8d68);
3116                 tg3_writephy(tp, 0x1c, 0x8c68);
3117         }
3118
3119         /* Clear pending interrupts... */
3120         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3121         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3122
3123         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
3124                 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
3125         else if (!(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
3126                 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3127
3128         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3129             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3130                 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3131                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
3132                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3133                 else
3134                         tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3135         }
3136
3137         current_link_up = 0;
3138         current_speed = SPEED_INVALID;
3139         current_duplex = DUPLEX_INVALID;
3140
3141         if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
3142                 u32 val;
3143
3144                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3145                 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3146                 if (!(val & (1 << 10))) {
3147                         val |= (1 << 10);
3148                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3149                         goto relink;
3150                 }
3151         }
3152
3153         bmsr = 0;
3154         for (i = 0; i < 100; i++) {
3155                 tg3_readphy(tp, MII_BMSR, &bmsr);
3156                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3157                     (bmsr & BMSR_LSTATUS))
3158                         break;
3159                 udelay(40);
3160         }
3161
3162         if (bmsr & BMSR_LSTATUS) {
3163                 u32 aux_stat, bmcr;
3164
3165                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3166                 for (i = 0; i < 2000; i++) {
3167                         udelay(10);
3168                         if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3169                             aux_stat)
3170                                 break;
3171                 }
3172
3173                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3174                                              &current_speed,
3175                                              &current_duplex);
3176
3177                 bmcr = 0;
3178                 for (i = 0; i < 200; i++) {
3179                         tg3_readphy(tp, MII_BMCR, &bmcr);
3180                         if (tg3_readphy(tp, MII_BMCR, &bmcr))
3181                                 continue;
3182                         if (bmcr && bmcr != 0x7fff)
3183                                 break;
3184                         udelay(10);
3185                 }
3186
3187                 lcl_adv = 0;
3188                 rmt_adv = 0;
3189
3190                 tp->link_config.active_speed = current_speed;
3191                 tp->link_config.active_duplex = current_duplex;
3192
3193                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3194                         if ((bmcr & BMCR_ANENABLE) &&
3195                             tg3_copper_is_advertising_all(tp,
3196                                                 tp->link_config.advertising)) {
3197                                 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3198                                                                   &rmt_adv))
3199                                         current_link_up = 1;
3200                         }
3201                 } else {
3202                         if (!(bmcr & BMCR_ANENABLE) &&
3203                             tp->link_config.speed == current_speed &&
3204                             tp->link_config.duplex == current_duplex &&
3205                             tp->link_config.flowctrl ==
3206                             tp->link_config.active_flowctrl) {
3207                                 current_link_up = 1;
3208                         }
3209                 }
3210
3211                 if (current_link_up == 1 &&
3212                     tp->link_config.active_duplex == DUPLEX_FULL)
3213                         tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
3214         }
3215
3216 relink:
3217         if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
3218                 u32 tmp;
3219
3220                 tg3_phy_copper_begin(tp);
3221
3222                 tg3_readphy(tp, MII_BMSR, &tmp);
3223                 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
3224                     (tmp & BMSR_LSTATUS))
3225                         current_link_up = 1;
3226         }
3227
3228         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3229         if (current_link_up == 1) {
3230                 if (tp->link_config.active_speed == SPEED_100 ||
3231                     tp->link_config.active_speed == SPEED_10)
3232                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3233                 else
3234                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3235         } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)
3236                 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3237         else
3238                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3239
3240         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3241         if (tp->link_config.active_duplex == DUPLEX_HALF)
3242                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3243
3244         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
3245                 if (current_link_up == 1 &&
3246                     tg3_5700_link_polarity(tp, tp->link_config.active_speed))
3247                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
3248                 else
3249                         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
3250         }
3251
3252         /* ??? Without this setting Netgear GA302T PHY does not
3253          * ??? send/receive packets...
3254          */
3255         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
3256             tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3257                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3258                 tw32_f(MAC_MI_MODE, tp->mi_mode);
3259                 udelay(80);
3260         }
3261
3262         tw32_f(MAC_MODE, tp->mac_mode);
3263         udelay(40);
3264
3265         if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3266                 /* Polled via timer. */
3267                 tw32_f(MAC_EVENT, 0);
3268         } else {
3269                 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3270         }
3271         udelay(40);
3272
3273         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3274             current_link_up == 1 &&
3275             tp->link_config.active_speed == SPEED_1000 &&
3276             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3277              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3278                 udelay(120);
3279                 tw32_f(MAC_STATUS,
3280                      (MAC_STATUS_SYNC_CHANGED |
3281                       MAC_STATUS_CFG_CHANGED));
3282                 udelay(40);
3283                 tg3_write_mem(tp,
3284                               NIC_SRAM_FIRMWARE_MBOX,
3285                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3286         }
3287
3288         /* Prevent send BD corruption. */
3289         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3290                 u16 oldlnkctl, newlnkctl;
3291
3292                 pci_read_config_word(tp->pdev,
3293                                      tp->pcie_cap + PCI_EXP_LNKCTL,
3294                                      &oldlnkctl);
3295                 if (tp->link_config.active_speed == SPEED_100 ||
3296                     tp->link_config.active_speed == SPEED_10)
3297                         newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3298                 else
3299                         newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3300                 if (newlnkctl != oldlnkctl)
3301                         pci_write_config_word(tp->pdev,
3302                                               tp->pcie_cap + PCI_EXP_LNKCTL,
3303                                               newlnkctl);
3304         }
3305
3306         if (current_link_up != netif_carrier_ok(tp->dev)) {
3307                 if (current_link_up)
3308                         netif_carrier_on(tp->dev);
3309                 else
3310                         netif_carrier_off(tp->dev);
3311                 tg3_link_report(tp);
3312         }
3313
3314         return 0;
3315 }
3316
3317 struct tg3_fiber_aneginfo {
3318         int state;
3319 #define ANEG_STATE_UNKNOWN              0
3320 #define ANEG_STATE_AN_ENABLE            1
3321 #define ANEG_STATE_RESTART_INIT         2
3322 #define ANEG_STATE_RESTART              3
3323 #define ANEG_STATE_DISABLE_LINK_OK      4
3324 #define ANEG_STATE_ABILITY_DETECT_INIT  5
3325 #define ANEG_STATE_ABILITY_DETECT       6
3326 #define ANEG_STATE_ACK_DETECT_INIT      7
3327 #define ANEG_STATE_ACK_DETECT           8
3328 #define ANEG_STATE_COMPLETE_ACK_INIT    9
3329 #define ANEG_STATE_COMPLETE_ACK         10
3330 #define ANEG_STATE_IDLE_DETECT_INIT     11
3331 #define ANEG_STATE_IDLE_DETECT          12
3332 #define ANEG_STATE_LINK_OK              13
3333 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
3334 #define ANEG_STATE_NEXT_PAGE_WAIT       15
3335
3336         u32 flags;
3337 #define MR_AN_ENABLE            0x00000001
3338 #define MR_RESTART_AN           0x00000002
3339 #define MR_AN_COMPLETE          0x00000004
3340 #define MR_PAGE_RX              0x00000008
3341 #define MR_NP_LOADED            0x00000010
3342 #define MR_TOGGLE_TX            0x00000020
3343 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
3344 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
3345 #define MR_LP_ADV_SYM_PAUSE     0x00000100
3346 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
3347 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3348 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3349 #define MR_LP_ADV_NEXT_PAGE     0x00001000
3350 #define MR_TOGGLE_RX            0x00002000
3351 #define MR_NP_RX                0x00004000
3352
3353 #define MR_LINK_OK              0x80000000
3354
3355         unsigned long link_time, cur_time;
3356
3357         u32 ability_match_cfg;
3358         int ability_match_count;
3359
3360         char ability_match, idle_match, ack_match;
3361
3362         u32 txconfig, rxconfig;
3363 #define ANEG_CFG_NP             0x00000080
3364 #define ANEG_CFG_ACK            0x00000040
3365 #define ANEG_CFG_RF2            0x00000020
3366 #define ANEG_CFG_RF1            0x00000010
3367 #define ANEG_CFG_PS2            0x00000001
3368 #define ANEG_CFG_PS1            0x00008000
3369 #define ANEG_CFG_HD             0x00004000
3370 #define ANEG_CFG_FD             0x00002000
3371 #define ANEG_CFG_INVAL          0x00001f06
3372
3373 };
3374 #define ANEG_OK         0
3375 #define ANEG_DONE       1
3376 #define ANEG_TIMER_ENAB 2
3377 #define ANEG_FAILED     -1
3378
3379 #define ANEG_STATE_SETTLE_TIME  10000
3380
3381 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3382                                    struct tg3_fiber_aneginfo *ap)
3383 {
3384         u16 flowctrl;
3385         unsigned long delta;
3386         u32 rx_cfg_reg;
3387         int ret;
3388
3389         if (ap->state == ANEG_STATE_UNKNOWN) {
3390                 ap->rxconfig = 0;
3391                 ap->link_time = 0;
3392                 ap->cur_time = 0;
3393                 ap->ability_match_cfg = 0;
3394                 ap->ability_match_count = 0;
3395                 ap->ability_match = 0;
3396                 ap->idle_match = 0;
3397                 ap->ack_match = 0;
3398         }
3399         ap->cur_time++;
3400
3401         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3402                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3403
3404                 if (rx_cfg_reg != ap->ability_match_cfg) {
3405                         ap->ability_match_cfg = rx_cfg_reg;
3406                         ap->ability_match = 0;
3407                         ap->ability_match_count = 0;
3408                 } else {
3409                         if (++ap->ability_match_count > 1) {
3410                                 ap->ability_match = 1;
3411                                 ap->ability_match_cfg = rx_cfg_reg;
3412                         }
3413                 }
3414                 if (rx_cfg_reg & ANEG_CFG_ACK)
3415                         ap->ack_match = 1;
3416                 else
3417                         ap->ack_match = 0;
3418
3419                 ap->idle_match = 0;
3420         } else {
3421                 ap->idle_match = 1;
3422                 ap->ability_match_cfg = 0;
3423                 ap->ability_match_count = 0;
3424                 ap->ability_match = 0;
3425                 ap->ack_match = 0;
3426
3427                 rx_cfg_reg = 0;
3428         }
3429
3430         ap->rxconfig = rx_cfg_reg;
3431         ret = ANEG_OK;
3432
3433         switch(ap->state) {
3434         case ANEG_STATE_UNKNOWN:
3435                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3436                         ap->state = ANEG_STATE_AN_ENABLE;
3437
3438                 /* fallthru */
3439         case ANEG_STATE_AN_ENABLE:
3440                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3441                 if (ap->flags & MR_AN_ENABLE) {
3442                         ap->link_time = 0;
3443                         ap->cur_time = 0;
3444                         ap->ability_match_cfg = 0;
3445                         ap->ability_match_count = 0;
3446                         ap->ability_match = 0;
3447                         ap->idle_match = 0;
3448                         ap->ack_match = 0;
3449
3450                         ap->state = ANEG_STATE_RESTART_INIT;
3451                 } else {
3452                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
3453                 }
3454                 break;
3455
3456         case ANEG_STATE_RESTART_INIT:
3457                 ap->link_time = ap->cur_time;
3458                 ap->flags &= ~(MR_NP_LOADED);
3459                 ap->txconfig = 0;
3460                 tw32(MAC_TX_AUTO_NEG, 0);
3461                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3462                 tw32_f(MAC_MODE, tp->mac_mode);
3463                 udelay(40);
3464
3465                 ret = ANEG_TIMER_ENAB;
3466                 ap->state = ANEG_STATE_RESTART;
3467
3468                 /* fallthru */
3469         case ANEG_STATE_RESTART:
3470                 delta = ap->cur_time - ap->link_time;
3471                 if (delta > ANEG_STATE_SETTLE_TIME) {
3472                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3473                 } else {
3474                         ret = ANEG_TIMER_ENAB;
3475                 }
3476                 break;
3477
3478         case ANEG_STATE_DISABLE_LINK_OK:
3479                 ret = ANEG_DONE;
3480                 break;
3481
3482         case ANEG_STATE_ABILITY_DETECT_INIT:
3483                 ap->flags &= ~(MR_TOGGLE_TX);
3484                 ap->txconfig = ANEG_CFG_FD;
3485                 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3486                 if (flowctrl & ADVERTISE_1000XPAUSE)
3487                         ap->txconfig |= ANEG_CFG_PS1;
3488                 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3489                         ap->txconfig |= ANEG_CFG_PS2;
3490                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3491                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3492                 tw32_f(MAC_MODE, tp->mac_mode);
3493                 udelay(40);
3494
3495                 ap->state = ANEG_STATE_ABILITY_DETECT;
3496                 break;
3497
3498         case ANEG_STATE_ABILITY_DETECT:
3499                 if (ap->ability_match != 0 && ap->rxconfig != 0) {
3500                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
3501                 }
3502                 break;
3503
3504         case ANEG_STATE_ACK_DETECT_INIT:
3505                 ap->txconfig |= ANEG_CFG_ACK;
3506                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3507                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3508                 tw32_f(MAC_MODE, tp->mac_mode);
3509                 udelay(40);
3510
3511                 ap->state = ANEG_STATE_ACK_DETECT;
3512
3513                 /* fallthru */
3514         case ANEG_STATE_ACK_DETECT:
3515                 if (ap->ack_match != 0) {
3516                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3517                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3518                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3519                         } else {
3520                                 ap->state = ANEG_STATE_AN_ENABLE;
3521                         }
3522                 } else if (ap->ability_match != 0 &&
3523                            ap->rxconfig == 0) {
3524                         ap->state = ANEG_STATE_AN_ENABLE;
3525                 }
3526                 break;
3527
3528         case ANEG_STATE_COMPLETE_ACK_INIT:
3529                 if (ap->rxconfig & ANEG_CFG_INVAL) {
3530                         ret = ANEG_FAILED;
3531                         break;
3532                 }
3533                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3534                                MR_LP_ADV_HALF_DUPLEX |
3535                                MR_LP_ADV_SYM_PAUSE |
3536                                MR_LP_ADV_ASYM_PAUSE |
3537                                MR_LP_ADV_REMOTE_FAULT1 |
3538                                MR_LP_ADV_REMOTE_FAULT2 |
3539                                MR_LP_ADV_NEXT_PAGE |
3540                                MR_TOGGLE_RX |
3541                                MR_NP_RX);
3542                 if (ap->rxconfig & ANEG_CFG_FD)
3543                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3544                 if (ap->rxconfig & ANEG_CFG_HD)
3545                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3546                 if (ap->rxconfig & ANEG_CFG_PS1)
3547                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
3548                 if (ap->rxconfig & ANEG_CFG_PS2)
3549                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3550                 if (ap->rxconfig & ANEG_CFG_RF1)
3551                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3552                 if (ap->rxconfig & ANEG_CFG_RF2)
3553                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3554                 if (ap->rxconfig & ANEG_CFG_NP)
3555                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
3556
3557                 ap->link_time = ap->cur_time;
3558
3559                 ap->flags ^= (MR_TOGGLE_TX);
3560                 if (ap->rxconfig & 0x0008)
3561                         ap->flags |= MR_TOGGLE_RX;
3562                 if (ap->rxconfig & ANEG_CFG_NP)
3563                         ap->flags |= MR_NP_RX;
3564                 ap->flags |= MR_PAGE_RX;
3565
3566                 ap->state = ANEG_STATE_COMPLETE_ACK;
3567                 ret = ANEG_TIMER_ENAB;
3568                 break;
3569
3570         case ANEG_STATE_COMPLETE_ACK:
3571                 if (ap->ability_match != 0 &&
3572                     ap->rxconfig == 0) {
3573                         ap->state = ANEG_STATE_AN_ENABLE;
3574                         break;
3575                 }
3576                 delta = ap->cur_time - ap->link_time;
3577                 if (delta > ANEG_STATE_SETTLE_TIME) {
3578                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3579                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3580                         } else {
3581                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3582                                     !(ap->flags & MR_NP_RX)) {
3583                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3584                                 } else {
3585                                         ret = ANEG_FAILED;
3586                                 }
3587                         }
3588                 }
3589                 break;
3590
3591         case ANEG_STATE_IDLE_DETECT_INIT:
3592                 ap->link_time = ap->cur_time;
3593                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3594                 tw32_f(MAC_MODE, tp->mac_mode);
3595                 udelay(40);
3596
3597                 ap->state = ANEG_STATE_IDLE_DETECT;
3598                 ret = ANEG_TIMER_ENAB;
3599                 break;
3600
3601         case ANEG_STATE_IDLE_DETECT:
3602                 if (ap->ability_match != 0 &&
3603                     ap->rxconfig == 0) {
3604                         ap->state = ANEG_STATE_AN_ENABLE;
3605                         break;
3606                 }
3607                 delta = ap->cur_time - ap->link_time;
3608                 if (delta > ANEG_STATE_SETTLE_TIME) {
3609                         /* XXX another gem from the Broadcom driver :( */
3610                         ap->state = ANEG_STATE_LINK_OK;
3611                 }
3612                 break;
3613
3614         case ANEG_STATE_LINK_OK:
3615                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3616                 ret = ANEG_DONE;
3617                 break;
3618
3619         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3620                 /* ??? unimplemented */
3621                 break;
3622
3623         case ANEG_STATE_NEXT_PAGE_WAIT:
3624                 /* ??? unimplemented */
3625                 break;
3626
3627         default:
3628                 ret = ANEG_FAILED;
3629                 break;
3630         }
3631
3632         return ret;
3633 }
3634
3635 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
3636 {
3637         int res = 0;
3638         struct tg3_fiber_aneginfo aninfo;
3639         int status = ANEG_FAILED;
3640         unsigned int tick;
3641         u32 tmp;
3642
3643         tw32_f(MAC_TX_AUTO_NEG, 0);
3644
3645         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3646         tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3647         udelay(40);
3648
3649         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3650         udelay(40);
3651
3652         memset(&aninfo, 0, sizeof(aninfo));
3653         aninfo.flags |= MR_AN_ENABLE;
3654         aninfo.state = ANEG_STATE_UNKNOWN;
3655         aninfo.cur_time = 0;
3656         tick = 0;
3657         while (++tick < 195000) {
3658                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3659                 if (status == ANEG_DONE || status == ANEG_FAILED)
3660                         break;
3661
3662                 udelay(1);
3663         }
3664
3665         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3666         tw32_f(MAC_MODE, tp->mac_mode);
3667         udelay(40);
3668
3669         *txflags = aninfo.txconfig;
3670         *rxflags = aninfo.flags;
3671
3672         if (status == ANEG_DONE &&
3673             (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3674                              MR_LP_ADV_FULL_DUPLEX)))
3675                 res = 1;
3676
3677         return res;
3678 }
3679
3680 static void tg3_init_bcm8002(struct tg3 *tp)
3681 {
3682         u32 mac_status = tr32(MAC_STATUS);
3683         int i;
3684
3685         /* Reset when initting first time or we have a link. */
3686         if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3687             !(mac_status & MAC_STATUS_PCS_SYNCED))
3688                 return;
3689
3690         /* Set PLL lock range. */
3691         tg3_writephy(tp, 0x16, 0x8007);
3692
3693         /* SW reset */
3694         tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3695
3696         /* Wait for reset to complete. */
3697         /* XXX schedule_timeout() ... */
3698         for (i = 0; i < 500; i++)
3699                 udelay(10);
3700
3701         /* Config mode; select PMA/Ch 1 regs. */
3702         tg3_writephy(tp, 0x10, 0x8411);
3703
3704         /* Enable auto-lock and comdet, select txclk for tx. */
3705         tg3_writephy(tp, 0x11, 0x0a10);
3706
3707         tg3_writephy(tp, 0x18, 0x00a0);
3708         tg3_writephy(tp, 0x16, 0x41ff);
3709
3710         /* Assert and deassert POR. */
3711         tg3_writephy(tp, 0x13, 0x0400);
3712         udelay(40);
3713         tg3_writephy(tp, 0x13, 0x0000);
3714
3715         tg3_writephy(tp, 0x11, 0x0a50);
3716         udelay(40);
3717         tg3_writephy(tp, 0x11, 0x0a10);
3718
3719         /* Wait for signal to stabilize */
3720         /* XXX schedule_timeout() ... */
3721         for (i = 0; i < 15000; i++)
3722                 udelay(10);
3723
3724         /* Deselect the channel register so we can read the PHYID
3725          * later.
3726          */
3727         tg3_writephy(tp, 0x10, 0x8011);
3728 }
3729
3730 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3731 {
3732         u16 flowctrl;
3733         u32 sg_dig_ctrl, sg_dig_status;
3734         u32 serdes_cfg, expected_sg_dig_ctrl;
3735         int workaround, port_a;
3736         int current_link_up;
3737
3738         serdes_cfg = 0;
3739         expected_sg_dig_ctrl = 0;
3740         workaround = 0;
3741         port_a = 1;
3742         current_link_up = 0;
3743
3744         if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3745             tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3746                 workaround = 1;
3747                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3748                         port_a = 0;
3749
3750                 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3751                 /* preserve bits 20-23 for voltage regulator */
3752                 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3753         }
3754
3755         sg_dig_ctrl = tr32(SG_DIG_CTRL);
3756
3757         if (tp->link_config.autoneg != AUTONEG_ENABLE) {
3758                 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
3759                         if (workaround) {
3760                                 u32 val = serdes_cfg;
3761
3762                                 if (port_a)
3763                                         val |= 0xc010000;
3764                                 else
3765                                         val |= 0x4010000;
3766                                 tw32_f(MAC_SERDES_CFG, val);
3767                         }
3768
3769                         tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3770                 }
3771                 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3772                         tg3_setup_flow_control(tp, 0, 0);
3773                         current_link_up = 1;
3774                 }
3775                 goto out;
3776         }
3777
3778         /* Want auto-negotiation.  */
3779         expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
3780
3781         flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3782         if (flowctrl & ADVERTISE_1000XPAUSE)
3783                 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3784         if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3785                 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
3786
3787         if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3788                 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
3789                     tp->serdes_counter &&
3790                     ((mac_status & (MAC_STATUS_PCS_SYNCED |
3791                                     MAC_STATUS_RCVD_CFG)) ==
3792                      MAC_STATUS_PCS_SYNCED)) {
3793                         tp->serdes_counter--;
3794                         current_link_up = 1;
3795                         goto out;
3796                 }
3797 restart_autoneg:
3798                 if (workaround)
3799                         tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
3800                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
3801                 udelay(5);
3802                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3803
3804                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3805                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3806         } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3807                                  MAC_STATUS_SIGNAL_DET)) {
3808                 sg_dig_status = tr32(SG_DIG_STATUS);
3809                 mac_status = tr32(MAC_STATUS);
3810
3811                 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
3812                     (mac_status & MAC_STATUS_PCS_SYNCED)) {
3813                         u32 local_adv = 0, remote_adv = 0;
3814
3815                         if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3816                                 local_adv |= ADVERTISE_1000XPAUSE;
3817                         if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3818                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3819
3820                         if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
3821                                 remote_adv |= LPA_1000XPAUSE;
3822                         if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
3823                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3824
3825                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3826                         current_link_up = 1;
3827                         tp->serdes_counter = 0;
3828                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3829                 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3830                         if (tp->serdes_counter)
3831                                 tp->serdes_counter--;
3832                         else {
3833                                 if (workaround) {
3834                                         u32 val = serdes_cfg;
3835
3836                                         if (port_a)
3837                                                 val |= 0xc010000;
3838                                         else
3839                                                 val |= 0x4010000;
3840
3841                                         tw32_f(MAC_SERDES_CFG, val);
3842                                 }
3843
3844                                 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3845                                 udelay(40);
3846
3847                                 /* Link parallel detection - link is up */
3848                                 /* only if we have PCS_SYNC and not */
3849                                 /* receiving config code words */
3850                                 mac_status = tr32(MAC_STATUS);
3851                                 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3852                                     !(mac_status & MAC_STATUS_RCVD_CFG)) {
3853                                         tg3_setup_flow_control(tp, 0, 0);
3854                                         current_link_up = 1;
3855                                         tp->tg3_flags2 |=
3856                                                 TG3_FLG2_PARALLEL_DETECT;
3857                                         tp->serdes_counter =
3858                                                 SERDES_PARALLEL_DET_TIMEOUT;
3859                                 } else
3860                                         goto restart_autoneg;
3861                         }
3862                 }
3863         } else {
3864                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3865                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3866         }
3867
3868 out:
3869         return current_link_up;
3870 }
3871
3872 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3873 {
3874         int current_link_up = 0;
3875
3876         if (!(mac_status & MAC_STATUS_PCS_SYNCED))
3877                 goto out;
3878
3879         if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3880                 u32 txflags, rxflags;
3881                 int i;
3882
3883                 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3884                         u32 local_adv = 0, remote_adv = 0;
3885
3886                         if (txflags & ANEG_CFG_PS1)
3887                                 local_adv |= ADVERTISE_1000XPAUSE;
3888                         if (txflags & ANEG_CFG_PS2)
3889                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3890
3891                         if (rxflags & MR_LP_ADV_SYM_PAUSE)
3892                                 remote_adv |= LPA_1000XPAUSE;
3893                         if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3894                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3895
3896                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3897
3898                         current_link_up = 1;
3899                 }
3900                 for (i = 0; i < 30; i++) {
3901                         udelay(20);
3902                         tw32_f(MAC_STATUS,
3903                                (MAC_STATUS_SYNC_CHANGED |
3904                                 MAC_STATUS_CFG_CHANGED));
3905                         udelay(40);
3906                         if ((tr32(MAC_STATUS) &
3907                              (MAC_STATUS_SYNC_CHANGED |
3908                               MAC_STATUS_CFG_CHANGED)) == 0)
3909                                 break;
3910                 }
3911
3912                 mac_status = tr32(MAC_STATUS);
3913                 if (current_link_up == 0 &&
3914                     (mac_status & MAC_STATUS_PCS_SYNCED) &&
3915                     !(mac_status & MAC_STATUS_RCVD_CFG))
3916                         current_link_up = 1;
3917         } else {
3918                 tg3_setup_flow_control(tp, 0, 0);
3919
3920                 /* Forcing 1000FD link up. */
3921                 current_link_up = 1;
3922
3923                 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3924                 udelay(40);
3925
3926                 tw32_f(MAC_MODE, tp->mac_mode);
3927                 udelay(40);
3928         }
3929
3930 out:
3931         return current_link_up;
3932 }
3933
3934 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3935 {
3936         u32 orig_pause_cfg;
3937         u16 orig_active_speed;
3938         u8 orig_active_duplex;
3939         u32 mac_status;
3940         int current_link_up;
3941         int i;
3942
3943         orig_pause_cfg = tp->link_config.active_flowctrl;
3944         orig_active_speed = tp->link_config.active_speed;
3945         orig_active_duplex = tp->link_config.active_duplex;
3946
3947         if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3948             netif_carrier_ok(tp->dev) &&
3949             (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3950                 mac_status = tr32(MAC_STATUS);
3951                 mac_status &= (MAC_STATUS_PCS_SYNCED |
3952                                MAC_STATUS_SIGNAL_DET |
3953                                MAC_STATUS_CFG_CHANGED |
3954                                MAC_STATUS_RCVD_CFG);
3955                 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3956                                    MAC_STATUS_SIGNAL_DET)) {
3957                         tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3958                                             MAC_STATUS_CFG_CHANGED));
3959                         return 0;
3960                 }
3961         }
3962
3963         tw32_f(MAC_TX_AUTO_NEG, 0);
3964
3965         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3966         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3967         tw32_f(MAC_MODE, tp->mac_mode);
3968         udelay(40);
3969
3970         if (tp->phy_id == PHY_ID_BCM8002)
3971                 tg3_init_bcm8002(tp);
3972
3973         /* Enable link change event even when serdes polling.  */
3974         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3975         udelay(40);
3976
3977         current_link_up = 0;
3978         mac_status = tr32(MAC_STATUS);
3979
3980         if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
3981                 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
3982         else
3983                 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
3984
3985         tp->napi[0].hw_status->status =
3986                 (SD_STATUS_UPDATED |
3987                  (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
3988
3989         for (i = 0; i < 100; i++) {
3990                 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3991                                     MAC_STATUS_CFG_CHANGED));
3992                 udelay(5);
3993                 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3994                                          MAC_STATUS_CFG_CHANGED |
3995                                          MAC_STATUS_LNKSTATE_CHANGED)) == 0)
3996                         break;
3997         }
3998
3999         mac_status = tr32(MAC_STATUS);
4000         if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
4001                 current_link_up = 0;
4002                 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
4003                     tp->serdes_counter == 0) {
4004                         tw32_f(MAC_MODE, (tp->mac_mode |
4005                                           MAC_MODE_SEND_CONFIGS));
4006                         udelay(1);
4007                         tw32_f(MAC_MODE, tp->mac_mode);
4008                 }
4009         }
4010
4011         if (current_link_up == 1) {
4012                 tp->link_config.active_speed = SPEED_1000;
4013                 tp->link_config.active_duplex = DUPLEX_FULL;
4014                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4015                                     LED_CTRL_LNKLED_OVERRIDE |
4016                                     LED_CTRL_1000MBPS_ON));
4017         } else {
4018                 tp->link_config.active_speed = SPEED_INVALID;
4019                 tp->link_config.active_duplex = DUPLEX_INVALID;
4020                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4021                                     LED_CTRL_LNKLED_OVERRIDE |
4022                                     LED_CTRL_TRAFFIC_OVERRIDE));
4023         }
4024
4025         if (current_link_up != netif_carrier_ok(tp->dev)) {
4026                 if (current_link_up)
4027                         netif_carrier_on(tp->dev);
4028                 else
4029                         netif_carrier_off(tp->dev);
4030                 tg3_link_report(tp);
4031         } else {
4032                 u32 now_pause_cfg = tp->link_config.active_flowctrl;
4033                 if (orig_pause_cfg != now_pause_cfg ||
4034                     orig_active_speed != tp->link_config.active_speed ||
4035                     orig_active_duplex != tp->link_config.active_duplex)
4036                         tg3_link_report(tp);
4037         }
4038
4039         return 0;
4040 }
4041
4042 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
4043 {
4044         int current_link_up, err = 0;
4045         u32 bmsr, bmcr;
4046         u16 current_speed;
4047         u8 current_duplex;
4048         u32 local_adv, remote_adv;
4049
4050         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4051         tw32_f(MAC_MODE, tp->mac_mode);
4052         udelay(40);
4053
4054         tw32(MAC_EVENT, 0);
4055
4056         tw32_f(MAC_STATUS,
4057              (MAC_STATUS_SYNC_CHANGED |
4058               MAC_STATUS_CFG_CHANGED |
4059               MAC_STATUS_MI_COMPLETION |
4060               MAC_STATUS_LNKSTATE_CHANGED));
4061         udelay(40);
4062
4063         if (force_reset)
4064                 tg3_phy_reset(tp);
4065
4066         current_link_up = 0;
4067         current_speed = SPEED_INVALID;
4068         current_duplex = DUPLEX_INVALID;
4069
4070         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4071         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4072         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
4073                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4074                         bmsr |= BMSR_LSTATUS;
4075                 else
4076                         bmsr &= ~BMSR_LSTATUS;
4077         }
4078
4079         err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4080
4081         if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
4082             (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4083                 /* do nothing, just check for link up at the end */
4084         } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4085                 u32 adv, new_adv;
4086
4087                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4088                 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4089                                   ADVERTISE_1000XPAUSE |
4090                                   ADVERTISE_1000XPSE_ASYM |
4091                                   ADVERTISE_SLCT);
4092
4093                 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4094
4095                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4096                         new_adv |= ADVERTISE_1000XHALF;
4097                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4098                         new_adv |= ADVERTISE_1000XFULL;
4099
4100                 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4101                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
4102                         bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4103                         tg3_writephy(tp, MII_BMCR, bmcr);
4104
4105                         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4106                         tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
4107                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4108
4109                         return err;
4110                 }
4111         } else {
4112                 u32 new_bmcr;
4113
4114                 bmcr &= ~BMCR_SPEED1000;
4115                 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4116
4117                 if (tp->link_config.duplex == DUPLEX_FULL)
4118                         new_bmcr |= BMCR_FULLDPLX;
4119
4120                 if (new_bmcr != bmcr) {
4121                         /* BMCR_SPEED1000 is a reserved bit that needs
4122                          * to be set on write.
4123                          */
4124                         new_bmcr |= BMCR_SPEED1000;
4125
4126                         /* Force a linkdown */
4127                         if (netif_carrier_ok(tp->dev)) {
4128                                 u32 adv;
4129
4130                                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4131                                 adv &= ~(ADVERTISE_1000XFULL |
4132                                          ADVERTISE_1000XHALF |
4133                                          ADVERTISE_SLCT);
4134                                 tg3_writephy(tp, MII_ADVERTISE, adv);
4135                                 tg3_writephy(tp, MII_BMCR, bmcr |
4136                                                            BMCR_ANRESTART |
4137                                                            BMCR_ANENABLE);
4138                                 udelay(10);
4139                                 netif_carrier_off(tp->dev);
4140                         }
4141                         tg3_writephy(tp, MII_BMCR, new_bmcr);
4142                         bmcr = new_bmcr;
4143                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4144                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4145                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4146                             ASIC_REV_5714) {
4147                                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4148                                         bmsr |= BMSR_LSTATUS;
4149                                 else
4150                                         bmsr &= ~BMSR_LSTATUS;
4151                         }
4152                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4153                 }
4154         }
4155
4156         if (bmsr & BMSR_LSTATUS) {
4157                 current_speed = SPEED_1000;
4158                 current_link_up = 1;
4159                 if (bmcr & BMCR_FULLDPLX)
4160                         current_duplex = DUPLEX_FULL;
4161                 else
4162                         current_duplex = DUPLEX_HALF;
4163
4164                 local_adv = 0;
4165                 remote_adv = 0;
4166
4167                 if (bmcr & BMCR_ANENABLE) {
4168                         u32 common;
4169
4170                         err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4171                         err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4172                         common = local_adv & remote_adv;
4173                         if (common & (ADVERTISE_1000XHALF |
4174                                       ADVERTISE_1000XFULL)) {
4175                                 if (common & ADVERTISE_1000XFULL)
4176                                         current_duplex = DUPLEX_FULL;
4177                                 else
4178                                         current_duplex = DUPLEX_HALF;
4179                         }
4180                         else
4181                                 current_link_up = 0;
4182                 }
4183         }
4184
4185         if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4186                 tg3_setup_flow_control(tp, local_adv, remote_adv);
4187
4188         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4189         if (tp->link_config.active_duplex == DUPLEX_HALF)
4190                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4191
4192         tw32_f(MAC_MODE, tp->mac_mode);
4193         udelay(40);
4194
4195         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4196
4197         tp->link_config.active_speed = current_speed;
4198         tp->link_config.active_duplex = current_duplex;
4199
4200         if (current_link_up != netif_carrier_ok(tp->dev)) {
4201                 if (current_link_up)
4202                         netif_carrier_on(tp->dev);
4203                 else {
4204                         netif_carrier_off(tp->dev);
4205                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4206                 }
4207                 tg3_link_report(tp);
4208         }
4209         return err;
4210 }
4211
4212 static void tg3_serdes_parallel_detect(struct tg3 *tp)
4213 {
4214         if (tp->serdes_counter) {
4215                 /* Give autoneg time to complete. */
4216                 tp->serdes_counter--;
4217                 return;
4218         }
4219         if (!netif_carrier_ok(tp->dev) &&
4220             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4221                 u32 bmcr;
4222
4223                 tg3_readphy(tp, MII_BMCR, &bmcr);
4224                 if (bmcr & BMCR_ANENABLE) {
4225                         u32 phy1, phy2;
4226
4227                         /* Select shadow register 0x1f */
4228                         tg3_writephy(tp, 0x1c, 0x7c00);
4229                         tg3_readphy(tp, 0x1c, &phy1);
4230
4231                         /* Select expansion interrupt status register */
4232                         tg3_writephy(tp, 0x17, 0x0f01);
4233                         tg3_readphy(tp, 0x15, &phy2);
4234                         tg3_readphy(tp, 0x15, &phy2);
4235
4236                         if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4237                                 /* We have signal detect and not receiving
4238                                  * config code words, link is up by parallel
4239                                  * detection.
4240                                  */
4241
4242                                 bmcr &= ~BMCR_ANENABLE;
4243                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4244                                 tg3_writephy(tp, MII_BMCR, bmcr);
4245                                 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
4246                         }
4247                 }
4248         }
4249         else if (netif_carrier_ok(tp->dev) &&
4250                  (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4251                  (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4252                 u32 phy2;
4253
4254                 /* Select expansion interrupt status register */
4255                 tg3_writephy(tp, 0x17, 0x0f01);
4256                 tg3_readphy(tp, 0x15, &phy2);
4257                 if (phy2 & 0x20) {
4258                         u32 bmcr;
4259
4260                         /* Config code words received, turn on autoneg. */
4261                         tg3_readphy(tp, MII_BMCR, &bmcr);
4262                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4263
4264                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4265
4266                 }
4267         }
4268 }
4269
4270 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4271 {
4272         int err;
4273
4274         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4275                 err = tg3_setup_fiber_phy(tp, force_reset);
4276         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
4277                 err = tg3_setup_fiber_mii_phy(tp, force_reset);
4278         } else {
4279                 err = tg3_setup_copper_phy(tp, force_reset);
4280         }
4281
4282         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
4283                 u32 val, scale;
4284
4285                 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4286                 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4287                         scale = 65;
4288                 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4289                         scale = 6;
4290                 else
4291                         scale = 12;
4292
4293                 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4294                 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4295                 tw32(GRC_MISC_CFG, val);
4296         }
4297
4298         if (tp->link_config.active_speed == SPEED_1000 &&
4299             tp->link_config.active_duplex == DUPLEX_HALF)
4300                 tw32(MAC_TX_LENGTHS,
4301                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4302                       (6 << TX_LENGTHS_IPG_SHIFT) |
4303                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4304         else
4305                 tw32(MAC_TX_LENGTHS,
4306                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4307                       (6 << TX_LENGTHS_IPG_SHIFT) |
4308                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4309
4310         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4311                 if (netif_carrier_ok(tp->dev)) {
4312                         tw32(HOSTCC_STAT_COAL_TICKS,
4313                              tp->coal.stats_block_coalesce_usecs);
4314                 } else {
4315                         tw32(HOSTCC_STAT_COAL_TICKS, 0);
4316                 }
4317         }
4318
4319         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4320                 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4321                 if (!netif_carrier_ok(tp->dev))
4322                         val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4323                               tp->pwrmgmt_thresh;
4324                 else
4325                         val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4326                 tw32(PCIE_PWR_MGMT_THRESH, val);
4327         }
4328
4329         return err;
4330 }
4331
4332 /* This is called whenever we suspect that the system chipset is re-
4333  * ordering the sequence of MMIO to the tx send mailbox. The symptom
4334  * is bogus tx completions. We try to recover by setting the
4335  * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4336  * in the workqueue.
4337  */
4338 static void tg3_tx_recover(struct tg3 *tp)
4339 {
4340         BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4341                tp->write32_tx_mbox == tg3_write_indirect_mbox);
4342
4343         printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
4344                "mapped I/O cycles to the network device, attempting to "
4345                "recover. Please report the problem to the driver maintainer "
4346                "and include system chipset information.\n", tp->dev->name);
4347
4348         spin_lock(&tp->lock);
4349         tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
4350         spin_unlock(&tp->lock);
4351 }
4352
4353 static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
4354 {
4355         smp_mb();
4356         return tnapi->tx_pending -
4357                ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
4358 }
4359
4360 /* Tigon3 never reports partial packet sends.  So we do not
4361  * need special logic to handle SKBs that have not had all
4362  * of their frags sent yet, like SunGEM does.
4363  */
4364 static void tg3_tx(struct tg3_napi *tnapi)
4365 {
4366         struct tg3 *tp = tnapi->tp;
4367         u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
4368         u32 sw_idx = tnapi->tx_cons;
4369         struct netdev_queue *txq;
4370         int index = tnapi - tp->napi;
4371
4372         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
4373                 index--;
4374
4375         txq = netdev_get_tx_queue(tp->dev, index);
4376
4377         while (sw_idx != hw_idx) {
4378                 struct ring_info *ri = &tnapi->tx_buffers[sw_idx];
4379                 struct sk_buff *skb = ri->skb;
4380                 int i, tx_bug = 0;
4381
4382                 if (unlikely(skb == NULL)) {
4383                         tg3_tx_recover(tp);
4384                         return;
4385                 }
4386
4387                 pci_unmap_single(tp->pdev,
4388                                  pci_unmap_addr(ri, mapping),
4389                                  skb_headlen(skb),
4390                                  PCI_DMA_TODEVICE);
4391
4392                 ri->skb = NULL;
4393
4394                 sw_idx = NEXT_TX(sw_idx);
4395
4396                 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
4397                         ri = &tnapi->tx_buffers[sw_idx];
4398                         if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4399                                 tx_bug = 1;
4400
4401                         pci_unmap_page(tp->pdev,
4402                                        pci_unmap_addr(ri, mapping),
4403                                        skb_shinfo(skb)->frags[i].size,
4404                                        PCI_DMA_TODEVICE);
4405                         sw_idx = NEXT_TX(sw_idx);
4406                 }
4407
4408                 dev_kfree_skb(skb);
4409
4410                 if (unlikely(tx_bug)) {
4411                         tg3_tx_recover(tp);
4412                         return;
4413                 }
4414         }
4415
4416         tnapi->tx_cons = sw_idx;
4417
4418         /* Need to make the tx_cons update visible to tg3_start_xmit()
4419          * before checking for netif_queue_stopped().  Without the
4420          * memory barrier, there is a small possibility that tg3_start_xmit()
4421          * will miss it and cause the queue to be stopped forever.
4422          */
4423         smp_mb();
4424
4425         if (unlikely(netif_tx_queue_stopped(txq) &&
4426                      (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
4427                 __netif_tx_lock(txq, smp_processor_id());
4428                 if (netif_tx_queue_stopped(txq) &&
4429                     (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
4430                         netif_tx_wake_queue(txq);
4431                 __netif_tx_unlock(txq);
4432         }
4433 }
4434
4435 static void tg3_rx_skb_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
4436 {
4437         if (!ri->skb)
4438                 return;
4439
4440         pci_unmap_single(tp->pdev, pci_unmap_addr(ri, mapping),
4441                          map_sz, PCI_DMA_FROMDEVICE);
4442         dev_kfree_skb_any(ri->skb);
4443         ri->skb = NULL;
4444 }
4445
4446 /* Returns size of skb allocated or < 0 on error.
4447  *
4448  * We only need to fill in the address because the other members
4449  * of the RX descriptor are invariant, see tg3_init_rings.
4450  *
4451  * Note the purposeful assymetry of cpu vs. chip accesses.  For
4452  * posting buffers we only dirty the first cache line of the RX
4453  * descriptor (containing the address).  Whereas for the RX status
4454  * buffers the cpu only reads the last cacheline of the RX descriptor
4455  * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4456  */
4457 static int tg3_alloc_rx_skb(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
4458                             u32 opaque_key, u32 dest_idx_unmasked)
4459 {
4460         struct tg3_rx_buffer_desc *desc;
4461         struct ring_info *map, *src_map;
4462         struct sk_buff *skb;
4463         dma_addr_t mapping;
4464         int skb_size, dest_idx;
4465
4466         src_map = NULL;
4467         switch (opaque_key) {
4468         case RXD_OPAQUE_RING_STD:
4469                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4470                 desc = &tpr->rx_std[dest_idx];
4471                 map = &tpr->rx_std_buffers[dest_idx];
4472                 skb_size = tp->rx_pkt_map_sz;
4473                 break;
4474
4475         case RXD_OPAQUE_RING_JUMBO:
4476                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4477                 desc = &tpr->rx_jmb[dest_idx].std;
4478                 map = &tpr->rx_jmb_buffers[dest_idx];
4479                 skb_size = TG3_RX_JMB_MAP_SZ;
4480                 break;
4481
4482         default:
4483                 return -EINVAL;
4484         }
4485
4486         /* Do not overwrite any of the map or rp information
4487          * until we are sure we can commit to a new buffer.
4488          *
4489          * Callers depend upon this behavior and assume that
4490          * we leave everything unchanged if we fail.
4491          */
4492         skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
4493         if (skb == NULL)
4494                 return -ENOMEM;
4495
4496         skb_reserve(skb, tp->rx_offset);
4497
4498         mapping = pci_map_single(tp->pdev, skb->data, skb_size,
4499                                  PCI_DMA_FROMDEVICE);
4500         if (pci_dma_mapping_error(tp->pdev, mapping)) {
4501                 dev_kfree_skb(skb);
4502                 return -EIO;
4503         }
4504
4505         map->skb = skb;
4506         pci_unmap_addr_set(map, mapping, mapping);
4507
4508         desc->addr_hi = ((u64)mapping >> 32);
4509         desc->addr_lo = ((u64)mapping & 0xffffffff);
4510
4511         return skb_size;
4512 }
4513
4514 /* We only need to move over in the address because the other
4515  * members of the RX descriptor are invariant.  See notes above
4516  * tg3_alloc_rx_skb for full details.
4517  */
4518 static void tg3_recycle_rx(struct tg3_napi *tnapi,
4519                            struct tg3_rx_prodring_set *dpr,
4520                            u32 opaque_key, int src_idx,
4521                            u32 dest_idx_unmasked)
4522 {
4523         struct tg3 *tp = tnapi->tp;
4524         struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4525         struct ring_info *src_map, *dest_map;
4526         int dest_idx;
4527         struct tg3_rx_prodring_set *spr = &tp->prodring[0];
4528
4529         switch (opaque_key) {
4530         case RXD_OPAQUE_RING_STD:
4531                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4532                 dest_desc = &dpr->rx_std[dest_idx];
4533                 dest_map = &dpr->rx_std_buffers[dest_idx];
4534                 src_desc = &spr->rx_std[src_idx];
4535                 src_map = &spr->rx_std_buffers[src_idx];
4536                 break;
4537
4538         case RXD_OPAQUE_RING_JUMBO:
4539                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4540                 dest_desc = &dpr->rx_jmb[dest_idx].std;
4541                 dest_map = &dpr->rx_jmb_buffers[dest_idx];
4542                 src_desc = &spr->rx_jmb[src_idx].std;
4543                 src_map = &spr->rx_jmb_buffers[src_idx];
4544                 break;
4545
4546         default:
4547                 return;
4548         }
4549
4550         dest_map->skb = src_map->skb;
4551         pci_unmap_addr_set(dest_map, mapping,
4552                            pci_unmap_addr(src_map, mapping));
4553         dest_desc->addr_hi = src_desc->addr_hi;
4554         dest_desc->addr_lo = src_desc->addr_lo;
4555         src_map->skb = NULL;
4556 }
4557
4558 /* The RX ring scheme is composed of multiple rings which post fresh
4559  * buffers to the chip, and one special ring the chip uses to report
4560  * status back to the host.
4561  *
4562  * The special ring reports the status of received packets to the
4563  * host.  The chip does not write into the original descriptor the
4564  * RX buffer was obtained from.  The chip simply takes the original
4565  * descriptor as provided by the host, updates the status and length
4566  * field, then writes this into the next status ring entry.
4567  *
4568  * Each ring the host uses to post buffers to the chip is described
4569  * by a TG3_BDINFO entry in the chips SRAM area.  When a packet arrives,
4570  * it is first placed into the on-chip ram.  When the packet's length
4571  * is known, it walks down the TG3_BDINFO entries to select the ring.
4572  * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4573  * which is within the range of the new packet's length is chosen.
4574  *
4575  * The "separate ring for rx status" scheme may sound queer, but it makes
4576  * sense from a cache coherency perspective.  If only the host writes
4577  * to the buffer post rings, and only the chip writes to the rx status
4578  * rings, then cache lines never move beyond shared-modified state.
4579  * If both the host and chip were to write into the same ring, cache line
4580  * eviction could occur since both entities want it in an exclusive state.
4581  */
4582 static int tg3_rx(struct tg3_napi *tnapi, int budget)
4583 {
4584         struct tg3 *tp = tnapi->tp;
4585         u32 work_mask, rx_std_posted = 0;
4586         u32 std_prod_idx, jmb_prod_idx;
4587         u32 sw_idx = tnapi->rx_rcb_ptr;
4588         u16 hw_idx;
4589         int received;
4590         struct tg3_rx_prodring_set *tpr = tnapi->prodring;
4591
4592         hw_idx = *(tnapi->rx_rcb_prod_idx);
4593         /*
4594          * We need to order the read of hw_idx and the read of
4595          * the opaque cookie.
4596          */
4597         rmb();
4598         work_mask = 0;
4599         received = 0;
4600         std_prod_idx = tpr->rx_std_prod_idx;
4601         jmb_prod_idx = tpr->rx_jmb_prod_idx;
4602         while (sw_idx != hw_idx && budget > 0) {
4603                 struct ring_info *ri;
4604                 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
4605                 unsigned int len;
4606                 struct sk_buff *skb;
4607                 dma_addr_t dma_addr;
4608                 u32 opaque_key, desc_idx, *post_ptr;
4609
4610                 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4611                 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4612                 if (opaque_key == RXD_OPAQUE_RING_STD) {
4613                         ri = &tp->prodring[0].rx_std_buffers[desc_idx];
4614                         dma_addr = pci_unmap_addr(ri, mapping);
4615                         skb = ri->skb;
4616                         post_ptr = &std_prod_idx;
4617                         rx_std_posted++;
4618                 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4619                         ri = &tp->prodring[0].rx_jmb_buffers[desc_idx];
4620                         dma_addr = pci_unmap_addr(ri, mapping);
4621                         skb = ri->skb;
4622                         post_ptr = &jmb_prod_idx;
4623                 } else
4624                         goto next_pkt_nopost;
4625
4626                 work_mask |= opaque_key;
4627
4628                 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4629                     (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4630                 drop_it:
4631                         tg3_recycle_rx(tnapi, tpr, opaque_key,
4632                                        desc_idx, *post_ptr);
4633                 drop_it_no_recycle:
4634                         /* Other statistics kept track of by card. */
4635                         tp->net_stats.rx_dropped++;
4636                         goto next_pkt;
4637                 }
4638
4639                 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4640                       ETH_FCS_LEN;
4641
4642                 if (len > RX_COPY_THRESHOLD &&
4643                     tp->rx_offset == NET_IP_ALIGN) {
4644                     /* rx_offset will likely not equal NET_IP_ALIGN
4645                      * if this is a 5701 card running in PCI-X mode
4646                      * [see tg3_get_invariants()]
4647                      */
4648                         int skb_size;
4649
4650                         skb_size = tg3_alloc_rx_skb(tp, tpr, opaque_key,
4651                                                     *post_ptr);
4652                         if (skb_size < 0)
4653                                 goto drop_it;
4654
4655                         ri->skb = NULL;
4656
4657                         pci_unmap_single(tp->pdev, dma_addr, skb_size,
4658                                          PCI_DMA_FROMDEVICE);
4659
4660                         skb_put(skb, len);
4661                 } else {
4662                         struct sk_buff *copy_skb;
4663
4664                         tg3_recycle_rx(tnapi, tpr, opaque_key,
4665                                        desc_idx, *post_ptr);
4666
4667                         copy_skb = netdev_alloc_skb(tp->dev,
4668                                                     len + TG3_RAW_IP_ALIGN);
4669                         if (copy_skb == NULL)
4670                                 goto drop_it_no_recycle;
4671
4672                         skb_reserve(copy_skb, TG3_RAW_IP_ALIGN);
4673                         skb_put(copy_skb, len);
4674                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4675                         skb_copy_from_linear_data(skb, copy_skb->data, len);
4676                         pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4677
4678                         /* We'll reuse the original ring buffer. */
4679                         skb = copy_skb;
4680                 }
4681
4682                 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4683                     (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4684                     (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4685                       >> RXD_TCPCSUM_SHIFT) == 0xffff))
4686                         skb->ip_summed = CHECKSUM_UNNECESSARY;
4687                 else
4688                         skb->ip_summed = CHECKSUM_NONE;
4689
4690                 skb->protocol = eth_type_trans(skb, tp->dev);
4691
4692                 if (len > (tp->dev->mtu + ETH_HLEN) &&
4693                     skb->protocol != htons(ETH_P_8021Q)) {
4694                         dev_kfree_skb(skb);
4695                         goto next_pkt;
4696                 }
4697
4698 #if TG3_VLAN_TAG_USED
4699                 if (tp->vlgrp != NULL &&
4700                     desc->type_flags & RXD_FLAG_VLAN) {
4701                         vlan_gro_receive(&tnapi->napi, tp->vlgrp,
4702                                          desc->err_vlan & RXD_VLAN_MASK, skb);
4703                 } else
4704 #endif
4705                         napi_gro_receive(&tnapi->napi, skb);
4706
4707                 received++;
4708                 budget--;
4709
4710 next_pkt:
4711                 (*post_ptr)++;
4712
4713                 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4714                         tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4715                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4716                                      tpr->rx_std_prod_idx);
4717                         work_mask &= ~RXD_OPAQUE_RING_STD;
4718                         rx_std_posted = 0;
4719                 }
4720 next_pkt_nopost:
4721                 sw_idx++;
4722                 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
4723
4724                 /* Refresh hw_idx to see if there is new work */
4725                 if (sw_idx == hw_idx) {
4726                         hw_idx = *(tnapi->rx_rcb_prod_idx);
4727                         rmb();
4728                 }
4729         }
4730
4731         /* ACK the status ring. */
4732         tnapi->rx_rcb_ptr = sw_idx;
4733         tw32_rx_mbox(tnapi->consmbox, sw_idx);
4734
4735         /* Refill RX ring(s). */
4736         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) {
4737                 if (work_mask & RXD_OPAQUE_RING_STD) {
4738                         tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4739                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4740                                      tpr->rx_std_prod_idx);
4741                 }
4742                 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4743                         tpr->rx_jmb_prod_idx = jmb_prod_idx %
4744                                                TG3_RX_JUMBO_RING_SIZE;
4745                         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
4746                                      tpr->rx_jmb_prod_idx);
4747                 }
4748                 mmiowb();
4749         } else if (work_mask) {
4750                 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
4751                  * updated before the producer indices can be updated.
4752                  */
4753                 smp_wmb();
4754
4755                 tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4756                 tpr->rx_jmb_prod_idx = jmb_prod_idx % TG3_RX_JUMBO_RING_SIZE;
4757
4758                 if (tnapi != &tp->napi[1])
4759                         napi_schedule(&tp->napi[1].napi);
4760         }
4761
4762         return received;
4763 }
4764
4765 static void tg3_poll_link(struct tg3 *tp)
4766 {
4767         /* handle link change and other phy events */
4768         if (!(tp->tg3_flags &
4769               (TG3_FLAG_USE_LINKCHG_REG |
4770                TG3_FLAG_POLL_SERDES))) {
4771                 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
4772
4773                 if (sblk->status & SD_STATUS_LINK_CHG) {
4774                         sblk->status = SD_STATUS_UPDATED |
4775                                        (sblk->status & ~SD_STATUS_LINK_CHG);
4776                         spin_lock(&tp->lock);
4777                         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4778                                 tw32_f(MAC_STATUS,
4779                                      (MAC_STATUS_SYNC_CHANGED |
4780                                       MAC_STATUS_CFG_CHANGED |
4781                                       MAC_STATUS_MI_COMPLETION |
4782                                       MAC_STATUS_LNKSTATE_CHANGED));
4783                                 udelay(40);
4784                         } else
4785                                 tg3_setup_phy(tp, 0);
4786                         spin_unlock(&tp->lock);
4787                 }
4788         }
4789 }
4790
4791 static void tg3_rx_prodring_xfer(struct tg3 *tp,
4792                                  struct tg3_rx_prodring_set *dpr,
4793                                  struct tg3_rx_prodring_set *spr)
4794 {
4795         u32 si, di, cpycnt, src_prod_idx;
4796         int i;
4797
4798         while (1) {
4799                 src_prod_idx = spr->rx_std_prod_idx;
4800
4801                 /* Make sure updates to the rx_std_buffers[] entries and the
4802                  * standard producer index are seen in the correct order.
4803                  */
4804                 smp_rmb();
4805
4806                 if (spr->rx_std_cons_idx == src_prod_idx)
4807                         break;
4808
4809                 if (spr->rx_std_cons_idx < src_prod_idx)
4810                         cpycnt = src_prod_idx - spr->rx_std_cons_idx;
4811                 else
4812                         cpycnt = TG3_RX_RING_SIZE - spr->rx_std_cons_idx;
4813
4814                 cpycnt = min(cpycnt, TG3_RX_RING_SIZE - dpr->rx_std_prod_idx);
4815
4816                 si = spr->rx_std_cons_idx;
4817                 di = dpr->rx_std_prod_idx;
4818
4819                 memcpy(&dpr->rx_std_buffers[di],
4820                        &spr->rx_std_buffers[si],
4821                        cpycnt * sizeof(struct ring_info));
4822
4823                 for (i = 0; i < cpycnt; i++, di++, si++) {
4824                         struct tg3_rx_buffer_desc *sbd, *dbd;
4825                         sbd = &spr->rx_std[si];
4826                         dbd = &dpr->rx_std[di];
4827                         dbd->addr_hi = sbd->addr_hi;
4828                         dbd->addr_lo = sbd->addr_lo;
4829                 }
4830
4831                 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) %
4832                                        TG3_RX_RING_SIZE;
4833                 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) %
4834                                        TG3_RX_RING_SIZE;
4835         }
4836
4837         while (1) {
4838                 src_prod_idx = spr->rx_jmb_prod_idx;
4839
4840                 /* Make sure updates to the rx_jmb_buffers[] entries and
4841                  * the jumbo producer index are seen in the correct order.
4842                  */
4843                 smp_rmb();
4844
4845                 if (spr->rx_jmb_cons_idx == src_prod_idx)
4846                         break;
4847
4848                 if (spr->rx_jmb_cons_idx < src_prod_idx)
4849                         cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
4850                 else
4851                         cpycnt = TG3_RX_JUMBO_RING_SIZE - spr->rx_jmb_cons_idx;
4852
4853                 cpycnt = min(cpycnt,
4854                              TG3_RX_JUMBO_RING_SIZE - dpr->rx_jmb_prod_idx);
4855
4856                 si = spr->rx_jmb_cons_idx;
4857                 di = dpr->rx_jmb_prod_idx;
4858
4859                 memcpy(&dpr->rx_jmb_buffers[di],
4860                        &spr->rx_jmb_buffers[si],
4861                        cpycnt * sizeof(struct ring_info));
4862
4863                 for (i = 0; i < cpycnt; i++, di++, si++) {
4864                         struct tg3_rx_buffer_desc *sbd, *dbd;
4865                         sbd = &spr->rx_jmb[si].std;
4866                         dbd = &dpr->rx_jmb[di].std;
4867                         dbd->addr_hi = sbd->addr_hi;
4868                         dbd->addr_lo = sbd->addr_lo;
4869                 }
4870
4871                 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) %
4872                                        TG3_RX_JUMBO_RING_SIZE;
4873                 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) %
4874                                        TG3_RX_JUMBO_RING_SIZE;
4875         }
4876 }
4877
4878 static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
4879 {
4880         struct tg3 *tp = tnapi->tp;
4881
4882         /* run TX completion thread */
4883         if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
4884                 tg3_tx(tnapi);
4885                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4886                         return work_done;
4887         }
4888
4889         /* run RX thread, within the bounds set by NAPI.
4890          * All RX "locking" is done by ensuring outside
4891          * code synchronizes with tg3->napi.poll()
4892          */
4893         if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
4894                 work_done += tg3_rx(tnapi, budget - work_done);
4895
4896         if ((tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) && tnapi == &tp->napi[1]) {
4897                 struct tg3_rx_prodring_set *dpr = &tp->prodring[0];
4898                 int i;
4899                 u32 std_prod_idx = dpr->rx_std_prod_idx;
4900                 u32 jmb_prod_idx = dpr->rx_jmb_prod_idx;
4901
4902                 for (i = 1; i < tp->irq_cnt; i++)
4903                         tg3_rx_prodring_xfer(tp, dpr, tp->napi[i].prodring);
4904
4905                 wmb();
4906
4907                 if (std_prod_idx != dpr->rx_std_prod_idx)
4908                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4909                                      dpr->rx_std_prod_idx);
4910
4911                 if (jmb_prod_idx != dpr->rx_jmb_prod_idx)
4912                         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
4913                                      dpr->rx_jmb_prod_idx);
4914
4915                 mmiowb();
4916         }
4917
4918         return work_done;
4919 }
4920
4921 static int tg3_poll_msix(struct napi_struct *napi, int budget)
4922 {
4923         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
4924         struct tg3 *tp = tnapi->tp;
4925         int work_done = 0;
4926         struct tg3_hw_status *sblk = tnapi->hw_status;
4927
4928         while (1) {
4929                 work_done = tg3_poll_work(tnapi, work_done, budget);
4930
4931                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4932                         goto tx_recovery;
4933
4934                 if (unlikely(work_done >= budget))
4935                         break;
4936
4937                 /* tp->last_tag is used in tg3_restart_ints() below
4938                  * to tell the hw how much work has been processed,
4939                  * so we must read it before checking for more work.
4940                  */
4941                 tnapi->last_tag = sblk->status_tag;
4942                 tnapi->last_irq_tag = tnapi->last_tag;
4943                 rmb();
4944
4945                 /* check for RX/TX work to do */
4946                 if (sblk->idx[0].tx_consumer == tnapi->tx_cons &&
4947                     *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr) {
4948                         napi_complete(napi);
4949                         /* Reenable interrupts. */
4950                         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
4951                         mmiowb();
4952                         break;
4953                 }
4954         }
4955
4956         return work_done;
4957
4958 tx_recovery:
4959         /* work_done is guaranteed to be less than budget. */
4960         napi_complete(napi);
4961         schedule_work(&tp->reset_task);
4962         return work_done;
4963 }
4964
4965 static int tg3_poll(struct napi_struct *napi, int budget)
4966 {
4967         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
4968         struct tg3 *tp = tnapi->tp;
4969         int work_done = 0;
4970         struct tg3_hw_status *sblk = tnapi->hw_status;
4971
4972         while (1) {
4973                 tg3_poll_link(tp);
4974
4975                 work_done = tg3_poll_work(tnapi, work_done, budget);
4976
4977                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4978                         goto tx_recovery;
4979
4980                 if (unlikely(work_done >= budget))
4981                         break;
4982
4983                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
4984                         /* tp->last_tag is used in tg3_int_reenable() below
4985                          * to tell the hw how much work has been processed,
4986                          * so we must read it before checking for more work.
4987                          */
4988                         tnapi->last_tag = sblk->status_tag;
4989                         tnapi->last_irq_tag = tnapi->last_tag;
4990                         rmb();
4991                 } else
4992                         sblk->status &= ~SD_STATUS_UPDATED;
4993
4994                 if (likely(!tg3_has_work(tnapi))) {
4995                         napi_complete(napi);
4996                         tg3_int_reenable(tnapi);
4997                         break;
4998                 }
4999         }
5000
5001         return work_done;
5002
5003 tx_recovery:
5004         /* work_done is guaranteed to be less than budget. */
5005         napi_complete(napi);
5006         schedule_work(&tp->reset_task);
5007         return work_done;
5008 }
5009
5010 static void tg3_irq_quiesce(struct tg3 *tp)
5011 {
5012         int i;
5013
5014         BUG_ON(tp->irq_sync);
5015
5016         tp->irq_sync = 1;
5017         smp_mb();
5018
5019         for (i = 0; i < tp->irq_cnt; i++)
5020                 synchronize_irq(tp->napi[i].irq_vec);
5021 }
5022
5023 static inline int tg3_irq_sync(struct tg3 *tp)
5024 {
5025         return tp->irq_sync;
5026 }
5027
5028 /* Fully shutdown all tg3 driver activity elsewhere in the system.
5029  * If irq_sync is non-zero, then the IRQ handler must be synchronized
5030  * with as well.  Most of the time, this is not necessary except when
5031  * shutting down the device.
5032  */
5033 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
5034 {
5035         spin_lock_bh(&tp->lock);
5036         if (irq_sync)
5037                 tg3_irq_quiesce(tp);
5038 }
5039
5040 static inline void tg3_full_unlock(struct tg3 *tp)
5041 {
5042         spin_unlock_bh(&tp->lock);
5043 }
5044
5045 /* One-shot MSI handler - Chip automatically disables interrupt
5046  * after sending MSI so driver doesn't have to do it.
5047  */
5048 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
5049 {
5050         struct tg3_napi *tnapi = dev_id;
5051         struct tg3 *tp = tnapi->tp;
5052
5053         prefetch(tnapi->hw_status);
5054         if (tnapi->rx_rcb)
5055                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5056
5057         if (likely(!tg3_irq_sync(tp)))
5058                 napi_schedule(&tnapi->napi);
5059
5060         return IRQ_HANDLED;
5061 }
5062
5063 /* MSI ISR - No need to check for interrupt sharing and no need to
5064  * flush status block and interrupt mailbox. PCI ordering rules
5065  * guarantee that MSI will arrive after the status block.
5066  */
5067 static irqreturn_t tg3_msi(int irq, void *dev_id)
5068 {
5069         struct tg3_napi *tnapi = dev_id;
5070         struct tg3 *tp = tnapi->tp;
5071
5072         prefetch(tnapi->hw_status);
5073         if (tnapi->rx_rcb)
5074                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5075         /*
5076          * Writing any value to intr-mbox-0 clears PCI INTA# and
5077          * chip-internal interrupt pending events.
5078          * Writing non-zero to intr-mbox-0 additional tells the
5079          * NIC to stop sending us irqs, engaging "in-intr-handler"
5080          * event coalescing.
5081          */
5082         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5083         if (likely(!tg3_irq_sync(tp)))
5084                 napi_schedule(&tnapi->napi);
5085
5086         return IRQ_RETVAL(1);
5087 }
5088
5089 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
5090 {
5091         struct tg3_napi *tnapi = dev_id;
5092         struct tg3 *tp = tnapi->tp;
5093         struct tg3_hw_status *sblk = tnapi->hw_status;
5094         unsigned int handled = 1;
5095
5096         /* In INTx mode, it is possible for the interrupt to arrive at
5097          * the CPU before the status block posted prior to the interrupt.
5098          * Reading the PCI State register will confirm whether the
5099          * interrupt is ours and will flush the status block.
5100          */
5101         if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
5102                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5103                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5104                         handled = 0;
5105                         goto out;
5106                 }
5107         }
5108
5109         /*
5110          * Writing any value to intr-mbox-0 clears PCI INTA# and
5111          * chip-internal interrupt pending events.
5112          * Writing non-zero to intr-mbox-0 additional tells the
5113          * NIC to stop sending us irqs, engaging "in-intr-handler"
5114          * event coalescing.
5115          *
5116          * Flush the mailbox to de-assert the IRQ immediately to prevent
5117          * spurious interrupts.  The flush impacts performance but
5118          * excessive spurious interrupts can be worse in some cases.
5119          */
5120         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5121         if (tg3_irq_sync(tp))
5122                 goto out;
5123         sblk->status &= ~SD_STATUS_UPDATED;
5124         if (likely(tg3_has_work(tnapi))) {
5125                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5126                 napi_schedule(&tnapi->napi);
5127         } else {
5128                 /* No work, shared interrupt perhaps?  re-enable
5129                  * interrupts, and flush that PCI write
5130                  */
5131                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
5132                                0x00000000);
5133         }
5134 out:
5135         return IRQ_RETVAL(handled);
5136 }
5137
5138 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
5139 {
5140         struct tg3_napi *tnapi = dev_id;
5141         struct tg3 *tp = tnapi->tp;
5142         struct tg3_hw_status *sblk = tnapi->hw_status;
5143         unsigned int handled = 1;
5144
5145         /* In INTx mode, it is possible for the interrupt to arrive at
5146          * the CPU before the status block posted prior to the interrupt.
5147          * Reading the PCI State register will confirm whether the
5148          * interrupt is ours and will flush the status block.
5149          */
5150         if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
5151                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5152                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5153                         handled = 0;
5154                         goto out;
5155                 }
5156         }
5157
5158         /*
5159          * writing any value to intr-mbox-0 clears PCI INTA# and
5160          * chip-internal interrupt pending events.
5161          * writing non-zero to intr-mbox-0 additional tells the
5162          * NIC to stop sending us irqs, engaging "in-intr-handler"
5163          * event coalescing.
5164          *
5165          * Flush the mailbox to de-assert the IRQ immediately to prevent
5166          * spurious interrupts.  The flush impacts performance but
5167          * excessive spurious interrupts can be worse in some cases.
5168          */
5169         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5170
5171         /*
5172          * In a shared interrupt configuration, sometimes other devices'
5173          * interrupts will scream.  We record the current status tag here
5174          * so that the above check can report that the screaming interrupts
5175          * are unhandled.  Eventually they will be silenced.
5176          */
5177         tnapi->last_irq_tag = sblk->status_tag;
5178
5179         if (tg3_irq_sync(tp))
5180                 goto out;
5181
5182         prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5183
5184         napi_schedule(&tnapi->napi);
5185
5186 out:
5187         return IRQ_RETVAL(handled);
5188 }
5189
5190 /* ISR for interrupt test */
5191 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
5192 {
5193         struct tg3_napi *tnapi = dev_id;
5194         struct tg3 *tp = tnapi->tp;
5195         struct tg3_hw_status *sblk = tnapi->hw_status;
5196
5197         if ((sblk->status & SD_STATUS_UPDATED) ||
5198             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5199                 tg3_disable_ints(tp);
5200                 return IRQ_RETVAL(1);
5201         }
5202         return IRQ_RETVAL(0);
5203 }
5204
5205 static int tg3_init_hw(struct tg3 *, int);
5206 static int tg3_halt(struct tg3 *, int, int);
5207
5208 /* Restart hardware after configuration changes, self-test, etc.
5209  * Invoked with tp->lock held.
5210  */
5211 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
5212         __releases(tp->lock)
5213         __acquires(tp->lock)
5214 {
5215         int err;
5216
5217         err = tg3_init_hw(tp, reset_phy);
5218         if (err) {
5219                 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
5220                        "aborting.\n", tp->dev->name);
5221                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5222                 tg3_full_unlock(tp);
5223                 del_timer_sync(&tp->timer);
5224                 tp->irq_sync = 0;
5225                 tg3_napi_enable(tp);
5226                 dev_close(tp->dev);
5227                 tg3_full_lock(tp, 0);
5228         }
5229         return err;
5230 }
5231
5232 #ifdef CONFIG_NET_POLL_CONTROLLER
5233 static void tg3_poll_controller(struct net_device *dev)
5234 {
5235         int i;
5236         struct tg3 *tp = netdev_priv(dev);
5237
5238         for (i = 0; i < tp->irq_cnt; i++)
5239                 tg3_interrupt(tp->napi[i].irq_vec, dev);
5240 }
5241 #endif
5242
5243 static void tg3_reset_task(struct work_struct *work)
5244 {
5245         struct tg3 *tp = container_of(work, struct tg3, reset_task);
5246         int err;
5247         unsigned int restart_timer;
5248
5249         tg3_full_lock(tp, 0);
5250
5251         if (!netif_running(tp->dev)) {
5252                 tg3_full_unlock(tp);
5253                 return;
5254         }
5255
5256         tg3_full_unlock(tp);
5257
5258         tg3_phy_stop(tp);
5259
5260         tg3_netif_stop(tp);
5261
5262         tg3_full_lock(tp, 1);
5263
5264         restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
5265         tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
5266
5267         if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
5268                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
5269                 tp->write32_rx_mbox = tg3_write_flush_reg32;
5270                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
5271                 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
5272         }
5273
5274         tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
5275         err = tg3_init_hw(tp, 1);
5276         if (err)
5277                 goto out;
5278
5279         tg3_netif_start(tp);
5280
5281         if (restart_timer)
5282                 mod_timer(&tp->timer, jiffies + 1);
5283
5284 out:
5285         tg3_full_unlock(tp);
5286
5287         if (!err)
5288                 tg3_phy_start(tp);
5289 }
5290
5291 static void tg3_dump_short_state(struct tg3 *tp)
5292 {
5293         printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5294                tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
5295         printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5296                tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
5297 }
5298
5299 static void tg3_tx_timeout(struct net_device *dev)
5300 {
5301         struct tg3 *tp = netdev_priv(dev);
5302
5303         if (netif_msg_tx_err(tp)) {
5304                 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
5305                        dev->name);
5306                 tg3_dump_short_state(tp);
5307         }
5308
5309         schedule_work(&tp->reset_task);
5310 }
5311
5312 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5313 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5314 {
5315         u32 base = (u32) mapping & 0xffffffff;
5316
5317         return ((base > 0xffffdcc0) &&
5318                 (base + len + 8 < base));
5319 }
5320
5321 /* Test for DMA addresses > 40-bit */
5322 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5323                                           int len)
5324 {
5325 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
5326         if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
5327                 return (((u64) mapping + len) > DMA_BIT_MASK(40));
5328         return 0;
5329 #else
5330         return 0;
5331 #endif
5332 }
5333
5334 static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32);
5335
5336 /* Workaround 4GB and 40-bit hardware DMA bugs. */
5337 static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
5338                                        struct sk_buff *skb, u32 last_plus_one,
5339                                        u32 *start, u32 base_flags, u32 mss)
5340 {
5341         struct tg3 *tp = tnapi->tp;
5342         struct sk_buff *new_skb;
5343         dma_addr_t new_addr = 0;
5344         u32 entry = *start;
5345         int i, ret = 0;
5346
5347         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5348                 new_skb = skb_copy(skb, GFP_ATOMIC);
5349         else {
5350                 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5351
5352                 new_skb = skb_copy_expand(skb,
5353                                           skb_headroom(skb) + more_headroom,
5354                                           skb_tailroom(skb), GFP_ATOMIC);
5355         }
5356
5357         if (!new_skb) {
5358                 ret = -1;
5359         } else {
5360                 /* New SKB is guaranteed to be linear. */
5361                 entry = *start;
5362                 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
5363                                           PCI_DMA_TODEVICE);
5364                 /* Make sure the mapping succeeded */
5365                 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
5366                         ret = -1;
5367                         dev_kfree_skb(new_skb);
5368                         new_skb = NULL;
5369
5370                 /* Make sure new skb does not cross any 4G boundaries.
5371                  * Drop the packet if it does.
5372                  */
5373                 } else if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5374                             tg3_4g_overflow_test(new_addr, new_skb->len)) {
5375                         pci_unmap_single(tp->pdev, new_addr, new_skb->len,
5376                                          PCI_DMA_TODEVICE);
5377                         ret = -1;
5378                         dev_kfree_skb(new_skb);
5379                         new_skb = NULL;
5380                 } else {
5381                         tg3_set_txd(tnapi, entry, new_addr, new_skb->len,
5382                                     base_flags, 1 | (mss << 1));
5383                         *start = NEXT_TX(entry);
5384                 }
5385         }
5386
5387         /* Now clean up the sw ring entries. */
5388         i = 0;
5389         while (entry != last_plus_one) {
5390                 int len;
5391
5392                 if (i == 0)
5393                         len = skb_headlen(skb);
5394                 else
5395                         len = skb_shinfo(skb)->frags[i-1].size;
5396
5397                 pci_unmap_single(tp->pdev,
5398                                  pci_unmap_addr(&tnapi->tx_buffers[entry],
5399                                                 mapping),
5400                                  len, PCI_DMA_TODEVICE);
5401                 if (i == 0) {
5402                         tnapi->tx_buffers[entry].skb = new_skb;
5403                         pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5404                                            new_addr);
5405                 } else {
5406                         tnapi->tx_buffers[entry].skb = NULL;
5407                 }
5408                 entry = NEXT_TX(entry);
5409                 i++;
5410         }
5411
5412         dev_kfree_skb(skb);
5413
5414         return ret;
5415 }
5416
5417 static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
5418                         dma_addr_t mapping, int len, u32 flags,
5419                         u32 mss_and_is_end)
5420 {
5421         struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
5422         int is_end = (mss_and_is_end & 0x1);
5423         u32 mss = (mss_and_is_end >> 1);
5424         u32 vlan_tag = 0;
5425
5426         if (is_end)
5427                 flags |= TXD_FLAG_END;
5428         if (flags & TXD_FLAG_VLAN) {
5429                 vlan_tag = flags >> 16;
5430                 flags &= 0xffff;
5431         }
5432         vlan_tag |= (mss << TXD_MSS_SHIFT);
5433
5434         txd->addr_hi = ((u64) mapping >> 32);
5435         txd->addr_lo = ((u64) mapping & 0xffffffff);
5436         txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5437         txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5438 }
5439
5440 /* hard_start_xmit for devices that don't have any bugs and
5441  * support TG3_FLG2_HW_TSO_2 and TG3_FLG2_HW_TSO_3 only.
5442  */
5443 static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5444                                   struct net_device *dev)
5445 {
5446         struct tg3 *tp = netdev_priv(dev);
5447         u32 len, entry, base_flags, mss;
5448         dma_addr_t mapping;
5449         struct tg3_napi *tnapi;
5450         struct netdev_queue *txq;
5451         unsigned int i, last;
5452
5453
5454         txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5455         tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5456         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
5457                 tnapi++;
5458
5459         /* We are running in BH disabled context with netif_tx_lock
5460          * and TX reclaim runs via tp->napi.poll inside of a software
5461          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5462          * no IRQ context deadlocks to worry about either.  Rejoice!
5463          */
5464         if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5465                 if (!netif_tx_queue_stopped(txq)) {
5466                         netif_tx_stop_queue(txq);
5467
5468                         /* This is a hard error, log it. */
5469                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5470                                "queue awake!\n", dev->name);
5471                 }
5472                 return NETDEV_TX_BUSY;
5473         }
5474
5475         entry = tnapi->tx_prod;
5476         base_flags = 0;
5477         mss = 0;
5478         if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5479                 int tcp_opt_len, ip_tcp_len;
5480                 u32 hdrlen;
5481
5482                 if (skb_header_cloned(skb) &&
5483                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5484                         dev_kfree_skb(skb);
5485                         goto out_unlock;
5486                 }
5487
5488                 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
5489                         hdrlen = skb_headlen(skb) - ETH_HLEN;
5490                 else {
5491                         struct iphdr *iph = ip_hdr(skb);
5492
5493                         tcp_opt_len = tcp_optlen(skb);
5494                         ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5495
5496                         iph->check = 0;
5497                         iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
5498                         hdrlen = ip_tcp_len + tcp_opt_len;
5499                 }
5500
5501                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5502                         mss |= (hdrlen & 0xc) << 12;
5503                         if (hdrlen & 0x10)
5504                                 base_flags |= 0x00000010;
5505                         base_flags |= (hdrlen & 0x3e0) << 5;
5506                 } else
5507                         mss |= hdrlen << 9;
5508
5509                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5510                                TXD_FLAG_CPU_POST_DMA);
5511
5512                 tcp_hdr(skb)->check = 0;
5513
5514         }
5515         else if (skb->ip_summed == CHECKSUM_PARTIAL)
5516                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5517 #if TG3_VLAN_TAG_USED
5518         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5519                 base_flags |= (TXD_FLAG_VLAN |
5520                                (vlan_tx_tag_get(skb) << 16));
5521 #endif
5522
5523         len = skb_headlen(skb);
5524
5525         /* Queue skb data, a.k.a. the main skb fragment. */
5526         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5527         if (pci_dma_mapping_error(tp->pdev, mapping)) {
5528                 dev_kfree_skb(skb);
5529                 goto out_unlock;
5530         }
5531
5532         tnapi->tx_buffers[entry].skb = skb;
5533         pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
5534
5535         if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
5536             !mss && skb->len > ETH_DATA_LEN)
5537                 base_flags |= TXD_FLAG_JMB_PKT;
5538
5539         tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5540                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5541
5542         entry = NEXT_TX(entry);
5543
5544         /* Now loop through additional data fragments, and queue them. */
5545         if (skb_shinfo(skb)->nr_frags > 0) {
5546                 last = skb_shinfo(skb)->nr_frags - 1;
5547                 for (i = 0; i <= last; i++) {
5548                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5549
5550                         len = frag->size;
5551                         mapping = pci_map_page(tp->pdev,
5552                                                frag->page,
5553                                                frag->page_offset,
5554                                                len, PCI_DMA_TODEVICE);
5555                         if (pci_dma_mapping_error(tp->pdev, mapping))
5556                                 goto dma_error;
5557
5558                         tnapi->tx_buffers[entry].skb = NULL;
5559                         pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5560                                            mapping);
5561
5562                         tg3_set_txd(tnapi, entry, mapping, len,
5563                                     base_flags, (i == last) | (mss << 1));
5564
5565                         entry = NEXT_TX(entry);
5566                 }
5567         }
5568
5569         /* Packets are ready, update Tx producer idx local and on card. */
5570         tw32_tx_mbox(tnapi->prodmbox, entry);
5571
5572         tnapi->tx_prod = entry;
5573         if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5574                 netif_tx_stop_queue(txq);
5575                 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5576                         netif_tx_wake_queue(txq);
5577         }
5578
5579 out_unlock:
5580         mmiowb();
5581
5582         return NETDEV_TX_OK;
5583
5584 dma_error:
5585         last = i;
5586         entry = tnapi->tx_prod;
5587         tnapi->tx_buffers[entry].skb = NULL;
5588         pci_unmap_single(tp->pdev,
5589                          pci_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5590                          skb_headlen(skb),
5591                          PCI_DMA_TODEVICE);
5592         for (i = 0; i <= last; i++) {
5593                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5594                 entry = NEXT_TX(entry);
5595
5596                 pci_unmap_page(tp->pdev,
5597                                pci_unmap_addr(&tnapi->tx_buffers[entry],
5598                                               mapping),
5599                                frag->size, PCI_DMA_TODEVICE);
5600         }
5601
5602         dev_kfree_skb(skb);
5603         return NETDEV_TX_OK;
5604 }
5605
5606 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *,
5607                                           struct net_device *);
5608
5609 /* Use GSO to workaround a rare TSO bug that may be triggered when the
5610  * TSO header is greater than 80 bytes.
5611  */
5612 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5613 {
5614         struct sk_buff *segs, *nskb;
5615         u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
5616
5617         /* Estimate the number of fragments in the worst case */
5618         if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
5619                 netif_stop_queue(tp->dev);
5620                 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
5621                         return NETDEV_TX_BUSY;
5622
5623                 netif_wake_queue(tp->dev);
5624         }
5625
5626         segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
5627         if (IS_ERR(segs))
5628                 goto tg3_tso_bug_end;
5629
5630         do {
5631                 nskb = segs;
5632                 segs = segs->next;
5633                 nskb->next = NULL;
5634                 tg3_start_xmit_dma_bug(nskb, tp->dev);
5635         } while (segs);
5636
5637 tg3_tso_bug_end:
5638         dev_kfree_skb(skb);
5639
5640         return NETDEV_TX_OK;
5641 }
5642
5643 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5644  * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5645  */
5646 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
5647                                           struct net_device *dev)
5648 {
5649         struct tg3 *tp = netdev_priv(dev);
5650         u32 len, entry, base_flags, mss;
5651         int would_hit_hwbug;
5652         dma_addr_t mapping;
5653         struct tg3_napi *tnapi;
5654         struct netdev_queue *txq;
5655         unsigned int i, last;
5656
5657
5658         txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5659         tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5660         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
5661                 tnapi++;
5662
5663         /* We are running in BH disabled context with netif_tx_lock
5664          * and TX reclaim runs via tp->napi.poll inside of a software
5665          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5666          * no IRQ context deadlocks to worry about either.  Rejoice!
5667          */
5668         if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5669                 if (!netif_tx_queue_stopped(txq)) {
5670                         netif_tx_stop_queue(txq);
5671
5672                         /* This is a hard error, log it. */
5673                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5674                                "queue awake!\n", dev->name);
5675                 }
5676                 return NETDEV_TX_BUSY;
5677         }
5678
5679         entry = tnapi->tx_prod;
5680         base_flags = 0;
5681         if (skb->ip_summed == CHECKSUM_PARTIAL)
5682                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5683
5684         if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5685                 struct iphdr *iph;
5686                 u32 tcp_opt_len, ip_tcp_len, hdr_len;
5687
5688                 if (skb_header_cloned(skb) &&
5689                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5690                         dev_kfree_skb(skb);
5691                         goto out_unlock;
5692                 }
5693
5694                 tcp_opt_len = tcp_optlen(skb);
5695                 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5696
5697                 hdr_len = ip_tcp_len + tcp_opt_len;
5698                 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
5699                              (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
5700                         return (tg3_tso_bug(tp, skb));
5701
5702                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5703                                TXD_FLAG_CPU_POST_DMA);
5704
5705                 iph = ip_hdr(skb);
5706                 iph->check = 0;
5707                 iph->tot_len = htons(mss + hdr_len);
5708                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
5709                         tcp_hdr(skb)->check = 0;
5710                         base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
5711                 } else
5712                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5713                                                                  iph->daddr, 0,
5714                                                                  IPPROTO_TCP,
5715                                                                  0);
5716
5717                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5718                         mss |= (hdr_len & 0xc) << 12;
5719                         if (hdr_len & 0x10)
5720                                 base_flags |= 0x00000010;
5721                         base_flags |= (hdr_len & 0x3e0) << 5;
5722                 } else if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)
5723                         mss |= hdr_len << 9;
5724                 else if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_1) ||
5725                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5726                         if (tcp_opt_len || iph->ihl > 5) {
5727                                 int tsflags;
5728
5729                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5730                                 mss |= (tsflags << 11);
5731                         }
5732                 } else {
5733                         if (tcp_opt_len || iph->ihl > 5) {
5734                                 int tsflags;
5735
5736                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5737                                 base_flags |= tsflags << 12;
5738                         }
5739                 }
5740         }
5741 #if TG3_VLAN_TAG_USED
5742         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5743                 base_flags |= (TXD_FLAG_VLAN |
5744                                (vlan_tx_tag_get(skb) << 16));
5745 #endif
5746
5747         if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
5748             !mss && skb->len > ETH_DATA_LEN)
5749                 base_flags |= TXD_FLAG_JMB_PKT;
5750
5751         len = skb_headlen(skb);
5752
5753         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5754         if (pci_dma_mapping_error(tp->pdev, mapping)) {
5755                 dev_kfree_skb(skb);
5756                 goto out_unlock;
5757         }
5758
5759         tnapi->tx_buffers[entry].skb = skb;
5760         pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
5761
5762         would_hit_hwbug = 0;
5763
5764         if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) && len <= 8)
5765                 would_hit_hwbug = 1;
5766
5767         if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5768             tg3_4g_overflow_test(mapping, len))
5769                 would_hit_hwbug = 1;
5770
5771         if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5772             tg3_40bit_overflow_test(tp, mapping, len))
5773                 would_hit_hwbug = 1;
5774
5775         if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
5776                 would_hit_hwbug = 1;
5777
5778         tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5779                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5780
5781         entry = NEXT_TX(entry);
5782
5783         /* Now loop through additional data fragments, and queue them. */
5784         if (skb_shinfo(skb)->nr_frags > 0) {
5785                 last = skb_shinfo(skb)->nr_frags - 1;
5786                 for (i = 0; i <= last; i++) {
5787                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5788
5789                         len = frag->size;
5790                         mapping = pci_map_page(tp->pdev,
5791                                                frag->page,
5792                                                frag->page_offset,
5793                                                len, PCI_DMA_TODEVICE);
5794
5795                         tnapi->tx_buffers[entry].skb = NULL;
5796                         pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5797                                            mapping);
5798                         if (pci_dma_mapping_error(tp->pdev, mapping))
5799                                 goto dma_error;
5800
5801                         if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) &&
5802                             len <= 8)
5803                                 would_hit_hwbug = 1;
5804
5805                         if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5806                             tg3_4g_overflow_test(mapping, len))
5807                                 would_hit_hwbug = 1;
5808
5809                         if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5810                             tg3_40bit_overflow_test(tp, mapping, len))
5811                                 would_hit_hwbug = 1;
5812
5813                         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5814                                 tg3_set_txd(tnapi, entry, mapping, len,
5815                                             base_flags, (i == last)|(mss << 1));
5816                         else
5817                                 tg3_set_txd(tnapi, entry, mapping, len,
5818                                             base_flags, (i == last));
5819
5820                         entry = NEXT_TX(entry);
5821                 }
5822         }
5823
5824         if (would_hit_hwbug) {
5825                 u32 last_plus_one = entry;
5826                 u32 start;
5827
5828                 start = entry - 1 - skb_shinfo(skb)->nr_frags;
5829                 start &= (TG3_TX_RING_SIZE - 1);
5830
5831                 /* If the workaround fails due to memory/mapping
5832                  * failure, silently drop this packet.
5833                  */
5834                 if (tigon3_dma_hwbug_workaround(tnapi, skb, last_plus_one,
5835                                                 &start, base_flags, mss))
5836                         goto out_unlock;
5837
5838                 entry = start;
5839         }
5840
5841         /* Packets are ready, update Tx producer idx local and on card. */
5842         tw32_tx_mbox(tnapi->prodmbox, entry);
5843
5844         tnapi->tx_prod = entry;
5845         if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5846                 netif_tx_stop_queue(txq);
5847                 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5848                         netif_tx_wake_queue(txq);
5849         }
5850
5851 out_unlock:
5852         mmiowb();
5853
5854         return NETDEV_TX_OK;
5855
5856 dma_error:
5857         last = i;
5858         entry = tnapi->tx_prod;
5859         tnapi->tx_buffers[entry].skb = NULL;
5860         pci_unmap_single(tp->pdev,
5861                          pci_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5862                          skb_headlen(skb),
5863                          PCI_DMA_TODEVICE);
5864         for (i = 0; i <= last; i++) {
5865                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5866                 entry = NEXT_TX(entry);
5867
5868                 pci_unmap_page(tp->pdev,
5869                                pci_unmap_addr(&tnapi->tx_buffers[entry],
5870                                               mapping),
5871                                frag->size, PCI_DMA_TODEVICE);
5872         }
5873
5874         dev_kfree_skb(skb);
5875         return NETDEV_TX_OK;
5876 }
5877
5878 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
5879                                int new_mtu)
5880 {
5881         dev->mtu = new_mtu;
5882
5883         if (new_mtu > ETH_DATA_LEN) {
5884                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
5885                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
5886                         ethtool_op_set_tso(dev, 0);
5887                 }
5888                 else
5889                         tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
5890         } else {
5891                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
5892                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
5893                 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
5894         }
5895 }
5896
5897 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
5898 {
5899         struct tg3 *tp = netdev_priv(dev);
5900         int err;
5901
5902         if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
5903                 return -EINVAL;
5904
5905         if (!netif_running(dev)) {
5906                 /* We'll just catch it later when the
5907                  * device is up'd.
5908                  */
5909                 tg3_set_mtu(dev, tp, new_mtu);
5910                 return 0;
5911         }
5912
5913         tg3_phy_stop(tp);
5914
5915         tg3_netif_stop(tp);
5916
5917         tg3_full_lock(tp, 1);
5918
5919         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5920
5921         tg3_set_mtu(dev, tp, new_mtu);
5922
5923         err = tg3_restart_hw(tp, 0);
5924
5925         if (!err)
5926                 tg3_netif_start(tp);
5927
5928         tg3_full_unlock(tp);
5929
5930         if (!err)
5931                 tg3_phy_start(tp);
5932
5933         return err;
5934 }
5935
5936 static void tg3_rx_prodring_free(struct tg3 *tp,
5937                                  struct tg3_rx_prodring_set *tpr)
5938 {
5939         int i;
5940
5941         if (tpr != &tp->prodring[0]) {
5942                 for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx;
5943                      i = (i + 1) % TG3_RX_RING_SIZE)
5944                         tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
5945                                         tp->rx_pkt_map_sz);
5946
5947                 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
5948                         for (i = tpr->rx_jmb_cons_idx;
5949                              i != tpr->rx_jmb_prod_idx;
5950                              i = (i + 1) % TG3_RX_JUMBO_RING_SIZE) {
5951                                 tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
5952                                                 TG3_RX_JMB_MAP_SZ);
5953                         }
5954                 }
5955
5956                 return;
5957         }
5958
5959         for (i = 0; i < TG3_RX_RING_SIZE; i++)
5960                 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
5961                                 tp->rx_pkt_map_sz);
5962
5963         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
5964                 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++)
5965                         tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
5966                                         TG3_RX_JMB_MAP_SZ);
5967         }
5968 }
5969
5970 /* Initialize tx/rx rings for packet processing.
5971  *
5972  * The chip has been shut down and the driver detached from
5973  * the networking, so no interrupts or new tx packets will
5974  * end up in the driver.  tp->{tx,}lock are held and thus
5975  * we may not sleep.
5976  */
5977 static int tg3_rx_prodring_alloc(struct tg3 *tp,
5978                                  struct tg3_rx_prodring_set *tpr)
5979 {
5980         u32 i, rx_pkt_dma_sz;
5981
5982         tpr->rx_std_cons_idx = 0;
5983         tpr->rx_std_prod_idx = 0;
5984         tpr->rx_jmb_cons_idx = 0;
5985         tpr->rx_jmb_prod_idx = 0;
5986
5987         if (tpr != &tp->prodring[0]) {
5988                 memset(&tpr->rx_std_buffers[0], 0, TG3_RX_STD_BUFF_RING_SIZE);
5989                 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE)
5990                         memset(&tpr->rx_jmb_buffers[0], 0,
5991                                TG3_RX_JMB_BUFF_RING_SIZE);
5992                 goto done;
5993         }
5994
5995         /* Zero out all descriptors. */
5996         memset(tpr->rx_std, 0, TG3_RX_RING_BYTES);
5997
5998         rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
5999         if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
6000             tp->dev->mtu > ETH_DATA_LEN)
6001                 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
6002         tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
6003
6004         /* Initialize invariants of the rings, we only set this
6005          * stuff once.  This works because the card does not
6006          * write into the rx buffer posting rings.
6007          */
6008         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
6009                 struct tg3_rx_buffer_desc *rxd;
6010
6011                 rxd = &tpr->rx_std[i];
6012                 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
6013                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
6014                 rxd->opaque = (RXD_OPAQUE_RING_STD |
6015                                (i << RXD_OPAQUE_INDEX_SHIFT));
6016         }
6017
6018         /* Now allocate fresh SKBs for each rx ring. */
6019         for (i = 0; i < tp->rx_pending; i++) {
6020                 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_STD, i) < 0) {
6021                         printk(KERN_WARNING PFX
6022                                "%s: Using a smaller RX standard ring, "
6023                                "only %d out of %d buffers were allocated "
6024                                "successfully.\n",
6025                                tp->dev->name, i, tp->rx_pending);
6026                         if (i == 0)
6027                                 goto initfail;
6028                         tp->rx_pending = i;
6029                         break;
6030                 }
6031         }
6032
6033         if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE))
6034                 goto done;
6035
6036         memset(tpr->rx_jmb, 0, TG3_RX_JUMBO_RING_BYTES);
6037
6038         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
6039                 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
6040                         struct tg3_rx_buffer_desc *rxd;
6041
6042                         rxd = &tpr->rx_jmb[i].std;
6043                         rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
6044                         rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
6045                                 RXD_FLAG_JUMBO;
6046                         rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
6047                                (i << RXD_OPAQUE_INDEX_SHIFT));
6048                 }
6049
6050                 for (i = 0; i < tp->rx_jumbo_pending; i++) {
6051                         if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_JUMBO,
6052                                              i) < 0) {
6053                                 printk(KERN_WARNING PFX
6054                                        "%s: Using a smaller RX jumbo ring, "
6055                                        "only %d out of %d buffers were "
6056                                        "allocated successfully.\n",
6057                                        tp->dev->name, i, tp->rx_jumbo_pending);
6058                                 if (i == 0)
6059                                         goto initfail;
6060                                 tp->rx_jumbo_pending = i;
6061                                 break;
6062                         }
6063                 }
6064         }
6065
6066 done:
6067         return 0;
6068
6069 initfail:
6070         tg3_rx_prodring_free(tp, tpr);
6071         return -ENOMEM;
6072 }
6073
6074 static void tg3_rx_prodring_fini(struct tg3 *tp,
6075                                  struct tg3_rx_prodring_set *tpr)
6076 {
6077         kfree(tpr->rx_std_buffers);
6078         tpr->rx_std_buffers = NULL;
6079         kfree(tpr->rx_jmb_buffers);
6080         tpr->rx_jmb_buffers = NULL;
6081         if (tpr->rx_std) {
6082                 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
6083                                     tpr->rx_std, tpr->rx_std_mapping);
6084                 tpr->rx_std = NULL;
6085         }
6086         if (tpr->rx_jmb) {
6087                 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
6088                                     tpr->rx_jmb, tpr->rx_jmb_mapping);
6089                 tpr->rx_jmb = NULL;
6090         }
6091 }
6092
6093 static int tg3_rx_prodring_init(struct tg3 *tp,
6094                                 struct tg3_rx_prodring_set *tpr)
6095 {
6096         tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE, GFP_KERNEL);
6097         if (!tpr->rx_std_buffers)
6098                 return -ENOMEM;
6099
6100         tpr->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
6101                                            &tpr->rx_std_mapping);
6102         if (!tpr->rx_std)
6103                 goto err_out;
6104
6105         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
6106                 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE,
6107                                               GFP_KERNEL);
6108                 if (!tpr->rx_jmb_buffers)
6109                         goto err_out;
6110
6111                 tpr->rx_jmb = pci_alloc_consistent(tp->pdev,
6112                                                    TG3_RX_JUMBO_RING_BYTES,
6113                                                    &tpr->rx_jmb_mapping);
6114                 if (!tpr->rx_jmb)
6115                         goto err_out;
6116         }
6117
6118         return 0;
6119
6120 err_out:
6121         tg3_rx_prodring_fini(tp, tpr);
6122         return -ENOMEM;
6123 }
6124
6125 /* Free up pending packets in all rx/tx rings.
6126  *
6127  * The chip has been shut down and the driver detached from
6128  * the networking, so no interrupts or new tx packets will
6129  * end up in the driver.  tp->{tx,}lock is not held and we are not
6130  * in an interrupt context and thus may sleep.
6131  */
6132 static void tg3_free_rings(struct tg3 *tp)
6133 {
6134         int i, j;
6135
6136         for (j = 0; j < tp->irq_cnt; j++) {
6137                 struct tg3_napi *tnapi = &tp->napi[j];
6138
6139                 if (!tnapi->tx_buffers)
6140                         continue;
6141
6142                 for (i = 0; i < TG3_TX_RING_SIZE; ) {
6143                         struct ring_info *txp;
6144                         struct sk_buff *skb;
6145                         unsigned int k;
6146
6147                         txp = &tnapi->tx_buffers[i];
6148                         skb = txp->skb;
6149
6150                         if (skb == NULL) {
6151                                 i++;
6152                                 continue;
6153                         }
6154
6155                         pci_unmap_single(tp->pdev,
6156                                          pci_unmap_addr(txp, mapping),
6157                                          skb_headlen(skb),
6158                                          PCI_DMA_TODEVICE);
6159                         txp->skb = NULL;
6160
6161                         i++;
6162
6163                         for (k = 0; k < skb_shinfo(skb)->nr_frags; k++) {
6164                                 txp = &tnapi->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
6165                                 pci_unmap_page(tp->pdev,
6166                                                pci_unmap_addr(txp, mapping),
6167                                                skb_shinfo(skb)->frags[k].size,
6168                                                PCI_DMA_TODEVICE);
6169                                 i++;
6170                         }
6171
6172                         dev_kfree_skb_any(skb);
6173                 }
6174
6175                 tg3_rx_prodring_free(tp, &tp->prodring[j]);
6176         }
6177 }
6178
6179 /* Initialize tx/rx rings for packet processing.
6180  *
6181  * The chip has been shut down and the driver detached from
6182  * the networking, so no interrupts or new tx packets will
6183  * end up in the driver.  tp->{tx,}lock are held and thus
6184  * we may not sleep.
6185  */
6186 static int tg3_init_rings(struct tg3 *tp)
6187 {
6188         int i;
6189
6190         /* Free up all the SKBs. */
6191         tg3_free_rings(tp);
6192
6193         for (i = 0; i < tp->irq_cnt; i++) {
6194                 struct tg3_napi *tnapi = &tp->napi[i];
6195
6196                 tnapi->last_tag = 0;
6197                 tnapi->last_irq_tag = 0;
6198                 tnapi->hw_status->status = 0;
6199                 tnapi->hw_status->status_tag = 0;
6200                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6201
6202                 tnapi->tx_prod = 0;
6203                 tnapi->tx_cons = 0;
6204                 if (tnapi->tx_ring)
6205                         memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
6206
6207                 tnapi->rx_rcb_ptr = 0;
6208                 if (tnapi->rx_rcb)
6209                         memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6210
6211                 if (tg3_rx_prodring_alloc(tp, &tp->prodring[i])) {
6212                         tg3_free_rings(tp);
6213                         return -ENOMEM;
6214                 }
6215         }
6216
6217         return 0;
6218 }
6219
6220 /*
6221  * Must not be invoked with interrupt sources disabled and
6222  * the hardware shutdown down.
6223  */
6224 static void tg3_free_consistent(struct tg3 *tp)
6225 {
6226         int i;
6227
6228         for (i = 0; i < tp->irq_cnt; i++) {
6229                 struct tg3_napi *tnapi = &tp->napi[i];
6230
6231                 if (tnapi->tx_ring) {
6232                         pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
6233                                 tnapi->tx_ring, tnapi->tx_desc_mapping);
6234                         tnapi->tx_ring = NULL;
6235                 }
6236
6237                 kfree(tnapi->tx_buffers);
6238                 tnapi->tx_buffers = NULL;
6239
6240                 if (tnapi->rx_rcb) {
6241                         pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
6242                                             tnapi->rx_rcb,
6243                                             tnapi->rx_rcb_mapping);
6244                         tnapi->rx_rcb = NULL;
6245                 }
6246
6247                 if (tnapi->hw_status) {
6248                         pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
6249                                             tnapi->hw_status,
6250                                             tnapi->status_mapping);
6251                         tnapi->hw_status = NULL;
6252                 }
6253         }
6254
6255         if (tp->hw_stats) {
6256                 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
6257                                     tp->hw_stats, tp->stats_mapping);
6258                 tp->hw_stats = NULL;
6259         }
6260
6261         for (i = 0; i < tp->irq_cnt; i++)
6262                 tg3_rx_prodring_fini(tp, &tp->prodring[i]);
6263 }
6264
6265 /*
6266  * Must not be invoked with interrupt sources disabled and
6267  * the hardware shutdown down.  Can sleep.
6268  */
6269 static int tg3_alloc_consistent(struct tg3 *tp)
6270 {
6271         int i;
6272
6273         for (i = 0; i < tp->irq_cnt; i++) {
6274                 if (tg3_rx_prodring_init(tp, &tp->prodring[i]))
6275                         goto err_out;
6276         }
6277
6278         tp->hw_stats = pci_alloc_consistent(tp->pdev,
6279                                             sizeof(struct tg3_hw_stats),
6280                                             &tp->stats_mapping);
6281         if (!tp->hw_stats)
6282                 goto err_out;
6283
6284         memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6285
6286         for (i = 0; i < tp->irq_cnt; i++) {
6287                 struct tg3_napi *tnapi = &tp->napi[i];
6288                 struct tg3_hw_status *sblk;
6289
6290                 tnapi->hw_status = pci_alloc_consistent(tp->pdev,
6291                                                         TG3_HW_STATUS_SIZE,
6292                                                         &tnapi->status_mapping);
6293                 if (!tnapi->hw_status)
6294                         goto err_out;
6295
6296                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6297                 sblk = tnapi->hw_status;
6298
6299                 /* If multivector TSS is enabled, vector 0 does not handle
6300                  * tx interrupts.  Don't allocate any resources for it.
6301                  */
6302                 if ((!i && !(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) ||
6303                     (i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))) {
6304                         tnapi->tx_buffers = kzalloc(sizeof(struct ring_info) *
6305                                                     TG3_TX_RING_SIZE,
6306                                                     GFP_KERNEL);
6307                         if (!tnapi->tx_buffers)
6308                                 goto err_out;
6309
6310                         tnapi->tx_ring = pci_alloc_consistent(tp->pdev,
6311                                                               TG3_TX_RING_BYTES,
6312                                                        &tnapi->tx_desc_mapping);
6313                         if (!tnapi->tx_ring)
6314                                 goto err_out;
6315                 }
6316
6317                 /*
6318                  * When RSS is enabled, the status block format changes
6319                  * slightly.  The "rx_jumbo_consumer", "reserved",
6320                  * and "rx_mini_consumer" members get mapped to the
6321                  * other three rx return ring producer indexes.
6322                  */
6323                 switch (i) {
6324                 default:
6325                         tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
6326                         break;
6327                 case 2:
6328                         tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer;
6329                         break;
6330                 case 3:
6331                         tnapi->rx_rcb_prod_idx = &sblk->reserved;
6332                         break;
6333                 case 4:
6334                         tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer;
6335                         break;
6336                 }
6337
6338                 tnapi->prodring = &tp->prodring[i];
6339
6340                 /*
6341                  * If multivector RSS is enabled, vector 0 does not handle
6342                  * rx or tx interrupts.  Don't allocate any resources for it.
6343                  */
6344                 if (!i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS))
6345                         continue;
6346
6347                 tnapi->rx_rcb = pci_alloc_consistent(tp->pdev,
6348                                                      TG3_RX_RCB_RING_BYTES(tp),
6349                                                      &tnapi->rx_rcb_mapping);
6350                 if (!tnapi->rx_rcb)
6351                         goto err_out;
6352
6353                 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6354         }
6355
6356         return 0;
6357
6358 err_out:
6359         tg3_free_consistent(tp);
6360         return -ENOMEM;
6361 }
6362
6363 #define MAX_WAIT_CNT 1000
6364
6365 /* To stop a block, clear the enable bit and poll till it
6366  * clears.  tp->lock is held.
6367  */
6368 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
6369 {
6370         unsigned int i;
6371         u32 val;
6372
6373         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6374                 switch (ofs) {
6375                 case RCVLSC_MODE:
6376                 case DMAC_MODE:
6377                 case MBFREE_MODE:
6378                 case BUFMGR_MODE:
6379                 case MEMARB_MODE:
6380                         /* We can't enable/disable these bits of the
6381                          * 5705/5750, just say success.
6382                          */
6383                         return 0;
6384
6385                 default:
6386                         break;
6387                 }
6388         }
6389
6390         val = tr32(ofs);
6391         val &= ~enable_bit;
6392         tw32_f(ofs, val);
6393
6394         for (i = 0; i < MAX_WAIT_CNT; i++) {
6395                 udelay(100);
6396                 val = tr32(ofs);
6397                 if ((val & enable_bit) == 0)
6398                         break;
6399         }
6400
6401         if (i == MAX_WAIT_CNT && !silent) {
6402                 printk(KERN_ERR PFX "tg3_stop_block timed out, "
6403                        "ofs=%lx enable_bit=%x\n",
6404                        ofs, enable_bit);
6405                 return -ENODEV;
6406         }
6407
6408         return 0;
6409 }
6410
6411 /* tp->lock is held. */
6412 static int tg3_abort_hw(struct tg3 *tp, int silent)
6413 {
6414         int i, err;
6415
6416         tg3_disable_ints(tp);
6417
6418         tp->rx_mode &= ~RX_MODE_ENABLE;
6419         tw32_f(MAC_RX_MODE, tp->rx_mode);
6420         udelay(10);
6421
6422         err  = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
6423         err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
6424         err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
6425         err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
6426         err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
6427         err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
6428
6429         err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
6430         err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
6431         err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
6432         err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
6433         err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
6434         err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
6435         err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
6436
6437         tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
6438         tw32_f(MAC_MODE, tp->mac_mode);
6439         udelay(40);
6440
6441         tp->tx_mode &= ~TX_MODE_ENABLE;
6442         tw32_f(MAC_TX_MODE, tp->tx_mode);
6443
6444         for (i = 0; i < MAX_WAIT_CNT; i++) {
6445                 udelay(100);
6446                 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
6447                         break;
6448         }
6449         if (i >= MAX_WAIT_CNT) {
6450                 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
6451                        "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
6452                        tp->dev->name, tr32(MAC_TX_MODE));
6453                 err |= -ENODEV;
6454         }
6455
6456         err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
6457         err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
6458         err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
6459
6460         tw32(FTQ_RESET, 0xffffffff);
6461         tw32(FTQ_RESET, 0x00000000);
6462
6463         err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
6464         err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
6465
6466         for (i = 0; i < tp->irq_cnt; i++) {
6467                 struct tg3_napi *tnapi = &tp->napi[i];
6468                 if (tnapi->hw_status)
6469                         memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6470         }
6471         if (tp->hw_stats)
6472                 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6473
6474         return err;
6475 }
6476
6477 static void tg3_ape_send_event(struct tg3 *tp, u32 event)
6478 {
6479         int i;
6480         u32 apedata;
6481
6482         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
6483         if (apedata != APE_SEG_SIG_MAGIC)
6484                 return;
6485
6486         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
6487         if (!(apedata & APE_FW_STATUS_READY))
6488                 return;
6489
6490         /* Wait for up to 1 millisecond for APE to service previous event. */
6491         for (i = 0; i < 10; i++) {
6492                 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
6493                         return;
6494
6495                 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
6496
6497                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6498                         tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
6499                                         event | APE_EVENT_STATUS_EVENT_PENDING);
6500
6501                 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
6502
6503                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6504                         break;
6505
6506                 udelay(100);
6507         }
6508
6509         if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6510                 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
6511 }
6512
6513 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
6514 {
6515         u32 event;
6516         u32 apedata;
6517
6518         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
6519                 return;
6520
6521         switch (kind) {
6522                 case RESET_KIND_INIT:
6523                         tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
6524                                         APE_HOST_SEG_SIG_MAGIC);
6525                         tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
6526                                         APE_HOST_SEG_LEN_MAGIC);
6527                         apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
6528                         tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
6529                         tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
6530                                         APE_HOST_DRIVER_ID_MAGIC);
6531                         tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
6532                                         APE_HOST_BEHAV_NO_PHYLOCK);
6533
6534                         event = APE_EVENT_STATUS_STATE_START;
6535                         break;
6536                 case RESET_KIND_SHUTDOWN:
6537                         /* With the interface we are currently using,
6538                          * APE does not track driver state.  Wiping
6539                          * out the HOST SEGMENT SIGNATURE forces
6540                          * the APE to assume OS absent status.
6541                          */
6542                         tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
6543
6544                         event = APE_EVENT_STATUS_STATE_UNLOAD;
6545                         break;
6546                 case RESET_KIND_SUSPEND:
6547                         event = APE_EVENT_STATUS_STATE_SUSPEND;
6548                         break;
6549                 default:
6550                         return;
6551         }
6552
6553         event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
6554
6555         tg3_ape_send_event(tp, event);
6556 }
6557
6558 /* tp->lock is held. */
6559 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
6560 {
6561         tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
6562                       NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
6563
6564         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6565                 switch (kind) {
6566                 case RESET_KIND_INIT:
6567                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6568                                       DRV_STATE_START);
6569                         break;
6570
6571                 case RESET_KIND_SHUTDOWN:
6572                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6573                                       DRV_STATE_UNLOAD);
6574                         break;
6575
6576                 case RESET_KIND_SUSPEND:
6577                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6578                                       DRV_STATE_SUSPEND);
6579                         break;
6580
6581                 default:
6582                         break;
6583                 }
6584         }
6585
6586         if (kind == RESET_KIND_INIT ||
6587             kind == RESET_KIND_SUSPEND)
6588                 tg3_ape_driver_state_change(tp, kind);
6589 }
6590
6591 /* tp->lock is held. */
6592 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
6593 {
6594         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6595                 switch (kind) {
6596                 case RESET_KIND_INIT:
6597                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6598                                       DRV_STATE_START_DONE);
6599                         break;
6600
6601                 case RESET_KIND_SHUTDOWN:
6602                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6603                                       DRV_STATE_UNLOAD_DONE);
6604                         break;
6605
6606                 default:
6607                         break;
6608                 }
6609         }
6610
6611         if (kind == RESET_KIND_SHUTDOWN)
6612                 tg3_ape_driver_state_change(tp, kind);
6613 }
6614
6615 /* tp->lock is held. */
6616 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
6617 {
6618         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6619                 switch (kind) {
6620                 case RESET_KIND_INIT:
6621                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6622                                       DRV_STATE_START);
6623                         break;
6624
6625                 case RESET_KIND_SHUTDOWN:
6626                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6627                                       DRV_STATE_UNLOAD);
6628                         break;
6629
6630                 case RESET_KIND_SUSPEND:
6631                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6632                                       DRV_STATE_SUSPEND);
6633                         break;
6634
6635                 default:
6636                         break;
6637                 }
6638         }
6639 }
6640
6641 static int tg3_poll_fw(struct tg3 *tp)
6642 {
6643         int i;
6644         u32 val;
6645
6646         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6647                 /* Wait up to 20ms for init done. */
6648                 for (i = 0; i < 200; i++) {
6649                         if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
6650                                 return 0;
6651                         udelay(100);
6652                 }
6653                 return -ENODEV;
6654         }
6655
6656         /* Wait for firmware initialization to complete. */
6657         for (i = 0; i < 100000; i++) {
6658                 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
6659                 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
6660                         break;
6661                 udelay(10);
6662         }
6663
6664         /* Chip might not be fitted with firmware.  Some Sun onboard
6665          * parts are configured like that.  So don't signal the timeout
6666          * of the above loop as an error, but do report the lack of
6667          * running firmware once.
6668          */
6669         if (i >= 100000 &&
6670             !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
6671                 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
6672
6673                 printk(KERN_INFO PFX "%s: No firmware running.\n",
6674                        tp->dev->name);
6675         }
6676
6677         return 0;
6678 }
6679
6680 /* Save PCI command register before chip reset */
6681 static void tg3_save_pci_state(struct tg3 *tp)
6682 {
6683         pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
6684 }
6685
6686 /* Restore PCI state after chip reset */
6687 static void tg3_restore_pci_state(struct tg3 *tp)
6688 {
6689         u32 val;
6690
6691         /* Re-enable indirect register accesses. */
6692         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
6693                                tp->misc_host_ctrl);
6694
6695         /* Set MAX PCI retry to zero. */
6696         val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
6697         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6698             (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
6699                 val |= PCISTATE_RETRY_SAME_DMA;
6700         /* Allow reads and writes to the APE register and memory space. */
6701         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
6702                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6703                        PCISTATE_ALLOW_APE_SHMEM_WR;
6704         pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
6705
6706         pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
6707
6708         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
6709                 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6710                         pcie_set_readrq(tp->pdev, 4096);
6711                 else {
6712                         pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
6713                                               tp->pci_cacheline_sz);
6714                         pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
6715                                               tp->pci_lat_timer);
6716                 }
6717         }
6718
6719         /* Make sure PCI-X relaxed ordering bit is clear. */
6720         if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
6721                 u16 pcix_cmd;
6722
6723                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6724                                      &pcix_cmd);
6725                 pcix_cmd &= ~PCI_X_CMD_ERO;
6726                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6727                                       pcix_cmd);
6728         }
6729
6730         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
6731
6732                 /* Chip reset on 5780 will reset MSI enable bit,
6733                  * so need to restore it.
6734                  */
6735                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6736                         u16 ctrl;
6737
6738                         pci_read_config_word(tp->pdev,
6739                                              tp->msi_cap + PCI_MSI_FLAGS,
6740                                              &ctrl);
6741                         pci_write_config_word(tp->pdev,
6742                                               tp->msi_cap + PCI_MSI_FLAGS,
6743                                               ctrl | PCI_MSI_FLAGS_ENABLE);
6744                         val = tr32(MSGINT_MODE);
6745                         tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
6746                 }
6747         }
6748 }
6749
6750 static void tg3_stop_fw(struct tg3 *);
6751
6752 /* tp->lock is held. */
6753 static int tg3_chip_reset(struct tg3 *tp)
6754 {
6755         u32 val;
6756         void (*write_op)(struct tg3 *, u32, u32);
6757         int i, err;
6758
6759         tg3_nvram_lock(tp);
6760
6761         tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
6762
6763         /* No matching tg3_nvram_unlock() after this because
6764          * chip reset below will undo the nvram lock.
6765          */
6766         tp->nvram_lock_cnt = 0;
6767
6768         /* GRC_MISC_CFG core clock reset will clear the memory
6769          * enable bit in PCI register 4 and the MSI enable bit
6770          * on some chips, so we save relevant registers here.
6771          */
6772         tg3_save_pci_state(tp);
6773
6774         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
6775             (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
6776                 tw32(GRC_FASTBOOT_PC, 0);
6777
6778         /*
6779          * We must avoid the readl() that normally takes place.
6780          * It locks machines, causes machine checks, and other
6781          * fun things.  So, temporarily disable the 5701
6782          * hardware workaround, while we do the reset.
6783          */
6784         write_op = tp->write32;
6785         if (write_op == tg3_write_flush_reg32)
6786                 tp->write32 = tg3_write32;
6787
6788         /* Prevent the irq handler from reading or writing PCI registers
6789          * during chip reset when the memory enable bit in the PCI command
6790          * register may be cleared.  The chip does not generate interrupt
6791          * at this time, but the irq handler may still be called due to irq
6792          * sharing or irqpoll.
6793          */
6794         tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
6795         for (i = 0; i < tp->irq_cnt; i++) {
6796                 struct tg3_napi *tnapi = &tp->napi[i];
6797                 if (tnapi->hw_status) {
6798                         tnapi->hw_status->status = 0;
6799                         tnapi->hw_status->status_tag = 0;
6800                 }
6801                 tnapi->last_tag = 0;
6802                 tnapi->last_irq_tag = 0;
6803         }
6804         smp_mb();
6805
6806         for (i = 0; i < tp->irq_cnt; i++)
6807                 synchronize_irq(tp->napi[i].irq_vec);
6808
6809         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6810                 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
6811                 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
6812         }
6813
6814         /* do the reset */
6815         val = GRC_MISC_CFG_CORECLK_RESET;
6816
6817         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
6818                 if (tr32(0x7e2c) == 0x60) {
6819                         tw32(0x7e2c, 0x20);
6820                 }
6821                 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6822                         tw32(GRC_MISC_CFG, (1 << 29));
6823                         val |= (1 << 29);
6824                 }
6825         }
6826
6827         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6828                 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
6829                 tw32(GRC_VCPU_EXT_CTRL,
6830                      tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
6831         }
6832
6833         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6834                 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
6835         tw32(GRC_MISC_CFG, val);
6836
6837         /* restore 5701 hardware bug workaround write method */
6838         tp->write32 = write_op;
6839
6840         /* Unfortunately, we have to delay before the PCI read back.
6841          * Some 575X chips even will not respond to a PCI cfg access
6842          * when the reset command is given to the chip.
6843          *
6844          * How do these hardware designers expect things to work
6845          * properly if the PCI write is posted for a long period
6846          * of time?  It is always necessary to have some method by
6847          * which a register read back can occur to push the write
6848          * out which does the reset.
6849          *
6850          * For most tg3 variants the trick below was working.
6851          * Ho hum...
6852          */
6853         udelay(120);
6854
6855         /* Flush PCI posted writes.  The normal MMIO registers
6856          * are inaccessible at this time so this is the only
6857          * way to make this reliably (actually, this is no longer
6858          * the case, see above).  I tried to use indirect
6859          * register read/write but this upset some 5701 variants.
6860          */
6861         pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
6862
6863         udelay(120);
6864
6865         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
6866                 u16 val16;
6867
6868                 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
6869                         int i;
6870                         u32 cfg_val;
6871
6872                         /* Wait for link training to complete.  */
6873                         for (i = 0; i < 5000; i++)
6874                                 udelay(100);
6875
6876                         pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
6877                         pci_write_config_dword(tp->pdev, 0xc4,
6878                                                cfg_val | (1 << 15));
6879                 }
6880
6881                 /* Clear the "no snoop" and "relaxed ordering" bits. */
6882                 pci_read_config_word(tp->pdev,
6883                                      tp->pcie_cap + PCI_EXP_DEVCTL,
6884                                      &val16);
6885                 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
6886                            PCI_EXP_DEVCTL_NOSNOOP_EN);
6887                 /*
6888                  * Older PCIe devices only support the 128 byte
6889                  * MPS setting.  Enforce the restriction.
6890                  */
6891                 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
6892                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784))
6893                         val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
6894                 pci_write_config_word(tp->pdev,
6895                                       tp->pcie_cap + PCI_EXP_DEVCTL,
6896                                       val16);
6897
6898                 pcie_set_readrq(tp->pdev, 4096);
6899
6900                 /* Clear error status */
6901                 pci_write_config_word(tp->pdev,
6902                                       tp->pcie_cap + PCI_EXP_DEVSTA,
6903                                       PCI_EXP_DEVSTA_CED |
6904                                       PCI_EXP_DEVSTA_NFED |
6905                                       PCI_EXP_DEVSTA_FED |
6906                                       PCI_EXP_DEVSTA_URD);
6907         }
6908
6909         tg3_restore_pci_state(tp);
6910
6911         tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
6912
6913         val = 0;
6914         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
6915                 val = tr32(MEMARB_MODE);
6916         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
6917
6918         if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
6919                 tg3_stop_fw(tp);
6920                 tw32(0x5000, 0x400);
6921         }
6922
6923         tw32(GRC_MODE, tp->grc_mode);
6924
6925         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
6926                 val = tr32(0xc4);
6927
6928                 tw32(0xc4, val | (1 << 15));
6929         }
6930
6931         if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
6932             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6933                 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
6934                 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
6935                         tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
6936                 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6937         }
6938
6939         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6940                 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
6941                 tw32_f(MAC_MODE, tp->mac_mode);
6942         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
6943                 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
6944                 tw32_f(MAC_MODE, tp->mac_mode);
6945         } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
6946                 tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
6947                 if (tp->mac_mode & MAC_MODE_APE_TX_EN)
6948                         tp->mac_mode |= MAC_MODE_TDE_ENABLE;
6949                 tw32_f(MAC_MODE, tp->mac_mode);
6950         } else
6951                 tw32_f(MAC_MODE, 0);
6952         udelay(40);
6953
6954         tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
6955
6956         err = tg3_poll_fw(tp);
6957         if (err)
6958                 return err;
6959
6960         tg3_mdio_start(tp);
6961
6962         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6963                 u8 phy_addr;
6964
6965                 phy_addr = tp->phy_addr;
6966                 tp->phy_addr = TG3_PHY_PCIE_ADDR;
6967
6968                 tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR,
6969                              TG3_PCIEPHY_TXB_BLK << TG3_PCIEPHY_BLOCK_SHIFT);
6970                 val = TG3_PCIEPHY_TX0CTRL1_TXOCM | TG3_PCIEPHY_TX0CTRL1_RDCTL |
6971                       TG3_PCIEPHY_TX0CTRL1_TXCMV | TG3_PCIEPHY_TX0CTRL1_TKSEL |
6972                       TG3_PCIEPHY_TX0CTRL1_NB_EN;
6973                 tg3_writephy(tp, TG3_PCIEPHY_TX0CTRL1, val);
6974                 udelay(10);
6975
6976                 tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR,
6977                              TG3_PCIEPHY_XGXS_BLK1 << TG3_PCIEPHY_BLOCK_SHIFT);
6978                 val = TG3_PCIEPHY_PWRMGMT4_LOWPWR_EN |
6979                       TG3_PCIEPHY_PWRMGMT4_L1PLLPD_EN;
6980                 tg3_writephy(tp, TG3_PCIEPHY_PWRMGMT4, val);
6981                 udelay(10);
6982
6983                 tp->phy_addr = phy_addr;
6984         }
6985
6986         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
6987             tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
6988             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
6989             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
6990             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765) {
6991                 val = tr32(0x7c00);
6992
6993                 tw32(0x7c00, val | (1 << 25));
6994         }
6995
6996         /* Reprobe ASF enable state.  */
6997         tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
6998         tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
6999         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
7000         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
7001                 u32 nic_cfg;
7002
7003                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
7004                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
7005                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
7006                         tp->last_event_jiffies = jiffies;
7007                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
7008                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
7009                 }
7010         }
7011
7012         return 0;
7013 }
7014
7015 /* tp->lock is held. */
7016 static void tg3_stop_fw(struct tg3 *tp)
7017 {
7018         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
7019            !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7020                 /* Wait for RX cpu to ACK the previous event. */
7021                 tg3_wait_for_event_ack(tp);
7022
7023                 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
7024
7025                 tg3_generate_fw_event(tp);
7026
7027                 /* Wait for RX cpu to ACK this event. */
7028                 tg3_wait_for_event_ack(tp);
7029         }
7030 }
7031
7032 /* tp->lock is held. */
7033 static int tg3_halt(struct tg3 *tp, int kind, int silent)
7034 {
7035         int err;
7036
7037         tg3_stop_fw(tp);
7038
7039         tg3_write_sig_pre_reset(tp, kind);
7040
7041         tg3_abort_hw(tp, silent);
7042         err = tg3_chip_reset(tp);
7043
7044         __tg3_set_mac_addr(tp, 0);
7045
7046         tg3_write_sig_legacy(tp, kind);
7047         tg3_write_sig_post_reset(tp, kind);
7048
7049         if (err)
7050                 return err;
7051
7052         return 0;
7053 }
7054
7055 #define RX_CPU_SCRATCH_BASE     0x30000
7056 #define RX_CPU_SCRATCH_SIZE     0x04000
7057 #define TX_CPU_SCRATCH_BASE     0x34000
7058 #define TX_CPU_SCRATCH_SIZE     0x04000
7059
7060 /* tp->lock is held. */
7061 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
7062 {
7063         int i;
7064
7065         BUG_ON(offset == TX_CPU_BASE &&
7066             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
7067
7068         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7069                 u32 val = tr32(GRC_VCPU_EXT_CTRL);
7070
7071                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
7072                 return 0;
7073         }
7074         if (offset == RX_CPU_BASE) {
7075                 for (i = 0; i < 10000; i++) {
7076                         tw32(offset + CPU_STATE, 0xffffffff);
7077                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
7078                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7079                                 break;
7080                 }
7081
7082                 tw32(offset + CPU_STATE, 0xffffffff);
7083                 tw32_f(offset + CPU_MODE,  CPU_MODE_HALT);
7084                 udelay(10);
7085         } else {
7086                 for (i = 0; i < 10000; i++) {
7087                         tw32(offset + CPU_STATE, 0xffffffff);
7088                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
7089                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7090                                 break;
7091                 }
7092         }
7093
7094         if (i >= 10000) {
7095                 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
7096                        "and %s CPU\n",
7097                        tp->dev->name,
7098                        (offset == RX_CPU_BASE ? "RX" : "TX"));
7099                 return -ENODEV;
7100         }
7101
7102         /* Clear firmware's nvram arbitration. */
7103         if (tp->tg3_flags & TG3_FLAG_NVRAM)
7104                 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
7105         return 0;
7106 }
7107
7108 struct fw_info {
7109         unsigned int fw_base;
7110         unsigned int fw_len;
7111         const __be32 *fw_data;
7112 };
7113
7114 /* tp->lock is held. */
7115 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
7116                                  int cpu_scratch_size, struct fw_info *info)
7117 {
7118         int err, lock_err, i;
7119         void (*write_op)(struct tg3 *, u32, u32);
7120
7121         if (cpu_base == TX_CPU_BASE &&
7122             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7123                 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
7124                        "TX cpu firmware on %s which is 5705.\n",
7125                        tp->dev->name);
7126                 return -EINVAL;
7127         }
7128
7129         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7130                 write_op = tg3_write_mem;
7131         else
7132                 write_op = tg3_write_indirect_reg32;
7133
7134         /* It is possible that bootcode is still loading at this point.
7135          * Get the nvram lock first before halting the cpu.
7136          */
7137         lock_err = tg3_nvram_lock(tp);
7138         err = tg3_halt_cpu(tp, cpu_base);
7139         if (!lock_err)
7140                 tg3_nvram_unlock(tp);
7141         if (err)
7142                 goto out;
7143
7144         for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
7145                 write_op(tp, cpu_scratch_base + i, 0);
7146         tw32(cpu_base + CPU_STATE, 0xffffffff);
7147         tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
7148         for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
7149                 write_op(tp, (cpu_scratch_base +
7150                               (info->fw_base & 0xffff) +
7151                               (i * sizeof(u32))),
7152                               be32_to_cpu(info->fw_data[i]));
7153
7154         err = 0;
7155
7156 out:
7157         return err;
7158 }
7159
7160 /* tp->lock is held. */
7161 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
7162 {
7163         struct fw_info info;
7164         const __be32 *fw_data;
7165         int err, i;
7166
7167         fw_data = (void *)tp->fw->data;
7168
7169         /* Firmware blob starts with version numbers, followed by
7170            start address and length. We are setting complete length.
7171            length = end_address_of_bss - start_address_of_text.
7172            Remainder is the blob to be loaded contiguously
7173            from start address. */
7174
7175         info.fw_base = be32_to_cpu(fw_data[1]);
7176         info.fw_len = tp->fw->size - 12;
7177         info.fw_data = &fw_data[3];
7178
7179         err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
7180                                     RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
7181                                     &info);
7182         if (err)
7183                 return err;
7184
7185         err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
7186                                     TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
7187                                     &info);
7188         if (err)
7189                 return err;
7190
7191         /* Now startup only the RX cpu. */
7192         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7193         tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
7194
7195         for (i = 0; i < 5; i++) {
7196                 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
7197                         break;
7198                 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7199                 tw32(RX_CPU_BASE + CPU_MODE,  CPU_MODE_HALT);
7200                 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
7201                 udelay(1000);
7202         }
7203         if (i >= 5) {
7204                 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
7205                        "to set RX CPU PC, is %08x should be %08x\n",
7206                        tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
7207                        info.fw_base);
7208                 return -ENODEV;
7209         }
7210         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7211         tw32_f(RX_CPU_BASE + CPU_MODE,  0x00000000);
7212
7213         return 0;
7214 }
7215
7216 /* 5705 needs a special version of the TSO firmware.  */
7217
7218 /* tp->lock is held. */
7219 static int tg3_load_tso_firmware(struct tg3 *tp)
7220 {
7221         struct fw_info info;
7222         const __be32 *fw_data;
7223         unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
7224         int err, i;
7225
7226         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7227                 return 0;
7228
7229         fw_data = (void *)tp->fw->data;
7230
7231         /* Firmware blob starts with version numbers, followed by
7232            start address and length. We are setting complete length.
7233            length = end_address_of_bss - start_address_of_text.
7234            Remainder is the blob to be loaded contiguously
7235            from start address. */
7236
7237         info.fw_base = be32_to_cpu(fw_data[1]);
7238         cpu_scratch_size = tp->fw_len;
7239         info.fw_len = tp->fw->size - 12;
7240         info.fw_data = &fw_data[3];
7241
7242         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7243                 cpu_base = RX_CPU_BASE;
7244                 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
7245         } else {
7246                 cpu_base = TX_CPU_BASE;
7247                 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
7248                 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
7249         }
7250
7251         err = tg3_load_firmware_cpu(tp, cpu_base,
7252                                     cpu_scratch_base, cpu_scratch_size,
7253                                     &info);
7254         if (err)
7255                 return err;
7256
7257         /* Now startup the cpu. */
7258         tw32(cpu_base + CPU_STATE, 0xffffffff);
7259         tw32_f(cpu_base + CPU_PC, info.fw_base);
7260
7261         for (i = 0; i < 5; i++) {
7262                 if (tr32(cpu_base + CPU_PC) == info.fw_base)
7263                         break;
7264                 tw32(cpu_base + CPU_STATE, 0xffffffff);
7265                 tw32(cpu_base + CPU_MODE,  CPU_MODE_HALT);
7266                 tw32_f(cpu_base + CPU_PC, info.fw_base);
7267                 udelay(1000);
7268         }
7269         if (i >= 5) {
7270                 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
7271                        "to set CPU PC, is %08x should be %08x\n",
7272                        tp->dev->name, tr32(cpu_base + CPU_PC),
7273                        info.fw_base);
7274                 return -ENODEV;
7275         }
7276         tw32(cpu_base + CPU_STATE, 0xffffffff);
7277         tw32_f(cpu_base + CPU_MODE,  0x00000000);
7278         return 0;
7279 }
7280
7281
7282 static int tg3_set_mac_addr(struct net_device *dev, void *p)
7283 {
7284         struct tg3 *tp = netdev_priv(dev);
7285         struct sockaddr *addr = p;
7286         int err = 0, skip_mac_1 = 0;
7287
7288         if (!is_valid_ether_addr(addr->sa_data))
7289                 return -EINVAL;
7290
7291         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7292
7293         if (!netif_running(dev))
7294                 return 0;
7295
7296         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
7297                 u32 addr0_high, addr0_low, addr1_high, addr1_low;
7298
7299                 addr0_high = tr32(MAC_ADDR_0_HIGH);
7300                 addr0_low = tr32(MAC_ADDR_0_LOW);
7301                 addr1_high = tr32(MAC_ADDR_1_HIGH);
7302                 addr1_low = tr32(MAC_ADDR_1_LOW);
7303
7304                 /* Skip MAC addr 1 if ASF is using it. */
7305                 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
7306                     !(addr1_high == 0 && addr1_low == 0))
7307                         skip_mac_1 = 1;
7308         }
7309         spin_lock_bh(&tp->lock);
7310         __tg3_set_mac_addr(tp, skip_mac_1);
7311         spin_unlock_bh(&tp->lock);
7312
7313         return err;
7314 }
7315
7316 /* tp->lock is held. */
7317 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
7318                            dma_addr_t mapping, u32 maxlen_flags,
7319                            u32 nic_addr)
7320 {
7321         tg3_write_mem(tp,
7322                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
7323                       ((u64) mapping >> 32));
7324         tg3_write_mem(tp,
7325                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
7326                       ((u64) mapping & 0xffffffff));
7327         tg3_write_mem(tp,
7328                       (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
7329                        maxlen_flags);
7330
7331         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7332                 tg3_write_mem(tp,
7333                               (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
7334                               nic_addr);
7335 }
7336
7337 static void __tg3_set_rx_mode(struct net_device *);
7338 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
7339 {
7340         int i;
7341
7342         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) {
7343                 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
7344                 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
7345                 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
7346         } else {
7347                 tw32(HOSTCC_TXCOL_TICKS, 0);
7348                 tw32(HOSTCC_TXMAX_FRAMES, 0);
7349                 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
7350         }
7351
7352         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
7353                 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
7354                 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
7355                 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
7356         } else {
7357                 tw32(HOSTCC_RXCOL_TICKS, 0);
7358                 tw32(HOSTCC_RXMAX_FRAMES, 0);
7359                 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
7360         }
7361
7362         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7363                 u32 val = ec->stats_block_coalesce_usecs;
7364
7365                 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
7366                 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
7367
7368                 if (!netif_carrier_ok(tp->dev))
7369                         val = 0;
7370
7371                 tw32(HOSTCC_STAT_COAL_TICKS, val);
7372         }
7373
7374         for (i = 0; i < tp->irq_cnt - 1; i++) {
7375                 u32 reg;
7376
7377                 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
7378                 tw32(reg, ec->rx_coalesce_usecs);
7379                 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
7380                 tw32(reg, ec->rx_max_coalesced_frames);
7381                 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
7382                 tw32(reg, ec->rx_max_coalesced_frames_irq);
7383
7384                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7385                         reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
7386                         tw32(reg, ec->tx_coalesce_usecs);
7387                         reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
7388                         tw32(reg, ec->tx_max_coalesced_frames);
7389                         reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
7390                         tw32(reg, ec->tx_max_coalesced_frames_irq);
7391                 }
7392         }
7393
7394         for (; i < tp->irq_max - 1; i++) {
7395                 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
7396                 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
7397                 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7398
7399                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7400                         tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
7401                         tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
7402                         tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7403                 }
7404         }
7405 }
7406
7407 /* tp->lock is held. */
7408 static void tg3_rings_reset(struct tg3 *tp)
7409 {
7410         int i;
7411         u32 stblk, txrcb, rxrcb, limit;
7412         struct tg3_napi *tnapi = &tp->napi[0];
7413
7414         /* Disable all transmit rings but the first. */
7415         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7416                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
7417         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7418                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
7419         else
7420                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7421
7422         for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7423              txrcb < limit; txrcb += TG3_BDINFO_SIZE)
7424                 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
7425                               BDINFO_FLAGS_DISABLED);
7426
7427
7428         /* Disable all receive return rings but the first. */
7429         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
7430                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
7431         else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7432                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
7433         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
7434                  GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7435                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
7436         else
7437                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7438
7439         for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7440              rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
7441                 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
7442                               BDINFO_FLAGS_DISABLED);
7443
7444         /* Disable interrupts */
7445         tw32_mailbox_f(tp->napi[0].int_mbox, 1);
7446
7447         /* Zero mailbox registers. */
7448         if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) {
7449                 for (i = 1; i < TG3_IRQ_MAX_VECS; i++) {
7450                         tp->napi[i].tx_prod = 0;
7451                         tp->napi[i].tx_cons = 0;
7452                         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
7453                                 tw32_mailbox(tp->napi[i].prodmbox, 0);
7454                         tw32_rx_mbox(tp->napi[i].consmbox, 0);
7455                         tw32_mailbox_f(tp->napi[i].int_mbox, 1);
7456                 }
7457                 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))
7458                         tw32_mailbox(tp->napi[0].prodmbox, 0);
7459         } else {
7460                 tp->napi[0].tx_prod = 0;
7461                 tp->napi[0].tx_cons = 0;
7462                 tw32_mailbox(tp->napi[0].prodmbox, 0);
7463                 tw32_rx_mbox(tp->napi[0].consmbox, 0);
7464         }
7465
7466         /* Make sure the NIC-based send BD rings are disabled. */
7467         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7468                 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
7469                 for (i = 0; i < 16; i++)
7470                         tw32_tx_mbox(mbox + i * 8, 0);
7471         }
7472
7473         txrcb = NIC_SRAM_SEND_RCB;
7474         rxrcb = NIC_SRAM_RCV_RET_RCB;
7475
7476         /* Clear status block in ram. */
7477         memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7478
7479         /* Set status block DMA address */
7480         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7481              ((u64) tnapi->status_mapping >> 32));
7482         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7483              ((u64) tnapi->status_mapping & 0xffffffff));
7484
7485         if (tnapi->tx_ring) {
7486                 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7487                                (TG3_TX_RING_SIZE <<
7488                                 BDINFO_FLAGS_MAXLEN_SHIFT),
7489                                NIC_SRAM_TX_BUFFER_DESC);
7490                 txrcb += TG3_BDINFO_SIZE;
7491         }
7492
7493         if (tnapi->rx_rcb) {
7494                 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7495                                (TG3_RX_RCB_RING_SIZE(tp) <<
7496                                 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7497                 rxrcb += TG3_BDINFO_SIZE;
7498         }
7499
7500         stblk = HOSTCC_STATBLCK_RING1;
7501
7502         for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
7503                 u64 mapping = (u64)tnapi->status_mapping;
7504                 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
7505                 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
7506
7507                 /* Clear status block in ram. */
7508                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7509
7510                 if (tnapi->tx_ring) {
7511                         tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7512                                        (TG3_TX_RING_SIZE <<
7513                                         BDINFO_FLAGS_MAXLEN_SHIFT),
7514                                        NIC_SRAM_TX_BUFFER_DESC);
7515                         txrcb += TG3_BDINFO_SIZE;
7516                 }
7517
7518                 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7519                                (TG3_RX_RCB_RING_SIZE(tp) <<
7520                                 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7521
7522                 stblk += 8;
7523                 rxrcb += TG3_BDINFO_SIZE;
7524         }
7525 }
7526
7527 /* tp->lock is held. */
7528 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
7529 {
7530         u32 val, rdmac_mode;
7531         int i, err, limit;
7532         struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
7533
7534         tg3_disable_ints(tp);
7535
7536         tg3_stop_fw(tp);
7537
7538         tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
7539
7540         if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
7541                 tg3_abort_hw(tp, 1);
7542         }
7543
7544         if (reset_phy &&
7545             !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB))
7546                 tg3_phy_reset(tp);
7547
7548         err = tg3_chip_reset(tp);
7549         if (err)
7550                 return err;
7551
7552         tg3_write_sig_legacy(tp, RESET_KIND_INIT);
7553
7554         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
7555                 val = tr32(TG3_CPMU_CTRL);
7556                 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
7557                 tw32(TG3_CPMU_CTRL, val);
7558
7559                 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7560                 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7561                 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7562                 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7563
7564                 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
7565                 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
7566                 val |= CPMU_LNK_AWARE_MACCLK_6_25;
7567                 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
7568
7569                 val = tr32(TG3_CPMU_HST_ACC);
7570                 val &= ~CPMU_HST_ACC_MACCLK_MASK;
7571                 val |= CPMU_HST_ACC_MACCLK_6_25;
7572                 tw32(TG3_CPMU_HST_ACC, val);
7573         }
7574
7575         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7576                 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
7577                 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
7578                        PCIE_PWR_MGMT_L1_THRESH_4MS;
7579                 tw32(PCIE_PWR_MGMT_THRESH, val);
7580
7581                 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
7582                 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
7583
7584                 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
7585
7586                 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
7587                 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
7588         }
7589
7590         if (tp->tg3_flags3 & TG3_FLG3_L1PLLPD_EN) {
7591                 u32 grc_mode = tr32(GRC_MODE);
7592
7593                 /* Access the lower 1K of PL PCIE block registers. */
7594                 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
7595                 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
7596
7597                 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1);
7598                 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1,
7599                      val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN);
7600
7601                 tw32(GRC_MODE, grc_mode);
7602         }
7603
7604         /* This works around an issue with Athlon chipsets on
7605          * B3 tigon3 silicon.  This bit has no effect on any
7606          * other revision.  But do not set this on PCI Express
7607          * chips and don't even touch the clocks if the CPMU is present.
7608          */
7609         if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
7610                 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
7611                         tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
7612                 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7613         }
7614
7615         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
7616             (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
7617                 val = tr32(TG3PCI_PCISTATE);
7618                 val |= PCISTATE_RETRY_SAME_DMA;
7619                 tw32(TG3PCI_PCISTATE, val);
7620         }
7621
7622         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7623                 /* Allow reads and writes to the
7624                  * APE register and memory space.
7625                  */
7626                 val = tr32(TG3PCI_PCISTATE);
7627                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
7628                        PCISTATE_ALLOW_APE_SHMEM_WR;
7629                 tw32(TG3PCI_PCISTATE, val);
7630         }
7631
7632         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
7633                 /* Enable some hw fixes.  */
7634                 val = tr32(TG3PCI_MSI_DATA);
7635                 val |= (1 << 26) | (1 << 28) | (1 << 29);
7636                 tw32(TG3PCI_MSI_DATA, val);
7637         }
7638
7639         /* Descriptor ring init may make accesses to the
7640          * NIC SRAM area to setup the TX descriptors, so we
7641          * can only do this after the hardware has been
7642          * successfully reset.
7643          */
7644         err = tg3_init_rings(tp);
7645         if (err)
7646                 return err;
7647
7648         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7649             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
7650                 val = tr32(TG3PCI_DMA_RW_CTRL) &
7651                       ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
7652                 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
7653         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
7654                    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
7655                 /* This value is determined during the probe time DMA
7656                  * engine test, tg3_test_dma.
7657                  */
7658                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
7659         }
7660
7661         tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
7662                           GRC_MODE_4X_NIC_SEND_RINGS |
7663                           GRC_MODE_NO_TX_PHDR_CSUM |
7664                           GRC_MODE_NO_RX_PHDR_CSUM);
7665         tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
7666
7667         /* Pseudo-header checksum is done by hardware logic and not
7668          * the offload processers, so make the chip do the pseudo-
7669          * header checksums on receive.  For transmit it is more
7670          * convenient to do the pseudo-header checksum in software
7671          * as Linux does that on transmit for us in all cases.
7672          */
7673         tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
7674
7675         tw32(GRC_MODE,
7676              tp->grc_mode |
7677              (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
7678
7679         /* Setup the timer prescalar register.  Clock is always 66Mhz. */
7680         val = tr32(GRC_MISC_CFG);
7681         val &= ~0xff;
7682         val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
7683         tw32(GRC_MISC_CFG, val);
7684
7685         /* Initialize MBUF/DESC pool. */
7686         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7687                 /* Do nothing.  */
7688         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
7689                 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
7690                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
7691                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
7692                 else
7693                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
7694                 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
7695                 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
7696         }
7697         else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7698                 int fw_len;
7699
7700                 fw_len = tp->fw_len;
7701                 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
7702                 tw32(BUFMGR_MB_POOL_ADDR,
7703                      NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
7704                 tw32(BUFMGR_MB_POOL_SIZE,
7705                      NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
7706         }
7707
7708         if (tp->dev->mtu <= ETH_DATA_LEN) {
7709                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7710                      tp->bufmgr_config.mbuf_read_dma_low_water);
7711                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7712                      tp->bufmgr_config.mbuf_mac_rx_low_water);
7713                 tw32(BUFMGR_MB_HIGH_WATER,
7714                      tp->bufmgr_config.mbuf_high_water);
7715         } else {
7716                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7717                      tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
7718                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7719                      tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
7720                 tw32(BUFMGR_MB_HIGH_WATER,
7721                      tp->bufmgr_config.mbuf_high_water_jumbo);
7722         }
7723         tw32(BUFMGR_DMA_LOW_WATER,
7724              tp->bufmgr_config.dma_low_water);
7725         tw32(BUFMGR_DMA_HIGH_WATER,
7726              tp->bufmgr_config.dma_high_water);
7727
7728         tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
7729         for (i = 0; i < 2000; i++) {
7730                 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
7731                         break;
7732                 udelay(10);
7733         }
7734         if (i >= 2000) {
7735                 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
7736                        tp->dev->name);
7737                 return -ENODEV;
7738         }
7739
7740         /* Setup replenish threshold. */
7741         val = tp->rx_pending / 8;
7742         if (val == 0)
7743                 val = 1;
7744         else if (val > tp->rx_std_max_post)
7745                 val = tp->rx_std_max_post;
7746         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7747                 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
7748                         tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
7749
7750                 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
7751                         val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
7752         }
7753
7754         tw32(RCVBDI_STD_THRESH, val);
7755
7756         /* Initialize TG3_BDINFO's at:
7757          *  RCVDBDI_STD_BD:     standard eth size rx ring
7758          *  RCVDBDI_JUMBO_BD:   jumbo frame rx ring
7759          *  RCVDBDI_MINI_BD:    small frame rx ring (??? does not work)
7760          *
7761          * like so:
7762          *  TG3_BDINFO_HOST_ADDR:       high/low parts of DMA address of ring
7763          *  TG3_BDINFO_MAXLEN_FLAGS:    (rx max buffer size << 16) |
7764          *                              ring attribute flags
7765          *  TG3_BDINFO_NIC_ADDR:        location of descriptors in nic SRAM
7766          *
7767          * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
7768          * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
7769          *
7770          * The size of each ring is fixed in the firmware, but the location is
7771          * configurable.
7772          */
7773         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7774              ((u64) tpr->rx_std_mapping >> 32));
7775         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7776              ((u64) tpr->rx_std_mapping & 0xffffffff));
7777         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717)
7778                 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
7779                      NIC_SRAM_RX_BUFFER_DESC);
7780
7781         /* Disable the mini ring */
7782         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7783                 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
7784                      BDINFO_FLAGS_DISABLED);
7785
7786         /* Program the jumbo buffer descriptor ring control
7787          * blocks on those devices that have them.
7788          */
7789         if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
7790             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
7791                 /* Setup replenish threshold. */
7792                 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
7793
7794                 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
7795                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7796                              ((u64) tpr->rx_jmb_mapping >> 32));
7797                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7798                              ((u64) tpr->rx_jmb_mapping & 0xffffffff));
7799                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7800                              (RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT) |
7801                              BDINFO_FLAGS_USE_EXT_RECV);
7802                         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717)
7803                                 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
7804                                      NIC_SRAM_RX_JUMBO_BUFFER_DESC);
7805                 } else {
7806                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7807                              BDINFO_FLAGS_DISABLED);
7808                 }
7809
7810                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7811                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7812                         val = (RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT) |
7813                               (RX_STD_MAX_SIZE << 2);
7814                 else
7815                         val = RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT;
7816         } else
7817                 val = RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT;
7818
7819         tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
7820
7821         tpr->rx_std_prod_idx = tp->rx_pending;
7822         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);
7823
7824         tpr->rx_jmb_prod_idx = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
7825                           tp->rx_jumbo_pending : 0;
7826         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
7827
7828         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7829             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
7830                 tw32(STD_REPLENISH_LWM, 32);
7831                 tw32(JMB_REPLENISH_LWM, 16);
7832         }
7833
7834         tg3_rings_reset(tp);
7835
7836         /* Initialize MAC address and backoff seed. */
7837         __tg3_set_mac_addr(tp, 0);
7838
7839         /* MTU + ethernet header + FCS + optional VLAN tag */
7840         tw32(MAC_RX_MTU_SIZE,
7841              tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
7842
7843         /* The slot time is changed by tg3_setup_phy if we
7844          * run at gigabit with half duplex.
7845          */
7846         tw32(MAC_TX_LENGTHS,
7847              (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
7848              (6 << TX_LENGTHS_IPG_SHIFT) |
7849              (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
7850
7851         /* Receive rules. */
7852         tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
7853         tw32(RCVLPC_CONFIG, 0x0181);
7854
7855         /* Calculate RDMAC_MODE setting early, we need it to determine
7856          * the RCVLPC_STATE_ENABLE mask.
7857          */
7858         rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
7859                       RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
7860                       RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
7861                       RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
7862                       RDMAC_MODE_LNGREAD_ENAB);
7863
7864         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
7865             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7866             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7867                 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
7868                               RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
7869                               RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
7870
7871         /* If statement applies to 5705 and 5750 PCI devices only */
7872         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7873              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7874             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
7875                 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
7876                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7877                         rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
7878                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7879                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
7880                         rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7881                 }
7882         }
7883
7884         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
7885                 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7886
7887         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7888                 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
7889
7890         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
7891             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7892             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7893                 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
7894
7895         /* Receive/send statistics. */
7896         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7897                 val = tr32(RCVLPC_STATS_ENABLE);
7898                 val &= ~RCVLPC_STATSENAB_DACK_FIX;
7899                 tw32(RCVLPC_STATS_ENABLE, val);
7900         } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
7901                    (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
7902                 val = tr32(RCVLPC_STATS_ENABLE);
7903                 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
7904                 tw32(RCVLPC_STATS_ENABLE, val);
7905         } else {
7906                 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
7907         }
7908         tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
7909         tw32(SNDDATAI_STATSENAB, 0xffffff);
7910         tw32(SNDDATAI_STATSCTRL,
7911              (SNDDATAI_SCTRL_ENABLE |
7912               SNDDATAI_SCTRL_FASTUPD));
7913
7914         /* Setup host coalescing engine. */
7915         tw32(HOSTCC_MODE, 0);
7916         for (i = 0; i < 2000; i++) {
7917                 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
7918                         break;
7919                 udelay(10);
7920         }
7921
7922         __tg3_set_coalesce(tp, &tp->coal);
7923
7924         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7925                 /* Status/statistics block address.  See tg3_timer,
7926                  * the tg3_periodic_fetch_stats call there, and
7927                  * tg3_get_stats to see how this works for 5705/5750 chips.
7928                  */
7929                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7930                      ((u64) tp->stats_mapping >> 32));
7931                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7932                      ((u64) tp->stats_mapping & 0xffffffff));
7933                 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
7934
7935                 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
7936
7937                 /* Clear statistics and status block memory areas */
7938                 for (i = NIC_SRAM_STATS_BLK;
7939                      i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
7940                      i += sizeof(u32)) {
7941                         tg3_write_mem(tp, i, 0);
7942                         udelay(40);
7943                 }
7944         }
7945
7946         tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
7947
7948         tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
7949         tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
7950         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7951                 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
7952
7953         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
7954                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
7955                 /* reset to prevent losing 1st rx packet intermittently */
7956                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7957                 udelay(10);
7958         }
7959
7960         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7961                 tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
7962         else
7963                 tp->mac_mode = 0;
7964         tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
7965                 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
7966         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7967             !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7968             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
7969                 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
7970         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
7971         udelay(40);
7972
7973         /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
7974          * If TG3_FLG2_IS_NIC is zero, we should read the
7975          * register to preserve the GPIO settings for LOMs. The GPIOs,
7976          * whether used as inputs or outputs, are set by boot code after
7977          * reset.
7978          */
7979         if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
7980                 u32 gpio_mask;
7981
7982                 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
7983                             GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
7984                             GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
7985
7986                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
7987                         gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
7988                                      GRC_LCLCTRL_GPIO_OUTPUT3;
7989
7990                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
7991                         gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
7992
7993                 tp->grc_local_ctrl &= ~gpio_mask;
7994                 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
7995
7996                 /* GPIO1 must be driven high for eeprom write protect */
7997                 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
7998                         tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
7999                                                GRC_LCLCTRL_GPIO_OUTPUT1);
8000         }
8001         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8002         udelay(100);
8003
8004         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX) {
8005                 val = tr32(MSGINT_MODE);
8006                 val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE;
8007                 tw32(MSGINT_MODE, val);
8008         }
8009
8010         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
8011                 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
8012                 udelay(40);
8013         }
8014
8015         val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
8016                WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
8017                WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
8018                WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
8019                WDMAC_MODE_LNGREAD_ENAB);
8020
8021         /* If statement applies to 5705 and 5750 PCI devices only */
8022         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
8023              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
8024             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
8025                 if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
8026                     (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
8027                      tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
8028                         /* nothing */
8029                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
8030                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
8031                            !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
8032                         val |= WDMAC_MODE_RX_ACCEL;
8033                 }
8034         }
8035
8036         /* Enable host coalescing bug fix */
8037         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
8038                 val |= WDMAC_MODE_STATUS_TAG_FIX;
8039
8040         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
8041                 val |= WDMAC_MODE_BURST_ALL_DATA;
8042
8043         tw32_f(WDMAC_MODE, val);
8044         udelay(40);
8045
8046         if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
8047                 u16 pcix_cmd;
8048
8049                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8050                                      &pcix_cmd);
8051                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
8052                         pcix_cmd &= ~PCI_X_CMD_MAX_READ;
8053                         pcix_cmd |= PCI_X_CMD_READ_2K;
8054                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
8055                         pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
8056                         pcix_cmd |= PCI_X_CMD_READ_2K;
8057                 }
8058                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8059                                       pcix_cmd);
8060         }
8061
8062         tw32_f(RDMAC_MODE, rdmac_mode);
8063         udelay(40);
8064
8065         tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
8066         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8067                 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
8068
8069         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
8070                 tw32(SNDDATAC_MODE,
8071                      SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
8072         else
8073                 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
8074
8075         tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
8076         tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
8077         tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
8078         tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
8079         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
8080                 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
8081         val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
8082         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
8083                 val |= SNDBDI_MODE_MULTI_TXQ_EN;
8084         tw32(SNDBDI_MODE, val);
8085         tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
8086
8087         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8088                 err = tg3_load_5701_a0_firmware_fix(tp);
8089                 if (err)
8090                         return err;
8091         }
8092
8093         if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
8094                 err = tg3_load_tso_firmware(tp);
8095                 if (err)
8096                         return err;
8097         }
8098
8099         tp->tx_mode = TX_MODE_ENABLE;
8100         tw32_f(MAC_TX_MODE, tp->tx_mode);
8101         udelay(100);
8102
8103         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) {
8104                 u32 reg = MAC_RSS_INDIR_TBL_0;
8105                 u8 *ent = (u8 *)&val;
8106
8107                 /* Setup the indirection table */
8108                 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
8109                         int idx = i % sizeof(val);
8110
8111                         ent[idx] = i % (tp->irq_cnt - 1);
8112                         if (idx == sizeof(val) - 1) {
8113                                 tw32(reg, val);
8114                                 reg += 4;
8115                         }
8116                 }
8117
8118                 /* Setup the "secret" hash key. */
8119                 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
8120                 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
8121                 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
8122                 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
8123                 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
8124                 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
8125                 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
8126                 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
8127                 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
8128                 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
8129         }
8130
8131         tp->rx_mode = RX_MODE_ENABLE;
8132         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
8133                 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
8134
8135         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)
8136                 tp->rx_mode |= RX_MODE_RSS_ENABLE |
8137                                RX_MODE_RSS_ITBL_HASH_BITS_7 |
8138                                RX_MODE_RSS_IPV6_HASH_EN |
8139                                RX_MODE_RSS_TCP_IPV6_HASH_EN |
8140                                RX_MODE_RSS_IPV4_HASH_EN |
8141                                RX_MODE_RSS_TCP_IPV4_HASH_EN;
8142
8143         tw32_f(MAC_RX_MODE, tp->rx_mode);
8144         udelay(10);
8145
8146         tw32(MAC_LED_CTRL, tp->led_ctrl);
8147
8148         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
8149         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
8150                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8151                 udelay(10);
8152         }
8153         tw32_f(MAC_RX_MODE, tp->rx_mode);
8154         udelay(10);
8155
8156         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
8157                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
8158                         !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
8159                         /* Set drive transmission level to 1.2V  */
8160                         /* only if the signal pre-emphasis bit is not set  */
8161                         val = tr32(MAC_SERDES_CFG);
8162                         val &= 0xfffff000;
8163                         val |= 0x880;
8164                         tw32(MAC_SERDES_CFG, val);
8165                 }
8166                 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
8167                         tw32(MAC_SERDES_CFG, 0x616000);
8168         }
8169
8170         /* Prevent chip from dropping frames when flow control
8171          * is enabled.
8172          */
8173         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
8174                 val = 1;
8175         else
8176                 val = 2;
8177         tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val);
8178
8179         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
8180             (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
8181                 /* Use hardware link auto-negotiation */
8182                 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
8183         }
8184
8185         if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
8186             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
8187                 u32 tmp;
8188
8189                 tmp = tr32(SERDES_RX_CTRL);
8190                 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
8191                 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
8192                 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
8193                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8194         }
8195
8196         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
8197                 if (tp->link_config.phy_is_low_power) {
8198                         tp->link_config.phy_is_low_power = 0;
8199                         tp->link_config.speed = tp->link_config.orig_speed;
8200                         tp->link_config.duplex = tp->link_config.orig_duplex;
8201                         tp->link_config.autoneg = tp->link_config.orig_autoneg;
8202                 }
8203
8204                 err = tg3_setup_phy(tp, 0);
8205                 if (err)
8206                         return err;
8207
8208                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8209                     !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)) {
8210                         u32 tmp;
8211
8212                         /* Clear CRC stats. */
8213                         if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
8214                                 tg3_writephy(tp, MII_TG3_TEST1,
8215                                              tmp | MII_TG3_TEST1_CRC_EN);
8216                                 tg3_readphy(tp, 0x14, &tmp);
8217                         }
8218                 }
8219         }
8220
8221         __tg3_set_rx_mode(tp->dev);
8222
8223         /* Initialize receive rules. */
8224         tw32(MAC_RCV_RULE_0,  0xc2000000 & RCV_RULE_DISABLE_MASK);
8225         tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
8226         tw32(MAC_RCV_RULE_1,  0x86000004 & RCV_RULE_DISABLE_MASK);
8227         tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
8228
8229         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
8230             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
8231                 limit = 8;
8232         else
8233                 limit = 16;
8234         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
8235                 limit -= 4;
8236         switch (limit) {
8237         case 16:
8238                 tw32(MAC_RCV_RULE_15,  0); tw32(MAC_RCV_VALUE_15,  0);
8239         case 15:
8240                 tw32(MAC_RCV_RULE_14,  0); tw32(MAC_RCV_VALUE_14,  0);
8241         case 14:
8242                 tw32(MAC_RCV_RULE_13,  0); tw32(MAC_RCV_VALUE_13,  0);
8243         case 13:
8244                 tw32(MAC_RCV_RULE_12,  0); tw32(MAC_RCV_VALUE_12,  0);
8245         case 12:
8246                 tw32(MAC_RCV_RULE_11,  0); tw32(MAC_RCV_VALUE_11,  0);
8247         case 11:
8248                 tw32(MAC_RCV_RULE_10,  0); tw32(MAC_RCV_VALUE_10,  0);
8249         case 10:
8250                 tw32(MAC_RCV_RULE_9,  0); tw32(MAC_RCV_VALUE_9,  0);
8251         case 9:
8252                 tw32(MAC_RCV_RULE_8,  0); tw32(MAC_RCV_VALUE_8,  0);
8253         case 8:
8254                 tw32(MAC_RCV_RULE_7,  0); tw32(MAC_RCV_VALUE_7,  0);
8255         case 7:
8256                 tw32(MAC_RCV_RULE_6,  0); tw32(MAC_RCV_VALUE_6,  0);
8257         case 6:
8258                 tw32(MAC_RCV_RULE_5,  0); tw32(MAC_RCV_VALUE_5,  0);
8259         case 5:
8260                 tw32(MAC_RCV_RULE_4,  0); tw32(MAC_RCV_VALUE_4,  0);
8261         case 4:
8262                 /* tw32(MAC_RCV_RULE_3,  0); tw32(MAC_RCV_VALUE_3,  0); */
8263         case 3:
8264                 /* tw32(MAC_RCV_RULE_2,  0); tw32(MAC_RCV_VALUE_2,  0); */
8265         case 2:
8266         case 1:
8267
8268         default:
8269                 break;
8270         }
8271
8272         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
8273                 /* Write our heartbeat update interval to APE. */
8274                 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
8275                                 APE_HOST_HEARTBEAT_INT_DISABLE);
8276
8277         tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
8278
8279         return 0;
8280 }
8281
8282 /* Called at device open time to get the chip ready for
8283  * packet processing.  Invoked with tp->lock held.
8284  */
8285 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
8286 {
8287         tg3_switch_clocks(tp);
8288
8289         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
8290
8291         return tg3_reset_hw(tp, reset_phy);
8292 }
8293
8294 #define TG3_STAT_ADD32(PSTAT, REG) \
8295 do {    u32 __val = tr32(REG); \
8296         (PSTAT)->low += __val; \
8297         if ((PSTAT)->low < __val) \
8298                 (PSTAT)->high += 1; \
8299 } while (0)
8300
8301 static void tg3_periodic_fetch_stats(struct tg3 *tp)
8302 {
8303         struct tg3_hw_stats *sp = tp->hw_stats;
8304
8305         if (!netif_carrier_ok(tp->dev))
8306                 return;
8307
8308         TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
8309         TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
8310         TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
8311         TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
8312         TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
8313         TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
8314         TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
8315         TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
8316         TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
8317         TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
8318         TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
8319         TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
8320         TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
8321
8322         TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
8323         TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
8324         TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
8325         TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
8326         TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
8327         TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
8328         TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
8329         TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
8330         TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
8331         TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
8332         TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
8333         TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
8334         TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
8335         TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
8336
8337         TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
8338         TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
8339         TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
8340 }
8341
8342 static void tg3_timer(unsigned long __opaque)
8343 {
8344         struct tg3 *tp = (struct tg3 *) __opaque;
8345
8346         if (tp->irq_sync)
8347                 goto restart_timer;
8348
8349         spin_lock(&tp->lock);
8350
8351         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8352                 /* All of this garbage is because when using non-tagged
8353                  * IRQ status the mailbox/status_block protocol the chip
8354                  * uses with the cpu is race prone.
8355                  */
8356                 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
8357                         tw32(GRC_LOCAL_CTRL,
8358                              tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
8359                 } else {
8360                         tw32(HOSTCC_MODE, tp->coalesce_mode |
8361                              HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
8362                 }
8363
8364                 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
8365                         tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
8366                         spin_unlock(&tp->lock);
8367                         schedule_work(&tp->reset_task);
8368                         return;
8369                 }
8370         }
8371
8372         /* This part only runs once per second. */
8373         if (!--tp->timer_counter) {
8374                 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
8375                         tg3_periodic_fetch_stats(tp);
8376
8377                 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
8378                         u32 mac_stat;
8379                         int phy_event;
8380
8381                         mac_stat = tr32(MAC_STATUS);
8382
8383                         phy_event = 0;
8384                         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
8385                                 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
8386                                         phy_event = 1;
8387                         } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
8388                                 phy_event = 1;
8389
8390                         if (phy_event)
8391                                 tg3_setup_phy(tp, 0);
8392                 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
8393                         u32 mac_stat = tr32(MAC_STATUS);
8394                         int need_setup = 0;
8395
8396                         if (netif_carrier_ok(tp->dev) &&
8397                             (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
8398                                 need_setup = 1;
8399                         }
8400                         if (! netif_carrier_ok(tp->dev) &&
8401                             (mac_stat & (MAC_STATUS_PCS_SYNCED |
8402                                          MAC_STATUS_SIGNAL_DET))) {
8403                                 need_setup = 1;
8404                         }
8405                         if (need_setup) {
8406                                 if (!tp->serdes_counter) {
8407                                         tw32_f(MAC_MODE,
8408                                              (tp->mac_mode &
8409                                               ~MAC_MODE_PORT_MODE_MASK));
8410                                         udelay(40);
8411                                         tw32_f(MAC_MODE, tp->mac_mode);
8412                                         udelay(40);
8413                                 }
8414                                 tg3_setup_phy(tp, 0);
8415                         }
8416                 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
8417                         tg3_serdes_parallel_detect(tp);
8418
8419                 tp->timer_counter = tp->timer_multiplier;
8420         }
8421
8422         /* Heartbeat is only sent once every 2 seconds.
8423          *
8424          * The heartbeat is to tell the ASF firmware that the host
8425          * driver is still alive.  In the event that the OS crashes,
8426          * ASF needs to reset the hardware to free up the FIFO space
8427          * that may be filled with rx packets destined for the host.
8428          * If the FIFO is full, ASF will no longer function properly.
8429          *
8430          * Unintended resets have been reported on real time kernels
8431          * where the timer doesn't run on time.  Netpoll will also have
8432          * same problem.
8433          *
8434          * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
8435          * to check the ring condition when the heartbeat is expiring
8436          * before doing the reset.  This will prevent most unintended
8437          * resets.
8438          */
8439         if (!--tp->asf_counter) {
8440                 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
8441                     !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
8442                         tg3_wait_for_event_ack(tp);
8443
8444                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
8445                                       FWCMD_NICDRV_ALIVE3);
8446                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
8447                         /* 5 seconds timeout */
8448                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
8449
8450                         tg3_generate_fw_event(tp);
8451                 }
8452                 tp->asf_counter = tp->asf_multiplier;
8453         }
8454
8455         spin_unlock(&tp->lock);
8456
8457 restart_timer:
8458         tp->timer.expires = jiffies + tp->timer_offset;
8459         add_timer(&tp->timer);
8460 }
8461
8462 static int tg3_request_irq(struct tg3 *tp, int irq_num)
8463 {
8464         irq_handler_t fn;
8465         unsigned long flags;
8466         char *name;
8467         struct tg3_napi *tnapi = &tp->napi[irq_num];
8468
8469         if (tp->irq_cnt == 1)
8470                 name = tp->dev->name;
8471         else {
8472                 name = &tnapi->irq_lbl[0];
8473                 snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
8474                 name[IFNAMSIZ-1] = 0;
8475         }
8476
8477         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8478                 fn = tg3_msi;
8479                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
8480                         fn = tg3_msi_1shot;
8481                 flags = IRQF_SAMPLE_RANDOM;
8482         } else {
8483                 fn = tg3_interrupt;
8484                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8485                         fn = tg3_interrupt_tagged;
8486                 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
8487         }
8488
8489         return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
8490 }
8491
8492 static int tg3_test_interrupt(struct tg3 *tp)
8493 {
8494         struct tg3_napi *tnapi = &tp->napi[0];
8495         struct net_device *dev = tp->dev;
8496         int err, i, intr_ok = 0;
8497         u32 val;
8498
8499         if (!netif_running(dev))
8500                 return -ENODEV;
8501
8502         tg3_disable_ints(tp);
8503
8504         free_irq(tnapi->irq_vec, tnapi);
8505
8506         /*
8507          * Turn off MSI one shot mode.  Otherwise this test has no
8508          * observable way to know whether the interrupt was delivered.
8509          */
8510         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
8511              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) &&
8512             (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8513                 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
8514                 tw32(MSGINT_MODE, val);
8515         }
8516
8517         err = request_irq(tnapi->irq_vec, tg3_test_isr,
8518                           IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi);
8519         if (err)
8520                 return err;
8521
8522         tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
8523         tg3_enable_ints(tp);
8524
8525         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8526                tnapi->coal_now);
8527
8528         for (i = 0; i < 5; i++) {
8529                 u32 int_mbox, misc_host_ctrl;
8530
8531                 int_mbox = tr32_mailbox(tnapi->int_mbox);
8532                 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
8533
8534                 if ((int_mbox != 0) ||
8535                     (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
8536                         intr_ok = 1;
8537                         break;
8538                 }
8539
8540                 msleep(10);
8541         }
8542
8543         tg3_disable_ints(tp);
8544
8545         free_irq(tnapi->irq_vec, tnapi);
8546
8547         err = tg3_request_irq(tp, 0);
8548
8549         if (err)
8550                 return err;
8551
8552         if (intr_ok) {
8553                 /* Reenable MSI one shot mode. */
8554                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
8555                      GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) &&
8556                     (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8557                         val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
8558                         tw32(MSGINT_MODE, val);
8559                 }
8560                 return 0;
8561         }
8562
8563         return -EIO;
8564 }
8565
8566 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
8567  * successfully restored
8568  */
8569 static int tg3_test_msi(struct tg3 *tp)
8570 {
8571         int err;
8572         u16 pci_cmd;
8573
8574         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
8575                 return 0;
8576
8577         /* Turn off SERR reporting in case MSI terminates with Master
8578          * Abort.
8579          */
8580         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
8581         pci_write_config_word(tp->pdev, PCI_COMMAND,
8582                               pci_cmd & ~PCI_COMMAND_SERR);
8583
8584         err = tg3_test_interrupt(tp);
8585
8586         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
8587
8588         if (!err)
8589                 return 0;
8590
8591         /* other failures */
8592         if (err != -EIO)
8593                 return err;
8594
8595         /* MSI test failed, go back to INTx mode */
8596         printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
8597                "switching to INTx mode. Please report this failure to "
8598                "the PCI maintainer and include system chipset information.\n",
8599                        tp->dev->name);
8600
8601         free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8602
8603         pci_disable_msi(tp->pdev);
8604
8605         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8606
8607         err = tg3_request_irq(tp, 0);
8608         if (err)
8609                 return err;
8610
8611         /* Need to reset the chip because the MSI cycle may have terminated
8612          * with Master Abort.
8613          */
8614         tg3_full_lock(tp, 1);
8615
8616         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8617         err = tg3_init_hw(tp, 1);
8618
8619         tg3_full_unlock(tp);
8620
8621         if (err)
8622                 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8623
8624         return err;
8625 }
8626
8627 static int tg3_request_firmware(struct tg3 *tp)
8628 {
8629         const __be32 *fw_data;
8630
8631         if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
8632                 printk(KERN_ERR "%s: Failed to load firmware \"%s\"\n",
8633                        tp->dev->name, tp->fw_needed);
8634                 return -ENOENT;
8635         }
8636
8637         fw_data = (void *)tp->fw->data;
8638
8639         /* Firmware blob starts with version numbers, followed by
8640          * start address and _full_ length including BSS sections
8641          * (which must be longer than the actual data, of course
8642          */
8643
8644         tp->fw_len = be32_to_cpu(fw_data[2]);   /* includes bss */
8645         if (tp->fw_len < (tp->fw->size - 12)) {
8646                 printk(KERN_ERR "%s: bogus length %d in \"%s\"\n",
8647                        tp->dev->name, tp->fw_len, tp->fw_needed);
8648                 release_firmware(tp->fw);
8649                 tp->fw = NULL;
8650                 return -EINVAL;
8651         }
8652
8653         /* We no longer need firmware; we have it. */
8654         tp->fw_needed = NULL;
8655         return 0;
8656 }
8657
8658 static bool tg3_enable_msix(struct tg3 *tp)
8659 {
8660         int i, rc, cpus = num_online_cpus();
8661         struct msix_entry msix_ent[tp->irq_max];
8662
8663         if (cpus == 1)
8664                 /* Just fallback to the simpler MSI mode. */
8665                 return false;
8666
8667         /*
8668          * We want as many rx rings enabled as there are cpus.
8669          * The first MSIX vector only deals with link interrupts, etc,
8670          * so we add one to the number of vectors we are requesting.
8671          */
8672         tp->irq_cnt = min_t(unsigned, cpus + 1, tp->irq_max);
8673
8674         for (i = 0; i < tp->irq_max; i++) {
8675                 msix_ent[i].entry  = i;
8676                 msix_ent[i].vector = 0;
8677         }
8678
8679         rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
8680         if (rc != 0) {
8681                 if (rc < TG3_RSS_MIN_NUM_MSIX_VECS)
8682                         return false;
8683                 if (pci_enable_msix(tp->pdev, msix_ent, rc))
8684                         return false;
8685                 printk(KERN_NOTICE
8686                        "%s: Requested %d MSI-X vectors, received %d\n",
8687                        tp->dev->name, tp->irq_cnt, rc);
8688                 tp->irq_cnt = rc;
8689         }
8690
8691         tp->tg3_flags3 |= TG3_FLG3_ENABLE_RSS;
8692
8693         for (i = 0; i < tp->irq_max; i++)
8694                 tp->napi[i].irq_vec = msix_ent[i].vector;
8695
8696         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
8697                 tp->tg3_flags3 |= TG3_FLG3_ENABLE_TSS;
8698                 tp->dev->real_num_tx_queues = tp->irq_cnt - 1;
8699         } else
8700                 tp->dev->real_num_tx_queues = 1;
8701
8702         return true;
8703 }
8704
8705 static void tg3_ints_init(struct tg3 *tp)
8706 {
8707         if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI_OR_MSIX) &&
8708             !(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8709                 /* All MSI supporting chips should support tagged
8710                  * status.  Assert that this is the case.
8711                  */
8712                 printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
8713                        "Not using MSI.\n", tp->dev->name);
8714                 goto defcfg;
8715         }
8716
8717         if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) && tg3_enable_msix(tp))
8718                 tp->tg3_flags2 |= TG3_FLG2_USING_MSIX;
8719         else if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) &&
8720                  pci_enable_msi(tp->pdev) == 0)
8721                 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
8722
8723         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8724                 u32 msi_mode = tr32(MSGINT_MODE);
8725                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8726                         msi_mode |= MSGINT_MODE_MULTIVEC_EN;
8727                 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
8728         }
8729 defcfg:
8730         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
8731                 tp->irq_cnt = 1;
8732                 tp->napi[0].irq_vec = tp->pdev->irq;
8733                 tp->dev->real_num_tx_queues = 1;
8734         }
8735 }
8736
8737 static void tg3_ints_fini(struct tg3 *tp)
8738 {
8739         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8740                 pci_disable_msix(tp->pdev);
8741         else if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
8742                 pci_disable_msi(tp->pdev);
8743         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI_OR_MSIX;
8744         tp->tg3_flags3 &= ~TG3_FLG3_ENABLE_RSS;
8745 }
8746
8747 static int tg3_open(struct net_device *dev)
8748 {
8749         struct tg3 *tp = netdev_priv(dev);
8750         int i, err;
8751
8752         if (tp->fw_needed) {
8753                 err = tg3_request_firmware(tp);
8754                 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8755                         if (err)
8756                                 return err;
8757                 } else if (err) {
8758                         printk(KERN_WARNING "%s: TSO capability disabled.\n",
8759                                tp->dev->name);
8760                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
8761                 } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8762                         printk(KERN_NOTICE "%s: TSO capability restored.\n",
8763                                tp->dev->name);
8764                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
8765                 }
8766         }
8767
8768         netif_carrier_off(tp->dev);
8769
8770         err = tg3_set_power_state(tp, PCI_D0);
8771         if (err)
8772                 return err;
8773
8774         tg3_full_lock(tp, 0);
8775
8776         tg3_disable_ints(tp);
8777         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8778
8779         tg3_full_unlock(tp);
8780
8781         /*
8782          * Setup interrupts first so we know how
8783          * many NAPI resources to allocate
8784          */
8785         tg3_ints_init(tp);
8786
8787         /* The placement of this call is tied
8788          * to the setup and use of Host TX descriptors.
8789          */
8790         err = tg3_alloc_consistent(tp);
8791         if (err)
8792                 goto err_out1;
8793
8794         tg3_napi_enable(tp);
8795
8796         for (i = 0; i < tp->irq_cnt; i++) {
8797                 struct tg3_napi *tnapi = &tp->napi[i];
8798                 err = tg3_request_irq(tp, i);
8799                 if (err) {
8800                         for (i--; i >= 0; i--)
8801                                 free_irq(tnapi->irq_vec, tnapi);
8802                         break;
8803                 }
8804         }
8805
8806         if (err)
8807                 goto err_out2;
8808
8809         tg3_full_lock(tp, 0);
8810
8811         err = tg3_init_hw(tp, 1);
8812         if (err) {
8813                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8814                 tg3_free_rings(tp);
8815         } else {
8816                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8817                         tp->timer_offset = HZ;
8818                 else
8819                         tp->timer_offset = HZ / 10;
8820
8821                 BUG_ON(tp->timer_offset > HZ);
8822                 tp->timer_counter = tp->timer_multiplier =
8823                         (HZ / tp->timer_offset);
8824                 tp->asf_counter = tp->asf_multiplier =
8825                         ((HZ / tp->timer_offset) * 2);
8826
8827                 init_timer(&tp->timer);
8828                 tp->timer.expires = jiffies + tp->timer_offset;
8829                 tp->timer.data = (unsigned long) tp;
8830                 tp->timer.function = tg3_timer;
8831         }
8832
8833         tg3_full_unlock(tp);
8834
8835         if (err)
8836                 goto err_out3;
8837
8838         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8839                 err = tg3_test_msi(tp);
8840
8841                 if (err) {
8842                         tg3_full_lock(tp, 0);
8843                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8844                         tg3_free_rings(tp);
8845                         tg3_full_unlock(tp);
8846
8847                         goto err_out2;
8848                 }
8849
8850                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
8851                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765 &&
8852                     (tp->tg3_flags2 & TG3_FLG2_USING_MSI) &&
8853                     (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)) {
8854                         u32 val = tr32(PCIE_TRANSACTION_CFG);
8855
8856                         tw32(PCIE_TRANSACTION_CFG,
8857                              val | PCIE_TRANS_CFG_1SHOT_MSI);
8858                 }
8859         }
8860
8861         tg3_phy_start(tp);
8862
8863         tg3_full_lock(tp, 0);
8864
8865         add_timer(&tp->timer);
8866         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
8867         tg3_enable_ints(tp);
8868
8869         tg3_full_unlock(tp);
8870
8871         netif_tx_start_all_queues(dev);
8872
8873         return 0;
8874
8875 err_out3:
8876         for (i = tp->irq_cnt - 1; i >= 0; i--) {
8877                 struct tg3_napi *tnapi = &tp->napi[i];
8878                 free_irq(tnapi->irq_vec, tnapi);
8879         }
8880
8881 err_out2:
8882         tg3_napi_disable(tp);
8883         tg3_free_consistent(tp);
8884
8885 err_out1:
8886         tg3_ints_fini(tp);
8887         return err;
8888 }
8889
8890 #if 0
8891 /*static*/ void tg3_dump_state(struct tg3 *tp)
8892 {
8893         u32 val32, val32_2, val32_3, val32_4, val32_5;
8894         u16 val16;
8895         int i;
8896         struct tg3_hw_status *sblk = tp->napi[0]->hw_status;
8897
8898         pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
8899         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
8900         printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
8901                val16, val32);
8902
8903         /* MAC block */
8904         printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
8905                tr32(MAC_MODE), tr32(MAC_STATUS));
8906         printk("       MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
8907                tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
8908         printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
8909                tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
8910         printk("       MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
8911                tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
8912
8913         /* Send data initiator control block */
8914         printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
8915                tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
8916         printk("       SNDDATAI_STATSCTRL[%08x]\n",
8917                tr32(SNDDATAI_STATSCTRL));
8918
8919         /* Send data completion control block */
8920         printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
8921
8922         /* Send BD ring selector block */
8923         printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
8924                tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
8925
8926         /* Send BD initiator control block */
8927         printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
8928                tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
8929
8930         /* Send BD completion control block */
8931         printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
8932
8933         /* Receive list placement control block */
8934         printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
8935                tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
8936         printk("       RCVLPC_STATSCTRL[%08x]\n",
8937                tr32(RCVLPC_STATSCTRL));
8938
8939         /* Receive data and receive BD initiator control block */
8940         printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
8941                tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
8942
8943         /* Receive data completion control block */
8944         printk("DEBUG: RCVDCC_MODE[%08x]\n",
8945                tr32(RCVDCC_MODE));
8946
8947         /* Receive BD initiator control block */
8948         printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
8949                tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
8950
8951         /* Receive BD completion control block */
8952         printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
8953                tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
8954
8955         /* Receive list selector control block */
8956         printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
8957                tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
8958
8959         /* Mbuf cluster free block */
8960         printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
8961                tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
8962
8963         /* Host coalescing control block */
8964         printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
8965                tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
8966         printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
8967                tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8968                tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8969         printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
8970                tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8971                tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8972         printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
8973                tr32(HOSTCC_STATS_BLK_NIC_ADDR));
8974         printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
8975                tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
8976
8977         /* Memory arbiter control block */
8978         printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
8979                tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
8980
8981         /* Buffer manager control block */
8982         printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
8983                tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
8984         printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
8985                tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
8986         printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
8987                "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
8988                tr32(BUFMGR_DMA_DESC_POOL_ADDR),
8989                tr32(BUFMGR_DMA_DESC_POOL_SIZE));
8990
8991         /* Read DMA control block */
8992         printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
8993                tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
8994
8995         /* Write DMA control block */
8996         printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
8997                tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
8998
8999         /* DMA completion block */
9000         printk("DEBUG: DMAC_MODE[%08x]\n",
9001                tr32(DMAC_MODE));
9002
9003         /* GRC block */
9004         printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
9005                tr32(GRC_MODE), tr32(GRC_MISC_CFG));
9006         printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
9007                tr32(GRC_LOCAL_CTRL));
9008
9009         /* TG3_BDINFOs */
9010         printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
9011                tr32(RCVDBDI_JUMBO_BD + 0x0),
9012                tr32(RCVDBDI_JUMBO_BD + 0x4),
9013                tr32(RCVDBDI_JUMBO_BD + 0x8),
9014                tr32(RCVDBDI_JUMBO_BD + 0xc));
9015         printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
9016                tr32(RCVDBDI_STD_BD + 0x0),
9017                tr32(RCVDBDI_STD_BD + 0x4),
9018                tr32(RCVDBDI_STD_BD + 0x8),
9019                tr32(RCVDBDI_STD_BD + 0xc));
9020         printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
9021                tr32(RCVDBDI_MINI_BD + 0x0),
9022                tr32(RCVDBDI_MINI_BD + 0x4),
9023                tr32(RCVDBDI_MINI_BD + 0x8),
9024                tr32(RCVDBDI_MINI_BD + 0xc));
9025
9026         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
9027         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
9028         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
9029         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
9030         printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
9031                val32, val32_2, val32_3, val32_4);
9032
9033         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
9034         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
9035         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
9036         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
9037         printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
9038                val32, val32_2, val32_3, val32_4);
9039
9040         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
9041         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
9042         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
9043         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
9044         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
9045         printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
9046                val32, val32_2, val32_3, val32_4, val32_5);
9047
9048         /* SW status block */
9049         printk(KERN_DEBUG
9050          "Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
9051                sblk->status,
9052                sblk->status_tag,
9053                sblk->rx_jumbo_consumer,
9054                sblk->rx_consumer,
9055                sblk->rx_mini_consumer,
9056                sblk->idx[0].rx_producer,
9057                sblk->idx[0].tx_consumer);
9058
9059         /* SW statistics block */
9060         printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
9061                ((u32 *)tp->hw_stats)[0],
9062                ((u32 *)tp->hw_stats)[1],
9063                ((u32 *)tp->hw_stats)[2],
9064                ((u32 *)tp->hw_stats)[3]);
9065
9066         /* Mailboxes */
9067         printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
9068                tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
9069                tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
9070                tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
9071                tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
9072
9073         /* NIC side send descriptors. */
9074         for (i = 0; i < 6; i++) {
9075                 unsigned long txd;
9076
9077                 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
9078                         + (i * sizeof(struct tg3_tx_buffer_desc));
9079                 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
9080                        i,
9081                        readl(txd + 0x0), readl(txd + 0x4),
9082                        readl(txd + 0x8), readl(txd + 0xc));
9083         }
9084
9085         /* NIC side RX descriptors. */
9086         for (i = 0; i < 6; i++) {
9087                 unsigned long rxd;
9088
9089                 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
9090                         + (i * sizeof(struct tg3_rx_buffer_desc));
9091                 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
9092                        i,
9093                        readl(rxd + 0x0), readl(rxd + 0x4),
9094                        readl(rxd + 0x8), readl(rxd + 0xc));
9095                 rxd += (4 * sizeof(u32));
9096                 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
9097                        i,
9098                        readl(rxd + 0x0), readl(rxd + 0x4),
9099                        readl(rxd + 0x8), readl(rxd + 0xc));
9100         }
9101
9102         for (i = 0; i < 6; i++) {
9103                 unsigned long rxd;
9104
9105                 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
9106                         + (i * sizeof(struct tg3_rx_buffer_desc));
9107                 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
9108                        i,
9109                        readl(rxd + 0x0), readl(rxd + 0x4),
9110                        readl(rxd + 0x8), readl(rxd + 0xc));
9111                 rxd += (4 * sizeof(u32));
9112                 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
9113                        i,
9114                        readl(rxd + 0x0), readl(rxd + 0x4),
9115                        readl(rxd + 0x8), readl(rxd + 0xc));
9116         }
9117 }
9118 #endif
9119
9120 static struct net_device_stats *tg3_get_stats(struct net_device *);
9121 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
9122
9123 static int tg3_close(struct net_device *dev)
9124 {
9125         int i;
9126         struct tg3 *tp = netdev_priv(dev);
9127
9128         tg3_napi_disable(tp);
9129         cancel_work_sync(&tp->reset_task);
9130
9131         netif_tx_stop_all_queues(dev);
9132
9133         del_timer_sync(&tp->timer);
9134
9135         tg3_phy_stop(tp);
9136
9137         tg3_full_lock(tp, 1);
9138 #if 0
9139         tg3_dump_state(tp);
9140 #endif
9141
9142         tg3_disable_ints(tp);
9143
9144         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9145         tg3_free_rings(tp);
9146         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
9147
9148         tg3_full_unlock(tp);
9149
9150         for (i = tp->irq_cnt - 1; i >= 0; i--) {
9151                 struct tg3_napi *tnapi = &tp->napi[i];
9152                 free_irq(tnapi->irq_vec, tnapi);
9153         }
9154
9155         tg3_ints_fini(tp);
9156
9157         memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
9158                sizeof(tp->net_stats_prev));
9159         memcpy(&tp->estats_prev, tg3_get_estats(tp),
9160                sizeof(tp->estats_prev));
9161
9162         tg3_free_consistent(tp);
9163
9164         tg3_set_power_state(tp, PCI_D3hot);
9165
9166         netif_carrier_off(tp->dev);
9167
9168         return 0;
9169 }
9170
9171 static inline unsigned long get_stat64(tg3_stat64_t *val)
9172 {
9173         unsigned long ret;
9174
9175 #if (BITS_PER_LONG == 32)
9176         ret = val->low;
9177 #else
9178         ret = ((u64)val->high << 32) | ((u64)val->low);
9179 #endif
9180         return ret;
9181 }
9182
9183 static inline u64 get_estat64(tg3_stat64_t *val)
9184 {
9185        return ((u64)val->high << 32) | ((u64)val->low);
9186 }
9187
9188 static unsigned long calc_crc_errors(struct tg3 *tp)
9189 {
9190         struct tg3_hw_stats *hw_stats = tp->hw_stats;
9191
9192         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
9193             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
9194              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
9195                 u32 val;
9196
9197                 spin_lock_bh(&tp->lock);
9198                 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
9199                         tg3_writephy(tp, MII_TG3_TEST1,
9200                                      val | MII_TG3_TEST1_CRC_EN);
9201                         tg3_readphy(tp, 0x14, &val);
9202                 } else
9203                         val = 0;
9204                 spin_unlock_bh(&tp->lock);
9205
9206                 tp->phy_crc_errors += val;
9207
9208                 return tp->phy_crc_errors;
9209         }
9210
9211         return get_stat64(&hw_stats->rx_fcs_errors);
9212 }
9213
9214 #define ESTAT_ADD(member) \
9215         estats->member =        old_estats->member + \
9216                                 get_estat64(&hw_stats->member)
9217
9218 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
9219 {
9220         struct tg3_ethtool_stats *estats = &tp->estats;
9221         struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
9222         struct tg3_hw_stats *hw_stats = tp->hw_stats;
9223
9224         if (!hw_stats)
9225                 return old_estats;
9226
9227         ESTAT_ADD(rx_octets);
9228         ESTAT_ADD(rx_fragments);
9229         ESTAT_ADD(rx_ucast_packets);
9230         ESTAT_ADD(rx_mcast_packets);
9231         ESTAT_ADD(rx_bcast_packets);
9232         ESTAT_ADD(rx_fcs_errors);
9233         ESTAT_ADD(rx_align_errors);
9234         ESTAT_ADD(rx_xon_pause_rcvd);
9235         ESTAT_ADD(rx_xoff_pause_rcvd);
9236         ESTAT_ADD(rx_mac_ctrl_rcvd);
9237         ESTAT_ADD(rx_xoff_entered);
9238         ESTAT_ADD(rx_frame_too_long_errors);
9239         ESTAT_ADD(rx_jabbers);
9240         ESTAT_ADD(rx_undersize_packets);
9241         ESTAT_ADD(rx_in_length_errors);
9242         ESTAT_ADD(rx_out_length_errors);
9243         ESTAT_ADD(rx_64_or_less_octet_packets);
9244         ESTAT_ADD(rx_65_to_127_octet_packets);
9245         ESTAT_ADD(rx_128_to_255_octet_packets);
9246         ESTAT_ADD(rx_256_to_511_octet_packets);
9247         ESTAT_ADD(rx_512_to_1023_octet_packets);
9248         ESTAT_ADD(rx_1024_to_1522_octet_packets);
9249         ESTAT_ADD(rx_1523_to_2047_octet_packets);
9250         ESTAT_ADD(rx_2048_to_4095_octet_packets);
9251         ESTAT_ADD(rx_4096_to_8191_octet_packets);
9252         ESTAT_ADD(rx_8192_to_9022_octet_packets);
9253
9254         ESTAT_ADD(tx_octets);
9255         ESTAT_ADD(tx_collisions);
9256         ESTAT_ADD(tx_xon_sent);
9257         ESTAT_ADD(tx_xoff_sent);
9258         ESTAT_ADD(tx_flow_control);
9259         ESTAT_ADD(tx_mac_errors);
9260         ESTAT_ADD(tx_single_collisions);
9261         ESTAT_ADD(tx_mult_collisions);
9262         ESTAT_ADD(tx_deferred);
9263         ESTAT_ADD(tx_excessive_collisions);
9264         ESTAT_ADD(tx_late_collisions);
9265         ESTAT_ADD(tx_collide_2times);
9266         ESTAT_ADD(tx_collide_3times);
9267         ESTAT_ADD(tx_collide_4times);
9268         ESTAT_ADD(tx_collide_5times);
9269         ESTAT_ADD(tx_collide_6times);
9270         ESTAT_ADD(tx_collide_7times);
9271         ESTAT_ADD(tx_collide_8times);
9272         ESTAT_ADD(tx_collide_9times);
9273         ESTAT_ADD(tx_collide_10times);
9274         ESTAT_ADD(tx_collide_11times);
9275         ESTAT_ADD(tx_collide_12times);
9276         ESTAT_ADD(tx_collide_13times);
9277         ESTAT_ADD(tx_collide_14times);
9278         ESTAT_ADD(tx_collide_15times);
9279         ESTAT_ADD(tx_ucast_packets);
9280         ESTAT_ADD(tx_mcast_packets);
9281         ESTAT_ADD(tx_bcast_packets);
9282         ESTAT_ADD(tx_carrier_sense_errors);
9283         ESTAT_ADD(tx_discards);
9284         ESTAT_ADD(tx_errors);
9285
9286         ESTAT_ADD(dma_writeq_full);
9287         ESTAT_ADD(dma_write_prioq_full);
9288         ESTAT_ADD(rxbds_empty);
9289         ESTAT_ADD(rx_discards);
9290         ESTAT_ADD(rx_errors);
9291         ESTAT_ADD(rx_threshold_hit);
9292
9293         ESTAT_ADD(dma_readq_full);
9294         ESTAT_ADD(dma_read_prioq_full);
9295         ESTAT_ADD(tx_comp_queue_full);
9296
9297         ESTAT_ADD(ring_set_send_prod_index);
9298         ESTAT_ADD(ring_status_update);
9299         ESTAT_ADD(nic_irqs);
9300         ESTAT_ADD(nic_avoided_irqs);
9301         ESTAT_ADD(nic_tx_threshold_hit);
9302
9303         return estats;
9304 }
9305
9306 static struct net_device_stats *tg3_get_stats(struct net_device *dev)
9307 {
9308         struct tg3 *tp = netdev_priv(dev);
9309         struct net_device_stats *stats = &tp->net_stats;
9310         struct net_device_stats *old_stats = &tp->net_stats_prev;
9311         struct tg3_hw_stats *hw_stats = tp->hw_stats;
9312
9313         if (!hw_stats)
9314                 return old_stats;
9315
9316         stats->rx_packets = old_stats->rx_packets +
9317                 get_stat64(&hw_stats->rx_ucast_packets) +
9318                 get_stat64(&hw_stats->rx_mcast_packets) +
9319                 get_stat64(&hw_stats->rx_bcast_packets);
9320
9321         stats->tx_packets = old_stats->tx_packets +
9322                 get_stat64(&hw_stats->tx_ucast_packets) +
9323                 get_stat64(&hw_stats->tx_mcast_packets) +
9324                 get_stat64(&hw_stats->tx_bcast_packets);
9325
9326         stats->rx_bytes = old_stats->rx_bytes +
9327                 get_stat64(&hw_stats->rx_octets);
9328         stats->tx_bytes = old_stats->tx_bytes +
9329                 get_stat64(&hw_stats->tx_octets);
9330
9331         stats->rx_errors = old_stats->rx_errors +
9332                 get_stat64(&hw_stats->rx_errors);
9333         stats->tx_errors = old_stats->tx_errors +
9334                 get_stat64(&hw_stats->tx_errors) +
9335                 get_stat64(&hw_stats->tx_mac_errors) +
9336                 get_stat64(&hw_stats->tx_carrier_sense_errors) +
9337                 get_stat64(&hw_stats->tx_discards);
9338
9339         stats->multicast = old_stats->multicast +
9340                 get_stat64(&hw_stats->rx_mcast_packets);
9341         stats->collisions = old_stats->collisions +
9342                 get_stat64(&hw_stats->tx_collisions);
9343
9344         stats->rx_length_errors = old_stats->rx_length_errors +
9345                 get_stat64(&hw_stats->rx_frame_too_long_errors) +
9346                 get_stat64(&hw_stats->rx_undersize_packets);
9347
9348         stats->rx_over_errors = old_stats->rx_over_errors +
9349                 get_stat64(&hw_stats->rxbds_empty);
9350         stats->rx_frame_errors = old_stats->rx_frame_errors +
9351                 get_stat64(&hw_stats->rx_align_errors);
9352         stats->tx_aborted_errors = old_stats->tx_aborted_errors +
9353                 get_stat64(&hw_stats->tx_discards);
9354         stats->tx_carrier_errors = old_stats->tx_carrier_errors +
9355                 get_stat64(&hw_stats->tx_carrier_sense_errors);
9356
9357         stats->rx_crc_errors = old_stats->rx_crc_errors +
9358                 calc_crc_errors(tp);
9359
9360         stats->rx_missed_errors = old_stats->rx_missed_errors +
9361                 get_stat64(&hw_stats->rx_discards);
9362
9363         return stats;
9364 }
9365
9366 static inline u32 calc_crc(unsigned char *buf, int len)
9367 {
9368         u32 reg;
9369         u32 tmp;
9370         int j, k;
9371
9372         reg = 0xffffffff;
9373
9374         for (j = 0; j < len; j++) {
9375                 reg ^= buf[j];
9376
9377                 for (k = 0; k < 8; k++) {
9378                         tmp = reg & 0x01;
9379
9380                         reg >>= 1;
9381
9382                         if (tmp) {
9383                                 reg ^= 0xedb88320;
9384                         }
9385                 }
9386         }
9387
9388         return ~reg;
9389 }
9390
9391 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
9392 {
9393         /* accept or reject all multicast frames */
9394         tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
9395         tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
9396         tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
9397         tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
9398 }
9399
9400 static void __tg3_set_rx_mode(struct net_device *dev)
9401 {
9402         struct tg3 *tp = netdev_priv(dev);
9403         u32 rx_mode;
9404
9405         rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
9406                                   RX_MODE_KEEP_VLAN_TAG);
9407
9408         /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9409          * flag clear.
9410          */
9411 #if TG3_VLAN_TAG_USED
9412         if (!tp->vlgrp &&
9413             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9414                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9415 #else
9416         /* By definition, VLAN is disabled always in this
9417          * case.
9418          */
9419         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9420                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9421 #endif
9422
9423         if (dev->flags & IFF_PROMISC) {
9424                 /* Promiscuous mode. */
9425                 rx_mode |= RX_MODE_PROMISC;
9426         } else if (dev->flags & IFF_ALLMULTI) {
9427                 /* Accept all multicast. */
9428                 tg3_set_multi (tp, 1);
9429         } else if (netdev_mc_empty(dev)) {
9430                 /* Reject all multicast. */
9431                 tg3_set_multi (tp, 0);
9432         } else {
9433                 /* Accept one or more multicast(s). */
9434                 struct dev_mc_list *mclist;
9435                 unsigned int i;
9436                 u32 mc_filter[4] = { 0, };
9437                 u32 regidx;
9438                 u32 bit;
9439                 u32 crc;
9440
9441                 for (i = 0, mclist = dev->mc_list; mclist && i < netdev_mc_count(dev);
9442                      i++, mclist = mclist->next) {
9443
9444                         crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
9445                         bit = ~crc & 0x7f;
9446                         regidx = (bit & 0x60) >> 5;
9447                         bit &= 0x1f;
9448                         mc_filter[regidx] |= (1 << bit);
9449                 }
9450
9451                 tw32(MAC_HASH_REG_0, mc_filter[0]);
9452                 tw32(MAC_HASH_REG_1, mc_filter[1]);
9453                 tw32(MAC_HASH_REG_2, mc_filter[2]);
9454                 tw32(MAC_HASH_REG_3, mc_filter[3]);
9455         }
9456
9457         if (rx_mode != tp->rx_mode) {
9458                 tp->rx_mode = rx_mode;
9459                 tw32_f(MAC_RX_MODE, rx_mode);
9460                 udelay(10);
9461         }
9462 }
9463
9464 static void tg3_set_rx_mode(struct net_device *dev)
9465 {
9466         struct tg3 *tp = netdev_priv(dev);
9467
9468         if (!netif_running(dev))
9469                 return;
9470
9471         tg3_full_lock(tp, 0);
9472         __tg3_set_rx_mode(dev);
9473         tg3_full_unlock(tp);
9474 }
9475
9476 #define TG3_REGDUMP_LEN         (32 * 1024)
9477
9478 static int tg3_get_regs_len(struct net_device *dev)
9479 {
9480         return TG3_REGDUMP_LEN;
9481 }
9482
9483 static void tg3_get_regs(struct net_device *dev,
9484                 struct ethtool_regs *regs, void *_p)
9485 {
9486         u32 *p = _p;
9487         struct tg3 *tp = netdev_priv(dev);
9488         u8 *orig_p = _p;
9489         int i;
9490
9491         regs->version = 0;
9492
9493         memset(p, 0, TG3_REGDUMP_LEN);
9494
9495         if (tp->link_config.phy_is_low_power)
9496                 return;
9497
9498         tg3_full_lock(tp, 0);
9499
9500 #define __GET_REG32(reg)        (*(p)++ = tr32(reg))
9501 #define GET_REG32_LOOP(base,len)                \
9502 do {    p = (u32 *)(orig_p + (base));           \
9503         for (i = 0; i < len; i += 4)            \
9504                 __GET_REG32((base) + i);        \
9505 } while (0)
9506 #define GET_REG32_1(reg)                        \
9507 do {    p = (u32 *)(orig_p + (reg));            \
9508         __GET_REG32((reg));                     \
9509 } while (0)
9510
9511         GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
9512         GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
9513         GET_REG32_LOOP(MAC_MODE, 0x4f0);
9514         GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
9515         GET_REG32_1(SNDDATAC_MODE);
9516         GET_REG32_LOOP(SNDBDS_MODE, 0x80);
9517         GET_REG32_LOOP(SNDBDI_MODE, 0x48);
9518         GET_REG32_1(SNDBDC_MODE);
9519         GET_REG32_LOOP(RCVLPC_MODE, 0x20);
9520         GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
9521         GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
9522         GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
9523         GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
9524         GET_REG32_1(RCVDCC_MODE);
9525         GET_REG32_LOOP(RCVBDI_MODE, 0x20);
9526         GET_REG32_LOOP(RCVCC_MODE, 0x14);
9527         GET_REG32_LOOP(RCVLSC_MODE, 0x08);
9528         GET_REG32_1(MBFREE_MODE);
9529         GET_REG32_LOOP(HOSTCC_MODE, 0x100);
9530         GET_REG32_LOOP(MEMARB_MODE, 0x10);
9531         GET_REG32_LOOP(BUFMGR_MODE, 0x58);
9532         GET_REG32_LOOP(RDMAC_MODE, 0x08);
9533         GET_REG32_LOOP(WDMAC_MODE, 0x08);
9534         GET_REG32_1(RX_CPU_MODE);
9535         GET_REG32_1(RX_CPU_STATE);
9536         GET_REG32_1(RX_CPU_PGMCTR);
9537         GET_REG32_1(RX_CPU_HWBKPT);
9538         GET_REG32_1(TX_CPU_MODE);
9539         GET_REG32_1(TX_CPU_STATE);
9540         GET_REG32_1(TX_CPU_PGMCTR);
9541         GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
9542         GET_REG32_LOOP(FTQ_RESET, 0x120);
9543         GET_REG32_LOOP(MSGINT_MODE, 0x0c);
9544         GET_REG32_1(DMAC_MODE);
9545         GET_REG32_LOOP(GRC_MODE, 0x4c);
9546         if (tp->tg3_flags & TG3_FLAG_NVRAM)
9547                 GET_REG32_LOOP(NVRAM_CMD, 0x24);
9548
9549 #undef __GET_REG32
9550 #undef GET_REG32_LOOP
9551 #undef GET_REG32_1
9552
9553         tg3_full_unlock(tp);
9554 }
9555
9556 static int tg3_get_eeprom_len(struct net_device *dev)
9557 {
9558         struct tg3 *tp = netdev_priv(dev);
9559
9560         return tp->nvram_size;
9561 }
9562
9563 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9564 {
9565         struct tg3 *tp = netdev_priv(dev);
9566         int ret;
9567         u8  *pd;
9568         u32 i, offset, len, b_offset, b_count;
9569         __be32 val;
9570
9571         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9572                 return -EINVAL;
9573
9574         if (tp->link_config.phy_is_low_power)
9575                 return -EAGAIN;
9576
9577         offset = eeprom->offset;
9578         len = eeprom->len;
9579         eeprom->len = 0;
9580
9581         eeprom->magic = TG3_EEPROM_MAGIC;
9582
9583         if (offset & 3) {
9584                 /* adjustments to start on required 4 byte boundary */
9585                 b_offset = offset & 3;
9586                 b_count = 4 - b_offset;
9587                 if (b_count > len) {
9588                         /* i.e. offset=1 len=2 */
9589                         b_count = len;
9590                 }
9591                 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
9592                 if (ret)
9593                         return ret;
9594                 memcpy(data, ((char*)&val) + b_offset, b_count);
9595                 len -= b_count;
9596                 offset += b_count;
9597                 eeprom->len += b_count;
9598         }
9599
9600         /* read bytes upto the last 4 byte boundary */
9601         pd = &data[eeprom->len];
9602         for (i = 0; i < (len - (len & 3)); i += 4) {
9603                 ret = tg3_nvram_read_be32(tp, offset + i, &val);
9604                 if (ret) {
9605                         eeprom->len += i;
9606                         return ret;
9607                 }
9608                 memcpy(pd + i, &val, 4);
9609         }
9610         eeprom->len += i;
9611
9612         if (len & 3) {
9613                 /* read last bytes not ending on 4 byte boundary */
9614                 pd = &data[eeprom->len];
9615                 b_count = len & 3;
9616                 b_offset = offset + len - b_count;
9617                 ret = tg3_nvram_read_be32(tp, b_offset, &val);
9618                 if (ret)
9619                         return ret;
9620                 memcpy(pd, &val, b_count);
9621                 eeprom->len += b_count;
9622         }
9623         return 0;
9624 }
9625
9626 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
9627
9628 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9629 {
9630         struct tg3 *tp = netdev_priv(dev);
9631         int ret;
9632         u32 offset, len, b_offset, odd_len;
9633         u8 *buf;
9634         __be32 start, end;
9635
9636         if (tp->link_config.phy_is_low_power)
9637                 return -EAGAIN;
9638
9639         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
9640             eeprom->magic != TG3_EEPROM_MAGIC)
9641                 return -EINVAL;
9642
9643         offset = eeprom->offset;
9644         len = eeprom->len;
9645
9646         if ((b_offset = (offset & 3))) {
9647                 /* adjustments to start on required 4 byte boundary */
9648                 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
9649                 if (ret)
9650                         return ret;
9651                 len += b_offset;
9652                 offset &= ~3;
9653                 if (len < 4)
9654                         len = 4;
9655         }
9656
9657         odd_len = 0;
9658         if (len & 3) {
9659                 /* adjustments to end on required 4 byte boundary */
9660                 odd_len = 1;
9661                 len = (len + 3) & ~3;
9662                 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
9663                 if (ret)
9664                         return ret;
9665         }
9666
9667         buf = data;
9668         if (b_offset || odd_len) {
9669                 buf = kmalloc(len, GFP_KERNEL);
9670                 if (!buf)
9671                         return -ENOMEM;
9672                 if (b_offset)
9673                         memcpy(buf, &start, 4);
9674                 if (odd_len)
9675                         memcpy(buf+len-4, &end, 4);
9676                 memcpy(buf + b_offset, data, eeprom->len);
9677         }
9678
9679         ret = tg3_nvram_write_block(tp, offset, len, buf);
9680
9681         if (buf != data)
9682                 kfree(buf);
9683
9684         return ret;
9685 }
9686
9687 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9688 {
9689         struct tg3 *tp = netdev_priv(dev);
9690
9691         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9692                 struct phy_device *phydev;
9693                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9694                         return -EAGAIN;
9695                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9696                 return phy_ethtool_gset(phydev, cmd);
9697         }
9698
9699         cmd->supported = (SUPPORTED_Autoneg);
9700
9701         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
9702                 cmd->supported |= (SUPPORTED_1000baseT_Half |
9703                                    SUPPORTED_1000baseT_Full);
9704
9705         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
9706                 cmd->supported |= (SUPPORTED_100baseT_Half |
9707                                   SUPPORTED_100baseT_Full |
9708                                   SUPPORTED_10baseT_Half |
9709                                   SUPPORTED_10baseT_Full |
9710                                   SUPPORTED_TP);
9711                 cmd->port = PORT_TP;
9712         } else {
9713                 cmd->supported |= SUPPORTED_FIBRE;
9714                 cmd->port = PORT_FIBRE;
9715         }
9716
9717         cmd->advertising = tp->link_config.advertising;
9718         if (netif_running(dev)) {
9719                 cmd->speed = tp->link_config.active_speed;
9720                 cmd->duplex = tp->link_config.active_duplex;
9721         }
9722         cmd->phy_address = tp->phy_addr;
9723         cmd->transceiver = XCVR_INTERNAL;
9724         cmd->autoneg = tp->link_config.autoneg;
9725         cmd->maxtxpkt = 0;
9726         cmd->maxrxpkt = 0;
9727         return 0;
9728 }
9729
9730 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9731 {
9732         struct tg3 *tp = netdev_priv(dev);
9733
9734         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9735                 struct phy_device *phydev;
9736                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9737                         return -EAGAIN;
9738                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9739                 return phy_ethtool_sset(phydev, cmd);
9740         }
9741
9742         if (cmd->autoneg != AUTONEG_ENABLE &&
9743             cmd->autoneg != AUTONEG_DISABLE)
9744                 return -EINVAL;
9745
9746         if (cmd->autoneg == AUTONEG_DISABLE &&
9747             cmd->duplex != DUPLEX_FULL &&
9748             cmd->duplex != DUPLEX_HALF)
9749                 return -EINVAL;
9750
9751         if (cmd->autoneg == AUTONEG_ENABLE) {
9752                 u32 mask = ADVERTISED_Autoneg |
9753                            ADVERTISED_Pause |
9754                            ADVERTISED_Asym_Pause;
9755
9756                 if (!(tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
9757                         mask |= ADVERTISED_1000baseT_Half |
9758                                 ADVERTISED_1000baseT_Full;
9759
9760                 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
9761                         mask |= ADVERTISED_100baseT_Half |
9762                                 ADVERTISED_100baseT_Full |
9763                                 ADVERTISED_10baseT_Half |
9764                                 ADVERTISED_10baseT_Full |
9765                                 ADVERTISED_TP;
9766                 else
9767                         mask |= ADVERTISED_FIBRE;
9768
9769                 if (cmd->advertising & ~mask)
9770                         return -EINVAL;
9771
9772                 mask &= (ADVERTISED_1000baseT_Half |
9773                          ADVERTISED_1000baseT_Full |
9774                          ADVERTISED_100baseT_Half |
9775                          ADVERTISED_100baseT_Full |
9776                          ADVERTISED_10baseT_Half |
9777                          ADVERTISED_10baseT_Full);
9778
9779                 cmd->advertising &= mask;
9780         } else {
9781                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
9782                         if (cmd->speed != SPEED_1000)
9783                                 return -EINVAL;
9784
9785                         if (cmd->duplex != DUPLEX_FULL)
9786                                 return -EINVAL;
9787                 } else {
9788                         if (cmd->speed != SPEED_100 &&
9789                             cmd->speed != SPEED_10)
9790                                 return -EINVAL;
9791                 }
9792         }
9793
9794         tg3_full_lock(tp, 0);
9795
9796         tp->link_config.autoneg = cmd->autoneg;
9797         if (cmd->autoneg == AUTONEG_ENABLE) {
9798                 tp->link_config.advertising = (cmd->advertising |
9799                                               ADVERTISED_Autoneg);
9800                 tp->link_config.speed = SPEED_INVALID;
9801                 tp->link_config.duplex = DUPLEX_INVALID;
9802         } else {
9803                 tp->link_config.advertising = 0;
9804                 tp->link_config.speed = cmd->speed;
9805                 tp->link_config.duplex = cmd->duplex;
9806         }
9807
9808         tp->link_config.orig_speed = tp->link_config.speed;
9809         tp->link_config.orig_duplex = tp->link_config.duplex;
9810         tp->link_config.orig_autoneg = tp->link_config.autoneg;
9811
9812         if (netif_running(dev))
9813                 tg3_setup_phy(tp, 1);
9814
9815         tg3_full_unlock(tp);
9816
9817         return 0;
9818 }
9819
9820 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
9821 {
9822         struct tg3 *tp = netdev_priv(dev);
9823
9824         strcpy(info->driver, DRV_MODULE_NAME);
9825         strcpy(info->version, DRV_MODULE_VERSION);
9826         strcpy(info->fw_version, tp->fw_ver);
9827         strcpy(info->bus_info, pci_name(tp->pdev));
9828 }
9829
9830 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9831 {
9832         struct tg3 *tp = netdev_priv(dev);
9833
9834         if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
9835             device_can_wakeup(&tp->pdev->dev))
9836                 wol->supported = WAKE_MAGIC;
9837         else
9838                 wol->supported = 0;
9839         wol->wolopts = 0;
9840         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
9841             device_can_wakeup(&tp->pdev->dev))
9842                 wol->wolopts = WAKE_MAGIC;
9843         memset(&wol->sopass, 0, sizeof(wol->sopass));
9844 }
9845
9846 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9847 {
9848         struct tg3 *tp = netdev_priv(dev);
9849         struct device *dp = &tp->pdev->dev;
9850
9851         if (wol->wolopts & ~WAKE_MAGIC)
9852                 return -EINVAL;
9853         if ((wol->wolopts & WAKE_MAGIC) &&
9854             !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
9855                 return -EINVAL;
9856
9857         spin_lock_bh(&tp->lock);
9858         if (wol->wolopts & WAKE_MAGIC) {
9859                 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
9860                 device_set_wakeup_enable(dp, true);
9861         } else {
9862                 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
9863                 device_set_wakeup_enable(dp, false);
9864         }
9865         spin_unlock_bh(&tp->lock);
9866
9867         return 0;
9868 }
9869
9870 static u32 tg3_get_msglevel(struct net_device *dev)
9871 {
9872         struct tg3 *tp = netdev_priv(dev);
9873         return tp->msg_enable;
9874 }
9875
9876 static void tg3_set_msglevel(struct net_device *dev, u32 value)
9877 {
9878         struct tg3 *tp = netdev_priv(dev);
9879         tp->msg_enable = value;
9880 }
9881
9882 static int tg3_set_tso(struct net_device *dev, u32 value)
9883 {
9884         struct tg3 *tp = netdev_priv(dev);
9885
9886         if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
9887                 if (value)
9888                         return -EINVAL;
9889                 return 0;
9890         }
9891         if ((dev->features & NETIF_F_IPV6_CSUM) &&
9892             ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
9893              (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3))) {
9894                 if (value) {
9895                         dev->features |= NETIF_F_TSO6;
9896                         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
9897                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9898                             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
9899                              GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
9900                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
9901                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9902                                 dev->features |= NETIF_F_TSO_ECN;
9903                 } else
9904                         dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
9905         }
9906         return ethtool_op_set_tso(dev, value);
9907 }
9908
9909 static int tg3_nway_reset(struct net_device *dev)
9910 {
9911         struct tg3 *tp = netdev_priv(dev);
9912         int r;
9913
9914         if (!netif_running(dev))
9915                 return -EAGAIN;
9916
9917         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9918                 return -EINVAL;
9919
9920         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9921                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9922                         return -EAGAIN;
9923                 r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
9924         } else {
9925                 u32 bmcr;
9926
9927                 spin_lock_bh(&tp->lock);
9928                 r = -EINVAL;
9929                 tg3_readphy(tp, MII_BMCR, &bmcr);
9930                 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
9931                     ((bmcr & BMCR_ANENABLE) ||
9932                      (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
9933                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
9934                                                    BMCR_ANENABLE);
9935                         r = 0;
9936                 }
9937                 spin_unlock_bh(&tp->lock);
9938         }
9939
9940         return r;
9941 }
9942
9943 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9944 {
9945         struct tg3 *tp = netdev_priv(dev);
9946
9947         ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
9948         ering->rx_mini_max_pending = 0;
9949         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9950                 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
9951         else
9952                 ering->rx_jumbo_max_pending = 0;
9953
9954         ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
9955
9956         ering->rx_pending = tp->rx_pending;
9957         ering->rx_mini_pending = 0;
9958         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9959                 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
9960         else
9961                 ering->rx_jumbo_pending = 0;
9962
9963         ering->tx_pending = tp->napi[0].tx_pending;
9964 }
9965
9966 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9967 {
9968         struct tg3 *tp = netdev_priv(dev);
9969         int i, irq_sync = 0, err = 0;
9970
9971         if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
9972             (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
9973             (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
9974             (ering->tx_pending <= MAX_SKB_FRAGS) ||
9975             ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
9976              (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
9977                 return -EINVAL;
9978
9979         if (netif_running(dev)) {
9980                 tg3_phy_stop(tp);
9981                 tg3_netif_stop(tp);
9982                 irq_sync = 1;
9983         }
9984
9985         tg3_full_lock(tp, irq_sync);
9986
9987         tp->rx_pending = ering->rx_pending;
9988
9989         if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
9990             tp->rx_pending > 63)
9991                 tp->rx_pending = 63;
9992         tp->rx_jumbo_pending = ering->rx_jumbo_pending;
9993
9994         for (i = 0; i < TG3_IRQ_MAX_VECS; i++)
9995                 tp->napi[i].tx_pending = ering->tx_pending;
9996
9997         if (netif_running(dev)) {
9998                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9999                 err = tg3_restart_hw(tp, 1);
10000                 if (!err)
10001                         tg3_netif_start(tp);
10002         }
10003
10004         tg3_full_unlock(tp);
10005
10006         if (irq_sync && !err)
10007                 tg3_phy_start(tp);
10008
10009         return err;
10010 }
10011
10012 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
10013 {
10014         struct tg3 *tp = netdev_priv(dev);
10015
10016         epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
10017
10018         if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
10019                 epause->rx_pause = 1;
10020         else
10021                 epause->rx_pause = 0;
10022
10023         if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
10024                 epause->tx_pause = 1;
10025         else
10026                 epause->tx_pause = 0;
10027 }
10028
10029 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
10030 {
10031         struct tg3 *tp = netdev_priv(dev);
10032         int err = 0;
10033
10034         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
10035                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
10036                         return -EAGAIN;
10037
10038                 if (epause->autoneg) {
10039                         u32 newadv;
10040                         struct phy_device *phydev;
10041
10042                         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
10043
10044                         if (epause->rx_pause) {
10045                                 if (epause->tx_pause)
10046                                         newadv = ADVERTISED_Pause;
10047                                 else
10048                                         newadv = ADVERTISED_Pause |
10049                                                  ADVERTISED_Asym_Pause;
10050                         } else if (epause->tx_pause) {
10051                                 newadv = ADVERTISED_Asym_Pause;
10052                         } else
10053                                 newadv = 0;
10054
10055                         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
10056                                 u32 oldadv = phydev->advertising &
10057                                              (ADVERTISED_Pause |
10058                                               ADVERTISED_Asym_Pause);
10059                                 if (oldadv != newadv) {
10060                                         phydev->advertising &=
10061                                                 ~(ADVERTISED_Pause |
10062                                                   ADVERTISED_Asym_Pause);
10063                                         phydev->advertising |= newadv;
10064                                         err = phy_start_aneg(phydev);
10065                                 }
10066                         } else {
10067                                 tp->link_config.advertising &=
10068                                                 ~(ADVERTISED_Pause |
10069                                                   ADVERTISED_Asym_Pause);
10070                                 tp->link_config.advertising |= newadv;
10071                         }
10072                 } else {
10073                         if (epause->rx_pause)
10074                                 tp->link_config.flowctrl |= FLOW_CTRL_RX;
10075                         else
10076                                 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
10077
10078                         if (epause->tx_pause)
10079                                 tp->link_config.flowctrl |= FLOW_CTRL_TX;
10080                         else
10081                                 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
10082
10083                         if (netif_running(dev))
10084                                 tg3_setup_flow_control(tp, 0, 0);
10085                 }
10086         } else {
10087                 int irq_sync = 0;
10088
10089                 if (netif_running(dev)) {
10090                         tg3_netif_stop(tp);
10091                         irq_sync = 1;
10092                 }
10093
10094                 tg3_full_lock(tp, irq_sync);
10095
10096                 if (epause->autoneg)
10097                         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
10098                 else
10099                         tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
10100                 if (epause->rx_pause)
10101                         tp->link_config.flowctrl |= FLOW_CTRL_RX;
10102                 else
10103                         tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
10104                 if (epause->tx_pause)
10105                         tp->link_config.flowctrl |= FLOW_CTRL_TX;
10106                 else
10107                         tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
10108
10109                 if (netif_running(dev)) {
10110                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10111                         err = tg3_restart_hw(tp, 1);
10112                         if (!err)
10113                                 tg3_netif_start(tp);
10114                 }
10115
10116                 tg3_full_unlock(tp);
10117         }
10118
10119         return err;
10120 }
10121
10122 static u32 tg3_get_rx_csum(struct net_device *dev)
10123 {
10124         struct tg3 *tp = netdev_priv(dev);
10125         return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
10126 }
10127
10128 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
10129 {
10130         struct tg3 *tp = netdev_priv(dev);
10131
10132         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10133                 if (data != 0)
10134                         return -EINVAL;
10135                 return 0;
10136         }
10137
10138         spin_lock_bh(&tp->lock);
10139         if (data)
10140                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
10141         else
10142                 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
10143         spin_unlock_bh(&tp->lock);
10144
10145         return 0;
10146 }
10147
10148 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
10149 {
10150         struct tg3 *tp = netdev_priv(dev);
10151
10152         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10153                 if (data != 0)
10154                         return -EINVAL;
10155                 return 0;
10156         }
10157
10158         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10159                 ethtool_op_set_tx_ipv6_csum(dev, data);
10160         else
10161                 ethtool_op_set_tx_csum(dev, data);
10162
10163         return 0;
10164 }
10165
10166 static int tg3_get_sset_count (struct net_device *dev, int sset)
10167 {
10168         switch (sset) {
10169         case ETH_SS_TEST:
10170                 return TG3_NUM_TEST;
10171         case ETH_SS_STATS:
10172                 return TG3_NUM_STATS;
10173         default:
10174                 return -EOPNOTSUPP;
10175         }
10176 }
10177
10178 static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
10179 {
10180         switch (stringset) {
10181         case ETH_SS_STATS:
10182                 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
10183                 break;
10184         case ETH_SS_TEST:
10185                 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
10186                 break;
10187         default:
10188                 WARN_ON(1);     /* we need a WARN() */
10189                 break;
10190         }
10191 }
10192
10193 static int tg3_phys_id(struct net_device *dev, u32 data)
10194 {
10195         struct tg3 *tp = netdev_priv(dev);
10196         int i;
10197
10198         if (!netif_running(tp->dev))
10199                 return -EAGAIN;
10200
10201         if (data == 0)
10202                 data = UINT_MAX / 2;
10203
10204         for (i = 0; i < (data * 2); i++) {
10205                 if ((i % 2) == 0)
10206                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10207                                            LED_CTRL_1000MBPS_ON |
10208                                            LED_CTRL_100MBPS_ON |
10209                                            LED_CTRL_10MBPS_ON |
10210                                            LED_CTRL_TRAFFIC_OVERRIDE |
10211                                            LED_CTRL_TRAFFIC_BLINK |
10212                                            LED_CTRL_TRAFFIC_LED);
10213
10214                 else
10215                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10216                                            LED_CTRL_TRAFFIC_OVERRIDE);
10217
10218                 if (msleep_interruptible(500))
10219                         break;
10220         }
10221         tw32(MAC_LED_CTRL, tp->led_ctrl);
10222         return 0;
10223 }
10224
10225 static void tg3_get_ethtool_stats (struct net_device *dev,
10226                                    struct ethtool_stats *estats, u64 *tmp_stats)
10227 {
10228         struct tg3 *tp = netdev_priv(dev);
10229         memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
10230 }
10231
10232 #define NVRAM_TEST_SIZE 0x100
10233 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE   0x14
10234 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE   0x18
10235 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE   0x1c
10236 #define NVRAM_SELFBOOT_HW_SIZE 0x20
10237 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
10238
10239 static int tg3_test_nvram(struct tg3 *tp)
10240 {
10241         u32 csum, magic;
10242         __be32 *buf;
10243         int i, j, k, err = 0, size;
10244
10245         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
10246                 return 0;
10247
10248         if (tg3_nvram_read(tp, 0, &magic) != 0)
10249                 return -EIO;
10250
10251         if (magic == TG3_EEPROM_MAGIC)
10252                 size = NVRAM_TEST_SIZE;
10253         else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
10254                 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
10255                     TG3_EEPROM_SB_FORMAT_1) {
10256                         switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
10257                         case TG3_EEPROM_SB_REVISION_0:
10258                                 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
10259                                 break;
10260                         case TG3_EEPROM_SB_REVISION_2:
10261                                 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
10262                                 break;
10263                         case TG3_EEPROM_SB_REVISION_3:
10264                                 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
10265                                 break;
10266                         default:
10267                                 return 0;
10268                         }
10269                 } else
10270                         return 0;
10271         } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
10272                 size = NVRAM_SELFBOOT_HW_SIZE;
10273         else
10274                 return -EIO;
10275
10276         buf = kmalloc(size, GFP_KERNEL);
10277         if (buf == NULL)
10278                 return -ENOMEM;
10279
10280         err = -EIO;
10281         for (i = 0, j = 0; i < size; i += 4, j++) {
10282                 err = tg3_nvram_read_be32(tp, i, &buf[j]);
10283                 if (err)
10284                         break;
10285         }
10286         if (i < size)
10287                 goto out;
10288
10289         /* Selfboot format */
10290         magic = be32_to_cpu(buf[0]);
10291         if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
10292             TG3_EEPROM_MAGIC_FW) {
10293                 u8 *buf8 = (u8 *) buf, csum8 = 0;
10294
10295                 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
10296                     TG3_EEPROM_SB_REVISION_2) {
10297                         /* For rev 2, the csum doesn't include the MBA. */
10298                         for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
10299                                 csum8 += buf8[i];
10300                         for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
10301                                 csum8 += buf8[i];
10302                 } else {
10303                         for (i = 0; i < size; i++)
10304                                 csum8 += buf8[i];
10305                 }
10306
10307                 if (csum8 == 0) {
10308                         err = 0;
10309                         goto out;
10310                 }
10311
10312                 err = -EIO;
10313                 goto out;
10314         }
10315
10316         if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
10317             TG3_EEPROM_MAGIC_HW) {
10318                 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
10319                 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
10320                 u8 *buf8 = (u8 *) buf;
10321
10322                 /* Separate the parity bits and the data bytes.  */
10323                 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
10324                         if ((i == 0) || (i == 8)) {
10325                                 int l;
10326                                 u8 msk;
10327
10328                                 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
10329                                         parity[k++] = buf8[i] & msk;
10330                                 i++;
10331                         }
10332                         else if (i == 16) {
10333                                 int l;
10334                                 u8 msk;
10335
10336                                 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
10337                                         parity[k++] = buf8[i] & msk;
10338                                 i++;
10339
10340                                 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
10341                                         parity[k++] = buf8[i] & msk;
10342                                 i++;
10343                         }
10344                         data[j++] = buf8[i];
10345                 }
10346
10347                 err = -EIO;
10348                 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
10349                         u8 hw8 = hweight8(data[i]);
10350
10351                         if ((hw8 & 0x1) && parity[i])
10352                                 goto out;
10353                         else if (!(hw8 & 0x1) && !parity[i])
10354                                 goto out;
10355                 }
10356                 err = 0;
10357                 goto out;
10358         }
10359
10360         /* Bootstrap checksum at offset 0x10 */
10361         csum = calc_crc((unsigned char *) buf, 0x10);
10362         if (csum != be32_to_cpu(buf[0x10/4]))
10363                 goto out;
10364
10365         /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
10366         csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
10367         if (csum != be32_to_cpu(buf[0xfc/4]))
10368                 goto out;
10369
10370         err = 0;
10371
10372 out:
10373         kfree(buf);
10374         return err;
10375 }
10376
10377 #define TG3_SERDES_TIMEOUT_SEC  2
10378 #define TG3_COPPER_TIMEOUT_SEC  6
10379
10380 static int tg3_test_link(struct tg3 *tp)
10381 {
10382         int i, max;
10383
10384         if (!netif_running(tp->dev))
10385                 return -ENODEV;
10386
10387         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
10388                 max = TG3_SERDES_TIMEOUT_SEC;
10389         else
10390                 max = TG3_COPPER_TIMEOUT_SEC;
10391
10392         for (i = 0; i < max; i++) {
10393                 if (netif_carrier_ok(tp->dev))
10394                         return 0;
10395
10396                 if (msleep_interruptible(1000))
10397                         break;
10398         }
10399
10400         return -EIO;
10401 }
10402
10403 /* Only test the commonly used registers */
10404 static int tg3_test_registers(struct tg3 *tp)
10405 {
10406         int i, is_5705, is_5750;
10407         u32 offset, read_mask, write_mask, val, save_val, read_val;
10408         static struct {
10409                 u16 offset;
10410                 u16 flags;
10411 #define TG3_FL_5705     0x1
10412 #define TG3_FL_NOT_5705 0x2
10413 #define TG3_FL_NOT_5788 0x4
10414 #define TG3_FL_NOT_5750 0x8
10415                 u32 read_mask;
10416                 u32 write_mask;
10417         } reg_tbl[] = {
10418                 /* MAC Control Registers */
10419                 { MAC_MODE, TG3_FL_NOT_5705,
10420                         0x00000000, 0x00ef6f8c },
10421                 { MAC_MODE, TG3_FL_5705,
10422                         0x00000000, 0x01ef6b8c },
10423                 { MAC_STATUS, TG3_FL_NOT_5705,
10424                         0x03800107, 0x00000000 },
10425                 { MAC_STATUS, TG3_FL_5705,
10426                         0x03800100, 0x00000000 },
10427                 { MAC_ADDR_0_HIGH, 0x0000,
10428                         0x00000000, 0x0000ffff },
10429                 { MAC_ADDR_0_LOW, 0x0000,
10430                         0x00000000, 0xffffffff },
10431                 { MAC_RX_MTU_SIZE, 0x0000,
10432                         0x00000000, 0x0000ffff },
10433                 { MAC_TX_MODE, 0x0000,
10434                         0x00000000, 0x00000070 },
10435                 { MAC_TX_LENGTHS, 0x0000,
10436                         0x00000000, 0x00003fff },
10437                 { MAC_RX_MODE, TG3_FL_NOT_5705,
10438                         0x00000000, 0x000007fc },
10439                 { MAC_RX_MODE, TG3_FL_5705,
10440                         0x00000000, 0x000007dc },
10441                 { MAC_HASH_REG_0, 0x0000,
10442                         0x00000000, 0xffffffff },
10443                 { MAC_HASH_REG_1, 0x0000,
10444                         0x00000000, 0xffffffff },
10445                 { MAC_HASH_REG_2, 0x0000,
10446                         0x00000000, 0xffffffff },
10447                 { MAC_HASH_REG_3, 0x0000,
10448                         0x00000000, 0xffffffff },
10449
10450                 /* Receive Data and Receive BD Initiator Control Registers. */
10451                 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
10452                         0x00000000, 0xffffffff },
10453                 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
10454                         0x00000000, 0xffffffff },
10455                 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
10456                         0x00000000, 0x00000003 },
10457                 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
10458                         0x00000000, 0xffffffff },
10459                 { RCVDBDI_STD_BD+0, 0x0000,
10460                         0x00000000, 0xffffffff },
10461                 { RCVDBDI_STD_BD+4, 0x0000,
10462                         0x00000000, 0xffffffff },
10463                 { RCVDBDI_STD_BD+8, 0x0000,
10464                         0x00000000, 0xffff0002 },
10465                 { RCVDBDI_STD_BD+0xc, 0x0000,
10466                         0x00000000, 0xffffffff },
10467
10468                 /* Receive BD Initiator Control Registers. */
10469                 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
10470                         0x00000000, 0xffffffff },
10471                 { RCVBDI_STD_THRESH, TG3_FL_5705,
10472                         0x00000000, 0x000003ff },
10473                 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
10474                         0x00000000, 0xffffffff },
10475
10476                 /* Host Coalescing Control Registers. */
10477                 { HOSTCC_MODE, TG3_FL_NOT_5705,
10478                         0x00000000, 0x00000004 },
10479                 { HOSTCC_MODE, TG3_FL_5705,
10480                         0x00000000, 0x000000f6 },
10481                 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
10482                         0x00000000, 0xffffffff },
10483                 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
10484                         0x00000000, 0x000003ff },
10485                 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
10486                         0x00000000, 0xffffffff },
10487                 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
10488                         0x00000000, 0x000003ff },
10489                 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
10490                         0x00000000, 0xffffffff },
10491                 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10492                         0x00000000, 0x000000ff },
10493                 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
10494                         0x00000000, 0xffffffff },
10495                 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10496                         0x00000000, 0x000000ff },
10497                 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
10498                         0x00000000, 0xffffffff },
10499                 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
10500                         0x00000000, 0xffffffff },
10501                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10502                         0x00000000, 0xffffffff },
10503                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10504                         0x00000000, 0x000000ff },
10505                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10506                         0x00000000, 0xffffffff },
10507                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10508                         0x00000000, 0x000000ff },
10509                 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
10510                         0x00000000, 0xffffffff },
10511                 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
10512                         0x00000000, 0xffffffff },
10513                 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
10514                         0x00000000, 0xffffffff },
10515                 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
10516                         0x00000000, 0xffffffff },
10517                 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
10518                         0x00000000, 0xffffffff },
10519                 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
10520                         0xffffffff, 0x00000000 },
10521                 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
10522                         0xffffffff, 0x00000000 },
10523
10524                 /* Buffer Manager Control Registers. */
10525                 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
10526                         0x00000000, 0x007fff80 },
10527                 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
10528                         0x00000000, 0x007fffff },
10529                 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
10530                         0x00000000, 0x0000003f },
10531                 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
10532                         0x00000000, 0x000001ff },
10533                 { BUFMGR_MB_HIGH_WATER, 0x0000,
10534                         0x00000000, 0x000001ff },
10535                 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
10536                         0xffffffff, 0x00000000 },
10537                 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
10538                         0xffffffff, 0x00000000 },
10539
10540                 /* Mailbox Registers */
10541                 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
10542                         0x00000000, 0x000001ff },
10543                 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
10544                         0x00000000, 0x000001ff },
10545                 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
10546                         0x00000000, 0x000007ff },
10547                 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
10548                         0x00000000, 0x000001ff },
10549
10550                 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
10551         };
10552
10553         is_5705 = is_5750 = 0;
10554         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10555                 is_5705 = 1;
10556                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10557                         is_5750 = 1;
10558         }
10559
10560         for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
10561                 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
10562                         continue;
10563
10564                 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
10565                         continue;
10566
10567                 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10568                     (reg_tbl[i].flags & TG3_FL_NOT_5788))
10569                         continue;
10570
10571                 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
10572                         continue;
10573
10574                 offset = (u32) reg_tbl[i].offset;
10575                 read_mask = reg_tbl[i].read_mask;
10576                 write_mask = reg_tbl[i].write_mask;
10577
10578                 /* Save the original register content */
10579                 save_val = tr32(offset);
10580
10581                 /* Determine the read-only value. */
10582                 read_val = save_val & read_mask;
10583
10584                 /* Write zero to the register, then make sure the read-only bits
10585                  * are not changed and the read/write bits are all zeros.
10586                  */
10587                 tw32(offset, 0);
10588
10589                 val = tr32(offset);
10590
10591                 /* Test the read-only and read/write bits. */
10592                 if (((val & read_mask) != read_val) || (val & write_mask))
10593                         goto out;
10594
10595                 /* Write ones to all the bits defined by RdMask and WrMask, then
10596                  * make sure the read-only bits are not changed and the
10597                  * read/write bits are all ones.
10598                  */
10599                 tw32(offset, read_mask | write_mask);
10600
10601                 val = tr32(offset);
10602
10603                 /* Test the read-only bits. */
10604                 if ((val & read_mask) != read_val)
10605                         goto out;
10606
10607                 /* Test the read/write bits. */
10608                 if ((val & write_mask) != write_mask)
10609                         goto out;
10610
10611                 tw32(offset, save_val);
10612         }
10613
10614         return 0;
10615
10616 out:
10617         if (netif_msg_hw(tp))
10618                 printk(KERN_ERR PFX "Register test failed at offset %x\n",
10619                        offset);
10620         tw32(offset, save_val);
10621         return -EIO;
10622 }
10623
10624 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
10625 {
10626         static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
10627         int i;
10628         u32 j;
10629
10630         for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
10631                 for (j = 0; j < len; j += 4) {
10632                         u32 val;
10633
10634                         tg3_write_mem(tp, offset + j, test_pattern[i]);
10635                         tg3_read_mem(tp, offset + j, &val);
10636                         if (val != test_pattern[i])
10637                                 return -EIO;
10638                 }
10639         }
10640         return 0;
10641 }
10642
10643 static int tg3_test_memory(struct tg3 *tp)
10644 {
10645         static struct mem_entry {
10646                 u32 offset;
10647                 u32 len;
10648         } mem_tbl_570x[] = {
10649                 { 0x00000000, 0x00b50},
10650                 { 0x00002000, 0x1c000},
10651                 { 0xffffffff, 0x00000}
10652         }, mem_tbl_5705[] = {
10653                 { 0x00000100, 0x0000c},
10654                 { 0x00000200, 0x00008},
10655                 { 0x00004000, 0x00800},
10656                 { 0x00006000, 0x01000},
10657                 { 0x00008000, 0x02000},
10658                 { 0x00010000, 0x0e000},
10659                 { 0xffffffff, 0x00000}
10660         }, mem_tbl_5755[] = {
10661                 { 0x00000200, 0x00008},
10662                 { 0x00004000, 0x00800},
10663                 { 0x00006000, 0x00800},
10664                 { 0x00008000, 0x02000},
10665                 { 0x00010000, 0x0c000},
10666                 { 0xffffffff, 0x00000}
10667         }, mem_tbl_5906[] = {
10668                 { 0x00000200, 0x00008},
10669                 { 0x00004000, 0x00400},
10670                 { 0x00006000, 0x00400},
10671                 { 0x00008000, 0x01000},
10672                 { 0x00010000, 0x01000},
10673                 { 0xffffffff, 0x00000}
10674         }, mem_tbl_5717[] = {
10675                 { 0x00000200, 0x00008},
10676                 { 0x00010000, 0x0a000},
10677                 { 0x00020000, 0x13c00},
10678                 { 0xffffffff, 0x00000}
10679         }, mem_tbl_57765[] = {
10680                 { 0x00000200, 0x00008},
10681                 { 0x00004000, 0x00800},
10682                 { 0x00006000, 0x09800},
10683                 { 0x00010000, 0x0a000},
10684                 { 0xffffffff, 0x00000}
10685         };
10686         struct mem_entry *mem_tbl;
10687         int err = 0;
10688         int i;
10689
10690         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
10691                 mem_tbl = mem_tbl_5717;
10692         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
10693                 mem_tbl = mem_tbl_57765;
10694         else if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10695                 mem_tbl = mem_tbl_5755;
10696         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10697                 mem_tbl = mem_tbl_5906;
10698         else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
10699                 mem_tbl = mem_tbl_5705;
10700         else
10701                 mem_tbl = mem_tbl_570x;
10702
10703         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
10704                 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
10705                     mem_tbl[i].len)) != 0)
10706                         break;
10707         }
10708
10709         return err;
10710 }
10711
10712 #define TG3_MAC_LOOPBACK        0
10713 #define TG3_PHY_LOOPBACK        1
10714
10715 static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
10716 {
10717         u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
10718         u32 desc_idx, coal_now;
10719         struct sk_buff *skb, *rx_skb;
10720         u8 *tx_data;
10721         dma_addr_t map;
10722         int num_pkts, tx_len, rx_len, i, err;
10723         struct tg3_rx_buffer_desc *desc;
10724         struct tg3_napi *tnapi, *rnapi;
10725         struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
10726
10727         if (tp->irq_cnt > 1) {
10728                 tnapi = &tp->napi[1];
10729                 rnapi = &tp->napi[1];
10730         } else {
10731                 tnapi = &tp->napi[0];
10732                 rnapi = &tp->napi[0];
10733         }
10734         coal_now = tnapi->coal_now | rnapi->coal_now;
10735
10736         if (loopback_mode == TG3_MAC_LOOPBACK) {
10737                 /* HW errata - mac loopback fails in some cases on 5780.
10738                  * Normal traffic and PHY loopback are not affected by
10739                  * errata.
10740                  */
10741                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
10742                         return 0;
10743
10744                 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
10745                            MAC_MODE_PORT_INT_LPBACK;
10746                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10747                         mac_mode |= MAC_MODE_LINK_POLARITY;
10748                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
10749                         mac_mode |= MAC_MODE_PORT_MODE_MII;
10750                 else
10751                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
10752                 tw32(MAC_MODE, mac_mode);
10753         } else if (loopback_mode == TG3_PHY_LOOPBACK) {
10754                 u32 val;
10755
10756                 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10757                         tg3_phy_fet_toggle_apd(tp, false);
10758                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
10759                 } else
10760                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
10761
10762                 tg3_phy_toggle_automdix(tp, 0);
10763
10764                 tg3_writephy(tp, MII_BMCR, val);
10765                 udelay(40);
10766
10767                 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
10768                 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10769                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10770                                 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x1800);
10771                         mac_mode |= MAC_MODE_PORT_MODE_MII;
10772                 } else
10773                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
10774
10775                 /* reset to prevent losing 1st rx packet intermittently */
10776                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
10777                         tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10778                         udelay(10);
10779                         tw32_f(MAC_RX_MODE, tp->rx_mode);
10780                 }
10781                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
10782                         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)
10783                                 mac_mode &= ~MAC_MODE_LINK_POLARITY;
10784                         else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411)
10785                                 mac_mode |= MAC_MODE_LINK_POLARITY;
10786                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
10787                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
10788                 }
10789                 tw32(MAC_MODE, mac_mode);
10790         }
10791         else
10792                 return -EINVAL;
10793
10794         err = -EIO;
10795
10796         tx_len = 1514;
10797         skb = netdev_alloc_skb(tp->dev, tx_len);
10798         if (!skb)
10799                 return -ENOMEM;
10800
10801         tx_data = skb_put(skb, tx_len);
10802         memcpy(tx_data, tp->dev->dev_addr, 6);
10803         memset(tx_data + 6, 0x0, 8);
10804
10805         tw32(MAC_RX_MTU_SIZE, tx_len + 4);
10806
10807         for (i = 14; i < tx_len; i++)
10808                 tx_data[i] = (u8) (i & 0xff);
10809
10810         map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
10811         if (pci_dma_mapping_error(tp->pdev, map)) {
10812                 dev_kfree_skb(skb);
10813                 return -EIO;
10814         }
10815
10816         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10817                rnapi->coal_now);
10818
10819         udelay(10);
10820
10821         rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
10822
10823         num_pkts = 0;
10824
10825         tg3_set_txd(tnapi, tnapi->tx_prod, map, tx_len, 0, 1);
10826
10827         tnapi->tx_prod++;
10828         num_pkts++;
10829
10830         tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
10831         tr32_mailbox(tnapi->prodmbox);
10832
10833         udelay(10);
10834
10835         /* 350 usec to allow enough time on some 10/100 Mbps devices.  */
10836         for (i = 0; i < 35; i++) {
10837                 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10838                        coal_now);
10839
10840                 udelay(10);
10841
10842                 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
10843                 rx_idx = rnapi->hw_status->idx[0].rx_producer;
10844                 if ((tx_idx == tnapi->tx_prod) &&
10845                     (rx_idx == (rx_start_idx + num_pkts)))
10846                         break;
10847         }
10848
10849         pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
10850         dev_kfree_skb(skb);
10851
10852         if (tx_idx != tnapi->tx_prod)
10853                 goto out;
10854
10855         if (rx_idx != rx_start_idx + num_pkts)
10856                 goto out;
10857
10858         desc = &rnapi->rx_rcb[rx_start_idx];
10859         desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
10860         opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
10861         if (opaque_key != RXD_OPAQUE_RING_STD)
10862                 goto out;
10863
10864         if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
10865             (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
10866                 goto out;
10867
10868         rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
10869         if (rx_len != tx_len)
10870                 goto out;
10871
10872         rx_skb = tpr->rx_std_buffers[desc_idx].skb;
10873
10874         map = pci_unmap_addr(&tpr->rx_std_buffers[desc_idx], mapping);
10875         pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
10876
10877         for (i = 14; i < tx_len; i++) {
10878                 if (*(rx_skb->data + i) != (u8) (i & 0xff))
10879                         goto out;
10880         }
10881         err = 0;
10882
10883         /* tg3_free_rings will unmap and free the rx_skb */
10884 out:
10885         return err;
10886 }
10887
10888 #define TG3_MAC_LOOPBACK_FAILED         1
10889 #define TG3_PHY_LOOPBACK_FAILED         2
10890 #define TG3_LOOPBACK_FAILED             (TG3_MAC_LOOPBACK_FAILED |      \
10891                                          TG3_PHY_LOOPBACK_FAILED)
10892
10893 static int tg3_test_loopback(struct tg3 *tp)
10894 {
10895         int err = 0;
10896         u32 cpmuctrl = 0;
10897
10898         if (!netif_running(tp->dev))
10899                 return TG3_LOOPBACK_FAILED;
10900
10901         err = tg3_reset_hw(tp, 1);
10902         if (err)
10903                 return TG3_LOOPBACK_FAILED;
10904
10905         /* Turn off gphy autopowerdown. */
10906         if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10907                 tg3_phy_toggle_apd(tp, false);
10908
10909         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
10910                 int i;
10911                 u32 status;
10912
10913                 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
10914
10915                 /* Wait for up to 40 microseconds to acquire lock. */
10916                 for (i = 0; i < 4; i++) {
10917                         status = tr32(TG3_CPMU_MUTEX_GNT);
10918                         if (status == CPMU_MUTEX_GNT_DRIVER)
10919                                 break;
10920                         udelay(10);
10921                 }
10922
10923                 if (status != CPMU_MUTEX_GNT_DRIVER)
10924                         return TG3_LOOPBACK_FAILED;
10925
10926                 /* Turn off link-based power management. */
10927                 cpmuctrl = tr32(TG3_CPMU_CTRL);
10928                 tw32(TG3_CPMU_CTRL,
10929                      cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
10930                                   CPMU_CTRL_LINK_AWARE_MODE));
10931         }
10932
10933         if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
10934                 err |= TG3_MAC_LOOPBACK_FAILED;
10935
10936         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
10937                 tw32(TG3_CPMU_CTRL, cpmuctrl);
10938
10939                 /* Release the mutex */
10940                 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
10941         }
10942
10943         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
10944             !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
10945                 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
10946                         err |= TG3_PHY_LOOPBACK_FAILED;
10947         }
10948
10949         /* Re-enable gphy autopowerdown. */
10950         if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10951                 tg3_phy_toggle_apd(tp, true);
10952
10953         return err;
10954 }
10955
10956 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
10957                           u64 *data)
10958 {
10959         struct tg3 *tp = netdev_priv(dev);
10960
10961         if (tp->link_config.phy_is_low_power)
10962                 tg3_set_power_state(tp, PCI_D0);
10963
10964         memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
10965
10966         if (tg3_test_nvram(tp) != 0) {
10967                 etest->flags |= ETH_TEST_FL_FAILED;
10968                 data[0] = 1;
10969         }
10970         if (tg3_test_link(tp) != 0) {
10971                 etest->flags |= ETH_TEST_FL_FAILED;
10972                 data[1] = 1;
10973         }
10974         if (etest->flags & ETH_TEST_FL_OFFLINE) {
10975                 int err, err2 = 0, irq_sync = 0;
10976
10977                 if (netif_running(dev)) {
10978                         tg3_phy_stop(tp);
10979                         tg3_netif_stop(tp);
10980                         irq_sync = 1;
10981                 }
10982
10983                 tg3_full_lock(tp, irq_sync);
10984
10985                 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
10986                 err = tg3_nvram_lock(tp);
10987                 tg3_halt_cpu(tp, RX_CPU_BASE);
10988                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10989                         tg3_halt_cpu(tp, TX_CPU_BASE);
10990                 if (!err)
10991                         tg3_nvram_unlock(tp);
10992
10993                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
10994                         tg3_phy_reset(tp);
10995
10996                 if (tg3_test_registers(tp) != 0) {
10997                         etest->flags |= ETH_TEST_FL_FAILED;
10998                         data[2] = 1;
10999                 }
11000                 if (tg3_test_memory(tp) != 0) {
11001                         etest->flags |= ETH_TEST_FL_FAILED;
11002                         data[3] = 1;
11003                 }
11004                 if ((data[4] = tg3_test_loopback(tp)) != 0)
11005                         etest->flags |= ETH_TEST_FL_FAILED;
11006
11007                 tg3_full_unlock(tp);
11008
11009                 if (tg3_test_interrupt(tp) != 0) {
11010                         etest->flags |= ETH_TEST_FL_FAILED;
11011                         data[5] = 1;
11012                 }
11013
11014                 tg3_full_lock(tp, 0);
11015
11016                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11017                 if (netif_running(dev)) {
11018                         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
11019                         err2 = tg3_restart_hw(tp, 1);
11020                         if (!err2)
11021                                 tg3_netif_start(tp);
11022                 }
11023
11024                 tg3_full_unlock(tp);
11025
11026                 if (irq_sync && !err2)
11027                         tg3_phy_start(tp);
11028         }
11029         if (tp->link_config.phy_is_low_power)
11030                 tg3_set_power_state(tp, PCI_D3hot);
11031
11032 }
11033
11034 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
11035 {
11036         struct mii_ioctl_data *data = if_mii(ifr);
11037         struct tg3 *tp = netdev_priv(dev);
11038         int err;
11039
11040         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
11041                 struct phy_device *phydev;
11042                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
11043                         return -EAGAIN;
11044                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
11045                 return phy_mii_ioctl(phydev, data, cmd);
11046         }
11047
11048         switch(cmd) {
11049         case SIOCGMIIPHY:
11050                 data->phy_id = tp->phy_addr;
11051
11052                 /* fallthru */
11053         case SIOCGMIIREG: {
11054                 u32 mii_regval;
11055
11056                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
11057                         break;                  /* We have no PHY */
11058
11059                 if (tp->link_config.phy_is_low_power)
11060                         return -EAGAIN;
11061
11062                 spin_lock_bh(&tp->lock);
11063                 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
11064                 spin_unlock_bh(&tp->lock);
11065
11066                 data->val_out = mii_regval;
11067
11068                 return err;
11069         }
11070
11071         case SIOCSMIIREG:
11072                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
11073                         break;                  /* We have no PHY */
11074
11075                 if (tp->link_config.phy_is_low_power)
11076                         return -EAGAIN;
11077
11078                 spin_lock_bh(&tp->lock);
11079                 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
11080                 spin_unlock_bh(&tp->lock);
11081
11082                 return err;
11083
11084         default:
11085                 /* do nothing */
11086                 break;
11087         }
11088         return -EOPNOTSUPP;
11089 }
11090
11091 #if TG3_VLAN_TAG_USED
11092 static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
11093 {
11094         struct tg3 *tp = netdev_priv(dev);
11095
11096         if (!netif_running(dev)) {
11097                 tp->vlgrp = grp;
11098                 return;
11099         }
11100
11101         tg3_netif_stop(tp);
11102
11103         tg3_full_lock(tp, 0);
11104
11105         tp->vlgrp = grp;
11106
11107         /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
11108         __tg3_set_rx_mode(dev);
11109
11110         tg3_netif_start(tp);
11111
11112         tg3_full_unlock(tp);
11113 }
11114 #endif
11115
11116 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11117 {
11118         struct tg3 *tp = netdev_priv(dev);
11119
11120         memcpy(ec, &tp->coal, sizeof(*ec));
11121         return 0;
11122 }
11123
11124 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11125 {
11126         struct tg3 *tp = netdev_priv(dev);
11127         u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
11128         u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
11129
11130         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
11131                 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
11132                 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
11133                 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
11134                 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
11135         }
11136
11137         if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
11138             (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
11139             (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
11140             (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
11141             (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
11142             (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
11143             (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
11144             (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
11145             (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
11146             (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
11147                 return -EINVAL;
11148
11149         /* No rx interrupts will be generated if both are zero */
11150         if ((ec->rx_coalesce_usecs == 0) &&
11151             (ec->rx_max_coalesced_frames == 0))
11152                 return -EINVAL;
11153
11154         /* No tx interrupts will be generated if both are zero */
11155         if ((ec->tx_coalesce_usecs == 0) &&
11156             (ec->tx_max_coalesced_frames == 0))
11157                 return -EINVAL;
11158
11159         /* Only copy relevant parameters, ignore all others. */
11160         tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
11161         tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
11162         tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
11163         tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
11164         tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
11165         tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
11166         tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
11167         tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
11168         tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
11169
11170         if (netif_running(dev)) {
11171                 tg3_full_lock(tp, 0);
11172                 __tg3_set_coalesce(tp, &tp->coal);
11173                 tg3_full_unlock(tp);
11174         }
11175         return 0;
11176 }
11177
11178 static const struct ethtool_ops tg3_ethtool_ops = {
11179         .get_settings           = tg3_get_settings,
11180         .set_settings           = tg3_set_settings,
11181         .get_drvinfo            = tg3_get_drvinfo,
11182         .get_regs_len           = tg3_get_regs_len,
11183         .get_regs               = tg3_get_regs,
11184         .get_wol                = tg3_get_wol,
11185         .set_wol                = tg3_set_wol,
11186         .get_msglevel           = tg3_get_msglevel,
11187         .set_msglevel           = tg3_set_msglevel,
11188         .nway_reset             = tg3_nway_reset,
11189         .get_link               = ethtool_op_get_link,
11190         .get_eeprom_len         = tg3_get_eeprom_len,
11191         .get_eeprom             = tg3_get_eeprom,
11192         .set_eeprom             = tg3_set_eeprom,
11193         .get_ringparam          = tg3_get_ringparam,
11194         .set_ringparam          = tg3_set_ringparam,
11195         .get_pauseparam         = tg3_get_pauseparam,
11196         .set_pauseparam         = tg3_set_pauseparam,
11197         .get_rx_csum            = tg3_get_rx_csum,
11198         .set_rx_csum            = tg3_set_rx_csum,
11199         .set_tx_csum            = tg3_set_tx_csum,
11200         .set_sg                 = ethtool_op_set_sg,
11201         .set_tso                = tg3_set_tso,
11202         .self_test              = tg3_self_test,
11203         .get_strings            = tg3_get_strings,
11204         .phys_id                = tg3_phys_id,
11205         .get_ethtool_stats      = tg3_get_ethtool_stats,
11206         .get_coalesce           = tg3_get_coalesce,
11207         .set_coalesce           = tg3_set_coalesce,
11208         .get_sset_count         = tg3_get_sset_count,
11209 };
11210
11211 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
11212 {
11213         u32 cursize, val, magic;
11214
11215         tp->nvram_size = EEPROM_CHIP_SIZE;
11216
11217         if (tg3_nvram_read(tp, 0, &magic) != 0)
11218                 return;
11219
11220         if ((magic != TG3_EEPROM_MAGIC) &&
11221             ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
11222             ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
11223                 return;
11224
11225         /*
11226          * Size the chip by reading offsets at increasing powers of two.
11227          * When we encounter our validation signature, we know the addressing
11228          * has wrapped around, and thus have our chip size.
11229          */
11230         cursize = 0x10;
11231
11232         while (cursize < tp->nvram_size) {
11233                 if (tg3_nvram_read(tp, cursize, &val) != 0)
11234                         return;
11235
11236                 if (val == magic)
11237                         break;
11238
11239                 cursize <<= 1;
11240         }
11241
11242         tp->nvram_size = cursize;
11243 }
11244
11245 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
11246 {
11247         u32 val;
11248
11249         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
11250             tg3_nvram_read(tp, 0, &val) != 0)
11251                 return;
11252
11253         /* Selfboot format */
11254         if (val != TG3_EEPROM_MAGIC) {
11255                 tg3_get_eeprom_size(tp);
11256                 return;
11257         }
11258
11259         if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
11260                 if (val != 0) {
11261                         /* This is confusing.  We want to operate on the
11262                          * 16-bit value at offset 0xf2.  The tg3_nvram_read()
11263                          * call will read from NVRAM and byteswap the data
11264                          * according to the byteswapping settings for all
11265                          * other register accesses.  This ensures the data we
11266                          * want will always reside in the lower 16-bits.
11267                          * However, the data in NVRAM is in LE format, which
11268                          * means the data from the NVRAM read will always be
11269                          * opposite the endianness of the CPU.  The 16-bit
11270                          * byteswap then brings the data to CPU endianness.
11271                          */
11272                         tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
11273                         return;
11274                 }
11275         }
11276         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11277 }
11278
11279 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
11280 {
11281         u32 nvcfg1;
11282
11283         nvcfg1 = tr32(NVRAM_CFG1);
11284         if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
11285                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11286         } else {
11287                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11288                 tw32(NVRAM_CFG1, nvcfg1);
11289         }
11290
11291         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
11292             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
11293                 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
11294                 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
11295                         tp->nvram_jedecnum = JEDEC_ATMEL;
11296                         tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11297                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11298                         break;
11299                 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
11300                         tp->nvram_jedecnum = JEDEC_ATMEL;
11301                         tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
11302                         break;
11303                 case FLASH_VENDOR_ATMEL_EEPROM:
11304                         tp->nvram_jedecnum = JEDEC_ATMEL;
11305                         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11306                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11307                         break;
11308                 case FLASH_VENDOR_ST:
11309                         tp->nvram_jedecnum = JEDEC_ST;
11310                         tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
11311                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11312                         break;
11313                 case FLASH_VENDOR_SAIFUN:
11314                         tp->nvram_jedecnum = JEDEC_SAIFUN;
11315                         tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
11316                         break;
11317                 case FLASH_VENDOR_SST_SMALL:
11318                 case FLASH_VENDOR_SST_LARGE:
11319                         tp->nvram_jedecnum = JEDEC_SST;
11320                         tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
11321                         break;
11322                 }
11323         } else {
11324                 tp->nvram_jedecnum = JEDEC_ATMEL;
11325                 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11326                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11327         }
11328 }
11329
11330 static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
11331 {
11332         switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
11333         case FLASH_5752PAGE_SIZE_256:
11334                 tp->nvram_pagesize = 256;
11335                 break;
11336         case FLASH_5752PAGE_SIZE_512:
11337                 tp->nvram_pagesize = 512;
11338                 break;
11339         case FLASH_5752PAGE_SIZE_1K:
11340                 tp->nvram_pagesize = 1024;
11341                 break;
11342         case FLASH_5752PAGE_SIZE_2K:
11343                 tp->nvram_pagesize = 2048;
11344                 break;
11345         case FLASH_5752PAGE_SIZE_4K:
11346                 tp->nvram_pagesize = 4096;
11347                 break;
11348         case FLASH_5752PAGE_SIZE_264:
11349                 tp->nvram_pagesize = 264;
11350                 break;
11351         case FLASH_5752PAGE_SIZE_528:
11352                 tp->nvram_pagesize = 528;
11353                 break;
11354         }
11355 }
11356
11357 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
11358 {
11359         u32 nvcfg1;
11360
11361         nvcfg1 = tr32(NVRAM_CFG1);
11362
11363         /* NVRAM protection for TPM */
11364         if (nvcfg1 & (1 << 27))
11365                 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11366
11367         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11368         case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
11369         case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
11370                 tp->nvram_jedecnum = JEDEC_ATMEL;
11371                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11372                 break;
11373         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11374                 tp->nvram_jedecnum = JEDEC_ATMEL;
11375                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11376                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11377                 break;
11378         case FLASH_5752VENDOR_ST_M45PE10:
11379         case FLASH_5752VENDOR_ST_M45PE20:
11380         case FLASH_5752VENDOR_ST_M45PE40:
11381                 tp->nvram_jedecnum = JEDEC_ST;
11382                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11383                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11384                 break;
11385         }
11386
11387         if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
11388                 tg3_nvram_get_pagesize(tp, nvcfg1);
11389         } else {
11390                 /* For eeprom, set pagesize to maximum eeprom size */
11391                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11392
11393                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11394                 tw32(NVRAM_CFG1, nvcfg1);
11395         }
11396 }
11397
11398 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
11399 {
11400         u32 nvcfg1, protect = 0;
11401
11402         nvcfg1 = tr32(NVRAM_CFG1);
11403
11404         /* NVRAM protection for TPM */
11405         if (nvcfg1 & (1 << 27)) {
11406                 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11407                 protect = 1;
11408         }
11409
11410         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11411         switch (nvcfg1) {
11412         case FLASH_5755VENDOR_ATMEL_FLASH_1:
11413         case FLASH_5755VENDOR_ATMEL_FLASH_2:
11414         case FLASH_5755VENDOR_ATMEL_FLASH_3:
11415         case FLASH_5755VENDOR_ATMEL_FLASH_5:
11416                 tp->nvram_jedecnum = JEDEC_ATMEL;
11417                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11418                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11419                 tp->nvram_pagesize = 264;
11420                 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
11421                     nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
11422                         tp->nvram_size = (protect ? 0x3e200 :
11423                                           TG3_NVRAM_SIZE_512KB);
11424                 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
11425                         tp->nvram_size = (protect ? 0x1f200 :
11426                                           TG3_NVRAM_SIZE_256KB);
11427                 else
11428                         tp->nvram_size = (protect ? 0x1f200 :
11429                                           TG3_NVRAM_SIZE_128KB);
11430                 break;
11431         case FLASH_5752VENDOR_ST_M45PE10:
11432         case FLASH_5752VENDOR_ST_M45PE20:
11433         case FLASH_5752VENDOR_ST_M45PE40:
11434                 tp->nvram_jedecnum = JEDEC_ST;
11435                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11436                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11437                 tp->nvram_pagesize = 256;
11438                 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
11439                         tp->nvram_size = (protect ?
11440                                           TG3_NVRAM_SIZE_64KB :
11441                                           TG3_NVRAM_SIZE_128KB);
11442                 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
11443                         tp->nvram_size = (protect ?
11444                                           TG3_NVRAM_SIZE_64KB :
11445                                           TG3_NVRAM_SIZE_256KB);
11446                 else
11447                         tp->nvram_size = (protect ?
11448                                           TG3_NVRAM_SIZE_128KB :
11449                                           TG3_NVRAM_SIZE_512KB);
11450                 break;
11451         }
11452 }
11453
11454 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
11455 {
11456         u32 nvcfg1;
11457
11458         nvcfg1 = tr32(NVRAM_CFG1);
11459
11460         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11461         case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
11462         case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11463         case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
11464         case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11465                 tp->nvram_jedecnum = JEDEC_ATMEL;
11466                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11467                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11468
11469                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11470                 tw32(NVRAM_CFG1, nvcfg1);
11471                 break;
11472         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11473         case FLASH_5755VENDOR_ATMEL_FLASH_1:
11474         case FLASH_5755VENDOR_ATMEL_FLASH_2:
11475         case FLASH_5755VENDOR_ATMEL_FLASH_3:
11476                 tp->nvram_jedecnum = JEDEC_ATMEL;
11477                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11478                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11479                 tp->nvram_pagesize = 264;
11480                 break;
11481         case FLASH_5752VENDOR_ST_M45PE10:
11482         case FLASH_5752VENDOR_ST_M45PE20:
11483         case FLASH_5752VENDOR_ST_M45PE40:
11484                 tp->nvram_jedecnum = JEDEC_ST;
11485                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11486                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11487                 tp->nvram_pagesize = 256;
11488                 break;
11489         }
11490 }
11491
11492 static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
11493 {
11494         u32 nvcfg1, protect = 0;
11495
11496         nvcfg1 = tr32(NVRAM_CFG1);
11497
11498         /* NVRAM protection for TPM */
11499         if (nvcfg1 & (1 << 27)) {
11500                 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11501                 protect = 1;
11502         }
11503
11504         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11505         switch (nvcfg1) {
11506         case FLASH_5761VENDOR_ATMEL_ADB021D:
11507         case FLASH_5761VENDOR_ATMEL_ADB041D:
11508         case FLASH_5761VENDOR_ATMEL_ADB081D:
11509         case FLASH_5761VENDOR_ATMEL_ADB161D:
11510         case FLASH_5761VENDOR_ATMEL_MDB021D:
11511         case FLASH_5761VENDOR_ATMEL_MDB041D:
11512         case FLASH_5761VENDOR_ATMEL_MDB081D:
11513         case FLASH_5761VENDOR_ATMEL_MDB161D:
11514                 tp->nvram_jedecnum = JEDEC_ATMEL;
11515                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11516                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11517                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11518                 tp->nvram_pagesize = 256;
11519                 break;
11520         case FLASH_5761VENDOR_ST_A_M45PE20:
11521         case FLASH_5761VENDOR_ST_A_M45PE40:
11522         case FLASH_5761VENDOR_ST_A_M45PE80:
11523         case FLASH_5761VENDOR_ST_A_M45PE16:
11524         case FLASH_5761VENDOR_ST_M_M45PE20:
11525         case FLASH_5761VENDOR_ST_M_M45PE40:
11526         case FLASH_5761VENDOR_ST_M_M45PE80:
11527         case FLASH_5761VENDOR_ST_M_M45PE16:
11528                 tp->nvram_jedecnum = JEDEC_ST;
11529                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11530                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11531                 tp->nvram_pagesize = 256;
11532                 break;
11533         }
11534
11535         if (protect) {
11536                 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
11537         } else {
11538                 switch (nvcfg1) {
11539                 case FLASH_5761VENDOR_ATMEL_ADB161D:
11540                 case FLASH_5761VENDOR_ATMEL_MDB161D:
11541                 case FLASH_5761VENDOR_ST_A_M45PE16:
11542                 case FLASH_5761VENDOR_ST_M_M45PE16:
11543                         tp->nvram_size = TG3_NVRAM_SIZE_2MB;
11544                         break;
11545                 case FLASH_5761VENDOR_ATMEL_ADB081D:
11546                 case FLASH_5761VENDOR_ATMEL_MDB081D:
11547                 case FLASH_5761VENDOR_ST_A_M45PE80:
11548                 case FLASH_5761VENDOR_ST_M_M45PE80:
11549                         tp->nvram_size = TG3_NVRAM_SIZE_1MB;
11550                         break;
11551                 case FLASH_5761VENDOR_ATMEL_ADB041D:
11552                 case FLASH_5761VENDOR_ATMEL_MDB041D:
11553                 case FLASH_5761VENDOR_ST_A_M45PE40:
11554                 case FLASH_5761VENDOR_ST_M_M45PE40:
11555                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11556                         break;
11557                 case FLASH_5761VENDOR_ATMEL_ADB021D:
11558                 case FLASH_5761VENDOR_ATMEL_MDB021D:
11559                 case FLASH_5761VENDOR_ST_A_M45PE20:
11560                 case FLASH_5761VENDOR_ST_M_M45PE20:
11561                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11562                         break;
11563                 }
11564         }
11565 }
11566
11567 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
11568 {
11569         tp->nvram_jedecnum = JEDEC_ATMEL;
11570         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11571         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11572 }
11573
11574 static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
11575 {
11576         u32 nvcfg1;
11577
11578         nvcfg1 = tr32(NVRAM_CFG1);
11579
11580         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11581         case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11582         case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11583                 tp->nvram_jedecnum = JEDEC_ATMEL;
11584                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11585                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11586
11587                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11588                 tw32(NVRAM_CFG1, nvcfg1);
11589                 return;
11590         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11591         case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11592         case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11593         case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11594         case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11595         case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11596         case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11597                 tp->nvram_jedecnum = JEDEC_ATMEL;
11598                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11599                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11600
11601                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11602                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11603                 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11604                 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11605                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11606                         break;
11607                 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11608                 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11609                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11610                         break;
11611                 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11612                 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11613                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11614                         break;
11615                 }
11616                 break;
11617         case FLASH_5752VENDOR_ST_M45PE10:
11618         case FLASH_5752VENDOR_ST_M45PE20:
11619         case FLASH_5752VENDOR_ST_M45PE40:
11620                 tp->nvram_jedecnum = JEDEC_ST;
11621                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11622                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11623
11624                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11625                 case FLASH_5752VENDOR_ST_M45PE10:
11626                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11627                         break;
11628                 case FLASH_5752VENDOR_ST_M45PE20:
11629                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11630                         break;
11631                 case FLASH_5752VENDOR_ST_M45PE40:
11632                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11633                         break;
11634                 }
11635                 break;
11636         default:
11637                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11638                 return;
11639         }
11640
11641         tg3_nvram_get_pagesize(tp, nvcfg1);
11642         if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11643                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11644 }
11645
11646
11647 static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp)
11648 {
11649         u32 nvcfg1;
11650
11651         nvcfg1 = tr32(NVRAM_CFG1);
11652
11653         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11654         case FLASH_5717VENDOR_ATMEL_EEPROM:
11655         case FLASH_5717VENDOR_MICRO_EEPROM:
11656                 tp->nvram_jedecnum = JEDEC_ATMEL;
11657                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11658                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11659
11660                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11661                 tw32(NVRAM_CFG1, nvcfg1);
11662                 return;
11663         case FLASH_5717VENDOR_ATMEL_MDB011D:
11664         case FLASH_5717VENDOR_ATMEL_ADB011B:
11665         case FLASH_5717VENDOR_ATMEL_ADB011D:
11666         case FLASH_5717VENDOR_ATMEL_MDB021D:
11667         case FLASH_5717VENDOR_ATMEL_ADB021B:
11668         case FLASH_5717VENDOR_ATMEL_ADB021D:
11669         case FLASH_5717VENDOR_ATMEL_45USPT:
11670                 tp->nvram_jedecnum = JEDEC_ATMEL;
11671                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11672                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11673
11674                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11675                 case FLASH_5717VENDOR_ATMEL_MDB021D:
11676                 case FLASH_5717VENDOR_ATMEL_ADB021B:
11677                 case FLASH_5717VENDOR_ATMEL_ADB021D:
11678                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11679                         break;
11680                 default:
11681                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11682                         break;
11683                 }
11684                 break;
11685         case FLASH_5717VENDOR_ST_M_M25PE10:
11686         case FLASH_5717VENDOR_ST_A_M25PE10:
11687         case FLASH_5717VENDOR_ST_M_M45PE10:
11688         case FLASH_5717VENDOR_ST_A_M45PE10:
11689         case FLASH_5717VENDOR_ST_M_M25PE20:
11690         case FLASH_5717VENDOR_ST_A_M25PE20:
11691         case FLASH_5717VENDOR_ST_M_M45PE20:
11692         case FLASH_5717VENDOR_ST_A_M45PE20:
11693         case FLASH_5717VENDOR_ST_25USPT:
11694         case FLASH_5717VENDOR_ST_45USPT:
11695                 tp->nvram_jedecnum = JEDEC_ST;
11696                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11697                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11698
11699                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11700                 case FLASH_5717VENDOR_ST_M_M25PE20:
11701                 case FLASH_5717VENDOR_ST_A_M25PE20:
11702                 case FLASH_5717VENDOR_ST_M_M45PE20:
11703                 case FLASH_5717VENDOR_ST_A_M45PE20:
11704                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11705                         break;
11706                 default:
11707                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11708                         break;
11709                 }
11710                 break;
11711         default:
11712                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11713                 return;
11714         }
11715
11716         tg3_nvram_get_pagesize(tp, nvcfg1);
11717         if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11718                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11719 }
11720
11721 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
11722 static void __devinit tg3_nvram_init(struct tg3 *tp)
11723 {
11724         tw32_f(GRC_EEPROM_ADDR,
11725              (EEPROM_ADDR_FSM_RESET |
11726               (EEPROM_DEFAULT_CLOCK_PERIOD <<
11727                EEPROM_ADDR_CLKPERD_SHIFT)));
11728
11729         msleep(1);
11730
11731         /* Enable seeprom accesses. */
11732         tw32_f(GRC_LOCAL_CTRL,
11733              tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
11734         udelay(100);
11735
11736         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11737             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
11738                 tp->tg3_flags |= TG3_FLAG_NVRAM;
11739
11740                 if (tg3_nvram_lock(tp)) {
11741                         printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
11742                                "tg3_nvram_init failed.\n", tp->dev->name);
11743                         return;
11744                 }
11745                 tg3_enable_nvram_access(tp);
11746
11747                 tp->nvram_size = 0;
11748
11749                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
11750                         tg3_get_5752_nvram_info(tp);
11751                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
11752                         tg3_get_5755_nvram_info(tp);
11753                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
11754                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11755                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11756                         tg3_get_5787_nvram_info(tp);
11757                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
11758                         tg3_get_5761_nvram_info(tp);
11759                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11760                         tg3_get_5906_nvram_info(tp);
11761                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
11762                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
11763                         tg3_get_57780_nvram_info(tp);
11764                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
11765                         tg3_get_5717_nvram_info(tp);
11766                 else
11767                         tg3_get_nvram_info(tp);
11768
11769                 if (tp->nvram_size == 0)
11770                         tg3_get_nvram_size(tp);
11771
11772                 tg3_disable_nvram_access(tp);
11773                 tg3_nvram_unlock(tp);
11774
11775         } else {
11776                 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
11777
11778                 tg3_get_eeprom_size(tp);
11779         }
11780 }
11781
11782 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
11783                                     u32 offset, u32 len, u8 *buf)
11784 {
11785         int i, j, rc = 0;
11786         u32 val;
11787
11788         for (i = 0; i < len; i += 4) {
11789                 u32 addr;
11790                 __be32 data;
11791
11792                 addr = offset + i;
11793
11794                 memcpy(&data, buf + i, 4);
11795
11796                 /*
11797                  * The SEEPROM interface expects the data to always be opposite
11798                  * the native endian format.  We accomplish this by reversing
11799                  * all the operations that would have been performed on the
11800                  * data from a call to tg3_nvram_read_be32().
11801                  */
11802                 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
11803
11804                 val = tr32(GRC_EEPROM_ADDR);
11805                 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
11806
11807                 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
11808                         EEPROM_ADDR_READ);
11809                 tw32(GRC_EEPROM_ADDR, val |
11810                         (0 << EEPROM_ADDR_DEVID_SHIFT) |
11811                         (addr & EEPROM_ADDR_ADDR_MASK) |
11812                         EEPROM_ADDR_START |
11813                         EEPROM_ADDR_WRITE);
11814
11815                 for (j = 0; j < 1000; j++) {
11816                         val = tr32(GRC_EEPROM_ADDR);
11817
11818                         if (val & EEPROM_ADDR_COMPLETE)
11819                                 break;
11820                         msleep(1);
11821                 }
11822                 if (!(val & EEPROM_ADDR_COMPLETE)) {
11823                         rc = -EBUSY;
11824                         break;
11825                 }
11826         }
11827
11828         return rc;
11829 }
11830
11831 /* offset and length are dword aligned */
11832 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
11833                 u8 *buf)
11834 {
11835         int ret = 0;
11836         u32 pagesize = tp->nvram_pagesize;
11837         u32 pagemask = pagesize - 1;
11838         u32 nvram_cmd;
11839         u8 *tmp;
11840
11841         tmp = kmalloc(pagesize, GFP_KERNEL);
11842         if (tmp == NULL)
11843                 return -ENOMEM;
11844
11845         while (len) {
11846                 int j;
11847                 u32 phy_addr, page_off, size;
11848
11849                 phy_addr = offset & ~pagemask;
11850
11851                 for (j = 0; j < pagesize; j += 4) {
11852                         ret = tg3_nvram_read_be32(tp, phy_addr + j,
11853                                                   (__be32 *) (tmp + j));
11854                         if (ret)
11855                                 break;
11856                 }
11857                 if (ret)
11858                         break;
11859
11860                 page_off = offset & pagemask;
11861                 size = pagesize;
11862                 if (len < size)
11863                         size = len;
11864
11865                 len -= size;
11866
11867                 memcpy(tmp + page_off, buf, size);
11868
11869                 offset = offset + (pagesize - page_off);
11870
11871                 tg3_enable_nvram_access(tp);
11872
11873                 /*
11874                  * Before we can erase the flash page, we need
11875                  * to issue a special "write enable" command.
11876                  */
11877                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11878
11879                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11880                         break;
11881
11882                 /* Erase the target page */
11883                 tw32(NVRAM_ADDR, phy_addr);
11884
11885                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
11886                         NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
11887
11888                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11889                         break;
11890
11891                 /* Issue another write enable to start the write. */
11892                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11893
11894                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11895                         break;
11896
11897                 for (j = 0; j < pagesize; j += 4) {
11898                         __be32 data;
11899
11900                         data = *((__be32 *) (tmp + j));
11901
11902                         tw32(NVRAM_WRDATA, be32_to_cpu(data));
11903
11904                         tw32(NVRAM_ADDR, phy_addr + j);
11905
11906                         nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
11907                                 NVRAM_CMD_WR;
11908
11909                         if (j == 0)
11910                                 nvram_cmd |= NVRAM_CMD_FIRST;
11911                         else if (j == (pagesize - 4))
11912                                 nvram_cmd |= NVRAM_CMD_LAST;
11913
11914                         if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11915                                 break;
11916                 }
11917                 if (ret)
11918                         break;
11919         }
11920
11921         nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11922         tg3_nvram_exec_cmd(tp, nvram_cmd);
11923
11924         kfree(tmp);
11925
11926         return ret;
11927 }
11928
11929 /* offset and length are dword aligned */
11930 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
11931                 u8 *buf)
11932 {
11933         int i, ret = 0;
11934
11935         for (i = 0; i < len; i += 4, offset += 4) {
11936                 u32 page_off, phy_addr, nvram_cmd;
11937                 __be32 data;
11938
11939                 memcpy(&data, buf + i, 4);
11940                 tw32(NVRAM_WRDATA, be32_to_cpu(data));
11941
11942                 page_off = offset % tp->nvram_pagesize;
11943
11944                 phy_addr = tg3_nvram_phys_addr(tp, offset);
11945
11946                 tw32(NVRAM_ADDR, phy_addr);
11947
11948                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
11949
11950                 if ((page_off == 0) || (i == 0))
11951                         nvram_cmd |= NVRAM_CMD_FIRST;
11952                 if (page_off == (tp->nvram_pagesize - 4))
11953                         nvram_cmd |= NVRAM_CMD_LAST;
11954
11955                 if (i == (len - 4))
11956                         nvram_cmd |= NVRAM_CMD_LAST;
11957
11958                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
11959                     !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
11960                     (tp->nvram_jedecnum == JEDEC_ST) &&
11961                     (nvram_cmd & NVRAM_CMD_FIRST)) {
11962
11963                         if ((ret = tg3_nvram_exec_cmd(tp,
11964                                 NVRAM_CMD_WREN | NVRAM_CMD_GO |
11965                                 NVRAM_CMD_DONE)))
11966
11967                                 break;
11968                 }
11969                 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11970                         /* We always do complete word writes to eeprom. */
11971                         nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
11972                 }
11973
11974                 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11975                         break;
11976         }
11977         return ret;
11978 }
11979
11980 /* offset and length are dword aligned */
11981 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
11982 {
11983         int ret;
11984
11985         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
11986                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
11987                        ~GRC_LCLCTRL_GPIO_OUTPUT1);
11988                 udelay(40);
11989         }
11990
11991         if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
11992                 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
11993         }
11994         else {
11995                 u32 grc_mode;
11996
11997                 ret = tg3_nvram_lock(tp);
11998                 if (ret)
11999                         return ret;
12000
12001                 tg3_enable_nvram_access(tp);
12002                 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
12003                     !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM))
12004                         tw32(NVRAM_WRITE1, 0x406);
12005
12006                 grc_mode = tr32(GRC_MODE);
12007                 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
12008
12009                 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
12010                         !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
12011
12012                         ret = tg3_nvram_write_block_buffered(tp, offset, len,
12013                                 buf);
12014                 }
12015                 else {
12016                         ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
12017                                 buf);
12018                 }
12019
12020                 grc_mode = tr32(GRC_MODE);
12021                 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
12022
12023                 tg3_disable_nvram_access(tp);
12024                 tg3_nvram_unlock(tp);
12025         }
12026
12027         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
12028                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
12029                 udelay(40);
12030         }
12031
12032         return ret;
12033 }
12034
12035 struct subsys_tbl_ent {
12036         u16 subsys_vendor, subsys_devid;
12037         u32 phy_id;
12038 };
12039
12040 static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
12041         /* Broadcom boards. */
12042         { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
12043         { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
12044         { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
12045         { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 },              /* BCM95700A9 */
12046         { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
12047         { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
12048         { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 },              /* BCM95701A7 */
12049         { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
12050         { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
12051         { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
12052         { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
12053
12054         /* 3com boards. */
12055         { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
12056         { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
12057         { PCI_VENDOR_ID_3COM, 0x1004, 0 },              /* 3C996SX */
12058         { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
12059         { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
12060
12061         /* DELL boards. */
12062         { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
12063         { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
12064         { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
12065         { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
12066
12067         /* Compaq boards. */
12068         { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
12069         { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
12070         { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 },              /* CHANGELING */
12071         { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
12072         { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
12073
12074         /* IBM boards. */
12075         { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
12076 };
12077
12078 static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
12079 {
12080         int i;
12081
12082         for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
12083                 if ((subsys_id_to_phy_id[i].subsys_vendor ==
12084                      tp->pdev->subsystem_vendor) &&
12085                     (subsys_id_to_phy_id[i].subsys_devid ==
12086                      tp->pdev->subsystem_device))
12087                         return &subsys_id_to_phy_id[i];
12088         }
12089         return NULL;
12090 }
12091
12092 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
12093 {
12094         u32 val;
12095         u16 pmcsr;
12096
12097         /* On some early chips the SRAM cannot be accessed in D3hot state,
12098          * so need make sure we're in D0.
12099          */
12100         pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
12101         pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
12102         pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
12103         msleep(1);
12104
12105         /* Make sure register accesses (indirect or otherwise)
12106          * will function correctly.
12107          */
12108         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12109                                tp->misc_host_ctrl);
12110
12111         /* The memory arbiter has to be enabled in order for SRAM accesses
12112          * to succeed.  Normally on powerup the tg3 chip firmware will make
12113          * sure it is enabled, but other entities such as system netboot
12114          * code might disable it.
12115          */
12116         val = tr32(MEMARB_MODE);
12117         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
12118
12119         tp->phy_id = PHY_ID_INVALID;
12120         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12121
12122         /* Assume an onboard device and WOL capable by default.  */
12123         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
12124
12125         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12126                 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
12127                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12128                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12129                 }
12130                 val = tr32(VCPU_CFGSHDW);
12131                 if (val & VCPU_CFGSHDW_ASPM_DBNC)
12132                         tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
12133                 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
12134                     (val & VCPU_CFGSHDW_WOL_MAGPKT))
12135                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12136                 goto done;
12137         }
12138
12139         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
12140         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
12141                 u32 nic_cfg, led_cfg;
12142                 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
12143                 int eeprom_phy_serdes = 0;
12144
12145                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
12146                 tp->nic_sram_data_cfg = nic_cfg;
12147
12148                 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
12149                 ver >>= NIC_SRAM_DATA_VER_SHIFT;
12150                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
12151                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
12152                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
12153                     (ver > 0) && (ver < 0x100))
12154                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
12155
12156                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
12157                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
12158
12159                 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
12160                     NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
12161                         eeprom_phy_serdes = 1;
12162
12163                 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
12164                 if (nic_phy_id != 0) {
12165                         u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
12166                         u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
12167
12168                         eeprom_phy_id  = (id1 >> 16) << 10;
12169                         eeprom_phy_id |= (id2 & 0xfc00) << 16;
12170                         eeprom_phy_id |= (id2 & 0x03ff) <<  0;
12171                 } else
12172                         eeprom_phy_id = 0;
12173
12174                 tp->phy_id = eeprom_phy_id;
12175                 if (eeprom_phy_serdes) {
12176                         if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
12177                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
12178                                 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
12179                         else
12180                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12181                 }
12182
12183                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
12184                         led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
12185                                     SHASTA_EXT_LED_MODE_MASK);
12186                 else
12187                         led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
12188
12189                 switch (led_cfg) {
12190                 default:
12191                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
12192                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12193                         break;
12194
12195                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
12196                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12197                         break;
12198
12199                 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
12200                         tp->led_ctrl = LED_CTRL_MODE_MAC;
12201
12202                         /* Default to PHY_1_MODE if 0 (MAC_MODE) is
12203                          * read on some older 5700/5701 bootcode.
12204                          */
12205                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
12206                             ASIC_REV_5700 ||
12207                             GET_ASIC_REV(tp->pci_chip_rev_id) ==
12208                             ASIC_REV_5701)
12209                                 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12210
12211                         break;
12212
12213                 case SHASTA_EXT_LED_SHARED:
12214                         tp->led_ctrl = LED_CTRL_MODE_SHARED;
12215                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
12216                             tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
12217                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12218                                                  LED_CTRL_MODE_PHY_2);
12219                         break;
12220
12221                 case SHASTA_EXT_LED_MAC:
12222                         tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
12223                         break;
12224
12225                 case SHASTA_EXT_LED_COMBO:
12226                         tp->led_ctrl = LED_CTRL_MODE_COMBO;
12227                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
12228                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12229                                                  LED_CTRL_MODE_PHY_2);
12230                         break;
12231
12232                 }
12233
12234                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12235                      GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
12236                     tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
12237                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12238
12239                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
12240                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12241
12242                 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
12243                         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
12244                         if ((tp->pdev->subsystem_vendor ==
12245                              PCI_VENDOR_ID_ARIMA) &&
12246                             (tp->pdev->subsystem_device == 0x205a ||
12247                              tp->pdev->subsystem_device == 0x2063))
12248                                 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12249                 } else {
12250                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12251                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12252                 }
12253
12254                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
12255                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
12256                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
12257                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
12258                 }
12259
12260                 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
12261                         (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
12262                         tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
12263
12264                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
12265                     !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
12266                         tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
12267
12268                 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
12269                     (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
12270                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12271
12272                 if (cfg2 & (1 << 17))
12273                         tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
12274
12275                 /* serdes signal pre-emphasis in register 0x590 set by */
12276                 /* bootcode if bit 18 is set */
12277                 if (cfg2 & (1 << 18))
12278                         tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
12279
12280                 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12281                       GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
12282                     (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
12283                         tp->tg3_flags3 |= TG3_FLG3_PHY_ENABLE_APD;
12284
12285                 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12286                         u32 cfg3;
12287
12288                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
12289                         if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
12290                                 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
12291                 }
12292
12293                 if (cfg4 & NIC_SRAM_RGMII_STD_IBND_DISABLE)
12294                         tp->tg3_flags3 |= TG3_FLG3_RGMII_STD_IBND_DISABLE;
12295                 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
12296                         tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
12297                 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
12298                         tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
12299         }
12300 done:
12301         device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
12302         device_set_wakeup_enable(&tp->pdev->dev,
12303                                  tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
12304 }
12305
12306 static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
12307 {
12308         int i;
12309         u32 val;
12310
12311         tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
12312         tw32(OTP_CTRL, cmd);
12313
12314         /* Wait for up to 1 ms for command to execute. */
12315         for (i = 0; i < 100; i++) {
12316                 val = tr32(OTP_STATUS);
12317                 if (val & OTP_STATUS_CMD_DONE)
12318                         break;
12319                 udelay(10);
12320         }
12321
12322         return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
12323 }
12324
12325 /* Read the gphy configuration from the OTP region of the chip.  The gphy
12326  * configuration is a 32-bit value that straddles the alignment boundary.
12327  * We do two 32-bit reads and then shift and merge the results.
12328  */
12329 static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
12330 {
12331         u32 bhalf_otp, thalf_otp;
12332
12333         tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
12334
12335         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
12336                 return 0;
12337
12338         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
12339
12340         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12341                 return 0;
12342
12343         thalf_otp = tr32(OTP_READ_DATA);
12344
12345         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
12346
12347         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12348                 return 0;
12349
12350         bhalf_otp = tr32(OTP_READ_DATA);
12351
12352         return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
12353 }
12354
12355 static int __devinit tg3_phy_probe(struct tg3 *tp)
12356 {
12357         u32 hw_phy_id_1, hw_phy_id_2;
12358         u32 hw_phy_id, hw_phy_id_masked;
12359         int err;
12360
12361         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
12362                 return tg3_phy_init(tp);
12363
12364         /* Reading the PHY ID register can conflict with ASF
12365          * firmware access to the PHY hardware.
12366          */
12367         err = 0;
12368         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12369             (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
12370                 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
12371         } else {
12372                 /* Now read the physical PHY_ID from the chip and verify
12373                  * that it is sane.  If it doesn't look good, we fall back
12374                  * to either the hard-coded table based PHY_ID and failing
12375                  * that the value found in the eeprom area.
12376                  */
12377                 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
12378                 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
12379
12380                 hw_phy_id  = (hw_phy_id_1 & 0xffff) << 10;
12381                 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
12382                 hw_phy_id |= (hw_phy_id_2 & 0x03ff) <<  0;
12383
12384                 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
12385         }
12386
12387         if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
12388                 tp->phy_id = hw_phy_id;
12389                 if (hw_phy_id_masked == PHY_ID_BCM8002)
12390                         tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12391                 else
12392                         tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
12393         } else {
12394                 if (tp->phy_id != PHY_ID_INVALID) {
12395                         /* Do nothing, phy ID already set up in
12396                          * tg3_get_eeprom_hw_cfg().
12397                          */
12398                 } else {
12399                         struct subsys_tbl_ent *p;
12400
12401                         /* No eeprom signature?  Try the hardcoded
12402                          * subsys device table.
12403                          */
12404                         p = lookup_by_subsys(tp);
12405                         if (!p)
12406                                 return -ENODEV;
12407
12408                         tp->phy_id = p->phy_id;
12409                         if (!tp->phy_id ||
12410                             tp->phy_id == PHY_ID_BCM8002)
12411                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12412                 }
12413         }
12414
12415         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
12416             !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
12417             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
12418                 u32 bmsr, adv_reg, tg3_ctrl, mask;
12419
12420                 tg3_readphy(tp, MII_BMSR, &bmsr);
12421                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
12422                     (bmsr & BMSR_LSTATUS))
12423                         goto skip_phy_reset;
12424
12425                 err = tg3_phy_reset(tp);
12426                 if (err)
12427                         return err;
12428
12429                 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
12430                            ADVERTISE_100HALF | ADVERTISE_100FULL |
12431                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
12432                 tg3_ctrl = 0;
12433                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
12434                         tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
12435                                     MII_TG3_CTRL_ADV_1000_FULL);
12436                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12437                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
12438                                 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
12439                                              MII_TG3_CTRL_ENABLE_AS_MASTER);
12440                 }
12441
12442                 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
12443                         ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
12444                         ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
12445                 if (!tg3_copper_is_advertising_all(tp, mask)) {
12446                         tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12447
12448                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
12449                                 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12450
12451                         tg3_writephy(tp, MII_BMCR,
12452                                      BMCR_ANENABLE | BMCR_ANRESTART);
12453                 }
12454                 tg3_phy_set_wirespeed(tp);
12455
12456                 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12457                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
12458                         tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12459         }
12460
12461 skip_phy_reset:
12462         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
12463                 err = tg3_init_5401phy_dsp(tp);
12464                 if (err)
12465                         return err;
12466         }
12467
12468         if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
12469                 err = tg3_init_5401phy_dsp(tp);
12470         }
12471
12472         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
12473                 tp->link_config.advertising =
12474                         (ADVERTISED_1000baseT_Half |
12475                          ADVERTISED_1000baseT_Full |
12476                          ADVERTISED_Autoneg |
12477                          ADVERTISED_FIBRE);
12478         if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
12479                 tp->link_config.advertising &=
12480                         ~(ADVERTISED_1000baseT_Half |
12481                           ADVERTISED_1000baseT_Full);
12482
12483         return err;
12484 }
12485
12486 static void __devinit tg3_read_partno(struct tg3 *tp)
12487 {
12488         unsigned char vpd_data[TG3_NVM_VPD_LEN];   /* in little-endian format */
12489         unsigned int i;
12490         u32 magic;
12491
12492         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
12493             tg3_nvram_read(tp, 0x0, &magic))
12494                 goto out_not_found;
12495
12496         if (magic == TG3_EEPROM_MAGIC) {
12497                 for (i = 0; i < TG3_NVM_VPD_LEN; i += 4) {
12498                         u32 tmp;
12499
12500                         /* The data is in little-endian format in NVRAM.
12501                          * Use the big-endian read routines to preserve
12502                          * the byte order as it exists in NVRAM.
12503                          */
12504                         if (tg3_nvram_read_be32(tp, TG3_NVM_VPD_OFF + i, &tmp))
12505                                 goto out_not_found;
12506
12507                         memcpy(&vpd_data[i], &tmp, sizeof(tmp));
12508                 }
12509         } else {
12510                 ssize_t cnt;
12511                 unsigned int pos = 0, i = 0;
12512
12513                 for (; pos < TG3_NVM_VPD_LEN && i < 3; i++, pos += cnt) {
12514                         cnt = pci_read_vpd(tp->pdev, pos,
12515                                            TG3_NVM_VPD_LEN - pos,
12516                                            &vpd_data[pos]);
12517                         if (cnt == -ETIMEDOUT || -EINTR)
12518                                 cnt = 0;
12519                         else if (cnt < 0)
12520                                 goto out_not_found;
12521                 }
12522                 if (pos != TG3_NVM_VPD_LEN)
12523                         goto out_not_found;
12524         }
12525
12526         /* Now parse and find the part number. */
12527         for (i = 0; i < TG3_NVM_VPD_LEN - 2; ) {
12528                 unsigned char val = vpd_data[i];
12529                 unsigned int block_end;
12530
12531                 if (val == 0x82 || val == 0x91) {
12532                         i = (i + 3 +
12533                              (vpd_data[i + 1] +
12534                               (vpd_data[i + 2] << 8)));
12535                         continue;
12536                 }
12537
12538                 if (val != 0x90)
12539                         goto out_not_found;
12540
12541                 block_end = (i + 3 +
12542                              (vpd_data[i + 1] +
12543                               (vpd_data[i + 2] << 8)));
12544                 i += 3;
12545
12546                 if (block_end > TG3_NVM_VPD_LEN)
12547                         goto out_not_found;
12548
12549                 while (i < (block_end - 2)) {
12550                         if (vpd_data[i + 0] == 'P' &&
12551                             vpd_data[i + 1] == 'N') {
12552                                 int partno_len = vpd_data[i + 2];
12553
12554                                 i += 3;
12555                                 if (partno_len > TG3_BPN_SIZE ||
12556                                     (partno_len + i) > TG3_NVM_VPD_LEN)
12557                                         goto out_not_found;
12558
12559                                 memcpy(tp->board_part_number,
12560                                        &vpd_data[i], partno_len);
12561
12562                                 /* Success. */
12563                                 return;
12564                         }
12565                         i += 3 + vpd_data[i + 2];
12566                 }
12567
12568                 /* Part number not found. */
12569                 goto out_not_found;
12570         }
12571
12572 out_not_found:
12573         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12574                 strcpy(tp->board_part_number, "BCM95906");
12575         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12576                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
12577                 strcpy(tp->board_part_number, "BCM57780");
12578         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12579                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
12580                 strcpy(tp->board_part_number, "BCM57760");
12581         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12582                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
12583                 strcpy(tp->board_part_number, "BCM57790");
12584         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12585                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
12586                 strcpy(tp->board_part_number, "BCM57788");
12587         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
12588                 strcpy(tp->board_part_number, "BCM57765");
12589         else
12590                 strcpy(tp->board_part_number, "none");
12591 }
12592
12593 static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
12594 {
12595         u32 val;
12596
12597         if (tg3_nvram_read(tp, offset, &val) ||
12598             (val & 0xfc000000) != 0x0c000000 ||
12599             tg3_nvram_read(tp, offset + 4, &val) ||
12600             val != 0)
12601                 return 0;
12602
12603         return 1;
12604 }
12605
12606 static void __devinit tg3_read_bc_ver(struct tg3 *tp)
12607 {
12608         u32 val, offset, start, ver_offset;
12609         int i;
12610         bool newver = false;
12611
12612         if (tg3_nvram_read(tp, 0xc, &offset) ||
12613             tg3_nvram_read(tp, 0x4, &start))
12614                 return;
12615
12616         offset = tg3_nvram_logical_addr(tp, offset);
12617
12618         if (tg3_nvram_read(tp, offset, &val))
12619                 return;
12620
12621         if ((val & 0xfc000000) == 0x0c000000) {
12622                 if (tg3_nvram_read(tp, offset + 4, &val))
12623                         return;
12624
12625                 if (val == 0)
12626                         newver = true;
12627         }
12628
12629         if (newver) {
12630                 if (tg3_nvram_read(tp, offset + 8, &ver_offset))
12631                         return;
12632
12633                 offset = offset + ver_offset - start;
12634                 for (i = 0; i < 16; i += 4) {
12635                         __be32 v;
12636                         if (tg3_nvram_read_be32(tp, offset + i, &v))
12637                                 return;
12638
12639                         memcpy(tp->fw_ver + i, &v, sizeof(v));
12640                 }
12641         } else {
12642                 u32 major, minor;
12643
12644                 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
12645                         return;
12646
12647                 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
12648                         TG3_NVM_BCVER_MAJSFT;
12649                 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
12650                 snprintf(&tp->fw_ver[0], 32, "v%d.%02d", major, minor);
12651         }
12652 }
12653
12654 static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
12655 {
12656         u32 val, major, minor;
12657
12658         /* Use native endian representation */
12659         if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
12660                 return;
12661
12662         major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
12663                 TG3_NVM_HWSB_CFG1_MAJSFT;
12664         minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
12665                 TG3_NVM_HWSB_CFG1_MINSFT;
12666
12667         snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
12668 }
12669
12670 static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
12671 {
12672         u32 offset, major, minor, build;
12673
12674         tp->fw_ver[0] = 's';
12675         tp->fw_ver[1] = 'b';
12676         tp->fw_ver[2] = '\0';
12677
12678         if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
12679                 return;
12680
12681         switch (val & TG3_EEPROM_SB_REVISION_MASK) {
12682         case TG3_EEPROM_SB_REVISION_0:
12683                 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
12684                 break;
12685         case TG3_EEPROM_SB_REVISION_2:
12686                 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
12687                 break;
12688         case TG3_EEPROM_SB_REVISION_3:
12689                 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
12690                 break;
12691         default:
12692                 return;
12693         }
12694
12695         if (tg3_nvram_read(tp, offset, &val))
12696                 return;
12697
12698         build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
12699                 TG3_EEPROM_SB_EDH_BLD_SHFT;
12700         major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
12701                 TG3_EEPROM_SB_EDH_MAJ_SHFT;
12702         minor =  val & TG3_EEPROM_SB_EDH_MIN_MASK;
12703
12704         if (minor > 99 || build > 26)
12705                 return;
12706
12707         snprintf(&tp->fw_ver[2], 30, " v%d.%02d", major, minor);
12708
12709         if (build > 0) {
12710                 tp->fw_ver[8] = 'a' + build - 1;
12711                 tp->fw_ver[9] = '\0';
12712         }
12713 }
12714
12715 static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
12716 {
12717         u32 val, offset, start;
12718         int i, vlen;
12719
12720         for (offset = TG3_NVM_DIR_START;
12721              offset < TG3_NVM_DIR_END;
12722              offset += TG3_NVM_DIRENT_SIZE) {
12723                 if (tg3_nvram_read(tp, offset, &val))
12724                         return;
12725
12726                 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
12727                         break;
12728         }
12729
12730         if (offset == TG3_NVM_DIR_END)
12731                 return;
12732
12733         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
12734                 start = 0x08000000;
12735         else if (tg3_nvram_read(tp, offset - 4, &start))
12736                 return;
12737
12738         if (tg3_nvram_read(tp, offset + 4, &offset) ||
12739             !tg3_fw_img_is_valid(tp, offset) ||
12740             tg3_nvram_read(tp, offset + 8, &val))
12741                 return;
12742
12743         offset += val - start;
12744
12745         vlen = strlen(tp->fw_ver);
12746
12747         tp->fw_ver[vlen++] = ',';
12748         tp->fw_ver[vlen++] = ' ';
12749
12750         for (i = 0; i < 4; i++) {
12751                 __be32 v;
12752                 if (tg3_nvram_read_be32(tp, offset, &v))
12753                         return;
12754
12755                 offset += sizeof(v);
12756
12757                 if (vlen > TG3_VER_SIZE - sizeof(v)) {
12758                         memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
12759                         break;
12760                 }
12761
12762                 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
12763                 vlen += sizeof(v);
12764         }
12765 }
12766
12767 static void __devinit tg3_read_dash_ver(struct tg3 *tp)
12768 {
12769         int vlen;
12770         u32 apedata;
12771
12772         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) ||
12773             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
12774                 return;
12775
12776         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
12777         if (apedata != APE_SEG_SIG_MAGIC)
12778                 return;
12779
12780         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
12781         if (!(apedata & APE_FW_STATUS_READY))
12782                 return;
12783
12784         apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
12785
12786         vlen = strlen(tp->fw_ver);
12787
12788         snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " DASH v%d.%d.%d.%d",
12789                  (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
12790                  (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
12791                  (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
12792                  (apedata & APE_FW_VERSION_BLDMSK));
12793 }
12794
12795 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
12796 {
12797         u32 val;
12798
12799         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) {
12800                 tp->fw_ver[0] = 's';
12801                 tp->fw_ver[1] = 'b';
12802                 tp->fw_ver[2] = '\0';
12803
12804                 return;
12805         }
12806
12807         if (tg3_nvram_read(tp, 0, &val))
12808                 return;
12809
12810         if (val == TG3_EEPROM_MAGIC)
12811                 tg3_read_bc_ver(tp);
12812         else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
12813                 tg3_read_sb_ver(tp, val);
12814         else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
12815                 tg3_read_hwsb_ver(tp);
12816         else
12817                 return;
12818
12819         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12820              (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
12821                 return;
12822
12823         tg3_read_mgmtfw_ver(tp);
12824
12825         tp->fw_ver[TG3_VER_SIZE - 1] = 0;
12826 }
12827
12828 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
12829
12830 static int __devinit tg3_get_invariants(struct tg3 *tp)
12831 {
12832         static struct pci_device_id write_reorder_chipsets[] = {
12833                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12834                              PCI_DEVICE_ID_AMD_FE_GATE_700C) },
12835                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12836                              PCI_DEVICE_ID_AMD_8131_BRIDGE) },
12837                 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
12838                              PCI_DEVICE_ID_VIA_8385_0) },
12839                 { },
12840         };
12841         u32 misc_ctrl_reg;
12842         u32 pci_state_reg, grc_misc_cfg;
12843         u32 val;
12844         u16 pci_cmd;
12845         int err;
12846
12847         /* Force memory write invalidate off.  If we leave it on,
12848          * then on 5700_BX chips we have to enable a workaround.
12849          * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
12850          * to match the cacheline size.  The Broadcom driver have this
12851          * workaround but turns MWI off all the times so never uses
12852          * it.  This seems to suggest that the workaround is insufficient.
12853          */
12854         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12855         pci_cmd &= ~PCI_COMMAND_INVALIDATE;
12856         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12857
12858         /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
12859          * has the register indirect write enable bit set before
12860          * we try to access any of the MMIO registers.  It is also
12861          * critical that the PCI-X hw workaround situation is decided
12862          * before that as well.
12863          */
12864         pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12865                               &misc_ctrl_reg);
12866
12867         tp->pci_chip_rev_id = (misc_ctrl_reg >>
12868                                MISC_HOST_CTRL_CHIPREV_SHIFT);
12869         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
12870                 u32 prod_id_asic_rev;
12871
12872                 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
12873                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
12874                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5724)
12875                         pci_read_config_dword(tp->pdev,
12876                                               TG3PCI_GEN2_PRODID_ASICREV,
12877                                               &prod_id_asic_rev);
12878                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 ||
12879                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 ||
12880                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||
12881                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||
12882                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
12883                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
12884                         pci_read_config_dword(tp->pdev,
12885                                               TG3PCI_GEN15_PRODID_ASICREV,
12886                                               &prod_id_asic_rev);
12887                 else
12888                         pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
12889                                               &prod_id_asic_rev);
12890
12891                 tp->pci_chip_rev_id = prod_id_asic_rev;
12892         }
12893
12894         /* Wrong chip ID in 5752 A0. This code can be removed later
12895          * as A0 is not in production.
12896          */
12897         if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
12898                 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
12899
12900         /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
12901          * we need to disable memory and use config. cycles
12902          * only to access all registers. The 5702/03 chips
12903          * can mistakenly decode the special cycles from the
12904          * ICH chipsets as memory write cycles, causing corruption
12905          * of register and memory space. Only certain ICH bridges
12906          * will drive special cycles with non-zero data during the
12907          * address phase which can fall within the 5703's address
12908          * range. This is not an ICH bug as the PCI spec allows
12909          * non-zero address during special cycles. However, only
12910          * these ICH bridges are known to drive non-zero addresses
12911          * during special cycles.
12912          *
12913          * Since special cycles do not cross PCI bridges, we only
12914          * enable this workaround if the 5703 is on the secondary
12915          * bus of these ICH bridges.
12916          */
12917         if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
12918             (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
12919                 static struct tg3_dev_id {
12920                         u32     vendor;
12921                         u32     device;
12922                         u32     rev;
12923                 } ich_chipsets[] = {
12924                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
12925                           PCI_ANY_ID },
12926                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
12927                           PCI_ANY_ID },
12928                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
12929                           0xa },
12930                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
12931                           PCI_ANY_ID },
12932                         { },
12933                 };
12934                 struct tg3_dev_id *pci_id = &ich_chipsets[0];
12935                 struct pci_dev *bridge = NULL;
12936
12937                 while (pci_id->vendor != 0) {
12938                         bridge = pci_get_device(pci_id->vendor, pci_id->device,
12939                                                 bridge);
12940                         if (!bridge) {
12941                                 pci_id++;
12942                                 continue;
12943                         }
12944                         if (pci_id->rev != PCI_ANY_ID) {
12945                                 if (bridge->revision > pci_id->rev)
12946                                         continue;
12947                         }
12948                         if (bridge->subordinate &&
12949                             (bridge->subordinate->number ==
12950                              tp->pdev->bus->number)) {
12951
12952                                 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
12953                                 pci_dev_put(bridge);
12954                                 break;
12955                         }
12956                 }
12957         }
12958
12959         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
12960                 static struct tg3_dev_id {
12961                         u32     vendor;
12962                         u32     device;
12963                 } bridge_chipsets[] = {
12964                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
12965                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
12966                         { },
12967                 };
12968                 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
12969                 struct pci_dev *bridge = NULL;
12970
12971                 while (pci_id->vendor != 0) {
12972                         bridge = pci_get_device(pci_id->vendor,
12973                                                 pci_id->device,
12974                                                 bridge);
12975                         if (!bridge) {
12976                                 pci_id++;
12977                                 continue;
12978                         }
12979                         if (bridge->subordinate &&
12980                             (bridge->subordinate->number <=
12981                              tp->pdev->bus->number) &&
12982                             (bridge->subordinate->subordinate >=
12983                              tp->pdev->bus->number)) {
12984                                 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
12985                                 pci_dev_put(bridge);
12986                                 break;
12987                         }
12988                 }
12989         }
12990
12991         /* The EPB bridge inside 5714, 5715, and 5780 cannot support
12992          * DMA addresses > 40-bit. This bridge may have other additional
12993          * 57xx devices behind it in some 4-port NIC designs for example.
12994          * Any tg3 device found behind the bridge will also need the 40-bit
12995          * DMA workaround.
12996          */
12997         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
12998             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
12999                 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
13000                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
13001                 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
13002         }
13003         else {
13004                 struct pci_dev *bridge = NULL;
13005
13006                 do {
13007                         bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
13008                                                 PCI_DEVICE_ID_SERVERWORKS_EPB,
13009                                                 bridge);
13010                         if (bridge && bridge->subordinate &&
13011                             (bridge->subordinate->number <=
13012                              tp->pdev->bus->number) &&
13013                             (bridge->subordinate->subordinate >=
13014                              tp->pdev->bus->number)) {
13015                                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
13016                                 pci_dev_put(bridge);
13017                                 break;
13018                         }
13019                 } while (bridge);
13020         }
13021
13022         /* Initialize misc host control in PCI block. */
13023         tp->misc_host_ctrl |= (misc_ctrl_reg &
13024                                MISC_HOST_CTRL_CHIPREV);
13025         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13026                                tp->misc_host_ctrl);
13027
13028         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
13029             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
13030             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
13031                 tp->pdev_peer = tg3_find_peer(tp);
13032
13033         /* Intentionally exclude ASIC_REV_5906 */
13034         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13035             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13036             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13037             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13038             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13039             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13040             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13041             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13042                 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
13043
13044         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13045             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13046             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
13047             (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13048             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13049                 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
13050
13051         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
13052             (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
13053                 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
13054
13055         /* 5700 B0 chips do not support checksumming correctly due
13056          * to hardware bugs.
13057          */
13058         if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
13059                 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
13060         else {
13061                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
13062                 tp->dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
13063                 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
13064                         tp->dev->features |= NETIF_F_IPV6_CSUM;
13065         }
13066
13067         /* Determine TSO capabilities */
13068         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13069             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13070                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_3;
13071         else if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13072                  GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13073                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
13074         else if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
13075                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
13076                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 &&
13077                     tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
13078                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
13079         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13080                    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13081                    tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
13082                 tp->tg3_flags2 |= TG3_FLG2_TSO_BUG;
13083                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
13084                         tp->fw_needed = FIRMWARE_TG3TSO5;
13085                 else
13086                         tp->fw_needed = FIRMWARE_TG3TSO;
13087         }
13088
13089         tp->irq_max = 1;
13090
13091         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
13092                 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
13093                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
13094                     GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
13095                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
13096                      tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
13097                      tp->pdev_peer == tp->pdev))
13098                         tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
13099
13100                 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13101                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13102                         tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
13103                 }
13104
13105                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13106                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
13107                         tp->tg3_flags |= TG3_FLAG_SUPPORT_MSIX;
13108                         tp->irq_max = TG3_IRQ_MAX_VECS;
13109                 }
13110         }
13111
13112         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13113             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13114                 tp->tg3_flags3 |= TG3_FLG3_SHORT_DMA_BUG;
13115         else if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS)) {
13116                 tp->tg3_flags3 |= TG3_FLG3_4G_DMA_BNDRY_BUG;
13117                 tp->tg3_flags3 |= TG3_FLG3_40BIT_DMA_LIMIT_BUG;
13118         }
13119
13120         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13121             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13122                 tp->tg3_flags3 |= TG3_FLG3_USE_JUMBO_BDFLAG;
13123
13124         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
13125              (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
13126                  (tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG))
13127                 tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE;
13128
13129         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13130                               &pci_state_reg);
13131
13132         tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
13133         if (tp->pcie_cap != 0) {
13134                 u16 lnkctl;
13135
13136                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
13137
13138                 pcie_set_readrq(tp->pdev, 4096);
13139
13140                 pci_read_config_word(tp->pdev,
13141                                      tp->pcie_cap + PCI_EXP_LNKCTL,
13142                                      &lnkctl);
13143                 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
13144                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13145                                 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
13146                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13147                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13148                             tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
13149                             tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
13150                                 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
13151                 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5717_A0) {
13152                         tp->tg3_flags3 |= TG3_FLG3_L1PLLPD_EN;
13153                 }
13154         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
13155                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
13156         } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
13157                    (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13158                 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
13159                 if (!tp->pcix_cap) {
13160                         printk(KERN_ERR PFX "Cannot find PCI-X "
13161                                             "capability, aborting.\n");
13162                         return -EIO;
13163                 }
13164
13165                 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
13166                         tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
13167         }
13168
13169         /* If we have an AMD 762 or VIA K8T800 chipset, write
13170          * reordering to the mailbox registers done by the host
13171          * controller can cause major troubles.  We read back from
13172          * every mailbox register write to force the writes to be
13173          * posted to the chip in order.
13174          */
13175         if (pci_dev_present(write_reorder_chipsets) &&
13176             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13177                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
13178
13179         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
13180                              &tp->pci_cacheline_sz);
13181         pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13182                              &tp->pci_lat_timer);
13183         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13184             tp->pci_lat_timer < 64) {
13185                 tp->pci_lat_timer = 64;
13186                 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13187                                       tp->pci_lat_timer);
13188         }
13189
13190         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
13191                 /* 5700 BX chips need to have their TX producer index
13192                  * mailboxes written twice to workaround a bug.
13193                  */
13194                 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
13195
13196                 /* If we are in PCI-X mode, enable register write workaround.
13197                  *
13198                  * The workaround is to use indirect register accesses
13199                  * for all chip writes not to mailbox registers.
13200                  */
13201                 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
13202                         u32 pm_reg;
13203
13204                         tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13205
13206                         /* The chip can have it's power management PCI config
13207                          * space registers clobbered due to this bug.
13208                          * So explicitly force the chip into D0 here.
13209                          */
13210                         pci_read_config_dword(tp->pdev,
13211                                               tp->pm_cap + PCI_PM_CTRL,
13212                                               &pm_reg);
13213                         pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
13214                         pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
13215                         pci_write_config_dword(tp->pdev,
13216                                                tp->pm_cap + PCI_PM_CTRL,
13217                                                pm_reg);
13218
13219                         /* Also, force SERR#/PERR# in PCI command. */
13220                         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13221                         pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
13222                         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13223                 }
13224         }
13225
13226         if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
13227                 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
13228         if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
13229                 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
13230
13231         /* Chip-specific fixup from Broadcom driver */
13232         if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
13233             (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
13234                 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
13235                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
13236         }
13237
13238         /* Default fast path register access methods */
13239         tp->read32 = tg3_read32;
13240         tp->write32 = tg3_write32;
13241         tp->read32_mbox = tg3_read32;
13242         tp->write32_mbox = tg3_write32;
13243         tp->write32_tx_mbox = tg3_write32;
13244         tp->write32_rx_mbox = tg3_write32;
13245
13246         /* Various workaround register access methods */
13247         if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
13248                 tp->write32 = tg3_write_indirect_reg32;
13249         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
13250                  ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
13251                   tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
13252                 /*
13253                  * Back to back register writes can cause problems on these
13254                  * chips, the workaround is to read back all reg writes
13255                  * except those to mailbox regs.
13256                  *
13257                  * See tg3_write_indirect_reg32().
13258                  */
13259                 tp->write32 = tg3_write_flush_reg32;
13260         }
13261
13262         if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
13263             (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
13264                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
13265                 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
13266                         tp->write32_rx_mbox = tg3_write_flush_reg32;
13267         }
13268
13269         if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
13270                 tp->read32 = tg3_read_indirect_reg32;
13271                 tp->write32 = tg3_write_indirect_reg32;
13272                 tp->read32_mbox = tg3_read_indirect_mbox;
13273                 tp->write32_mbox = tg3_write_indirect_mbox;
13274                 tp->write32_tx_mbox = tg3_write_indirect_mbox;
13275                 tp->write32_rx_mbox = tg3_write_indirect_mbox;
13276
13277                 iounmap(tp->regs);
13278                 tp->regs = NULL;
13279
13280                 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13281                 pci_cmd &= ~PCI_COMMAND_MEMORY;
13282                 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13283         }
13284         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13285                 tp->read32_mbox = tg3_read32_mbox_5906;
13286                 tp->write32_mbox = tg3_write32_mbox_5906;
13287                 tp->write32_tx_mbox = tg3_write32_mbox_5906;
13288                 tp->write32_rx_mbox = tg3_write32_mbox_5906;
13289         }
13290
13291         if (tp->write32 == tg3_write_indirect_reg32 ||
13292             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13293              (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13294               GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
13295                 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
13296
13297         /* Get eeprom hw config before calling tg3_set_power_state().
13298          * In particular, the TG3_FLG2_IS_NIC flag must be
13299          * determined before calling tg3_set_power_state() so that
13300          * we know whether or not to switch out of Vaux power.
13301          * When the flag is set, it means that GPIO1 is used for eeprom
13302          * write protect and also implies that it is a LOM where GPIOs
13303          * are not used to switch power.
13304          */
13305         tg3_get_eeprom_hw_cfg(tp);
13306
13307         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
13308                 /* Allow reads and writes to the
13309                  * APE register and memory space.
13310                  */
13311                 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
13312                                  PCISTATE_ALLOW_APE_SHMEM_WR;
13313                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
13314                                        pci_state_reg);
13315         }
13316
13317         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13318             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13319             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13320             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13321             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13322             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13323                 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
13324
13325         /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
13326          * GPIO1 driven high will bring 5700's external PHY out of reset.
13327          * It is also used as eeprom write protect on LOMs.
13328          */
13329         tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
13330         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13331             (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
13332                 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
13333                                        GRC_LCLCTRL_GPIO_OUTPUT1);
13334         /* Unused GPIO3 must be driven as output on 5752 because there
13335          * are no pull-up resistors on unused GPIO pins.
13336          */
13337         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
13338                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
13339
13340         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13341             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13342             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13343                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13344
13345         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
13346             tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
13347                 /* Turn off the debug UART. */
13348                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13349                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
13350                         /* Keep VMain power. */
13351                         tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
13352                                               GRC_LCLCTRL_GPIO_OUTPUT0;
13353         }
13354
13355         /* Force the chip into D0. */
13356         err = tg3_set_power_state(tp, PCI_D0);
13357         if (err) {
13358                 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
13359                        pci_name(tp->pdev));
13360                 return err;
13361         }
13362
13363         /* Derive initial jumbo mode from MTU assigned in
13364          * ether_setup() via the alloc_etherdev() call
13365          */
13366         if (tp->dev->mtu > ETH_DATA_LEN &&
13367             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13368                 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
13369
13370         /* Determine WakeOnLan speed to use. */
13371         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13372             tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
13373             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
13374             tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
13375                 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
13376         } else {
13377                 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
13378         }
13379
13380         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13381                 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
13382
13383         /* A few boards don't want Ethernet@WireSpeed phy feature */
13384         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13385             ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
13386              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
13387              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
13388             (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) ||
13389             (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
13390                 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
13391
13392         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
13393             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
13394                 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
13395         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
13396                 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
13397
13398         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
13399             !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
13400             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
13401             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 &&
13402             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
13403             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765) {
13404                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13405                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13406                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13407                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
13408                         if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
13409                             tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
13410                                 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
13411                         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
13412                                 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
13413                 } else
13414                         tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
13415         }
13416
13417         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13418             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
13419                 tp->phy_otp = tg3_read_otp_phycfg(tp);
13420                 if (tp->phy_otp == 0)
13421                         tp->phy_otp = TG3_OTP_DEFAULT;
13422         }
13423
13424         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
13425                 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
13426         else
13427                 tp->mi_mode = MAC_MI_MODE_BASE;
13428
13429         tp->coalesce_mode = 0;
13430         if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
13431             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
13432                 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
13433
13434         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13435             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
13436                 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
13437
13438         err = tg3_mdio_init(tp);
13439         if (err)
13440                 return err;
13441
13442         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
13443             (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0 ||
13444                  (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
13445                 return -ENOTSUPP;
13446
13447         /* Initialize data/descriptor byte/word swapping. */
13448         val = tr32(GRC_MODE);
13449         val &= GRC_MODE_HOST_STACKUP;
13450         tw32(GRC_MODE, val | tp->grc_mode);
13451
13452         tg3_switch_clocks(tp);
13453
13454         /* Clear this out for sanity. */
13455         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
13456
13457         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13458                               &pci_state_reg);
13459         if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
13460             (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
13461                 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
13462
13463                 if (chiprevid == CHIPREV_ID_5701_A0 ||
13464                     chiprevid == CHIPREV_ID_5701_B0 ||
13465                     chiprevid == CHIPREV_ID_5701_B2 ||
13466                     chiprevid == CHIPREV_ID_5701_B5) {
13467                         void __iomem *sram_base;
13468
13469                         /* Write some dummy words into the SRAM status block
13470                          * area, see if it reads back correctly.  If the return
13471                          * value is bad, force enable the PCIX workaround.
13472                          */
13473                         sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
13474
13475                         writel(0x00000000, sram_base);
13476                         writel(0x00000000, sram_base + 4);
13477                         writel(0xffffffff, sram_base + 4);
13478                         if (readl(sram_base) != 0x00000000)
13479                                 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13480                 }
13481         }
13482
13483         udelay(50);
13484         tg3_nvram_init(tp);
13485
13486         grc_misc_cfg = tr32(GRC_MISC_CFG);
13487         grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
13488
13489         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13490             (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
13491              grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
13492                 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
13493
13494         if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
13495             (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
13496                 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
13497         if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
13498                 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
13499                                       HOSTCC_MODE_CLRTICK_TXBD);
13500
13501                 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
13502                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13503                                        tp->misc_host_ctrl);
13504         }
13505
13506         /* Preserve the APE MAC_MODE bits */
13507         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
13508                 tp->mac_mode = tr32(MAC_MODE) |
13509                                MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
13510         else
13511                 tp->mac_mode = TG3_DEF_MAC_MODE;
13512
13513         /* these are limited to 10/100 only */
13514         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13515              (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
13516             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13517              tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13518              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
13519               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
13520               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
13521             (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13522              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
13523               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
13524               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
13525             tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
13526             (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
13527                 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
13528
13529         err = tg3_phy_probe(tp);
13530         if (err) {
13531                 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
13532                        pci_name(tp->pdev), err);
13533                 /* ... but do not return immediately ... */
13534                 tg3_mdio_fini(tp);
13535         }
13536
13537         tg3_read_partno(tp);
13538         tg3_read_fw_ver(tp);
13539
13540         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
13541                 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
13542         } else {
13543                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13544                         tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
13545                 else
13546                         tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
13547         }
13548
13549         /* 5700 {AX,BX} chips have a broken status block link
13550          * change bit implementation, so we must use the
13551          * status register in those cases.
13552          */
13553         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13554                 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
13555         else
13556                 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
13557
13558         /* The led_ctrl is set during tg3_phy_probe, here we might
13559          * have to force the link status polling mechanism based
13560          * upon subsystem IDs.
13561          */
13562         if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
13563             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13564             !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
13565                 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
13566                                   TG3_FLAG_USE_LINKCHG_REG);
13567         }
13568
13569         /* For all SERDES we poll the MAC status register. */
13570         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
13571                 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
13572         else
13573                 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
13574
13575         tp->rx_offset = NET_IP_ALIGN;
13576         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13577             (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
13578                 tp->rx_offset = 0;
13579
13580         tp->rx_std_max_post = TG3_RX_RING_SIZE;
13581
13582         /* Increment the rx prod index on the rx std ring by at most
13583          * 8 for these chips to workaround hw errata.
13584          */
13585         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13586             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13587             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
13588                 tp->rx_std_max_post = 8;
13589
13590         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
13591                 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
13592                                      PCIE_PWR_MGMT_L1_THRESH_MSK;
13593
13594         return err;
13595 }
13596
13597 #ifdef CONFIG_SPARC
13598 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
13599 {
13600         struct net_device *dev = tp->dev;
13601         struct pci_dev *pdev = tp->pdev;
13602         struct device_node *dp = pci_device_to_OF_node(pdev);
13603         const unsigned char *addr;
13604         int len;
13605
13606         addr = of_get_property(dp, "local-mac-address", &len);
13607         if (addr && len == 6) {
13608                 memcpy(dev->dev_addr, addr, 6);
13609                 memcpy(dev->perm_addr, dev->dev_addr, 6);
13610                 return 0;
13611         }
13612         return -ENODEV;
13613 }
13614
13615 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
13616 {
13617         struct net_device *dev = tp->dev;
13618
13619         memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
13620         memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
13621         return 0;
13622 }
13623 #endif
13624
13625 static int __devinit tg3_get_device_address(struct tg3 *tp)
13626 {
13627         struct net_device *dev = tp->dev;
13628         u32 hi, lo, mac_offset;
13629         int addr_ok = 0;
13630
13631 #ifdef CONFIG_SPARC
13632         if (!tg3_get_macaddr_sparc(tp))
13633                 return 0;
13634 #endif
13635
13636         mac_offset = 0x7c;
13637         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
13638             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13639                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
13640                         mac_offset = 0xcc;
13641                 if (tg3_nvram_lock(tp))
13642                         tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
13643                 else
13644                         tg3_nvram_unlock(tp);
13645         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
13646                 if (tr32(TG3_CPMU_STATUS) & TG3_CPMU_STATUS_PCIE_FUNC)
13647                         mac_offset = 0xcc;
13648         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13649                 mac_offset = 0x10;
13650
13651         /* First try to get it from MAC address mailbox. */
13652         tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
13653         if ((hi >> 16) == 0x484b) {
13654                 dev->dev_addr[0] = (hi >>  8) & 0xff;
13655                 dev->dev_addr[1] = (hi >>  0) & 0xff;
13656
13657                 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
13658                 dev->dev_addr[2] = (lo >> 24) & 0xff;
13659                 dev->dev_addr[3] = (lo >> 16) & 0xff;
13660                 dev->dev_addr[4] = (lo >>  8) & 0xff;
13661                 dev->dev_addr[5] = (lo >>  0) & 0xff;
13662
13663                 /* Some old bootcode may report a 0 MAC address in SRAM */
13664                 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
13665         }
13666         if (!addr_ok) {
13667                 /* Next, try NVRAM. */
13668                 if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) &&
13669                     !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
13670                     !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
13671                         memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
13672                         memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
13673                 }
13674                 /* Finally just fetch it out of the MAC control regs. */
13675                 else {
13676                         hi = tr32(MAC_ADDR_0_HIGH);
13677                         lo = tr32(MAC_ADDR_0_LOW);
13678
13679                         dev->dev_addr[5] = lo & 0xff;
13680                         dev->dev_addr[4] = (lo >> 8) & 0xff;
13681                         dev->dev_addr[3] = (lo >> 16) & 0xff;
13682                         dev->dev_addr[2] = (lo >> 24) & 0xff;
13683                         dev->dev_addr[1] = hi & 0xff;
13684                         dev->dev_addr[0] = (hi >> 8) & 0xff;
13685                 }
13686         }
13687
13688         if (!is_valid_ether_addr(&dev->dev_addr[0])) {
13689 #ifdef CONFIG_SPARC
13690                 if (!tg3_get_default_macaddr_sparc(tp))
13691                         return 0;
13692 #endif
13693                 return -EINVAL;
13694         }
13695         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
13696         return 0;
13697 }
13698
13699 #define BOUNDARY_SINGLE_CACHELINE       1
13700 #define BOUNDARY_MULTI_CACHELINE        2
13701
13702 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
13703 {
13704         int cacheline_size;
13705         u8 byte;
13706         int goal;
13707
13708         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
13709         if (byte == 0)
13710                 cacheline_size = 1024;
13711         else
13712                 cacheline_size = (int) byte * 4;
13713
13714         /* On 5703 and later chips, the boundary bits have no
13715          * effect.
13716          */
13717         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13718             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13719             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13720                 goto out;
13721
13722 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
13723         goal = BOUNDARY_MULTI_CACHELINE;
13724 #else
13725 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
13726         goal = BOUNDARY_SINGLE_CACHELINE;
13727 #else
13728         goal = 0;
13729 #endif
13730 #endif
13731
13732         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13733             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
13734                 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
13735                 goto out;
13736         }
13737
13738         if (!goal)
13739                 goto out;
13740
13741         /* PCI controllers on most RISC systems tend to disconnect
13742          * when a device tries to burst across a cache-line boundary.
13743          * Therefore, letting tg3 do so just wastes PCI bandwidth.
13744          *
13745          * Unfortunately, for PCI-E there are only limited
13746          * write-side controls for this, and thus for reads
13747          * we will still get the disconnects.  We'll also waste
13748          * these PCI cycles for both read and write for chips
13749          * other than 5700 and 5701 which do not implement the
13750          * boundary bits.
13751          */
13752         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13753             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
13754                 switch (cacheline_size) {
13755                 case 16:
13756                 case 32:
13757                 case 64:
13758                 case 128:
13759                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13760                                 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
13761                                         DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
13762                         } else {
13763                                 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13764                                         DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13765                         }
13766                         break;
13767
13768                 case 256:
13769                         val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
13770                                 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
13771                         break;
13772
13773                 default:
13774                         val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13775                                 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13776                         break;
13777                 }
13778         } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13779                 switch (cacheline_size) {
13780                 case 16:
13781                 case 32:
13782                 case 64:
13783                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13784                                 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13785                                 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
13786                                 break;
13787                         }
13788                         /* fallthrough */
13789                 case 128:
13790                 default:
13791                         val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13792                         val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
13793                         break;
13794                 }
13795         } else {
13796                 switch (cacheline_size) {
13797                 case 16:
13798                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13799                                 val |= (DMA_RWCTRL_READ_BNDRY_16 |
13800                                         DMA_RWCTRL_WRITE_BNDRY_16);
13801                                 break;
13802                         }
13803                         /* fallthrough */
13804                 case 32:
13805                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13806                                 val |= (DMA_RWCTRL_READ_BNDRY_32 |
13807                                         DMA_RWCTRL_WRITE_BNDRY_32);
13808                                 break;
13809                         }
13810                         /* fallthrough */
13811                 case 64:
13812                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13813                                 val |= (DMA_RWCTRL_READ_BNDRY_64 |
13814                                         DMA_RWCTRL_WRITE_BNDRY_64);
13815                                 break;
13816                         }
13817                         /* fallthrough */
13818                 case 128:
13819                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13820                                 val |= (DMA_RWCTRL_READ_BNDRY_128 |
13821                                         DMA_RWCTRL_WRITE_BNDRY_128);
13822                                 break;
13823                         }
13824                         /* fallthrough */
13825                 case 256:
13826                         val |= (DMA_RWCTRL_READ_BNDRY_256 |
13827                                 DMA_RWCTRL_WRITE_BNDRY_256);
13828                         break;
13829                 case 512:
13830                         val |= (DMA_RWCTRL_READ_BNDRY_512 |
13831                                 DMA_RWCTRL_WRITE_BNDRY_512);
13832                         break;
13833                 case 1024:
13834                 default:
13835                         val |= (DMA_RWCTRL_READ_BNDRY_1024 |
13836                                 DMA_RWCTRL_WRITE_BNDRY_1024);
13837                         break;
13838                 }
13839         }
13840
13841 out:
13842         return val;
13843 }
13844
13845 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
13846 {
13847         struct tg3_internal_buffer_desc test_desc;
13848         u32 sram_dma_descs;
13849         int i, ret;
13850
13851         sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
13852
13853         tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
13854         tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
13855         tw32(RDMAC_STATUS, 0);
13856         tw32(WDMAC_STATUS, 0);
13857
13858         tw32(BUFMGR_MODE, 0);
13859         tw32(FTQ_RESET, 0);
13860
13861         test_desc.addr_hi = ((u64) buf_dma) >> 32;
13862         test_desc.addr_lo = buf_dma & 0xffffffff;
13863         test_desc.nic_mbuf = 0x00002100;
13864         test_desc.len = size;
13865
13866         /*
13867          * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
13868          * the *second* time the tg3 driver was getting loaded after an
13869          * initial scan.
13870          *
13871          * Broadcom tells me:
13872          *   ...the DMA engine is connected to the GRC block and a DMA
13873          *   reset may affect the GRC block in some unpredictable way...
13874          *   The behavior of resets to individual blocks has not been tested.
13875          *
13876          * Broadcom noted the GRC reset will also reset all sub-components.
13877          */
13878         if (to_device) {
13879                 test_desc.cqid_sqid = (13 << 8) | 2;
13880
13881                 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
13882                 udelay(40);
13883         } else {
13884                 test_desc.cqid_sqid = (16 << 8) | 7;
13885
13886                 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
13887                 udelay(40);
13888         }
13889         test_desc.flags = 0x00000005;
13890
13891         for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
13892                 u32 val;
13893
13894                 val = *(((u32 *)&test_desc) + i);
13895                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
13896                                        sram_dma_descs + (i * sizeof(u32)));
13897                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
13898         }
13899         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
13900
13901         if (to_device) {
13902                 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
13903         } else {
13904                 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
13905         }
13906
13907         ret = -ENODEV;
13908         for (i = 0; i < 40; i++) {
13909                 u32 val;
13910
13911                 if (to_device)
13912                         val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
13913                 else
13914                         val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
13915                 if ((val & 0xffff) == sram_dma_descs) {
13916                         ret = 0;
13917                         break;
13918                 }
13919
13920                 udelay(100);
13921         }
13922
13923         return ret;
13924 }
13925
13926 #define TEST_BUFFER_SIZE        0x2000
13927
13928 static int __devinit tg3_test_dma(struct tg3 *tp)
13929 {
13930         dma_addr_t buf_dma;
13931         u32 *buf, saved_dma_rwctrl;
13932         int ret = 0;
13933
13934         buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
13935         if (!buf) {
13936                 ret = -ENOMEM;
13937                 goto out_nofree;
13938         }
13939
13940         tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
13941                           (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
13942
13943         tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
13944
13945         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13946             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13947                 goto out;
13948
13949         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13950                 /* DMA read watermark not used on PCIE */
13951                 tp->dma_rwctrl |= 0x00180000;
13952         } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
13953                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
13954                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
13955                         tp->dma_rwctrl |= 0x003f0000;
13956                 else
13957                         tp->dma_rwctrl |= 0x003f000f;
13958         } else {
13959                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13960                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
13961                         u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
13962                         u32 read_water = 0x7;
13963
13964                         /* If the 5704 is behind the EPB bridge, we can
13965                          * do the less restrictive ONE_DMA workaround for
13966                          * better performance.
13967                          */
13968                         if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
13969                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13970                                 tp->dma_rwctrl |= 0x8000;
13971                         else if (ccval == 0x6 || ccval == 0x7)
13972                                 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
13973
13974                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
13975                                 read_water = 4;
13976                         /* Set bit 23 to enable PCIX hw bug fix */
13977                         tp->dma_rwctrl |=
13978                                 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
13979                                 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
13980                                 (1 << 23);
13981                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
13982                         /* 5780 always in PCIX mode */
13983                         tp->dma_rwctrl |= 0x00144000;
13984                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
13985                         /* 5714 always in PCIX mode */
13986                         tp->dma_rwctrl |= 0x00148000;
13987                 } else {
13988                         tp->dma_rwctrl |= 0x001b000f;
13989                 }
13990         }
13991
13992         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13993             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13994                 tp->dma_rwctrl &= 0xfffffff0;
13995
13996         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13997             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
13998                 /* Remove this if it causes problems for some boards. */
13999                 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
14000
14001                 /* On 5700/5701 chips, we need to set this bit.
14002                  * Otherwise the chip will issue cacheline transactions
14003                  * to streamable DMA memory with not all the byte
14004                  * enables turned on.  This is an error on several
14005                  * RISC PCI controllers, in particular sparc64.
14006                  *
14007                  * On 5703/5704 chips, this bit has been reassigned
14008                  * a different meaning.  In particular, it is used
14009                  * on those chips to enable a PCI-X workaround.
14010                  */
14011                 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
14012         }
14013
14014         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14015
14016 #if 0
14017         /* Unneeded, already done by tg3_get_invariants.  */
14018         tg3_switch_clocks(tp);
14019 #endif
14020
14021         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
14022             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
14023                 goto out;
14024
14025         /* It is best to perform DMA test with maximum write burst size
14026          * to expose the 5700/5701 write DMA bug.
14027          */
14028         saved_dma_rwctrl = tp->dma_rwctrl;
14029         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14030         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14031
14032         while (1) {
14033                 u32 *p = buf, i;
14034
14035                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
14036                         p[i] = i;
14037
14038                 /* Send the buffer to the chip. */
14039                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
14040                 if (ret) {
14041                         printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
14042                         break;
14043                 }
14044
14045 #if 0
14046                 /* validate data reached card RAM correctly. */
14047                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14048                         u32 val;
14049                         tg3_read_mem(tp, 0x2100 + (i*4), &val);
14050                         if (le32_to_cpu(val) != p[i]) {
14051                                 printk(KERN_ERR "  tg3_test_dma()  Card buffer corrupted on write! (%d != %d)\n", val, i);
14052                                 /* ret = -ENODEV here? */
14053                         }
14054                         p[i] = 0;
14055                 }
14056 #endif
14057                 /* Now read it back. */
14058                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
14059                 if (ret) {
14060                         printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
14061
14062                         break;
14063                 }
14064
14065                 /* Verify it. */
14066                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14067                         if (p[i] == i)
14068                                 continue;
14069
14070                         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14071                             DMA_RWCTRL_WRITE_BNDRY_16) {
14072                                 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14073                                 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14074                                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14075                                 break;
14076                         } else {
14077                                 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
14078                                 ret = -ENODEV;
14079                                 goto out;
14080                         }
14081                 }
14082
14083                 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
14084                         /* Success. */
14085                         ret = 0;
14086                         break;
14087                 }
14088         }
14089         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14090             DMA_RWCTRL_WRITE_BNDRY_16) {
14091                 static struct pci_device_id dma_wait_state_chipsets[] = {
14092                         { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
14093                                      PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
14094                         { },
14095                 };
14096
14097                 /* DMA test passed without adjusting DMA boundary,
14098                  * now look for chipsets that are known to expose the
14099                  * DMA bug without failing the test.
14100                  */
14101                 if (pci_dev_present(dma_wait_state_chipsets)) {
14102                         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14103                         tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14104                 }
14105                 else
14106                         /* Safe to use the calculated DMA boundary. */
14107                         tp->dma_rwctrl = saved_dma_rwctrl;
14108
14109                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14110         }
14111
14112 out:
14113         pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
14114 out_nofree:
14115         return ret;
14116 }
14117
14118 static void __devinit tg3_init_link_config(struct tg3 *tp)
14119 {
14120         tp->link_config.advertising =
14121                 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
14122                  ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
14123                  ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
14124                  ADVERTISED_Autoneg | ADVERTISED_MII);
14125         tp->link_config.speed = SPEED_INVALID;
14126         tp->link_config.duplex = DUPLEX_INVALID;
14127         tp->link_config.autoneg = AUTONEG_ENABLE;
14128         tp->link_config.active_speed = SPEED_INVALID;
14129         tp->link_config.active_duplex = DUPLEX_INVALID;
14130         tp->link_config.phy_is_low_power = 0;
14131         tp->link_config.orig_speed = SPEED_INVALID;
14132         tp->link_config.orig_duplex = DUPLEX_INVALID;
14133         tp->link_config.orig_autoneg = AUTONEG_INVALID;
14134 }
14135
14136 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
14137 {
14138         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
14139             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
14140                 tp->bufmgr_config.mbuf_read_dma_low_water =
14141                         DEFAULT_MB_RDMA_LOW_WATER_5705;
14142                 tp->bufmgr_config.mbuf_mac_rx_low_water =
14143                         DEFAULT_MB_MACRX_LOW_WATER_57765;
14144                 tp->bufmgr_config.mbuf_high_water =
14145                         DEFAULT_MB_HIGH_WATER_57765;
14146
14147                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14148                         DEFAULT_MB_RDMA_LOW_WATER_5705;
14149                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14150                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765;
14151                 tp->bufmgr_config.mbuf_high_water_jumbo =
14152                         DEFAULT_MB_HIGH_WATER_JUMBO_57765;
14153         } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
14154                 tp->bufmgr_config.mbuf_read_dma_low_water =
14155                         DEFAULT_MB_RDMA_LOW_WATER_5705;
14156                 tp->bufmgr_config.mbuf_mac_rx_low_water =
14157                         DEFAULT_MB_MACRX_LOW_WATER_5705;
14158                 tp->bufmgr_config.mbuf_high_water =
14159                         DEFAULT_MB_HIGH_WATER_5705;
14160                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
14161                         tp->bufmgr_config.mbuf_mac_rx_low_water =
14162                                 DEFAULT_MB_MACRX_LOW_WATER_5906;
14163                         tp->bufmgr_config.mbuf_high_water =
14164                                 DEFAULT_MB_HIGH_WATER_5906;
14165                 }
14166
14167                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14168                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
14169                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14170                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
14171                 tp->bufmgr_config.mbuf_high_water_jumbo =
14172                         DEFAULT_MB_HIGH_WATER_JUMBO_5780;
14173         } else {
14174                 tp->bufmgr_config.mbuf_read_dma_low_water =
14175                         DEFAULT_MB_RDMA_LOW_WATER;
14176                 tp->bufmgr_config.mbuf_mac_rx_low_water =
14177                         DEFAULT_MB_MACRX_LOW_WATER;
14178                 tp->bufmgr_config.mbuf_high_water =
14179                         DEFAULT_MB_HIGH_WATER;
14180
14181                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14182                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
14183                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14184                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
14185                 tp->bufmgr_config.mbuf_high_water_jumbo =
14186                         DEFAULT_MB_HIGH_WATER_JUMBO;
14187         }
14188
14189         tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
14190         tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
14191 }
14192
14193 static char * __devinit tg3_phy_string(struct tg3 *tp)
14194 {
14195         switch (tp->phy_id & PHY_ID_MASK) {
14196         case PHY_ID_BCM5400:    return "5400";
14197         case PHY_ID_BCM5401:    return "5401";
14198         case PHY_ID_BCM5411:    return "5411";
14199         case PHY_ID_BCM5701:    return "5701";
14200         case PHY_ID_BCM5703:    return "5703";
14201         case PHY_ID_BCM5704:    return "5704";
14202         case PHY_ID_BCM5705:    return "5705";
14203         case PHY_ID_BCM5750:    return "5750";
14204         case PHY_ID_BCM5752:    return "5752";
14205         case PHY_ID_BCM5714:    return "5714";
14206         case PHY_ID_BCM5780:    return "5780";
14207         case PHY_ID_BCM5755:    return "5755";
14208         case PHY_ID_BCM5787:    return "5787";
14209         case PHY_ID_BCM5784:    return "5784";
14210         case PHY_ID_BCM5756:    return "5722/5756";
14211         case PHY_ID_BCM5906:    return "5906";
14212         case PHY_ID_BCM5761:    return "5761";
14213         case PHY_ID_BCM5718C:   return "5718C";
14214         case PHY_ID_BCM5718S:   return "5718S";
14215         case PHY_ID_BCM57765:   return "57765";
14216         case PHY_ID_BCM8002:    return "8002/serdes";
14217         case 0:                 return "serdes";
14218         default:                return "unknown";
14219         }
14220 }
14221
14222 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
14223 {
14224         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
14225                 strcpy(str, "PCI Express");
14226                 return str;
14227         } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
14228                 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
14229
14230                 strcpy(str, "PCIX:");
14231
14232                 if ((clock_ctrl == 7) ||
14233                     ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
14234                      GRC_MISC_CFG_BOARD_ID_5704CIOBE))
14235                         strcat(str, "133MHz");
14236                 else if (clock_ctrl == 0)
14237                         strcat(str, "33MHz");
14238                 else if (clock_ctrl == 2)
14239                         strcat(str, "50MHz");
14240                 else if (clock_ctrl == 4)
14241                         strcat(str, "66MHz");
14242                 else if (clock_ctrl == 6)
14243                         strcat(str, "100MHz");
14244         } else {
14245                 strcpy(str, "PCI:");
14246                 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
14247                         strcat(str, "66MHz");
14248                 else
14249                         strcat(str, "33MHz");
14250         }
14251         if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
14252                 strcat(str, ":32-bit");
14253         else
14254                 strcat(str, ":64-bit");
14255         return str;
14256 }
14257
14258 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
14259 {
14260         struct pci_dev *peer;
14261         unsigned int func, devnr = tp->pdev->devfn & ~7;
14262
14263         for (func = 0; func < 8; func++) {
14264                 peer = pci_get_slot(tp->pdev->bus, devnr | func);
14265                 if (peer && peer != tp->pdev)
14266                         break;
14267                 pci_dev_put(peer);
14268         }
14269         /* 5704 can be configured in single-port mode, set peer to
14270          * tp->pdev in that case.
14271          */
14272         if (!peer) {
14273                 peer = tp->pdev;
14274                 return peer;
14275         }
14276
14277         /*
14278          * We don't need to keep the refcount elevated; there's no way
14279          * to remove one half of this device without removing the other
14280          */
14281         pci_dev_put(peer);
14282
14283         return peer;
14284 }
14285
14286 static void __devinit tg3_init_coal(struct tg3 *tp)
14287 {
14288         struct ethtool_coalesce *ec = &tp->coal;
14289
14290         memset(ec, 0, sizeof(*ec));
14291         ec->cmd = ETHTOOL_GCOALESCE;
14292         ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
14293         ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
14294         ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
14295         ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
14296         ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
14297         ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
14298         ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
14299         ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
14300         ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
14301
14302         if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
14303                                  HOSTCC_MODE_CLRTICK_TXBD)) {
14304                 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
14305                 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
14306                 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
14307                 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
14308         }
14309
14310         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
14311                 ec->rx_coalesce_usecs_irq = 0;
14312                 ec->tx_coalesce_usecs_irq = 0;
14313                 ec->stats_block_coalesce_usecs = 0;
14314         }
14315 }
14316
14317 static const struct net_device_ops tg3_netdev_ops = {
14318         .ndo_open               = tg3_open,
14319         .ndo_stop               = tg3_close,
14320         .ndo_start_xmit         = tg3_start_xmit,
14321         .ndo_get_stats          = tg3_get_stats,
14322         .ndo_validate_addr      = eth_validate_addr,
14323         .ndo_set_multicast_list = tg3_set_rx_mode,
14324         .ndo_set_mac_address    = tg3_set_mac_addr,
14325         .ndo_do_ioctl           = tg3_ioctl,
14326         .ndo_tx_timeout         = tg3_tx_timeout,
14327         .ndo_change_mtu         = tg3_change_mtu,
14328 #if TG3_VLAN_TAG_USED
14329         .ndo_vlan_rx_register   = tg3_vlan_rx_register,
14330 #endif
14331 #ifdef CONFIG_NET_POLL_CONTROLLER
14332         .ndo_poll_controller    = tg3_poll_controller,
14333 #endif
14334 };
14335
14336 static const struct net_device_ops tg3_netdev_ops_dma_bug = {
14337         .ndo_open               = tg3_open,
14338         .ndo_stop               = tg3_close,
14339         .ndo_start_xmit         = tg3_start_xmit_dma_bug,
14340         .ndo_get_stats          = tg3_get_stats,
14341         .ndo_validate_addr      = eth_validate_addr,
14342         .ndo_set_multicast_list = tg3_set_rx_mode,
14343         .ndo_set_mac_address    = tg3_set_mac_addr,
14344         .ndo_do_ioctl           = tg3_ioctl,
14345         .ndo_tx_timeout         = tg3_tx_timeout,
14346         .ndo_change_mtu         = tg3_change_mtu,
14347 #if TG3_VLAN_TAG_USED
14348         .ndo_vlan_rx_register   = tg3_vlan_rx_register,
14349 #endif
14350 #ifdef CONFIG_NET_POLL_CONTROLLER
14351         .ndo_poll_controller    = tg3_poll_controller,
14352 #endif
14353 };
14354
14355 static int __devinit tg3_init_one(struct pci_dev *pdev,
14356                                   const struct pci_device_id *ent)
14357 {
14358         static int tg3_version_printed = 0;
14359         struct net_device *dev;
14360         struct tg3 *tp;
14361         int i, err, pm_cap;
14362         u32 sndmbx, rcvmbx, intmbx;
14363         char str[40];
14364         u64 dma_mask, persist_dma_mask;
14365
14366         if (tg3_version_printed++ == 0)
14367                 printk(KERN_INFO "%s", version);
14368
14369         err = pci_enable_device(pdev);
14370         if (err) {
14371                 printk(KERN_ERR PFX "Cannot enable PCI device, "
14372                        "aborting.\n");
14373                 return err;
14374         }
14375
14376         err = pci_request_regions(pdev, DRV_MODULE_NAME);
14377         if (err) {
14378                 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
14379                        "aborting.\n");
14380                 goto err_out_disable_pdev;
14381         }
14382
14383         pci_set_master(pdev);
14384
14385         /* Find power-management capability. */
14386         pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
14387         if (pm_cap == 0) {
14388                 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
14389                        "aborting.\n");
14390                 err = -EIO;
14391                 goto err_out_free_res;
14392         }
14393
14394         dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
14395         if (!dev) {
14396                 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
14397                 err = -ENOMEM;
14398                 goto err_out_free_res;
14399         }
14400
14401         SET_NETDEV_DEV(dev, &pdev->dev);
14402
14403 #if TG3_VLAN_TAG_USED
14404         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
14405 #endif
14406
14407         tp = netdev_priv(dev);
14408         tp->pdev = pdev;
14409         tp->dev = dev;
14410         tp->pm_cap = pm_cap;
14411         tp->rx_mode = TG3_DEF_RX_MODE;
14412         tp->tx_mode = TG3_DEF_TX_MODE;
14413
14414         if (tg3_debug > 0)
14415                 tp->msg_enable = tg3_debug;
14416         else
14417                 tp->msg_enable = TG3_DEF_MSG_ENABLE;
14418
14419         /* The word/byte swap controls here control register access byte
14420          * swapping.  DMA data byte swapping is controlled in the GRC_MODE
14421          * setting below.
14422          */
14423         tp->misc_host_ctrl =
14424                 MISC_HOST_CTRL_MASK_PCI_INT |
14425                 MISC_HOST_CTRL_WORD_SWAP |
14426                 MISC_HOST_CTRL_INDIR_ACCESS |
14427                 MISC_HOST_CTRL_PCISTATE_RW;
14428
14429         /* The NONFRM (non-frame) byte/word swap controls take effect
14430          * on descriptor entries, anything which isn't packet data.
14431          *
14432          * The StrongARM chips on the board (one for tx, one for rx)
14433          * are running in big-endian mode.
14434          */
14435         tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
14436                         GRC_MODE_WSWAP_NONFRM_DATA);
14437 #ifdef __BIG_ENDIAN
14438         tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
14439 #endif
14440         spin_lock_init(&tp->lock);
14441         spin_lock_init(&tp->indirect_lock);
14442         INIT_WORK(&tp->reset_task, tg3_reset_task);
14443
14444         tp->regs = pci_ioremap_bar(pdev, BAR_0);
14445         if (!tp->regs) {
14446                 printk(KERN_ERR PFX "Cannot map device registers, "
14447                        "aborting.\n");
14448                 err = -ENOMEM;
14449                 goto err_out_free_dev;
14450         }
14451
14452         tg3_init_link_config(tp);
14453
14454         tp->rx_pending = TG3_DEF_RX_RING_PENDING;
14455         tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
14456
14457         dev->ethtool_ops = &tg3_ethtool_ops;
14458         dev->watchdog_timeo = TG3_TX_TIMEOUT;
14459         dev->irq = pdev->irq;
14460
14461         err = tg3_get_invariants(tp);
14462         if (err) {
14463                 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
14464                        "aborting.\n");
14465                 goto err_out_iounmap;
14466         }
14467
14468         if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
14469             tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
14470                 dev->netdev_ops = &tg3_netdev_ops;
14471         else
14472                 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
14473
14474
14475         /* The EPB bridge inside 5714, 5715, and 5780 and any
14476          * device behind the EPB cannot support DMA addresses > 40-bit.
14477          * On 64-bit systems with IOMMU, use 40-bit dma_mask.
14478          * On 64-bit systems without IOMMU, use 64-bit dma_mask and
14479          * do DMA address check in tg3_start_xmit().
14480          */
14481         if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
14482                 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
14483         else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
14484                 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
14485 #ifdef CONFIG_HIGHMEM
14486                 dma_mask = DMA_BIT_MASK(64);
14487 #endif
14488         } else
14489                 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
14490
14491         /* Configure DMA attributes. */
14492         if (dma_mask > DMA_BIT_MASK(32)) {
14493                 err = pci_set_dma_mask(pdev, dma_mask);
14494                 if (!err) {
14495                         dev->features |= NETIF_F_HIGHDMA;
14496                         err = pci_set_consistent_dma_mask(pdev,
14497                                                           persist_dma_mask);
14498                         if (err < 0) {
14499                                 printk(KERN_ERR PFX "Unable to obtain 64 bit "
14500                                        "DMA for consistent allocations\n");
14501                                 goto err_out_iounmap;
14502                         }
14503                 }
14504         }
14505         if (err || dma_mask == DMA_BIT_MASK(32)) {
14506                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
14507                 if (err) {
14508                         printk(KERN_ERR PFX "No usable DMA configuration, "
14509                                "aborting.\n");
14510                         goto err_out_iounmap;
14511                 }
14512         }
14513
14514         tg3_init_bufmgr_config(tp);
14515
14516         /* Selectively allow TSO based on operating conditions */
14517         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
14518             (tp->fw_needed && !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)))
14519                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
14520         else {
14521                 tp->tg3_flags2 &= ~(TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG);
14522                 tp->fw_needed = NULL;
14523         }
14524
14525         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
14526                 tp->fw_needed = FIRMWARE_TG3;
14527
14528         /* TSO is on by default on chips that support hardware TSO.
14529          * Firmware TSO on older chips gives lower performance, so it
14530          * is off by default, but can be enabled using ethtool.
14531          */
14532         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) &&
14533             (dev->features & NETIF_F_IP_CSUM))
14534                 dev->features |= NETIF_F_TSO;
14535
14536         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
14537             (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3)) {
14538                 if (dev->features & NETIF_F_IPV6_CSUM)
14539                         dev->features |= NETIF_F_TSO6;
14540                 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
14541                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
14542                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
14543                      GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
14544                         GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
14545                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
14546                         dev->features |= NETIF_F_TSO_ECN;
14547         }
14548
14549         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
14550             !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
14551             !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
14552                 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
14553                 tp->rx_pending = 63;
14554         }
14555
14556         err = tg3_get_device_address(tp);
14557         if (err) {
14558                 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
14559                        "aborting.\n");
14560                 goto err_out_iounmap;
14561         }
14562
14563         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
14564                 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
14565                 if (!tp->aperegs) {
14566                         printk(KERN_ERR PFX "Cannot map APE registers, "
14567                                "aborting.\n");
14568                         err = -ENOMEM;
14569                         goto err_out_iounmap;
14570                 }
14571
14572                 tg3_ape_lock_init(tp);
14573
14574                 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
14575                         tg3_read_dash_ver(tp);
14576         }
14577
14578         /*
14579          * Reset chip in case UNDI or EFI driver did not shutdown
14580          * DMA self test will enable WDMAC and we'll see (spurious)
14581          * pending DMA on the PCI bus at that point.
14582          */
14583         if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
14584             (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
14585                 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
14586                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14587         }
14588
14589         err = tg3_test_dma(tp);
14590         if (err) {
14591                 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
14592                 goto err_out_apeunmap;
14593         }
14594
14595         /* flow control autonegotiation is default behavior */
14596         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
14597         tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
14598
14599         intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
14600         rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
14601         sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
14602         for (i = 0; i < TG3_IRQ_MAX_VECS; i++) {
14603                 struct tg3_napi *tnapi = &tp->napi[i];
14604
14605                 tnapi->tp = tp;
14606                 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
14607
14608                 tnapi->int_mbox = intmbx;
14609                 if (i < 4)
14610                         intmbx += 0x8;
14611                 else
14612                         intmbx += 0x4;
14613
14614                 tnapi->consmbox = rcvmbx;
14615                 tnapi->prodmbox = sndmbx;
14616
14617                 if (i) {
14618                         tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
14619                         netif_napi_add(dev, &tnapi->napi, tg3_poll_msix, 64);
14620                 } else {
14621                         tnapi->coal_now = HOSTCC_MODE_NOW;
14622                         netif_napi_add(dev, &tnapi->napi, tg3_poll, 64);
14623                 }
14624
14625                 if (!(tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX))
14626                         break;
14627
14628                 /*
14629                  * If we support MSIX, we'll be using RSS.  If we're using
14630                  * RSS, the first vector only handles link interrupts and the
14631                  * remaining vectors handle rx and tx interrupts.  Reuse the
14632                  * mailbox values for the next iteration.  The values we setup
14633                  * above are still useful for the single vectored mode.
14634                  */
14635                 if (!i)
14636                         continue;
14637
14638                 rcvmbx += 0x8;
14639
14640                 if (sndmbx & 0x4)
14641                         sndmbx -= 0x4;
14642                 else
14643                         sndmbx += 0xc;
14644         }
14645
14646         tg3_init_coal(tp);
14647
14648         pci_set_drvdata(pdev, dev);
14649
14650         err = register_netdev(dev);
14651         if (err) {
14652                 printk(KERN_ERR PFX "Cannot register net device, "
14653                        "aborting.\n");
14654                 goto err_out_apeunmap;
14655         }
14656
14657         printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
14658                dev->name,
14659                tp->board_part_number,
14660                tp->pci_chip_rev_id,
14661                tg3_bus_string(tp, str),
14662                dev->dev_addr);
14663
14664         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
14665                 struct phy_device *phydev;
14666                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
14667                 printk(KERN_INFO
14668                        "%s: attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
14669                        tp->dev->name, phydev->drv->name,
14670                        dev_name(&phydev->dev));
14671         } else
14672                 printk(KERN_INFO
14673                        "%s: attached PHY is %s (%s Ethernet) (WireSpeed[%d])\n",
14674                        tp->dev->name, tg3_phy_string(tp),
14675                        ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
14676                         ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
14677                          "10/100/1000Base-T")),
14678                        (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0);
14679
14680         printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
14681                dev->name,
14682                (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
14683                (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
14684                (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
14685                (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
14686                (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
14687         printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
14688                dev->name, tp->dma_rwctrl,
14689                (pdev->dma_mask == DMA_BIT_MASK(32)) ? 32 :
14690                 (((u64) pdev->dma_mask == DMA_BIT_MASK(40)) ? 40 : 64));
14691
14692         return 0;
14693
14694 err_out_apeunmap:
14695         if (tp->aperegs) {
14696                 iounmap(tp->aperegs);
14697                 tp->aperegs = NULL;
14698         }
14699
14700 err_out_iounmap:
14701         if (tp->regs) {
14702                 iounmap(tp->regs);
14703                 tp->regs = NULL;
14704         }
14705
14706 err_out_free_dev:
14707         free_netdev(dev);
14708
14709 err_out_free_res:
14710         pci_release_regions(pdev);
14711
14712 err_out_disable_pdev:
14713         pci_disable_device(pdev);
14714         pci_set_drvdata(pdev, NULL);
14715         return err;
14716 }
14717
14718 static void __devexit tg3_remove_one(struct pci_dev *pdev)
14719 {
14720         struct net_device *dev = pci_get_drvdata(pdev);
14721
14722         if (dev) {
14723                 struct tg3 *tp = netdev_priv(dev);
14724
14725                 if (tp->fw)
14726                         release_firmware(tp->fw);
14727
14728                 flush_scheduled_work();
14729
14730                 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
14731                         tg3_phy_fini(tp);
14732                         tg3_mdio_fini(tp);
14733                 }
14734
14735                 unregister_netdev(dev);
14736                 if (tp->aperegs) {
14737                         iounmap(tp->aperegs);
14738                         tp->aperegs = NULL;
14739                 }
14740                 if (tp->regs) {
14741                         iounmap(tp->regs);
14742                         tp->regs = NULL;
14743                 }
14744                 free_netdev(dev);
14745                 pci_release_regions(pdev);
14746                 pci_disable_device(pdev);
14747                 pci_set_drvdata(pdev, NULL);
14748         }
14749 }
14750
14751 static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
14752 {
14753         struct net_device *dev = pci_get_drvdata(pdev);
14754         struct tg3 *tp = netdev_priv(dev);
14755         pci_power_t target_state;
14756         int err;
14757
14758         /* PCI register 4 needs to be saved whether netif_running() or not.
14759          * MSI address and data need to be saved if using MSI and
14760          * netif_running().
14761          */
14762         pci_save_state(pdev);
14763
14764         if (!netif_running(dev))
14765                 return 0;
14766
14767         flush_scheduled_work();
14768         tg3_phy_stop(tp);
14769         tg3_netif_stop(tp);
14770
14771         del_timer_sync(&tp->timer);
14772
14773         tg3_full_lock(tp, 1);
14774         tg3_disable_ints(tp);
14775         tg3_full_unlock(tp);
14776
14777         netif_device_detach(dev);
14778
14779         tg3_full_lock(tp, 0);
14780         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14781         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
14782         tg3_full_unlock(tp);
14783
14784         target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
14785
14786         err = tg3_set_power_state(tp, target_state);
14787         if (err) {
14788                 int err2;
14789
14790                 tg3_full_lock(tp, 0);
14791
14792                 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
14793                 err2 = tg3_restart_hw(tp, 1);
14794                 if (err2)
14795                         goto out;
14796
14797                 tp->timer.expires = jiffies + tp->timer_offset;
14798                 add_timer(&tp->timer);
14799
14800                 netif_device_attach(dev);
14801                 tg3_netif_start(tp);
14802
14803 out:
14804                 tg3_full_unlock(tp);
14805
14806                 if (!err2)
14807                         tg3_phy_start(tp);
14808         }
14809
14810         return err;
14811 }
14812
14813 static int tg3_resume(struct pci_dev *pdev)
14814 {
14815         struct net_device *dev = pci_get_drvdata(pdev);
14816         struct tg3 *tp = netdev_priv(dev);
14817         int err;
14818
14819         pci_restore_state(tp->pdev);
14820
14821         if (!netif_running(dev))
14822                 return 0;
14823
14824         err = tg3_set_power_state(tp, PCI_D0);
14825         if (err)
14826                 return err;
14827
14828         netif_device_attach(dev);
14829
14830         tg3_full_lock(tp, 0);
14831
14832         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
14833         err = tg3_restart_hw(tp, 1);
14834         if (err)
14835                 goto out;
14836
14837         tp->timer.expires = jiffies + tp->timer_offset;
14838         add_timer(&tp->timer);
14839
14840         tg3_netif_start(tp);
14841
14842 out:
14843         tg3_full_unlock(tp);
14844
14845         if (!err)
14846                 tg3_phy_start(tp);
14847
14848         return err;
14849 }
14850
14851 static struct pci_driver tg3_driver = {
14852         .name           = DRV_MODULE_NAME,
14853         .id_table       = tg3_pci_tbl,
14854         .probe          = tg3_init_one,
14855         .remove         = __devexit_p(tg3_remove_one),
14856         .suspend        = tg3_suspend,
14857         .resume         = tg3_resume
14858 };
14859
14860 static int __init tg3_init(void)
14861 {
14862         return pci_register_driver(&tg3_driver);
14863 }
14864
14865 static void __exit tg3_cleanup(void)
14866 {
14867         pci_unregister_driver(&tg3_driver);
14868 }
14869
14870 module_init(tg3_init);
14871 module_exit(tg3_cleanup);