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   1 /*
   2  * tc35815.c: A TOSHIBA TC35815CF PCI 10/100Mbps ethernet driver for linux.
   3  *
   4  * Based on skelton.c by Donald Becker.
   5  *
   6  * This driver is a replacement of older and less maintained version.
   7  * This is a header of the older version:
   8  *      -----<snip>-----
   9  *      Copyright 2001 MontaVista Software Inc.
  10  *      Author: MontaVista Software, Inc.
  11  *              ahennessy@mvista.com
  12  *      Copyright (C) 2000-2001 Toshiba Corporation
  13  *      static const char *version =
  14  *              "tc35815.c:v0.00 26/07/2000 by Toshiba Corporation\n";
  15  *      -----<snip>-----
  16  *
  17  * This file is subject to the terms and conditions of the GNU General Public
  18  * License.  See the file "COPYING" in the main directory of this archive
  19  * for more details.
  20  *
  21  * (C) Copyright TOSHIBA CORPORATION 2004-2005
  22  * All Rights Reserved.
  23  */
  24
  25 #define DRV_VERSION     "1.39"
  26 static const char *version = "tc35815.c:v" DRV_VERSION "\n";
  27 #define MODNAME                 "tc35815"
  28
  29 #include <linux/module.h>
  30 #include <linux/kernel.h>
  31 #include <linux/types.h>
  32 #include <linux/fcntl.h>
  33 #include <linux/interrupt.h>
  34 #include <linux/ioport.h>
  35 #include <linux/in.h>
  36 #include <linux/if_vlan.h>
  37 #include <linux/slab.h>
  38 #include <linux/string.h>
  39 #include <linux/spinlock.h>
  40 #include <linux/errno.h>
  41 #include <linux/init.h>
  42 #include <linux/netdevice.h>
  43 #include <linux/etherdevice.h>
  44 #include <linux/skbuff.h>
  45 #include <linux/delay.h>
  46 #include <linux/pci.h>
  47 #include <linux/phy.h>
  48 #include <linux/workqueue.h>
  49 #include <linux/platform_device.h>
  50 #include <asm/io.h>
  51 #include <asm/byteorder.h>
  52
  53 enum tc35815_chiptype {
  54         TC35815CF = 0,
  55         TC35815_NWU,
  56         TC35815_TX4939,
  57 };
  58
  59 /* indexed by tc35815_chiptype, above */
  60 static const struct {
  61         const char *name;
  62 } chip_info[] __devinitdata = {
  63         { "TOSHIBA TC35815CF 10/100BaseTX" },
  64         { "TOSHIBA TC35815 with Wake on LAN" },
  65         { "TOSHIBA TC35815/TX4939" },
  66 };
  67
  68 static DEFINE_PCI_DEVICE_TABLE(tc35815_pci_tbl) = {
  69         {PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_TC35815CF), .driver_data = TC35815CF },
  70         {PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_TC35815_NWU), .driver_data = TC35815_NWU },
  71         {PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_TC35815_TX4939), .driver_data = TC35815_TX4939 },
  72         {0,}
  73 };
  74 MODULE_DEVICE_TABLE(pci, tc35815_pci_tbl);
  75
  76 /* see MODULE_PARM_DESC */
  77 static struct tc35815_options {
  78         int speed;
  79         int duplex;
  80 } options;
  81
  82 /*
  83  * Registers
  84  */
  85 struct tc35815_regs {
  86         __u32 DMA_Ctl;          /* 0x00 */
  87         __u32 TxFrmPtr;
  88         __u32 TxThrsh;
  89         __u32 TxPollCtr;
  90         __u32 BLFrmPtr;
  91         __u32 RxFragSize;
  92         __u32 Int_En;
  93         __u32 FDA_Bas;
  94         __u32 FDA_Lim;          /* 0x20 */
  95         __u32 Int_Src;
  96         __u32 unused0[2];
  97         __u32 PauseCnt;
  98         __u32 RemPauCnt;
  99         __u32 TxCtlFrmStat;
 100         __u32 unused1;
 101         __u32 MAC_Ctl;          /* 0x40 */
 102         __u32 CAM_Ctl;
 103         __u32 Tx_Ctl;
 104         __u32 Tx_Stat;
 105         __u32 Rx_Ctl;
 106         __u32 Rx_Stat;
 107         __u32 MD_Data;
 108         __u32 MD_CA;
 109         __u32 CAM_Adr;          /* 0x60 */
 110         __u32 CAM_Data;
 111         __u32 CAM_Ena;
 112         __u32 PROM_Ctl;
 113         __u32 PROM_Data;
 114         __u32 Algn_Cnt;
 115         __u32 CRC_Cnt;
 116         __u32 Miss_Cnt;
 117 };
 118
 119 /*
 120  * Bit assignments
 121  */
 122 /* DMA_Ctl bit asign ------------------------------------------------------- */
 123 #define DMA_RxAlign            0x00c00000 /* 1:Reception Alignment           */
 124 #define DMA_RxAlign_1          0x00400000
 125 #define DMA_RxAlign_2          0x00800000
 126 #define DMA_RxAlign_3          0x00c00000
 127 #define DMA_M66EnStat          0x00080000 /* 1:66MHz Enable State            */
 128 #define DMA_IntMask            0x00040000 /* 1:Interupt mask                 */
 129 #define DMA_SWIntReq           0x00020000 /* 1:Software Interrupt request    */
 130 #define DMA_TxWakeUp           0x00010000 /* 1:Transmit Wake Up              */
 131 #define DMA_RxBigE             0x00008000 /* 1:Receive Big Endian            */
 132 #define DMA_TxBigE             0x00004000 /* 1:Transmit Big Endian           */
 133 #define DMA_TestMode           0x00002000 /* 1:Test Mode                     */
 134 #define DMA_PowrMgmnt          0x00001000 /* 1:Power Management              */
 135 #define DMA_DmBurst_Mask       0x000001fc /* DMA Burst size                  */
 136
 137 /* RxFragSize bit asign ---------------------------------------------------- */
 138 #define RxFrag_EnPack          0x00008000 /* 1:Enable Packing                */
 139 #define RxFrag_MinFragMask     0x00000ffc /* Minimum Fragment                */
 140
 141 /* MAC_Ctl bit asign ------------------------------------------------------- */
 142 #define MAC_Link10             0x00008000 /* 1:Link Status 10Mbits           */
 143 #define MAC_EnMissRoll         0x00002000 /* 1:Enable Missed Roll            */
 144 #define MAC_MissRoll           0x00000400 /* 1:Missed Roll                   */
 145 #define MAC_Loop10             0x00000080 /* 1:Loop 10 Mbps                  */
 146 #define MAC_Conn_Auto          0x00000000 /*00:Connection mode (Automatic)   */
 147 #define MAC_Conn_10M           0x00000020 /*01:                (10Mbps endec)*/
 148 #define MAC_Conn_Mll           0x00000040 /*10:                (Mll clock)   */
 149 #define MAC_MacLoop            0x00000010 /* 1:MAC Loopback                  */
 150 #define MAC_FullDup            0x00000008 /* 1:Full Duplex 0:Half Duplex     */
 151 #define MAC_Reset              0x00000004 /* 1:Software Reset                */
 152 #define MAC_HaltImm            0x00000002 /* 1:Halt Immediate                */
 153 #define MAC_HaltReq            0x00000001 /* 1:Halt request                  */
 154
 155 /* PROM_Ctl bit asign ------------------------------------------------------ */
 156 #define PROM_Busy              0x00008000 /* 1:Busy (Start Operation)        */
 157 #define PROM_Read              0x00004000 /*10:Read operation                */
 158 #define PROM_Write             0x00002000 /*01:Write operation               */
 159 #define PROM_Erase             0x00006000 /*11:Erase operation               */
 160                                           /*00:Enable or Disable Writting,   */
 161                                           /*      as specified in PROM_Addr. */
 162 #define PROM_Addr_Ena          0x00000030 /*11xxxx:PROM Write enable         */
 163                                           /*00xxxx:           disable        */
 164
 165 /* CAM_Ctl bit asign ------------------------------------------------------- */
 166 #define CAM_CompEn             0x00000010 /* 1:CAM Compare Enable            */
 167 #define CAM_NegCAM             0x00000008 /* 1:Reject packets CAM recognizes,*/
 168                                           /*                    accept other */
 169 #define CAM_BroadAcc           0x00000004 /* 1:Broadcast assept              */
 170 #define CAM_GroupAcc           0x00000002 /* 1:Multicast assept              */
 171 #define CAM_StationAcc         0x00000001 /* 1:unicast accept                */
 172
 173 /* CAM_Ena bit asign ------------------------------------------------------- */
 174 #define CAM_ENTRY_MAX                  21   /* CAM Data entry max count      */
 175 #define CAM_Ena_Mask ((1<<CAM_ENTRY_MAX)-1) /* CAM Enable bits (Max 21bits)  */
 176 #define CAM_Ena_Bit(index)      (1 << (index))
 177 #define CAM_ENTRY_DESTINATION   0
 178 #define CAM_ENTRY_SOURCE        1
 179 #define CAM_ENTRY_MACCTL        20
 180
 181 /* Tx_Ctl bit asign -------------------------------------------------------- */
 182 #define Tx_En                  0x00000001 /* 1:Transmit enable               */
 183 #define Tx_TxHalt              0x00000002 /* 1:Transmit Halt Request         */
 184 #define Tx_NoPad               0x00000004 /* 1:Suppress Padding              */
 185 #define Tx_NoCRC               0x00000008 /* 1:Suppress Padding              */
 186 #define Tx_FBack               0x00000010 /* 1:Fast Back-off                 */
 187 #define Tx_EnUnder             0x00000100 /* 1:Enable Underrun               */
 188 #define Tx_EnExDefer           0x00000200 /* 1:Enable Excessive Deferral     */
 189 #define Tx_EnLCarr             0x00000400 /* 1:Enable Lost Carrier           */
 190 #define Tx_EnExColl            0x00000800 /* 1:Enable Excessive Collision    */
 191 #define Tx_EnLateColl          0x00001000 /* 1:Enable Late Collision         */
 192 #define Tx_EnTxPar             0x00002000 /* 1:Enable Transmit Parity        */
 193 #define Tx_EnComp              0x00004000 /* 1:Enable Completion             */
 194
 195 /* Tx_Stat bit asign ------------------------------------------------------- */
 196 #define Tx_TxColl_MASK         0x0000000F /* Tx Collision Count              */
 197 #define Tx_ExColl              0x00000010 /* Excessive Collision             */
 198 #define Tx_TXDefer             0x00000020 /* Transmit Defered                */
 199 #define Tx_Paused              0x00000040 /* Transmit Paused                 */
 200 #define Tx_IntTx               0x00000080 /* Interrupt on Tx                 */
 201 #define Tx_Under               0x00000100 /* Underrun                        */
 202 #define Tx_Defer               0x00000200 /* Deferral                        */
 203 #define Tx_NCarr               0x00000400 /* No Carrier                      */
 204 #define Tx_10Stat              0x00000800 /* 10Mbps Status                   */
 205 #define Tx_LateColl            0x00001000 /* Late Collision                  */
 206 #define Tx_TxPar               0x00002000 /* Tx Parity Error                 */
 207 #define Tx_Comp                0x00004000 /* Completion                      */
 208 #define Tx_Halted              0x00008000 /* Tx Halted                       */
 209 #define Tx_SQErr               0x00010000 /* Signal Quality Error(SQE)       */
 210
 211 /* Rx_Ctl bit asign -------------------------------------------------------- */
 212 #define Rx_EnGood              0x00004000 /* 1:Enable Good                   */
 213 #define Rx_EnRxPar             0x00002000 /* 1:Enable Receive Parity         */
 214 #define Rx_EnLongErr           0x00000800 /* 1:Enable Long Error             */
 215 #define Rx_EnOver              0x00000400 /* 1:Enable OverFlow               */
 216 #define Rx_EnCRCErr            0x00000200 /* 1:Enable CRC Error              */
 217 #define Rx_EnAlign             0x00000100 /* 1:Enable Alignment              */
 218 #define Rx_IgnoreCRC           0x00000040 /* 1:Ignore CRC Value              */
 219 #define Rx_StripCRC            0x00000010 /* 1:Strip CRC Value               */
 220 #define Rx_ShortEn             0x00000008 /* 1:Short Enable                  */
 221 #define Rx_LongEn              0x00000004 /* 1:Long Enable                   */
 222 #define Rx_RxHalt              0x00000002 /* 1:Receive Halt Request          */
 223 #define Rx_RxEn                0x00000001 /* 1:Receive Intrrupt Enable       */
 224
 225 /* Rx_Stat bit asign ------------------------------------------------------- */
 226 #define Rx_Halted              0x00008000 /* Rx Halted                       */
 227 #define Rx_Good                0x00004000 /* Rx Good                         */
 228 #define Rx_RxPar               0x00002000 /* Rx Parity Error                 */
 229 #define Rx_TypePkt             0x00001000 /* Rx Type Packet                  */
 230 #define Rx_LongErr             0x00000800 /* Rx Long Error                   */
 231 #define Rx_Over                0x00000400 /* Rx Overflow                     */
 232 #define Rx_CRCErr              0x00000200 /* Rx CRC Error                    */
 233 #define Rx_Align               0x00000100 /* Rx Alignment Error              */
 234 #define Rx_10Stat              0x00000080 /* Rx 10Mbps Status                */
 235 #define Rx_IntRx               0x00000040 /* Rx Interrupt                    */
 236 #define Rx_CtlRecd             0x00000020 /* Rx Control Receive              */
 237 #define Rx_InLenErr            0x00000010 /* Rx In Range Frame Length Error  */
 238
 239 #define Rx_Stat_Mask           0x0000FFF0 /* Rx All Status Mask              */
 240
 241 /* Int_En bit asign -------------------------------------------------------- */
 242 #define Int_NRAbtEn            0x00000800 /* 1:Non-recoverable Abort Enable  */
 243 #define Int_TxCtlCmpEn         0x00000400 /* 1:Transmit Ctl Complete Enable  */
 244 #define Int_DmParErrEn         0x00000200 /* 1:DMA Parity Error Enable       */
 245 #define Int_DParDEn            0x00000100 /* 1:Data Parity Error Enable      */
 246 #define Int_EarNotEn           0x00000080 /* 1:Early Notify Enable           */
 247 #define Int_DParErrEn          0x00000040 /* 1:Detected Parity Error Enable  */
 248 #define Int_SSysErrEn          0x00000020 /* 1:Signalled System Error Enable */
 249 #define Int_RMasAbtEn          0x00000010 /* 1:Received Master Abort Enable  */
 250 #define Int_RTargAbtEn         0x00000008 /* 1:Received Target Abort Enable  */
 251 #define Int_STargAbtEn         0x00000004 /* 1:Signalled Target Abort Enable */
 252 #define Int_BLExEn             0x00000002 /* 1:Buffer List Exhausted Enable  */
 253 #define Int_FDAExEn            0x00000001 /* 1:Free Descriptor Area          */
 254                                           /*               Exhausted Enable  */
 255
 256 /* Int_Src bit asign ------------------------------------------------------- */
 257 #define Int_NRabt              0x00004000 /* 1:Non Recoverable error         */
 258 #define Int_DmParErrStat       0x00002000 /* 1:DMA Parity Error & Clear      */
 259 #define Int_BLEx               0x00001000 /* 1:Buffer List Empty & Clear     */
 260 #define Int_FDAEx              0x00000800 /* 1:FDA Empty & Clear             */
 261 #define Int_IntNRAbt           0x00000400 /* 1:Non Recoverable Abort         */
 262 #define Int_IntCmp             0x00000200 /* 1:MAC control packet complete   */
 263 #define Int_IntExBD            0x00000100 /* 1:Interrupt Extra BD & Clear    */
 264 #define Int_DmParErr           0x00000080 /* 1:DMA Parity Error & Clear      */
 265 #define Int_IntEarNot          0x00000040 /* 1:Receive Data write & Clear    */
 266 #define Int_SWInt              0x00000020 /* 1:Software request & Clear      */
 267 #define Int_IntBLEx            0x00000010 /* 1:Buffer List Empty & Clear     */
 268 #define Int_IntFDAEx           0x00000008 /* 1:FDA Empty & Clear             */
 269 #define Int_IntPCI             0x00000004 /* 1:PCI controller & Clear        */
 270 #define Int_IntMacRx           0x00000002 /* 1:Rx controller & Clear         */
 271 #define Int_IntMacTx           0x00000001 /* 1:Tx controller & Clear         */
 272
 273 /* MD_CA bit asign --------------------------------------------------------- */
 274 #define MD_CA_PreSup           0x00001000 /* 1:Preamble Supress              */
 275 #define MD_CA_Busy             0x00000800 /* 1:Busy (Start Operation)        */
 276 #define MD_CA_Wr               0x00000400 /* 1:Write 0:Read                  */
 277
 278
 279 /*
 280  * Descriptors
 281  */
 282
 283 /* Frame descripter */
 284 struct FDesc {
 285         volatile __u32 FDNext;
 286         volatile __u32 FDSystem;
 287         volatile __u32 FDStat;
 288         volatile __u32 FDCtl;
 289 };
 290
 291 /* Buffer descripter */
 292 struct BDesc {
 293         volatile __u32 BuffData;
 294         volatile __u32 BDCtl;
 295 };
 296
 297 #define FD_ALIGN        16
 298
 299 /* Frame Descripter bit asign ---------------------------------------------- */
 300 #define FD_FDLength_MASK       0x0000FFFF /* Length MASK                     */
 301 #define FD_BDCnt_MASK          0x001F0000 /* BD count MASK in FD             */
 302 #define FD_FrmOpt_MASK         0x7C000000 /* Frame option MASK               */
 303 #define FD_FrmOpt_BigEndian    0x40000000 /* Tx/Rx */
 304 #define FD_FrmOpt_IntTx        0x20000000 /* Tx only */
 305 #define FD_FrmOpt_NoCRC        0x10000000 /* Tx only */
 306 #define FD_FrmOpt_NoPadding    0x08000000 /* Tx only */
 307 #define FD_FrmOpt_Packing      0x04000000 /* Rx only */
 308 #define FD_CownsFD             0x80000000 /* FD Controller owner bit         */
 309 #define FD_Next_EOL            0x00000001 /* FD EOL indicator                */
 310 #define FD_BDCnt_SHIFT         16
 311
 312 /* Buffer Descripter bit asign --------------------------------------------- */
 313 #define BD_BuffLength_MASK     0x0000FFFF /* Recieve Data Size               */
 314 #define BD_RxBDID_MASK         0x00FF0000 /* BD ID Number MASK               */
 315 #define BD_RxBDSeqN_MASK       0x7F000000 /* Rx BD Sequence Number           */
 316 #define BD_CownsBD             0x80000000 /* BD Controller owner bit         */
 317 #define BD_RxBDID_SHIFT        16
 318 #define BD_RxBDSeqN_SHIFT      24
 319
 320
 321 /* Some useful constants. */
 322
 323 #define TX_CTL_CMD      (Tx_EnTxPar | Tx_EnLateColl | \
 324         Tx_EnExColl | Tx_EnLCarr | Tx_EnExDefer | Tx_EnUnder | \
 325         Tx_En)  /* maybe  0x7b01 */
 326 /* Do not use Rx_StripCRC -- it causes trouble on BLEx/FDAEx condition */
 327 #define RX_CTL_CMD      (Rx_EnGood | Rx_EnRxPar | Rx_EnLongErr | Rx_EnOver \
 328         | Rx_EnCRCErr | Rx_EnAlign | Rx_RxEn) /* maybe 0x6f01 */
 329 #define INT_EN_CMD  (Int_NRAbtEn | \
 330         Int_DmParErrEn | Int_DParDEn | Int_DParErrEn | \
 331         Int_SSysErrEn  | Int_RMasAbtEn | Int_RTargAbtEn | \
 332         Int_STargAbtEn | \
 333         Int_BLExEn  | Int_FDAExEn) /* maybe 0xb7f*/
 334 #define DMA_CTL_CMD     DMA_BURST_SIZE
 335 #define HAVE_DMA_RXALIGN(lp)    likely((lp)->chiptype != TC35815CF)
 336
 337 /* Tuning parameters */
 338 #define DMA_BURST_SIZE  32
 339 #define TX_THRESHOLD    1024
 340 /* used threshold with packet max byte for low pci transfer ability.*/
 341 #define TX_THRESHOLD_MAX 1536
 342 /* setting threshold max value when overrun error occured this count. */
 343 #define TX_THRESHOLD_KEEP_LIMIT 10
 344
 345 /* 16 + RX_BUF_NUM * 8 + RX_FD_NUM * 16 + TX_FD_NUM * 32 <= PAGE_SIZE*FD_PAGE_NUM */
 346 #define FD_PAGE_NUM 4
 347 #define RX_BUF_NUM      128     /* < 256 */
 348 #define RX_FD_NUM       256     /* >= 32 */
 349 #define TX_FD_NUM       128
 350 #if RX_CTL_CMD & Rx_LongEn
 351 #define RX_BUF_SIZE     PAGE_SIZE
 352 #elif RX_CTL_CMD & Rx_StripCRC
 353 #define RX_BUF_SIZE     \
 354         L1_CACHE_ALIGN(ETH_FRAME_LEN + VLAN_HLEN + NET_IP_ALIGN)
 355 #else
 356 #define RX_BUF_SIZE     \
 357         L1_CACHE_ALIGN(ETH_FRAME_LEN + VLAN_HLEN + ETH_FCS_LEN + NET_IP_ALIGN)
 358 #endif
 359 #define RX_FD_RESERVE   (2 / 2) /* max 2 BD per RxFD */
 360 #define NAPI_WEIGHT     16
 361
 362 struct TxFD {
 363         struct FDesc fd;
 364         struct BDesc bd;
 365         struct BDesc unused;
 366 };
 367
 368 struct RxFD {
 369         struct FDesc fd;
 370         struct BDesc bd[0];     /* variable length */
 371 };
 372
 373 struct FrFD {
 374         struct FDesc fd;
 375         struct BDesc bd[RX_BUF_NUM];
 376 };
 377
 378
 379 #define tc_readl(addr)  ioread32(addr)
 380 #define tc_writel(d, addr)      iowrite32(d, addr)
 381
 382 #define TC35815_TX_TIMEOUT  msecs_to_jiffies(400)
 383
 384 /* Information that need to be kept for each controller. */
 385 struct tc35815_local {
 386         struct pci_dev *pci_dev;
 387
 388         struct net_device *dev;
 389         struct napi_struct napi;
 390
 391         /* statistics */
 392         struct {
 393                 int max_tx_qlen;
 394                 int tx_ints;
 395                 int rx_ints;
 396                 int tx_underrun;
 397         } lstats;
 398
 399         /* Tx control lock.  This protects the transmit buffer ring
 400          * state along with the "tx full" state of the driver.  This
 401          * means all netif_queue flow control actions are protected
 402          * by this lock as well.
 403          */
 404         spinlock_t lock;
 405
 406         struct mii_bus *mii_bus;
 407         struct phy_device *phy_dev;
 408         int duplex;
 409         int speed;
 410         int link;
 411         struct work_struct restart_work;
 412
 413         /*
 414          * Transmitting: Batch Mode.
 415          *      1 BD in 1 TxFD.
 416          * Receiving: Non-Packing Mode.
 417          *      1 circular FD for Free Buffer List.
 418          *      RX_BUF_NUM BD in Free Buffer FD.
 419          *      One Free Buffer BD has ETH_FRAME_LEN data buffer.
 420          */
 421         void *fd_buf;   /* for TxFD, RxFD, FrFD */
 422         dma_addr_t fd_buf_dma;
 423         struct TxFD *tfd_base;
 424         unsigned int tfd_start;
 425         unsigned int tfd_end;
 426         struct RxFD *rfd_base;
 427         struct RxFD *rfd_limit;
 428         struct RxFD *rfd_cur;
 429         struct FrFD *fbl_ptr;
 430         unsigned int fbl_count;
 431         struct {
 432                 struct sk_buff *skb;
 433                 dma_addr_t skb_dma;
 434         } tx_skbs[TX_FD_NUM], rx_skbs[RX_BUF_NUM];
 435         u32 msg_enable;
 436         enum tc35815_chiptype chiptype;
 437 };
 438
 439 static inline dma_addr_t fd_virt_to_bus(struct tc35815_local *lp, void *virt)
 440 {
 441         return lp->fd_buf_dma + ((u8 *)virt - (u8 *)lp->fd_buf);
 442 }
 443 #ifdef DEBUG
 444 static inline void *fd_bus_to_virt(struct tc35815_local *lp, dma_addr_t bus)
 445 {
 446         return (void *)((u8 *)lp->fd_buf + (bus - lp->fd_buf_dma));
 447 }
 448 #endif
 449 static struct sk_buff *alloc_rxbuf_skb(struct net_device *dev,
 450                                        struct pci_dev *hwdev,
 451                                        dma_addr_t *dma_handle)
 452 {
 453         struct sk_buff *skb;
 454         skb = dev_alloc_skb(RX_BUF_SIZE);
 455         if (!skb)
 456                 return NULL;
 457         *dma_handle = pci_map_single(hwdev, skb->data, RX_BUF_SIZE,
 458                                      PCI_DMA_FROMDEVICE);
 459         if (pci_dma_mapping_error(hwdev, *dma_handle)) {
 460                 dev_kfree_skb_any(skb);
 461                 return NULL;
 462         }
 463         skb_reserve(skb, 2);    /* make IP header 4byte aligned */
 464         return skb;
 465 }
 466
 467 static void free_rxbuf_skb(struct pci_dev *hwdev, struct sk_buff *skb, dma_addr_t dma_handle)
 468 {
 469         pci_unmap_single(hwdev, dma_handle, RX_BUF_SIZE,
 470                          PCI_DMA_FROMDEVICE);
 471         dev_kfree_skb_any(skb);
 472 }
 473
 474 /* Index to functions, as function prototypes. */
 475
 476 static int      tc35815_open(struct net_device *dev);
 477 static int      tc35815_send_packet(struct sk_buff *skb, struct net_device *dev);
 478 static irqreturn_t      tc35815_interrupt(int irq, void *dev_id);
 479 static int      tc35815_rx(struct net_device *dev, int limit);
 480 static int      tc35815_poll(struct napi_struct *napi, int budget);
 481 static void     tc35815_txdone(struct net_device *dev);
 482 static int      tc35815_close(struct net_device *dev);
 483 static struct   net_device_stats *tc35815_get_stats(struct net_device *dev);
 484 static void     tc35815_set_multicast_list(struct net_device *dev);
 485 static void     tc35815_tx_timeout(struct net_device *dev);
 486 static int      tc35815_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
 487 #ifdef CONFIG_NET_POLL_CONTROLLER
 488 static void     tc35815_poll_controller(struct net_device *dev);
 489 #endif
 490 static const struct ethtool_ops tc35815_ethtool_ops;
 491
 492 /* Example routines you must write ;->. */
 493 static void     tc35815_chip_reset(struct net_device *dev);
 494 static void     tc35815_chip_init(struct net_device *dev);
 495
 496 #ifdef DEBUG
 497 static void     panic_queues(struct net_device *dev);
 498 #endif
 499
 500 static void tc35815_restart_work(struct work_struct *work);
 501
 502 static int tc_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
 503 {
 504         struct net_device *dev = bus->priv;
 505         struct tc35815_regs __iomem *tr =
 506                 (struct tc35815_regs __iomem *)dev->base_addr;
 507         unsigned long timeout = jiffies + HZ;
 508
 509         tc_writel(MD_CA_Busy | (mii_id << 5) | (regnum & 0x1f), &tr->MD_CA);
 510         udelay(12); /* it takes 32 x 400ns at least */
 511         while (tc_readl(&tr->MD_CA) & MD_CA_Busy) {
 512                 if (time_after(jiffies, timeout))
 513                         return -EIO;
 514                 cpu_relax();
 515         }
 516         return tc_readl(&tr->MD_Data) & 0xffff;
 517 }
 518
 519 static int tc_mdio_write(struct mii_bus *bus, int mii_id, int regnum, u16 val)
 520 {
 521         struct net_device *dev = bus->priv;
 522         struct tc35815_regs __iomem *tr =
 523                 (struct tc35815_regs __iomem *)dev->base_addr;
 524         unsigned long timeout = jiffies + HZ;
 525
 526         tc_writel(val, &tr->MD_Data);
 527         tc_writel(MD_CA_Busy | MD_CA_Wr | (mii_id << 5) | (regnum & 0x1f),
 528                   &tr->MD_CA);
 529         udelay(12); /* it takes 32 x 400ns at least */
 530         while (tc_readl(&tr->MD_CA) & MD_CA_Busy) {
 531                 if (time_after(jiffies, timeout))
 532                         return -EIO;
 533                 cpu_relax();
 534         }
 535         return 0;
 536 }
 537
 538 static void tc_handle_link_change(struct net_device *dev)
 539 {
 540         struct tc35815_local *lp = netdev_priv(dev);
 541         struct phy_device *phydev = lp->phy_dev;
 542         unsigned long flags;
 543         int status_change = 0;
 544
 545         spin_lock_irqsave(&lp->lock, flags);
 546         if (phydev->link &&
 547             (lp->speed != phydev->speed || lp->duplex != phydev->duplex)) {
 548                 struct tc35815_regs __iomem *tr =
 549                         (struct tc35815_regs __iomem *)dev->base_addr;
 550                 u32 reg;
 551
 552                 reg = tc_readl(&tr->MAC_Ctl);
 553                 reg |= MAC_HaltReq;
 554                 tc_writel(reg, &tr->MAC_Ctl);
 555                 if (phydev->duplex == DUPLEX_FULL)
 556                         reg |= MAC_FullDup;
 557                 else
 558                         reg &= ~MAC_FullDup;
 559                 tc_writel(reg, &tr->MAC_Ctl);
 560                 reg &= ~MAC_HaltReq;
 561                 tc_writel(reg, &tr->MAC_Ctl);
 562
 563                 /*
 564                  * TX4939 PCFG.SPEEDn bit will be changed on
 565                  * NETDEV_CHANGE event.
 566                  */
 567                 /*
 568                  * WORKAROUND: enable LostCrS only if half duplex
 569                  * operation.
 570                  * (TX4939 does not have EnLCarr)
 571                  */
 572                 if (phydev->duplex == DUPLEX_HALF &&
 573                     lp->chiptype != TC35815_TX4939)
 574                         tc_writel(tc_readl(&tr->Tx_Ctl) | Tx_EnLCarr,
 575                                   &tr->Tx_Ctl);
 576
 577                 lp->speed = phydev->speed;
 578                 lp->duplex = phydev->duplex;
 579                 status_change = 1;
 580         }
 581
 582         if (phydev->link != lp->link) {
 583                 if (phydev->link) {
 584                         /* delayed promiscuous enabling */
 585                         if (dev->flags & IFF_PROMISC)
 586                                 tc35815_set_multicast_list(dev);
 587                 } else {
 588                         lp->speed = 0;
 589                         lp->duplex = -1;
 590                 }
 591                 lp->link = phydev->link;
 592
 593                 status_change = 1;
 594         }
 595         spin_unlock_irqrestore(&lp->lock, flags);
 596
 597         if (status_change && netif_msg_link(lp)) {
 598                 phy_print_status(phydev);
 599                 pr_debug("%s: MII BMCR %04x BMSR %04x LPA %04x\n",
 600                          dev->name,
 601                          phy_read(phydev, MII_BMCR),
 602                          phy_read(phydev, MII_BMSR),
 603                          phy_read(phydev, MII_LPA));
 604         }
 605 }
 606
 607 static int tc_mii_probe(struct net_device *dev)
 608 {
 609         struct tc35815_local *lp = netdev_priv(dev);
 610         struct phy_device *phydev = NULL;
 611         int phy_addr;
 612         u32 dropmask;
 613
 614         /* find the first phy */
 615         for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) {
 616                 if (lp->mii_bus->phy_map[phy_addr]) {
 617                         if (phydev) {
 618                                 printk(KERN_ERR "%s: multiple PHYs found\n",
 619                                        dev->name);
 620                                 return -EINVAL;
 621                         }
 622                         phydev = lp->mii_bus->phy_map[phy_addr];
 623                         break;
 624                 }
 625         }
 626
 627         if (!phydev) {
 628                 printk(KERN_ERR "%s: no PHY found\n", dev->name);
 629                 return -ENODEV;
 630         }
 631
 632         /* attach the mac to the phy */
 633         phydev = phy_connect(dev, dev_name(&phydev->dev),
 634                              &tc_handle_link_change, 0,
 635                              lp->chiptype == TC35815_TX4939 ?
 636                              PHY_INTERFACE_MODE_RMII : PHY_INTERFACE_MODE_MII);
 637         if (IS_ERR(phydev)) {
 638                 printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
 639                 return PTR_ERR(phydev);
 640         }
 641         printk(KERN_INFO "%s: attached PHY driver [%s] "
 642                 "(mii_bus:phy_addr=%s, id=%x)\n",
 643                 dev->name, phydev->drv->name, dev_name(&phydev->dev),
 644                 phydev->phy_id);
 645
 646         /* mask with MAC supported features */
 647         phydev->supported &= PHY_BASIC_FEATURES;
 648         dropmask = 0;
 649         if (options.speed == 10)
 650                 dropmask |= SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full;
 651         else if (options.speed == 100)
 652                 dropmask |= SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full;
 653         if (options.duplex == 1)
 654                 dropmask |= SUPPORTED_10baseT_Full | SUPPORTED_100baseT_Full;
 655         else if (options.duplex == 2)
 656                 dropmask |= SUPPORTED_10baseT_Half | SUPPORTED_100baseT_Half;
 657         phydev->supported &= ~dropmask;
 658         phydev->advertising = phydev->supported;
 659
 660         lp->link = 0;
 661         lp->speed = 0;
 662         lp->duplex = -1;
 663         lp->phy_dev = phydev;
 664
 665         return 0;
 666 }
 667
 668 static int tc_mii_init(struct net_device *dev)
 669 {
 670         struct tc35815_local *lp = netdev_priv(dev);
 671         int err;
 672         int i;
 673
 674         lp->mii_bus = mdiobus_alloc();
 675         if (lp->mii_bus == NULL) {
 676                 err = -ENOMEM;
 677                 goto err_out;
 678         }
 679
 680         lp->mii_bus->name = "tc35815_mii_bus";
 681         lp->mii_bus->read = tc_mdio_read;
 682         lp->mii_bus->write = tc_mdio_write;
 683         snprintf(lp->mii_bus->id, MII_BUS_ID_SIZE, "%x",
 684                  (lp->pci_dev->bus->number << 8) | lp->pci_dev->devfn);
 685         lp->mii_bus->priv = dev;
 686         lp->mii_bus->parent = &lp->pci_dev->dev;
 687         lp->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
 688         if (!lp->mii_bus->irq) {
 689                 err = -ENOMEM;
 690                 goto err_out_free_mii_bus;
 691         }
 692
 693         for (i = 0; i < PHY_MAX_ADDR; i++)
 694                 lp->mii_bus->irq[i] = PHY_POLL;
 695
 696         err = mdiobus_register(lp->mii_bus);
 697         if (err)
 698                 goto err_out_free_mdio_irq;
 699         err = tc_mii_probe(dev);
 700         if (err)
 701                 goto err_out_unregister_bus;
 702         return 0;
 703
 704 err_out_unregister_bus:
 705         mdiobus_unregister(lp->mii_bus);
 706 err_out_free_mdio_irq:
 707         kfree(lp->mii_bus->irq);
 708 err_out_free_mii_bus:
 709         mdiobus_free(lp->mii_bus);
 710 err_out:
 711         return err;
 712 }
 713
 714 #ifdef CONFIG_CPU_TX49XX
 715 /*
 716  * Find a platform_device providing a MAC address.  The platform code
 717  * should provide a "tc35815-mac" device with a MAC address in its
 718  * platform_data.
 719  */
 720 static int __devinit tc35815_mac_match(struct device *dev, void *data)
 721 {
 722         struct platform_device *plat_dev = to_platform_device(dev);
 723         struct pci_dev *pci_dev = data;
 724         unsigned int id = pci_dev->irq;
 725         return !strcmp(plat_dev->name, "tc35815-mac") && plat_dev->id == id;
 726 }
 727
 728 static int __devinit tc35815_read_plat_dev_addr(struct net_device *dev)
 729 {
 730         struct tc35815_local *lp = netdev_priv(dev);
 731         struct device *pd = bus_find_device(&platform_bus_type, NULL,
 732                                             lp->pci_dev, tc35815_mac_match);
 733         if (pd) {
 734                 if (pd->platform_data)
 735                         memcpy(dev->dev_addr, pd->platform_data, ETH_ALEN);
 736                 put_device(pd);
 737                 return is_valid_ether_addr(dev->dev_addr) ? 0 : -ENODEV;
 738         }
 739         return -ENODEV;
 740 }
 741 #else
 742 static int __devinit tc35815_read_plat_dev_addr(struct net_device *dev)
 743 {
 744         return -ENODEV;
 745 }
 746 #endif
 747
 748 static int __devinit tc35815_init_dev_addr(struct net_device *dev)
 749 {
 750         struct tc35815_regs __iomem *tr =
 751                 (struct tc35815_regs __iomem *)dev->base_addr;
 752         int i;
 753
 754         while (tc_readl(&tr->PROM_Ctl) & PROM_Busy)
 755                 ;
 756         for (i = 0; i < 6; i += 2) {
 757                 unsigned short data;
 758                 tc_writel(PROM_Busy | PROM_Read | (i / 2 + 2), &tr->PROM_Ctl);
 759                 while (tc_readl(&tr->PROM_Ctl) & PROM_Busy)
 760                         ;
 761                 data = tc_readl(&tr->PROM_Data);
 762                 dev->dev_addr[i] = data & 0xff;
 763                 dev->dev_addr[i+1] = data >> 8;
 764         }
 765         if (!is_valid_ether_addr(dev->dev_addr))
 766                 return tc35815_read_plat_dev_addr(dev);
 767         return 0;
 768 }
 769
 770 static const struct net_device_ops tc35815_netdev_ops = {
 771         .ndo_open               = tc35815_open,
 772         .ndo_stop               = tc35815_close,
 773         .ndo_start_xmit         = tc35815_send_packet,
 774         .ndo_get_stats          = tc35815_get_stats,
 775         .ndo_set_multicast_list = tc35815_set_multicast_list,
 776         .ndo_tx_timeout         = tc35815_tx_timeout,
 777         .ndo_do_ioctl           = tc35815_ioctl,
 778         .ndo_validate_addr      = eth_validate_addr,
 779         .ndo_change_mtu         = eth_change_mtu,
 780         .ndo_set_mac_address    = eth_mac_addr,
 781 #ifdef CONFIG_NET_POLL_CONTROLLER
 782         .ndo_poll_controller    = tc35815_poll_controller,
 783 #endif
 784 };
 785
 786 static int __devinit tc35815_init_one(struct pci_dev *pdev,
 787                                       const struct pci_device_id *ent)
 788 {
 789         void __iomem *ioaddr = NULL;
 790         struct net_device *dev;
 791         struct tc35815_local *lp;
 792         int rc;
 793
 794         static int printed_version;
 795         if (!printed_version++) {
 796                 printk(version);
 797                 dev_printk(KERN_DEBUG, &pdev->dev,
 798                            "speed:%d duplex:%d\n",
 799                            options.speed, options.duplex);
 800         }
 801
 802         if (!pdev->irq) {
 803                 dev_warn(&pdev->dev, "no IRQ assigned.\n");
 804                 return -ENODEV;
 805         }
 806
 807         /* dev zeroed in alloc_etherdev */
 808         dev = alloc_etherdev(sizeof(*lp));
 809         if (dev == NULL) {
 810                 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
 811                 return -ENOMEM;
 812         }
 813         SET_NETDEV_DEV(dev, &pdev->dev);
 814         lp = netdev_priv(dev);
 815         lp->dev = dev;
 816
 817         /* enable device (incl. PCI PM wakeup), and bus-mastering */
 818         rc = pcim_enable_device(pdev);
 819         if (rc)
 820                 goto err_out;
 821         rc = pcim_iomap_regions(pdev, 1 << 1, MODNAME);
 822         if (rc)
 823                 goto err_out;
 824         pci_set_master(pdev);
 825         ioaddr = pcim_iomap_table(pdev)[1];
 826
 827         /* Initialize the device structure. */
 828         dev->netdev_ops = &tc35815_netdev_ops;
 829         dev->ethtool_ops = &tc35815_ethtool_ops;
 830         dev->watchdog_timeo = TC35815_TX_TIMEOUT;
 831         netif_napi_add(dev, &lp->napi, tc35815_poll, NAPI_WEIGHT);
 832
 833         dev->irq = pdev->irq;
 834         dev->base_addr = (unsigned long)ioaddr;
 835
 836         INIT_WORK(&lp->restart_work, tc35815_restart_work);
 837         spin_lock_init(&lp->lock);
 838         lp->pci_dev = pdev;
 839         lp->chiptype = ent->driver_data;
 840
 841         lp->msg_enable = NETIF_MSG_TX_ERR | NETIF_MSG_HW | NETIF_MSG_DRV | NETIF_MSG_LINK;
 842         pci_set_drvdata(pdev, dev);
 843
 844         /* Soft reset the chip. */
 845         tc35815_chip_reset(dev);
 846
 847         /* Retrieve the ethernet address. */
 848         if (tc35815_init_dev_addr(dev)) {
 849                 dev_warn(&pdev->dev, "not valid ether addr\n");
 850                 random_ether_addr(dev->dev_addr);
 851         }
 852
 853         rc = register_netdev(dev);
 854         if (rc)
 855                 goto err_out;
 856
 857         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
 858         printk(KERN_INFO "%s: %s at 0x%lx, %pM, IRQ %d\n",
 859                 dev->name,
 860                 chip_info[ent->driver_data].name,
 861                 dev->base_addr,
 862                 dev->dev_addr,
 863                 dev->irq);
 864
 865         rc = tc_mii_init(dev);
 866         if (rc)
 867                 goto err_out_unregister;
 868
 869         return 0;
 870
 871 err_out_unregister:
 872         unregister_netdev(dev);
 873 err_out:
 874         free_netdev(dev);
 875         return rc;
 876 }
 877
 878
 879 static void __devexit tc35815_remove_one(struct pci_dev *pdev)
 880 {
 881         struct net_device *dev = pci_get_drvdata(pdev);
 882         struct tc35815_local *lp = netdev_priv(dev);
 883
 884         phy_disconnect(lp->phy_dev);
 885         mdiobus_unregister(lp->mii_bus);
 886         kfree(lp->mii_bus->irq);
 887         mdiobus_free(lp->mii_bus);
 888         unregister_netdev(dev);
 889         free_netdev(dev);
 890         pci_set_drvdata(pdev, NULL);
 891 }
 892
 893 static int
 894 tc35815_init_queues(struct net_device *dev)
 895 {
 896         struct tc35815_local *lp = netdev_priv(dev);
 897         int i;
 898         unsigned long fd_addr;
 899
 900         if (!lp->fd_buf) {
 901                 BUG_ON(sizeof(struct FDesc) +
 902                        sizeof(struct BDesc) * RX_BUF_NUM +
 903                        sizeof(struct FDesc) * RX_FD_NUM +
 904                        sizeof(struct TxFD) * TX_FD_NUM >
 905                        PAGE_SIZE * FD_PAGE_NUM);
 906
 907                 lp->fd_buf = pci_alloc_consistent(lp->pci_dev,
 908                                                   PAGE_SIZE * FD_PAGE_NUM,
 909                                                   &lp->fd_buf_dma);
 910                 if (!lp->fd_buf)
 911                         return -ENOMEM;
 912                 for (i = 0; i < RX_BUF_NUM; i++) {
 913                         lp->rx_skbs[i].skb =
 914                                 alloc_rxbuf_skb(dev, lp->pci_dev,
 915                                                 &lp->rx_skbs[i].skb_dma);
 916                         if (!lp->rx_skbs[i].skb) {
 917                                 while (--i >= 0) {
 918                                         free_rxbuf_skb(lp->pci_dev,
 919                                                        lp->rx_skbs[i].skb,
 920                                                        lp->rx_skbs[i].skb_dma);
 921                                         lp->rx_skbs[i].skb = NULL;
 922                                 }
 923                                 pci_free_consistent(lp->pci_dev,
 924                                                     PAGE_SIZE * FD_PAGE_NUM,
 925                                                     lp->fd_buf,
 926                                                     lp->fd_buf_dma);
 927                                 lp->fd_buf = NULL;
 928                                 return -ENOMEM;
 929                         }
 930                 }
 931                 printk(KERN_DEBUG "%s: FD buf %p DataBuf",
 932                        dev->name, lp->fd_buf);
 933                 printk("\n");
 934         } else {
 935                 for (i = 0; i < FD_PAGE_NUM; i++)
 936                         clear_page((void *)((unsigned long)lp->fd_buf +
 937                                             i * PAGE_SIZE));
 938         }
 939         fd_addr = (unsigned long)lp->fd_buf;
 940
 941         /* Free Descriptors (for Receive) */
 942         lp->rfd_base = (struct RxFD *)fd_addr;
 943         fd_addr += sizeof(struct RxFD) * RX_FD_NUM;
 944         for (i = 0; i < RX_FD_NUM; i++)
 945                 lp->rfd_base[i].fd.FDCtl = cpu_to_le32(FD_CownsFD);
 946         lp->rfd_cur = lp->rfd_base;
 947         lp->rfd_limit = (struct RxFD *)fd_addr - (RX_FD_RESERVE + 1);
 948
 949         /* Transmit Descriptors */
 950         lp->tfd_base = (struct TxFD *)fd_addr;
 951         fd_addr += sizeof(struct TxFD) * TX_FD_NUM;
 952         for (i = 0; i < TX_FD_NUM; i++) {
 953                 lp->tfd_base[i].fd.FDNext = cpu_to_le32(fd_virt_to_bus(lp, &lp->tfd_base[i+1]));
 954                 lp->tfd_base[i].fd.FDSystem = cpu_to_le32(0xffffffff);
 955                 lp->tfd_base[i].fd.FDCtl = cpu_to_le32(0);
 956         }
 957         lp->tfd_base[TX_FD_NUM-1].fd.FDNext = cpu_to_le32(fd_virt_to_bus(lp, &lp->tfd_base[0]));
 958         lp->tfd_start = 0;
 959         lp->tfd_end = 0;
 960
 961         /* Buffer List (for Receive) */
 962         lp->fbl_ptr = (struct FrFD *)fd_addr;
 963         lp->fbl_ptr->fd.FDNext = cpu_to_le32(fd_virt_to_bus(lp, lp->fbl_ptr));
 964         lp->fbl_ptr->fd.FDCtl = cpu_to_le32(RX_BUF_NUM | FD_CownsFD);
 965         /*
 966          * move all allocated skbs to head of rx_skbs[] array.
 967          * fbl_count mighe not be RX_BUF_NUM if alloc_rxbuf_skb() in
 968          * tc35815_rx() had failed.
 969          */
 970         lp->fbl_count = 0;
 971         for (i = 0; i < RX_BUF_NUM; i++) {
 972                 if (lp->rx_skbs[i].skb) {
 973                         if (i != lp->fbl_count) {
 974                                 lp->rx_skbs[lp->fbl_count].skb =
 975                                         lp->rx_skbs[i].skb;
 976                                 lp->rx_skbs[lp->fbl_count].skb_dma =
 977                                         lp->rx_skbs[i].skb_dma;
 978                         }
 979                         lp->fbl_count++;
 980                 }
 981         }
 982         for (i = 0; i < RX_BUF_NUM; i++) {
 983                 if (i >= lp->fbl_count) {
 984                         lp->fbl_ptr->bd[i].BuffData = 0;
 985                         lp->fbl_ptr->bd[i].BDCtl = 0;
 986                         continue;
 987                 }
 988                 lp->fbl_ptr->bd[i].BuffData =
 989                         cpu_to_le32(lp->rx_skbs[i].skb_dma);
 990                 /* BDID is index of FrFD.bd[] */
 991                 lp->fbl_ptr->bd[i].BDCtl =
 992                         cpu_to_le32(BD_CownsBD | (i << BD_RxBDID_SHIFT) |
 993                                     RX_BUF_SIZE);
 994         }
 995
 996         printk(KERN_DEBUG "%s: TxFD %p RxFD %p FrFD %p\n",
 997                dev->name, lp->tfd_base, lp->rfd_base, lp->fbl_ptr);
 998         return 0;
 999 }
1000
1001 static void
1002 tc35815_clear_queues(struct net_device *dev)
1003 {
1004         struct tc35815_local *lp = netdev_priv(dev);
1005         int i;
1006
1007         for (i = 0; i < TX_FD_NUM; i++) {
1008                 u32 fdsystem = le32_to_cpu(lp->tfd_base[i].fd.FDSystem);
1009                 struct sk_buff *skb =
1010                         fdsystem != 0xffffffff ?
1011                         lp->tx_skbs[fdsystem].skb : NULL;
1012 #ifdef DEBUG
1013                 if (lp->tx_skbs[i].skb != skb) {
1014                         printk("%s: tx_skbs mismatch(%d).\n", dev->name, i);
1015                         panic_queues(dev);
1016                 }
1017 #else
1018                 BUG_ON(lp->tx_skbs[i].skb != skb);
1019 #endif
1020                 if (skb) {
1021                         pci_unmap_single(lp->pci_dev, lp->tx_skbs[i].skb_dma, skb->len, PCI_DMA_TODEVICE);
1022                         lp->tx_skbs[i].skb = NULL;
1023                         lp->tx_skbs[i].skb_dma = 0;
1024                         dev_kfree_skb_any(skb);
1025                 }
1026                 lp->tfd_base[i].fd.FDSystem = cpu_to_le32(0xffffffff);
1027         }
1028
1029         tc35815_init_queues(dev);
1030 }
1031
1032 static void
1033 tc35815_free_queues(struct net_device *dev)
1034 {
1035         struct tc35815_local *lp = netdev_priv(dev);
1036         int i;
1037
1038         if (lp->tfd_base) {
1039                 for (i = 0; i < TX_FD_NUM; i++) {
1040                         u32 fdsystem = le32_to_cpu(lp->tfd_base[i].fd.FDSystem);
1041                         struct sk_buff *skb =
1042                                 fdsystem != 0xffffffff ?
1043                                 lp->tx_skbs[fdsystem].skb : NULL;
1044 #ifdef DEBUG
1045                         if (lp->tx_skbs[i].skb != skb) {
1046                                 printk("%s: tx_skbs mismatch(%d).\n", dev->name, i);
1047                                 panic_queues(dev);
1048                         }
1049 #else
1050                         BUG_ON(lp->tx_skbs[i].skb != skb);
1051 #endif
1052                         if (skb) {
1053                                 dev_kfree_skb(skb);
1054                                 pci_unmap_single(lp->pci_dev, lp->tx_skbs[i].skb_dma, skb->len, PCI_DMA_TODEVICE);
1055                                 lp->tx_skbs[i].skb = NULL;
1056                                 lp->tx_skbs[i].skb_dma = 0;
1057                         }
1058                         lp->tfd_base[i].fd.FDSystem = cpu_to_le32(0xffffffff);
1059                 }
1060         }
1061
1062         lp->rfd_base = NULL;
1063         lp->rfd_limit = NULL;
1064         lp->rfd_cur = NULL;
1065         lp->fbl_ptr = NULL;
1066
1067         for (i = 0; i < RX_BUF_NUM; i++) {
1068                 if (lp->rx_skbs[i].skb) {
1069                         free_rxbuf_skb(lp->pci_dev, lp->rx_skbs[i].skb,
1070                                        lp->rx_skbs[i].skb_dma);
1071                         lp->rx_skbs[i].skb = NULL;
1072                 }
1073         }
1074         if (lp->fd_buf) {
1075                 pci_free_consistent(lp->pci_dev, PAGE_SIZE * FD_PAGE_NUM,
1076                                     lp->fd_buf, lp->fd_buf_dma);
1077                 lp->fd_buf = NULL;
1078         }
1079 }
1080
1081 static void
1082 dump_txfd(struct TxFD *fd)
1083 {
1084         printk("TxFD(%p): %08x %08x %08x %08x\n", fd,
1085                le32_to_cpu(fd->fd.FDNext),
1086                le32_to_cpu(fd->fd.FDSystem),
1087                le32_to_cpu(fd->fd.FDStat),
1088                le32_to_cpu(fd->fd.FDCtl));
1089         printk("BD: ");
1090         printk(" %08x %08x",
1091                le32_to_cpu(fd->bd.BuffData),
1092                le32_to_cpu(fd->bd.BDCtl));
1093         printk("\n");
1094 }
1095
1096 static int
1097 dump_rxfd(struct RxFD *fd)
1098 {
1099         int i, bd_count = (le32_to_cpu(fd->fd.FDCtl) & FD_BDCnt_MASK) >> FD_BDCnt_SHIFT;
1100         if (bd_count > 8)
1101                 bd_count = 8;
1102         printk("RxFD(%p): %08x %08x %08x %08x\n", fd,
1103                le32_to_cpu(fd->fd.FDNext),
1104                le32_to_cpu(fd->fd.FDSystem),
1105                le32_to_cpu(fd->fd.FDStat),
1106                le32_to_cpu(fd->fd.FDCtl));
1107         if (le32_to_cpu(fd->fd.FDCtl) & FD_CownsFD)
1108                 return 0;
1109         printk("BD: ");
1110         for (i = 0; i < bd_count; i++)
1111                 printk(" %08x %08x",
1112                        le32_to_cpu(fd->bd[i].BuffData),
1113                        le32_to_cpu(fd->bd[i].BDCtl));
1114         printk("\n");
1115         return bd_count;
1116 }
1117
1118 #ifdef DEBUG
1119 static void
1120 dump_frfd(struct FrFD *fd)
1121 {
1122         int i;
1123         printk("FrFD(%p): %08x %08x %08x %08x\n", fd,
1124                le32_to_cpu(fd->fd.FDNext),
1125                le32_to_cpu(fd->fd.FDSystem),
1126                le32_to_cpu(fd->fd.FDStat),
1127                le32_to_cpu(fd->fd.FDCtl));
1128         printk("BD: ");
1129         for (i = 0; i < RX_BUF_NUM; i++)
1130                 printk(" %08x %08x",
1131                        le32_to_cpu(fd->bd[i].BuffData),
1132                        le32_to_cpu(fd->bd[i].BDCtl));
1133         printk("\n");
1134 }
1135
1136 static void
1137 panic_queues(struct net_device *dev)
1138 {
1139         struct tc35815_local *lp = netdev_priv(dev);
1140         int i;
1141
1142         printk("TxFD base %p, start %u, end %u\n",
1143                lp->tfd_base, lp->tfd_start, lp->tfd_end);
1144         printk("RxFD base %p limit %p cur %p\n",
1145                lp->rfd_base, lp->rfd_limit, lp->rfd_cur);
1146         printk("FrFD %p\n", lp->fbl_ptr);
1147         for (i = 0; i < TX_FD_NUM; i++)
1148                 dump_txfd(&lp->tfd_base[i]);
1149         for (i = 0; i < RX_FD_NUM; i++) {
1150                 int bd_count = dump_rxfd(&lp->rfd_base[i]);
1151                 i += (bd_count + 1) / 2;        /* skip BDs */
1152         }
1153         dump_frfd(lp->fbl_ptr);
1154         panic("%s: Illegal queue state.", dev->name);
1155 }
1156 #endif
1157
1158 static void print_eth(const u8 *add)
1159 {
1160         printk(KERN_DEBUG "print_eth(%p)\n", add);
1161         printk(KERN_DEBUG " %pM => %pM : %02x%02x\n",
1162                 add + 6, add, add[12], add[13]);
1163 }
1164
1165 static int tc35815_tx_full(struct net_device *dev)
1166 {
1167         struct tc35815_local *lp = netdev_priv(dev);
1168         return ((lp->tfd_start + 1) % TX_FD_NUM == lp->tfd_end);
1169 }
1170
1171 static void tc35815_restart(struct net_device *dev)
1172 {
1173         struct tc35815_local *lp = netdev_priv(dev);
1174
1175         if (lp->phy_dev) {
1176                 int timeout;
1177
1178                 phy_write(lp->phy_dev, MII_BMCR, BMCR_RESET);
1179                 timeout = 100;
1180                 while (--timeout) {
1181                         if (!(phy_read(lp->phy_dev, MII_BMCR) & BMCR_RESET))
1182                                 break;
1183                         udelay(1);
1184                 }
1185                 if (!timeout)
1186                         printk(KERN_ERR "%s: BMCR reset failed.\n", dev->name);
1187         }
1188
1189         spin_lock_irq(&lp->lock);
1190         tc35815_chip_reset(dev);
1191         tc35815_clear_queues(dev);
1192         tc35815_chip_init(dev);
1193         /* Reconfigure CAM again since tc35815_chip_init() initialize it. */
1194         tc35815_set_multicast_list(dev);
1195         spin_unlock_irq(&lp->lock);
1196
1197         netif_wake_queue(dev);
1198 }
1199
1200 static void tc35815_restart_work(struct work_struct *work)
1201 {
1202         struct tc35815_local *lp =
1203                 container_of(work, struct tc35815_local, restart_work);
1204         struct net_device *dev = lp->dev;
1205
1206         tc35815_restart(dev);
1207 }
1208
1209 static void tc35815_schedule_restart(struct net_device *dev)
1210 {
1211         struct tc35815_local *lp = netdev_priv(dev);
1212         struct tc35815_regs __iomem *tr =
1213                 (struct tc35815_regs __iomem *)dev->base_addr;
1214
1215         /* disable interrupts */
1216         tc_writel(0, &tr->Int_En);
1217         tc_writel(tc_readl(&tr->DMA_Ctl) | DMA_IntMask, &tr->DMA_Ctl);
1218         schedule_work(&lp->restart_work);
1219 }
1220
1221 static void tc35815_tx_timeout(struct net_device *dev)
1222 {
1223         struct tc35815_regs __iomem *tr =
1224                 (struct tc35815_regs __iomem *)dev->base_addr;
1225
1226         printk(KERN_WARNING "%s: transmit timed out, status %#x\n",
1227                dev->name, tc_readl(&tr->Tx_Stat));
1228
1229         /* Try to restart the adaptor. */
1230         tc35815_schedule_restart(dev);
1231         dev->stats.tx_errors++;
1232 }
1233
1234 /*
1235  * Open/initialize the controller. This is called (in the current kernel)
1236  * sometime after booting when the 'ifconfig' program is run.
1237  *
1238  * This routine should set everything up anew at each open, even
1239  * registers that "should" only need to be set once at boot, so that
1240  * there is non-reboot way to recover if something goes wrong.
1241  */
1242 static int
1243 tc35815_open(struct net_device *dev)
1244 {
1245         struct tc35815_local *lp = netdev_priv(dev);
1246
1247         /*
1248          * This is used if the interrupt line can turned off (shared).
1249          * See 3c503.c for an example of selecting the IRQ at config-time.
1250          */
1251         if (request_irq(dev->irq, tc35815_interrupt, IRQF_SHARED,
1252                         dev->name, dev))
1253                 return -EAGAIN;
1254
1255         tc35815_chip_reset(dev);
1256
1257         if (tc35815_init_queues(dev) != 0) {
1258                 free_irq(dev->irq, dev);
1259                 return -EAGAIN;
1260         }
1261
1262         napi_enable(&lp->napi);
1263
1264         /* Reset the hardware here. Don't forget to set the station address. */
1265         spin_lock_irq(&lp->lock);
1266         tc35815_chip_init(dev);
1267         spin_unlock_irq(&lp->lock);
1268
1269         netif_carrier_off(dev);
1270         /* schedule a link state check */
1271         phy_start(lp->phy_dev);
1272
1273         /* We are now ready to accept transmit requeusts from
1274          * the queueing layer of the networking.
1275          */
1276         netif_start_queue(dev);
1277
1278         return 0;
1279 }
1280
1281 /* This will only be invoked if your driver is _not_ in XOFF state.
1282  * What this means is that you need not check it, and that this
1283  * invariant will hold if you make sure that the netif_*_queue()
1284  * calls are done at the proper times.
1285  */
1286 static int tc35815_send_packet(struct sk_buff *skb, struct net_device *dev)
1287 {
1288         struct tc35815_local *lp = netdev_priv(dev);
1289         struct TxFD *txfd;
1290         unsigned long flags;
1291
1292         /* If some error occurs while trying to transmit this
1293          * packet, you should return '1' from this function.
1294          * In such a case you _may not_ do anything to the
1295          * SKB, it is still owned by the network queueing
1296          * layer when an error is returned.  This means you
1297          * may not modify any SKB fields, you may not free
1298          * the SKB, etc.
1299          */
1300
1301         /* This is the most common case for modern hardware.
1302          * The spinlock protects this code from the TX complete
1303          * hardware interrupt handler.  Queue flow control is
1304          * thus managed under this lock as well.
1305          */
1306         spin_lock_irqsave(&lp->lock, flags);
1307
1308         /* failsafe... (handle txdone now if half of FDs are used) */
1309         if ((lp->tfd_start + TX_FD_NUM - lp->tfd_end) % TX_FD_NUM >
1310             TX_FD_NUM / 2)
1311                 tc35815_txdone(dev);
1312
1313         if (netif_msg_pktdata(lp))
1314                 print_eth(skb->data);
1315 #ifdef DEBUG
1316         if (lp->tx_skbs[lp->tfd_start].skb) {
1317                 printk("%s: tx_skbs conflict.\n", dev->name);
1318                 panic_queues(dev);
1319         }
1320 #else
1321         BUG_ON(lp->tx_skbs[lp->tfd_start].skb);
1322 #endif
1323         lp->tx_skbs[lp->tfd_start].skb = skb;
1324         lp->tx_skbs[lp->tfd_start].skb_dma = pci_map_single(lp->pci_dev, skb->data, skb->len, PCI_DMA_TODEVICE);
1325
1326         /*add to ring */
1327         txfd = &lp->tfd_base[lp->tfd_start];
1328         txfd->bd.BuffData = cpu_to_le32(lp->tx_skbs[lp->tfd_start].skb_dma);
1329         txfd->bd.BDCtl = cpu_to_le32(skb->len);
1330         txfd->fd.FDSystem = cpu_to_le32(lp->tfd_start);
1331         txfd->fd.FDCtl = cpu_to_le32(FD_CownsFD | (1 << FD_BDCnt_SHIFT));
1332
1333         if (lp->tfd_start == lp->tfd_end) {
1334                 struct tc35815_regs __iomem *tr =
1335                         (struct tc35815_regs __iomem *)dev->base_addr;
1336                 /* Start DMA Transmitter. */
1337                 txfd->fd.FDNext |= cpu_to_le32(FD_Next_EOL);
1338                 txfd->fd.FDCtl |= cpu_to_le32(FD_FrmOpt_IntTx);
1339                 if (netif_msg_tx_queued(lp)) {
1340                         printk("%s: starting TxFD.\n", dev->name);
1341                         dump_txfd(txfd);
1342                 }
1343                 tc_writel(fd_virt_to_bus(lp, txfd), &tr->TxFrmPtr);
1344         } else {
1345                 txfd->fd.FDNext &= cpu_to_le32(~FD_Next_EOL);
1346                 if (netif_msg_tx_queued(lp)) {
1347                         printk("%s: queueing TxFD.\n", dev->name);
1348                         dump_txfd(txfd);
1349                 }
1350         }
1351         lp->tfd_start = (lp->tfd_start + 1) % TX_FD_NUM;
1352
1353         dev->trans_start = jiffies;
1354
1355         /* If we just used up the very last entry in the
1356          * TX ring on this device, tell the queueing
1357          * layer to send no more.
1358          */
1359         if (tc35815_tx_full(dev)) {
1360                 if (netif_msg_tx_queued(lp))
1361                         printk(KERN_WARNING "%s: TxFD Exhausted.\n", dev->name);
1362                 netif_stop_queue(dev);
1363         }
1364
1365         /* When the TX completion hw interrupt arrives, this
1366          * is when the transmit statistics are updated.
1367          */
1368
1369         spin_unlock_irqrestore(&lp->lock, flags);
1370         return NETDEV_TX_OK;
1371 }
1372
1373 #define FATAL_ERROR_INT \
1374         (Int_IntPCI | Int_DmParErr | Int_IntNRAbt)
1375 static void tc35815_fatal_error_interrupt(struct net_device *dev, u32 status)
1376 {
1377         static int count;
1378         printk(KERN_WARNING "%s: Fatal Error Intterrupt (%#x):",
1379                dev->name, status);
1380         if (status & Int_IntPCI)
1381                 printk(" IntPCI");
1382         if (status & Int_DmParErr)
1383                 printk(" DmParErr");
1384         if (status & Int_IntNRAbt)
1385                 printk(" IntNRAbt");
1386         printk("\n");
1387         if (count++ > 100)
1388                 panic("%s: Too many fatal errors.", dev->name);
1389         printk(KERN_WARNING "%s: Resetting ...\n", dev->name);
1390         /* Try to restart the adaptor. */
1391         tc35815_schedule_restart(dev);
1392 }
1393
1394 static int tc35815_do_interrupt(struct net_device *dev, u32 status, int limit)
1395 {
1396         struct tc35815_local *lp = netdev_priv(dev);
1397         int ret = -1;
1398
1399         /* Fatal errors... */
1400         if (status & FATAL_ERROR_INT) {
1401                 tc35815_fatal_error_interrupt(dev, status);
1402                 return 0;
1403         }
1404         /* recoverable errors */
1405         if (status & Int_IntFDAEx) {
1406                 if (netif_msg_rx_err(lp))
1407                         dev_warn(&dev->dev,
1408                                  "Free Descriptor Area Exhausted (%#x).\n",
1409                                  status);
1410                 dev->stats.rx_dropped++;
1411                 ret = 0;
1412         }
1413         if (status & Int_IntBLEx) {
1414                 if (netif_msg_rx_err(lp))
1415                         dev_warn(&dev->dev,
1416                                  "Buffer List Exhausted (%#x).\n",
1417                                  status);
1418                 dev->stats.rx_dropped++;
1419                 ret = 0;
1420         }
1421         if (status & Int_IntExBD) {
1422                 if (netif_msg_rx_err(lp))
1423                         dev_warn(&dev->dev,
1424                                  "Excessive Buffer Descriptiors (%#x).\n",
1425                                  status);
1426                 dev->stats.rx_length_errors++;
1427                 ret = 0;
1428         }
1429
1430         /* normal notification */
1431         if (status & Int_IntMacRx) {
1432                 /* Got a packet(s). */
1433                 ret = tc35815_rx(dev, limit);
1434                 lp->lstats.rx_ints++;
1435         }
1436         if (status & Int_IntMacTx) {
1437                 /* Transmit complete. */
1438                 lp->lstats.tx_ints++;
1439                 tc35815_txdone(dev);
1440                 netif_wake_queue(dev);
1441                 if (ret < 0)
1442                         ret = 0;
1443         }
1444         return ret;
1445 }
1446
1447 /*
1448  * The typical workload of the driver:
1449  * Handle the network interface interrupts.
1450  */
1451 static irqreturn_t tc35815_interrupt(int irq, void *dev_id)
1452 {
1453         struct net_device *dev = dev_id;
1454         struct tc35815_local *lp = netdev_priv(dev);
1455         struct tc35815_regs __iomem *tr =
1456                 (struct tc35815_regs __iomem *)dev->base_addr;
1457         u32 dmactl = tc_readl(&tr->DMA_Ctl);
1458
1459         if (!(dmactl & DMA_IntMask)) {
1460                 /* disable interrupts */
1461                 tc_writel(dmactl | DMA_IntMask, &tr->DMA_Ctl);
1462                 if (napi_schedule_prep(&lp->napi))
1463                         __napi_schedule(&lp->napi);
1464                 else {
1465                         printk(KERN_ERR "%s: interrupt taken in poll\n",
1466                                dev->name);
1467                         BUG();
1468                 }
1469                 (void)tc_readl(&tr->Int_Src);   /* flush */
1470                 return IRQ_HANDLED;
1471         }
1472         return IRQ_NONE;
1473 }
1474
1475 #ifdef CONFIG_NET_POLL_CONTROLLER
1476 static void tc35815_poll_controller(struct net_device *dev)
1477 {
1478         disable_irq(dev->irq);
1479         tc35815_interrupt(dev->irq, dev);
1480         enable_irq(dev->irq);
1481 }
1482 #endif
1483
1484 /* We have a good packet(s), get it/them out of the buffers. */
1485 static int
1486 tc35815_rx(struct net_device *dev, int limit)
1487 {
1488         struct tc35815_local *lp = netdev_priv(dev);
1489         unsigned int fdctl;
1490         int i;
1491         int received = 0;
1492
1493         while (!((fdctl = le32_to_cpu(lp->rfd_cur->fd.FDCtl)) & FD_CownsFD)) {
1494                 int status = le32_to_cpu(lp->rfd_cur->fd.FDStat);
1495                 int pkt_len = fdctl & FD_FDLength_MASK;
1496                 int bd_count = (fdctl & FD_BDCnt_MASK) >> FD_BDCnt_SHIFT;
1497 #ifdef DEBUG
1498                 struct RxFD *next_rfd;
1499 #endif
1500 #if (RX_CTL_CMD & Rx_StripCRC) == 0
1501                 pkt_len -= ETH_FCS_LEN;
1502 #endif
1503
1504                 if (netif_msg_rx_status(lp))
1505                         dump_rxfd(lp->rfd_cur);
1506                 if (status & Rx_Good) {
1507                         struct sk_buff *skb;
1508                         unsigned char *data;
1509                         int cur_bd;
1510
1511                         if (--limit < 0)
1512                                 break;
1513                         BUG_ON(bd_count > 1);
1514                         cur_bd = (le32_to_cpu(lp->rfd_cur->bd[0].BDCtl)
1515                                   & BD_RxBDID_MASK) >> BD_RxBDID_SHIFT;
1516 #ifdef DEBUG
1517                         if (cur_bd >= RX_BUF_NUM) {
1518                                 printk("%s: invalid BDID.\n", dev->name);
1519                                 panic_queues(dev);
1520                         }
1521                         BUG_ON(lp->rx_skbs[cur_bd].skb_dma !=
1522                                (le32_to_cpu(lp->rfd_cur->bd[0].BuffData) & ~3));
1523                         if (!lp->rx_skbs[cur_bd].skb) {
1524                                 printk("%s: NULL skb.\n", dev->name);
1525                                 panic_queues(dev);
1526                         }
1527 #else
1528                         BUG_ON(cur_bd >= RX_BUF_NUM);
1529 #endif
1530                         skb = lp->rx_skbs[cur_bd].skb;
1531                         prefetch(skb->data);
1532                         lp->rx_skbs[cur_bd].skb = NULL;
1533                         pci_unmap_single(lp->pci_dev,
1534                                          lp->rx_skbs[cur_bd].skb_dma,
1535                                          RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
1536                         if (!HAVE_DMA_RXALIGN(lp) && NET_IP_ALIGN)
1537                                 memmove(skb->data, skb->data - NET_IP_ALIGN,
1538                                         pkt_len);
1539                         data = skb_put(skb, pkt_len);
1540                         if (netif_msg_pktdata(lp))
1541                                 print_eth(data);
1542                         skb->protocol = eth_type_trans(skb, dev);
1543                         netif_receive_skb(skb);
1544                         received++;
1545                         dev->stats.rx_packets++;
1546                         dev->stats.rx_bytes += pkt_len;
1547                 } else {
1548                         dev->stats.rx_errors++;
1549                         if (netif_msg_rx_err(lp))
1550                                 dev_info(&dev->dev, "Rx error (status %x)\n",
1551                                          status & Rx_Stat_Mask);
1552                         /* WORKAROUND: LongErr and CRCErr means Overflow. */
1553                         if ((status & Rx_LongErr) && (status & Rx_CRCErr)) {
1554                                 status &= ~(Rx_LongErr|Rx_CRCErr);
1555                                 status |= Rx_Over;
1556                         }
1557                         if (status & Rx_LongErr)
1558                                 dev->stats.rx_length_errors++;
1559                         if (status & Rx_Over)
1560                                 dev->stats.rx_fifo_errors++;
1561                         if (status & Rx_CRCErr)
1562                                 dev->stats.rx_crc_errors++;
1563                         if (status & Rx_Align)
1564                                 dev->stats.rx_frame_errors++;
1565                 }
1566
1567                 if (bd_count > 0) {
1568                         /* put Free Buffer back to controller */
1569                         int bdctl = le32_to_cpu(lp->rfd_cur->bd[bd_count - 1].BDCtl);
1570                         unsigned char id =
1571                                 (bdctl & BD_RxBDID_MASK) >> BD_RxBDID_SHIFT;
1572 #ifdef DEBUG
1573                         if (id >= RX_BUF_NUM) {
1574                                 printk("%s: invalid BDID.\n", dev->name);
1575                                 panic_queues(dev);
1576                         }
1577 #else
1578                         BUG_ON(id >= RX_BUF_NUM);
1579 #endif
1580                         /* free old buffers */
1581                         lp->fbl_count--;
1582                         while (lp->fbl_count < RX_BUF_NUM)
1583                         {
1584                                 unsigned char curid =
1585                                         (id + 1 + lp->fbl_count) % RX_BUF_NUM;
1586                                 struct BDesc *bd = &lp->fbl_ptr->bd[curid];
1587 #ifdef DEBUG
1588                                 bdctl = le32_to_cpu(bd->BDCtl);
1589                                 if (bdctl & BD_CownsBD) {
1590                                         printk("%s: Freeing invalid BD.\n",
1591                                                dev->name);
1592                                         panic_queues(dev);
1593                                 }
1594 #endif
1595                                 /* pass BD to controller */
1596                                 if (!lp->rx_skbs[curid].skb) {
1597                                         lp->rx_skbs[curid].skb =
1598                                                 alloc_rxbuf_skb(dev,
1599                                                                 lp->pci_dev,
1600                                                                 &lp->rx_skbs[curid].skb_dma);
1601                                         if (!lp->rx_skbs[curid].skb)
1602                                                 break; /* try on next reception */
1603                                         bd->BuffData = cpu_to_le32(lp->rx_skbs[curid].skb_dma);
1604                                 }
1605                                 /* Note: BDLength was modified by chip. */
1606                                 bd->BDCtl = cpu_to_le32(BD_CownsBD |
1607                                                         (curid << BD_RxBDID_SHIFT) |
1608                                                         RX_BUF_SIZE);
1609                                 lp->fbl_count++;
1610                         }
1611                 }
1612
1613                 /* put RxFD back to controller */
1614 #ifdef DEBUG
1615                 next_rfd = fd_bus_to_virt(lp,
1616                                           le32_to_cpu(lp->rfd_cur->fd.FDNext));
1617                 if (next_rfd < lp->rfd_base || next_rfd > lp->rfd_limit) {
1618                         printk("%s: RxFD FDNext invalid.\n", dev->name);
1619                         panic_queues(dev);
1620                 }
1621 #endif
1622                 for (i = 0; i < (bd_count + 1) / 2 + 1; i++) {
1623                         /* pass FD to controller */
1624 #ifdef DEBUG
1625                         lp->rfd_cur->fd.FDNext = cpu_to_le32(0xdeaddead);
1626 #else
1627                         lp->rfd_cur->fd.FDNext = cpu_to_le32(FD_Next_EOL);
1628 #endif
1629                         lp->rfd_cur->fd.FDCtl = cpu_to_le32(FD_CownsFD);
1630                         lp->rfd_cur++;
1631                 }
1632                 if (lp->rfd_cur > lp->rfd_limit)
1633                         lp->rfd_cur = lp->rfd_base;
1634 #ifdef DEBUG
1635                 if (lp->rfd_cur != next_rfd)
1636                         printk("rfd_cur = %p, next_rfd %p\n",
1637                                lp->rfd_cur, next_rfd);
1638 #endif
1639         }
1640
1641         return received;
1642 }
1643
1644 static int tc35815_poll(struct napi_struct *napi, int budget)
1645 {
1646         struct tc35815_local *lp = container_of(napi, struct tc35815_local, napi);
1647         struct net_device *dev = lp->dev;
1648         struct tc35815_regs __iomem *tr =
1649                 (struct tc35815_regs __iomem *)dev->base_addr;
1650         int received = 0, handled;
1651         u32 status;
1652
1653         spin_lock(&lp->lock);
1654         status = tc_readl(&tr->Int_Src);
1655         do {
1656                 /* BLEx, FDAEx will be cleared later */
1657                 tc_writel(status & ~(Int_BLEx | Int_FDAEx),
1658                           &tr->Int_Src);        /* write to clear */
1659
1660                 handled = tc35815_do_interrupt(dev, status, budget - received);
1661                 if (status & (Int_BLEx | Int_FDAEx))
1662                         tc_writel(status & (Int_BLEx | Int_FDAEx),
1663                                   &tr->Int_Src);
1664                 if (handled >= 0) {
1665                         received += handled;
1666                         if (received >= budget)
1667                                 break;
1668                 }
1669                 status = tc_readl(&tr->Int_Src);
1670         } while (status);
1671         spin_unlock(&lp->lock);
1672
1673         if (received < budget) {
1674                 napi_complete(napi);
1675                 /* enable interrupts */
1676                 tc_writel(tc_readl(&tr->DMA_Ctl) & ~DMA_IntMask, &tr->DMA_Ctl);
1677         }
1678         return received;
1679 }
1680
1681 #define TX_STA_ERR      (Tx_ExColl|Tx_Under|Tx_Defer|Tx_NCarr|Tx_LateColl|Tx_TxPar|Tx_SQErr)
1682
1683 static void
1684 tc35815_check_tx_stat(struct net_device *dev, int status)
1685 {
1686         struct tc35815_local *lp = netdev_priv(dev);
1687         const char *msg = NULL;
1688
1689         /* count collisions */
1690         if (status & Tx_ExColl)
1691                 dev->stats.collisions += 16;
1692         if (status & Tx_TxColl_MASK)
1693                 dev->stats.collisions += status & Tx_TxColl_MASK;
1694
1695         /* TX4939 does not have NCarr */
1696         if (lp->chiptype == TC35815_TX4939)
1697                 status &= ~Tx_NCarr;
1698         /* WORKAROUND: ignore LostCrS in full duplex operation */
1699         if (!lp->link || lp->duplex == DUPLEX_FULL)
1700                 status &= ~Tx_NCarr;
1701
1702         if (!(status & TX_STA_ERR)) {
1703                 /* no error. */
1704                 dev->stats.tx_packets++;
1705                 return;
1706         }
1707
1708         dev->stats.tx_errors++;
1709         if (status & Tx_ExColl) {
1710                 dev->stats.tx_aborted_errors++;
1711                 msg = "Excessive Collision.";
1712         }
1713         if (status & Tx_Under) {
1714                 dev->stats.tx_fifo_errors++;
1715                 msg = "Tx FIFO Underrun.";
1716                 if (lp->lstats.tx_underrun < TX_THRESHOLD_KEEP_LIMIT) {
1717                         lp->lstats.tx_underrun++;
1718                         if (lp->lstats.tx_underrun >= TX_THRESHOLD_KEEP_LIMIT) {
1719                                 struct tc35815_regs __iomem *tr =
1720                                         (struct tc35815_regs __iomem *)dev->base_addr;
1721                                 tc_writel(TX_THRESHOLD_MAX, &tr->TxThrsh);
1722                                 msg = "Tx FIFO Underrun.Change Tx threshold to max.";
1723                         }
1724                 }
1725         }
1726         if (status & Tx_Defer) {
1727                 dev->stats.tx_fifo_errors++;
1728                 msg = "Excessive Deferral.";
1729         }
1730         if (status & Tx_NCarr) {
1731                 dev->stats.tx_carrier_errors++;
1732                 msg = "Lost Carrier Sense.";
1733         }
1734         if (status & Tx_LateColl) {
1735                 dev->stats.tx_aborted_errors++;
1736                 msg = "Late Collision.";
1737         }
1738         if (status & Tx_TxPar) {
1739                 dev->stats.tx_fifo_errors++;
1740                 msg = "Transmit Parity Error.";
1741         }
1742         if (status & Tx_SQErr) {
1743                 dev->stats.tx_heartbeat_errors++;
1744                 msg = "Signal Quality Error.";
1745         }
1746         if (msg && netif_msg_tx_err(lp))
1747                 printk(KERN_WARNING "%s: %s (%#x)\n", dev->name, msg, status);
1748 }
1749
1750 /* This handles TX complete events posted by the device
1751  * via interrupts.
1752  */
1753 static void
1754 tc35815_txdone(struct net_device *dev)
1755 {
1756         struct tc35815_local *lp = netdev_priv(dev);
1757         struct TxFD *txfd;
1758         unsigned int fdctl;
1759
1760         txfd = &lp->tfd_base[lp->tfd_end];
1761         while (lp->tfd_start != lp->tfd_end &&
1762                !((fdctl = le32_to_cpu(txfd->fd.FDCtl)) & FD_CownsFD)) {
1763                 int status = le32_to_cpu(txfd->fd.FDStat);
1764                 struct sk_buff *skb;
1765                 unsigned long fdnext = le32_to_cpu(txfd->fd.FDNext);
1766                 u32 fdsystem = le32_to_cpu(txfd->fd.FDSystem);
1767
1768                 if (netif_msg_tx_done(lp)) {
1769                         printk("%s: complete TxFD.\n", dev->name);
1770                         dump_txfd(txfd);
1771                 }
1772                 tc35815_check_tx_stat(dev, status);
1773
1774                 skb = fdsystem != 0xffffffff ?
1775                         lp->tx_skbs[fdsystem].skb : NULL;
1776 #ifdef DEBUG
1777                 if (lp->tx_skbs[lp->tfd_end].skb != skb) {
1778                         printk("%s: tx_skbs mismatch.\n", dev->name);
1779                         panic_queues(dev);
1780                 }
1781 #else
1782                 BUG_ON(lp->tx_skbs[lp->tfd_end].skb != skb);
1783 #endif
1784                 if (skb) {
1785                         dev->stats.tx_bytes += skb->len;
1786                         pci_unmap_single(lp->pci_dev, lp->tx_skbs[lp->tfd_end].skb_dma, skb->len, PCI_DMA_TODEVICE);
1787                         lp->tx_skbs[lp->tfd_end].skb = NULL;
1788                         lp->tx_skbs[lp->tfd_end].skb_dma = 0;
1789                         dev_kfree_skb_any(skb);
1790                 }
1791                 txfd->fd.FDSystem = cpu_to_le32(0xffffffff);
1792
1793                 lp->tfd_end = (lp->tfd_end + 1) % TX_FD_NUM;
1794                 txfd = &lp->tfd_base[lp->tfd_end];
1795 #ifdef DEBUG
1796                 if ((fdnext & ~FD_Next_EOL) != fd_virt_to_bus(lp, txfd)) {
1797                         printk("%s: TxFD FDNext invalid.\n", dev->name);
1798                         panic_queues(dev);
1799                 }
1800 #endif
1801                 if (fdnext & FD_Next_EOL) {
1802                         /* DMA Transmitter has been stopping... */
1803                         if (lp->tfd_end != lp->tfd_start) {
1804                                 struct tc35815_regs __iomem *tr =
1805                                         (struct tc35815_regs __iomem *)dev->base_addr;
1806                                 int head = (lp->tfd_start + TX_FD_NUM - 1) % TX_FD_NUM;
1807                                 struct TxFD *txhead = &lp->tfd_base[head];
1808                                 int qlen = (lp->tfd_start + TX_FD_NUM
1809                                             - lp->tfd_end) % TX_FD_NUM;
1810
1811 #ifdef DEBUG
1812                                 if (!(le32_to_cpu(txfd->fd.FDCtl) & FD_CownsFD)) {
1813                                         printk("%s: TxFD FDCtl invalid.\n", dev->name);
1814                                         panic_queues(dev);
1815                                 }
1816 #endif
1817                                 /* log max queue length */
1818                                 if (lp->lstats.max_tx_qlen < qlen)
1819                                         lp->lstats.max_tx_qlen = qlen;
1820
1821
1822                                 /* start DMA Transmitter again */
1823                                 txhead->fd.FDNext |= cpu_to_le32(FD_Next_EOL);
1824                                 txhead->fd.FDCtl |= cpu_to_le32(FD_FrmOpt_IntTx);
1825                                 if (netif_msg_tx_queued(lp)) {
1826                                         printk("%s: start TxFD on queue.\n",
1827                                                dev->name);
1828                                         dump_txfd(txfd);
1829                                 }
1830                                 tc_writel(fd_virt_to_bus(lp, txfd), &tr->TxFrmPtr);
1831                         }
1832                         break;
1833                 }
1834         }
1835
1836         /* If we had stopped the queue due to a "tx full"
1837          * condition, and space has now been made available,
1838          * wake up the queue.
1839          */
1840         if (netif_queue_stopped(dev) && !tc35815_tx_full(dev))
1841                 netif_wake_queue(dev);
1842 }
1843
1844 /* The inverse routine to tc35815_open(). */
1845 static int
1846 tc35815_close(struct net_device *dev)
1847 {
1848         struct tc35815_local *lp = netdev_priv(dev);
1849
1850         netif_stop_queue(dev);
1851         napi_disable(&lp->napi);
1852         if (lp->phy_dev)
1853                 phy_stop(lp->phy_dev);
1854         cancel_work_sync(&lp->restart_work);
1855
1856         /* Flush the Tx and disable Rx here. */
1857         tc35815_chip_reset(dev);
1858         free_irq(dev->irq, dev);
1859
1860         tc35815_free_queues(dev);
1861
1862         return 0;
1863
1864 }
1865
1866 /*
1867  * Get the current statistics.
1868  * This may be called with the card open or closed.
1869  */
1870 static struct net_device_stats *tc35815_get_stats(struct net_device *dev)
1871 {
1872         struct tc35815_regs __iomem *tr =
1873                 (struct tc35815_regs __iomem *)dev->base_addr;
1874         if (netif_running(dev))
1875                 /* Update the statistics from the device registers. */
1876                 dev->stats.rx_missed_errors += tc_readl(&tr->Miss_Cnt);
1877
1878         return &dev->stats;
1879 }
1880
1881 static void tc35815_set_cam_entry(struct net_device *dev, int index, unsigned char *addr)
1882 {
1883         struct tc35815_local *lp = netdev_priv(dev);
1884         struct tc35815_regs __iomem *tr =
1885                 (struct tc35815_regs __iomem *)dev->base_addr;
1886         int cam_index = index * 6;
1887         u32 cam_data;
1888         u32 saved_addr;
1889
1890         saved_addr = tc_readl(&tr->CAM_Adr);
1891
1892         if (netif_msg_hw(lp))
1893                 printk(KERN_DEBUG "%s: CAM %d: %pM\n",
1894                         dev->name, index, addr);
1895         if (index & 1) {
1896                 /* read modify write */
1897                 tc_writel(cam_index - 2, &tr->CAM_Adr);
1898                 cam_data = tc_readl(&tr->CAM_Data) & 0xffff0000;
1899                 cam_data |= addr[0] << 8 | addr[1];
1900                 tc_writel(cam_data, &tr->CAM_Data);
1901                 /* write whole word */
1902                 tc_writel(cam_index + 2, &tr->CAM_Adr);
1903                 cam_data = (addr[2] << 24) | (addr[3] << 16) | (addr[4] << 8) | addr[5];
1904                 tc_writel(cam_data, &tr->CAM_Data);
1905         } else {
1906                 /* write whole word */
1907                 tc_writel(cam_index, &tr->CAM_Adr);
1908                 cam_data = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
1909                 tc_writel(cam_data, &tr->CAM_Data);
1910                 /* read modify write */
1911                 tc_writel(cam_index + 4, &tr->CAM_Adr);
1912                 cam_data = tc_readl(&tr->CAM_Data) & 0x0000ffff;
1913                 cam_data |= addr[4] << 24 | (addr[5] << 16);
1914                 tc_writel(cam_data, &tr->CAM_Data);
1915         }
1916
1917         tc_writel(saved_addr, &tr->CAM_Adr);
1918 }
1919
1920
1921 /*
1922  * Set or clear the multicast filter for this adaptor.
1923  * num_addrs == -1      Promiscuous mode, receive all packets
1924  * num_addrs == 0       Normal mode, clear multicast list
1925  * num_addrs > 0        Multicast mode, receive normal and MC packets,
1926  *                      and do best-effort filtering.
1927  */
1928 static void
1929 tc35815_set_multicast_list(struct net_device *dev)
1930 {
1931         struct tc35815_regs __iomem *tr =
1932                 (struct tc35815_regs __iomem *)dev->base_addr;
1933
1934         if (dev->flags & IFF_PROMISC) {
1935                 /* With some (all?) 100MHalf HUB, controller will hang
1936                  * if we enabled promiscuous mode before linkup... */
1937                 struct tc35815_local *lp = netdev_priv(dev);
1938
1939                 if (!lp->link)
1940                         return;
1941                 /* Enable promiscuous mode */
1942                 tc_writel(CAM_CompEn | CAM_BroadAcc | CAM_GroupAcc | CAM_StationAcc, &tr->CAM_Ctl);
1943         } else if ((dev->flags & IFF_ALLMULTI) ||
1944                   netdev_mc_count(dev) > CAM_ENTRY_MAX - 3) {
1945                 /* CAM 0, 1, 20 are reserved. */
1946                 /* Disable promiscuous mode, use normal mode. */
1947                 tc_writel(CAM_CompEn | CAM_BroadAcc | CAM_GroupAcc, &tr->CAM_Ctl);
1948         } else if (!netdev_mc_empty(dev)) {
1949                 struct dev_mc_list *cur_addr = dev->mc_list;
1950                 int i;
1951                 int ena_bits = CAM_Ena_Bit(CAM_ENTRY_SOURCE);
1952
1953                 tc_writel(0, &tr->CAM_Ctl);
1954                 /* Walk the address list, and load the filter */
1955                 for (i = 0; i < netdev_mc_count(dev); i++, cur_addr = cur_addr->next) {
1956                         if (!cur_addr)
1957                                 break;
1958                         /* entry 0,1 is reserved. */
1959                         tc35815_set_cam_entry(dev, i + 2, cur_addr->dmi_addr);
1960                         ena_bits |= CAM_Ena_Bit(i + 2);
1961                 }
1962                 tc_writel(ena_bits, &tr->CAM_Ena);
1963                 tc_writel(CAM_CompEn | CAM_BroadAcc, &tr->CAM_Ctl);
1964         } else {
1965                 tc_writel(CAM_Ena_Bit(CAM_ENTRY_SOURCE), &tr->CAM_Ena);
1966                 tc_writel(CAM_CompEn | CAM_BroadAcc, &tr->CAM_Ctl);
1967         }
1968 }
1969
1970 static void tc35815_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1971 {
1972         struct tc35815_local *lp = netdev_priv(dev);
1973         strcpy(info->driver, MODNAME);
1974         strcpy(info->version, DRV_VERSION);
1975         strcpy(info->bus_info, pci_name(lp->pci_dev));
1976 }
1977
1978 static int tc35815_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1979 {
1980         struct tc35815_local *lp = netdev_priv(dev);
1981
1982         if (!lp->phy_dev)
1983                 return -ENODEV;
1984         return phy_ethtool_gset(lp->phy_dev, cmd);
1985 }
1986
1987 static int tc35815_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1988 {
1989         struct tc35815_local *lp = netdev_priv(dev);
1990
1991         if (!lp->phy_dev)
1992                 return -ENODEV;
1993         return phy_ethtool_sset(lp->phy_dev, cmd);
1994 }
1995
1996 static u32 tc35815_get_msglevel(struct net_device *dev)
1997 {
1998         struct tc35815_local *lp = netdev_priv(dev);
1999         return lp->msg_enable;
2000 }
2001
2002 static void tc35815_set_msglevel(struct net_device *dev, u32 datum)
2003 {
2004         struct tc35815_local *lp = netdev_priv(dev);
2005         lp->msg_enable = datum;
2006 }
2007
2008 static int tc35815_get_sset_count(struct net_device *dev, int sset)
2009 {
2010         struct tc35815_local *lp = netdev_priv(dev);
2011
2012         switch (sset) {
2013         case ETH_SS_STATS:
2014                 return sizeof(lp->lstats) / sizeof(int);
2015         default:
2016                 return -EOPNOTSUPP;
2017         }
2018 }
2019
2020 static void tc35815_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *stats, u64 *data)
2021 {
2022         struct tc35815_local *lp = netdev_priv(dev);
2023         data[0] = lp->lstats.max_tx_qlen;
2024         data[1] = lp->lstats.tx_ints;
2025         data[2] = lp->lstats.rx_ints;
2026         data[3] = lp->lstats.tx_underrun;
2027 }
2028
2029 static struct {
2030         const char str[ETH_GSTRING_LEN];
2031 } ethtool_stats_keys[] = {
2032         { "max_tx_qlen" },
2033         { "tx_ints" },
2034         { "rx_ints" },
2035         { "tx_underrun" },
2036 };
2037
2038 static void tc35815_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2039 {
2040         memcpy(data, ethtool_stats_keys, sizeof(ethtool_stats_keys));
2041 }
2042
2043 static const struct ethtool_ops tc35815_ethtool_ops = {
2044         .get_drvinfo            = tc35815_get_drvinfo,
2045         .get_settings           = tc35815_get_settings,
2046         .set_settings           = tc35815_set_settings,
2047         .get_link               = ethtool_op_get_link,
2048         .get_msglevel           = tc35815_get_msglevel,
2049         .set_msglevel           = tc35815_set_msglevel,
2050         .get_strings            = tc35815_get_strings,
2051         .get_sset_count         = tc35815_get_sset_count,
2052         .get_ethtool_stats      = tc35815_get_ethtool_stats,
2053 };
2054
2055 static int tc35815_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2056 {
2057         struct tc35815_local *lp = netdev_priv(dev);
2058
2059         if (!netif_running(dev))
2060                 return -EINVAL;
2061         if (!lp->phy_dev)
2062                 return -ENODEV;
2063         return phy_mii_ioctl(lp->phy_dev, if_mii(rq), cmd);
2064 }
2065
2066 static void tc35815_chip_reset(struct net_device *dev)
2067 {
2068         struct tc35815_regs __iomem *tr =
2069                 (struct tc35815_regs __iomem *)dev->base_addr;
2070         int i;
2071         /* reset the controller */
2072         tc_writel(MAC_Reset, &tr->MAC_Ctl);
2073         udelay(4); /* 3200ns */
2074         i = 0;
2075         while (tc_readl(&tr->MAC_Ctl) & MAC_Reset) {
2076                 if (i++ > 100) {
2077                         printk(KERN_ERR "%s: MAC reset failed.\n", dev->name);
2078                         break;
2079                 }
2080                 mdelay(1);
2081         }
2082         tc_writel(0, &tr->MAC_Ctl);
2083
2084         /* initialize registers to default value */
2085         tc_writel(0, &tr->DMA_Ctl);
2086         tc_writel(0, &tr->TxThrsh);
2087         tc_writel(0, &tr->TxPollCtr);
2088         tc_writel(0, &tr->RxFragSize);
2089         tc_writel(0, &tr->Int_En);
2090         tc_writel(0, &tr->FDA_Bas);
2091         tc_writel(0, &tr->FDA_Lim);
2092         tc_writel(0xffffffff, &tr->Int_Src);    /* Write 1 to clear */
2093         tc_writel(0, &tr->CAM_Ctl);
2094         tc_writel(0, &tr->Tx_Ctl);
2095         tc_writel(0, &tr->Rx_Ctl);
2096         tc_writel(0, &tr->CAM_Ena);
2097         (void)tc_readl(&tr->Miss_Cnt);  /* Read to clear */
2098
2099         /* initialize internal SRAM */
2100         tc_writel(DMA_TestMode, &tr->DMA_Ctl);
2101         for (i = 0; i < 0x1000; i += 4) {
2102                 tc_writel(i, &tr->CAM_Adr);
2103                 tc_writel(0, &tr->CAM_Data);
2104         }
2105         tc_writel(0, &tr->DMA_Ctl);
2106 }
2107
2108 static void tc35815_chip_init(struct net_device *dev)
2109 {
2110         struct tc35815_local *lp = netdev_priv(dev);
2111         struct tc35815_regs __iomem *tr =
2112                 (struct tc35815_regs __iomem *)dev->base_addr;
2113         unsigned long txctl = TX_CTL_CMD;
2114
2115         /* load station address to CAM */
2116         tc35815_set_cam_entry(dev, CAM_ENTRY_SOURCE, dev->dev_addr);
2117
2118         /* Enable CAM (broadcast and unicast) */
2119         tc_writel(CAM_Ena_Bit(CAM_ENTRY_SOURCE), &tr->CAM_Ena);
2120         tc_writel(CAM_CompEn | CAM_BroadAcc, &tr->CAM_Ctl);
2121
2122         /* Use DMA_RxAlign_2 to make IP header 4-byte aligned. */
2123         if (HAVE_DMA_RXALIGN(lp))
2124                 tc_writel(DMA_BURST_SIZE | DMA_RxAlign_2, &tr->DMA_Ctl);
2125         else
2126                 tc_writel(DMA_BURST_SIZE, &tr->DMA_Ctl);
2127         tc_writel(0, &tr->TxPollCtr);   /* Batch mode */
2128         tc_writel(TX_THRESHOLD, &tr->TxThrsh);
2129         tc_writel(INT_EN_CMD, &tr->Int_En);
2130
2131         /* set queues */
2132         tc_writel(fd_virt_to_bus(lp, lp->rfd_base), &tr->FDA_Bas);
2133         tc_writel((unsigned long)lp->rfd_limit - (unsigned long)lp->rfd_base,
2134                   &tr->FDA_Lim);
2135         /*
2136          * Activation method:
2137          * First, enable the MAC Transmitter and the DMA Receive circuits.
2138          * Then enable the DMA Transmitter and the MAC Receive circuits.
2139          */
2140         tc_writel(fd_virt_to_bus(lp, lp->fbl_ptr), &tr->BLFrmPtr);      /* start DMA receiver */
2141         tc_writel(RX_CTL_CMD, &tr->Rx_Ctl);     /* start MAC receiver */
2142
2143         /* start MAC transmitter */
2144         /* TX4939 does not have EnLCarr */
2145         if (lp->chiptype == TC35815_TX4939)
2146                 txctl &= ~Tx_EnLCarr;
2147         /* WORKAROUND: ignore LostCrS in full duplex operation */
2148         if (!lp->phy_dev || !lp->link || lp->duplex == DUPLEX_FULL)
2149                 txctl &= ~Tx_EnLCarr;
2150         tc_writel(txctl, &tr->Tx_Ctl);
2151 }
2152
2153 #ifdef CONFIG_PM
2154 static int tc35815_suspend(struct pci_dev *pdev, pm_message_t state)
2155 {
2156         struct net_device *dev = pci_get_drvdata(pdev);
2157         struct tc35815_local *lp = netdev_priv(dev);
2158         unsigned long flags;
2159
2160         pci_save_state(pdev);
2161         if (!netif_running(dev))
2162                 return 0;
2163         netif_device_detach(dev);
2164         if (lp->phy_dev)
2165                 phy_stop(lp->phy_dev);
2166         spin_lock_irqsave(&lp->lock, flags);
2167         tc35815_chip_reset(dev);
2168         spin_unlock_irqrestore(&lp->lock, flags);
2169         pci_set_power_state(pdev, PCI_D3hot);
2170         return 0;
2171 }
2172
2173 static int tc35815_resume(struct pci_dev *pdev)
2174 {
2175         struct net_device *dev = pci_get_drvdata(pdev);
2176         struct tc35815_local *lp = netdev_priv(dev);
2177
2178         pci_restore_state(pdev);
2179         if (!netif_running(dev))
2180                 return 0;
2181         pci_set_power_state(pdev, PCI_D0);
2182         tc35815_restart(dev);
2183         netif_carrier_off(dev);
2184         if (lp->phy_dev)
2185                 phy_start(lp->phy_dev);
2186         netif_device_attach(dev);
2187         return 0;
2188 }
2189 #endif /* CONFIG_PM */
2190
2191 static struct pci_driver tc35815_pci_driver = {
2192         .name           = MODNAME,
2193         .id_table       = tc35815_pci_tbl,
2194         .probe          = tc35815_init_one,
2195         .remove         = __devexit_p(tc35815_remove_one),
2196 #ifdef CONFIG_PM
2197         .suspend        = tc35815_suspend,
2198         .resume         = tc35815_resume,
2199 #endif
2200 };
2201
2202 module_param_named(speed, options.speed, int, 0);
2203 MODULE_PARM_DESC(speed, "0:auto, 10:10Mbps, 100:100Mbps");
2204 module_param_named(duplex, options.duplex, int, 0);
2205 MODULE_PARM_DESC(duplex, "0:auto, 1:half, 2:full");
2206
2207 static int __init tc35815_init_module(void)
2208 {
2209         return pci_register_driver(&tc35815_pci_driver);
2210 }
2211
2212 static void __exit tc35815_cleanup_module(void)
2213 {
2214         pci_unregister_driver(&tc35815_pci_driver);
2215 }
2216
2217 module_init(tc35815_init_module);
2218 module_exit(tc35815_cleanup_module);
2219
2220 MODULE_DESCRIPTION("TOSHIBA TC35815 PCI 10M/100M Ethernet driver");
2221 MODULE_LICENSE("GPL");