2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 #include <linux/crc32.h>
26 #include <linux/kernel.h>
27 #include <linux/module.h>
28 #include <linux/netdevice.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/etherdevice.h>
31 #include <linux/ethtool.h>
32 #include <linux/pci.h>
35 #include <linux/tcp.h>
37 #include <linux/delay.h>
38 #include <linux/workqueue.h>
39 #include <linux/if_vlan.h>
40 #include <linux/prefetch.h>
41 #include <linux/debugfs.h>
42 #include <linux/mii.h>
46 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
47 #define SKY2_VLAN_TAG_USED 1
52 #define DRV_NAME "sky2"
53 #define DRV_VERSION "1.26"
54 #define PFX DRV_NAME " "
57 * The Yukon II chipset takes 64 bit command blocks (called list elements)
58 * that are organized into three (receive, transmit, status) different rings
62 #define RX_LE_SIZE 1024
63 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
64 #define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
65 #define RX_DEF_PENDING RX_MAX_PENDING
67 /* This is the worst case number of transmit list elements for a single skb:
68 VLAN:GSO + CKSUM + Data + skb_frags * DMA */
69 #define MAX_SKB_TX_LE (2 + (sizeof(dma_addr_t)/sizeof(u32))*(MAX_SKB_FRAGS+1))
70 #define TX_MIN_PENDING (MAX_SKB_TX_LE+1)
71 #define TX_MAX_PENDING 4096
72 #define TX_DEF_PENDING 127
74 #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
75 #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
76 #define TX_WATCHDOG (5 * HZ)
77 #define NAPI_WEIGHT 64
78 #define PHY_RETRIES 1000
80 #define SKY2_EEPROM_MAGIC 0x9955aabb
83 #define RING_NEXT(x,s) (((x)+1) & ((s)-1))
85 static const u32 default_msg =
86 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
87 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
88 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
90 static int debug = -1; /* defaults above */
91 module_param(debug, int, 0);
92 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
94 static int copybreak __read_mostly = 128;
95 module_param(copybreak, int, 0);
96 MODULE_PARM_DESC(copybreak, "Receive copy threshold");
98 static int disable_msi = 0;
99 module_param(disable_msi, int, 0);
100 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
102 static DEFINE_PCI_DEVICE_TABLE(sky2_id_table) = {
103 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
105 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E01) }, /* SK-9E21M */
106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
109 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4355) }, /* 88E8040T */
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4357) }, /* 88E8042 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */
133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
137 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
138 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
139 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436C) }, /* 88E8072 */
140 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436D) }, /* 88E8055 */
141 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4370) }, /* 88E8075 */
142 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4380) }, /* 88E8057 */
143 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4381) }, /* 88E8059 */
147 MODULE_DEVICE_TABLE(pci, sky2_id_table);
149 /* Avoid conditionals by using array */
150 static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
151 static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
152 static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
154 static void sky2_set_multicast(struct net_device *dev);
156 /* Access to PHY via serial interconnect */
157 static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
161 gma_write16(hw, port, GM_SMI_DATA, val);
162 gma_write16(hw, port, GM_SMI_CTRL,
163 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
165 for (i = 0; i < PHY_RETRIES; i++) {
166 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
170 if (!(ctrl & GM_SMI_CT_BUSY))
176 dev_warn(&hw->pdev->dev,"%s: phy write timeout\n", hw->dev[port]->name);
180 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
184 static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
188 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
189 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
191 for (i = 0; i < PHY_RETRIES; i++) {
192 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
196 if (ctrl & GM_SMI_CT_RD_VAL) {
197 *val = gma_read16(hw, port, GM_SMI_DATA);
204 dev_warn(&hw->pdev->dev, "%s: phy read timeout\n", hw->dev[port]->name);
207 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
211 static inline u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
214 __gm_phy_read(hw, port, reg, &v);
219 static void sky2_power_on(struct sky2_hw *hw)
221 /* switch power to VCC (WA for VAUX problem) */
222 sky2_write8(hw, B0_POWER_CTRL,
223 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
225 /* disable Core Clock Division, */
226 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
228 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
229 /* enable bits are inverted */
230 sky2_write8(hw, B2_Y2_CLK_GATE,
231 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
232 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
233 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
235 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
237 if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
240 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
242 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
243 /* set all bits to 0 except bits 15..12 and 8 */
244 reg &= P_ASPM_CONTROL_MSK;
245 sky2_pci_write32(hw, PCI_DEV_REG4, reg);
247 reg = sky2_pci_read32(hw, PCI_DEV_REG5);
248 /* set all bits to 0 except bits 28 & 27 */
249 reg &= P_CTL_TIM_VMAIN_AV_MSK;
250 sky2_pci_write32(hw, PCI_DEV_REG5, reg);
252 sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
254 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
255 reg = sky2_read32(hw, B2_GP_IO);
256 reg |= GLB_GPIO_STAT_RACE_DIS;
257 sky2_write32(hw, B2_GP_IO, reg);
259 sky2_read32(hw, B2_GP_IO);
262 /* Turn on "driver loaded" LED */
263 sky2_write16(hw, B0_CTST, Y2_LED_STAT_ON);
266 static void sky2_power_aux(struct sky2_hw *hw)
268 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
269 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
271 /* enable bits are inverted */
272 sky2_write8(hw, B2_Y2_CLK_GATE,
273 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
274 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
275 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
277 /* switch power to VAUX if supported and PME from D3cold */
278 if ( (sky2_read32(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
279 pci_pme_capable(hw->pdev, PCI_D3cold))
280 sky2_write8(hw, B0_POWER_CTRL,
281 (PC_VAUX_ENA | PC_VCC_ENA |
282 PC_VAUX_ON | PC_VCC_OFF));
284 /* turn off "driver loaded LED" */
285 sky2_write16(hw, B0_CTST, Y2_LED_STAT_OFF);
288 static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
292 /* disable all GMAC IRQ's */
293 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
295 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
296 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
297 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
298 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
300 reg = gma_read16(hw, port, GM_RX_CTRL);
301 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
302 gma_write16(hw, port, GM_RX_CTRL, reg);
305 /* flow control to advertise bits */
306 static const u16 copper_fc_adv[] = {
308 [FC_TX] = PHY_M_AN_ASP,
309 [FC_RX] = PHY_M_AN_PC,
310 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
313 /* flow control to advertise bits when using 1000BaseX */
314 static const u16 fiber_fc_adv[] = {
315 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
316 [FC_TX] = PHY_M_P_ASYM_MD_X,
317 [FC_RX] = PHY_M_P_SYM_MD_X,
318 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
321 /* flow control to GMA disable bits */
322 static const u16 gm_fc_disable[] = {
323 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
324 [FC_TX] = GM_GPCR_FC_RX_DIS,
325 [FC_RX] = GM_GPCR_FC_TX_DIS,
330 static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
332 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
333 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
335 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) &&
336 !(hw->flags & SKY2_HW_NEWER_PHY)) {
337 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
339 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
341 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
343 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
344 if (hw->chip_id == CHIP_ID_YUKON_EC)
345 /* set downshift counter to 3x and enable downshift */
346 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
348 /* set master & slave downshift counter to 1x */
349 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
351 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
354 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
355 if (sky2_is_copper(hw)) {
356 if (!(hw->flags & SKY2_HW_GIGABIT)) {
357 /* enable automatic crossover */
358 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
360 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
361 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
364 /* Enable Class A driver for FE+ A0 */
365 spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2);
366 spec |= PHY_M_FESC_SEL_CL_A;
367 gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec);
370 /* disable energy detect */
371 ctrl &= ~PHY_M_PC_EN_DET_MSK;
373 /* enable automatic crossover */
374 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
376 /* downshift on PHY 88E1112 and 88E1149 is changed */
377 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) &&
378 (hw->flags & SKY2_HW_NEWER_PHY)) {
379 /* set downshift counter to 3x and enable downshift */
380 ctrl &= ~PHY_M_PC_DSC_MSK;
381 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
385 /* workaround for deviation #4.88 (CRC errors) */
386 /* disable Automatic Crossover */
388 ctrl &= ~PHY_M_PC_MDIX_MSK;
391 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
393 /* special setup for PHY 88E1112 Fiber */
394 if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) {
395 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
397 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
398 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
399 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
400 ctrl &= ~PHY_M_MAC_MD_MSK;
401 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
402 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
404 if (hw->pmd_type == 'P') {
405 /* select page 1 to access Fiber registers */
406 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
408 /* for SFP-module set SIGDET polarity to low */
409 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
410 ctrl |= PHY_M_FIB_SIGD_POL;
411 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
414 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
422 if (sky2->flags & SKY2_FLAG_AUTO_SPEED) {
423 if (sky2_is_copper(hw)) {
424 if (sky2->advertising & ADVERTISED_1000baseT_Full)
425 ct1000 |= PHY_M_1000C_AFD;
426 if (sky2->advertising & ADVERTISED_1000baseT_Half)
427 ct1000 |= PHY_M_1000C_AHD;
428 if (sky2->advertising & ADVERTISED_100baseT_Full)
429 adv |= PHY_M_AN_100_FD;
430 if (sky2->advertising & ADVERTISED_100baseT_Half)
431 adv |= PHY_M_AN_100_HD;
432 if (sky2->advertising & ADVERTISED_10baseT_Full)
433 adv |= PHY_M_AN_10_FD;
434 if (sky2->advertising & ADVERTISED_10baseT_Half)
435 adv |= PHY_M_AN_10_HD;
437 } else { /* special defines for FIBER (88E1040S only) */
438 if (sky2->advertising & ADVERTISED_1000baseT_Full)
439 adv |= PHY_M_AN_1000X_AFD;
440 if (sky2->advertising & ADVERTISED_1000baseT_Half)
441 adv |= PHY_M_AN_1000X_AHD;
444 /* Restart Auto-negotiation */
445 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
447 /* forced speed/duplex settings */
448 ct1000 = PHY_M_1000C_MSE;
450 /* Disable auto update for duplex flow control and duplex */
451 reg |= GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_SPD_DIS;
453 switch (sky2->speed) {
455 ctrl |= PHY_CT_SP1000;
456 reg |= GM_GPCR_SPEED_1000;
459 ctrl |= PHY_CT_SP100;
460 reg |= GM_GPCR_SPEED_100;
464 if (sky2->duplex == DUPLEX_FULL) {
465 reg |= GM_GPCR_DUP_FULL;
466 ctrl |= PHY_CT_DUP_MD;
467 } else if (sky2->speed < SPEED_1000)
468 sky2->flow_mode = FC_NONE;
471 if (sky2->flags & SKY2_FLAG_AUTO_PAUSE) {
472 if (sky2_is_copper(hw))
473 adv |= copper_fc_adv[sky2->flow_mode];
475 adv |= fiber_fc_adv[sky2->flow_mode];
477 reg |= GM_GPCR_AU_FCT_DIS;
478 reg |= gm_fc_disable[sky2->flow_mode];
480 /* Forward pause packets to GMAC? */
481 if (sky2->flow_mode & FC_RX)
482 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
484 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
487 gma_write16(hw, port, GM_GP_CTRL, reg);
489 if (hw->flags & SKY2_HW_GIGABIT)
490 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
492 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
493 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
495 /* Setup Phy LED's */
496 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
499 switch (hw->chip_id) {
500 case CHIP_ID_YUKON_FE:
501 /* on 88E3082 these bits are at 11..9 (shifted left) */
502 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
504 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
506 /* delete ACT LED control bits */
507 ctrl &= ~PHY_M_FELP_LED1_MSK;
508 /* change ACT LED control to blink mode */
509 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
510 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
513 case CHIP_ID_YUKON_FE_P:
514 /* Enable Link Partner Next Page */
515 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
516 ctrl |= PHY_M_PC_ENA_LIP_NP;
518 /* disable Energy Detect and enable scrambler */
519 ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB);
520 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
522 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
523 ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) |
524 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) |
525 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED);
527 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
530 case CHIP_ID_YUKON_XL:
531 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
533 /* select page 3 to access LED control register */
534 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
536 /* set LED Function Control register */
537 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
538 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
539 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
540 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
541 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
543 /* set Polarity Control register */
544 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
545 (PHY_M_POLC_LS1_P_MIX(4) |
546 PHY_M_POLC_IS0_P_MIX(4) |
547 PHY_M_POLC_LOS_CTRL(2) |
548 PHY_M_POLC_INIT_CTRL(2) |
549 PHY_M_POLC_STA1_CTRL(2) |
550 PHY_M_POLC_STA0_CTRL(2)));
552 /* restore page register */
553 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
556 case CHIP_ID_YUKON_EC_U:
557 case CHIP_ID_YUKON_EX:
558 case CHIP_ID_YUKON_SUPR:
559 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
561 /* select page 3 to access LED control register */
562 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
564 /* set LED Function Control register */
565 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
566 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
567 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
568 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
569 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
571 /* set Blink Rate in LED Timer Control Register */
572 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
573 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
574 /* restore page register */
575 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
579 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
580 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
582 /* turn off the Rx LED (LED_RX) */
583 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
586 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_UL_2) {
587 /* apply fixes in PHY AFE */
588 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
590 /* increase differential signal amplitude in 10BASE-T */
591 gm_phy_write(hw, port, 0x18, 0xaa99);
592 gm_phy_write(hw, port, 0x17, 0x2011);
594 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
595 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
596 gm_phy_write(hw, port, 0x18, 0xa204);
597 gm_phy_write(hw, port, 0x17, 0x2002);
600 /* set page register to 0 */
601 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
602 } else if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
603 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
604 /* apply workaround for integrated resistors calibration */
605 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
606 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
607 } else if (hw->chip_id == CHIP_ID_YUKON_OPT && hw->chip_rev == 0) {
608 /* apply fixes in PHY AFE */
609 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00ff);
611 /* apply RDAC termination workaround */
612 gm_phy_write(hw, port, 24, 0x2800);
613 gm_phy_write(hw, port, 23, 0x2001);
615 /* set page register back to 0 */
616 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
617 } else if (hw->chip_id != CHIP_ID_YUKON_EX &&
618 hw->chip_id < CHIP_ID_YUKON_SUPR) {
619 /* no effect on Yukon-XL */
620 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
622 if (!(sky2->flags & SKY2_FLAG_AUTO_SPEED) ||
623 sky2->speed == SPEED_100) {
624 /* turn on 100 Mbps LED (LED_LINK100) */
625 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
629 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
633 /* Enable phy interrupt on auto-negotiation complete (or link up) */
634 if (sky2->flags & SKY2_FLAG_AUTO_SPEED)
635 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
637 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
640 static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
641 static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA };
643 static void sky2_phy_power_up(struct sky2_hw *hw, unsigned port)
647 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
648 reg1 &= ~phy_power[port];
650 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
651 reg1 |= coma_mode[port];
653 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
654 sky2_pci_read32(hw, PCI_DEV_REG1);
656 if (hw->chip_id == CHIP_ID_YUKON_FE)
657 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_ANE);
658 else if (hw->flags & SKY2_HW_ADV_POWER_CTL)
659 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
662 static void sky2_phy_power_down(struct sky2_hw *hw, unsigned port)
667 /* release GPHY Control reset */
668 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
670 /* release GMAC reset */
671 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
673 if (hw->flags & SKY2_HW_NEWER_PHY) {
674 /* select page 2 to access MAC control register */
675 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
677 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
678 /* allow GMII Power Down */
679 ctrl &= ~PHY_M_MAC_GMIF_PUP;
680 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
682 /* set page register back to 0 */
683 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
686 /* setup General Purpose Control Register */
687 gma_write16(hw, port, GM_GP_CTRL,
688 GM_GPCR_FL_PASS | GM_GPCR_SPEED_100 |
689 GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS |
692 if (hw->chip_id != CHIP_ID_YUKON_EC) {
693 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
694 /* select page 2 to access MAC control register */
695 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
697 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
698 /* enable Power Down */
699 ctrl |= PHY_M_PC_POW_D_ENA;
700 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
702 /* set page register back to 0 */
703 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
706 /* set IEEE compatible Power Down Mode (dev. #4.99) */
707 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_PDOWN);
710 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
711 reg1 |= phy_power[port]; /* set PHY to PowerDown/COMA Mode */
712 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
715 /* Force a renegotiation */
716 static void sky2_phy_reinit(struct sky2_port *sky2)
718 spin_lock_bh(&sky2->phy_lock);
719 sky2_phy_init(sky2->hw, sky2->port);
720 spin_unlock_bh(&sky2->phy_lock);
723 /* Put device in state to listen for Wake On Lan */
724 static void sky2_wol_init(struct sky2_port *sky2)
726 struct sky2_hw *hw = sky2->hw;
727 unsigned port = sky2->port;
728 enum flow_control save_mode;
732 /* Bring hardware out of reset */
733 sky2_write16(hw, B0_CTST, CS_RST_CLR);
734 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
736 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
737 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
740 * sky2_reset will re-enable on resume
742 save_mode = sky2->flow_mode;
743 ctrl = sky2->advertising;
745 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
746 sky2->flow_mode = FC_NONE;
748 spin_lock_bh(&sky2->phy_lock);
749 sky2_phy_power_up(hw, port);
750 sky2_phy_init(hw, port);
751 spin_unlock_bh(&sky2->phy_lock);
753 sky2->flow_mode = save_mode;
754 sky2->advertising = ctrl;
756 /* Set GMAC to no flow control and auto update for speed/duplex */
757 gma_write16(hw, port, GM_GP_CTRL,
758 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
759 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
761 /* Set WOL address */
762 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
763 sky2->netdev->dev_addr, ETH_ALEN);
765 /* Turn on appropriate WOL control bits */
766 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
768 if (sky2->wol & WAKE_PHY)
769 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
771 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
773 if (sky2->wol & WAKE_MAGIC)
774 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
776 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;
778 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
779 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
781 /* Turn on legacy PCI-Express PME mode */
782 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
783 reg1 |= PCI_Y2_PME_LEGACY;
784 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
787 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
791 static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
793 struct net_device *dev = hw->dev[port];
795 if ( (hw->chip_id == CHIP_ID_YUKON_EX &&
796 hw->chip_rev != CHIP_REV_YU_EX_A0) ||
797 hw->chip_id >= CHIP_ID_YUKON_FE_P) {
798 /* Yukon-Extreme B0 and further Extreme devices */
799 /* enable Store & Forward mode for TX */
801 if (dev->mtu <= ETH_DATA_LEN)
802 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
803 TX_JUMBO_DIS | TX_STFW_ENA);
806 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
807 TX_JUMBO_ENA| TX_STFW_ENA);
809 if (dev->mtu <= ETH_DATA_LEN)
810 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
812 /* set Tx GMAC FIFO Almost Empty Threshold */
813 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
814 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
816 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
818 /* Can't do offload because of lack of store/forward */
819 dev->features &= ~(NETIF_F_TSO | NETIF_F_SG | NETIF_F_ALL_CSUM);
824 static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
826 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
830 const u8 *addr = hw->dev[port]->dev_addr;
832 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
833 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
835 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
837 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
838 /* WA DEV_472 -- looks like crossed wires on port 2 */
839 /* clear GMAC 1 Control reset */
840 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
842 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
843 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
844 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
845 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
846 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
849 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
851 /* Enable Transmit FIFO Underrun */
852 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
854 spin_lock_bh(&sky2->phy_lock);
855 sky2_phy_power_up(hw, port);
856 sky2_phy_init(hw, port);
857 spin_unlock_bh(&sky2->phy_lock);
860 reg = gma_read16(hw, port, GM_PHY_ADDR);
861 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
863 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
864 gma_read16(hw, port, i);
865 gma_write16(hw, port, GM_PHY_ADDR, reg);
867 /* transmit control */
868 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
870 /* receive control reg: unicast + multicast + no FCS */
871 gma_write16(hw, port, GM_RX_CTRL,
872 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
874 /* transmit flow control */
875 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
877 /* transmit parameter */
878 gma_write16(hw, port, GM_TX_PARAM,
879 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
880 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
881 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
882 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
884 /* serial mode register */
885 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
886 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
888 if (hw->dev[port]->mtu > ETH_DATA_LEN)
889 reg |= GM_SMOD_JUMBO_ENA;
891 gma_write16(hw, port, GM_SERIAL_MODE, reg);
893 /* virtual address for data */
894 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
896 /* physical address: used for pause frames */
897 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
899 /* ignore counter overflows */
900 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
901 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
902 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
904 /* Configure Rx MAC FIFO */
905 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
906 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
907 if (hw->chip_id == CHIP_ID_YUKON_EX ||
908 hw->chip_id == CHIP_ID_YUKON_FE_P)
909 rx_reg |= GMF_RX_OVER_ON;
911 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
913 if (hw->chip_id == CHIP_ID_YUKON_XL) {
914 /* Hardware errata - clear flush mask */
915 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), 0);
917 /* Flush Rx MAC FIFO on any flow control or error */
918 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
921 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
922 reg = RX_GMF_FL_THR_DEF + 1;
923 /* Another magic mystery workaround from sk98lin */
924 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
925 hw->chip_rev == CHIP_REV_YU_FE2_A0)
927 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg);
929 /* Configure Tx MAC FIFO */
930 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
931 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
933 /* On chips without ram buffer, pause is controled by MAC level */
934 if (!(hw->flags & SKY2_HW_RAM_BUFFER)) {
935 /* Pause threshold is scaled by 8 in bytes */
936 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
937 hw->chip_rev == CHIP_REV_YU_FE2_A0)
941 sky2_write16(hw, SK_REG(port, RX_GMF_UP_THR), reg);
942 sky2_write16(hw, SK_REG(port, RX_GMF_LP_THR), 768 / 8);
944 sky2_set_tx_stfwd(hw, port);
947 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
948 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
949 /* disable dynamic watermark */
950 reg = sky2_read16(hw, SK_REG(port, TX_GMF_EA));
951 reg &= ~TX_DYN_WM_ENA;
952 sky2_write16(hw, SK_REG(port, TX_GMF_EA), reg);
956 /* Assign Ram Buffer allocation to queue */
957 static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
961 /* convert from K bytes to qwords used for hw register */
964 end = start + space - 1;
966 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
967 sky2_write32(hw, RB_ADDR(q, RB_START), start);
968 sky2_write32(hw, RB_ADDR(q, RB_END), end);
969 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
970 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
972 if (q == Q_R1 || q == Q_R2) {
973 u32 tp = space - space/4;
975 /* On receive queue's set the thresholds
976 * give receiver priority when > 3/4 full
977 * send pause when down to 2K
979 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
980 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
983 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
984 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
986 /* Enable store & forward on Tx queue's because
987 * Tx FIFO is only 1K on Yukon
989 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
992 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
993 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
996 /* Setup Bus Memory Interface */
997 static void sky2_qset(struct sky2_hw *hw, u16 q)
999 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
1000 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
1001 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
1002 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
1005 /* Setup prefetch unit registers. This is the interface between
1006 * hardware and driver list elements
1008 static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
1009 dma_addr_t addr, u32 last)
1011 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1012 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
1013 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), upper_32_bits(addr));
1014 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), lower_32_bits(addr));
1015 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
1016 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
1018 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
1021 static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2, u16 *slot)
1023 struct sky2_tx_le *le = sky2->tx_le + *slot;
1024 struct tx_ring_info *re = sky2->tx_ring + *slot;
1026 *slot = RING_NEXT(*slot, sky2->tx_ring_size);
1033 static void tx_init(struct sky2_port *sky2)
1035 struct sky2_tx_le *le;
1037 sky2->tx_prod = sky2->tx_cons = 0;
1038 sky2->tx_tcpsum = 0;
1039 sky2->tx_last_mss = 0;
1041 le = get_tx_le(sky2, &sky2->tx_prod);
1043 le->opcode = OP_ADDR64 | HW_OWNER;
1044 sky2->tx_last_upper = 0;
1047 /* Update chip's next pointer */
1048 static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
1050 /* Make sure write' to descriptors are complete before we tell hardware */
1052 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
1054 /* Synchronize I/O on since next processor may write to tail */
1059 static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
1061 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
1062 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
1067 /* Build description to hardware for one receive segment */
1068 static void sky2_rx_add(struct sky2_port *sky2, u8 op,
1069 dma_addr_t map, unsigned len)
1071 struct sky2_rx_le *le;
1073 if (sizeof(dma_addr_t) > sizeof(u32)) {
1074 le = sky2_next_rx(sky2);
1075 le->addr = cpu_to_le32(upper_32_bits(map));
1076 le->opcode = OP_ADDR64 | HW_OWNER;
1079 le = sky2_next_rx(sky2);
1080 le->addr = cpu_to_le32(lower_32_bits(map));
1081 le->length = cpu_to_le16(len);
1082 le->opcode = op | HW_OWNER;
1085 /* Build description to hardware for one possibly fragmented skb */
1086 static void sky2_rx_submit(struct sky2_port *sky2,
1087 const struct rx_ring_info *re)
1091 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
1093 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
1094 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
1098 static int sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
1101 struct sk_buff *skb = re->skb;
1104 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
1105 if (unlikely(pci_dma_mapping_error(pdev, re->data_addr)))
1108 pci_unmap_len_set(re, data_size, size);
1110 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1111 re->frag_addr[i] = pci_map_page(pdev,
1112 skb_shinfo(skb)->frags[i].page,
1113 skb_shinfo(skb)->frags[i].page_offset,
1114 skb_shinfo(skb)->frags[i].size,
1115 PCI_DMA_FROMDEVICE);
1119 static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
1121 struct sk_buff *skb = re->skb;
1124 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
1125 PCI_DMA_FROMDEVICE);
1127 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1128 pci_unmap_page(pdev, re->frag_addr[i],
1129 skb_shinfo(skb)->frags[i].size,
1130 PCI_DMA_FROMDEVICE);
1133 /* Tell chip where to start receive checksum.
1134 * Actually has two checksums, but set both same to avoid possible byte
1137 static void rx_set_checksum(struct sky2_port *sky2)
1139 struct sky2_rx_le *le = sky2_next_rx(sky2);
1141 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
1143 le->opcode = OP_TCPSTART | HW_OWNER;
1145 sky2_write32(sky2->hw,
1146 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1147 (sky2->flags & SKY2_FLAG_RX_CHECKSUM)
1148 ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
1152 * The RX Stop command will not work for Yukon-2 if the BMU does not
1153 * reach the end of packet and since we can't make sure that we have
1154 * incoming data, we must reset the BMU while it is not doing a DMA
1155 * transfer. Since it is possible that the RX path is still active,
1156 * the RX RAM buffer will be stopped first, so any possible incoming
1157 * data will not trigger a DMA. After the RAM buffer is stopped, the
1158 * BMU is polled until any DMA in progress is ended and only then it
1161 static void sky2_rx_stop(struct sky2_port *sky2)
1163 struct sky2_hw *hw = sky2->hw;
1164 unsigned rxq = rxqaddr[sky2->port];
1167 /* disable the RAM Buffer receive queue */
1168 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
1170 for (i = 0; i < 0xffff; i++)
1171 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
1172 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
1175 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
1176 sky2->netdev->name);
1178 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1180 /* reset the Rx prefetch unit */
1181 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1185 /* Clean out receive buffer area, assumes receiver hardware stopped */
1186 static void sky2_rx_clean(struct sky2_port *sky2)
1190 memset(sky2->rx_le, 0, RX_LE_BYTES);
1191 for (i = 0; i < sky2->rx_pending; i++) {
1192 struct rx_ring_info *re = sky2->rx_ring + i;
1195 sky2_rx_unmap_skb(sky2->hw->pdev, re);
1202 /* Basic MII support */
1203 static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1205 struct mii_ioctl_data *data = if_mii(ifr);
1206 struct sky2_port *sky2 = netdev_priv(dev);
1207 struct sky2_hw *hw = sky2->hw;
1208 int err = -EOPNOTSUPP;
1210 if (!netif_running(dev))
1211 return -ENODEV; /* Phy still in reset */
1215 data->phy_id = PHY_ADDR_MARV;
1221 spin_lock_bh(&sky2->phy_lock);
1222 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
1223 spin_unlock_bh(&sky2->phy_lock);
1225 data->val_out = val;
1230 spin_lock_bh(&sky2->phy_lock);
1231 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1233 spin_unlock_bh(&sky2->phy_lock);
1239 #ifdef SKY2_VLAN_TAG_USED
1240 static void sky2_set_vlan_mode(struct sky2_hw *hw, u16 port, bool onoff)
1243 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1245 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1248 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1250 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1255 static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1257 struct sky2_port *sky2 = netdev_priv(dev);
1258 struct sky2_hw *hw = sky2->hw;
1259 u16 port = sky2->port;
1261 netif_tx_lock_bh(dev);
1262 napi_disable(&hw->napi);
1265 sky2_set_vlan_mode(hw, port, grp != NULL);
1267 sky2_read32(hw, B0_Y2_SP_LISR);
1268 napi_enable(&hw->napi);
1269 netif_tx_unlock_bh(dev);
1273 /* Amount of required worst case padding in rx buffer */
1274 static inline unsigned sky2_rx_pad(const struct sky2_hw *hw)
1276 return (hw->flags & SKY2_HW_RAM_BUFFER) ? 8 : 2;
1280 * Allocate an skb for receiving. If the MTU is large enough
1281 * make the skb non-linear with a fragment list of pages.
1283 static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
1285 struct sk_buff *skb;
1288 skb = netdev_alloc_skb(sky2->netdev,
1289 sky2->rx_data_size + sky2_rx_pad(sky2->hw));
1293 if (sky2->hw->flags & SKY2_HW_RAM_BUFFER) {
1294 unsigned char *start;
1296 * Workaround for a bug in FIFO that cause hang
1297 * if the FIFO if the receive buffer is not 64 byte aligned.
1298 * The buffer returned from netdev_alloc_skb is
1299 * aligned except if slab debugging is enabled.
1301 start = PTR_ALIGN(skb->data, 8);
1302 skb_reserve(skb, start - skb->data);
1304 skb_reserve(skb, NET_IP_ALIGN);
1306 for (i = 0; i < sky2->rx_nfrags; i++) {
1307 struct page *page = alloc_page(GFP_ATOMIC);
1311 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
1321 static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
1323 sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
1327 * Allocate and setup receiver buffer pool.
1328 * Normal case this ends up creating one list element for skb
1329 * in the receive ring. Worst case if using large MTU and each
1330 * allocation falls on a different 64 bit region, that results
1331 * in 6 list elements per ring entry.
1332 * One element is used for checksum enable/disable, and one
1333 * extra to avoid wrap.
1335 static int sky2_rx_start(struct sky2_port *sky2)
1337 struct sky2_hw *hw = sky2->hw;
1338 struct rx_ring_info *re;
1339 unsigned rxq = rxqaddr[sky2->port];
1340 unsigned i, size, thresh;
1342 sky2->rx_put = sky2->rx_next = 0;
1345 /* On PCI express lowering the watermark gives better performance */
1346 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1347 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1349 /* These chips have no ram buffer?
1350 * MAC Rx RAM Read is controlled by hardware */
1351 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1352 (hw->chip_rev == CHIP_REV_YU_EC_U_A1 ||
1353 hw->chip_rev == CHIP_REV_YU_EC_U_B0))
1354 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
1356 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1358 if (!(hw->flags & SKY2_HW_NEW_LE))
1359 rx_set_checksum(sky2);
1361 /* Space needed for frame data + headers rounded up */
1362 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
1364 /* Stopping point for hardware truncation */
1365 thresh = (size - 8) / sizeof(u32);
1367 sky2->rx_nfrags = size >> PAGE_SHIFT;
1368 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1370 /* Compute residue after pages */
1371 size -= sky2->rx_nfrags << PAGE_SHIFT;
1373 /* Optimize to handle small packets and headers */
1374 if (size < copybreak)
1376 if (size < ETH_HLEN)
1379 sky2->rx_data_size = size;
1382 for (i = 0; i < sky2->rx_pending; i++) {
1383 re = sky2->rx_ring + i;
1385 re->skb = sky2_rx_alloc(sky2);
1389 if (sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size)) {
1390 dev_kfree_skb(re->skb);
1395 sky2_rx_submit(sky2, re);
1399 * The receiver hangs if it receives frames larger than the
1400 * packet buffer. As a workaround, truncate oversize frames, but
1401 * the register is limited to 9 bits, so if you do frames > 2052
1402 * you better get the MTU right!
1405 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1407 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1408 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1411 /* Tell chip about available buffers */
1412 sky2_rx_update(sky2, rxq);
1414 if (hw->chip_id == CHIP_ID_YUKON_EX ||
1415 hw->chip_id == CHIP_ID_YUKON_SUPR) {
1417 * Disable flushing of non ASF packets;
1418 * must be done after initializing the BMUs;
1419 * drivers without ASF support should do this too, otherwise
1420 * it may happen that they cannot run on ASF devices;
1421 * remember that the MAC FIFO isn't reset during initialization.
1423 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_MACSEC_FLUSH_OFF);
1426 if (hw->chip_id >= CHIP_ID_YUKON_SUPR) {
1427 /* Enable RX Home Address & Routing Header checksum fix */
1428 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_FL_CTRL),
1429 RX_IPV6_SA_MOB_ENA | RX_IPV6_DA_MOB_ENA);
1431 /* Enable TX Home Address & Routing Header checksum fix */
1432 sky2_write32(hw, Q_ADDR(txqaddr[sky2->port], Q_TEST),
1433 TBMU_TEST_HOME_ADD_FIX_EN | TBMU_TEST_ROUTING_ADD_FIX_EN);
1440 sky2_rx_clean(sky2);
1444 static int sky2_alloc_buffers(struct sky2_port *sky2)
1446 struct sky2_hw *hw = sky2->hw;
1448 /* must be power of 2 */
1449 sky2->tx_le = pci_alloc_consistent(hw->pdev,
1450 sky2->tx_ring_size *
1451 sizeof(struct sky2_tx_le),
1456 sky2->tx_ring = kcalloc(sky2->tx_ring_size, sizeof(struct tx_ring_info),
1461 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1465 memset(sky2->rx_le, 0, RX_LE_BYTES);
1467 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
1477 static void sky2_free_buffers(struct sky2_port *sky2)
1479 struct sky2_hw *hw = sky2->hw;
1482 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1483 sky2->rx_le, sky2->rx_le_map);
1487 pci_free_consistent(hw->pdev,
1488 sky2->tx_ring_size * sizeof(struct sky2_tx_le),
1489 sky2->tx_le, sky2->tx_le_map);
1492 kfree(sky2->tx_ring);
1493 kfree(sky2->rx_ring);
1495 sky2->tx_ring = NULL;
1496 sky2->rx_ring = NULL;
1499 /* Bring up network interface. */
1500 static int sky2_up(struct net_device *dev)
1502 struct sky2_port *sky2 = netdev_priv(dev);
1503 struct sky2_hw *hw = sky2->hw;
1504 unsigned port = sky2->port;
1507 struct net_device *otherdev = hw->dev[sky2->port^1];
1510 * On dual port PCI-X card, there is an problem where status
1511 * can be received out of order due to split transactions
1513 if (otherdev && netif_running(otherdev) &&
1514 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1517 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1518 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1519 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1523 netif_carrier_off(dev);
1525 err = sky2_alloc_buffers(sky2);
1531 sky2_mac_init(hw, port);
1533 /* Register is number of 4K blocks on internal RAM buffer. */
1534 ramsize = sky2_read8(hw, B2_E_0) * 4;
1538 pr_debug(PFX "%s: ram buffer %dK\n", dev->name, ramsize);
1540 rxspace = ramsize / 2;
1542 rxspace = 8 + (2*(ramsize - 16))/3;
1544 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1545 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1547 /* Make sure SyncQ is disabled */
1548 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1552 sky2_qset(hw, txqaddr[port]);
1554 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1555 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1556 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1558 /* Set almost empty threshold */
1559 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1560 hw->chip_rev == CHIP_REV_YU_EC_U_A0)
1561 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
1563 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1564 sky2->tx_ring_size - 1);
1566 #ifdef SKY2_VLAN_TAG_USED
1567 sky2_set_vlan_mode(hw, port, sky2->vlgrp != NULL);
1570 err = sky2_rx_start(sky2);
1574 /* Enable interrupts from phy/mac for port */
1575 imask = sky2_read32(hw, B0_IMSK);
1576 imask |= portirq_msk[port];
1577 sky2_write32(hw, B0_IMSK, imask);
1578 sky2_read32(hw, B0_IMSK);
1580 if (netif_msg_ifup(sky2))
1581 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1586 sky2_free_buffers(sky2);
1590 /* Modular subtraction in ring */
1591 static inline int tx_inuse(const struct sky2_port *sky2)
1593 return (sky2->tx_prod - sky2->tx_cons) & (sky2->tx_ring_size - 1);
1596 /* Number of list elements available for next tx */
1597 static inline int tx_avail(const struct sky2_port *sky2)
1599 return sky2->tx_pending - tx_inuse(sky2);
1602 /* Estimate of number of transmit list elements required */
1603 static unsigned tx_le_req(const struct sk_buff *skb)
1607 count = (skb_shinfo(skb)->nr_frags + 1)
1608 * (sizeof(dma_addr_t) / sizeof(u32));
1610 if (skb_is_gso(skb))
1612 else if (sizeof(dma_addr_t) == sizeof(u32))
1613 ++count; /* possible vlan */
1615 if (skb->ip_summed == CHECKSUM_PARTIAL)
1621 static void sky2_tx_unmap(struct pci_dev *pdev,
1622 const struct tx_ring_info *re)
1624 if (re->flags & TX_MAP_SINGLE)
1625 pci_unmap_single(pdev, pci_unmap_addr(re, mapaddr),
1626 pci_unmap_len(re, maplen),
1628 else if (re->flags & TX_MAP_PAGE)
1629 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1630 pci_unmap_len(re, maplen),
1635 * Put one packet in ring for transmit.
1636 * A single packet can generate multiple list elements, and
1637 * the number of ring elements will probably be less than the number
1638 * of list elements used.
1640 static netdev_tx_t sky2_xmit_frame(struct sk_buff *skb,
1641 struct net_device *dev)
1643 struct sky2_port *sky2 = netdev_priv(dev);
1644 struct sky2_hw *hw = sky2->hw;
1645 struct sky2_tx_le *le = NULL;
1646 struct tx_ring_info *re;
1654 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1655 return NETDEV_TX_BUSY;
1657 len = skb_headlen(skb);
1658 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
1660 if (pci_dma_mapping_error(hw->pdev, mapping))
1663 slot = sky2->tx_prod;
1664 if (unlikely(netif_msg_tx_queued(sky2)))
1665 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1666 dev->name, slot, skb->len);
1668 /* Send high bits if needed */
1669 upper = upper_32_bits(mapping);
1670 if (upper != sky2->tx_last_upper) {
1671 le = get_tx_le(sky2, &slot);
1672 le->addr = cpu_to_le32(upper);
1673 sky2->tx_last_upper = upper;
1674 le->opcode = OP_ADDR64 | HW_OWNER;
1677 /* Check for TCP Segmentation Offload */
1678 mss = skb_shinfo(skb)->gso_size;
1681 if (!(hw->flags & SKY2_HW_NEW_LE))
1682 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb);
1684 if (mss != sky2->tx_last_mss) {
1685 le = get_tx_le(sky2, &slot);
1686 le->addr = cpu_to_le32(mss);
1688 if (hw->flags & SKY2_HW_NEW_LE)
1689 le->opcode = OP_MSS | HW_OWNER;
1691 le->opcode = OP_LRGLEN | HW_OWNER;
1692 sky2->tx_last_mss = mss;
1697 #ifdef SKY2_VLAN_TAG_USED
1698 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1699 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1701 le = get_tx_le(sky2, &slot);
1703 le->opcode = OP_VLAN|HW_OWNER;
1705 le->opcode |= OP_VLAN;
1706 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1711 /* Handle TCP checksum offload */
1712 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1713 /* On Yukon EX (some versions) encoding change. */
1714 if (hw->flags & SKY2_HW_AUTO_TX_SUM)
1715 ctrl |= CALSUM; /* auto checksum */
1717 const unsigned offset = skb_transport_offset(skb);
1720 tcpsum = offset << 16; /* sum start */
1721 tcpsum |= offset + skb->csum_offset; /* sum write */
1723 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1724 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1727 if (tcpsum != sky2->tx_tcpsum) {
1728 sky2->tx_tcpsum = tcpsum;
1730 le = get_tx_le(sky2, &slot);
1731 le->addr = cpu_to_le32(tcpsum);
1732 le->length = 0; /* initial checksum value */
1733 le->ctrl = 1; /* one packet */
1734 le->opcode = OP_TCPLISW | HW_OWNER;
1739 re = sky2->tx_ring + slot;
1740 re->flags = TX_MAP_SINGLE;
1741 pci_unmap_addr_set(re, mapaddr, mapping);
1742 pci_unmap_len_set(re, maplen, len);
1744 le = get_tx_le(sky2, &slot);
1745 le->addr = cpu_to_le32(lower_32_bits(mapping));
1746 le->length = cpu_to_le16(len);
1748 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
1751 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1752 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1754 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1755 frag->size, PCI_DMA_TODEVICE);
1757 if (pci_dma_mapping_error(hw->pdev, mapping))
1758 goto mapping_unwind;
1760 upper = upper_32_bits(mapping);
1761 if (upper != sky2->tx_last_upper) {
1762 le = get_tx_le(sky2, &slot);
1763 le->addr = cpu_to_le32(upper);
1764 sky2->tx_last_upper = upper;
1765 le->opcode = OP_ADDR64 | HW_OWNER;
1768 re = sky2->tx_ring + slot;
1769 re->flags = TX_MAP_PAGE;
1770 pci_unmap_addr_set(re, mapaddr, mapping);
1771 pci_unmap_len_set(re, maplen, frag->size);
1773 le = get_tx_le(sky2, &slot);
1774 le->addr = cpu_to_le32(lower_32_bits(mapping));
1775 le->length = cpu_to_le16(frag->size);
1777 le->opcode = OP_BUFFER | HW_OWNER;
1783 sky2->tx_prod = slot;
1785 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1786 netif_stop_queue(dev);
1788 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
1790 return NETDEV_TX_OK;
1793 for (i = sky2->tx_prod; i != slot; i = RING_NEXT(i, sky2->tx_ring_size)) {
1794 re = sky2->tx_ring + i;
1796 sky2_tx_unmap(hw->pdev, re);
1800 if (net_ratelimit())
1801 dev_warn(&hw->pdev->dev, "%s: tx mapping error\n", dev->name);
1803 return NETDEV_TX_OK;
1807 * Free ring elements from starting at tx_cons until "done"
1810 * 1. The hardware will tell us about partial completion of multi-part
1811 * buffers so make sure not to free skb to early.
1812 * 2. This may run in parallel start_xmit because the it only
1813 * looks at the tail of the queue of FIFO (tx_cons), not
1814 * the head (tx_prod)
1816 static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
1818 struct net_device *dev = sky2->netdev;
1821 BUG_ON(done >= sky2->tx_ring_size);
1823 for (idx = sky2->tx_cons; idx != done;
1824 idx = RING_NEXT(idx, sky2->tx_ring_size)) {
1825 struct tx_ring_info *re = sky2->tx_ring + idx;
1826 struct sk_buff *skb = re->skb;
1828 sky2_tx_unmap(sky2->hw->pdev, re);
1831 if (unlikely(netif_msg_tx_done(sky2)))
1832 printk(KERN_DEBUG "%s: tx done %u\n",
1835 dev->stats.tx_packets++;
1836 dev->stats.tx_bytes += skb->len;
1838 dev_kfree_skb_any(skb);
1840 sky2->tx_next = RING_NEXT(idx, sky2->tx_ring_size);
1844 sky2->tx_cons = idx;
1847 /* Wake unless it's detached, and called e.g. from sky2_down() */
1848 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4 && netif_device_present(dev))
1849 netif_wake_queue(dev);
1852 static void sky2_tx_reset(struct sky2_hw *hw, unsigned port)
1854 /* Disable Force Sync bit and Enable Alloc bit */
1855 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1856 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1858 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1859 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1860 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1862 /* Reset the PCI FIFO of the async Tx queue */
1863 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1864 BMU_RST_SET | BMU_FIFO_RST);
1866 /* Reset the Tx prefetch units */
1867 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1870 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1871 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1874 /* Network shutdown */
1875 static int sky2_down(struct net_device *dev)
1877 struct sky2_port *sky2 = netdev_priv(dev);
1878 struct sky2_hw *hw = sky2->hw;
1879 unsigned port = sky2->port;
1883 /* Never really got started! */
1887 if (netif_msg_ifdown(sky2))
1888 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1890 /* Force flow control off */
1891 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1893 /* Stop transmitter */
1894 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1895 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1897 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
1898 RB_RST_SET | RB_DIS_OP_MD);
1900 ctrl = gma_read16(hw, port, GM_GP_CTRL);
1901 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
1902 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1904 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1906 /* Workaround shared GMAC reset */
1907 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 &&
1908 port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
1909 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1911 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1913 /* Force any delayed status interrrupt and NAPI */
1914 sky2_write32(hw, STAT_LEV_TIMER_CNT, 0);
1915 sky2_write32(hw, STAT_TX_TIMER_CNT, 0);
1916 sky2_write32(hw, STAT_ISR_TIMER_CNT, 0);
1917 sky2_read8(hw, STAT_ISR_TIMER_CTRL);
1921 /* Disable port IRQ */
1922 imask = sky2_read32(hw, B0_IMSK);
1923 imask &= ~portirq_msk[port];
1924 sky2_write32(hw, B0_IMSK, imask);
1925 sky2_read32(hw, B0_IMSK);
1927 synchronize_irq(hw->pdev->irq);
1928 napi_synchronize(&hw->napi);
1930 spin_lock_bh(&sky2->phy_lock);
1931 sky2_phy_power_down(hw, port);
1932 spin_unlock_bh(&sky2->phy_lock);
1934 sky2_tx_reset(hw, port);
1936 /* Free any pending frames stuck in HW queue */
1937 sky2_tx_complete(sky2, sky2->tx_prod);
1939 sky2_rx_clean(sky2);
1941 sky2_free_buffers(sky2);
1946 static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1948 if (hw->flags & SKY2_HW_FIBRE_PHY)
1951 if (!(hw->flags & SKY2_HW_GIGABIT)) {
1952 if (aux & PHY_M_PS_SPEED_100)
1958 switch (aux & PHY_M_PS_SPEED_MSK) {
1959 case PHY_M_PS_SPEED_1000:
1961 case PHY_M_PS_SPEED_100:
1968 static void sky2_link_up(struct sky2_port *sky2)
1970 struct sky2_hw *hw = sky2->hw;
1971 unsigned port = sky2->port;
1973 static const char *fc_name[] = {
1981 reg = gma_read16(hw, port, GM_GP_CTRL);
1982 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1983 gma_write16(hw, port, GM_GP_CTRL, reg);
1985 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1987 netif_carrier_on(sky2->netdev);
1989 mod_timer(&hw->watchdog_timer, jiffies + 1);
1991 /* Turn on link LED */
1992 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
1993 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1995 if (netif_msg_link(sky2))
1996 printk(KERN_INFO PFX
1997 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
1998 sky2->netdev->name, sky2->speed,
1999 sky2->duplex == DUPLEX_FULL ? "full" : "half",
2000 fc_name[sky2->flow_status]);
2003 static void sky2_link_down(struct sky2_port *sky2)
2005 struct sky2_hw *hw = sky2->hw;
2006 unsigned port = sky2->port;
2009 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
2011 reg = gma_read16(hw, port, GM_GP_CTRL);
2012 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
2013 gma_write16(hw, port, GM_GP_CTRL, reg);
2015 netif_carrier_off(sky2->netdev);
2017 /* Turn off link LED */
2018 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
2020 if (netif_msg_link(sky2))
2021 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
2023 sky2_phy_init(hw, port);
2026 static enum flow_control sky2_flow(int rx, int tx)
2029 return tx ? FC_BOTH : FC_RX;
2031 return tx ? FC_TX : FC_NONE;
2034 static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
2036 struct sky2_hw *hw = sky2->hw;
2037 unsigned port = sky2->port;
2040 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
2041 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
2042 if (lpa & PHY_M_AN_RF) {
2043 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
2047 if (!(aux & PHY_M_PS_SPDUP_RES)) {
2048 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
2049 sky2->netdev->name);
2053 sky2->speed = sky2_phy_speed(hw, aux);
2054 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2056 /* Since the pause result bits seem to in different positions on
2057 * different chips. look at registers.
2059 if (hw->flags & SKY2_HW_FIBRE_PHY) {
2060 /* Shift for bits in fiber PHY */
2061 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
2062 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
2064 if (advert & ADVERTISE_1000XPAUSE)
2065 advert |= ADVERTISE_PAUSE_CAP;
2066 if (advert & ADVERTISE_1000XPSE_ASYM)
2067 advert |= ADVERTISE_PAUSE_ASYM;
2068 if (lpa & LPA_1000XPAUSE)
2069 lpa |= LPA_PAUSE_CAP;
2070 if (lpa & LPA_1000XPAUSE_ASYM)
2071 lpa |= LPA_PAUSE_ASYM;
2074 sky2->flow_status = FC_NONE;
2075 if (advert & ADVERTISE_PAUSE_CAP) {
2076 if (lpa & LPA_PAUSE_CAP)
2077 sky2->flow_status = FC_BOTH;
2078 else if (advert & ADVERTISE_PAUSE_ASYM)
2079 sky2->flow_status = FC_RX;
2080 } else if (advert & ADVERTISE_PAUSE_ASYM) {
2081 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
2082 sky2->flow_status = FC_TX;
2085 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000 &&
2086 !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
2087 sky2->flow_status = FC_NONE;
2089 if (sky2->flow_status & FC_TX)
2090 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
2092 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2097 /* Interrupt from PHY */
2098 static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
2100 struct net_device *dev = hw->dev[port];
2101 struct sky2_port *sky2 = netdev_priv(dev);
2102 u16 istatus, phystat;
2104 if (!netif_running(dev))
2107 spin_lock(&sky2->phy_lock);
2108 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2109 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
2111 if (netif_msg_intr(sky2))
2112 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
2113 sky2->netdev->name, istatus, phystat);
2115 if (istatus & PHY_M_IS_AN_COMPL) {
2116 if (sky2_autoneg_done(sky2, phystat) == 0)
2121 if (istatus & PHY_M_IS_LSP_CHANGE)
2122 sky2->speed = sky2_phy_speed(hw, phystat);
2124 if (istatus & PHY_M_IS_DUP_CHANGE)
2126 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2128 if (istatus & PHY_M_IS_LST_CHANGE) {
2129 if (phystat & PHY_M_PS_LINK_UP)
2132 sky2_link_down(sky2);
2135 spin_unlock(&sky2->phy_lock);
2138 /* Special quick link interrupt (Yukon-2 Optima only) */
2139 static void sky2_qlink_intr(struct sky2_hw *hw)
2141 struct sky2_port *sky2 = netdev_priv(hw->dev[0]);
2146 imask = sky2_read32(hw, B0_IMSK);
2147 imask &= ~Y2_IS_PHY_QLNK;
2148 sky2_write32(hw, B0_IMSK, imask);
2150 /* reset PHY Link Detect */
2151 phy = sky2_pci_read16(hw, PSM_CONFIG_REG4);
2152 sky2_pci_write16(hw, PSM_CONFIG_REG4, phy | 1);
2157 /* Transmit timeout is only called if we are running, carrier is up
2158 * and tx queue is full (stopped).
2160 static void sky2_tx_timeout(struct net_device *dev)
2162 struct sky2_port *sky2 = netdev_priv(dev);
2163 struct sky2_hw *hw = sky2->hw;
2165 if (netif_msg_timer(sky2))
2166 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
2168 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
2169 dev->name, sky2->tx_cons, sky2->tx_prod,
2170 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
2171 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
2173 /* can't restart safely under softirq */
2174 schedule_work(&hw->restart_work);
2177 static int sky2_change_mtu(struct net_device *dev, int new_mtu)
2179 struct sky2_port *sky2 = netdev_priv(dev);
2180 struct sky2_hw *hw = sky2->hw;
2181 unsigned port = sky2->port;
2186 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2189 if (new_mtu > ETH_DATA_LEN &&
2190 (hw->chip_id == CHIP_ID_YUKON_FE ||
2191 hw->chip_id == CHIP_ID_YUKON_FE_P))
2194 if (!netif_running(dev)) {
2199 imask = sky2_read32(hw, B0_IMSK);
2200 sky2_write32(hw, B0_IMSK, 0);
2202 dev->trans_start = jiffies; /* prevent tx timeout */
2203 netif_stop_queue(dev);
2204 napi_disable(&hw->napi);
2206 synchronize_irq(hw->pdev->irq);
2208 if (!(hw->flags & SKY2_HW_RAM_BUFFER))
2209 sky2_set_tx_stfwd(hw, port);
2211 ctl = gma_read16(hw, port, GM_GP_CTRL);
2212 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
2214 sky2_rx_clean(sky2);
2218 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
2219 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
2221 if (dev->mtu > ETH_DATA_LEN)
2222 mode |= GM_SMOD_JUMBO_ENA;
2224 gma_write16(hw, port, GM_SERIAL_MODE, mode);
2226 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
2228 err = sky2_rx_start(sky2);
2229 sky2_write32(hw, B0_IMSK, imask);
2231 sky2_read32(hw, B0_Y2_SP_LISR);
2232 napi_enable(&hw->napi);
2237 gma_write16(hw, port, GM_GP_CTRL, ctl);
2239 netif_wake_queue(dev);
2245 /* For small just reuse existing skb for next receive */
2246 static struct sk_buff *receive_copy(struct sky2_port *sky2,
2247 const struct rx_ring_info *re,
2250 struct sk_buff *skb;
2252 skb = netdev_alloc_skb_ip_align(sky2->netdev, length);
2254 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
2255 length, PCI_DMA_FROMDEVICE);
2256 skb_copy_from_linear_data(re->skb, skb->data, length);
2257 skb->ip_summed = re->skb->ip_summed;
2258 skb->csum = re->skb->csum;
2259 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
2260 length, PCI_DMA_FROMDEVICE);
2261 re->skb->ip_summed = CHECKSUM_NONE;
2262 skb_put(skb, length);
2267 /* Adjust length of skb with fragments to match received data */
2268 static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
2269 unsigned int length)
2274 /* put header into skb */
2275 size = min(length, hdr_space);
2280 num_frags = skb_shinfo(skb)->nr_frags;
2281 for (i = 0; i < num_frags; i++) {
2282 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2285 /* don't need this page */
2286 __free_page(frag->page);
2287 --skb_shinfo(skb)->nr_frags;
2289 size = min(length, (unsigned) PAGE_SIZE);
2292 skb->data_len += size;
2293 skb->truesize += size;
2300 /* Normal packet - take skb from ring element and put in a new one */
2301 static struct sk_buff *receive_new(struct sky2_port *sky2,
2302 struct rx_ring_info *re,
2303 unsigned int length)
2305 struct sk_buff *skb, *nskb;
2306 unsigned hdr_space = sky2->rx_data_size;
2308 /* Don't be tricky about reusing pages (yet) */
2309 nskb = sky2_rx_alloc(sky2);
2310 if (unlikely(!nskb))
2314 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2316 prefetch(skb->data);
2318 if (sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space)) {
2319 dev_kfree_skb(nskb);
2324 if (skb_shinfo(skb)->nr_frags)
2325 skb_put_frags(skb, hdr_space, length);
2327 skb_put(skb, length);
2332 * Receive one packet.
2333 * For larger packets, get new buffer.
2335 static struct sk_buff *sky2_receive(struct net_device *dev,
2336 u16 length, u32 status)
2338 struct sky2_port *sky2 = netdev_priv(dev);
2339 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
2340 struct sk_buff *skb = NULL;
2341 u16 count = (status & GMR_FS_LEN) >> 16;
2343 #ifdef SKY2_VLAN_TAG_USED
2344 /* Account for vlan tag */
2345 if (sky2->vlgrp && (status & GMR_FS_VLAN))
2349 if (unlikely(netif_msg_rx_status(sky2)))
2350 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
2351 dev->name, sky2->rx_next, status, length);
2353 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
2354 prefetch(sky2->rx_ring + sky2->rx_next);
2356 /* This chip has hardware problems that generates bogus status.
2357 * So do only marginal checking and expect higher level protocols
2358 * to handle crap frames.
2360 if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
2361 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 &&
2365 if (status & GMR_FS_ANY_ERR)
2368 if (!(status & GMR_FS_RX_OK))
2371 /* if length reported by DMA does not match PHY, packet was truncated */
2372 if (length != count)
2376 if (length < copybreak)
2377 skb = receive_copy(sky2, re, length);
2379 skb = receive_new(sky2, re, length);
2381 sky2_rx_submit(sky2, re);
2386 /* Truncation of overlength packets
2387 causes PHY length to not match MAC length */
2388 ++dev->stats.rx_length_errors;
2389 if (netif_msg_rx_err(sky2) && net_ratelimit())
2390 pr_info(PFX "%s: rx length error: status %#x length %d\n",
2391 dev->name, status, length);
2395 ++dev->stats.rx_errors;
2396 if (status & GMR_FS_RX_FF_OV) {
2397 dev->stats.rx_over_errors++;
2401 if (netif_msg_rx_err(sky2) && net_ratelimit())
2402 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
2403 dev->name, status, length);
2405 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
2406 dev->stats.rx_length_errors++;
2407 if (status & GMR_FS_FRAGMENT)
2408 dev->stats.rx_frame_errors++;
2409 if (status & GMR_FS_CRC_ERR)
2410 dev->stats.rx_crc_errors++;
2415 /* Transmit complete */
2416 static inline void sky2_tx_done(struct net_device *dev, u16 last)
2418 struct sky2_port *sky2 = netdev_priv(dev);
2420 if (netif_running(dev))
2421 sky2_tx_complete(sky2, last);
2424 static inline void sky2_skb_rx(const struct sky2_port *sky2,
2425 u32 status, struct sk_buff *skb)
2427 #ifdef SKY2_VLAN_TAG_USED
2428 u16 vlan_tag = be16_to_cpu(sky2->rx_tag);
2429 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2430 if (skb->ip_summed == CHECKSUM_NONE)
2431 vlan_hwaccel_receive_skb(skb, sky2->vlgrp, vlan_tag);
2433 vlan_gro_receive(&sky2->hw->napi, sky2->vlgrp,
2438 if (skb->ip_summed == CHECKSUM_NONE)
2439 netif_receive_skb(skb);
2441 napi_gro_receive(&sky2->hw->napi, skb);
2444 static inline void sky2_rx_done(struct sky2_hw *hw, unsigned port,
2445 unsigned packets, unsigned bytes)
2448 struct net_device *dev = hw->dev[port];
2450 dev->stats.rx_packets += packets;
2451 dev->stats.rx_bytes += bytes;
2452 dev->last_rx = jiffies;
2453 sky2_rx_update(netdev_priv(dev), rxqaddr[port]);
2457 /* Process status response ring */
2458 static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx)
2461 unsigned int total_bytes[2] = { 0 };
2462 unsigned int total_packets[2] = { 0 };
2466 struct sky2_port *sky2;
2467 struct sky2_status_le *le = hw->st_le + hw->st_idx;
2469 struct net_device *dev;
2470 struct sk_buff *skb;
2473 u8 opcode = le->opcode;
2475 if (!(opcode & HW_OWNER))
2478 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
2480 port = le->css & CSS_LINK_BIT;
2481 dev = hw->dev[port];
2482 sky2 = netdev_priv(dev);
2483 length = le16_to_cpu(le->length);
2484 status = le32_to_cpu(le->status);
2487 switch (opcode & ~HW_OWNER) {
2489 total_packets[port]++;
2490 total_bytes[port] += length;
2491 skb = sky2_receive(dev, length, status);
2492 if (unlikely(!skb)) {
2493 dev->stats.rx_dropped++;
2497 /* This chip reports checksum status differently */
2498 if (hw->flags & SKY2_HW_NEW_LE) {
2499 if ((sky2->flags & SKY2_FLAG_RX_CHECKSUM) &&
2500 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
2501 (le->css & CSS_TCPUDPCSOK))
2502 skb->ip_summed = CHECKSUM_UNNECESSARY;
2504 skb->ip_summed = CHECKSUM_NONE;
2507 skb->protocol = eth_type_trans(skb, dev);
2509 sky2_skb_rx(sky2, status, skb);
2511 /* Stop after net poll weight */
2512 if (++work_done >= to_do)
2516 #ifdef SKY2_VLAN_TAG_USED
2518 sky2->rx_tag = length;
2522 sky2->rx_tag = length;
2526 if (!(sky2->flags & SKY2_FLAG_RX_CHECKSUM))
2529 /* If this happens then driver assuming wrong format */
2530 if (unlikely(hw->flags & SKY2_HW_NEW_LE)) {
2531 if (net_ratelimit())
2532 printk(KERN_NOTICE "%s: unexpected"
2533 " checksum status\n",
2538 /* Both checksum counters are programmed to start at
2539 * the same offset, so unless there is a problem they
2540 * should match. This failure is an early indication that
2541 * hardware receive checksumming won't work.
2543 if (likely(status >> 16 == (status & 0xffff))) {
2544 skb = sky2->rx_ring[sky2->rx_next].skb;
2545 skb->ip_summed = CHECKSUM_COMPLETE;
2546 skb->csum = le16_to_cpu(status);
2548 printk(KERN_NOTICE PFX "%s: hardware receive "
2549 "checksum problem (status = %#x)\n",
2551 sky2->flags &= ~SKY2_FLAG_RX_CHECKSUM;
2553 sky2_write32(sky2->hw,
2554 Q_ADDR(rxqaddr[port], Q_CSR),
2560 /* TX index reports status for both ports */
2561 sky2_tx_done(hw->dev[0], status & 0xfff);
2563 sky2_tx_done(hw->dev[1],
2564 ((status >> 24) & 0xff)
2565 | (u16)(length & 0xf) << 8);
2569 if (net_ratelimit())
2570 printk(KERN_WARNING PFX
2571 "unknown status opcode 0x%x\n", opcode);
2573 } while (hw->st_idx != idx);
2575 /* Fully processed status ring so clear irq */
2576 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2579 sky2_rx_done(hw, 0, total_packets[0], total_bytes[0]);
2580 sky2_rx_done(hw, 1, total_packets[1], total_bytes[1]);
2585 static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2587 struct net_device *dev = hw->dev[port];
2589 if (net_ratelimit())
2590 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2593 if (status & Y2_IS_PAR_RD1) {
2594 if (net_ratelimit())
2595 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2598 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2601 if (status & Y2_IS_PAR_WR1) {
2602 if (net_ratelimit())
2603 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2606 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2609 if (status & Y2_IS_PAR_MAC1) {
2610 if (net_ratelimit())
2611 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
2612 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2615 if (status & Y2_IS_PAR_RX1) {
2616 if (net_ratelimit())
2617 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
2618 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2621 if (status & Y2_IS_TCP_TXA1) {
2622 if (net_ratelimit())
2623 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2625 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2629 static void sky2_hw_intr(struct sky2_hw *hw)
2631 struct pci_dev *pdev = hw->pdev;
2632 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2633 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2637 if (status & Y2_IS_TIST_OV)
2638 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2640 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
2643 pci_err = sky2_pci_read16(hw, PCI_STATUS);
2644 if (net_ratelimit())
2645 dev_err(&pdev->dev, "PCI hardware error (0x%x)\n",
2648 sky2_pci_write16(hw, PCI_STATUS,
2649 pci_err | PCI_STATUS_ERROR_BITS);
2652 if (status & Y2_IS_PCI_EXP) {
2653 /* PCI-Express uncorrectable Error occurred */
2656 err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2657 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2659 if (net_ratelimit())
2660 dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err);
2662 sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2665 if (status & Y2_HWE_L1_MASK)
2666 sky2_hw_error(hw, 0, status);
2668 if (status & Y2_HWE_L1_MASK)
2669 sky2_hw_error(hw, 1, status);
2672 static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2674 struct net_device *dev = hw->dev[port];
2675 struct sky2_port *sky2 = netdev_priv(dev);
2676 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2678 if (netif_msg_intr(sky2))
2679 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2682 if (status & GM_IS_RX_CO_OV)
2683 gma_read16(hw, port, GM_RX_IRQ_SRC);
2685 if (status & GM_IS_TX_CO_OV)
2686 gma_read16(hw, port, GM_TX_IRQ_SRC);
2688 if (status & GM_IS_RX_FF_OR) {
2689 ++dev->stats.rx_fifo_errors;
2690 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2693 if (status & GM_IS_TX_FF_UR) {
2694 ++dev->stats.tx_fifo_errors;
2695 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2699 /* This should never happen it is a bug. */
2700 static void sky2_le_error(struct sky2_hw *hw, unsigned port, u16 q)
2702 struct net_device *dev = hw->dev[port];
2703 u16 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
2705 dev_err(&hw->pdev->dev, PFX
2706 "%s: descriptor error q=%#x get=%u put=%u\n",
2707 dev->name, (unsigned) q, (unsigned) idx,
2708 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
2710 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
2713 static int sky2_rx_hung(struct net_device *dev)
2715 struct sky2_port *sky2 = netdev_priv(dev);
2716 struct sky2_hw *hw = sky2->hw;
2717 unsigned port = sky2->port;
2718 unsigned rxq = rxqaddr[port];
2719 u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP));
2720 u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV));
2721 u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP));
2722 u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL));
2724 /* If idle and MAC or PCI is stuck */
2725 if (sky2->check.last == dev->last_rx &&
2726 ((mac_rp == sky2->check.mac_rp &&
2727 mac_lev != 0 && mac_lev >= sky2->check.mac_lev) ||
2728 /* Check if the PCI RX hang */
2729 (fifo_rp == sky2->check.fifo_rp &&
2730 fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) {
2731 printk(KERN_DEBUG PFX "%s: hung mac %d:%d fifo %d (%d:%d)\n",
2732 dev->name, mac_lev, mac_rp, fifo_lev, fifo_rp,
2733 sky2_read8(hw, Q_ADDR(rxq, Q_WP)));
2736 sky2->check.last = dev->last_rx;
2737 sky2->check.mac_rp = mac_rp;
2738 sky2->check.mac_lev = mac_lev;
2739 sky2->check.fifo_rp = fifo_rp;
2740 sky2->check.fifo_lev = fifo_lev;
2745 static void sky2_watchdog(unsigned long arg)
2747 struct sky2_hw *hw = (struct sky2_hw *) arg;
2749 /* Check for lost IRQ once a second */
2750 if (sky2_read32(hw, B0_ISRC)) {
2751 napi_schedule(&hw->napi);
2755 for (i = 0; i < hw->ports; i++) {
2756 struct net_device *dev = hw->dev[i];
2757 if (!netif_running(dev))
2761 /* For chips with Rx FIFO, check if stuck */
2762 if ((hw->flags & SKY2_HW_RAM_BUFFER) &&
2763 sky2_rx_hung(dev)) {
2764 pr_info(PFX "%s: receiver hang detected\n",
2766 schedule_work(&hw->restart_work);
2775 mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ));
2778 /* Hardware/software error handling */
2779 static void sky2_err_intr(struct sky2_hw *hw, u32 status)
2781 if (net_ratelimit())
2782 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
2784 if (status & Y2_IS_HW_ERR)
2787 if (status & Y2_IS_IRQ_MAC1)
2788 sky2_mac_intr(hw, 0);
2790 if (status & Y2_IS_IRQ_MAC2)
2791 sky2_mac_intr(hw, 1);
2793 if (status & Y2_IS_CHK_RX1)
2794 sky2_le_error(hw, 0, Q_R1);
2796 if (status & Y2_IS_CHK_RX2)
2797 sky2_le_error(hw, 1, Q_R2);
2799 if (status & Y2_IS_CHK_TXA1)
2800 sky2_le_error(hw, 0, Q_XA1);
2802 if (status & Y2_IS_CHK_TXA2)
2803 sky2_le_error(hw, 1, Q_XA2);
2806 static int sky2_poll(struct napi_struct *napi, int work_limit)
2808 struct sky2_hw *hw = container_of(napi, struct sky2_hw, napi);
2809 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
2813 if (unlikely(status & Y2_IS_ERROR))
2814 sky2_err_intr(hw, status);
2816 if (status & Y2_IS_IRQ_PHY1)
2817 sky2_phy_intr(hw, 0);
2819 if (status & Y2_IS_IRQ_PHY2)
2820 sky2_phy_intr(hw, 1);
2822 if (status & Y2_IS_PHY_QLNK)
2823 sky2_qlink_intr(hw);
2825 while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) {
2826 work_done += sky2_status_intr(hw, work_limit - work_done, idx);
2828 if (work_done >= work_limit)
2832 napi_complete(napi);
2833 sky2_read32(hw, B0_Y2_SP_LISR);
2839 static irqreturn_t sky2_intr(int irq, void *dev_id)
2841 struct sky2_hw *hw = dev_id;
2844 /* Reading this mask interrupts as side effect */
2845 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2846 if (status == 0 || status == ~0)
2849 prefetch(&hw->st_le[hw->st_idx]);
2851 napi_schedule(&hw->napi);
2856 #ifdef CONFIG_NET_POLL_CONTROLLER
2857 static void sky2_netpoll(struct net_device *dev)
2859 struct sky2_port *sky2 = netdev_priv(dev);
2861 napi_schedule(&sky2->hw->napi);
2865 /* Chip internal frequency for clock calculations */
2866 static u32 sky2_mhz(const struct sky2_hw *hw)
2868 switch (hw->chip_id) {
2869 case CHIP_ID_YUKON_EC:
2870 case CHIP_ID_YUKON_EC_U:
2871 case CHIP_ID_YUKON_EX:
2872 case CHIP_ID_YUKON_SUPR:
2873 case CHIP_ID_YUKON_UL_2:
2874 case CHIP_ID_YUKON_OPT:
2877 case CHIP_ID_YUKON_FE:
2880 case CHIP_ID_YUKON_FE_P:
2883 case CHIP_ID_YUKON_XL:
2891 static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
2893 return sky2_mhz(hw) * us;
2896 static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
2898 return clk / sky2_mhz(hw);
2902 static int __devinit sky2_init(struct sky2_hw *hw)
2906 /* Enable all clocks and check for bad PCI access */
2907 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
2909 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2911 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2912 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2914 switch(hw->chip_id) {
2915 case CHIP_ID_YUKON_XL:
2916 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_NEWER_PHY;
2919 case CHIP_ID_YUKON_EC_U:
2920 hw->flags = SKY2_HW_GIGABIT
2922 | SKY2_HW_ADV_POWER_CTL;
2925 case CHIP_ID_YUKON_EX:
2926 hw->flags = SKY2_HW_GIGABIT
2929 | SKY2_HW_ADV_POWER_CTL;
2931 /* New transmit checksum */
2932 if (hw->chip_rev != CHIP_REV_YU_EX_B0)
2933 hw->flags |= SKY2_HW_AUTO_TX_SUM;
2936 case CHIP_ID_YUKON_EC:
2937 /* This rev is really old, and requires untested workarounds */
2938 if (hw->chip_rev == CHIP_REV_YU_EC_A1) {
2939 dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n");
2942 hw->flags = SKY2_HW_GIGABIT;
2945 case CHIP_ID_YUKON_FE:
2948 case CHIP_ID_YUKON_FE_P:
2949 hw->flags = SKY2_HW_NEWER_PHY
2951 | SKY2_HW_AUTO_TX_SUM
2952 | SKY2_HW_ADV_POWER_CTL;
2955 case CHIP_ID_YUKON_SUPR:
2956 hw->flags = SKY2_HW_GIGABIT
2959 | SKY2_HW_AUTO_TX_SUM
2960 | SKY2_HW_ADV_POWER_CTL;
2963 case CHIP_ID_YUKON_UL_2:
2964 hw->flags = SKY2_HW_GIGABIT
2965 | SKY2_HW_ADV_POWER_CTL;
2968 case CHIP_ID_YUKON_OPT:
2969 hw->flags = SKY2_HW_GIGABIT
2971 | SKY2_HW_ADV_POWER_CTL;
2975 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
2980 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
2981 if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P')
2982 hw->flags |= SKY2_HW_FIBRE_PHY;
2985 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2986 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2987 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2991 if (sky2_read8(hw, B2_E_0))
2992 hw->flags |= SKY2_HW_RAM_BUFFER;
2997 static void sky2_reset(struct sky2_hw *hw)
2999 struct pci_dev *pdev = hw->pdev;
3002 u32 hwe_mask = Y2_HWE_ALL_MASK;
3005 if (hw->chip_id == CHIP_ID_YUKON_EX) {
3006 status = sky2_read16(hw, HCU_CCSR);
3007 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
3008 HCU_CCSR_UC_STATE_MSK);
3009 sky2_write16(hw, HCU_CCSR, status);
3011 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
3012 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
3015 sky2_write8(hw, B0_CTST, CS_RST_SET);
3016 sky2_write8(hw, B0_CTST, CS_RST_CLR);
3018 /* allow writes to PCI config */
3019 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3021 /* clear PCI errors, if any */
3022 status = sky2_pci_read16(hw, PCI_STATUS);
3023 status |= PCI_STATUS_ERROR_BITS;
3024 sky2_pci_write16(hw, PCI_STATUS, status);
3026 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
3028 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3030 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
3033 /* If error bit is stuck on ignore it */
3034 if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP)
3035 dev_info(&pdev->dev, "ignoring stuck error report bit\n");
3037 hwe_mask |= Y2_IS_PCI_EXP;
3042 for (i = 0; i < hw->ports; i++) {
3043 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
3044 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
3046 if (hw->chip_id == CHIP_ID_YUKON_EX ||
3047 hw->chip_id == CHIP_ID_YUKON_SUPR)
3048 sky2_write16(hw, SK_REG(i, GMAC_CTRL),
3049 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
3054 if (hw->chip_id == CHIP_ID_YUKON_SUPR && hw->chip_rev > CHIP_REV_YU_SU_B0) {
3055 /* enable MACSec clock gating */
3056 sky2_pci_write32(hw, PCI_DEV_REG3, P_CLK_MACSEC_DIS);
3059 if (hw->chip_id == CHIP_ID_YUKON_OPT) {
3063 if (hw->chip_rev == 0) {
3064 /* disable PCI-E PHY power down (set PHY reg 0x80, bit 7 */
3065 sky2_write32(hw, Y2_PEX_PHY_DATA, (0x80UL << 16) | (1 << 7));
3067 /* set PHY Link Detect Timer to 1.1 second (11x 100ms) */
3070 /* set PHY Link Detect Timer to 0.4 second (4x 100ms) */
3074 reg <<= PSM_CONFIG_REG4_TIMER_PHY_LINK_DETECT_BASE;
3076 /* reset PHY Link Detect */
3077 sky2_pci_write16(hw, PSM_CONFIG_REG4,
3078 reg | PSM_CONFIG_REG4_RST_PHY_LINK_DETECT);
3079 sky2_pci_write16(hw, PSM_CONFIG_REG4, reg);
3082 /* enable PHY Quick Link */
3083 msk = sky2_read32(hw, B0_IMSK);
3084 msk |= Y2_IS_PHY_QLNK;
3085 sky2_write32(hw, B0_IMSK, msk);
3087 /* check if PSMv2 was running before */
3088 reg = sky2_pci_read16(hw, PSM_CONFIG_REG3);
3089 if (reg & PCI_EXP_LNKCTL_ASPMC) {
3090 int cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3091 /* restore the PCIe Link Control register */
3092 sky2_pci_write16(hw, cap + PCI_EXP_LNKCTL, reg);
3095 /* re-enable PEX PM in PEX PHY debug reg. 8 (clear bit 12) */
3096 sky2_write32(hw, Y2_PEX_PHY_DATA, PEX_DB_ACCESS | (0x08UL << 16));
3099 /* Clear I2C IRQ noise */
3100 sky2_write32(hw, B2_I2C_IRQ, 1);
3102 /* turn off hardware timer (unused) */
3103 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
3104 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
3106 /* Turn off descriptor polling */
3107 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
3109 /* Turn off receive timestamp */
3110 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
3111 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
3113 /* enable the Tx Arbiters */
3114 for (i = 0; i < hw->ports; i++)
3115 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
3117 /* Initialize ram interface */
3118 for (i = 0; i < hw->ports; i++) {
3119 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
3121 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
3122 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
3123 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
3124 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
3125 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
3126 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
3127 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
3128 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
3129 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
3130 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
3131 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
3132 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
3135 sky2_write32(hw, B0_HWE_IMSK, hwe_mask);
3137 for (i = 0; i < hw->ports; i++)
3138 sky2_gmac_reset(hw, i);
3140 memset(hw->st_le, 0, STATUS_LE_BYTES);
3143 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
3144 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
3146 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
3147 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
3149 /* Set the list last index */
3150 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
3152 sky2_write16(hw, STAT_TX_IDX_TH, 10);
3153 sky2_write8(hw, STAT_FIFO_WM, 16);
3155 /* set Status-FIFO ISR watermark */
3156 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
3157 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
3159 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
3161 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
3162 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
3163 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
3165 /* enable status unit */
3166 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
3168 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3169 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3170 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3173 /* Take device down (offline).
3174 * Equivalent to doing dev_stop() but this does not
3175 * inform upper layers of the transistion.
3177 static void sky2_detach(struct net_device *dev)
3179 if (netif_running(dev)) {
3181 netif_device_detach(dev); /* stop txq */
3182 netif_tx_unlock(dev);
3187 /* Bring device back after doing sky2_detach */
3188 static int sky2_reattach(struct net_device *dev)
3192 if (netif_running(dev)) {
3195 printk(KERN_INFO PFX "%s: could not restart %d\n",
3199 netif_device_attach(dev);
3200 sky2_set_multicast(dev);
3207 static void sky2_restart(struct work_struct *work)
3209 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
3213 for (i = 0; i < hw->ports; i++)
3214 sky2_detach(hw->dev[i]);
3216 napi_disable(&hw->napi);
3217 sky2_write32(hw, B0_IMSK, 0);
3219 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3220 napi_enable(&hw->napi);
3222 for (i = 0; i < hw->ports; i++)
3223 sky2_reattach(hw->dev[i]);
3228 static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
3230 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
3233 static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3235 const struct sky2_port *sky2 = netdev_priv(dev);
3237 wol->supported = sky2_wol_supported(sky2->hw);
3238 wol->wolopts = sky2->wol;
3241 static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3243 struct sky2_port *sky2 = netdev_priv(dev);
3244 struct sky2_hw *hw = sky2->hw;
3246 if ((wol->wolopts & ~sky2_wol_supported(sky2->hw)) ||
3247 !device_can_wakeup(&hw->pdev->dev))
3250 sky2->wol = wol->wolopts;
3252 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3253 hw->chip_id == CHIP_ID_YUKON_EX ||
3254 hw->chip_id == CHIP_ID_YUKON_FE_P)
3255 sky2_write32(hw, B0_CTST, sky2->wol
3256 ? Y2_HW_WOL_ON : Y2_HW_WOL_OFF);
3258 device_set_wakeup_enable(&hw->pdev->dev, sky2->wol);
3260 if (!netif_running(dev))
3261 sky2_wol_init(sky2);
3265 static u32 sky2_supported_modes(const struct sky2_hw *hw)
3267 if (sky2_is_copper(hw)) {
3268 u32 modes = SUPPORTED_10baseT_Half
3269 | SUPPORTED_10baseT_Full
3270 | SUPPORTED_100baseT_Half
3271 | SUPPORTED_100baseT_Full
3272 | SUPPORTED_Autoneg | SUPPORTED_TP;
3274 if (hw->flags & SKY2_HW_GIGABIT)
3275 modes |= SUPPORTED_1000baseT_Half
3276 | SUPPORTED_1000baseT_Full;
3279 return SUPPORTED_1000baseT_Half
3280 | SUPPORTED_1000baseT_Full
3285 static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3287 struct sky2_port *sky2 = netdev_priv(dev);
3288 struct sky2_hw *hw = sky2->hw;
3290 ecmd->transceiver = XCVR_INTERNAL;
3291 ecmd->supported = sky2_supported_modes(hw);
3292 ecmd->phy_address = PHY_ADDR_MARV;
3293 if (sky2_is_copper(hw)) {
3294 ecmd->port = PORT_TP;
3295 ecmd->speed = sky2->speed;
3297 ecmd->speed = SPEED_1000;
3298 ecmd->port = PORT_FIBRE;
3301 ecmd->advertising = sky2->advertising;
3302 ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_SPEED)
3303 ? AUTONEG_ENABLE : AUTONEG_DISABLE;
3304 ecmd->duplex = sky2->duplex;
3308 static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3310 struct sky2_port *sky2 = netdev_priv(dev);
3311 const struct sky2_hw *hw = sky2->hw;
3312 u32 supported = sky2_supported_modes(hw);
3314 if (ecmd->autoneg == AUTONEG_ENABLE) {
3315 sky2->flags |= SKY2_FLAG_AUTO_SPEED;
3316 ecmd->advertising = supported;
3322 switch (ecmd->speed) {
3324 if (ecmd->duplex == DUPLEX_FULL)
3325 setting = SUPPORTED_1000baseT_Full;
3326 else if (ecmd->duplex == DUPLEX_HALF)
3327 setting = SUPPORTED_1000baseT_Half;
3332 if (ecmd->duplex == DUPLEX_FULL)
3333 setting = SUPPORTED_100baseT_Full;
3334 else if (ecmd->duplex == DUPLEX_HALF)
3335 setting = SUPPORTED_100baseT_Half;
3341 if (ecmd->duplex == DUPLEX_FULL)
3342 setting = SUPPORTED_10baseT_Full;
3343 else if (ecmd->duplex == DUPLEX_HALF)
3344 setting = SUPPORTED_10baseT_Half;
3352 if ((setting & supported) == 0)
3355 sky2->speed = ecmd->speed;
3356 sky2->duplex = ecmd->duplex;
3357 sky2->flags &= ~SKY2_FLAG_AUTO_SPEED;
3360 sky2->advertising = ecmd->advertising;
3362 if (netif_running(dev)) {
3363 sky2_phy_reinit(sky2);
3364 sky2_set_multicast(dev);
3370 static void sky2_get_drvinfo(struct net_device *dev,
3371 struct ethtool_drvinfo *info)
3373 struct sky2_port *sky2 = netdev_priv(dev);
3375 strcpy(info->driver, DRV_NAME);
3376 strcpy(info->version, DRV_VERSION);
3377 strcpy(info->fw_version, "N/A");
3378 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
3381 static const struct sky2_stat {
3382 char name[ETH_GSTRING_LEN];
3385 { "tx_bytes", GM_TXO_OK_HI },
3386 { "rx_bytes", GM_RXO_OK_HI },
3387 { "tx_broadcast", GM_TXF_BC_OK },
3388 { "rx_broadcast", GM_RXF_BC_OK },
3389 { "tx_multicast", GM_TXF_MC_OK },
3390 { "rx_multicast", GM_RXF_MC_OK },
3391 { "tx_unicast", GM_TXF_UC_OK },
3392 { "rx_unicast", GM_RXF_UC_OK },
3393 { "tx_mac_pause", GM_TXF_MPAUSE },
3394 { "rx_mac_pause", GM_RXF_MPAUSE },
3395 { "collisions", GM_TXF_COL },
3396 { "late_collision",GM_TXF_LAT_COL },
3397 { "aborted", GM_TXF_ABO_COL },
3398 { "single_collisions", GM_TXF_SNG_COL },
3399 { "multi_collisions", GM_TXF_MUL_COL },
3401 { "rx_short", GM_RXF_SHT },
3402 { "rx_runt", GM_RXE_FRAG },
3403 { "rx_64_byte_packets", GM_RXF_64B },
3404 { "rx_65_to_127_byte_packets", GM_RXF_127B },
3405 { "rx_128_to_255_byte_packets", GM_RXF_255B },
3406 { "rx_256_to_511_byte_packets", GM_RXF_511B },
3407 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
3408 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
3409 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
3410 { "rx_too_long", GM_RXF_LNG_ERR },
3411 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
3412 { "rx_jabber", GM_RXF_JAB_PKT },
3413 { "rx_fcs_error", GM_RXF_FCS_ERR },
3415 { "tx_64_byte_packets", GM_TXF_64B },
3416 { "tx_65_to_127_byte_packets", GM_TXF_127B },
3417 { "tx_128_to_255_byte_packets", GM_TXF_255B },
3418 { "tx_256_to_511_byte_packets", GM_TXF_511B },
3419 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
3420 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
3421 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
3422 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
3425 static u32 sky2_get_rx_csum(struct net_device *dev)
3427 struct sky2_port *sky2 = netdev_priv(dev);
3429 return !!(sky2->flags & SKY2_FLAG_RX_CHECKSUM);
3432 static int sky2_set_rx_csum(struct net_device *dev, u32 data)
3434 struct sky2_port *sky2 = netdev_priv(dev);
3437 sky2->flags |= SKY2_FLAG_RX_CHECKSUM;
3439 sky2->flags &= ~SKY2_FLAG_RX_CHECKSUM;
3441 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
3442 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
3447 static u32 sky2_get_msglevel(struct net_device *netdev)
3449 struct sky2_port *sky2 = netdev_priv(netdev);
3450 return sky2->msg_enable;
3453 static int sky2_nway_reset(struct net_device *dev)
3455 struct sky2_port *sky2 = netdev_priv(dev);
3457 if (!netif_running(dev) || !(sky2->flags & SKY2_FLAG_AUTO_SPEED))
3460 sky2_phy_reinit(sky2);
3461 sky2_set_multicast(dev);
3466 static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
3468 struct sky2_hw *hw = sky2->hw;
3469 unsigned port = sky2->port;
3472 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
3473 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
3474 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
3475 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
3477 for (i = 2; i < count; i++)
3478 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
3481 static void sky2_set_msglevel(struct net_device *netdev, u32 value)
3483 struct sky2_port *sky2 = netdev_priv(netdev);
3484 sky2->msg_enable = value;
3487 static int sky2_get_sset_count(struct net_device *dev, int sset)
3491 return ARRAY_SIZE(sky2_stats);
3497 static void sky2_get_ethtool_stats(struct net_device *dev,
3498 struct ethtool_stats *stats, u64 * data)
3500 struct sky2_port *sky2 = netdev_priv(dev);
3502 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
3505 static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
3509 switch (stringset) {
3511 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
3512 memcpy(data + i * ETH_GSTRING_LEN,
3513 sky2_stats[i].name, ETH_GSTRING_LEN);
3518 static int sky2_set_mac_address(struct net_device *dev, void *p)
3520 struct sky2_port *sky2 = netdev_priv(dev);
3521 struct sky2_hw *hw = sky2->hw;
3522 unsigned port = sky2->port;
3523 const struct sockaddr *addr = p;
3525 if (!is_valid_ether_addr(addr->sa_data))
3526 return -EADDRNOTAVAIL;
3528 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
3529 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
3530 dev->dev_addr, ETH_ALEN);
3531 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
3532 dev->dev_addr, ETH_ALEN);
3534 /* virtual address for data */
3535 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3537 /* physical address: used for pause frames */
3538 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
3543 static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
3547 bit = ether_crc(ETH_ALEN, addr) & 63;
3548 filter[bit >> 3] |= 1 << (bit & 7);
3551 static void sky2_set_multicast(struct net_device *dev)
3553 struct sky2_port *sky2 = netdev_priv(dev);
3554 struct sky2_hw *hw = sky2->hw;
3555 unsigned port = sky2->port;
3556 struct dev_mc_list *list = dev->mc_list;
3560 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
3562 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
3563 memset(filter, 0, sizeof(filter));
3565 reg = gma_read16(hw, port, GM_RX_CTRL);
3566 reg |= GM_RXCR_UCF_ENA;
3568 if (dev->flags & IFF_PROMISC) /* promiscuous */
3569 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
3570 else if (dev->flags & IFF_ALLMULTI)
3571 memset(filter, 0xff, sizeof(filter));
3572 else if (dev->mc_count == 0 && !rx_pause)
3573 reg &= ~GM_RXCR_MCF_ENA;
3576 reg |= GM_RXCR_MCF_ENA;
3579 sky2_add_filter(filter, pause_mc_addr);
3581 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
3582 sky2_add_filter(filter, list->dmi_addr);
3585 gma_write16(hw, port, GM_MC_ADDR_H1,
3586 (u16) filter[0] | ((u16) filter[1] << 8));
3587 gma_write16(hw, port, GM_MC_ADDR_H2,
3588 (u16) filter[2] | ((u16) filter[3] << 8));
3589 gma_write16(hw, port, GM_MC_ADDR_H3,
3590 (u16) filter[4] | ((u16) filter[5] << 8));
3591 gma_write16(hw, port, GM_MC_ADDR_H4,
3592 (u16) filter[6] | ((u16) filter[7] << 8));
3594 gma_write16(hw, port, GM_RX_CTRL, reg);
3597 /* Can have one global because blinking is controlled by
3598 * ethtool and that is always under RTNL mutex
3600 static void sky2_led(struct sky2_port *sky2, enum led_mode mode)
3602 struct sky2_hw *hw = sky2->hw;
3603 unsigned port = sky2->port;
3605 spin_lock_bh(&sky2->phy_lock);
3606 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3607 hw->chip_id == CHIP_ID_YUKON_EX ||
3608 hw->chip_id == CHIP_ID_YUKON_SUPR) {
3610 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3611 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3615 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3616 PHY_M_LEDC_LOS_CTRL(8) |
3617 PHY_M_LEDC_INIT_CTRL(8) |
3618 PHY_M_LEDC_STA1_CTRL(8) |
3619 PHY_M_LEDC_STA0_CTRL(8));
3622 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3623 PHY_M_LEDC_LOS_CTRL(9) |
3624 PHY_M_LEDC_INIT_CTRL(9) |
3625 PHY_M_LEDC_STA1_CTRL(9) |
3626 PHY_M_LEDC_STA0_CTRL(9));
3629 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3630 PHY_M_LEDC_LOS_CTRL(0xa) |
3631 PHY_M_LEDC_INIT_CTRL(0xa) |
3632 PHY_M_LEDC_STA1_CTRL(0xa) |
3633 PHY_M_LEDC_STA0_CTRL(0xa));
3636 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3637 PHY_M_LEDC_LOS_CTRL(1) |
3638 PHY_M_LEDC_INIT_CTRL(8) |
3639 PHY_M_LEDC_STA1_CTRL(7) |
3640 PHY_M_LEDC_STA0_CTRL(7));
3643 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3645 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
3646 PHY_M_LED_MO_DUP(mode) |
3647 PHY_M_LED_MO_10(mode) |
3648 PHY_M_LED_MO_100(mode) |
3649 PHY_M_LED_MO_1000(mode) |
3650 PHY_M_LED_MO_RX(mode) |
3651 PHY_M_LED_MO_TX(mode));
3653 spin_unlock_bh(&sky2->phy_lock);
3656 /* blink LED's for finding board */
3657 static int sky2_phys_id(struct net_device *dev, u32 data)
3659 struct sky2_port *sky2 = netdev_priv(dev);
3665 for (i = 0; i < data; i++) {
3666 sky2_led(sky2, MO_LED_ON);
3667 if (msleep_interruptible(500))
3669 sky2_led(sky2, MO_LED_OFF);
3670 if (msleep_interruptible(500))
3673 sky2_led(sky2, MO_LED_NORM);
3678 static void sky2_get_pauseparam(struct net_device *dev,
3679 struct ethtool_pauseparam *ecmd)
3681 struct sky2_port *sky2 = netdev_priv(dev);
3683 switch (sky2->flow_mode) {
3685 ecmd->tx_pause = ecmd->rx_pause = 0;
3688 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3691 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3694 ecmd->tx_pause = ecmd->rx_pause = 1;
3697 ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_PAUSE)
3698 ? AUTONEG_ENABLE : AUTONEG_DISABLE;
3701 static int sky2_set_pauseparam(struct net_device *dev,
3702 struct ethtool_pauseparam *ecmd)
3704 struct sky2_port *sky2 = netdev_priv(dev);
3706 if (ecmd->autoneg == AUTONEG_ENABLE)
3707 sky2->flags |= SKY2_FLAG_AUTO_PAUSE;
3709 sky2->flags &= ~SKY2_FLAG_AUTO_PAUSE;
3711 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
3713 if (netif_running(dev))
3714 sky2_phy_reinit(sky2);
3719 static int sky2_get_coalesce(struct net_device *dev,
3720 struct ethtool_coalesce *ecmd)
3722 struct sky2_port *sky2 = netdev_priv(dev);
3723 struct sky2_hw *hw = sky2->hw;
3725 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3726 ecmd->tx_coalesce_usecs = 0;
3728 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3729 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3731 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3733 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3734 ecmd->rx_coalesce_usecs = 0;
3736 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3737 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3739 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3741 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3742 ecmd->rx_coalesce_usecs_irq = 0;
3744 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3745 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3748 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3753 /* Note: this affect both ports */
3754 static int sky2_set_coalesce(struct net_device *dev,
3755 struct ethtool_coalesce *ecmd)
3757 struct sky2_port *sky2 = netdev_priv(dev);
3758 struct sky2_hw *hw = sky2->hw;
3759 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
3761 if (ecmd->tx_coalesce_usecs > tmax ||
3762 ecmd->rx_coalesce_usecs > tmax ||
3763 ecmd->rx_coalesce_usecs_irq > tmax)
3766 if (ecmd->tx_max_coalesced_frames >= sky2->tx_ring_size-1)
3768 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
3770 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
3773 if (ecmd->tx_coalesce_usecs == 0)
3774 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3776 sky2_write32(hw, STAT_TX_TIMER_INI,
3777 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3778 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3780 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3782 if (ecmd->rx_coalesce_usecs == 0)
3783 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3785 sky2_write32(hw, STAT_LEV_TIMER_INI,
3786 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3787 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3789 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3791 if (ecmd->rx_coalesce_usecs_irq == 0)
3792 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3794 sky2_write32(hw, STAT_ISR_TIMER_INI,
3795 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3796 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3798 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3802 static void sky2_get_ringparam(struct net_device *dev,
3803 struct ethtool_ringparam *ering)
3805 struct sky2_port *sky2 = netdev_priv(dev);
3807 ering->rx_max_pending = RX_MAX_PENDING;
3808 ering->rx_mini_max_pending = 0;
3809 ering->rx_jumbo_max_pending = 0;
3810 ering->tx_max_pending = TX_MAX_PENDING;
3812 ering->rx_pending = sky2->rx_pending;
3813 ering->rx_mini_pending = 0;
3814 ering->rx_jumbo_pending = 0;
3815 ering->tx_pending = sky2->tx_pending;
3818 static int sky2_set_ringparam(struct net_device *dev,
3819 struct ethtool_ringparam *ering)
3821 struct sky2_port *sky2 = netdev_priv(dev);
3823 if (ering->rx_pending > RX_MAX_PENDING ||
3824 ering->rx_pending < 8 ||
3825 ering->tx_pending < TX_MIN_PENDING ||
3826 ering->tx_pending > TX_MAX_PENDING)
3831 sky2->rx_pending = ering->rx_pending;
3832 sky2->tx_pending = ering->tx_pending;
3833 sky2->tx_ring_size = roundup_pow_of_two(sky2->tx_pending+1);
3835 return sky2_reattach(dev);
3838 static int sky2_get_regs_len(struct net_device *dev)
3843 static int sky2_reg_access_ok(struct sky2_hw *hw, unsigned int b)
3845 /* This complicated switch statement is to make sure and
3846 * only access regions that are unreserved.
3847 * Some blocks are only valid on dual port cards.
3851 case 5: /* Tx Arbiter 2 */
3853 case 14 ... 15: /* TX2 */
3854 case 17: case 19: /* Ram Buffer 2 */
3855 case 22 ... 23: /* Tx Ram Buffer 2 */
3856 case 25: /* Rx MAC Fifo 1 */
3857 case 27: /* Tx MAC Fifo 2 */
3858 case 31: /* GPHY 2 */
3859 case 40 ... 47: /* Pattern Ram 2 */
3860 case 52: case 54: /* TCP Segmentation 2 */
3861 case 112 ... 116: /* GMAC 2 */
3862 return hw->ports > 1;
3864 case 0: /* Control */
3865 case 2: /* Mac address */
3866 case 4: /* Tx Arbiter 1 */
3867 case 7: /* PCI express reg */
3869 case 12 ... 13: /* TX1 */
3870 case 16: case 18:/* Rx Ram Buffer 1 */
3871 case 20 ... 21: /* Tx Ram Buffer 1 */
3872 case 24: /* Rx MAC Fifo 1 */
3873 case 26: /* Tx MAC Fifo 1 */
3874 case 28 ... 29: /* Descriptor and status unit */
3875 case 30: /* GPHY 1*/
3876 case 32 ... 39: /* Pattern Ram 1 */
3877 case 48: case 50: /* TCP Segmentation 1 */
3878 case 56 ... 60: /* PCI space */
3879 case 80 ... 84: /* GMAC 1 */
3888 * Returns copy of control register region
3889 * Note: ethtool_get_regs always provides full size (16k) buffer
3891 static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3894 const struct sky2_port *sky2 = netdev_priv(dev);
3895 const void __iomem *io = sky2->hw->regs;
3900 for (b = 0; b < 128; b++) {
3901 /* skip poisonous diagnostic ram region in block 3 */
3903 memcpy_fromio(p + 0x10, io + 0x10, 128 - 0x10);
3904 else if (sky2_reg_access_ok(sky2->hw, b))
3905 memcpy_fromio(p, io, 128);
3914 /* In order to do Jumbo packets on these chips, need to turn off the
3915 * transmit store/forward. Therefore checksum offload won't work.
3917 static int no_tx_offload(struct net_device *dev)
3919 const struct sky2_port *sky2 = netdev_priv(dev);
3920 const struct sky2_hw *hw = sky2->hw;
3922 return dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U;
3925 static int sky2_set_tx_csum(struct net_device *dev, u32 data)
3927 if (data && no_tx_offload(dev))
3930 return ethtool_op_set_tx_csum(dev, data);
3934 static int sky2_set_tso(struct net_device *dev, u32 data)
3936 if (data && no_tx_offload(dev))
3939 return ethtool_op_set_tso(dev, data);
3942 static int sky2_get_eeprom_len(struct net_device *dev)
3944 struct sky2_port *sky2 = netdev_priv(dev);
3945 struct sky2_hw *hw = sky2->hw;
3948 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
3949 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
3952 static int sky2_vpd_wait(const struct sky2_hw *hw, int cap, u16 busy)
3954 unsigned long start = jiffies;
3956 while ( (sky2_pci_read16(hw, cap + PCI_VPD_ADDR) & PCI_VPD_ADDR_F) == busy) {
3957 /* Can take up to 10.6 ms for write */
3958 if (time_after(jiffies, start + HZ/4)) {
3959 dev_err(&hw->pdev->dev, PFX "VPD cycle timed out");
3968 static int sky2_vpd_read(struct sky2_hw *hw, int cap, void *data,
3969 u16 offset, size_t length)
3973 while (length > 0) {
3976 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset);
3977 rc = sky2_vpd_wait(hw, cap, 0);
3981 val = sky2_pci_read32(hw, cap + PCI_VPD_DATA);
3983 memcpy(data, &val, min(sizeof(val), length));
3984 offset += sizeof(u32);
3985 data += sizeof(u32);
3986 length -= sizeof(u32);
3992 static int sky2_vpd_write(struct sky2_hw *hw, int cap, const void *data,
3993 u16 offset, unsigned int length)
3998 for (i = 0; i < length; i += sizeof(u32)) {
3999 u32 val = *(u32 *)(data + i);
4001 sky2_pci_write32(hw, cap + PCI_VPD_DATA, val);
4002 sky2_pci_write32(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F);
4004 rc = sky2_vpd_wait(hw, cap, PCI_VPD_ADDR_F);
4011 static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4014 struct sky2_port *sky2 = netdev_priv(dev);
4015 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
4020 eeprom->magic = SKY2_EEPROM_MAGIC;
4022 return sky2_vpd_read(sky2->hw, cap, data, eeprom->offset, eeprom->len);
4025 static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4028 struct sky2_port *sky2 = netdev_priv(dev);
4029 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
4034 if (eeprom->magic != SKY2_EEPROM_MAGIC)
4037 /* Partial writes not supported */
4038 if ((eeprom->offset & 3) || (eeprom->len & 3))
4041 return sky2_vpd_write(sky2->hw, cap, data, eeprom->offset, eeprom->len);
4045 static const struct ethtool_ops sky2_ethtool_ops = {
4046 .get_settings = sky2_get_settings,
4047 .set_settings = sky2_set_settings,
4048 .get_drvinfo = sky2_get_drvinfo,
4049 .get_wol = sky2_get_wol,
4050 .set_wol = sky2_set_wol,
4051 .get_msglevel = sky2_get_msglevel,
4052 .set_msglevel = sky2_set_msglevel,
4053 .nway_reset = sky2_nway_reset,
4054 .get_regs_len = sky2_get_regs_len,
4055 .get_regs = sky2_get_regs,
4056 .get_link = ethtool_op_get_link,
4057 .get_eeprom_len = sky2_get_eeprom_len,
4058 .get_eeprom = sky2_get_eeprom,
4059 .set_eeprom = sky2_set_eeprom,
4060 .set_sg = ethtool_op_set_sg,
4061 .set_tx_csum = sky2_set_tx_csum,
4062 .set_tso = sky2_set_tso,
4063 .get_rx_csum = sky2_get_rx_csum,
4064 .set_rx_csum = sky2_set_rx_csum,
4065 .get_strings = sky2_get_strings,
4066 .get_coalesce = sky2_get_coalesce,
4067 .set_coalesce = sky2_set_coalesce,
4068 .get_ringparam = sky2_get_ringparam,
4069 .set_ringparam = sky2_set_ringparam,
4070 .get_pauseparam = sky2_get_pauseparam,
4071 .set_pauseparam = sky2_set_pauseparam,
4072 .phys_id = sky2_phys_id,
4073 .get_sset_count = sky2_get_sset_count,
4074 .get_ethtool_stats = sky2_get_ethtool_stats,
4077 #ifdef CONFIG_SKY2_DEBUG
4079 static struct dentry *sky2_debug;
4083 * Read and parse the first part of Vital Product Data
4085 #define VPD_SIZE 128
4086 #define VPD_MAGIC 0x82
4088 static const struct vpd_tag {
4092 { "PN", "Part Number" },
4093 { "EC", "Engineering Level" },
4094 { "MN", "Manufacturer" },
4095 { "SN", "Serial Number" },
4096 { "YA", "Asset Tag" },
4097 { "VL", "First Error Log Message" },
4098 { "VF", "Second Error Log Message" },
4099 { "VB", "Boot Agent ROM Configuration" },
4100 { "VE", "EFI UNDI Configuration" },
4103 static void sky2_show_vpd(struct seq_file *seq, struct sky2_hw *hw)
4111 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
4112 vpd_size = 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
4114 seq_printf(seq, "%s Product Data\n", pci_name(hw->pdev));
4115 buf = kmalloc(vpd_size, GFP_KERNEL);
4117 seq_puts(seq, "no memory!\n");
4121 if (pci_read_vpd(hw->pdev, 0, vpd_size, buf) < 0) {
4122 seq_puts(seq, "VPD read failed\n");
4126 if (buf[0] != VPD_MAGIC) {
4127 seq_printf(seq, "VPD tag mismatch: %#x\n", buf[0]);
4131 if (len == 0 || len > vpd_size - 4) {
4132 seq_printf(seq, "Invalid id length: %d\n", len);
4136 seq_printf(seq, "%.*s\n", len, buf + 3);
4139 while (offs < vpd_size - 4) {
4142 if (!memcmp("RW", buf + offs, 2)) /* end marker */
4144 len = buf[offs + 2];
4145 if (offs + len + 3 >= vpd_size)
4148 for (i = 0; i < ARRAY_SIZE(vpd_tags); i++) {
4149 if (!memcmp(vpd_tags[i].tag, buf + offs, 2)) {
4150 seq_printf(seq, " %s: %.*s\n",
4151 vpd_tags[i].label, len, buf + offs + 3);
4161 static int sky2_debug_show(struct seq_file *seq, void *v)
4163 struct net_device *dev = seq->private;
4164 const struct sky2_port *sky2 = netdev_priv(dev);
4165 struct sky2_hw *hw = sky2->hw;
4166 unsigned port = sky2->port;
4170 sky2_show_vpd(seq, hw);
4172 seq_printf(seq, "\nIRQ src=%x mask=%x control=%x\n",
4173 sky2_read32(hw, B0_ISRC),
4174 sky2_read32(hw, B0_IMSK),
4175 sky2_read32(hw, B0_Y2_SP_ICR));
4177 if (!netif_running(dev)) {
4178 seq_printf(seq, "network not running\n");
4182 napi_disable(&hw->napi);
4183 last = sky2_read16(hw, STAT_PUT_IDX);
4185 if (hw->st_idx == last)
4186 seq_puts(seq, "Status ring (empty)\n");
4188 seq_puts(seq, "Status ring\n");
4189 for (idx = hw->st_idx; idx != last && idx < STATUS_RING_SIZE;
4190 idx = RING_NEXT(idx, STATUS_RING_SIZE)) {
4191 const struct sky2_status_le *le = hw->st_le + idx;
4192 seq_printf(seq, "[%d] %#x %d %#x\n",
4193 idx, le->opcode, le->length, le->status);
4195 seq_puts(seq, "\n");
4198 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n",
4199 sky2->tx_cons, sky2->tx_prod,
4200 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
4201 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
4203 /* Dump contents of tx ring */
4205 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < sky2->tx_ring_size;
4206 idx = RING_NEXT(idx, sky2->tx_ring_size)) {
4207 const struct sky2_tx_le *le = sky2->tx_le + idx;
4208 u32 a = le32_to_cpu(le->addr);
4211 seq_printf(seq, "%u:", idx);
4214 switch(le->opcode & ~HW_OWNER) {
4216 seq_printf(seq, " %#x:", a);
4219 seq_printf(seq, " mtu=%d", a);
4222 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length));
4225 seq_printf(seq, " csum=%#x", a);
4228 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length));
4231 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length));
4234 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length));
4237 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode,
4238 a, le16_to_cpu(le->length));
4241 if (le->ctrl & EOP) {
4242 seq_putc(seq, '\n');
4247 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
4248 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
4249 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
4250 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
4252 sky2_read32(hw, B0_Y2_SP_LISR);
4253 napi_enable(&hw->napi);
4257 static int sky2_debug_open(struct inode *inode, struct file *file)
4259 return single_open(file, sky2_debug_show, inode->i_private);
4262 static const struct file_operations sky2_debug_fops = {
4263 .owner = THIS_MODULE,
4264 .open = sky2_debug_open,
4266 .llseek = seq_lseek,
4267 .release = single_release,
4271 * Use network device events to create/remove/rename
4272 * debugfs file entries
4274 static int sky2_device_event(struct notifier_block *unused,
4275 unsigned long event, void *ptr)
4277 struct net_device *dev = ptr;
4278 struct sky2_port *sky2 = netdev_priv(dev);
4280 if (dev->netdev_ops->ndo_open != sky2_up || !sky2_debug)
4284 case NETDEV_CHANGENAME:
4285 if (sky2->debugfs) {
4286 sky2->debugfs = debugfs_rename(sky2_debug, sky2->debugfs,
4287 sky2_debug, dev->name);
4291 case NETDEV_GOING_DOWN:
4292 if (sky2->debugfs) {
4293 printk(KERN_DEBUG PFX "%s: remove debugfs\n",
4295 debugfs_remove(sky2->debugfs);
4296 sky2->debugfs = NULL;
4301 sky2->debugfs = debugfs_create_file(dev->name, S_IRUGO,
4304 if (IS_ERR(sky2->debugfs))
4305 sky2->debugfs = NULL;
4311 static struct notifier_block sky2_notifier = {
4312 .notifier_call = sky2_device_event,
4316 static __init void sky2_debug_init(void)
4320 ent = debugfs_create_dir("sky2", NULL);
4321 if (!ent || IS_ERR(ent))
4325 register_netdevice_notifier(&sky2_notifier);
4328 static __exit void sky2_debug_cleanup(void)
4331 unregister_netdevice_notifier(&sky2_notifier);
4332 debugfs_remove(sky2_debug);
4338 #define sky2_debug_init()
4339 #define sky2_debug_cleanup()
4342 /* Two copies of network device operations to handle special case of
4343 not allowing netpoll on second port */
4344 static const struct net_device_ops sky2_netdev_ops[2] = {
4346 .ndo_open = sky2_up,
4347 .ndo_stop = sky2_down,
4348 .ndo_start_xmit = sky2_xmit_frame,
4349 .ndo_do_ioctl = sky2_ioctl,
4350 .ndo_validate_addr = eth_validate_addr,
4351 .ndo_set_mac_address = sky2_set_mac_address,
4352 .ndo_set_multicast_list = sky2_set_multicast,
4353 .ndo_change_mtu = sky2_change_mtu,
4354 .ndo_tx_timeout = sky2_tx_timeout,
4355 #ifdef SKY2_VLAN_TAG_USED
4356 .ndo_vlan_rx_register = sky2_vlan_rx_register,
4358 #ifdef CONFIG_NET_POLL_CONTROLLER
4359 .ndo_poll_controller = sky2_netpoll,
4363 .ndo_open = sky2_up,
4364 .ndo_stop = sky2_down,
4365 .ndo_start_xmit = sky2_xmit_frame,
4366 .ndo_do_ioctl = sky2_ioctl,
4367 .ndo_validate_addr = eth_validate_addr,
4368 .ndo_set_mac_address = sky2_set_mac_address,
4369 .ndo_set_multicast_list = sky2_set_multicast,
4370 .ndo_change_mtu = sky2_change_mtu,
4371 .ndo_tx_timeout = sky2_tx_timeout,
4372 #ifdef SKY2_VLAN_TAG_USED
4373 .ndo_vlan_rx_register = sky2_vlan_rx_register,
4378 /* Initialize network device */
4379 static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
4381 int highmem, int wol)
4383 struct sky2_port *sky2;
4384 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
4387 dev_err(&hw->pdev->dev, "etherdev alloc failed\n");
4391 SET_NETDEV_DEV(dev, &hw->pdev->dev);
4392 dev->irq = hw->pdev->irq;
4393 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
4394 dev->watchdog_timeo = TX_WATCHDOG;
4395 dev->netdev_ops = &sky2_netdev_ops[port];
4397 sky2 = netdev_priv(dev);
4400 sky2->msg_enable = netif_msg_init(debug, default_msg);
4402 /* Auto speed and flow control */
4403 sky2->flags = SKY2_FLAG_AUTO_SPEED | SKY2_FLAG_AUTO_PAUSE;
4404 if (hw->chip_id != CHIP_ID_YUKON_XL)
4405 sky2->flags |= SKY2_FLAG_RX_CHECKSUM;
4407 sky2->flow_mode = FC_BOTH;
4411 sky2->advertising = sky2_supported_modes(hw);
4414 spin_lock_init(&sky2->phy_lock);
4416 sky2->tx_pending = TX_DEF_PENDING;
4417 sky2->tx_ring_size = roundup_pow_of_two(TX_DEF_PENDING+1);
4418 sky2->rx_pending = RX_DEF_PENDING;
4420 hw->dev[port] = dev;
4424 dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
4426 dev->features |= NETIF_F_HIGHDMA;
4428 #ifdef SKY2_VLAN_TAG_USED
4429 /* The workaround for FE+ status conflicts with VLAN tag detection. */
4430 if (!(sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
4431 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0)) {
4432 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
4436 /* read the mac address */
4437 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
4438 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
4443 static void __devinit sky2_show_addr(struct net_device *dev)
4445 const struct sky2_port *sky2 = netdev_priv(dev);
4447 if (netif_msg_probe(sky2))
4448 printk(KERN_INFO PFX "%s: addr %pM\n",
4449 dev->name, dev->dev_addr);
4452 /* Handle software interrupt used during MSI test */
4453 static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
4455 struct sky2_hw *hw = dev_id;
4456 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
4461 if (status & Y2_IS_IRQ_SW) {
4462 hw->flags |= SKY2_HW_USE_MSI;
4463 wake_up(&hw->msi_wait);
4464 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4466 sky2_write32(hw, B0_Y2_SP_ICR, 2);
4471 /* Test interrupt path by forcing a a software IRQ */
4472 static int __devinit sky2_test_msi(struct sky2_hw *hw)
4474 struct pci_dev *pdev = hw->pdev;
4477 init_waitqueue_head (&hw->msi_wait);
4479 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
4481 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
4483 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
4487 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
4488 sky2_read8(hw, B0_CTST);
4490 wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10);
4492 if (!(hw->flags & SKY2_HW_USE_MSI)) {
4493 /* MSI test failed, go back to INTx mode */
4494 dev_info(&pdev->dev, "No interrupt generated using MSI, "
4495 "switching to INTx mode.\n");
4498 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4501 sky2_write32(hw, B0_IMSK, 0);
4502 sky2_read32(hw, B0_IMSK);
4504 free_irq(pdev->irq, hw);
4509 /* This driver supports yukon2 chipset only */
4510 static const char *sky2_name(u8 chipid, char *buf, int sz)
4512 const char *name[] = {
4514 "EC Ultra", /* 0xb4 */
4515 "Extreme", /* 0xb5 */
4519 "Supreme", /* 0xb9 */
4521 "Unknown", /* 0xbb */
4522 "Optima", /* 0xbc */
4525 if (chipid >= CHIP_ID_YUKON_XL && chipid <= CHIP_ID_YUKON_OPT)
4526 strncpy(buf, name[chipid - CHIP_ID_YUKON_XL], sz);
4528 snprintf(buf, sz, "(chip %#x)", chipid);
4532 static int __devinit sky2_probe(struct pci_dev *pdev,
4533 const struct pci_device_id *ent)
4535 struct net_device *dev;
4537 int err, using_dac = 0, wol_default;
4541 err = pci_enable_device(pdev);
4543 dev_err(&pdev->dev, "cannot enable PCI device\n");
4547 /* Get configuration information
4548 * Note: only regular PCI config access once to test for HW issues
4549 * other PCI access through shared memory for speed and to
4550 * avoid MMCONFIG problems.
4552 err = pci_read_config_dword(pdev, PCI_DEV_REG2, ®);
4554 dev_err(&pdev->dev, "PCI read config failed\n");
4559 dev_err(&pdev->dev, "PCI configuration read error\n");
4563 err = pci_request_regions(pdev, DRV_NAME);
4565 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
4566 goto err_out_disable;
4569 pci_set_master(pdev);
4571 if (sizeof(dma_addr_t) > sizeof(u32) &&
4572 !(err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))) {
4574 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
4576 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
4577 "for consistent allocations\n");
4578 goto err_out_free_regions;
4581 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
4583 dev_err(&pdev->dev, "no usable DMA configuration\n");
4584 goto err_out_free_regions;
4590 /* The sk98lin vendor driver uses hardware byte swapping but
4591 * this driver uses software swapping.
4593 reg &= ~PCI_REV_DESC;
4594 err = pci_write_config_dword(pdev,PCI_DEV_REG2, reg);
4596 dev_err(&pdev->dev, "PCI write config failed\n");
4597 goto err_out_free_regions;
4601 wol_default = device_may_wakeup(&pdev->dev) ? WAKE_MAGIC : 0;
4605 hw = kzalloc(sizeof(*hw) + strlen(DRV_NAME "@pci:")
4606 + strlen(pci_name(pdev)) + 1, GFP_KERNEL);
4608 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
4609 goto err_out_free_regions;
4613 sprintf(hw->irq_name, DRV_NAME "@pci:%s", pci_name(pdev));
4615 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
4617 dev_err(&pdev->dev, "cannot map device registers\n");
4618 goto err_out_free_hw;
4621 /* ring for status responses */
4622 hw->st_le = pci_alloc_consistent(pdev, STATUS_LE_BYTES, &hw->st_dma);
4624 goto err_out_iounmap;
4626 err = sky2_init(hw);
4628 goto err_out_iounmap;
4630 dev_info(&pdev->dev, "Yukon-2 %s chip revision %d\n",
4631 sky2_name(hw->chip_id, buf1, sizeof(buf1)), hw->chip_rev);
4635 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
4638 goto err_out_free_pci;
4641 if (!disable_msi && pci_enable_msi(pdev) == 0) {
4642 err = sky2_test_msi(hw);
4643 if (err == -EOPNOTSUPP)
4644 pci_disable_msi(pdev);
4646 goto err_out_free_netdev;
4649 err = register_netdev(dev);
4651 dev_err(&pdev->dev, "cannot register net device\n");
4652 goto err_out_free_netdev;
4655 netif_carrier_off(dev);
4657 netif_napi_add(dev, &hw->napi, sky2_poll, NAPI_WEIGHT);
4659 err = request_irq(pdev->irq, sky2_intr,
4660 (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED,
4663 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
4664 goto err_out_unregister;
4666 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
4667 napi_enable(&hw->napi);
4669 sky2_show_addr(dev);
4671 if (hw->ports > 1) {
4672 struct net_device *dev1;
4675 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
4676 if (dev1 && (err = register_netdev(dev1)) == 0)
4677 sky2_show_addr(dev1);
4679 dev_warn(&pdev->dev,
4680 "register of second port failed (%d)\n", err);
4688 setup_timer(&hw->watchdog_timer, sky2_watchdog, (unsigned long) hw);
4689 INIT_WORK(&hw->restart_work, sky2_restart);
4691 pci_set_drvdata(pdev, hw);
4692 pdev->d3_delay = 150;
4697 if (hw->flags & SKY2_HW_USE_MSI)
4698 pci_disable_msi(pdev);
4699 unregister_netdev(dev);
4700 err_out_free_netdev:
4703 sky2_write8(hw, B0_CTST, CS_RST_SET);
4704 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
4709 err_out_free_regions:
4710 pci_release_regions(pdev);
4712 pci_disable_device(pdev);
4714 pci_set_drvdata(pdev, NULL);
4718 static void __devexit sky2_remove(struct pci_dev *pdev)
4720 struct sky2_hw *hw = pci_get_drvdata(pdev);
4726 del_timer_sync(&hw->watchdog_timer);
4727 cancel_work_sync(&hw->restart_work);
4729 for (i = hw->ports-1; i >= 0; --i)
4730 unregister_netdev(hw->dev[i]);
4732 sky2_write32(hw, B0_IMSK, 0);
4736 sky2_write8(hw, B0_CTST, CS_RST_SET);
4737 sky2_read8(hw, B0_CTST);
4739 free_irq(pdev->irq, hw);
4740 if (hw->flags & SKY2_HW_USE_MSI)
4741 pci_disable_msi(pdev);
4742 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
4743 pci_release_regions(pdev);
4744 pci_disable_device(pdev);
4746 for (i = hw->ports-1; i >= 0; --i)
4747 free_netdev(hw->dev[i]);
4752 pci_set_drvdata(pdev, NULL);
4756 static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
4758 struct sky2_hw *hw = pci_get_drvdata(pdev);
4764 del_timer_sync(&hw->watchdog_timer);
4765 cancel_work_sync(&hw->restart_work);
4768 for (i = 0; i < hw->ports; i++) {
4769 struct net_device *dev = hw->dev[i];
4770 struct sky2_port *sky2 = netdev_priv(dev);
4775 sky2_wol_init(sky2);
4780 sky2_write32(hw, B0_IMSK, 0);
4781 napi_disable(&hw->napi);
4785 pci_save_state(pdev);
4786 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
4787 pci_set_power_state(pdev, pci_choose_state(pdev, state));
4792 static int sky2_resume(struct pci_dev *pdev)
4794 struct sky2_hw *hw = pci_get_drvdata(pdev);
4800 err = pci_set_power_state(pdev, PCI_D0);
4804 err = pci_restore_state(pdev);
4808 pci_enable_wake(pdev, PCI_D0, 0);
4810 /* Re-enable all clocks */
4811 if (hw->chip_id == CHIP_ID_YUKON_EX ||
4812 hw->chip_id == CHIP_ID_YUKON_EC_U ||
4813 hw->chip_id == CHIP_ID_YUKON_FE_P)
4814 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
4817 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
4818 napi_enable(&hw->napi);
4821 for (i = 0; i < hw->ports; i++) {
4822 err = sky2_reattach(hw->dev[i]);
4832 dev_err(&pdev->dev, "resume failed (%d)\n", err);
4833 pci_disable_device(pdev);
4838 static void sky2_shutdown(struct pci_dev *pdev)
4840 struct sky2_hw *hw = pci_get_drvdata(pdev);
4847 del_timer_sync(&hw->watchdog_timer);
4849 for (i = 0; i < hw->ports; i++) {
4850 struct net_device *dev = hw->dev[i];
4851 struct sky2_port *sky2 = netdev_priv(dev);
4855 sky2_wol_init(sky2);
4863 pci_enable_wake(pdev, PCI_D3hot, wol);
4864 pci_enable_wake(pdev, PCI_D3cold, wol);
4866 pci_disable_device(pdev);
4867 pci_set_power_state(pdev, PCI_D3hot);
4870 static struct pci_driver sky2_driver = {
4872 .id_table = sky2_id_table,
4873 .probe = sky2_probe,
4874 .remove = __devexit_p(sky2_remove),
4876 .suspend = sky2_suspend,
4877 .resume = sky2_resume,
4879 .shutdown = sky2_shutdown,
4882 static int __init sky2_init_module(void)
4884 pr_info(PFX "driver version " DRV_VERSION "\n");
4887 return pci_register_driver(&sky2_driver);
4890 static void __exit sky2_cleanup_module(void)
4892 pci_unregister_driver(&sky2_driver);
4893 sky2_debug_cleanup();
4896 module_init(sky2_init_module);
4897 module_exit(sky2_cleanup_module);
4899 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
4900 MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
4901 MODULE_LICENSE("GPL");
4902 MODULE_VERSION(DRV_VERSION);