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   1 /*
   2  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
   3  *
   4  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
   5  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
   6  * Copyright (c) a lot of people too. Please respect their work.
   7  *
   8  * See MAINTAINERS file for support contact information.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/moduleparam.h>
  13 #include <linux/pci.h>
  14 #include <linux/netdevice.h>
  15 #include <linux/etherdevice.h>
  16 #include <linux/delay.h>
  17 #include <linux/ethtool.h>
  18 #include <linux/mii.h>
  19 #include <linux/if_vlan.h>
  20 #include <linux/crc32.h>
  21 #include <linux/in.h>
  22 #include <linux/ip.h>
  23 #include <linux/tcp.h>
  24 #include <linux/init.h>
  25 #include <linux/dma-mapping.h>
  26
  27 #include <asm/system.h>
  28 #include <asm/io.h>
  29 #include <asm/irq.h>
  30
  31 #define RTL8169_VERSION "2.3LK-NAPI"
  32 #define MODULENAME "r8169"
  33 #define PFX MODULENAME ": "
  34
  35 #ifdef RTL8169_DEBUG
  36 #define assert(expr) \
  37         if (!(expr)) {                                  \
  38                 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
  39                 #expr,__FILE__,__func__,__LINE__);              \
  40         }
  41 #define dprintk(fmt, args...) \
  42         do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
  43 #else
  44 #define assert(expr) do {} while (0)
  45 #define dprintk(fmt, args...)   do {} while (0)
  46 #endif /* RTL8169_DEBUG */
  47
  48 #define R8169_MSG_DEFAULT \
  49         (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
  50
  51 #define TX_BUFFS_AVAIL(tp) \
  52         (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
  53
  54 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
  55 static const int max_interrupt_work = 20;
  56
  57 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  58    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
  59 static const int multicast_filter_limit = 32;
  60
  61 /* MAC address length */
  62 #define MAC_ADDR_LEN    6
  63
  64 #define MAX_READ_REQUEST_SHIFT  12
  65 #define RX_FIFO_THRESH  7       /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
  66 #define RX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
  67 #define TX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
  68 #define EarlyTxThld     0x3F    /* 0x3F means NO early transmit */
  69 #define RxPacketMaxSize 0x3FE8  /* 16K - 1 - ETH_HLEN - VLAN - CRC... */
  70 #define SafeMtu         0x1c20  /* ... actually life sucks beyond ~7k */
  71 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
  72
  73 #define R8169_REGS_SIZE         256
  74 #define R8169_NAPI_WEIGHT       64
  75 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
  76 #define NUM_RX_DESC     256     /* Number of Rx descriptor registers */
  77 #define RX_BUF_SIZE     1536    /* Rx Buffer size */
  78 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
  79 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
  80
  81 #define RTL8169_TX_TIMEOUT      (6*HZ)
  82 #define RTL8169_PHY_TIMEOUT     (10*HZ)
  83
  84 /* write/read MMIO register */
  85 #define RTL_W8(reg, val8)       writeb ((val8), ioaddr + (reg))
  86 #define RTL_W16(reg, val16)     writew ((val16), ioaddr + (reg))
  87 #define RTL_W32(reg, val32)     writel ((val32), ioaddr + (reg))
  88 #define RTL_R8(reg)             readb (ioaddr + (reg))
  89 #define RTL_R16(reg)            readw (ioaddr + (reg))
  90 #define RTL_R32(reg)            ((unsigned long) readl (ioaddr + (reg)))
  91
  92 enum mac_version {
  93         RTL_GIGA_MAC_VER_01 = 0x01, // 8169
  94         RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
  95         RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
  96         RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
  97         RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
  98         RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
  99         RTL_GIGA_MAC_VER_07 = 0x07, // 8102e
 100         RTL_GIGA_MAC_VER_08 = 0x08, // 8102e
 101         RTL_GIGA_MAC_VER_09 = 0x09, // 8102e
 102         RTL_GIGA_MAC_VER_10 = 0x0a, // 8101e
 103         RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
 104         RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be
 105         RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb
 106         RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ?
 107         RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ?
 108         RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec
 109         RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf
 110         RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP
 111         RTL_GIGA_MAC_VER_19 = 0x13, // 8168C
 112         RTL_GIGA_MAC_VER_20 = 0x14  // 8168C
 113 };
 114
 115 #define _R(NAME,MAC,MASK) \
 116         { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
 117
 118 static const struct {
 119         const char *name;
 120         u8 mac_version;
 121         u32 RxConfigMask;       /* Clears the bits supported by this chip */
 122 } rtl_chip_info[] = {
 123         _R("RTL8169",           RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
 124         _R("RTL8169s",          RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
 125         _R("RTL8110s",          RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
 126         _R("RTL8169sb/8110sb",  RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
 127         _R("RTL8169sc/8110sc",  RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
 128         _R("RTL8169sc/8110sc",  RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
 129         _R("RTL8102e",          RTL_GIGA_MAC_VER_07, 0xff7e1880), // PCI-E
 130         _R("RTL8102e",          RTL_GIGA_MAC_VER_08, 0xff7e1880), // PCI-E
 131         _R("RTL8102e",          RTL_GIGA_MAC_VER_09, 0xff7e1880), // PCI-E
 132         _R("RTL8101e",          RTL_GIGA_MAC_VER_10, 0xff7e1880), // PCI-E
 133         _R("RTL8168b/8111b",    RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
 134         _R("RTL8168b/8111b",    RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
 135         _R("RTL8101e",          RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
 136         _R("RTL8100e",          RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
 137         _R("RTL8100e",          RTL_GIGA_MAC_VER_15, 0xff7e1880), // PCI-E 8139
 138         _R("RTL8168b/8111b",    RTL_GIGA_MAC_VER_17, 0xff7e1880), // PCI-E
 139         _R("RTL8101e",          RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E
 140         _R("RTL8168cp/8111cp",  RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E
 141         _R("RTL8168c/8111c",    RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E
 142         _R("RTL8168c/8111c",    RTL_GIGA_MAC_VER_20, 0xff7e1880)  // PCI-E
 143 };
 144 #undef _R
 145
 146 enum cfg_version {
 147         RTL_CFG_0 = 0x00,
 148         RTL_CFG_1,
 149         RTL_CFG_2
 150 };
 151
 152 static void rtl_hw_start_8169(struct net_device *);
 153 static void rtl_hw_start_8168(struct net_device *);
 154 static void rtl_hw_start_8101(struct net_device *);
 155
 156 static struct pci_device_id rtl8169_pci_tbl[] = {
 157         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8129), 0, 0, RTL_CFG_0 },
 158         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8136), 0, 0, RTL_CFG_2 },
 159         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8167), 0, 0, RTL_CFG_0 },
 160         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8168), 0, 0, RTL_CFG_1 },
 161         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8169), 0, 0, RTL_CFG_0 },
 162         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4300), 0, 0, RTL_CFG_0 },
 163         { PCI_DEVICE(PCI_VENDOR_ID_AT,          0xc107), 0, 0, RTL_CFG_0 },
 164         { PCI_DEVICE(0x16ec,                    0x0116), 0, 0, RTL_CFG_0 },
 165         { PCI_VENDOR_ID_LINKSYS,                0x1032,
 166                 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
 167         { 0x0001,                               0x8168,
 168                 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
 169         {0,},
 170 };
 171
 172 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
 173
 174 static int rx_copybreak = 200;
 175 static int use_dac;
 176 static struct {
 177         u32 msg_enable;
 178 } debug = { -1 };
 179
 180 enum rtl_registers {
 181         MAC0            = 0,    /* Ethernet hardware address. */
 182         MAC4            = 4,
 183         MAR0            = 8,    /* Multicast filter. */
 184         CounterAddrLow          = 0x10,
 185         CounterAddrHigh         = 0x14,
 186         TxDescStartAddrLow      = 0x20,
 187         TxDescStartAddrHigh     = 0x24,
 188         TxHDescStartAddrLow     = 0x28,
 189         TxHDescStartAddrHigh    = 0x2c,
 190         FLASH           = 0x30,
 191         ERSR            = 0x36,
 192         ChipCmd         = 0x37,
 193         TxPoll          = 0x38,
 194         IntrMask        = 0x3c,
 195         IntrStatus      = 0x3e,
 196         TxConfig        = 0x40,
 197         RxConfig        = 0x44,
 198         RxMissed        = 0x4c,
 199         Cfg9346         = 0x50,
 200         Config0         = 0x51,
 201         Config1         = 0x52,
 202         Config2         = 0x53,
 203         Config3         = 0x54,
 204         Config4         = 0x55,
 205         Config5         = 0x56,
 206         MultiIntr       = 0x5c,
 207         PHYAR           = 0x60,
 208         PHYstatus       = 0x6c,
 209         RxMaxSize       = 0xda,
 210         CPlusCmd        = 0xe0,
 211         IntrMitigate    = 0xe2,
 212         RxDescAddrLow   = 0xe4,
 213         RxDescAddrHigh  = 0xe8,
 214         EarlyTxThres    = 0xec,
 215         FuncEvent       = 0xf0,
 216         FuncEventMask   = 0xf4,
 217         FuncPresetState = 0xf8,
 218         FuncForceEvent  = 0xfc,
 219 };
 220
 221 enum rtl8110_registers {
 222         TBICSR                  = 0x64,
 223         TBI_ANAR                = 0x68,
 224         TBI_LPAR                = 0x6a,
 225 };
 226
 227 enum rtl8168_8101_registers {
 228         CSIDR                   = 0x64,
 229         CSIAR                   = 0x68,
 230 #define CSIAR_FLAG                      0x80000000
 231 #define CSIAR_WRITE_CMD                 0x80000000
 232 #define CSIAR_BYTE_ENABLE               0x0f
 233 #define CSIAR_BYTE_ENABLE_SHIFT         12
 234 #define CSIAR_ADDR_MASK                 0x0fff
 235
 236         EPHYAR                  = 0x80,
 237 #define EPHYAR_FLAG                     0x80000000
 238 #define EPHYAR_WRITE_CMD                0x80000000
 239 #define EPHYAR_REG_MASK                 0x1f
 240 #define EPHYAR_REG_SHIFT                16
 241 #define EPHYAR_DATA_MASK                0xffff
 242         DBG_REG                 = 0xd1,
 243 #define FIX_NAK_1                       (1 << 4)
 244 #define FIX_NAK_2                       (1 << 3)
 245 };
 246
 247 enum rtl_register_content {
 248         /* InterruptStatusBits */
 249         SYSErr          = 0x8000,
 250         PCSTimeout      = 0x4000,
 251         SWInt           = 0x0100,
 252         TxDescUnavail   = 0x0080,
 253         RxFIFOOver      = 0x0040,
 254         LinkChg         = 0x0020,
 255         RxOverflow      = 0x0010,
 256         TxErr           = 0x0008,
 257         TxOK            = 0x0004,
 258         RxErr           = 0x0002,
 259         RxOK            = 0x0001,
 260
 261         /* RxStatusDesc */
 262         RxFOVF  = (1 << 23),
 263         RxRWT   = (1 << 22),
 264         RxRES   = (1 << 21),
 265         RxRUNT  = (1 << 20),
 266         RxCRC   = (1 << 19),
 267
 268         /* ChipCmdBits */
 269         CmdReset        = 0x10,
 270         CmdRxEnb        = 0x08,
 271         CmdTxEnb        = 0x04,
 272         RxBufEmpty      = 0x01,
 273
 274         /* TXPoll register p.5 */
 275         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
 276         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
 277         FSWInt          = 0x01,         /* Forced software interrupt */
 278
 279         /* Cfg9346Bits */
 280         Cfg9346_Lock    = 0x00,
 281         Cfg9346_Unlock  = 0xc0,
 282
 283         /* rx_mode_bits */
 284         AcceptErr       = 0x20,
 285         AcceptRunt      = 0x10,
 286         AcceptBroadcast = 0x08,
 287         AcceptMulticast = 0x04,
 288         AcceptMyPhys    = 0x02,
 289         AcceptAllPhys   = 0x01,
 290
 291         /* RxConfigBits */
 292         RxCfgFIFOShift  = 13,
 293         RxCfgDMAShift   =  8,
 294
 295         /* TxConfigBits */
 296         TxInterFrameGapShift = 24,
 297         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
 298
 299         /* Config1 register p.24 */
 300         LEDS1           = (1 << 7),
 301         LEDS0           = (1 << 6),
 302         MSIEnable       = (1 << 5),     /* Enable Message Signaled Interrupt */
 303         Speed_down      = (1 << 4),
 304         MEMMAP          = (1 << 3),
 305         IOMAP           = (1 << 2),
 306         VPD             = (1 << 1),
 307         PMEnable        = (1 << 0),     /* Power Management Enable */
 308
 309         /* Config2 register p. 25 */
 310         PCI_Clock_66MHz = 0x01,
 311         PCI_Clock_33MHz = 0x00,
 312
 313         /* Config3 register p.25 */
 314         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
 315         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
 316         Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
 317
 318         /* Config5 register p.27 */
 319         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
 320         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
 321         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
 322         LanWake         = (1 << 1),     /* LanWake enable/disable */
 323         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
 324
 325         /* TBICSR p.28 */
 326         TBIReset        = 0x80000000,
 327         TBILoopback     = 0x40000000,
 328         TBINwEnable     = 0x20000000,
 329         TBINwRestart    = 0x10000000,
 330         TBILinkOk       = 0x02000000,
 331         TBINwComplete   = 0x01000000,
 332
 333         /* CPlusCmd p.31 */
 334         EnableBist      = (1 << 15),    // 8168 8101
 335         Mac_dbgo_oe     = (1 << 14),    // 8168 8101
 336         Normal_mode     = (1 << 13),    // unused
 337         Force_half_dup  = (1 << 12),    // 8168 8101
 338         Force_rxflow_en = (1 << 11),    // 8168 8101
 339         Force_txflow_en = (1 << 10),    // 8168 8101
 340         Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
 341         ASF             = (1 << 8),     // 8168 8101
 342         PktCntrDisable  = (1 << 7),     // 8168 8101
 343         Mac_dbgo_sel    = 0x001c,       // 8168
 344         RxVlan          = (1 << 6),
 345         RxChkSum        = (1 << 5),
 346         PCIDAC          = (1 << 4),
 347         PCIMulRW        = (1 << 3),
 348         INTT_0          = 0x0000,       // 8168
 349         INTT_1          = 0x0001,       // 8168
 350         INTT_2          = 0x0002,       // 8168
 351         INTT_3          = 0x0003,       // 8168
 352
 353         /* rtl8169_PHYstatus */
 354         TBI_Enable      = 0x80,
 355         TxFlowCtrl      = 0x40,
 356         RxFlowCtrl      = 0x20,
 357         _1000bpsF       = 0x10,
 358         _100bps         = 0x08,
 359         _10bps          = 0x04,
 360         LinkStatus      = 0x02,
 361         FullDup         = 0x01,
 362
 363         /* _TBICSRBit */
 364         TBILinkOK       = 0x02000000,
 365
 366         /* DumpCounterCommand */
 367         CounterDump     = 0x8,
 368 };
 369
 370 enum desc_status_bit {
 371         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
 372         RingEnd         = (1 << 30), /* End of descriptor ring */
 373         FirstFrag       = (1 << 29), /* First segment of a packet */
 374         LastFrag        = (1 << 28), /* Final segment of a packet */
 375
 376         /* Tx private */
 377         LargeSend       = (1 << 27), /* TCP Large Send Offload (TSO) */
 378         MSSShift        = 16,        /* MSS value position */
 379         MSSMask         = 0xfff,     /* MSS value + LargeSend bit: 12 bits */
 380         IPCS            = (1 << 18), /* Calculate IP checksum */
 381         UDPCS           = (1 << 17), /* Calculate UDP/IP checksum */
 382         TCPCS           = (1 << 16), /* Calculate TCP/IP checksum */
 383         TxVlanTag       = (1 << 17), /* Add VLAN tag */
 384
 385         /* Rx private */
 386         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
 387         PID0            = (1 << 17), /* Protocol ID bit 2/2 */
 388
 389 #define RxProtoUDP      (PID1)
 390 #define RxProtoTCP      (PID0)
 391 #define RxProtoIP       (PID1 | PID0)
 392 #define RxProtoMask     RxProtoIP
 393
 394         IPFail          = (1 << 16), /* IP checksum failed */
 395         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
 396         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
 397         RxVlanTag       = (1 << 16), /* VLAN tag available */
 398 };
 399
 400 #define RsvdMask        0x3fffc000
 401
 402 struct TxDesc {
 403         __le32 opts1;
 404         __le32 opts2;
 405         __le64 addr;
 406 };
 407
 408 struct RxDesc {
 409         __le32 opts1;
 410         __le32 opts2;
 411         __le64 addr;
 412 };
 413
 414 struct ring_info {
 415         struct sk_buff  *skb;
 416         u32             len;
 417         u8              __pad[sizeof(void *) - sizeof(u32)];
 418 };
 419
 420 enum features {
 421         RTL_FEATURE_WOL         = (1 << 0),
 422         RTL_FEATURE_MSI         = (1 << 1),
 423         RTL_FEATURE_GMII        = (1 << 2),
 424 };
 425
 426 struct rtl8169_private {
 427         void __iomem *mmio_addr;        /* memory map physical address */
 428         struct pci_dev *pci_dev;        /* Index of PCI device */
 429         struct net_device *dev;
 430         struct napi_struct napi;
 431         spinlock_t lock;                /* spin lock flag */
 432         u32 msg_enable;
 433         int chipset;
 434         int mac_version;
 435         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
 436         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
 437         u32 dirty_rx;
 438         u32 dirty_tx;
 439         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
 440         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
 441         dma_addr_t TxPhyAddr;
 442         dma_addr_t RxPhyAddr;
 443         struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */
 444         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
 445         unsigned align;
 446         unsigned rx_buf_sz;
 447         struct timer_list timer;
 448         u16 cp_cmd;
 449         u16 intr_event;
 450         u16 napi_event;
 451         u16 intr_mask;
 452         int phy_auto_nego_reg;
 453         int phy_1000_ctrl_reg;
 454 #ifdef CONFIG_R8169_VLAN
 455         struct vlan_group *vlgrp;
 456 #endif
 457         int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
 458         int (*get_settings)(struct net_device *, struct ethtool_cmd *);
 459         void (*phy_reset_enable)(void __iomem *);
 460         void (*hw_start)(struct net_device *);
 461         unsigned int (*phy_reset_pending)(void __iomem *);
 462         unsigned int (*link_ok)(void __iomem *);
 463         int pcie_cap;
 464         struct delayed_work task;
 465         unsigned features;
 466
 467         struct mii_if_info mii;
 468 };
 469
 470 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
 471 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
 472 module_param(rx_copybreak, int, 0);
 473 MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
 474 module_param(use_dac, int, 0);
 475 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
 476 module_param_named(debug, debug.msg_enable, int, 0);
 477 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
 478 MODULE_LICENSE("GPL");
 479 MODULE_VERSION(RTL8169_VERSION);
 480
 481 static int rtl8169_open(struct net_device *dev);
 482 static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev);
 483 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
 484 static int rtl8169_init_ring(struct net_device *dev);
 485 static void rtl_hw_start(struct net_device *dev);
 486 static int rtl8169_close(struct net_device *dev);
 487 static void rtl_set_rx_mode(struct net_device *dev);
 488 static void rtl8169_tx_timeout(struct net_device *dev);
 489 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
 490 static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
 491                                 void __iomem *, u32 budget);
 492 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
 493 static void rtl8169_down(struct net_device *dev);
 494 static void rtl8169_rx_clear(struct rtl8169_private *tp);
 495 static int rtl8169_poll(struct napi_struct *napi, int budget);
 496
 497 static const unsigned int rtl8169_rx_config =
 498         (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
 499
 500 static void mdio_write(void __iomem *ioaddr, int reg_addr, int value)
 501 {
 502         int i;
 503
 504         RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
 505
 506         for (i = 20; i > 0; i--) {
 507                 /*
 508                  * Check if the RTL8169 has completed writing to the specified
 509                  * MII register.
 510                  */
 511                 if (!(RTL_R32(PHYAR) & 0x80000000))
 512                         break;
 513                 udelay(25);
 514         }
 515 }
 516
 517 static int mdio_read(void __iomem *ioaddr, int reg_addr)
 518 {
 519         int i, value = -1;
 520
 521         RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
 522
 523         for (i = 20; i > 0; i--) {
 524                 /*
 525                  * Check if the RTL8169 has completed retrieving data from
 526                  * the specified MII register.
 527                  */
 528                 if (RTL_R32(PHYAR) & 0x80000000) {
 529                         value = RTL_R32(PHYAR) & 0xffff;
 530                         break;
 531                 }
 532                 udelay(25);
 533         }
 534         return value;
 535 }
 536
 537 static void mdio_patch(void __iomem *ioaddr, int reg_addr, int value)
 538 {
 539         mdio_write(ioaddr, reg_addr, mdio_read(ioaddr, reg_addr) | value);
 540 }
 541
 542 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
 543                            int val)
 544 {
 545         struct rtl8169_private *tp = netdev_priv(dev);
 546         void __iomem *ioaddr = tp->mmio_addr;
 547
 548         mdio_write(ioaddr, location, val);
 549 }
 550
 551 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
 552 {
 553         struct rtl8169_private *tp = netdev_priv(dev);
 554         void __iomem *ioaddr = tp->mmio_addr;
 555
 556         return mdio_read(ioaddr, location);
 557 }
 558
 559 static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
 560 {
 561         unsigned int i;
 562
 563         RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
 564                 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
 565
 566         for (i = 0; i < 100; i++) {
 567                 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
 568                         break;
 569                 udelay(10);
 570         }
 571 }
 572
 573 static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
 574 {
 575         u16 value = 0xffff;
 576         unsigned int i;
 577
 578         RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
 579
 580         for (i = 0; i < 100; i++) {
 581                 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
 582                         value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
 583                         break;
 584                 }
 585                 udelay(10);
 586         }
 587
 588         return value;
 589 }
 590
 591 static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
 592 {
 593         unsigned int i;
 594
 595         RTL_W32(CSIDR, value);
 596         RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
 597                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
 598
 599         for (i = 0; i < 100; i++) {
 600                 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
 601                         break;
 602                 udelay(10);
 603         }
 604 }
 605
 606 static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
 607 {
 608         u32 value = ~0x00;
 609         unsigned int i;
 610
 611         RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
 612                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
 613
 614         for (i = 0; i < 100; i++) {
 615                 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
 616                         value = RTL_R32(CSIDR);
 617                         break;
 618                 }
 619                 udelay(10);
 620         }
 621
 622         return value;
 623 }
 624
 625 static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
 626 {
 627         RTL_W16(IntrMask, 0x0000);
 628
 629         RTL_W16(IntrStatus, 0xffff);
 630 }
 631
 632 static void rtl8169_asic_down(void __iomem *ioaddr)
 633 {
 634         RTL_W8(ChipCmd, 0x00);
 635         rtl8169_irq_mask_and_ack(ioaddr);
 636         RTL_R16(CPlusCmd);
 637 }
 638
 639 static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr)
 640 {
 641         return RTL_R32(TBICSR) & TBIReset;
 642 }
 643
 644 static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr)
 645 {
 646         return mdio_read(ioaddr, MII_BMCR) & BMCR_RESET;
 647 }
 648
 649 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
 650 {
 651         return RTL_R32(TBICSR) & TBILinkOk;
 652 }
 653
 654 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
 655 {
 656         return RTL_R8(PHYstatus) & LinkStatus;
 657 }
 658
 659 static void rtl8169_tbi_reset_enable(void __iomem *ioaddr)
 660 {
 661         RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
 662 }
 663
 664 static void rtl8169_xmii_reset_enable(void __iomem *ioaddr)
 665 {
 666         unsigned int val;
 667
 668         val = mdio_read(ioaddr, MII_BMCR) | BMCR_RESET;
 669         mdio_write(ioaddr, MII_BMCR, val & 0xffff);
 670 }
 671
 672 static void rtl8169_check_link_status(struct net_device *dev,
 673                                       struct rtl8169_private *tp,
 674                                       void __iomem *ioaddr)
 675 {
 676         unsigned long flags;
 677
 678         spin_lock_irqsave(&tp->lock, flags);
 679         if (tp->link_ok(ioaddr)) {
 680                 netif_carrier_on(dev);
 681                 if (netif_msg_ifup(tp))
 682                         printk(KERN_INFO PFX "%s: link up\n", dev->name);
 683         } else {
 684                 if (netif_msg_ifdown(tp))
 685                         printk(KERN_INFO PFX "%s: link down\n", dev->name);
 686                 netif_carrier_off(dev);
 687         }
 688         spin_unlock_irqrestore(&tp->lock, flags);
 689 }
 690
 691 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
 692 {
 693         struct rtl8169_private *tp = netdev_priv(dev);
 694         void __iomem *ioaddr = tp->mmio_addr;
 695         u8 options;
 696
 697         wol->wolopts = 0;
 698
 699 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
 700         wol->supported = WAKE_ANY;
 701
 702         spin_lock_irq(&tp->lock);
 703
 704         options = RTL_R8(Config1);
 705         if (!(options & PMEnable))
 706                 goto out_unlock;
 707
 708         options = RTL_R8(Config3);
 709         if (options & LinkUp)
 710                 wol->wolopts |= WAKE_PHY;
 711         if (options & MagicPacket)
 712                 wol->wolopts |= WAKE_MAGIC;
 713
 714         options = RTL_R8(Config5);
 715         if (options & UWF)
 716                 wol->wolopts |= WAKE_UCAST;
 717         if (options & BWF)
 718                 wol->wolopts |= WAKE_BCAST;
 719         if (options & MWF)
 720                 wol->wolopts |= WAKE_MCAST;
 721
 722 out_unlock:
 723         spin_unlock_irq(&tp->lock);
 724 }
 725
 726 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
 727 {
 728         struct rtl8169_private *tp = netdev_priv(dev);
 729         void __iomem *ioaddr = tp->mmio_addr;
 730         unsigned int i;
 731         static struct {
 732                 u32 opt;
 733                 u16 reg;
 734                 u8  mask;
 735         } cfg[] = {
 736                 { WAKE_ANY,   Config1, PMEnable },
 737                 { WAKE_PHY,   Config3, LinkUp },
 738                 { WAKE_MAGIC, Config3, MagicPacket },
 739                 { WAKE_UCAST, Config5, UWF },
 740                 { WAKE_BCAST, Config5, BWF },
 741                 { WAKE_MCAST, Config5, MWF },
 742                 { WAKE_ANY,   Config5, LanWake }
 743         };
 744
 745         spin_lock_irq(&tp->lock);
 746
 747         RTL_W8(Cfg9346, Cfg9346_Unlock);
 748
 749         for (i = 0; i < ARRAY_SIZE(cfg); i++) {
 750                 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
 751                 if (wol->wolopts & cfg[i].opt)
 752                         options |= cfg[i].mask;
 753                 RTL_W8(cfg[i].reg, options);
 754         }
 755
 756         RTL_W8(Cfg9346, Cfg9346_Lock);
 757
 758         if (wol->wolopts)
 759                 tp->features |= RTL_FEATURE_WOL;
 760         else
 761                 tp->features &= ~RTL_FEATURE_WOL;
 762         device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
 763
 764         spin_unlock_irq(&tp->lock);
 765
 766         return 0;
 767 }
 768
 769 static void rtl8169_get_drvinfo(struct net_device *dev,
 770                                 struct ethtool_drvinfo *info)
 771 {
 772         struct rtl8169_private *tp = netdev_priv(dev);
 773
 774         strcpy(info->driver, MODULENAME);
 775         strcpy(info->version, RTL8169_VERSION);
 776         strcpy(info->bus_info, pci_name(tp->pci_dev));
 777 }
 778
 779 static int rtl8169_get_regs_len(struct net_device *dev)
 780 {
 781         return R8169_REGS_SIZE;
 782 }
 783
 784 static int rtl8169_set_speed_tbi(struct net_device *dev,
 785                                  u8 autoneg, u16 speed, u8 duplex)
 786 {
 787         struct rtl8169_private *tp = netdev_priv(dev);
 788         void __iomem *ioaddr = tp->mmio_addr;
 789         int ret = 0;
 790         u32 reg;
 791
 792         reg = RTL_R32(TBICSR);
 793         if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
 794             (duplex == DUPLEX_FULL)) {
 795                 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
 796         } else if (autoneg == AUTONEG_ENABLE)
 797                 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
 798         else {
 799                 if (netif_msg_link(tp)) {
 800                         printk(KERN_WARNING "%s: "
 801                                "incorrect speed setting refused in TBI mode\n",
 802                                dev->name);
 803                 }
 804                 ret = -EOPNOTSUPP;
 805         }
 806
 807         return ret;
 808 }
 809
 810 static int rtl8169_set_speed_xmii(struct net_device *dev,
 811                                   u8 autoneg, u16 speed, u8 duplex)
 812 {
 813         struct rtl8169_private *tp = netdev_priv(dev);
 814         void __iomem *ioaddr = tp->mmio_addr;
 815         int auto_nego, giga_ctrl;
 816
 817         auto_nego = mdio_read(ioaddr, MII_ADVERTISE);
 818         auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
 819                        ADVERTISE_100HALF | ADVERTISE_100FULL);
 820         giga_ctrl = mdio_read(ioaddr, MII_CTRL1000);
 821         giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
 822
 823         if (autoneg == AUTONEG_ENABLE) {
 824                 auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
 825                               ADVERTISE_100HALF | ADVERTISE_100FULL);
 826                 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
 827         } else {
 828                 if (speed == SPEED_10)
 829                         auto_nego |= ADVERTISE_10HALF | ADVERTISE_10FULL;
 830                 else if (speed == SPEED_100)
 831                         auto_nego |= ADVERTISE_100HALF | ADVERTISE_100FULL;
 832                 else if (speed == SPEED_1000)
 833                         giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
 834
 835                 if (duplex == DUPLEX_HALF)
 836                         auto_nego &= ~(ADVERTISE_10FULL | ADVERTISE_100FULL);
 837
 838                 if (duplex == DUPLEX_FULL)
 839                         auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_100HALF);
 840
 841                 /* This tweak comes straight from Realtek's driver. */
 842                 if ((speed == SPEED_100) && (duplex == DUPLEX_HALF) &&
 843                     ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
 844                      (tp->mac_version == RTL_GIGA_MAC_VER_16))) {
 845                         auto_nego = ADVERTISE_100HALF | ADVERTISE_CSMA;
 846                 }
 847         }
 848
 849         /* The 8100e/8101e/8102e do Fast Ethernet only. */
 850         if ((tp->mac_version == RTL_GIGA_MAC_VER_07) ||
 851             (tp->mac_version == RTL_GIGA_MAC_VER_08) ||
 852             (tp->mac_version == RTL_GIGA_MAC_VER_09) ||
 853             (tp->mac_version == RTL_GIGA_MAC_VER_10) ||
 854             (tp->mac_version == RTL_GIGA_MAC_VER_13) ||
 855             (tp->mac_version == RTL_GIGA_MAC_VER_14) ||
 856             (tp->mac_version == RTL_GIGA_MAC_VER_15) ||
 857             (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
 858                 if ((giga_ctrl & (ADVERTISE_1000FULL | ADVERTISE_1000HALF)) &&
 859                     netif_msg_link(tp)) {
 860                         printk(KERN_INFO "%s: PHY does not support 1000Mbps.\n",
 861                                dev->name);
 862                 }
 863                 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
 864         }
 865
 866         auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
 867
 868         if ((tp->mac_version == RTL_GIGA_MAC_VER_11) ||
 869             (tp->mac_version == RTL_GIGA_MAC_VER_12) ||
 870             (tp->mac_version >= RTL_GIGA_MAC_VER_17)) {
 871                 /*
 872                  * Wake up the PHY.
 873                  * Vendor specific (0x1f) and reserved (0x0e) MII registers.
 874                  */
 875                 mdio_write(ioaddr, 0x1f, 0x0000);
 876                 mdio_write(ioaddr, 0x0e, 0x0000);
 877         }
 878
 879         tp->phy_auto_nego_reg = auto_nego;
 880         tp->phy_1000_ctrl_reg = giga_ctrl;
 881
 882         mdio_write(ioaddr, MII_ADVERTISE, auto_nego);
 883         mdio_write(ioaddr, MII_CTRL1000, giga_ctrl);
 884         mdio_write(ioaddr, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART);
 885         return 0;
 886 }
 887
 888 static int rtl8169_set_speed(struct net_device *dev,
 889                              u8 autoneg, u16 speed, u8 duplex)
 890 {
 891         struct rtl8169_private *tp = netdev_priv(dev);
 892         int ret;
 893
 894         ret = tp->set_speed(dev, autoneg, speed, duplex);
 895
 896         if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
 897                 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
 898
 899         return ret;
 900 }
 901
 902 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 903 {
 904         struct rtl8169_private *tp = netdev_priv(dev);
 905         unsigned long flags;
 906         int ret;
 907
 908         spin_lock_irqsave(&tp->lock, flags);
 909         ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
 910         spin_unlock_irqrestore(&tp->lock, flags);
 911
 912         return ret;
 913 }
 914
 915 static u32 rtl8169_get_rx_csum(struct net_device *dev)
 916 {
 917         struct rtl8169_private *tp = netdev_priv(dev);
 918
 919         return tp->cp_cmd & RxChkSum;
 920 }
 921
 922 static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
 923 {
 924         struct rtl8169_private *tp = netdev_priv(dev);
 925         void __iomem *ioaddr = tp->mmio_addr;
 926         unsigned long flags;
 927
 928         spin_lock_irqsave(&tp->lock, flags);
 929
 930         if (data)
 931                 tp->cp_cmd |= RxChkSum;
 932         else
 933                 tp->cp_cmd &= ~RxChkSum;
 934
 935         RTL_W16(CPlusCmd, tp->cp_cmd);
 936         RTL_R16(CPlusCmd);
 937
 938         spin_unlock_irqrestore(&tp->lock, flags);
 939
 940         return 0;
 941 }
 942
 943 #ifdef CONFIG_R8169_VLAN
 944
 945 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
 946                                       struct sk_buff *skb)
 947 {
 948         return (tp->vlgrp && vlan_tx_tag_present(skb)) ?
 949                 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
 950 }
 951
 952 static void rtl8169_vlan_rx_register(struct net_device *dev,
 953                                      struct vlan_group *grp)
 954 {
 955         struct rtl8169_private *tp = netdev_priv(dev);
 956         void __iomem *ioaddr = tp->mmio_addr;
 957         unsigned long flags;
 958
 959         spin_lock_irqsave(&tp->lock, flags);
 960         tp->vlgrp = grp;
 961         if (tp->vlgrp)
 962                 tp->cp_cmd |= RxVlan;
 963         else
 964                 tp->cp_cmd &= ~RxVlan;
 965         RTL_W16(CPlusCmd, tp->cp_cmd);
 966         RTL_R16(CPlusCmd);
 967         spin_unlock_irqrestore(&tp->lock, flags);
 968 }
 969
 970 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
 971                                struct sk_buff *skb)
 972 {
 973         u32 opts2 = le32_to_cpu(desc->opts2);
 974         struct vlan_group *vlgrp = tp->vlgrp;
 975         int ret;
 976
 977         if (vlgrp && (opts2 & RxVlanTag)) {
 978                 vlan_hwaccel_receive_skb(skb, vlgrp, swab16(opts2 & 0xffff));
 979                 ret = 0;
 980         } else
 981                 ret = -1;
 982         desc->opts2 = 0;
 983         return ret;
 984 }
 985
 986 #else /* !CONFIG_R8169_VLAN */
 987
 988 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
 989                                       struct sk_buff *skb)
 990 {
 991         return 0;
 992 }
 993
 994 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
 995                                struct sk_buff *skb)
 996 {
 997         return -1;
 998 }
 999
1000 #endif
1001
1002 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1003 {
1004         struct rtl8169_private *tp = netdev_priv(dev);
1005         void __iomem *ioaddr = tp->mmio_addr;
1006         u32 status;
1007
1008         cmd->supported =
1009                 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1010         cmd->port = PORT_FIBRE;
1011         cmd->transceiver = XCVR_INTERNAL;
1012
1013         status = RTL_R32(TBICSR);
1014         cmd->advertising = (status & TBINwEnable) ?  ADVERTISED_Autoneg : 0;
1015         cmd->autoneg = !!(status & TBINwEnable);
1016
1017         cmd->speed = SPEED_1000;
1018         cmd->duplex = DUPLEX_FULL; /* Always set */
1019
1020         return 0;
1021 }
1022
1023 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1024 {
1025         struct rtl8169_private *tp = netdev_priv(dev);
1026
1027         return mii_ethtool_gset(&tp->mii, cmd);
1028 }
1029
1030 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1031 {
1032         struct rtl8169_private *tp = netdev_priv(dev);
1033         unsigned long flags;
1034         int rc;
1035
1036         spin_lock_irqsave(&tp->lock, flags);
1037
1038         rc = tp->get_settings(dev, cmd);
1039
1040         spin_unlock_irqrestore(&tp->lock, flags);
1041         return rc;
1042 }
1043
1044 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1045                              void *p)
1046 {
1047         struct rtl8169_private *tp = netdev_priv(dev);
1048         unsigned long flags;
1049
1050         if (regs->len > R8169_REGS_SIZE)
1051                 regs->len = R8169_REGS_SIZE;
1052
1053         spin_lock_irqsave(&tp->lock, flags);
1054         memcpy_fromio(p, tp->mmio_addr, regs->len);
1055         spin_unlock_irqrestore(&tp->lock, flags);
1056 }
1057
1058 static u32 rtl8169_get_msglevel(struct net_device *dev)
1059 {
1060         struct rtl8169_private *tp = netdev_priv(dev);
1061
1062         return tp->msg_enable;
1063 }
1064
1065 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1066 {
1067         struct rtl8169_private *tp = netdev_priv(dev);
1068
1069         tp->msg_enable = value;
1070 }
1071
1072 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1073         "tx_packets",
1074         "rx_packets",
1075         "tx_errors",
1076         "rx_errors",
1077         "rx_missed",
1078         "align_errors",
1079         "tx_single_collisions",
1080         "tx_multi_collisions",
1081         "unicast",
1082         "broadcast",
1083         "multicast",
1084         "tx_aborted",
1085         "tx_underrun",
1086 };
1087
1088 struct rtl8169_counters {
1089         __le64  tx_packets;
1090         __le64  rx_packets;
1091         __le64  tx_errors;
1092         __le32  rx_errors;
1093         __le16  rx_missed;
1094         __le16  align_errors;
1095         __le32  tx_one_collision;
1096         __le32  tx_multi_collision;
1097         __le64  rx_unicast;
1098         __le64  rx_broadcast;
1099         __le32  rx_multicast;
1100         __le16  tx_aborted;
1101         __le16  tx_underun;
1102 };
1103
1104 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1105 {
1106         switch (sset) {
1107         case ETH_SS_STATS:
1108                 return ARRAY_SIZE(rtl8169_gstrings);
1109         default:
1110                 return -EOPNOTSUPP;
1111         }
1112 }
1113
1114 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1115                                       struct ethtool_stats *stats, u64 *data)
1116 {
1117         struct rtl8169_private *tp = netdev_priv(dev);
1118         void __iomem *ioaddr = tp->mmio_addr;
1119         struct rtl8169_counters *counters;
1120         dma_addr_t paddr;
1121         u32 cmd;
1122
1123         ASSERT_RTNL();
1124
1125         counters = pci_alloc_consistent(tp->pci_dev, sizeof(*counters), &paddr);
1126         if (!counters)
1127                 return;
1128
1129         RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1130         cmd = (u64)paddr & DMA_32BIT_MASK;
1131         RTL_W32(CounterAddrLow, cmd);
1132         RTL_W32(CounterAddrLow, cmd | CounterDump);
1133
1134         while (RTL_R32(CounterAddrLow) & CounterDump) {
1135                 if (msleep_interruptible(1))
1136                         break;
1137         }
1138
1139         RTL_W32(CounterAddrLow, 0);
1140         RTL_W32(CounterAddrHigh, 0);
1141
1142         data[0] = le64_to_cpu(counters->tx_packets);
1143         data[1] = le64_to_cpu(counters->rx_packets);
1144         data[2] = le64_to_cpu(counters->tx_errors);
1145         data[3] = le32_to_cpu(counters->rx_errors);
1146         data[4] = le16_to_cpu(counters->rx_missed);
1147         data[5] = le16_to_cpu(counters->align_errors);
1148         data[6] = le32_to_cpu(counters->tx_one_collision);
1149         data[7] = le32_to_cpu(counters->tx_multi_collision);
1150         data[8] = le64_to_cpu(counters->rx_unicast);
1151         data[9] = le64_to_cpu(counters->rx_broadcast);
1152         data[10] = le32_to_cpu(counters->rx_multicast);
1153         data[11] = le16_to_cpu(counters->tx_aborted);
1154         data[12] = le16_to_cpu(counters->tx_underun);
1155
1156         pci_free_consistent(tp->pci_dev, sizeof(*counters), counters, paddr);
1157 }
1158
1159 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1160 {
1161         switch(stringset) {
1162         case ETH_SS_STATS:
1163                 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1164                 break;
1165         }
1166 }
1167
1168 static const struct ethtool_ops rtl8169_ethtool_ops = {
1169         .get_drvinfo            = rtl8169_get_drvinfo,
1170         .get_regs_len           = rtl8169_get_regs_len,
1171         .get_link               = ethtool_op_get_link,
1172         .get_settings           = rtl8169_get_settings,
1173         .set_settings           = rtl8169_set_settings,
1174         .get_msglevel           = rtl8169_get_msglevel,
1175         .set_msglevel           = rtl8169_set_msglevel,
1176         .get_rx_csum            = rtl8169_get_rx_csum,
1177         .set_rx_csum            = rtl8169_set_rx_csum,
1178         .set_tx_csum            = ethtool_op_set_tx_csum,
1179         .set_sg                 = ethtool_op_set_sg,
1180         .set_tso                = ethtool_op_set_tso,
1181         .get_regs               = rtl8169_get_regs,
1182         .get_wol                = rtl8169_get_wol,
1183         .set_wol                = rtl8169_set_wol,
1184         .get_strings            = rtl8169_get_strings,
1185         .get_sset_count         = rtl8169_get_sset_count,
1186         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
1187 };
1188
1189 static void rtl8169_write_gmii_reg_bit(void __iomem *ioaddr, int reg,
1190                                        int bitnum, int bitval)
1191 {
1192         int val;
1193
1194         val = mdio_read(ioaddr, reg);
1195         val = (bitval == 1) ?
1196                 val | (bitval << bitnum) :  val & ~(0x0001 << bitnum);
1197         mdio_write(ioaddr, reg, val & 0xffff);
1198 }
1199
1200 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1201                                     void __iomem *ioaddr)
1202 {
1203         /*
1204          * The driver currently handles the 8168Bf and the 8168Be identically
1205          * but they can be identified more specifically through the test below
1206          * if needed:
1207          *
1208          * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1209          *
1210          * Same thing for the 8101Eb and the 8101Ec:
1211          *
1212          * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1213          */
1214         const struct {
1215                 u32 mask;
1216                 u32 val;
1217                 int mac_version;
1218         } mac_info[] = {
1219                 /* 8168B family. */
1220                 { 0x7c800000, 0x3c800000,       RTL_GIGA_MAC_VER_18 },
1221                 { 0x7cf00000, 0x3c000000,       RTL_GIGA_MAC_VER_19 },
1222                 { 0x7cf00000, 0x3c200000,       RTL_GIGA_MAC_VER_20 },
1223                 { 0x7c800000, 0x3c000000,       RTL_GIGA_MAC_VER_20 },
1224
1225                 /* 8168B family. */
1226                 { 0x7cf00000, 0x38000000,       RTL_GIGA_MAC_VER_12 },
1227                 { 0x7cf00000, 0x38500000,       RTL_GIGA_MAC_VER_17 },
1228                 { 0x7c800000, 0x38000000,       RTL_GIGA_MAC_VER_17 },
1229                 { 0x7c800000, 0x30000000,       RTL_GIGA_MAC_VER_11 },
1230
1231                 /* 8101 family. */
1232                 { 0x7cf00000, 0x34a00000,       RTL_GIGA_MAC_VER_09 },
1233                 { 0x7cf00000, 0x24a00000,       RTL_GIGA_MAC_VER_09 },
1234                 { 0x7cf00000, 0x34900000,       RTL_GIGA_MAC_VER_08 },
1235                 { 0x7cf00000, 0x24900000,       RTL_GIGA_MAC_VER_08 },
1236                 { 0x7cf00000, 0x34800000,       RTL_GIGA_MAC_VER_07 },
1237                 { 0x7cf00000, 0x24800000,       RTL_GIGA_MAC_VER_07 },
1238                 { 0x7cf00000, 0x34000000,       RTL_GIGA_MAC_VER_13 },
1239                 { 0x7cf00000, 0x34300000,       RTL_GIGA_MAC_VER_10 },
1240                 { 0x7cf00000, 0x34200000,       RTL_GIGA_MAC_VER_16 },
1241                 { 0x7c800000, 0x34800000,       RTL_GIGA_MAC_VER_09 },
1242                 { 0x7c800000, 0x24800000,       RTL_GIGA_MAC_VER_09 },
1243                 { 0x7c800000, 0x34000000,       RTL_GIGA_MAC_VER_16 },
1244                 /* FIXME: where did these entries come from ? -- FR */
1245                 { 0xfc800000, 0x38800000,       RTL_GIGA_MAC_VER_15 },
1246                 { 0xfc800000, 0x30800000,       RTL_GIGA_MAC_VER_14 },
1247
1248                 /* 8110 family. */
1249                 { 0xfc800000, 0x98000000,       RTL_GIGA_MAC_VER_06 },
1250                 { 0xfc800000, 0x18000000,       RTL_GIGA_MAC_VER_05 },
1251                 { 0xfc800000, 0x10000000,       RTL_GIGA_MAC_VER_04 },
1252                 { 0xfc800000, 0x04000000,       RTL_GIGA_MAC_VER_03 },
1253                 { 0xfc800000, 0x00800000,       RTL_GIGA_MAC_VER_02 },
1254                 { 0xfc800000, 0x00000000,       RTL_GIGA_MAC_VER_01 },
1255
1256                 { 0x00000000, 0x00000000,       RTL_GIGA_MAC_VER_01 }   /* Catch-all */
1257         }, *p = mac_info;
1258         u32 reg;
1259
1260         reg = RTL_R32(TxConfig);
1261         while ((reg & p->mask) != p->val)
1262                 p++;
1263         tp->mac_version = p->mac_version;
1264
1265         if (p->mask == 0x00000000) {
1266                 struct pci_dev *pdev = tp->pci_dev;
1267
1268                 dev_info(&pdev->dev, "unknown MAC (%08x)\n", reg);
1269         }
1270 }
1271
1272 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1273 {
1274         dprintk("mac_version = 0x%02x\n", tp->mac_version);
1275 }
1276
1277 struct phy_reg {
1278         u16 reg;
1279         u16 val;
1280 };
1281
1282 static void rtl_phy_write(void __iomem *ioaddr, struct phy_reg *regs, int len)
1283 {
1284         while (len-- > 0) {
1285                 mdio_write(ioaddr, regs->reg, regs->val);
1286                 regs++;
1287         }
1288 }
1289
1290 static void rtl8169s_hw_phy_config(void __iomem *ioaddr)
1291 {
1292         struct {
1293                 u16 regs[5]; /* Beware of bit-sign propagation */
1294         } phy_magic[5] = { {
1295                 { 0x0000,       //w 4 15 12 0
1296                   0x00a1,       //w 3 15 0 00a1
1297                   0x0008,       //w 2 15 0 0008
1298                   0x1020,       //w 1 15 0 1020
1299                   0x1000 } },{  //w 0 15 0 1000
1300                 { 0x7000,       //w 4 15 12 7
1301                   0xff41,       //w 3 15 0 ff41
1302                   0xde60,       //w 2 15 0 de60
1303                   0x0140,       //w 1 15 0 0140
1304                   0x0077 } },{  //w 0 15 0 0077
1305                 { 0xa000,       //w 4 15 12 a
1306                   0xdf01,       //w 3 15 0 df01
1307                   0xdf20,       //w 2 15 0 df20
1308                   0xff95,       //w 1 15 0 ff95
1309                   0xfa00 } },{  //w 0 15 0 fa00
1310                 { 0xb000,       //w 4 15 12 b
1311                   0xff41,       //w 3 15 0 ff41
1312                   0xde20,       //w 2 15 0 de20
1313                   0x0140,       //w 1 15 0 0140
1314                   0x00bb } },{  //w 0 15 0 00bb
1315                 { 0xf000,       //w 4 15 12 f
1316                   0xdf01,       //w 3 15 0 df01
1317                   0xdf20,       //w 2 15 0 df20
1318                   0xff95,       //w 1 15 0 ff95
1319                   0xbf00 }      //w 0 15 0 bf00
1320                 }
1321         }, *p = phy_magic;
1322         unsigned int i;
1323
1324         mdio_write(ioaddr, 0x1f, 0x0001);               //w 31 2 0 1
1325         mdio_write(ioaddr, 0x15, 0x1000);               //w 21 15 0 1000
1326         mdio_write(ioaddr, 0x18, 0x65c7);               //w 24 15 0 65c7
1327         rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0);   //w 4 11 11 0
1328
1329         for (i = 0; i < ARRAY_SIZE(phy_magic); i++, p++) {
1330                 int val, pos = 4;
1331
1332                 val = (mdio_read(ioaddr, pos) & 0x0fff) | (p->regs[0] & 0xffff);
1333                 mdio_write(ioaddr, pos, val);
1334                 while (--pos >= 0)
1335                         mdio_write(ioaddr, pos, p->regs[4 - pos] & 0xffff);
1336                 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 1); //w 4 11 11 1
1337                 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1338         }
1339         mdio_write(ioaddr, 0x1f, 0x0000); //w 31 2 0 0
1340 }
1341
1342 static void rtl8169sb_hw_phy_config(void __iomem *ioaddr)
1343 {
1344         struct phy_reg phy_reg_init[] = {
1345                 { 0x1f, 0x0002 },
1346                 { 0x01, 0x90d0 },
1347                 { 0x1f, 0x0000 }
1348         };
1349
1350         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1351 }
1352
1353 static void rtl8168cp_hw_phy_config(void __iomem *ioaddr)
1354 {
1355         struct phy_reg phy_reg_init[] = {
1356                 { 0x1f, 0x0000 },
1357                 { 0x1d, 0x0f00 },
1358                 { 0x1f, 0x0002 },
1359                 { 0x0c, 0x1ec8 },
1360                 { 0x1f, 0x0000 }
1361         };
1362
1363         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1364 }
1365
1366 static void rtl8168c_hw_phy_config(void __iomem *ioaddr)
1367 {
1368         struct phy_reg phy_reg_init[] = {
1369                 { 0x1f, 0x0001 },
1370                 { 0x12, 0x2300 },
1371                 { 0x1f, 0x0002 },
1372                 { 0x00, 0x88d4 },
1373                 { 0x01, 0x82b1 },
1374                 { 0x03, 0x7002 },
1375                 { 0x08, 0x9e30 },
1376                 { 0x09, 0x01f0 },
1377                 { 0x0a, 0x5500 },
1378                 { 0x0c, 0x00c8 },
1379                 { 0x1f, 0x0003 },
1380                 { 0x12, 0xc096 },
1381                 { 0x16, 0x000a },
1382                 { 0x1f, 0x0000 },
1383                 { 0x1f, 0x0000 },
1384                 { 0x09, 0x2000 },
1385                 { 0x09, 0x0000 }
1386         };
1387
1388         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1389
1390         mdio_patch(ioaddr, 0x14, 1 << 5);
1391         mdio_patch(ioaddr, 0x0d, 1 << 5);
1392         mdio_write(ioaddr, 0x1f, 0x0000);
1393 }
1394
1395 static void rtl8168cx_hw_phy_config(void __iomem *ioaddr)
1396 {
1397         struct phy_reg phy_reg_init[] = {
1398                 { 0x1f, 0x0001 },
1399                 { 0x12, 0x2300 },
1400                 { 0x03, 0x802f },
1401                 { 0x02, 0x4f02 },
1402                 { 0x01, 0x0409 },
1403                 { 0x00, 0xf099 },
1404                 { 0x04, 0x9800 },
1405                 { 0x04, 0x9000 },
1406                 { 0x1d, 0x3d98 },
1407                 { 0x1f, 0x0002 },
1408                 { 0x0c, 0x7eb8 },
1409                 { 0x06, 0x0761 },
1410                 { 0x1f, 0x0003 },
1411                 { 0x16, 0x0f0a },
1412                 { 0x1f, 0x0000 }
1413         };
1414
1415         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1416
1417         mdio_patch(ioaddr, 0x16, 1 << 0);
1418         mdio_patch(ioaddr, 0x14, 1 << 5);
1419         mdio_patch(ioaddr, 0x0d, 1 << 5);
1420         mdio_write(ioaddr, 0x1f, 0x0000);
1421 }
1422
1423 static void rtl8102e_hw_phy_config(void __iomem *ioaddr)
1424 {
1425         struct phy_reg phy_reg_init[] = {
1426                 { 0x1f, 0x0003 },
1427                 { 0x08, 0x441d },
1428                 { 0x01, 0x9100 },
1429                 { 0x1f, 0x0000 }
1430         };
1431
1432         mdio_write(ioaddr, 0x1f, 0x0000);
1433         mdio_patch(ioaddr, 0x11, 1 << 12);
1434         mdio_patch(ioaddr, 0x19, 1 << 13);
1435
1436         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1437 }
1438
1439 static void rtl_hw_phy_config(struct net_device *dev)
1440 {
1441         struct rtl8169_private *tp = netdev_priv(dev);
1442         void __iomem *ioaddr = tp->mmio_addr;
1443
1444         rtl8169_print_mac_version(tp);
1445
1446         switch (tp->mac_version) {
1447         case RTL_GIGA_MAC_VER_01:
1448                 break;
1449         case RTL_GIGA_MAC_VER_02:
1450         case RTL_GIGA_MAC_VER_03:
1451                 rtl8169s_hw_phy_config(ioaddr);
1452                 break;
1453         case RTL_GIGA_MAC_VER_04:
1454                 rtl8169sb_hw_phy_config(ioaddr);
1455                 break;
1456         case RTL_GIGA_MAC_VER_07:
1457         case RTL_GIGA_MAC_VER_08:
1458         case RTL_GIGA_MAC_VER_09:
1459                 rtl8102e_hw_phy_config(ioaddr);
1460                 break;
1461         case RTL_GIGA_MAC_VER_18:
1462                 rtl8168cp_hw_phy_config(ioaddr);
1463                 break;
1464         case RTL_GIGA_MAC_VER_19:
1465                 rtl8168c_hw_phy_config(ioaddr);
1466                 break;
1467         case RTL_GIGA_MAC_VER_20:
1468                 rtl8168cx_hw_phy_config(ioaddr);
1469                 break;
1470         default:
1471                 break;
1472         }
1473 }
1474
1475 static void rtl8169_phy_timer(unsigned long __opaque)
1476 {
1477         struct net_device *dev = (struct net_device *)__opaque;
1478         struct rtl8169_private *tp = netdev_priv(dev);
1479         struct timer_list *timer = &tp->timer;
1480         void __iomem *ioaddr = tp->mmio_addr;
1481         unsigned long timeout = RTL8169_PHY_TIMEOUT;
1482
1483         assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1484
1485         if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1486                 return;
1487
1488         spin_lock_irq(&tp->lock);
1489
1490         if (tp->phy_reset_pending(ioaddr)) {
1491                 /*
1492                  * A busy loop could burn quite a few cycles on nowadays CPU.
1493                  * Let's delay the execution of the timer for a few ticks.
1494                  */
1495                 timeout = HZ/10;
1496                 goto out_mod_timer;
1497         }
1498
1499         if (tp->link_ok(ioaddr))
1500                 goto out_unlock;
1501
1502         if (netif_msg_link(tp))
1503                 printk(KERN_WARNING "%s: PHY reset until link up\n", dev->name);
1504
1505         tp->phy_reset_enable(ioaddr);
1506
1507 out_mod_timer:
1508         mod_timer(timer, jiffies + timeout);
1509 out_unlock:
1510         spin_unlock_irq(&tp->lock);
1511 }
1512
1513 static inline void rtl8169_delete_timer(struct net_device *dev)
1514 {
1515         struct rtl8169_private *tp = netdev_priv(dev);
1516         struct timer_list *timer = &tp->timer;
1517
1518         if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1519                 return;
1520
1521         del_timer_sync(timer);
1522 }
1523
1524 static inline void rtl8169_request_timer(struct net_device *dev)
1525 {
1526         struct rtl8169_private *tp = netdev_priv(dev);
1527         struct timer_list *timer = &tp->timer;
1528
1529         if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1530                 return;
1531
1532         mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
1533 }
1534
1535 #ifdef CONFIG_NET_POLL_CONTROLLER
1536 /*
1537  * Polling 'interrupt' - used by things like netconsole to send skbs
1538  * without having to re-enable interrupts. It's not called while
1539  * the interrupt routine is executing.
1540  */
1541 static void rtl8169_netpoll(struct net_device *dev)
1542 {
1543         struct rtl8169_private *tp = netdev_priv(dev);
1544         struct pci_dev *pdev = tp->pci_dev;
1545
1546         disable_irq(pdev->irq);
1547         rtl8169_interrupt(pdev->irq, dev);
1548         enable_irq(pdev->irq);
1549 }
1550 #endif
1551
1552 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
1553                                   void __iomem *ioaddr)
1554 {
1555         iounmap(ioaddr);
1556         pci_release_regions(pdev);
1557         pci_disable_device(pdev);
1558         free_netdev(dev);
1559 }
1560
1561 static void rtl8169_phy_reset(struct net_device *dev,
1562                               struct rtl8169_private *tp)
1563 {
1564         void __iomem *ioaddr = tp->mmio_addr;
1565         unsigned int i;
1566
1567         tp->phy_reset_enable(ioaddr);
1568         for (i = 0; i < 100; i++) {
1569                 if (!tp->phy_reset_pending(ioaddr))
1570                         return;
1571                 msleep(1);
1572         }
1573         if (netif_msg_link(tp))
1574                 printk(KERN_ERR "%s: PHY reset failed.\n", dev->name);
1575 }
1576
1577 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
1578 {
1579         void __iomem *ioaddr = tp->mmio_addr;
1580
1581         rtl_hw_phy_config(dev);
1582
1583         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
1584                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1585                 RTL_W8(0x82, 0x01);
1586         }
1587
1588         pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
1589
1590         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
1591                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
1592
1593         if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
1594                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1595                 RTL_W8(0x82, 0x01);
1596                 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
1597                 mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0
1598         }
1599
1600         rtl8169_phy_reset(dev, tp);
1601
1602         /*
1603          * rtl8169_set_speed_xmii takes good care of the Fast Ethernet
1604          * only 8101. Don't panic.
1605          */
1606         rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL);
1607
1608         if ((RTL_R8(PHYstatus) & TBI_Enable) && netif_msg_link(tp))
1609                 printk(KERN_INFO PFX "%s: TBI auto-negotiating\n", dev->name);
1610 }
1611
1612 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
1613 {
1614         void __iomem *ioaddr = tp->mmio_addr;
1615         u32 high;
1616         u32 low;
1617
1618         low  = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
1619         high = addr[4] | (addr[5] << 8);
1620
1621         spin_lock_irq(&tp->lock);
1622
1623         RTL_W8(Cfg9346, Cfg9346_Unlock);
1624         RTL_W32(MAC0, low);
1625         RTL_W32(MAC4, high);
1626         RTL_W8(Cfg9346, Cfg9346_Lock);
1627
1628         spin_unlock_irq(&tp->lock);
1629 }
1630
1631 static int rtl_set_mac_address(struct net_device *dev, void *p)
1632 {
1633         struct rtl8169_private *tp = netdev_priv(dev);
1634         struct sockaddr *addr = p;
1635
1636         if (!is_valid_ether_addr(addr->sa_data))
1637                 return -EADDRNOTAVAIL;
1638
1639         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1640
1641         rtl_rar_set(tp, dev->dev_addr);
1642
1643         return 0;
1644 }
1645
1646 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1647 {
1648         struct rtl8169_private *tp = netdev_priv(dev);
1649         struct mii_ioctl_data *data = if_mii(ifr);
1650
1651         if (!netif_running(dev))
1652                 return -ENODEV;
1653
1654         switch (cmd) {
1655         case SIOCGMIIPHY:
1656                 data->phy_id = 32; /* Internal PHY */
1657                 return 0;
1658
1659         case SIOCGMIIREG:
1660                 data->val_out = mdio_read(tp->mmio_addr, data->reg_num & 0x1f);
1661                 return 0;
1662
1663         case SIOCSMIIREG:
1664                 if (!capable(CAP_NET_ADMIN))
1665                         return -EPERM;
1666                 mdio_write(tp->mmio_addr, data->reg_num & 0x1f, data->val_in);
1667                 return 0;
1668         }
1669         return -EOPNOTSUPP;
1670 }
1671
1672 static const struct rtl_cfg_info {
1673         void (*hw_start)(struct net_device *);
1674         unsigned int region;
1675         unsigned int align;
1676         u16 intr_event;
1677         u16 napi_event;
1678         unsigned features;
1679 } rtl_cfg_infos [] = {
1680         [RTL_CFG_0] = {
1681                 .hw_start       = rtl_hw_start_8169,
1682                 .region         = 1,
1683                 .align          = 0,
1684                 .intr_event     = SYSErr | LinkChg | RxOverflow |
1685                                   RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
1686                 .napi_event     = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
1687                 .features       = RTL_FEATURE_GMII
1688         },
1689         [RTL_CFG_1] = {
1690                 .hw_start       = rtl_hw_start_8168,
1691                 .region         = 2,
1692                 .align          = 8,
1693                 .intr_event     = SYSErr | LinkChg | RxOverflow |
1694                                   TxErr | TxOK | RxOK | RxErr,
1695                 .napi_event     = TxErr | TxOK | RxOK | RxOverflow,
1696                 .features       = RTL_FEATURE_GMII | RTL_FEATURE_MSI
1697         },
1698         [RTL_CFG_2] = {
1699                 .hw_start       = rtl_hw_start_8101,
1700                 .region         = 2,
1701                 .align          = 8,
1702                 .intr_event     = SYSErr | LinkChg | RxOverflow | PCSTimeout |
1703                                   RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
1704                 .napi_event     = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
1705                 .features       = RTL_FEATURE_MSI
1706         }
1707 };
1708
1709 /* Cfg9346_Unlock assumed. */
1710 static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
1711                             const struct rtl_cfg_info *cfg)
1712 {
1713         unsigned msi = 0;
1714         u8 cfg2;
1715
1716         cfg2 = RTL_R8(Config2) & ~MSIEnable;
1717         if (cfg->features & RTL_FEATURE_MSI) {
1718                 if (pci_enable_msi(pdev)) {
1719                         dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
1720                 } else {
1721                         cfg2 |= MSIEnable;
1722                         msi = RTL_FEATURE_MSI;
1723                 }
1724         }
1725         RTL_W8(Config2, cfg2);
1726         return msi;
1727 }
1728
1729 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
1730 {
1731         if (tp->features & RTL_FEATURE_MSI) {
1732                 pci_disable_msi(pdev);
1733                 tp->features &= ~RTL_FEATURE_MSI;
1734         }
1735 }
1736
1737 static int rtl_eeprom_read(struct pci_dev *pdev, int cap, int addr, __le32 *val)
1738 {
1739         int ret, count = 100;
1740         u16 status = 0;
1741         u32 value;
1742
1743         ret = pci_write_config_word(pdev, cap + PCI_VPD_ADDR, addr);
1744         if (ret < 0)
1745                 return ret;
1746
1747         do {
1748                 udelay(10);
1749                 ret = pci_read_config_word(pdev, cap + PCI_VPD_ADDR, &status);
1750                 if (ret < 0)
1751                         return ret;
1752         } while (!(status & PCI_VPD_ADDR_F) && --count);
1753
1754         if (!(status & PCI_VPD_ADDR_F))
1755                 return -ETIMEDOUT;
1756
1757         ret = pci_read_config_dword(pdev, cap + PCI_VPD_DATA, &value);
1758         if (ret < 0)
1759                 return ret;
1760
1761         *val = cpu_to_le32(value);
1762
1763         return 0;
1764 }
1765
1766 static void rtl_init_mac_address(struct rtl8169_private *tp,
1767                                  void __iomem *ioaddr)
1768 {
1769         struct pci_dev *pdev = tp->pci_dev;
1770         u8 cfg1;
1771         int vpd_cap;
1772         u8 mac[8];
1773         DECLARE_MAC_BUF(buf);
1774
1775         cfg1 = RTL_R8(Config1);
1776         if (!(cfg1  & VPD)) {
1777                 dprintk("VPD access not enabled, enabling\n");
1778                 RTL_W8(Cfg9346, Cfg9346_Unlock);
1779                 RTL_W8(Config1, cfg1 | VPD);
1780                 RTL_W8(Cfg9346, Cfg9346_Lock);
1781         }
1782
1783         vpd_cap = pci_find_capability(pdev, PCI_CAP_ID_VPD);
1784         if (!vpd_cap)
1785                 return;
1786
1787         /* MAC address is stored in EEPROM at offset 0x0e
1788          * Realtek says: "The VPD address does not have to be a DWORD-aligned
1789          * address as defined in the PCI 2.2 Specifications, but the VPD data
1790          * is always consecutive 4-byte data starting from the VPD address
1791          * specified."
1792          */
1793         if (rtl_eeprom_read(pdev, vpd_cap, 0x000e, (__le32*)&mac[0]) < 0 ||
1794             rtl_eeprom_read(pdev, vpd_cap, 0x0012, (__le32*)&mac[4]) < 0) {
1795                 dprintk("Reading MAC address from EEPROM failed\n");
1796                 return;
1797         }
1798
1799         dprintk("MAC address found in EEPROM: %s\n", print_mac(buf, mac));
1800
1801         /* Write MAC address */
1802         rtl_rar_set(tp, mac);
1803 }
1804
1805 static int __devinit
1806 rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1807 {
1808         const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
1809         const unsigned int region = cfg->region;
1810         struct rtl8169_private *tp;
1811         struct mii_if_info *mii;
1812         struct net_device *dev;
1813         void __iomem *ioaddr;
1814         unsigned int i;
1815         int rc;
1816
1817         if (netif_msg_drv(&debug)) {
1818                 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
1819                        MODULENAME, RTL8169_VERSION);
1820         }
1821
1822         dev = alloc_etherdev(sizeof (*tp));
1823         if (!dev) {
1824                 if (netif_msg_drv(&debug))
1825                         dev_err(&pdev->dev, "unable to alloc new ethernet\n");
1826                 rc = -ENOMEM;
1827                 goto out;
1828         }
1829
1830         SET_NETDEV_DEV(dev, &pdev->dev);
1831         tp = netdev_priv(dev);
1832         tp->dev = dev;
1833         tp->pci_dev = pdev;
1834         tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
1835
1836         mii = &tp->mii;
1837         mii->dev = dev;
1838         mii->mdio_read = rtl_mdio_read;
1839         mii->mdio_write = rtl_mdio_write;
1840         mii->phy_id_mask = 0x1f;
1841         mii->reg_num_mask = 0x1f;
1842         mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
1843
1844         /* enable device (incl. PCI PM wakeup and hotplug setup) */
1845         rc = pci_enable_device(pdev);
1846         if (rc < 0) {
1847                 if (netif_msg_probe(tp))
1848                         dev_err(&pdev->dev, "enable failure\n");
1849                 goto err_out_free_dev_1;
1850         }
1851
1852         rc = pci_set_mwi(pdev);
1853         if (rc < 0)
1854                 goto err_out_disable_2;
1855
1856         /* make sure PCI base addr 1 is MMIO */
1857         if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
1858                 if (netif_msg_probe(tp)) {
1859                         dev_err(&pdev->dev,
1860                                 "region #%d not an MMIO resource, aborting\n",
1861                                 region);
1862                 }
1863                 rc = -ENODEV;
1864                 goto err_out_mwi_3;
1865         }
1866
1867         /* check for weird/broken PCI region reporting */
1868         if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
1869                 if (netif_msg_probe(tp)) {
1870                         dev_err(&pdev->dev,
1871                                 "Invalid PCI region size(s), aborting\n");
1872                 }
1873                 rc = -ENODEV;
1874                 goto err_out_mwi_3;
1875         }
1876
1877         rc = pci_request_regions(pdev, MODULENAME);
1878         if (rc < 0) {
1879                 if (netif_msg_probe(tp))
1880                         dev_err(&pdev->dev, "could not request regions.\n");
1881                 goto err_out_mwi_3;
1882         }
1883
1884         tp->cp_cmd = PCIMulRW | RxChkSum;
1885
1886         if ((sizeof(dma_addr_t) > 4) &&
1887             !pci_set_dma_mask(pdev, DMA_64BIT_MASK) && use_dac) {
1888                 tp->cp_cmd |= PCIDAC;
1889                 dev->features |= NETIF_F_HIGHDMA;
1890         } else {
1891                 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1892                 if (rc < 0) {
1893                         if (netif_msg_probe(tp)) {
1894                                 dev_err(&pdev->dev,
1895                                         "DMA configuration failed.\n");
1896                         }
1897                         goto err_out_free_res_4;
1898                 }
1899         }
1900
1901         pci_set_master(pdev);
1902
1903         /* ioremap MMIO region */
1904         ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
1905         if (!ioaddr) {
1906                 if (netif_msg_probe(tp))
1907                         dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
1908                 rc = -EIO;
1909                 goto err_out_free_res_4;
1910         }
1911
1912         tp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
1913         if (!tp->pcie_cap && netif_msg_probe(tp))
1914                 dev_info(&pdev->dev, "no PCI Express capability\n");
1915
1916         /* Unneeded ? Don't mess with Mrs. Murphy. */
1917         rtl8169_irq_mask_and_ack(ioaddr);
1918
1919         /* Soft reset the chip. */
1920         RTL_W8(ChipCmd, CmdReset);
1921
1922         /* Check that the chip has finished the reset. */
1923         for (i = 0; i < 100; i++) {
1924                 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1925                         break;
1926                 msleep_interruptible(1);
1927         }
1928
1929         /* Identify chip attached to board */
1930         rtl8169_get_mac_version(tp, ioaddr);
1931
1932         rtl8169_print_mac_version(tp);
1933
1934         for (i = 0; i < ARRAY_SIZE(rtl_chip_info); i++) {
1935                 if (tp->mac_version == rtl_chip_info[i].mac_version)
1936                         break;
1937         }
1938         if (i == ARRAY_SIZE(rtl_chip_info)) {
1939                 /* Unknown chip: assume array element #0, original RTL-8169 */
1940                 if (netif_msg_probe(tp)) {
1941                         dev_printk(KERN_DEBUG, &pdev->dev,
1942                                 "unknown chip version, assuming %s\n",
1943                                 rtl_chip_info[0].name);
1944                 }
1945                 i = 0;
1946         }
1947         tp->chipset = i;
1948
1949         RTL_W8(Cfg9346, Cfg9346_Unlock);
1950         RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
1951         RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
1952         if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
1953                 tp->features |= RTL_FEATURE_WOL;
1954         if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
1955                 tp->features |= RTL_FEATURE_WOL;
1956         tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
1957         RTL_W8(Cfg9346, Cfg9346_Lock);
1958
1959         if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
1960             (RTL_R8(PHYstatus) & TBI_Enable)) {
1961                 tp->set_speed = rtl8169_set_speed_tbi;
1962                 tp->get_settings = rtl8169_gset_tbi;
1963                 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
1964                 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
1965                 tp->link_ok = rtl8169_tbi_link_ok;
1966
1967                 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
1968         } else {
1969                 tp->set_speed = rtl8169_set_speed_xmii;
1970                 tp->get_settings = rtl8169_gset_xmii;
1971                 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
1972                 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
1973                 tp->link_ok = rtl8169_xmii_link_ok;
1974
1975                 dev->do_ioctl = rtl8169_ioctl;
1976         }
1977
1978         spin_lock_init(&tp->lock);
1979
1980         rtl_init_mac_address(tp, ioaddr);
1981
1982         /* Get MAC address */
1983         for (i = 0; i < MAC_ADDR_LEN; i++)
1984                 dev->dev_addr[i] = RTL_R8(MAC0 + i);
1985         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1986
1987         dev->open = rtl8169_open;
1988         dev->hard_start_xmit = rtl8169_start_xmit;
1989         dev->get_stats = rtl8169_get_stats;
1990         SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
1991         dev->stop = rtl8169_close;
1992         dev->tx_timeout = rtl8169_tx_timeout;
1993         dev->set_multicast_list = rtl_set_rx_mode;
1994         dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
1995         dev->irq = pdev->irq;
1996         dev->base_addr = (unsigned long) ioaddr;
1997         dev->change_mtu = rtl8169_change_mtu;
1998         dev->set_mac_address = rtl_set_mac_address;
1999
2000         netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
2001
2002 #ifdef CONFIG_R8169_VLAN
2003         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
2004         dev->vlan_rx_register = rtl8169_vlan_rx_register;
2005 #endif
2006
2007 #ifdef CONFIG_NET_POLL_CONTROLLER
2008         dev->poll_controller = rtl8169_netpoll;
2009 #endif
2010
2011         tp->intr_mask = 0xffff;
2012         tp->mmio_addr = ioaddr;
2013         tp->align = cfg->align;
2014         tp->hw_start = cfg->hw_start;
2015         tp->intr_event = cfg->intr_event;
2016         tp->napi_event = cfg->napi_event;
2017
2018         init_timer(&tp->timer);
2019         tp->timer.data = (unsigned long) dev;
2020         tp->timer.function = rtl8169_phy_timer;
2021
2022         rc = register_netdev(dev);
2023         if (rc < 0)
2024                 goto err_out_msi_5;
2025
2026         pci_set_drvdata(pdev, dev);
2027
2028         if (netif_msg_probe(tp)) {
2029                 u32 xid = RTL_R32(TxConfig) & 0x7cf0f8ff;
2030
2031                 printk(KERN_INFO "%s: %s at 0x%lx, "
2032                        "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
2033                        "XID %08x IRQ %d\n",
2034                        dev->name,
2035                        rtl_chip_info[tp->chipset].name,
2036                        dev->base_addr,
2037                        dev->dev_addr[0], dev->dev_addr[1],
2038                        dev->dev_addr[2], dev->dev_addr[3],
2039                        dev->dev_addr[4], dev->dev_addr[5], xid, dev->irq);
2040         }
2041
2042         rtl8169_init_phy(dev, tp);
2043         device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
2044
2045 out:
2046         return rc;
2047
2048 err_out_msi_5:
2049         rtl_disable_msi(pdev, tp);
2050         iounmap(ioaddr);
2051 err_out_free_res_4:
2052         pci_release_regions(pdev);
2053 err_out_mwi_3:
2054         pci_clear_mwi(pdev);
2055 err_out_disable_2:
2056         pci_disable_device(pdev);
2057 err_out_free_dev_1:
2058         free_netdev(dev);
2059         goto out;
2060 }
2061
2062 static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
2063 {
2064         struct net_device *dev = pci_get_drvdata(pdev);
2065         struct rtl8169_private *tp = netdev_priv(dev);
2066
2067         flush_scheduled_work();
2068
2069         unregister_netdev(dev);
2070         rtl_disable_msi(pdev, tp);
2071         rtl8169_release_board(pdev, dev, tp->mmio_addr);
2072         pci_set_drvdata(pdev, NULL);
2073 }
2074
2075 static void rtl8169_set_rxbufsize(struct rtl8169_private *tp,
2076                                   struct net_device *dev)
2077 {
2078         unsigned int mtu = dev->mtu;
2079
2080         tp->rx_buf_sz = (mtu > RX_BUF_SIZE) ? mtu + ETH_HLEN + 8 : RX_BUF_SIZE;
2081 }
2082
2083 static int rtl8169_open(struct net_device *dev)
2084 {
2085         struct rtl8169_private *tp = netdev_priv(dev);
2086         struct pci_dev *pdev = tp->pci_dev;
2087         int retval = -ENOMEM;
2088
2089
2090         rtl8169_set_rxbufsize(tp, dev);
2091
2092         /*
2093          * Rx and Tx desscriptors needs 256 bytes alignment.
2094          * pci_alloc_consistent provides more.
2095          */
2096         tp->TxDescArray = pci_alloc_consistent(pdev, R8169_TX_RING_BYTES,
2097                                                &tp->TxPhyAddr);
2098         if (!tp->TxDescArray)
2099                 goto out;
2100
2101         tp->RxDescArray = pci_alloc_consistent(pdev, R8169_RX_RING_BYTES,
2102                                                &tp->RxPhyAddr);
2103         if (!tp->RxDescArray)
2104                 goto err_free_tx_0;
2105
2106         retval = rtl8169_init_ring(dev);
2107         if (retval < 0)
2108                 goto err_free_rx_1;
2109
2110         INIT_DELAYED_WORK(&tp->task, NULL);
2111
2112         smp_mb();
2113
2114         retval = request_irq(dev->irq, rtl8169_interrupt,
2115                              (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
2116                              dev->name, dev);
2117         if (retval < 0)
2118                 goto err_release_ring_2;
2119
2120         napi_enable(&tp->napi);
2121
2122         rtl_hw_start(dev);
2123
2124         rtl8169_request_timer(dev);
2125
2126         rtl8169_check_link_status(dev, tp, tp->mmio_addr);
2127 out:
2128         return retval;
2129
2130 err_release_ring_2:
2131         rtl8169_rx_clear(tp);
2132 err_free_rx_1:
2133         pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
2134                             tp->RxPhyAddr);
2135 err_free_tx_0:
2136         pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
2137                             tp->TxPhyAddr);
2138         goto out;
2139 }
2140
2141 static void rtl8169_hw_reset(void __iomem *ioaddr)
2142 {
2143         /* Disable interrupts */
2144         rtl8169_irq_mask_and_ack(ioaddr);
2145
2146         /* Reset the chipset */
2147         RTL_W8(ChipCmd, CmdReset);
2148
2149         /* PCI commit */
2150         RTL_R8(ChipCmd);
2151 }
2152
2153 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
2154 {
2155         void __iomem *ioaddr = tp->mmio_addr;
2156         u32 cfg = rtl8169_rx_config;
2157
2158         cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
2159         RTL_W32(RxConfig, cfg);
2160
2161         /* Set DMA burst size and Interframe Gap Time */
2162         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
2163                 (InterFrameGap << TxInterFrameGapShift));
2164 }
2165
2166 static void rtl_hw_start(struct net_device *dev)
2167 {
2168         struct rtl8169_private *tp = netdev_priv(dev);
2169         void __iomem *ioaddr = tp->mmio_addr;
2170         unsigned int i;
2171
2172         /* Soft reset the chip. */
2173         RTL_W8(ChipCmd, CmdReset);
2174
2175         /* Check that the chip has finished the reset. */
2176         for (i = 0; i < 100; i++) {
2177                 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
2178                         break;
2179                 msleep_interruptible(1);
2180         }
2181
2182         tp->hw_start(dev);
2183
2184         netif_start_queue(dev);
2185 }
2186
2187
2188 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
2189                                          void __iomem *ioaddr)
2190 {
2191         /*
2192          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
2193          * register to be written before TxDescAddrLow to work.
2194          * Switching from MMIO to I/O access fixes the issue as well.
2195          */
2196         RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
2197         RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_32BIT_MASK);
2198         RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
2199         RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_32BIT_MASK);
2200 }
2201
2202 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
2203 {
2204         u16 cmd;
2205
2206         cmd = RTL_R16(CPlusCmd);
2207         RTL_W16(CPlusCmd, cmd);
2208         return cmd;
2209 }
2210
2211 static void rtl_set_rx_max_size(void __iomem *ioaddr)
2212 {
2213         /* Low hurts. Let's disable the filtering. */
2214         RTL_W16(RxMaxSize, 16383);
2215 }
2216
2217 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
2218 {
2219         struct {
2220                 u32 mac_version;
2221                 u32 clk;
2222                 u32 val;
2223         } cfg2_info [] = {
2224                 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
2225                 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
2226                 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
2227                 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
2228         }, *p = cfg2_info;
2229         unsigned int i;
2230         u32 clk;
2231
2232         clk = RTL_R8(Config2) & PCI_Clock_66MHz;
2233         for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
2234                 if ((p->mac_version == mac_version) && (p->clk == clk)) {
2235                         RTL_W32(0x7c, p->val);
2236                         break;
2237                 }
2238         }
2239 }
2240
2241 static void rtl_hw_start_8169(struct net_device *dev)
2242 {
2243         struct rtl8169_private *tp = netdev_priv(dev);
2244         void __iomem *ioaddr = tp->mmio_addr;
2245         struct pci_dev *pdev = tp->pci_dev;
2246
2247         if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
2248                 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
2249                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
2250         }
2251
2252         RTL_W8(Cfg9346, Cfg9346_Unlock);
2253         if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
2254             (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2255             (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
2256             (tp->mac_version == RTL_GIGA_MAC_VER_04))
2257                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2258
2259         RTL_W8(EarlyTxThres, EarlyTxThld);
2260
2261         rtl_set_rx_max_size(ioaddr);
2262
2263         if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
2264             (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2265             (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
2266             (tp->mac_version == RTL_GIGA_MAC_VER_04))
2267                 rtl_set_rx_tx_config_registers(tp);
2268
2269         tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
2270
2271         if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2272             (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
2273                 dprintk("Set MAC Reg C+CR Offset 0xE0. "
2274                         "Bit-3 and bit-14 MUST be 1\n");
2275                 tp->cp_cmd |= (1 << 14);
2276         }
2277
2278         RTL_W16(CPlusCmd, tp->cp_cmd);
2279
2280         rtl8169_set_magic_reg(ioaddr, tp->mac_version);
2281
2282         /*
2283          * Undocumented corner. Supposedly:
2284          * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
2285          */
2286         RTL_W16(IntrMitigate, 0x0000);
2287
2288         rtl_set_rx_tx_desc_registers(tp, ioaddr);
2289
2290         if ((tp->mac_version != RTL_GIGA_MAC_VER_01) &&
2291             (tp->mac_version != RTL_GIGA_MAC_VER_02) &&
2292             (tp->mac_version != RTL_GIGA_MAC_VER_03) &&
2293             (tp->mac_version != RTL_GIGA_MAC_VER_04)) {
2294                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2295                 rtl_set_rx_tx_config_registers(tp);
2296         }
2297
2298         RTL_W8(Cfg9346, Cfg9346_Lock);
2299
2300         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
2301         RTL_R8(IntrMask);
2302
2303         RTL_W32(RxMissed, 0);
2304
2305         rtl_set_rx_mode(dev);
2306
2307         /* no early-rx interrupts */
2308         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
2309
2310         /* Enable all known interrupts by setting the interrupt mask. */
2311         RTL_W16(IntrMask, tp->intr_event);
2312 }
2313
2314 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
2315 {
2316         struct net_device *dev = pci_get_drvdata(pdev);
2317         struct rtl8169_private *tp = netdev_priv(dev);
2318         int cap = tp->pcie_cap;
2319
2320         if (cap) {
2321                 u16 ctl;
2322
2323                 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
2324                 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
2325                 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
2326         }
2327 }
2328
2329 static void rtl_csi_access_enable(void __iomem *ioaddr)
2330 {
2331         u32 csi;
2332
2333         csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
2334         rtl_csi_write(ioaddr, 0x070c, csi | 0x27000000);
2335 }
2336
2337 struct ephy_info {
2338         unsigned int offset;
2339         u16 mask;
2340         u16 bits;
2341 };
2342
2343 static void rtl_ephy_init(void __iomem *ioaddr, struct ephy_info *e, int len)
2344 {
2345         u16 w;
2346
2347         while (len-- > 0) {
2348                 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
2349                 rtl_ephy_write(ioaddr, e->offset, w);
2350                 e++;
2351         }
2352 }
2353
2354 static void rtl_hw_start_8168(struct net_device *dev)
2355 {
2356         struct rtl8169_private *tp = netdev_priv(dev);
2357         void __iomem *ioaddr = tp->mmio_addr;
2358         struct pci_dev *pdev = tp->pci_dev;
2359
2360         RTL_W8(Cfg9346, Cfg9346_Unlock);
2361
2362         RTL_W8(EarlyTxThres, EarlyTxThld);
2363
2364         rtl_set_rx_max_size(ioaddr);
2365
2366         rtl_set_rx_tx_config_registers(tp);
2367
2368         tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
2369
2370         RTL_W16(CPlusCmd, tp->cp_cmd);
2371
2372         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2373
2374         RTL_W16(IntrMitigate, 0x5151);
2375
2376         /* Work around for RxFIFO overflow. */
2377         if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
2378                 tp->intr_event |= RxFIFOOver | PCSTimeout;
2379                 tp->intr_event &= ~RxOverflow;
2380         }
2381
2382         rtl_set_rx_tx_desc_registers(tp, ioaddr);
2383
2384         RTL_W8(Cfg9346, Cfg9346_Lock);
2385
2386         RTL_R8(IntrMask);
2387
2388         rtl_set_rx_mode(dev);
2389
2390         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2391
2392         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
2393
2394         RTL_W16(IntrMask, tp->intr_event);
2395 }
2396
2397 #define R810X_CPCMD_QUIRK_MASK (\
2398         EnableBist | \
2399         Mac_dbgo_oe | \
2400         Force_half_dup | \
2401         Force_half_dup | \
2402         Force_txflow_en | \
2403         Cxpl_dbg_sel | \
2404         ASF | \
2405         PktCntrDisable | \
2406         PCIDAC | \
2407         PCIMulRW)
2408
2409 static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
2410 {
2411         static struct ephy_info e_info_8102e_1[] = {
2412                 { 0x01, 0, 0x6e65 },
2413                 { 0x02, 0, 0x091f },
2414                 { 0x03, 0, 0xc2f9 },
2415                 { 0x06, 0, 0xafb5 },
2416                 { 0x07, 0, 0x0e00 },
2417                 { 0x19, 0, 0xec80 },
2418                 { 0x01, 0, 0x2e65 },
2419                 { 0x01, 0, 0x6e65 }
2420         };
2421         u8 cfg1;
2422
2423         rtl_csi_access_enable(ioaddr);
2424
2425         RTL_W8(DBG_REG, FIX_NAK_1);
2426
2427         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2428
2429         RTL_W8(Config1,
2430                LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
2431         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2432
2433         cfg1 = RTL_R8(Config1);
2434         if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
2435                 RTL_W8(Config1, cfg1 & ~LEDS0);
2436
2437         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
2438
2439         rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
2440 }
2441
2442 static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
2443 {
2444         rtl_csi_access_enable(ioaddr);
2445
2446         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2447
2448         RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
2449         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2450
2451         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
2452 }
2453
2454 static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
2455 {
2456         rtl_hw_start_8102e_2(ioaddr, pdev);
2457
2458         rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
2459 }
2460
2461 static void rtl_hw_start_8101(struct net_device *dev)
2462 {
2463         struct rtl8169_private *tp = netdev_priv(dev);
2464         void __iomem *ioaddr = tp->mmio_addr;
2465         struct pci_dev *pdev = tp->pci_dev;
2466
2467         if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
2468             (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
2469                 int cap = tp->pcie_cap;
2470
2471                 if (cap) {
2472                         pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
2473                                               PCI_EXP_DEVCTL_NOSNOOP_EN);
2474                 }
2475         }
2476
2477         switch (tp->mac_version) {
2478         case RTL_GIGA_MAC_VER_07:
2479                 rtl_hw_start_8102e_1(ioaddr, pdev);
2480                 break;
2481
2482         case RTL_GIGA_MAC_VER_08:
2483                 rtl_hw_start_8102e_3(ioaddr, pdev);
2484                 break;
2485
2486         case RTL_GIGA_MAC_VER_09:
2487                 rtl_hw_start_8102e_2(ioaddr, pdev);
2488                 break;
2489         }
2490
2491         RTL_W8(Cfg9346, Cfg9346_Unlock);
2492
2493         RTL_W8(EarlyTxThres, EarlyTxThld);
2494
2495         rtl_set_rx_max_size(ioaddr);
2496
2497         tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
2498
2499         RTL_W16(CPlusCmd, tp->cp_cmd);
2500
2501         RTL_W16(IntrMitigate, 0x0000);
2502
2503         rtl_set_rx_tx_desc_registers(tp, ioaddr);
2504
2505         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2506         rtl_set_rx_tx_config_registers(tp);
2507
2508         RTL_W8(Cfg9346, Cfg9346_Lock);
2509
2510         RTL_R8(IntrMask);
2511
2512         rtl_set_rx_mode(dev);
2513
2514         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2515
2516         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
2517
2518         RTL_W16(IntrMask, tp->intr_event);
2519 }
2520
2521 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
2522 {
2523         struct rtl8169_private *tp = netdev_priv(dev);
2524         int ret = 0;
2525
2526         if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
2527                 return -EINVAL;
2528
2529         dev->mtu = new_mtu;
2530
2531         if (!netif_running(dev))
2532                 goto out;
2533
2534         rtl8169_down(dev);
2535
2536         rtl8169_set_rxbufsize(tp, dev);
2537
2538         ret = rtl8169_init_ring(dev);
2539         if (ret < 0)
2540                 goto out;
2541
2542         napi_enable(&tp->napi);
2543
2544         rtl_hw_start(dev);
2545
2546         rtl8169_request_timer(dev);
2547
2548 out:
2549         return ret;
2550 }
2551
2552 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
2553 {
2554         desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
2555         desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
2556 }
2557
2558 static void rtl8169_free_rx_skb(struct rtl8169_private *tp,
2559                                 struct sk_buff **sk_buff, struct RxDesc *desc)
2560 {
2561         struct pci_dev *pdev = tp->pci_dev;
2562
2563         pci_unmap_single(pdev, le64_to_cpu(desc->addr), tp->rx_buf_sz,
2564                          PCI_DMA_FROMDEVICE);
2565         dev_kfree_skb(*sk_buff);
2566         *sk_buff = NULL;
2567         rtl8169_make_unusable_by_asic(desc);
2568 }
2569
2570 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
2571 {
2572         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
2573
2574         desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
2575 }
2576
2577 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
2578                                        u32 rx_buf_sz)
2579 {
2580         desc->addr = cpu_to_le64(mapping);
2581         wmb();
2582         rtl8169_mark_to_asic(desc, rx_buf_sz);
2583 }
2584
2585 static struct sk_buff *rtl8169_alloc_rx_skb(struct pci_dev *pdev,
2586                                             struct net_device *dev,
2587                                             struct RxDesc *desc, int rx_buf_sz,
2588                                             unsigned int align)
2589 {
2590         struct sk_buff *skb;
2591         dma_addr_t mapping;
2592         unsigned int pad;
2593
2594         pad = align ? align : NET_IP_ALIGN;
2595
2596         skb = netdev_alloc_skb(dev, rx_buf_sz + pad);
2597         if (!skb)
2598                 goto err_out;
2599
2600         skb_reserve(skb, align ? ((pad - 1) & (unsigned long)skb->data) : pad);
2601
2602         mapping = pci_map_single(pdev, skb->data, rx_buf_sz,
2603                                  PCI_DMA_FROMDEVICE);
2604
2605         rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
2606 out:
2607         return skb;
2608
2609 err_out:
2610         rtl8169_make_unusable_by_asic(desc);
2611         goto out;
2612 }
2613
2614 static void rtl8169_rx_clear(struct rtl8169_private *tp)
2615 {
2616         unsigned int i;
2617
2618         for (i = 0; i < NUM_RX_DESC; i++) {
2619                 if (tp->Rx_skbuff[i]) {
2620                         rtl8169_free_rx_skb(tp, tp->Rx_skbuff + i,
2621                                             tp->RxDescArray + i);
2622                 }
2623         }
2624 }
2625
2626 static u32 rtl8169_rx_fill(struct rtl8169_private *tp, struct net_device *dev,
2627                            u32 start, u32 end)
2628 {
2629         u32 cur;
2630
2631         for (cur = start; end - cur != 0; cur++) {
2632                 struct sk_buff *skb;
2633                 unsigned int i = cur % NUM_RX_DESC;
2634
2635                 WARN_ON((s32)(end - cur) < 0);
2636
2637                 if (tp->Rx_skbuff[i])
2638                         continue;
2639
2640                 skb = rtl8169_alloc_rx_skb(tp->pci_dev, dev,
2641                                            tp->RxDescArray + i,
2642                                            tp->rx_buf_sz, tp->align);
2643                 if (!skb)
2644                         break;
2645
2646                 tp->Rx_skbuff[i] = skb;
2647         }
2648         return cur - start;
2649 }
2650
2651 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
2652 {
2653         desc->opts1 |= cpu_to_le32(RingEnd);
2654 }
2655
2656 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
2657 {
2658         tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
2659 }
2660
2661 static int rtl8169_init_ring(struct net_device *dev)
2662 {
2663         struct rtl8169_private *tp = netdev_priv(dev);
2664
2665         rtl8169_init_ring_indexes(tp);
2666
2667         memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
2668         memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));
2669
2670         if (rtl8169_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC)
2671                 goto err_out;
2672
2673         rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
2674
2675         return 0;
2676
2677 err_out:
2678         rtl8169_rx_clear(tp);
2679         return -ENOMEM;
2680 }
2681
2682 static void rtl8169_unmap_tx_skb(struct pci_dev *pdev, struct ring_info *tx_skb,
2683                                  struct TxDesc *desc)
2684 {
2685         unsigned int len = tx_skb->len;
2686
2687         pci_unmap_single(pdev, le64_to_cpu(desc->addr), len, PCI_DMA_TODEVICE);
2688         desc->opts1 = 0x00;
2689         desc->opts2 = 0x00;
2690         desc->addr = 0x00;
2691         tx_skb->len = 0;
2692 }
2693
2694 static void rtl8169_tx_clear(struct rtl8169_private *tp)
2695 {
2696         unsigned int i;
2697
2698         for (i = tp->dirty_tx; i < tp->dirty_tx + NUM_TX_DESC; i++) {
2699                 unsigned int entry = i % NUM_TX_DESC;
2700                 struct ring_info *tx_skb = tp->tx_skb + entry;
2701                 unsigned int len = tx_skb->len;
2702
2703                 if (len) {
2704                         struct sk_buff *skb = tx_skb->skb;
2705
2706                         rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb,
2707                                              tp->TxDescArray + entry);
2708                         if (skb) {
2709                                 dev_kfree_skb(skb);
2710                                 tx_skb->skb = NULL;
2711                         }
2712                         tp->dev->stats.tx_dropped++;
2713                 }
2714         }
2715         tp->cur_tx = tp->dirty_tx = 0;
2716 }
2717
2718 static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
2719 {
2720         struct rtl8169_private *tp = netdev_priv(dev);
2721
2722         PREPARE_DELAYED_WORK(&tp->task, task);
2723         schedule_delayed_work(&tp->task, 4);
2724 }
2725
2726 static void rtl8169_wait_for_quiescence(struct net_device *dev)
2727 {
2728         struct rtl8169_private *tp = netdev_priv(dev);
2729         void __iomem *ioaddr = tp->mmio_addr;
2730
2731         synchronize_irq(dev->irq);
2732
2733         /* Wait for any pending NAPI task to complete */
2734         napi_disable(&tp->napi);
2735
2736         rtl8169_irq_mask_and_ack(ioaddr);
2737
2738         tp->intr_mask = 0xffff;
2739         RTL_W16(IntrMask, tp->intr_event);
2740         napi_enable(&tp->napi);
2741 }
2742
2743 static void rtl8169_reinit_task(struct work_struct *work)
2744 {
2745         struct rtl8169_private *tp =
2746                 container_of(work, struct rtl8169_private, task.work);
2747         struct net_device *dev = tp->dev;
2748         int ret;
2749
2750         rtnl_lock();
2751
2752         if (!netif_running(dev))
2753                 goto out_unlock;
2754
2755         rtl8169_wait_for_quiescence(dev);
2756         rtl8169_close(dev);
2757
2758         ret = rtl8169_open(dev);
2759         if (unlikely(ret < 0)) {
2760                 if (net_ratelimit() && netif_msg_drv(tp)) {
2761                         printk(KERN_ERR PFX "%s: reinit failure (status = %d)."
2762                                " Rescheduling.\n", dev->name, ret);
2763                 }
2764                 rtl8169_schedule_work(dev, rtl8169_reinit_task);
2765         }
2766
2767 out_unlock:
2768         rtnl_unlock();
2769 }
2770
2771 static void rtl8169_reset_task(struct work_struct *work)
2772 {
2773         struct rtl8169_private *tp =
2774                 container_of(work, struct rtl8169_private, task.work);
2775         struct net_device *dev = tp->dev;
2776
2777         rtnl_lock();
2778
2779         if (!netif_running(dev))
2780                 goto out_unlock;
2781
2782         rtl8169_wait_for_quiescence(dev);
2783
2784         rtl8169_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0);
2785         rtl8169_tx_clear(tp);
2786
2787         if (tp->dirty_rx == tp->cur_rx) {
2788                 rtl8169_init_ring_indexes(tp);
2789                 rtl_hw_start(dev);
2790                 netif_wake_queue(dev);
2791                 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
2792         } else {
2793                 if (net_ratelimit() && netif_msg_intr(tp)) {
2794                         printk(KERN_EMERG PFX "%s: Rx buffers shortage\n",
2795                                dev->name);
2796                 }
2797                 rtl8169_schedule_work(dev, rtl8169_reset_task);
2798         }
2799
2800 out_unlock:
2801         rtnl_unlock();
2802 }
2803
2804 static void rtl8169_tx_timeout(struct net_device *dev)
2805 {
2806         struct rtl8169_private *tp = netdev_priv(dev);
2807
2808         rtl8169_hw_reset(tp->mmio_addr);
2809
2810         /* Let's wait a bit while any (async) irq lands on */
2811         rtl8169_schedule_work(dev, rtl8169_reset_task);
2812 }
2813
2814 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
2815                               u32 opts1)
2816 {
2817         struct skb_shared_info *info = skb_shinfo(skb);
2818         unsigned int cur_frag, entry;
2819         struct TxDesc * uninitialized_var(txd);
2820
2821         entry = tp->cur_tx;
2822         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
2823                 skb_frag_t *frag = info->frags + cur_frag;
2824                 dma_addr_t mapping;
2825                 u32 status, len;
2826                 void *addr;
2827
2828                 entry = (entry + 1) % NUM_TX_DESC;
2829
2830                 txd = tp->TxDescArray + entry;
2831                 len = frag->size;
2832                 addr = ((void *) page_address(frag->page)) + frag->page_offset;
2833                 mapping = pci_map_single(tp->pci_dev, addr, len, PCI_DMA_TODEVICE);
2834
2835                 /* anti gcc 2.95.3 bugware (sic) */
2836                 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
2837
2838                 txd->opts1 = cpu_to_le32(status);
2839                 txd->addr = cpu_to_le64(mapping);
2840
2841                 tp->tx_skb[entry].len = len;
2842         }
2843
2844         if (cur_frag) {
2845                 tp->tx_skb[entry].skb = skb;
2846                 txd->opts1 |= cpu_to_le32(LastFrag);
2847         }
2848
2849         return cur_frag;
2850 }
2851
2852 static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
2853 {
2854         if (dev->features & NETIF_F_TSO) {
2855                 u32 mss = skb_shinfo(skb)->gso_size;
2856
2857                 if (mss)
2858                         return LargeSend | ((mss & MSSMask) << MSSShift);
2859         }
2860         if (skb->ip_summed == CHECKSUM_PARTIAL) {
2861                 const struct iphdr *ip = ip_hdr(skb);
2862
2863                 if (ip->protocol == IPPROTO_TCP)
2864                         return IPCS | TCPCS;
2865                 else if (ip->protocol == IPPROTO_UDP)
2866                         return IPCS | UDPCS;
2867                 WARN_ON(1);     /* we need a WARN() */
2868         }
2869         return 0;
2870 }
2871
2872 static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev)
2873 {
2874         struct rtl8169_private *tp = netdev_priv(dev);
2875         unsigned int frags, entry = tp->cur_tx % NUM_TX_DESC;
2876         struct TxDesc *txd = tp->TxDescArray + entry;
2877         void __iomem *ioaddr = tp->mmio_addr;
2878         dma_addr_t mapping;
2879         u32 status, len;
2880         u32 opts1;
2881         int ret = NETDEV_TX_OK;
2882
2883         if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
2884                 if (netif_msg_drv(tp)) {
2885                         printk(KERN_ERR
2886                                "%s: BUG! Tx Ring full when queue awake!\n",
2887                                dev->name);
2888                 }
2889                 goto err_stop;
2890         }
2891
2892         if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
2893                 goto err_stop;
2894
2895         opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
2896
2897         frags = rtl8169_xmit_frags(tp, skb, opts1);
2898         if (frags) {
2899                 len = skb_headlen(skb);
2900                 opts1 |= FirstFrag;
2901         } else {
2902                 len = skb->len;
2903
2904                 if (unlikely(len < ETH_ZLEN)) {
2905                         if (skb_padto(skb, ETH_ZLEN))
2906                                 goto err_update_stats;
2907                         len = ETH_ZLEN;
2908                 }
2909
2910                 opts1 |= FirstFrag | LastFrag;
2911                 tp->tx_skb[entry].skb = skb;
2912         }
2913
2914         mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
2915
2916         tp->tx_skb[entry].len = len;
2917         txd->addr = cpu_to_le64(mapping);
2918         txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
2919
2920         wmb();
2921
2922         /* anti gcc 2.95.3 bugware (sic) */
2923         status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
2924         txd->opts1 = cpu_to_le32(status);
2925
2926         dev->trans_start = jiffies;
2927
2928         tp->cur_tx += frags + 1;
2929
2930         smp_wmb();
2931
2932         RTL_W8(TxPoll, NPQ);    /* set polling bit */
2933
2934         if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
2935                 netif_stop_queue(dev);
2936                 smp_rmb();
2937                 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
2938                         netif_wake_queue(dev);
2939         }
2940
2941 out:
2942         return ret;
2943
2944 err_stop:
2945         netif_stop_queue(dev);
2946         ret = NETDEV_TX_BUSY;
2947 err_update_stats:
2948         dev->stats.tx_dropped++;
2949         goto out;
2950 }
2951
2952 static void rtl8169_pcierr_interrupt(struct net_device *dev)
2953 {
2954         struct rtl8169_private *tp = netdev_priv(dev);
2955         struct pci_dev *pdev = tp->pci_dev;
2956         void __iomem *ioaddr = tp->mmio_addr;
2957         u16 pci_status, pci_cmd;
2958
2959         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2960         pci_read_config_word(pdev, PCI_STATUS, &pci_status);
2961
2962         if (netif_msg_intr(tp)) {
2963                 printk(KERN_ERR
2964                        "%s: PCI error (cmd = 0x%04x, status = 0x%04x).\n",
2965                        dev->name, pci_cmd, pci_status);
2966         }
2967
2968         /*
2969          * The recovery sequence below admits a very elaborated explanation:
2970          * - it seems to work;
2971          * - I did not see what else could be done;
2972          * - it makes iop3xx happy.
2973          *
2974          * Feel free to adjust to your needs.
2975          */
2976         if (pdev->broken_parity_status)
2977                 pci_cmd &= ~PCI_COMMAND_PARITY;
2978         else
2979                 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
2980
2981         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
2982
2983         pci_write_config_word(pdev, PCI_STATUS,
2984                 pci_status & (PCI_STATUS_DETECTED_PARITY |
2985                 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
2986                 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
2987
2988         /* The infamous DAC f*ckup only happens at boot time */
2989         if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
2990                 if (netif_msg_intr(tp))
2991                         printk(KERN_INFO "%s: disabling PCI DAC.\n", dev->name);
2992                 tp->cp_cmd &= ~PCIDAC;
2993                 RTL_W16(CPlusCmd, tp->cp_cmd);
2994                 dev->features &= ~NETIF_F_HIGHDMA;
2995         }
2996
2997         rtl8169_hw_reset(ioaddr);
2998
2999         rtl8169_schedule_work(dev, rtl8169_reinit_task);
3000 }
3001
3002 static void rtl8169_tx_interrupt(struct net_device *dev,
3003                                  struct rtl8169_private *tp,
3004                                  void __iomem *ioaddr)
3005 {
3006         unsigned int dirty_tx, tx_left;
3007
3008         dirty_tx = tp->dirty_tx;
3009         smp_rmb();
3010         tx_left = tp->cur_tx - dirty_tx;
3011
3012         while (tx_left > 0) {
3013                 unsigned int entry = dirty_tx % NUM_TX_DESC;
3014                 struct ring_info *tx_skb = tp->tx_skb + entry;
3015                 u32 len = tx_skb->len;
3016                 u32 status;
3017
3018                 rmb();
3019                 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
3020                 if (status & DescOwn)
3021                         break;
3022
3023                 dev->stats.tx_bytes += len;
3024                 dev->stats.tx_packets++;
3025
3026                 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, tp->TxDescArray + entry);
3027
3028                 if (status & LastFrag) {
3029                         dev_kfree_skb_irq(tx_skb->skb);
3030                         tx_skb->skb = NULL;
3031                 }
3032                 dirty_tx++;
3033                 tx_left--;
3034         }
3035
3036         if (tp->dirty_tx != dirty_tx) {
3037                 tp->dirty_tx = dirty_tx;
3038                 smp_wmb();
3039                 if (netif_queue_stopped(dev) &&
3040                     (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
3041                         netif_wake_queue(dev);
3042                 }
3043                 /*
3044                  * 8168 hack: TxPoll requests are lost when the Tx packets are
3045                  * too close. Let's kick an extra TxPoll request when a burst
3046                  * of start_xmit activity is detected (if it is not detected,
3047                  * it is slow enough). -- FR
3048                  */
3049                 smp_rmb();
3050                 if (tp->cur_tx != dirty_tx)
3051                         RTL_W8(TxPoll, NPQ);
3052         }
3053 }
3054
3055 static inline int rtl8169_fragmented_frame(u32 status)
3056 {
3057         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
3058 }
3059
3060 static inline void rtl8169_rx_csum(struct sk_buff *skb, struct RxDesc *desc)
3061 {
3062         u32 opts1 = le32_to_cpu(desc->opts1);
3063         u32 status = opts1 & RxProtoMask;
3064
3065         if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
3066             ((status == RxProtoUDP) && !(opts1 & UDPFail)) ||
3067             ((status == RxProtoIP) && !(opts1 & IPFail)))
3068                 skb->ip_summed = CHECKSUM_UNNECESSARY;
3069         else
3070                 skb->ip_summed = CHECKSUM_NONE;
3071 }
3072
3073 static inline bool rtl8169_try_rx_copy(struct sk_buff **sk_buff,
3074                                        struct rtl8169_private *tp, int pkt_size,
3075                                        dma_addr_t addr)
3076 {
3077         struct sk_buff *skb;
3078         bool done = false;
3079
3080         if (pkt_size >= rx_copybreak)
3081                 goto out;
3082
3083         skb = netdev_alloc_skb(tp->dev, pkt_size + NET_IP_ALIGN);
3084         if (!skb)
3085                 goto out;
3086
3087         pci_dma_sync_single_for_cpu(tp->pci_dev, addr, pkt_size,
3088                                     PCI_DMA_FROMDEVICE);
3089         skb_reserve(skb, NET_IP_ALIGN);
3090         skb_copy_from_linear_data(*sk_buff, skb->data, pkt_size);
3091         *sk_buff = skb;
3092         done = true;
3093 out:
3094         return done;
3095 }
3096
3097 static int rtl8169_rx_interrupt(struct net_device *dev,
3098                                 struct rtl8169_private *tp,
3099                                 void __iomem *ioaddr, u32 budget)
3100 {
3101         unsigned int cur_rx, rx_left;
3102         unsigned int delta, count;
3103
3104         cur_rx = tp->cur_rx;
3105         rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
3106         rx_left = min(rx_left, budget);
3107
3108         for (; rx_left > 0; rx_left--, cur_rx++) {
3109                 unsigned int entry = cur_rx % NUM_RX_DESC;
3110                 struct RxDesc *desc = tp->RxDescArray + entry;
3111                 u32 status;
3112
3113                 rmb();
3114                 status = le32_to_cpu(desc->opts1);
3115
3116                 if (status & DescOwn)
3117                         break;
3118                 if (unlikely(status & RxRES)) {
3119                         if (netif_msg_rx_err(tp)) {
3120                                 printk(KERN_INFO
3121                                        "%s: Rx ERROR. status = %08x\n",
3122                                        dev->name, status);
3123                         }
3124                         dev->stats.rx_errors++;
3125                         if (status & (RxRWT | RxRUNT))
3126                                 dev->stats.rx_length_errors++;
3127                         if (status & RxCRC)
3128                                 dev->stats.rx_crc_errors++;
3129                         if (status & RxFOVF) {
3130                                 rtl8169_schedule_work(dev, rtl8169_reset_task);
3131                                 dev->stats.rx_fifo_errors++;
3132                         }
3133                         rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
3134                 } else {
3135                         struct sk_buff *skb = tp->Rx_skbuff[entry];
3136                         dma_addr_t addr = le64_to_cpu(desc->addr);
3137                         int pkt_size = (status & 0x00001FFF) - 4;
3138                         struct pci_dev *pdev = tp->pci_dev;
3139
3140                         /*
3141                          * The driver does not support incoming fragmented
3142                          * frames. They are seen as a symptom of over-mtu
3143                          * sized frames.
3144                          */
3145                         if (unlikely(rtl8169_fragmented_frame(status))) {
3146                                 dev->stats.rx_dropped++;
3147                                 dev->stats.rx_length_errors++;
3148                                 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
3149                                 continue;
3150                         }
3151
3152                         rtl8169_rx_csum(skb, desc);
3153
3154                         if (rtl8169_try_rx_copy(&skb, tp, pkt_size, addr)) {
3155                                 pci_dma_sync_single_for_device(pdev, addr,
3156                                         pkt_size, PCI_DMA_FROMDEVICE);
3157                                 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
3158                         } else {
3159                                 pci_unmap_single(pdev, addr, tp->rx_buf_sz,
3160                                                  PCI_DMA_FROMDEVICE);
3161                                 tp->Rx_skbuff[entry] = NULL;
3162                         }
3163
3164                         skb_put(skb, pkt_size);
3165                         skb->protocol = eth_type_trans(skb, dev);
3166
3167                         if (rtl8169_rx_vlan_skb(tp, desc, skb) < 0)
3168                                 netif_receive_skb(skb);
3169
3170                         dev->last_rx = jiffies;
3171                         dev->stats.rx_bytes += pkt_size;
3172                         dev->stats.rx_packets++;
3173                 }
3174
3175                 /* Work around for AMD plateform. */
3176                 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
3177                     (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
3178                         desc->opts2 = 0;
3179                         cur_rx++;
3180                 }
3181         }
3182
3183         count = cur_rx - tp->cur_rx;
3184         tp->cur_rx = cur_rx;
3185
3186         delta = rtl8169_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx);
3187         if (!delta && count && netif_msg_intr(tp))
3188                 printk(KERN_INFO "%s: no Rx buffer allocated\n", dev->name);
3189         tp->dirty_rx += delta;
3190
3191         /*
3192          * FIXME: until there is periodic timer to try and refill the ring,
3193          * a temporary shortage may definitely kill the Rx process.
3194          * - disable the asic to try and avoid an overflow and kick it again
3195          *   after refill ?
3196          * - how do others driver handle this condition (Uh oh...).
3197          */
3198         if ((tp->dirty_rx + NUM_RX_DESC == tp->cur_rx) && netif_msg_intr(tp))
3199                 printk(KERN_EMERG "%s: Rx buffers exhausted\n", dev->name);
3200
3201         return count;
3202 }
3203
3204 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
3205 {
3206         struct net_device *dev = dev_instance;
3207         struct rtl8169_private *tp = netdev_priv(dev);
3208         void __iomem *ioaddr = tp->mmio_addr;
3209         int handled = 0;
3210         int status;
3211
3212         status = RTL_R16(IntrStatus);
3213
3214         /* hotplug/major error/no more work/shared irq */
3215         if ((status == 0xffff) || !status)
3216                 goto out;
3217
3218         handled = 1;
3219
3220         if (unlikely(!netif_running(dev))) {
3221                 rtl8169_asic_down(ioaddr);
3222                 goto out;
3223         }
3224
3225         status &= tp->intr_mask;
3226         RTL_W16(IntrStatus,
3227                 (status & RxFIFOOver) ? (status | RxOverflow) : status);
3228
3229         if (!(status & tp->intr_event))
3230                 goto out;
3231
3232         /* Work around for rx fifo overflow */
3233         if (unlikely(status & RxFIFOOver) &&
3234             (tp->mac_version == RTL_GIGA_MAC_VER_11)) {
3235                 netif_stop_queue(dev);
3236                 rtl8169_tx_timeout(dev);
3237                 goto out;
3238         }
3239
3240         if (unlikely(status & SYSErr)) {
3241                 rtl8169_pcierr_interrupt(dev);
3242                 goto out;
3243         }
3244
3245         if (status & LinkChg)
3246                 rtl8169_check_link_status(dev, tp, ioaddr);
3247
3248         if (status & tp->napi_event) {
3249                 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
3250                 tp->intr_mask = ~tp->napi_event;
3251
3252                 if (likely(netif_rx_schedule_prep(dev, &tp->napi)))
3253                         __netif_rx_schedule(dev, &tp->napi);
3254                 else if (netif_msg_intr(tp)) {
3255                         printk(KERN_INFO "%s: interrupt %04x in poll\n",
3256                                dev->name, status);
3257                 }
3258         }
3259 out:
3260         return IRQ_RETVAL(handled);
3261 }
3262
3263 static int rtl8169_poll(struct napi_struct *napi, int budget)
3264 {
3265         struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
3266         struct net_device *dev = tp->dev;
3267         void __iomem *ioaddr = tp->mmio_addr;
3268         int work_done;
3269
3270         work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
3271         rtl8169_tx_interrupt(dev, tp, ioaddr);
3272
3273         if (work_done < budget) {
3274                 netif_rx_complete(dev, napi);
3275                 tp->intr_mask = 0xffff;
3276                 /*
3277                  * 20040426: the barrier is not strictly required but the
3278                  * behavior of the irq handler could be less predictable
3279                  * without it. Btw, the lack of flush for the posted pci
3280                  * write is safe - FR
3281                  */
3282                 smp_wmb();
3283                 RTL_W16(IntrMask, tp->intr_event);
3284         }
3285
3286         return work_done;
3287 }
3288
3289 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
3290 {
3291         struct rtl8169_private *tp = netdev_priv(dev);
3292
3293         if (tp->mac_version > RTL_GIGA_MAC_VER_06)
3294                 return;
3295
3296         dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
3297         RTL_W32(RxMissed, 0);
3298 }
3299
3300 static void rtl8169_down(struct net_device *dev)
3301 {
3302         struct rtl8169_private *tp = netdev_priv(dev);
3303         void __iomem *ioaddr = tp->mmio_addr;
3304         unsigned int intrmask;
3305
3306         rtl8169_delete_timer(dev);
3307
3308         netif_stop_queue(dev);
3309
3310         napi_disable(&tp->napi);
3311
3312 core_down:
3313         spin_lock_irq(&tp->lock);
3314
3315         rtl8169_asic_down(ioaddr);
3316
3317         rtl8169_rx_missed(dev, ioaddr);
3318
3319         spin_unlock_irq(&tp->lock);
3320
3321         synchronize_irq(dev->irq);
3322
3323         /* Give a racing hard_start_xmit a few cycles to complete. */
3324         synchronize_sched();  /* FIXME: should this be synchronize_irq()? */
3325
3326         /*
3327          * And now for the 50k$ question: are IRQ disabled or not ?
3328          *
3329          * Two paths lead here:
3330          * 1) dev->close
3331          *    -> netif_running() is available to sync the current code and the
3332          *       IRQ handler. See rtl8169_interrupt for details.
3333          * 2) dev->change_mtu
3334          *    -> rtl8169_poll can not be issued again and re-enable the
3335          *       interruptions. Let's simply issue the IRQ down sequence again.
3336          *
3337          * No loop if hotpluged or major error (0xffff).
3338          */
3339         intrmask = RTL_R16(IntrMask);
3340         if (intrmask && (intrmask != 0xffff))
3341                 goto core_down;
3342
3343         rtl8169_tx_clear(tp);
3344
3345         rtl8169_rx_clear(tp);
3346 }
3347
3348 static int rtl8169_close(struct net_device *dev)
3349 {
3350         struct rtl8169_private *tp = netdev_priv(dev);
3351         struct pci_dev *pdev = tp->pci_dev;
3352
3353         rtl8169_down(dev);
3354
3355         free_irq(dev->irq, dev);
3356
3357         pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
3358                             tp->RxPhyAddr);
3359         pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
3360                             tp->TxPhyAddr);
3361         tp->TxDescArray = NULL;
3362         tp->RxDescArray = NULL;
3363
3364         return 0;
3365 }
3366
3367 static void rtl_set_rx_mode(struct net_device *dev)
3368 {
3369         struct rtl8169_private *tp = netdev_priv(dev);
3370         void __iomem *ioaddr = tp->mmio_addr;
3371         unsigned long flags;
3372         u32 mc_filter[2];       /* Multicast hash filter */
3373         int rx_mode;
3374         u32 tmp = 0;
3375
3376         if (dev->flags & IFF_PROMISC) {
3377                 /* Unconditionally log net taps. */
3378                 if (netif_msg_link(tp)) {
3379                         printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n",
3380                                dev->name);
3381                 }
3382                 rx_mode =
3383                     AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
3384                     AcceptAllPhys;
3385                 mc_filter[1] = mc_filter[0] = 0xffffffff;
3386         } else if ((dev->mc_count > multicast_filter_limit)
3387                    || (dev->flags & IFF_ALLMULTI)) {
3388                 /* Too many to filter perfectly -- accept all multicasts. */
3389                 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
3390                 mc_filter[1] = mc_filter[0] = 0xffffffff;
3391         } else {
3392                 struct dev_mc_list *mclist;
3393                 unsigned int i;
3394
3395                 rx_mode = AcceptBroadcast | AcceptMyPhys;
3396                 mc_filter[1] = mc_filter[0] = 0;
3397                 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
3398                      i++, mclist = mclist->next) {
3399                         int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
3400                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
3401                         rx_mode |= AcceptMulticast;
3402                 }
3403         }
3404
3405         spin_lock_irqsave(&tp->lock, flags);
3406
3407         tmp = rtl8169_rx_config | rx_mode |
3408               (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
3409
3410         if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
3411                 u32 data = mc_filter[0];
3412
3413                 mc_filter[0] = swab32(mc_filter[1]);
3414                 mc_filter[1] = swab32(data);
3415         }
3416
3417         RTL_W32(MAR0 + 0, mc_filter[0]);
3418         RTL_W32(MAR0 + 4, mc_filter[1]);
3419
3420         RTL_W32(RxConfig, tmp);
3421
3422         spin_unlock_irqrestore(&tp->lock, flags);
3423 }
3424
3425 /**
3426  *  rtl8169_get_stats - Get rtl8169 read/write statistics
3427  *  @dev: The Ethernet Device to get statistics for
3428  *
3429  *  Get TX/RX statistics for rtl8169
3430  */
3431 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
3432 {
3433         struct rtl8169_private *tp = netdev_priv(dev);
3434         void __iomem *ioaddr = tp->mmio_addr;
3435         unsigned long flags;
3436
3437         if (netif_running(dev)) {
3438                 spin_lock_irqsave(&tp->lock, flags);
3439                 rtl8169_rx_missed(dev, ioaddr);
3440                 spin_unlock_irqrestore(&tp->lock, flags);
3441         }
3442
3443         return &dev->stats;
3444 }
3445
3446 #ifdef CONFIG_PM
3447
3448 static int rtl8169_suspend(struct pci_dev *pdev, pm_message_t state)
3449 {
3450         struct net_device *dev = pci_get_drvdata(pdev);
3451         struct rtl8169_private *tp = netdev_priv(dev);
3452         void __iomem *ioaddr = tp->mmio_addr;
3453
3454         if (!netif_running(dev))
3455                 goto out_pci_suspend;
3456
3457         netif_device_detach(dev);
3458         netif_stop_queue(dev);
3459
3460         spin_lock_irq(&tp->lock);
3461
3462         rtl8169_asic_down(ioaddr);
3463
3464         rtl8169_rx_missed(dev, ioaddr);
3465
3466         spin_unlock_irq(&tp->lock);
3467
3468 out_pci_suspend:
3469         pci_save_state(pdev);
3470         pci_enable_wake(pdev, pci_choose_state(pdev, state),
3471                 (tp->features & RTL_FEATURE_WOL) ? 1 : 0);
3472         pci_set_power_state(pdev, pci_choose_state(pdev, state));
3473
3474         return 0;
3475 }
3476
3477 static int rtl8169_resume(struct pci_dev *pdev)
3478 {
3479         struct net_device *dev = pci_get_drvdata(pdev);
3480
3481         pci_set_power_state(pdev, PCI_D0);
3482         pci_restore_state(pdev);
3483         pci_enable_wake(pdev, PCI_D0, 0);
3484
3485         if (!netif_running(dev))
3486                 goto out;
3487
3488         netif_device_attach(dev);
3489
3490         rtl8169_schedule_work(dev, rtl8169_reset_task);
3491 out:
3492         return 0;
3493 }
3494
3495 #endif /* CONFIG_PM */
3496
3497 static struct pci_driver rtl8169_pci_driver = {
3498         .name           = MODULENAME,
3499         .id_table       = rtl8169_pci_tbl,
3500         .probe          = rtl8169_init_one,
3501         .remove         = __devexit_p(rtl8169_remove_one),
3502 #ifdef CONFIG_PM
3503         .suspend        = rtl8169_suspend,
3504         .resume         = rtl8169_resume,
3505 #endif
3506 };
3507
3508 static int __init rtl8169_init_module(void)
3509 {
3510         return pci_register_driver(&rtl8169_pci_driver);
3511 }
3512
3513 static void __exit rtl8169_cleanup_module(void)
3514 {
3515         pci_unregister_driver(&rtl8169_pci_driver);
3516 }
3517
3518 module_init(rtl8169_init_module);
3519 module_exit(rtl8169_cleanup_module);