SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/net/r8169.c

   1 /*
   2  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
   3  *
   4  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
   5  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
   6  * Copyright (c) a lot of people too. Please respect their work.
   7  *
   8  * See MAINTAINERS file for support contact information.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/moduleparam.h>
  13 #include <linux/pci.h>
  14 #include <linux/netdevice.h>
  15 #include <linux/etherdevice.h>
  16 #include <linux/delay.h>
  17 #include <linux/ethtool.h>
  18 #include <linux/mii.h>
  19 #include <linux/if_vlan.h>
  20 #include <linux/crc32.h>
  21 #include <linux/in.h>
  22 #include <linux/ip.h>
  23 #include <linux/tcp.h>
  24 #include <linux/init.h>
  25 #include <linux/dma-mapping.h>
  26
  27 #include <asm/system.h>
  28 #include <asm/io.h>
  29 #include <asm/irq.h>
  30
  31 #define RTL8169_VERSION "2.3LK-NAPI"
  32 #define MODULENAME "r8169"
  33 #define PFX MODULENAME ": "
  34
  35 #ifdef RTL8169_DEBUG
  36 #define assert(expr) \
  37         if (!(expr)) {                                  \
  38                 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
  39                 #expr,__FILE__,__func__,__LINE__);              \
  40         }
  41 #define dprintk(fmt, args...) \
  42         do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
  43 #else
  44 #define assert(expr) do {} while (0)
  45 #define dprintk(fmt, args...)   do {} while (0)
  46 #endif /* RTL8169_DEBUG */
  47
  48 #define R8169_MSG_DEFAULT \
  49         (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
  50
  51 #define TX_BUFFS_AVAIL(tp) \
  52         (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
  53
  54 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
  55 static const int max_interrupt_work = 20;
  56
  57 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  58    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
  59 static const int multicast_filter_limit = 32;
  60
  61 /* MAC address length */
  62 #define MAC_ADDR_LEN    6
  63
  64 #define MAX_READ_REQUEST_SHIFT  12
  65 #define RX_FIFO_THRESH  7       /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
  66 #define RX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
  67 #define TX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
  68 #define EarlyTxThld     0x3F    /* 0x3F means NO early transmit */
  69 #define RxPacketMaxSize 0x3FE8  /* 16K - 1 - ETH_HLEN - VLAN - CRC... */
  70 #define SafeMtu         0x1c20  /* ... actually life sucks beyond ~7k */
  71 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
  72
  73 #define R8169_REGS_SIZE         256
  74 #define R8169_NAPI_WEIGHT       64
  75 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
  76 #define NUM_RX_DESC     256     /* Number of Rx descriptor registers */
  77 #define RX_BUF_SIZE     1536    /* Rx Buffer size */
  78 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
  79 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
  80
  81 #define RTL8169_TX_TIMEOUT      (6*HZ)
  82 #define RTL8169_PHY_TIMEOUT     (10*HZ)
  83
  84 #define RTL_EEPROM_SIG          cpu_to_le32(0x8129)
  85 #define RTL_EEPROM_SIG_MASK     cpu_to_le32(0xffff)
  86 #define RTL_EEPROM_SIG_ADDR     0x0000
  87
  88 /* write/read MMIO register */
  89 #define RTL_W8(reg, val8)       writeb ((val8), ioaddr + (reg))
  90 #define RTL_W16(reg, val16)     writew ((val16), ioaddr + (reg))
  91 #define RTL_W32(reg, val32)     writel ((val32), ioaddr + (reg))
  92 #define RTL_R8(reg)             readb (ioaddr + (reg))
  93 #define RTL_R16(reg)            readw (ioaddr + (reg))
  94 #define RTL_R32(reg)            ((unsigned long) readl (ioaddr + (reg)))
  95
  96 enum mac_version {
  97         RTL_GIGA_MAC_NONE   = 0x00,
  98         RTL_GIGA_MAC_VER_01 = 0x01, // 8169
  99         RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
 100         RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
 101         RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
 102         RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
 103         RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
 104         RTL_GIGA_MAC_VER_07 = 0x07, // 8102e
 105         RTL_GIGA_MAC_VER_08 = 0x08, // 8102e
 106         RTL_GIGA_MAC_VER_09 = 0x09, // 8102e
 107         RTL_GIGA_MAC_VER_10 = 0x0a, // 8101e
 108         RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
 109         RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be
 110         RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb
 111         RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ?
 112         RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ?
 113         RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec
 114         RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf
 115         RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP
 116         RTL_GIGA_MAC_VER_19 = 0x13, // 8168C
 117         RTL_GIGA_MAC_VER_20 = 0x14, // 8168C
 118         RTL_GIGA_MAC_VER_21 = 0x15, // 8168C
 119         RTL_GIGA_MAC_VER_22 = 0x16, // 8168C
 120         RTL_GIGA_MAC_VER_23 = 0x17, // 8168CP
 121         RTL_GIGA_MAC_VER_24 = 0x18, // 8168CP
 122         RTL_GIGA_MAC_VER_25 = 0x19  // 8168D
 123 };
 124
 125 #define _R(NAME,MAC,MASK) \
 126         { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
 127
 128 static const struct {
 129         const char *name;
 130         u8 mac_version;
 131         u32 RxConfigMask;       /* Clears the bits supported by this chip */
 132 } rtl_chip_info[] = {
 133         _R("RTL8169",           RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
 134         _R("RTL8169s",          RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
 135         _R("RTL8110s",          RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
 136         _R("RTL8169sb/8110sb",  RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
 137         _R("RTL8169sc/8110sc",  RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
 138         _R("RTL8169sc/8110sc",  RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
 139         _R("RTL8102e",          RTL_GIGA_MAC_VER_07, 0xff7e1880), // PCI-E
 140         _R("RTL8102e",          RTL_GIGA_MAC_VER_08, 0xff7e1880), // PCI-E
 141         _R("RTL8102e",          RTL_GIGA_MAC_VER_09, 0xff7e1880), // PCI-E
 142         _R("RTL8101e",          RTL_GIGA_MAC_VER_10, 0xff7e1880), // PCI-E
 143         _R("RTL8168b/8111b",    RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
 144         _R("RTL8168b/8111b",    RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
 145         _R("RTL8101e",          RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
 146         _R("RTL8100e",          RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
 147         _R("RTL8100e",          RTL_GIGA_MAC_VER_15, 0xff7e1880), // PCI-E 8139
 148         _R("RTL8168b/8111b",    RTL_GIGA_MAC_VER_17, 0xff7e1880), // PCI-E
 149         _R("RTL8101e",          RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E
 150         _R("RTL8168cp/8111cp",  RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E
 151         _R("RTL8168c/8111c",    RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E
 152         _R("RTL8168c/8111c",    RTL_GIGA_MAC_VER_20, 0xff7e1880), // PCI-E
 153         _R("RTL8168c/8111c",    RTL_GIGA_MAC_VER_21, 0xff7e1880), // PCI-E
 154         _R("RTL8168c/8111c",    RTL_GIGA_MAC_VER_22, 0xff7e1880), // PCI-E
 155         _R("RTL8168cp/8111cp",  RTL_GIGA_MAC_VER_23, 0xff7e1880), // PCI-E
 156         _R("RTL8168cp/8111cp",  RTL_GIGA_MAC_VER_24, 0xff7e1880), // PCI-E
 157         _R("RTL8168d/8111d",    RTL_GIGA_MAC_VER_25, 0xff7e1880)  // PCI-E
 158 };
 159 #undef _R
 160
 161 enum cfg_version {
 162         RTL_CFG_0 = 0x00,
 163         RTL_CFG_1,
 164         RTL_CFG_2
 165 };
 166
 167 static void rtl_hw_start_8169(struct net_device *);
 168 static void rtl_hw_start_8168(struct net_device *);
 169 static void rtl_hw_start_8101(struct net_device *);
 170
 171 static struct pci_device_id rtl8169_pci_tbl[] = {
 172         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8129), 0, 0, RTL_CFG_0 },
 173         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8136), 0, 0, RTL_CFG_2 },
 174         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8167), 0, 0, RTL_CFG_0 },
 175         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8168), 0, 0, RTL_CFG_1 },
 176         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8169), 0, 0, RTL_CFG_0 },
 177         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4300), 0, 0, RTL_CFG_0 },
 178         { PCI_DEVICE(PCI_VENDOR_ID_AT,          0xc107), 0, 0, RTL_CFG_0 },
 179         { PCI_DEVICE(0x16ec,                    0x0116), 0, 0, RTL_CFG_0 },
 180         { PCI_VENDOR_ID_LINKSYS,                0x1032,
 181                 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
 182         { 0x0001,                               0x8168,
 183                 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
 184         {0,},
 185 };
 186
 187 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
 188
 189 static int rx_copybreak = 200;
 190 static int use_dac;
 191 static struct {
 192         u32 msg_enable;
 193 } debug = { -1 };
 194
 195 enum rtl_registers {
 196         MAC0            = 0,    /* Ethernet hardware address. */
 197         MAC4            = 4,
 198         MAR0            = 8,    /* Multicast filter. */
 199         CounterAddrLow          = 0x10,
 200         CounterAddrHigh         = 0x14,
 201         TxDescStartAddrLow      = 0x20,
 202         TxDescStartAddrHigh     = 0x24,
 203         TxHDescStartAddrLow     = 0x28,
 204         TxHDescStartAddrHigh    = 0x2c,
 205         FLASH           = 0x30,
 206         ERSR            = 0x36,
 207         ChipCmd         = 0x37,
 208         TxPoll          = 0x38,
 209         IntrMask        = 0x3c,
 210         IntrStatus      = 0x3e,
 211         TxConfig        = 0x40,
 212         RxConfig        = 0x44,
 213         RxMissed        = 0x4c,
 214         Cfg9346         = 0x50,
 215         Config0         = 0x51,
 216         Config1         = 0x52,
 217         Config2         = 0x53,
 218         Config3         = 0x54,
 219         Config4         = 0x55,
 220         Config5         = 0x56,
 221         MultiIntr       = 0x5c,
 222         PHYAR           = 0x60,
 223         PHYstatus       = 0x6c,
 224         RxMaxSize       = 0xda,
 225         CPlusCmd        = 0xe0,
 226         IntrMitigate    = 0xe2,
 227         RxDescAddrLow   = 0xe4,
 228         RxDescAddrHigh  = 0xe8,
 229         EarlyTxThres    = 0xec,
 230         FuncEvent       = 0xf0,
 231         FuncEventMask   = 0xf4,
 232         FuncPresetState = 0xf8,
 233         FuncForceEvent  = 0xfc,
 234 };
 235
 236 enum rtl8110_registers {
 237         TBICSR                  = 0x64,
 238         TBI_ANAR                = 0x68,
 239         TBI_LPAR                = 0x6a,
 240 };
 241
 242 enum rtl8168_8101_registers {
 243         CSIDR                   = 0x64,
 244         CSIAR                   = 0x68,
 245 #define CSIAR_FLAG                      0x80000000
 246 #define CSIAR_WRITE_CMD                 0x80000000
 247 #define CSIAR_BYTE_ENABLE               0x0f
 248 #define CSIAR_BYTE_ENABLE_SHIFT         12
 249 #define CSIAR_ADDR_MASK                 0x0fff
 250
 251         EPHYAR                  = 0x80,
 252 #define EPHYAR_FLAG                     0x80000000
 253 #define EPHYAR_WRITE_CMD                0x80000000
 254 #define EPHYAR_REG_MASK                 0x1f
 255 #define EPHYAR_REG_SHIFT                16
 256 #define EPHYAR_DATA_MASK                0xffff
 257         DBG_REG                 = 0xd1,
 258 #define FIX_NAK_1                       (1 << 4)
 259 #define FIX_NAK_2                       (1 << 3)
 260 };
 261
 262 enum rtl_register_content {
 263         /* InterruptStatusBits */
 264         SYSErr          = 0x8000,
 265         PCSTimeout      = 0x4000,
 266         SWInt           = 0x0100,
 267         TxDescUnavail   = 0x0080,
 268         RxFIFOOver      = 0x0040,
 269         LinkChg         = 0x0020,
 270         RxOverflow      = 0x0010,
 271         TxErr           = 0x0008,
 272         TxOK            = 0x0004,
 273         RxErr           = 0x0002,
 274         RxOK            = 0x0001,
 275
 276         /* RxStatusDesc */
 277         RxFOVF  = (1 << 23),
 278         RxRWT   = (1 << 22),
 279         RxRES   = (1 << 21),
 280         RxRUNT  = (1 << 20),
 281         RxCRC   = (1 << 19),
 282
 283         /* ChipCmdBits */
 284         CmdReset        = 0x10,
 285         CmdRxEnb        = 0x08,
 286         CmdTxEnb        = 0x04,
 287         RxBufEmpty      = 0x01,
 288
 289         /* TXPoll register p.5 */
 290         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
 291         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
 292         FSWInt          = 0x01,         /* Forced software interrupt */
 293
 294         /* Cfg9346Bits */
 295         Cfg9346_Lock    = 0x00,
 296         Cfg9346_Unlock  = 0xc0,
 297
 298         /* rx_mode_bits */
 299         AcceptErr       = 0x20,
 300         AcceptRunt      = 0x10,
 301         AcceptBroadcast = 0x08,
 302         AcceptMulticast = 0x04,
 303         AcceptMyPhys    = 0x02,
 304         AcceptAllPhys   = 0x01,
 305
 306         /* RxConfigBits */
 307         RxCfgFIFOShift  = 13,
 308         RxCfgDMAShift   =  8,
 309
 310         /* TxConfigBits */
 311         TxInterFrameGapShift = 24,
 312         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
 313
 314         /* Config1 register p.24 */
 315         LEDS1           = (1 << 7),
 316         LEDS0           = (1 << 6),
 317         MSIEnable       = (1 << 5),     /* Enable Message Signaled Interrupt */
 318         Speed_down      = (1 << 4),
 319         MEMMAP          = (1 << 3),
 320         IOMAP           = (1 << 2),
 321         VPD             = (1 << 1),
 322         PMEnable        = (1 << 0),     /* Power Management Enable */
 323
 324         /* Config2 register p. 25 */
 325         PCI_Clock_66MHz = 0x01,
 326         PCI_Clock_33MHz = 0x00,
 327
 328         /* Config3 register p.25 */
 329         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
 330         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
 331         Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
 332
 333         /* Config5 register p.27 */
 334         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
 335         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
 336         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
 337         LanWake         = (1 << 1),     /* LanWake enable/disable */
 338         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
 339
 340         /* TBICSR p.28 */
 341         TBIReset        = 0x80000000,
 342         TBILoopback     = 0x40000000,
 343         TBINwEnable     = 0x20000000,
 344         TBINwRestart    = 0x10000000,
 345         TBILinkOk       = 0x02000000,
 346         TBINwComplete   = 0x01000000,
 347
 348         /* CPlusCmd p.31 */
 349         EnableBist      = (1 << 15),    // 8168 8101
 350         Mac_dbgo_oe     = (1 << 14),    // 8168 8101
 351         Normal_mode     = (1 << 13),    // unused
 352         Force_half_dup  = (1 << 12),    // 8168 8101
 353         Force_rxflow_en = (1 << 11),    // 8168 8101
 354         Force_txflow_en = (1 << 10),    // 8168 8101
 355         Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
 356         ASF             = (1 << 8),     // 8168 8101
 357         PktCntrDisable  = (1 << 7),     // 8168 8101
 358         Mac_dbgo_sel    = 0x001c,       // 8168
 359         RxVlan          = (1 << 6),
 360         RxChkSum        = (1 << 5),
 361         PCIDAC          = (1 << 4),
 362         PCIMulRW        = (1 << 3),
 363         INTT_0          = 0x0000,       // 8168
 364         INTT_1          = 0x0001,       // 8168
 365         INTT_2          = 0x0002,       // 8168
 366         INTT_3          = 0x0003,       // 8168
 367
 368         /* rtl8169_PHYstatus */
 369         TBI_Enable      = 0x80,
 370         TxFlowCtrl      = 0x40,
 371         RxFlowCtrl      = 0x20,
 372         _1000bpsF       = 0x10,
 373         _100bps         = 0x08,
 374         _10bps          = 0x04,
 375         LinkStatus      = 0x02,
 376         FullDup         = 0x01,
 377
 378         /* _TBICSRBit */
 379         TBILinkOK       = 0x02000000,
 380
 381         /* DumpCounterCommand */
 382         CounterDump     = 0x8,
 383 };
 384
 385 enum desc_status_bit {
 386         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
 387         RingEnd         = (1 << 30), /* End of descriptor ring */
 388         FirstFrag       = (1 << 29), /* First segment of a packet */
 389         LastFrag        = (1 << 28), /* Final segment of a packet */
 390
 391         /* Tx private */
 392         LargeSend       = (1 << 27), /* TCP Large Send Offload (TSO) */
 393         MSSShift        = 16,        /* MSS value position */
 394         MSSMask         = 0xfff,     /* MSS value + LargeSend bit: 12 bits */
 395         IPCS            = (1 << 18), /* Calculate IP checksum */
 396         UDPCS           = (1 << 17), /* Calculate UDP/IP checksum */
 397         TCPCS           = (1 << 16), /* Calculate TCP/IP checksum */
 398         TxVlanTag       = (1 << 17), /* Add VLAN tag */
 399
 400         /* Rx private */
 401         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
 402         PID0            = (1 << 17), /* Protocol ID bit 2/2 */
 403
 404 #define RxProtoUDP      (PID1)
 405 #define RxProtoTCP      (PID0)
 406 #define RxProtoIP       (PID1 | PID0)
 407 #define RxProtoMask     RxProtoIP
 408
 409         IPFail          = (1 << 16), /* IP checksum failed */
 410         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
 411         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
 412         RxVlanTag       = (1 << 16), /* VLAN tag available */
 413 };
 414
 415 #define RsvdMask        0x3fffc000
 416
 417 struct TxDesc {
 418         __le32 opts1;
 419         __le32 opts2;
 420         __le64 addr;
 421 };
 422
 423 struct RxDesc {
 424         __le32 opts1;
 425         __le32 opts2;
 426         __le64 addr;
 427 };
 428
 429 struct ring_info {
 430         struct sk_buff  *skb;
 431         u32             len;
 432         u8              __pad[sizeof(void *) - sizeof(u32)];
 433 };
 434
 435 enum features {
 436         RTL_FEATURE_WOL         = (1 << 0),
 437         RTL_FEATURE_MSI         = (1 << 1),
 438         RTL_FEATURE_GMII        = (1 << 2),
 439 };
 440
 441 struct rtl8169_counters {
 442         __le64  tx_packets;
 443         __le64  rx_packets;
 444         __le64  tx_errors;
 445         __le32  rx_errors;
 446         __le16  rx_missed;
 447         __le16  align_errors;
 448         __le32  tx_one_collision;
 449         __le32  tx_multi_collision;
 450         __le64  rx_unicast;
 451         __le64  rx_broadcast;
 452         __le32  rx_multicast;
 453         __le16  tx_aborted;
 454         __le16  tx_underun;
 455 };
 456
 457 struct rtl8169_private {
 458         void __iomem *mmio_addr;        /* memory map physical address */
 459         struct pci_dev *pci_dev;        /* Index of PCI device */
 460         struct net_device *dev;
 461         struct napi_struct napi;
 462         spinlock_t lock;                /* spin lock flag */
 463         u32 msg_enable;
 464         int chipset;
 465         int mac_version;
 466         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
 467         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
 468         u32 dirty_rx;
 469         u32 dirty_tx;
 470         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
 471         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
 472         dma_addr_t TxPhyAddr;
 473         dma_addr_t RxPhyAddr;
 474         struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */
 475         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
 476         unsigned align;
 477         unsigned rx_buf_sz;
 478         struct timer_list timer;
 479         u16 cp_cmd;
 480         u16 intr_event;
 481         u16 napi_event;
 482         u16 intr_mask;
 483         int phy_1000_ctrl_reg;
 484 #ifdef CONFIG_R8169_VLAN
 485         struct vlan_group *vlgrp;
 486 #endif
 487         int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
 488         int (*get_settings)(struct net_device *, struct ethtool_cmd *);
 489         void (*phy_reset_enable)(void __iomem *);
 490         void (*hw_start)(struct net_device *);
 491         unsigned int (*phy_reset_pending)(void __iomem *);
 492         unsigned int (*link_ok)(void __iomem *);
 493         int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
 494         int pcie_cap;
 495         struct delayed_work task;
 496         unsigned features;
 497
 498         struct mii_if_info mii;
 499         struct rtl8169_counters counters;
 500 };
 501
 502 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
 503 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
 504 module_param(rx_copybreak, int, 0);
 505 MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
 506 module_param(use_dac, int, 0);
 507 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
 508 module_param_named(debug, debug.msg_enable, int, 0);
 509 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
 510 MODULE_LICENSE("GPL");
 511 MODULE_VERSION(RTL8169_VERSION);
 512
 513 static int rtl8169_open(struct net_device *dev);
 514 static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev);
 515 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
 516 static int rtl8169_init_ring(struct net_device *dev);
 517 static void rtl_hw_start(struct net_device *dev);
 518 static int rtl8169_close(struct net_device *dev);
 519 static void rtl_set_rx_mode(struct net_device *dev);
 520 static void rtl8169_tx_timeout(struct net_device *dev);
 521 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
 522 static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
 523                                 void __iomem *, u32 budget);
 524 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
 525 static void rtl8169_down(struct net_device *dev);
 526 static void rtl8169_rx_clear(struct rtl8169_private *tp);
 527 static int rtl8169_poll(struct napi_struct *napi, int budget);
 528
 529 static const unsigned int rtl8169_rx_config =
 530         (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
 531
 532 static void mdio_write(void __iomem *ioaddr, int reg_addr, int value)
 533 {
 534         int i;
 535
 536         RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
 537
 538         for (i = 20; i > 0; i--) {
 539                 /*
 540                  * Check if the RTL8169 has completed writing to the specified
 541                  * MII register.
 542                  */
 543                 if (!(RTL_R32(PHYAR) & 0x80000000))
 544                         break;
 545                 udelay(25);
 546         }
 547 }
 548
 549 static int mdio_read(void __iomem *ioaddr, int reg_addr)
 550 {
 551         int i, value = -1;
 552
 553         RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
 554
 555         for (i = 20; i > 0; i--) {
 556                 /*
 557                  * Check if the RTL8169 has completed retrieving data from
 558                  * the specified MII register.
 559                  */
 560                 if (RTL_R32(PHYAR) & 0x80000000) {
 561                         value = RTL_R32(PHYAR) & 0xffff;
 562                         break;
 563                 }
 564                 udelay(25);
 565         }
 566         return value;
 567 }
 568
 569 static void mdio_patch(void __iomem *ioaddr, int reg_addr, int value)
 570 {
 571         mdio_write(ioaddr, reg_addr, mdio_read(ioaddr, reg_addr) | value);
 572 }
 573
 574 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
 575                            int val)
 576 {
 577         struct rtl8169_private *tp = netdev_priv(dev);
 578         void __iomem *ioaddr = tp->mmio_addr;
 579
 580         mdio_write(ioaddr, location, val);
 581 }
 582
 583 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
 584 {
 585         struct rtl8169_private *tp = netdev_priv(dev);
 586         void __iomem *ioaddr = tp->mmio_addr;
 587
 588         return mdio_read(ioaddr, location);
 589 }
 590
 591 static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
 592 {
 593         unsigned int i;
 594
 595         RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
 596                 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
 597
 598         for (i = 0; i < 100; i++) {
 599                 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
 600                         break;
 601                 udelay(10);
 602         }
 603 }
 604
 605 static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
 606 {
 607         u16 value = 0xffff;
 608         unsigned int i;
 609
 610         RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
 611
 612         for (i = 0; i < 100; i++) {
 613                 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
 614                         value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
 615                         break;
 616                 }
 617                 udelay(10);
 618         }
 619
 620         return value;
 621 }
 622
 623 static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
 624 {
 625         unsigned int i;
 626
 627         RTL_W32(CSIDR, value);
 628         RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
 629                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
 630
 631         for (i = 0; i < 100; i++) {
 632                 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
 633                         break;
 634                 udelay(10);
 635         }
 636 }
 637
 638 static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
 639 {
 640         u32 value = ~0x00;
 641         unsigned int i;
 642
 643         RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
 644                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
 645
 646         for (i = 0; i < 100; i++) {
 647                 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
 648                         value = RTL_R32(CSIDR);
 649                         break;
 650                 }
 651                 udelay(10);
 652         }
 653
 654         return value;
 655 }
 656
 657 static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
 658 {
 659         RTL_W16(IntrMask, 0x0000);
 660
 661         RTL_W16(IntrStatus, 0xffff);
 662 }
 663
 664 static void rtl8169_asic_down(void __iomem *ioaddr)
 665 {
 666         RTL_W8(ChipCmd, 0x00);
 667         rtl8169_irq_mask_and_ack(ioaddr);
 668         RTL_R16(CPlusCmd);
 669 }
 670
 671 static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr)
 672 {
 673         return RTL_R32(TBICSR) & TBIReset;
 674 }
 675
 676 static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr)
 677 {
 678         return mdio_read(ioaddr, MII_BMCR) & BMCR_RESET;
 679 }
 680
 681 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
 682 {
 683         return RTL_R32(TBICSR) & TBILinkOk;
 684 }
 685
 686 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
 687 {
 688         return RTL_R8(PHYstatus) & LinkStatus;
 689 }
 690
 691 static void rtl8169_tbi_reset_enable(void __iomem *ioaddr)
 692 {
 693         RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
 694 }
 695
 696 static void rtl8169_xmii_reset_enable(void __iomem *ioaddr)
 697 {
 698         unsigned int val;
 699
 700         val = mdio_read(ioaddr, MII_BMCR) | BMCR_RESET;
 701         mdio_write(ioaddr, MII_BMCR, val & 0xffff);
 702 }
 703
 704 static void rtl8169_check_link_status(struct net_device *dev,
 705                                       struct rtl8169_private *tp,
 706                                       void __iomem *ioaddr)
 707 {
 708         unsigned long flags;
 709
 710         spin_lock_irqsave(&tp->lock, flags);
 711         if (tp->link_ok(ioaddr)) {
 712                 netif_carrier_on(dev);
 713                 if (netif_msg_ifup(tp))
 714                         printk(KERN_INFO PFX "%s: link up\n", dev->name);
 715         } else {
 716                 if (netif_msg_ifdown(tp))
 717                         printk(KERN_INFO PFX "%s: link down\n", dev->name);
 718                 netif_carrier_off(dev);
 719         }
 720         spin_unlock_irqrestore(&tp->lock, flags);
 721 }
 722
 723 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
 724 {
 725         struct rtl8169_private *tp = netdev_priv(dev);
 726         void __iomem *ioaddr = tp->mmio_addr;
 727         u8 options;
 728
 729         wol->wolopts = 0;
 730
 731 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
 732         wol->supported = WAKE_ANY;
 733
 734         spin_lock_irq(&tp->lock);
 735
 736         options = RTL_R8(Config1);
 737         if (!(options & PMEnable))
 738                 goto out_unlock;
 739
 740         options = RTL_R8(Config3);
 741         if (options & LinkUp)
 742                 wol->wolopts |= WAKE_PHY;
 743         if (options & MagicPacket)
 744                 wol->wolopts |= WAKE_MAGIC;
 745
 746         options = RTL_R8(Config5);
 747         if (options & UWF)
 748                 wol->wolopts |= WAKE_UCAST;
 749         if (options & BWF)
 750                 wol->wolopts |= WAKE_BCAST;
 751         if (options & MWF)
 752                 wol->wolopts |= WAKE_MCAST;
 753
 754 out_unlock:
 755         spin_unlock_irq(&tp->lock);
 756 }
 757
 758 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
 759 {
 760         struct rtl8169_private *tp = netdev_priv(dev);
 761         void __iomem *ioaddr = tp->mmio_addr;
 762         unsigned int i;
 763         static struct {
 764                 u32 opt;
 765                 u16 reg;
 766                 u8  mask;
 767         } cfg[] = {
 768                 { WAKE_ANY,   Config1, PMEnable },
 769                 { WAKE_PHY,   Config3, LinkUp },
 770                 { WAKE_MAGIC, Config3, MagicPacket },
 771                 { WAKE_UCAST, Config5, UWF },
 772                 { WAKE_BCAST, Config5, BWF },
 773                 { WAKE_MCAST, Config5, MWF },
 774                 { WAKE_ANY,   Config5, LanWake }
 775         };
 776
 777         spin_lock_irq(&tp->lock);
 778
 779         RTL_W8(Cfg9346, Cfg9346_Unlock);
 780
 781         for (i = 0; i < ARRAY_SIZE(cfg); i++) {
 782                 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
 783                 if (wol->wolopts & cfg[i].opt)
 784                         options |= cfg[i].mask;
 785                 RTL_W8(cfg[i].reg, options);
 786         }
 787
 788         RTL_W8(Cfg9346, Cfg9346_Lock);
 789
 790         if (wol->wolopts)
 791                 tp->features |= RTL_FEATURE_WOL;
 792         else
 793                 tp->features &= ~RTL_FEATURE_WOL;
 794         device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
 795
 796         spin_unlock_irq(&tp->lock);
 797
 798         return 0;
 799 }
 800
 801 static void rtl8169_get_drvinfo(struct net_device *dev,
 802                                 struct ethtool_drvinfo *info)
 803 {
 804         struct rtl8169_private *tp = netdev_priv(dev);
 805
 806         strcpy(info->driver, MODULENAME);
 807         strcpy(info->version, RTL8169_VERSION);
 808         strcpy(info->bus_info, pci_name(tp->pci_dev));
 809 }
 810
 811 static int rtl8169_get_regs_len(struct net_device *dev)
 812 {
 813         return R8169_REGS_SIZE;
 814 }
 815
 816 static int rtl8169_set_speed_tbi(struct net_device *dev,
 817                                  u8 autoneg, u16 speed, u8 duplex)
 818 {
 819         struct rtl8169_private *tp = netdev_priv(dev);
 820         void __iomem *ioaddr = tp->mmio_addr;
 821         int ret = 0;
 822         u32 reg;
 823
 824         reg = RTL_R32(TBICSR);
 825         if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
 826             (duplex == DUPLEX_FULL)) {
 827                 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
 828         } else if (autoneg == AUTONEG_ENABLE)
 829                 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
 830         else {
 831                 if (netif_msg_link(tp)) {
 832                         printk(KERN_WARNING "%s: "
 833                                "incorrect speed setting refused in TBI mode\n",
 834                                dev->name);
 835                 }
 836                 ret = -EOPNOTSUPP;
 837         }
 838
 839         return ret;
 840 }
 841
 842 static int rtl8169_set_speed_xmii(struct net_device *dev,
 843                                   u8 autoneg, u16 speed, u8 duplex)
 844 {
 845         struct rtl8169_private *tp = netdev_priv(dev);
 846         void __iomem *ioaddr = tp->mmio_addr;
 847         int giga_ctrl, bmcr;
 848
 849         if (autoneg == AUTONEG_ENABLE) {
 850                 int auto_nego;
 851
 852                 auto_nego = mdio_read(ioaddr, MII_ADVERTISE);
 853                 auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
 854                               ADVERTISE_100HALF | ADVERTISE_100FULL);
 855                 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
 856
 857                 giga_ctrl = mdio_read(ioaddr, MII_CTRL1000);
 858                 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
 859
 860                 /* The 8100e/8101e/8102e do Fast Ethernet only. */
 861                 if ((tp->mac_version != RTL_GIGA_MAC_VER_07) &&
 862                     (tp->mac_version != RTL_GIGA_MAC_VER_08) &&
 863                     (tp->mac_version != RTL_GIGA_MAC_VER_09) &&
 864                     (tp->mac_version != RTL_GIGA_MAC_VER_10) &&
 865                     (tp->mac_version != RTL_GIGA_MAC_VER_13) &&
 866                     (tp->mac_version != RTL_GIGA_MAC_VER_14) &&
 867                     (tp->mac_version != RTL_GIGA_MAC_VER_15) &&
 868                     (tp->mac_version != RTL_GIGA_MAC_VER_16)) {
 869                         giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
 870                 } else if (netif_msg_link(tp)) {
 871                         printk(KERN_INFO "%s: PHY does not support 1000Mbps.\n",
 872                                dev->name);
 873                 }
 874
 875                 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
 876
 877                 if ((tp->mac_version == RTL_GIGA_MAC_VER_11) ||
 878                     (tp->mac_version == RTL_GIGA_MAC_VER_12) ||
 879                     (tp->mac_version >= RTL_GIGA_MAC_VER_17)) {
 880                         /*
 881                          * Wake up the PHY.
 882                          * Vendor specific (0x1f) and reserved (0x0e) MII
 883                          * registers.
 884                          */
 885                         mdio_write(ioaddr, 0x1f, 0x0000);
 886                         mdio_write(ioaddr, 0x0e, 0x0000);
 887                 }
 888
 889                 mdio_write(ioaddr, MII_ADVERTISE, auto_nego);
 890                 mdio_write(ioaddr, MII_CTRL1000, giga_ctrl);
 891         } else {
 892                 giga_ctrl = 0;
 893
 894                 if (speed == SPEED_10)
 895                         bmcr = 0;
 896                 else if (speed == SPEED_100)
 897                         bmcr = BMCR_SPEED100;
 898                 else
 899                         return -EINVAL;
 900
 901                 if (duplex == DUPLEX_FULL)
 902                         bmcr |= BMCR_FULLDPLX;
 903
 904                 mdio_write(ioaddr, 0x1f, 0x0000);
 905         }
 906
 907         tp->phy_1000_ctrl_reg = giga_ctrl;
 908
 909         mdio_write(ioaddr, MII_BMCR, bmcr);
 910
 911         if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
 912             (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
 913                 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
 914                         mdio_write(ioaddr, 0x17, 0x2138);
 915                         mdio_write(ioaddr, 0x0e, 0x0260);
 916                 } else {
 917                         mdio_write(ioaddr, 0x17, 0x2108);
 918                         mdio_write(ioaddr, 0x0e, 0x0000);
 919                 }
 920         }
 921
 922         return 0;
 923 }
 924
 925 static int rtl8169_set_speed(struct net_device *dev,
 926                              u8 autoneg, u16 speed, u8 duplex)
 927 {
 928         struct rtl8169_private *tp = netdev_priv(dev);
 929         int ret;
 930
 931         ret = tp->set_speed(dev, autoneg, speed, duplex);
 932
 933         if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
 934                 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
 935
 936         return ret;
 937 }
 938
 939 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 940 {
 941         struct rtl8169_private *tp = netdev_priv(dev);
 942         unsigned long flags;
 943         int ret;
 944
 945         spin_lock_irqsave(&tp->lock, flags);
 946         ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
 947         spin_unlock_irqrestore(&tp->lock, flags);
 948
 949         return ret;
 950 }
 951
 952 static u32 rtl8169_get_rx_csum(struct net_device *dev)
 953 {
 954         struct rtl8169_private *tp = netdev_priv(dev);
 955
 956         return tp->cp_cmd & RxChkSum;
 957 }
 958
 959 static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
 960 {
 961         struct rtl8169_private *tp = netdev_priv(dev);
 962         void __iomem *ioaddr = tp->mmio_addr;
 963         unsigned long flags;
 964
 965         spin_lock_irqsave(&tp->lock, flags);
 966
 967         if (data)
 968                 tp->cp_cmd |= RxChkSum;
 969         else
 970                 tp->cp_cmd &= ~RxChkSum;
 971
 972         RTL_W16(CPlusCmd, tp->cp_cmd);
 973         RTL_R16(CPlusCmd);
 974
 975         spin_unlock_irqrestore(&tp->lock, flags);
 976
 977         return 0;
 978 }
 979
 980 #ifdef CONFIG_R8169_VLAN
 981
 982 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
 983                                       struct sk_buff *skb)
 984 {
 985         return (tp->vlgrp && vlan_tx_tag_present(skb)) ?
 986                 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
 987 }
 988
 989 static void rtl8169_vlan_rx_register(struct net_device *dev,
 990                                      struct vlan_group *grp)
 991 {
 992         struct rtl8169_private *tp = netdev_priv(dev);
 993         void __iomem *ioaddr = tp->mmio_addr;
 994         unsigned long flags;
 995
 996         spin_lock_irqsave(&tp->lock, flags);
 997         tp->vlgrp = grp;
 998         if (tp->vlgrp)
 999                 tp->cp_cmd |= RxVlan;
1000         else
1001                 tp->cp_cmd &= ~RxVlan;
1002         RTL_W16(CPlusCmd, tp->cp_cmd);
1003         RTL_R16(CPlusCmd);
1004         spin_unlock_irqrestore(&tp->lock, flags);
1005 }
1006
1007 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
1008                                struct sk_buff *skb)
1009 {
1010         u32 opts2 = le32_to_cpu(desc->opts2);
1011         struct vlan_group *vlgrp = tp->vlgrp;
1012         int ret;
1013
1014         if (vlgrp && (opts2 & RxVlanTag)) {
1015                 vlan_hwaccel_receive_skb(skb, vlgrp, swab16(opts2 & 0xffff));
1016                 ret = 0;
1017         } else
1018                 ret = -1;
1019         desc->opts2 = 0;
1020         return ret;
1021 }
1022
1023 #else /* !CONFIG_R8169_VLAN */
1024
1025 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1026                                       struct sk_buff *skb)
1027 {
1028         return 0;
1029 }
1030
1031 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
1032                                struct sk_buff *skb)
1033 {
1034         return -1;
1035 }
1036
1037 #endif
1038
1039 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1040 {
1041         struct rtl8169_private *tp = netdev_priv(dev);
1042         void __iomem *ioaddr = tp->mmio_addr;
1043         u32 status;
1044
1045         cmd->supported =
1046                 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1047         cmd->port = PORT_FIBRE;
1048         cmd->transceiver = XCVR_INTERNAL;
1049
1050         status = RTL_R32(TBICSR);
1051         cmd->advertising = (status & TBINwEnable) ?  ADVERTISED_Autoneg : 0;
1052         cmd->autoneg = !!(status & TBINwEnable);
1053
1054         cmd->speed = SPEED_1000;
1055         cmd->duplex = DUPLEX_FULL; /* Always set */
1056
1057         return 0;
1058 }
1059
1060 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1061 {
1062         struct rtl8169_private *tp = netdev_priv(dev);
1063
1064         return mii_ethtool_gset(&tp->mii, cmd);
1065 }
1066
1067 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1068 {
1069         struct rtl8169_private *tp = netdev_priv(dev);
1070         unsigned long flags;
1071         int rc;
1072
1073         spin_lock_irqsave(&tp->lock, flags);
1074
1075         rc = tp->get_settings(dev, cmd);
1076
1077         spin_unlock_irqrestore(&tp->lock, flags);
1078         return rc;
1079 }
1080
1081 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1082                              void *p)
1083 {
1084         struct rtl8169_private *tp = netdev_priv(dev);
1085         unsigned long flags;
1086
1087         if (regs->len > R8169_REGS_SIZE)
1088                 regs->len = R8169_REGS_SIZE;
1089
1090         spin_lock_irqsave(&tp->lock, flags);
1091         memcpy_fromio(p, tp->mmio_addr, regs->len);
1092         spin_unlock_irqrestore(&tp->lock, flags);
1093 }
1094
1095 static u32 rtl8169_get_msglevel(struct net_device *dev)
1096 {
1097         struct rtl8169_private *tp = netdev_priv(dev);
1098
1099         return tp->msg_enable;
1100 }
1101
1102 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1103 {
1104         struct rtl8169_private *tp = netdev_priv(dev);
1105
1106         tp->msg_enable = value;
1107 }
1108
1109 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1110         "tx_packets",
1111         "rx_packets",
1112         "tx_errors",
1113         "rx_errors",
1114         "rx_missed",
1115         "align_errors",
1116         "tx_single_collisions",
1117         "tx_multi_collisions",
1118         "unicast",
1119         "broadcast",
1120         "multicast",
1121         "tx_aborted",
1122         "tx_underrun",
1123 };
1124
1125 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1126 {
1127         switch (sset) {
1128         case ETH_SS_STATS:
1129                 return ARRAY_SIZE(rtl8169_gstrings);
1130         default:
1131                 return -EOPNOTSUPP;
1132         }
1133 }
1134
1135 static void rtl8169_update_counters(struct net_device *dev)
1136 {
1137         struct rtl8169_private *tp = netdev_priv(dev);
1138         void __iomem *ioaddr = tp->mmio_addr;
1139         struct rtl8169_counters *counters;
1140         dma_addr_t paddr;
1141         u32 cmd;
1142         int wait = 1000;
1143
1144         /*
1145          * Some chips are unable to dump tally counters when the receiver
1146          * is disabled.
1147          */
1148         if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1149                 return;
1150
1151         counters = pci_alloc_consistent(tp->pci_dev, sizeof(*counters), &paddr);
1152         if (!counters)
1153                 return;
1154
1155         RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1156         cmd = (u64)paddr & DMA_BIT_MASK(32);
1157         RTL_W32(CounterAddrLow, cmd);
1158         RTL_W32(CounterAddrLow, cmd | CounterDump);
1159
1160         while (wait--) {
1161                 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
1162                         /* copy updated counters */
1163                         memcpy(&tp->counters, counters, sizeof(*counters));
1164                         break;
1165                 }
1166                 udelay(10);
1167         }
1168
1169         RTL_W32(CounterAddrLow, 0);
1170         RTL_W32(CounterAddrHigh, 0);
1171
1172         pci_free_consistent(tp->pci_dev, sizeof(*counters), counters, paddr);
1173 }
1174
1175 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1176                                       struct ethtool_stats *stats, u64 *data)
1177 {
1178         struct rtl8169_private *tp = netdev_priv(dev);
1179
1180         ASSERT_RTNL();
1181
1182         rtl8169_update_counters(dev);
1183
1184         data[0] = le64_to_cpu(tp->counters.tx_packets);
1185         data[1] = le64_to_cpu(tp->counters.rx_packets);
1186         data[2] = le64_to_cpu(tp->counters.tx_errors);
1187         data[3] = le32_to_cpu(tp->counters.rx_errors);
1188         data[4] = le16_to_cpu(tp->counters.rx_missed);
1189         data[5] = le16_to_cpu(tp->counters.align_errors);
1190         data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1191         data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1192         data[8] = le64_to_cpu(tp->counters.rx_unicast);
1193         data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1194         data[10] = le32_to_cpu(tp->counters.rx_multicast);
1195         data[11] = le16_to_cpu(tp->counters.tx_aborted);
1196         data[12] = le16_to_cpu(tp->counters.tx_underun);
1197 }
1198
1199 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1200 {
1201         switch(stringset) {
1202         case ETH_SS_STATS:
1203                 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1204                 break;
1205         }
1206 }
1207
1208 static const struct ethtool_ops rtl8169_ethtool_ops = {
1209         .get_drvinfo            = rtl8169_get_drvinfo,
1210         .get_regs_len           = rtl8169_get_regs_len,
1211         .get_link               = ethtool_op_get_link,
1212         .get_settings           = rtl8169_get_settings,
1213         .set_settings           = rtl8169_set_settings,
1214         .get_msglevel           = rtl8169_get_msglevel,
1215         .set_msglevel           = rtl8169_set_msglevel,
1216         .get_rx_csum            = rtl8169_get_rx_csum,
1217         .set_rx_csum            = rtl8169_set_rx_csum,
1218         .set_tx_csum            = ethtool_op_set_tx_csum,
1219         .set_sg                 = ethtool_op_set_sg,
1220         .set_tso                = ethtool_op_set_tso,
1221         .get_regs               = rtl8169_get_regs,
1222         .get_wol                = rtl8169_get_wol,
1223         .set_wol                = rtl8169_set_wol,
1224         .get_strings            = rtl8169_get_strings,
1225         .get_sset_count         = rtl8169_get_sset_count,
1226         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
1227 };
1228
1229 static void rtl8169_write_gmii_reg_bit(void __iomem *ioaddr, int reg,
1230                                        int bitnum, int bitval)
1231 {
1232         int val;
1233
1234         val = mdio_read(ioaddr, reg);
1235         val = (bitval == 1) ?
1236                 val | (bitval << bitnum) :  val & ~(0x0001 << bitnum);
1237         mdio_write(ioaddr, reg, val & 0xffff);
1238 }
1239
1240 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1241                                     void __iomem *ioaddr)
1242 {
1243         /*
1244          * The driver currently handles the 8168Bf and the 8168Be identically
1245          * but they can be identified more specifically through the test below
1246          * if needed:
1247          *
1248          * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1249          *
1250          * Same thing for the 8101Eb and the 8101Ec:
1251          *
1252          * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1253          */
1254         const struct {
1255                 u32 mask;
1256                 u32 val;
1257                 int mac_version;
1258         } mac_info[] = {
1259                 /* 8168D family. */
1260                 { 0x7c800000, 0x28000000,       RTL_GIGA_MAC_VER_25 },
1261
1262                 /* 8168C family. */
1263                 { 0x7cf00000, 0x3ca00000,       RTL_GIGA_MAC_VER_24 },
1264                 { 0x7cf00000, 0x3c900000,       RTL_GIGA_MAC_VER_23 },
1265                 { 0x7cf00000, 0x3c800000,       RTL_GIGA_MAC_VER_18 },
1266                 { 0x7c800000, 0x3c800000,       RTL_GIGA_MAC_VER_24 },
1267                 { 0x7cf00000, 0x3c000000,       RTL_GIGA_MAC_VER_19 },
1268                 { 0x7cf00000, 0x3c200000,       RTL_GIGA_MAC_VER_20 },
1269                 { 0x7cf00000, 0x3c300000,       RTL_GIGA_MAC_VER_21 },
1270                 { 0x7cf00000, 0x3c400000,       RTL_GIGA_MAC_VER_22 },
1271                 { 0x7c800000, 0x3c000000,       RTL_GIGA_MAC_VER_22 },
1272
1273                 /* 8168B family. */
1274                 { 0x7cf00000, 0x38000000,       RTL_GIGA_MAC_VER_12 },
1275                 { 0x7cf00000, 0x38500000,       RTL_GIGA_MAC_VER_17 },
1276                 { 0x7c800000, 0x38000000,       RTL_GIGA_MAC_VER_17 },
1277                 { 0x7c800000, 0x30000000,       RTL_GIGA_MAC_VER_11 },
1278
1279                 /* 8101 family. */
1280                 { 0x7cf00000, 0x34a00000,       RTL_GIGA_MAC_VER_09 },
1281                 { 0x7cf00000, 0x24a00000,       RTL_GIGA_MAC_VER_09 },
1282                 { 0x7cf00000, 0x34900000,       RTL_GIGA_MAC_VER_08 },
1283                 { 0x7cf00000, 0x24900000,       RTL_GIGA_MAC_VER_08 },
1284                 { 0x7cf00000, 0x34800000,       RTL_GIGA_MAC_VER_07 },
1285                 { 0x7cf00000, 0x24800000,       RTL_GIGA_MAC_VER_07 },
1286                 { 0x7cf00000, 0x34000000,       RTL_GIGA_MAC_VER_13 },
1287                 { 0x7cf00000, 0x34300000,       RTL_GIGA_MAC_VER_10 },
1288                 { 0x7cf00000, 0x34200000,       RTL_GIGA_MAC_VER_16 },
1289                 { 0x7c800000, 0x34800000,       RTL_GIGA_MAC_VER_09 },
1290                 { 0x7c800000, 0x24800000,       RTL_GIGA_MAC_VER_09 },
1291                 { 0x7c800000, 0x34000000,       RTL_GIGA_MAC_VER_16 },
1292                 /* FIXME: where did these entries come from ? -- FR */
1293                 { 0xfc800000, 0x38800000,       RTL_GIGA_MAC_VER_15 },
1294                 { 0xfc800000, 0x30800000,       RTL_GIGA_MAC_VER_14 },
1295
1296                 /* 8110 family. */
1297                 { 0xfc800000, 0x98000000,       RTL_GIGA_MAC_VER_06 },
1298                 { 0xfc800000, 0x18000000,       RTL_GIGA_MAC_VER_05 },
1299                 { 0xfc800000, 0x10000000,       RTL_GIGA_MAC_VER_04 },
1300                 { 0xfc800000, 0x04000000,       RTL_GIGA_MAC_VER_03 },
1301                 { 0xfc800000, 0x00800000,       RTL_GIGA_MAC_VER_02 },
1302                 { 0xfc800000, 0x00000000,       RTL_GIGA_MAC_VER_01 },
1303
1304                 /* Catch-all */
1305                 { 0x00000000, 0x00000000,       RTL_GIGA_MAC_NONE   }
1306         }, *p = mac_info;
1307         u32 reg;
1308
1309         reg = RTL_R32(TxConfig);
1310         while ((reg & p->mask) != p->val)
1311                 p++;
1312         tp->mac_version = p->mac_version;
1313 }
1314
1315 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1316 {
1317         dprintk("mac_version = 0x%02x\n", tp->mac_version);
1318 }
1319
1320 struct phy_reg {
1321         u16 reg;
1322         u16 val;
1323 };
1324
1325 static void rtl_phy_write(void __iomem *ioaddr, struct phy_reg *regs, int len)
1326 {
1327         while (len-- > 0) {
1328                 mdio_write(ioaddr, regs->reg, regs->val);
1329                 regs++;
1330         }
1331 }
1332
1333 static void rtl8169s_hw_phy_config(void __iomem *ioaddr)
1334 {
1335         struct {
1336                 u16 regs[5]; /* Beware of bit-sign propagation */
1337         } phy_magic[5] = { {
1338                 { 0x0000,       //w 4 15 12 0
1339                   0x00a1,       //w 3 15 0 00a1
1340                   0x0008,       //w 2 15 0 0008
1341                   0x1020,       //w 1 15 0 1020
1342                   0x1000 } },{  //w 0 15 0 1000
1343                 { 0x7000,       //w 4 15 12 7
1344                   0xff41,       //w 3 15 0 ff41
1345                   0xde60,       //w 2 15 0 de60
1346                   0x0140,       //w 1 15 0 0140
1347                   0x0077 } },{  //w 0 15 0 0077
1348                 { 0xa000,       //w 4 15 12 a
1349                   0xdf01,       //w 3 15 0 df01
1350                   0xdf20,       //w 2 15 0 df20
1351                   0xff95,       //w 1 15 0 ff95
1352                   0xfa00 } },{  //w 0 15 0 fa00
1353                 { 0xb000,       //w 4 15 12 b
1354                   0xff41,       //w 3 15 0 ff41
1355                   0xde20,       //w 2 15 0 de20
1356                   0x0140,       //w 1 15 0 0140
1357                   0x00bb } },{  //w 0 15 0 00bb
1358                 { 0xf000,       //w 4 15 12 f
1359                   0xdf01,       //w 3 15 0 df01
1360                   0xdf20,       //w 2 15 0 df20
1361                   0xff95,       //w 1 15 0 ff95
1362                   0xbf00 }      //w 0 15 0 bf00
1363                 }
1364         }, *p = phy_magic;
1365         unsigned int i;
1366
1367         mdio_write(ioaddr, 0x1f, 0x0001);               //w 31 2 0 1
1368         mdio_write(ioaddr, 0x15, 0x1000);               //w 21 15 0 1000
1369         mdio_write(ioaddr, 0x18, 0x65c7);               //w 24 15 0 65c7
1370         rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0);   //w 4 11 11 0
1371
1372         for (i = 0; i < ARRAY_SIZE(phy_magic); i++, p++) {
1373                 int val, pos = 4;
1374
1375                 val = (mdio_read(ioaddr, pos) & 0x0fff) | (p->regs[0] & 0xffff);
1376                 mdio_write(ioaddr, pos, val);
1377                 while (--pos >= 0)
1378                         mdio_write(ioaddr, pos, p->regs[4 - pos] & 0xffff);
1379                 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 1); //w 4 11 11 1
1380                 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1381         }
1382         mdio_write(ioaddr, 0x1f, 0x0000); //w 31 2 0 0
1383 }
1384
1385 static void rtl8169sb_hw_phy_config(void __iomem *ioaddr)
1386 {
1387         struct phy_reg phy_reg_init[] = {
1388                 { 0x1f, 0x0002 },
1389                 { 0x01, 0x90d0 },
1390                 { 0x1f, 0x0000 }
1391         };
1392
1393         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1394 }
1395
1396 static void rtl8168bb_hw_phy_config(void __iomem *ioaddr)
1397 {
1398         struct phy_reg phy_reg_init[] = {
1399                 { 0x10, 0xf41b },
1400                 { 0x1f, 0x0000 }
1401         };
1402
1403         mdio_write(ioaddr, 0x1f, 0x0001);
1404         mdio_patch(ioaddr, 0x16, 1 << 0);
1405
1406         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1407 }
1408
1409 static void rtl8168bef_hw_phy_config(void __iomem *ioaddr)
1410 {
1411         struct phy_reg phy_reg_init[] = {
1412                 { 0x1f, 0x0001 },
1413                 { 0x10, 0xf41b },
1414                 { 0x1f, 0x0000 }
1415         };
1416
1417         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1418 }
1419
1420 static void rtl8168cp_1_hw_phy_config(void __iomem *ioaddr)
1421 {
1422         struct phy_reg phy_reg_init[] = {
1423                 { 0x1f, 0x0000 },
1424                 { 0x1d, 0x0f00 },
1425                 { 0x1f, 0x0002 },
1426                 { 0x0c, 0x1ec8 },
1427                 { 0x1f, 0x0000 }
1428         };
1429
1430         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1431 }
1432
1433 static void rtl8168cp_2_hw_phy_config(void __iomem *ioaddr)
1434 {
1435         struct phy_reg phy_reg_init[] = {
1436                 { 0x1f, 0x0001 },
1437                 { 0x1d, 0x3d98 },
1438                 { 0x1f, 0x0000 }
1439         };
1440
1441         mdio_write(ioaddr, 0x1f, 0x0000);
1442         mdio_patch(ioaddr, 0x14, 1 << 5);
1443         mdio_patch(ioaddr, 0x0d, 1 << 5);
1444
1445         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1446 }
1447
1448 static void rtl8168c_1_hw_phy_config(void __iomem *ioaddr)
1449 {
1450         struct phy_reg phy_reg_init[] = {
1451                 { 0x1f, 0x0001 },
1452                 { 0x12, 0x2300 },
1453                 { 0x1f, 0x0002 },
1454                 { 0x00, 0x88d4 },
1455                 { 0x01, 0x82b1 },
1456                 { 0x03, 0x7002 },
1457                 { 0x08, 0x9e30 },
1458                 { 0x09, 0x01f0 },
1459                 { 0x0a, 0x5500 },
1460                 { 0x0c, 0x00c8 },
1461                 { 0x1f, 0x0003 },
1462                 { 0x12, 0xc096 },
1463                 { 0x16, 0x000a },
1464                 { 0x1f, 0x0000 },
1465                 { 0x1f, 0x0000 },
1466                 { 0x09, 0x2000 },
1467                 { 0x09, 0x0000 }
1468         };
1469
1470         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1471
1472         mdio_patch(ioaddr, 0x14, 1 << 5);
1473         mdio_patch(ioaddr, 0x0d, 1 << 5);
1474         mdio_write(ioaddr, 0x1f, 0x0000);
1475 }
1476
1477 static void rtl8168c_2_hw_phy_config(void __iomem *ioaddr)
1478 {
1479         struct phy_reg phy_reg_init[] = {
1480                 { 0x1f, 0x0001 },
1481                 { 0x12, 0x2300 },
1482                 { 0x03, 0x802f },
1483                 { 0x02, 0x4f02 },
1484                 { 0x01, 0x0409 },
1485                 { 0x00, 0xf099 },
1486                 { 0x04, 0x9800 },
1487                 { 0x04, 0x9000 },
1488                 { 0x1d, 0x3d98 },
1489                 { 0x1f, 0x0002 },
1490                 { 0x0c, 0x7eb8 },
1491                 { 0x06, 0x0761 },
1492                 { 0x1f, 0x0003 },
1493                 { 0x16, 0x0f0a },
1494                 { 0x1f, 0x0000 }
1495         };
1496
1497         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1498
1499         mdio_patch(ioaddr, 0x16, 1 << 0);
1500         mdio_patch(ioaddr, 0x14, 1 << 5);
1501         mdio_patch(ioaddr, 0x0d, 1 << 5);
1502         mdio_write(ioaddr, 0x1f, 0x0000);
1503 }
1504
1505 static void rtl8168c_3_hw_phy_config(void __iomem *ioaddr)
1506 {
1507         struct phy_reg phy_reg_init[] = {
1508                 { 0x1f, 0x0001 },
1509                 { 0x12, 0x2300 },
1510                 { 0x1d, 0x3d98 },
1511                 { 0x1f, 0x0002 },
1512                 { 0x0c, 0x7eb8 },
1513                 { 0x06, 0x5461 },
1514                 { 0x1f, 0x0003 },
1515                 { 0x16, 0x0f0a },
1516                 { 0x1f, 0x0000 }
1517         };
1518
1519         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1520
1521         mdio_patch(ioaddr, 0x16, 1 << 0);
1522         mdio_patch(ioaddr, 0x14, 1 << 5);
1523         mdio_patch(ioaddr, 0x0d, 1 << 5);
1524         mdio_write(ioaddr, 0x1f, 0x0000);
1525 }
1526
1527 static void rtl8168c_4_hw_phy_config(void __iomem *ioaddr)
1528 {
1529         rtl8168c_3_hw_phy_config(ioaddr);
1530 }
1531
1532 static void rtl8168d_hw_phy_config(void __iomem *ioaddr)
1533 {
1534         struct phy_reg phy_reg_init_0[] = {
1535                 { 0x1f, 0x0001 },
1536                 { 0x09, 0x2770 },
1537                 { 0x08, 0x04d0 },
1538                 { 0x0b, 0xad15 },
1539                 { 0x0c, 0x5bf0 },
1540                 { 0x1c, 0xf101 },
1541                 { 0x1f, 0x0003 },
1542                 { 0x14, 0x94d7 },
1543                 { 0x12, 0xf4d6 },
1544                 { 0x09, 0xca0f },
1545                 { 0x1f, 0x0002 },
1546                 { 0x0b, 0x0b10 },
1547                 { 0x0c, 0xd1f7 },
1548                 { 0x1f, 0x0002 },
1549                 { 0x06, 0x5461 },
1550                 { 0x1f, 0x0002 },
1551                 { 0x05, 0x6662 },
1552                 { 0x1f, 0x0000 },
1553                 { 0x14, 0x0060 },
1554                 { 0x1f, 0x0000 },
1555                 { 0x0d, 0xf8a0 },
1556                 { 0x1f, 0x0005 },
1557                 { 0x05, 0xffc2 }
1558         };
1559
1560         rtl_phy_write(ioaddr, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
1561
1562         if (mdio_read(ioaddr, 0x06) == 0xc400) {
1563                 struct phy_reg phy_reg_init_1[] = {
1564                         { 0x1f, 0x0005 },
1565                         { 0x01, 0x0300 },
1566                         { 0x1f, 0x0000 },
1567                         { 0x11, 0x401c },
1568                         { 0x16, 0x4100 },
1569                         { 0x1f, 0x0005 },
1570                         { 0x07, 0x0010 },
1571                         { 0x05, 0x83dc },
1572                         { 0x06, 0x087d },
1573                         { 0x05, 0x8300 },
1574                         { 0x06, 0x0101 },
1575                         { 0x06, 0x05f8 },
1576                         { 0x06, 0xf9fa },
1577                         { 0x06, 0xfbef },
1578                         { 0x06, 0x79e2 },
1579                         { 0x06, 0x835f },
1580                         { 0x06, 0xe0f8 },
1581                         { 0x06, 0x9ae1 },
1582                         { 0x06, 0xf89b },
1583                         { 0x06, 0xef31 },
1584                         { 0x06, 0x3b65 },
1585                         { 0x06, 0xaa07 },
1586                         { 0x06, 0x81e4 },
1587                         { 0x06, 0xf89a },
1588                         { 0x06, 0xe5f8 },
1589                         { 0x06, 0x9baf },
1590                         { 0x06, 0x06ae },
1591                         { 0x05, 0x83dc },
1592                         { 0x06, 0x8300 },
1593                 };
1594
1595                 rtl_phy_write(ioaddr, phy_reg_init_1,
1596                               ARRAY_SIZE(phy_reg_init_1));
1597         }
1598
1599         mdio_write(ioaddr, 0x1f, 0x0000);
1600 }
1601
1602 static void rtl8102e_hw_phy_config(void __iomem *ioaddr)
1603 {
1604         struct phy_reg phy_reg_init[] = {
1605                 { 0x1f, 0x0003 },
1606                 { 0x08, 0x441d },
1607                 { 0x01, 0x9100 },
1608                 { 0x1f, 0x0000 }
1609         };
1610
1611         mdio_write(ioaddr, 0x1f, 0x0000);
1612         mdio_patch(ioaddr, 0x11, 1 << 12);
1613         mdio_patch(ioaddr, 0x19, 1 << 13);
1614
1615         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1616 }
1617
1618 static void rtl_hw_phy_config(struct net_device *dev)
1619 {
1620         struct rtl8169_private *tp = netdev_priv(dev);
1621         void __iomem *ioaddr = tp->mmio_addr;
1622
1623         rtl8169_print_mac_version(tp);
1624
1625         switch (tp->mac_version) {
1626         case RTL_GIGA_MAC_VER_01:
1627                 break;
1628         case RTL_GIGA_MAC_VER_02:
1629         case RTL_GIGA_MAC_VER_03:
1630                 rtl8169s_hw_phy_config(ioaddr);
1631                 break;
1632         case RTL_GIGA_MAC_VER_04:
1633                 rtl8169sb_hw_phy_config(ioaddr);
1634                 break;
1635         case RTL_GIGA_MAC_VER_07:
1636         case RTL_GIGA_MAC_VER_08:
1637         case RTL_GIGA_MAC_VER_09:
1638                 rtl8102e_hw_phy_config(ioaddr);
1639                 break;
1640         case RTL_GIGA_MAC_VER_11:
1641                 rtl8168bb_hw_phy_config(ioaddr);
1642                 break;
1643         case RTL_GIGA_MAC_VER_12:
1644                 rtl8168bef_hw_phy_config(ioaddr);
1645                 break;
1646         case RTL_GIGA_MAC_VER_17:
1647                 rtl8168bef_hw_phy_config(ioaddr);
1648                 break;
1649         case RTL_GIGA_MAC_VER_18:
1650                 rtl8168cp_1_hw_phy_config(ioaddr);
1651                 break;
1652         case RTL_GIGA_MAC_VER_19:
1653                 rtl8168c_1_hw_phy_config(ioaddr);
1654                 break;
1655         case RTL_GIGA_MAC_VER_20:
1656                 rtl8168c_2_hw_phy_config(ioaddr);
1657                 break;
1658         case RTL_GIGA_MAC_VER_21:
1659                 rtl8168c_3_hw_phy_config(ioaddr);
1660                 break;
1661         case RTL_GIGA_MAC_VER_22:
1662                 rtl8168c_4_hw_phy_config(ioaddr);
1663                 break;
1664         case RTL_GIGA_MAC_VER_23:
1665         case RTL_GIGA_MAC_VER_24:
1666                 rtl8168cp_2_hw_phy_config(ioaddr);
1667                 break;
1668         case RTL_GIGA_MAC_VER_25:
1669                 rtl8168d_hw_phy_config(ioaddr);
1670                 break;
1671
1672         default:
1673                 break;
1674         }
1675 }
1676
1677 static void rtl8169_phy_timer(unsigned long __opaque)
1678 {
1679         struct net_device *dev = (struct net_device *)__opaque;
1680         struct rtl8169_private *tp = netdev_priv(dev);
1681         struct timer_list *timer = &tp->timer;
1682         void __iomem *ioaddr = tp->mmio_addr;
1683         unsigned long timeout = RTL8169_PHY_TIMEOUT;
1684
1685         assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1686
1687         if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1688                 return;
1689
1690         spin_lock_irq(&tp->lock);
1691
1692         if (tp->phy_reset_pending(ioaddr)) {
1693                 /*
1694                  * A busy loop could burn quite a few cycles on nowadays CPU.
1695                  * Let's delay the execution of the timer for a few ticks.
1696                  */
1697                 timeout = HZ/10;
1698                 goto out_mod_timer;
1699         }
1700
1701         if (tp->link_ok(ioaddr))
1702                 goto out_unlock;
1703
1704         if (netif_msg_link(tp))
1705                 printk(KERN_WARNING "%s: PHY reset until link up\n", dev->name);
1706
1707         tp->phy_reset_enable(ioaddr);
1708
1709 out_mod_timer:
1710         mod_timer(timer, jiffies + timeout);
1711 out_unlock:
1712         spin_unlock_irq(&tp->lock);
1713 }
1714
1715 static inline void rtl8169_delete_timer(struct net_device *dev)
1716 {
1717         struct rtl8169_private *tp = netdev_priv(dev);
1718         struct timer_list *timer = &tp->timer;
1719
1720         if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1721                 return;
1722
1723         del_timer_sync(timer);
1724 }
1725
1726 static inline void rtl8169_request_timer(struct net_device *dev)
1727 {
1728         struct rtl8169_private *tp = netdev_priv(dev);
1729         struct timer_list *timer = &tp->timer;
1730
1731         if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1732                 return;
1733
1734         mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
1735 }
1736
1737 #ifdef CONFIG_NET_POLL_CONTROLLER
1738 /*
1739  * Polling 'interrupt' - used by things like netconsole to send skbs
1740  * without having to re-enable interrupts. It's not called while
1741  * the interrupt routine is executing.
1742  */
1743 static void rtl8169_netpoll(struct net_device *dev)
1744 {
1745         struct rtl8169_private *tp = netdev_priv(dev);
1746         struct pci_dev *pdev = tp->pci_dev;
1747
1748         disable_irq(pdev->irq);
1749         rtl8169_interrupt(pdev->irq, dev);
1750         enable_irq(pdev->irq);
1751 }
1752 #endif
1753
1754 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
1755                                   void __iomem *ioaddr)
1756 {
1757         iounmap(ioaddr);
1758         pci_release_regions(pdev);
1759         pci_disable_device(pdev);
1760         free_netdev(dev);
1761 }
1762
1763 static void rtl8169_phy_reset(struct net_device *dev,
1764                               struct rtl8169_private *tp)
1765 {
1766         void __iomem *ioaddr = tp->mmio_addr;
1767         unsigned int i;
1768
1769         tp->phy_reset_enable(ioaddr);
1770         for (i = 0; i < 100; i++) {
1771                 if (!tp->phy_reset_pending(ioaddr))
1772                         return;
1773                 msleep(1);
1774         }
1775         if (netif_msg_link(tp))
1776                 printk(KERN_ERR "%s: PHY reset failed.\n", dev->name);
1777 }
1778
1779 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
1780 {
1781         void __iomem *ioaddr = tp->mmio_addr;
1782
1783         rtl_hw_phy_config(dev);
1784
1785         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
1786                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1787                 RTL_W8(0x82, 0x01);
1788         }
1789
1790         pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
1791
1792         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
1793                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
1794
1795         if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
1796                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1797                 RTL_W8(0x82, 0x01);
1798                 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
1799                 mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0
1800         }
1801
1802         rtl8169_phy_reset(dev, tp);
1803
1804         /*
1805          * rtl8169_set_speed_xmii takes good care of the Fast Ethernet
1806          * only 8101. Don't panic.
1807          */
1808         rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL);
1809
1810         if ((RTL_R8(PHYstatus) & TBI_Enable) && netif_msg_link(tp))
1811                 printk(KERN_INFO PFX "%s: TBI auto-negotiating\n", dev->name);
1812 }
1813
1814 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
1815 {
1816         void __iomem *ioaddr = tp->mmio_addr;
1817         u32 high;
1818         u32 low;
1819
1820         low  = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
1821         high = addr[4] | (addr[5] << 8);
1822
1823         spin_lock_irq(&tp->lock);
1824
1825         RTL_W8(Cfg9346, Cfg9346_Unlock);
1826         RTL_W32(MAC0, low);
1827         RTL_W32(MAC4, high);
1828         RTL_W8(Cfg9346, Cfg9346_Lock);
1829
1830         spin_unlock_irq(&tp->lock);
1831 }
1832
1833 static int rtl_set_mac_address(struct net_device *dev, void *p)
1834 {
1835         struct rtl8169_private *tp = netdev_priv(dev);
1836         struct sockaddr *addr = p;
1837
1838         if (!is_valid_ether_addr(addr->sa_data))
1839                 return -EADDRNOTAVAIL;
1840
1841         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1842
1843         rtl_rar_set(tp, dev->dev_addr);
1844
1845         return 0;
1846 }
1847
1848 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1849 {
1850         struct rtl8169_private *tp = netdev_priv(dev);
1851         struct mii_ioctl_data *data = if_mii(ifr);
1852
1853         return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
1854 }
1855
1856 static int rtl_xmii_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
1857 {
1858         switch (cmd) {
1859         case SIOCGMIIPHY:
1860                 data->phy_id = 32; /* Internal PHY */
1861                 return 0;
1862
1863         case SIOCGMIIREG:
1864                 data->val_out = mdio_read(tp->mmio_addr, data->reg_num & 0x1f);
1865                 return 0;
1866
1867         case SIOCSMIIREG:
1868                 if (!capable(CAP_NET_ADMIN))
1869                         return -EPERM;
1870                 mdio_write(tp->mmio_addr, data->reg_num & 0x1f, data->val_in);
1871                 return 0;
1872         }
1873         return -EOPNOTSUPP;
1874 }
1875
1876 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
1877 {
1878         return -EOPNOTSUPP;
1879 }
1880
1881 static const struct rtl_cfg_info {
1882         void (*hw_start)(struct net_device *);
1883         unsigned int region;
1884         unsigned int align;
1885         u16 intr_event;
1886         u16 napi_event;
1887         unsigned features;
1888         u8 default_ver;
1889 } rtl_cfg_infos [] = {
1890         [RTL_CFG_0] = {
1891                 .hw_start       = rtl_hw_start_8169,
1892                 .region         = 1,
1893                 .align          = 0,
1894                 .intr_event     = SYSErr | LinkChg | RxOverflow |
1895                                   RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
1896                 .napi_event     = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
1897                 .features       = RTL_FEATURE_GMII,
1898                 .default_ver    = RTL_GIGA_MAC_VER_01,
1899         },
1900         [RTL_CFG_1] = {
1901                 .hw_start       = rtl_hw_start_8168,
1902                 .region         = 2,
1903                 .align          = 8,
1904                 .intr_event     = SYSErr | LinkChg | RxOverflow |
1905                                   TxErr | TxOK | RxOK | RxErr,
1906                 .napi_event     = TxErr | TxOK | RxOK | RxOverflow,
1907                 .features       = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
1908                 .default_ver    = RTL_GIGA_MAC_VER_11,
1909         },
1910         [RTL_CFG_2] = {
1911                 .hw_start       = rtl_hw_start_8101,
1912                 .region         = 2,
1913                 .align          = 8,
1914                 .intr_event     = SYSErr | LinkChg | RxOverflow | PCSTimeout |
1915                                   RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
1916                 .napi_event     = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
1917                 .features       = RTL_FEATURE_MSI,
1918                 .default_ver    = RTL_GIGA_MAC_VER_13,
1919         }
1920 };
1921
1922 /* Cfg9346_Unlock assumed. */
1923 static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
1924                             const struct rtl_cfg_info *cfg)
1925 {
1926         unsigned msi = 0;
1927         u8 cfg2;
1928
1929         cfg2 = RTL_R8(Config2) & ~MSIEnable;
1930         if (cfg->features & RTL_FEATURE_MSI) {
1931                 if (pci_enable_msi(pdev)) {
1932                         dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
1933                 } else {
1934                         cfg2 |= MSIEnable;
1935                         msi = RTL_FEATURE_MSI;
1936                 }
1937         }
1938         RTL_W8(Config2, cfg2);
1939         return msi;
1940 }
1941
1942 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
1943 {
1944         if (tp->features & RTL_FEATURE_MSI) {
1945                 pci_disable_msi(pdev);
1946                 tp->features &= ~RTL_FEATURE_MSI;
1947         }
1948 }
1949
1950 static const struct net_device_ops rtl8169_netdev_ops = {
1951         .ndo_open               = rtl8169_open,
1952         .ndo_stop               = rtl8169_close,
1953         .ndo_get_stats          = rtl8169_get_stats,
1954         .ndo_start_xmit         = rtl8169_start_xmit,
1955         .ndo_tx_timeout         = rtl8169_tx_timeout,
1956         .ndo_validate_addr      = eth_validate_addr,
1957         .ndo_change_mtu         = rtl8169_change_mtu,
1958         .ndo_set_mac_address    = rtl_set_mac_address,
1959         .ndo_do_ioctl           = rtl8169_ioctl,
1960         .ndo_set_multicast_list = rtl_set_rx_mode,
1961 #ifdef CONFIG_R8169_VLAN
1962         .ndo_vlan_rx_register   = rtl8169_vlan_rx_register,
1963 #endif
1964 #ifdef CONFIG_NET_POLL_CONTROLLER
1965         .ndo_poll_controller    = rtl8169_netpoll,
1966 #endif
1967
1968 };
1969
1970 static int __devinit
1971 rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1972 {
1973         const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
1974         const unsigned int region = cfg->region;
1975         struct rtl8169_private *tp;
1976         struct mii_if_info *mii;
1977         struct net_device *dev;
1978         void __iomem *ioaddr;
1979         unsigned int i;
1980         int rc;
1981
1982         if (netif_msg_drv(&debug)) {
1983                 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
1984                        MODULENAME, RTL8169_VERSION);
1985         }
1986
1987         dev = alloc_etherdev(sizeof (*tp));
1988         if (!dev) {
1989                 if (netif_msg_drv(&debug))
1990                         dev_err(&pdev->dev, "unable to alloc new ethernet\n");
1991                 rc = -ENOMEM;
1992                 goto out;
1993         }
1994
1995         SET_NETDEV_DEV(dev, &pdev->dev);
1996         dev->netdev_ops = &rtl8169_netdev_ops;
1997         tp = netdev_priv(dev);
1998         tp->dev = dev;
1999         tp->pci_dev = pdev;
2000         tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
2001
2002         mii = &tp->mii;
2003         mii->dev = dev;
2004         mii->mdio_read = rtl_mdio_read;
2005         mii->mdio_write = rtl_mdio_write;
2006         mii->phy_id_mask = 0x1f;
2007         mii->reg_num_mask = 0x1f;
2008         mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
2009
2010         /* enable device (incl. PCI PM wakeup and hotplug setup) */
2011         rc = pci_enable_device(pdev);
2012         if (rc < 0) {
2013                 if (netif_msg_probe(tp))
2014                         dev_err(&pdev->dev, "enable failure\n");
2015                 goto err_out_free_dev_1;
2016         }
2017
2018         rc = pci_set_mwi(pdev);
2019         if (rc < 0)
2020                 goto err_out_disable_2;
2021
2022         /* make sure PCI base addr 1 is MMIO */
2023         if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
2024                 if (netif_msg_probe(tp)) {
2025                         dev_err(&pdev->dev,
2026                                 "region #%d not an MMIO resource, aborting\n",
2027                                 region);
2028                 }
2029                 rc = -ENODEV;
2030                 goto err_out_mwi_3;
2031         }
2032
2033         /* check for weird/broken PCI region reporting */
2034         if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
2035                 if (netif_msg_probe(tp)) {
2036                         dev_err(&pdev->dev,
2037                                 "Invalid PCI region size(s), aborting\n");
2038                 }
2039                 rc = -ENODEV;
2040                 goto err_out_mwi_3;
2041         }
2042
2043         rc = pci_request_regions(pdev, MODULENAME);
2044         if (rc < 0) {
2045                 if (netif_msg_probe(tp))
2046                         dev_err(&pdev->dev, "could not request regions.\n");
2047                 goto err_out_mwi_3;
2048         }
2049
2050         tp->cp_cmd = PCIMulRW | RxChkSum;
2051
2052         if ((sizeof(dma_addr_t) > 4) &&
2053             !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
2054                 tp->cp_cmd |= PCIDAC;
2055                 dev->features |= NETIF_F_HIGHDMA;
2056         } else {
2057                 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2058                 if (rc < 0) {
2059                         if (netif_msg_probe(tp)) {
2060                                 dev_err(&pdev->dev,
2061                                         "DMA configuration failed.\n");
2062                         }
2063                         goto err_out_free_res_4;
2064                 }
2065         }
2066
2067         pci_set_master(pdev);
2068
2069         /* ioremap MMIO region */
2070         ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
2071         if (!ioaddr) {
2072                 if (netif_msg_probe(tp))
2073                         dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
2074                 rc = -EIO;
2075                 goto err_out_free_res_4;
2076         }
2077
2078         tp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
2079         if (!tp->pcie_cap && netif_msg_probe(tp))
2080                 dev_info(&pdev->dev, "no PCI Express capability\n");
2081
2082         RTL_W16(IntrMask, 0x0000);
2083
2084         /* Soft reset the chip. */
2085         RTL_W8(ChipCmd, CmdReset);
2086
2087         /* Check that the chip has finished the reset. */
2088         for (i = 0; i < 100; i++) {
2089                 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
2090                         break;
2091                 msleep_interruptible(1);
2092         }
2093
2094         RTL_W16(IntrStatus, 0xffff);
2095
2096         /* Identify chip attached to board */
2097         rtl8169_get_mac_version(tp, ioaddr);
2098
2099         /* Use appropriate default if unknown */
2100         if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2101                 if (netif_msg_probe(tp)) {
2102                         dev_notice(&pdev->dev,
2103                                    "unknown MAC, using family default\n");
2104                 }
2105                 tp->mac_version = cfg->default_ver;
2106         }
2107
2108         rtl8169_print_mac_version(tp);
2109
2110         for (i = 0; i < ARRAY_SIZE(rtl_chip_info); i++) {
2111                 if (tp->mac_version == rtl_chip_info[i].mac_version)
2112                         break;
2113         }
2114         if (i == ARRAY_SIZE(rtl_chip_info)) {
2115                 dev_err(&pdev->dev,
2116                         "driver bug, MAC version not found in rtl_chip_info\n");
2117                 goto err_out_msi_5;
2118         }
2119         tp->chipset = i;
2120
2121         RTL_W8(Cfg9346, Cfg9346_Unlock);
2122         RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
2123         RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
2124         if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
2125                 tp->features |= RTL_FEATURE_WOL;
2126         if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
2127                 tp->features |= RTL_FEATURE_WOL;
2128         tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
2129         RTL_W8(Cfg9346, Cfg9346_Lock);
2130
2131         if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
2132             (RTL_R8(PHYstatus) & TBI_Enable)) {
2133                 tp->set_speed = rtl8169_set_speed_tbi;
2134                 tp->get_settings = rtl8169_gset_tbi;
2135                 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
2136                 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
2137                 tp->link_ok = rtl8169_tbi_link_ok;
2138                 tp->do_ioctl = rtl_tbi_ioctl;
2139
2140                 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
2141         } else {
2142                 tp->set_speed = rtl8169_set_speed_xmii;
2143                 tp->get_settings = rtl8169_gset_xmii;
2144                 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
2145                 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
2146                 tp->link_ok = rtl8169_xmii_link_ok;
2147                 tp->do_ioctl = rtl_xmii_ioctl;
2148         }
2149
2150         spin_lock_init(&tp->lock);
2151
2152         tp->mmio_addr = ioaddr;
2153
2154         /* Get MAC address */
2155         for (i = 0; i < MAC_ADDR_LEN; i++)
2156                 dev->dev_addr[i] = RTL_R8(MAC0 + i);
2157         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
2158
2159         SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
2160         dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
2161         dev->irq = pdev->irq;
2162         dev->base_addr = (unsigned long) ioaddr;
2163
2164         netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
2165
2166 #ifdef CONFIG_R8169_VLAN
2167         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
2168 #endif
2169
2170         tp->intr_mask = 0xffff;
2171         tp->align = cfg->align;
2172         tp->hw_start = cfg->hw_start;
2173         tp->intr_event = cfg->intr_event;
2174         tp->napi_event = cfg->napi_event;
2175
2176         init_timer(&tp->timer);
2177         tp->timer.data = (unsigned long) dev;
2178         tp->timer.function = rtl8169_phy_timer;
2179
2180         rc = register_netdev(dev);
2181         if (rc < 0)
2182                 goto err_out_msi_5;
2183
2184         pci_set_drvdata(pdev, dev);
2185
2186         if (netif_msg_probe(tp)) {
2187                 u32 xid = RTL_R32(TxConfig) & 0x7cf0f8ff;
2188
2189                 printk(KERN_INFO "%s: %s at 0x%lx, "
2190                        "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
2191                        "XID %08x IRQ %d\n",
2192                        dev->name,
2193                        rtl_chip_info[tp->chipset].name,
2194                        dev->base_addr,
2195                        dev->dev_addr[0], dev->dev_addr[1],
2196                        dev->dev_addr[2], dev->dev_addr[3],
2197                        dev->dev_addr[4], dev->dev_addr[5], xid, dev->irq);
2198         }
2199
2200         rtl8169_init_phy(dev, tp);
2201         device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
2202
2203 out:
2204         return rc;
2205
2206 err_out_msi_5:
2207         rtl_disable_msi(pdev, tp);
2208         iounmap(ioaddr);
2209 err_out_free_res_4:
2210         pci_release_regions(pdev);
2211 err_out_mwi_3:
2212         pci_clear_mwi(pdev);
2213 err_out_disable_2:
2214         pci_disable_device(pdev);
2215 err_out_free_dev_1:
2216         free_netdev(dev);
2217         goto out;
2218 }
2219
2220 static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
2221 {
2222         struct net_device *dev = pci_get_drvdata(pdev);
2223         struct rtl8169_private *tp = netdev_priv(dev);
2224
2225         flush_scheduled_work();
2226
2227         unregister_netdev(dev);
2228         rtl_disable_msi(pdev, tp);
2229         rtl8169_release_board(pdev, dev, tp->mmio_addr);
2230         pci_set_drvdata(pdev, NULL);
2231 }
2232
2233 static void rtl8169_set_rxbufsize(struct rtl8169_private *tp,
2234                                   struct net_device *dev)
2235 {
2236         unsigned int mtu = dev->mtu;
2237
2238         tp->rx_buf_sz = (mtu > RX_BUF_SIZE) ? mtu + ETH_HLEN + 8 : RX_BUF_SIZE;
2239 }
2240
2241 static int rtl8169_open(struct net_device *dev)
2242 {
2243         struct rtl8169_private *tp = netdev_priv(dev);
2244         struct pci_dev *pdev = tp->pci_dev;
2245         int retval = -ENOMEM;
2246
2247
2248         rtl8169_set_rxbufsize(tp, dev);
2249
2250         /*
2251          * Rx and Tx desscriptors needs 256 bytes alignment.
2252          * pci_alloc_consistent provides more.
2253          */
2254         tp->TxDescArray = pci_alloc_consistent(pdev, R8169_TX_RING_BYTES,
2255                                                &tp->TxPhyAddr);
2256         if (!tp->TxDescArray)
2257                 goto out;
2258
2259         tp->RxDescArray = pci_alloc_consistent(pdev, R8169_RX_RING_BYTES,
2260                                                &tp->RxPhyAddr);
2261         if (!tp->RxDescArray)
2262                 goto err_free_tx_0;
2263
2264         retval = rtl8169_init_ring(dev);
2265         if (retval < 0)
2266                 goto err_free_rx_1;
2267
2268         INIT_DELAYED_WORK(&tp->task, NULL);
2269
2270         smp_mb();
2271
2272         retval = request_irq(dev->irq, rtl8169_interrupt,
2273                              (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
2274                              dev->name, dev);
2275         if (retval < 0)
2276                 goto err_release_ring_2;
2277
2278         napi_enable(&tp->napi);
2279
2280         rtl_hw_start(dev);
2281
2282         rtl8169_request_timer(dev);
2283
2284         rtl8169_check_link_status(dev, tp, tp->mmio_addr);
2285 out:
2286         return retval;
2287
2288 err_release_ring_2:
2289         rtl8169_rx_clear(tp);
2290 err_free_rx_1:
2291         pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
2292                             tp->RxPhyAddr);
2293 err_free_tx_0:
2294         pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
2295                             tp->TxPhyAddr);
2296         goto out;
2297 }
2298
2299 static void rtl8169_hw_reset(void __iomem *ioaddr)
2300 {
2301         /* Disable interrupts */
2302         rtl8169_irq_mask_and_ack(ioaddr);
2303
2304         /* Reset the chipset */
2305         RTL_W8(ChipCmd, CmdReset);
2306
2307         /* PCI commit */
2308         RTL_R8(ChipCmd);
2309 }
2310
2311 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
2312 {
2313         void __iomem *ioaddr = tp->mmio_addr;
2314         u32 cfg = rtl8169_rx_config;
2315
2316         cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
2317         RTL_W32(RxConfig, cfg);
2318
2319         /* Set DMA burst size and Interframe Gap Time */
2320         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
2321                 (InterFrameGap << TxInterFrameGapShift));
2322 }
2323
2324 static void rtl_hw_start(struct net_device *dev)
2325 {
2326         struct rtl8169_private *tp = netdev_priv(dev);
2327         void __iomem *ioaddr = tp->mmio_addr;
2328         unsigned int i;
2329
2330         /* Soft reset the chip. */
2331         RTL_W8(ChipCmd, CmdReset);
2332
2333         /* Check that the chip has finished the reset. */
2334         for (i = 0; i < 100; i++) {
2335                 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
2336                         break;
2337                 msleep_interruptible(1);
2338         }
2339
2340         tp->hw_start(dev);
2341
2342         netif_start_queue(dev);
2343 }
2344
2345
2346 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
2347                                          void __iomem *ioaddr)
2348 {
2349         /*
2350          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
2351          * register to be written before TxDescAddrLow to work.
2352          * Switching from MMIO to I/O access fixes the issue as well.
2353          */
2354         RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
2355         RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
2356         RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
2357         RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
2358 }
2359
2360 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
2361 {
2362         u16 cmd;
2363
2364         cmd = RTL_R16(CPlusCmd);
2365         RTL_W16(CPlusCmd, cmd);
2366         return cmd;
2367 }
2368
2369 static void rtl_set_rx_max_size(void __iomem *ioaddr)
2370 {
2371         /* Low hurts. Let's disable the filtering. */
2372         RTL_W16(RxMaxSize, 16383);
2373 }
2374
2375 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
2376 {
2377         struct {
2378                 u32 mac_version;
2379                 u32 clk;
2380                 u32 val;
2381         } cfg2_info [] = {
2382                 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
2383                 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
2384                 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
2385                 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
2386         }, *p = cfg2_info;
2387         unsigned int i;
2388         u32 clk;
2389
2390         clk = RTL_R8(Config2) & PCI_Clock_66MHz;
2391         for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
2392                 if ((p->mac_version == mac_version) && (p->clk == clk)) {
2393                         RTL_W32(0x7c, p->val);
2394                         break;
2395                 }
2396         }
2397 }
2398
2399 static void rtl_hw_start_8169(struct net_device *dev)
2400 {
2401         struct rtl8169_private *tp = netdev_priv(dev);
2402         void __iomem *ioaddr = tp->mmio_addr;
2403         struct pci_dev *pdev = tp->pci_dev;
2404
2405         if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
2406                 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
2407                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
2408         }
2409
2410         RTL_W8(Cfg9346, Cfg9346_Unlock);
2411         if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
2412             (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2413             (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
2414             (tp->mac_version == RTL_GIGA_MAC_VER_04))
2415                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2416
2417         RTL_W8(EarlyTxThres, EarlyTxThld);
2418
2419         rtl_set_rx_max_size(ioaddr);
2420
2421         if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
2422             (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2423             (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
2424             (tp->mac_version == RTL_GIGA_MAC_VER_04))
2425                 rtl_set_rx_tx_config_registers(tp);
2426
2427         tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
2428
2429         if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2430             (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
2431                 dprintk("Set MAC Reg C+CR Offset 0xE0. "
2432                         "Bit-3 and bit-14 MUST be 1\n");
2433                 tp->cp_cmd |= (1 << 14);
2434         }
2435
2436         RTL_W16(CPlusCmd, tp->cp_cmd);
2437
2438         rtl8169_set_magic_reg(ioaddr, tp->mac_version);
2439
2440         /*
2441          * Undocumented corner. Supposedly:
2442          * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
2443          */
2444         RTL_W16(IntrMitigate, 0x0000);
2445
2446         rtl_set_rx_tx_desc_registers(tp, ioaddr);
2447
2448         if ((tp->mac_version != RTL_GIGA_MAC_VER_01) &&
2449             (tp->mac_version != RTL_GIGA_MAC_VER_02) &&
2450             (tp->mac_version != RTL_GIGA_MAC_VER_03) &&
2451             (tp->mac_version != RTL_GIGA_MAC_VER_04)) {
2452                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2453                 rtl_set_rx_tx_config_registers(tp);
2454         }
2455
2456         RTL_W8(Cfg9346, Cfg9346_Lock);
2457
2458         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
2459         RTL_R8(IntrMask);
2460
2461         RTL_W32(RxMissed, 0);
2462
2463         rtl_set_rx_mode(dev);
2464
2465         /* no early-rx interrupts */
2466         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
2467
2468         /* Enable all known interrupts by setting the interrupt mask. */
2469         RTL_W16(IntrMask, tp->intr_event);
2470 }
2471
2472 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
2473 {
2474         struct net_device *dev = pci_get_drvdata(pdev);
2475         struct rtl8169_private *tp = netdev_priv(dev);
2476         int cap = tp->pcie_cap;
2477
2478         if (cap) {
2479                 u16 ctl;
2480
2481                 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
2482                 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
2483                 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
2484         }
2485 }
2486
2487 static void rtl_csi_access_enable(void __iomem *ioaddr)
2488 {
2489         u32 csi;
2490
2491         csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
2492         rtl_csi_write(ioaddr, 0x070c, csi | 0x27000000);
2493 }
2494
2495 struct ephy_info {
2496         unsigned int offset;
2497         u16 mask;
2498         u16 bits;
2499 };
2500
2501 static void rtl_ephy_init(void __iomem *ioaddr, struct ephy_info *e, int len)
2502 {
2503         u16 w;
2504
2505         while (len-- > 0) {
2506                 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
2507                 rtl_ephy_write(ioaddr, e->offset, w);
2508                 e++;
2509         }
2510 }
2511
2512 static void rtl_disable_clock_request(struct pci_dev *pdev)
2513 {
2514         struct net_device *dev = pci_get_drvdata(pdev);
2515         struct rtl8169_private *tp = netdev_priv(dev);
2516         int cap = tp->pcie_cap;
2517
2518         if (cap) {
2519                 u16 ctl;
2520
2521                 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
2522                 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
2523                 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
2524         }
2525 }
2526
2527 #define R8168_CPCMD_QUIRK_MASK (\
2528         EnableBist | \
2529         Mac_dbgo_oe | \
2530         Force_half_dup | \
2531         Force_rxflow_en | \
2532         Force_txflow_en | \
2533         Cxpl_dbg_sel | \
2534         ASF | \
2535         PktCntrDisable | \
2536         Mac_dbgo_sel)
2537
2538 static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
2539 {
2540         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2541
2542         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
2543
2544         rtl_tx_performance_tweak(pdev,
2545                 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
2546 }
2547
2548 static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
2549 {
2550         rtl_hw_start_8168bb(ioaddr, pdev);
2551
2552         RTL_W8(EarlyTxThres, EarlyTxThld);
2553
2554         RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
2555 }
2556
2557 static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
2558 {
2559         RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
2560
2561         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2562
2563         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2564
2565         rtl_disable_clock_request(pdev);
2566
2567         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
2568 }
2569
2570 static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
2571 {
2572         static struct ephy_info e_info_8168cp[] = {
2573                 { 0x01, 0,      0x0001 },
2574                 { 0x02, 0x0800, 0x1000 },
2575                 { 0x03, 0,      0x0042 },
2576                 { 0x06, 0x0080, 0x0000 },
2577                 { 0x07, 0,      0x2000 }
2578         };
2579
2580         rtl_csi_access_enable(ioaddr);
2581
2582         rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
2583
2584         __rtl_hw_start_8168cp(ioaddr, pdev);
2585 }
2586
2587 static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
2588 {
2589         rtl_csi_access_enable(ioaddr);
2590
2591         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2592
2593         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2594
2595         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
2596 }
2597
2598 static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
2599 {
2600         rtl_csi_access_enable(ioaddr);
2601
2602         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2603
2604         /* Magic. */
2605         RTL_W8(DBG_REG, 0x20);
2606
2607         RTL_W8(EarlyTxThres, EarlyTxThld);
2608
2609         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2610
2611         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
2612 }
2613
2614 static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
2615 {
2616         static struct ephy_info e_info_8168c_1[] = {
2617                 { 0x02, 0x0800, 0x1000 },
2618                 { 0x03, 0,      0x0002 },
2619                 { 0x06, 0x0080, 0x0000 }
2620         };
2621
2622         rtl_csi_access_enable(ioaddr);
2623
2624         RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
2625
2626         rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
2627
2628         __rtl_hw_start_8168cp(ioaddr, pdev);
2629 }
2630
2631 static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
2632 {
2633         static struct ephy_info e_info_8168c_2[] = {
2634                 { 0x01, 0,      0x0001 },
2635                 { 0x03, 0x0400, 0x0220 }
2636         };
2637
2638         rtl_csi_access_enable(ioaddr);
2639
2640         rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
2641
2642         __rtl_hw_start_8168cp(ioaddr, pdev);
2643 }
2644
2645 static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
2646 {
2647         rtl_hw_start_8168c_2(ioaddr, pdev);
2648 }
2649
2650 static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
2651 {
2652         rtl_csi_access_enable(ioaddr);
2653
2654         __rtl_hw_start_8168cp(ioaddr, pdev);
2655 }
2656
2657 static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
2658 {
2659         rtl_csi_access_enable(ioaddr);
2660
2661         rtl_disable_clock_request(pdev);
2662
2663         RTL_W8(EarlyTxThres, EarlyTxThld);
2664
2665         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2666
2667         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
2668 }
2669
2670 static void rtl_hw_start_8168(struct net_device *dev)
2671 {
2672         struct rtl8169_private *tp = netdev_priv(dev);
2673         void __iomem *ioaddr = tp->mmio_addr;
2674         struct pci_dev *pdev = tp->pci_dev;
2675
2676         RTL_W8(Cfg9346, Cfg9346_Unlock);
2677
2678         RTL_W8(EarlyTxThres, EarlyTxThld);
2679
2680         rtl_set_rx_max_size(ioaddr);
2681
2682         tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
2683
2684         RTL_W16(CPlusCmd, tp->cp_cmd);
2685
2686         RTL_W16(IntrMitigate, 0x5151);
2687
2688         /* Work around for RxFIFO overflow. */
2689         if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
2690                 tp->intr_event |= RxFIFOOver | PCSTimeout;
2691                 tp->intr_event &= ~RxOverflow;
2692         }
2693
2694         rtl_set_rx_tx_desc_registers(tp, ioaddr);
2695
2696         rtl_set_rx_mode(dev);
2697
2698         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
2699                 (InterFrameGap << TxInterFrameGapShift));
2700
2701         RTL_R8(IntrMask);
2702
2703         switch (tp->mac_version) {
2704         case RTL_GIGA_MAC_VER_11:
2705                 rtl_hw_start_8168bb(ioaddr, pdev);
2706         break;
2707
2708         case RTL_GIGA_MAC_VER_12:
2709         case RTL_GIGA_MAC_VER_17:
2710                 rtl_hw_start_8168bef(ioaddr, pdev);
2711         break;
2712
2713         case RTL_GIGA_MAC_VER_18:
2714                 rtl_hw_start_8168cp_1(ioaddr, pdev);
2715         break;
2716
2717         case RTL_GIGA_MAC_VER_19:
2718                 rtl_hw_start_8168c_1(ioaddr, pdev);
2719         break;
2720
2721         case RTL_GIGA_MAC_VER_20:
2722                 rtl_hw_start_8168c_2(ioaddr, pdev);
2723         break;
2724
2725         case RTL_GIGA_MAC_VER_21:
2726                 rtl_hw_start_8168c_3(ioaddr, pdev);
2727         break;
2728
2729         case RTL_GIGA_MAC_VER_22:
2730                 rtl_hw_start_8168c_4(ioaddr, pdev);
2731         break;
2732
2733         case RTL_GIGA_MAC_VER_23:
2734                 rtl_hw_start_8168cp_2(ioaddr, pdev);
2735         break;
2736
2737         case RTL_GIGA_MAC_VER_24:
2738                 rtl_hw_start_8168cp_3(ioaddr, pdev);
2739         break;
2740
2741         case RTL_GIGA_MAC_VER_25:
2742                 rtl_hw_start_8168d(ioaddr, pdev);
2743         break;
2744
2745         default:
2746                 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
2747                         dev->name, tp->mac_version);
2748         break;
2749         }
2750
2751         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2752
2753         RTL_W8(Cfg9346, Cfg9346_Lock);
2754
2755         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
2756
2757         RTL_W16(IntrMask, tp->intr_event);
2758 }
2759
2760 #define R810X_CPCMD_QUIRK_MASK (\
2761         EnableBist | \
2762         Mac_dbgo_oe | \
2763         Force_half_dup | \
2764         Force_half_dup | \
2765         Force_txflow_en | \
2766         Cxpl_dbg_sel | \
2767         ASF | \
2768         PktCntrDisable | \
2769         PCIDAC | \
2770         PCIMulRW)
2771
2772 static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
2773 {
2774         static struct ephy_info e_info_8102e_1[] = {
2775                 { 0x01, 0, 0x6e65 },
2776                 { 0x02, 0, 0x091f },
2777                 { 0x03, 0, 0xc2f9 },
2778                 { 0x06, 0, 0xafb5 },
2779                 { 0x07, 0, 0x0e00 },
2780                 { 0x19, 0, 0xec80 },
2781                 { 0x01, 0, 0x2e65 },
2782                 { 0x01, 0, 0x6e65 }
2783         };
2784         u8 cfg1;
2785
2786         rtl_csi_access_enable(ioaddr);
2787
2788         RTL_W8(DBG_REG, FIX_NAK_1);
2789
2790         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2791
2792         RTL_W8(Config1,
2793                LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
2794         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2795
2796         cfg1 = RTL_R8(Config1);
2797         if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
2798                 RTL_W8(Config1, cfg1 & ~LEDS0);
2799
2800         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
2801
2802         rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
2803 }
2804
2805 static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
2806 {
2807         rtl_csi_access_enable(ioaddr);
2808
2809         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2810
2811         RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
2812         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2813
2814         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
2815 }
2816
2817 static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
2818 {
2819         rtl_hw_start_8102e_2(ioaddr, pdev);
2820
2821         rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
2822 }
2823
2824 static void rtl_hw_start_8101(struct net_device *dev)
2825 {
2826         struct rtl8169_private *tp = netdev_priv(dev);
2827         void __iomem *ioaddr = tp->mmio_addr;
2828         struct pci_dev *pdev = tp->pci_dev;
2829
2830         if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
2831             (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
2832                 int cap = tp->pcie_cap;
2833
2834                 if (cap) {
2835                         pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
2836                                               PCI_EXP_DEVCTL_NOSNOOP_EN);
2837                 }
2838         }
2839
2840         switch (tp->mac_version) {
2841         case RTL_GIGA_MAC_VER_07:
2842                 rtl_hw_start_8102e_1(ioaddr, pdev);
2843                 break;
2844
2845         case RTL_GIGA_MAC_VER_08:
2846                 rtl_hw_start_8102e_3(ioaddr, pdev);
2847                 break;
2848
2849         case RTL_GIGA_MAC_VER_09:
2850                 rtl_hw_start_8102e_2(ioaddr, pdev);
2851                 break;
2852         }
2853
2854         RTL_W8(Cfg9346, Cfg9346_Unlock);
2855
2856         RTL_W8(EarlyTxThres, EarlyTxThld);
2857
2858         rtl_set_rx_max_size(ioaddr);
2859
2860         tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
2861
2862         RTL_W16(CPlusCmd, tp->cp_cmd);
2863
2864         RTL_W16(IntrMitigate, 0x0000);
2865
2866         rtl_set_rx_tx_desc_registers(tp, ioaddr);
2867
2868         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2869         rtl_set_rx_tx_config_registers(tp);
2870
2871         RTL_W8(Cfg9346, Cfg9346_Lock);
2872
2873         RTL_R8(IntrMask);
2874
2875         rtl_set_rx_mode(dev);
2876
2877         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2878
2879         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
2880
2881         RTL_W16(IntrMask, tp->intr_event);
2882 }
2883
2884 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
2885 {
2886         struct rtl8169_private *tp = netdev_priv(dev);
2887         int ret = 0;
2888
2889         if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
2890                 return -EINVAL;
2891
2892         dev->mtu = new_mtu;
2893
2894         if (!netif_running(dev))
2895                 goto out;
2896
2897         rtl8169_down(dev);
2898
2899         rtl8169_set_rxbufsize(tp, dev);
2900
2901         ret = rtl8169_init_ring(dev);
2902         if (ret < 0)
2903                 goto out;
2904
2905         napi_enable(&tp->napi);
2906
2907         rtl_hw_start(dev);
2908
2909         rtl8169_request_timer(dev);
2910
2911 out:
2912         return ret;
2913 }
2914
2915 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
2916 {
2917         desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
2918         desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
2919 }
2920
2921 static void rtl8169_free_rx_skb(struct rtl8169_private *tp,
2922                                 struct sk_buff **sk_buff, struct RxDesc *desc)
2923 {
2924         struct pci_dev *pdev = tp->pci_dev;
2925
2926         pci_unmap_single(pdev, le64_to_cpu(desc->addr), tp->rx_buf_sz,
2927                          PCI_DMA_FROMDEVICE);
2928         dev_kfree_skb(*sk_buff);
2929         *sk_buff = NULL;
2930         rtl8169_make_unusable_by_asic(desc);
2931 }
2932
2933 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
2934 {
2935         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
2936
2937         desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
2938 }
2939
2940 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
2941                                        u32 rx_buf_sz)
2942 {
2943         desc->addr = cpu_to_le64(mapping);
2944         wmb();
2945         rtl8169_mark_to_asic(desc, rx_buf_sz);
2946 }
2947
2948 static struct sk_buff *rtl8169_alloc_rx_skb(struct pci_dev *pdev,
2949                                             struct net_device *dev,
2950                                             struct RxDesc *desc, int rx_buf_sz,
2951                                             unsigned int align)
2952 {
2953         struct sk_buff *skb;
2954         dma_addr_t mapping;
2955         unsigned int pad;
2956
2957         pad = align ? align : NET_IP_ALIGN;
2958
2959         skb = netdev_alloc_skb(dev, rx_buf_sz + pad);
2960         if (!skb)
2961                 goto err_out;
2962
2963         skb_reserve(skb, align ? ((pad - 1) & (unsigned long)skb->data) : pad);
2964
2965         mapping = pci_map_single(pdev, skb->data, rx_buf_sz,
2966                                  PCI_DMA_FROMDEVICE);
2967
2968         rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
2969 out:
2970         return skb;
2971
2972 err_out:
2973         rtl8169_make_unusable_by_asic(desc);
2974         goto out;
2975 }
2976
2977 static void rtl8169_rx_clear(struct rtl8169_private *tp)
2978 {
2979         unsigned int i;
2980
2981         for (i = 0; i < NUM_RX_DESC; i++) {
2982                 if (tp->Rx_skbuff[i]) {
2983                         rtl8169_free_rx_skb(tp, tp->Rx_skbuff + i,
2984                                             tp->RxDescArray + i);
2985                 }
2986         }
2987 }
2988
2989 static u32 rtl8169_rx_fill(struct rtl8169_private *tp, struct net_device *dev,
2990                            u32 start, u32 end)
2991 {
2992         u32 cur;
2993
2994         for (cur = start; end - cur != 0; cur++) {
2995                 struct sk_buff *skb;
2996                 unsigned int i = cur % NUM_RX_DESC;
2997
2998                 WARN_ON((s32)(end - cur) < 0);
2999
3000                 if (tp->Rx_skbuff[i])
3001                         continue;
3002
3003                 skb = rtl8169_alloc_rx_skb(tp->pci_dev, dev,
3004                                            tp->RxDescArray + i,
3005                                            tp->rx_buf_sz, tp->align);
3006                 if (!skb)
3007                         break;
3008
3009                 tp->Rx_skbuff[i] = skb;
3010         }
3011         return cur - start;
3012 }
3013
3014 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
3015 {
3016         desc->opts1 |= cpu_to_le32(RingEnd);
3017 }
3018
3019 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
3020 {
3021         tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
3022 }
3023
3024 static int rtl8169_init_ring(struct net_device *dev)
3025 {
3026         struct rtl8169_private *tp = netdev_priv(dev);
3027
3028         rtl8169_init_ring_indexes(tp);
3029
3030         memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
3031         memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));
3032
3033         if (rtl8169_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC)
3034                 goto err_out;
3035
3036         rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
3037
3038         return 0;
3039
3040 err_out:
3041         rtl8169_rx_clear(tp);
3042         return -ENOMEM;
3043 }
3044
3045 static void rtl8169_unmap_tx_skb(struct pci_dev *pdev, struct ring_info *tx_skb,
3046                                  struct TxDesc *desc)
3047 {
3048         unsigned int len = tx_skb->len;
3049
3050         pci_unmap_single(pdev, le64_to_cpu(desc->addr), len, PCI_DMA_TODEVICE);
3051         desc->opts1 = 0x00;
3052         desc->opts2 = 0x00;
3053         desc->addr = 0x00;
3054         tx_skb->len = 0;
3055 }
3056
3057 static void rtl8169_tx_clear(struct rtl8169_private *tp)
3058 {
3059         unsigned int i;
3060
3061         for (i = tp->dirty_tx; i < tp->dirty_tx + NUM_TX_DESC; i++) {
3062                 unsigned int entry = i % NUM_TX_DESC;
3063                 struct ring_info *tx_skb = tp->tx_skb + entry;
3064                 unsigned int len = tx_skb->len;
3065
3066                 if (len) {
3067                         struct sk_buff *skb = tx_skb->skb;
3068
3069                         rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb,
3070                                              tp->TxDescArray + entry);
3071                         if (skb) {
3072                                 dev_kfree_skb(skb);
3073                                 tx_skb->skb = NULL;
3074                         }
3075                         tp->dev->stats.tx_dropped++;
3076                 }
3077         }
3078         tp->cur_tx = tp->dirty_tx = 0;
3079 }
3080
3081 static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
3082 {
3083         struct rtl8169_private *tp = netdev_priv(dev);
3084
3085         PREPARE_DELAYED_WORK(&tp->task, task);
3086         schedule_delayed_work(&tp->task, 4);
3087 }
3088
3089 static void rtl8169_wait_for_quiescence(struct net_device *dev)
3090 {
3091         struct rtl8169_private *tp = netdev_priv(dev);
3092         void __iomem *ioaddr = tp->mmio_addr;
3093
3094         synchronize_irq(dev->irq);
3095
3096         /* Wait for any pending NAPI task to complete */
3097         napi_disable(&tp->napi);
3098
3099         rtl8169_irq_mask_and_ack(ioaddr);
3100
3101         tp->intr_mask = 0xffff;
3102         RTL_W16(IntrMask, tp->intr_event);
3103         napi_enable(&tp->napi);
3104 }
3105
3106 static void rtl8169_reinit_task(struct work_struct *work)
3107 {
3108         struct rtl8169_private *tp =
3109                 container_of(work, struct rtl8169_private, task.work);
3110         struct net_device *dev = tp->dev;
3111         int ret;
3112
3113         rtnl_lock();
3114
3115         if (!netif_running(dev))
3116                 goto out_unlock;
3117
3118         rtl8169_wait_for_quiescence(dev);
3119         rtl8169_close(dev);
3120
3121         ret = rtl8169_open(dev);
3122         if (unlikely(ret < 0)) {
3123                 if (net_ratelimit() && netif_msg_drv(tp)) {
3124                         printk(KERN_ERR PFX "%s: reinit failure (status = %d)."
3125                                " Rescheduling.\n", dev->name, ret);
3126                 }
3127                 rtl8169_schedule_work(dev, rtl8169_reinit_task);
3128         }
3129
3130 out_unlock:
3131         rtnl_unlock();
3132 }
3133
3134 static void rtl8169_reset_task(struct work_struct *work)
3135 {
3136         struct rtl8169_private *tp =
3137                 container_of(work, struct rtl8169_private, task.work);
3138         struct net_device *dev = tp->dev;
3139
3140         rtnl_lock();
3141
3142         if (!netif_running(dev))
3143                 goto out_unlock;
3144
3145         rtl8169_wait_for_quiescence(dev);
3146
3147         rtl8169_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0);
3148         rtl8169_tx_clear(tp);
3149
3150         if (tp->dirty_rx == tp->cur_rx) {
3151                 rtl8169_init_ring_indexes(tp);
3152                 rtl_hw_start(dev);
3153                 netif_wake_queue(dev);
3154                 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
3155         } else {
3156                 if (net_ratelimit() && netif_msg_intr(tp)) {
3157                         printk(KERN_EMERG PFX "%s: Rx buffers shortage\n",
3158                                dev->name);
3159                 }
3160                 rtl8169_schedule_work(dev, rtl8169_reset_task);
3161         }
3162
3163 out_unlock:
3164         rtnl_unlock();
3165 }
3166
3167 static void rtl8169_tx_timeout(struct net_device *dev)
3168 {
3169         struct rtl8169_private *tp = netdev_priv(dev);
3170
3171         rtl8169_hw_reset(tp->mmio_addr);
3172
3173         /* Let's wait a bit while any (async) irq lands on */
3174         rtl8169_schedule_work(dev, rtl8169_reset_task);
3175 }
3176
3177 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
3178                               u32 opts1)
3179 {
3180         struct skb_shared_info *info = skb_shinfo(skb);
3181         unsigned int cur_frag, entry;
3182         struct TxDesc * uninitialized_var(txd);
3183
3184         entry = tp->cur_tx;
3185         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
3186                 skb_frag_t *frag = info->frags + cur_frag;
3187                 dma_addr_t mapping;
3188                 u32 status, len;
3189                 void *addr;
3190
3191                 entry = (entry + 1) % NUM_TX_DESC;
3192
3193                 txd = tp->TxDescArray + entry;
3194                 len = frag->size;
3195                 addr = ((void *) page_address(frag->page)) + frag->page_offset;
3196                 mapping = pci_map_single(tp->pci_dev, addr, len, PCI_DMA_TODEVICE);
3197
3198                 /* anti gcc 2.95.3 bugware (sic) */
3199                 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
3200
3201                 txd->opts1 = cpu_to_le32(status);
3202                 txd->addr = cpu_to_le64(mapping);
3203
3204                 tp->tx_skb[entry].len = len;
3205         }
3206
3207         if (cur_frag) {
3208                 tp->tx_skb[entry].skb = skb;
3209                 txd->opts1 |= cpu_to_le32(LastFrag);
3210         }
3211
3212         return cur_frag;
3213 }
3214
3215 static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
3216 {
3217         if (dev->features & NETIF_F_TSO) {
3218                 u32 mss = skb_shinfo(skb)->gso_size;
3219
3220                 if (mss)
3221                         return LargeSend | ((mss & MSSMask) << MSSShift);
3222         }
3223         if (skb->ip_summed == CHECKSUM_PARTIAL) {
3224                 const struct iphdr *ip = ip_hdr(skb);
3225
3226                 if (ip->protocol == IPPROTO_TCP)
3227                         return IPCS | TCPCS;
3228                 else if (ip->protocol == IPPROTO_UDP)
3229                         return IPCS | UDPCS;
3230                 WARN_ON(1);     /* we need a WARN() */
3231         }
3232         return 0;
3233 }
3234
3235 static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev)
3236 {
3237         struct rtl8169_private *tp = netdev_priv(dev);
3238         unsigned int frags, entry = tp->cur_tx % NUM_TX_DESC;
3239         struct TxDesc *txd = tp->TxDescArray + entry;
3240         void __iomem *ioaddr = tp->mmio_addr;
3241         dma_addr_t mapping;
3242         u32 status, len;
3243         u32 opts1;
3244         int ret = NETDEV_TX_OK;
3245
3246         if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
3247                 if (netif_msg_drv(tp)) {
3248                         printk(KERN_ERR
3249                                "%s: BUG! Tx Ring full when queue awake!\n",
3250                                dev->name);
3251                 }
3252                 goto err_stop;
3253         }
3254
3255         if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
3256                 goto err_stop;
3257
3258         opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
3259
3260         frags = rtl8169_xmit_frags(tp, skb, opts1);
3261         if (frags) {
3262                 len = skb_headlen(skb);
3263                 opts1 |= FirstFrag;
3264         } else {
3265                 len = skb->len;
3266                 opts1 |= FirstFrag | LastFrag;
3267                 tp->tx_skb[entry].skb = skb;
3268         }
3269
3270         mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
3271
3272         tp->tx_skb[entry].len = len;
3273         txd->addr = cpu_to_le64(mapping);
3274         txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
3275
3276         wmb();
3277
3278         /* anti gcc 2.95.3 bugware (sic) */
3279         status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
3280         txd->opts1 = cpu_to_le32(status);
3281
3282         dev->trans_start = jiffies;
3283
3284         tp->cur_tx += frags + 1;
3285
3286         smp_wmb();
3287
3288         RTL_W8(TxPoll, NPQ);    /* set polling bit */
3289
3290         if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
3291                 netif_stop_queue(dev);
3292                 smp_rmb();
3293                 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
3294                         netif_wake_queue(dev);
3295         }
3296
3297 out:
3298         return ret;
3299
3300 err_stop:
3301         netif_stop_queue(dev);
3302         ret = NETDEV_TX_BUSY;
3303         dev->stats.tx_dropped++;
3304         goto out;
3305 }
3306
3307 static void rtl8169_pcierr_interrupt(struct net_device *dev)
3308 {
3309         struct rtl8169_private *tp = netdev_priv(dev);
3310         struct pci_dev *pdev = tp->pci_dev;
3311         void __iomem *ioaddr = tp->mmio_addr;
3312         u16 pci_status, pci_cmd;
3313
3314         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
3315         pci_read_config_word(pdev, PCI_STATUS, &pci_status);
3316
3317         if (netif_msg_intr(tp)) {
3318                 printk(KERN_ERR
3319                        "%s: PCI error (cmd = 0x%04x, status = 0x%04x).\n",
3320                        dev->name, pci_cmd, pci_status);
3321         }
3322
3323         /*
3324          * The recovery sequence below admits a very elaborated explanation:
3325          * - it seems to work;
3326          * - I did not see what else could be done;
3327          * - it makes iop3xx happy.
3328          *
3329          * Feel free to adjust to your needs.
3330          */
3331         if (pdev->broken_parity_status)
3332                 pci_cmd &= ~PCI_COMMAND_PARITY;
3333         else
3334                 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
3335
3336         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
3337
3338         pci_write_config_word(pdev, PCI_STATUS,
3339                 pci_status & (PCI_STATUS_DETECTED_PARITY |
3340                 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
3341                 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
3342
3343         /* The infamous DAC f*ckup only happens at boot time */
3344         if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
3345                 if (netif_msg_intr(tp))
3346                         printk(KERN_INFO "%s: disabling PCI DAC.\n", dev->name);
3347                 tp->cp_cmd &= ~PCIDAC;
3348                 RTL_W16(CPlusCmd, tp->cp_cmd);
3349                 dev->features &= ~NETIF_F_HIGHDMA;
3350         }
3351
3352         rtl8169_hw_reset(ioaddr);
3353
3354         rtl8169_schedule_work(dev, rtl8169_reinit_task);
3355 }
3356
3357 static void rtl8169_tx_interrupt(struct net_device *dev,
3358                                  struct rtl8169_private *tp,
3359                                  void __iomem *ioaddr)
3360 {
3361         unsigned int dirty_tx, tx_left;
3362
3363         dirty_tx = tp->dirty_tx;
3364         smp_rmb();
3365         tx_left = tp->cur_tx - dirty_tx;
3366
3367         while (tx_left > 0) {
3368                 unsigned int entry = dirty_tx % NUM_TX_DESC;
3369                 struct ring_info *tx_skb = tp->tx_skb + entry;
3370                 u32 len = tx_skb->len;
3371                 u32 status;
3372
3373                 rmb();
3374                 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
3375                 if (status & DescOwn)
3376                         break;
3377
3378                 dev->stats.tx_bytes += len;
3379                 dev->stats.tx_packets++;
3380
3381                 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, tp->TxDescArray + entry);
3382
3383                 if (status & LastFrag) {
3384                         dev_kfree_skb_irq(tx_skb->skb);
3385                         tx_skb->skb = NULL;
3386                 }
3387                 dirty_tx++;
3388                 tx_left--;
3389         }
3390
3391         if (tp->dirty_tx != dirty_tx) {
3392                 tp->dirty_tx = dirty_tx;
3393                 smp_wmb();
3394                 if (netif_queue_stopped(dev) &&
3395                     (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
3396                         netif_wake_queue(dev);
3397                 }
3398                 /*
3399                  * 8168 hack: TxPoll requests are lost when the Tx packets are
3400                  * too close. Let's kick an extra TxPoll request when a burst
3401                  * of start_xmit activity is detected (if it is not detected,
3402                  * it is slow enough). -- FR
3403                  */
3404                 smp_rmb();
3405                 if (tp->cur_tx != dirty_tx)
3406                         RTL_W8(TxPoll, NPQ);
3407         }
3408 }
3409
3410 static inline int rtl8169_fragmented_frame(u32 status)
3411 {
3412         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
3413 }
3414
3415 static inline void rtl8169_rx_csum(struct sk_buff *skb, struct RxDesc *desc)
3416 {
3417         u32 opts1 = le32_to_cpu(desc->opts1);
3418         u32 status = opts1 & RxProtoMask;
3419
3420         if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
3421             ((status == RxProtoUDP) && !(opts1 & UDPFail)) ||
3422             ((status == RxProtoIP) && !(opts1 & IPFail)))
3423                 skb->ip_summed = CHECKSUM_UNNECESSARY;
3424         else
3425                 skb->ip_summed = CHECKSUM_NONE;
3426 }
3427
3428 static inline bool rtl8169_try_rx_copy(struct sk_buff **sk_buff,
3429                                        struct rtl8169_private *tp, int pkt_size,
3430                                        dma_addr_t addr)
3431 {
3432         struct sk_buff *skb;
3433         bool done = false;
3434
3435         if (pkt_size >= rx_copybreak)
3436                 goto out;
3437
3438         skb = netdev_alloc_skb(tp->dev, pkt_size + NET_IP_ALIGN);
3439         if (!skb)
3440                 goto out;
3441
3442         pci_dma_sync_single_for_cpu(tp->pci_dev, addr, pkt_size,
3443                                     PCI_DMA_FROMDEVICE);
3444         skb_reserve(skb, NET_IP_ALIGN);
3445         skb_copy_from_linear_data(*sk_buff, skb->data, pkt_size);
3446         *sk_buff = skb;
3447         done = true;
3448 out:
3449         return done;
3450 }
3451
3452 static int rtl8169_rx_interrupt(struct net_device *dev,
3453                                 struct rtl8169_private *tp,
3454                                 void __iomem *ioaddr, u32 budget)
3455 {
3456         unsigned int cur_rx, rx_left;
3457         unsigned int delta, count;
3458
3459         cur_rx = tp->cur_rx;
3460         rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
3461         rx_left = min(rx_left, budget);
3462
3463         for (; rx_left > 0; rx_left--, cur_rx++) {
3464                 unsigned int entry = cur_rx % NUM_RX_DESC;
3465                 struct RxDesc *desc = tp->RxDescArray + entry;
3466                 u32 status;
3467
3468                 rmb();
3469                 status = le32_to_cpu(desc->opts1);
3470
3471                 if (status & DescOwn)
3472                         break;
3473                 if (unlikely(status & RxRES)) {
3474                         if (netif_msg_rx_err(tp)) {
3475                                 printk(KERN_INFO
3476                                        "%s: Rx ERROR. status = %08x\n",
3477                                        dev->name, status);
3478                         }
3479                         dev->stats.rx_errors++;
3480                         if (status & (RxRWT | RxRUNT))
3481                                 dev->stats.rx_length_errors++;
3482                         if (status & RxCRC)
3483                                 dev->stats.rx_crc_errors++;
3484                         if (status & RxFOVF) {
3485                                 rtl8169_schedule_work(dev, rtl8169_reset_task);
3486                                 dev->stats.rx_fifo_errors++;
3487                         }
3488                         rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
3489                 } else {
3490                         struct sk_buff *skb = tp->Rx_skbuff[entry];
3491                         dma_addr_t addr = le64_to_cpu(desc->addr);
3492                         int pkt_size = (status & 0x00001FFF) - 4;
3493                         struct pci_dev *pdev = tp->pci_dev;
3494
3495                         /*
3496                          * The driver does not support incoming fragmented
3497                          * frames. They are seen as a symptom of over-mtu
3498                          * sized frames.
3499                          */
3500                         if (unlikely(rtl8169_fragmented_frame(status))) {
3501                                 dev->stats.rx_dropped++;
3502                                 dev->stats.rx_length_errors++;
3503                                 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
3504                                 continue;
3505                         }
3506
3507                         rtl8169_rx_csum(skb, desc);
3508
3509                         if (rtl8169_try_rx_copy(&skb, tp, pkt_size, addr)) {
3510                                 pci_dma_sync_single_for_device(pdev, addr,
3511                                         pkt_size, PCI_DMA_FROMDEVICE);
3512                                 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
3513                         } else {
3514                                 pci_unmap_single(pdev, addr, tp->rx_buf_sz,
3515                                                  PCI_DMA_FROMDEVICE);
3516                                 tp->Rx_skbuff[entry] = NULL;
3517                         }
3518
3519                         skb_put(skb, pkt_size);
3520                         skb->protocol = eth_type_trans(skb, dev);
3521
3522                         if (rtl8169_rx_vlan_skb(tp, desc, skb) < 0)
3523                                 netif_receive_skb(skb);
3524
3525                         dev->stats.rx_bytes += pkt_size;
3526                         dev->stats.rx_packets++;
3527                 }
3528
3529                 /* Work around for AMD plateform. */
3530                 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
3531                     (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
3532                         desc->opts2 = 0;
3533                         cur_rx++;
3534                 }
3535         }
3536
3537         count = cur_rx - tp->cur_rx;
3538         tp->cur_rx = cur_rx;
3539
3540         delta = rtl8169_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx);
3541         if (!delta && count && netif_msg_intr(tp))
3542                 printk(KERN_INFO "%s: no Rx buffer allocated\n", dev->name);
3543         tp->dirty_rx += delta;
3544
3545         /*
3546          * FIXME: until there is periodic timer to try and refill the ring,
3547          * a temporary shortage may definitely kill the Rx process.
3548          * - disable the asic to try and avoid an overflow and kick it again
3549          *   after refill ?
3550          * - how do others driver handle this condition (Uh oh...).
3551          */
3552         if ((tp->dirty_rx + NUM_RX_DESC == tp->cur_rx) && netif_msg_intr(tp))
3553                 printk(KERN_EMERG "%s: Rx buffers exhausted\n", dev->name);
3554
3555         return count;
3556 }
3557
3558 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
3559 {
3560         struct net_device *dev = dev_instance;
3561         struct rtl8169_private *tp = netdev_priv(dev);
3562         void __iomem *ioaddr = tp->mmio_addr;
3563         int handled = 0;
3564         int status;
3565
3566         status = RTL_R16(IntrStatus);
3567
3568         /* hotplug/major error/no more work/shared irq */
3569         if ((status == 0xffff) || !status)
3570                 goto out;
3571
3572         handled = 1;
3573
3574         if (unlikely(!netif_running(dev))) {
3575                 rtl8169_asic_down(ioaddr);
3576                 goto out;
3577         }
3578
3579         status &= tp->intr_mask;
3580         RTL_W16(IntrStatus,
3581                 (status & RxFIFOOver) ? (status | RxOverflow) : status);
3582
3583         if (!(status & tp->intr_event))
3584                 goto out;
3585
3586         /* Work around for rx fifo overflow */
3587         if (unlikely(status & RxFIFOOver) &&
3588             (tp->mac_version == RTL_GIGA_MAC_VER_11)) {
3589                 netif_stop_queue(dev);
3590                 rtl8169_tx_timeout(dev);
3591                 goto out;
3592         }
3593
3594         if (unlikely(status & SYSErr)) {
3595                 rtl8169_pcierr_interrupt(dev);
3596                 goto out;
3597         }
3598
3599         if (status & LinkChg)
3600                 rtl8169_check_link_status(dev, tp, ioaddr);
3601
3602         if (status & tp->napi_event) {
3603                 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
3604                 tp->intr_mask = ~tp->napi_event;
3605
3606                 if (likely(napi_schedule_prep(&tp->napi)))
3607                         __napi_schedule(&tp->napi);
3608                 else if (netif_msg_intr(tp)) {
3609                         printk(KERN_INFO "%s: interrupt %04x in poll\n",
3610                                dev->name, status);
3611                 }
3612         }
3613 out:
3614         return IRQ_RETVAL(handled);
3615 }
3616
3617 static int rtl8169_poll(struct napi_struct *napi, int budget)
3618 {
3619         struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
3620         struct net_device *dev = tp->dev;
3621         void __iomem *ioaddr = tp->mmio_addr;
3622         int work_done;
3623
3624         work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
3625         rtl8169_tx_interrupt(dev, tp, ioaddr);
3626
3627         if (work_done < budget) {
3628                 napi_complete(napi);
3629                 tp->intr_mask = 0xffff;
3630                 /*
3631                  * 20040426: the barrier is not strictly required but the
3632                  * behavior of the irq handler could be less predictable
3633                  * without it. Btw, the lack of flush for the posted pci
3634                  * write is safe - FR
3635                  */
3636                 smp_wmb();
3637                 RTL_W16(IntrMask, tp->intr_event);
3638         }
3639
3640         return work_done;
3641 }
3642
3643 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
3644 {
3645         struct rtl8169_private *tp = netdev_priv(dev);
3646
3647         if (tp->mac_version > RTL_GIGA_MAC_VER_06)
3648                 return;
3649
3650         dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
3651         RTL_W32(RxMissed, 0);
3652 }
3653
3654 static void rtl8169_down(struct net_device *dev)
3655 {
3656         struct rtl8169_private *tp = netdev_priv(dev);
3657         void __iomem *ioaddr = tp->mmio_addr;
3658         unsigned int intrmask;
3659
3660         rtl8169_delete_timer(dev);
3661
3662         netif_stop_queue(dev);
3663
3664         napi_disable(&tp->napi);
3665
3666 core_down:
3667         spin_lock_irq(&tp->lock);
3668
3669         rtl8169_asic_down(ioaddr);
3670
3671         rtl8169_rx_missed(dev, ioaddr);
3672
3673         spin_unlock_irq(&tp->lock);
3674
3675         synchronize_irq(dev->irq);
3676
3677         /* Give a racing hard_start_xmit a few cycles to complete. */
3678         synchronize_sched();  /* FIXME: should this be synchronize_irq()? */
3679
3680         /*
3681          * And now for the 50k$ question: are IRQ disabled or not ?
3682          *
3683          * Two paths lead here:
3684          * 1) dev->close
3685          *    -> netif_running() is available to sync the current code and the
3686          *       IRQ handler. See rtl8169_interrupt for details.
3687          * 2) dev->change_mtu
3688          *    -> rtl8169_poll can not be issued again and re-enable the
3689          *       interruptions. Let's simply issue the IRQ down sequence again.
3690          *
3691          * No loop if hotpluged or major error (0xffff).
3692          */
3693         intrmask = RTL_R16(IntrMask);
3694         if (intrmask && (intrmask != 0xffff))
3695                 goto core_down;
3696
3697         rtl8169_tx_clear(tp);
3698
3699         rtl8169_rx_clear(tp);
3700 }
3701
3702 static int rtl8169_close(struct net_device *dev)
3703 {
3704         struct rtl8169_private *tp = netdev_priv(dev);
3705         struct pci_dev *pdev = tp->pci_dev;
3706
3707         /* update counters before going down */
3708         rtl8169_update_counters(dev);
3709
3710         rtl8169_down(dev);
3711
3712         free_irq(dev->irq, dev);
3713
3714         pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
3715                             tp->RxPhyAddr);
3716         pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
3717                             tp->TxPhyAddr);
3718         tp->TxDescArray = NULL;
3719         tp->RxDescArray = NULL;
3720
3721         return 0;
3722 }
3723
3724 static void rtl_set_rx_mode(struct net_device *dev)
3725 {
3726         struct rtl8169_private *tp = netdev_priv(dev);
3727         void __iomem *ioaddr = tp->mmio_addr;
3728         unsigned long flags;
3729         u32 mc_filter[2];       /* Multicast hash filter */
3730         int rx_mode;
3731         u32 tmp = 0;
3732
3733         if (dev->flags & IFF_PROMISC) {
3734                 /* Unconditionally log net taps. */
3735                 if (netif_msg_link(tp)) {
3736                         printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n",
3737                                dev->name);
3738                 }
3739                 rx_mode =
3740                     AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
3741                     AcceptAllPhys;
3742                 mc_filter[1] = mc_filter[0] = 0xffffffff;
3743         } else if ((dev->mc_count > multicast_filter_limit)
3744                    || (dev->flags & IFF_ALLMULTI)) {
3745                 /* Too many to filter perfectly -- accept all multicasts. */
3746                 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
3747                 mc_filter[1] = mc_filter[0] = 0xffffffff;
3748         } else {
3749                 struct dev_mc_list *mclist;
3750                 unsigned int i;
3751
3752                 rx_mode = AcceptBroadcast | AcceptMyPhys;
3753                 mc_filter[1] = mc_filter[0] = 0;
3754                 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
3755                      i++, mclist = mclist->next) {
3756                         int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
3757                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
3758                         rx_mode |= AcceptMulticast;
3759                 }
3760         }
3761
3762         spin_lock_irqsave(&tp->lock, flags);
3763
3764         tmp = rtl8169_rx_config | rx_mode |
3765               (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
3766
3767         if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
3768                 u32 data = mc_filter[0];
3769
3770                 mc_filter[0] = swab32(mc_filter[1]);
3771                 mc_filter[1] = swab32(data);
3772         }
3773
3774         RTL_W32(MAR0 + 0, mc_filter[0]);
3775         RTL_W32(MAR0 + 4, mc_filter[1]);
3776
3777         RTL_W32(RxConfig, tmp);
3778
3779         spin_unlock_irqrestore(&tp->lock, flags);
3780 }
3781
3782 /**
3783  *  rtl8169_get_stats - Get rtl8169 read/write statistics
3784  *  @dev: The Ethernet Device to get statistics for
3785  *
3786  *  Get TX/RX statistics for rtl8169
3787  */
3788 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
3789 {
3790         struct rtl8169_private *tp = netdev_priv(dev);
3791         void __iomem *ioaddr = tp->mmio_addr;
3792         unsigned long flags;
3793
3794         if (netif_running(dev)) {
3795                 spin_lock_irqsave(&tp->lock, flags);
3796                 rtl8169_rx_missed(dev, ioaddr);
3797                 spin_unlock_irqrestore(&tp->lock, flags);
3798         }
3799
3800         return &dev->stats;
3801 }
3802
3803 static void rtl8169_net_suspend(struct net_device *dev)
3804 {
3805         struct rtl8169_private *tp = netdev_priv(dev);
3806         void __iomem *ioaddr = tp->mmio_addr;
3807
3808         if (!netif_running(dev))
3809                 return;
3810
3811         netif_device_detach(dev);
3812         netif_stop_queue(dev);
3813
3814         spin_lock_irq(&tp->lock);
3815
3816         rtl8169_asic_down(ioaddr);
3817
3818         rtl8169_rx_missed(dev, ioaddr);
3819
3820         spin_unlock_irq(&tp->lock);
3821 }
3822
3823 #ifdef CONFIG_PM
3824
3825 static int rtl8169_suspend(struct device *device)
3826 {
3827         struct pci_dev *pdev = to_pci_dev(device);
3828         struct net_device *dev = pci_get_drvdata(pdev);
3829
3830         rtl8169_net_suspend(dev);
3831
3832         return 0;
3833 }
3834
3835 static int rtl8169_resume(struct device *device)
3836 {
3837         struct pci_dev *pdev = to_pci_dev(device);
3838         struct net_device *dev = pci_get_drvdata(pdev);
3839
3840         if (!netif_running(dev))
3841                 goto out;
3842
3843         netif_device_attach(dev);
3844
3845         rtl8169_schedule_work(dev, rtl8169_reset_task);
3846 out:
3847         return 0;
3848 }
3849
3850 static struct dev_pm_ops rtl8169_pm_ops = {
3851         .suspend = rtl8169_suspend,
3852         .resume = rtl8169_resume,
3853         .freeze = rtl8169_suspend,
3854         .thaw = rtl8169_resume,
3855         .poweroff = rtl8169_suspend,
3856         .restore = rtl8169_resume,
3857 };
3858
3859 #define RTL8169_PM_OPS  (&rtl8169_pm_ops)
3860
3861 #else /* !CONFIG_PM */
3862
3863 #define RTL8169_PM_OPS  NULL
3864
3865 #endif /* !CONFIG_PM */
3866
3867 static void rtl_shutdown(struct pci_dev *pdev)
3868 {
3869         struct net_device *dev = pci_get_drvdata(pdev);
3870
3871         rtl8169_net_suspend(dev);
3872
3873         if (system_state == SYSTEM_POWER_OFF) {
3874                 pci_wake_from_d3(pdev, true);
3875                 pci_set_power_state(pdev, PCI_D3hot);
3876         }
3877 }
3878
3879 static struct pci_driver rtl8169_pci_driver = {
3880         .name           = MODULENAME,
3881         .id_table       = rtl8169_pci_tbl,
3882         .probe          = rtl8169_init_one,
3883         .remove         = __devexit_p(rtl8169_remove_one),
3884         .shutdown       = rtl_shutdown,
3885         .driver.pm      = RTL8169_PM_OPS,
3886 };
3887
3888 static int __init rtl8169_init_module(void)
3889 {
3890         return pci_register_driver(&rtl8169_pci_driver);
3891 }
3892
3893 static void __exit rtl8169_cleanup_module(void)
3894 {
3895         pci_unregister_driver(&rtl8169_pci_driver);
3896 }
3897
3898 module_init(rtl8169_init_module);
3899 module_exit(rtl8169_cleanup_module);