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   1 /*
   2  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
   3  *
   4  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
   5  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
   6  * Copyright (c) a lot of people too. Please respect their work.
   7  *
   8  * See MAINTAINERS file for support contact information.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/moduleparam.h>
  13 #include <linux/pci.h>
  14 #include <linux/netdevice.h>
  15 #include <linux/etherdevice.h>
  16 #include <linux/delay.h>
  17 #include <linux/ethtool.h>
  18 #include <linux/mii.h>
  19 #include <linux/if_vlan.h>
  20 #include <linux/crc32.h>
  21 #include <linux/in.h>
  22 #include <linux/ip.h>
  23 #include <linux/tcp.h>
  24 #include <linux/init.h>
  25 #include <linux/dma-mapping.h>
  26
  27 #include <asm/system.h>
  28 #include <asm/io.h>
  29 #include <asm/irq.h>
  30
  31 #define RTL8169_VERSION "2.3LK-NAPI"
  32 #define MODULENAME "r8169"
  33 #define PFX MODULENAME ": "
  34
  35 #ifdef RTL8169_DEBUG
  36 #define assert(expr) \
  37         if (!(expr)) {                                  \
  38                 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
  39                 #expr,__FILE__,__func__,__LINE__);              \
  40         }
  41 #define dprintk(fmt, args...) \
  42         do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
  43 #else
  44 #define assert(expr) do {} while (0)
  45 #define dprintk(fmt, args...)   do {} while (0)
  46 #endif /* RTL8169_DEBUG */
  47
  48 #define R8169_MSG_DEFAULT \
  49         (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
  50
  51 #define TX_BUFFS_AVAIL(tp) \
  52         (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
  53
  54 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
  55 static const int max_interrupt_work = 20;
  56
  57 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  58    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
  59 static const int multicast_filter_limit = 32;
  60
  61 /* MAC address length */
  62 #define MAC_ADDR_LEN    6
  63
  64 #define MAX_READ_REQUEST_SHIFT  12
  65 #define RX_FIFO_THRESH  7       /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
  66 #define RX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
  67 #define TX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
  68 #define EarlyTxThld     0x3F    /* 0x3F means NO early transmit */
  69 #define RxPacketMaxSize 0x3FE8  /* 16K - 1 - ETH_HLEN - VLAN - CRC... */
  70 #define SafeMtu         0x1c20  /* ... actually life sucks beyond ~7k */
  71 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
  72
  73 #define R8169_REGS_SIZE         256
  74 #define R8169_NAPI_WEIGHT       64
  75 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
  76 #define NUM_RX_DESC     256     /* Number of Rx descriptor registers */
  77 #define RX_BUF_SIZE     1536    /* Rx Buffer size */
  78 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
  79 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
  80
  81 #define RTL8169_TX_TIMEOUT      (6*HZ)
  82 #define RTL8169_PHY_TIMEOUT     (10*HZ)
  83
  84 /* write/read MMIO register */
  85 #define RTL_W8(reg, val8)       writeb ((val8), ioaddr + (reg))
  86 #define RTL_W16(reg, val16)     writew ((val16), ioaddr + (reg))
  87 #define RTL_W32(reg, val32)     writel ((val32), ioaddr + (reg))
  88 #define RTL_R8(reg)             readb (ioaddr + (reg))
  89 #define RTL_R16(reg)            readw (ioaddr + (reg))
  90 #define RTL_R32(reg)            ((unsigned long) readl (ioaddr + (reg)))
  91
  92 enum mac_version {
  93         RTL_GIGA_MAC_VER_01 = 0x01, // 8169
  94         RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
  95         RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
  96         RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
  97         RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
  98         RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
  99         RTL_GIGA_MAC_VER_07 = 0x07, // 8102e
 100         RTL_GIGA_MAC_VER_08 = 0x08, // 8102e
 101         RTL_GIGA_MAC_VER_09 = 0x09, // 8102e
 102         RTL_GIGA_MAC_VER_10 = 0x0a, // 8101e
 103         RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
 104         RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be
 105         RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb
 106         RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ?
 107         RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ?
 108         RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec
 109         RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf
 110         RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP
 111         RTL_GIGA_MAC_VER_19 = 0x13, // 8168C
 112         RTL_GIGA_MAC_VER_20 = 0x14, // 8168C
 113         RTL_GIGA_MAC_VER_21 = 0x15, // 8168C
 114         RTL_GIGA_MAC_VER_22 = 0x16, // 8168C
 115         RTL_GIGA_MAC_VER_23 = 0x17, // 8168CP
 116         RTL_GIGA_MAC_VER_24 = 0x18  // 8168CP
 117 };
 118
 119 #define _R(NAME,MAC,MASK) \
 120         { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
 121
 122 static const struct {
 123         const char *name;
 124         u8 mac_version;
 125         u32 RxConfigMask;       /* Clears the bits supported by this chip */
 126 } rtl_chip_info[] = {
 127         _R("RTL8169",           RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
 128         _R("RTL8169s",          RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
 129         _R("RTL8110s",          RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
 130         _R("RTL8169sb/8110sb",  RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
 131         _R("RTL8169sc/8110sc",  RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
 132         _R("RTL8169sc/8110sc",  RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
 133         _R("RTL8102e",          RTL_GIGA_MAC_VER_07, 0xff7e1880), // PCI-E
 134         _R("RTL8102e",          RTL_GIGA_MAC_VER_08, 0xff7e1880), // PCI-E
 135         _R("RTL8102e",          RTL_GIGA_MAC_VER_09, 0xff7e1880), // PCI-E
 136         _R("RTL8101e",          RTL_GIGA_MAC_VER_10, 0xff7e1880), // PCI-E
 137         _R("RTL8168b/8111b",    RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
 138         _R("RTL8168b/8111b",    RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
 139         _R("RTL8101e",          RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
 140         _R("RTL8100e",          RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
 141         _R("RTL8100e",          RTL_GIGA_MAC_VER_15, 0xff7e1880), // PCI-E 8139
 142         _R("RTL8168b/8111b",    RTL_GIGA_MAC_VER_17, 0xff7e1880), // PCI-E
 143         _R("RTL8101e",          RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E
 144         _R("RTL8168cp/8111cp",  RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E
 145         _R("RTL8168c/8111c",    RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E
 146         _R("RTL8168c/8111c",    RTL_GIGA_MAC_VER_20, 0xff7e1880), // PCI-E
 147         _R("RTL8168c/8111c",    RTL_GIGA_MAC_VER_21, 0xff7e1880), // PCI-E
 148         _R("RTL8168c/8111c",    RTL_GIGA_MAC_VER_22, 0xff7e1880), // PCI-E
 149         _R("RTL8168cp/8111cp",  RTL_GIGA_MAC_VER_23, 0xff7e1880), // PCI-E
 150         _R("RTL8168cp/8111cp",  RTL_GIGA_MAC_VER_24, 0xff7e1880)  // PCI-E
 151 };
 152 #undef _R
 153
 154 enum cfg_version {
 155         RTL_CFG_0 = 0x00,
 156         RTL_CFG_1,
 157         RTL_CFG_2
 158 };
 159
 160 static void rtl_hw_start_8169(struct net_device *);
 161 static void rtl_hw_start_8168(struct net_device *);
 162 static void rtl_hw_start_8101(struct net_device *);
 163
 164 static struct pci_device_id rtl8169_pci_tbl[] = {
 165         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8129), 0, 0, RTL_CFG_0 },
 166         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8136), 0, 0, RTL_CFG_2 },
 167         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8167), 0, 0, RTL_CFG_0 },
 168         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8168), 0, 0, RTL_CFG_1 },
 169         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8169), 0, 0, RTL_CFG_0 },
 170         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4300), 0, 0, RTL_CFG_0 },
 171         { PCI_DEVICE(PCI_VENDOR_ID_AT,          0xc107), 0, 0, RTL_CFG_0 },
 172         { PCI_DEVICE(0x16ec,                    0x0116), 0, 0, RTL_CFG_0 },
 173         { PCI_VENDOR_ID_LINKSYS,                0x1032,
 174                 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
 175         { 0x0001,                               0x8168,
 176                 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
 177         {0,},
 178 };
 179
 180 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
 181
 182 static int rx_copybreak = 200;
 183 static int use_dac;
 184 static struct {
 185         u32 msg_enable;
 186 } debug = { -1 };
 187
 188 enum rtl_registers {
 189         MAC0            = 0,    /* Ethernet hardware address. */
 190         MAC4            = 4,
 191         MAR0            = 8,    /* Multicast filter. */
 192         CounterAddrLow          = 0x10,
 193         CounterAddrHigh         = 0x14,
 194         TxDescStartAddrLow      = 0x20,
 195         TxDescStartAddrHigh     = 0x24,
 196         TxHDescStartAddrLow     = 0x28,
 197         TxHDescStartAddrHigh    = 0x2c,
 198         FLASH           = 0x30,
 199         ERSR            = 0x36,
 200         ChipCmd         = 0x37,
 201         TxPoll          = 0x38,
 202         IntrMask        = 0x3c,
 203         IntrStatus      = 0x3e,
 204         TxConfig        = 0x40,
 205         RxConfig        = 0x44,
 206         RxMissed        = 0x4c,
 207         Cfg9346         = 0x50,
 208         Config0         = 0x51,
 209         Config1         = 0x52,
 210         Config2         = 0x53,
 211         Config3         = 0x54,
 212         Config4         = 0x55,
 213         Config5         = 0x56,
 214         MultiIntr       = 0x5c,
 215         PHYAR           = 0x60,
 216         PHYstatus       = 0x6c,
 217         RxMaxSize       = 0xda,
 218         CPlusCmd        = 0xe0,
 219         IntrMitigate    = 0xe2,
 220         RxDescAddrLow   = 0xe4,
 221         RxDescAddrHigh  = 0xe8,
 222         EarlyTxThres    = 0xec,
 223         FuncEvent       = 0xf0,
 224         FuncEventMask   = 0xf4,
 225         FuncPresetState = 0xf8,
 226         FuncForceEvent  = 0xfc,
 227 };
 228
 229 enum rtl8110_registers {
 230         TBICSR                  = 0x64,
 231         TBI_ANAR                = 0x68,
 232         TBI_LPAR                = 0x6a,
 233 };
 234
 235 enum rtl8168_8101_registers {
 236         CSIDR                   = 0x64,
 237         CSIAR                   = 0x68,
 238 #define CSIAR_FLAG                      0x80000000
 239 #define CSIAR_WRITE_CMD                 0x80000000
 240 #define CSIAR_BYTE_ENABLE               0x0f
 241 #define CSIAR_BYTE_ENABLE_SHIFT         12
 242 #define CSIAR_ADDR_MASK                 0x0fff
 243
 244         EPHYAR                  = 0x80,
 245 #define EPHYAR_FLAG                     0x80000000
 246 #define EPHYAR_WRITE_CMD                0x80000000
 247 #define EPHYAR_REG_MASK                 0x1f
 248 #define EPHYAR_REG_SHIFT                16
 249 #define EPHYAR_DATA_MASK                0xffff
 250         DBG_REG                 = 0xd1,
 251 #define FIX_NAK_1                       (1 << 4)
 252 #define FIX_NAK_2                       (1 << 3)
 253 };
 254
 255 enum rtl_register_content {
 256         /* InterruptStatusBits */
 257         SYSErr          = 0x8000,
 258         PCSTimeout      = 0x4000,
 259         SWInt           = 0x0100,
 260         TxDescUnavail   = 0x0080,
 261         RxFIFOOver      = 0x0040,
 262         LinkChg         = 0x0020,
 263         RxOverflow      = 0x0010,
 264         TxErr           = 0x0008,
 265         TxOK            = 0x0004,
 266         RxErr           = 0x0002,
 267         RxOK            = 0x0001,
 268
 269         /* RxStatusDesc */
 270         RxFOVF  = (1 << 23),
 271         RxRWT   = (1 << 22),
 272         RxRES   = (1 << 21),
 273         RxRUNT  = (1 << 20),
 274         RxCRC   = (1 << 19),
 275
 276         /* ChipCmdBits */
 277         CmdReset        = 0x10,
 278         CmdRxEnb        = 0x08,
 279         CmdTxEnb        = 0x04,
 280         RxBufEmpty      = 0x01,
 281
 282         /* TXPoll register p.5 */
 283         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
 284         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
 285         FSWInt          = 0x01,         /* Forced software interrupt */
 286
 287         /* Cfg9346Bits */
 288         Cfg9346_Lock    = 0x00,
 289         Cfg9346_Unlock  = 0xc0,
 290
 291         /* rx_mode_bits */
 292         AcceptErr       = 0x20,
 293         AcceptRunt      = 0x10,
 294         AcceptBroadcast = 0x08,
 295         AcceptMulticast = 0x04,
 296         AcceptMyPhys    = 0x02,
 297         AcceptAllPhys   = 0x01,
 298
 299         /* RxConfigBits */
 300         RxCfgFIFOShift  = 13,
 301         RxCfgDMAShift   =  8,
 302
 303         /* TxConfigBits */
 304         TxInterFrameGapShift = 24,
 305         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
 306
 307         /* Config1 register p.24 */
 308         LEDS1           = (1 << 7),
 309         LEDS0           = (1 << 6),
 310         MSIEnable       = (1 << 5),     /* Enable Message Signaled Interrupt */
 311         Speed_down      = (1 << 4),
 312         MEMMAP          = (1 << 3),
 313         IOMAP           = (1 << 2),
 314         VPD             = (1 << 1),
 315         PMEnable        = (1 << 0),     /* Power Management Enable */
 316
 317         /* Config2 register p. 25 */
 318         PCI_Clock_66MHz = 0x01,
 319         PCI_Clock_33MHz = 0x00,
 320
 321         /* Config3 register p.25 */
 322         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
 323         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
 324         Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
 325
 326         /* Config5 register p.27 */
 327         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
 328         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
 329         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
 330         LanWake         = (1 << 1),     /* LanWake enable/disable */
 331         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
 332
 333         /* TBICSR p.28 */
 334         TBIReset        = 0x80000000,
 335         TBILoopback     = 0x40000000,
 336         TBINwEnable     = 0x20000000,
 337         TBINwRestart    = 0x10000000,
 338         TBILinkOk       = 0x02000000,
 339         TBINwComplete   = 0x01000000,
 340
 341         /* CPlusCmd p.31 */
 342         EnableBist      = (1 << 15),    // 8168 8101
 343         Mac_dbgo_oe     = (1 << 14),    // 8168 8101
 344         Normal_mode     = (1 << 13),    // unused
 345         Force_half_dup  = (1 << 12),    // 8168 8101
 346         Force_rxflow_en = (1 << 11),    // 8168 8101
 347         Force_txflow_en = (1 << 10),    // 8168 8101
 348         Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
 349         ASF             = (1 << 8),     // 8168 8101
 350         PktCntrDisable  = (1 << 7),     // 8168 8101
 351         Mac_dbgo_sel    = 0x001c,       // 8168
 352         RxVlan          = (1 << 6),
 353         RxChkSum        = (1 << 5),
 354         PCIDAC          = (1 << 4),
 355         PCIMulRW        = (1 << 3),
 356         INTT_0          = 0x0000,       // 8168
 357         INTT_1          = 0x0001,       // 8168
 358         INTT_2          = 0x0002,       // 8168
 359         INTT_3          = 0x0003,       // 8168
 360
 361         /* rtl8169_PHYstatus */
 362         TBI_Enable      = 0x80,
 363         TxFlowCtrl      = 0x40,
 364         RxFlowCtrl      = 0x20,
 365         _1000bpsF       = 0x10,
 366         _100bps         = 0x08,
 367         _10bps          = 0x04,
 368         LinkStatus      = 0x02,
 369         FullDup         = 0x01,
 370
 371         /* _TBICSRBit */
 372         TBILinkOK       = 0x02000000,
 373
 374         /* DumpCounterCommand */
 375         CounterDump     = 0x8,
 376 };
 377
 378 enum desc_status_bit {
 379         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
 380         RingEnd         = (1 << 30), /* End of descriptor ring */
 381         FirstFrag       = (1 << 29), /* First segment of a packet */
 382         LastFrag        = (1 << 28), /* Final segment of a packet */
 383
 384         /* Tx private */
 385         LargeSend       = (1 << 27), /* TCP Large Send Offload (TSO) */
 386         MSSShift        = 16,        /* MSS value position */
 387         MSSMask         = 0xfff,     /* MSS value + LargeSend bit: 12 bits */
 388         IPCS            = (1 << 18), /* Calculate IP checksum */
 389         UDPCS           = (1 << 17), /* Calculate UDP/IP checksum */
 390         TCPCS           = (1 << 16), /* Calculate TCP/IP checksum */
 391         TxVlanTag       = (1 << 17), /* Add VLAN tag */
 392
 393         /* Rx private */
 394         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
 395         PID0            = (1 << 17), /* Protocol ID bit 2/2 */
 396
 397 #define RxProtoUDP      (PID1)
 398 #define RxProtoTCP      (PID0)
 399 #define RxProtoIP       (PID1 | PID0)
 400 #define RxProtoMask     RxProtoIP
 401
 402         IPFail          = (1 << 16), /* IP checksum failed */
 403         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
 404         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
 405         RxVlanTag       = (1 << 16), /* VLAN tag available */
 406 };
 407
 408 #define RsvdMask        0x3fffc000
 409
 410 struct TxDesc {
 411         __le32 opts1;
 412         __le32 opts2;
 413         __le64 addr;
 414 };
 415
 416 struct RxDesc {
 417         __le32 opts1;
 418         __le32 opts2;
 419         __le64 addr;
 420 };
 421
 422 struct ring_info {
 423         struct sk_buff  *skb;
 424         u32             len;
 425         u8              __pad[sizeof(void *) - sizeof(u32)];
 426 };
 427
 428 enum features {
 429         RTL_FEATURE_WOL         = (1 << 0),
 430         RTL_FEATURE_MSI         = (1 << 1),
 431         RTL_FEATURE_GMII        = (1 << 2),
 432 };
 433
 434 struct rtl8169_private {
 435         void __iomem *mmio_addr;        /* memory map physical address */
 436         struct pci_dev *pci_dev;        /* Index of PCI device */
 437         struct net_device *dev;
 438         struct napi_struct napi;
 439         spinlock_t lock;                /* spin lock flag */
 440         u32 msg_enable;
 441         int chipset;
 442         int mac_version;
 443         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
 444         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
 445         u32 dirty_rx;
 446         u32 dirty_tx;
 447         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
 448         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
 449         dma_addr_t TxPhyAddr;
 450         dma_addr_t RxPhyAddr;
 451         struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */
 452         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
 453         unsigned align;
 454         unsigned rx_buf_sz;
 455         struct timer_list timer;
 456         u16 cp_cmd;
 457         u16 intr_event;
 458         u16 napi_event;
 459         u16 intr_mask;
 460         int phy_auto_nego_reg;
 461         int phy_1000_ctrl_reg;
 462 #ifdef CONFIG_R8169_VLAN
 463         struct vlan_group *vlgrp;
 464 #endif
 465         int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
 466         int (*get_settings)(struct net_device *, struct ethtool_cmd *);
 467         void (*phy_reset_enable)(void __iomem *);
 468         void (*hw_start)(struct net_device *);
 469         unsigned int (*phy_reset_pending)(void __iomem *);
 470         unsigned int (*link_ok)(void __iomem *);
 471         int pcie_cap;
 472         struct delayed_work task;
 473         unsigned features;
 474
 475         struct mii_if_info mii;
 476 };
 477
 478 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
 479 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
 480 module_param(rx_copybreak, int, 0);
 481 MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
 482 module_param(use_dac, int, 0);
 483 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
 484 module_param_named(debug, debug.msg_enable, int, 0);
 485 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
 486 MODULE_LICENSE("GPL");
 487 MODULE_VERSION(RTL8169_VERSION);
 488
 489 static int rtl8169_open(struct net_device *dev);
 490 static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev);
 491 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
 492 static int rtl8169_init_ring(struct net_device *dev);
 493 static void rtl_hw_start(struct net_device *dev);
 494 static int rtl8169_close(struct net_device *dev);
 495 static void rtl_set_rx_mode(struct net_device *dev);
 496 static void rtl8169_tx_timeout(struct net_device *dev);
 497 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
 498 static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
 499                                 void __iomem *, u32 budget);
 500 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
 501 static void rtl8169_down(struct net_device *dev);
 502 static void rtl8169_rx_clear(struct rtl8169_private *tp);
 503 static int rtl8169_poll(struct napi_struct *napi, int budget);
 504
 505 static const unsigned int rtl8169_rx_config =
 506         (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
 507
 508 static void mdio_write(void __iomem *ioaddr, int reg_addr, int value)
 509 {
 510         int i;
 511
 512         RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
 513
 514         for (i = 20; i > 0; i--) {
 515                 /*
 516                  * Check if the RTL8169 has completed writing to the specified
 517                  * MII register.
 518                  */
 519                 if (!(RTL_R32(PHYAR) & 0x80000000))
 520                         break;
 521                 udelay(25);
 522         }
 523 }
 524
 525 static int mdio_read(void __iomem *ioaddr, int reg_addr)
 526 {
 527         int i, value = -1;
 528
 529         RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
 530
 531         for (i = 20; i > 0; i--) {
 532                 /*
 533                  * Check if the RTL8169 has completed retrieving data from
 534                  * the specified MII register.
 535                  */
 536                 if (RTL_R32(PHYAR) & 0x80000000) {
 537                         value = RTL_R32(PHYAR) & 0xffff;
 538                         break;
 539                 }
 540                 udelay(25);
 541         }
 542         return value;
 543 }
 544
 545 static void mdio_patch(void __iomem *ioaddr, int reg_addr, int value)
 546 {
 547         mdio_write(ioaddr, reg_addr, mdio_read(ioaddr, reg_addr) | value);
 548 }
 549
 550 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
 551                            int val)
 552 {
 553         struct rtl8169_private *tp = netdev_priv(dev);
 554         void __iomem *ioaddr = tp->mmio_addr;
 555
 556         mdio_write(ioaddr, location, val);
 557 }
 558
 559 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
 560 {
 561         struct rtl8169_private *tp = netdev_priv(dev);
 562         void __iomem *ioaddr = tp->mmio_addr;
 563
 564         return mdio_read(ioaddr, location);
 565 }
 566
 567 static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
 568 {
 569         unsigned int i;
 570
 571         RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
 572                 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
 573
 574         for (i = 0; i < 100; i++) {
 575                 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
 576                         break;
 577                 udelay(10);
 578         }
 579 }
 580
 581 static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
 582 {
 583         u16 value = 0xffff;
 584         unsigned int i;
 585
 586         RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
 587
 588         for (i = 0; i < 100; i++) {
 589                 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
 590                         value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
 591                         break;
 592                 }
 593                 udelay(10);
 594         }
 595
 596         return value;
 597 }
 598
 599 static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
 600 {
 601         unsigned int i;
 602
 603         RTL_W32(CSIDR, value);
 604         RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
 605                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
 606
 607         for (i = 0; i < 100; i++) {
 608                 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
 609                         break;
 610                 udelay(10);
 611         }
 612 }
 613
 614 static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
 615 {
 616         u32 value = ~0x00;
 617         unsigned int i;
 618
 619         RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
 620                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
 621
 622         for (i = 0; i < 100; i++) {
 623                 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
 624                         value = RTL_R32(CSIDR);
 625                         break;
 626                 }
 627                 udelay(10);
 628         }
 629
 630         return value;
 631 }
 632
 633 static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
 634 {
 635         RTL_W16(IntrMask, 0x0000);
 636
 637         RTL_W16(IntrStatus, 0xffff);
 638 }
 639
 640 static void rtl8169_asic_down(void __iomem *ioaddr)
 641 {
 642         RTL_W8(ChipCmd, 0x00);
 643         rtl8169_irq_mask_and_ack(ioaddr);
 644         RTL_R16(CPlusCmd);
 645 }
 646
 647 static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr)
 648 {
 649         return RTL_R32(TBICSR) & TBIReset;
 650 }
 651
 652 static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr)
 653 {
 654         return mdio_read(ioaddr, MII_BMCR) & BMCR_RESET;
 655 }
 656
 657 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
 658 {
 659         return RTL_R32(TBICSR) & TBILinkOk;
 660 }
 661
 662 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
 663 {
 664         return RTL_R8(PHYstatus) & LinkStatus;
 665 }
 666
 667 static void rtl8169_tbi_reset_enable(void __iomem *ioaddr)
 668 {
 669         RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
 670 }
 671
 672 static void rtl8169_xmii_reset_enable(void __iomem *ioaddr)
 673 {
 674         unsigned int val;
 675
 676         val = mdio_read(ioaddr, MII_BMCR) | BMCR_RESET;
 677         mdio_write(ioaddr, MII_BMCR, val & 0xffff);
 678 }
 679
 680 static void rtl8169_check_link_status(struct net_device *dev,
 681                                       struct rtl8169_private *tp,
 682                                       void __iomem *ioaddr)
 683 {
 684         unsigned long flags;
 685
 686         spin_lock_irqsave(&tp->lock, flags);
 687         if (tp->link_ok(ioaddr)) {
 688                 netif_carrier_on(dev);
 689                 if (netif_msg_ifup(tp))
 690                         printk(KERN_INFO PFX "%s: link up\n", dev->name);
 691         } else {
 692                 if (netif_msg_ifdown(tp))
 693                         printk(KERN_INFO PFX "%s: link down\n", dev->name);
 694                 netif_carrier_off(dev);
 695         }
 696         spin_unlock_irqrestore(&tp->lock, flags);
 697 }
 698
 699 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
 700 {
 701         struct rtl8169_private *tp = netdev_priv(dev);
 702         void __iomem *ioaddr = tp->mmio_addr;
 703         u8 options;
 704
 705         wol->wolopts = 0;
 706
 707 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
 708         wol->supported = WAKE_ANY;
 709
 710         spin_lock_irq(&tp->lock);
 711
 712         options = RTL_R8(Config1);
 713         if (!(options & PMEnable))
 714                 goto out_unlock;
 715
 716         options = RTL_R8(Config3);
 717         if (options & LinkUp)
 718                 wol->wolopts |= WAKE_PHY;
 719         if (options & MagicPacket)
 720                 wol->wolopts |= WAKE_MAGIC;
 721
 722         options = RTL_R8(Config5);
 723         if (options & UWF)
 724                 wol->wolopts |= WAKE_UCAST;
 725         if (options & BWF)
 726                 wol->wolopts |= WAKE_BCAST;
 727         if (options & MWF)
 728                 wol->wolopts |= WAKE_MCAST;
 729
 730 out_unlock:
 731         spin_unlock_irq(&tp->lock);
 732 }
 733
 734 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
 735 {
 736         struct rtl8169_private *tp = netdev_priv(dev);
 737         void __iomem *ioaddr = tp->mmio_addr;
 738         unsigned int i;
 739         static struct {
 740                 u32 opt;
 741                 u16 reg;
 742                 u8  mask;
 743         } cfg[] = {
 744                 { WAKE_ANY,   Config1, PMEnable },
 745                 { WAKE_PHY,   Config3, LinkUp },
 746                 { WAKE_MAGIC, Config3, MagicPacket },
 747                 { WAKE_UCAST, Config5, UWF },
 748                 { WAKE_BCAST, Config5, BWF },
 749                 { WAKE_MCAST, Config5, MWF },
 750                 { WAKE_ANY,   Config5, LanWake }
 751         };
 752
 753         spin_lock_irq(&tp->lock);
 754
 755         RTL_W8(Cfg9346, Cfg9346_Unlock);
 756
 757         for (i = 0; i < ARRAY_SIZE(cfg); i++) {
 758                 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
 759                 if (wol->wolopts & cfg[i].opt)
 760                         options |= cfg[i].mask;
 761                 RTL_W8(cfg[i].reg, options);
 762         }
 763
 764         RTL_W8(Cfg9346, Cfg9346_Lock);
 765
 766         if (wol->wolopts)
 767                 tp->features |= RTL_FEATURE_WOL;
 768         else
 769                 tp->features &= ~RTL_FEATURE_WOL;
 770         device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
 771
 772         spin_unlock_irq(&tp->lock);
 773
 774         return 0;
 775 }
 776
 777 static void rtl8169_get_drvinfo(struct net_device *dev,
 778                                 struct ethtool_drvinfo *info)
 779 {
 780         struct rtl8169_private *tp = netdev_priv(dev);
 781
 782         strcpy(info->driver, MODULENAME);
 783         strcpy(info->version, RTL8169_VERSION);
 784         strcpy(info->bus_info, pci_name(tp->pci_dev));
 785 }
 786
 787 static int rtl8169_get_regs_len(struct net_device *dev)
 788 {
 789         return R8169_REGS_SIZE;
 790 }
 791
 792 static int rtl8169_set_speed_tbi(struct net_device *dev,
 793                                  u8 autoneg, u16 speed, u8 duplex)
 794 {
 795         struct rtl8169_private *tp = netdev_priv(dev);
 796         void __iomem *ioaddr = tp->mmio_addr;
 797         int ret = 0;
 798         u32 reg;
 799
 800         reg = RTL_R32(TBICSR);
 801         if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
 802             (duplex == DUPLEX_FULL)) {
 803                 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
 804         } else if (autoneg == AUTONEG_ENABLE)
 805                 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
 806         else {
 807                 if (netif_msg_link(tp)) {
 808                         printk(KERN_WARNING "%s: "
 809                                "incorrect speed setting refused in TBI mode\n",
 810                                dev->name);
 811                 }
 812                 ret = -EOPNOTSUPP;
 813         }
 814
 815         return ret;
 816 }
 817
 818 static int rtl8169_set_speed_xmii(struct net_device *dev,
 819                                   u8 autoneg, u16 speed, u8 duplex)
 820 {
 821         struct rtl8169_private *tp = netdev_priv(dev);
 822         void __iomem *ioaddr = tp->mmio_addr;
 823         int auto_nego, giga_ctrl;
 824
 825         auto_nego = mdio_read(ioaddr, MII_ADVERTISE);
 826         auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
 827                        ADVERTISE_100HALF | ADVERTISE_100FULL);
 828         giga_ctrl = mdio_read(ioaddr, MII_CTRL1000);
 829         giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
 830
 831         if (autoneg == AUTONEG_ENABLE) {
 832                 auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
 833                               ADVERTISE_100HALF | ADVERTISE_100FULL);
 834                 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
 835         } else {
 836                 if (speed == SPEED_10)
 837                         auto_nego |= ADVERTISE_10HALF | ADVERTISE_10FULL;
 838                 else if (speed == SPEED_100)
 839                         auto_nego |= ADVERTISE_100HALF | ADVERTISE_100FULL;
 840                 else if (speed == SPEED_1000)
 841                         giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
 842
 843                 if (duplex == DUPLEX_HALF)
 844                         auto_nego &= ~(ADVERTISE_10FULL | ADVERTISE_100FULL);
 845
 846                 if (duplex == DUPLEX_FULL)
 847                         auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_100HALF);
 848
 849                 /* This tweak comes straight from Realtek's driver. */
 850                 if ((speed == SPEED_100) && (duplex == DUPLEX_HALF) &&
 851                     ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
 852                      (tp->mac_version == RTL_GIGA_MAC_VER_16))) {
 853                         auto_nego = ADVERTISE_100HALF | ADVERTISE_CSMA;
 854                 }
 855         }
 856
 857         /* The 8100e/8101e/8102e do Fast Ethernet only. */
 858         if ((tp->mac_version == RTL_GIGA_MAC_VER_07) ||
 859             (tp->mac_version == RTL_GIGA_MAC_VER_08) ||
 860             (tp->mac_version == RTL_GIGA_MAC_VER_09) ||
 861             (tp->mac_version == RTL_GIGA_MAC_VER_10) ||
 862             (tp->mac_version == RTL_GIGA_MAC_VER_13) ||
 863             (tp->mac_version == RTL_GIGA_MAC_VER_14) ||
 864             (tp->mac_version == RTL_GIGA_MAC_VER_15) ||
 865             (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
 866                 if ((giga_ctrl & (ADVERTISE_1000FULL | ADVERTISE_1000HALF)) &&
 867                     netif_msg_link(tp)) {
 868                         printk(KERN_INFO "%s: PHY does not support 1000Mbps.\n",
 869                                dev->name);
 870                 }
 871                 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
 872         }
 873
 874         auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
 875
 876         if ((tp->mac_version == RTL_GIGA_MAC_VER_11) ||
 877             (tp->mac_version == RTL_GIGA_MAC_VER_12) ||
 878             (tp->mac_version >= RTL_GIGA_MAC_VER_17)) {
 879                 /*
 880                  * Wake up the PHY.
 881                  * Vendor specific (0x1f) and reserved (0x0e) MII registers.
 882                  */
 883                 mdio_write(ioaddr, 0x1f, 0x0000);
 884                 mdio_write(ioaddr, 0x0e, 0x0000);
 885         }
 886
 887         tp->phy_auto_nego_reg = auto_nego;
 888         tp->phy_1000_ctrl_reg = giga_ctrl;
 889
 890         mdio_write(ioaddr, MII_ADVERTISE, auto_nego);
 891         mdio_write(ioaddr, MII_CTRL1000, giga_ctrl);
 892         mdio_write(ioaddr, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART);
 893         return 0;
 894 }
 895
 896 static int rtl8169_set_speed(struct net_device *dev,
 897                              u8 autoneg, u16 speed, u8 duplex)
 898 {
 899         struct rtl8169_private *tp = netdev_priv(dev);
 900         int ret;
 901
 902         ret = tp->set_speed(dev, autoneg, speed, duplex);
 903
 904         if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
 905                 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
 906
 907         return ret;
 908 }
 909
 910 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 911 {
 912         struct rtl8169_private *tp = netdev_priv(dev);
 913         unsigned long flags;
 914         int ret;
 915
 916         spin_lock_irqsave(&tp->lock, flags);
 917         ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
 918         spin_unlock_irqrestore(&tp->lock, flags);
 919
 920         return ret;
 921 }
 922
 923 static u32 rtl8169_get_rx_csum(struct net_device *dev)
 924 {
 925         struct rtl8169_private *tp = netdev_priv(dev);
 926
 927         return tp->cp_cmd & RxChkSum;
 928 }
 929
 930 static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
 931 {
 932         struct rtl8169_private *tp = netdev_priv(dev);
 933         void __iomem *ioaddr = tp->mmio_addr;
 934         unsigned long flags;
 935
 936         spin_lock_irqsave(&tp->lock, flags);
 937
 938         if (data)
 939                 tp->cp_cmd |= RxChkSum;
 940         else
 941                 tp->cp_cmd &= ~RxChkSum;
 942
 943         RTL_W16(CPlusCmd, tp->cp_cmd);
 944         RTL_R16(CPlusCmd);
 945
 946         spin_unlock_irqrestore(&tp->lock, flags);
 947
 948         return 0;
 949 }
 950
 951 #ifdef CONFIG_R8169_VLAN
 952
 953 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
 954                                       struct sk_buff *skb)
 955 {
 956         return (tp->vlgrp && vlan_tx_tag_present(skb)) ?
 957                 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
 958 }
 959
 960 static void rtl8169_vlan_rx_register(struct net_device *dev,
 961                                      struct vlan_group *grp)
 962 {
 963         struct rtl8169_private *tp = netdev_priv(dev);
 964         void __iomem *ioaddr = tp->mmio_addr;
 965         unsigned long flags;
 966
 967         spin_lock_irqsave(&tp->lock, flags);
 968         tp->vlgrp = grp;
 969         if (tp->vlgrp)
 970                 tp->cp_cmd |= RxVlan;
 971         else
 972                 tp->cp_cmd &= ~RxVlan;
 973         RTL_W16(CPlusCmd, tp->cp_cmd);
 974         RTL_R16(CPlusCmd);
 975         spin_unlock_irqrestore(&tp->lock, flags);
 976 }
 977
 978 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
 979                                struct sk_buff *skb)
 980 {
 981         u32 opts2 = le32_to_cpu(desc->opts2);
 982         struct vlan_group *vlgrp = tp->vlgrp;
 983         int ret;
 984
 985         if (vlgrp && (opts2 & RxVlanTag)) {
 986                 vlan_hwaccel_receive_skb(skb, vlgrp, swab16(opts2 & 0xffff));
 987                 ret = 0;
 988         } else
 989                 ret = -1;
 990         desc->opts2 = 0;
 991         return ret;
 992 }
 993
 994 #else /* !CONFIG_R8169_VLAN */
 995
 996 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
 997                                       struct sk_buff *skb)
 998 {
 999         return 0;
1000 }
1001
1002 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
1003                                struct sk_buff *skb)
1004 {
1005         return -1;
1006 }
1007
1008 #endif
1009
1010 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1011 {
1012         struct rtl8169_private *tp = netdev_priv(dev);
1013         void __iomem *ioaddr = tp->mmio_addr;
1014         u32 status;
1015
1016         cmd->supported =
1017                 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1018         cmd->port = PORT_FIBRE;
1019         cmd->transceiver = XCVR_INTERNAL;
1020
1021         status = RTL_R32(TBICSR);
1022         cmd->advertising = (status & TBINwEnable) ?  ADVERTISED_Autoneg : 0;
1023         cmd->autoneg = !!(status & TBINwEnable);
1024
1025         cmd->speed = SPEED_1000;
1026         cmd->duplex = DUPLEX_FULL; /* Always set */
1027
1028         return 0;
1029 }
1030
1031 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1032 {
1033         struct rtl8169_private *tp = netdev_priv(dev);
1034
1035         return mii_ethtool_gset(&tp->mii, cmd);
1036 }
1037
1038 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1039 {
1040         struct rtl8169_private *tp = netdev_priv(dev);
1041         unsigned long flags;
1042         int rc;
1043
1044         spin_lock_irqsave(&tp->lock, flags);
1045
1046         rc = tp->get_settings(dev, cmd);
1047
1048         spin_unlock_irqrestore(&tp->lock, flags);
1049         return rc;
1050 }
1051
1052 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1053                              void *p)
1054 {
1055         struct rtl8169_private *tp = netdev_priv(dev);
1056         unsigned long flags;
1057
1058         if (regs->len > R8169_REGS_SIZE)
1059                 regs->len = R8169_REGS_SIZE;
1060
1061         spin_lock_irqsave(&tp->lock, flags);
1062         memcpy_fromio(p, tp->mmio_addr, regs->len);
1063         spin_unlock_irqrestore(&tp->lock, flags);
1064 }
1065
1066 static u32 rtl8169_get_msglevel(struct net_device *dev)
1067 {
1068         struct rtl8169_private *tp = netdev_priv(dev);
1069
1070         return tp->msg_enable;
1071 }
1072
1073 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1074 {
1075         struct rtl8169_private *tp = netdev_priv(dev);
1076
1077         tp->msg_enable = value;
1078 }
1079
1080 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1081         "tx_packets",
1082         "rx_packets",
1083         "tx_errors",
1084         "rx_errors",
1085         "rx_missed",
1086         "align_errors",
1087         "tx_single_collisions",
1088         "tx_multi_collisions",
1089         "unicast",
1090         "broadcast",
1091         "multicast",
1092         "tx_aborted",
1093         "tx_underrun",
1094 };
1095
1096 struct rtl8169_counters {
1097         __le64  tx_packets;
1098         __le64  rx_packets;
1099         __le64  tx_errors;
1100         __le32  rx_errors;
1101         __le16  rx_missed;
1102         __le16  align_errors;
1103         __le32  tx_one_collision;
1104         __le32  tx_multi_collision;
1105         __le64  rx_unicast;
1106         __le64  rx_broadcast;
1107         __le32  rx_multicast;
1108         __le16  tx_aborted;
1109         __le16  tx_underun;
1110 };
1111
1112 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1113 {
1114         switch (sset) {
1115         case ETH_SS_STATS:
1116                 return ARRAY_SIZE(rtl8169_gstrings);
1117         default:
1118                 return -EOPNOTSUPP;
1119         }
1120 }
1121
1122 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1123                                       struct ethtool_stats *stats, u64 *data)
1124 {
1125         struct rtl8169_private *tp = netdev_priv(dev);
1126         void __iomem *ioaddr = tp->mmio_addr;
1127         struct rtl8169_counters *counters;
1128         dma_addr_t paddr;
1129         u32 cmd;
1130
1131         ASSERT_RTNL();
1132
1133         counters = pci_alloc_consistent(tp->pci_dev, sizeof(*counters), &paddr);
1134         if (!counters)
1135                 return;
1136
1137         RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1138         cmd = (u64)paddr & DMA_32BIT_MASK;
1139         RTL_W32(CounterAddrLow, cmd);
1140         RTL_W32(CounterAddrLow, cmd | CounterDump);
1141
1142         while (RTL_R32(CounterAddrLow) & CounterDump) {
1143                 if (msleep_interruptible(1))
1144                         break;
1145         }
1146
1147         RTL_W32(CounterAddrLow, 0);
1148         RTL_W32(CounterAddrHigh, 0);
1149
1150         data[0] = le64_to_cpu(counters->tx_packets);
1151         data[1] = le64_to_cpu(counters->rx_packets);
1152         data[2] = le64_to_cpu(counters->tx_errors);
1153         data[3] = le32_to_cpu(counters->rx_errors);
1154         data[4] = le16_to_cpu(counters->rx_missed);
1155         data[5] = le16_to_cpu(counters->align_errors);
1156         data[6] = le32_to_cpu(counters->tx_one_collision);
1157         data[7] = le32_to_cpu(counters->tx_multi_collision);
1158         data[8] = le64_to_cpu(counters->rx_unicast);
1159         data[9] = le64_to_cpu(counters->rx_broadcast);
1160         data[10] = le32_to_cpu(counters->rx_multicast);
1161         data[11] = le16_to_cpu(counters->tx_aborted);
1162         data[12] = le16_to_cpu(counters->tx_underun);
1163
1164         pci_free_consistent(tp->pci_dev, sizeof(*counters), counters, paddr);
1165 }
1166
1167 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1168 {
1169         switch(stringset) {
1170         case ETH_SS_STATS:
1171                 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1172                 break;
1173         }
1174 }
1175
1176 static const struct ethtool_ops rtl8169_ethtool_ops = {
1177         .get_drvinfo            = rtl8169_get_drvinfo,
1178         .get_regs_len           = rtl8169_get_regs_len,
1179         .get_link               = ethtool_op_get_link,
1180         .get_settings           = rtl8169_get_settings,
1181         .set_settings           = rtl8169_set_settings,
1182         .get_msglevel           = rtl8169_get_msglevel,
1183         .set_msglevel           = rtl8169_set_msglevel,
1184         .get_rx_csum            = rtl8169_get_rx_csum,
1185         .set_rx_csum            = rtl8169_set_rx_csum,
1186         .set_tx_csum            = ethtool_op_set_tx_csum,
1187         .set_sg                 = ethtool_op_set_sg,
1188         .set_tso                = ethtool_op_set_tso,
1189         .get_regs               = rtl8169_get_regs,
1190         .get_wol                = rtl8169_get_wol,
1191         .set_wol                = rtl8169_set_wol,
1192         .get_strings            = rtl8169_get_strings,
1193         .get_sset_count         = rtl8169_get_sset_count,
1194         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
1195 };
1196
1197 static void rtl8169_write_gmii_reg_bit(void __iomem *ioaddr, int reg,
1198                                        int bitnum, int bitval)
1199 {
1200         int val;
1201
1202         val = mdio_read(ioaddr, reg);
1203         val = (bitval == 1) ?
1204                 val | (bitval << bitnum) :  val & ~(0x0001 << bitnum);
1205         mdio_write(ioaddr, reg, val & 0xffff);
1206 }
1207
1208 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1209                                     void __iomem *ioaddr)
1210 {
1211         /*
1212          * The driver currently handles the 8168Bf and the 8168Be identically
1213          * but they can be identified more specifically through the test below
1214          * if needed:
1215          *
1216          * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1217          *
1218          * Same thing for the 8101Eb and the 8101Ec:
1219          *
1220          * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1221          */
1222         const struct {
1223                 u32 mask;
1224                 u32 val;
1225                 int mac_version;
1226         } mac_info[] = {
1227                 /* 8168C family. */
1228                 { 0x7cf00000, 0x3ca00000,       RTL_GIGA_MAC_VER_24 },
1229                 { 0x7cf00000, 0x3c900000,       RTL_GIGA_MAC_VER_23 },
1230                 { 0x7cf00000, 0x3c800000,       RTL_GIGA_MAC_VER_18 },
1231                 { 0x7c800000, 0x3c800000,       RTL_GIGA_MAC_VER_24 },
1232                 { 0x7cf00000, 0x3c000000,       RTL_GIGA_MAC_VER_19 },
1233                 { 0x7cf00000, 0x3c200000,       RTL_GIGA_MAC_VER_20 },
1234                 { 0x7cf00000, 0x3c300000,       RTL_GIGA_MAC_VER_21 },
1235                 { 0x7cf00000, 0x3c400000,       RTL_GIGA_MAC_VER_22 },
1236                 { 0x7c800000, 0x3c000000,       RTL_GIGA_MAC_VER_22 },
1237
1238                 /* 8168B family. */
1239                 { 0x7cf00000, 0x38000000,       RTL_GIGA_MAC_VER_12 },
1240                 { 0x7cf00000, 0x38500000,       RTL_GIGA_MAC_VER_17 },
1241                 { 0x7c800000, 0x38000000,       RTL_GIGA_MAC_VER_17 },
1242                 { 0x7c800000, 0x30000000,       RTL_GIGA_MAC_VER_11 },
1243
1244                 /* 8101 family. */
1245                 { 0x7cf00000, 0x34a00000,       RTL_GIGA_MAC_VER_09 },
1246                 { 0x7cf00000, 0x24a00000,       RTL_GIGA_MAC_VER_09 },
1247                 { 0x7cf00000, 0x34900000,       RTL_GIGA_MAC_VER_08 },
1248                 { 0x7cf00000, 0x24900000,       RTL_GIGA_MAC_VER_08 },
1249                 { 0x7cf00000, 0x34800000,       RTL_GIGA_MAC_VER_07 },
1250                 { 0x7cf00000, 0x24800000,       RTL_GIGA_MAC_VER_07 },
1251                 { 0x7cf00000, 0x34000000,       RTL_GIGA_MAC_VER_13 },
1252                 { 0x7cf00000, 0x34300000,       RTL_GIGA_MAC_VER_10 },
1253                 { 0x7cf00000, 0x34200000,       RTL_GIGA_MAC_VER_16 },
1254                 { 0x7c800000, 0x34800000,       RTL_GIGA_MAC_VER_09 },
1255                 { 0x7c800000, 0x24800000,       RTL_GIGA_MAC_VER_09 },
1256                 { 0x7c800000, 0x34000000,       RTL_GIGA_MAC_VER_16 },
1257                 /* FIXME: where did these entries come from ? -- FR */
1258                 { 0xfc800000, 0x38800000,       RTL_GIGA_MAC_VER_15 },
1259                 { 0xfc800000, 0x30800000,       RTL_GIGA_MAC_VER_14 },
1260
1261                 /* 8110 family. */
1262                 { 0xfc800000, 0x98000000,       RTL_GIGA_MAC_VER_06 },
1263                 { 0xfc800000, 0x18000000,       RTL_GIGA_MAC_VER_05 },
1264                 { 0xfc800000, 0x10000000,       RTL_GIGA_MAC_VER_04 },
1265                 { 0xfc800000, 0x04000000,       RTL_GIGA_MAC_VER_03 },
1266                 { 0xfc800000, 0x00800000,       RTL_GIGA_MAC_VER_02 },
1267                 { 0xfc800000, 0x00000000,       RTL_GIGA_MAC_VER_01 },
1268
1269                 { 0x00000000, 0x00000000,       RTL_GIGA_MAC_VER_01 }   /* Catch-all */
1270         }, *p = mac_info;
1271         u32 reg;
1272
1273         reg = RTL_R32(TxConfig);
1274         while ((reg & p->mask) != p->val)
1275                 p++;
1276         tp->mac_version = p->mac_version;
1277
1278         if (p->mask == 0x00000000) {
1279                 struct pci_dev *pdev = tp->pci_dev;
1280
1281                 dev_info(&pdev->dev, "unknown MAC (%08x)\n", reg);
1282         }
1283 }
1284
1285 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1286 {
1287         dprintk("mac_version = 0x%02x\n", tp->mac_version);
1288 }
1289
1290 struct phy_reg {
1291         u16 reg;
1292         u16 val;
1293 };
1294
1295 static void rtl_phy_write(void __iomem *ioaddr, struct phy_reg *regs, int len)
1296 {
1297         while (len-- > 0) {
1298                 mdio_write(ioaddr, regs->reg, regs->val);
1299                 regs++;
1300         }
1301 }
1302
1303 static void rtl8169s_hw_phy_config(void __iomem *ioaddr)
1304 {
1305         struct {
1306                 u16 regs[5]; /* Beware of bit-sign propagation */
1307         } phy_magic[5] = { {
1308                 { 0x0000,       //w 4 15 12 0
1309                   0x00a1,       //w 3 15 0 00a1
1310                   0x0008,       //w 2 15 0 0008
1311                   0x1020,       //w 1 15 0 1020
1312                   0x1000 } },{  //w 0 15 0 1000
1313                 { 0x7000,       //w 4 15 12 7
1314                   0xff41,       //w 3 15 0 ff41
1315                   0xde60,       //w 2 15 0 de60
1316                   0x0140,       //w 1 15 0 0140
1317                   0x0077 } },{  //w 0 15 0 0077
1318                 { 0xa000,       //w 4 15 12 a
1319                   0xdf01,       //w 3 15 0 df01
1320                   0xdf20,       //w 2 15 0 df20
1321                   0xff95,       //w 1 15 0 ff95
1322                   0xfa00 } },{  //w 0 15 0 fa00
1323                 { 0xb000,       //w 4 15 12 b
1324                   0xff41,       //w 3 15 0 ff41
1325                   0xde20,       //w 2 15 0 de20
1326                   0x0140,       //w 1 15 0 0140
1327                   0x00bb } },{  //w 0 15 0 00bb
1328                 { 0xf000,       //w 4 15 12 f
1329                   0xdf01,       //w 3 15 0 df01
1330                   0xdf20,       //w 2 15 0 df20
1331                   0xff95,       //w 1 15 0 ff95
1332                   0xbf00 }      //w 0 15 0 bf00
1333                 }
1334         }, *p = phy_magic;
1335         unsigned int i;
1336
1337         mdio_write(ioaddr, 0x1f, 0x0001);               //w 31 2 0 1
1338         mdio_write(ioaddr, 0x15, 0x1000);               //w 21 15 0 1000
1339         mdio_write(ioaddr, 0x18, 0x65c7);               //w 24 15 0 65c7
1340         rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0);   //w 4 11 11 0
1341
1342         for (i = 0; i < ARRAY_SIZE(phy_magic); i++, p++) {
1343                 int val, pos = 4;
1344
1345                 val = (mdio_read(ioaddr, pos) & 0x0fff) | (p->regs[0] & 0xffff);
1346                 mdio_write(ioaddr, pos, val);
1347                 while (--pos >= 0)
1348                         mdio_write(ioaddr, pos, p->regs[4 - pos] & 0xffff);
1349                 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 1); //w 4 11 11 1
1350                 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1351         }
1352         mdio_write(ioaddr, 0x1f, 0x0000); //w 31 2 0 0
1353 }
1354
1355 static void rtl8169sb_hw_phy_config(void __iomem *ioaddr)
1356 {
1357         struct phy_reg phy_reg_init[] = {
1358                 { 0x1f, 0x0002 },
1359                 { 0x01, 0x90d0 },
1360                 { 0x1f, 0x0000 }
1361         };
1362
1363         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1364 }
1365
1366 static void rtl8168bb_hw_phy_config(void __iomem *ioaddr)
1367 {
1368         struct phy_reg phy_reg_init[] = {
1369                 { 0x10, 0xf41b },
1370                 { 0x1f, 0x0000 }
1371         };
1372
1373         mdio_write(ioaddr, 0x1f, 0x0001);
1374         mdio_patch(ioaddr, 0x16, 1 << 0);
1375
1376         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1377 }
1378
1379 static void rtl8168bef_hw_phy_config(void __iomem *ioaddr)
1380 {
1381         struct phy_reg phy_reg_init[] = {
1382                 { 0x1f, 0x0001 },
1383                 { 0x10, 0xf41b },
1384                 { 0x1f, 0x0000 }
1385         };
1386
1387         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1388 }
1389
1390 static void rtl8168cp_1_hw_phy_config(void __iomem *ioaddr)
1391 {
1392         struct phy_reg phy_reg_init[] = {
1393                 { 0x1f, 0x0000 },
1394                 { 0x1d, 0x0f00 },
1395                 { 0x1f, 0x0002 },
1396                 { 0x0c, 0x1ec8 },
1397                 { 0x1f, 0x0000 }
1398         };
1399
1400         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1401 }
1402
1403 static void rtl8168cp_2_hw_phy_config(void __iomem *ioaddr)
1404 {
1405         struct phy_reg phy_reg_init[] = {
1406                 { 0x1f, 0x0001 },
1407                 { 0x1d, 0x3d98 },
1408                 { 0x1f, 0x0000 }
1409         };
1410
1411         mdio_write(ioaddr, 0x1f, 0x0000);
1412         mdio_patch(ioaddr, 0x14, 1 << 5);
1413         mdio_patch(ioaddr, 0x0d, 1 << 5);
1414
1415         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1416 }
1417
1418 static void rtl8168c_1_hw_phy_config(void __iomem *ioaddr)
1419 {
1420         struct phy_reg phy_reg_init[] = {
1421                 { 0x1f, 0x0001 },
1422                 { 0x12, 0x2300 },
1423                 { 0x1f, 0x0002 },
1424                 { 0x00, 0x88d4 },
1425                 { 0x01, 0x82b1 },
1426                 { 0x03, 0x7002 },
1427                 { 0x08, 0x9e30 },
1428                 { 0x09, 0x01f0 },
1429                 { 0x0a, 0x5500 },
1430                 { 0x0c, 0x00c8 },
1431                 { 0x1f, 0x0003 },
1432                 { 0x12, 0xc096 },
1433                 { 0x16, 0x000a },
1434                 { 0x1f, 0x0000 },
1435                 { 0x1f, 0x0000 },
1436                 { 0x09, 0x2000 },
1437                 { 0x09, 0x0000 }
1438         };
1439
1440         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1441
1442         mdio_patch(ioaddr, 0x14, 1 << 5);
1443         mdio_patch(ioaddr, 0x0d, 1 << 5);
1444         mdio_write(ioaddr, 0x1f, 0x0000);
1445 }
1446
1447 static void rtl8168c_2_hw_phy_config(void __iomem *ioaddr)
1448 {
1449         struct phy_reg phy_reg_init[] = {
1450                 { 0x1f, 0x0001 },
1451                 { 0x12, 0x2300 },
1452                 { 0x03, 0x802f },
1453                 { 0x02, 0x4f02 },
1454                 { 0x01, 0x0409 },
1455                 { 0x00, 0xf099 },
1456                 { 0x04, 0x9800 },
1457                 { 0x04, 0x9000 },
1458                 { 0x1d, 0x3d98 },
1459                 { 0x1f, 0x0002 },
1460                 { 0x0c, 0x7eb8 },
1461                 { 0x06, 0x0761 },
1462                 { 0x1f, 0x0003 },
1463                 { 0x16, 0x0f0a },
1464                 { 0x1f, 0x0000 }
1465         };
1466
1467         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1468
1469         mdio_patch(ioaddr, 0x16, 1 << 0);
1470         mdio_patch(ioaddr, 0x14, 1 << 5);
1471         mdio_patch(ioaddr, 0x0d, 1 << 5);
1472         mdio_write(ioaddr, 0x1f, 0x0000);
1473 }
1474
1475 static void rtl8168c_3_hw_phy_config(void __iomem *ioaddr)
1476 {
1477         struct phy_reg phy_reg_init[] = {
1478                 { 0x1f, 0x0001 },
1479                 { 0x12, 0x2300 },
1480                 { 0x1d, 0x3d98 },
1481                 { 0x1f, 0x0002 },
1482                 { 0x0c, 0x7eb8 },
1483                 { 0x06, 0x5461 },
1484                 { 0x1f, 0x0003 },
1485                 { 0x16, 0x0f0a },
1486                 { 0x1f, 0x0000 }
1487         };
1488
1489         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1490
1491         mdio_patch(ioaddr, 0x16, 1 << 0);
1492         mdio_patch(ioaddr, 0x14, 1 << 5);
1493         mdio_patch(ioaddr, 0x0d, 1 << 5);
1494         mdio_write(ioaddr, 0x1f, 0x0000);
1495 }
1496
1497 static void rtl8168c_4_hw_phy_config(void __iomem *ioaddr)
1498 {
1499         rtl8168c_3_hw_phy_config(ioaddr);
1500 }
1501
1502 static void rtl8102e_hw_phy_config(void __iomem *ioaddr)
1503 {
1504         struct phy_reg phy_reg_init[] = {
1505                 { 0x1f, 0x0003 },
1506                 { 0x08, 0x441d },
1507                 { 0x01, 0x9100 },
1508                 { 0x1f, 0x0000 }
1509         };
1510
1511         mdio_write(ioaddr, 0x1f, 0x0000);
1512         mdio_patch(ioaddr, 0x11, 1 << 12);
1513         mdio_patch(ioaddr, 0x19, 1 << 13);
1514
1515         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1516 }
1517
1518 static void rtl_hw_phy_config(struct net_device *dev)
1519 {
1520         struct rtl8169_private *tp = netdev_priv(dev);
1521         void __iomem *ioaddr = tp->mmio_addr;
1522
1523         rtl8169_print_mac_version(tp);
1524
1525         switch (tp->mac_version) {
1526         case RTL_GIGA_MAC_VER_01:
1527                 break;
1528         case RTL_GIGA_MAC_VER_02:
1529         case RTL_GIGA_MAC_VER_03:
1530                 rtl8169s_hw_phy_config(ioaddr);
1531                 break;
1532         case RTL_GIGA_MAC_VER_04:
1533                 rtl8169sb_hw_phy_config(ioaddr);
1534                 break;
1535         case RTL_GIGA_MAC_VER_07:
1536         case RTL_GIGA_MAC_VER_08:
1537         case RTL_GIGA_MAC_VER_09:
1538                 rtl8102e_hw_phy_config(ioaddr);
1539                 break;
1540         case RTL_GIGA_MAC_VER_11:
1541                 rtl8168bb_hw_phy_config(ioaddr);
1542                 break;
1543         case RTL_GIGA_MAC_VER_12:
1544                 rtl8168bef_hw_phy_config(ioaddr);
1545                 break;
1546         case RTL_GIGA_MAC_VER_17:
1547                 rtl8168bef_hw_phy_config(ioaddr);
1548                 break;
1549         case RTL_GIGA_MAC_VER_18:
1550                 rtl8168cp_1_hw_phy_config(ioaddr);
1551                 break;
1552         case RTL_GIGA_MAC_VER_19:
1553                 rtl8168c_1_hw_phy_config(ioaddr);
1554                 break;
1555         case RTL_GIGA_MAC_VER_20:
1556                 rtl8168c_2_hw_phy_config(ioaddr);
1557                 break;
1558         case RTL_GIGA_MAC_VER_21:
1559                 rtl8168c_3_hw_phy_config(ioaddr);
1560                 break;
1561         case RTL_GIGA_MAC_VER_22:
1562                 rtl8168c_4_hw_phy_config(ioaddr);
1563                 break;
1564         case RTL_GIGA_MAC_VER_23:
1565         case RTL_GIGA_MAC_VER_24:
1566                 rtl8168cp_2_hw_phy_config(ioaddr);
1567                 break;
1568
1569         default:
1570                 break;
1571         }
1572 }
1573
1574 static void rtl8169_phy_timer(unsigned long __opaque)
1575 {
1576         struct net_device *dev = (struct net_device *)__opaque;
1577         struct rtl8169_private *tp = netdev_priv(dev);
1578         struct timer_list *timer = &tp->timer;
1579         void __iomem *ioaddr = tp->mmio_addr;
1580         unsigned long timeout = RTL8169_PHY_TIMEOUT;
1581
1582         assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1583
1584         if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1585                 return;
1586
1587         spin_lock_irq(&tp->lock);
1588
1589         if (tp->phy_reset_pending(ioaddr)) {
1590                 /*
1591                  * A busy loop could burn quite a few cycles on nowadays CPU.
1592                  * Let's delay the execution of the timer for a few ticks.
1593                  */
1594                 timeout = HZ/10;
1595                 goto out_mod_timer;
1596         }
1597
1598         if (tp->link_ok(ioaddr))
1599                 goto out_unlock;
1600
1601         if (netif_msg_link(tp))
1602                 printk(KERN_WARNING "%s: PHY reset until link up\n", dev->name);
1603
1604         tp->phy_reset_enable(ioaddr);
1605
1606 out_mod_timer:
1607         mod_timer(timer, jiffies + timeout);
1608 out_unlock:
1609         spin_unlock_irq(&tp->lock);
1610 }
1611
1612 static inline void rtl8169_delete_timer(struct net_device *dev)
1613 {
1614         struct rtl8169_private *tp = netdev_priv(dev);
1615         struct timer_list *timer = &tp->timer;
1616
1617         if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1618                 return;
1619
1620         del_timer_sync(timer);
1621 }
1622
1623 static inline void rtl8169_request_timer(struct net_device *dev)
1624 {
1625         struct rtl8169_private *tp = netdev_priv(dev);
1626         struct timer_list *timer = &tp->timer;
1627
1628         if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1629                 return;
1630
1631         mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
1632 }
1633
1634 #ifdef CONFIG_NET_POLL_CONTROLLER
1635 /*
1636  * Polling 'interrupt' - used by things like netconsole to send skbs
1637  * without having to re-enable interrupts. It's not called while
1638  * the interrupt routine is executing.
1639  */
1640 static void rtl8169_netpoll(struct net_device *dev)
1641 {
1642         struct rtl8169_private *tp = netdev_priv(dev);
1643         struct pci_dev *pdev = tp->pci_dev;
1644
1645         disable_irq(pdev->irq);
1646         rtl8169_interrupt(pdev->irq, dev);
1647         enable_irq(pdev->irq);
1648 }
1649 #endif
1650
1651 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
1652                                   void __iomem *ioaddr)
1653 {
1654         iounmap(ioaddr);
1655         pci_release_regions(pdev);
1656         pci_disable_device(pdev);
1657         free_netdev(dev);
1658 }
1659
1660 static void rtl8169_phy_reset(struct net_device *dev,
1661                               struct rtl8169_private *tp)
1662 {
1663         void __iomem *ioaddr = tp->mmio_addr;
1664         unsigned int i;
1665
1666         tp->phy_reset_enable(ioaddr);
1667         for (i = 0; i < 100; i++) {
1668                 if (!tp->phy_reset_pending(ioaddr))
1669                         return;
1670                 msleep(1);
1671         }
1672         if (netif_msg_link(tp))
1673                 printk(KERN_ERR "%s: PHY reset failed.\n", dev->name);
1674 }
1675
1676 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
1677 {
1678         void __iomem *ioaddr = tp->mmio_addr;
1679
1680         rtl_hw_phy_config(dev);
1681
1682         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
1683                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1684                 RTL_W8(0x82, 0x01);
1685         }
1686
1687         pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
1688
1689         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
1690                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
1691
1692         if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
1693                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1694                 RTL_W8(0x82, 0x01);
1695                 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
1696                 mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0
1697         }
1698
1699         rtl8169_phy_reset(dev, tp);
1700
1701         /*
1702          * rtl8169_set_speed_xmii takes good care of the Fast Ethernet
1703          * only 8101. Don't panic.
1704          */
1705         rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL);
1706
1707         if ((RTL_R8(PHYstatus) & TBI_Enable) && netif_msg_link(tp))
1708                 printk(KERN_INFO PFX "%s: TBI auto-negotiating\n", dev->name);
1709 }
1710
1711 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
1712 {
1713         void __iomem *ioaddr = tp->mmio_addr;
1714         u32 high;
1715         u32 low;
1716
1717         low  = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
1718         high = addr[4] | (addr[5] << 8);
1719
1720         spin_lock_irq(&tp->lock);
1721
1722         RTL_W8(Cfg9346, Cfg9346_Unlock);
1723         RTL_W32(MAC0, low);
1724         RTL_W32(MAC4, high);
1725         RTL_W8(Cfg9346, Cfg9346_Lock);
1726
1727         spin_unlock_irq(&tp->lock);
1728 }
1729
1730 static int rtl_set_mac_address(struct net_device *dev, void *p)
1731 {
1732         struct rtl8169_private *tp = netdev_priv(dev);
1733         struct sockaddr *addr = p;
1734
1735         if (!is_valid_ether_addr(addr->sa_data))
1736                 return -EADDRNOTAVAIL;
1737
1738         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1739
1740         rtl_rar_set(tp, dev->dev_addr);
1741
1742         return 0;
1743 }
1744
1745 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1746 {
1747         struct rtl8169_private *tp = netdev_priv(dev);
1748         struct mii_ioctl_data *data = if_mii(ifr);
1749
1750         if (!netif_running(dev))
1751                 return -ENODEV;
1752
1753         switch (cmd) {
1754         case SIOCGMIIPHY:
1755                 data->phy_id = 32; /* Internal PHY */
1756                 return 0;
1757
1758         case SIOCGMIIREG:
1759                 data->val_out = mdio_read(tp->mmio_addr, data->reg_num & 0x1f);
1760                 return 0;
1761
1762         case SIOCSMIIREG:
1763                 if (!capable(CAP_NET_ADMIN))
1764                         return -EPERM;
1765                 mdio_write(tp->mmio_addr, data->reg_num & 0x1f, data->val_in);
1766                 return 0;
1767         }
1768         return -EOPNOTSUPP;
1769 }
1770
1771 static const struct rtl_cfg_info {
1772         void (*hw_start)(struct net_device *);
1773         unsigned int region;
1774         unsigned int align;
1775         u16 intr_event;
1776         u16 napi_event;
1777         unsigned features;
1778 } rtl_cfg_infos [] = {
1779         [RTL_CFG_0] = {
1780                 .hw_start       = rtl_hw_start_8169,
1781                 .region         = 1,
1782                 .align          = 0,
1783                 .intr_event     = SYSErr | LinkChg | RxOverflow |
1784                                   RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
1785                 .napi_event     = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
1786                 .features       = RTL_FEATURE_GMII
1787         },
1788         [RTL_CFG_1] = {
1789                 .hw_start       = rtl_hw_start_8168,
1790                 .region         = 2,
1791                 .align          = 8,
1792                 .intr_event     = SYSErr | LinkChg | RxOverflow |
1793                                   TxErr | TxOK | RxOK | RxErr,
1794                 .napi_event     = TxErr | TxOK | RxOK | RxOverflow,
1795                 .features       = RTL_FEATURE_GMII | RTL_FEATURE_MSI
1796         },
1797         [RTL_CFG_2] = {
1798                 .hw_start       = rtl_hw_start_8101,
1799                 .region         = 2,
1800                 .align          = 8,
1801                 .intr_event     = SYSErr | LinkChg | RxOverflow | PCSTimeout |
1802                                   RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
1803                 .napi_event     = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
1804                 .features       = RTL_FEATURE_MSI
1805         }
1806 };
1807
1808 /* Cfg9346_Unlock assumed. */
1809 static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
1810                             const struct rtl_cfg_info *cfg)
1811 {
1812         unsigned msi = 0;
1813         u8 cfg2;
1814
1815         cfg2 = RTL_R8(Config2) & ~MSIEnable;
1816         if (cfg->features & RTL_FEATURE_MSI) {
1817                 if (pci_enable_msi(pdev)) {
1818                         dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
1819                 } else {
1820                         cfg2 |= MSIEnable;
1821                         msi = RTL_FEATURE_MSI;
1822                 }
1823         }
1824         RTL_W8(Config2, cfg2);
1825         return msi;
1826 }
1827
1828 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
1829 {
1830         if (tp->features & RTL_FEATURE_MSI) {
1831                 pci_disable_msi(pdev);
1832                 tp->features &= ~RTL_FEATURE_MSI;
1833         }
1834 }
1835
1836 static int rtl_eeprom_read(struct pci_dev *pdev, int cap, int addr, __le32 *val)
1837 {
1838         int ret, count = 100;
1839         u16 status = 0;
1840         u32 value;
1841
1842         ret = pci_write_config_word(pdev, cap + PCI_VPD_ADDR, addr);
1843         if (ret < 0)
1844                 return ret;
1845
1846         do {
1847                 udelay(10);
1848                 ret = pci_read_config_word(pdev, cap + PCI_VPD_ADDR, &status);
1849                 if (ret < 0)
1850                         return ret;
1851         } while (!(status & PCI_VPD_ADDR_F) && --count);
1852
1853         if (!(status & PCI_VPD_ADDR_F))
1854                 return -ETIMEDOUT;
1855
1856         ret = pci_read_config_dword(pdev, cap + PCI_VPD_DATA, &value);
1857         if (ret < 0)
1858                 return ret;
1859
1860         *val = cpu_to_le32(value);
1861
1862         return 0;
1863 }
1864
1865 static void rtl_init_mac_address(struct rtl8169_private *tp,
1866                                  void __iomem *ioaddr)
1867 {
1868         struct pci_dev *pdev = tp->pci_dev;
1869         u8 cfg1;
1870         int vpd_cap;
1871         u8 mac[8];
1872         DECLARE_MAC_BUF(buf);
1873
1874         cfg1 = RTL_R8(Config1);
1875         if (!(cfg1  & VPD)) {
1876                 dprintk("VPD access not enabled, enabling\n");
1877                 RTL_W8(Cfg9346, Cfg9346_Unlock);
1878                 RTL_W8(Config1, cfg1 | VPD);
1879                 RTL_W8(Cfg9346, Cfg9346_Lock);
1880         }
1881
1882         vpd_cap = pci_find_capability(pdev, PCI_CAP_ID_VPD);
1883         if (!vpd_cap)
1884                 return;
1885
1886         /* MAC address is stored in EEPROM at offset 0x0e
1887          * Realtek says: "The VPD address does not have to be a DWORD-aligned
1888          * address as defined in the PCI 2.2 Specifications, but the VPD data
1889          * is always consecutive 4-byte data starting from the VPD address
1890          * specified."
1891          */
1892         if (rtl_eeprom_read(pdev, vpd_cap, 0x000e, (__le32*)&mac[0]) < 0 ||
1893             rtl_eeprom_read(pdev, vpd_cap, 0x0012, (__le32*)&mac[4]) < 0) {
1894                 dprintk("Reading MAC address from EEPROM failed\n");
1895                 return;
1896         }
1897
1898         dprintk("MAC address found in EEPROM: %s\n", print_mac(buf, mac));
1899
1900         /* Write MAC address */
1901         rtl_rar_set(tp, mac);
1902 }
1903
1904 static int __devinit
1905 rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1906 {
1907         const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
1908         const unsigned int region = cfg->region;
1909         struct rtl8169_private *tp;
1910         struct mii_if_info *mii;
1911         struct net_device *dev;
1912         void __iomem *ioaddr;
1913         unsigned int i;
1914         int rc;
1915
1916         if (netif_msg_drv(&debug)) {
1917                 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
1918                        MODULENAME, RTL8169_VERSION);
1919         }
1920
1921         dev = alloc_etherdev(sizeof (*tp));
1922         if (!dev) {
1923                 if (netif_msg_drv(&debug))
1924                         dev_err(&pdev->dev, "unable to alloc new ethernet\n");
1925                 rc = -ENOMEM;
1926                 goto out;
1927         }
1928
1929         SET_NETDEV_DEV(dev, &pdev->dev);
1930         tp = netdev_priv(dev);
1931         tp->dev = dev;
1932         tp->pci_dev = pdev;
1933         tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
1934
1935         mii = &tp->mii;
1936         mii->dev = dev;
1937         mii->mdio_read = rtl_mdio_read;
1938         mii->mdio_write = rtl_mdio_write;
1939         mii->phy_id_mask = 0x1f;
1940         mii->reg_num_mask = 0x1f;
1941         mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
1942
1943         /* enable device (incl. PCI PM wakeup and hotplug setup) */
1944         rc = pci_enable_device(pdev);
1945         if (rc < 0) {
1946                 if (netif_msg_probe(tp))
1947                         dev_err(&pdev->dev, "enable failure\n");
1948                 goto err_out_free_dev_1;
1949         }
1950
1951         rc = pci_set_mwi(pdev);
1952         if (rc < 0)
1953                 goto err_out_disable_2;
1954
1955         /* make sure PCI base addr 1 is MMIO */
1956         if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
1957                 if (netif_msg_probe(tp)) {
1958                         dev_err(&pdev->dev,
1959                                 "region #%d not an MMIO resource, aborting\n",
1960                                 region);
1961                 }
1962                 rc = -ENODEV;
1963                 goto err_out_mwi_3;
1964         }
1965
1966         /* check for weird/broken PCI region reporting */
1967         if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
1968                 if (netif_msg_probe(tp)) {
1969                         dev_err(&pdev->dev,
1970                                 "Invalid PCI region size(s), aborting\n");
1971                 }
1972                 rc = -ENODEV;
1973                 goto err_out_mwi_3;
1974         }
1975
1976         rc = pci_request_regions(pdev, MODULENAME);
1977         if (rc < 0) {
1978                 if (netif_msg_probe(tp))
1979                         dev_err(&pdev->dev, "could not request regions.\n");
1980                 goto err_out_mwi_3;
1981         }
1982
1983         tp->cp_cmd = PCIMulRW | RxChkSum;
1984
1985         if ((sizeof(dma_addr_t) > 4) &&
1986             !pci_set_dma_mask(pdev, DMA_64BIT_MASK) && use_dac) {
1987                 tp->cp_cmd |= PCIDAC;
1988                 dev->features |= NETIF_F_HIGHDMA;
1989         } else {
1990                 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1991                 if (rc < 0) {
1992                         if (netif_msg_probe(tp)) {
1993                                 dev_err(&pdev->dev,
1994                                         "DMA configuration failed.\n");
1995                         }
1996                         goto err_out_free_res_4;
1997                 }
1998         }
1999
2000         pci_set_master(pdev);
2001
2002         /* ioremap MMIO region */
2003         ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
2004         if (!ioaddr) {
2005                 if (netif_msg_probe(tp))
2006                         dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
2007                 rc = -EIO;
2008                 goto err_out_free_res_4;
2009         }
2010
2011         tp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
2012         if (!tp->pcie_cap && netif_msg_probe(tp))
2013                 dev_info(&pdev->dev, "no PCI Express capability\n");
2014
2015         /* Unneeded ? Don't mess with Mrs. Murphy. */
2016         rtl8169_irq_mask_and_ack(ioaddr);
2017
2018         /* Soft reset the chip. */
2019         RTL_W8(ChipCmd, CmdReset);
2020
2021         /* Check that the chip has finished the reset. */
2022         for (i = 0; i < 100; i++) {
2023                 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
2024                         break;
2025                 msleep_interruptible(1);
2026         }
2027
2028         /* Identify chip attached to board */
2029         rtl8169_get_mac_version(tp, ioaddr);
2030
2031         rtl8169_print_mac_version(tp);
2032
2033         for (i = 0; i < ARRAY_SIZE(rtl_chip_info); i++) {
2034                 if (tp->mac_version == rtl_chip_info[i].mac_version)
2035                         break;
2036         }
2037         if (i == ARRAY_SIZE(rtl_chip_info)) {
2038                 /* Unknown chip: assume array element #0, original RTL-8169 */
2039                 if (netif_msg_probe(tp)) {
2040                         dev_printk(KERN_DEBUG, &pdev->dev,
2041                                 "unknown chip version, assuming %s\n",
2042                                 rtl_chip_info[0].name);
2043                 }
2044                 i = 0;
2045         }
2046         tp->chipset = i;
2047
2048         RTL_W8(Cfg9346, Cfg9346_Unlock);
2049         RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
2050         RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
2051         if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
2052                 tp->features |= RTL_FEATURE_WOL;
2053         if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
2054                 tp->features |= RTL_FEATURE_WOL;
2055         tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
2056         RTL_W8(Cfg9346, Cfg9346_Lock);
2057
2058         if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
2059             (RTL_R8(PHYstatus) & TBI_Enable)) {
2060                 tp->set_speed = rtl8169_set_speed_tbi;
2061                 tp->get_settings = rtl8169_gset_tbi;
2062                 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
2063                 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
2064                 tp->link_ok = rtl8169_tbi_link_ok;
2065
2066                 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
2067         } else {
2068                 tp->set_speed = rtl8169_set_speed_xmii;
2069                 tp->get_settings = rtl8169_gset_xmii;
2070                 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
2071                 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
2072                 tp->link_ok = rtl8169_xmii_link_ok;
2073
2074                 dev->do_ioctl = rtl8169_ioctl;
2075         }
2076
2077         spin_lock_init(&tp->lock);
2078
2079         rtl_init_mac_address(tp, ioaddr);
2080
2081         /* Get MAC address */
2082         for (i = 0; i < MAC_ADDR_LEN; i++)
2083                 dev->dev_addr[i] = RTL_R8(MAC0 + i);
2084         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
2085
2086         dev->open = rtl8169_open;
2087         dev->hard_start_xmit = rtl8169_start_xmit;
2088         dev->get_stats = rtl8169_get_stats;
2089         SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
2090         dev->stop = rtl8169_close;
2091         dev->tx_timeout = rtl8169_tx_timeout;
2092         dev->set_multicast_list = rtl_set_rx_mode;
2093         dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
2094         dev->irq = pdev->irq;
2095         dev->base_addr = (unsigned long) ioaddr;
2096         dev->change_mtu = rtl8169_change_mtu;
2097         dev->set_mac_address = rtl_set_mac_address;
2098
2099         netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
2100
2101 #ifdef CONFIG_R8169_VLAN
2102         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
2103         dev->vlan_rx_register = rtl8169_vlan_rx_register;
2104 #endif
2105
2106 #ifdef CONFIG_NET_POLL_CONTROLLER
2107         dev->poll_controller = rtl8169_netpoll;
2108 #endif
2109
2110         tp->intr_mask = 0xffff;
2111         tp->mmio_addr = ioaddr;
2112         tp->align = cfg->align;
2113         tp->hw_start = cfg->hw_start;
2114         tp->intr_event = cfg->intr_event;
2115         tp->napi_event = cfg->napi_event;
2116
2117         init_timer(&tp->timer);
2118         tp->timer.data = (unsigned long) dev;
2119         tp->timer.function = rtl8169_phy_timer;
2120
2121         rc = register_netdev(dev);
2122         if (rc < 0)
2123                 goto err_out_msi_5;
2124
2125         pci_set_drvdata(pdev, dev);
2126
2127         if (netif_msg_probe(tp)) {
2128                 u32 xid = RTL_R32(TxConfig) & 0x7cf0f8ff;
2129
2130                 printk(KERN_INFO "%s: %s at 0x%lx, "
2131                        "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
2132                        "XID %08x IRQ %d\n",
2133                        dev->name,
2134                        rtl_chip_info[tp->chipset].name,
2135                        dev->base_addr,
2136                        dev->dev_addr[0], dev->dev_addr[1],
2137                        dev->dev_addr[2], dev->dev_addr[3],
2138                        dev->dev_addr[4], dev->dev_addr[5], xid, dev->irq);
2139         }
2140
2141         rtl8169_init_phy(dev, tp);
2142         device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
2143
2144 out:
2145         return rc;
2146
2147 err_out_msi_5:
2148         rtl_disable_msi(pdev, tp);
2149         iounmap(ioaddr);
2150 err_out_free_res_4:
2151         pci_release_regions(pdev);
2152 err_out_mwi_3:
2153         pci_clear_mwi(pdev);
2154 err_out_disable_2:
2155         pci_disable_device(pdev);
2156 err_out_free_dev_1:
2157         free_netdev(dev);
2158         goto out;
2159 }
2160
2161 static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
2162 {
2163         struct net_device *dev = pci_get_drvdata(pdev);
2164         struct rtl8169_private *tp = netdev_priv(dev);
2165
2166         flush_scheduled_work();
2167
2168         unregister_netdev(dev);
2169         rtl_disable_msi(pdev, tp);
2170         rtl8169_release_board(pdev, dev, tp->mmio_addr);
2171         pci_set_drvdata(pdev, NULL);
2172 }
2173
2174 static void rtl8169_set_rxbufsize(struct rtl8169_private *tp,
2175                                   struct net_device *dev)
2176 {
2177         unsigned int mtu = dev->mtu;
2178
2179         tp->rx_buf_sz = (mtu > RX_BUF_SIZE) ? mtu + ETH_HLEN + 8 : RX_BUF_SIZE;
2180 }
2181
2182 static int rtl8169_open(struct net_device *dev)
2183 {
2184         struct rtl8169_private *tp = netdev_priv(dev);
2185         struct pci_dev *pdev = tp->pci_dev;
2186         int retval = -ENOMEM;
2187
2188
2189         rtl8169_set_rxbufsize(tp, dev);
2190
2191         /*
2192          * Rx and Tx desscriptors needs 256 bytes alignment.
2193          * pci_alloc_consistent provides more.
2194          */
2195         tp->TxDescArray = pci_alloc_consistent(pdev, R8169_TX_RING_BYTES,
2196                                                &tp->TxPhyAddr);
2197         if (!tp->TxDescArray)
2198                 goto out;
2199
2200         tp->RxDescArray = pci_alloc_consistent(pdev, R8169_RX_RING_BYTES,
2201                                                &tp->RxPhyAddr);
2202         if (!tp->RxDescArray)
2203                 goto err_free_tx_0;
2204
2205         retval = rtl8169_init_ring(dev);
2206         if (retval < 0)
2207                 goto err_free_rx_1;
2208
2209         INIT_DELAYED_WORK(&tp->task, NULL);
2210
2211         smp_mb();
2212
2213         retval = request_irq(dev->irq, rtl8169_interrupt,
2214                              (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
2215                              dev->name, dev);
2216         if (retval < 0)
2217                 goto err_release_ring_2;
2218
2219         napi_enable(&tp->napi);
2220
2221         rtl_hw_start(dev);
2222
2223         rtl8169_request_timer(dev);
2224
2225         rtl8169_check_link_status(dev, tp, tp->mmio_addr);
2226 out:
2227         return retval;
2228
2229 err_release_ring_2:
2230         rtl8169_rx_clear(tp);
2231 err_free_rx_1:
2232         pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
2233                             tp->RxPhyAddr);
2234 err_free_tx_0:
2235         pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
2236                             tp->TxPhyAddr);
2237         goto out;
2238 }
2239
2240 static void rtl8169_hw_reset(void __iomem *ioaddr)
2241 {
2242         /* Disable interrupts */
2243         rtl8169_irq_mask_and_ack(ioaddr);
2244
2245         /* Reset the chipset */
2246         RTL_W8(ChipCmd, CmdReset);
2247
2248         /* PCI commit */
2249         RTL_R8(ChipCmd);
2250 }
2251
2252 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
2253 {
2254         void __iomem *ioaddr = tp->mmio_addr;
2255         u32 cfg = rtl8169_rx_config;
2256
2257         cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
2258         RTL_W32(RxConfig, cfg);
2259
2260         /* Set DMA burst size and Interframe Gap Time */
2261         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
2262                 (InterFrameGap << TxInterFrameGapShift));
2263 }
2264
2265 static void rtl_hw_start(struct net_device *dev)
2266 {
2267         struct rtl8169_private *tp = netdev_priv(dev);
2268         void __iomem *ioaddr = tp->mmio_addr;
2269         unsigned int i;
2270
2271         /* Soft reset the chip. */
2272         RTL_W8(ChipCmd, CmdReset);
2273
2274         /* Check that the chip has finished the reset. */
2275         for (i = 0; i < 100; i++) {
2276                 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
2277                         break;
2278                 msleep_interruptible(1);
2279         }
2280
2281         tp->hw_start(dev);
2282
2283         netif_start_queue(dev);
2284 }
2285
2286
2287 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
2288                                          void __iomem *ioaddr)
2289 {
2290         /*
2291          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
2292          * register to be written before TxDescAddrLow to work.
2293          * Switching from MMIO to I/O access fixes the issue as well.
2294          */
2295         RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
2296         RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_32BIT_MASK);
2297         RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
2298         RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_32BIT_MASK);
2299 }
2300
2301 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
2302 {
2303         u16 cmd;
2304
2305         cmd = RTL_R16(CPlusCmd);
2306         RTL_W16(CPlusCmd, cmd);
2307         return cmd;
2308 }
2309
2310 static void rtl_set_rx_max_size(void __iomem *ioaddr)
2311 {
2312         /* Low hurts. Let's disable the filtering. */
2313         RTL_W16(RxMaxSize, 16383);
2314 }
2315
2316 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
2317 {
2318         struct {
2319                 u32 mac_version;
2320                 u32 clk;
2321                 u32 val;
2322         } cfg2_info [] = {
2323                 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
2324                 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
2325                 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
2326                 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
2327         }, *p = cfg2_info;
2328         unsigned int i;
2329         u32 clk;
2330
2331         clk = RTL_R8(Config2) & PCI_Clock_66MHz;
2332         for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
2333                 if ((p->mac_version == mac_version) && (p->clk == clk)) {
2334                         RTL_W32(0x7c, p->val);
2335                         break;
2336                 }
2337         }
2338 }
2339
2340 static void rtl_hw_start_8169(struct net_device *dev)
2341 {
2342         struct rtl8169_private *tp = netdev_priv(dev);
2343         void __iomem *ioaddr = tp->mmio_addr;
2344         struct pci_dev *pdev = tp->pci_dev;
2345
2346         if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
2347                 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
2348                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
2349         }
2350
2351         RTL_W8(Cfg9346, Cfg9346_Unlock);
2352         if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
2353             (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2354             (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
2355             (tp->mac_version == RTL_GIGA_MAC_VER_04))
2356                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2357
2358         RTL_W8(EarlyTxThres, EarlyTxThld);
2359
2360         rtl_set_rx_max_size(ioaddr);
2361
2362         if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
2363             (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2364             (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
2365             (tp->mac_version == RTL_GIGA_MAC_VER_04))
2366                 rtl_set_rx_tx_config_registers(tp);
2367
2368         tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
2369
2370         if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2371             (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
2372                 dprintk("Set MAC Reg C+CR Offset 0xE0. "
2373                         "Bit-3 and bit-14 MUST be 1\n");
2374                 tp->cp_cmd |= (1 << 14);
2375         }
2376
2377         RTL_W16(CPlusCmd, tp->cp_cmd);
2378
2379         rtl8169_set_magic_reg(ioaddr, tp->mac_version);
2380
2381         /*
2382          * Undocumented corner. Supposedly:
2383          * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
2384          */
2385         RTL_W16(IntrMitigate, 0x0000);
2386
2387         rtl_set_rx_tx_desc_registers(tp, ioaddr);
2388
2389         if ((tp->mac_version != RTL_GIGA_MAC_VER_01) &&
2390             (tp->mac_version != RTL_GIGA_MAC_VER_02) &&
2391             (tp->mac_version != RTL_GIGA_MAC_VER_03) &&
2392             (tp->mac_version != RTL_GIGA_MAC_VER_04)) {
2393                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2394                 rtl_set_rx_tx_config_registers(tp);
2395         }
2396
2397         RTL_W8(Cfg9346, Cfg9346_Lock);
2398
2399         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
2400         RTL_R8(IntrMask);
2401
2402         RTL_W32(RxMissed, 0);
2403
2404         rtl_set_rx_mode(dev);
2405
2406         /* no early-rx interrupts */
2407         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
2408
2409         /* Enable all known interrupts by setting the interrupt mask. */
2410         RTL_W16(IntrMask, tp->intr_event);
2411 }
2412
2413 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
2414 {
2415         struct net_device *dev = pci_get_drvdata(pdev);
2416         struct rtl8169_private *tp = netdev_priv(dev);
2417         int cap = tp->pcie_cap;
2418
2419         if (cap) {
2420                 u16 ctl;
2421
2422                 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
2423                 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
2424                 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
2425         }
2426 }
2427
2428 static void rtl_csi_access_enable(void __iomem *ioaddr)
2429 {
2430         u32 csi;
2431
2432         csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
2433         rtl_csi_write(ioaddr, 0x070c, csi | 0x27000000);
2434 }
2435
2436 struct ephy_info {
2437         unsigned int offset;
2438         u16 mask;
2439         u16 bits;
2440 };
2441
2442 static void rtl_ephy_init(void __iomem *ioaddr, struct ephy_info *e, int len)
2443 {
2444         u16 w;
2445
2446         while (len-- > 0) {
2447                 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
2448                 rtl_ephy_write(ioaddr, e->offset, w);
2449                 e++;
2450         }
2451 }
2452
2453 static void rtl_disable_clock_request(struct pci_dev *pdev)
2454 {
2455         struct net_device *dev = pci_get_drvdata(pdev);
2456         struct rtl8169_private *tp = netdev_priv(dev);
2457         int cap = tp->pcie_cap;
2458
2459         if (cap) {
2460                 u16 ctl;
2461
2462                 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
2463                 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
2464                 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
2465         }
2466 }
2467
2468 #define R8168_CPCMD_QUIRK_MASK (\
2469         EnableBist | \
2470         Mac_dbgo_oe | \
2471         Force_half_dup | \
2472         Force_rxflow_en | \
2473         Force_txflow_en | \
2474         Cxpl_dbg_sel | \
2475         ASF | \
2476         PktCntrDisable | \
2477         Mac_dbgo_sel)
2478
2479 static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
2480 {
2481         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2482
2483         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
2484
2485         rtl_tx_performance_tweak(pdev,
2486                 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
2487 }
2488
2489 static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
2490 {
2491         rtl_hw_start_8168bb(ioaddr, pdev);
2492
2493         RTL_W8(EarlyTxThres, EarlyTxThld);
2494
2495         RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
2496 }
2497
2498 static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
2499 {
2500         RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
2501
2502         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2503
2504         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2505
2506         rtl_disable_clock_request(pdev);
2507
2508         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
2509 }
2510
2511 static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
2512 {
2513         static struct ephy_info e_info_8168cp[] = {
2514                 { 0x01, 0,      0x0001 },
2515                 { 0x02, 0x0800, 0x1000 },
2516                 { 0x03, 0,      0x0042 },
2517                 { 0x06, 0x0080, 0x0000 },
2518                 { 0x07, 0,      0x2000 }
2519         };
2520
2521         rtl_csi_access_enable(ioaddr);
2522
2523         rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
2524
2525         __rtl_hw_start_8168cp(ioaddr, pdev);
2526 }
2527
2528 static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
2529 {
2530         rtl_csi_access_enable(ioaddr);
2531
2532         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2533
2534         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2535
2536         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
2537 }
2538
2539 static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
2540 {
2541         rtl_csi_access_enable(ioaddr);
2542
2543         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2544
2545         /* Magic. */
2546         RTL_W8(DBG_REG, 0x20);
2547
2548         RTL_W8(EarlyTxThres, EarlyTxThld);
2549
2550         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2551
2552         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
2553 }
2554
2555 static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
2556 {
2557         static struct ephy_info e_info_8168c_1[] = {
2558                 { 0x02, 0x0800, 0x1000 },
2559                 { 0x03, 0,      0x0002 },
2560                 { 0x06, 0x0080, 0x0000 }
2561         };
2562
2563         rtl_csi_access_enable(ioaddr);
2564
2565         RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
2566
2567         rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
2568
2569         __rtl_hw_start_8168cp(ioaddr, pdev);
2570 }
2571
2572 static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
2573 {
2574         static struct ephy_info e_info_8168c_2[] = {
2575                 { 0x01, 0,      0x0001 },
2576                 { 0x03, 0x0400, 0x0220 }
2577         };
2578
2579         rtl_csi_access_enable(ioaddr);
2580
2581         rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
2582
2583         __rtl_hw_start_8168cp(ioaddr, pdev);
2584 }
2585
2586 static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
2587 {
2588         rtl_hw_start_8168c_2(ioaddr, pdev);
2589 }
2590
2591 static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
2592 {
2593         rtl_csi_access_enable(ioaddr);
2594
2595         __rtl_hw_start_8168cp(ioaddr, pdev);
2596 }
2597
2598 static void rtl_hw_start_8168(struct net_device *dev)
2599 {
2600         struct rtl8169_private *tp = netdev_priv(dev);
2601         void __iomem *ioaddr = tp->mmio_addr;
2602         struct pci_dev *pdev = tp->pci_dev;
2603
2604         RTL_W8(Cfg9346, Cfg9346_Unlock);
2605
2606         RTL_W8(EarlyTxThres, EarlyTxThld);
2607
2608         rtl_set_rx_max_size(ioaddr);
2609
2610         tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
2611
2612         RTL_W16(CPlusCmd, tp->cp_cmd);
2613
2614         RTL_W16(IntrMitigate, 0x5151);
2615
2616         /* Work around for RxFIFO overflow. */
2617         if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
2618                 tp->intr_event |= RxFIFOOver | PCSTimeout;
2619                 tp->intr_event &= ~RxOverflow;
2620         }
2621
2622         rtl_set_rx_tx_desc_registers(tp, ioaddr);
2623
2624         rtl_set_rx_mode(dev);
2625
2626         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
2627                 (InterFrameGap << TxInterFrameGapShift));
2628
2629         RTL_R8(IntrMask);
2630
2631         switch (tp->mac_version) {
2632         case RTL_GIGA_MAC_VER_11:
2633                 rtl_hw_start_8168bb(ioaddr, pdev);
2634         break;
2635
2636         case RTL_GIGA_MAC_VER_12:
2637         case RTL_GIGA_MAC_VER_17:
2638                 rtl_hw_start_8168bef(ioaddr, pdev);
2639         break;
2640
2641         case RTL_GIGA_MAC_VER_18:
2642                 rtl_hw_start_8168cp_1(ioaddr, pdev);
2643         break;
2644
2645         case RTL_GIGA_MAC_VER_19:
2646                 rtl_hw_start_8168c_1(ioaddr, pdev);
2647         break;
2648
2649         case RTL_GIGA_MAC_VER_20:
2650                 rtl_hw_start_8168c_2(ioaddr, pdev);
2651         break;
2652
2653         case RTL_GIGA_MAC_VER_21:
2654                 rtl_hw_start_8168c_3(ioaddr, pdev);
2655         break;
2656
2657         case RTL_GIGA_MAC_VER_22:
2658                 rtl_hw_start_8168c_4(ioaddr, pdev);
2659         break;
2660
2661         case RTL_GIGA_MAC_VER_23:
2662                 rtl_hw_start_8168cp_2(ioaddr, pdev);
2663         break;
2664
2665         case RTL_GIGA_MAC_VER_24:
2666                 rtl_hw_start_8168cp_3(ioaddr, pdev);
2667         break;
2668
2669         default:
2670                 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
2671                         dev->name, tp->mac_version);
2672         break;
2673         }
2674
2675         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2676
2677         RTL_W8(Cfg9346, Cfg9346_Lock);
2678
2679         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
2680
2681         RTL_W16(IntrMask, tp->intr_event);
2682 }
2683
2684 #define R810X_CPCMD_QUIRK_MASK (\
2685         EnableBist | \
2686         Mac_dbgo_oe | \
2687         Force_half_dup | \
2688         Force_half_dup | \
2689         Force_txflow_en | \
2690         Cxpl_dbg_sel | \
2691         ASF | \
2692         PktCntrDisable | \
2693         PCIDAC | \
2694         PCIMulRW)
2695
2696 static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
2697 {
2698         static struct ephy_info e_info_8102e_1[] = {
2699                 { 0x01, 0, 0x6e65 },
2700                 { 0x02, 0, 0x091f },
2701                 { 0x03, 0, 0xc2f9 },
2702                 { 0x06, 0, 0xafb5 },
2703                 { 0x07, 0, 0x0e00 },
2704                 { 0x19, 0, 0xec80 },
2705                 { 0x01, 0, 0x2e65 },
2706                 { 0x01, 0, 0x6e65 }
2707         };
2708         u8 cfg1;
2709
2710         rtl_csi_access_enable(ioaddr);
2711
2712         RTL_W8(DBG_REG, FIX_NAK_1);
2713
2714         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2715
2716         RTL_W8(Config1,
2717                LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
2718         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2719
2720         cfg1 = RTL_R8(Config1);
2721         if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
2722                 RTL_W8(Config1, cfg1 & ~LEDS0);
2723
2724         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
2725
2726         rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
2727 }
2728
2729 static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
2730 {
2731         rtl_csi_access_enable(ioaddr);
2732
2733         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2734
2735         RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
2736         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2737
2738         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
2739 }
2740
2741 static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
2742 {
2743         rtl_hw_start_8102e_2(ioaddr, pdev);
2744
2745         rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
2746 }
2747
2748 static void rtl_hw_start_8101(struct net_device *dev)
2749 {
2750         struct rtl8169_private *tp = netdev_priv(dev);
2751         void __iomem *ioaddr = tp->mmio_addr;
2752         struct pci_dev *pdev = tp->pci_dev;
2753
2754         if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
2755             (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
2756                 int cap = tp->pcie_cap;
2757
2758                 if (cap) {
2759                         pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
2760                                               PCI_EXP_DEVCTL_NOSNOOP_EN);
2761                 }
2762         }
2763
2764         switch (tp->mac_version) {
2765         case RTL_GIGA_MAC_VER_07:
2766                 rtl_hw_start_8102e_1(ioaddr, pdev);
2767                 break;
2768
2769         case RTL_GIGA_MAC_VER_08:
2770                 rtl_hw_start_8102e_3(ioaddr, pdev);
2771                 break;
2772
2773         case RTL_GIGA_MAC_VER_09:
2774                 rtl_hw_start_8102e_2(ioaddr, pdev);
2775                 break;
2776         }
2777
2778         RTL_W8(Cfg9346, Cfg9346_Unlock);
2779
2780         RTL_W8(EarlyTxThres, EarlyTxThld);
2781
2782         rtl_set_rx_max_size(ioaddr);
2783
2784         tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
2785
2786         RTL_W16(CPlusCmd, tp->cp_cmd);
2787
2788         RTL_W16(IntrMitigate, 0x0000);
2789
2790         rtl_set_rx_tx_desc_registers(tp, ioaddr);
2791
2792         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2793         rtl_set_rx_tx_config_registers(tp);
2794
2795         RTL_W8(Cfg9346, Cfg9346_Lock);
2796
2797         RTL_R8(IntrMask);
2798
2799         rtl_set_rx_mode(dev);
2800
2801         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2802
2803         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
2804
2805         RTL_W16(IntrMask, tp->intr_event);
2806 }
2807
2808 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
2809 {
2810         struct rtl8169_private *tp = netdev_priv(dev);
2811         int ret = 0;
2812
2813         if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
2814                 return -EINVAL;
2815
2816         dev->mtu = new_mtu;
2817
2818         if (!netif_running(dev))
2819                 goto out;
2820
2821         rtl8169_down(dev);
2822
2823         rtl8169_set_rxbufsize(tp, dev);
2824
2825         ret = rtl8169_init_ring(dev);
2826         if (ret < 0)
2827                 goto out;
2828
2829         napi_enable(&tp->napi);
2830
2831         rtl_hw_start(dev);
2832
2833         rtl8169_request_timer(dev);
2834
2835 out:
2836         return ret;
2837 }
2838
2839 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
2840 {
2841         desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
2842         desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
2843 }
2844
2845 static void rtl8169_free_rx_skb(struct rtl8169_private *tp,
2846                                 struct sk_buff **sk_buff, struct RxDesc *desc)
2847 {
2848         struct pci_dev *pdev = tp->pci_dev;
2849
2850         pci_unmap_single(pdev, le64_to_cpu(desc->addr), tp->rx_buf_sz,
2851                          PCI_DMA_FROMDEVICE);
2852         dev_kfree_skb(*sk_buff);
2853         *sk_buff = NULL;
2854         rtl8169_make_unusable_by_asic(desc);
2855 }
2856
2857 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
2858 {
2859         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
2860
2861         desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
2862 }
2863
2864 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
2865                                        u32 rx_buf_sz)
2866 {
2867         desc->addr = cpu_to_le64(mapping);
2868         wmb();
2869         rtl8169_mark_to_asic(desc, rx_buf_sz);
2870 }
2871
2872 static struct sk_buff *rtl8169_alloc_rx_skb(struct pci_dev *pdev,
2873                                             struct net_device *dev,
2874                                             struct RxDesc *desc, int rx_buf_sz,
2875                                             unsigned int align)
2876 {
2877         struct sk_buff *skb;
2878         dma_addr_t mapping;
2879         unsigned int pad;
2880
2881         pad = align ? align : NET_IP_ALIGN;
2882
2883         skb = netdev_alloc_skb(dev, rx_buf_sz + pad);
2884         if (!skb)
2885                 goto err_out;
2886
2887         skb_reserve(skb, align ? ((pad - 1) & (unsigned long)skb->data) : pad);
2888
2889         mapping = pci_map_single(pdev, skb->data, rx_buf_sz,
2890                                  PCI_DMA_FROMDEVICE);
2891
2892         rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
2893 out:
2894         return skb;
2895
2896 err_out:
2897         rtl8169_make_unusable_by_asic(desc);
2898         goto out;
2899 }
2900
2901 static void rtl8169_rx_clear(struct rtl8169_private *tp)
2902 {
2903         unsigned int i;
2904
2905         for (i = 0; i < NUM_RX_DESC; i++) {
2906                 if (tp->Rx_skbuff[i]) {
2907                         rtl8169_free_rx_skb(tp, tp->Rx_skbuff + i,
2908                                             tp->RxDescArray + i);
2909                 }
2910         }
2911 }
2912
2913 static u32 rtl8169_rx_fill(struct rtl8169_private *tp, struct net_device *dev,
2914                            u32 start, u32 end)
2915 {
2916         u32 cur;
2917
2918         for (cur = start; end - cur != 0; cur++) {
2919                 struct sk_buff *skb;
2920                 unsigned int i = cur % NUM_RX_DESC;
2921
2922                 WARN_ON((s32)(end - cur) < 0);
2923
2924                 if (tp->Rx_skbuff[i])
2925                         continue;
2926
2927                 skb = rtl8169_alloc_rx_skb(tp->pci_dev, dev,
2928                                            tp->RxDescArray + i,
2929                                            tp->rx_buf_sz, tp->align);
2930                 if (!skb)
2931                         break;
2932
2933                 tp->Rx_skbuff[i] = skb;
2934         }
2935         return cur - start;
2936 }
2937
2938 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
2939 {
2940         desc->opts1 |= cpu_to_le32(RingEnd);
2941 }
2942
2943 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
2944 {
2945         tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
2946 }
2947
2948 static int rtl8169_init_ring(struct net_device *dev)
2949 {
2950         struct rtl8169_private *tp = netdev_priv(dev);
2951
2952         rtl8169_init_ring_indexes(tp);
2953
2954         memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
2955         memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));
2956
2957         if (rtl8169_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC)
2958                 goto err_out;
2959
2960         rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
2961
2962         return 0;
2963
2964 err_out:
2965         rtl8169_rx_clear(tp);
2966         return -ENOMEM;
2967 }
2968
2969 static void rtl8169_unmap_tx_skb(struct pci_dev *pdev, struct ring_info *tx_skb,
2970                                  struct TxDesc *desc)
2971 {
2972         unsigned int len = tx_skb->len;
2973
2974         pci_unmap_single(pdev, le64_to_cpu(desc->addr), len, PCI_DMA_TODEVICE);
2975         desc->opts1 = 0x00;
2976         desc->opts2 = 0x00;
2977         desc->addr = 0x00;
2978         tx_skb->len = 0;
2979 }
2980
2981 static void rtl8169_tx_clear(struct rtl8169_private *tp)
2982 {
2983         unsigned int i;
2984
2985         for (i = tp->dirty_tx; i < tp->dirty_tx + NUM_TX_DESC; i++) {
2986                 unsigned int entry = i % NUM_TX_DESC;
2987                 struct ring_info *tx_skb = tp->tx_skb + entry;
2988                 unsigned int len = tx_skb->len;
2989
2990                 if (len) {
2991                         struct sk_buff *skb = tx_skb->skb;
2992
2993                         rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb,
2994                                              tp->TxDescArray + entry);
2995                         if (skb) {
2996                                 dev_kfree_skb(skb);
2997                                 tx_skb->skb = NULL;
2998                         }
2999                         tp->dev->stats.tx_dropped++;
3000                 }
3001         }
3002         tp->cur_tx = tp->dirty_tx = 0;
3003 }
3004
3005 static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
3006 {
3007         struct rtl8169_private *tp = netdev_priv(dev);
3008
3009         PREPARE_DELAYED_WORK(&tp->task, task);
3010         schedule_delayed_work(&tp->task, 4);
3011 }
3012
3013 static void rtl8169_wait_for_quiescence(struct net_device *dev)
3014 {
3015         struct rtl8169_private *tp = netdev_priv(dev);
3016         void __iomem *ioaddr = tp->mmio_addr;
3017
3018         synchronize_irq(dev->irq);
3019
3020         /* Wait for any pending NAPI task to complete */
3021         napi_disable(&tp->napi);
3022
3023         rtl8169_irq_mask_and_ack(ioaddr);
3024
3025         tp->intr_mask = 0xffff;
3026         RTL_W16(IntrMask, tp->intr_event);
3027         napi_enable(&tp->napi);
3028 }
3029
3030 static void rtl8169_reinit_task(struct work_struct *work)
3031 {
3032         struct rtl8169_private *tp =
3033                 container_of(work, struct rtl8169_private, task.work);
3034         struct net_device *dev = tp->dev;
3035         int ret;
3036
3037         rtnl_lock();
3038
3039         if (!netif_running(dev))
3040                 goto out_unlock;
3041
3042         rtl8169_wait_for_quiescence(dev);
3043         rtl8169_close(dev);
3044
3045         ret = rtl8169_open(dev);
3046         if (unlikely(ret < 0)) {
3047                 if (net_ratelimit() && netif_msg_drv(tp)) {
3048                         printk(KERN_ERR PFX "%s: reinit failure (status = %d)."
3049                                " Rescheduling.\n", dev->name, ret);
3050                 }
3051                 rtl8169_schedule_work(dev, rtl8169_reinit_task);
3052         }
3053
3054 out_unlock:
3055         rtnl_unlock();
3056 }
3057
3058 static void rtl8169_reset_task(struct work_struct *work)
3059 {
3060         struct rtl8169_private *tp =
3061                 container_of(work, struct rtl8169_private, task.work);
3062         struct net_device *dev = tp->dev;
3063
3064         rtnl_lock();
3065
3066         if (!netif_running(dev))
3067                 goto out_unlock;
3068
3069         rtl8169_wait_for_quiescence(dev);
3070
3071         rtl8169_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0);
3072         rtl8169_tx_clear(tp);
3073
3074         if (tp->dirty_rx == tp->cur_rx) {
3075                 rtl8169_init_ring_indexes(tp);
3076                 rtl_hw_start(dev);
3077                 netif_wake_queue(dev);
3078                 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
3079         } else {
3080                 if (net_ratelimit() && netif_msg_intr(tp)) {
3081                         printk(KERN_EMERG PFX "%s: Rx buffers shortage\n",
3082                                dev->name);
3083                 }
3084                 rtl8169_schedule_work(dev, rtl8169_reset_task);
3085         }
3086
3087 out_unlock:
3088         rtnl_unlock();
3089 }
3090
3091 static void rtl8169_tx_timeout(struct net_device *dev)
3092 {
3093         struct rtl8169_private *tp = netdev_priv(dev);
3094
3095         rtl8169_hw_reset(tp->mmio_addr);
3096
3097         /* Let's wait a bit while any (async) irq lands on */
3098         rtl8169_schedule_work(dev, rtl8169_reset_task);
3099 }
3100
3101 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
3102                               u32 opts1)
3103 {
3104         struct skb_shared_info *info = skb_shinfo(skb);
3105         unsigned int cur_frag, entry;
3106         struct TxDesc * uninitialized_var(txd);
3107
3108         entry = tp->cur_tx;
3109         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
3110                 skb_frag_t *frag = info->frags + cur_frag;
3111                 dma_addr_t mapping;
3112                 u32 status, len;
3113                 void *addr;
3114
3115                 entry = (entry + 1) % NUM_TX_DESC;
3116
3117                 txd = tp->TxDescArray + entry;
3118                 len = frag->size;
3119                 addr = ((void *) page_address(frag->page)) + frag->page_offset;
3120                 mapping = pci_map_single(tp->pci_dev, addr, len, PCI_DMA_TODEVICE);
3121
3122                 /* anti gcc 2.95.3 bugware (sic) */
3123                 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
3124
3125                 txd->opts1 = cpu_to_le32(status);
3126                 txd->addr = cpu_to_le64(mapping);
3127
3128                 tp->tx_skb[entry].len = len;
3129         }
3130
3131         if (cur_frag) {
3132                 tp->tx_skb[entry].skb = skb;
3133                 txd->opts1 |= cpu_to_le32(LastFrag);
3134         }
3135
3136         return cur_frag;
3137 }
3138
3139 static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
3140 {
3141         if (dev->features & NETIF_F_TSO) {
3142                 u32 mss = skb_shinfo(skb)->gso_size;
3143
3144                 if (mss)
3145                         return LargeSend | ((mss & MSSMask) << MSSShift);
3146         }
3147         if (skb->ip_summed == CHECKSUM_PARTIAL) {
3148                 const struct iphdr *ip = ip_hdr(skb);
3149
3150                 if (ip->protocol == IPPROTO_TCP)
3151                         return IPCS | TCPCS;
3152                 else if (ip->protocol == IPPROTO_UDP)
3153                         return IPCS | UDPCS;
3154                 WARN_ON(1);     /* we need a WARN() */
3155         }
3156         return 0;
3157 }
3158
3159 static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev)
3160 {
3161         struct rtl8169_private *tp = netdev_priv(dev);
3162         unsigned int frags, entry = tp->cur_tx % NUM_TX_DESC;
3163         struct TxDesc *txd = tp->TxDescArray + entry;
3164         void __iomem *ioaddr = tp->mmio_addr;
3165         dma_addr_t mapping;
3166         u32 status, len;
3167         u32 opts1;
3168         int ret = NETDEV_TX_OK;
3169
3170         if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
3171                 if (netif_msg_drv(tp)) {
3172                         printk(KERN_ERR
3173                                "%s: BUG! Tx Ring full when queue awake!\n",
3174                                dev->name);
3175                 }
3176                 goto err_stop;
3177         }
3178
3179         if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
3180                 goto err_stop;
3181
3182         opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
3183
3184         frags = rtl8169_xmit_frags(tp, skb, opts1);
3185         if (frags) {
3186                 len = skb_headlen(skb);
3187                 opts1 |= FirstFrag;
3188         } else {
3189                 len = skb->len;
3190
3191                 if (unlikely(len < ETH_ZLEN)) {
3192                         if (skb_padto(skb, ETH_ZLEN))
3193                                 goto err_update_stats;
3194                         len = ETH_ZLEN;
3195                 }
3196
3197                 opts1 |= FirstFrag | LastFrag;
3198                 tp->tx_skb[entry].skb = skb;
3199         }
3200
3201         mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
3202
3203         tp->tx_skb[entry].len = len;
3204         txd->addr = cpu_to_le64(mapping);
3205         txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
3206
3207         wmb();
3208
3209         /* anti gcc 2.95.3 bugware (sic) */
3210         status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
3211         txd->opts1 = cpu_to_le32(status);
3212
3213         dev->trans_start = jiffies;
3214
3215         tp->cur_tx += frags + 1;
3216
3217         smp_wmb();
3218
3219         RTL_W8(TxPoll, NPQ);    /* set polling bit */
3220
3221         if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
3222                 netif_stop_queue(dev);
3223                 smp_rmb();
3224                 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
3225                         netif_wake_queue(dev);
3226         }
3227
3228 out:
3229         return ret;
3230
3231 err_stop:
3232         netif_stop_queue(dev);
3233         ret = NETDEV_TX_BUSY;
3234 err_update_stats:
3235         dev->stats.tx_dropped++;
3236         goto out;
3237 }
3238
3239 static void rtl8169_pcierr_interrupt(struct net_device *dev)
3240 {
3241         struct rtl8169_private *tp = netdev_priv(dev);
3242         struct pci_dev *pdev = tp->pci_dev;
3243         void __iomem *ioaddr = tp->mmio_addr;
3244         u16 pci_status, pci_cmd;
3245
3246         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
3247         pci_read_config_word(pdev, PCI_STATUS, &pci_status);
3248
3249         if (netif_msg_intr(tp)) {
3250                 printk(KERN_ERR
3251                        "%s: PCI error (cmd = 0x%04x, status = 0x%04x).\n",
3252                        dev->name, pci_cmd, pci_status);
3253         }
3254
3255         /*
3256          * The recovery sequence below admits a very elaborated explanation:
3257          * - it seems to work;
3258          * - I did not see what else could be done;
3259          * - it makes iop3xx happy.
3260          *
3261          * Feel free to adjust to your needs.
3262          */
3263         if (pdev->broken_parity_status)
3264                 pci_cmd &= ~PCI_COMMAND_PARITY;
3265         else
3266                 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
3267
3268         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
3269
3270         pci_write_config_word(pdev, PCI_STATUS,
3271                 pci_status & (PCI_STATUS_DETECTED_PARITY |
3272                 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
3273                 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
3274
3275         /* The infamous DAC f*ckup only happens at boot time */
3276         if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
3277                 if (netif_msg_intr(tp))
3278                         printk(KERN_INFO "%s: disabling PCI DAC.\n", dev->name);
3279                 tp->cp_cmd &= ~PCIDAC;
3280                 RTL_W16(CPlusCmd, tp->cp_cmd);
3281                 dev->features &= ~NETIF_F_HIGHDMA;
3282         }
3283
3284         rtl8169_hw_reset(ioaddr);
3285
3286         rtl8169_schedule_work(dev, rtl8169_reinit_task);
3287 }
3288
3289 static void rtl8169_tx_interrupt(struct net_device *dev,
3290                                  struct rtl8169_private *tp,
3291                                  void __iomem *ioaddr)
3292 {
3293         unsigned int dirty_tx, tx_left;
3294
3295         dirty_tx = tp->dirty_tx;
3296         smp_rmb();
3297         tx_left = tp->cur_tx - dirty_tx;
3298
3299         while (tx_left > 0) {
3300                 unsigned int entry = dirty_tx % NUM_TX_DESC;
3301                 struct ring_info *tx_skb = tp->tx_skb + entry;
3302                 u32 len = tx_skb->len;
3303                 u32 status;
3304
3305                 rmb();
3306                 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
3307                 if (status & DescOwn)
3308                         break;
3309
3310                 dev->stats.tx_bytes += len;
3311                 dev->stats.tx_packets++;
3312
3313                 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, tp->TxDescArray + entry);
3314
3315                 if (status & LastFrag) {
3316                         dev_kfree_skb_irq(tx_skb->skb);
3317                         tx_skb->skb = NULL;
3318                 }
3319                 dirty_tx++;
3320                 tx_left--;
3321         }
3322
3323         if (tp->dirty_tx != dirty_tx) {
3324                 tp->dirty_tx = dirty_tx;
3325                 smp_wmb();
3326                 if (netif_queue_stopped(dev) &&
3327                     (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
3328                         netif_wake_queue(dev);
3329                 }
3330                 /*
3331                  * 8168 hack: TxPoll requests are lost when the Tx packets are
3332                  * too close. Let's kick an extra TxPoll request when a burst
3333                  * of start_xmit activity is detected (if it is not detected,
3334                  * it is slow enough). -- FR
3335                  */
3336                 smp_rmb();
3337                 if (tp->cur_tx != dirty_tx)
3338                         RTL_W8(TxPoll, NPQ);
3339         }
3340 }
3341
3342 static inline int rtl8169_fragmented_frame(u32 status)
3343 {
3344         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
3345 }
3346
3347 static inline void rtl8169_rx_csum(struct sk_buff *skb, struct RxDesc *desc)
3348 {
3349         u32 opts1 = le32_to_cpu(desc->opts1);
3350         u32 status = opts1 & RxProtoMask;
3351
3352         if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
3353             ((status == RxProtoUDP) && !(opts1 & UDPFail)) ||
3354             ((status == RxProtoIP) && !(opts1 & IPFail)))
3355                 skb->ip_summed = CHECKSUM_UNNECESSARY;
3356         else
3357                 skb->ip_summed = CHECKSUM_NONE;
3358 }
3359
3360 static inline bool rtl8169_try_rx_copy(struct sk_buff **sk_buff,
3361                                        struct rtl8169_private *tp, int pkt_size,
3362                                        dma_addr_t addr)
3363 {
3364         struct sk_buff *skb;
3365         bool done = false;
3366
3367         if (pkt_size >= rx_copybreak)
3368                 goto out;
3369
3370         skb = netdev_alloc_skb(tp->dev, pkt_size + NET_IP_ALIGN);
3371         if (!skb)
3372                 goto out;
3373
3374         pci_dma_sync_single_for_cpu(tp->pci_dev, addr, pkt_size,
3375                                     PCI_DMA_FROMDEVICE);
3376         skb_reserve(skb, NET_IP_ALIGN);
3377         skb_copy_from_linear_data(*sk_buff, skb->data, pkt_size);
3378         *sk_buff = skb;
3379         done = true;
3380 out:
3381         return done;
3382 }
3383
3384 static int rtl8169_rx_interrupt(struct net_device *dev,
3385                                 struct rtl8169_private *tp,
3386                                 void __iomem *ioaddr, u32 budget)
3387 {
3388         unsigned int cur_rx, rx_left;
3389         unsigned int delta, count;
3390
3391         cur_rx = tp->cur_rx;
3392         rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
3393         rx_left = min(rx_left, budget);
3394
3395         for (; rx_left > 0; rx_left--, cur_rx++) {
3396                 unsigned int entry = cur_rx % NUM_RX_DESC;
3397                 struct RxDesc *desc = tp->RxDescArray + entry;
3398                 u32 status;
3399
3400                 rmb();
3401                 status = le32_to_cpu(desc->opts1);
3402
3403                 if (status & DescOwn)
3404                         break;
3405                 if (unlikely(status & RxRES)) {
3406                         if (netif_msg_rx_err(tp)) {
3407                                 printk(KERN_INFO
3408                                        "%s: Rx ERROR. status = %08x\n",
3409                                        dev->name, status);
3410                         }
3411                         dev->stats.rx_errors++;
3412                         if (status & (RxRWT | RxRUNT))
3413                                 dev->stats.rx_length_errors++;
3414                         if (status & RxCRC)
3415                                 dev->stats.rx_crc_errors++;
3416                         if (status & RxFOVF) {
3417                                 rtl8169_schedule_work(dev, rtl8169_reset_task);
3418                                 dev->stats.rx_fifo_errors++;
3419                         }
3420                         rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
3421                 } else {
3422                         struct sk_buff *skb = tp->Rx_skbuff[entry];
3423                         dma_addr_t addr = le64_to_cpu(desc->addr);
3424                         int pkt_size = (status & 0x00001FFF) - 4;
3425                         struct pci_dev *pdev = tp->pci_dev;
3426
3427                         /*
3428                          * The driver does not support incoming fragmented
3429                          * frames. They are seen as a symptom of over-mtu
3430                          * sized frames.
3431                          */
3432                         if (unlikely(rtl8169_fragmented_frame(status))) {
3433                                 dev->stats.rx_dropped++;
3434                                 dev->stats.rx_length_errors++;
3435                                 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
3436                                 continue;
3437                         }
3438
3439                         rtl8169_rx_csum(skb, desc);
3440
3441                         if (rtl8169_try_rx_copy(&skb, tp, pkt_size, addr)) {
3442                                 pci_dma_sync_single_for_device(pdev, addr,
3443                                         pkt_size, PCI_DMA_FROMDEVICE);
3444                                 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
3445                         } else {
3446                                 pci_unmap_single(pdev, addr, tp->rx_buf_sz,
3447                                                  PCI_DMA_FROMDEVICE);
3448                                 tp->Rx_skbuff[entry] = NULL;
3449                         }
3450
3451                         skb_put(skb, pkt_size);
3452                         skb->protocol = eth_type_trans(skb, dev);
3453
3454                         if (rtl8169_rx_vlan_skb(tp, desc, skb) < 0)
3455                                 netif_receive_skb(skb);
3456
3457                         dev->last_rx = jiffies;
3458                         dev->stats.rx_bytes += pkt_size;
3459                         dev->stats.rx_packets++;
3460                 }
3461
3462                 /* Work around for AMD plateform. */
3463                 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
3464                     (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
3465                         desc->opts2 = 0;
3466                         cur_rx++;
3467                 }
3468         }
3469
3470         count = cur_rx - tp->cur_rx;
3471         tp->cur_rx = cur_rx;
3472
3473         delta = rtl8169_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx);
3474         if (!delta && count && netif_msg_intr(tp))
3475                 printk(KERN_INFO "%s: no Rx buffer allocated\n", dev->name);
3476         tp->dirty_rx += delta;
3477
3478         /*
3479          * FIXME: until there is periodic timer to try and refill the ring,
3480          * a temporary shortage may definitely kill the Rx process.
3481          * - disable the asic to try and avoid an overflow and kick it again
3482          *   after refill ?
3483          * - how do others driver handle this condition (Uh oh...).
3484          */
3485         if ((tp->dirty_rx + NUM_RX_DESC == tp->cur_rx) && netif_msg_intr(tp))
3486                 printk(KERN_EMERG "%s: Rx buffers exhausted\n", dev->name);
3487
3488         return count;
3489 }
3490
3491 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
3492 {
3493         struct net_device *dev = dev_instance;
3494         struct rtl8169_private *tp = netdev_priv(dev);
3495         void __iomem *ioaddr = tp->mmio_addr;
3496         int handled = 0;
3497         int status;
3498
3499         status = RTL_R16(IntrStatus);
3500
3501         /* hotplug/major error/no more work/shared irq */
3502         if ((status == 0xffff) || !status)
3503                 goto out;
3504
3505         handled = 1;
3506
3507         if (unlikely(!netif_running(dev))) {
3508                 rtl8169_asic_down(ioaddr);
3509                 goto out;
3510         }
3511
3512         status &= tp->intr_mask;
3513         RTL_W16(IntrStatus,
3514                 (status & RxFIFOOver) ? (status | RxOverflow) : status);
3515
3516         if (!(status & tp->intr_event))
3517                 goto out;
3518
3519         /* Work around for rx fifo overflow */
3520         if (unlikely(status & RxFIFOOver) &&
3521             (tp->mac_version == RTL_GIGA_MAC_VER_11)) {
3522                 netif_stop_queue(dev);
3523                 rtl8169_tx_timeout(dev);
3524                 goto out;
3525         }
3526
3527         if (unlikely(status & SYSErr)) {
3528                 rtl8169_pcierr_interrupt(dev);
3529                 goto out;
3530         }
3531
3532         if (status & LinkChg)
3533                 rtl8169_check_link_status(dev, tp, ioaddr);
3534
3535         if (status & tp->napi_event) {
3536                 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
3537                 tp->intr_mask = ~tp->napi_event;
3538
3539                 if (likely(netif_rx_schedule_prep(dev, &tp->napi)))
3540                         __netif_rx_schedule(dev, &tp->napi);
3541                 else if (netif_msg_intr(tp)) {
3542                         printk(KERN_INFO "%s: interrupt %04x in poll\n",
3543                                dev->name, status);
3544                 }
3545         }
3546 out:
3547         return IRQ_RETVAL(handled);
3548 }
3549
3550 static int rtl8169_poll(struct napi_struct *napi, int budget)
3551 {
3552         struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
3553         struct net_device *dev = tp->dev;
3554         void __iomem *ioaddr = tp->mmio_addr;
3555         int work_done;
3556
3557         work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
3558         rtl8169_tx_interrupt(dev, tp, ioaddr);
3559
3560         if (work_done < budget) {
3561                 netif_rx_complete(dev, napi);
3562                 tp->intr_mask = 0xffff;
3563                 /*
3564                  * 20040426: the barrier is not strictly required but the
3565                  * behavior of the irq handler could be less predictable
3566                  * without it. Btw, the lack of flush for the posted pci
3567                  * write is safe - FR
3568                  */
3569                 smp_wmb();
3570                 RTL_W16(IntrMask, tp->intr_event);
3571         }
3572
3573         return work_done;
3574 }
3575
3576 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
3577 {
3578         struct rtl8169_private *tp = netdev_priv(dev);
3579
3580         if (tp->mac_version > RTL_GIGA_MAC_VER_06)
3581                 return;
3582
3583         dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
3584         RTL_W32(RxMissed, 0);
3585 }
3586
3587 static void rtl8169_down(struct net_device *dev)
3588 {
3589         struct rtl8169_private *tp = netdev_priv(dev);
3590         void __iomem *ioaddr = tp->mmio_addr;
3591         unsigned int intrmask;
3592
3593         rtl8169_delete_timer(dev);
3594
3595         netif_stop_queue(dev);
3596
3597         napi_disable(&tp->napi);
3598
3599 core_down:
3600         spin_lock_irq(&tp->lock);
3601
3602         rtl8169_asic_down(ioaddr);
3603
3604         rtl8169_rx_missed(dev, ioaddr);
3605
3606         spin_unlock_irq(&tp->lock);
3607
3608         synchronize_irq(dev->irq);
3609
3610         /* Give a racing hard_start_xmit a few cycles to complete. */
3611         synchronize_sched();  /* FIXME: should this be synchronize_irq()? */
3612
3613         /*
3614          * And now for the 50k$ question: are IRQ disabled or not ?
3615          *
3616          * Two paths lead here:
3617          * 1) dev->close
3618          *    -> netif_running() is available to sync the current code and the
3619          *       IRQ handler. See rtl8169_interrupt for details.
3620          * 2) dev->change_mtu
3621          *    -> rtl8169_poll can not be issued again and re-enable the
3622          *       interruptions. Let's simply issue the IRQ down sequence again.
3623          *
3624          * No loop if hotpluged or major error (0xffff).
3625          */
3626         intrmask = RTL_R16(IntrMask);
3627         if (intrmask && (intrmask != 0xffff))
3628                 goto core_down;
3629
3630         rtl8169_tx_clear(tp);
3631
3632         rtl8169_rx_clear(tp);
3633 }
3634
3635 static int rtl8169_close(struct net_device *dev)
3636 {
3637         struct rtl8169_private *tp = netdev_priv(dev);
3638         struct pci_dev *pdev = tp->pci_dev;
3639
3640         rtl8169_down(dev);
3641
3642         free_irq(dev->irq, dev);
3643
3644         pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
3645                             tp->RxPhyAddr);
3646         pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
3647                             tp->TxPhyAddr);
3648         tp->TxDescArray = NULL;
3649         tp->RxDescArray = NULL;
3650
3651         return 0;
3652 }
3653
3654 static void rtl_set_rx_mode(struct net_device *dev)
3655 {
3656         struct rtl8169_private *tp = netdev_priv(dev);
3657         void __iomem *ioaddr = tp->mmio_addr;
3658         unsigned long flags;
3659         u32 mc_filter[2];       /* Multicast hash filter */
3660         int rx_mode;
3661         u32 tmp = 0;
3662
3663         if (dev->flags & IFF_PROMISC) {
3664                 /* Unconditionally log net taps. */
3665                 if (netif_msg_link(tp)) {
3666                         printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n",
3667                                dev->name);
3668                 }
3669                 rx_mode =
3670                     AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
3671                     AcceptAllPhys;
3672                 mc_filter[1] = mc_filter[0] = 0xffffffff;
3673         } else if ((dev->mc_count > multicast_filter_limit)
3674                    || (dev->flags & IFF_ALLMULTI)) {
3675                 /* Too many to filter perfectly -- accept all multicasts. */
3676                 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
3677                 mc_filter[1] = mc_filter[0] = 0xffffffff;
3678         } else {
3679                 struct dev_mc_list *mclist;
3680                 unsigned int i;
3681
3682                 rx_mode = AcceptBroadcast | AcceptMyPhys;
3683                 mc_filter[1] = mc_filter[0] = 0;
3684                 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
3685                      i++, mclist = mclist->next) {
3686                         int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
3687                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
3688                         rx_mode |= AcceptMulticast;
3689                 }
3690         }
3691
3692         spin_lock_irqsave(&tp->lock, flags);
3693
3694         tmp = rtl8169_rx_config | rx_mode |
3695               (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
3696
3697         if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
3698                 u32 data = mc_filter[0];
3699
3700                 mc_filter[0] = swab32(mc_filter[1]);
3701                 mc_filter[1] = swab32(data);
3702         }
3703
3704         RTL_W32(MAR0 + 0, mc_filter[0]);
3705         RTL_W32(MAR0 + 4, mc_filter[1]);
3706
3707         RTL_W32(RxConfig, tmp);
3708
3709         spin_unlock_irqrestore(&tp->lock, flags);
3710 }
3711
3712 /**
3713  *  rtl8169_get_stats - Get rtl8169 read/write statistics
3714  *  @dev: The Ethernet Device to get statistics for
3715  *
3716  *  Get TX/RX statistics for rtl8169
3717  */
3718 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
3719 {
3720         struct rtl8169_private *tp = netdev_priv(dev);
3721         void __iomem *ioaddr = tp->mmio_addr;
3722         unsigned long flags;
3723
3724         if (netif_running(dev)) {
3725                 spin_lock_irqsave(&tp->lock, flags);
3726                 rtl8169_rx_missed(dev, ioaddr);
3727                 spin_unlock_irqrestore(&tp->lock, flags);
3728         }
3729
3730         return &dev->stats;
3731 }
3732
3733 #ifdef CONFIG_PM
3734
3735 static int rtl8169_suspend(struct pci_dev *pdev, pm_message_t state)
3736 {
3737         struct net_device *dev = pci_get_drvdata(pdev);
3738         struct rtl8169_private *tp = netdev_priv(dev);
3739         void __iomem *ioaddr = tp->mmio_addr;
3740
3741         if (!netif_running(dev))
3742                 goto out_pci_suspend;
3743
3744         netif_device_detach(dev);
3745         netif_stop_queue(dev);
3746
3747         spin_lock_irq(&tp->lock);
3748
3749         rtl8169_asic_down(ioaddr);
3750
3751         rtl8169_rx_missed(dev, ioaddr);
3752
3753         spin_unlock_irq(&tp->lock);
3754
3755 out_pci_suspend:
3756         pci_save_state(pdev);
3757         pci_enable_wake(pdev, pci_choose_state(pdev, state),
3758                 (tp->features & RTL_FEATURE_WOL) ? 1 : 0);
3759         pci_set_power_state(pdev, pci_choose_state(pdev, state));
3760
3761         return 0;
3762 }
3763
3764 static int rtl8169_resume(struct pci_dev *pdev)
3765 {
3766         struct net_device *dev = pci_get_drvdata(pdev);
3767
3768         pci_set_power_state(pdev, PCI_D0);
3769         pci_restore_state(pdev);
3770         pci_enable_wake(pdev, PCI_D0, 0);
3771
3772         if (!netif_running(dev))
3773                 goto out;
3774
3775         netif_device_attach(dev);
3776
3777         rtl8169_schedule_work(dev, rtl8169_reset_task);
3778 out:
3779         return 0;
3780 }
3781
3782 #endif /* CONFIG_PM */
3783
3784 static struct pci_driver rtl8169_pci_driver = {
3785         .name           = MODULENAME,
3786         .id_table       = rtl8169_pci_tbl,
3787         .probe          = rtl8169_init_one,
3788         .remove         = __devexit_p(rtl8169_remove_one),
3789 #ifdef CONFIG_PM
3790         .suspend        = rtl8169_suspend,
3791         .resume         = rtl8169_resume,
3792 #endif
3793 };
3794
3795 static int __init rtl8169_init_module(void)
3796 {
3797         return pci_register_driver(&rtl8169_pci_driver);
3798 }
3799
3800 static void __exit rtl8169_cleanup_module(void)
3801 {
3802         pci_unregister_driver(&rtl8169_pci_driver);
3803 }
3804
3805 module_init(rtl8169_init_module);
3806 module_exit(rtl8169_cleanup_module);