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   1 /*
   2  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
   3  *
   4  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
   5  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
   6  * Copyright (c) a lot of people too. Please respect their work.
   7  *
   8  * See MAINTAINERS file for support contact information.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/moduleparam.h>
  13 #include <linux/pci.h>
  14 #include <linux/netdevice.h>
  15 #include <linux/etherdevice.h>
  16 #include <linux/delay.h>
  17 #include <linux/ethtool.h>
  18 #include <linux/mii.h>
  19 #include <linux/if_vlan.h>
  20 #include <linux/crc32.h>
  21 #include <linux/in.h>
  22 #include <linux/ip.h>
  23 #include <linux/tcp.h>
  24 #include <linux/init.h>
  25 #include <linux/dma-mapping.h>
  26
  27 #include <asm/system.h>
  28 #include <asm/io.h>
  29 #include <asm/irq.h>
  30
  31 #ifdef CONFIG_R8169_NAPI
  32 #define NAPI_SUFFIX     "-NAPI"
  33 #else
  34 #define NAPI_SUFFIX     ""
  35 #endif
  36
  37 #define RTL8169_VERSION "2.2LK" NAPI_SUFFIX
  38 #define MODULENAME "r8169"
  39 #define PFX MODULENAME ": "
  40
  41 #ifdef RTL8169_DEBUG
  42 #define assert(expr) \
  43         if (!(expr)) {                                  \
  44                 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
  45                 #expr,__FILE__,__FUNCTION__,__LINE__);          \
  46         }
  47 #define dprintk(fmt, args...) \
  48         do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
  49 #else
  50 #define assert(expr) do {} while (0)
  51 #define dprintk(fmt, args...)   do {} while (0)
  52 #endif /* RTL8169_DEBUG */
  53
  54 #define R8169_MSG_DEFAULT \
  55         (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
  56
  57 #define TX_BUFFS_AVAIL(tp) \
  58         (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
  59
  60 #ifdef CONFIG_R8169_NAPI
  61 #define rtl8169_rx_skb                  netif_receive_skb
  62 #define rtl8169_rx_hwaccel_skb          vlan_hwaccel_receive_skb
  63 #define rtl8169_rx_quota(count, quota)  min(count, quota)
  64 #else
  65 #define rtl8169_rx_skb                  netif_rx
  66 #define rtl8169_rx_hwaccel_skb          vlan_hwaccel_rx
  67 #define rtl8169_rx_quota(count, quota)  count
  68 #endif
  69
  70 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
  71 static const int max_interrupt_work = 20;
  72
  73 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  74    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
  75 static const int multicast_filter_limit = 32;
  76
  77 /* MAC address length */
  78 #define MAC_ADDR_LEN    6
  79
  80 #define RX_FIFO_THRESH  7       /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
  81 #define RX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
  82 #define TX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
  83 #define EarlyTxThld     0x3F    /* 0x3F means NO early transmit */
  84 #define RxPacketMaxSize 0x3FE8  /* 16K - 1 - ETH_HLEN - VLAN - CRC... */
  85 #define SafeMtu         0x1c20  /* ... actually life sucks beyond ~7k */
  86 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
  87
  88 #define R8169_REGS_SIZE         256
  89 #define R8169_NAPI_WEIGHT       64
  90 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
  91 #define NUM_RX_DESC     256     /* Number of Rx descriptor registers */
  92 #define RX_BUF_SIZE     1536    /* Rx Buffer size */
  93 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
  94 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
  95
  96 #define RTL8169_TX_TIMEOUT      (6*HZ)
  97 #define RTL8169_PHY_TIMEOUT     (10*HZ)
  98
  99 /* write/read MMIO register */
 100 #define RTL_W8(reg, val8)       writeb ((val8), ioaddr + (reg))
 101 #define RTL_W16(reg, val16)     writew ((val16), ioaddr + (reg))
 102 #define RTL_W32(reg, val32)     writel ((val32), ioaddr + (reg))
 103 #define RTL_R8(reg)             readb (ioaddr + (reg))
 104 #define RTL_R16(reg)            readw (ioaddr + (reg))
 105 #define RTL_R32(reg)            ((unsigned long) readl (ioaddr + (reg)))
 106
 107 enum mac_version {
 108         RTL_GIGA_MAC_VER_01 = 0x01, // 8169
 109         RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
 110         RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
 111         RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
 112         RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
 113         RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
 114         RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
 115         RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be
 116         RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb
 117         RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ?
 118         RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ?
 119         RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec
 120         RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf
 121         RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP
 122         RTL_GIGA_MAC_VER_19 = 0x13, // 8168C
 123         RTL_GIGA_MAC_VER_20 = 0x14  // 8168C
 124 };
 125
 126 #define _R(NAME,MAC,MASK) \
 127         { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
 128
 129 static const struct {
 130         const char *name;
 131         u8 mac_version;
 132         u32 RxConfigMask;       /* Clears the bits supported by this chip */
 133 } rtl_chip_info[] = {
 134         _R("RTL8169",           RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
 135         _R("RTL8169s",          RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
 136         _R("RTL8110s",          RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
 137         _R("RTL8169sb/8110sb",  RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
 138         _R("RTL8169sc/8110sc",  RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
 139         _R("RTL8169sc/8110sc",  RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
 140         _R("RTL8168b/8111b",    RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
 141         _R("RTL8168b/8111b",    RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
 142         _R("RTL8101e",          RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
 143         _R("RTL8100e",          RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
 144         _R("RTL8100e",          RTL_GIGA_MAC_VER_15, 0xff7e1880), // PCI-E 8139
 145         _R("RTL8168b/8111b",    RTL_GIGA_MAC_VER_17, 0xff7e1880), // PCI-E
 146         _R("RTL8101e",          RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E
 147         _R("RTL8168cp/8111cp",  RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E
 148         _R("RTL8168c/8111c",    RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E
 149         _R("RTL8168c/8111c",    RTL_GIGA_MAC_VER_20, 0xff7e1880)  // PCI-E
 150 };
 151 #undef _R
 152
 153 enum cfg_version {
 154         RTL_CFG_0 = 0x00,
 155         RTL_CFG_1,
 156         RTL_CFG_2
 157 };
 158
 159 static void rtl_hw_start_8169(struct net_device *);
 160 static void rtl_hw_start_8168(struct net_device *);
 161 static void rtl_hw_start_8101(struct net_device *);
 162
 163 static struct pci_device_id rtl8169_pci_tbl[] = {
 164         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8129), 0, 0, RTL_CFG_0 },
 165         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8136), 0, 0, RTL_CFG_2 },
 166         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8167), 0, 0, RTL_CFG_0 },
 167         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8168), 0, 0, RTL_CFG_1 },
 168         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8169), 0, 0, RTL_CFG_0 },
 169         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4300), 0, 0, RTL_CFG_0 },
 170         { PCI_DEVICE(PCI_VENDOR_ID_AT,          0xc107), 0, 0, RTL_CFG_0 },
 171         { PCI_DEVICE(0x16ec,                    0x0116), 0, 0, RTL_CFG_0 },
 172         { PCI_VENDOR_ID_LINKSYS,                0x1032,
 173                 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
 174         { 0x0001,                               0x8168,
 175                 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
 176         {0,},
 177 };
 178
 179 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
 180
 181 static int rx_copybreak = 200;
 182 static int use_dac;
 183 static struct {
 184         u32 msg_enable;
 185 } debug = { -1 };
 186
 187 enum rtl_registers {
 188         MAC0            = 0,    /* Ethernet hardware address. */
 189         MAC4            = 4,
 190         MAR0            = 8,    /* Multicast filter. */
 191         CounterAddrLow          = 0x10,
 192         CounterAddrHigh         = 0x14,
 193         TxDescStartAddrLow      = 0x20,
 194         TxDescStartAddrHigh     = 0x24,
 195         TxHDescStartAddrLow     = 0x28,
 196         TxHDescStartAddrHigh    = 0x2c,
 197         FLASH           = 0x30,
 198         ERSR            = 0x36,
 199         ChipCmd         = 0x37,
 200         TxPoll          = 0x38,
 201         IntrMask        = 0x3c,
 202         IntrStatus      = 0x3e,
 203         TxConfig        = 0x40,
 204         RxConfig        = 0x44,
 205         RxMissed        = 0x4c,
 206         Cfg9346         = 0x50,
 207         Config0         = 0x51,
 208         Config1         = 0x52,
 209         Config2         = 0x53,
 210         Config3         = 0x54,
 211         Config4         = 0x55,
 212         Config5         = 0x56,
 213         MultiIntr       = 0x5c,
 214         PHYAR           = 0x60,
 215         TBICSR          = 0x64,
 216         TBI_ANAR        = 0x68,
 217         TBI_LPAR        = 0x6a,
 218         PHYstatus       = 0x6c,
 219         RxMaxSize       = 0xda,
 220         CPlusCmd        = 0xe0,
 221         IntrMitigate    = 0xe2,
 222         RxDescAddrLow   = 0xe4,
 223         RxDescAddrHigh  = 0xe8,
 224         EarlyTxThres    = 0xec,
 225         FuncEvent       = 0xf0,
 226         FuncEventMask   = 0xf4,
 227         FuncPresetState = 0xf8,
 228         FuncForceEvent  = 0xfc,
 229 };
 230
 231 enum rtl_register_content {
 232         /* InterruptStatusBits */
 233         SYSErr          = 0x8000,
 234         PCSTimeout      = 0x4000,
 235         SWInt           = 0x0100,
 236         TxDescUnavail   = 0x0080,
 237         RxFIFOOver      = 0x0040,
 238         LinkChg         = 0x0020,
 239         RxOverflow      = 0x0010,
 240         TxErr           = 0x0008,
 241         TxOK            = 0x0004,
 242         RxErr           = 0x0002,
 243         RxOK            = 0x0001,
 244
 245         /* RxStatusDesc */
 246         RxFOVF  = (1 << 23),
 247         RxRWT   = (1 << 22),
 248         RxRES   = (1 << 21),
 249         RxRUNT  = (1 << 20),
 250         RxCRC   = (1 << 19),
 251
 252         /* ChipCmdBits */
 253         CmdReset        = 0x10,
 254         CmdRxEnb        = 0x08,
 255         CmdTxEnb        = 0x04,
 256         RxBufEmpty      = 0x01,
 257
 258         /* TXPoll register p.5 */
 259         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
 260         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
 261         FSWInt          = 0x01,         /* Forced software interrupt */
 262
 263         /* Cfg9346Bits */
 264         Cfg9346_Lock    = 0x00,
 265         Cfg9346_Unlock  = 0xc0,
 266
 267         /* rx_mode_bits */
 268         AcceptErr       = 0x20,
 269         AcceptRunt      = 0x10,
 270         AcceptBroadcast = 0x08,
 271         AcceptMulticast = 0x04,
 272         AcceptMyPhys    = 0x02,
 273         AcceptAllPhys   = 0x01,
 274
 275         /* RxConfigBits */
 276         RxCfgFIFOShift  = 13,
 277         RxCfgDMAShift   =  8,
 278
 279         /* TxConfigBits */
 280         TxInterFrameGapShift = 24,
 281         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
 282
 283         /* Config1 register p.24 */
 284         MSIEnable       = (1 << 5),     /* Enable Message Signaled Interrupt */
 285         PMEnable        = (1 << 0),     /* Power Management Enable */
 286
 287         /* Config2 register p. 25 */
 288         PCI_Clock_66MHz = 0x01,
 289         PCI_Clock_33MHz = 0x00,
 290
 291         /* Config3 register p.25 */
 292         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
 293         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
 294
 295         /* Config5 register p.27 */
 296         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
 297         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
 298         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
 299         LanWake         = (1 << 1),     /* LanWake enable/disable */
 300         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
 301
 302         /* TBICSR p.28 */
 303         TBIReset        = 0x80000000,
 304         TBILoopback     = 0x40000000,
 305         TBINwEnable     = 0x20000000,
 306         TBINwRestart    = 0x10000000,
 307         TBILinkOk       = 0x02000000,
 308         TBINwComplete   = 0x01000000,
 309
 310         /* CPlusCmd p.31 */
 311         PktCntrDisable  = (1 << 7),     // 8168
 312         RxVlan          = (1 << 6),
 313         RxChkSum        = (1 << 5),
 314         PCIDAC          = (1 << 4),
 315         PCIMulRW        = (1 << 3),
 316         INTT_0          = 0x0000,       // 8168
 317         INTT_1          = 0x0001,       // 8168
 318         INTT_2          = 0x0002,       // 8168
 319         INTT_3          = 0x0003,       // 8168
 320
 321         /* rtl8169_PHYstatus */
 322         TBI_Enable      = 0x80,
 323         TxFlowCtrl      = 0x40,
 324         RxFlowCtrl      = 0x20,
 325         _1000bpsF       = 0x10,
 326         _100bps         = 0x08,
 327         _10bps          = 0x04,
 328         LinkStatus      = 0x02,
 329         FullDup         = 0x01,
 330
 331         /* _TBICSRBit */
 332         TBILinkOK       = 0x02000000,
 333
 334         /* DumpCounterCommand */
 335         CounterDump     = 0x8,
 336 };
 337
 338 enum desc_status_bit {
 339         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
 340         RingEnd         = (1 << 30), /* End of descriptor ring */
 341         FirstFrag       = (1 << 29), /* First segment of a packet */
 342         LastFrag        = (1 << 28), /* Final segment of a packet */
 343
 344         /* Tx private */
 345         LargeSend       = (1 << 27), /* TCP Large Send Offload (TSO) */
 346         MSSShift        = 16,        /* MSS value position */
 347         MSSMask         = 0xfff,     /* MSS value + LargeSend bit: 12 bits */
 348         IPCS            = (1 << 18), /* Calculate IP checksum */
 349         UDPCS           = (1 << 17), /* Calculate UDP/IP checksum */
 350         TCPCS           = (1 << 16), /* Calculate TCP/IP checksum */
 351         TxVlanTag       = (1 << 17), /* Add VLAN tag */
 352
 353         /* Rx private */
 354         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
 355         PID0            = (1 << 17), /* Protocol ID bit 2/2 */
 356
 357 #define RxProtoUDP      (PID1)
 358 #define RxProtoTCP      (PID0)
 359 #define RxProtoIP       (PID1 | PID0)
 360 #define RxProtoMask     RxProtoIP
 361
 362         IPFail          = (1 << 16), /* IP checksum failed */
 363         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
 364         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
 365         RxVlanTag       = (1 << 16), /* VLAN tag available */
 366 };
 367
 368 #define RsvdMask        0x3fffc000
 369
 370 struct TxDesc {
 371         __le32 opts1;
 372         __le32 opts2;
 373         __le64 addr;
 374 };
 375
 376 struct RxDesc {
 377         __le32 opts1;
 378         __le32 opts2;
 379         __le64 addr;
 380 };
 381
 382 struct ring_info {
 383         struct sk_buff  *skb;
 384         u32             len;
 385         u8              __pad[sizeof(void *) - sizeof(u32)];
 386 };
 387
 388 enum features {
 389         RTL_FEATURE_WOL = (1 << 0),
 390         RTL_FEATURE_MSI = (1 << 1),
 391 };
 392
 393 struct rtl8169_private {
 394         void __iomem *mmio_addr;        /* memory map physical address */
 395         struct pci_dev *pci_dev;        /* Index of PCI device */
 396         struct net_device *dev;
 397 #ifdef CONFIG_R8169_NAPI
 398         struct napi_struct napi;
 399 #endif
 400         spinlock_t lock;                /* spin lock flag */
 401         u32 msg_enable;
 402         int chipset;
 403         int mac_version;
 404         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
 405         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
 406         u32 dirty_rx;
 407         u32 dirty_tx;
 408         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
 409         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
 410         dma_addr_t TxPhyAddr;
 411         dma_addr_t RxPhyAddr;
 412         struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */
 413         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
 414         unsigned align;
 415         unsigned rx_buf_sz;
 416         struct timer_list timer;
 417         u16 cp_cmd;
 418         u16 intr_event;
 419         u16 napi_event;
 420         u16 intr_mask;
 421         int phy_auto_nego_reg;
 422         int phy_1000_ctrl_reg;
 423 #ifdef CONFIG_R8169_VLAN
 424         struct vlan_group *vlgrp;
 425 #endif
 426         int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
 427         void (*get_settings)(struct net_device *, struct ethtool_cmd *);
 428         void (*phy_reset_enable)(void __iomem *);
 429         void (*hw_start)(struct net_device *);
 430         unsigned int (*phy_reset_pending)(void __iomem *);
 431         unsigned int (*link_ok)(void __iomem *);
 432         struct delayed_work task;
 433         unsigned features;
 434 };
 435
 436 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
 437 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
 438 module_param(rx_copybreak, int, 0);
 439 MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
 440 module_param(use_dac, int, 0);
 441 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
 442 module_param_named(debug, debug.msg_enable, int, 0);
 443 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
 444 MODULE_LICENSE("GPL");
 445 MODULE_VERSION(RTL8169_VERSION);
 446
 447 static int rtl8169_open(struct net_device *dev);
 448 static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev);
 449 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
 450 static int rtl8169_init_ring(struct net_device *dev);
 451 static void rtl_hw_start(struct net_device *dev);
 452 static int rtl8169_close(struct net_device *dev);
 453 static void rtl_set_rx_mode(struct net_device *dev);
 454 static void rtl8169_tx_timeout(struct net_device *dev);
 455 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
 456 static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
 457                                 void __iomem *, u32 budget);
 458 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
 459 static void rtl8169_down(struct net_device *dev);
 460 static void rtl8169_rx_clear(struct rtl8169_private *tp);
 461
 462 #ifdef CONFIG_R8169_NAPI
 463 static int rtl8169_poll(struct napi_struct *napi, int budget);
 464 #endif
 465
 466 static const unsigned int rtl8169_rx_config =
 467         (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
 468
 469 static void mdio_write(void __iomem *ioaddr, int reg_addr, int value)
 470 {
 471         int i;
 472
 473         RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0xFF) << 16 | value);
 474
 475         for (i = 20; i > 0; i--) {
 476                 /*
 477                  * Check if the RTL8169 has completed writing to the specified
 478                  * MII register.
 479                  */
 480                 if (!(RTL_R32(PHYAR) & 0x80000000))
 481                         break;
 482                 udelay(25);
 483         }
 484 }
 485
 486 static int mdio_read(void __iomem *ioaddr, int reg_addr)
 487 {
 488         int i, value = -1;
 489
 490         RTL_W32(PHYAR, 0x0 | (reg_addr & 0xFF) << 16);
 491
 492         for (i = 20; i > 0; i--) {
 493                 /*
 494                  * Check if the RTL8169 has completed retrieving data from
 495                  * the specified MII register.
 496                  */
 497                 if (RTL_R32(PHYAR) & 0x80000000) {
 498                         value = (int) (RTL_R32(PHYAR) & 0xFFFF);
 499                         break;
 500                 }
 501                 udelay(25);
 502         }
 503         return value;
 504 }
 505
 506 static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
 507 {
 508         RTL_W16(IntrMask, 0x0000);
 509
 510         RTL_W16(IntrStatus, 0xffff);
 511 }
 512
 513 static void rtl8169_asic_down(void __iomem *ioaddr)
 514 {
 515         RTL_W8(ChipCmd, 0x00);
 516         rtl8169_irq_mask_and_ack(ioaddr);
 517         RTL_R16(CPlusCmd);
 518 }
 519
 520 static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr)
 521 {
 522         return RTL_R32(TBICSR) & TBIReset;
 523 }
 524
 525 static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr)
 526 {
 527         return mdio_read(ioaddr, MII_BMCR) & BMCR_RESET;
 528 }
 529
 530 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
 531 {
 532         return RTL_R32(TBICSR) & TBILinkOk;
 533 }
 534
 535 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
 536 {
 537         return RTL_R8(PHYstatus) & LinkStatus;
 538 }
 539
 540 static void rtl8169_tbi_reset_enable(void __iomem *ioaddr)
 541 {
 542         RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
 543 }
 544
 545 static void rtl8169_xmii_reset_enable(void __iomem *ioaddr)
 546 {
 547         unsigned int val;
 548
 549         val = mdio_read(ioaddr, MII_BMCR) | BMCR_RESET;
 550         mdio_write(ioaddr, MII_BMCR, val & 0xffff);
 551 }
 552
 553 static void rtl8169_check_link_status(struct net_device *dev,
 554                                       struct rtl8169_private *tp,
 555                                       void __iomem *ioaddr)
 556 {
 557         unsigned long flags;
 558
 559         spin_lock_irqsave(&tp->lock, flags);
 560         if (tp->link_ok(ioaddr)) {
 561                 netif_carrier_on(dev);
 562                 if (netif_msg_ifup(tp))
 563                         printk(KERN_INFO PFX "%s: link up\n", dev->name);
 564         } else {
 565                 if (netif_msg_ifdown(tp))
 566                         printk(KERN_INFO PFX "%s: link down\n", dev->name);
 567                 netif_carrier_off(dev);
 568         }
 569         spin_unlock_irqrestore(&tp->lock, flags);
 570 }
 571
 572 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
 573 {
 574         struct rtl8169_private *tp = netdev_priv(dev);
 575         void __iomem *ioaddr = tp->mmio_addr;
 576         u8 options;
 577
 578         wol->wolopts = 0;
 579
 580 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
 581         wol->supported = WAKE_ANY;
 582
 583         spin_lock_irq(&tp->lock);
 584
 585         options = RTL_R8(Config1);
 586         if (!(options & PMEnable))
 587                 goto out_unlock;
 588
 589         options = RTL_R8(Config3);
 590         if (options & LinkUp)
 591                 wol->wolopts |= WAKE_PHY;
 592         if (options & MagicPacket)
 593                 wol->wolopts |= WAKE_MAGIC;
 594
 595         options = RTL_R8(Config5);
 596         if (options & UWF)
 597                 wol->wolopts |= WAKE_UCAST;
 598         if (options & BWF)
 599                 wol->wolopts |= WAKE_BCAST;
 600         if (options & MWF)
 601                 wol->wolopts |= WAKE_MCAST;
 602
 603 out_unlock:
 604         spin_unlock_irq(&tp->lock);
 605 }
 606
 607 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
 608 {
 609         struct rtl8169_private *tp = netdev_priv(dev);
 610         void __iomem *ioaddr = tp->mmio_addr;
 611         unsigned int i;
 612         static struct {
 613                 u32 opt;
 614                 u16 reg;
 615                 u8  mask;
 616         } cfg[] = {
 617                 { WAKE_ANY,   Config1, PMEnable },
 618                 { WAKE_PHY,   Config3, LinkUp },
 619                 { WAKE_MAGIC, Config3, MagicPacket },
 620                 { WAKE_UCAST, Config5, UWF },
 621                 { WAKE_BCAST, Config5, BWF },
 622                 { WAKE_MCAST, Config5, MWF },
 623                 { WAKE_ANY,   Config5, LanWake }
 624         };
 625
 626         spin_lock_irq(&tp->lock);
 627
 628         RTL_W8(Cfg9346, Cfg9346_Unlock);
 629
 630         for (i = 0; i < ARRAY_SIZE(cfg); i++) {
 631                 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
 632                 if (wol->wolopts & cfg[i].opt)
 633                         options |= cfg[i].mask;
 634                 RTL_W8(cfg[i].reg, options);
 635         }
 636
 637         RTL_W8(Cfg9346, Cfg9346_Lock);
 638
 639         if (wol->wolopts)
 640                 tp->features |= RTL_FEATURE_WOL;
 641         else
 642                 tp->features &= ~RTL_FEATURE_WOL;
 643
 644         spin_unlock_irq(&tp->lock);
 645
 646         return 0;
 647 }
 648
 649 static void rtl8169_get_drvinfo(struct net_device *dev,
 650                                 struct ethtool_drvinfo *info)
 651 {
 652         struct rtl8169_private *tp = netdev_priv(dev);
 653
 654         strcpy(info->driver, MODULENAME);
 655         strcpy(info->version, RTL8169_VERSION);
 656         strcpy(info->bus_info, pci_name(tp->pci_dev));
 657 }
 658
 659 static int rtl8169_get_regs_len(struct net_device *dev)
 660 {
 661         return R8169_REGS_SIZE;
 662 }
 663
 664 static int rtl8169_set_speed_tbi(struct net_device *dev,
 665                                  u8 autoneg, u16 speed, u8 duplex)
 666 {
 667         struct rtl8169_private *tp = netdev_priv(dev);
 668         void __iomem *ioaddr = tp->mmio_addr;
 669         int ret = 0;
 670         u32 reg;
 671
 672         reg = RTL_R32(TBICSR);
 673         if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
 674             (duplex == DUPLEX_FULL)) {
 675                 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
 676         } else if (autoneg == AUTONEG_ENABLE)
 677                 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
 678         else {
 679                 if (netif_msg_link(tp)) {
 680                         printk(KERN_WARNING "%s: "
 681                                "incorrect speed setting refused in TBI mode\n",
 682                                dev->name);
 683                 }
 684                 ret = -EOPNOTSUPP;
 685         }
 686
 687         return ret;
 688 }
 689
 690 static int rtl8169_set_speed_xmii(struct net_device *dev,
 691                                   u8 autoneg, u16 speed, u8 duplex)
 692 {
 693         struct rtl8169_private *tp = netdev_priv(dev);
 694         void __iomem *ioaddr = tp->mmio_addr;
 695         int auto_nego, giga_ctrl;
 696
 697         auto_nego = mdio_read(ioaddr, MII_ADVERTISE);
 698         auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
 699                        ADVERTISE_100HALF | ADVERTISE_100FULL);
 700         giga_ctrl = mdio_read(ioaddr, MII_CTRL1000);
 701         giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
 702
 703         if (autoneg == AUTONEG_ENABLE) {
 704                 auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
 705                               ADVERTISE_100HALF | ADVERTISE_100FULL);
 706                 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
 707         } else {
 708                 if (speed == SPEED_10)
 709                         auto_nego |= ADVERTISE_10HALF | ADVERTISE_10FULL;
 710                 else if (speed == SPEED_100)
 711                         auto_nego |= ADVERTISE_100HALF | ADVERTISE_100FULL;
 712                 else if (speed == SPEED_1000)
 713                         giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
 714
 715                 if (duplex == DUPLEX_HALF)
 716                         auto_nego &= ~(ADVERTISE_10FULL | ADVERTISE_100FULL);
 717
 718                 if (duplex == DUPLEX_FULL)
 719                         auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_100HALF);
 720
 721                 /* This tweak comes straight from Realtek's driver. */
 722                 if ((speed == SPEED_100) && (duplex == DUPLEX_HALF) &&
 723                     ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
 724                      (tp->mac_version == RTL_GIGA_MAC_VER_16))) {
 725                         auto_nego = ADVERTISE_100HALF | ADVERTISE_CSMA;
 726                 }
 727         }
 728
 729         /* The 8100e/8101e do Fast Ethernet only. */
 730         if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
 731             (tp->mac_version == RTL_GIGA_MAC_VER_14) ||
 732             (tp->mac_version == RTL_GIGA_MAC_VER_15) ||
 733             (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
 734                 if ((giga_ctrl & (ADVERTISE_1000FULL | ADVERTISE_1000HALF)) &&
 735                     netif_msg_link(tp)) {
 736                         printk(KERN_INFO "%s: PHY does not support 1000Mbps.\n",
 737                                dev->name);
 738                 }
 739                 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
 740         }
 741
 742         auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
 743
 744         if ((tp->mac_version == RTL_GIGA_MAC_VER_12) ||
 745             (tp->mac_version == RTL_GIGA_MAC_VER_17)) {
 746                 /* Vendor specific (0x1f) and reserved (0x0e) MII registers. */
 747                 mdio_write(ioaddr, 0x1f, 0x0000);
 748                 mdio_write(ioaddr, 0x0e, 0x0000);
 749         }
 750
 751         tp->phy_auto_nego_reg = auto_nego;
 752         tp->phy_1000_ctrl_reg = giga_ctrl;
 753
 754         mdio_write(ioaddr, MII_ADVERTISE, auto_nego);
 755         mdio_write(ioaddr, MII_CTRL1000, giga_ctrl);
 756         mdio_write(ioaddr, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART);
 757         return 0;
 758 }
 759
 760 static int rtl8169_set_speed(struct net_device *dev,
 761                              u8 autoneg, u16 speed, u8 duplex)
 762 {
 763         struct rtl8169_private *tp = netdev_priv(dev);
 764         int ret;
 765
 766         ret = tp->set_speed(dev, autoneg, speed, duplex);
 767
 768         if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
 769                 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
 770
 771         return ret;
 772 }
 773
 774 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 775 {
 776         struct rtl8169_private *tp = netdev_priv(dev);
 777         unsigned long flags;
 778         int ret;
 779
 780         spin_lock_irqsave(&tp->lock, flags);
 781         ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
 782         spin_unlock_irqrestore(&tp->lock, flags);
 783
 784         return ret;
 785 }
 786
 787 static u32 rtl8169_get_rx_csum(struct net_device *dev)
 788 {
 789         struct rtl8169_private *tp = netdev_priv(dev);
 790
 791         return tp->cp_cmd & RxChkSum;
 792 }
 793
 794 static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
 795 {
 796         struct rtl8169_private *tp = netdev_priv(dev);
 797         void __iomem *ioaddr = tp->mmio_addr;
 798         unsigned long flags;
 799
 800         spin_lock_irqsave(&tp->lock, flags);
 801
 802         if (data)
 803                 tp->cp_cmd |= RxChkSum;
 804         else
 805                 tp->cp_cmd &= ~RxChkSum;
 806
 807         RTL_W16(CPlusCmd, tp->cp_cmd);
 808         RTL_R16(CPlusCmd);
 809
 810         spin_unlock_irqrestore(&tp->lock, flags);
 811
 812         return 0;
 813 }
 814
 815 #ifdef CONFIG_R8169_VLAN
 816
 817 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
 818                                       struct sk_buff *skb)
 819 {
 820         return (tp->vlgrp && vlan_tx_tag_present(skb)) ?
 821                 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
 822 }
 823
 824 static void rtl8169_vlan_rx_register(struct net_device *dev,
 825                                      struct vlan_group *grp)
 826 {
 827         struct rtl8169_private *tp = netdev_priv(dev);
 828         void __iomem *ioaddr = tp->mmio_addr;
 829         unsigned long flags;
 830
 831         spin_lock_irqsave(&tp->lock, flags);
 832         tp->vlgrp = grp;
 833         if (tp->vlgrp)
 834                 tp->cp_cmd |= RxVlan;
 835         else
 836                 tp->cp_cmd &= ~RxVlan;
 837         RTL_W16(CPlusCmd, tp->cp_cmd);
 838         RTL_R16(CPlusCmd);
 839         spin_unlock_irqrestore(&tp->lock, flags);
 840 }
 841
 842 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
 843                                struct sk_buff *skb)
 844 {
 845         u32 opts2 = le32_to_cpu(desc->opts2);
 846         int ret;
 847
 848         if (tp->vlgrp && (opts2 & RxVlanTag)) {
 849                 rtl8169_rx_hwaccel_skb(skb, tp->vlgrp, swab16(opts2 & 0xffff));
 850                 ret = 0;
 851         } else
 852                 ret = -1;
 853         desc->opts2 = 0;
 854         return ret;
 855 }
 856
 857 #else /* !CONFIG_R8169_VLAN */
 858
 859 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
 860                                       struct sk_buff *skb)
 861 {
 862         return 0;
 863 }
 864
 865 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
 866                                struct sk_buff *skb)
 867 {
 868         return -1;
 869 }
 870
 871 #endif
 872
 873 static void rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
 874 {
 875         struct rtl8169_private *tp = netdev_priv(dev);
 876         void __iomem *ioaddr = tp->mmio_addr;
 877         u32 status;
 878
 879         cmd->supported =
 880                 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
 881         cmd->port = PORT_FIBRE;
 882         cmd->transceiver = XCVR_INTERNAL;
 883
 884         status = RTL_R32(TBICSR);
 885         cmd->advertising = (status & TBINwEnable) ?  ADVERTISED_Autoneg : 0;
 886         cmd->autoneg = !!(status & TBINwEnable);
 887
 888         cmd->speed = SPEED_1000;
 889         cmd->duplex = DUPLEX_FULL; /* Always set */
 890 }
 891
 892 static void rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
 893 {
 894         struct rtl8169_private *tp = netdev_priv(dev);
 895         void __iomem *ioaddr = tp->mmio_addr;
 896         u8 status;
 897
 898         cmd->supported = SUPPORTED_10baseT_Half |
 899                          SUPPORTED_10baseT_Full |
 900                          SUPPORTED_100baseT_Half |
 901                          SUPPORTED_100baseT_Full |
 902                          SUPPORTED_1000baseT_Full |
 903                          SUPPORTED_Autoneg |
 904                          SUPPORTED_TP;
 905
 906         cmd->autoneg = 1;
 907         cmd->advertising = ADVERTISED_TP | ADVERTISED_Autoneg;
 908
 909         if (tp->phy_auto_nego_reg & ADVERTISE_10HALF)
 910                 cmd->advertising |= ADVERTISED_10baseT_Half;
 911         if (tp->phy_auto_nego_reg & ADVERTISE_10FULL)
 912                 cmd->advertising |= ADVERTISED_10baseT_Full;
 913         if (tp->phy_auto_nego_reg & ADVERTISE_100HALF)
 914                 cmd->advertising |= ADVERTISED_100baseT_Half;
 915         if (tp->phy_auto_nego_reg & ADVERTISE_100FULL)
 916                 cmd->advertising |= ADVERTISED_100baseT_Full;
 917         if (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL)
 918                 cmd->advertising |= ADVERTISED_1000baseT_Full;
 919
 920         status = RTL_R8(PHYstatus);
 921
 922         if (status & _1000bpsF)
 923                 cmd->speed = SPEED_1000;
 924         else if (status & _100bps)
 925                 cmd->speed = SPEED_100;
 926         else if (status & _10bps)
 927                 cmd->speed = SPEED_10;
 928
 929         if (status & TxFlowCtrl)
 930                 cmd->advertising |= ADVERTISED_Asym_Pause;
 931         if (status & RxFlowCtrl)
 932                 cmd->advertising |= ADVERTISED_Pause;
 933
 934         cmd->duplex = ((status & _1000bpsF) || (status & FullDup)) ?
 935                       DUPLEX_FULL : DUPLEX_HALF;
 936 }
 937
 938 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 939 {
 940         struct rtl8169_private *tp = netdev_priv(dev);
 941         unsigned long flags;
 942
 943         spin_lock_irqsave(&tp->lock, flags);
 944
 945         tp->get_settings(dev, cmd);
 946
 947         spin_unlock_irqrestore(&tp->lock, flags);
 948         return 0;
 949 }
 950
 951 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
 952                              void *p)
 953 {
 954         struct rtl8169_private *tp = netdev_priv(dev);
 955         unsigned long flags;
 956
 957         if (regs->len > R8169_REGS_SIZE)
 958                 regs->len = R8169_REGS_SIZE;
 959
 960         spin_lock_irqsave(&tp->lock, flags);
 961         memcpy_fromio(p, tp->mmio_addr, regs->len);
 962         spin_unlock_irqrestore(&tp->lock, flags);
 963 }
 964
 965 static u32 rtl8169_get_msglevel(struct net_device *dev)
 966 {
 967         struct rtl8169_private *tp = netdev_priv(dev);
 968
 969         return tp->msg_enable;
 970 }
 971
 972 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
 973 {
 974         struct rtl8169_private *tp = netdev_priv(dev);
 975
 976         tp->msg_enable = value;
 977 }
 978
 979 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
 980         "tx_packets",
 981         "rx_packets",
 982         "tx_errors",
 983         "rx_errors",
 984         "rx_missed",
 985         "align_errors",
 986         "tx_single_collisions",
 987         "tx_multi_collisions",
 988         "unicast",
 989         "broadcast",
 990         "multicast",
 991         "tx_aborted",
 992         "tx_underrun",
 993 };
 994
 995 struct rtl8169_counters {
 996         __le64  tx_packets;
 997         __le64  rx_packets;
 998         __le64  tx_errors;
 999         __le32  rx_errors;
1000         __le16  rx_missed;
1001         __le16  align_errors;
1002         __le32  tx_one_collision;
1003         __le32  tx_multi_collision;
1004         __le64  rx_unicast;
1005         __le64  rx_broadcast;
1006         __le32  rx_multicast;
1007         __le16  tx_aborted;
1008         __le16  tx_underun;
1009 };
1010
1011 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1012 {
1013         switch (sset) {
1014         case ETH_SS_STATS:
1015                 return ARRAY_SIZE(rtl8169_gstrings);
1016         default:
1017                 return -EOPNOTSUPP;
1018         }
1019 }
1020
1021 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1022                                       struct ethtool_stats *stats, u64 *data)
1023 {
1024         struct rtl8169_private *tp = netdev_priv(dev);
1025         void __iomem *ioaddr = tp->mmio_addr;
1026         struct rtl8169_counters *counters;
1027         dma_addr_t paddr;
1028         u32 cmd;
1029
1030         ASSERT_RTNL();
1031
1032         counters = pci_alloc_consistent(tp->pci_dev, sizeof(*counters), &paddr);
1033         if (!counters)
1034                 return;
1035
1036         RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1037         cmd = (u64)paddr & DMA_32BIT_MASK;
1038         RTL_W32(CounterAddrLow, cmd);
1039         RTL_W32(CounterAddrLow, cmd | CounterDump);
1040
1041         while (RTL_R32(CounterAddrLow) & CounterDump) {
1042                 if (msleep_interruptible(1))
1043                         break;
1044         }
1045
1046         RTL_W32(CounterAddrLow, 0);
1047         RTL_W32(CounterAddrHigh, 0);
1048
1049         data[0] = le64_to_cpu(counters->tx_packets);
1050         data[1] = le64_to_cpu(counters->rx_packets);
1051         data[2] = le64_to_cpu(counters->tx_errors);
1052         data[3] = le32_to_cpu(counters->rx_errors);
1053         data[4] = le16_to_cpu(counters->rx_missed);
1054         data[5] = le16_to_cpu(counters->align_errors);
1055         data[6] = le32_to_cpu(counters->tx_one_collision);
1056         data[7] = le32_to_cpu(counters->tx_multi_collision);
1057         data[8] = le64_to_cpu(counters->rx_unicast);
1058         data[9] = le64_to_cpu(counters->rx_broadcast);
1059         data[10] = le32_to_cpu(counters->rx_multicast);
1060         data[11] = le16_to_cpu(counters->tx_aborted);
1061         data[12] = le16_to_cpu(counters->tx_underun);
1062
1063         pci_free_consistent(tp->pci_dev, sizeof(*counters), counters, paddr);
1064 }
1065
1066 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1067 {
1068         switch(stringset) {
1069         case ETH_SS_STATS:
1070                 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1071                 break;
1072         }
1073 }
1074
1075 static const struct ethtool_ops rtl8169_ethtool_ops = {
1076         .get_drvinfo            = rtl8169_get_drvinfo,
1077         .get_regs_len           = rtl8169_get_regs_len,
1078         .get_link               = ethtool_op_get_link,
1079         .get_settings           = rtl8169_get_settings,
1080         .set_settings           = rtl8169_set_settings,
1081         .get_msglevel           = rtl8169_get_msglevel,
1082         .set_msglevel           = rtl8169_set_msglevel,
1083         .get_rx_csum            = rtl8169_get_rx_csum,
1084         .set_rx_csum            = rtl8169_set_rx_csum,
1085         .set_tx_csum            = ethtool_op_set_tx_csum,
1086         .set_sg                 = ethtool_op_set_sg,
1087         .set_tso                = ethtool_op_set_tso,
1088         .get_regs               = rtl8169_get_regs,
1089         .get_wol                = rtl8169_get_wol,
1090         .set_wol                = rtl8169_set_wol,
1091         .get_strings            = rtl8169_get_strings,
1092         .get_sset_count         = rtl8169_get_sset_count,
1093         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
1094 };
1095
1096 static void rtl8169_write_gmii_reg_bit(void __iomem *ioaddr, int reg,
1097                                        int bitnum, int bitval)
1098 {
1099         int val;
1100
1101         val = mdio_read(ioaddr, reg);
1102         val = (bitval == 1) ?
1103                 val | (bitval << bitnum) :  val & ~(0x0001 << bitnum);
1104         mdio_write(ioaddr, reg, val & 0xffff);
1105 }
1106
1107 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1108                                     void __iomem *ioaddr)
1109 {
1110         /*
1111          * The driver currently handles the 8168Bf and the 8168Be identically
1112          * but they can be identified more specifically through the test below
1113          * if needed:
1114          *
1115          * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1116          *
1117          * Same thing for the 8101Eb and the 8101Ec:
1118          *
1119          * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1120          */
1121         const struct {
1122                 u32 mask;
1123                 u32 val;
1124                 int mac_version;
1125         } mac_info[] = {
1126                 /* 8168B family. */
1127                 { 0x7c800000, 0x3c800000,       RTL_GIGA_MAC_VER_18 },
1128                 { 0x7cf00000, 0x3c000000,       RTL_GIGA_MAC_VER_19 },
1129                 { 0x7cf00000, 0x3c200000,       RTL_GIGA_MAC_VER_20 },
1130                 { 0x7c800000, 0x3c000000,       RTL_GIGA_MAC_VER_20 },
1131
1132                 /* 8168B family. */
1133                 { 0x7cf00000, 0x38000000,       RTL_GIGA_MAC_VER_12 },
1134                 { 0x7cf00000, 0x38500000,       RTL_GIGA_MAC_VER_17 },
1135                 { 0x7c800000, 0x38000000,       RTL_GIGA_MAC_VER_17 },
1136                 { 0x7c800000, 0x30000000,       RTL_GIGA_MAC_VER_11 },
1137
1138                 /* 8101 family. */
1139                 { 0x7cf00000, 0x34000000,       RTL_GIGA_MAC_VER_13 },
1140                 { 0x7cf00000, 0x34200000,       RTL_GIGA_MAC_VER_16 },
1141                 { 0x7c800000, 0x34000000,       RTL_GIGA_MAC_VER_16 },
1142                 /* FIXME: where did these entries come from ? -- FR */
1143                 { 0xfc800000, 0x38800000,       RTL_GIGA_MAC_VER_15 },
1144                 { 0xfc800000, 0x30800000,       RTL_GIGA_MAC_VER_14 },
1145
1146                 /* 8110 family. */
1147                 { 0xfc800000, 0x98000000,       RTL_GIGA_MAC_VER_06 },
1148                 { 0xfc800000, 0x18000000,       RTL_GIGA_MAC_VER_05 },
1149                 { 0xfc800000, 0x10000000,       RTL_GIGA_MAC_VER_04 },
1150                 { 0xfc800000, 0x04000000,       RTL_GIGA_MAC_VER_03 },
1151                 { 0xfc800000, 0x00800000,       RTL_GIGA_MAC_VER_02 },
1152                 { 0xfc800000, 0x00000000,       RTL_GIGA_MAC_VER_01 },
1153
1154                 { 0x00000000, 0x00000000,       RTL_GIGA_MAC_VER_01 }   /* Catch-all */
1155         }, *p = mac_info;
1156         u32 reg;
1157
1158         reg = RTL_R32(TxConfig);
1159         while ((reg & p->mask) != p->val)
1160                 p++;
1161         tp->mac_version = p->mac_version;
1162
1163         if (p->mask == 0x00000000) {
1164                 struct pci_dev *pdev = tp->pci_dev;
1165
1166                 dev_info(&pdev->dev, "unknown MAC (%08x)\n", reg);
1167         }
1168 }
1169
1170 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1171 {
1172         dprintk("mac_version = 0x%02x\n", tp->mac_version);
1173 }
1174
1175 struct phy_reg {
1176         u16 reg;
1177         u16 val;
1178 };
1179
1180 static void rtl_phy_write(void __iomem *ioaddr, struct phy_reg *regs, int len)
1181 {
1182         while (len-- > 0) {
1183                 mdio_write(ioaddr, regs->reg, regs->val);
1184                 regs++;
1185         }
1186 }
1187
1188 static void rtl8169s_hw_phy_config(void __iomem *ioaddr)
1189 {
1190         struct {
1191                 u16 regs[5]; /* Beware of bit-sign propagation */
1192         } phy_magic[5] = { {
1193                 { 0x0000,       //w 4 15 12 0
1194                   0x00a1,       //w 3 15 0 00a1
1195                   0x0008,       //w 2 15 0 0008
1196                   0x1020,       //w 1 15 0 1020
1197                   0x1000 } },{  //w 0 15 0 1000
1198                 { 0x7000,       //w 4 15 12 7
1199                   0xff41,       //w 3 15 0 ff41
1200                   0xde60,       //w 2 15 0 de60
1201                   0x0140,       //w 1 15 0 0140
1202                   0x0077 } },{  //w 0 15 0 0077
1203                 { 0xa000,       //w 4 15 12 a
1204                   0xdf01,       //w 3 15 0 df01
1205                   0xdf20,       //w 2 15 0 df20
1206                   0xff95,       //w 1 15 0 ff95
1207                   0xfa00 } },{  //w 0 15 0 fa00
1208                 { 0xb000,       //w 4 15 12 b
1209                   0xff41,       //w 3 15 0 ff41
1210                   0xde20,       //w 2 15 0 de20
1211                   0x0140,       //w 1 15 0 0140
1212                   0x00bb } },{  //w 0 15 0 00bb
1213                 { 0xf000,       //w 4 15 12 f
1214                   0xdf01,       //w 3 15 0 df01
1215                   0xdf20,       //w 2 15 0 df20
1216                   0xff95,       //w 1 15 0 ff95
1217                   0xbf00 }      //w 0 15 0 bf00
1218                 }
1219         }, *p = phy_magic;
1220         unsigned int i;
1221
1222         mdio_write(ioaddr, 0x1f, 0x0001);               //w 31 2 0 1
1223         mdio_write(ioaddr, 0x15, 0x1000);               //w 21 15 0 1000
1224         mdio_write(ioaddr, 0x18, 0x65c7);               //w 24 15 0 65c7
1225         rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0);   //w 4 11 11 0
1226
1227         for (i = 0; i < ARRAY_SIZE(phy_magic); i++, p++) {
1228                 int val, pos = 4;
1229
1230                 val = (mdio_read(ioaddr, pos) & 0x0fff) | (p->regs[0] & 0xffff);
1231                 mdio_write(ioaddr, pos, val);
1232                 while (--pos >= 0)
1233                         mdio_write(ioaddr, pos, p->regs[4 - pos] & 0xffff);
1234                 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 1); //w 4 11 11 1
1235                 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1236         }
1237         mdio_write(ioaddr, 0x1f, 0x0000); //w 31 2 0 0
1238 }
1239
1240 static void rtl8169sb_hw_phy_config(void __iomem *ioaddr)
1241 {
1242         struct phy_reg phy_reg_init[] = {
1243                 { 0x1f, 0x0002 },
1244                 { 0x01, 0x90d0 },
1245                 { 0x1f, 0x0000 }
1246         };
1247
1248         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1249 }
1250 static void rtl8168b_hw_phy_config(void __iomem *ioaddr)
1251 {
1252         struct phy_reg phy_reg_init[] = {
1253                 { 0x1f, 0x0000 },
1254                 { 0x10, 0xf41b },
1255                 { 0x1f, 0x0000 }
1256         };
1257
1258         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1259 }
1260
1261 static void rtl8168cp_hw_phy_config(void __iomem *ioaddr)
1262 {
1263         struct phy_reg phy_reg_init[] = {
1264                 { 0x1f, 0x0000 },
1265                 { 0x1d, 0x0f00 },
1266                 { 0x1f, 0x0002 },
1267                 { 0x0c, 0x1ec8 },
1268                 { 0x1f, 0x0000 }
1269         };
1270
1271         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1272 }
1273
1274 static void rtl8168c_hw_phy_config(void __iomem *ioaddr)
1275 {
1276         struct phy_reg phy_reg_init[] = {
1277                 { 0x1f, 0x0001 },
1278                 { 0x12, 0x2300 },
1279                 { 0x1f, 0x0002 },
1280                 { 0x00, 0x88d4 },
1281                 { 0x01, 0x82b1 },
1282                 { 0x03, 0x7002 },
1283                 { 0x08, 0x9e30 },
1284                 { 0x09, 0x01f0 },
1285                 { 0x0a, 0x5500 },
1286                 { 0x0c, 0x00c8 },
1287                 { 0x1f, 0x0003 },
1288                 { 0x12, 0xc096 },
1289                 { 0x16, 0x000a },
1290                 { 0x1f, 0x0000 }
1291         };
1292
1293         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1294 }
1295
1296 static void rtl8168cx_hw_phy_config(void __iomem *ioaddr)
1297 {
1298         struct phy_reg phy_reg_init[] = {
1299                 { 0x1f, 0x0000 },
1300                 { 0x12, 0x2300 },
1301                 { 0x1f, 0x0003 },
1302                 { 0x16, 0x0f0a },
1303                 { 0x1f, 0x0000 },
1304                 { 0x1f, 0x0002 },
1305                 { 0x0c, 0x7eb8 },
1306                 { 0x1f, 0x0000 }
1307         };
1308
1309         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1310 }
1311
1312 static void rtl_hw_phy_config(struct net_device *dev)
1313 {
1314         struct rtl8169_private *tp = netdev_priv(dev);
1315         void __iomem *ioaddr = tp->mmio_addr;
1316
1317         rtl8169_print_mac_version(tp);
1318
1319         switch (tp->mac_version) {
1320         case RTL_GIGA_MAC_VER_01:
1321                 break;
1322         case RTL_GIGA_MAC_VER_02:
1323         case RTL_GIGA_MAC_VER_03:
1324                 rtl8169s_hw_phy_config(ioaddr);
1325                 break;
1326         case RTL_GIGA_MAC_VER_04:
1327                 rtl8169sb_hw_phy_config(ioaddr);
1328                 break;
1329         case RTL_GIGA_MAC_VER_11:
1330         case RTL_GIGA_MAC_VER_12:
1331         case RTL_GIGA_MAC_VER_17:
1332                 rtl8168b_hw_phy_config(ioaddr);
1333                 break;
1334         case RTL_GIGA_MAC_VER_18:
1335                 rtl8168cp_hw_phy_config(ioaddr);
1336                 break;
1337         case RTL_GIGA_MAC_VER_19:
1338                 rtl8168c_hw_phy_config(ioaddr);
1339                 break;
1340         case RTL_GIGA_MAC_VER_20:
1341                 rtl8168cx_hw_phy_config(ioaddr);
1342                 break;
1343         default:
1344                 break;
1345         }
1346 }
1347
1348 static void rtl8169_phy_timer(unsigned long __opaque)
1349 {
1350         struct net_device *dev = (struct net_device *)__opaque;
1351         struct rtl8169_private *tp = netdev_priv(dev);
1352         struct timer_list *timer = &tp->timer;
1353         void __iomem *ioaddr = tp->mmio_addr;
1354         unsigned long timeout = RTL8169_PHY_TIMEOUT;
1355
1356         assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1357
1358         if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1359                 return;
1360
1361         spin_lock_irq(&tp->lock);
1362
1363         if (tp->phy_reset_pending(ioaddr)) {
1364                 /*
1365                  * A busy loop could burn quite a few cycles on nowadays CPU.
1366                  * Let's delay the execution of the timer for a few ticks.
1367                  */
1368                 timeout = HZ/10;
1369                 goto out_mod_timer;
1370         }
1371
1372         if (tp->link_ok(ioaddr))
1373                 goto out_unlock;
1374
1375         if (netif_msg_link(tp))
1376                 printk(KERN_WARNING "%s: PHY reset until link up\n", dev->name);
1377
1378         tp->phy_reset_enable(ioaddr);
1379
1380 out_mod_timer:
1381         mod_timer(timer, jiffies + timeout);
1382 out_unlock:
1383         spin_unlock_irq(&tp->lock);
1384 }
1385
1386 static inline void rtl8169_delete_timer(struct net_device *dev)
1387 {
1388         struct rtl8169_private *tp = netdev_priv(dev);
1389         struct timer_list *timer = &tp->timer;
1390
1391         if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1392                 return;
1393
1394         del_timer_sync(timer);
1395 }
1396
1397 static inline void rtl8169_request_timer(struct net_device *dev)
1398 {
1399         struct rtl8169_private *tp = netdev_priv(dev);
1400         struct timer_list *timer = &tp->timer;
1401
1402         if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1403                 return;
1404
1405         mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
1406 }
1407
1408 #ifdef CONFIG_NET_POLL_CONTROLLER
1409 /*
1410  * Polling 'interrupt' - used by things like netconsole to send skbs
1411  * without having to re-enable interrupts. It's not called while
1412  * the interrupt routine is executing.
1413  */
1414 static void rtl8169_netpoll(struct net_device *dev)
1415 {
1416         struct rtl8169_private *tp = netdev_priv(dev);
1417         struct pci_dev *pdev = tp->pci_dev;
1418
1419         disable_irq(pdev->irq);
1420         rtl8169_interrupt(pdev->irq, dev);
1421         enable_irq(pdev->irq);
1422 }
1423 #endif
1424
1425 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
1426                                   void __iomem *ioaddr)
1427 {
1428         iounmap(ioaddr);
1429         pci_release_regions(pdev);
1430         pci_disable_device(pdev);
1431         free_netdev(dev);
1432 }
1433
1434 static void rtl8169_phy_reset(struct net_device *dev,
1435                               struct rtl8169_private *tp)
1436 {
1437         void __iomem *ioaddr = tp->mmio_addr;
1438         unsigned int i;
1439
1440         tp->phy_reset_enable(ioaddr);
1441         for (i = 0; i < 100; i++) {
1442                 if (!tp->phy_reset_pending(ioaddr))
1443                         return;
1444                 msleep(1);
1445         }
1446         if (netif_msg_link(tp))
1447                 printk(KERN_ERR "%s: PHY reset failed.\n", dev->name);
1448 }
1449
1450 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
1451 {
1452         void __iomem *ioaddr = tp->mmio_addr;
1453
1454         rtl_hw_phy_config(dev);
1455
1456         dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1457         RTL_W8(0x82, 0x01);
1458
1459         pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
1460
1461         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
1462                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
1463
1464         if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
1465                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1466                 RTL_W8(0x82, 0x01);
1467                 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
1468                 mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0
1469         }
1470
1471         rtl8169_phy_reset(dev, tp);
1472
1473         /*
1474          * rtl8169_set_speed_xmii takes good care of the Fast Ethernet
1475          * only 8101. Don't panic.
1476          */
1477         rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL);
1478
1479         if ((RTL_R8(PHYstatus) & TBI_Enable) && netif_msg_link(tp))
1480                 printk(KERN_INFO PFX "%s: TBI auto-negotiating\n", dev->name);
1481 }
1482
1483 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
1484 {
1485         void __iomem *ioaddr = tp->mmio_addr;
1486         u32 high;
1487         u32 low;
1488
1489         low  = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
1490         high = addr[4] | (addr[5] << 8);
1491
1492         spin_lock_irq(&tp->lock);
1493
1494         RTL_W8(Cfg9346, Cfg9346_Unlock);
1495         RTL_W32(MAC0, low);
1496         RTL_W32(MAC4, high);
1497         RTL_W8(Cfg9346, Cfg9346_Lock);
1498
1499         spin_unlock_irq(&tp->lock);
1500 }
1501
1502 static int rtl_set_mac_address(struct net_device *dev, void *p)
1503 {
1504         struct rtl8169_private *tp = netdev_priv(dev);
1505         struct sockaddr *addr = p;
1506
1507         if (!is_valid_ether_addr(addr->sa_data))
1508                 return -EADDRNOTAVAIL;
1509
1510         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1511
1512         rtl_rar_set(tp, dev->dev_addr);
1513
1514         return 0;
1515 }
1516
1517 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1518 {
1519         struct rtl8169_private *tp = netdev_priv(dev);
1520         struct mii_ioctl_data *data = if_mii(ifr);
1521
1522         if (!netif_running(dev))
1523                 return -ENODEV;
1524
1525         switch (cmd) {
1526         case SIOCGMIIPHY:
1527                 data->phy_id = 32; /* Internal PHY */
1528                 return 0;
1529
1530         case SIOCGMIIREG:
1531                 data->val_out = mdio_read(tp->mmio_addr, data->reg_num & 0x1f);
1532                 return 0;
1533
1534         case SIOCSMIIREG:
1535                 if (!capable(CAP_NET_ADMIN))
1536                         return -EPERM;
1537                 mdio_write(tp->mmio_addr, data->reg_num & 0x1f, data->val_in);
1538                 return 0;
1539         }
1540         return -EOPNOTSUPP;
1541 }
1542
1543 static const struct rtl_cfg_info {
1544         void (*hw_start)(struct net_device *);
1545         unsigned int region;
1546         unsigned int align;
1547         u16 intr_event;
1548         u16 napi_event;
1549         unsigned msi;
1550 } rtl_cfg_infos [] = {
1551         [RTL_CFG_0] = {
1552                 .hw_start       = rtl_hw_start_8169,
1553                 .region         = 1,
1554                 .align          = 0,
1555                 .intr_event     = SYSErr | LinkChg | RxOverflow |
1556                                   RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
1557                 .napi_event     = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
1558                 .msi            = 0
1559         },
1560         [RTL_CFG_1] = {
1561                 .hw_start       = rtl_hw_start_8168,
1562                 .region         = 2,
1563                 .align          = 8,
1564                 .intr_event     = SYSErr | LinkChg | RxOverflow |
1565                                   TxErr | TxOK | RxOK | RxErr,
1566                 .napi_event     = TxErr | TxOK | RxOK | RxOverflow,
1567                 .msi            = RTL_FEATURE_MSI
1568         },
1569         [RTL_CFG_2] = {
1570                 .hw_start       = rtl_hw_start_8101,
1571                 .region         = 2,
1572                 .align          = 8,
1573                 .intr_event     = SYSErr | LinkChg | RxOverflow | PCSTimeout |
1574                                   RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
1575                 .napi_event     = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
1576                 .msi            = RTL_FEATURE_MSI
1577         }
1578 };
1579
1580 /* Cfg9346_Unlock assumed. */
1581 static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
1582                             const struct rtl_cfg_info *cfg)
1583 {
1584         unsigned msi = 0;
1585         u8 cfg2;
1586
1587         cfg2 = RTL_R8(Config2) & ~MSIEnable;
1588         if (cfg->msi) {
1589                 if (pci_enable_msi(pdev)) {
1590                         dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
1591                 } else {
1592                         cfg2 |= MSIEnable;
1593                         msi = RTL_FEATURE_MSI;
1594                 }
1595         }
1596         RTL_W8(Config2, cfg2);
1597         return msi;
1598 }
1599
1600 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
1601 {
1602         if (tp->features & RTL_FEATURE_MSI) {
1603                 pci_disable_msi(pdev);
1604                 tp->features &= ~RTL_FEATURE_MSI;
1605         }
1606 }
1607
1608 static int __devinit
1609 rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1610 {
1611         const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
1612         const unsigned int region = cfg->region;
1613         struct rtl8169_private *tp;
1614         struct net_device *dev;
1615         void __iomem *ioaddr;
1616         unsigned int i;
1617         int rc;
1618
1619         if (netif_msg_drv(&debug)) {
1620                 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
1621                        MODULENAME, RTL8169_VERSION);
1622         }
1623
1624         dev = alloc_etherdev(sizeof (*tp));
1625         if (!dev) {
1626                 if (netif_msg_drv(&debug))
1627                         dev_err(&pdev->dev, "unable to alloc new ethernet\n");
1628                 rc = -ENOMEM;
1629                 goto out;
1630         }
1631
1632         SET_NETDEV_DEV(dev, &pdev->dev);
1633         tp = netdev_priv(dev);
1634         tp->dev = dev;
1635         tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
1636
1637         /* enable device (incl. PCI PM wakeup and hotplug setup) */
1638         rc = pci_enable_device(pdev);
1639         if (rc < 0) {
1640                 if (netif_msg_probe(tp))
1641                         dev_err(&pdev->dev, "enable failure\n");
1642                 goto err_out_free_dev_1;
1643         }
1644
1645         rc = pci_set_mwi(pdev);
1646         if (rc < 0)
1647                 goto err_out_disable_2;
1648
1649         /* make sure PCI base addr 1 is MMIO */
1650         if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
1651                 if (netif_msg_probe(tp)) {
1652                         dev_err(&pdev->dev,
1653                                 "region #%d not an MMIO resource, aborting\n",
1654                                 region);
1655                 }
1656                 rc = -ENODEV;
1657                 goto err_out_mwi_3;
1658         }
1659
1660         /* check for weird/broken PCI region reporting */
1661         if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
1662                 if (netif_msg_probe(tp)) {
1663                         dev_err(&pdev->dev,
1664                                 "Invalid PCI region size(s), aborting\n");
1665                 }
1666                 rc = -ENODEV;
1667                 goto err_out_mwi_3;
1668         }
1669
1670         rc = pci_request_regions(pdev, MODULENAME);
1671         if (rc < 0) {
1672                 if (netif_msg_probe(tp))
1673                         dev_err(&pdev->dev, "could not request regions.\n");
1674                 goto err_out_mwi_3;
1675         }
1676
1677         tp->cp_cmd = PCIMulRW | RxChkSum;
1678
1679         if ((sizeof(dma_addr_t) > 4) &&
1680             !pci_set_dma_mask(pdev, DMA_64BIT_MASK) && use_dac) {
1681                 tp->cp_cmd |= PCIDAC;
1682                 dev->features |= NETIF_F_HIGHDMA;
1683         } else {
1684                 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1685                 if (rc < 0) {
1686                         if (netif_msg_probe(tp)) {
1687                                 dev_err(&pdev->dev,
1688                                         "DMA configuration failed.\n");
1689                         }
1690                         goto err_out_free_res_4;
1691                 }
1692         }
1693
1694         pci_set_master(pdev);
1695
1696         /* ioremap MMIO region */
1697         ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
1698         if (!ioaddr) {
1699                 if (netif_msg_probe(tp))
1700                         dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
1701                 rc = -EIO;
1702                 goto err_out_free_res_4;
1703         }
1704
1705         /* Unneeded ? Don't mess with Mrs. Murphy. */
1706         rtl8169_irq_mask_and_ack(ioaddr);
1707
1708         /* Soft reset the chip. */
1709         RTL_W8(ChipCmd, CmdReset);
1710
1711         /* Check that the chip has finished the reset. */
1712         for (i = 0; i < 100; i++) {
1713                 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1714                         break;
1715                 msleep_interruptible(1);
1716         }
1717
1718         /* Identify chip attached to board */
1719         rtl8169_get_mac_version(tp, ioaddr);
1720
1721         rtl8169_print_mac_version(tp);
1722
1723         for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--) {
1724                 if (tp->mac_version == rtl_chip_info[i].mac_version)
1725                         break;
1726         }
1727         if (i < 0) {
1728                 /* Unknown chip: assume array element #0, original RTL-8169 */
1729                 if (netif_msg_probe(tp)) {
1730                         dev_printk(KERN_DEBUG, &pdev->dev,
1731                                 "unknown chip version, assuming %s\n",
1732                                 rtl_chip_info[0].name);
1733                 }
1734                 i++;
1735         }
1736         tp->chipset = i;
1737
1738         RTL_W8(Cfg9346, Cfg9346_Unlock);
1739         RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
1740         RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
1741         tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
1742         RTL_W8(Cfg9346, Cfg9346_Lock);
1743
1744         if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
1745             (RTL_R8(PHYstatus) & TBI_Enable)) {
1746                 tp->set_speed = rtl8169_set_speed_tbi;
1747                 tp->get_settings = rtl8169_gset_tbi;
1748                 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
1749                 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
1750                 tp->link_ok = rtl8169_tbi_link_ok;
1751
1752                 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
1753         } else {
1754                 tp->set_speed = rtl8169_set_speed_xmii;
1755                 tp->get_settings = rtl8169_gset_xmii;
1756                 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
1757                 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
1758                 tp->link_ok = rtl8169_xmii_link_ok;
1759
1760                 dev->do_ioctl = rtl8169_ioctl;
1761         }
1762
1763         /* Get MAC address.  FIXME: read EEPROM */
1764         for (i = 0; i < MAC_ADDR_LEN; i++)
1765                 dev->dev_addr[i] = RTL_R8(MAC0 + i);
1766         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1767
1768         dev->open = rtl8169_open;
1769         dev->hard_start_xmit = rtl8169_start_xmit;
1770         dev->get_stats = rtl8169_get_stats;
1771         SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
1772         dev->stop = rtl8169_close;
1773         dev->tx_timeout = rtl8169_tx_timeout;
1774         dev->set_multicast_list = rtl_set_rx_mode;
1775         dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
1776         dev->irq = pdev->irq;
1777         dev->base_addr = (unsigned long) ioaddr;
1778         dev->change_mtu = rtl8169_change_mtu;
1779         dev->set_mac_address = rtl_set_mac_address;
1780
1781 #ifdef CONFIG_R8169_NAPI
1782         netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
1783 #endif
1784
1785 #ifdef CONFIG_R8169_VLAN
1786         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1787         dev->vlan_rx_register = rtl8169_vlan_rx_register;
1788 #endif
1789
1790 #ifdef CONFIG_NET_POLL_CONTROLLER
1791         dev->poll_controller = rtl8169_netpoll;
1792 #endif
1793
1794         tp->intr_mask = 0xffff;
1795         tp->pci_dev = pdev;
1796         tp->mmio_addr = ioaddr;
1797         tp->align = cfg->align;
1798         tp->hw_start = cfg->hw_start;
1799         tp->intr_event = cfg->intr_event;
1800         tp->napi_event = cfg->napi_event;
1801
1802         init_timer(&tp->timer);
1803         tp->timer.data = (unsigned long) dev;
1804         tp->timer.function = rtl8169_phy_timer;
1805
1806         spin_lock_init(&tp->lock);
1807
1808         rc = register_netdev(dev);
1809         if (rc < 0)
1810                 goto err_out_msi_5;
1811
1812         pci_set_drvdata(pdev, dev);
1813
1814         if (netif_msg_probe(tp)) {
1815                 u32 xid = RTL_R32(TxConfig) & 0x7cf0f8ff;
1816
1817                 printk(KERN_INFO "%s: %s at 0x%lx, "
1818                        "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
1819                        "XID %08x IRQ %d\n",
1820                        dev->name,
1821                        rtl_chip_info[tp->chipset].name,
1822                        dev->base_addr,
1823                        dev->dev_addr[0], dev->dev_addr[1],
1824                        dev->dev_addr[2], dev->dev_addr[3],
1825                        dev->dev_addr[4], dev->dev_addr[5], xid, dev->irq);
1826         }
1827
1828         rtl8169_init_phy(dev, tp);
1829
1830 out:
1831         return rc;
1832
1833 err_out_msi_5:
1834         rtl_disable_msi(pdev, tp);
1835         iounmap(ioaddr);
1836 err_out_free_res_4:
1837         pci_release_regions(pdev);
1838 err_out_mwi_3:
1839         pci_clear_mwi(pdev);
1840 err_out_disable_2:
1841         pci_disable_device(pdev);
1842 err_out_free_dev_1:
1843         free_netdev(dev);
1844         goto out;
1845 }
1846
1847 static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
1848 {
1849         struct net_device *dev = pci_get_drvdata(pdev);
1850         struct rtl8169_private *tp = netdev_priv(dev);
1851
1852         flush_scheduled_work();
1853
1854         unregister_netdev(dev);
1855         rtl_disable_msi(pdev, tp);
1856         rtl8169_release_board(pdev, dev, tp->mmio_addr);
1857         pci_set_drvdata(pdev, NULL);
1858 }
1859
1860 static void rtl8169_set_rxbufsize(struct rtl8169_private *tp,
1861                                   struct net_device *dev)
1862 {
1863         unsigned int mtu = dev->mtu;
1864
1865         tp->rx_buf_sz = (mtu > RX_BUF_SIZE) ? mtu + ETH_HLEN + 8 : RX_BUF_SIZE;
1866 }
1867
1868 static int rtl8169_open(struct net_device *dev)
1869 {
1870         struct rtl8169_private *tp = netdev_priv(dev);
1871         struct pci_dev *pdev = tp->pci_dev;
1872         int retval = -ENOMEM;
1873
1874
1875         rtl8169_set_rxbufsize(tp, dev);
1876
1877         /*
1878          * Rx and Tx desscriptors needs 256 bytes alignment.
1879          * pci_alloc_consistent provides more.
1880          */
1881         tp->TxDescArray = pci_alloc_consistent(pdev, R8169_TX_RING_BYTES,
1882                                                &tp->TxPhyAddr);
1883         if (!tp->TxDescArray)
1884                 goto out;
1885
1886         tp->RxDescArray = pci_alloc_consistent(pdev, R8169_RX_RING_BYTES,
1887                                                &tp->RxPhyAddr);
1888         if (!tp->RxDescArray)
1889                 goto err_free_tx_0;
1890
1891         retval = rtl8169_init_ring(dev);
1892         if (retval < 0)
1893                 goto err_free_rx_1;
1894
1895         INIT_DELAYED_WORK(&tp->task, NULL);
1896
1897         smp_mb();
1898
1899         retval = request_irq(dev->irq, rtl8169_interrupt,
1900                              (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
1901                              dev->name, dev);
1902         if (retval < 0)
1903                 goto err_release_ring_2;
1904
1905 #ifdef CONFIG_R8169_NAPI
1906         napi_enable(&tp->napi);
1907 #endif
1908
1909         rtl_hw_start(dev);
1910
1911         rtl8169_request_timer(dev);
1912
1913         rtl8169_check_link_status(dev, tp, tp->mmio_addr);
1914 out:
1915         return retval;
1916
1917 err_release_ring_2:
1918         rtl8169_rx_clear(tp);
1919 err_free_rx_1:
1920         pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
1921                             tp->RxPhyAddr);
1922 err_free_tx_0:
1923         pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
1924                             tp->TxPhyAddr);
1925         goto out;
1926 }
1927
1928 static void rtl8169_hw_reset(void __iomem *ioaddr)
1929 {
1930         /* Disable interrupts */
1931         rtl8169_irq_mask_and_ack(ioaddr);
1932
1933         /* Reset the chipset */
1934         RTL_W8(ChipCmd, CmdReset);
1935
1936         /* PCI commit */
1937         RTL_R8(ChipCmd);
1938 }
1939
1940 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
1941 {
1942         void __iomem *ioaddr = tp->mmio_addr;
1943         u32 cfg = rtl8169_rx_config;
1944
1945         cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
1946         RTL_W32(RxConfig, cfg);
1947
1948         /* Set DMA burst size and Interframe Gap Time */
1949         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
1950                 (InterFrameGap << TxInterFrameGapShift));
1951 }
1952
1953 static void rtl_hw_start(struct net_device *dev)
1954 {
1955         struct rtl8169_private *tp = netdev_priv(dev);
1956         void __iomem *ioaddr = tp->mmio_addr;
1957         unsigned int i;
1958
1959         /* Soft reset the chip. */
1960         RTL_W8(ChipCmd, CmdReset);
1961
1962         /* Check that the chip has finished the reset. */
1963         for (i = 0; i < 100; i++) {
1964                 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1965                         break;
1966                 msleep_interruptible(1);
1967         }
1968
1969         tp->hw_start(dev);
1970
1971         netif_start_queue(dev);
1972 }
1973
1974
1975 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
1976                                          void __iomem *ioaddr)
1977 {
1978         /*
1979          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
1980          * register to be written before TxDescAddrLow to work.
1981          * Switching from MMIO to I/O access fixes the issue as well.
1982          */
1983         RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
1984         RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_32BIT_MASK);
1985         RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
1986         RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_32BIT_MASK);
1987 }
1988
1989 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
1990 {
1991         u16 cmd;
1992
1993         cmd = RTL_R16(CPlusCmd);
1994         RTL_W16(CPlusCmd, cmd);
1995         return cmd;
1996 }
1997
1998 static void rtl_set_rx_max_size(void __iomem *ioaddr)
1999 {
2000         /* Low hurts. Let's disable the filtering. */
2001         RTL_W16(RxMaxSize, 16383);
2002 }
2003
2004 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
2005 {
2006         struct {
2007                 u32 mac_version;
2008                 u32 clk;
2009                 u32 val;
2010         } cfg2_info [] = {
2011                 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
2012                 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
2013                 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
2014                 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
2015         }, *p = cfg2_info;
2016         unsigned int i;
2017         u32 clk;
2018
2019         clk = RTL_R8(Config2) & PCI_Clock_66MHz;
2020         for (i = 0; i < ARRAY_SIZE(cfg2_info); i++) {
2021                 if ((p->mac_version == mac_version) && (p->clk == clk)) {
2022                         RTL_W32(0x7c, p->val);
2023                         break;
2024                 }
2025         }
2026 }
2027
2028 static void rtl_hw_start_8169(struct net_device *dev)
2029 {
2030         struct rtl8169_private *tp = netdev_priv(dev);
2031         void __iomem *ioaddr = tp->mmio_addr;
2032         struct pci_dev *pdev = tp->pci_dev;
2033
2034         if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
2035                 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
2036                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
2037         }
2038
2039         RTL_W8(Cfg9346, Cfg9346_Unlock);
2040         if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
2041             (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2042             (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
2043             (tp->mac_version == RTL_GIGA_MAC_VER_04))
2044                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2045
2046         RTL_W8(EarlyTxThres, EarlyTxThld);
2047
2048         rtl_set_rx_max_size(ioaddr);
2049
2050         if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
2051             (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2052             (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
2053             (tp->mac_version == RTL_GIGA_MAC_VER_04))
2054                 rtl_set_rx_tx_config_registers(tp);
2055
2056         tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
2057
2058         if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2059             (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
2060                 dprintk("Set MAC Reg C+CR Offset 0xE0. "
2061                         "Bit-3 and bit-14 MUST be 1\n");
2062                 tp->cp_cmd |= (1 << 14);
2063         }
2064
2065         RTL_W16(CPlusCmd, tp->cp_cmd);
2066
2067         rtl8169_set_magic_reg(ioaddr, tp->mac_version);
2068
2069         /*
2070          * Undocumented corner. Supposedly:
2071          * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
2072          */
2073         RTL_W16(IntrMitigate, 0x0000);
2074
2075         rtl_set_rx_tx_desc_registers(tp, ioaddr);
2076
2077         if ((tp->mac_version != RTL_GIGA_MAC_VER_01) &&
2078             (tp->mac_version != RTL_GIGA_MAC_VER_02) &&
2079             (tp->mac_version != RTL_GIGA_MAC_VER_03) &&
2080             (tp->mac_version != RTL_GIGA_MAC_VER_04)) {
2081                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2082                 rtl_set_rx_tx_config_registers(tp);
2083         }
2084
2085         RTL_W8(Cfg9346, Cfg9346_Lock);
2086
2087         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
2088         RTL_R8(IntrMask);
2089
2090         RTL_W32(RxMissed, 0);
2091
2092         rtl_set_rx_mode(dev);
2093
2094         /* no early-rx interrupts */
2095         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
2096
2097         /* Enable all known interrupts by setting the interrupt mask. */
2098         RTL_W16(IntrMask, tp->intr_event);
2099 }
2100
2101 static void rtl_hw_start_8168(struct net_device *dev)
2102 {
2103         struct rtl8169_private *tp = netdev_priv(dev);
2104         void __iomem *ioaddr = tp->mmio_addr;
2105         struct pci_dev *pdev = tp->pci_dev;
2106         u8 ctl;
2107
2108         RTL_W8(Cfg9346, Cfg9346_Unlock);
2109
2110         RTL_W8(EarlyTxThres, EarlyTxThld);
2111
2112         rtl_set_rx_max_size(ioaddr);
2113
2114         rtl_set_rx_tx_config_registers(tp);
2115
2116         tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
2117
2118         RTL_W16(CPlusCmd, tp->cp_cmd);
2119
2120         /* Tx performance tweak. */
2121         pci_read_config_byte(pdev, 0x69, &ctl);
2122         ctl = (ctl & ~0x70) | 0x50;
2123         pci_write_config_byte(pdev, 0x69, ctl);
2124
2125         RTL_W16(IntrMitigate, 0x5151);
2126
2127         /* Work around for RxFIFO overflow. */
2128         if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
2129                 tp->intr_event |= RxFIFOOver | PCSTimeout;
2130                 tp->intr_event &= ~RxOverflow;
2131         }
2132
2133         rtl_set_rx_tx_desc_registers(tp, ioaddr);
2134
2135         RTL_W8(Cfg9346, Cfg9346_Lock);
2136
2137         RTL_R8(IntrMask);
2138
2139         RTL_W32(RxMissed, 0);
2140
2141         rtl_set_rx_mode(dev);
2142
2143         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2144
2145         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
2146
2147         RTL_W16(IntrMask, tp->intr_event);
2148 }
2149
2150 static void rtl_hw_start_8101(struct net_device *dev)
2151 {
2152         struct rtl8169_private *tp = netdev_priv(dev);
2153         void __iomem *ioaddr = tp->mmio_addr;
2154         struct pci_dev *pdev = tp->pci_dev;
2155
2156         if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
2157             (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
2158                 pci_write_config_word(pdev, 0x68, 0x00);
2159                 pci_write_config_word(pdev, 0x69, 0x08);
2160         }
2161
2162         RTL_W8(Cfg9346, Cfg9346_Unlock);
2163
2164         RTL_W8(EarlyTxThres, EarlyTxThld);
2165
2166         rtl_set_rx_max_size(ioaddr);
2167
2168         tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
2169
2170         RTL_W16(CPlusCmd, tp->cp_cmd);
2171
2172         RTL_W16(IntrMitigate, 0x0000);
2173
2174         rtl_set_rx_tx_desc_registers(tp, ioaddr);
2175
2176         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2177         rtl_set_rx_tx_config_registers(tp);
2178
2179         RTL_W8(Cfg9346, Cfg9346_Lock);
2180
2181         RTL_R8(IntrMask);
2182
2183         RTL_W32(RxMissed, 0);
2184
2185         rtl_set_rx_mode(dev);
2186
2187         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2188
2189         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
2190
2191         RTL_W16(IntrMask, tp->intr_event);
2192 }
2193
2194 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
2195 {
2196         struct rtl8169_private *tp = netdev_priv(dev);
2197         int ret = 0;
2198
2199         if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
2200                 return -EINVAL;
2201
2202         dev->mtu = new_mtu;
2203
2204         if (!netif_running(dev))
2205                 goto out;
2206
2207         rtl8169_down(dev);
2208
2209         rtl8169_set_rxbufsize(tp, dev);
2210
2211         ret = rtl8169_init_ring(dev);
2212         if (ret < 0)
2213                 goto out;
2214
2215 #ifdef CONFIG_R8169_NAPI
2216         napi_enable(&tp->napi);
2217 #endif
2218
2219         rtl_hw_start(dev);
2220
2221         rtl8169_request_timer(dev);
2222
2223 out:
2224         return ret;
2225 }
2226
2227 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
2228 {
2229         desc->addr = 0x0badbadbadbadbadull;
2230         desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
2231 }
2232
2233 static void rtl8169_free_rx_skb(struct rtl8169_private *tp,
2234                                 struct sk_buff **sk_buff, struct RxDesc *desc)
2235 {
2236         struct pci_dev *pdev = tp->pci_dev;
2237
2238         pci_unmap_single(pdev, le64_to_cpu(desc->addr), tp->rx_buf_sz,
2239                          PCI_DMA_FROMDEVICE);
2240         dev_kfree_skb(*sk_buff);
2241         *sk_buff = NULL;
2242         rtl8169_make_unusable_by_asic(desc);
2243 }
2244
2245 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
2246 {
2247         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
2248
2249         desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
2250 }
2251
2252 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
2253                                        u32 rx_buf_sz)
2254 {
2255         desc->addr = cpu_to_le64(mapping);
2256         wmb();
2257         rtl8169_mark_to_asic(desc, rx_buf_sz);
2258 }
2259
2260 static struct sk_buff *rtl8169_alloc_rx_skb(struct pci_dev *pdev,
2261                                             struct net_device *dev,
2262                                             struct RxDesc *desc, int rx_buf_sz,
2263                                             unsigned int align)
2264 {
2265         struct sk_buff *skb;
2266         dma_addr_t mapping;
2267         unsigned int pad;
2268
2269         pad = align ? align : NET_IP_ALIGN;
2270
2271         skb = netdev_alloc_skb(dev, rx_buf_sz + pad);
2272         if (!skb)
2273                 goto err_out;
2274
2275         skb_reserve(skb, align ? ((pad - 1) & (unsigned long)skb->data) : pad);
2276
2277         mapping = pci_map_single(pdev, skb->data, rx_buf_sz,
2278                                  PCI_DMA_FROMDEVICE);
2279
2280         rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
2281 out:
2282         return skb;
2283
2284 err_out:
2285         rtl8169_make_unusable_by_asic(desc);
2286         goto out;
2287 }
2288
2289 static void rtl8169_rx_clear(struct rtl8169_private *tp)
2290 {
2291         unsigned int i;
2292
2293         for (i = 0; i < NUM_RX_DESC; i++) {
2294                 if (tp->Rx_skbuff[i]) {
2295                         rtl8169_free_rx_skb(tp, tp->Rx_skbuff + i,
2296                                             tp->RxDescArray + i);
2297                 }
2298         }
2299 }
2300
2301 static u32 rtl8169_rx_fill(struct rtl8169_private *tp, struct net_device *dev,
2302                            u32 start, u32 end)
2303 {
2304         u32 cur;
2305
2306         for (cur = start; end - cur != 0; cur++) {
2307                 struct sk_buff *skb;
2308                 unsigned int i = cur % NUM_RX_DESC;
2309
2310                 WARN_ON((s32)(end - cur) < 0);
2311
2312                 if (tp->Rx_skbuff[i])
2313                         continue;
2314
2315                 skb = rtl8169_alloc_rx_skb(tp->pci_dev, dev,
2316                                            tp->RxDescArray + i,
2317                                            tp->rx_buf_sz, tp->align);
2318                 if (!skb)
2319                         break;
2320
2321                 tp->Rx_skbuff[i] = skb;
2322         }
2323         return cur - start;
2324 }
2325
2326 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
2327 {
2328         desc->opts1 |= cpu_to_le32(RingEnd);
2329 }
2330
2331 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
2332 {
2333         tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
2334 }
2335
2336 static int rtl8169_init_ring(struct net_device *dev)
2337 {
2338         struct rtl8169_private *tp = netdev_priv(dev);
2339
2340         rtl8169_init_ring_indexes(tp);
2341
2342         memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
2343         memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));
2344
2345         if (rtl8169_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC)
2346                 goto err_out;
2347
2348         rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
2349
2350         return 0;
2351
2352 err_out:
2353         rtl8169_rx_clear(tp);
2354         return -ENOMEM;
2355 }
2356
2357 static void rtl8169_unmap_tx_skb(struct pci_dev *pdev, struct ring_info *tx_skb,
2358                                  struct TxDesc *desc)
2359 {
2360         unsigned int len = tx_skb->len;
2361
2362         pci_unmap_single(pdev, le64_to_cpu(desc->addr), len, PCI_DMA_TODEVICE);
2363         desc->opts1 = 0x00;
2364         desc->opts2 = 0x00;
2365         desc->addr = 0x00;
2366         tx_skb->len = 0;
2367 }
2368
2369 static void rtl8169_tx_clear(struct rtl8169_private *tp)
2370 {
2371         unsigned int i;
2372
2373         for (i = tp->dirty_tx; i < tp->dirty_tx + NUM_TX_DESC; i++) {
2374                 unsigned int entry = i % NUM_TX_DESC;
2375                 struct ring_info *tx_skb = tp->tx_skb + entry;
2376                 unsigned int len = tx_skb->len;
2377
2378                 if (len) {
2379                         struct sk_buff *skb = tx_skb->skb;
2380
2381                         rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb,
2382                                              tp->TxDescArray + entry);
2383                         if (skb) {
2384                                 dev_kfree_skb(skb);
2385                                 tx_skb->skb = NULL;
2386                         }
2387                         tp->dev->stats.tx_dropped++;
2388                 }
2389         }
2390         tp->cur_tx = tp->dirty_tx = 0;
2391 }
2392
2393 static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
2394 {
2395         struct rtl8169_private *tp = netdev_priv(dev);
2396
2397         PREPARE_DELAYED_WORK(&tp->task, task);
2398         schedule_delayed_work(&tp->task, 4);
2399 }
2400
2401 static void rtl8169_wait_for_quiescence(struct net_device *dev)
2402 {
2403         struct rtl8169_private *tp = netdev_priv(dev);
2404         void __iomem *ioaddr = tp->mmio_addr;
2405
2406         synchronize_irq(dev->irq);
2407
2408         /* Wait for any pending NAPI task to complete */
2409 #ifdef CONFIG_R8169_NAPI
2410         napi_disable(&tp->napi);
2411 #endif
2412
2413         rtl8169_irq_mask_and_ack(ioaddr);
2414
2415 #ifdef CONFIG_R8169_NAPI
2416         napi_enable(&tp->napi);
2417 #endif
2418 }
2419
2420 static void rtl8169_reinit_task(struct work_struct *work)
2421 {
2422         struct rtl8169_private *tp =
2423                 container_of(work, struct rtl8169_private, task.work);
2424         struct net_device *dev = tp->dev;
2425         int ret;
2426
2427         rtnl_lock();
2428
2429         if (!netif_running(dev))
2430                 goto out_unlock;
2431
2432         rtl8169_wait_for_quiescence(dev);
2433         rtl8169_close(dev);
2434
2435         ret = rtl8169_open(dev);
2436         if (unlikely(ret < 0)) {
2437                 if (net_ratelimit() && netif_msg_drv(tp)) {
2438                         printk(KERN_ERR PFX "%s: reinit failure (status = %d)."
2439                                " Rescheduling.\n", dev->name, ret);
2440                 }
2441                 rtl8169_schedule_work(dev, rtl8169_reinit_task);
2442         }
2443
2444 out_unlock:
2445         rtnl_unlock();
2446 }
2447
2448 static void rtl8169_reset_task(struct work_struct *work)
2449 {
2450         struct rtl8169_private *tp =
2451                 container_of(work, struct rtl8169_private, task.work);
2452         struct net_device *dev = tp->dev;
2453
2454         rtnl_lock();
2455
2456         if (!netif_running(dev))
2457                 goto out_unlock;
2458
2459         rtl8169_wait_for_quiescence(dev);
2460
2461         rtl8169_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0);
2462         rtl8169_tx_clear(tp);
2463
2464         if (tp->dirty_rx == tp->cur_rx) {
2465                 rtl8169_init_ring_indexes(tp);
2466                 rtl_hw_start(dev);
2467                 netif_wake_queue(dev);
2468                 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
2469         } else {
2470                 if (net_ratelimit() && netif_msg_intr(tp)) {
2471                         printk(KERN_EMERG PFX "%s: Rx buffers shortage\n",
2472                                dev->name);
2473                 }
2474                 rtl8169_schedule_work(dev, rtl8169_reset_task);
2475         }
2476
2477 out_unlock:
2478         rtnl_unlock();
2479 }
2480
2481 static void rtl8169_tx_timeout(struct net_device *dev)
2482 {
2483         struct rtl8169_private *tp = netdev_priv(dev);
2484
2485         rtl8169_hw_reset(tp->mmio_addr);
2486
2487         /* Let's wait a bit while any (async) irq lands on */
2488         rtl8169_schedule_work(dev, rtl8169_reset_task);
2489 }
2490
2491 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
2492                               u32 opts1)
2493 {
2494         struct skb_shared_info *info = skb_shinfo(skb);
2495         unsigned int cur_frag, entry;
2496         struct TxDesc * uninitialized_var(txd);
2497
2498         entry = tp->cur_tx;
2499         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
2500                 skb_frag_t *frag = info->frags + cur_frag;
2501                 dma_addr_t mapping;
2502                 u32 status, len;
2503                 void *addr;
2504
2505                 entry = (entry + 1) % NUM_TX_DESC;
2506
2507                 txd = tp->TxDescArray + entry;
2508                 len = frag->size;
2509                 addr = ((void *) page_address(frag->page)) + frag->page_offset;
2510                 mapping = pci_map_single(tp->pci_dev, addr, len, PCI_DMA_TODEVICE);
2511
2512                 /* anti gcc 2.95.3 bugware (sic) */
2513                 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
2514
2515                 txd->opts1 = cpu_to_le32(status);
2516                 txd->addr = cpu_to_le64(mapping);
2517
2518                 tp->tx_skb[entry].len = len;
2519         }
2520
2521         if (cur_frag) {
2522                 tp->tx_skb[entry].skb = skb;
2523                 txd->opts1 |= cpu_to_le32(LastFrag);
2524         }
2525
2526         return cur_frag;
2527 }
2528
2529 static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
2530 {
2531         if (dev->features & NETIF_F_TSO) {
2532                 u32 mss = skb_shinfo(skb)->gso_size;
2533
2534                 if (mss)
2535                         return LargeSend | ((mss & MSSMask) << MSSShift);
2536         }
2537         if (skb->ip_summed == CHECKSUM_PARTIAL) {
2538                 const struct iphdr *ip = ip_hdr(skb);
2539
2540                 if (ip->protocol == IPPROTO_TCP)
2541                         return IPCS | TCPCS;
2542                 else if (ip->protocol == IPPROTO_UDP)
2543                         return IPCS | UDPCS;
2544                 WARN_ON(1);     /* we need a WARN() */
2545         }
2546         return 0;
2547 }
2548
2549 static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev)
2550 {
2551         struct rtl8169_private *tp = netdev_priv(dev);
2552         unsigned int frags, entry = tp->cur_tx % NUM_TX_DESC;
2553         struct TxDesc *txd = tp->TxDescArray + entry;
2554         void __iomem *ioaddr = tp->mmio_addr;
2555         dma_addr_t mapping;
2556         u32 status, len;
2557         u32 opts1;
2558         int ret = NETDEV_TX_OK;
2559
2560         if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
2561                 if (netif_msg_drv(tp)) {
2562                         printk(KERN_ERR
2563                                "%s: BUG! Tx Ring full when queue awake!\n",
2564                                dev->name);
2565                 }
2566                 goto err_stop;
2567         }
2568
2569         if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
2570                 goto err_stop;
2571
2572         opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
2573
2574         frags = rtl8169_xmit_frags(tp, skb, opts1);
2575         if (frags) {
2576                 len = skb_headlen(skb);
2577                 opts1 |= FirstFrag;
2578         } else {
2579                 len = skb->len;
2580
2581                 if (unlikely(len < ETH_ZLEN)) {
2582                         if (skb_padto(skb, ETH_ZLEN))
2583                                 goto err_update_stats;
2584                         len = ETH_ZLEN;
2585                 }
2586
2587                 opts1 |= FirstFrag | LastFrag;
2588                 tp->tx_skb[entry].skb = skb;
2589         }
2590
2591         mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
2592
2593         tp->tx_skb[entry].len = len;
2594         txd->addr = cpu_to_le64(mapping);
2595         txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
2596
2597         wmb();
2598
2599         /* anti gcc 2.95.3 bugware (sic) */
2600         status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
2601         txd->opts1 = cpu_to_le32(status);
2602
2603         dev->trans_start = jiffies;
2604
2605         tp->cur_tx += frags + 1;
2606
2607         smp_wmb();
2608
2609         RTL_W8(TxPoll, NPQ);    /* set polling bit */
2610
2611         if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
2612                 netif_stop_queue(dev);
2613                 smp_rmb();
2614                 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
2615                         netif_wake_queue(dev);
2616         }
2617
2618 out:
2619         return ret;
2620
2621 err_stop:
2622         netif_stop_queue(dev);
2623         ret = NETDEV_TX_BUSY;
2624 err_update_stats:
2625         dev->stats.tx_dropped++;
2626         goto out;
2627 }
2628
2629 static void rtl8169_pcierr_interrupt(struct net_device *dev)
2630 {
2631         struct rtl8169_private *tp = netdev_priv(dev);
2632         struct pci_dev *pdev = tp->pci_dev;
2633         void __iomem *ioaddr = tp->mmio_addr;
2634         u16 pci_status, pci_cmd;
2635
2636         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2637         pci_read_config_word(pdev, PCI_STATUS, &pci_status);
2638
2639         if (netif_msg_intr(tp)) {
2640                 printk(KERN_ERR
2641                        "%s: PCI error (cmd = 0x%04x, status = 0x%04x).\n",
2642                        dev->name, pci_cmd, pci_status);
2643         }
2644
2645         /*
2646          * The recovery sequence below admits a very elaborated explanation:
2647          * - it seems to work;
2648          * - I did not see what else could be done;
2649          * - it makes iop3xx happy.
2650          *
2651          * Feel free to adjust to your needs.
2652          */
2653         if (pdev->broken_parity_status)
2654                 pci_cmd &= ~PCI_COMMAND_PARITY;
2655         else
2656                 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
2657
2658         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
2659
2660         pci_write_config_word(pdev, PCI_STATUS,
2661                 pci_status & (PCI_STATUS_DETECTED_PARITY |
2662                 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
2663                 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
2664
2665         /* The infamous DAC f*ckup only happens at boot time */
2666         if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
2667                 if (netif_msg_intr(tp))
2668                         printk(KERN_INFO "%s: disabling PCI DAC.\n", dev->name);
2669                 tp->cp_cmd &= ~PCIDAC;
2670                 RTL_W16(CPlusCmd, tp->cp_cmd);
2671                 dev->features &= ~NETIF_F_HIGHDMA;
2672         }
2673
2674         rtl8169_hw_reset(ioaddr);
2675
2676         rtl8169_schedule_work(dev, rtl8169_reinit_task);
2677 }
2678
2679 static void rtl8169_tx_interrupt(struct net_device *dev,
2680                                  struct rtl8169_private *tp,
2681                                  void __iomem *ioaddr)
2682 {
2683         unsigned int dirty_tx, tx_left;
2684
2685         dirty_tx = tp->dirty_tx;
2686         smp_rmb();
2687         tx_left = tp->cur_tx - dirty_tx;
2688
2689         while (tx_left > 0) {
2690                 unsigned int entry = dirty_tx % NUM_TX_DESC;
2691                 struct ring_info *tx_skb = tp->tx_skb + entry;
2692                 u32 len = tx_skb->len;
2693                 u32 status;
2694
2695                 rmb();
2696                 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
2697                 if (status & DescOwn)
2698                         break;
2699
2700                 dev->stats.tx_bytes += len;
2701                 dev->stats.tx_packets++;
2702
2703                 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, tp->TxDescArray + entry);
2704
2705                 if (status & LastFrag) {
2706                         dev_kfree_skb_irq(tx_skb->skb);
2707                         tx_skb->skb = NULL;
2708                 }
2709                 dirty_tx++;
2710                 tx_left--;
2711         }
2712
2713         if (tp->dirty_tx != dirty_tx) {
2714                 tp->dirty_tx = dirty_tx;
2715                 smp_wmb();
2716                 if (netif_queue_stopped(dev) &&
2717                     (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
2718                         netif_wake_queue(dev);
2719                 }
2720                 /*
2721                  * 8168 hack: TxPoll requests are lost when the Tx packets are
2722                  * too close. Let's kick an extra TxPoll request when a burst
2723                  * of start_xmit activity is detected (if it is not detected,
2724                  * it is slow enough). -- FR
2725                  */
2726                 smp_rmb();
2727                 if (tp->cur_tx != dirty_tx)
2728                         RTL_W8(TxPoll, NPQ);
2729         }
2730 }
2731
2732 static inline int rtl8169_fragmented_frame(u32 status)
2733 {
2734         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
2735 }
2736
2737 static inline void rtl8169_rx_csum(struct sk_buff *skb, struct RxDesc *desc)
2738 {
2739         u32 opts1 = le32_to_cpu(desc->opts1);
2740         u32 status = opts1 & RxProtoMask;
2741
2742         if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
2743             ((status == RxProtoUDP) && !(opts1 & UDPFail)) ||
2744             ((status == RxProtoIP) && !(opts1 & IPFail)))
2745                 skb->ip_summed = CHECKSUM_UNNECESSARY;
2746         else
2747                 skb->ip_summed = CHECKSUM_NONE;
2748 }
2749
2750 static inline bool rtl8169_try_rx_copy(struct sk_buff **sk_buff,
2751                                        struct rtl8169_private *tp, int pkt_size,
2752                                        dma_addr_t addr)
2753 {
2754         struct sk_buff *skb;
2755         bool done = false;
2756
2757         if (pkt_size >= rx_copybreak)
2758                 goto out;
2759
2760         skb = netdev_alloc_skb(tp->dev, pkt_size + NET_IP_ALIGN);
2761         if (!skb)
2762                 goto out;
2763
2764         pci_dma_sync_single_for_cpu(tp->pci_dev, addr, pkt_size,
2765                                     PCI_DMA_FROMDEVICE);
2766         skb_reserve(skb, NET_IP_ALIGN);
2767         skb_copy_from_linear_data(*sk_buff, skb->data, pkt_size);
2768         *sk_buff = skb;
2769         done = true;
2770 out:
2771         return done;
2772 }
2773
2774 static int rtl8169_rx_interrupt(struct net_device *dev,
2775                                 struct rtl8169_private *tp,
2776                                 void __iomem *ioaddr, u32 budget)
2777 {
2778         unsigned int cur_rx, rx_left;
2779         unsigned int delta, count;
2780
2781         cur_rx = tp->cur_rx;
2782         rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
2783         rx_left = rtl8169_rx_quota(rx_left, budget);
2784
2785         for (; rx_left > 0; rx_left--, cur_rx++) {
2786                 unsigned int entry = cur_rx % NUM_RX_DESC;
2787                 struct RxDesc *desc = tp->RxDescArray + entry;
2788                 u32 status;
2789
2790                 rmb();
2791                 status = le32_to_cpu(desc->opts1);
2792
2793                 if (status & DescOwn)
2794                         break;
2795                 if (unlikely(status & RxRES)) {
2796                         if (netif_msg_rx_err(tp)) {
2797                                 printk(KERN_INFO
2798                                        "%s: Rx ERROR. status = %08x\n",
2799                                        dev->name, status);
2800                         }
2801                         dev->stats.rx_errors++;
2802                         if (status & (RxRWT | RxRUNT))
2803                                 dev->stats.rx_length_errors++;
2804                         if (status & RxCRC)
2805                                 dev->stats.rx_crc_errors++;
2806                         if (status & RxFOVF) {
2807                                 rtl8169_schedule_work(dev, rtl8169_reset_task);
2808                                 dev->stats.rx_fifo_errors++;
2809                         }
2810                         rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
2811                 } else {
2812                         struct sk_buff *skb = tp->Rx_skbuff[entry];
2813                         dma_addr_t addr = le64_to_cpu(desc->addr);
2814                         int pkt_size = (status & 0x00001FFF) - 4;
2815                         struct pci_dev *pdev = tp->pci_dev;
2816
2817                         /*
2818                          * The driver does not support incoming fragmented
2819                          * frames. They are seen as a symptom of over-mtu
2820                          * sized frames.
2821                          */
2822                         if (unlikely(rtl8169_fragmented_frame(status))) {
2823                                 dev->stats.rx_dropped++;
2824                                 dev->stats.rx_length_errors++;
2825                                 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
2826                                 continue;
2827                         }
2828
2829                         rtl8169_rx_csum(skb, desc);
2830
2831                         if (rtl8169_try_rx_copy(&skb, tp, pkt_size, addr)) {
2832                                 pci_dma_sync_single_for_device(pdev, addr,
2833                                         pkt_size, PCI_DMA_FROMDEVICE);
2834                                 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
2835                         } else {
2836                                 pci_unmap_single(pdev, addr, pkt_size,
2837                                                  PCI_DMA_FROMDEVICE);
2838                                 tp->Rx_skbuff[entry] = NULL;
2839                         }
2840
2841                         skb_put(skb, pkt_size);
2842                         skb->protocol = eth_type_trans(skb, dev);
2843
2844                         if (rtl8169_rx_vlan_skb(tp, desc, skb) < 0)
2845                                 rtl8169_rx_skb(skb);
2846
2847                         dev->last_rx = jiffies;
2848                         dev->stats.rx_bytes += pkt_size;
2849                         dev->stats.rx_packets++;
2850                 }
2851
2852                 /* Work around for AMD plateform. */
2853                 if ((desc->opts2 & 0xfffe000) &&
2854                     (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
2855                         desc->opts2 = 0;
2856                         cur_rx++;
2857                 }
2858         }
2859
2860         count = cur_rx - tp->cur_rx;
2861         tp->cur_rx = cur_rx;
2862
2863         delta = rtl8169_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx);
2864         if (!delta && count && netif_msg_intr(tp))
2865                 printk(KERN_INFO "%s: no Rx buffer allocated\n", dev->name);
2866         tp->dirty_rx += delta;
2867
2868         /*
2869          * FIXME: until there is periodic timer to try and refill the ring,
2870          * a temporary shortage may definitely kill the Rx process.
2871          * - disable the asic to try and avoid an overflow and kick it again
2872          *   after refill ?
2873          * - how do others driver handle this condition (Uh oh...).
2874          */
2875         if ((tp->dirty_rx + NUM_RX_DESC == tp->cur_rx) && netif_msg_intr(tp))
2876                 printk(KERN_EMERG "%s: Rx buffers exhausted\n", dev->name);
2877
2878         return count;
2879 }
2880
2881 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
2882 {
2883         struct net_device *dev = dev_instance;
2884         struct rtl8169_private *tp = netdev_priv(dev);
2885         int boguscnt = max_interrupt_work;
2886         void __iomem *ioaddr = tp->mmio_addr;
2887         int status;
2888         int handled = 0;
2889
2890         do {
2891                 status = RTL_R16(IntrStatus);
2892
2893                 /* hotplug/major error/no more work/shared irq */
2894                 if ((status == 0xFFFF) || !status)
2895                         break;
2896
2897                 handled = 1;
2898
2899                 if (unlikely(!netif_running(dev))) {
2900                         rtl8169_asic_down(ioaddr);
2901                         goto out;
2902                 }
2903
2904                 status &= tp->intr_mask;
2905                 RTL_W16(IntrStatus,
2906                         (status & RxFIFOOver) ? (status | RxOverflow) : status);
2907
2908                 if (!(status & tp->intr_event))
2909                         break;
2910
2911                 /* Work around for rx fifo overflow */
2912                 if (unlikely(status & RxFIFOOver) &&
2913                     (tp->mac_version == RTL_GIGA_MAC_VER_11)) {
2914                         netif_stop_queue(dev);
2915                         rtl8169_tx_timeout(dev);
2916                         break;
2917                 }
2918
2919                 if (unlikely(status & SYSErr)) {
2920                         rtl8169_pcierr_interrupt(dev);
2921                         break;
2922                 }
2923
2924                 if (status & LinkChg)
2925                         rtl8169_check_link_status(dev, tp, ioaddr);
2926
2927 #ifdef CONFIG_R8169_NAPI
2928                 if (status & tp->napi_event) {
2929                         RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
2930                         tp->intr_mask = ~tp->napi_event;
2931
2932                 if (likely(netif_rx_schedule_prep(dev, &tp->napi)))
2933                         __netif_rx_schedule(dev, &tp->napi);
2934                         else if (netif_msg_intr(tp)) {
2935                                 printk(KERN_INFO "%s: interrupt %04x in poll\n",
2936                                        dev->name, status);
2937                         }
2938                 }
2939                 break;
2940 #else
2941                 /* Rx interrupt */
2942                 if (status & (RxOK | RxOverflow | RxFIFOOver))
2943                         rtl8169_rx_interrupt(dev, tp, ioaddr, ~(u32)0);
2944
2945                 /* Tx interrupt */
2946                 if (status & (TxOK | TxErr))
2947                         rtl8169_tx_interrupt(dev, tp, ioaddr);
2948 #endif
2949
2950                 boguscnt--;
2951         } while (boguscnt > 0);
2952
2953         if (boguscnt <= 0) {
2954                 if (netif_msg_intr(tp) && net_ratelimit() ) {
2955                         printk(KERN_WARNING
2956                                "%s: Too much work at interrupt!\n", dev->name);
2957                 }
2958                 /* Clear all interrupt sources. */
2959                 RTL_W16(IntrStatus, 0xffff);
2960         }
2961 out:
2962         return IRQ_RETVAL(handled);
2963 }
2964
2965 #ifdef CONFIG_R8169_NAPI
2966 static int rtl8169_poll(struct napi_struct *napi, int budget)
2967 {
2968         struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
2969         struct net_device *dev = tp->dev;
2970         void __iomem *ioaddr = tp->mmio_addr;
2971         int work_done;
2972
2973         work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
2974         rtl8169_tx_interrupt(dev, tp, ioaddr);
2975
2976         if (work_done < budget) {
2977                 netif_rx_complete(dev, napi);
2978                 tp->intr_mask = 0xffff;
2979                 /*
2980                  * 20040426: the barrier is not strictly required but the
2981                  * behavior of the irq handler could be less predictable
2982                  * without it. Btw, the lack of flush for the posted pci
2983                  * write is safe - FR
2984                  */
2985                 smp_wmb();
2986                 RTL_W16(IntrMask, tp->intr_event);
2987         }
2988
2989         return work_done;
2990 }
2991 #endif
2992
2993 static void rtl8169_down(struct net_device *dev)
2994 {
2995         struct rtl8169_private *tp = netdev_priv(dev);
2996         void __iomem *ioaddr = tp->mmio_addr;
2997         unsigned int intrmask;
2998
2999         rtl8169_delete_timer(dev);
3000
3001         netif_stop_queue(dev);
3002
3003 #ifdef CONFIG_R8169_NAPI
3004         napi_disable(&tp->napi);
3005 #endif
3006
3007 core_down:
3008         spin_lock_irq(&tp->lock);
3009
3010         rtl8169_asic_down(ioaddr);
3011
3012         /* Update the error counts. */
3013         dev->stats.rx_missed_errors += RTL_R32(RxMissed);
3014         RTL_W32(RxMissed, 0);
3015
3016         spin_unlock_irq(&tp->lock);
3017
3018         synchronize_irq(dev->irq);
3019
3020         /* Give a racing hard_start_xmit a few cycles to complete. */
3021         synchronize_sched();  /* FIXME: should this be synchronize_irq()? */
3022
3023         /*
3024          * And now for the 50k$ question: are IRQ disabled or not ?
3025          *
3026          * Two paths lead here:
3027          * 1) dev->close
3028          *    -> netif_running() is available to sync the current code and the
3029          *       IRQ handler. See rtl8169_interrupt for details.
3030          * 2) dev->change_mtu
3031          *    -> rtl8169_poll can not be issued again and re-enable the
3032          *       interruptions. Let's simply issue the IRQ down sequence again.
3033          *
3034          * No loop if hotpluged or major error (0xffff).
3035          */
3036         intrmask = RTL_R16(IntrMask);
3037         if (intrmask && (intrmask != 0xffff))
3038                 goto core_down;
3039
3040         rtl8169_tx_clear(tp);
3041
3042         rtl8169_rx_clear(tp);
3043 }
3044
3045 static int rtl8169_close(struct net_device *dev)
3046 {
3047         struct rtl8169_private *tp = netdev_priv(dev);
3048         struct pci_dev *pdev = tp->pci_dev;
3049
3050         rtl8169_down(dev);
3051
3052         free_irq(dev->irq, dev);
3053
3054         pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
3055                             tp->RxPhyAddr);
3056         pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
3057                             tp->TxPhyAddr);
3058         tp->TxDescArray = NULL;
3059         tp->RxDescArray = NULL;
3060
3061         return 0;
3062 }
3063
3064 static void rtl_set_rx_mode(struct net_device *dev)
3065 {
3066         struct rtl8169_private *tp = netdev_priv(dev);
3067         void __iomem *ioaddr = tp->mmio_addr;
3068         unsigned long flags;
3069         u32 mc_filter[2];       /* Multicast hash filter */
3070         int rx_mode;
3071         u32 tmp = 0;
3072
3073         if (dev->flags & IFF_PROMISC) {
3074                 /* Unconditionally log net taps. */
3075                 if (netif_msg_link(tp)) {
3076                         printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n",
3077                                dev->name);
3078                 }
3079                 rx_mode =
3080                     AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
3081                     AcceptAllPhys;
3082                 mc_filter[1] = mc_filter[0] = 0xffffffff;
3083         } else if ((dev->mc_count > multicast_filter_limit)
3084                    || (dev->flags & IFF_ALLMULTI)) {
3085                 /* Too many to filter perfectly -- accept all multicasts. */
3086                 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
3087                 mc_filter[1] = mc_filter[0] = 0xffffffff;
3088         } else {
3089                 struct dev_mc_list *mclist;
3090                 unsigned int i;
3091
3092                 rx_mode = AcceptBroadcast | AcceptMyPhys;
3093                 mc_filter[1] = mc_filter[0] = 0;
3094                 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
3095                      i++, mclist = mclist->next) {
3096                         int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
3097                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
3098                         rx_mode |= AcceptMulticast;
3099                 }
3100         }
3101
3102         spin_lock_irqsave(&tp->lock, flags);
3103
3104         tmp = rtl8169_rx_config | rx_mode |
3105               (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
3106
3107         if ((tp->mac_version == RTL_GIGA_MAC_VER_11) ||
3108             (tp->mac_version == RTL_GIGA_MAC_VER_12) ||
3109             (tp->mac_version == RTL_GIGA_MAC_VER_13) ||
3110             (tp->mac_version == RTL_GIGA_MAC_VER_14) ||
3111             (tp->mac_version == RTL_GIGA_MAC_VER_15) ||
3112             (tp->mac_version == RTL_GIGA_MAC_VER_16) ||
3113             (tp->mac_version == RTL_GIGA_MAC_VER_17)) {
3114                 mc_filter[0] = 0xffffffff;
3115                 mc_filter[1] = 0xffffffff;
3116         }
3117
3118         RTL_W32(MAR0 + 0, mc_filter[0]);
3119         RTL_W32(MAR0 + 4, mc_filter[1]);
3120
3121         RTL_W32(RxConfig, tmp);
3122
3123         spin_unlock_irqrestore(&tp->lock, flags);
3124 }
3125
3126 /**
3127  *  rtl8169_get_stats - Get rtl8169 read/write statistics
3128  *  @dev: The Ethernet Device to get statistics for
3129  *
3130  *  Get TX/RX statistics for rtl8169
3131  */
3132 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
3133 {
3134         struct rtl8169_private *tp = netdev_priv(dev);
3135         void __iomem *ioaddr = tp->mmio_addr;
3136         unsigned long flags;
3137
3138         if (netif_running(dev)) {
3139                 spin_lock_irqsave(&tp->lock, flags);
3140                 dev->stats.rx_missed_errors += RTL_R32(RxMissed);
3141                 RTL_W32(RxMissed, 0);
3142                 spin_unlock_irqrestore(&tp->lock, flags);
3143         }
3144
3145         return &dev->stats;
3146 }
3147
3148 #ifdef CONFIG_PM
3149
3150 static int rtl8169_suspend(struct pci_dev *pdev, pm_message_t state)
3151 {
3152         struct net_device *dev = pci_get_drvdata(pdev);
3153         struct rtl8169_private *tp = netdev_priv(dev);
3154         void __iomem *ioaddr = tp->mmio_addr;
3155
3156         if (!netif_running(dev))
3157                 goto out_pci_suspend;
3158
3159         netif_device_detach(dev);
3160         netif_stop_queue(dev);
3161
3162         spin_lock_irq(&tp->lock);
3163
3164         rtl8169_asic_down(ioaddr);
3165
3166         dev->stats.rx_missed_errors += RTL_R32(RxMissed);
3167         RTL_W32(RxMissed, 0);
3168
3169         spin_unlock_irq(&tp->lock);
3170
3171 out_pci_suspend:
3172         pci_save_state(pdev);
3173         pci_enable_wake(pdev, pci_choose_state(pdev, state),
3174                 (tp->features & RTL_FEATURE_WOL) ? 1 : 0);
3175         pci_set_power_state(pdev, pci_choose_state(pdev, state));
3176
3177         return 0;
3178 }
3179
3180 static int rtl8169_resume(struct pci_dev *pdev)
3181 {
3182         struct net_device *dev = pci_get_drvdata(pdev);
3183
3184         pci_set_power_state(pdev, PCI_D0);
3185         pci_restore_state(pdev);
3186         pci_enable_wake(pdev, PCI_D0, 0);
3187
3188         if (!netif_running(dev))
3189                 goto out;
3190
3191         netif_device_attach(dev);
3192
3193         rtl8169_schedule_work(dev, rtl8169_reset_task);
3194 out:
3195         return 0;
3196 }
3197
3198 #endif /* CONFIG_PM */
3199
3200 static struct pci_driver rtl8169_pci_driver = {
3201         .name           = MODULENAME,
3202         .id_table       = rtl8169_pci_tbl,
3203         .probe          = rtl8169_init_one,
3204         .remove         = __devexit_p(rtl8169_remove_one),
3205 #ifdef CONFIG_PM
3206         .suspend        = rtl8169_suspend,
3207         .resume         = rtl8169_resume,
3208 #endif
3209 };
3210
3211 static int __init rtl8169_init_module(void)
3212 {
3213         return pci_register_driver(&rtl8169_pci_driver);
3214 }
3215
3216 static void __exit rtl8169_cleanup_module(void)
3217 {
3218         pci_unregister_driver(&rtl8169_pci_driver);
3219 }
3220
3221 module_init(rtl8169_init_module);
3222 module_exit(rtl8169_cleanup_module);