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   1 /*
   2  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
   3  *
   4  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
   5  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
   6  * Copyright (c) a lot of people too. Please respect their work.
   7  *
   8  * See MAINTAINERS file for support contact information.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/moduleparam.h>
  13 #include <linux/pci.h>
  14 #include <linux/netdevice.h>
  15 #include <linux/etherdevice.h>
  16 #include <linux/delay.h>
  17 #include <linux/ethtool.h>
  18 #include <linux/mii.h>
  19 #include <linux/if_vlan.h>
  20 #include <linux/crc32.h>
  21 #include <linux/in.h>
  22 #include <linux/ip.h>
  23 #include <linux/tcp.h>
  24 #include <linux/init.h>
  25 #include <linux/dma-mapping.h>
  26
  27 #include <asm/system.h>
  28 #include <asm/io.h>
  29 #include <asm/irq.h>
  30
  31 #define RTL8169_VERSION "2.3LK-NAPI"
  32 #define MODULENAME "r8169"
  33 #define PFX MODULENAME ": "
  34
  35 #ifdef RTL8169_DEBUG
  36 #define assert(expr) \
  37         if (!(expr)) {                                  \
  38                 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
  39                 #expr,__FILE__,__FUNCTION__,__LINE__);          \
  40         }
  41 #define dprintk(fmt, args...) \
  42         do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
  43 #else
  44 #define assert(expr) do {} while (0)
  45 #define dprintk(fmt, args...)   do {} while (0)
  46 #endif /* RTL8169_DEBUG */
  47
  48 #define R8169_MSG_DEFAULT \
  49         (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
  50
  51 #define TX_BUFFS_AVAIL(tp) \
  52         (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
  53
  54 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
  55 static const int max_interrupt_work = 20;
  56
  57 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  58    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
  59 static const int multicast_filter_limit = 32;
  60
  61 /* MAC address length */
  62 #define MAC_ADDR_LEN    6
  63
  64 #define RX_FIFO_THRESH  7       /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
  65 #define RX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
  66 #define TX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
  67 #define EarlyTxThld     0x3F    /* 0x3F means NO early transmit */
  68 #define RxPacketMaxSize 0x3FE8  /* 16K - 1 - ETH_HLEN - VLAN - CRC... */
  69 #define SafeMtu         0x1c20  /* ... actually life sucks beyond ~7k */
  70 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
  71
  72 #define R8169_REGS_SIZE         256
  73 #define R8169_NAPI_WEIGHT       64
  74 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
  75 #define NUM_RX_DESC     256     /* Number of Rx descriptor registers */
  76 #define RX_BUF_SIZE     1536    /* Rx Buffer size */
  77 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
  78 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
  79
  80 #define RTL8169_TX_TIMEOUT      (6*HZ)
  81 #define RTL8169_PHY_TIMEOUT     (10*HZ)
  82
  83 /* write/read MMIO register */
  84 #define RTL_W8(reg, val8)       writeb ((val8), ioaddr + (reg))
  85 #define RTL_W16(reg, val16)     writew ((val16), ioaddr + (reg))
  86 #define RTL_W32(reg, val32)     writel ((val32), ioaddr + (reg))
  87 #define RTL_R8(reg)             readb (ioaddr + (reg))
  88 #define RTL_R16(reg)            readw (ioaddr + (reg))
  89 #define RTL_R32(reg)            ((unsigned long) readl (ioaddr + (reg)))
  90
  91 enum mac_version {
  92         RTL_GIGA_MAC_VER_01 = 0x01, // 8169
  93         RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
  94         RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
  95         RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
  96         RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
  97         RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
  98         RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
  99         RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be
 100         RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb
 101         RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ?
 102         RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ?
 103         RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec
 104         RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf
 105         RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP
 106         RTL_GIGA_MAC_VER_19 = 0x13, // 8168C
 107         RTL_GIGA_MAC_VER_20 = 0x14  // 8168C
 108 };
 109
 110 #define _R(NAME,MAC,MASK) \
 111         { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
 112
 113 static const struct {
 114         const char *name;
 115         u8 mac_version;
 116         u32 RxConfigMask;       /* Clears the bits supported by this chip */
 117 } rtl_chip_info[] = {
 118         _R("RTL8169",           RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
 119         _R("RTL8169s",          RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
 120         _R("RTL8110s",          RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
 121         _R("RTL8169sb/8110sb",  RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
 122         _R("RTL8169sc/8110sc",  RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
 123         _R("RTL8169sc/8110sc",  RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
 124         _R("RTL8168b/8111b",    RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
 125         _R("RTL8168b/8111b",    RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
 126         _R("RTL8101e",          RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
 127         _R("RTL8100e",          RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
 128         _R("RTL8100e",          RTL_GIGA_MAC_VER_15, 0xff7e1880), // PCI-E 8139
 129         _R("RTL8168b/8111b",    RTL_GIGA_MAC_VER_17, 0xff7e1880), // PCI-E
 130         _R("RTL8101e",          RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E
 131         _R("RTL8168cp/8111cp",  RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E
 132         _R("RTL8168c/8111c",    RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E
 133         _R("RTL8168c/8111c",    RTL_GIGA_MAC_VER_20, 0xff7e1880)  // PCI-E
 134 };
 135 #undef _R
 136
 137 enum cfg_version {
 138         RTL_CFG_0 = 0x00,
 139         RTL_CFG_1,
 140         RTL_CFG_2
 141 };
 142
 143 static void rtl_hw_start_8169(struct net_device *);
 144 static void rtl_hw_start_8168(struct net_device *);
 145 static void rtl_hw_start_8101(struct net_device *);
 146
 147 static struct pci_device_id rtl8169_pci_tbl[] = {
 148         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8129), 0, 0, RTL_CFG_0 },
 149         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8136), 0, 0, RTL_CFG_2 },
 150         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8167), 0, 0, RTL_CFG_0 },
 151         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8168), 0, 0, RTL_CFG_1 },
 152         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8169), 0, 0, RTL_CFG_0 },
 153         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4300), 0, 0, RTL_CFG_0 },
 154         { PCI_DEVICE(PCI_VENDOR_ID_AT,          0xc107), 0, 0, RTL_CFG_0 },
 155         { PCI_DEVICE(0x16ec,                    0x0116), 0, 0, RTL_CFG_0 },
 156         { PCI_VENDOR_ID_LINKSYS,                0x1032,
 157                 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
 158         { 0x0001,                               0x8168,
 159                 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
 160         {0,},
 161 };
 162
 163 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
 164
 165 static int rx_copybreak = 200;
 166 static int use_dac;
 167 static struct {
 168         u32 msg_enable;
 169 } debug = { -1 };
 170
 171 enum rtl_registers {
 172         MAC0            = 0,    /* Ethernet hardware address. */
 173         MAC4            = 4,
 174         MAR0            = 8,    /* Multicast filter. */
 175         CounterAddrLow          = 0x10,
 176         CounterAddrHigh         = 0x14,
 177         TxDescStartAddrLow      = 0x20,
 178         TxDescStartAddrHigh     = 0x24,
 179         TxHDescStartAddrLow     = 0x28,
 180         TxHDescStartAddrHigh    = 0x2c,
 181         FLASH           = 0x30,
 182         ERSR            = 0x36,
 183         ChipCmd         = 0x37,
 184         TxPoll          = 0x38,
 185         IntrMask        = 0x3c,
 186         IntrStatus      = 0x3e,
 187         TxConfig        = 0x40,
 188         RxConfig        = 0x44,
 189         RxMissed        = 0x4c,
 190         Cfg9346         = 0x50,
 191         Config0         = 0x51,
 192         Config1         = 0x52,
 193         Config2         = 0x53,
 194         Config3         = 0x54,
 195         Config4         = 0x55,
 196         Config5         = 0x56,
 197         MultiIntr       = 0x5c,
 198         PHYAR           = 0x60,
 199         TBICSR          = 0x64,
 200         TBI_ANAR        = 0x68,
 201         TBI_LPAR        = 0x6a,
 202         PHYstatus       = 0x6c,
 203         RxMaxSize       = 0xda,
 204         CPlusCmd        = 0xe0,
 205         IntrMitigate    = 0xe2,
 206         RxDescAddrLow   = 0xe4,
 207         RxDescAddrHigh  = 0xe8,
 208         EarlyTxThres    = 0xec,
 209         FuncEvent       = 0xf0,
 210         FuncEventMask   = 0xf4,
 211         FuncPresetState = 0xf8,
 212         FuncForceEvent  = 0xfc,
 213 };
 214
 215 enum rtl_register_content {
 216         /* InterruptStatusBits */
 217         SYSErr          = 0x8000,
 218         PCSTimeout      = 0x4000,
 219         SWInt           = 0x0100,
 220         TxDescUnavail   = 0x0080,
 221         RxFIFOOver      = 0x0040,
 222         LinkChg         = 0x0020,
 223         RxOverflow      = 0x0010,
 224         TxErr           = 0x0008,
 225         TxOK            = 0x0004,
 226         RxErr           = 0x0002,
 227         RxOK            = 0x0001,
 228
 229         /* RxStatusDesc */
 230         RxFOVF  = (1 << 23),
 231         RxRWT   = (1 << 22),
 232         RxRES   = (1 << 21),
 233         RxRUNT  = (1 << 20),
 234         RxCRC   = (1 << 19),
 235
 236         /* ChipCmdBits */
 237         CmdReset        = 0x10,
 238         CmdRxEnb        = 0x08,
 239         CmdTxEnb        = 0x04,
 240         RxBufEmpty      = 0x01,
 241
 242         /* TXPoll register p.5 */
 243         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
 244         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
 245         FSWInt          = 0x01,         /* Forced software interrupt */
 246
 247         /* Cfg9346Bits */
 248         Cfg9346_Lock    = 0x00,
 249         Cfg9346_Unlock  = 0xc0,
 250
 251         /* rx_mode_bits */
 252         AcceptErr       = 0x20,
 253         AcceptRunt      = 0x10,
 254         AcceptBroadcast = 0x08,
 255         AcceptMulticast = 0x04,
 256         AcceptMyPhys    = 0x02,
 257         AcceptAllPhys   = 0x01,
 258
 259         /* RxConfigBits */
 260         RxCfgFIFOShift  = 13,
 261         RxCfgDMAShift   =  8,
 262
 263         /* TxConfigBits */
 264         TxInterFrameGapShift = 24,
 265         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
 266
 267         /* Config1 register p.24 */
 268         MSIEnable       = (1 << 5),     /* Enable Message Signaled Interrupt */
 269         PMEnable        = (1 << 0),     /* Power Management Enable */
 270
 271         /* Config2 register p. 25 */
 272         PCI_Clock_66MHz = 0x01,
 273         PCI_Clock_33MHz = 0x00,
 274
 275         /* Config3 register p.25 */
 276         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
 277         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
 278
 279         /* Config5 register p.27 */
 280         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
 281         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
 282         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
 283         LanWake         = (1 << 1),     /* LanWake enable/disable */
 284         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
 285
 286         /* TBICSR p.28 */
 287         TBIReset        = 0x80000000,
 288         TBILoopback     = 0x40000000,
 289         TBINwEnable     = 0x20000000,
 290         TBINwRestart    = 0x10000000,
 291         TBILinkOk       = 0x02000000,
 292         TBINwComplete   = 0x01000000,
 293
 294         /* CPlusCmd p.31 */
 295         PktCntrDisable  = (1 << 7),     // 8168
 296         RxVlan          = (1 << 6),
 297         RxChkSum        = (1 << 5),
 298         PCIDAC          = (1 << 4),
 299         PCIMulRW        = (1 << 3),
 300         INTT_0          = 0x0000,       // 8168
 301         INTT_1          = 0x0001,       // 8168
 302         INTT_2          = 0x0002,       // 8168
 303         INTT_3          = 0x0003,       // 8168
 304
 305         /* rtl8169_PHYstatus */
 306         TBI_Enable      = 0x80,
 307         TxFlowCtrl      = 0x40,
 308         RxFlowCtrl      = 0x20,
 309         _1000bpsF       = 0x10,
 310         _100bps         = 0x08,
 311         _10bps          = 0x04,
 312         LinkStatus      = 0x02,
 313         FullDup         = 0x01,
 314
 315         /* _TBICSRBit */
 316         TBILinkOK       = 0x02000000,
 317
 318         /* DumpCounterCommand */
 319         CounterDump     = 0x8,
 320 };
 321
 322 enum desc_status_bit {
 323         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
 324         RingEnd         = (1 << 30), /* End of descriptor ring */
 325         FirstFrag       = (1 << 29), /* First segment of a packet */
 326         LastFrag        = (1 << 28), /* Final segment of a packet */
 327
 328         /* Tx private */
 329         LargeSend       = (1 << 27), /* TCP Large Send Offload (TSO) */
 330         MSSShift        = 16,        /* MSS value position */
 331         MSSMask         = 0xfff,     /* MSS value + LargeSend bit: 12 bits */
 332         IPCS            = (1 << 18), /* Calculate IP checksum */
 333         UDPCS           = (1 << 17), /* Calculate UDP/IP checksum */
 334         TCPCS           = (1 << 16), /* Calculate TCP/IP checksum */
 335         TxVlanTag       = (1 << 17), /* Add VLAN tag */
 336
 337         /* Rx private */
 338         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
 339         PID0            = (1 << 17), /* Protocol ID bit 2/2 */
 340
 341 #define RxProtoUDP      (PID1)
 342 #define RxProtoTCP      (PID0)
 343 #define RxProtoIP       (PID1 | PID0)
 344 #define RxProtoMask     RxProtoIP
 345
 346         IPFail          = (1 << 16), /* IP checksum failed */
 347         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
 348         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
 349         RxVlanTag       = (1 << 16), /* VLAN tag available */
 350 };
 351
 352 #define RsvdMask        0x3fffc000
 353
 354 struct TxDesc {
 355         __le32 opts1;
 356         __le32 opts2;
 357         __le64 addr;
 358 };
 359
 360 struct RxDesc {
 361         __le32 opts1;
 362         __le32 opts2;
 363         __le64 addr;
 364 };
 365
 366 struct ring_info {
 367         struct sk_buff  *skb;
 368         u32             len;
 369         u8              __pad[sizeof(void *) - sizeof(u32)];
 370 };
 371
 372 enum features {
 373         RTL_FEATURE_WOL         = (1 << 0),
 374         RTL_FEATURE_MSI         = (1 << 1),
 375         RTL_FEATURE_GMII        = (1 << 2),
 376 };
 377
 378 struct rtl8169_private {
 379         void __iomem *mmio_addr;        /* memory map physical address */
 380         struct pci_dev *pci_dev;        /* Index of PCI device */
 381         struct net_device *dev;
 382         struct napi_struct napi;
 383         spinlock_t lock;                /* spin lock flag */
 384         u32 msg_enable;
 385         int chipset;
 386         int mac_version;
 387         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
 388         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
 389         u32 dirty_rx;
 390         u32 dirty_tx;
 391         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
 392         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
 393         dma_addr_t TxPhyAddr;
 394         dma_addr_t RxPhyAddr;
 395         struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */
 396         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
 397         unsigned align;
 398         unsigned rx_buf_sz;
 399         struct timer_list timer;
 400         u16 cp_cmd;
 401         u16 intr_event;
 402         u16 napi_event;
 403         u16 intr_mask;
 404         int phy_auto_nego_reg;
 405         int phy_1000_ctrl_reg;
 406 #ifdef CONFIG_R8169_VLAN
 407         struct vlan_group *vlgrp;
 408 #endif
 409         int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
 410         int (*get_settings)(struct net_device *, struct ethtool_cmd *);
 411         void (*phy_reset_enable)(void __iomem *);
 412         void (*hw_start)(struct net_device *);
 413         unsigned int (*phy_reset_pending)(void __iomem *);
 414         unsigned int (*link_ok)(void __iomem *);
 415         struct delayed_work task;
 416         unsigned features;
 417
 418         struct mii_if_info mii;
 419 };
 420
 421 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
 422 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
 423 module_param(rx_copybreak, int, 0);
 424 MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
 425 module_param(use_dac, int, 0);
 426 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
 427 module_param_named(debug, debug.msg_enable, int, 0);
 428 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
 429 MODULE_LICENSE("GPL");
 430 MODULE_VERSION(RTL8169_VERSION);
 431
 432 static int rtl8169_open(struct net_device *dev);
 433 static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev);
 434 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
 435 static int rtl8169_init_ring(struct net_device *dev);
 436 static void rtl_hw_start(struct net_device *dev);
 437 static int rtl8169_close(struct net_device *dev);
 438 static void rtl_set_rx_mode(struct net_device *dev);
 439 static void rtl8169_tx_timeout(struct net_device *dev);
 440 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
 441 static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
 442                                 void __iomem *, u32 budget);
 443 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
 444 static void rtl8169_down(struct net_device *dev);
 445 static void rtl8169_rx_clear(struct rtl8169_private *tp);
 446 static int rtl8169_poll(struct napi_struct *napi, int budget);
 447
 448 static const unsigned int rtl8169_rx_config =
 449         (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
 450
 451 static void mdio_write(void __iomem *ioaddr, int reg_addr, int value)
 452 {
 453         int i;
 454
 455         RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
 456
 457         for (i = 20; i > 0; i--) {
 458                 /*
 459                  * Check if the RTL8169 has completed writing to the specified
 460                  * MII register.
 461                  */
 462                 if (!(RTL_R32(PHYAR) & 0x80000000))
 463                         break;
 464                 udelay(25);
 465         }
 466 }
 467
 468 static int mdio_read(void __iomem *ioaddr, int reg_addr)
 469 {
 470         int i, value = -1;
 471
 472         RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
 473
 474         for (i = 20; i > 0; i--) {
 475                 /*
 476                  * Check if the RTL8169 has completed retrieving data from
 477                  * the specified MII register.
 478                  */
 479                 if (RTL_R32(PHYAR) & 0x80000000) {
 480                         value = RTL_R32(PHYAR) & 0xffff;
 481                         break;
 482                 }
 483                 udelay(25);
 484         }
 485         return value;
 486 }
 487
 488 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
 489                            int val)
 490 {
 491         struct rtl8169_private *tp = netdev_priv(dev);
 492         void __iomem *ioaddr = tp->mmio_addr;
 493
 494         mdio_write(ioaddr, location, val);
 495 }
 496
 497 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
 498 {
 499         struct rtl8169_private *tp = netdev_priv(dev);
 500         void __iomem *ioaddr = tp->mmio_addr;
 501
 502         return mdio_read(ioaddr, location);
 503 }
 504
 505 static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
 506 {
 507         RTL_W16(IntrMask, 0x0000);
 508
 509         RTL_W16(IntrStatus, 0xffff);
 510 }
 511
 512 static void rtl8169_asic_down(void __iomem *ioaddr)
 513 {
 514         RTL_W8(ChipCmd, 0x00);
 515         rtl8169_irq_mask_and_ack(ioaddr);
 516         RTL_R16(CPlusCmd);
 517 }
 518
 519 static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr)
 520 {
 521         return RTL_R32(TBICSR) & TBIReset;
 522 }
 523
 524 static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr)
 525 {
 526         return mdio_read(ioaddr, MII_BMCR) & BMCR_RESET;
 527 }
 528
 529 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
 530 {
 531         return RTL_R32(TBICSR) & TBILinkOk;
 532 }
 533
 534 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
 535 {
 536         return RTL_R8(PHYstatus) & LinkStatus;
 537 }
 538
 539 static void rtl8169_tbi_reset_enable(void __iomem *ioaddr)
 540 {
 541         RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
 542 }
 543
 544 static void rtl8169_xmii_reset_enable(void __iomem *ioaddr)
 545 {
 546         unsigned int val;
 547
 548         val = mdio_read(ioaddr, MII_BMCR) | BMCR_RESET;
 549         mdio_write(ioaddr, MII_BMCR, val & 0xffff);
 550 }
 551
 552 static void rtl8169_check_link_status(struct net_device *dev,
 553                                       struct rtl8169_private *tp,
 554                                       void __iomem *ioaddr)
 555 {
 556         unsigned long flags;
 557
 558         spin_lock_irqsave(&tp->lock, flags);
 559         if (tp->link_ok(ioaddr)) {
 560                 netif_carrier_on(dev);
 561                 if (netif_msg_ifup(tp))
 562                         printk(KERN_INFO PFX "%s: link up\n", dev->name);
 563         } else {
 564                 if (netif_msg_ifdown(tp))
 565                         printk(KERN_INFO PFX "%s: link down\n", dev->name);
 566                 netif_carrier_off(dev);
 567         }
 568         spin_unlock_irqrestore(&tp->lock, flags);
 569 }
 570
 571 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
 572 {
 573         struct rtl8169_private *tp = netdev_priv(dev);
 574         void __iomem *ioaddr = tp->mmio_addr;
 575         u8 options;
 576
 577         wol->wolopts = 0;
 578
 579 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
 580         wol->supported = WAKE_ANY;
 581
 582         spin_lock_irq(&tp->lock);
 583
 584         options = RTL_R8(Config1);
 585         if (!(options & PMEnable))
 586                 goto out_unlock;
 587
 588         options = RTL_R8(Config3);
 589         if (options & LinkUp)
 590                 wol->wolopts |= WAKE_PHY;
 591         if (options & MagicPacket)
 592                 wol->wolopts |= WAKE_MAGIC;
 593
 594         options = RTL_R8(Config5);
 595         if (options & UWF)
 596                 wol->wolopts |= WAKE_UCAST;
 597         if (options & BWF)
 598                 wol->wolopts |= WAKE_BCAST;
 599         if (options & MWF)
 600                 wol->wolopts |= WAKE_MCAST;
 601
 602 out_unlock:
 603         spin_unlock_irq(&tp->lock);
 604 }
 605
 606 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
 607 {
 608         struct rtl8169_private *tp = netdev_priv(dev);
 609         void __iomem *ioaddr = tp->mmio_addr;
 610         unsigned int i;
 611         static struct {
 612                 u32 opt;
 613                 u16 reg;
 614                 u8  mask;
 615         } cfg[] = {
 616                 { WAKE_ANY,   Config1, PMEnable },
 617                 { WAKE_PHY,   Config3, LinkUp },
 618                 { WAKE_MAGIC, Config3, MagicPacket },
 619                 { WAKE_UCAST, Config5, UWF },
 620                 { WAKE_BCAST, Config5, BWF },
 621                 { WAKE_MCAST, Config5, MWF },
 622                 { WAKE_ANY,   Config5, LanWake }
 623         };
 624
 625         spin_lock_irq(&tp->lock);
 626
 627         RTL_W8(Cfg9346, Cfg9346_Unlock);
 628
 629         for (i = 0; i < ARRAY_SIZE(cfg); i++) {
 630                 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
 631                 if (wol->wolopts & cfg[i].opt)
 632                         options |= cfg[i].mask;
 633                 RTL_W8(cfg[i].reg, options);
 634         }
 635
 636         RTL_W8(Cfg9346, Cfg9346_Lock);
 637
 638         if (wol->wolopts)
 639                 tp->features |= RTL_FEATURE_WOL;
 640         else
 641                 tp->features &= ~RTL_FEATURE_WOL;
 642
 643         spin_unlock_irq(&tp->lock);
 644
 645         return 0;
 646 }
 647
 648 static void rtl8169_get_drvinfo(struct net_device *dev,
 649                                 struct ethtool_drvinfo *info)
 650 {
 651         struct rtl8169_private *tp = netdev_priv(dev);
 652
 653         strcpy(info->driver, MODULENAME);
 654         strcpy(info->version, RTL8169_VERSION);
 655         strcpy(info->bus_info, pci_name(tp->pci_dev));
 656 }
 657
 658 static int rtl8169_get_regs_len(struct net_device *dev)
 659 {
 660         return R8169_REGS_SIZE;
 661 }
 662
 663 static int rtl8169_set_speed_tbi(struct net_device *dev,
 664                                  u8 autoneg, u16 speed, u8 duplex)
 665 {
 666         struct rtl8169_private *tp = netdev_priv(dev);
 667         void __iomem *ioaddr = tp->mmio_addr;
 668         int ret = 0;
 669         u32 reg;
 670
 671         reg = RTL_R32(TBICSR);
 672         if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
 673             (duplex == DUPLEX_FULL)) {
 674                 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
 675         } else if (autoneg == AUTONEG_ENABLE)
 676                 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
 677         else {
 678                 if (netif_msg_link(tp)) {
 679                         printk(KERN_WARNING "%s: "
 680                                "incorrect speed setting refused in TBI mode\n",
 681                                dev->name);
 682                 }
 683                 ret = -EOPNOTSUPP;
 684         }
 685
 686         return ret;
 687 }
 688
 689 static int rtl8169_set_speed_xmii(struct net_device *dev,
 690                                   u8 autoneg, u16 speed, u8 duplex)
 691 {
 692         struct rtl8169_private *tp = netdev_priv(dev);
 693         void __iomem *ioaddr = tp->mmio_addr;
 694         int auto_nego, giga_ctrl;
 695
 696         auto_nego = mdio_read(ioaddr, MII_ADVERTISE);
 697         auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
 698                        ADVERTISE_100HALF | ADVERTISE_100FULL);
 699         giga_ctrl = mdio_read(ioaddr, MII_CTRL1000);
 700         giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
 701
 702         if (autoneg == AUTONEG_ENABLE) {
 703                 auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
 704                               ADVERTISE_100HALF | ADVERTISE_100FULL);
 705                 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
 706         } else {
 707                 if (speed == SPEED_10)
 708                         auto_nego |= ADVERTISE_10HALF | ADVERTISE_10FULL;
 709                 else if (speed == SPEED_100)
 710                         auto_nego |= ADVERTISE_100HALF | ADVERTISE_100FULL;
 711                 else if (speed == SPEED_1000)
 712                         giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
 713
 714                 if (duplex == DUPLEX_HALF)
 715                         auto_nego &= ~(ADVERTISE_10FULL | ADVERTISE_100FULL);
 716
 717                 if (duplex == DUPLEX_FULL)
 718                         auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_100HALF);
 719
 720                 /* This tweak comes straight from Realtek's driver. */
 721                 if ((speed == SPEED_100) && (duplex == DUPLEX_HALF) &&
 722                     ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
 723                      (tp->mac_version == RTL_GIGA_MAC_VER_16))) {
 724                         auto_nego = ADVERTISE_100HALF | ADVERTISE_CSMA;
 725                 }
 726         }
 727
 728         /* The 8100e/8101e do Fast Ethernet only. */
 729         if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
 730             (tp->mac_version == RTL_GIGA_MAC_VER_14) ||
 731             (tp->mac_version == RTL_GIGA_MAC_VER_15) ||
 732             (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
 733                 if ((giga_ctrl & (ADVERTISE_1000FULL | ADVERTISE_1000HALF)) &&
 734                     netif_msg_link(tp)) {
 735                         printk(KERN_INFO "%s: PHY does not support 1000Mbps.\n",
 736                                dev->name);
 737                 }
 738                 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
 739         }
 740
 741         auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
 742
 743         if ((tp->mac_version == RTL_GIGA_MAC_VER_12) ||
 744             (tp->mac_version == RTL_GIGA_MAC_VER_17)) {
 745                 /* Vendor specific (0x1f) and reserved (0x0e) MII registers. */
 746                 mdio_write(ioaddr, 0x1f, 0x0000);
 747                 mdio_write(ioaddr, 0x0e, 0x0000);
 748         }
 749
 750         tp->phy_auto_nego_reg = auto_nego;
 751         tp->phy_1000_ctrl_reg = giga_ctrl;
 752
 753         mdio_write(ioaddr, MII_ADVERTISE, auto_nego);
 754         mdio_write(ioaddr, MII_CTRL1000, giga_ctrl);
 755         mdio_write(ioaddr, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART);
 756         return 0;
 757 }
 758
 759 static int rtl8169_set_speed(struct net_device *dev,
 760                              u8 autoneg, u16 speed, u8 duplex)
 761 {
 762         struct rtl8169_private *tp = netdev_priv(dev);
 763         int ret;
 764
 765         ret = tp->set_speed(dev, autoneg, speed, duplex);
 766
 767         if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
 768                 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
 769
 770         return ret;
 771 }
 772
 773 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 774 {
 775         struct rtl8169_private *tp = netdev_priv(dev);
 776         unsigned long flags;
 777         int ret;
 778
 779         spin_lock_irqsave(&tp->lock, flags);
 780         ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
 781         spin_unlock_irqrestore(&tp->lock, flags);
 782
 783         return ret;
 784 }
 785
 786 static u32 rtl8169_get_rx_csum(struct net_device *dev)
 787 {
 788         struct rtl8169_private *tp = netdev_priv(dev);
 789
 790         return tp->cp_cmd & RxChkSum;
 791 }
 792
 793 static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
 794 {
 795         struct rtl8169_private *tp = netdev_priv(dev);
 796         void __iomem *ioaddr = tp->mmio_addr;
 797         unsigned long flags;
 798
 799         spin_lock_irqsave(&tp->lock, flags);
 800
 801         if (data)
 802                 tp->cp_cmd |= RxChkSum;
 803         else
 804                 tp->cp_cmd &= ~RxChkSum;
 805
 806         RTL_W16(CPlusCmd, tp->cp_cmd);
 807         RTL_R16(CPlusCmd);
 808
 809         spin_unlock_irqrestore(&tp->lock, flags);
 810
 811         return 0;
 812 }
 813
 814 #ifdef CONFIG_R8169_VLAN
 815
 816 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
 817                                       struct sk_buff *skb)
 818 {
 819         return (tp->vlgrp && vlan_tx_tag_present(skb)) ?
 820                 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
 821 }
 822
 823 static void rtl8169_vlan_rx_register(struct net_device *dev,
 824                                      struct vlan_group *grp)
 825 {
 826         struct rtl8169_private *tp = netdev_priv(dev);
 827         void __iomem *ioaddr = tp->mmio_addr;
 828         unsigned long flags;
 829
 830         spin_lock_irqsave(&tp->lock, flags);
 831         tp->vlgrp = grp;
 832         if (tp->vlgrp)
 833                 tp->cp_cmd |= RxVlan;
 834         else
 835                 tp->cp_cmd &= ~RxVlan;
 836         RTL_W16(CPlusCmd, tp->cp_cmd);
 837         RTL_R16(CPlusCmd);
 838         spin_unlock_irqrestore(&tp->lock, flags);
 839 }
 840
 841 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
 842                                struct sk_buff *skb)
 843 {
 844         u32 opts2 = le32_to_cpu(desc->opts2);
 845         struct vlan_group *vlgrp = tp->vlgrp;
 846         int ret;
 847
 848         if (vlgrp && (opts2 & RxVlanTag)) {
 849                 vlan_hwaccel_receive_skb(skb, vlgrp, swab16(opts2 & 0xffff));
 850                 ret = 0;
 851         } else
 852                 ret = -1;
 853         desc->opts2 = 0;
 854         return ret;
 855 }
 856
 857 #else /* !CONFIG_R8169_VLAN */
 858
 859 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
 860                                       struct sk_buff *skb)
 861 {
 862         return 0;
 863 }
 864
 865 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
 866                                struct sk_buff *skb)
 867 {
 868         return -1;
 869 }
 870
 871 #endif
 872
 873 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
 874 {
 875         struct rtl8169_private *tp = netdev_priv(dev);
 876         void __iomem *ioaddr = tp->mmio_addr;
 877         u32 status;
 878
 879         cmd->supported =
 880                 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
 881         cmd->port = PORT_FIBRE;
 882         cmd->transceiver = XCVR_INTERNAL;
 883
 884         status = RTL_R32(TBICSR);
 885         cmd->advertising = (status & TBINwEnable) ?  ADVERTISED_Autoneg : 0;
 886         cmd->autoneg = !!(status & TBINwEnable);
 887
 888         cmd->speed = SPEED_1000;
 889         cmd->duplex = DUPLEX_FULL; /* Always set */
 890
 891         return 0;
 892 }
 893
 894 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
 895 {
 896         struct rtl8169_private *tp = netdev_priv(dev);
 897
 898         return mii_ethtool_gset(&tp->mii, cmd);
 899 }
 900
 901 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 902 {
 903         struct rtl8169_private *tp = netdev_priv(dev);
 904         unsigned long flags;
 905         int rc;
 906
 907         spin_lock_irqsave(&tp->lock, flags);
 908
 909         rc = tp->get_settings(dev, cmd);
 910
 911         spin_unlock_irqrestore(&tp->lock, flags);
 912         return rc;
 913 }
 914
 915 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
 916                              void *p)
 917 {
 918         struct rtl8169_private *tp = netdev_priv(dev);
 919         unsigned long flags;
 920
 921         if (regs->len > R8169_REGS_SIZE)
 922                 regs->len = R8169_REGS_SIZE;
 923
 924         spin_lock_irqsave(&tp->lock, flags);
 925         memcpy_fromio(p, tp->mmio_addr, regs->len);
 926         spin_unlock_irqrestore(&tp->lock, flags);
 927 }
 928
 929 static u32 rtl8169_get_msglevel(struct net_device *dev)
 930 {
 931         struct rtl8169_private *tp = netdev_priv(dev);
 932
 933         return tp->msg_enable;
 934 }
 935
 936 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
 937 {
 938         struct rtl8169_private *tp = netdev_priv(dev);
 939
 940         tp->msg_enable = value;
 941 }
 942
 943 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
 944         "tx_packets",
 945         "rx_packets",
 946         "tx_errors",
 947         "rx_errors",
 948         "rx_missed",
 949         "align_errors",
 950         "tx_single_collisions",
 951         "tx_multi_collisions",
 952         "unicast",
 953         "broadcast",
 954         "multicast",
 955         "tx_aborted",
 956         "tx_underrun",
 957 };
 958
 959 struct rtl8169_counters {
 960         __le64  tx_packets;
 961         __le64  rx_packets;
 962         __le64  tx_errors;
 963         __le32  rx_errors;
 964         __le16  rx_missed;
 965         __le16  align_errors;
 966         __le32  tx_one_collision;
 967         __le32  tx_multi_collision;
 968         __le64  rx_unicast;
 969         __le64  rx_broadcast;
 970         __le32  rx_multicast;
 971         __le16  tx_aborted;
 972         __le16  tx_underun;
 973 };
 974
 975 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
 976 {
 977         switch (sset) {
 978         case ETH_SS_STATS:
 979                 return ARRAY_SIZE(rtl8169_gstrings);
 980         default:
 981                 return -EOPNOTSUPP;
 982         }
 983 }
 984
 985 static void rtl8169_get_ethtool_stats(struct net_device *dev,
 986                                       struct ethtool_stats *stats, u64 *data)
 987 {
 988         struct rtl8169_private *tp = netdev_priv(dev);
 989         void __iomem *ioaddr = tp->mmio_addr;
 990         struct rtl8169_counters *counters;
 991         dma_addr_t paddr;
 992         u32 cmd;
 993
 994         ASSERT_RTNL();
 995
 996         counters = pci_alloc_consistent(tp->pci_dev, sizeof(*counters), &paddr);
 997         if (!counters)
 998                 return;
 999
1000         RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1001         cmd = (u64)paddr & DMA_32BIT_MASK;
1002         RTL_W32(CounterAddrLow, cmd);
1003         RTL_W32(CounterAddrLow, cmd | CounterDump);
1004
1005         while (RTL_R32(CounterAddrLow) & CounterDump) {
1006                 if (msleep_interruptible(1))
1007                         break;
1008         }
1009
1010         RTL_W32(CounterAddrLow, 0);
1011         RTL_W32(CounterAddrHigh, 0);
1012
1013         data[0] = le64_to_cpu(counters->tx_packets);
1014         data[1] = le64_to_cpu(counters->rx_packets);
1015         data[2] = le64_to_cpu(counters->tx_errors);
1016         data[3] = le32_to_cpu(counters->rx_errors);
1017         data[4] = le16_to_cpu(counters->rx_missed);
1018         data[5] = le16_to_cpu(counters->align_errors);
1019         data[6] = le32_to_cpu(counters->tx_one_collision);
1020         data[7] = le32_to_cpu(counters->tx_multi_collision);
1021         data[8] = le64_to_cpu(counters->rx_unicast);
1022         data[9] = le64_to_cpu(counters->rx_broadcast);
1023         data[10] = le32_to_cpu(counters->rx_multicast);
1024         data[11] = le16_to_cpu(counters->tx_aborted);
1025         data[12] = le16_to_cpu(counters->tx_underun);
1026
1027         pci_free_consistent(tp->pci_dev, sizeof(*counters), counters, paddr);
1028 }
1029
1030 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1031 {
1032         switch(stringset) {
1033         case ETH_SS_STATS:
1034                 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1035                 break;
1036         }
1037 }
1038
1039 static const struct ethtool_ops rtl8169_ethtool_ops = {
1040         .get_drvinfo            = rtl8169_get_drvinfo,
1041         .get_regs_len           = rtl8169_get_regs_len,
1042         .get_link               = ethtool_op_get_link,
1043         .get_settings           = rtl8169_get_settings,
1044         .set_settings           = rtl8169_set_settings,
1045         .get_msglevel           = rtl8169_get_msglevel,
1046         .set_msglevel           = rtl8169_set_msglevel,
1047         .get_rx_csum            = rtl8169_get_rx_csum,
1048         .set_rx_csum            = rtl8169_set_rx_csum,
1049         .set_tx_csum            = ethtool_op_set_tx_csum,
1050         .set_sg                 = ethtool_op_set_sg,
1051         .set_tso                = ethtool_op_set_tso,
1052         .get_regs               = rtl8169_get_regs,
1053         .get_wol                = rtl8169_get_wol,
1054         .set_wol                = rtl8169_set_wol,
1055         .get_strings            = rtl8169_get_strings,
1056         .get_sset_count         = rtl8169_get_sset_count,
1057         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
1058 };
1059
1060 static void rtl8169_write_gmii_reg_bit(void __iomem *ioaddr, int reg,
1061                                        int bitnum, int bitval)
1062 {
1063         int val;
1064
1065         val = mdio_read(ioaddr, reg);
1066         val = (bitval == 1) ?
1067                 val | (bitval << bitnum) :  val & ~(0x0001 << bitnum);
1068         mdio_write(ioaddr, reg, val & 0xffff);
1069 }
1070
1071 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1072                                     void __iomem *ioaddr)
1073 {
1074         /*
1075          * The driver currently handles the 8168Bf and the 8168Be identically
1076          * but they can be identified more specifically through the test below
1077          * if needed:
1078          *
1079          * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1080          *
1081          * Same thing for the 8101Eb and the 8101Ec:
1082          *
1083          * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1084          */
1085         const struct {
1086                 u32 mask;
1087                 u32 val;
1088                 int mac_version;
1089         } mac_info[] = {
1090                 /* 8168B family. */
1091                 { 0x7c800000, 0x3c800000,       RTL_GIGA_MAC_VER_18 },
1092                 { 0x7cf00000, 0x3c000000,       RTL_GIGA_MAC_VER_19 },
1093                 { 0x7cf00000, 0x3c200000,       RTL_GIGA_MAC_VER_20 },
1094                 { 0x7c800000, 0x3c000000,       RTL_GIGA_MAC_VER_20 },
1095
1096                 /* 8168B family. */
1097                 { 0x7cf00000, 0x38000000,       RTL_GIGA_MAC_VER_12 },
1098                 { 0x7cf00000, 0x38500000,       RTL_GIGA_MAC_VER_17 },
1099                 { 0x7c800000, 0x38000000,       RTL_GIGA_MAC_VER_17 },
1100                 { 0x7c800000, 0x30000000,       RTL_GIGA_MAC_VER_11 },
1101
1102                 /* 8101 family. */
1103                 { 0x7cf00000, 0x34000000,       RTL_GIGA_MAC_VER_13 },
1104                 { 0x7cf00000, 0x34200000,       RTL_GIGA_MAC_VER_16 },
1105                 { 0x7c800000, 0x34000000,       RTL_GIGA_MAC_VER_16 },
1106                 /* FIXME: where did these entries come from ? -- FR */
1107                 { 0xfc800000, 0x38800000,       RTL_GIGA_MAC_VER_15 },
1108                 { 0xfc800000, 0x30800000,       RTL_GIGA_MAC_VER_14 },
1109
1110                 /* 8110 family. */
1111                 { 0xfc800000, 0x98000000,       RTL_GIGA_MAC_VER_06 },
1112                 { 0xfc800000, 0x18000000,       RTL_GIGA_MAC_VER_05 },
1113                 { 0xfc800000, 0x10000000,       RTL_GIGA_MAC_VER_04 },
1114                 { 0xfc800000, 0x04000000,       RTL_GIGA_MAC_VER_03 },
1115                 { 0xfc800000, 0x00800000,       RTL_GIGA_MAC_VER_02 },
1116                 { 0xfc800000, 0x00000000,       RTL_GIGA_MAC_VER_01 },
1117
1118                 { 0x00000000, 0x00000000,       RTL_GIGA_MAC_VER_01 }   /* Catch-all */
1119         }, *p = mac_info;
1120         u32 reg;
1121
1122         reg = RTL_R32(TxConfig);
1123         while ((reg & p->mask) != p->val)
1124                 p++;
1125         tp->mac_version = p->mac_version;
1126
1127         if (p->mask == 0x00000000) {
1128                 struct pci_dev *pdev = tp->pci_dev;
1129
1130                 dev_info(&pdev->dev, "unknown MAC (%08x)\n", reg);
1131         }
1132 }
1133
1134 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1135 {
1136         dprintk("mac_version = 0x%02x\n", tp->mac_version);
1137 }
1138
1139 struct phy_reg {
1140         u16 reg;
1141         u16 val;
1142 };
1143
1144 static void rtl_phy_write(void __iomem *ioaddr, struct phy_reg *regs, int len)
1145 {
1146         while (len-- > 0) {
1147                 mdio_write(ioaddr, regs->reg, regs->val);
1148                 regs++;
1149         }
1150 }
1151
1152 static void rtl8169s_hw_phy_config(void __iomem *ioaddr)
1153 {
1154         struct {
1155                 u16 regs[5]; /* Beware of bit-sign propagation */
1156         } phy_magic[5] = { {
1157                 { 0x0000,       //w 4 15 12 0
1158                   0x00a1,       //w 3 15 0 00a1
1159                   0x0008,       //w 2 15 0 0008
1160                   0x1020,       //w 1 15 0 1020
1161                   0x1000 } },{  //w 0 15 0 1000
1162                 { 0x7000,       //w 4 15 12 7
1163                   0xff41,       //w 3 15 0 ff41
1164                   0xde60,       //w 2 15 0 de60
1165                   0x0140,       //w 1 15 0 0140
1166                   0x0077 } },{  //w 0 15 0 0077
1167                 { 0xa000,       //w 4 15 12 a
1168                   0xdf01,       //w 3 15 0 df01
1169                   0xdf20,       //w 2 15 0 df20
1170                   0xff95,       //w 1 15 0 ff95
1171                   0xfa00 } },{  //w 0 15 0 fa00
1172                 { 0xb000,       //w 4 15 12 b
1173                   0xff41,       //w 3 15 0 ff41
1174                   0xde20,       //w 2 15 0 de20
1175                   0x0140,       //w 1 15 0 0140
1176                   0x00bb } },{  //w 0 15 0 00bb
1177                 { 0xf000,       //w 4 15 12 f
1178                   0xdf01,       //w 3 15 0 df01
1179                   0xdf20,       //w 2 15 0 df20
1180                   0xff95,       //w 1 15 0 ff95
1181                   0xbf00 }      //w 0 15 0 bf00
1182                 }
1183         }, *p = phy_magic;
1184         unsigned int i;
1185
1186         mdio_write(ioaddr, 0x1f, 0x0001);               //w 31 2 0 1
1187         mdio_write(ioaddr, 0x15, 0x1000);               //w 21 15 0 1000
1188         mdio_write(ioaddr, 0x18, 0x65c7);               //w 24 15 0 65c7
1189         rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0);   //w 4 11 11 0
1190
1191         for (i = 0; i < ARRAY_SIZE(phy_magic); i++, p++) {
1192                 int val, pos = 4;
1193
1194                 val = (mdio_read(ioaddr, pos) & 0x0fff) | (p->regs[0] & 0xffff);
1195                 mdio_write(ioaddr, pos, val);
1196                 while (--pos >= 0)
1197                         mdio_write(ioaddr, pos, p->regs[4 - pos] & 0xffff);
1198                 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 1); //w 4 11 11 1
1199                 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1200         }
1201         mdio_write(ioaddr, 0x1f, 0x0000); //w 31 2 0 0
1202 }
1203
1204 static void rtl8169sb_hw_phy_config(void __iomem *ioaddr)
1205 {
1206         struct phy_reg phy_reg_init[] = {
1207                 { 0x1f, 0x0002 },
1208                 { 0x01, 0x90d0 },
1209                 { 0x1f, 0x0000 }
1210         };
1211
1212         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1213 }
1214
1215 static void rtl8168cp_hw_phy_config(void __iomem *ioaddr)
1216 {
1217         struct phy_reg phy_reg_init[] = {
1218                 { 0x1f, 0x0000 },
1219                 { 0x1d, 0x0f00 },
1220                 { 0x1f, 0x0002 },
1221                 { 0x0c, 0x1ec8 },
1222                 { 0x1f, 0x0000 }
1223         };
1224
1225         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1226 }
1227
1228 static void rtl8168c_hw_phy_config(void __iomem *ioaddr)
1229 {
1230         struct phy_reg phy_reg_init[] = {
1231                 { 0x1f, 0x0001 },
1232                 { 0x12, 0x2300 },
1233                 { 0x1f, 0x0002 },
1234                 { 0x00, 0x88d4 },
1235                 { 0x01, 0x82b1 },
1236                 { 0x03, 0x7002 },
1237                 { 0x08, 0x9e30 },
1238                 { 0x09, 0x01f0 },
1239                 { 0x0a, 0x5500 },
1240                 { 0x0c, 0x00c8 },
1241                 { 0x1f, 0x0003 },
1242                 { 0x12, 0xc096 },
1243                 { 0x16, 0x000a },
1244                 { 0x1f, 0x0000 }
1245         };
1246
1247         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1248 }
1249
1250 static void rtl8168cx_hw_phy_config(void __iomem *ioaddr)
1251 {
1252         struct phy_reg phy_reg_init[] = {
1253                 { 0x1f, 0x0000 },
1254                 { 0x12, 0x2300 },
1255                 { 0x1f, 0x0003 },
1256                 { 0x16, 0x0f0a },
1257                 { 0x1f, 0x0000 },
1258                 { 0x1f, 0x0002 },
1259                 { 0x0c, 0x7eb8 },
1260                 { 0x1f, 0x0000 }
1261         };
1262
1263         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1264 }
1265
1266 static void rtl_hw_phy_config(struct net_device *dev)
1267 {
1268         struct rtl8169_private *tp = netdev_priv(dev);
1269         void __iomem *ioaddr = tp->mmio_addr;
1270
1271         rtl8169_print_mac_version(tp);
1272
1273         switch (tp->mac_version) {
1274         case RTL_GIGA_MAC_VER_01:
1275                 break;
1276         case RTL_GIGA_MAC_VER_02:
1277         case RTL_GIGA_MAC_VER_03:
1278                 rtl8169s_hw_phy_config(ioaddr);
1279                 break;
1280         case RTL_GIGA_MAC_VER_04:
1281                 rtl8169sb_hw_phy_config(ioaddr);
1282                 break;
1283         case RTL_GIGA_MAC_VER_18:
1284                 rtl8168cp_hw_phy_config(ioaddr);
1285                 break;
1286         case RTL_GIGA_MAC_VER_19:
1287                 rtl8168c_hw_phy_config(ioaddr);
1288                 break;
1289         case RTL_GIGA_MAC_VER_20:
1290                 rtl8168cx_hw_phy_config(ioaddr);
1291                 break;
1292         default:
1293                 break;
1294         }
1295 }
1296
1297 static void rtl8169_phy_timer(unsigned long __opaque)
1298 {
1299         struct net_device *dev = (struct net_device *)__opaque;
1300         struct rtl8169_private *tp = netdev_priv(dev);
1301         struct timer_list *timer = &tp->timer;
1302         void __iomem *ioaddr = tp->mmio_addr;
1303         unsigned long timeout = RTL8169_PHY_TIMEOUT;
1304
1305         assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1306
1307         if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1308                 return;
1309
1310         spin_lock_irq(&tp->lock);
1311
1312         if (tp->phy_reset_pending(ioaddr)) {
1313                 /*
1314                  * A busy loop could burn quite a few cycles on nowadays CPU.
1315                  * Let's delay the execution of the timer for a few ticks.
1316                  */
1317                 timeout = HZ/10;
1318                 goto out_mod_timer;
1319         }
1320
1321         if (tp->link_ok(ioaddr))
1322                 goto out_unlock;
1323
1324         if (netif_msg_link(tp))
1325                 printk(KERN_WARNING "%s: PHY reset until link up\n", dev->name);
1326
1327         tp->phy_reset_enable(ioaddr);
1328
1329 out_mod_timer:
1330         mod_timer(timer, jiffies + timeout);
1331 out_unlock:
1332         spin_unlock_irq(&tp->lock);
1333 }
1334
1335 static inline void rtl8169_delete_timer(struct net_device *dev)
1336 {
1337         struct rtl8169_private *tp = netdev_priv(dev);
1338         struct timer_list *timer = &tp->timer;
1339
1340         if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1341                 return;
1342
1343         del_timer_sync(timer);
1344 }
1345
1346 static inline void rtl8169_request_timer(struct net_device *dev)
1347 {
1348         struct rtl8169_private *tp = netdev_priv(dev);
1349         struct timer_list *timer = &tp->timer;
1350
1351         if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1352                 return;
1353
1354         mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
1355 }
1356
1357 #ifdef CONFIG_NET_POLL_CONTROLLER
1358 /*
1359  * Polling 'interrupt' - used by things like netconsole to send skbs
1360  * without having to re-enable interrupts. It's not called while
1361  * the interrupt routine is executing.
1362  */
1363 static void rtl8169_netpoll(struct net_device *dev)
1364 {
1365         struct rtl8169_private *tp = netdev_priv(dev);
1366         struct pci_dev *pdev = tp->pci_dev;
1367
1368         disable_irq(pdev->irq);
1369         rtl8169_interrupt(pdev->irq, dev);
1370         enable_irq(pdev->irq);
1371 }
1372 #endif
1373
1374 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
1375                                   void __iomem *ioaddr)
1376 {
1377         iounmap(ioaddr);
1378         pci_release_regions(pdev);
1379         pci_disable_device(pdev);
1380         free_netdev(dev);
1381 }
1382
1383 static void rtl8169_phy_reset(struct net_device *dev,
1384                               struct rtl8169_private *tp)
1385 {
1386         void __iomem *ioaddr = tp->mmio_addr;
1387         unsigned int i;
1388
1389         tp->phy_reset_enable(ioaddr);
1390         for (i = 0; i < 100; i++) {
1391                 if (!tp->phy_reset_pending(ioaddr))
1392                         return;
1393                 msleep(1);
1394         }
1395         if (netif_msg_link(tp))
1396                 printk(KERN_ERR "%s: PHY reset failed.\n", dev->name);
1397 }
1398
1399 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
1400 {
1401         void __iomem *ioaddr = tp->mmio_addr;
1402
1403         rtl_hw_phy_config(dev);
1404
1405         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
1406                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1407                 RTL_W8(0x82, 0x01);
1408         }
1409
1410         pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
1411
1412         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
1413                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
1414
1415         if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
1416                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1417                 RTL_W8(0x82, 0x01);
1418                 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
1419                 mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0
1420         }
1421
1422         rtl8169_phy_reset(dev, tp);
1423
1424         /*
1425          * rtl8169_set_speed_xmii takes good care of the Fast Ethernet
1426          * only 8101. Don't panic.
1427          */
1428         rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL);
1429
1430         if ((RTL_R8(PHYstatus) & TBI_Enable) && netif_msg_link(tp))
1431                 printk(KERN_INFO PFX "%s: TBI auto-negotiating\n", dev->name);
1432 }
1433
1434 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
1435 {
1436         void __iomem *ioaddr = tp->mmio_addr;
1437         u32 high;
1438         u32 low;
1439
1440         low  = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
1441         high = addr[4] | (addr[5] << 8);
1442
1443         spin_lock_irq(&tp->lock);
1444
1445         RTL_W8(Cfg9346, Cfg9346_Unlock);
1446         RTL_W32(MAC0, low);
1447         RTL_W32(MAC4, high);
1448         RTL_W8(Cfg9346, Cfg9346_Lock);
1449
1450         spin_unlock_irq(&tp->lock);
1451 }
1452
1453 static int rtl_set_mac_address(struct net_device *dev, void *p)
1454 {
1455         struct rtl8169_private *tp = netdev_priv(dev);
1456         struct sockaddr *addr = p;
1457
1458         if (!is_valid_ether_addr(addr->sa_data))
1459                 return -EADDRNOTAVAIL;
1460
1461         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1462
1463         rtl_rar_set(tp, dev->dev_addr);
1464
1465         return 0;
1466 }
1467
1468 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1469 {
1470         struct rtl8169_private *tp = netdev_priv(dev);
1471         struct mii_ioctl_data *data = if_mii(ifr);
1472
1473         if (!netif_running(dev))
1474                 return -ENODEV;
1475
1476         switch (cmd) {
1477         case SIOCGMIIPHY:
1478                 data->phy_id = 32; /* Internal PHY */
1479                 return 0;
1480
1481         case SIOCGMIIREG:
1482                 data->val_out = mdio_read(tp->mmio_addr, data->reg_num & 0x1f);
1483                 return 0;
1484
1485         case SIOCSMIIREG:
1486                 if (!capable(CAP_NET_ADMIN))
1487                         return -EPERM;
1488                 mdio_write(tp->mmio_addr, data->reg_num & 0x1f, data->val_in);
1489                 return 0;
1490         }
1491         return -EOPNOTSUPP;
1492 }
1493
1494 static const struct rtl_cfg_info {
1495         void (*hw_start)(struct net_device *);
1496         unsigned int region;
1497         unsigned int align;
1498         u16 intr_event;
1499         u16 napi_event;
1500         unsigned features;
1501 } rtl_cfg_infos [] = {
1502         [RTL_CFG_0] = {
1503                 .hw_start       = rtl_hw_start_8169,
1504                 .region         = 1,
1505                 .align          = 0,
1506                 .intr_event     = SYSErr | LinkChg | RxOverflow |
1507                                   RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
1508                 .napi_event     = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
1509                 .features       = RTL_FEATURE_GMII
1510         },
1511         [RTL_CFG_1] = {
1512                 .hw_start       = rtl_hw_start_8168,
1513                 .region         = 2,
1514                 .align          = 8,
1515                 .intr_event     = SYSErr | LinkChg | RxOverflow |
1516                                   TxErr | TxOK | RxOK | RxErr,
1517                 .napi_event     = TxErr | TxOK | RxOK | RxOverflow,
1518                 .features       = RTL_FEATURE_GMII | RTL_FEATURE_MSI
1519         },
1520         [RTL_CFG_2] = {
1521                 .hw_start       = rtl_hw_start_8101,
1522                 .region         = 2,
1523                 .align          = 8,
1524                 .intr_event     = SYSErr | LinkChg | RxOverflow | PCSTimeout |
1525                                   RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
1526                 .napi_event     = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
1527                 .features       = RTL_FEATURE_MSI
1528         }
1529 };
1530
1531 /* Cfg9346_Unlock assumed. */
1532 static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
1533                             const struct rtl_cfg_info *cfg)
1534 {
1535         unsigned msi = 0;
1536         u8 cfg2;
1537
1538         cfg2 = RTL_R8(Config2) & ~MSIEnable;
1539         if (cfg->features & RTL_FEATURE_MSI) {
1540                 if (pci_enable_msi(pdev)) {
1541                         dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
1542                 } else {
1543                         cfg2 |= MSIEnable;
1544                         msi = RTL_FEATURE_MSI;
1545                 }
1546         }
1547         RTL_W8(Config2, cfg2);
1548         return msi;
1549 }
1550
1551 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
1552 {
1553         if (tp->features & RTL_FEATURE_MSI) {
1554                 pci_disable_msi(pdev);
1555                 tp->features &= ~RTL_FEATURE_MSI;
1556         }
1557 }
1558
1559 static int __devinit
1560 rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1561 {
1562         const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
1563         const unsigned int region = cfg->region;
1564         struct rtl8169_private *tp;
1565         struct mii_if_info *mii;
1566         struct net_device *dev;
1567         void __iomem *ioaddr;
1568         unsigned int i;
1569         int rc;
1570
1571         if (netif_msg_drv(&debug)) {
1572                 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
1573                        MODULENAME, RTL8169_VERSION);
1574         }
1575
1576         dev = alloc_etherdev(sizeof (*tp));
1577         if (!dev) {
1578                 if (netif_msg_drv(&debug))
1579                         dev_err(&pdev->dev, "unable to alloc new ethernet\n");
1580                 rc = -ENOMEM;
1581                 goto out;
1582         }
1583
1584         SET_NETDEV_DEV(dev, &pdev->dev);
1585         tp = netdev_priv(dev);
1586         tp->dev = dev;
1587         tp->pci_dev = pdev;
1588         tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
1589
1590         mii = &tp->mii;
1591         mii->dev = dev;
1592         mii->mdio_read = rtl_mdio_read;
1593         mii->mdio_write = rtl_mdio_write;
1594         mii->phy_id_mask = 0x1f;
1595         mii->reg_num_mask = 0x1f;
1596         mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
1597
1598         /* enable device (incl. PCI PM wakeup and hotplug setup) */
1599         rc = pci_enable_device(pdev);
1600         if (rc < 0) {
1601                 if (netif_msg_probe(tp))
1602                         dev_err(&pdev->dev, "enable failure\n");
1603                 goto err_out_free_dev_1;
1604         }
1605
1606         rc = pci_set_mwi(pdev);
1607         if (rc < 0)
1608                 goto err_out_disable_2;
1609
1610         /* make sure PCI base addr 1 is MMIO */
1611         if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
1612                 if (netif_msg_probe(tp)) {
1613                         dev_err(&pdev->dev,
1614                                 "region #%d not an MMIO resource, aborting\n",
1615                                 region);
1616                 }
1617                 rc = -ENODEV;
1618                 goto err_out_mwi_3;
1619         }
1620
1621         /* check for weird/broken PCI region reporting */
1622         if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
1623                 if (netif_msg_probe(tp)) {
1624                         dev_err(&pdev->dev,
1625                                 "Invalid PCI region size(s), aborting\n");
1626                 }
1627                 rc = -ENODEV;
1628                 goto err_out_mwi_3;
1629         }
1630
1631         rc = pci_request_regions(pdev, MODULENAME);
1632         if (rc < 0) {
1633                 if (netif_msg_probe(tp))
1634                         dev_err(&pdev->dev, "could not request regions.\n");
1635                 goto err_out_mwi_3;
1636         }
1637
1638         tp->cp_cmd = PCIMulRW | RxChkSum;
1639
1640         if ((sizeof(dma_addr_t) > 4) &&
1641             !pci_set_dma_mask(pdev, DMA_64BIT_MASK) && use_dac) {
1642                 tp->cp_cmd |= PCIDAC;
1643                 dev->features |= NETIF_F_HIGHDMA;
1644         } else {
1645                 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1646                 if (rc < 0) {
1647                         if (netif_msg_probe(tp)) {
1648                                 dev_err(&pdev->dev,
1649                                         "DMA configuration failed.\n");
1650                         }
1651                         goto err_out_free_res_4;
1652                 }
1653         }
1654
1655         pci_set_master(pdev);
1656
1657         /* ioremap MMIO region */
1658         ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
1659         if (!ioaddr) {
1660                 if (netif_msg_probe(tp))
1661                         dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
1662                 rc = -EIO;
1663                 goto err_out_free_res_4;
1664         }
1665
1666         /* Unneeded ? Don't mess with Mrs. Murphy. */
1667         rtl8169_irq_mask_and_ack(ioaddr);
1668
1669         /* Soft reset the chip. */
1670         RTL_W8(ChipCmd, CmdReset);
1671
1672         /* Check that the chip has finished the reset. */
1673         for (i = 0; i < 100; i++) {
1674                 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1675                         break;
1676                 msleep_interruptible(1);
1677         }
1678
1679         /* Identify chip attached to board */
1680         rtl8169_get_mac_version(tp, ioaddr);
1681
1682         rtl8169_print_mac_version(tp);
1683
1684         for (i = 0; i < ARRAY_SIZE(rtl_chip_info); i++) {
1685                 if (tp->mac_version == rtl_chip_info[i].mac_version)
1686                         break;
1687         }
1688         if (i == ARRAY_SIZE(rtl_chip_info)) {
1689                 /* Unknown chip: assume array element #0, original RTL-8169 */
1690                 if (netif_msg_probe(tp)) {
1691                         dev_printk(KERN_DEBUG, &pdev->dev,
1692                                 "unknown chip version, assuming %s\n",
1693                                 rtl_chip_info[0].name);
1694                 }
1695                 i = 0;
1696         }
1697         tp->chipset = i;
1698
1699         RTL_W8(Cfg9346, Cfg9346_Unlock);
1700         RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
1701         RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
1702         tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
1703         RTL_W8(Cfg9346, Cfg9346_Lock);
1704
1705         if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
1706             (RTL_R8(PHYstatus) & TBI_Enable)) {
1707                 tp->set_speed = rtl8169_set_speed_tbi;
1708                 tp->get_settings = rtl8169_gset_tbi;
1709                 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
1710                 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
1711                 tp->link_ok = rtl8169_tbi_link_ok;
1712
1713                 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
1714         } else {
1715                 tp->set_speed = rtl8169_set_speed_xmii;
1716                 tp->get_settings = rtl8169_gset_xmii;
1717                 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
1718                 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
1719                 tp->link_ok = rtl8169_xmii_link_ok;
1720
1721                 dev->do_ioctl = rtl8169_ioctl;
1722         }
1723
1724         /* Get MAC address.  FIXME: read EEPROM */
1725         for (i = 0; i < MAC_ADDR_LEN; i++)
1726                 dev->dev_addr[i] = RTL_R8(MAC0 + i);
1727         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1728
1729         dev->open = rtl8169_open;
1730         dev->hard_start_xmit = rtl8169_start_xmit;
1731         dev->get_stats = rtl8169_get_stats;
1732         SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
1733         dev->stop = rtl8169_close;
1734         dev->tx_timeout = rtl8169_tx_timeout;
1735         dev->set_multicast_list = rtl_set_rx_mode;
1736         dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
1737         dev->irq = pdev->irq;
1738         dev->base_addr = (unsigned long) ioaddr;
1739         dev->change_mtu = rtl8169_change_mtu;
1740         dev->set_mac_address = rtl_set_mac_address;
1741
1742         netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
1743
1744 #ifdef CONFIG_R8169_VLAN
1745         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1746         dev->vlan_rx_register = rtl8169_vlan_rx_register;
1747 #endif
1748
1749 #ifdef CONFIG_NET_POLL_CONTROLLER
1750         dev->poll_controller = rtl8169_netpoll;
1751 #endif
1752
1753         tp->intr_mask = 0xffff;
1754         tp->mmio_addr = ioaddr;
1755         tp->align = cfg->align;
1756         tp->hw_start = cfg->hw_start;
1757         tp->intr_event = cfg->intr_event;
1758         tp->napi_event = cfg->napi_event;
1759
1760         init_timer(&tp->timer);
1761         tp->timer.data = (unsigned long) dev;
1762         tp->timer.function = rtl8169_phy_timer;
1763
1764         spin_lock_init(&tp->lock);
1765
1766         rc = register_netdev(dev);
1767         if (rc < 0)
1768                 goto err_out_msi_5;
1769
1770         pci_set_drvdata(pdev, dev);
1771
1772         if (netif_msg_probe(tp)) {
1773                 u32 xid = RTL_R32(TxConfig) & 0x7cf0f8ff;
1774
1775                 printk(KERN_INFO "%s: %s at 0x%lx, "
1776                        "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
1777                        "XID %08x IRQ %d\n",
1778                        dev->name,
1779                        rtl_chip_info[tp->chipset].name,
1780                        dev->base_addr,
1781                        dev->dev_addr[0], dev->dev_addr[1],
1782                        dev->dev_addr[2], dev->dev_addr[3],
1783                        dev->dev_addr[4], dev->dev_addr[5], xid, dev->irq);
1784         }
1785
1786         rtl8169_init_phy(dev, tp);
1787
1788 out:
1789         return rc;
1790
1791 err_out_msi_5:
1792         rtl_disable_msi(pdev, tp);
1793         iounmap(ioaddr);
1794 err_out_free_res_4:
1795         pci_release_regions(pdev);
1796 err_out_mwi_3:
1797         pci_clear_mwi(pdev);
1798 err_out_disable_2:
1799         pci_disable_device(pdev);
1800 err_out_free_dev_1:
1801         free_netdev(dev);
1802         goto out;
1803 }
1804
1805 static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
1806 {
1807         struct net_device *dev = pci_get_drvdata(pdev);
1808         struct rtl8169_private *tp = netdev_priv(dev);
1809
1810         flush_scheduled_work();
1811
1812         unregister_netdev(dev);
1813         rtl_disable_msi(pdev, tp);
1814         rtl8169_release_board(pdev, dev, tp->mmio_addr);
1815         pci_set_drvdata(pdev, NULL);
1816 }
1817
1818 static void rtl8169_set_rxbufsize(struct rtl8169_private *tp,
1819                                   struct net_device *dev)
1820 {
1821         unsigned int mtu = dev->mtu;
1822
1823         tp->rx_buf_sz = (mtu > RX_BUF_SIZE) ? mtu + ETH_HLEN + 8 : RX_BUF_SIZE;
1824 }
1825
1826 static int rtl8169_open(struct net_device *dev)
1827 {
1828         struct rtl8169_private *tp = netdev_priv(dev);
1829         struct pci_dev *pdev = tp->pci_dev;
1830         int retval = -ENOMEM;
1831
1832
1833         rtl8169_set_rxbufsize(tp, dev);
1834
1835         /*
1836          * Rx and Tx desscriptors needs 256 bytes alignment.
1837          * pci_alloc_consistent provides more.
1838          */
1839         tp->TxDescArray = pci_alloc_consistent(pdev, R8169_TX_RING_BYTES,
1840                                                &tp->TxPhyAddr);
1841         if (!tp->TxDescArray)
1842                 goto out;
1843
1844         tp->RxDescArray = pci_alloc_consistent(pdev, R8169_RX_RING_BYTES,
1845                                                &tp->RxPhyAddr);
1846         if (!tp->RxDescArray)
1847                 goto err_free_tx_0;
1848
1849         retval = rtl8169_init_ring(dev);
1850         if (retval < 0)
1851                 goto err_free_rx_1;
1852
1853         INIT_DELAYED_WORK(&tp->task, NULL);
1854
1855         smp_mb();
1856
1857         retval = request_irq(dev->irq, rtl8169_interrupt,
1858                              (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
1859                              dev->name, dev);
1860         if (retval < 0)
1861                 goto err_release_ring_2;
1862
1863         napi_enable(&tp->napi);
1864
1865         rtl_hw_start(dev);
1866
1867         rtl8169_request_timer(dev);
1868
1869         rtl8169_check_link_status(dev, tp, tp->mmio_addr);
1870 out:
1871         return retval;
1872
1873 err_release_ring_2:
1874         rtl8169_rx_clear(tp);
1875 err_free_rx_1:
1876         pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
1877                             tp->RxPhyAddr);
1878 err_free_tx_0:
1879         pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
1880                             tp->TxPhyAddr);
1881         goto out;
1882 }
1883
1884 static void rtl8169_hw_reset(void __iomem *ioaddr)
1885 {
1886         /* Disable interrupts */
1887         rtl8169_irq_mask_and_ack(ioaddr);
1888
1889         /* Reset the chipset */
1890         RTL_W8(ChipCmd, CmdReset);
1891
1892         /* PCI commit */
1893         RTL_R8(ChipCmd);
1894 }
1895
1896 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
1897 {
1898         void __iomem *ioaddr = tp->mmio_addr;
1899         u32 cfg = rtl8169_rx_config;
1900
1901         cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
1902         RTL_W32(RxConfig, cfg);
1903
1904         /* Set DMA burst size and Interframe Gap Time */
1905         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
1906                 (InterFrameGap << TxInterFrameGapShift));
1907 }
1908
1909 static void rtl_hw_start(struct net_device *dev)
1910 {
1911         struct rtl8169_private *tp = netdev_priv(dev);
1912         void __iomem *ioaddr = tp->mmio_addr;
1913         unsigned int i;
1914
1915         /* Soft reset the chip. */
1916         RTL_W8(ChipCmd, CmdReset);
1917
1918         /* Check that the chip has finished the reset. */
1919         for (i = 0; i < 100; i++) {
1920                 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1921                         break;
1922                 msleep_interruptible(1);
1923         }
1924
1925         tp->hw_start(dev);
1926
1927         netif_start_queue(dev);
1928 }
1929
1930
1931 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
1932                                          void __iomem *ioaddr)
1933 {
1934         /*
1935          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
1936          * register to be written before TxDescAddrLow to work.
1937          * Switching from MMIO to I/O access fixes the issue as well.
1938          */
1939         RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
1940         RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_32BIT_MASK);
1941         RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
1942         RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_32BIT_MASK);
1943 }
1944
1945 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
1946 {
1947         u16 cmd;
1948
1949         cmd = RTL_R16(CPlusCmd);
1950         RTL_W16(CPlusCmd, cmd);
1951         return cmd;
1952 }
1953
1954 static void rtl_set_rx_max_size(void __iomem *ioaddr)
1955 {
1956         /* Low hurts. Let's disable the filtering. */
1957         RTL_W16(RxMaxSize, 16383);
1958 }
1959
1960 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
1961 {
1962         struct {
1963                 u32 mac_version;
1964                 u32 clk;
1965                 u32 val;
1966         } cfg2_info [] = {
1967                 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
1968                 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
1969                 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
1970                 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
1971         }, *p = cfg2_info;
1972         unsigned int i;
1973         u32 clk;
1974
1975         clk = RTL_R8(Config2) & PCI_Clock_66MHz;
1976         for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
1977                 if ((p->mac_version == mac_version) && (p->clk == clk)) {
1978                         RTL_W32(0x7c, p->val);
1979                         break;
1980                 }
1981         }
1982 }
1983
1984 static void rtl_hw_start_8169(struct net_device *dev)
1985 {
1986         struct rtl8169_private *tp = netdev_priv(dev);
1987         void __iomem *ioaddr = tp->mmio_addr;
1988         struct pci_dev *pdev = tp->pci_dev;
1989
1990         if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
1991                 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
1992                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
1993         }
1994
1995         RTL_W8(Cfg9346, Cfg9346_Unlock);
1996         if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
1997             (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
1998             (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
1999             (tp->mac_version == RTL_GIGA_MAC_VER_04))
2000                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2001
2002         RTL_W8(EarlyTxThres, EarlyTxThld);
2003
2004         rtl_set_rx_max_size(ioaddr);
2005
2006         if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
2007             (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2008             (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
2009             (tp->mac_version == RTL_GIGA_MAC_VER_04))
2010                 rtl_set_rx_tx_config_registers(tp);
2011
2012         tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
2013
2014         if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2015             (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
2016                 dprintk("Set MAC Reg C+CR Offset 0xE0. "
2017                         "Bit-3 and bit-14 MUST be 1\n");
2018                 tp->cp_cmd |= (1 << 14);
2019         }
2020
2021         RTL_W16(CPlusCmd, tp->cp_cmd);
2022
2023         rtl8169_set_magic_reg(ioaddr, tp->mac_version);
2024
2025         /*
2026          * Undocumented corner. Supposedly:
2027          * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
2028          */
2029         RTL_W16(IntrMitigate, 0x0000);
2030
2031         rtl_set_rx_tx_desc_registers(tp, ioaddr);
2032
2033         if ((tp->mac_version != RTL_GIGA_MAC_VER_01) &&
2034             (tp->mac_version != RTL_GIGA_MAC_VER_02) &&
2035             (tp->mac_version != RTL_GIGA_MAC_VER_03) &&
2036             (tp->mac_version != RTL_GIGA_MAC_VER_04)) {
2037                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2038                 rtl_set_rx_tx_config_registers(tp);
2039         }
2040
2041         RTL_W8(Cfg9346, Cfg9346_Lock);
2042
2043         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
2044         RTL_R8(IntrMask);
2045
2046         RTL_W32(RxMissed, 0);
2047
2048         rtl_set_rx_mode(dev);
2049
2050         /* no early-rx interrupts */
2051         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
2052
2053         /* Enable all known interrupts by setting the interrupt mask. */
2054         RTL_W16(IntrMask, tp->intr_event);
2055 }
2056
2057 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u8 force)
2058 {
2059         u8 ctl;
2060
2061         pci_read_config_byte(pdev, 0x69, &ctl);
2062         ctl = (ctl & ~0x70) | force;
2063         pci_write_config_byte(pdev, 0x69, ctl);
2064 }
2065
2066 static void rtl_hw_start_8168(struct net_device *dev)
2067 {
2068         struct rtl8169_private *tp = netdev_priv(dev);
2069         void __iomem *ioaddr = tp->mmio_addr;
2070         struct pci_dev *pdev = tp->pci_dev;
2071
2072         RTL_W8(Cfg9346, Cfg9346_Unlock);
2073
2074         RTL_W8(EarlyTxThres, EarlyTxThld);
2075
2076         rtl_set_rx_max_size(ioaddr);
2077
2078         rtl_set_rx_tx_config_registers(tp);
2079
2080         tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
2081
2082         RTL_W16(CPlusCmd, tp->cp_cmd);
2083
2084         rtl_tx_performance_tweak(pdev, 0x50);
2085
2086         RTL_W16(IntrMitigate, 0x5151);
2087
2088         /* Work around for RxFIFO overflow. */
2089         if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
2090                 tp->intr_event |= RxFIFOOver | PCSTimeout;
2091                 tp->intr_event &= ~RxOverflow;
2092         }
2093
2094         rtl_set_rx_tx_desc_registers(tp, ioaddr);
2095
2096         RTL_W8(Cfg9346, Cfg9346_Lock);
2097
2098         RTL_R8(IntrMask);
2099
2100         RTL_W32(RxMissed, 0);
2101
2102         rtl_set_rx_mode(dev);
2103
2104         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2105
2106         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
2107
2108         RTL_W16(IntrMask, tp->intr_event);
2109 }
2110
2111 static void rtl_hw_start_8101(struct net_device *dev)
2112 {
2113         struct rtl8169_private *tp = netdev_priv(dev);
2114         void __iomem *ioaddr = tp->mmio_addr;
2115         struct pci_dev *pdev = tp->pci_dev;
2116
2117         if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
2118             (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
2119                 pci_write_config_word(pdev, 0x68, 0x00);
2120                 pci_write_config_word(pdev, 0x69, 0x08);
2121         }
2122
2123         RTL_W8(Cfg9346, Cfg9346_Unlock);
2124
2125         RTL_W8(EarlyTxThres, EarlyTxThld);
2126
2127         rtl_set_rx_max_size(ioaddr);
2128
2129         tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
2130
2131         RTL_W16(CPlusCmd, tp->cp_cmd);
2132
2133         RTL_W16(IntrMitigate, 0x0000);
2134
2135         rtl_set_rx_tx_desc_registers(tp, ioaddr);
2136
2137         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2138         rtl_set_rx_tx_config_registers(tp);
2139
2140         RTL_W8(Cfg9346, Cfg9346_Lock);
2141
2142         RTL_R8(IntrMask);
2143
2144         RTL_W32(RxMissed, 0);
2145
2146         rtl_set_rx_mode(dev);
2147
2148         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2149
2150         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
2151
2152         RTL_W16(IntrMask, tp->intr_event);
2153 }
2154
2155 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
2156 {
2157         struct rtl8169_private *tp = netdev_priv(dev);
2158         int ret = 0;
2159
2160         if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
2161                 return -EINVAL;
2162
2163         dev->mtu = new_mtu;
2164
2165         if (!netif_running(dev))
2166                 goto out;
2167
2168         rtl8169_down(dev);
2169
2170         rtl8169_set_rxbufsize(tp, dev);
2171
2172         ret = rtl8169_init_ring(dev);
2173         if (ret < 0)
2174                 goto out;
2175
2176         napi_enable(&tp->napi);
2177
2178         rtl_hw_start(dev);
2179
2180         rtl8169_request_timer(dev);
2181
2182 out:
2183         return ret;
2184 }
2185
2186 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
2187 {
2188         desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
2189         desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
2190 }
2191
2192 static void rtl8169_free_rx_skb(struct rtl8169_private *tp,
2193                                 struct sk_buff **sk_buff, struct RxDesc *desc)
2194 {
2195         struct pci_dev *pdev = tp->pci_dev;
2196
2197         pci_unmap_single(pdev, le64_to_cpu(desc->addr), tp->rx_buf_sz,
2198                          PCI_DMA_FROMDEVICE);
2199         dev_kfree_skb(*sk_buff);
2200         *sk_buff = NULL;
2201         rtl8169_make_unusable_by_asic(desc);
2202 }
2203
2204 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
2205 {
2206         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
2207
2208         desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
2209 }
2210
2211 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
2212                                        u32 rx_buf_sz)
2213 {
2214         desc->addr = cpu_to_le64(mapping);
2215         wmb();
2216         rtl8169_mark_to_asic(desc, rx_buf_sz);
2217 }
2218
2219 static struct sk_buff *rtl8169_alloc_rx_skb(struct pci_dev *pdev,
2220                                             struct net_device *dev,
2221                                             struct RxDesc *desc, int rx_buf_sz,
2222                                             unsigned int align)
2223 {
2224         struct sk_buff *skb;
2225         dma_addr_t mapping;
2226         unsigned int pad;
2227
2228         pad = align ? align : NET_IP_ALIGN;
2229
2230         skb = netdev_alloc_skb(dev, rx_buf_sz + pad);
2231         if (!skb)
2232                 goto err_out;
2233
2234         skb_reserve(skb, align ? ((pad - 1) & (unsigned long)skb->data) : pad);
2235
2236         mapping = pci_map_single(pdev, skb->data, rx_buf_sz,
2237                                  PCI_DMA_FROMDEVICE);
2238
2239         rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
2240 out:
2241         return skb;
2242
2243 err_out:
2244         rtl8169_make_unusable_by_asic(desc);
2245         goto out;
2246 }
2247
2248 static void rtl8169_rx_clear(struct rtl8169_private *tp)
2249 {
2250         unsigned int i;
2251
2252         for (i = 0; i < NUM_RX_DESC; i++) {
2253                 if (tp->Rx_skbuff[i]) {
2254                         rtl8169_free_rx_skb(tp, tp->Rx_skbuff + i,
2255                                             tp->RxDescArray + i);
2256                 }
2257         }
2258 }
2259
2260 static u32 rtl8169_rx_fill(struct rtl8169_private *tp, struct net_device *dev,
2261                            u32 start, u32 end)
2262 {
2263         u32 cur;
2264
2265         for (cur = start; end - cur != 0; cur++) {
2266                 struct sk_buff *skb;
2267                 unsigned int i = cur % NUM_RX_DESC;
2268
2269                 WARN_ON((s32)(end - cur) < 0);
2270
2271                 if (tp->Rx_skbuff[i])
2272                         continue;
2273
2274                 skb = rtl8169_alloc_rx_skb(tp->pci_dev, dev,
2275                                            tp->RxDescArray + i,
2276                                            tp->rx_buf_sz, tp->align);
2277                 if (!skb)
2278                         break;
2279
2280                 tp->Rx_skbuff[i] = skb;
2281         }
2282         return cur - start;
2283 }
2284
2285 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
2286 {
2287         desc->opts1 |= cpu_to_le32(RingEnd);
2288 }
2289
2290 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
2291 {
2292         tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
2293 }
2294
2295 static int rtl8169_init_ring(struct net_device *dev)
2296 {
2297         struct rtl8169_private *tp = netdev_priv(dev);
2298
2299         rtl8169_init_ring_indexes(tp);
2300
2301         memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
2302         memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));
2303
2304         if (rtl8169_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC)
2305                 goto err_out;
2306
2307         rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
2308
2309         return 0;
2310
2311 err_out:
2312         rtl8169_rx_clear(tp);
2313         return -ENOMEM;
2314 }
2315
2316 static void rtl8169_unmap_tx_skb(struct pci_dev *pdev, struct ring_info *tx_skb,
2317                                  struct TxDesc *desc)
2318 {
2319         unsigned int len = tx_skb->len;
2320
2321         pci_unmap_single(pdev, le64_to_cpu(desc->addr), len, PCI_DMA_TODEVICE);
2322         desc->opts1 = 0x00;
2323         desc->opts2 = 0x00;
2324         desc->addr = 0x00;
2325         tx_skb->len = 0;
2326 }
2327
2328 static void rtl8169_tx_clear(struct rtl8169_private *tp)
2329 {
2330         unsigned int i;
2331
2332         for (i = tp->dirty_tx; i < tp->dirty_tx + NUM_TX_DESC; i++) {
2333                 unsigned int entry = i % NUM_TX_DESC;
2334                 struct ring_info *tx_skb = tp->tx_skb + entry;
2335                 unsigned int len = tx_skb->len;
2336
2337                 if (len) {
2338                         struct sk_buff *skb = tx_skb->skb;
2339
2340                         rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb,
2341                                              tp->TxDescArray + entry);
2342                         if (skb) {
2343                                 dev_kfree_skb(skb);
2344                                 tx_skb->skb = NULL;
2345                         }
2346                         tp->dev->stats.tx_dropped++;
2347                 }
2348         }
2349         tp->cur_tx = tp->dirty_tx = 0;
2350 }
2351
2352 static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
2353 {
2354         struct rtl8169_private *tp = netdev_priv(dev);
2355
2356         PREPARE_DELAYED_WORK(&tp->task, task);
2357         schedule_delayed_work(&tp->task, 4);
2358 }
2359
2360 static void rtl8169_wait_for_quiescence(struct net_device *dev)
2361 {
2362         struct rtl8169_private *tp = netdev_priv(dev);
2363         void __iomem *ioaddr = tp->mmio_addr;
2364
2365         synchronize_irq(dev->irq);
2366
2367         /* Wait for any pending NAPI task to complete */
2368         napi_disable(&tp->napi);
2369
2370         rtl8169_irq_mask_and_ack(ioaddr);
2371
2372         tp->intr_mask = 0xffff;
2373         RTL_W16(IntrMask, tp->intr_event);
2374         napi_enable(&tp->napi);
2375 }
2376
2377 static void rtl8169_reinit_task(struct work_struct *work)
2378 {
2379         struct rtl8169_private *tp =
2380                 container_of(work, struct rtl8169_private, task.work);
2381         struct net_device *dev = tp->dev;
2382         int ret;
2383
2384         rtnl_lock();
2385
2386         if (!netif_running(dev))
2387                 goto out_unlock;
2388
2389         rtl8169_wait_for_quiescence(dev);
2390         rtl8169_close(dev);
2391
2392         ret = rtl8169_open(dev);
2393         if (unlikely(ret < 0)) {
2394                 if (net_ratelimit() && netif_msg_drv(tp)) {
2395                         printk(KERN_ERR PFX "%s: reinit failure (status = %d)."
2396                                " Rescheduling.\n", dev->name, ret);
2397                 }
2398                 rtl8169_schedule_work(dev, rtl8169_reinit_task);
2399         }
2400
2401 out_unlock:
2402         rtnl_unlock();
2403 }
2404
2405 static void rtl8169_reset_task(struct work_struct *work)
2406 {
2407         struct rtl8169_private *tp =
2408                 container_of(work, struct rtl8169_private, task.work);
2409         struct net_device *dev = tp->dev;
2410
2411         rtnl_lock();
2412
2413         if (!netif_running(dev))
2414                 goto out_unlock;
2415
2416         rtl8169_wait_for_quiescence(dev);
2417
2418         rtl8169_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0);
2419         rtl8169_tx_clear(tp);
2420
2421         if (tp->dirty_rx == tp->cur_rx) {
2422                 rtl8169_init_ring_indexes(tp);
2423                 rtl_hw_start(dev);
2424                 netif_wake_queue(dev);
2425                 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
2426         } else {
2427                 if (net_ratelimit() && netif_msg_intr(tp)) {
2428                         printk(KERN_EMERG PFX "%s: Rx buffers shortage\n",
2429                                dev->name);
2430                 }
2431                 rtl8169_schedule_work(dev, rtl8169_reset_task);
2432         }
2433
2434 out_unlock:
2435         rtnl_unlock();
2436 }
2437
2438 static void rtl8169_tx_timeout(struct net_device *dev)
2439 {
2440         struct rtl8169_private *tp = netdev_priv(dev);
2441
2442         rtl8169_hw_reset(tp->mmio_addr);
2443
2444         /* Let's wait a bit while any (async) irq lands on */
2445         rtl8169_schedule_work(dev, rtl8169_reset_task);
2446 }
2447
2448 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
2449                               u32 opts1)
2450 {
2451         struct skb_shared_info *info = skb_shinfo(skb);
2452         unsigned int cur_frag, entry;
2453         struct TxDesc * uninitialized_var(txd);
2454
2455         entry = tp->cur_tx;
2456         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
2457                 skb_frag_t *frag = info->frags + cur_frag;
2458                 dma_addr_t mapping;
2459                 u32 status, len;
2460                 void *addr;
2461
2462                 entry = (entry + 1) % NUM_TX_DESC;
2463
2464                 txd = tp->TxDescArray + entry;
2465                 len = frag->size;
2466                 addr = ((void *) page_address(frag->page)) + frag->page_offset;
2467                 mapping = pci_map_single(tp->pci_dev, addr, len, PCI_DMA_TODEVICE);
2468
2469                 /* anti gcc 2.95.3 bugware (sic) */
2470                 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
2471
2472                 txd->opts1 = cpu_to_le32(status);
2473                 txd->addr = cpu_to_le64(mapping);
2474
2475                 tp->tx_skb[entry].len = len;
2476         }
2477
2478         if (cur_frag) {
2479                 tp->tx_skb[entry].skb = skb;
2480                 txd->opts1 |= cpu_to_le32(LastFrag);
2481         }
2482
2483         return cur_frag;
2484 }
2485
2486 static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
2487 {
2488         if (dev->features & NETIF_F_TSO) {
2489                 u32 mss = skb_shinfo(skb)->gso_size;
2490
2491                 if (mss)
2492                         return LargeSend | ((mss & MSSMask) << MSSShift);
2493         }
2494         if (skb->ip_summed == CHECKSUM_PARTIAL) {
2495                 const struct iphdr *ip = ip_hdr(skb);
2496
2497                 if (ip->protocol == IPPROTO_TCP)
2498                         return IPCS | TCPCS;
2499                 else if (ip->protocol == IPPROTO_UDP)
2500                         return IPCS | UDPCS;
2501                 WARN_ON(1);     /* we need a WARN() */
2502         }
2503         return 0;
2504 }
2505
2506 static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev)
2507 {
2508         struct rtl8169_private *tp = netdev_priv(dev);
2509         unsigned int frags, entry = tp->cur_tx % NUM_TX_DESC;
2510         struct TxDesc *txd = tp->TxDescArray + entry;
2511         void __iomem *ioaddr = tp->mmio_addr;
2512         dma_addr_t mapping;
2513         u32 status, len;
2514         u32 opts1;
2515         int ret = NETDEV_TX_OK;
2516
2517         if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
2518                 if (netif_msg_drv(tp)) {
2519                         printk(KERN_ERR
2520                                "%s: BUG! Tx Ring full when queue awake!\n",
2521                                dev->name);
2522                 }
2523                 goto err_stop;
2524         }
2525
2526         if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
2527                 goto err_stop;
2528
2529         opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
2530
2531         frags = rtl8169_xmit_frags(tp, skb, opts1);
2532         if (frags) {
2533                 len = skb_headlen(skb);
2534                 opts1 |= FirstFrag;
2535         } else {
2536                 len = skb->len;
2537
2538                 if (unlikely(len < ETH_ZLEN)) {
2539                         if (skb_padto(skb, ETH_ZLEN))
2540                                 goto err_update_stats;
2541                         len = ETH_ZLEN;
2542                 }
2543
2544                 opts1 |= FirstFrag | LastFrag;
2545                 tp->tx_skb[entry].skb = skb;
2546         }
2547
2548         mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
2549
2550         tp->tx_skb[entry].len = len;
2551         txd->addr = cpu_to_le64(mapping);
2552         txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
2553
2554         wmb();
2555
2556         /* anti gcc 2.95.3 bugware (sic) */
2557         status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
2558         txd->opts1 = cpu_to_le32(status);
2559
2560         dev->trans_start = jiffies;
2561
2562         tp->cur_tx += frags + 1;
2563
2564         smp_wmb();
2565
2566         RTL_W8(TxPoll, NPQ);    /* set polling bit */
2567
2568         if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
2569                 netif_stop_queue(dev);
2570                 smp_rmb();
2571                 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
2572                         netif_wake_queue(dev);
2573         }
2574
2575 out:
2576         return ret;
2577
2578 err_stop:
2579         netif_stop_queue(dev);
2580         ret = NETDEV_TX_BUSY;
2581 err_update_stats:
2582         dev->stats.tx_dropped++;
2583         goto out;
2584 }
2585
2586 static void rtl8169_pcierr_interrupt(struct net_device *dev)
2587 {
2588         struct rtl8169_private *tp = netdev_priv(dev);
2589         struct pci_dev *pdev = tp->pci_dev;
2590         void __iomem *ioaddr = tp->mmio_addr;
2591         u16 pci_status, pci_cmd;
2592
2593         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2594         pci_read_config_word(pdev, PCI_STATUS, &pci_status);
2595
2596         if (netif_msg_intr(tp)) {
2597                 printk(KERN_ERR
2598                        "%s: PCI error (cmd = 0x%04x, status = 0x%04x).\n",
2599                        dev->name, pci_cmd, pci_status);
2600         }
2601
2602         /*
2603          * The recovery sequence below admits a very elaborated explanation:
2604          * - it seems to work;
2605          * - I did not see what else could be done;
2606          * - it makes iop3xx happy.
2607          *
2608          * Feel free to adjust to your needs.
2609          */
2610         if (pdev->broken_parity_status)
2611                 pci_cmd &= ~PCI_COMMAND_PARITY;
2612         else
2613                 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
2614
2615         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
2616
2617         pci_write_config_word(pdev, PCI_STATUS,
2618                 pci_status & (PCI_STATUS_DETECTED_PARITY |
2619                 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
2620                 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
2621
2622         /* The infamous DAC f*ckup only happens at boot time */
2623         if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
2624                 if (netif_msg_intr(tp))
2625                         printk(KERN_INFO "%s: disabling PCI DAC.\n", dev->name);
2626                 tp->cp_cmd &= ~PCIDAC;
2627                 RTL_W16(CPlusCmd, tp->cp_cmd);
2628                 dev->features &= ~NETIF_F_HIGHDMA;
2629         }
2630
2631         rtl8169_hw_reset(ioaddr);
2632
2633         rtl8169_schedule_work(dev, rtl8169_reinit_task);
2634 }
2635
2636 static void rtl8169_tx_interrupt(struct net_device *dev,
2637                                  struct rtl8169_private *tp,
2638                                  void __iomem *ioaddr)
2639 {
2640         unsigned int dirty_tx, tx_left;
2641
2642         dirty_tx = tp->dirty_tx;
2643         smp_rmb();
2644         tx_left = tp->cur_tx - dirty_tx;
2645
2646         while (tx_left > 0) {
2647                 unsigned int entry = dirty_tx % NUM_TX_DESC;
2648                 struct ring_info *tx_skb = tp->tx_skb + entry;
2649                 u32 len = tx_skb->len;
2650                 u32 status;
2651
2652                 rmb();
2653                 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
2654                 if (status & DescOwn)
2655                         break;
2656
2657                 dev->stats.tx_bytes += len;
2658                 dev->stats.tx_packets++;
2659
2660                 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, tp->TxDescArray + entry);
2661
2662                 if (status & LastFrag) {
2663                         dev_kfree_skb_irq(tx_skb->skb);
2664                         tx_skb->skb = NULL;
2665                 }
2666                 dirty_tx++;
2667                 tx_left--;
2668         }
2669
2670         if (tp->dirty_tx != dirty_tx) {
2671                 tp->dirty_tx = dirty_tx;
2672                 smp_wmb();
2673                 if (netif_queue_stopped(dev) &&
2674                     (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
2675                         netif_wake_queue(dev);
2676                 }
2677                 /*
2678                  * 8168 hack: TxPoll requests are lost when the Tx packets are
2679                  * too close. Let's kick an extra TxPoll request when a burst
2680                  * of start_xmit activity is detected (if it is not detected,
2681                  * it is slow enough). -- FR
2682                  */
2683                 smp_rmb();
2684                 if (tp->cur_tx != dirty_tx)
2685                         RTL_W8(TxPoll, NPQ);
2686         }
2687 }
2688
2689 static inline int rtl8169_fragmented_frame(u32 status)
2690 {
2691         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
2692 }
2693
2694 static inline void rtl8169_rx_csum(struct sk_buff *skb, struct RxDesc *desc)
2695 {
2696         u32 opts1 = le32_to_cpu(desc->opts1);
2697         u32 status = opts1 & RxProtoMask;
2698
2699         if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
2700             ((status == RxProtoUDP) && !(opts1 & UDPFail)) ||
2701             ((status == RxProtoIP) && !(opts1 & IPFail)))
2702                 skb->ip_summed = CHECKSUM_UNNECESSARY;
2703         else
2704                 skb->ip_summed = CHECKSUM_NONE;
2705 }
2706
2707 static inline bool rtl8169_try_rx_copy(struct sk_buff **sk_buff,
2708                                        struct rtl8169_private *tp, int pkt_size,
2709                                        dma_addr_t addr)
2710 {
2711         struct sk_buff *skb;
2712         bool done = false;
2713
2714         if (pkt_size >= rx_copybreak)
2715                 goto out;
2716
2717         skb = netdev_alloc_skb(tp->dev, pkt_size + NET_IP_ALIGN);
2718         if (!skb)
2719                 goto out;
2720
2721         pci_dma_sync_single_for_cpu(tp->pci_dev, addr, pkt_size,
2722                                     PCI_DMA_FROMDEVICE);
2723         skb_reserve(skb, NET_IP_ALIGN);
2724         skb_copy_from_linear_data(*sk_buff, skb->data, pkt_size);
2725         *sk_buff = skb;
2726         done = true;
2727 out:
2728         return done;
2729 }
2730
2731 static int rtl8169_rx_interrupt(struct net_device *dev,
2732                                 struct rtl8169_private *tp,
2733                                 void __iomem *ioaddr, u32 budget)
2734 {
2735         unsigned int cur_rx, rx_left;
2736         unsigned int delta, count;
2737
2738         cur_rx = tp->cur_rx;
2739         rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
2740         rx_left = min(rx_left, budget);
2741
2742         for (; rx_left > 0; rx_left--, cur_rx++) {
2743                 unsigned int entry = cur_rx % NUM_RX_DESC;
2744                 struct RxDesc *desc = tp->RxDescArray + entry;
2745                 u32 status;
2746
2747                 rmb();
2748                 status = le32_to_cpu(desc->opts1);
2749
2750                 if (status & DescOwn)
2751                         break;
2752                 if (unlikely(status & RxRES)) {
2753                         if (netif_msg_rx_err(tp)) {
2754                                 printk(KERN_INFO
2755                                        "%s: Rx ERROR. status = %08x\n",
2756                                        dev->name, status);
2757                         }
2758                         dev->stats.rx_errors++;
2759                         if (status & (RxRWT | RxRUNT))
2760                                 dev->stats.rx_length_errors++;
2761                         if (status & RxCRC)
2762                                 dev->stats.rx_crc_errors++;
2763                         if (status & RxFOVF) {
2764                                 rtl8169_schedule_work(dev, rtl8169_reset_task);
2765                                 dev->stats.rx_fifo_errors++;
2766                         }
2767                         rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
2768                 } else {
2769                         struct sk_buff *skb = tp->Rx_skbuff[entry];
2770                         dma_addr_t addr = le64_to_cpu(desc->addr);
2771                         int pkt_size = (status & 0x00001FFF) - 4;
2772                         struct pci_dev *pdev = tp->pci_dev;
2773
2774                         /*
2775                          * The driver does not support incoming fragmented
2776                          * frames. They are seen as a symptom of over-mtu
2777                          * sized frames.
2778                          */
2779                         if (unlikely(rtl8169_fragmented_frame(status))) {
2780                                 dev->stats.rx_dropped++;
2781                                 dev->stats.rx_length_errors++;
2782                                 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
2783                                 continue;
2784                         }
2785
2786                         rtl8169_rx_csum(skb, desc);
2787
2788                         if (rtl8169_try_rx_copy(&skb, tp, pkt_size, addr)) {
2789                                 pci_dma_sync_single_for_device(pdev, addr,
2790                                         pkt_size, PCI_DMA_FROMDEVICE);
2791                                 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
2792                         } else {
2793                                 pci_unmap_single(pdev, addr, pkt_size,
2794                                                  PCI_DMA_FROMDEVICE);
2795                                 tp->Rx_skbuff[entry] = NULL;
2796                         }
2797
2798                         skb_put(skb, pkt_size);
2799                         skb->protocol = eth_type_trans(skb, dev);
2800
2801                         if (rtl8169_rx_vlan_skb(tp, desc, skb) < 0)
2802                                 netif_receive_skb(skb);
2803
2804                         dev->last_rx = jiffies;
2805                         dev->stats.rx_bytes += pkt_size;
2806                         dev->stats.rx_packets++;
2807                 }
2808
2809                 /* Work around for AMD plateform. */
2810                 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
2811                     (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
2812                         desc->opts2 = 0;
2813                         cur_rx++;
2814                 }
2815         }
2816
2817         count = cur_rx - tp->cur_rx;
2818         tp->cur_rx = cur_rx;
2819
2820         delta = rtl8169_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx);
2821         if (!delta && count && netif_msg_intr(tp))
2822                 printk(KERN_INFO "%s: no Rx buffer allocated\n", dev->name);
2823         tp->dirty_rx += delta;
2824
2825         /*
2826          * FIXME: until there is periodic timer to try and refill the ring,
2827          * a temporary shortage may definitely kill the Rx process.
2828          * - disable the asic to try and avoid an overflow and kick it again
2829          *   after refill ?
2830          * - how do others driver handle this condition (Uh oh...).
2831          */
2832         if ((tp->dirty_rx + NUM_RX_DESC == tp->cur_rx) && netif_msg_intr(tp))
2833                 printk(KERN_EMERG "%s: Rx buffers exhausted\n", dev->name);
2834
2835         return count;
2836 }
2837
2838 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
2839 {
2840         struct net_device *dev = dev_instance;
2841         struct rtl8169_private *tp = netdev_priv(dev);
2842         void __iomem *ioaddr = tp->mmio_addr;
2843         int handled = 0;
2844         int status;
2845
2846         status = RTL_R16(IntrStatus);
2847
2848         /* hotplug/major error/no more work/shared irq */
2849         if ((status == 0xffff) || !status)
2850                 goto out;
2851
2852         handled = 1;
2853
2854         if (unlikely(!netif_running(dev))) {
2855                 rtl8169_asic_down(ioaddr);
2856                 goto out;
2857         }
2858
2859         status &= tp->intr_mask;
2860         RTL_W16(IntrStatus,
2861                 (status & RxFIFOOver) ? (status | RxOverflow) : status);
2862
2863         if (!(status & tp->intr_event))
2864                 goto out;
2865
2866         /* Work around for rx fifo overflow */
2867         if (unlikely(status & RxFIFOOver) &&
2868             (tp->mac_version == RTL_GIGA_MAC_VER_11)) {
2869                 netif_stop_queue(dev);
2870                 rtl8169_tx_timeout(dev);
2871                 goto out;
2872         }
2873
2874         if (unlikely(status & SYSErr)) {
2875                 rtl8169_pcierr_interrupt(dev);
2876                 goto out;
2877         }
2878
2879         if (status & LinkChg)
2880                 rtl8169_check_link_status(dev, tp, ioaddr);
2881
2882         if (status & tp->napi_event) {
2883                 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
2884                 tp->intr_mask = ~tp->napi_event;
2885
2886                 if (likely(netif_rx_schedule_prep(dev, &tp->napi)))
2887                         __netif_rx_schedule(dev, &tp->napi);
2888                 else if (netif_msg_intr(tp)) {
2889                         printk(KERN_INFO "%s: interrupt %04x in poll\n",
2890                                dev->name, status);
2891                 }
2892         }
2893 out:
2894         return IRQ_RETVAL(handled);
2895 }
2896
2897 static int rtl8169_poll(struct napi_struct *napi, int budget)
2898 {
2899         struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
2900         struct net_device *dev = tp->dev;
2901         void __iomem *ioaddr = tp->mmio_addr;
2902         int work_done;
2903
2904         work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
2905         rtl8169_tx_interrupt(dev, tp, ioaddr);
2906
2907         if (work_done < budget) {
2908                 netif_rx_complete(dev, napi);
2909                 tp->intr_mask = 0xffff;
2910                 /*
2911                  * 20040426: the barrier is not strictly required but the
2912                  * behavior of the irq handler could be less predictable
2913                  * without it. Btw, the lack of flush for the posted pci
2914                  * write is safe - FR
2915                  */
2916                 smp_wmb();
2917                 RTL_W16(IntrMask, tp->intr_event);
2918         }
2919
2920         return work_done;
2921 }
2922
2923 static void rtl8169_down(struct net_device *dev)
2924 {
2925         struct rtl8169_private *tp = netdev_priv(dev);
2926         void __iomem *ioaddr = tp->mmio_addr;
2927         unsigned int intrmask;
2928
2929         rtl8169_delete_timer(dev);
2930
2931         netif_stop_queue(dev);
2932
2933         napi_disable(&tp->napi);
2934
2935 core_down:
2936         spin_lock_irq(&tp->lock);
2937
2938         rtl8169_asic_down(ioaddr);
2939
2940         /* Update the error counts. */
2941         dev->stats.rx_missed_errors += RTL_R32(RxMissed);
2942         RTL_W32(RxMissed, 0);
2943
2944         spin_unlock_irq(&tp->lock);
2945
2946         synchronize_irq(dev->irq);
2947
2948         /* Give a racing hard_start_xmit a few cycles to complete. */
2949         synchronize_sched();  /* FIXME: should this be synchronize_irq()? */
2950
2951         /*
2952          * And now for the 50k$ question: are IRQ disabled or not ?
2953          *
2954          * Two paths lead here:
2955          * 1) dev->close
2956          *    -> netif_running() is available to sync the current code and the
2957          *       IRQ handler. See rtl8169_interrupt for details.
2958          * 2) dev->change_mtu
2959          *    -> rtl8169_poll can not be issued again and re-enable the
2960          *       interruptions. Let's simply issue the IRQ down sequence again.
2961          *
2962          * No loop if hotpluged or major error (0xffff).
2963          */
2964         intrmask = RTL_R16(IntrMask);
2965         if (intrmask && (intrmask != 0xffff))
2966                 goto core_down;
2967
2968         rtl8169_tx_clear(tp);
2969
2970         rtl8169_rx_clear(tp);
2971 }
2972
2973 static int rtl8169_close(struct net_device *dev)
2974 {
2975         struct rtl8169_private *tp = netdev_priv(dev);
2976         struct pci_dev *pdev = tp->pci_dev;
2977
2978         rtl8169_down(dev);
2979
2980         free_irq(dev->irq, dev);
2981
2982         pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
2983                             tp->RxPhyAddr);
2984         pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
2985                             tp->TxPhyAddr);
2986         tp->TxDescArray = NULL;
2987         tp->RxDescArray = NULL;
2988
2989         return 0;
2990 }
2991
2992 static void rtl_set_rx_mode(struct net_device *dev)
2993 {
2994         struct rtl8169_private *tp = netdev_priv(dev);
2995         void __iomem *ioaddr = tp->mmio_addr;
2996         unsigned long flags;
2997         u32 mc_filter[2];       /* Multicast hash filter */
2998         int rx_mode;
2999         u32 tmp = 0;
3000
3001         if (dev->flags & IFF_PROMISC) {
3002                 /* Unconditionally log net taps. */
3003                 if (netif_msg_link(tp)) {
3004                         printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n",
3005                                dev->name);
3006                 }
3007                 rx_mode =
3008                     AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
3009                     AcceptAllPhys;
3010                 mc_filter[1] = mc_filter[0] = 0xffffffff;
3011         } else if ((dev->mc_count > multicast_filter_limit)
3012                    || (dev->flags & IFF_ALLMULTI)) {
3013                 /* Too many to filter perfectly -- accept all multicasts. */
3014                 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
3015                 mc_filter[1] = mc_filter[0] = 0xffffffff;
3016         } else {
3017                 struct dev_mc_list *mclist;
3018                 unsigned int i;
3019
3020                 rx_mode = AcceptBroadcast | AcceptMyPhys;
3021                 mc_filter[1] = mc_filter[0] = 0;
3022                 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
3023                      i++, mclist = mclist->next) {
3024                         int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
3025                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
3026                         rx_mode |= AcceptMulticast;
3027                 }
3028         }
3029
3030         spin_lock_irqsave(&tp->lock, flags);
3031
3032         tmp = rtl8169_rx_config | rx_mode |
3033               (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
3034
3035         if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
3036                 u32 data = mc_filter[0];
3037
3038                 mc_filter[0] = swab32(mc_filter[1]);
3039                 mc_filter[1] = swab32(data);
3040         }
3041
3042         RTL_W32(MAR0 + 0, mc_filter[0]);
3043         RTL_W32(MAR0 + 4, mc_filter[1]);
3044
3045         RTL_W32(RxConfig, tmp);
3046
3047         spin_unlock_irqrestore(&tp->lock, flags);
3048 }
3049
3050 /**
3051  *  rtl8169_get_stats - Get rtl8169 read/write statistics
3052  *  @dev: The Ethernet Device to get statistics for
3053  *
3054  *  Get TX/RX statistics for rtl8169
3055  */
3056 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
3057 {
3058         struct rtl8169_private *tp = netdev_priv(dev);
3059         void __iomem *ioaddr = tp->mmio_addr;
3060         unsigned long flags;
3061
3062         if (netif_running(dev)) {
3063                 spin_lock_irqsave(&tp->lock, flags);
3064                 dev->stats.rx_missed_errors += RTL_R32(RxMissed);
3065                 RTL_W32(RxMissed, 0);
3066                 spin_unlock_irqrestore(&tp->lock, flags);
3067         }
3068
3069         return &dev->stats;
3070 }
3071
3072 #ifdef CONFIG_PM
3073
3074 static int rtl8169_suspend(struct pci_dev *pdev, pm_message_t state)
3075 {
3076         struct net_device *dev = pci_get_drvdata(pdev);
3077         struct rtl8169_private *tp = netdev_priv(dev);
3078         void __iomem *ioaddr = tp->mmio_addr;
3079
3080         if (!netif_running(dev))
3081                 goto out_pci_suspend;
3082
3083         netif_device_detach(dev);
3084         netif_stop_queue(dev);
3085
3086         spin_lock_irq(&tp->lock);
3087
3088         rtl8169_asic_down(ioaddr);
3089
3090         dev->stats.rx_missed_errors += RTL_R32(RxMissed);
3091         RTL_W32(RxMissed, 0);
3092
3093         spin_unlock_irq(&tp->lock);
3094
3095 out_pci_suspend:
3096         pci_save_state(pdev);
3097         pci_enable_wake(pdev, pci_choose_state(pdev, state),
3098                 (tp->features & RTL_FEATURE_WOL) ? 1 : 0);
3099         pci_set_power_state(pdev, pci_choose_state(pdev, state));
3100
3101         return 0;
3102 }
3103
3104 static int rtl8169_resume(struct pci_dev *pdev)
3105 {
3106         struct net_device *dev = pci_get_drvdata(pdev);
3107
3108         pci_set_power_state(pdev, PCI_D0);
3109         pci_restore_state(pdev);
3110         pci_enable_wake(pdev, PCI_D0, 0);
3111
3112         if (!netif_running(dev))
3113                 goto out;
3114
3115         netif_device_attach(dev);
3116
3117         rtl8169_schedule_work(dev, rtl8169_reset_task);
3118 out:
3119         return 0;
3120 }
3121
3122 #endif /* CONFIG_PM */
3123
3124 static struct pci_driver rtl8169_pci_driver = {
3125         .name           = MODULENAME,
3126         .id_table       = rtl8169_pci_tbl,
3127         .probe          = rtl8169_init_one,
3128         .remove         = __devexit_p(rtl8169_remove_one),
3129 #ifdef CONFIG_PM
3130         .suspend        = rtl8169_suspend,
3131         .resume         = rtl8169_resume,
3132 #endif
3133 };
3134
3135 static int __init rtl8169_init_module(void)
3136 {
3137         return pci_register_driver(&rtl8169_pci_driver);
3138 }
3139
3140 static void __exit rtl8169_cleanup_module(void)
3141 {
3142         pci_unregister_driver(&rtl8169_pci_driver);
3143 }
3144
3145 module_init(rtl8169_init_module);
3146 module_exit(rtl8169_cleanup_module);