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   1 /*
   2  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
   3  *
   4  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
   5  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
   6  * Copyright (c) a lot of people too. Please respect their work.
   7  *
   8  * See MAINTAINERS file for support contact information.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/moduleparam.h>
  13 #include <linux/pci.h>
  14 #include <linux/netdevice.h>
  15 #include <linux/etherdevice.h>
  16 #include <linux/delay.h>
  17 #include <linux/ethtool.h>
  18 #include <linux/mii.h>
  19 #include <linux/if_vlan.h>
  20 #include <linux/crc32.h>
  21 #include <linux/in.h>
  22 #include <linux/ip.h>
  23 #include <linux/tcp.h>
  24 #include <linux/init.h>
  25 #include <linux/dma-mapping.h>
  26
  27 #include <asm/system.h>
  28 #include <asm/io.h>
  29 #include <asm/irq.h>
  30
  31 #define RTL8169_VERSION "2.3LK-NAPI"
  32 #define MODULENAME "r8169"
  33 #define PFX MODULENAME ": "
  34
  35 #ifdef RTL8169_DEBUG
  36 #define assert(expr) \
  37         if (!(expr)) {                                  \
  38                 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
  39                 #expr,__FILE__,__func__,__LINE__);              \
  40         }
  41 #define dprintk(fmt, args...) \
  42         do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
  43 #else
  44 #define assert(expr) do {} while (0)
  45 #define dprintk(fmt, args...)   do {} while (0)
  46 #endif /* RTL8169_DEBUG */
  47
  48 #define R8169_MSG_DEFAULT \
  49         (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
  50
  51 #define TX_BUFFS_AVAIL(tp) \
  52         (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
  53
  54 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  55    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
  56 static const int multicast_filter_limit = 32;
  57
  58 /* MAC address length */
  59 #define MAC_ADDR_LEN    6
  60
  61 #define MAX_READ_REQUEST_SHIFT  12
  62 #define RX_FIFO_THRESH  7       /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
  63 #define RX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
  64 #define TX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
  65 #define EarlyTxThld     0x3F    /* 0x3F means NO early transmit */
  66 #define SafeMtu         0x1c20  /* ... actually life sucks beyond ~7k */
  67 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
  68
  69 #define R8169_REGS_SIZE         256
  70 #define R8169_NAPI_WEIGHT       64
  71 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
  72 #define NUM_RX_DESC     256     /* Number of Rx descriptor registers */
  73 #define RX_BUF_SIZE     1536    /* Rx Buffer size */
  74 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
  75 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
  76
  77 #define RTL8169_TX_TIMEOUT      (6*HZ)
  78 #define RTL8169_PHY_TIMEOUT     (10*HZ)
  79
  80 #define RTL_EEPROM_SIG          cpu_to_le32(0x8129)
  81 #define RTL_EEPROM_SIG_MASK     cpu_to_le32(0xffff)
  82 #define RTL_EEPROM_SIG_ADDR     0x0000
  83
  84 /* write/read MMIO register */
  85 #define RTL_W8(reg, val8)       writeb ((val8), ioaddr + (reg))
  86 #define RTL_W16(reg, val16)     writew ((val16), ioaddr + (reg))
  87 #define RTL_W32(reg, val32)     writel ((val32), ioaddr + (reg))
  88 #define RTL_R8(reg)             readb (ioaddr + (reg))
  89 #define RTL_R16(reg)            readw (ioaddr + (reg))
  90 #define RTL_R32(reg)            ((unsigned long) readl (ioaddr + (reg)))
  91
  92 enum mac_version {
  93         RTL_GIGA_MAC_NONE   = 0x00,
  94         RTL_GIGA_MAC_VER_01 = 0x01, // 8169
  95         RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
  96         RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
  97         RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
  98         RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
  99         RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
 100         RTL_GIGA_MAC_VER_07 = 0x07, // 8102e
 101         RTL_GIGA_MAC_VER_08 = 0x08, // 8102e
 102         RTL_GIGA_MAC_VER_09 = 0x09, // 8102e
 103         RTL_GIGA_MAC_VER_10 = 0x0a, // 8101e
 104         RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
 105         RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be
 106         RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb
 107         RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ?
 108         RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ?
 109         RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec
 110         RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf
 111         RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP
 112         RTL_GIGA_MAC_VER_19 = 0x13, // 8168C
 113         RTL_GIGA_MAC_VER_20 = 0x14, // 8168C
 114         RTL_GIGA_MAC_VER_21 = 0x15, // 8168C
 115         RTL_GIGA_MAC_VER_22 = 0x16, // 8168C
 116         RTL_GIGA_MAC_VER_23 = 0x17, // 8168CP
 117         RTL_GIGA_MAC_VER_24 = 0x18, // 8168CP
 118         RTL_GIGA_MAC_VER_25 = 0x19  // 8168D
 119 };
 120
 121 #define _R(NAME,MAC,MASK) \
 122         { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
 123
 124 static const struct {
 125         const char *name;
 126         u8 mac_version;
 127         u32 RxConfigMask;       /* Clears the bits supported by this chip */
 128 } rtl_chip_info[] = {
 129         _R("RTL8169",           RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
 130         _R("RTL8169s",          RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
 131         _R("RTL8110s",          RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
 132         _R("RTL8169sb/8110sb",  RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
 133         _R("RTL8169sc/8110sc",  RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
 134         _R("RTL8169sc/8110sc",  RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
 135         _R("RTL8102e",          RTL_GIGA_MAC_VER_07, 0xff7e1880), // PCI-E
 136         _R("RTL8102e",          RTL_GIGA_MAC_VER_08, 0xff7e1880), // PCI-E
 137         _R("RTL8102e",          RTL_GIGA_MAC_VER_09, 0xff7e1880), // PCI-E
 138         _R("RTL8101e",          RTL_GIGA_MAC_VER_10, 0xff7e1880), // PCI-E
 139         _R("RTL8168b/8111b",    RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
 140         _R("RTL8168b/8111b",    RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
 141         _R("RTL8101e",          RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
 142         _R("RTL8100e",          RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
 143         _R("RTL8100e",          RTL_GIGA_MAC_VER_15, 0xff7e1880), // PCI-E 8139
 144         _R("RTL8168b/8111b",    RTL_GIGA_MAC_VER_17, 0xff7e1880), // PCI-E
 145         _R("RTL8101e",          RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E
 146         _R("RTL8168cp/8111cp",  RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E
 147         _R("RTL8168c/8111c",    RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E
 148         _R("RTL8168c/8111c",    RTL_GIGA_MAC_VER_20, 0xff7e1880), // PCI-E
 149         _R("RTL8168c/8111c",    RTL_GIGA_MAC_VER_21, 0xff7e1880), // PCI-E
 150         _R("RTL8168c/8111c",    RTL_GIGA_MAC_VER_22, 0xff7e1880), // PCI-E
 151         _R("RTL8168cp/8111cp",  RTL_GIGA_MAC_VER_23, 0xff7e1880), // PCI-E
 152         _R("RTL8168cp/8111cp",  RTL_GIGA_MAC_VER_24, 0xff7e1880), // PCI-E
 153         _R("RTL8168d/8111d",    RTL_GIGA_MAC_VER_25, 0xff7e1880)  // PCI-E
 154 };
 155 #undef _R
 156
 157 enum cfg_version {
 158         RTL_CFG_0 = 0x00,
 159         RTL_CFG_1,
 160         RTL_CFG_2
 161 };
 162
 163 static void rtl_hw_start_8169(struct net_device *);
 164 static void rtl_hw_start_8168(struct net_device *);
 165 static void rtl_hw_start_8101(struct net_device *);
 166
 167 static struct pci_device_id rtl8169_pci_tbl[] = {
 168         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8129), 0, 0, RTL_CFG_0 },
 169         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8136), 0, 0, RTL_CFG_2 },
 170         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8167), 0, 0, RTL_CFG_0 },
 171         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8168), 0, 0, RTL_CFG_1 },
 172         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8169), 0, 0, RTL_CFG_0 },
 173         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4300), 0, 0, RTL_CFG_0 },
 174         { PCI_DEVICE(PCI_VENDOR_ID_AT,          0xc107), 0, 0, RTL_CFG_0 },
 175         { PCI_DEVICE(0x16ec,                    0x0116), 0, 0, RTL_CFG_0 },
 176         { PCI_VENDOR_ID_LINKSYS,                0x1032,
 177                 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
 178         { 0x0001,                               0x8168,
 179                 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
 180         {0,},
 181 };
 182
 183 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
 184
 185 static int rx_copybreak = 200;
 186 static int use_dac;
 187 static struct {
 188         u32 msg_enable;
 189 } debug = { -1 };
 190
 191 enum rtl_registers {
 192         MAC0            = 0,    /* Ethernet hardware address. */
 193         MAC4            = 4,
 194         MAR0            = 8,    /* Multicast filter. */
 195         CounterAddrLow          = 0x10,
 196         CounterAddrHigh         = 0x14,
 197         TxDescStartAddrLow      = 0x20,
 198         TxDescStartAddrHigh     = 0x24,
 199         TxHDescStartAddrLow     = 0x28,
 200         TxHDescStartAddrHigh    = 0x2c,
 201         FLASH           = 0x30,
 202         ERSR            = 0x36,
 203         ChipCmd         = 0x37,
 204         TxPoll          = 0x38,
 205         IntrMask        = 0x3c,
 206         IntrStatus      = 0x3e,
 207         TxConfig        = 0x40,
 208         RxConfig        = 0x44,
 209         RxMissed        = 0x4c,
 210         Cfg9346         = 0x50,
 211         Config0         = 0x51,
 212         Config1         = 0x52,
 213         Config2         = 0x53,
 214         Config3         = 0x54,
 215         Config4         = 0x55,
 216         Config5         = 0x56,
 217         MultiIntr       = 0x5c,
 218         PHYAR           = 0x60,
 219         PHYstatus       = 0x6c,
 220         RxMaxSize       = 0xda,
 221         CPlusCmd        = 0xe0,
 222         IntrMitigate    = 0xe2,
 223         RxDescAddrLow   = 0xe4,
 224         RxDescAddrHigh  = 0xe8,
 225         EarlyTxThres    = 0xec,
 226         FuncEvent       = 0xf0,
 227         FuncEventMask   = 0xf4,
 228         FuncPresetState = 0xf8,
 229         FuncForceEvent  = 0xfc,
 230 };
 231
 232 enum rtl8110_registers {
 233         TBICSR                  = 0x64,
 234         TBI_ANAR                = 0x68,
 235         TBI_LPAR                = 0x6a,
 236 };
 237
 238 enum rtl8168_8101_registers {
 239         CSIDR                   = 0x64,
 240         CSIAR                   = 0x68,
 241 #define CSIAR_FLAG                      0x80000000
 242 #define CSIAR_WRITE_CMD                 0x80000000
 243 #define CSIAR_BYTE_ENABLE               0x0f
 244 #define CSIAR_BYTE_ENABLE_SHIFT         12
 245 #define CSIAR_ADDR_MASK                 0x0fff
 246
 247         EPHYAR                  = 0x80,
 248 #define EPHYAR_FLAG                     0x80000000
 249 #define EPHYAR_WRITE_CMD                0x80000000
 250 #define EPHYAR_REG_MASK                 0x1f
 251 #define EPHYAR_REG_SHIFT                16
 252 #define EPHYAR_DATA_MASK                0xffff
 253         DBG_REG                 = 0xd1,
 254 #define FIX_NAK_1                       (1 << 4)
 255 #define FIX_NAK_2                       (1 << 3)
 256 };
 257
 258 enum rtl_register_content {
 259         /* InterruptStatusBits */
 260         SYSErr          = 0x8000,
 261         PCSTimeout      = 0x4000,
 262         SWInt           = 0x0100,
 263         TxDescUnavail   = 0x0080,
 264         RxFIFOOver      = 0x0040,
 265         LinkChg         = 0x0020,
 266         RxOverflow      = 0x0010,
 267         TxErr           = 0x0008,
 268         TxOK            = 0x0004,
 269         RxErr           = 0x0002,
 270         RxOK            = 0x0001,
 271
 272         /* RxStatusDesc */
 273         RxFOVF  = (1 << 23),
 274         RxRWT   = (1 << 22),
 275         RxRES   = (1 << 21),
 276         RxRUNT  = (1 << 20),
 277         RxCRC   = (1 << 19),
 278
 279         /* ChipCmdBits */
 280         CmdReset        = 0x10,
 281         CmdRxEnb        = 0x08,
 282         CmdTxEnb        = 0x04,
 283         RxBufEmpty      = 0x01,
 284
 285         /* TXPoll register p.5 */
 286         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
 287         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
 288         FSWInt          = 0x01,         /* Forced software interrupt */
 289
 290         /* Cfg9346Bits */
 291         Cfg9346_Lock    = 0x00,
 292         Cfg9346_Unlock  = 0xc0,
 293
 294         /* rx_mode_bits */
 295         AcceptErr       = 0x20,
 296         AcceptRunt      = 0x10,
 297         AcceptBroadcast = 0x08,
 298         AcceptMulticast = 0x04,
 299         AcceptMyPhys    = 0x02,
 300         AcceptAllPhys   = 0x01,
 301
 302         /* RxConfigBits */
 303         RxCfgFIFOShift  = 13,
 304         RxCfgDMAShift   =  8,
 305
 306         /* TxConfigBits */
 307         TxInterFrameGapShift = 24,
 308         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
 309
 310         /* Config1 register p.24 */
 311         LEDS1           = (1 << 7),
 312         LEDS0           = (1 << 6),
 313         MSIEnable       = (1 << 5),     /* Enable Message Signaled Interrupt */
 314         Speed_down      = (1 << 4),
 315         MEMMAP          = (1 << 3),
 316         IOMAP           = (1 << 2),
 317         VPD             = (1 << 1),
 318         PMEnable        = (1 << 0),     /* Power Management Enable */
 319
 320         /* Config2 register p. 25 */
 321         PCI_Clock_66MHz = 0x01,
 322         PCI_Clock_33MHz = 0x00,
 323
 324         /* Config3 register p.25 */
 325         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
 326         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
 327         Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
 328
 329         /* Config5 register p.27 */
 330         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
 331         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
 332         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
 333         LanWake         = (1 << 1),     /* LanWake enable/disable */
 334         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
 335
 336         /* TBICSR p.28 */
 337         TBIReset        = 0x80000000,
 338         TBILoopback     = 0x40000000,
 339         TBINwEnable     = 0x20000000,
 340         TBINwRestart    = 0x10000000,
 341         TBILinkOk       = 0x02000000,
 342         TBINwComplete   = 0x01000000,
 343
 344         /* CPlusCmd p.31 */
 345         EnableBist      = (1 << 15),    // 8168 8101
 346         Mac_dbgo_oe     = (1 << 14),    // 8168 8101
 347         Normal_mode     = (1 << 13),    // unused
 348         Force_half_dup  = (1 << 12),    // 8168 8101
 349         Force_rxflow_en = (1 << 11),    // 8168 8101
 350         Force_txflow_en = (1 << 10),    // 8168 8101
 351         Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
 352         ASF             = (1 << 8),     // 8168 8101
 353         PktCntrDisable  = (1 << 7),     // 8168 8101
 354         Mac_dbgo_sel    = 0x001c,       // 8168
 355         RxVlan          = (1 << 6),
 356         RxChkSum        = (1 << 5),
 357         PCIDAC          = (1 << 4),
 358         PCIMulRW        = (1 << 3),
 359         INTT_0          = 0x0000,       // 8168
 360         INTT_1          = 0x0001,       // 8168
 361         INTT_2          = 0x0002,       // 8168
 362         INTT_3          = 0x0003,       // 8168
 363
 364         /* rtl8169_PHYstatus */
 365         TBI_Enable      = 0x80,
 366         TxFlowCtrl      = 0x40,
 367         RxFlowCtrl      = 0x20,
 368         _1000bpsF       = 0x10,
 369         _100bps         = 0x08,
 370         _10bps          = 0x04,
 371         LinkStatus      = 0x02,
 372         FullDup         = 0x01,
 373
 374         /* _TBICSRBit */
 375         TBILinkOK       = 0x02000000,
 376
 377         /* DumpCounterCommand */
 378         CounterDump     = 0x8,
 379 };
 380
 381 enum desc_status_bit {
 382         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
 383         RingEnd         = (1 << 30), /* End of descriptor ring */
 384         FirstFrag       = (1 << 29), /* First segment of a packet */
 385         LastFrag        = (1 << 28), /* Final segment of a packet */
 386
 387         /* Tx private */
 388         LargeSend       = (1 << 27), /* TCP Large Send Offload (TSO) */
 389         MSSShift        = 16,        /* MSS value position */
 390         MSSMask         = 0xfff,     /* MSS value + LargeSend bit: 12 bits */
 391         IPCS            = (1 << 18), /* Calculate IP checksum */
 392         UDPCS           = (1 << 17), /* Calculate UDP/IP checksum */
 393         TCPCS           = (1 << 16), /* Calculate TCP/IP checksum */
 394         TxVlanTag       = (1 << 17), /* Add VLAN tag */
 395
 396         /* Rx private */
 397         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
 398         PID0            = (1 << 17), /* Protocol ID bit 2/2 */
 399
 400 #define RxProtoUDP      (PID1)
 401 #define RxProtoTCP      (PID0)
 402 #define RxProtoIP       (PID1 | PID0)
 403 #define RxProtoMask     RxProtoIP
 404
 405         IPFail          = (1 << 16), /* IP checksum failed */
 406         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
 407         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
 408         RxVlanTag       = (1 << 16), /* VLAN tag available */
 409 };
 410
 411 #define RsvdMask        0x3fffc000
 412
 413 struct TxDesc {
 414         __le32 opts1;
 415         __le32 opts2;
 416         __le64 addr;
 417 };
 418
 419 struct RxDesc {
 420         __le32 opts1;
 421         __le32 opts2;
 422         __le64 addr;
 423 };
 424
 425 struct ring_info {
 426         struct sk_buff  *skb;
 427         u32             len;
 428         u8              __pad[sizeof(void *) - sizeof(u32)];
 429 };
 430
 431 enum features {
 432         RTL_FEATURE_WOL         = (1 << 0),
 433         RTL_FEATURE_MSI         = (1 << 1),
 434         RTL_FEATURE_GMII        = (1 << 2),
 435 };
 436
 437 struct rtl8169_counters {
 438         __le64  tx_packets;
 439         __le64  rx_packets;
 440         __le64  tx_errors;
 441         __le32  rx_errors;
 442         __le16  rx_missed;
 443         __le16  align_errors;
 444         __le32  tx_one_collision;
 445         __le32  tx_multi_collision;
 446         __le64  rx_unicast;
 447         __le64  rx_broadcast;
 448         __le32  rx_multicast;
 449         __le16  tx_aborted;
 450         __le16  tx_underun;
 451 };
 452
 453 struct rtl8169_private {
 454         void __iomem *mmio_addr;        /* memory map physical address */
 455         struct pci_dev *pci_dev;        /* Index of PCI device */
 456         struct net_device *dev;
 457         struct napi_struct napi;
 458         spinlock_t lock;                /* spin lock flag */
 459         u32 msg_enable;
 460         int chipset;
 461         int mac_version;
 462         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
 463         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
 464         u32 dirty_rx;
 465         u32 dirty_tx;
 466         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
 467         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
 468         dma_addr_t TxPhyAddr;
 469         dma_addr_t RxPhyAddr;
 470         struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */
 471         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
 472         unsigned align;
 473         unsigned rx_buf_sz;
 474         struct timer_list timer;
 475         u16 cp_cmd;
 476         u16 intr_event;
 477         u16 napi_event;
 478         u16 intr_mask;
 479         int phy_1000_ctrl_reg;
 480 #ifdef CONFIG_R8169_VLAN
 481         struct vlan_group *vlgrp;
 482 #endif
 483         int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
 484         int (*get_settings)(struct net_device *, struct ethtool_cmd *);
 485         void (*phy_reset_enable)(void __iomem *);
 486         void (*hw_start)(struct net_device *);
 487         unsigned int (*phy_reset_pending)(void __iomem *);
 488         unsigned int (*link_ok)(void __iomem *);
 489         int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
 490         int pcie_cap;
 491         struct delayed_work task;
 492         unsigned features;
 493
 494         struct mii_if_info mii;
 495         struct rtl8169_counters counters;
 496 };
 497
 498 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
 499 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
 500 module_param(rx_copybreak, int, 0);
 501 MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
 502 module_param(use_dac, int, 0);
 503 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
 504 module_param_named(debug, debug.msg_enable, int, 0);
 505 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
 506 MODULE_LICENSE("GPL");
 507 MODULE_VERSION(RTL8169_VERSION);
 508
 509 static int rtl8169_open(struct net_device *dev);
 510 static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev);
 511 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
 512 static int rtl8169_init_ring(struct net_device *dev);
 513 static void rtl_hw_start(struct net_device *dev);
 514 static int rtl8169_close(struct net_device *dev);
 515 static void rtl_set_rx_mode(struct net_device *dev);
 516 static void rtl8169_tx_timeout(struct net_device *dev);
 517 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
 518 static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
 519                                 void __iomem *, u32 budget);
 520 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
 521 static void rtl8169_down(struct net_device *dev);
 522 static void rtl8169_rx_clear(struct rtl8169_private *tp);
 523 static int rtl8169_poll(struct napi_struct *napi, int budget);
 524
 525 static const unsigned int rtl8169_rx_config =
 526         (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
 527
 528 static void mdio_write(void __iomem *ioaddr, int reg_addr, int value)
 529 {
 530         int i;
 531
 532         RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
 533
 534         for (i = 20; i > 0; i--) {
 535                 /*
 536                  * Check if the RTL8169 has completed writing to the specified
 537                  * MII register.
 538                  */
 539                 if (!(RTL_R32(PHYAR) & 0x80000000))
 540                         break;
 541                 udelay(25);
 542         }
 543 }
 544
 545 static int mdio_read(void __iomem *ioaddr, int reg_addr)
 546 {
 547         int i, value = -1;
 548
 549         RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
 550
 551         for (i = 20; i > 0; i--) {
 552                 /*
 553                  * Check if the RTL8169 has completed retrieving data from
 554                  * the specified MII register.
 555                  */
 556                 if (RTL_R32(PHYAR) & 0x80000000) {
 557                         value = RTL_R32(PHYAR) & 0xffff;
 558                         break;
 559                 }
 560                 udelay(25);
 561         }
 562         return value;
 563 }
 564
 565 static void mdio_patch(void __iomem *ioaddr, int reg_addr, int value)
 566 {
 567         mdio_write(ioaddr, reg_addr, mdio_read(ioaddr, reg_addr) | value);
 568 }
 569
 570 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
 571                            int val)
 572 {
 573         struct rtl8169_private *tp = netdev_priv(dev);
 574         void __iomem *ioaddr = tp->mmio_addr;
 575
 576         mdio_write(ioaddr, location, val);
 577 }
 578
 579 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
 580 {
 581         struct rtl8169_private *tp = netdev_priv(dev);
 582         void __iomem *ioaddr = tp->mmio_addr;
 583
 584         return mdio_read(ioaddr, location);
 585 }
 586
 587 static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
 588 {
 589         unsigned int i;
 590
 591         RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
 592                 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
 593
 594         for (i = 0; i < 100; i++) {
 595                 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
 596                         break;
 597                 udelay(10);
 598         }
 599 }
 600
 601 static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
 602 {
 603         u16 value = 0xffff;
 604         unsigned int i;
 605
 606         RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
 607
 608         for (i = 0; i < 100; i++) {
 609                 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
 610                         value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
 611                         break;
 612                 }
 613                 udelay(10);
 614         }
 615
 616         return value;
 617 }
 618
 619 static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
 620 {
 621         unsigned int i;
 622
 623         RTL_W32(CSIDR, value);
 624         RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
 625                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
 626
 627         for (i = 0; i < 100; i++) {
 628                 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
 629                         break;
 630                 udelay(10);
 631         }
 632 }
 633
 634 static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
 635 {
 636         u32 value = ~0x00;
 637         unsigned int i;
 638
 639         RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
 640                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
 641
 642         for (i = 0; i < 100; i++) {
 643                 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
 644                         value = RTL_R32(CSIDR);
 645                         break;
 646                 }
 647                 udelay(10);
 648         }
 649
 650         return value;
 651 }
 652
 653 static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
 654 {
 655         RTL_W16(IntrMask, 0x0000);
 656
 657         RTL_W16(IntrStatus, 0xffff);
 658 }
 659
 660 static void rtl8169_asic_down(void __iomem *ioaddr)
 661 {
 662         RTL_W8(ChipCmd, 0x00);
 663         rtl8169_irq_mask_and_ack(ioaddr);
 664         RTL_R16(CPlusCmd);
 665 }
 666
 667 static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr)
 668 {
 669         return RTL_R32(TBICSR) & TBIReset;
 670 }
 671
 672 static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr)
 673 {
 674         return mdio_read(ioaddr, MII_BMCR) & BMCR_RESET;
 675 }
 676
 677 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
 678 {
 679         return RTL_R32(TBICSR) & TBILinkOk;
 680 }
 681
 682 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
 683 {
 684         return RTL_R8(PHYstatus) & LinkStatus;
 685 }
 686
 687 static void rtl8169_tbi_reset_enable(void __iomem *ioaddr)
 688 {
 689         RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
 690 }
 691
 692 static void rtl8169_xmii_reset_enable(void __iomem *ioaddr)
 693 {
 694         unsigned int val;
 695
 696         val = mdio_read(ioaddr, MII_BMCR) | BMCR_RESET;
 697         mdio_write(ioaddr, MII_BMCR, val & 0xffff);
 698 }
 699
 700 static void rtl8169_check_link_status(struct net_device *dev,
 701                                       struct rtl8169_private *tp,
 702                                       void __iomem *ioaddr)
 703 {
 704         unsigned long flags;
 705
 706         spin_lock_irqsave(&tp->lock, flags);
 707         if (tp->link_ok(ioaddr)) {
 708                 netif_carrier_on(dev);
 709                 if (netif_msg_ifup(tp))
 710                         printk(KERN_INFO PFX "%s: link up\n", dev->name);
 711         } else {
 712                 if (netif_msg_ifdown(tp))
 713                         printk(KERN_INFO PFX "%s: link down\n", dev->name);
 714                 netif_carrier_off(dev);
 715         }
 716         spin_unlock_irqrestore(&tp->lock, flags);
 717 }
 718
 719 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
 720 {
 721         struct rtl8169_private *tp = netdev_priv(dev);
 722         void __iomem *ioaddr = tp->mmio_addr;
 723         u8 options;
 724
 725         wol->wolopts = 0;
 726
 727 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
 728         wol->supported = WAKE_ANY;
 729
 730         spin_lock_irq(&tp->lock);
 731
 732         options = RTL_R8(Config1);
 733         if (!(options & PMEnable))
 734                 goto out_unlock;
 735
 736         options = RTL_R8(Config3);
 737         if (options & LinkUp)
 738                 wol->wolopts |= WAKE_PHY;
 739         if (options & MagicPacket)
 740                 wol->wolopts |= WAKE_MAGIC;
 741
 742         options = RTL_R8(Config5);
 743         if (options & UWF)
 744                 wol->wolopts |= WAKE_UCAST;
 745         if (options & BWF)
 746                 wol->wolopts |= WAKE_BCAST;
 747         if (options & MWF)
 748                 wol->wolopts |= WAKE_MCAST;
 749
 750 out_unlock:
 751         spin_unlock_irq(&tp->lock);
 752 }
 753
 754 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
 755 {
 756         struct rtl8169_private *tp = netdev_priv(dev);
 757         void __iomem *ioaddr = tp->mmio_addr;
 758         unsigned int i;
 759         static struct {
 760                 u32 opt;
 761                 u16 reg;
 762                 u8  mask;
 763         } cfg[] = {
 764                 { WAKE_ANY,   Config1, PMEnable },
 765                 { WAKE_PHY,   Config3, LinkUp },
 766                 { WAKE_MAGIC, Config3, MagicPacket },
 767                 { WAKE_UCAST, Config5, UWF },
 768                 { WAKE_BCAST, Config5, BWF },
 769                 { WAKE_MCAST, Config5, MWF },
 770                 { WAKE_ANY,   Config5, LanWake }
 771         };
 772
 773         spin_lock_irq(&tp->lock);
 774
 775         RTL_W8(Cfg9346, Cfg9346_Unlock);
 776
 777         for (i = 0; i < ARRAY_SIZE(cfg); i++) {
 778                 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
 779                 if (wol->wolopts & cfg[i].opt)
 780                         options |= cfg[i].mask;
 781                 RTL_W8(cfg[i].reg, options);
 782         }
 783
 784         RTL_W8(Cfg9346, Cfg9346_Lock);
 785
 786         if (wol->wolopts)
 787                 tp->features |= RTL_FEATURE_WOL;
 788         else
 789                 tp->features &= ~RTL_FEATURE_WOL;
 790         device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
 791
 792         spin_unlock_irq(&tp->lock);
 793
 794         return 0;
 795 }
 796
 797 static void rtl8169_get_drvinfo(struct net_device *dev,
 798                                 struct ethtool_drvinfo *info)
 799 {
 800         struct rtl8169_private *tp = netdev_priv(dev);
 801
 802         strcpy(info->driver, MODULENAME);
 803         strcpy(info->version, RTL8169_VERSION);
 804         strcpy(info->bus_info, pci_name(tp->pci_dev));
 805 }
 806
 807 static int rtl8169_get_regs_len(struct net_device *dev)
 808 {
 809         return R8169_REGS_SIZE;
 810 }
 811
 812 static int rtl8169_set_speed_tbi(struct net_device *dev,
 813                                  u8 autoneg, u16 speed, u8 duplex)
 814 {
 815         struct rtl8169_private *tp = netdev_priv(dev);
 816         void __iomem *ioaddr = tp->mmio_addr;
 817         int ret = 0;
 818         u32 reg;
 819
 820         reg = RTL_R32(TBICSR);
 821         if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
 822             (duplex == DUPLEX_FULL)) {
 823                 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
 824         } else if (autoneg == AUTONEG_ENABLE)
 825                 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
 826         else {
 827                 if (netif_msg_link(tp)) {
 828                         printk(KERN_WARNING "%s: "
 829                                "incorrect speed setting refused in TBI mode\n",
 830                                dev->name);
 831                 }
 832                 ret = -EOPNOTSUPP;
 833         }
 834
 835         return ret;
 836 }
 837
 838 static int rtl8169_set_speed_xmii(struct net_device *dev,
 839                                   u8 autoneg, u16 speed, u8 duplex)
 840 {
 841         struct rtl8169_private *tp = netdev_priv(dev);
 842         void __iomem *ioaddr = tp->mmio_addr;
 843         int giga_ctrl, bmcr;
 844
 845         if (autoneg == AUTONEG_ENABLE) {
 846                 int auto_nego;
 847
 848                 auto_nego = mdio_read(ioaddr, MII_ADVERTISE);
 849                 auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
 850                               ADVERTISE_100HALF | ADVERTISE_100FULL);
 851                 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
 852
 853                 giga_ctrl = mdio_read(ioaddr, MII_CTRL1000);
 854                 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
 855
 856                 /* The 8100e/8101e/8102e do Fast Ethernet only. */
 857                 if ((tp->mac_version != RTL_GIGA_MAC_VER_07) &&
 858                     (tp->mac_version != RTL_GIGA_MAC_VER_08) &&
 859                     (tp->mac_version != RTL_GIGA_MAC_VER_09) &&
 860                     (tp->mac_version != RTL_GIGA_MAC_VER_10) &&
 861                     (tp->mac_version != RTL_GIGA_MAC_VER_13) &&
 862                     (tp->mac_version != RTL_GIGA_MAC_VER_14) &&
 863                     (tp->mac_version != RTL_GIGA_MAC_VER_15) &&
 864                     (tp->mac_version != RTL_GIGA_MAC_VER_16)) {
 865                         giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
 866                 } else if (netif_msg_link(tp)) {
 867                         printk(KERN_INFO "%s: PHY does not support 1000Mbps.\n",
 868                                dev->name);
 869                 }
 870
 871                 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
 872
 873                 if ((tp->mac_version == RTL_GIGA_MAC_VER_11) ||
 874                     (tp->mac_version == RTL_GIGA_MAC_VER_12) ||
 875                     (tp->mac_version >= RTL_GIGA_MAC_VER_17)) {
 876                         /*
 877                          * Wake up the PHY.
 878                          * Vendor specific (0x1f) and reserved (0x0e) MII
 879                          * registers.
 880                          */
 881                         mdio_write(ioaddr, 0x1f, 0x0000);
 882                         mdio_write(ioaddr, 0x0e, 0x0000);
 883                 }
 884
 885                 mdio_write(ioaddr, MII_ADVERTISE, auto_nego);
 886                 mdio_write(ioaddr, MII_CTRL1000, giga_ctrl);
 887         } else {
 888                 giga_ctrl = 0;
 889
 890                 if (speed == SPEED_10)
 891                         bmcr = 0;
 892                 else if (speed == SPEED_100)
 893                         bmcr = BMCR_SPEED100;
 894                 else
 895                         return -EINVAL;
 896
 897                 if (duplex == DUPLEX_FULL)
 898                         bmcr |= BMCR_FULLDPLX;
 899
 900                 mdio_write(ioaddr, 0x1f, 0x0000);
 901         }
 902
 903         tp->phy_1000_ctrl_reg = giga_ctrl;
 904
 905         mdio_write(ioaddr, MII_BMCR, bmcr);
 906
 907         if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
 908             (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
 909                 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
 910                         mdio_write(ioaddr, 0x17, 0x2138);
 911                         mdio_write(ioaddr, 0x0e, 0x0260);
 912                 } else {
 913                         mdio_write(ioaddr, 0x17, 0x2108);
 914                         mdio_write(ioaddr, 0x0e, 0x0000);
 915                 }
 916         }
 917
 918         return 0;
 919 }
 920
 921 static int rtl8169_set_speed(struct net_device *dev,
 922                              u8 autoneg, u16 speed, u8 duplex)
 923 {
 924         struct rtl8169_private *tp = netdev_priv(dev);
 925         int ret;
 926
 927         ret = tp->set_speed(dev, autoneg, speed, duplex);
 928
 929         if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
 930                 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
 931
 932         return ret;
 933 }
 934
 935 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 936 {
 937         struct rtl8169_private *tp = netdev_priv(dev);
 938         unsigned long flags;
 939         int ret;
 940
 941         spin_lock_irqsave(&tp->lock, flags);
 942         ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
 943         spin_unlock_irqrestore(&tp->lock, flags);
 944
 945         return ret;
 946 }
 947
 948 static u32 rtl8169_get_rx_csum(struct net_device *dev)
 949 {
 950         struct rtl8169_private *tp = netdev_priv(dev);
 951
 952         return tp->cp_cmd & RxChkSum;
 953 }
 954
 955 static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
 956 {
 957         struct rtl8169_private *tp = netdev_priv(dev);
 958         void __iomem *ioaddr = tp->mmio_addr;
 959         unsigned long flags;
 960
 961         spin_lock_irqsave(&tp->lock, flags);
 962
 963         if (data)
 964                 tp->cp_cmd |= RxChkSum;
 965         else
 966                 tp->cp_cmd &= ~RxChkSum;
 967
 968         RTL_W16(CPlusCmd, tp->cp_cmd);
 969         RTL_R16(CPlusCmd);
 970
 971         spin_unlock_irqrestore(&tp->lock, flags);
 972
 973         return 0;
 974 }
 975
 976 #ifdef CONFIG_R8169_VLAN
 977
 978 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
 979                                       struct sk_buff *skb)
 980 {
 981         return (tp->vlgrp && vlan_tx_tag_present(skb)) ?
 982                 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
 983 }
 984
 985 static void rtl8169_vlan_rx_register(struct net_device *dev,
 986                                      struct vlan_group *grp)
 987 {
 988         struct rtl8169_private *tp = netdev_priv(dev);
 989         void __iomem *ioaddr = tp->mmio_addr;
 990         unsigned long flags;
 991
 992         spin_lock_irqsave(&tp->lock, flags);
 993         tp->vlgrp = grp;
 994         if (tp->vlgrp)
 995                 tp->cp_cmd |= RxVlan;
 996         else
 997                 tp->cp_cmd &= ~RxVlan;
 998         RTL_W16(CPlusCmd, tp->cp_cmd);
 999         RTL_R16(CPlusCmd);
1000         spin_unlock_irqrestore(&tp->lock, flags);
1001 }
1002
1003 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
1004                                struct sk_buff *skb)
1005 {
1006         u32 opts2 = le32_to_cpu(desc->opts2);
1007         struct vlan_group *vlgrp = tp->vlgrp;
1008         int ret;
1009
1010         if (vlgrp && (opts2 & RxVlanTag)) {
1011                 vlan_hwaccel_receive_skb(skb, vlgrp, swab16(opts2 & 0xffff));
1012                 ret = 0;
1013         } else
1014                 ret = -1;
1015         desc->opts2 = 0;
1016         return ret;
1017 }
1018
1019 #else /* !CONFIG_R8169_VLAN */
1020
1021 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1022                                       struct sk_buff *skb)
1023 {
1024         return 0;
1025 }
1026
1027 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
1028                                struct sk_buff *skb)
1029 {
1030         return -1;
1031 }
1032
1033 #endif
1034
1035 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1036 {
1037         struct rtl8169_private *tp = netdev_priv(dev);
1038         void __iomem *ioaddr = tp->mmio_addr;
1039         u32 status;
1040
1041         cmd->supported =
1042                 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1043         cmd->port = PORT_FIBRE;
1044         cmd->transceiver = XCVR_INTERNAL;
1045
1046         status = RTL_R32(TBICSR);
1047         cmd->advertising = (status & TBINwEnable) ?  ADVERTISED_Autoneg : 0;
1048         cmd->autoneg = !!(status & TBINwEnable);
1049
1050         cmd->speed = SPEED_1000;
1051         cmd->duplex = DUPLEX_FULL; /* Always set */
1052
1053         return 0;
1054 }
1055
1056 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1057 {
1058         struct rtl8169_private *tp = netdev_priv(dev);
1059
1060         return mii_ethtool_gset(&tp->mii, cmd);
1061 }
1062
1063 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1064 {
1065         struct rtl8169_private *tp = netdev_priv(dev);
1066         unsigned long flags;
1067         int rc;
1068
1069         spin_lock_irqsave(&tp->lock, flags);
1070
1071         rc = tp->get_settings(dev, cmd);
1072
1073         spin_unlock_irqrestore(&tp->lock, flags);
1074         return rc;
1075 }
1076
1077 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1078                              void *p)
1079 {
1080         struct rtl8169_private *tp = netdev_priv(dev);
1081         unsigned long flags;
1082
1083         if (regs->len > R8169_REGS_SIZE)
1084                 regs->len = R8169_REGS_SIZE;
1085
1086         spin_lock_irqsave(&tp->lock, flags);
1087         memcpy_fromio(p, tp->mmio_addr, regs->len);
1088         spin_unlock_irqrestore(&tp->lock, flags);
1089 }
1090
1091 static u32 rtl8169_get_msglevel(struct net_device *dev)
1092 {
1093         struct rtl8169_private *tp = netdev_priv(dev);
1094
1095         return tp->msg_enable;
1096 }
1097
1098 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1099 {
1100         struct rtl8169_private *tp = netdev_priv(dev);
1101
1102         tp->msg_enable = value;
1103 }
1104
1105 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1106         "tx_packets",
1107         "rx_packets",
1108         "tx_errors",
1109         "rx_errors",
1110         "rx_missed",
1111         "align_errors",
1112         "tx_single_collisions",
1113         "tx_multi_collisions",
1114         "unicast",
1115         "broadcast",
1116         "multicast",
1117         "tx_aborted",
1118         "tx_underrun",
1119 };
1120
1121 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1122 {
1123         switch (sset) {
1124         case ETH_SS_STATS:
1125                 return ARRAY_SIZE(rtl8169_gstrings);
1126         default:
1127                 return -EOPNOTSUPP;
1128         }
1129 }
1130
1131 static void rtl8169_update_counters(struct net_device *dev)
1132 {
1133         struct rtl8169_private *tp = netdev_priv(dev);
1134         void __iomem *ioaddr = tp->mmio_addr;
1135         struct rtl8169_counters *counters;
1136         dma_addr_t paddr;
1137         u32 cmd;
1138         int wait = 1000;
1139
1140         /*
1141          * Some chips are unable to dump tally counters when the receiver
1142          * is disabled.
1143          */
1144         if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1145                 return;
1146
1147         counters = pci_alloc_consistent(tp->pci_dev, sizeof(*counters), &paddr);
1148         if (!counters)
1149                 return;
1150
1151         RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1152         cmd = (u64)paddr & DMA_BIT_MASK(32);
1153         RTL_W32(CounterAddrLow, cmd);
1154         RTL_W32(CounterAddrLow, cmd | CounterDump);
1155
1156         while (wait--) {
1157                 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
1158                         /* copy updated counters */
1159                         memcpy(&tp->counters, counters, sizeof(*counters));
1160                         break;
1161                 }
1162                 udelay(10);
1163         }
1164
1165         RTL_W32(CounterAddrLow, 0);
1166         RTL_W32(CounterAddrHigh, 0);
1167
1168         pci_free_consistent(tp->pci_dev, sizeof(*counters), counters, paddr);
1169 }
1170
1171 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1172                                       struct ethtool_stats *stats, u64 *data)
1173 {
1174         struct rtl8169_private *tp = netdev_priv(dev);
1175
1176         ASSERT_RTNL();
1177
1178         rtl8169_update_counters(dev);
1179
1180         data[0] = le64_to_cpu(tp->counters.tx_packets);
1181         data[1] = le64_to_cpu(tp->counters.rx_packets);
1182         data[2] = le64_to_cpu(tp->counters.tx_errors);
1183         data[3] = le32_to_cpu(tp->counters.rx_errors);
1184         data[4] = le16_to_cpu(tp->counters.rx_missed);
1185         data[5] = le16_to_cpu(tp->counters.align_errors);
1186         data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1187         data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1188         data[8] = le64_to_cpu(tp->counters.rx_unicast);
1189         data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1190         data[10] = le32_to_cpu(tp->counters.rx_multicast);
1191         data[11] = le16_to_cpu(tp->counters.tx_aborted);
1192         data[12] = le16_to_cpu(tp->counters.tx_underun);
1193 }
1194
1195 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1196 {
1197         switch(stringset) {
1198         case ETH_SS_STATS:
1199                 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1200                 break;
1201         }
1202 }
1203
1204 static const struct ethtool_ops rtl8169_ethtool_ops = {
1205         .get_drvinfo            = rtl8169_get_drvinfo,
1206         .get_regs_len           = rtl8169_get_regs_len,
1207         .get_link               = ethtool_op_get_link,
1208         .get_settings           = rtl8169_get_settings,
1209         .set_settings           = rtl8169_set_settings,
1210         .get_msglevel           = rtl8169_get_msglevel,
1211         .set_msglevel           = rtl8169_set_msglevel,
1212         .get_rx_csum            = rtl8169_get_rx_csum,
1213         .set_rx_csum            = rtl8169_set_rx_csum,
1214         .set_tx_csum            = ethtool_op_set_tx_csum,
1215         .set_sg                 = ethtool_op_set_sg,
1216         .set_tso                = ethtool_op_set_tso,
1217         .get_regs               = rtl8169_get_regs,
1218         .get_wol                = rtl8169_get_wol,
1219         .set_wol                = rtl8169_set_wol,
1220         .get_strings            = rtl8169_get_strings,
1221         .get_sset_count         = rtl8169_get_sset_count,
1222         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
1223 };
1224
1225 static void rtl8169_write_gmii_reg_bit(void __iomem *ioaddr, int reg,
1226                                        int bitnum, int bitval)
1227 {
1228         int val;
1229
1230         val = mdio_read(ioaddr, reg);
1231         val = (bitval == 1) ?
1232                 val | (bitval << bitnum) :  val & ~(0x0001 << bitnum);
1233         mdio_write(ioaddr, reg, val & 0xffff);
1234 }
1235
1236 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1237                                     void __iomem *ioaddr)
1238 {
1239         /*
1240          * The driver currently handles the 8168Bf and the 8168Be identically
1241          * but they can be identified more specifically through the test below
1242          * if needed:
1243          *
1244          * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1245          *
1246          * Same thing for the 8101Eb and the 8101Ec:
1247          *
1248          * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1249          */
1250         const struct {
1251                 u32 mask;
1252                 u32 val;
1253                 int mac_version;
1254         } mac_info[] = {
1255                 /* 8168D family. */
1256                 { 0x7c800000, 0x28000000,       RTL_GIGA_MAC_VER_25 },
1257
1258                 /* 8168C family. */
1259                 { 0x7cf00000, 0x3ca00000,       RTL_GIGA_MAC_VER_24 },
1260                 { 0x7cf00000, 0x3c900000,       RTL_GIGA_MAC_VER_23 },
1261                 { 0x7cf00000, 0x3c800000,       RTL_GIGA_MAC_VER_18 },
1262                 { 0x7c800000, 0x3c800000,       RTL_GIGA_MAC_VER_24 },
1263                 { 0x7cf00000, 0x3c000000,       RTL_GIGA_MAC_VER_19 },
1264                 { 0x7cf00000, 0x3c200000,       RTL_GIGA_MAC_VER_20 },
1265                 { 0x7cf00000, 0x3c300000,       RTL_GIGA_MAC_VER_21 },
1266                 { 0x7cf00000, 0x3c400000,       RTL_GIGA_MAC_VER_22 },
1267                 { 0x7c800000, 0x3c000000,       RTL_GIGA_MAC_VER_22 },
1268
1269                 /* 8168B family. */
1270                 { 0x7cf00000, 0x38000000,       RTL_GIGA_MAC_VER_12 },
1271                 { 0x7cf00000, 0x38500000,       RTL_GIGA_MAC_VER_17 },
1272                 { 0x7c800000, 0x38000000,       RTL_GIGA_MAC_VER_17 },
1273                 { 0x7c800000, 0x30000000,       RTL_GIGA_MAC_VER_11 },
1274
1275                 /* 8101 family. */
1276                 { 0x7cf00000, 0x34a00000,       RTL_GIGA_MAC_VER_09 },
1277                 { 0x7cf00000, 0x24a00000,       RTL_GIGA_MAC_VER_09 },
1278                 { 0x7cf00000, 0x34900000,       RTL_GIGA_MAC_VER_08 },
1279                 { 0x7cf00000, 0x24900000,       RTL_GIGA_MAC_VER_08 },
1280                 { 0x7cf00000, 0x34800000,       RTL_GIGA_MAC_VER_07 },
1281                 { 0x7cf00000, 0x24800000,       RTL_GIGA_MAC_VER_07 },
1282                 { 0x7cf00000, 0x34000000,       RTL_GIGA_MAC_VER_13 },
1283                 { 0x7cf00000, 0x34300000,       RTL_GIGA_MAC_VER_10 },
1284                 { 0x7cf00000, 0x34200000,       RTL_GIGA_MAC_VER_16 },
1285                 { 0x7c800000, 0x34800000,       RTL_GIGA_MAC_VER_09 },
1286                 { 0x7c800000, 0x24800000,       RTL_GIGA_MAC_VER_09 },
1287                 { 0x7c800000, 0x34000000,       RTL_GIGA_MAC_VER_16 },
1288                 /* FIXME: where did these entries come from ? -- FR */
1289                 { 0xfc800000, 0x38800000,       RTL_GIGA_MAC_VER_15 },
1290                 { 0xfc800000, 0x30800000,       RTL_GIGA_MAC_VER_14 },
1291
1292                 /* 8110 family. */
1293                 { 0xfc800000, 0x98000000,       RTL_GIGA_MAC_VER_06 },
1294                 { 0xfc800000, 0x18000000,       RTL_GIGA_MAC_VER_05 },
1295                 { 0xfc800000, 0x10000000,       RTL_GIGA_MAC_VER_04 },
1296                 { 0xfc800000, 0x04000000,       RTL_GIGA_MAC_VER_03 },
1297                 { 0xfc800000, 0x00800000,       RTL_GIGA_MAC_VER_02 },
1298                 { 0xfc800000, 0x00000000,       RTL_GIGA_MAC_VER_01 },
1299
1300                 /* Catch-all */
1301                 { 0x00000000, 0x00000000,       RTL_GIGA_MAC_NONE   }
1302         }, *p = mac_info;
1303         u32 reg;
1304
1305         reg = RTL_R32(TxConfig);
1306         while ((reg & p->mask) != p->val)
1307                 p++;
1308         tp->mac_version = p->mac_version;
1309 }
1310
1311 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1312 {
1313         dprintk("mac_version = 0x%02x\n", tp->mac_version);
1314 }
1315
1316 struct phy_reg {
1317         u16 reg;
1318         u16 val;
1319 };
1320
1321 static void rtl_phy_write(void __iomem *ioaddr, struct phy_reg *regs, int len)
1322 {
1323         while (len-- > 0) {
1324                 mdio_write(ioaddr, regs->reg, regs->val);
1325                 regs++;
1326         }
1327 }
1328
1329 static void rtl8169s_hw_phy_config(void __iomem *ioaddr)
1330 {
1331         struct {
1332                 u16 regs[5]; /* Beware of bit-sign propagation */
1333         } phy_magic[5] = { {
1334                 { 0x0000,       //w 4 15 12 0
1335                   0x00a1,       //w 3 15 0 00a1
1336                   0x0008,       //w 2 15 0 0008
1337                   0x1020,       //w 1 15 0 1020
1338                   0x1000 } },{  //w 0 15 0 1000
1339                 { 0x7000,       //w 4 15 12 7
1340                   0xff41,       //w 3 15 0 ff41
1341                   0xde60,       //w 2 15 0 de60
1342                   0x0140,       //w 1 15 0 0140
1343                   0x0077 } },{  //w 0 15 0 0077
1344                 { 0xa000,       //w 4 15 12 a
1345                   0xdf01,       //w 3 15 0 df01
1346                   0xdf20,       //w 2 15 0 df20
1347                   0xff95,       //w 1 15 0 ff95
1348                   0xfa00 } },{  //w 0 15 0 fa00
1349                 { 0xb000,       //w 4 15 12 b
1350                   0xff41,       //w 3 15 0 ff41
1351                   0xde20,       //w 2 15 0 de20
1352                   0x0140,       //w 1 15 0 0140
1353                   0x00bb } },{  //w 0 15 0 00bb
1354                 { 0xf000,       //w 4 15 12 f
1355                   0xdf01,       //w 3 15 0 df01
1356                   0xdf20,       //w 2 15 0 df20
1357                   0xff95,       //w 1 15 0 ff95
1358                   0xbf00 }      //w 0 15 0 bf00
1359                 }
1360         }, *p = phy_magic;
1361         unsigned int i;
1362
1363         mdio_write(ioaddr, 0x1f, 0x0001);               //w 31 2 0 1
1364         mdio_write(ioaddr, 0x15, 0x1000);               //w 21 15 0 1000
1365         mdio_write(ioaddr, 0x18, 0x65c7);               //w 24 15 0 65c7
1366         rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0);   //w 4 11 11 0
1367
1368         for (i = 0; i < ARRAY_SIZE(phy_magic); i++, p++) {
1369                 int val, pos = 4;
1370
1371                 val = (mdio_read(ioaddr, pos) & 0x0fff) | (p->regs[0] & 0xffff);
1372                 mdio_write(ioaddr, pos, val);
1373                 while (--pos >= 0)
1374                         mdio_write(ioaddr, pos, p->regs[4 - pos] & 0xffff);
1375                 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 1); //w 4 11 11 1
1376                 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1377         }
1378         mdio_write(ioaddr, 0x1f, 0x0000); //w 31 2 0 0
1379 }
1380
1381 static void rtl8169sb_hw_phy_config(void __iomem *ioaddr)
1382 {
1383         struct phy_reg phy_reg_init[] = {
1384                 { 0x1f, 0x0002 },
1385                 { 0x01, 0x90d0 },
1386                 { 0x1f, 0x0000 }
1387         };
1388
1389         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1390 }
1391
1392 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp,
1393                                            void __iomem *ioaddr)
1394 {
1395         struct pci_dev *pdev = tp->pci_dev;
1396         u16 vendor_id, device_id;
1397
1398         pci_read_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID, &vendor_id);
1399         pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &device_id);
1400
1401         if ((vendor_id != PCI_VENDOR_ID_GIGABYTE) || (device_id != 0xe000))
1402                 return;
1403
1404         mdio_write(ioaddr, 0x1f, 0x0001);
1405         mdio_write(ioaddr, 0x10, 0xf01b);
1406         mdio_write(ioaddr, 0x1f, 0x0000);
1407 }
1408
1409 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp,
1410                                      void __iomem *ioaddr)
1411 {
1412         struct phy_reg phy_reg_init[] = {
1413                 { 0x1f, 0x0001 },
1414                 { 0x04, 0x0000 },
1415                 { 0x03, 0x00a1 },
1416                 { 0x02, 0x0008 },
1417                 { 0x01, 0x0120 },
1418                 { 0x00, 0x1000 },
1419                 { 0x04, 0x0800 },
1420                 { 0x04, 0x9000 },
1421                 { 0x03, 0x802f },
1422                 { 0x02, 0x4f02 },
1423                 { 0x01, 0x0409 },
1424                 { 0x00, 0xf099 },
1425                 { 0x04, 0x9800 },
1426                 { 0x04, 0xa000 },
1427                 { 0x03, 0xdf01 },
1428                 { 0x02, 0xdf20 },
1429                 { 0x01, 0xff95 },
1430                 { 0x00, 0xba00 },
1431                 { 0x04, 0xa800 },
1432                 { 0x04, 0xf000 },
1433                 { 0x03, 0xdf01 },
1434                 { 0x02, 0xdf20 },
1435                 { 0x01, 0x101a },
1436                 { 0x00, 0xa0ff },
1437                 { 0x04, 0xf800 },
1438                 { 0x04, 0x0000 },
1439                 { 0x1f, 0x0000 },
1440
1441                 { 0x1f, 0x0001 },
1442                 { 0x10, 0xf41b },
1443                 { 0x14, 0xfb54 },
1444                 { 0x18, 0xf5c7 },
1445                 { 0x1f, 0x0000 },
1446
1447                 { 0x1f, 0x0001 },
1448                 { 0x17, 0x0cc0 },
1449                 { 0x1f, 0x0000 }
1450         };
1451
1452         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1453
1454         rtl8169scd_hw_phy_config_quirk(tp, ioaddr);
1455 }
1456
1457 static void rtl8169sce_hw_phy_config(void __iomem *ioaddr)
1458 {
1459         struct phy_reg phy_reg_init[] = {
1460                 { 0x1f, 0x0001 },
1461                 { 0x04, 0x0000 },
1462                 { 0x03, 0x00a1 },
1463                 { 0x02, 0x0008 },
1464                 { 0x01, 0x0120 },
1465                 { 0x00, 0x1000 },
1466                 { 0x04, 0x0800 },
1467                 { 0x04, 0x9000 },
1468                 { 0x03, 0x802f },
1469                 { 0x02, 0x4f02 },
1470                 { 0x01, 0x0409 },
1471                 { 0x00, 0xf099 },
1472                 { 0x04, 0x9800 },
1473                 { 0x04, 0xa000 },
1474                 { 0x03, 0xdf01 },
1475                 { 0x02, 0xdf20 },
1476                 { 0x01, 0xff95 },
1477                 { 0x00, 0xba00 },
1478                 { 0x04, 0xa800 },
1479                 { 0x04, 0xf000 },
1480                 { 0x03, 0xdf01 },
1481                 { 0x02, 0xdf20 },
1482                 { 0x01, 0x101a },
1483                 { 0x00, 0xa0ff },
1484                 { 0x04, 0xf800 },
1485                 { 0x04, 0x0000 },
1486                 { 0x1f, 0x0000 },
1487
1488                 { 0x1f, 0x0001 },
1489                 { 0x0b, 0x8480 },
1490                 { 0x1f, 0x0000 },
1491
1492                 { 0x1f, 0x0001 },
1493                 { 0x18, 0x67c7 },
1494                 { 0x04, 0x2000 },
1495                 { 0x03, 0x002f },
1496                 { 0x02, 0x4360 },
1497                 { 0x01, 0x0109 },
1498                 { 0x00, 0x3022 },
1499                 { 0x04, 0x2800 },
1500                 { 0x1f, 0x0000 },
1501
1502                 { 0x1f, 0x0001 },
1503                 { 0x17, 0x0cc0 },
1504                 { 0x1f, 0x0000 }
1505         };
1506
1507         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1508 }
1509
1510 static void rtl8168bb_hw_phy_config(void __iomem *ioaddr)
1511 {
1512         struct phy_reg phy_reg_init[] = {
1513                 { 0x10, 0xf41b },
1514                 { 0x1f, 0x0000 }
1515         };
1516
1517         mdio_write(ioaddr, 0x1f, 0x0001);
1518         mdio_patch(ioaddr, 0x16, 1 << 0);
1519
1520         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1521 }
1522
1523 static void rtl8168bef_hw_phy_config(void __iomem *ioaddr)
1524 {
1525         struct phy_reg phy_reg_init[] = {
1526                 { 0x1f, 0x0001 },
1527                 { 0x10, 0xf41b },
1528                 { 0x1f, 0x0000 }
1529         };
1530
1531         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1532 }
1533
1534 static void rtl8168cp_1_hw_phy_config(void __iomem *ioaddr)
1535 {
1536         struct phy_reg phy_reg_init[] = {
1537                 { 0x1f, 0x0000 },
1538                 { 0x1d, 0x0f00 },
1539                 { 0x1f, 0x0002 },
1540                 { 0x0c, 0x1ec8 },
1541                 { 0x1f, 0x0000 }
1542         };
1543
1544         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1545 }
1546
1547 static void rtl8168cp_2_hw_phy_config(void __iomem *ioaddr)
1548 {
1549         struct phy_reg phy_reg_init[] = {
1550                 { 0x1f, 0x0001 },
1551                 { 0x1d, 0x3d98 },
1552                 { 0x1f, 0x0000 }
1553         };
1554
1555         mdio_write(ioaddr, 0x1f, 0x0000);
1556         mdio_patch(ioaddr, 0x14, 1 << 5);
1557         mdio_patch(ioaddr, 0x0d, 1 << 5);
1558
1559         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1560 }
1561
1562 static void rtl8168c_1_hw_phy_config(void __iomem *ioaddr)
1563 {
1564         struct phy_reg phy_reg_init[] = {
1565                 { 0x1f, 0x0001 },
1566                 { 0x12, 0x2300 },
1567                 { 0x1f, 0x0002 },
1568                 { 0x00, 0x88d4 },
1569                 { 0x01, 0x82b1 },
1570                 { 0x03, 0x7002 },
1571                 { 0x08, 0x9e30 },
1572                 { 0x09, 0x01f0 },
1573                 { 0x0a, 0x5500 },
1574                 { 0x0c, 0x00c8 },
1575                 { 0x1f, 0x0003 },
1576                 { 0x12, 0xc096 },
1577                 { 0x16, 0x000a },
1578                 { 0x1f, 0x0000 },
1579                 { 0x1f, 0x0000 },
1580                 { 0x09, 0x2000 },
1581                 { 0x09, 0x0000 }
1582         };
1583
1584         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1585
1586         mdio_patch(ioaddr, 0x14, 1 << 5);
1587         mdio_patch(ioaddr, 0x0d, 1 << 5);
1588         mdio_write(ioaddr, 0x1f, 0x0000);
1589 }
1590
1591 static void rtl8168c_2_hw_phy_config(void __iomem *ioaddr)
1592 {
1593         struct phy_reg phy_reg_init[] = {
1594                 { 0x1f, 0x0001 },
1595                 { 0x12, 0x2300 },
1596                 { 0x03, 0x802f },
1597                 { 0x02, 0x4f02 },
1598                 { 0x01, 0x0409 },
1599                 { 0x00, 0xf099 },
1600                 { 0x04, 0x9800 },
1601                 { 0x04, 0x9000 },
1602                 { 0x1d, 0x3d98 },
1603                 { 0x1f, 0x0002 },
1604                 { 0x0c, 0x7eb8 },
1605                 { 0x06, 0x0761 },
1606                 { 0x1f, 0x0003 },
1607                 { 0x16, 0x0f0a },
1608                 { 0x1f, 0x0000 }
1609         };
1610
1611         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1612
1613         mdio_patch(ioaddr, 0x16, 1 << 0);
1614         mdio_patch(ioaddr, 0x14, 1 << 5);
1615         mdio_patch(ioaddr, 0x0d, 1 << 5);
1616         mdio_write(ioaddr, 0x1f, 0x0000);
1617 }
1618
1619 static void rtl8168c_3_hw_phy_config(void __iomem *ioaddr)
1620 {
1621         struct phy_reg phy_reg_init[] = {
1622                 { 0x1f, 0x0001 },
1623                 { 0x12, 0x2300 },
1624                 { 0x1d, 0x3d98 },
1625                 { 0x1f, 0x0002 },
1626                 { 0x0c, 0x7eb8 },
1627                 { 0x06, 0x5461 },
1628                 { 0x1f, 0x0003 },
1629                 { 0x16, 0x0f0a },
1630                 { 0x1f, 0x0000 }
1631         };
1632
1633         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1634
1635         mdio_patch(ioaddr, 0x16, 1 << 0);
1636         mdio_patch(ioaddr, 0x14, 1 << 5);
1637         mdio_patch(ioaddr, 0x0d, 1 << 5);
1638         mdio_write(ioaddr, 0x1f, 0x0000);
1639 }
1640
1641 static void rtl8168c_4_hw_phy_config(void __iomem *ioaddr)
1642 {
1643         rtl8168c_3_hw_phy_config(ioaddr);
1644 }
1645
1646 static void rtl8168d_hw_phy_config(void __iomem *ioaddr)
1647 {
1648         struct phy_reg phy_reg_init_0[] = {
1649                 { 0x1f, 0x0001 },
1650                 { 0x09, 0x2770 },
1651                 { 0x08, 0x04d0 },
1652                 { 0x0b, 0xad15 },
1653                 { 0x0c, 0x5bf0 },
1654                 { 0x1c, 0xf101 },
1655                 { 0x1f, 0x0003 },
1656                 { 0x14, 0x94d7 },
1657                 { 0x12, 0xf4d6 },
1658                 { 0x09, 0xca0f },
1659                 { 0x1f, 0x0002 },
1660                 { 0x0b, 0x0b10 },
1661                 { 0x0c, 0xd1f7 },
1662                 { 0x1f, 0x0002 },
1663                 { 0x06, 0x5461 },
1664                 { 0x1f, 0x0002 },
1665                 { 0x05, 0x6662 },
1666                 { 0x1f, 0x0000 },
1667                 { 0x14, 0x0060 },
1668                 { 0x1f, 0x0000 },
1669                 { 0x0d, 0xf8a0 },
1670                 { 0x1f, 0x0005 },
1671                 { 0x05, 0xffc2 }
1672         };
1673
1674         rtl_phy_write(ioaddr, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
1675
1676         if (mdio_read(ioaddr, 0x06) == 0xc400) {
1677                 struct phy_reg phy_reg_init_1[] = {
1678                         { 0x1f, 0x0005 },
1679                         { 0x01, 0x0300 },
1680                         { 0x1f, 0x0000 },
1681                         { 0x11, 0x401c },
1682                         { 0x16, 0x4100 },
1683                         { 0x1f, 0x0005 },
1684                         { 0x07, 0x0010 },
1685                         { 0x05, 0x83dc },
1686                         { 0x06, 0x087d },
1687                         { 0x05, 0x8300 },
1688                         { 0x06, 0x0101 },
1689                         { 0x06, 0x05f8 },
1690                         { 0x06, 0xf9fa },
1691                         { 0x06, 0xfbef },
1692                         { 0x06, 0x79e2 },
1693                         { 0x06, 0x835f },
1694                         { 0x06, 0xe0f8 },
1695                         { 0x06, 0x9ae1 },
1696                         { 0x06, 0xf89b },
1697                         { 0x06, 0xef31 },
1698                         { 0x06, 0x3b65 },
1699                         { 0x06, 0xaa07 },
1700                         { 0x06, 0x81e4 },
1701                         { 0x06, 0xf89a },
1702                         { 0x06, 0xe5f8 },
1703                         { 0x06, 0x9baf },
1704                         { 0x06, 0x06ae },
1705                         { 0x05, 0x83dc },
1706                         { 0x06, 0x8300 },
1707                 };
1708
1709                 rtl_phy_write(ioaddr, phy_reg_init_1,
1710                               ARRAY_SIZE(phy_reg_init_1));
1711         }
1712
1713         mdio_write(ioaddr, 0x1f, 0x0000);
1714 }
1715
1716 static void rtl8102e_hw_phy_config(void __iomem *ioaddr)
1717 {
1718         struct phy_reg phy_reg_init[] = {
1719                 { 0x1f, 0x0003 },
1720                 { 0x08, 0x441d },
1721                 { 0x01, 0x9100 },
1722                 { 0x1f, 0x0000 }
1723         };
1724
1725         mdio_write(ioaddr, 0x1f, 0x0000);
1726         mdio_patch(ioaddr, 0x11, 1 << 12);
1727         mdio_patch(ioaddr, 0x19, 1 << 13);
1728
1729         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1730 }
1731
1732 static void rtl_hw_phy_config(struct net_device *dev)
1733 {
1734         struct rtl8169_private *tp = netdev_priv(dev);
1735         void __iomem *ioaddr = tp->mmio_addr;
1736
1737         rtl8169_print_mac_version(tp);
1738
1739         switch (tp->mac_version) {
1740         case RTL_GIGA_MAC_VER_01:
1741                 break;
1742         case RTL_GIGA_MAC_VER_02:
1743         case RTL_GIGA_MAC_VER_03:
1744                 rtl8169s_hw_phy_config(ioaddr);
1745                 break;
1746         case RTL_GIGA_MAC_VER_04:
1747                 rtl8169sb_hw_phy_config(ioaddr);
1748                 break;
1749         case RTL_GIGA_MAC_VER_05:
1750                 rtl8169scd_hw_phy_config(tp, ioaddr);
1751                 break;
1752         case RTL_GIGA_MAC_VER_06:
1753                 rtl8169sce_hw_phy_config(ioaddr);
1754                 break;
1755         case RTL_GIGA_MAC_VER_07:
1756         case RTL_GIGA_MAC_VER_08:
1757         case RTL_GIGA_MAC_VER_09:
1758                 rtl8102e_hw_phy_config(ioaddr);
1759                 break;
1760         case RTL_GIGA_MAC_VER_11:
1761                 rtl8168bb_hw_phy_config(ioaddr);
1762                 break;
1763         case RTL_GIGA_MAC_VER_12:
1764                 rtl8168bef_hw_phy_config(ioaddr);
1765                 break;
1766         case RTL_GIGA_MAC_VER_17:
1767                 rtl8168bef_hw_phy_config(ioaddr);
1768                 break;
1769         case RTL_GIGA_MAC_VER_18:
1770                 rtl8168cp_1_hw_phy_config(ioaddr);
1771                 break;
1772         case RTL_GIGA_MAC_VER_19:
1773                 rtl8168c_1_hw_phy_config(ioaddr);
1774                 break;
1775         case RTL_GIGA_MAC_VER_20:
1776                 rtl8168c_2_hw_phy_config(ioaddr);
1777                 break;
1778         case RTL_GIGA_MAC_VER_21:
1779                 rtl8168c_3_hw_phy_config(ioaddr);
1780                 break;
1781         case RTL_GIGA_MAC_VER_22:
1782                 rtl8168c_4_hw_phy_config(ioaddr);
1783                 break;
1784         case RTL_GIGA_MAC_VER_23:
1785         case RTL_GIGA_MAC_VER_24:
1786                 rtl8168cp_2_hw_phy_config(ioaddr);
1787                 break;
1788         case RTL_GIGA_MAC_VER_25:
1789                 rtl8168d_hw_phy_config(ioaddr);
1790                 break;
1791
1792         default:
1793                 break;
1794         }
1795 }
1796
1797 static void rtl8169_phy_timer(unsigned long __opaque)
1798 {
1799         struct net_device *dev = (struct net_device *)__opaque;
1800         struct rtl8169_private *tp = netdev_priv(dev);
1801         struct timer_list *timer = &tp->timer;
1802         void __iomem *ioaddr = tp->mmio_addr;
1803         unsigned long timeout = RTL8169_PHY_TIMEOUT;
1804
1805         assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1806
1807         if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1808                 return;
1809
1810         spin_lock_irq(&tp->lock);
1811
1812         if (tp->phy_reset_pending(ioaddr)) {
1813                 /*
1814                  * A busy loop could burn quite a few cycles on nowadays CPU.
1815                  * Let's delay the execution of the timer for a few ticks.
1816                  */
1817                 timeout = HZ/10;
1818                 goto out_mod_timer;
1819         }
1820
1821         if (tp->link_ok(ioaddr))
1822                 goto out_unlock;
1823
1824         if (netif_msg_link(tp))
1825                 printk(KERN_WARNING "%s: PHY reset until link up\n", dev->name);
1826
1827         tp->phy_reset_enable(ioaddr);
1828
1829 out_mod_timer:
1830         mod_timer(timer, jiffies + timeout);
1831 out_unlock:
1832         spin_unlock_irq(&tp->lock);
1833 }
1834
1835 static inline void rtl8169_delete_timer(struct net_device *dev)
1836 {
1837         struct rtl8169_private *tp = netdev_priv(dev);
1838         struct timer_list *timer = &tp->timer;
1839
1840         if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1841                 return;
1842
1843         del_timer_sync(timer);
1844 }
1845
1846 static inline void rtl8169_request_timer(struct net_device *dev)
1847 {
1848         struct rtl8169_private *tp = netdev_priv(dev);
1849         struct timer_list *timer = &tp->timer;
1850
1851         if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1852                 return;
1853
1854         mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
1855 }
1856
1857 #ifdef CONFIG_NET_POLL_CONTROLLER
1858 /*
1859  * Polling 'interrupt' - used by things like netconsole to send skbs
1860  * without having to re-enable interrupts. It's not called while
1861  * the interrupt routine is executing.
1862  */
1863 static void rtl8169_netpoll(struct net_device *dev)
1864 {
1865         struct rtl8169_private *tp = netdev_priv(dev);
1866         struct pci_dev *pdev = tp->pci_dev;
1867
1868         disable_irq(pdev->irq);
1869         rtl8169_interrupt(pdev->irq, dev);
1870         enable_irq(pdev->irq);
1871 }
1872 #endif
1873
1874 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
1875                                   void __iomem *ioaddr)
1876 {
1877         iounmap(ioaddr);
1878         pci_release_regions(pdev);
1879         pci_disable_device(pdev);
1880         free_netdev(dev);
1881 }
1882
1883 static void rtl8169_phy_reset(struct net_device *dev,
1884                               struct rtl8169_private *tp)
1885 {
1886         void __iomem *ioaddr = tp->mmio_addr;
1887         unsigned int i;
1888
1889         tp->phy_reset_enable(ioaddr);
1890         for (i = 0; i < 100; i++) {
1891                 if (!tp->phy_reset_pending(ioaddr))
1892                         return;
1893                 msleep(1);
1894         }
1895         if (netif_msg_link(tp))
1896                 printk(KERN_ERR "%s: PHY reset failed.\n", dev->name);
1897 }
1898
1899 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
1900 {
1901         void __iomem *ioaddr = tp->mmio_addr;
1902
1903         rtl_hw_phy_config(dev);
1904
1905         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
1906                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1907                 RTL_W8(0x82, 0x01);
1908         }
1909
1910         pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
1911
1912         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
1913                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
1914
1915         if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
1916                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1917                 RTL_W8(0x82, 0x01);
1918                 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
1919                 mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0
1920         }
1921
1922         rtl8169_phy_reset(dev, tp);
1923
1924         /*
1925          * rtl8169_set_speed_xmii takes good care of the Fast Ethernet
1926          * only 8101. Don't panic.
1927          */
1928         rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL);
1929
1930         if ((RTL_R8(PHYstatus) & TBI_Enable) && netif_msg_link(tp))
1931                 printk(KERN_INFO PFX "%s: TBI auto-negotiating\n", dev->name);
1932 }
1933
1934 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
1935 {
1936         void __iomem *ioaddr = tp->mmio_addr;
1937         u32 high;
1938         u32 low;
1939
1940         low  = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
1941         high = addr[4] | (addr[5] << 8);
1942
1943         spin_lock_irq(&tp->lock);
1944
1945         RTL_W8(Cfg9346, Cfg9346_Unlock);
1946         RTL_W32(MAC0, low);
1947         RTL_W32(MAC4, high);
1948         RTL_W8(Cfg9346, Cfg9346_Lock);
1949
1950         spin_unlock_irq(&tp->lock);
1951 }
1952
1953 static int rtl_set_mac_address(struct net_device *dev, void *p)
1954 {
1955         struct rtl8169_private *tp = netdev_priv(dev);
1956         struct sockaddr *addr = p;
1957
1958         if (!is_valid_ether_addr(addr->sa_data))
1959                 return -EADDRNOTAVAIL;
1960
1961         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1962
1963         rtl_rar_set(tp, dev->dev_addr);
1964
1965         return 0;
1966 }
1967
1968 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1969 {
1970         struct rtl8169_private *tp = netdev_priv(dev);
1971         struct mii_ioctl_data *data = if_mii(ifr);
1972
1973         return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
1974 }
1975
1976 static int rtl_xmii_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
1977 {
1978         switch (cmd) {
1979         case SIOCGMIIPHY:
1980                 data->phy_id = 32; /* Internal PHY */
1981                 return 0;
1982
1983         case SIOCGMIIREG:
1984                 data->val_out = mdio_read(tp->mmio_addr, data->reg_num & 0x1f);
1985                 return 0;
1986
1987         case SIOCSMIIREG:
1988                 if (!capable(CAP_NET_ADMIN))
1989                         return -EPERM;
1990                 mdio_write(tp->mmio_addr, data->reg_num & 0x1f, data->val_in);
1991                 return 0;
1992         }
1993         return -EOPNOTSUPP;
1994 }
1995
1996 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
1997 {
1998         return -EOPNOTSUPP;
1999 }
2000
2001 static const struct rtl_cfg_info {
2002         void (*hw_start)(struct net_device *);
2003         unsigned int region;
2004         unsigned int align;
2005         u16 intr_event;
2006         u16 napi_event;
2007         unsigned features;
2008         u8 default_ver;
2009 } rtl_cfg_infos [] = {
2010         [RTL_CFG_0] = {
2011                 .hw_start       = rtl_hw_start_8169,
2012                 .region         = 1,
2013                 .align          = 0,
2014                 .intr_event     = SYSErr | LinkChg | RxOverflow |
2015                                   RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
2016                 .napi_event     = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
2017                 .features       = RTL_FEATURE_GMII,
2018                 .default_ver    = RTL_GIGA_MAC_VER_01,
2019         },
2020         [RTL_CFG_1] = {
2021                 .hw_start       = rtl_hw_start_8168,
2022                 .region         = 2,
2023                 .align          = 8,
2024                 .intr_event     = SYSErr | LinkChg | RxOverflow |
2025                                   TxErr | TxOK | RxOK | RxErr,
2026                 .napi_event     = TxErr | TxOK | RxOK | RxOverflow,
2027                 .features       = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
2028                 .default_ver    = RTL_GIGA_MAC_VER_11,
2029         },
2030         [RTL_CFG_2] = {
2031                 .hw_start       = rtl_hw_start_8101,
2032                 .region         = 2,
2033                 .align          = 8,
2034                 .intr_event     = SYSErr | LinkChg | RxOverflow | PCSTimeout |
2035                                   RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
2036                 .napi_event     = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
2037                 .features       = RTL_FEATURE_MSI,
2038                 .default_ver    = RTL_GIGA_MAC_VER_13,
2039         }
2040 };
2041
2042 /* Cfg9346_Unlock assumed. */
2043 static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
2044                             const struct rtl_cfg_info *cfg)
2045 {
2046         unsigned msi = 0;
2047         u8 cfg2;
2048
2049         cfg2 = RTL_R8(Config2) & ~MSIEnable;
2050         if (cfg->features & RTL_FEATURE_MSI) {
2051                 if (pci_enable_msi(pdev)) {
2052                         dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
2053                 } else {
2054                         cfg2 |= MSIEnable;
2055                         msi = RTL_FEATURE_MSI;
2056                 }
2057         }
2058         RTL_W8(Config2, cfg2);
2059         return msi;
2060 }
2061
2062 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
2063 {
2064         if (tp->features & RTL_FEATURE_MSI) {
2065                 pci_disable_msi(pdev);
2066                 tp->features &= ~RTL_FEATURE_MSI;
2067         }
2068 }
2069
2070 static const struct net_device_ops rtl8169_netdev_ops = {
2071         .ndo_open               = rtl8169_open,
2072         .ndo_stop               = rtl8169_close,
2073         .ndo_get_stats          = rtl8169_get_stats,
2074         .ndo_start_xmit         = rtl8169_start_xmit,
2075         .ndo_tx_timeout         = rtl8169_tx_timeout,
2076         .ndo_validate_addr      = eth_validate_addr,
2077         .ndo_change_mtu         = rtl8169_change_mtu,
2078         .ndo_set_mac_address    = rtl_set_mac_address,
2079         .ndo_do_ioctl           = rtl8169_ioctl,
2080         .ndo_set_multicast_list = rtl_set_rx_mode,
2081 #ifdef CONFIG_R8169_VLAN
2082         .ndo_vlan_rx_register   = rtl8169_vlan_rx_register,
2083 #endif
2084 #ifdef CONFIG_NET_POLL_CONTROLLER
2085         .ndo_poll_controller    = rtl8169_netpoll,
2086 #endif
2087
2088 };
2089
2090 static int __devinit
2091 rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
2092 {
2093         const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
2094         const unsigned int region = cfg->region;
2095         struct rtl8169_private *tp;
2096         struct mii_if_info *mii;
2097         struct net_device *dev;
2098         void __iomem *ioaddr;
2099         unsigned int i;
2100         int rc;
2101
2102         if (netif_msg_drv(&debug)) {
2103                 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
2104                        MODULENAME, RTL8169_VERSION);
2105         }
2106
2107         dev = alloc_etherdev(sizeof (*tp));
2108         if (!dev) {
2109                 if (netif_msg_drv(&debug))
2110                         dev_err(&pdev->dev, "unable to alloc new ethernet\n");
2111                 rc = -ENOMEM;
2112                 goto out;
2113         }
2114
2115         SET_NETDEV_DEV(dev, &pdev->dev);
2116         dev->netdev_ops = &rtl8169_netdev_ops;
2117         tp = netdev_priv(dev);
2118         tp->dev = dev;
2119         tp->pci_dev = pdev;
2120         tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
2121
2122         mii = &tp->mii;
2123         mii->dev = dev;
2124         mii->mdio_read = rtl_mdio_read;
2125         mii->mdio_write = rtl_mdio_write;
2126         mii->phy_id_mask = 0x1f;
2127         mii->reg_num_mask = 0x1f;
2128         mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
2129
2130         /* enable device (incl. PCI PM wakeup and hotplug setup) */
2131         rc = pci_enable_device(pdev);
2132         if (rc < 0) {
2133                 if (netif_msg_probe(tp))
2134                         dev_err(&pdev->dev, "enable failure\n");
2135                 goto err_out_free_dev_1;
2136         }
2137
2138         rc = pci_set_mwi(pdev);
2139         if (rc < 0)
2140                 goto err_out_disable_2;
2141
2142         /* make sure PCI base addr 1 is MMIO */
2143         if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
2144                 if (netif_msg_probe(tp)) {
2145                         dev_err(&pdev->dev,
2146                                 "region #%d not an MMIO resource, aborting\n",
2147                                 region);
2148                 }
2149                 rc = -ENODEV;
2150                 goto err_out_mwi_3;
2151         }
2152
2153         /* check for weird/broken PCI region reporting */
2154         if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
2155                 if (netif_msg_probe(tp)) {
2156                         dev_err(&pdev->dev,
2157                                 "Invalid PCI region size(s), aborting\n");
2158                 }
2159                 rc = -ENODEV;
2160                 goto err_out_mwi_3;
2161         }
2162
2163         rc = pci_request_regions(pdev, MODULENAME);
2164         if (rc < 0) {
2165                 if (netif_msg_probe(tp))
2166                         dev_err(&pdev->dev, "could not request regions.\n");
2167                 goto err_out_mwi_3;
2168         }
2169
2170         tp->cp_cmd = PCIMulRW | RxChkSum;
2171
2172         if ((sizeof(dma_addr_t) > 4) &&
2173             !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
2174                 tp->cp_cmd |= PCIDAC;
2175                 dev->features |= NETIF_F_HIGHDMA;
2176         } else {
2177                 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2178                 if (rc < 0) {
2179                         if (netif_msg_probe(tp)) {
2180                                 dev_err(&pdev->dev,
2181                                         "DMA configuration failed.\n");
2182                         }
2183                         goto err_out_free_res_4;
2184                 }
2185         }
2186
2187         /* ioremap MMIO region */
2188         ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
2189         if (!ioaddr) {
2190                 if (netif_msg_probe(tp))
2191                         dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
2192                 rc = -EIO;
2193                 goto err_out_free_res_4;
2194         }
2195
2196         tp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
2197         if (!tp->pcie_cap && netif_msg_probe(tp))
2198                 dev_info(&pdev->dev, "no PCI Express capability\n");
2199
2200         RTL_W16(IntrMask, 0x0000);
2201
2202         /* Soft reset the chip. */
2203         RTL_W8(ChipCmd, CmdReset);
2204
2205         /* Check that the chip has finished the reset. */
2206         for (i = 0; i < 100; i++) {
2207                 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
2208                         break;
2209                 msleep_interruptible(1);
2210         }
2211
2212         RTL_W16(IntrStatus, 0xffff);
2213
2214         pci_set_master(pdev);
2215
2216         /* Identify chip attached to board */
2217         rtl8169_get_mac_version(tp, ioaddr);
2218
2219         /* Use appropriate default if unknown */
2220         if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2221                 if (netif_msg_probe(tp)) {
2222                         dev_notice(&pdev->dev,
2223                                    "unknown MAC, using family default\n");
2224                 }
2225                 tp->mac_version = cfg->default_ver;
2226         }
2227
2228         rtl8169_print_mac_version(tp);
2229
2230         for (i = 0; i < ARRAY_SIZE(rtl_chip_info); i++) {
2231                 if (tp->mac_version == rtl_chip_info[i].mac_version)
2232                         break;
2233         }
2234         if (i == ARRAY_SIZE(rtl_chip_info)) {
2235                 dev_err(&pdev->dev,
2236                         "driver bug, MAC version not found in rtl_chip_info\n");
2237                 goto err_out_msi_5;
2238         }
2239         tp->chipset = i;
2240
2241         RTL_W8(Cfg9346, Cfg9346_Unlock);
2242         RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
2243         RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
2244         if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
2245                 tp->features |= RTL_FEATURE_WOL;
2246         if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
2247                 tp->features |= RTL_FEATURE_WOL;
2248         tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
2249         RTL_W8(Cfg9346, Cfg9346_Lock);
2250
2251         if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
2252             (RTL_R8(PHYstatus) & TBI_Enable)) {
2253                 tp->set_speed = rtl8169_set_speed_tbi;
2254                 tp->get_settings = rtl8169_gset_tbi;
2255                 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
2256                 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
2257                 tp->link_ok = rtl8169_tbi_link_ok;
2258                 tp->do_ioctl = rtl_tbi_ioctl;
2259
2260                 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
2261         } else {
2262                 tp->set_speed = rtl8169_set_speed_xmii;
2263                 tp->get_settings = rtl8169_gset_xmii;
2264                 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
2265                 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
2266                 tp->link_ok = rtl8169_xmii_link_ok;
2267                 tp->do_ioctl = rtl_xmii_ioctl;
2268         }
2269
2270         spin_lock_init(&tp->lock);
2271
2272         tp->mmio_addr = ioaddr;
2273
2274         /* Get MAC address */
2275         for (i = 0; i < MAC_ADDR_LEN; i++)
2276                 dev->dev_addr[i] = RTL_R8(MAC0 + i);
2277         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
2278
2279         SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
2280         dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
2281         dev->irq = pdev->irq;
2282         dev->base_addr = (unsigned long) ioaddr;
2283
2284         netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
2285
2286 #ifdef CONFIG_R8169_VLAN
2287         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
2288 #endif
2289
2290         tp->intr_mask = 0xffff;
2291         tp->align = cfg->align;
2292         tp->hw_start = cfg->hw_start;
2293         tp->intr_event = cfg->intr_event;
2294         tp->napi_event = cfg->napi_event;
2295
2296         init_timer(&tp->timer);
2297         tp->timer.data = (unsigned long) dev;
2298         tp->timer.function = rtl8169_phy_timer;
2299
2300         rc = register_netdev(dev);
2301         if (rc < 0)
2302                 goto err_out_msi_5;
2303
2304         pci_set_drvdata(pdev, dev);
2305
2306         if (netif_msg_probe(tp)) {
2307                 u32 xid = RTL_R32(TxConfig) & 0x9cf0f8ff;
2308
2309                 printk(KERN_INFO "%s: %s at 0x%lx, "
2310                        "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
2311                        "XID %08x IRQ %d\n",
2312                        dev->name,
2313                        rtl_chip_info[tp->chipset].name,
2314                        dev->base_addr,
2315                        dev->dev_addr[0], dev->dev_addr[1],
2316                        dev->dev_addr[2], dev->dev_addr[3],
2317                        dev->dev_addr[4], dev->dev_addr[5], xid, dev->irq);
2318         }
2319
2320         rtl8169_init_phy(dev, tp);
2321         device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
2322
2323 out:
2324         return rc;
2325
2326 err_out_msi_5:
2327         rtl_disable_msi(pdev, tp);
2328         iounmap(ioaddr);
2329 err_out_free_res_4:
2330         pci_release_regions(pdev);
2331 err_out_mwi_3:
2332         pci_clear_mwi(pdev);
2333 err_out_disable_2:
2334         pci_disable_device(pdev);
2335 err_out_free_dev_1:
2336         free_netdev(dev);
2337         goto out;
2338 }
2339
2340 static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
2341 {
2342         struct net_device *dev = pci_get_drvdata(pdev);
2343         struct rtl8169_private *tp = netdev_priv(dev);
2344
2345         flush_scheduled_work();
2346
2347         unregister_netdev(dev);
2348         rtl_disable_msi(pdev, tp);
2349         rtl8169_release_board(pdev, dev, tp->mmio_addr);
2350         pci_set_drvdata(pdev, NULL);
2351 }
2352
2353 static void rtl8169_set_rxbufsize(struct rtl8169_private *tp,
2354                                   struct net_device *dev)
2355 {
2356         unsigned int mtu = dev->mtu;
2357
2358         tp->rx_buf_sz = (mtu > RX_BUF_SIZE) ? mtu + ETH_HLEN + 8 : RX_BUF_SIZE;
2359 }
2360
2361 static int rtl8169_open(struct net_device *dev)
2362 {
2363         struct rtl8169_private *tp = netdev_priv(dev);
2364         struct pci_dev *pdev = tp->pci_dev;
2365         int retval = -ENOMEM;
2366
2367
2368         rtl8169_set_rxbufsize(tp, dev);
2369
2370         /*
2371          * Rx and Tx desscriptors needs 256 bytes alignment.
2372          * pci_alloc_consistent provides more.
2373          */
2374         tp->TxDescArray = pci_alloc_consistent(pdev, R8169_TX_RING_BYTES,
2375                                                &tp->TxPhyAddr);
2376         if (!tp->TxDescArray)
2377                 goto out;
2378
2379         tp->RxDescArray = pci_alloc_consistent(pdev, R8169_RX_RING_BYTES,
2380                                                &tp->RxPhyAddr);
2381         if (!tp->RxDescArray)
2382                 goto err_free_tx_0;
2383
2384         retval = rtl8169_init_ring(dev);
2385         if (retval < 0)
2386                 goto err_free_rx_1;
2387
2388         INIT_DELAYED_WORK(&tp->task, NULL);
2389
2390         smp_mb();
2391
2392         retval = request_irq(dev->irq, rtl8169_interrupt,
2393                              (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
2394                              dev->name, dev);
2395         if (retval < 0)
2396                 goto err_release_ring_2;
2397
2398         napi_enable(&tp->napi);
2399
2400         rtl_hw_start(dev);
2401
2402         rtl8169_request_timer(dev);
2403
2404         rtl8169_check_link_status(dev, tp, tp->mmio_addr);
2405 out:
2406         return retval;
2407
2408 err_release_ring_2:
2409         rtl8169_rx_clear(tp);
2410 err_free_rx_1:
2411         pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
2412                             tp->RxPhyAddr);
2413 err_free_tx_0:
2414         pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
2415                             tp->TxPhyAddr);
2416         goto out;
2417 }
2418
2419 static void rtl8169_hw_reset(void __iomem *ioaddr)
2420 {
2421         /* Disable interrupts */
2422         rtl8169_irq_mask_and_ack(ioaddr);
2423
2424         /* Reset the chipset */
2425         RTL_W8(ChipCmd, CmdReset);
2426
2427         /* PCI commit */
2428         RTL_R8(ChipCmd);
2429 }
2430
2431 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
2432 {
2433         void __iomem *ioaddr = tp->mmio_addr;
2434         u32 cfg = rtl8169_rx_config;
2435
2436         cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
2437         RTL_W32(RxConfig, cfg);
2438
2439         /* Set DMA burst size and Interframe Gap Time */
2440         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
2441                 (InterFrameGap << TxInterFrameGapShift));
2442 }
2443
2444 static void rtl_hw_start(struct net_device *dev)
2445 {
2446         struct rtl8169_private *tp = netdev_priv(dev);
2447         void __iomem *ioaddr = tp->mmio_addr;
2448         unsigned int i;
2449
2450         /* Soft reset the chip. */
2451         RTL_W8(ChipCmd, CmdReset);
2452
2453         /* Check that the chip has finished the reset. */
2454         for (i = 0; i < 100; i++) {
2455                 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
2456                         break;
2457                 msleep_interruptible(1);
2458         }
2459
2460         tp->hw_start(dev);
2461
2462         netif_start_queue(dev);
2463 }
2464
2465
2466 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
2467                                          void __iomem *ioaddr)
2468 {
2469         /*
2470          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
2471          * register to be written before TxDescAddrLow to work.
2472          * Switching from MMIO to I/O access fixes the issue as well.
2473          */
2474         RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
2475         RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
2476         RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
2477         RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
2478 }
2479
2480 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
2481 {
2482         u16 cmd;
2483
2484         cmd = RTL_R16(CPlusCmd);
2485         RTL_W16(CPlusCmd, cmd);
2486         return cmd;
2487 }
2488
2489 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
2490 {
2491         /* Low hurts. Let's disable the filtering. */
2492         RTL_W16(RxMaxSize, rx_buf_sz);
2493 }
2494
2495 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
2496 {
2497         struct {
2498                 u32 mac_version;
2499                 u32 clk;
2500                 u32 val;
2501         } cfg2_info [] = {
2502                 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
2503                 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
2504                 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
2505                 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
2506         }, *p = cfg2_info;
2507         unsigned int i;
2508         u32 clk;
2509
2510         clk = RTL_R8(Config2) & PCI_Clock_66MHz;
2511         for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
2512                 if ((p->mac_version == mac_version) && (p->clk == clk)) {
2513                         RTL_W32(0x7c, p->val);
2514                         break;
2515                 }
2516         }
2517 }
2518
2519 static void rtl_hw_start_8169(struct net_device *dev)
2520 {
2521         struct rtl8169_private *tp = netdev_priv(dev);
2522         void __iomem *ioaddr = tp->mmio_addr;
2523         struct pci_dev *pdev = tp->pci_dev;
2524
2525         if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
2526                 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
2527                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
2528         }
2529
2530         RTL_W8(Cfg9346, Cfg9346_Unlock);
2531         if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
2532             (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2533             (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
2534             (tp->mac_version == RTL_GIGA_MAC_VER_04))
2535                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2536
2537         RTL_W8(EarlyTxThres, EarlyTxThld);
2538
2539         rtl_set_rx_max_size(ioaddr, tp->rx_buf_sz);
2540
2541         if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
2542             (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2543             (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
2544             (tp->mac_version == RTL_GIGA_MAC_VER_04))
2545                 rtl_set_rx_tx_config_registers(tp);
2546
2547         tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
2548
2549         if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2550             (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
2551                 dprintk("Set MAC Reg C+CR Offset 0xE0. "
2552                         "Bit-3 and bit-14 MUST be 1\n");
2553                 tp->cp_cmd |= (1 << 14);
2554         }
2555
2556         RTL_W16(CPlusCmd, tp->cp_cmd);
2557
2558         rtl8169_set_magic_reg(ioaddr, tp->mac_version);
2559
2560         /*
2561          * Undocumented corner. Supposedly:
2562          * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
2563          */
2564         RTL_W16(IntrMitigate, 0x0000);
2565
2566         rtl_set_rx_tx_desc_registers(tp, ioaddr);
2567
2568         if ((tp->mac_version != RTL_GIGA_MAC_VER_01) &&
2569             (tp->mac_version != RTL_GIGA_MAC_VER_02) &&
2570             (tp->mac_version != RTL_GIGA_MAC_VER_03) &&
2571             (tp->mac_version != RTL_GIGA_MAC_VER_04)) {
2572                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2573                 rtl_set_rx_tx_config_registers(tp);
2574         }
2575
2576         RTL_W8(Cfg9346, Cfg9346_Lock);
2577
2578         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
2579         RTL_R8(IntrMask);
2580
2581         RTL_W32(RxMissed, 0);
2582
2583         rtl_set_rx_mode(dev);
2584
2585         /* no early-rx interrupts */
2586         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
2587
2588         /* Enable all known interrupts by setting the interrupt mask. */
2589         RTL_W16(IntrMask, tp->intr_event);
2590 }
2591
2592 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
2593 {
2594         struct net_device *dev = pci_get_drvdata(pdev);
2595         struct rtl8169_private *tp = netdev_priv(dev);
2596         int cap = tp->pcie_cap;
2597
2598         if (cap) {
2599                 u16 ctl;
2600
2601                 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
2602                 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
2603                 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
2604         }
2605 }
2606
2607 static void rtl_csi_access_enable(void __iomem *ioaddr)
2608 {
2609         u32 csi;
2610
2611         csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
2612         rtl_csi_write(ioaddr, 0x070c, csi | 0x27000000);
2613 }
2614
2615 struct ephy_info {
2616         unsigned int offset;
2617         u16 mask;
2618         u16 bits;
2619 };
2620
2621 static void rtl_ephy_init(void __iomem *ioaddr, struct ephy_info *e, int len)
2622 {
2623         u16 w;
2624
2625         while (len-- > 0) {
2626                 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
2627                 rtl_ephy_write(ioaddr, e->offset, w);
2628                 e++;
2629         }
2630 }
2631
2632 static void rtl_disable_clock_request(struct pci_dev *pdev)
2633 {
2634         struct net_device *dev = pci_get_drvdata(pdev);
2635         struct rtl8169_private *tp = netdev_priv(dev);
2636         int cap = tp->pcie_cap;
2637
2638         if (cap) {
2639                 u16 ctl;
2640
2641                 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
2642                 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
2643                 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
2644         }
2645 }
2646
2647 #define R8168_CPCMD_QUIRK_MASK (\
2648         EnableBist | \
2649         Mac_dbgo_oe | \
2650         Force_half_dup | \
2651         Force_rxflow_en | \
2652         Force_txflow_en | \
2653         Cxpl_dbg_sel | \
2654         ASF | \
2655         PktCntrDisable | \
2656         Mac_dbgo_sel)
2657
2658 static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
2659 {
2660         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2661
2662         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
2663
2664         rtl_tx_performance_tweak(pdev,
2665                 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
2666 }
2667
2668 static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
2669 {
2670         rtl_hw_start_8168bb(ioaddr, pdev);
2671
2672         RTL_W8(EarlyTxThres, EarlyTxThld);
2673
2674         RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
2675 }
2676
2677 static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
2678 {
2679         RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
2680
2681         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2682
2683         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2684
2685         rtl_disable_clock_request(pdev);
2686
2687         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
2688 }
2689
2690 static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
2691 {
2692         static struct ephy_info e_info_8168cp[] = {
2693                 { 0x01, 0,      0x0001 },
2694                 { 0x02, 0x0800, 0x1000 },
2695                 { 0x03, 0,      0x0042 },
2696                 { 0x06, 0x0080, 0x0000 },
2697                 { 0x07, 0,      0x2000 }
2698         };
2699
2700         rtl_csi_access_enable(ioaddr);
2701
2702         rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
2703
2704         __rtl_hw_start_8168cp(ioaddr, pdev);
2705 }
2706
2707 static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
2708 {
2709         rtl_csi_access_enable(ioaddr);
2710
2711         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2712
2713         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2714
2715         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
2716 }
2717
2718 static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
2719 {
2720         rtl_csi_access_enable(ioaddr);
2721
2722         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2723
2724         /* Magic. */
2725         RTL_W8(DBG_REG, 0x20);
2726
2727         RTL_W8(EarlyTxThres, EarlyTxThld);
2728
2729         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2730
2731         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
2732 }
2733
2734 static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
2735 {
2736         static struct ephy_info e_info_8168c_1[] = {
2737                 { 0x02, 0x0800, 0x1000 },
2738                 { 0x03, 0,      0x0002 },
2739                 { 0x06, 0x0080, 0x0000 }
2740         };
2741
2742         rtl_csi_access_enable(ioaddr);
2743
2744         RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
2745
2746         rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
2747
2748         __rtl_hw_start_8168cp(ioaddr, pdev);
2749 }
2750
2751 static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
2752 {
2753         static struct ephy_info e_info_8168c_2[] = {
2754                 { 0x01, 0,      0x0001 },
2755                 { 0x03, 0x0400, 0x0220 }
2756         };
2757
2758         rtl_csi_access_enable(ioaddr);
2759
2760         rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
2761
2762         __rtl_hw_start_8168cp(ioaddr, pdev);
2763 }
2764
2765 static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
2766 {
2767         rtl_hw_start_8168c_2(ioaddr, pdev);
2768 }
2769
2770 static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
2771 {
2772         rtl_csi_access_enable(ioaddr);
2773
2774         __rtl_hw_start_8168cp(ioaddr, pdev);
2775 }
2776
2777 static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
2778 {
2779         rtl_csi_access_enable(ioaddr);
2780
2781         rtl_disable_clock_request(pdev);
2782
2783         RTL_W8(EarlyTxThres, EarlyTxThld);
2784
2785         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2786
2787         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
2788 }
2789
2790 static void rtl_hw_start_8168(struct net_device *dev)
2791 {
2792         struct rtl8169_private *tp = netdev_priv(dev);
2793         void __iomem *ioaddr = tp->mmio_addr;
2794         struct pci_dev *pdev = tp->pci_dev;
2795
2796         RTL_W8(Cfg9346, Cfg9346_Unlock);
2797
2798         RTL_W8(EarlyTxThres, EarlyTxThld);
2799
2800         rtl_set_rx_max_size(ioaddr, tp->rx_buf_sz);
2801
2802         tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
2803
2804         RTL_W16(CPlusCmd, tp->cp_cmd);
2805
2806         RTL_W16(IntrMitigate, 0x5151);
2807
2808         /* Work around for RxFIFO overflow. */
2809         if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
2810                 tp->intr_event |= RxFIFOOver | PCSTimeout;
2811                 tp->intr_event &= ~RxOverflow;
2812         }
2813
2814         rtl_set_rx_tx_desc_registers(tp, ioaddr);
2815
2816         rtl_set_rx_mode(dev);
2817
2818         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
2819                 (InterFrameGap << TxInterFrameGapShift));
2820
2821         RTL_R8(IntrMask);
2822
2823         switch (tp->mac_version) {
2824         case RTL_GIGA_MAC_VER_11:
2825                 rtl_hw_start_8168bb(ioaddr, pdev);
2826         break;
2827
2828         case RTL_GIGA_MAC_VER_12:
2829         case RTL_GIGA_MAC_VER_17:
2830                 rtl_hw_start_8168bef(ioaddr, pdev);
2831         break;
2832
2833         case RTL_GIGA_MAC_VER_18:
2834                 rtl_hw_start_8168cp_1(ioaddr, pdev);
2835         break;
2836
2837         case RTL_GIGA_MAC_VER_19:
2838                 rtl_hw_start_8168c_1(ioaddr, pdev);
2839         break;
2840
2841         case RTL_GIGA_MAC_VER_20:
2842                 rtl_hw_start_8168c_2(ioaddr, pdev);
2843         break;
2844
2845         case RTL_GIGA_MAC_VER_21:
2846                 rtl_hw_start_8168c_3(ioaddr, pdev);
2847         break;
2848
2849         case RTL_GIGA_MAC_VER_22:
2850                 rtl_hw_start_8168c_4(ioaddr, pdev);
2851         break;
2852
2853         case RTL_GIGA_MAC_VER_23:
2854                 rtl_hw_start_8168cp_2(ioaddr, pdev);
2855         break;
2856
2857         case RTL_GIGA_MAC_VER_24:
2858                 rtl_hw_start_8168cp_3(ioaddr, pdev);
2859         break;
2860
2861         case RTL_GIGA_MAC_VER_25:
2862                 rtl_hw_start_8168d(ioaddr, pdev);
2863         break;
2864
2865         default:
2866                 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
2867                         dev->name, tp->mac_version);
2868         break;
2869         }
2870
2871         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2872
2873         RTL_W8(Cfg9346, Cfg9346_Lock);
2874
2875         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
2876
2877         RTL_W16(IntrMask, tp->intr_event);
2878 }
2879
2880 #define R810X_CPCMD_QUIRK_MASK (\
2881         EnableBist | \
2882         Mac_dbgo_oe | \
2883         Force_half_dup | \
2884         Force_rxflow_en | \
2885         Force_txflow_en | \
2886         Cxpl_dbg_sel | \
2887         ASF | \
2888         PktCntrDisable | \
2889         PCIDAC | \
2890         PCIMulRW)
2891
2892 static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
2893 {
2894         static struct ephy_info e_info_8102e_1[] = {
2895                 { 0x01, 0, 0x6e65 },
2896                 { 0x02, 0, 0x091f },
2897                 { 0x03, 0, 0xc2f9 },
2898                 { 0x06, 0, 0xafb5 },
2899                 { 0x07, 0, 0x0e00 },
2900                 { 0x19, 0, 0xec80 },
2901                 { 0x01, 0, 0x2e65 },
2902                 { 0x01, 0, 0x6e65 }
2903         };
2904         u8 cfg1;
2905
2906         rtl_csi_access_enable(ioaddr);
2907
2908         RTL_W8(DBG_REG, FIX_NAK_1);
2909
2910         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2911
2912         RTL_W8(Config1,
2913                LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
2914         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2915
2916         cfg1 = RTL_R8(Config1);
2917         if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
2918                 RTL_W8(Config1, cfg1 & ~LEDS0);
2919
2920         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
2921
2922         rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
2923 }
2924
2925 static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
2926 {
2927         rtl_csi_access_enable(ioaddr);
2928
2929         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2930
2931         RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
2932         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2933
2934         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
2935 }
2936
2937 static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
2938 {
2939         rtl_hw_start_8102e_2(ioaddr, pdev);
2940
2941         rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
2942 }
2943
2944 static void rtl_hw_start_8101(struct net_device *dev)
2945 {
2946         struct rtl8169_private *tp = netdev_priv(dev);
2947         void __iomem *ioaddr = tp->mmio_addr;
2948         struct pci_dev *pdev = tp->pci_dev;
2949
2950         if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
2951             (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
2952                 int cap = tp->pcie_cap;
2953
2954                 if (cap) {
2955                         pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
2956                                               PCI_EXP_DEVCTL_NOSNOOP_EN);
2957                 }
2958         }
2959
2960         switch (tp->mac_version) {
2961         case RTL_GIGA_MAC_VER_07:
2962                 rtl_hw_start_8102e_1(ioaddr, pdev);
2963                 break;
2964
2965         case RTL_GIGA_MAC_VER_08:
2966                 rtl_hw_start_8102e_3(ioaddr, pdev);
2967                 break;
2968
2969         case RTL_GIGA_MAC_VER_09:
2970                 rtl_hw_start_8102e_2(ioaddr, pdev);
2971                 break;
2972         }
2973
2974         RTL_W8(Cfg9346, Cfg9346_Unlock);
2975
2976         RTL_W8(EarlyTxThres, EarlyTxThld);
2977
2978         rtl_set_rx_max_size(ioaddr, tp->rx_buf_sz);
2979
2980         tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
2981
2982         RTL_W16(CPlusCmd, tp->cp_cmd);
2983
2984         RTL_W16(IntrMitigate, 0x0000);
2985
2986         rtl_set_rx_tx_desc_registers(tp, ioaddr);
2987
2988         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2989         rtl_set_rx_tx_config_registers(tp);
2990
2991         RTL_W8(Cfg9346, Cfg9346_Lock);
2992
2993         RTL_R8(IntrMask);
2994
2995         rtl_set_rx_mode(dev);
2996
2997         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2998
2999         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
3000
3001         RTL_W16(IntrMask, tp->intr_event);
3002 }
3003
3004 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
3005 {
3006         struct rtl8169_private *tp = netdev_priv(dev);
3007         int ret = 0;
3008
3009         if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
3010                 return -EINVAL;
3011
3012         dev->mtu = new_mtu;
3013
3014         if (!netif_running(dev))
3015                 goto out;
3016
3017         rtl8169_down(dev);
3018
3019         rtl8169_set_rxbufsize(tp, dev);
3020
3021         ret = rtl8169_init_ring(dev);
3022         if (ret < 0)
3023                 goto out;
3024
3025         napi_enable(&tp->napi);
3026
3027         rtl_hw_start(dev);
3028
3029         rtl8169_request_timer(dev);
3030
3031 out:
3032         return ret;
3033 }
3034
3035 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
3036 {
3037         desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
3038         desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
3039 }
3040
3041 static void rtl8169_free_rx_skb(struct rtl8169_private *tp,
3042                                 struct sk_buff **sk_buff, struct RxDesc *desc)
3043 {
3044         struct pci_dev *pdev = tp->pci_dev;
3045
3046         pci_unmap_single(pdev, le64_to_cpu(desc->addr), tp->rx_buf_sz,
3047                          PCI_DMA_FROMDEVICE);
3048         dev_kfree_skb(*sk_buff);
3049         *sk_buff = NULL;
3050         rtl8169_make_unusable_by_asic(desc);
3051 }
3052
3053 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
3054 {
3055         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
3056
3057         desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
3058 }
3059
3060 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
3061                                        u32 rx_buf_sz)
3062 {
3063         desc->addr = cpu_to_le64(mapping);
3064         wmb();
3065         rtl8169_mark_to_asic(desc, rx_buf_sz);
3066 }
3067
3068 static struct sk_buff *rtl8169_alloc_rx_skb(struct pci_dev *pdev,
3069                                             struct net_device *dev,
3070                                             struct RxDesc *desc, int rx_buf_sz,
3071                                             unsigned int align)
3072 {
3073         struct sk_buff *skb;
3074         dma_addr_t mapping;
3075         unsigned int pad;
3076
3077         pad = align ? align : NET_IP_ALIGN;
3078
3079         skb = netdev_alloc_skb(dev, rx_buf_sz + pad);
3080         if (!skb)
3081                 goto err_out;
3082
3083         skb_reserve(skb, align ? ((pad - 1) & (unsigned long)skb->data) : pad);
3084
3085         mapping = pci_map_single(pdev, skb->data, rx_buf_sz,
3086                                  PCI_DMA_FROMDEVICE);
3087
3088         rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
3089 out:
3090         return skb;
3091
3092 err_out:
3093         rtl8169_make_unusable_by_asic(desc);
3094         goto out;
3095 }
3096
3097 static void rtl8169_rx_clear(struct rtl8169_private *tp)
3098 {
3099         unsigned int i;
3100
3101         for (i = 0; i < NUM_RX_DESC; i++) {
3102                 if (tp->Rx_skbuff[i]) {
3103                         rtl8169_free_rx_skb(tp, tp->Rx_skbuff + i,
3104                                             tp->RxDescArray + i);
3105                 }
3106         }
3107 }
3108
3109 static u32 rtl8169_rx_fill(struct rtl8169_private *tp, struct net_device *dev,
3110                            u32 start, u32 end)
3111 {
3112         u32 cur;
3113
3114         for (cur = start; end - cur != 0; cur++) {
3115                 struct sk_buff *skb;
3116                 unsigned int i = cur % NUM_RX_DESC;
3117
3118                 WARN_ON((s32)(end - cur) < 0);
3119
3120                 if (tp->Rx_skbuff[i])
3121                         continue;
3122
3123                 skb = rtl8169_alloc_rx_skb(tp->pci_dev, dev,
3124                                            tp->RxDescArray + i,
3125                                            tp->rx_buf_sz, tp->align);
3126                 if (!skb)
3127                         break;
3128
3129                 tp->Rx_skbuff[i] = skb;
3130         }
3131         return cur - start;
3132 }
3133
3134 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
3135 {
3136         desc->opts1 |= cpu_to_le32(RingEnd);
3137 }
3138
3139 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
3140 {
3141         tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
3142 }
3143
3144 static int rtl8169_init_ring(struct net_device *dev)
3145 {
3146         struct rtl8169_private *tp = netdev_priv(dev);
3147
3148         rtl8169_init_ring_indexes(tp);
3149
3150         memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
3151         memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));
3152
3153         if (rtl8169_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC)
3154                 goto err_out;
3155
3156         rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
3157
3158         return 0;
3159
3160 err_out:
3161         rtl8169_rx_clear(tp);
3162         return -ENOMEM;
3163 }
3164
3165 static void rtl8169_unmap_tx_skb(struct pci_dev *pdev, struct ring_info *tx_skb,
3166                                  struct TxDesc *desc)
3167 {
3168         unsigned int len = tx_skb->len;
3169
3170         pci_unmap_single(pdev, le64_to_cpu(desc->addr), len, PCI_DMA_TODEVICE);
3171         desc->opts1 = 0x00;
3172         desc->opts2 = 0x00;
3173         desc->addr = 0x00;
3174         tx_skb->len = 0;
3175 }
3176
3177 static void rtl8169_tx_clear(struct rtl8169_private *tp)
3178 {
3179         unsigned int i;
3180
3181         for (i = tp->dirty_tx; i < tp->dirty_tx + NUM_TX_DESC; i++) {
3182                 unsigned int entry = i % NUM_TX_DESC;
3183                 struct ring_info *tx_skb = tp->tx_skb + entry;
3184                 unsigned int len = tx_skb->len;
3185
3186                 if (len) {
3187                         struct sk_buff *skb = tx_skb->skb;
3188
3189                         rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb,
3190                                              tp->TxDescArray + entry);
3191                         if (skb) {
3192                                 dev_kfree_skb(skb);
3193                                 tx_skb->skb = NULL;
3194                         }
3195                         tp->dev->stats.tx_dropped++;
3196                 }
3197         }
3198         tp->cur_tx = tp->dirty_tx = 0;
3199 }
3200
3201 static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
3202 {
3203         struct rtl8169_private *tp = netdev_priv(dev);
3204
3205         PREPARE_DELAYED_WORK(&tp->task, task);
3206         schedule_delayed_work(&tp->task, 4);
3207 }
3208
3209 static void rtl8169_wait_for_quiescence(struct net_device *dev)
3210 {
3211         struct rtl8169_private *tp = netdev_priv(dev);
3212         void __iomem *ioaddr = tp->mmio_addr;
3213
3214         synchronize_irq(dev->irq);
3215
3216         /* Wait for any pending NAPI task to complete */
3217         napi_disable(&tp->napi);
3218
3219         rtl8169_irq_mask_and_ack(ioaddr);
3220
3221         tp->intr_mask = 0xffff;
3222         RTL_W16(IntrMask, tp->intr_event);
3223         napi_enable(&tp->napi);
3224 }
3225
3226 static void rtl8169_reinit_task(struct work_struct *work)
3227 {
3228         struct rtl8169_private *tp =
3229                 container_of(work, struct rtl8169_private, task.work);
3230         struct net_device *dev = tp->dev;
3231         int ret;
3232
3233         rtnl_lock();
3234
3235         if (!netif_running(dev))
3236                 goto out_unlock;
3237
3238         rtl8169_wait_for_quiescence(dev);
3239         rtl8169_close(dev);
3240
3241         ret = rtl8169_open(dev);
3242         if (unlikely(ret < 0)) {
3243                 if (net_ratelimit() && netif_msg_drv(tp)) {
3244                         printk(KERN_ERR PFX "%s: reinit failure (status = %d)."
3245                                " Rescheduling.\n", dev->name, ret);
3246                 }
3247                 rtl8169_schedule_work(dev, rtl8169_reinit_task);
3248         }
3249
3250 out_unlock:
3251         rtnl_unlock();
3252 }
3253
3254 static void rtl8169_reset_task(struct work_struct *work)
3255 {
3256         struct rtl8169_private *tp =
3257                 container_of(work, struct rtl8169_private, task.work);
3258         struct net_device *dev = tp->dev;
3259
3260         rtnl_lock();
3261
3262         if (!netif_running(dev))
3263                 goto out_unlock;
3264
3265         rtl8169_wait_for_quiescence(dev);
3266
3267         rtl8169_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0);
3268         rtl8169_tx_clear(tp);
3269
3270         if (tp->dirty_rx == tp->cur_rx) {
3271                 rtl8169_init_ring_indexes(tp);
3272                 rtl_hw_start(dev);
3273                 netif_wake_queue(dev);
3274                 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
3275         } else {
3276                 if (net_ratelimit() && netif_msg_intr(tp)) {
3277                         printk(KERN_EMERG PFX "%s: Rx buffers shortage\n",
3278                                dev->name);
3279                 }
3280                 rtl8169_schedule_work(dev, rtl8169_reset_task);
3281         }
3282
3283 out_unlock:
3284         rtnl_unlock();
3285 }
3286
3287 static void rtl8169_tx_timeout(struct net_device *dev)
3288 {
3289         struct rtl8169_private *tp = netdev_priv(dev);
3290
3291         rtl8169_hw_reset(tp->mmio_addr);
3292
3293         /* Let's wait a bit while any (async) irq lands on */
3294         rtl8169_schedule_work(dev, rtl8169_reset_task);
3295 }
3296
3297 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
3298                               u32 opts1)
3299 {
3300         struct skb_shared_info *info = skb_shinfo(skb);
3301         unsigned int cur_frag, entry;
3302         struct TxDesc * uninitialized_var(txd);
3303
3304         entry = tp->cur_tx;
3305         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
3306                 skb_frag_t *frag = info->frags + cur_frag;
3307                 dma_addr_t mapping;
3308                 u32 status, len;
3309                 void *addr;
3310
3311                 entry = (entry + 1) % NUM_TX_DESC;
3312
3313                 txd = tp->TxDescArray + entry;
3314                 len = frag->size;
3315                 addr = ((void *) page_address(frag->page)) + frag->page_offset;
3316                 mapping = pci_map_single(tp->pci_dev, addr, len, PCI_DMA_TODEVICE);
3317
3318                 /* anti gcc 2.95.3 bugware (sic) */
3319                 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
3320
3321                 txd->opts1 = cpu_to_le32(status);
3322                 txd->addr = cpu_to_le64(mapping);
3323
3324                 tp->tx_skb[entry].len = len;
3325         }
3326
3327         if (cur_frag) {
3328                 tp->tx_skb[entry].skb = skb;
3329                 txd->opts1 |= cpu_to_le32(LastFrag);
3330         }
3331
3332         return cur_frag;
3333 }
3334
3335 static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
3336 {
3337         if (dev->features & NETIF_F_TSO) {
3338                 u32 mss = skb_shinfo(skb)->gso_size;
3339
3340                 if (mss)
3341                         return LargeSend | ((mss & MSSMask) << MSSShift);
3342         }
3343         if (skb->ip_summed == CHECKSUM_PARTIAL) {
3344                 const struct iphdr *ip = ip_hdr(skb);
3345
3346                 if (ip->protocol == IPPROTO_TCP)
3347                         return IPCS | TCPCS;
3348                 else if (ip->protocol == IPPROTO_UDP)
3349                         return IPCS | UDPCS;
3350                 WARN_ON(1);     /* we need a WARN() */
3351         }
3352         return 0;
3353 }
3354
3355 static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev)
3356 {
3357         struct rtl8169_private *tp = netdev_priv(dev);
3358         unsigned int frags, entry = tp->cur_tx % NUM_TX_DESC;
3359         struct TxDesc *txd = tp->TxDescArray + entry;
3360         void __iomem *ioaddr = tp->mmio_addr;
3361         dma_addr_t mapping;
3362         u32 status, len;
3363         u32 opts1;
3364         int ret = NETDEV_TX_OK;
3365
3366         if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
3367                 if (netif_msg_drv(tp)) {
3368                         printk(KERN_ERR
3369                                "%s: BUG! Tx Ring full when queue awake!\n",
3370                                dev->name);
3371                 }
3372                 goto err_stop;
3373         }
3374
3375         if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
3376                 goto err_stop;
3377
3378         opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
3379
3380         frags = rtl8169_xmit_frags(tp, skb, opts1);
3381         if (frags) {
3382                 len = skb_headlen(skb);
3383                 opts1 |= FirstFrag;
3384         } else {
3385                 len = skb->len;
3386                 opts1 |= FirstFrag | LastFrag;
3387                 tp->tx_skb[entry].skb = skb;
3388         }
3389
3390         mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
3391
3392         tp->tx_skb[entry].len = len;
3393         txd->addr = cpu_to_le64(mapping);
3394         txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
3395
3396         wmb();
3397
3398         /* anti gcc 2.95.3 bugware (sic) */
3399         status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
3400         txd->opts1 = cpu_to_le32(status);
3401
3402         tp->cur_tx += frags + 1;
3403
3404         smp_wmb();
3405
3406         RTL_W8(TxPoll, NPQ);    /* set polling bit */
3407
3408         if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
3409                 netif_stop_queue(dev);
3410                 smp_rmb();
3411                 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
3412                         netif_wake_queue(dev);
3413         }
3414
3415 out:
3416         return ret;
3417
3418 err_stop:
3419         netif_stop_queue(dev);
3420         ret = NETDEV_TX_BUSY;
3421         dev->stats.tx_dropped++;
3422         goto out;
3423 }
3424
3425 static void rtl8169_pcierr_interrupt(struct net_device *dev)
3426 {
3427         struct rtl8169_private *tp = netdev_priv(dev);
3428         struct pci_dev *pdev = tp->pci_dev;
3429         void __iomem *ioaddr = tp->mmio_addr;
3430         u16 pci_status, pci_cmd;
3431
3432         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
3433         pci_read_config_word(pdev, PCI_STATUS, &pci_status);
3434
3435         if (netif_msg_intr(tp)) {
3436                 printk(KERN_ERR
3437                        "%s: PCI error (cmd = 0x%04x, status = 0x%04x).\n",
3438                        dev->name, pci_cmd, pci_status);
3439         }
3440
3441         /*
3442          * The recovery sequence below admits a very elaborated explanation:
3443          * - it seems to work;
3444          * - I did not see what else could be done;
3445          * - it makes iop3xx happy.
3446          *
3447          * Feel free to adjust to your needs.
3448          */
3449         if (pdev->broken_parity_status)
3450                 pci_cmd &= ~PCI_COMMAND_PARITY;
3451         else
3452                 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
3453
3454         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
3455
3456         pci_write_config_word(pdev, PCI_STATUS,
3457                 pci_status & (PCI_STATUS_DETECTED_PARITY |
3458                 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
3459                 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
3460
3461         /* The infamous DAC f*ckup only happens at boot time */
3462         if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
3463                 if (netif_msg_intr(tp))
3464                         printk(KERN_INFO "%s: disabling PCI DAC.\n", dev->name);
3465                 tp->cp_cmd &= ~PCIDAC;
3466                 RTL_W16(CPlusCmd, tp->cp_cmd);
3467                 dev->features &= ~NETIF_F_HIGHDMA;
3468         }
3469
3470         rtl8169_hw_reset(ioaddr);
3471
3472         rtl8169_schedule_work(dev, rtl8169_reinit_task);
3473 }
3474
3475 static void rtl8169_tx_interrupt(struct net_device *dev,
3476                                  struct rtl8169_private *tp,
3477                                  void __iomem *ioaddr)
3478 {
3479         unsigned int dirty_tx, tx_left;
3480
3481         dirty_tx = tp->dirty_tx;
3482         smp_rmb();
3483         tx_left = tp->cur_tx - dirty_tx;
3484
3485         while (tx_left > 0) {
3486                 unsigned int entry = dirty_tx % NUM_TX_DESC;
3487                 struct ring_info *tx_skb = tp->tx_skb + entry;
3488                 u32 len = tx_skb->len;
3489                 u32 status;
3490
3491                 rmb();
3492                 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
3493                 if (status & DescOwn)
3494                         break;
3495
3496                 dev->stats.tx_bytes += len;
3497                 dev->stats.tx_packets++;
3498
3499                 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, tp->TxDescArray + entry);
3500
3501                 if (status & LastFrag) {
3502                         dev_kfree_skb(tx_skb->skb);
3503                         tx_skb->skb = NULL;
3504                 }
3505                 dirty_tx++;
3506                 tx_left--;
3507         }
3508
3509         if (tp->dirty_tx != dirty_tx) {
3510                 tp->dirty_tx = dirty_tx;
3511                 smp_wmb();
3512                 if (netif_queue_stopped(dev) &&
3513                     (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
3514                         netif_wake_queue(dev);
3515                 }
3516                 /*
3517                  * 8168 hack: TxPoll requests are lost when the Tx packets are
3518                  * too close. Let's kick an extra TxPoll request when a burst
3519                  * of start_xmit activity is detected (if it is not detected,
3520                  * it is slow enough). -- FR
3521                  */
3522                 smp_rmb();
3523                 if (tp->cur_tx != dirty_tx)
3524                         RTL_W8(TxPoll, NPQ);
3525         }
3526 }
3527
3528 static inline int rtl8169_fragmented_frame(u32 status)
3529 {
3530         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
3531 }
3532
3533 static inline void rtl8169_rx_csum(struct sk_buff *skb, struct RxDesc *desc)
3534 {
3535         u32 opts1 = le32_to_cpu(desc->opts1);
3536         u32 status = opts1 & RxProtoMask;
3537
3538         if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
3539             ((status == RxProtoUDP) && !(opts1 & UDPFail)) ||
3540             ((status == RxProtoIP) && !(opts1 & IPFail)))
3541                 skb->ip_summed = CHECKSUM_UNNECESSARY;
3542         else
3543                 skb->ip_summed = CHECKSUM_NONE;
3544 }
3545
3546 static inline bool rtl8169_try_rx_copy(struct sk_buff **sk_buff,
3547                                        struct rtl8169_private *tp, int pkt_size,
3548                                        dma_addr_t addr)
3549 {
3550         struct sk_buff *skb;
3551         bool done = false;
3552
3553         if (pkt_size >= rx_copybreak)
3554                 goto out;
3555
3556         skb = netdev_alloc_skb(tp->dev, pkt_size + NET_IP_ALIGN);
3557         if (!skb)
3558                 goto out;
3559
3560         pci_dma_sync_single_for_cpu(tp->pci_dev, addr, pkt_size,
3561                                     PCI_DMA_FROMDEVICE);
3562         skb_reserve(skb, NET_IP_ALIGN);
3563         skb_copy_from_linear_data(*sk_buff, skb->data, pkt_size);
3564         *sk_buff = skb;
3565         done = true;
3566 out:
3567         return done;
3568 }
3569
3570 static int rtl8169_rx_interrupt(struct net_device *dev,
3571                                 struct rtl8169_private *tp,
3572                                 void __iomem *ioaddr, u32 budget)
3573 {
3574         unsigned int cur_rx, rx_left;
3575         unsigned int delta, count;
3576
3577         cur_rx = tp->cur_rx;
3578         rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
3579         rx_left = min(rx_left, budget);
3580
3581         for (; rx_left > 0; rx_left--, cur_rx++) {
3582                 unsigned int entry = cur_rx % NUM_RX_DESC;
3583                 struct RxDesc *desc = tp->RxDescArray + entry;
3584                 u32 status;
3585
3586                 rmb();
3587                 status = le32_to_cpu(desc->opts1);
3588
3589                 if (status & DescOwn)
3590                         break;
3591                 if (unlikely(status & RxRES)) {
3592                         if (netif_msg_rx_err(tp)) {
3593                                 printk(KERN_INFO
3594                                        "%s: Rx ERROR. status = %08x\n",
3595                                        dev->name, status);
3596                         }
3597                         dev->stats.rx_errors++;
3598                         if (status & (RxRWT | RxRUNT))
3599                                 dev->stats.rx_length_errors++;
3600                         if (status & RxCRC)
3601                                 dev->stats.rx_crc_errors++;
3602                         if (status & RxFOVF) {
3603                                 rtl8169_schedule_work(dev, rtl8169_reset_task);
3604                                 dev->stats.rx_fifo_errors++;
3605                         }
3606                         rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
3607                 } else {
3608                         struct sk_buff *skb = tp->Rx_skbuff[entry];
3609                         dma_addr_t addr = le64_to_cpu(desc->addr);
3610                         int pkt_size = (status & 0x00001FFF) - 4;
3611                         struct pci_dev *pdev = tp->pci_dev;
3612
3613                         /*
3614                          * The driver does not support incoming fragmented
3615                          * frames. They are seen as a symptom of over-mtu
3616                          * sized frames.
3617                          */
3618                         if (unlikely(rtl8169_fragmented_frame(status))) {
3619                                 dev->stats.rx_dropped++;
3620                                 dev->stats.rx_length_errors++;
3621                                 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
3622                                 continue;
3623                         }
3624
3625                         rtl8169_rx_csum(skb, desc);
3626
3627                         if (rtl8169_try_rx_copy(&skb, tp, pkt_size, addr)) {
3628                                 pci_dma_sync_single_for_device(pdev, addr,
3629                                         pkt_size, PCI_DMA_FROMDEVICE);
3630                                 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
3631                         } else {
3632                                 pci_unmap_single(pdev, addr, tp->rx_buf_sz,
3633                                                  PCI_DMA_FROMDEVICE);
3634                                 tp->Rx_skbuff[entry] = NULL;
3635                         }
3636
3637                         skb_put(skb, pkt_size);
3638                         skb->protocol = eth_type_trans(skb, dev);
3639
3640                         if (rtl8169_rx_vlan_skb(tp, desc, skb) < 0)
3641                                 netif_receive_skb(skb);
3642
3643                         dev->stats.rx_bytes += pkt_size;
3644                         dev->stats.rx_packets++;
3645                 }
3646
3647                 /* Work around for AMD plateform. */
3648                 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
3649                     (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
3650                         desc->opts2 = 0;
3651                         cur_rx++;
3652                 }
3653         }
3654
3655         count = cur_rx - tp->cur_rx;
3656         tp->cur_rx = cur_rx;
3657
3658         delta = rtl8169_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx);
3659         if (!delta && count && netif_msg_intr(tp))
3660                 printk(KERN_INFO "%s: no Rx buffer allocated\n", dev->name);
3661         tp->dirty_rx += delta;
3662
3663         /*
3664          * FIXME: until there is periodic timer to try and refill the ring,
3665          * a temporary shortage may definitely kill the Rx process.
3666          * - disable the asic to try and avoid an overflow and kick it again
3667          *   after refill ?
3668          * - how do others driver handle this condition (Uh oh...).
3669          */
3670         if ((tp->dirty_rx + NUM_RX_DESC == tp->cur_rx) && netif_msg_intr(tp))
3671                 printk(KERN_EMERG "%s: Rx buffers exhausted\n", dev->name);
3672
3673         return count;
3674 }
3675
3676 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
3677 {
3678         struct net_device *dev = dev_instance;
3679         struct rtl8169_private *tp = netdev_priv(dev);
3680         void __iomem *ioaddr = tp->mmio_addr;
3681         int handled = 0;
3682         int status;
3683
3684         /* loop handling interrupts until we have no new ones or
3685          * we hit a invalid/hotplug case.
3686          */
3687         status = RTL_R16(IntrStatus);
3688         while (status && status != 0xffff) {
3689                 handled = 1;
3690
3691                 /* Handle all of the error cases first. These will reset
3692                  * the chip, so just exit the loop.
3693                  */
3694                 if (unlikely(!netif_running(dev))) {
3695                         rtl8169_asic_down(ioaddr);
3696                         break;
3697                 }
3698
3699                 /* Work around for rx fifo overflow */
3700                 if (unlikely(status & RxFIFOOver) &&
3701                 (tp->mac_version == RTL_GIGA_MAC_VER_11)) {
3702                         netif_stop_queue(dev);
3703                         rtl8169_tx_timeout(dev);
3704                         break;
3705                 }
3706
3707                 if (unlikely(status & SYSErr)) {
3708                         rtl8169_pcierr_interrupt(dev);
3709                         break;
3710                 }
3711
3712                 if (status & LinkChg)
3713                         rtl8169_check_link_status(dev, tp, ioaddr);
3714
3715                 /* We need to see the lastest version of tp->intr_mask to
3716                  * avoid ignoring an MSI interrupt and having to wait for
3717                  * another event which may never come.
3718                  */
3719                 smp_rmb();
3720                 if (status & tp->intr_mask & tp->napi_event) {
3721                         RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
3722                         tp->intr_mask = ~tp->napi_event;
3723
3724                         if (likely(napi_schedule_prep(&tp->napi)))
3725                                 __napi_schedule(&tp->napi);
3726                         else if (netif_msg_intr(tp)) {
3727                                 printk(KERN_INFO "%s: interrupt %04x in poll\n",
3728                                 dev->name, status);
3729                         }
3730                 }
3731
3732                 /* We only get a new MSI interrupt when all active irq
3733                  * sources on the chip have been acknowledged. So, ack
3734                  * everything we've seen and check if new sources have become
3735                  * active to avoid blocking all interrupts from the chip.
3736                  */
3737                 RTL_W16(IntrStatus,
3738                         (status & RxFIFOOver) ? (status | RxOverflow) : status);
3739                 status = RTL_R16(IntrStatus);
3740         }
3741
3742         return IRQ_RETVAL(handled);
3743 }
3744
3745 static int rtl8169_poll(struct napi_struct *napi, int budget)
3746 {
3747         struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
3748         struct net_device *dev = tp->dev;
3749         void __iomem *ioaddr = tp->mmio_addr;
3750         int work_done;
3751
3752         work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
3753         rtl8169_tx_interrupt(dev, tp, ioaddr);
3754
3755         if (work_done < budget) {
3756                 napi_complete(napi);
3757
3758                 /* We need for force the visibility of tp->intr_mask
3759                  * for other CPUs, as we can loose an MSI interrupt
3760                  * and potentially wait for a retransmit timeout if we don't.
3761                  * The posted write to IntrMask is safe, as it will
3762                  * eventually make it to the chip and we won't loose anything
3763                  * until it does.
3764                  */
3765                 tp->intr_mask = 0xffff;
3766                 smp_wmb();
3767                 RTL_W16(IntrMask, tp->intr_event);
3768         }
3769
3770         return work_done;
3771 }
3772
3773 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
3774 {
3775         struct rtl8169_private *tp = netdev_priv(dev);
3776
3777         if (tp->mac_version > RTL_GIGA_MAC_VER_06)
3778                 return;
3779
3780         dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
3781         RTL_W32(RxMissed, 0);
3782 }
3783
3784 static void rtl8169_down(struct net_device *dev)
3785 {
3786         struct rtl8169_private *tp = netdev_priv(dev);
3787         void __iomem *ioaddr = tp->mmio_addr;
3788         unsigned int intrmask;
3789
3790         rtl8169_delete_timer(dev);
3791
3792         netif_stop_queue(dev);
3793
3794         napi_disable(&tp->napi);
3795
3796 core_down:
3797         spin_lock_irq(&tp->lock);
3798
3799         rtl8169_asic_down(ioaddr);
3800
3801         rtl8169_rx_missed(dev, ioaddr);
3802
3803         spin_unlock_irq(&tp->lock);
3804
3805         synchronize_irq(dev->irq);
3806
3807         /* Give a racing hard_start_xmit a few cycles to complete. */
3808         synchronize_sched();  /* FIXME: should this be synchronize_irq()? */
3809
3810         /*
3811          * And now for the 50k$ question: are IRQ disabled or not ?
3812          *
3813          * Two paths lead here:
3814          * 1) dev->close
3815          *    -> netif_running() is available to sync the current code and the
3816          *       IRQ handler. See rtl8169_interrupt for details.
3817          * 2) dev->change_mtu
3818          *    -> rtl8169_poll can not be issued again and re-enable the
3819          *       interruptions. Let's simply issue the IRQ down sequence again.
3820          *
3821          * No loop if hotpluged or major error (0xffff).
3822          */
3823         intrmask = RTL_R16(IntrMask);
3824         if (intrmask && (intrmask != 0xffff))
3825                 goto core_down;
3826
3827         rtl8169_tx_clear(tp);
3828
3829         rtl8169_rx_clear(tp);
3830 }
3831
3832 static int rtl8169_close(struct net_device *dev)
3833 {
3834         struct rtl8169_private *tp = netdev_priv(dev);
3835         struct pci_dev *pdev = tp->pci_dev;
3836
3837         /* update counters before going down */
3838         rtl8169_update_counters(dev);
3839
3840         rtl8169_down(dev);
3841
3842         free_irq(dev->irq, dev);
3843
3844         pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
3845                             tp->RxPhyAddr);
3846         pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
3847                             tp->TxPhyAddr);
3848         tp->TxDescArray = NULL;
3849         tp->RxDescArray = NULL;
3850
3851         return 0;
3852 }
3853
3854 static void rtl_set_rx_mode(struct net_device *dev)
3855 {
3856         struct rtl8169_private *tp = netdev_priv(dev);
3857         void __iomem *ioaddr = tp->mmio_addr;
3858         unsigned long flags;
3859         u32 mc_filter[2];       /* Multicast hash filter */
3860         int rx_mode;
3861         u32 tmp = 0;
3862
3863         if (dev->flags & IFF_PROMISC) {
3864                 /* Unconditionally log net taps. */
3865                 if (netif_msg_link(tp)) {
3866                         printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n",
3867                                dev->name);
3868                 }
3869                 rx_mode =
3870                     AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
3871                     AcceptAllPhys;
3872                 mc_filter[1] = mc_filter[0] = 0xffffffff;
3873         } else if ((dev->mc_count > multicast_filter_limit)
3874                    || (dev->flags & IFF_ALLMULTI)) {
3875                 /* Too many to filter perfectly -- accept all multicasts. */
3876                 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
3877                 mc_filter[1] = mc_filter[0] = 0xffffffff;
3878         } else {
3879                 struct dev_mc_list *mclist;
3880                 unsigned int i;
3881
3882                 rx_mode = AcceptBroadcast | AcceptMyPhys;
3883                 mc_filter[1] = mc_filter[0] = 0;
3884                 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
3885                      i++, mclist = mclist->next) {
3886                         int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
3887                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
3888                         rx_mode |= AcceptMulticast;
3889                 }
3890         }
3891
3892         spin_lock_irqsave(&tp->lock, flags);
3893
3894         tmp = rtl8169_rx_config | rx_mode |
3895               (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
3896
3897         if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
3898                 u32 data = mc_filter[0];
3899
3900                 mc_filter[0] = swab32(mc_filter[1]);
3901                 mc_filter[1] = swab32(data);
3902         }
3903
3904         RTL_W32(MAR0 + 0, mc_filter[0]);
3905         RTL_W32(MAR0 + 4, mc_filter[1]);
3906
3907         RTL_W32(RxConfig, tmp);
3908
3909         spin_unlock_irqrestore(&tp->lock, flags);
3910 }
3911
3912 /**
3913  *  rtl8169_get_stats - Get rtl8169 read/write statistics
3914  *  @dev: The Ethernet Device to get statistics for
3915  *
3916  *  Get TX/RX statistics for rtl8169
3917  */
3918 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
3919 {
3920         struct rtl8169_private *tp = netdev_priv(dev);
3921         void __iomem *ioaddr = tp->mmio_addr;
3922         unsigned long flags;
3923
3924         if (netif_running(dev)) {
3925                 spin_lock_irqsave(&tp->lock, flags);
3926                 rtl8169_rx_missed(dev, ioaddr);
3927                 spin_unlock_irqrestore(&tp->lock, flags);
3928         }
3929
3930         return &dev->stats;
3931 }
3932
3933 static void rtl8169_net_suspend(struct net_device *dev)
3934 {
3935         if (!netif_running(dev))
3936                 return;
3937
3938         netif_device_detach(dev);
3939         netif_stop_queue(dev);
3940 }
3941
3942 #ifdef CONFIG_PM
3943
3944 static int rtl8169_suspend(struct device *device)
3945 {
3946         struct pci_dev *pdev = to_pci_dev(device);
3947         struct net_device *dev = pci_get_drvdata(pdev);
3948
3949         rtl8169_net_suspend(dev);
3950
3951         return 0;
3952 }
3953
3954 static int rtl8169_resume(struct device *device)
3955 {
3956         struct pci_dev *pdev = to_pci_dev(device);
3957         struct net_device *dev = pci_get_drvdata(pdev);
3958
3959         if (!netif_running(dev))
3960                 goto out;
3961
3962         netif_device_attach(dev);
3963
3964         rtl8169_schedule_work(dev, rtl8169_reset_task);
3965 out:
3966         return 0;
3967 }
3968
3969 static struct dev_pm_ops rtl8169_pm_ops = {
3970         .suspend = rtl8169_suspend,
3971         .resume = rtl8169_resume,
3972         .freeze = rtl8169_suspend,
3973         .thaw = rtl8169_resume,
3974         .poweroff = rtl8169_suspend,
3975         .restore = rtl8169_resume,
3976 };
3977
3978 #define RTL8169_PM_OPS  (&rtl8169_pm_ops)
3979
3980 #else /* !CONFIG_PM */
3981
3982 #define RTL8169_PM_OPS  NULL
3983
3984 #endif /* !CONFIG_PM */
3985
3986 static void rtl_shutdown(struct pci_dev *pdev)
3987 {
3988         struct net_device *dev = pci_get_drvdata(pdev);
3989         struct rtl8169_private *tp = netdev_priv(dev);
3990         void __iomem *ioaddr = tp->mmio_addr;
3991
3992         rtl8169_net_suspend(dev);
3993
3994         spin_lock_irq(&tp->lock);
3995
3996         rtl8169_asic_down(ioaddr);
3997
3998         spin_unlock_irq(&tp->lock);
3999
4000         if (system_state == SYSTEM_POWER_OFF) {
4001                 /* WoL fails with some 8168 when the receiver is disabled. */
4002                 if (tp->features & RTL_FEATURE_WOL) {
4003                         pci_clear_master(pdev);
4004
4005                         RTL_W8(ChipCmd, CmdRxEnb);
4006                         /* PCI commit */
4007                         RTL_R8(ChipCmd);
4008                 }
4009
4010                 pci_wake_from_d3(pdev, true);
4011                 pci_set_power_state(pdev, PCI_D3hot);
4012         }
4013 }
4014
4015 static struct pci_driver rtl8169_pci_driver = {
4016         .name           = MODULENAME,
4017         .id_table       = rtl8169_pci_tbl,
4018         .probe          = rtl8169_init_one,
4019         .remove         = __devexit_p(rtl8169_remove_one),
4020         .shutdown       = rtl_shutdown,
4021         .driver.pm      = RTL8169_PM_OPS,
4022 };
4023
4024 static int __init rtl8169_init_module(void)
4025 {
4026         return pci_register_driver(&rtl8169_pci_driver);
4027 }
4028
4029 static void __exit rtl8169_cleanup_module(void)
4030 {
4031         pci_unregister_driver(&rtl8169_pci_driver);
4032 }
4033
4034 module_init(rtl8169_init_module);
4035 module_exit(rtl8169_cleanup_module);