SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/net/r8169.c

   1 /*
   2  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
   3  *
   4  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
   5  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
   6  * Copyright (c) a lot of people too. Please respect their work.
   7  *
   8  * See MAINTAINERS file for support contact information.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/moduleparam.h>
  13 #include <linux/pci.h>
  14 #include <linux/netdevice.h>
  15 #include <linux/etherdevice.h>
  16 #include <linux/delay.h>
  17 #include <linux/ethtool.h>
  18 #include <linux/mii.h>
  19 #include <linux/if_vlan.h>
  20 #include <linux/crc32.h>
  21 #include <linux/in.h>
  22 #include <linux/ip.h>
  23 #include <linux/tcp.h>
  24 #include <linux/init.h>
  25 #include <linux/dma-mapping.h>
  26
  27 #include <asm/system.h>
  28 #include <asm/io.h>
  29 #include <asm/irq.h>
  30
  31 #ifdef CONFIG_R8169_NAPI
  32 #define NAPI_SUFFIX     "-NAPI"
  33 #else
  34 #define NAPI_SUFFIX     ""
  35 #endif
  36
  37 #define RTL8169_VERSION "2.2LK" NAPI_SUFFIX
  38 #define MODULENAME "r8169"
  39 #define PFX MODULENAME ": "
  40
  41 #ifdef RTL8169_DEBUG
  42 #define assert(expr) \
  43         if (!(expr)) {                                  \
  44                 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
  45                 #expr,__FILE__,__FUNCTION__,__LINE__);          \
  46         }
  47 #define dprintk(fmt, args...) \
  48         do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
  49 #else
  50 #define assert(expr) do {} while (0)
  51 #define dprintk(fmt, args...)   do {} while (0)
  52 #endif /* RTL8169_DEBUG */
  53
  54 #define R8169_MSG_DEFAULT \
  55         (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
  56
  57 #define TX_BUFFS_AVAIL(tp) \
  58         (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
  59
  60 #ifdef CONFIG_R8169_NAPI
  61 #define rtl8169_rx_skb                  netif_receive_skb
  62 #define rtl8169_rx_hwaccel_skb          vlan_hwaccel_receive_skb
  63 #define rtl8169_rx_quota(count, quota)  min(count, quota)
  64 #else
  65 #define rtl8169_rx_skb                  netif_rx
  66 #define rtl8169_rx_hwaccel_skb          vlan_hwaccel_rx
  67 #define rtl8169_rx_quota(count, quota)  count
  68 #endif
  69
  70 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
  71 static const int max_interrupt_work = 20;
  72
  73 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  74    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
  75 static const int multicast_filter_limit = 32;
  76
  77 /* MAC address length */
  78 #define MAC_ADDR_LEN    6
  79
  80 #define RX_FIFO_THRESH  7       /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
  81 #define RX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
  82 #define TX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
  83 #define EarlyTxThld     0x3F    /* 0x3F means NO early transmit */
  84 #define RxPacketMaxSize 0x3FE8  /* 16K - 1 - ETH_HLEN - VLAN - CRC... */
  85 #define SafeMtu         0x1c20  /* ... actually life sucks beyond ~7k */
  86 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
  87
  88 #define R8169_REGS_SIZE         256
  89 #define R8169_NAPI_WEIGHT       64
  90 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
  91 #define NUM_RX_DESC     256     /* Number of Rx descriptor registers */
  92 #define RX_BUF_SIZE     1536    /* Rx Buffer size */
  93 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
  94 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
  95
  96 #define RTL8169_TX_TIMEOUT      (6*HZ)
  97 #define RTL8169_PHY_TIMEOUT     (10*HZ)
  98
  99 /* write/read MMIO register */
 100 #define RTL_W8(reg, val8)       writeb ((val8), ioaddr + (reg))
 101 #define RTL_W16(reg, val16)     writew ((val16), ioaddr + (reg))
 102 #define RTL_W32(reg, val32)     writel ((val32), ioaddr + (reg))
 103 #define RTL_R8(reg)             readb (ioaddr + (reg))
 104 #define RTL_R16(reg)            readw (ioaddr + (reg))
 105 #define RTL_R32(reg)            ((unsigned long) readl (ioaddr + (reg)))
 106
 107 enum mac_version {
 108         RTL_GIGA_MAC_VER_01 = 0x01, // 8169
 109         RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
 110         RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
 111         RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
 112         RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
 113         RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
 114         RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
 115         RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be 8168Bf
 116         RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb 8101Ec
 117         RTL_GIGA_MAC_VER_14 = 0x0e, // 8101
 118         RTL_GIGA_MAC_VER_15 = 0x0f  // 8101
 119 };
 120
 121 enum phy_version {
 122         RTL_GIGA_PHY_VER_C = 0x03, /* PHY Reg 0x03 bit0-3 == 0x0000 */
 123         RTL_GIGA_PHY_VER_D = 0x04, /* PHY Reg 0x03 bit0-3 == 0x0000 */
 124         RTL_GIGA_PHY_VER_E = 0x05, /* PHY Reg 0x03 bit0-3 == 0x0000 */
 125         RTL_GIGA_PHY_VER_F = 0x06, /* PHY Reg 0x03 bit0-3 == 0x0001 */
 126         RTL_GIGA_PHY_VER_G = 0x07, /* PHY Reg 0x03 bit0-3 == 0x0002 */
 127         RTL_GIGA_PHY_VER_H = 0x08, /* PHY Reg 0x03 bit0-3 == 0x0003 */
 128 };
 129
 130 #define _R(NAME,MAC,MASK) \
 131         { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
 132
 133 static const struct {
 134         const char *name;
 135         u8 mac_version;
 136         u32 RxConfigMask;       /* Clears the bits supported by this chip */
 137 } rtl_chip_info[] = {
 138         _R("RTL8169",           RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
 139         _R("RTL8169s",          RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
 140         _R("RTL8110s",          RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
 141         _R("RTL8169sb/8110sb",  RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
 142         _R("RTL8169sc/8110sc",  RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
 143         _R("RTL8169sc/8110sc",  RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
 144         _R("RTL8168b/8111b",    RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
 145         _R("RTL8168b/8111b",    RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
 146         _R("RTL8101e",          RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
 147         _R("RTL8100e",          RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
 148         _R("RTL8100e",          RTL_GIGA_MAC_VER_15, 0xff7e1880)  // PCI-E 8139
 149 };
 150 #undef _R
 151
 152 enum cfg_version {
 153         RTL_CFG_0 = 0x00,
 154         RTL_CFG_1,
 155         RTL_CFG_2
 156 };
 157
 158 static void rtl_hw_start_8169(struct net_device *);
 159 static void rtl_hw_start_8168(struct net_device *);
 160 static void rtl_hw_start_8101(struct net_device *);
 161
 162 static struct pci_device_id rtl8169_pci_tbl[] = {
 163         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8129), 0, 0, RTL_CFG_0 },
 164         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8136), 0, 0, RTL_CFG_2 },
 165         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8167), 0, 0, RTL_CFG_0 },
 166         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8168), 0, 0, RTL_CFG_1 },
 167         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8169), 0, 0, RTL_CFG_0 },
 168         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4300), 0, 0, RTL_CFG_0 },
 169         { PCI_DEVICE(0x1259,                    0xc107), 0, 0, RTL_CFG_0 },
 170         { PCI_DEVICE(0x16ec,                    0x0116), 0, 0, RTL_CFG_0 },
 171         { PCI_VENDOR_ID_LINKSYS,                0x1032,
 172                 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
 173         {0,},
 174 };
 175
 176 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
 177
 178 static int rx_copybreak = 200;
 179 static int use_dac;
 180 static struct {
 181         u32 msg_enable;
 182 } debug = { -1 };
 183
 184 enum rtl_registers {
 185         MAC0            = 0,    /* Ethernet hardware address. */
 186         MAC4            = 4,
 187         MAR0            = 8,    /* Multicast filter. */
 188         CounterAddrLow          = 0x10,
 189         CounterAddrHigh         = 0x14,
 190         TxDescStartAddrLow      = 0x20,
 191         TxDescStartAddrHigh     = 0x24,
 192         TxHDescStartAddrLow     = 0x28,
 193         TxHDescStartAddrHigh    = 0x2c,
 194         FLASH           = 0x30,
 195         ERSR            = 0x36,
 196         ChipCmd         = 0x37,
 197         TxPoll          = 0x38,
 198         IntrMask        = 0x3c,
 199         IntrStatus      = 0x3e,
 200         TxConfig        = 0x40,
 201         RxConfig        = 0x44,
 202         RxMissed        = 0x4c,
 203         Cfg9346         = 0x50,
 204         Config0         = 0x51,
 205         Config1         = 0x52,
 206         Config2         = 0x53,
 207         Config3         = 0x54,
 208         Config4         = 0x55,
 209         Config5         = 0x56,
 210         MultiIntr       = 0x5c,
 211         PHYAR           = 0x60,
 212         TBICSR          = 0x64,
 213         TBI_ANAR        = 0x68,
 214         TBI_LPAR        = 0x6a,
 215         PHYstatus       = 0x6c,
 216         RxMaxSize       = 0xda,
 217         CPlusCmd        = 0xe0,
 218         IntrMitigate    = 0xe2,
 219         RxDescAddrLow   = 0xe4,
 220         RxDescAddrHigh  = 0xe8,
 221         EarlyTxThres    = 0xec,
 222         FuncEvent       = 0xf0,
 223         FuncEventMask   = 0xf4,
 224         FuncPresetState = 0xf8,
 225         FuncForceEvent  = 0xfc,
 226 };
 227
 228 enum rtl_register_content {
 229         /* InterruptStatusBits */
 230         SYSErr          = 0x8000,
 231         PCSTimeout      = 0x4000,
 232         SWInt           = 0x0100,
 233         TxDescUnavail   = 0x0080,
 234         RxFIFOOver      = 0x0040,
 235         LinkChg         = 0x0020,
 236         RxOverflow      = 0x0010,
 237         TxErr           = 0x0008,
 238         TxOK            = 0x0004,
 239         RxErr           = 0x0002,
 240         RxOK            = 0x0001,
 241
 242         /* RxStatusDesc */
 243         RxFOVF  = (1 << 23),
 244         RxRWT   = (1 << 22),
 245         RxRES   = (1 << 21),
 246         RxRUNT  = (1 << 20),
 247         RxCRC   = (1 << 19),
 248
 249         /* ChipCmdBits */
 250         CmdReset        = 0x10,
 251         CmdRxEnb        = 0x08,
 252         CmdTxEnb        = 0x04,
 253         RxBufEmpty      = 0x01,
 254
 255         /* TXPoll register p.5 */
 256         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
 257         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
 258         FSWInt          = 0x01,         /* Forced software interrupt */
 259
 260         /* Cfg9346Bits */
 261         Cfg9346_Lock    = 0x00,
 262         Cfg9346_Unlock  = 0xc0,
 263
 264         /* rx_mode_bits */
 265         AcceptErr       = 0x20,
 266         AcceptRunt      = 0x10,
 267         AcceptBroadcast = 0x08,
 268         AcceptMulticast = 0x04,
 269         AcceptMyPhys    = 0x02,
 270         AcceptAllPhys   = 0x01,
 271
 272         /* RxConfigBits */
 273         RxCfgFIFOShift  = 13,
 274         RxCfgDMAShift   =  8,
 275
 276         /* TxConfigBits */
 277         TxInterFrameGapShift = 24,
 278         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
 279
 280         /* Config1 register p.24 */
 281         PMEnable        = (1 << 0),     /* Power Management Enable */
 282
 283         /* Config2 register p. 25 */
 284         PCI_Clock_66MHz = 0x01,
 285         PCI_Clock_33MHz = 0x00,
 286
 287         /* Config3 register p.25 */
 288         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
 289         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
 290
 291         /* Config5 register p.27 */
 292         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
 293         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
 294         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
 295         LanWake         = (1 << 1),     /* LanWake enable/disable */
 296         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
 297
 298         /* TBICSR p.28 */
 299         TBIReset        = 0x80000000,
 300         TBILoopback     = 0x40000000,
 301         TBINwEnable     = 0x20000000,
 302         TBINwRestart    = 0x10000000,
 303         TBILinkOk       = 0x02000000,
 304         TBINwComplete   = 0x01000000,
 305
 306         /* CPlusCmd p.31 */
 307         PktCntrDisable  = (1 << 7),     // 8168
 308         RxVlan          = (1 << 6),
 309         RxChkSum        = (1 << 5),
 310         PCIDAC          = (1 << 4),
 311         PCIMulRW        = (1 << 3),
 312         INTT_0          = 0x0000,       // 8168
 313         INTT_1          = 0x0001,       // 8168
 314         INTT_2          = 0x0002,       // 8168
 315         INTT_3          = 0x0003,       // 8168
 316
 317         /* rtl8169_PHYstatus */
 318         TBI_Enable      = 0x80,
 319         TxFlowCtrl      = 0x40,
 320         RxFlowCtrl      = 0x20,
 321         _1000bpsF       = 0x10,
 322         _100bps         = 0x08,
 323         _10bps          = 0x04,
 324         LinkStatus      = 0x02,
 325         FullDup         = 0x01,
 326
 327         /* _TBICSRBit */
 328         TBILinkOK       = 0x02000000,
 329
 330         /* DumpCounterCommand */
 331         CounterDump     = 0x8,
 332 };
 333
 334 enum desc_status_bit {
 335         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
 336         RingEnd         = (1 << 30), /* End of descriptor ring */
 337         FirstFrag       = (1 << 29), /* First segment of a packet */
 338         LastFrag        = (1 << 28), /* Final segment of a packet */
 339
 340         /* Tx private */
 341         LargeSend       = (1 << 27), /* TCP Large Send Offload (TSO) */
 342         MSSShift        = 16,        /* MSS value position */
 343         MSSMask         = 0xfff,     /* MSS value + LargeSend bit: 12 bits */
 344         IPCS            = (1 << 18), /* Calculate IP checksum */
 345         UDPCS           = (1 << 17), /* Calculate UDP/IP checksum */
 346         TCPCS           = (1 << 16), /* Calculate TCP/IP checksum */
 347         TxVlanTag       = (1 << 17), /* Add VLAN tag */
 348
 349         /* Rx private */
 350         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
 351         PID0            = (1 << 17), /* Protocol ID bit 2/2 */
 352
 353 #define RxProtoUDP      (PID1)
 354 #define RxProtoTCP      (PID0)
 355 #define RxProtoIP       (PID1 | PID0)
 356 #define RxProtoMask     RxProtoIP
 357
 358         IPFail          = (1 << 16), /* IP checksum failed */
 359         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
 360         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
 361         RxVlanTag       = (1 << 16), /* VLAN tag available */
 362 };
 363
 364 #define RsvdMask        0x3fffc000
 365
 366 struct TxDesc {
 367         __le32 opts1;
 368         __le32 opts2;
 369         __le64 addr;
 370 };
 371
 372 struct RxDesc {
 373         __le32 opts1;
 374         __le32 opts2;
 375         __le64 addr;
 376 };
 377
 378 struct ring_info {
 379         struct sk_buff  *skb;
 380         u32             len;
 381         u8              __pad[sizeof(void *) - sizeof(u32)];
 382 };
 383
 384 struct rtl8169_private {
 385         void __iomem *mmio_addr;        /* memory map physical address */
 386         struct pci_dev *pci_dev;        /* Index of PCI device */
 387         struct net_device *dev;
 388         struct napi_struct napi;
 389         struct net_device_stats stats;  /* statistics of net device */
 390         spinlock_t lock;                /* spin lock flag */
 391         u32 msg_enable;
 392         int chipset;
 393         int mac_version;
 394         int phy_version;
 395         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
 396         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
 397         u32 dirty_rx;
 398         u32 dirty_tx;
 399         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
 400         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
 401         dma_addr_t TxPhyAddr;
 402         dma_addr_t RxPhyAddr;
 403         struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */
 404         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
 405         unsigned align;
 406         unsigned rx_buf_sz;
 407         struct timer_list timer;
 408         u16 cp_cmd;
 409         u16 intr_event;
 410         u16 napi_event;
 411         u16 intr_mask;
 412         int phy_auto_nego_reg;
 413         int phy_1000_ctrl_reg;
 414 #ifdef CONFIG_R8169_VLAN
 415         struct vlan_group *vlgrp;
 416 #endif
 417         int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
 418         void (*get_settings)(struct net_device *, struct ethtool_cmd *);
 419         void (*phy_reset_enable)(void __iomem *);
 420         void (*hw_start)(struct net_device *);
 421         unsigned int (*phy_reset_pending)(void __iomem *);
 422         unsigned int (*link_ok)(void __iomem *);
 423         struct delayed_work task;
 424         unsigned wol_enabled : 1;
 425 };
 426
 427 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
 428 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
 429 module_param(rx_copybreak, int, 0);
 430 MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
 431 module_param(use_dac, int, 0);
 432 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
 433 module_param_named(debug, debug.msg_enable, int, 0);
 434 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
 435 MODULE_LICENSE("GPL");
 436 MODULE_VERSION(RTL8169_VERSION);
 437
 438 static int rtl8169_open(struct net_device *dev);
 439 static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev);
 440 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
 441 static int rtl8169_init_ring(struct net_device *dev);
 442 static void rtl_hw_start(struct net_device *dev);
 443 static int rtl8169_close(struct net_device *dev);
 444 static void rtl_set_rx_mode(struct net_device *dev);
 445 static void rtl8169_tx_timeout(struct net_device *dev);
 446 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
 447 static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
 448                                 void __iomem *, u32 budget);
 449 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
 450 static void rtl8169_down(struct net_device *dev);
 451 static void rtl8169_rx_clear(struct rtl8169_private *tp);
 452
 453 #ifdef CONFIG_R8169_NAPI
 454 static int rtl8169_poll(struct napi_struct *napi, int budget);
 455 #endif
 456
 457 static const unsigned int rtl8169_rx_config =
 458         (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
 459
 460 static void mdio_write(void __iomem *ioaddr, int reg_addr, int value)
 461 {
 462         int i;
 463
 464         RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0xFF) << 16 | value);
 465
 466         for (i = 20; i > 0; i--) {
 467                 /*
 468                  * Check if the RTL8169 has completed writing to the specified
 469                  * MII register.
 470                  */
 471                 if (!(RTL_R32(PHYAR) & 0x80000000))
 472                         break;
 473                 udelay(25);
 474         }
 475 }
 476
 477 static int mdio_read(void __iomem *ioaddr, int reg_addr)
 478 {
 479         int i, value = -1;
 480
 481         RTL_W32(PHYAR, 0x0 | (reg_addr & 0xFF) << 16);
 482
 483         for (i = 20; i > 0; i--) {
 484                 /*
 485                  * Check if the RTL8169 has completed retrieving data from
 486                  * the specified MII register.
 487                  */
 488                 if (RTL_R32(PHYAR) & 0x80000000) {
 489                         value = (int) (RTL_R32(PHYAR) & 0xFFFF);
 490                         break;
 491                 }
 492                 udelay(25);
 493         }
 494         return value;
 495 }
 496
 497 static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
 498 {
 499         RTL_W16(IntrMask, 0x0000);
 500
 501         RTL_W16(IntrStatus, 0xffff);
 502 }
 503
 504 static void rtl8169_asic_down(void __iomem *ioaddr)
 505 {
 506         RTL_W8(ChipCmd, 0x00);
 507         rtl8169_irq_mask_and_ack(ioaddr);
 508         RTL_R16(CPlusCmd);
 509 }
 510
 511 static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr)
 512 {
 513         return RTL_R32(TBICSR) & TBIReset;
 514 }
 515
 516 static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr)
 517 {
 518         return mdio_read(ioaddr, MII_BMCR) & BMCR_RESET;
 519 }
 520
 521 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
 522 {
 523         return RTL_R32(TBICSR) & TBILinkOk;
 524 }
 525
 526 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
 527 {
 528         return RTL_R8(PHYstatus) & LinkStatus;
 529 }
 530
 531 static void rtl8169_tbi_reset_enable(void __iomem *ioaddr)
 532 {
 533         RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
 534 }
 535
 536 static void rtl8169_xmii_reset_enable(void __iomem *ioaddr)
 537 {
 538         unsigned int val;
 539
 540         val = mdio_read(ioaddr, MII_BMCR) | BMCR_RESET;
 541         mdio_write(ioaddr, MII_BMCR, val & 0xffff);
 542 }
 543
 544 static void rtl8169_check_link_status(struct net_device *dev,
 545                                       struct rtl8169_private *tp,
 546                                       void __iomem *ioaddr)
 547 {
 548         unsigned long flags;
 549
 550         spin_lock_irqsave(&tp->lock, flags);
 551         if (tp->link_ok(ioaddr)) {
 552                 netif_carrier_on(dev);
 553                 if (netif_msg_ifup(tp))
 554                         printk(KERN_INFO PFX "%s: link up\n", dev->name);
 555         } else {
 556                 if (netif_msg_ifdown(tp))
 557                         printk(KERN_INFO PFX "%s: link down\n", dev->name);
 558                 netif_carrier_off(dev);
 559         }
 560         spin_unlock_irqrestore(&tp->lock, flags);
 561 }
 562
 563 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
 564 {
 565         struct rtl8169_private *tp = netdev_priv(dev);
 566         void __iomem *ioaddr = tp->mmio_addr;
 567         u8 options;
 568
 569         wol->wolopts = 0;
 570
 571 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
 572         wol->supported = WAKE_ANY;
 573
 574         spin_lock_irq(&tp->lock);
 575
 576         options = RTL_R8(Config1);
 577         if (!(options & PMEnable))
 578                 goto out_unlock;
 579
 580         options = RTL_R8(Config3);
 581         if (options & LinkUp)
 582                 wol->wolopts |= WAKE_PHY;
 583         if (options & MagicPacket)
 584                 wol->wolopts |= WAKE_MAGIC;
 585
 586         options = RTL_R8(Config5);
 587         if (options & UWF)
 588                 wol->wolopts |= WAKE_UCAST;
 589         if (options & BWF)
 590                 wol->wolopts |= WAKE_BCAST;
 591         if (options & MWF)
 592                 wol->wolopts |= WAKE_MCAST;
 593
 594 out_unlock:
 595         spin_unlock_irq(&tp->lock);
 596 }
 597
 598 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
 599 {
 600         struct rtl8169_private *tp = netdev_priv(dev);
 601         void __iomem *ioaddr = tp->mmio_addr;
 602         unsigned int i;
 603         static struct {
 604                 u32 opt;
 605                 u16 reg;
 606                 u8  mask;
 607         } cfg[] = {
 608                 { WAKE_ANY,   Config1, PMEnable },
 609                 { WAKE_PHY,   Config3, LinkUp },
 610                 { WAKE_MAGIC, Config3, MagicPacket },
 611                 { WAKE_UCAST, Config5, UWF },
 612                 { WAKE_BCAST, Config5, BWF },
 613                 { WAKE_MCAST, Config5, MWF },
 614                 { WAKE_ANY,   Config5, LanWake }
 615         };
 616
 617         spin_lock_irq(&tp->lock);
 618
 619         RTL_W8(Cfg9346, Cfg9346_Unlock);
 620
 621         for (i = 0; i < ARRAY_SIZE(cfg); i++) {
 622                 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
 623                 if (wol->wolopts & cfg[i].opt)
 624                         options |= cfg[i].mask;
 625                 RTL_W8(cfg[i].reg, options);
 626         }
 627
 628         RTL_W8(Cfg9346, Cfg9346_Lock);
 629
 630         tp->wol_enabled = (wol->wolopts) ? 1 : 0;
 631
 632         spin_unlock_irq(&tp->lock);
 633
 634         return 0;
 635 }
 636
 637 static void rtl8169_get_drvinfo(struct net_device *dev,
 638                                 struct ethtool_drvinfo *info)
 639 {
 640         struct rtl8169_private *tp = netdev_priv(dev);
 641
 642         strcpy(info->driver, MODULENAME);
 643         strcpy(info->version, RTL8169_VERSION);
 644         strcpy(info->bus_info, pci_name(tp->pci_dev));
 645 }
 646
 647 static int rtl8169_get_regs_len(struct net_device *dev)
 648 {
 649         return R8169_REGS_SIZE;
 650 }
 651
 652 static int rtl8169_set_speed_tbi(struct net_device *dev,
 653                                  u8 autoneg, u16 speed, u8 duplex)
 654 {
 655         struct rtl8169_private *tp = netdev_priv(dev);
 656         void __iomem *ioaddr = tp->mmio_addr;
 657         int ret = 0;
 658         u32 reg;
 659
 660         reg = RTL_R32(TBICSR);
 661         if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
 662             (duplex == DUPLEX_FULL)) {
 663                 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
 664         } else if (autoneg == AUTONEG_ENABLE)
 665                 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
 666         else {
 667                 if (netif_msg_link(tp)) {
 668                         printk(KERN_WARNING "%s: "
 669                                "incorrect speed setting refused in TBI mode\n",
 670                                dev->name);
 671                 }
 672                 ret = -EOPNOTSUPP;
 673         }
 674
 675         return ret;
 676 }
 677
 678 static int rtl8169_set_speed_xmii(struct net_device *dev,
 679                                   u8 autoneg, u16 speed, u8 duplex)
 680 {
 681         struct rtl8169_private *tp = netdev_priv(dev);
 682         void __iomem *ioaddr = tp->mmio_addr;
 683         int auto_nego, giga_ctrl;
 684
 685         auto_nego = mdio_read(ioaddr, MII_ADVERTISE);
 686         auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
 687                        ADVERTISE_100HALF | ADVERTISE_100FULL);
 688         giga_ctrl = mdio_read(ioaddr, MII_CTRL1000);
 689         giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
 690
 691         if (autoneg == AUTONEG_ENABLE) {
 692                 auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
 693                               ADVERTISE_100HALF | ADVERTISE_100FULL);
 694                 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
 695         } else {
 696                 if (speed == SPEED_10)
 697                         auto_nego |= ADVERTISE_10HALF | ADVERTISE_10FULL;
 698                 else if (speed == SPEED_100)
 699                         auto_nego |= ADVERTISE_100HALF | ADVERTISE_100FULL;
 700                 else if (speed == SPEED_1000)
 701                         giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
 702
 703                 if (duplex == DUPLEX_HALF)
 704                         auto_nego &= ~(ADVERTISE_10FULL | ADVERTISE_100FULL);
 705
 706                 if (duplex == DUPLEX_FULL)
 707                         auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_100HALF);
 708
 709                 /* This tweak comes straight from Realtek's driver. */
 710                 if ((speed == SPEED_100) && (duplex == DUPLEX_HALF) &&
 711                     (tp->mac_version == RTL_GIGA_MAC_VER_13)) {
 712                         auto_nego = ADVERTISE_100HALF | ADVERTISE_CSMA;
 713                 }
 714         }
 715
 716         /* The 8100e/8101e do Fast Ethernet only. */
 717         if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
 718             (tp->mac_version == RTL_GIGA_MAC_VER_14) ||
 719             (tp->mac_version == RTL_GIGA_MAC_VER_15)) {
 720                 if ((giga_ctrl & (ADVERTISE_1000FULL | ADVERTISE_1000HALF)) &&
 721                     netif_msg_link(tp)) {
 722                         printk(KERN_INFO "%s: PHY does not support 1000Mbps.\n",
 723                                dev->name);
 724                 }
 725                 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
 726         }
 727
 728         auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
 729
 730         if (tp->mac_version == RTL_GIGA_MAC_VER_12) {
 731                 /* Vendor specific (0x1f) and reserved (0x0e) MII registers. */
 732                 mdio_write(ioaddr, 0x1f, 0x0000);
 733                 mdio_write(ioaddr, 0x0e, 0x0000);
 734         }
 735
 736         tp->phy_auto_nego_reg = auto_nego;
 737         tp->phy_1000_ctrl_reg = giga_ctrl;
 738
 739         mdio_write(ioaddr, MII_ADVERTISE, auto_nego);
 740         mdio_write(ioaddr, MII_CTRL1000, giga_ctrl);
 741         mdio_write(ioaddr, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART);
 742         return 0;
 743 }
 744
 745 static int rtl8169_set_speed(struct net_device *dev,
 746                              u8 autoneg, u16 speed, u8 duplex)
 747 {
 748         struct rtl8169_private *tp = netdev_priv(dev);
 749         int ret;
 750
 751         ret = tp->set_speed(dev, autoneg, speed, duplex);
 752
 753         if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
 754                 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
 755
 756         return ret;
 757 }
 758
 759 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 760 {
 761         struct rtl8169_private *tp = netdev_priv(dev);
 762         unsigned long flags;
 763         int ret;
 764
 765         spin_lock_irqsave(&tp->lock, flags);
 766         ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
 767         spin_unlock_irqrestore(&tp->lock, flags);
 768
 769         return ret;
 770 }
 771
 772 static u32 rtl8169_get_rx_csum(struct net_device *dev)
 773 {
 774         struct rtl8169_private *tp = netdev_priv(dev);
 775
 776         return tp->cp_cmd & RxChkSum;
 777 }
 778
 779 static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
 780 {
 781         struct rtl8169_private *tp = netdev_priv(dev);
 782         void __iomem *ioaddr = tp->mmio_addr;
 783         unsigned long flags;
 784
 785         spin_lock_irqsave(&tp->lock, flags);
 786
 787         if (data)
 788                 tp->cp_cmd |= RxChkSum;
 789         else
 790                 tp->cp_cmd &= ~RxChkSum;
 791
 792         RTL_W16(CPlusCmd, tp->cp_cmd);
 793         RTL_R16(CPlusCmd);
 794
 795         spin_unlock_irqrestore(&tp->lock, flags);
 796
 797         return 0;
 798 }
 799
 800 #ifdef CONFIG_R8169_VLAN
 801
 802 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
 803                                       struct sk_buff *skb)
 804 {
 805         return (tp->vlgrp && vlan_tx_tag_present(skb)) ?
 806                 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
 807 }
 808
 809 static void rtl8169_vlan_rx_register(struct net_device *dev,
 810                                      struct vlan_group *grp)
 811 {
 812         struct rtl8169_private *tp = netdev_priv(dev);
 813         void __iomem *ioaddr = tp->mmio_addr;
 814         unsigned long flags;
 815
 816         spin_lock_irqsave(&tp->lock, flags);
 817         tp->vlgrp = grp;
 818         if (tp->vlgrp)
 819                 tp->cp_cmd |= RxVlan;
 820         else
 821                 tp->cp_cmd &= ~RxVlan;
 822         RTL_W16(CPlusCmd, tp->cp_cmd);
 823         RTL_R16(CPlusCmd);
 824         spin_unlock_irqrestore(&tp->lock, flags);
 825 }
 826
 827 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
 828                                struct sk_buff *skb)
 829 {
 830         u32 opts2 = le32_to_cpu(desc->opts2);
 831         int ret;
 832
 833         if (tp->vlgrp && (opts2 & RxVlanTag)) {
 834                 rtl8169_rx_hwaccel_skb(skb, tp->vlgrp, swab16(opts2 & 0xffff));
 835                 ret = 0;
 836         } else
 837                 ret = -1;
 838         desc->opts2 = 0;
 839         return ret;
 840 }
 841
 842 #else /* !CONFIG_R8169_VLAN */
 843
 844 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
 845                                       struct sk_buff *skb)
 846 {
 847         return 0;
 848 }
 849
 850 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
 851                                struct sk_buff *skb)
 852 {
 853         return -1;
 854 }
 855
 856 #endif
 857
 858 static void rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
 859 {
 860         struct rtl8169_private *tp = netdev_priv(dev);
 861         void __iomem *ioaddr = tp->mmio_addr;
 862         u32 status;
 863
 864         cmd->supported =
 865                 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
 866         cmd->port = PORT_FIBRE;
 867         cmd->transceiver = XCVR_INTERNAL;
 868
 869         status = RTL_R32(TBICSR);
 870         cmd->advertising = (status & TBINwEnable) ?  ADVERTISED_Autoneg : 0;
 871         cmd->autoneg = !!(status & TBINwEnable);
 872
 873         cmd->speed = SPEED_1000;
 874         cmd->duplex = DUPLEX_FULL; /* Always set */
 875 }
 876
 877 static void rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
 878 {
 879         struct rtl8169_private *tp = netdev_priv(dev);
 880         void __iomem *ioaddr = tp->mmio_addr;
 881         u8 status;
 882
 883         cmd->supported = SUPPORTED_10baseT_Half |
 884                          SUPPORTED_10baseT_Full |
 885                          SUPPORTED_100baseT_Half |
 886                          SUPPORTED_100baseT_Full |
 887                          SUPPORTED_1000baseT_Full |
 888                          SUPPORTED_Autoneg |
 889                          SUPPORTED_TP;
 890
 891         cmd->autoneg = 1;
 892         cmd->advertising = ADVERTISED_TP | ADVERTISED_Autoneg;
 893
 894         if (tp->phy_auto_nego_reg & ADVERTISE_10HALF)
 895                 cmd->advertising |= ADVERTISED_10baseT_Half;
 896         if (tp->phy_auto_nego_reg & ADVERTISE_10FULL)
 897                 cmd->advertising |= ADVERTISED_10baseT_Full;
 898         if (tp->phy_auto_nego_reg & ADVERTISE_100HALF)
 899                 cmd->advertising |= ADVERTISED_100baseT_Half;
 900         if (tp->phy_auto_nego_reg & ADVERTISE_100FULL)
 901                 cmd->advertising |= ADVERTISED_100baseT_Full;
 902         if (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL)
 903                 cmd->advertising |= ADVERTISED_1000baseT_Full;
 904
 905         status = RTL_R8(PHYstatus);
 906
 907         if (status & _1000bpsF)
 908                 cmd->speed = SPEED_1000;
 909         else if (status & _100bps)
 910                 cmd->speed = SPEED_100;
 911         else if (status & _10bps)
 912                 cmd->speed = SPEED_10;
 913
 914         if (status & TxFlowCtrl)
 915                 cmd->advertising |= ADVERTISED_Asym_Pause;
 916         if (status & RxFlowCtrl)
 917                 cmd->advertising |= ADVERTISED_Pause;
 918
 919         cmd->duplex = ((status & _1000bpsF) || (status & FullDup)) ?
 920                       DUPLEX_FULL : DUPLEX_HALF;
 921 }
 922
 923 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 924 {
 925         struct rtl8169_private *tp = netdev_priv(dev);
 926         unsigned long flags;
 927
 928         spin_lock_irqsave(&tp->lock, flags);
 929
 930         tp->get_settings(dev, cmd);
 931
 932         spin_unlock_irqrestore(&tp->lock, flags);
 933         return 0;
 934 }
 935
 936 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
 937                              void *p)
 938 {
 939         struct rtl8169_private *tp = netdev_priv(dev);
 940         unsigned long flags;
 941
 942         if (regs->len > R8169_REGS_SIZE)
 943                 regs->len = R8169_REGS_SIZE;
 944
 945         spin_lock_irqsave(&tp->lock, flags);
 946         memcpy_fromio(p, tp->mmio_addr, regs->len);
 947         spin_unlock_irqrestore(&tp->lock, flags);
 948 }
 949
 950 static u32 rtl8169_get_msglevel(struct net_device *dev)
 951 {
 952         struct rtl8169_private *tp = netdev_priv(dev);
 953
 954         return tp->msg_enable;
 955 }
 956
 957 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
 958 {
 959         struct rtl8169_private *tp = netdev_priv(dev);
 960
 961         tp->msg_enable = value;
 962 }
 963
 964 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
 965         "tx_packets",
 966         "rx_packets",
 967         "tx_errors",
 968         "rx_errors",
 969         "rx_missed",
 970         "align_errors",
 971         "tx_single_collisions",
 972         "tx_multi_collisions",
 973         "unicast",
 974         "broadcast",
 975         "multicast",
 976         "tx_aborted",
 977         "tx_underrun",
 978 };
 979
 980 struct rtl8169_counters {
 981         __le64  tx_packets;
 982         __le64  rx_packets;
 983         __le64  tx_errors;
 984         __le32  rx_errors;
 985         __le16  rx_missed;
 986         __le16  align_errors;
 987         __le32  tx_one_collision;
 988         __le32  tx_multi_collision;
 989         __le64  rx_unicast;
 990         __le64  rx_broadcast;
 991         __le32  rx_multicast;
 992         __le16  tx_aborted;
 993         __le16  tx_underun;
 994 };
 995
 996 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
 997 {
 998         switch (sset) {
 999         case ETH_SS_STATS:
1000                 return ARRAY_SIZE(rtl8169_gstrings);
1001         default:
1002                 return -EOPNOTSUPP;
1003         }
1004 }
1005
1006 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1007                                       struct ethtool_stats *stats, u64 *data)
1008 {
1009         struct rtl8169_private *tp = netdev_priv(dev);
1010         void __iomem *ioaddr = tp->mmio_addr;
1011         struct rtl8169_counters *counters;
1012         dma_addr_t paddr;
1013         u32 cmd;
1014
1015         ASSERT_RTNL();
1016
1017         counters = pci_alloc_consistent(tp->pci_dev, sizeof(*counters), &paddr);
1018         if (!counters)
1019                 return;
1020
1021         RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1022         cmd = (u64)paddr & DMA_32BIT_MASK;
1023         RTL_W32(CounterAddrLow, cmd);
1024         RTL_W32(CounterAddrLow, cmd | CounterDump);
1025
1026         while (RTL_R32(CounterAddrLow) & CounterDump) {
1027                 if (msleep_interruptible(1))
1028                         break;
1029         }
1030
1031         RTL_W32(CounterAddrLow, 0);
1032         RTL_W32(CounterAddrHigh, 0);
1033
1034         data[0] = le64_to_cpu(counters->tx_packets);
1035         data[1] = le64_to_cpu(counters->rx_packets);
1036         data[2] = le64_to_cpu(counters->tx_errors);
1037         data[3] = le32_to_cpu(counters->rx_errors);
1038         data[4] = le16_to_cpu(counters->rx_missed);
1039         data[5] = le16_to_cpu(counters->align_errors);
1040         data[6] = le32_to_cpu(counters->tx_one_collision);
1041         data[7] = le32_to_cpu(counters->tx_multi_collision);
1042         data[8] = le64_to_cpu(counters->rx_unicast);
1043         data[9] = le64_to_cpu(counters->rx_broadcast);
1044         data[10] = le32_to_cpu(counters->rx_multicast);
1045         data[11] = le16_to_cpu(counters->tx_aborted);
1046         data[12] = le16_to_cpu(counters->tx_underun);
1047
1048         pci_free_consistent(tp->pci_dev, sizeof(*counters), counters, paddr);
1049 }
1050
1051 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1052 {
1053         switch(stringset) {
1054         case ETH_SS_STATS:
1055                 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1056                 break;
1057         }
1058 }
1059
1060 static const struct ethtool_ops rtl8169_ethtool_ops = {
1061         .get_drvinfo            = rtl8169_get_drvinfo,
1062         .get_regs_len           = rtl8169_get_regs_len,
1063         .get_link               = ethtool_op_get_link,
1064         .get_settings           = rtl8169_get_settings,
1065         .set_settings           = rtl8169_set_settings,
1066         .get_msglevel           = rtl8169_get_msglevel,
1067         .set_msglevel           = rtl8169_set_msglevel,
1068         .get_rx_csum            = rtl8169_get_rx_csum,
1069         .set_rx_csum            = rtl8169_set_rx_csum,
1070         .set_tx_csum            = ethtool_op_set_tx_csum,
1071         .set_sg                 = ethtool_op_set_sg,
1072         .set_tso                = ethtool_op_set_tso,
1073         .get_regs               = rtl8169_get_regs,
1074         .get_wol                = rtl8169_get_wol,
1075         .set_wol                = rtl8169_set_wol,
1076         .get_strings            = rtl8169_get_strings,
1077         .get_sset_count         = rtl8169_get_sset_count,
1078         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
1079 };
1080
1081 static void rtl8169_write_gmii_reg_bit(void __iomem *ioaddr, int reg,
1082                                        int bitnum, int bitval)
1083 {
1084         int val;
1085
1086         val = mdio_read(ioaddr, reg);
1087         val = (bitval == 1) ?
1088                 val | (bitval << bitnum) :  val & ~(0x0001 << bitnum);
1089         mdio_write(ioaddr, reg, val & 0xffff);
1090 }
1091
1092 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1093                                     void __iomem *ioaddr)
1094 {
1095         /*
1096          * The driver currently handles the 8168Bf and the 8168Be identically
1097          * but they can be identified more specifically through the test below
1098          * if needed:
1099          *
1100          * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1101          *
1102          * Same thing for the 8101Eb and the 8101Ec:
1103          *
1104          * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1105          */
1106         const struct {
1107                 u32 mask;
1108                 int mac_version;
1109         } mac_info[] = {
1110                 { 0x38800000,   RTL_GIGA_MAC_VER_15 },
1111                 { 0x38000000,   RTL_GIGA_MAC_VER_12 },
1112                 { 0x34000000,   RTL_GIGA_MAC_VER_13 },
1113                 { 0x30800000,   RTL_GIGA_MAC_VER_14 },
1114                 { 0x30000000,   RTL_GIGA_MAC_VER_11 },
1115                 { 0x98000000,   RTL_GIGA_MAC_VER_06 },
1116                 { 0x18000000,   RTL_GIGA_MAC_VER_05 },
1117                 { 0x10000000,   RTL_GIGA_MAC_VER_04 },
1118                 { 0x04000000,   RTL_GIGA_MAC_VER_03 },
1119                 { 0x00800000,   RTL_GIGA_MAC_VER_02 },
1120                 { 0x00000000,   RTL_GIGA_MAC_VER_01 }   /* Catch-all */
1121         }, *p = mac_info;
1122         u32 reg;
1123
1124         reg = RTL_R32(TxConfig) & 0xfc800000;
1125         while ((reg & p->mask) != p->mask)
1126                 p++;
1127         tp->mac_version = p->mac_version;
1128 }
1129
1130 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1131 {
1132         dprintk("mac_version = 0x%02x\n", tp->mac_version);
1133 }
1134
1135 static void rtl8169_get_phy_version(struct rtl8169_private *tp,
1136                                     void __iomem *ioaddr)
1137 {
1138         const struct {
1139                 u16 mask;
1140                 u16 set;
1141                 int phy_version;
1142         } phy_info[] = {
1143                 { 0x000f, 0x0002, RTL_GIGA_PHY_VER_G },
1144                 { 0x000f, 0x0001, RTL_GIGA_PHY_VER_F },
1145                 { 0x000f, 0x0000, RTL_GIGA_PHY_VER_E },
1146                 { 0x0000, 0x0000, RTL_GIGA_PHY_VER_D } /* Catch-all */
1147         }, *p = phy_info;
1148         u16 reg;
1149
1150         reg = mdio_read(ioaddr, MII_PHYSID2) & 0xffff;
1151         while ((reg & p->mask) != p->set)
1152                 p++;
1153         tp->phy_version = p->phy_version;
1154 }
1155
1156 static void rtl8169_print_phy_version(struct rtl8169_private *tp)
1157 {
1158         struct {
1159                 int version;
1160                 char *msg;
1161                 u32 reg;
1162         } phy_print[] = {
1163                 { RTL_GIGA_PHY_VER_G, "RTL_GIGA_PHY_VER_G", 0x0002 },
1164                 { RTL_GIGA_PHY_VER_F, "RTL_GIGA_PHY_VER_F", 0x0001 },
1165                 { RTL_GIGA_PHY_VER_E, "RTL_GIGA_PHY_VER_E", 0x0000 },
1166                 { RTL_GIGA_PHY_VER_D, "RTL_GIGA_PHY_VER_D", 0x0000 },
1167                 { 0, NULL, 0x0000 }
1168         }, *p;
1169
1170         for (p = phy_print; p->msg; p++) {
1171                 if (tp->phy_version == p->version) {
1172                         dprintk("phy_version == %s (%04x)\n", p->msg, p->reg);
1173                         return;
1174                 }
1175         }
1176         dprintk("phy_version == Unknown\n");
1177 }
1178
1179 static void rtl8169_hw_phy_config(struct net_device *dev)
1180 {
1181         struct rtl8169_private *tp = netdev_priv(dev);
1182         void __iomem *ioaddr = tp->mmio_addr;
1183         struct {
1184                 u16 regs[5]; /* Beware of bit-sign propagation */
1185         } phy_magic[5] = { {
1186                 { 0x0000,       //w 4 15 12 0
1187                   0x00a1,       //w 3 15 0 00a1
1188                   0x0008,       //w 2 15 0 0008
1189                   0x1020,       //w 1 15 0 1020
1190                   0x1000 } },{  //w 0 15 0 1000
1191                 { 0x7000,       //w 4 15 12 7
1192                   0xff41,       //w 3 15 0 ff41
1193                   0xde60,       //w 2 15 0 de60
1194                   0x0140,       //w 1 15 0 0140
1195                   0x0077 } },{  //w 0 15 0 0077
1196                 { 0xa000,       //w 4 15 12 a
1197                   0xdf01,       //w 3 15 0 df01
1198                   0xdf20,       //w 2 15 0 df20
1199                   0xff95,       //w 1 15 0 ff95
1200                   0xfa00 } },{  //w 0 15 0 fa00
1201                 { 0xb000,       //w 4 15 12 b
1202                   0xff41,       //w 3 15 0 ff41
1203                   0xde20,       //w 2 15 0 de20
1204                   0x0140,       //w 1 15 0 0140
1205                   0x00bb } },{  //w 0 15 0 00bb
1206                 { 0xf000,       //w 4 15 12 f
1207                   0xdf01,       //w 3 15 0 df01
1208                   0xdf20,       //w 2 15 0 df20
1209                   0xff95,       //w 1 15 0 ff95
1210                   0xbf00 }      //w 0 15 0 bf00
1211                 }
1212         }, *p = phy_magic;
1213         unsigned int i;
1214
1215         rtl8169_print_mac_version(tp);
1216         rtl8169_print_phy_version(tp);
1217
1218         if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1219                 return;
1220         if (tp->phy_version >= RTL_GIGA_PHY_VER_H)
1221                 return;
1222
1223         dprintk("MAC version != 0 && PHY version == 0 or 1\n");
1224         dprintk("Do final_reg2.cfg\n");
1225
1226         /* Shazam ! */
1227
1228         if (tp->mac_version == RTL_GIGA_MAC_VER_04) {
1229                 mdio_write(ioaddr, 31, 0x0002);
1230                 mdio_write(ioaddr,  1, 0x90d0);
1231                 mdio_write(ioaddr, 31, 0x0000);
1232                 return;
1233         }
1234
1235         if ((tp->mac_version != RTL_GIGA_MAC_VER_02) &&
1236             (tp->mac_version != RTL_GIGA_MAC_VER_03))
1237                 return;
1238
1239         mdio_write(ioaddr, 31, 0x0001);                 //w 31 2 0 1
1240         mdio_write(ioaddr, 21, 0x1000);                 //w 21 15 0 1000
1241         mdio_write(ioaddr, 24, 0x65c7);                 //w 24 15 0 65c7
1242         rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0);   //w 4 11 11 0
1243
1244         for (i = 0; i < ARRAY_SIZE(phy_magic); i++, p++) {
1245                 int val, pos = 4;
1246
1247                 val = (mdio_read(ioaddr, pos) & 0x0fff) | (p->regs[0] & 0xffff);
1248                 mdio_write(ioaddr, pos, val);
1249                 while (--pos >= 0)
1250                         mdio_write(ioaddr, pos, p->regs[4 - pos] & 0xffff);
1251                 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 1); //w 4 11 11 1
1252                 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1253         }
1254         mdio_write(ioaddr, 31, 0x0000); //w 31 2 0 0
1255 }
1256
1257 static void rtl8169_phy_timer(unsigned long __opaque)
1258 {
1259         struct net_device *dev = (struct net_device *)__opaque;
1260         struct rtl8169_private *tp = netdev_priv(dev);
1261         struct timer_list *timer = &tp->timer;
1262         void __iomem *ioaddr = tp->mmio_addr;
1263         unsigned long timeout = RTL8169_PHY_TIMEOUT;
1264
1265         assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1266         assert(tp->phy_version < RTL_GIGA_PHY_VER_H);
1267
1268         if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1269                 return;
1270
1271         spin_lock_irq(&tp->lock);
1272
1273         if (tp->phy_reset_pending(ioaddr)) {
1274                 /*
1275                  * A busy loop could burn quite a few cycles on nowadays CPU.
1276                  * Let's delay the execution of the timer for a few ticks.
1277                  */
1278                 timeout = HZ/10;
1279                 goto out_mod_timer;
1280         }
1281
1282         if (tp->link_ok(ioaddr))
1283                 goto out_unlock;
1284
1285         if (netif_msg_link(tp))
1286                 printk(KERN_WARNING "%s: PHY reset until link up\n", dev->name);
1287
1288         tp->phy_reset_enable(ioaddr);
1289
1290 out_mod_timer:
1291         mod_timer(timer, jiffies + timeout);
1292 out_unlock:
1293         spin_unlock_irq(&tp->lock);
1294 }
1295
1296 static inline void rtl8169_delete_timer(struct net_device *dev)
1297 {
1298         struct rtl8169_private *tp = netdev_priv(dev);
1299         struct timer_list *timer = &tp->timer;
1300
1301         if ((tp->mac_version <= RTL_GIGA_MAC_VER_01) ||
1302             (tp->phy_version >= RTL_GIGA_PHY_VER_H))
1303                 return;
1304
1305         del_timer_sync(timer);
1306 }
1307
1308 static inline void rtl8169_request_timer(struct net_device *dev)
1309 {
1310         struct rtl8169_private *tp = netdev_priv(dev);
1311         struct timer_list *timer = &tp->timer;
1312
1313         if ((tp->mac_version <= RTL_GIGA_MAC_VER_01) ||
1314             (tp->phy_version >= RTL_GIGA_PHY_VER_H))
1315                 return;
1316
1317         mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
1318 }
1319
1320 #ifdef CONFIG_NET_POLL_CONTROLLER
1321 /*
1322  * Polling 'interrupt' - used by things like netconsole to send skbs
1323  * without having to re-enable interrupts. It's not called while
1324  * the interrupt routine is executing.
1325  */
1326 static void rtl8169_netpoll(struct net_device *dev)
1327 {
1328         struct rtl8169_private *tp = netdev_priv(dev);
1329         struct pci_dev *pdev = tp->pci_dev;
1330
1331         disable_irq(pdev->irq);
1332         rtl8169_interrupt(pdev->irq, dev);
1333         enable_irq(pdev->irq);
1334 }
1335 #endif
1336
1337 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
1338                                   void __iomem *ioaddr)
1339 {
1340         iounmap(ioaddr);
1341         pci_release_regions(pdev);
1342         pci_disable_device(pdev);
1343         free_netdev(dev);
1344 }
1345
1346 static void rtl8169_phy_reset(struct net_device *dev,
1347                               struct rtl8169_private *tp)
1348 {
1349         void __iomem *ioaddr = tp->mmio_addr;
1350         unsigned int i;
1351
1352         tp->phy_reset_enable(ioaddr);
1353         for (i = 0; i < 100; i++) {
1354                 if (!tp->phy_reset_pending(ioaddr))
1355                         return;
1356                 msleep(1);
1357         }
1358         if (netif_msg_link(tp))
1359                 printk(KERN_ERR "%s: PHY reset failed.\n", dev->name);
1360 }
1361
1362 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
1363 {
1364         void __iomem *ioaddr = tp->mmio_addr;
1365
1366         rtl8169_hw_phy_config(dev);
1367
1368         dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1369         RTL_W8(0x82, 0x01);
1370
1371         pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
1372
1373         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
1374                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
1375
1376         if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
1377                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1378                 RTL_W8(0x82, 0x01);
1379                 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
1380                 mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0
1381         }
1382
1383         rtl8169_phy_reset(dev, tp);
1384
1385         /*
1386          * rtl8169_set_speed_xmii takes good care of the Fast Ethernet
1387          * only 8101. Don't panic.
1388          */
1389         rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL);
1390
1391         if ((RTL_R8(PHYstatus) & TBI_Enable) && netif_msg_link(tp))
1392                 printk(KERN_INFO PFX "%s: TBI auto-negotiating\n", dev->name);
1393 }
1394
1395 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
1396 {
1397         void __iomem *ioaddr = tp->mmio_addr;
1398         u32 high;
1399         u32 low;
1400
1401         low  = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
1402         high = addr[4] | (addr[5] << 8);
1403
1404         spin_lock_irq(&tp->lock);
1405
1406         RTL_W8(Cfg9346, Cfg9346_Unlock);
1407         RTL_W32(MAC0, low);
1408         RTL_W32(MAC4, high);
1409         RTL_W8(Cfg9346, Cfg9346_Lock);
1410
1411         spin_unlock_irq(&tp->lock);
1412 }
1413
1414 static int rtl_set_mac_address(struct net_device *dev, void *p)
1415 {
1416         struct rtl8169_private *tp = netdev_priv(dev);
1417         struct sockaddr *addr = p;
1418
1419         if (!is_valid_ether_addr(addr->sa_data))
1420                 return -EADDRNOTAVAIL;
1421
1422         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1423
1424         rtl_rar_set(tp, dev->dev_addr);
1425
1426         return 0;
1427 }
1428
1429 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1430 {
1431         struct rtl8169_private *tp = netdev_priv(dev);
1432         struct mii_ioctl_data *data = if_mii(ifr);
1433
1434         if (!netif_running(dev))
1435                 return -ENODEV;
1436
1437         switch (cmd) {
1438         case SIOCGMIIPHY:
1439                 data->phy_id = 32; /* Internal PHY */
1440                 return 0;
1441
1442         case SIOCGMIIREG:
1443                 data->val_out = mdio_read(tp->mmio_addr, data->reg_num & 0x1f);
1444                 return 0;
1445
1446         case SIOCSMIIREG:
1447                 if (!capable(CAP_NET_ADMIN))
1448                         return -EPERM;
1449                 mdio_write(tp->mmio_addr, data->reg_num & 0x1f, data->val_in);
1450                 return 0;
1451         }
1452         return -EOPNOTSUPP;
1453 }
1454
1455 static const struct rtl_cfg_info {
1456         void (*hw_start)(struct net_device *);
1457         unsigned int region;
1458         unsigned int align;
1459         u16 intr_event;
1460         u16 napi_event;
1461 } rtl_cfg_infos [] = {
1462         [RTL_CFG_0] = {
1463                 .hw_start       = rtl_hw_start_8169,
1464                 .region         = 1,
1465                 .align          = 0,
1466                 .intr_event     = SYSErr | LinkChg | RxOverflow |
1467                                   RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
1468                 .napi_event     = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow
1469         },
1470         [RTL_CFG_1] = {
1471                 .hw_start       = rtl_hw_start_8168,
1472                 .region         = 2,
1473                 .align          = 8,
1474                 .intr_event     = SYSErr | LinkChg | RxOverflow |
1475                                   TxErr | TxOK | RxOK | RxErr,
1476                 .napi_event     = TxErr | TxOK | RxOK | RxOverflow
1477         },
1478         [RTL_CFG_2] = {
1479                 .hw_start       = rtl_hw_start_8101,
1480                 .region         = 2,
1481                 .align          = 8,
1482                 .intr_event     = SYSErr | LinkChg | RxOverflow | PCSTimeout |
1483                                   RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
1484                 .napi_event     = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow
1485         }
1486 };
1487
1488 static int __devinit
1489 rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1490 {
1491         const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
1492         const unsigned int region = cfg->region;
1493         struct rtl8169_private *tp;
1494         struct net_device *dev;
1495         void __iomem *ioaddr;
1496         unsigned int i;
1497         int rc;
1498
1499         if (netif_msg_drv(&debug)) {
1500                 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
1501                        MODULENAME, RTL8169_VERSION);
1502         }
1503
1504         dev = alloc_etherdev(sizeof (*tp));
1505         if (!dev) {
1506                 if (netif_msg_drv(&debug))
1507                         dev_err(&pdev->dev, "unable to alloc new ethernet\n");
1508                 rc = -ENOMEM;
1509                 goto out;
1510         }
1511
1512         SET_NETDEV_DEV(dev, &pdev->dev);
1513         tp = netdev_priv(dev);
1514         tp->dev = dev;
1515         tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
1516
1517         /* enable device (incl. PCI PM wakeup and hotplug setup) */
1518         rc = pci_enable_device(pdev);
1519         if (rc < 0) {
1520                 if (netif_msg_probe(tp))
1521                         dev_err(&pdev->dev, "enable failure\n");
1522                 goto err_out_free_dev_1;
1523         }
1524
1525         rc = pci_set_mwi(pdev);
1526         if (rc < 0)
1527                 goto err_out_disable_2;
1528
1529         /* make sure PCI base addr 1 is MMIO */
1530         if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
1531                 if (netif_msg_probe(tp)) {
1532                         dev_err(&pdev->dev,
1533                                 "region #%d not an MMIO resource, aborting\n",
1534                                 region);
1535                 }
1536                 rc = -ENODEV;
1537                 goto err_out_mwi_3;
1538         }
1539
1540         /* check for weird/broken PCI region reporting */
1541         if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
1542                 if (netif_msg_probe(tp)) {
1543                         dev_err(&pdev->dev,
1544                                 "Invalid PCI region size(s), aborting\n");
1545                 }
1546                 rc = -ENODEV;
1547                 goto err_out_mwi_3;
1548         }
1549
1550         rc = pci_request_regions(pdev, MODULENAME);
1551         if (rc < 0) {
1552                 if (netif_msg_probe(tp))
1553                         dev_err(&pdev->dev, "could not request regions.\n");
1554                 goto err_out_mwi_3;
1555         }
1556
1557         tp->cp_cmd = PCIMulRW | RxChkSum;
1558
1559         if ((sizeof(dma_addr_t) > 4) &&
1560             !pci_set_dma_mask(pdev, DMA_64BIT_MASK) && use_dac) {
1561                 tp->cp_cmd |= PCIDAC;
1562                 dev->features |= NETIF_F_HIGHDMA;
1563         } else {
1564                 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1565                 if (rc < 0) {
1566                         if (netif_msg_probe(tp)) {
1567                                 dev_err(&pdev->dev,
1568                                         "DMA configuration failed.\n");
1569                         }
1570                         goto err_out_free_res_4;
1571                 }
1572         }
1573
1574         pci_set_master(pdev);
1575
1576         /* ioremap MMIO region */
1577         ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
1578         if (!ioaddr) {
1579                 if (netif_msg_probe(tp))
1580                         dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
1581                 rc = -EIO;
1582                 goto err_out_free_res_4;
1583         }
1584
1585         /* Unneeded ? Don't mess with Mrs. Murphy. */
1586         rtl8169_irq_mask_and_ack(ioaddr);
1587
1588         /* Soft reset the chip. */
1589         RTL_W8(ChipCmd, CmdReset);
1590
1591         /* Check that the chip has finished the reset. */
1592         for (i = 0; i < 100; i++) {
1593                 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1594                         break;
1595                 msleep_interruptible(1);
1596         }
1597
1598         /* Identify chip attached to board */
1599         rtl8169_get_mac_version(tp, ioaddr);
1600         rtl8169_get_phy_version(tp, ioaddr);
1601
1602         rtl8169_print_mac_version(tp);
1603         rtl8169_print_phy_version(tp);
1604
1605         for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--) {
1606                 if (tp->mac_version == rtl_chip_info[i].mac_version)
1607                         break;
1608         }
1609         if (i < 0) {
1610                 /* Unknown chip: assume array element #0, original RTL-8169 */
1611                 if (netif_msg_probe(tp)) {
1612                         dev_printk(KERN_DEBUG, &pdev->dev,
1613                                 "unknown chip version, assuming %s\n",
1614                                 rtl_chip_info[0].name);
1615                 }
1616                 i++;
1617         }
1618         tp->chipset = i;
1619
1620         RTL_W8(Cfg9346, Cfg9346_Unlock);
1621         RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
1622         RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
1623         RTL_W8(Cfg9346, Cfg9346_Lock);
1624
1625         if (RTL_R8(PHYstatus) & TBI_Enable) {
1626                 tp->set_speed = rtl8169_set_speed_tbi;
1627                 tp->get_settings = rtl8169_gset_tbi;
1628                 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
1629                 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
1630                 tp->link_ok = rtl8169_tbi_link_ok;
1631
1632                 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
1633         } else {
1634                 tp->set_speed = rtl8169_set_speed_xmii;
1635                 tp->get_settings = rtl8169_gset_xmii;
1636                 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
1637                 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
1638                 tp->link_ok = rtl8169_xmii_link_ok;
1639
1640                 dev->do_ioctl = rtl8169_ioctl;
1641         }
1642
1643         /* Get MAC address.  FIXME: read EEPROM */
1644         for (i = 0; i < MAC_ADDR_LEN; i++)
1645                 dev->dev_addr[i] = RTL_R8(MAC0 + i);
1646         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1647
1648         dev->open = rtl8169_open;
1649         dev->hard_start_xmit = rtl8169_start_xmit;
1650         dev->get_stats = rtl8169_get_stats;
1651         SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
1652         dev->stop = rtl8169_close;
1653         dev->tx_timeout = rtl8169_tx_timeout;
1654         dev->set_multicast_list = rtl_set_rx_mode;
1655         dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
1656         dev->irq = pdev->irq;
1657         dev->base_addr = (unsigned long) ioaddr;
1658         dev->change_mtu = rtl8169_change_mtu;
1659         dev->set_mac_address = rtl_set_mac_address;
1660
1661 #ifdef CONFIG_R8169_NAPI
1662         netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
1663 #endif
1664
1665 #ifdef CONFIG_R8169_VLAN
1666         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1667         dev->vlan_rx_register = rtl8169_vlan_rx_register;
1668 #endif
1669
1670 #ifdef CONFIG_NET_POLL_CONTROLLER
1671         dev->poll_controller = rtl8169_netpoll;
1672 #endif
1673
1674         tp->intr_mask = 0xffff;
1675         tp->pci_dev = pdev;
1676         tp->mmio_addr = ioaddr;
1677         tp->align = cfg->align;
1678         tp->hw_start = cfg->hw_start;
1679         tp->intr_event = cfg->intr_event;
1680         tp->napi_event = cfg->napi_event;
1681
1682         init_timer(&tp->timer);
1683         tp->timer.data = (unsigned long) dev;
1684         tp->timer.function = rtl8169_phy_timer;
1685
1686         spin_lock_init(&tp->lock);
1687
1688         rc = register_netdev(dev);
1689         if (rc < 0)
1690                 goto err_out_unmap_5;
1691
1692         pci_set_drvdata(pdev, dev);
1693
1694         if (netif_msg_probe(tp)) {
1695                 u32 xid = RTL_R32(TxConfig) & 0x7cf0f8ff;
1696
1697                 printk(KERN_INFO "%s: %s at 0x%lx, "
1698                        "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
1699                        "XID %08x IRQ %d\n",
1700                        dev->name,
1701                        rtl_chip_info[tp->chipset].name,
1702                        dev->base_addr,
1703                        dev->dev_addr[0], dev->dev_addr[1],
1704                        dev->dev_addr[2], dev->dev_addr[3],
1705                        dev->dev_addr[4], dev->dev_addr[5], xid, dev->irq);
1706         }
1707
1708         rtl8169_init_phy(dev, tp);
1709
1710 out:
1711         return rc;
1712
1713 err_out_unmap_5:
1714         iounmap(ioaddr);
1715 err_out_free_res_4:
1716         pci_release_regions(pdev);
1717 err_out_mwi_3:
1718         pci_clear_mwi(pdev);
1719 err_out_disable_2:
1720         pci_disable_device(pdev);
1721 err_out_free_dev_1:
1722         free_netdev(dev);
1723         goto out;
1724 }
1725
1726 static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
1727 {
1728         struct net_device *dev = pci_get_drvdata(pdev);
1729         struct rtl8169_private *tp = netdev_priv(dev);
1730
1731         flush_scheduled_work();
1732
1733         unregister_netdev(dev);
1734         rtl8169_release_board(pdev, dev, tp->mmio_addr);
1735         pci_set_drvdata(pdev, NULL);
1736 }
1737
1738 static void rtl8169_set_rxbufsize(struct rtl8169_private *tp,
1739                                   struct net_device *dev)
1740 {
1741         unsigned int mtu = dev->mtu;
1742
1743         tp->rx_buf_sz = (mtu > RX_BUF_SIZE) ? mtu + ETH_HLEN + 8 : RX_BUF_SIZE;
1744 }
1745
1746 static int rtl8169_open(struct net_device *dev)
1747 {
1748         struct rtl8169_private *tp = netdev_priv(dev);
1749         struct pci_dev *pdev = tp->pci_dev;
1750         int retval = -ENOMEM;
1751
1752
1753         rtl8169_set_rxbufsize(tp, dev);
1754
1755         /*
1756          * Rx and Tx desscriptors needs 256 bytes alignment.
1757          * pci_alloc_consistent provides more.
1758          */
1759         tp->TxDescArray = pci_alloc_consistent(pdev, R8169_TX_RING_BYTES,
1760                                                &tp->TxPhyAddr);
1761         if (!tp->TxDescArray)
1762                 goto out;
1763
1764         tp->RxDescArray = pci_alloc_consistent(pdev, R8169_RX_RING_BYTES,
1765                                                &tp->RxPhyAddr);
1766         if (!tp->RxDescArray)
1767                 goto err_free_tx_0;
1768
1769         retval = rtl8169_init_ring(dev);
1770         if (retval < 0)
1771                 goto err_free_rx_1;
1772
1773         INIT_DELAYED_WORK(&tp->task, NULL);
1774
1775         smp_mb();
1776
1777         retval = request_irq(dev->irq, rtl8169_interrupt, IRQF_SHARED,
1778                              dev->name, dev);
1779         if (retval < 0)
1780                 goto err_release_ring_2;
1781
1782 #ifdef CONFIG_R8169_NAPI
1783         napi_enable(&tp->napi);
1784 #endif
1785
1786         rtl_hw_start(dev);
1787
1788         rtl8169_request_timer(dev);
1789
1790         rtl8169_check_link_status(dev, tp, tp->mmio_addr);
1791 out:
1792         return retval;
1793
1794 err_release_ring_2:
1795         rtl8169_rx_clear(tp);
1796 err_free_rx_1:
1797         pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
1798                             tp->RxPhyAddr);
1799 err_free_tx_0:
1800         pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
1801                             tp->TxPhyAddr);
1802         goto out;
1803 }
1804
1805 static void rtl8169_hw_reset(void __iomem *ioaddr)
1806 {
1807         /* Disable interrupts */
1808         rtl8169_irq_mask_and_ack(ioaddr);
1809
1810         /* Reset the chipset */
1811         RTL_W8(ChipCmd, CmdReset);
1812
1813         /* PCI commit */
1814         RTL_R8(ChipCmd);
1815 }
1816
1817 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
1818 {
1819         void __iomem *ioaddr = tp->mmio_addr;
1820         u32 cfg = rtl8169_rx_config;
1821
1822         cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
1823         RTL_W32(RxConfig, cfg);
1824
1825         /* Set DMA burst size and Interframe Gap Time */
1826         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
1827                 (InterFrameGap << TxInterFrameGapShift));
1828 }
1829
1830 static void rtl_hw_start(struct net_device *dev)
1831 {
1832         struct rtl8169_private *tp = netdev_priv(dev);
1833         void __iomem *ioaddr = tp->mmio_addr;
1834         unsigned int i;
1835
1836         /* Soft reset the chip. */
1837         RTL_W8(ChipCmd, CmdReset);
1838
1839         /* Check that the chip has finished the reset. */
1840         for (i = 0; i < 100; i++) {
1841                 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1842                         break;
1843                 msleep_interruptible(1);
1844         }
1845
1846         tp->hw_start(dev);
1847
1848         netif_start_queue(dev);
1849 }
1850
1851
1852 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
1853                                          void __iomem *ioaddr)
1854 {
1855         /*
1856          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
1857          * register to be written before TxDescAddrLow to work.
1858          * Switching from MMIO to I/O access fixes the issue as well.
1859          */
1860         RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
1861         RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_32BIT_MASK);
1862         RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
1863         RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_32BIT_MASK);
1864 }
1865
1866 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
1867 {
1868         u16 cmd;
1869
1870         cmd = RTL_R16(CPlusCmd);
1871         RTL_W16(CPlusCmd, cmd);
1872         return cmd;
1873 }
1874
1875 static void rtl_set_rx_max_size(void __iomem *ioaddr)
1876 {
1877         /* Low hurts. Let's disable the filtering. */
1878         RTL_W16(RxMaxSize, 16383);
1879 }
1880
1881 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
1882 {
1883         struct {
1884                 u32 mac_version;
1885                 u32 clk;
1886                 u32 val;
1887         } cfg2_info [] = {
1888                 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
1889                 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
1890                 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
1891                 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
1892         }, *p = cfg2_info;
1893         unsigned int i;
1894         u32 clk;
1895
1896         clk = RTL_R8(Config2) & PCI_Clock_66MHz;
1897         for (i = 0; i < ARRAY_SIZE(cfg2_info); i++) {
1898                 if ((p->mac_version == mac_version) && (p->clk == clk)) {
1899                         RTL_W32(0x7c, p->val);
1900                         break;
1901                 }
1902         }
1903 }
1904
1905 static void rtl_hw_start_8169(struct net_device *dev)
1906 {
1907         struct rtl8169_private *tp = netdev_priv(dev);
1908         void __iomem *ioaddr = tp->mmio_addr;
1909         struct pci_dev *pdev = tp->pci_dev;
1910
1911         if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
1912                 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
1913                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
1914         }
1915
1916         RTL_W8(Cfg9346, Cfg9346_Unlock);
1917         if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
1918             (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
1919             (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
1920             (tp->mac_version == RTL_GIGA_MAC_VER_04))
1921                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
1922
1923         RTL_W8(EarlyTxThres, EarlyTxThld);
1924
1925         rtl_set_rx_max_size(ioaddr);
1926
1927         if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
1928             (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
1929             (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
1930             (tp->mac_version == RTL_GIGA_MAC_VER_04))
1931                 rtl_set_rx_tx_config_registers(tp);
1932
1933         tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
1934
1935         if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
1936             (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
1937                 dprintk("Set MAC Reg C+CR Offset 0xE0. "
1938                         "Bit-3 and bit-14 MUST be 1\n");
1939                 tp->cp_cmd |= (1 << 14);
1940         }
1941
1942         RTL_W16(CPlusCmd, tp->cp_cmd);
1943
1944         rtl8169_set_magic_reg(ioaddr, tp->mac_version);
1945
1946         /*
1947          * Undocumented corner. Supposedly:
1948          * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
1949          */
1950         RTL_W16(IntrMitigate, 0x0000);
1951
1952         rtl_set_rx_tx_desc_registers(tp, ioaddr);
1953
1954         if ((tp->mac_version != RTL_GIGA_MAC_VER_01) &&
1955             (tp->mac_version != RTL_GIGA_MAC_VER_02) &&
1956             (tp->mac_version != RTL_GIGA_MAC_VER_03) &&
1957             (tp->mac_version != RTL_GIGA_MAC_VER_04)) {
1958                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
1959                 rtl_set_rx_tx_config_registers(tp);
1960         }
1961
1962         RTL_W8(Cfg9346, Cfg9346_Lock);
1963
1964         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
1965         RTL_R8(IntrMask);
1966
1967         RTL_W32(RxMissed, 0);
1968
1969         rtl_set_rx_mode(dev);
1970
1971         /* no early-rx interrupts */
1972         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
1973
1974         /* Enable all known interrupts by setting the interrupt mask. */
1975         RTL_W16(IntrMask, tp->intr_event);
1976 }
1977
1978 static void rtl_hw_start_8168(struct net_device *dev)
1979 {
1980         struct rtl8169_private *tp = netdev_priv(dev);
1981         void __iomem *ioaddr = tp->mmio_addr;
1982         struct pci_dev *pdev = tp->pci_dev;
1983         u8 ctl;
1984
1985         RTL_W8(Cfg9346, Cfg9346_Unlock);
1986
1987         RTL_W8(EarlyTxThres, EarlyTxThld);
1988
1989         rtl_set_rx_max_size(ioaddr);
1990
1991         rtl_set_rx_tx_config_registers(tp);
1992
1993         tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
1994
1995         RTL_W16(CPlusCmd, tp->cp_cmd);
1996
1997         /* Tx performance tweak. */
1998         pci_read_config_byte(pdev, 0x69, &ctl);
1999         ctl = (ctl & ~0x70) | 0x50;
2000         pci_write_config_byte(pdev, 0x69, ctl);
2001
2002         RTL_W16(IntrMitigate, 0x5151);
2003
2004         /* Work around for RxFIFO overflow. */
2005         if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
2006                 tp->intr_event |= RxFIFOOver | PCSTimeout;
2007                 tp->intr_event &= ~RxOverflow;
2008         }
2009
2010         rtl_set_rx_tx_desc_registers(tp, ioaddr);
2011
2012         RTL_W8(Cfg9346, Cfg9346_Lock);
2013
2014         RTL_R8(IntrMask);
2015
2016         RTL_W32(RxMissed, 0);
2017
2018         rtl_set_rx_mode(dev);
2019
2020         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2021
2022         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
2023
2024         RTL_W16(IntrMask, tp->intr_event);
2025 }
2026
2027 static void rtl_hw_start_8101(struct net_device *dev)
2028 {
2029         struct rtl8169_private *tp = netdev_priv(dev);
2030         void __iomem *ioaddr = tp->mmio_addr;
2031         struct pci_dev *pdev = tp->pci_dev;
2032
2033         if (tp->mac_version == RTL_GIGA_MAC_VER_13) {
2034                 pci_write_config_word(pdev, 0x68, 0x00);
2035                 pci_write_config_word(pdev, 0x69, 0x08);
2036         }
2037
2038         RTL_W8(Cfg9346, Cfg9346_Unlock);
2039
2040         RTL_W8(EarlyTxThres, EarlyTxThld);
2041
2042         rtl_set_rx_max_size(ioaddr);
2043
2044         tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
2045
2046         RTL_W16(CPlusCmd, tp->cp_cmd);
2047
2048         RTL_W16(IntrMitigate, 0x0000);
2049
2050         rtl_set_rx_tx_desc_registers(tp, ioaddr);
2051
2052         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2053         rtl_set_rx_tx_config_registers(tp);
2054
2055         RTL_W8(Cfg9346, Cfg9346_Lock);
2056
2057         RTL_R8(IntrMask);
2058
2059         RTL_W32(RxMissed, 0);
2060
2061         rtl_set_rx_mode(dev);
2062
2063         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2064
2065         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
2066
2067         RTL_W16(IntrMask, tp->intr_event);
2068 }
2069
2070 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
2071 {
2072         struct rtl8169_private *tp = netdev_priv(dev);
2073         int ret = 0;
2074
2075         if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
2076                 return -EINVAL;
2077
2078         dev->mtu = new_mtu;
2079
2080         if (!netif_running(dev))
2081                 goto out;
2082
2083         rtl8169_down(dev);
2084
2085         rtl8169_set_rxbufsize(tp, dev);
2086
2087         ret = rtl8169_init_ring(dev);
2088         if (ret < 0)
2089                 goto out;
2090
2091 #ifdef CONFIG_R8169_NAPI
2092         napi_enable(&tp->napi);
2093 #endif
2094
2095         rtl_hw_start(dev);
2096
2097         rtl8169_request_timer(dev);
2098
2099 out:
2100         return ret;
2101 }
2102
2103 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
2104 {
2105         desc->addr = 0x0badbadbadbadbadull;
2106         desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
2107 }
2108
2109 static void rtl8169_free_rx_skb(struct rtl8169_private *tp,
2110                                 struct sk_buff **sk_buff, struct RxDesc *desc)
2111 {
2112         struct pci_dev *pdev = tp->pci_dev;
2113
2114         pci_unmap_single(pdev, le64_to_cpu(desc->addr), tp->rx_buf_sz,
2115                          PCI_DMA_FROMDEVICE);
2116         dev_kfree_skb(*sk_buff);
2117         *sk_buff = NULL;
2118         rtl8169_make_unusable_by_asic(desc);
2119 }
2120
2121 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
2122 {
2123         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
2124
2125         desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
2126 }
2127
2128 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
2129                                        u32 rx_buf_sz)
2130 {
2131         desc->addr = cpu_to_le64(mapping);
2132         wmb();
2133         rtl8169_mark_to_asic(desc, rx_buf_sz);
2134 }
2135
2136 static struct sk_buff *rtl8169_alloc_rx_skb(struct pci_dev *pdev,
2137                                             struct net_device *dev,
2138                                             struct RxDesc *desc, int rx_buf_sz,
2139                                             unsigned int align)
2140 {
2141         struct sk_buff *skb;
2142         dma_addr_t mapping;
2143         unsigned int pad;
2144
2145         pad = align ? align : NET_IP_ALIGN;
2146
2147         skb = netdev_alloc_skb(dev, rx_buf_sz + pad);
2148         if (!skb)
2149                 goto err_out;
2150
2151         skb_reserve(skb, align ? ((pad - 1) & (unsigned long)skb->data) : pad);
2152
2153         mapping = pci_map_single(pdev, skb->data, rx_buf_sz,
2154                                  PCI_DMA_FROMDEVICE);
2155
2156         rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
2157 out:
2158         return skb;
2159
2160 err_out:
2161         rtl8169_make_unusable_by_asic(desc);
2162         goto out;
2163 }
2164
2165 static void rtl8169_rx_clear(struct rtl8169_private *tp)
2166 {
2167         unsigned int i;
2168
2169         for (i = 0; i < NUM_RX_DESC; i++) {
2170                 if (tp->Rx_skbuff[i]) {
2171                         rtl8169_free_rx_skb(tp, tp->Rx_skbuff + i,
2172                                             tp->RxDescArray + i);
2173                 }
2174         }
2175 }
2176
2177 static u32 rtl8169_rx_fill(struct rtl8169_private *tp, struct net_device *dev,
2178                            u32 start, u32 end)
2179 {
2180         u32 cur;
2181
2182         for (cur = start; end - cur != 0; cur++) {
2183                 struct sk_buff *skb;
2184                 unsigned int i = cur % NUM_RX_DESC;
2185
2186                 WARN_ON((s32)(end - cur) < 0);
2187
2188                 if (tp->Rx_skbuff[i])
2189                         continue;
2190
2191                 skb = rtl8169_alloc_rx_skb(tp->pci_dev, dev,
2192                                            tp->RxDescArray + i,
2193                                            tp->rx_buf_sz, tp->align);
2194                 if (!skb)
2195                         break;
2196
2197                 tp->Rx_skbuff[i] = skb;
2198         }
2199         return cur - start;
2200 }
2201
2202 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
2203 {
2204         desc->opts1 |= cpu_to_le32(RingEnd);
2205 }
2206
2207 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
2208 {
2209         tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
2210 }
2211
2212 static int rtl8169_init_ring(struct net_device *dev)
2213 {
2214         struct rtl8169_private *tp = netdev_priv(dev);
2215
2216         rtl8169_init_ring_indexes(tp);
2217
2218         memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
2219         memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));
2220
2221         if (rtl8169_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC)
2222                 goto err_out;
2223
2224         rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
2225
2226         return 0;
2227
2228 err_out:
2229         rtl8169_rx_clear(tp);
2230         return -ENOMEM;
2231 }
2232
2233 static void rtl8169_unmap_tx_skb(struct pci_dev *pdev, struct ring_info *tx_skb,
2234                                  struct TxDesc *desc)
2235 {
2236         unsigned int len = tx_skb->len;
2237
2238         pci_unmap_single(pdev, le64_to_cpu(desc->addr), len, PCI_DMA_TODEVICE);
2239         desc->opts1 = 0x00;
2240         desc->opts2 = 0x00;
2241         desc->addr = 0x00;
2242         tx_skb->len = 0;
2243 }
2244
2245 static void rtl8169_tx_clear(struct rtl8169_private *tp)
2246 {
2247         unsigned int i;
2248
2249         for (i = tp->dirty_tx; i < tp->dirty_tx + NUM_TX_DESC; i++) {
2250                 unsigned int entry = i % NUM_TX_DESC;
2251                 struct ring_info *tx_skb = tp->tx_skb + entry;
2252                 unsigned int len = tx_skb->len;
2253
2254                 if (len) {
2255                         struct sk_buff *skb = tx_skb->skb;
2256
2257                         rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb,
2258                                              tp->TxDescArray + entry);
2259                         if (skb) {
2260                                 dev_kfree_skb(skb);
2261                                 tx_skb->skb = NULL;
2262                         }
2263                         tp->stats.tx_dropped++;
2264                 }
2265         }
2266         tp->cur_tx = tp->dirty_tx = 0;
2267 }
2268
2269 static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
2270 {
2271         struct rtl8169_private *tp = netdev_priv(dev);
2272
2273         PREPARE_DELAYED_WORK(&tp->task, task);
2274         schedule_delayed_work(&tp->task, 4);
2275 }
2276
2277 static void rtl8169_wait_for_quiescence(struct net_device *dev)
2278 {
2279         struct rtl8169_private *tp = netdev_priv(dev);
2280         void __iomem *ioaddr = tp->mmio_addr;
2281
2282         synchronize_irq(dev->irq);
2283
2284         /* Wait for any pending NAPI task to complete */
2285 #ifdef CONFIG_R8169_NAPI
2286         napi_disable(&tp->napi);
2287 #endif
2288
2289         rtl8169_irq_mask_and_ack(ioaddr);
2290
2291 #ifdef CONFIG_R8169_NAPI
2292         napi_enable(&tp->napi);
2293 #endif
2294 }
2295
2296 static void rtl8169_reinit_task(struct work_struct *work)
2297 {
2298         struct rtl8169_private *tp =
2299                 container_of(work, struct rtl8169_private, task.work);
2300         struct net_device *dev = tp->dev;
2301         int ret;
2302
2303         rtnl_lock();
2304
2305         if (!netif_running(dev))
2306                 goto out_unlock;
2307
2308         rtl8169_wait_for_quiescence(dev);
2309         rtl8169_close(dev);
2310
2311         ret = rtl8169_open(dev);
2312         if (unlikely(ret < 0)) {
2313                 if (net_ratelimit() && netif_msg_drv(tp)) {
2314                         printk(PFX KERN_ERR "%s: reinit failure (status = %d)."
2315                                " Rescheduling.\n", dev->name, ret);
2316                 }
2317                 rtl8169_schedule_work(dev, rtl8169_reinit_task);
2318         }
2319
2320 out_unlock:
2321         rtnl_unlock();
2322 }
2323
2324 static void rtl8169_reset_task(struct work_struct *work)
2325 {
2326         struct rtl8169_private *tp =
2327                 container_of(work, struct rtl8169_private, task.work);
2328         struct net_device *dev = tp->dev;
2329
2330         rtnl_lock();
2331
2332         if (!netif_running(dev))
2333                 goto out_unlock;
2334
2335         rtl8169_wait_for_quiescence(dev);
2336
2337         rtl8169_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0);
2338         rtl8169_tx_clear(tp);
2339
2340         if (tp->dirty_rx == tp->cur_rx) {
2341                 rtl8169_init_ring_indexes(tp);
2342                 rtl_hw_start(dev);
2343                 netif_wake_queue(dev);
2344         } else {
2345                 if (net_ratelimit() && netif_msg_intr(tp)) {
2346                         printk(PFX KERN_EMERG "%s: Rx buffers shortage\n",
2347                                dev->name);
2348                 }
2349                 rtl8169_schedule_work(dev, rtl8169_reset_task);
2350         }
2351
2352 out_unlock:
2353         rtnl_unlock();
2354 }
2355
2356 static void rtl8169_tx_timeout(struct net_device *dev)
2357 {
2358         struct rtl8169_private *tp = netdev_priv(dev);
2359
2360         rtl8169_hw_reset(tp->mmio_addr);
2361
2362         /* Let's wait a bit while any (async) irq lands on */
2363         rtl8169_schedule_work(dev, rtl8169_reset_task);
2364 }
2365
2366 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
2367                               u32 opts1)
2368 {
2369         struct skb_shared_info *info = skb_shinfo(skb);
2370         unsigned int cur_frag, entry;
2371         struct TxDesc * uninitialized_var(txd);
2372
2373         entry = tp->cur_tx;
2374         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
2375                 skb_frag_t *frag = info->frags + cur_frag;
2376                 dma_addr_t mapping;
2377                 u32 status, len;
2378                 void *addr;
2379
2380                 entry = (entry + 1) % NUM_TX_DESC;
2381
2382                 txd = tp->TxDescArray + entry;
2383                 len = frag->size;
2384                 addr = ((void *) page_address(frag->page)) + frag->page_offset;
2385                 mapping = pci_map_single(tp->pci_dev, addr, len, PCI_DMA_TODEVICE);
2386
2387                 /* anti gcc 2.95.3 bugware (sic) */
2388                 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
2389
2390                 txd->opts1 = cpu_to_le32(status);
2391                 txd->addr = cpu_to_le64(mapping);
2392
2393                 tp->tx_skb[entry].len = len;
2394         }
2395
2396         if (cur_frag) {
2397                 tp->tx_skb[entry].skb = skb;
2398                 txd->opts1 |= cpu_to_le32(LastFrag);
2399         }
2400
2401         return cur_frag;
2402 }
2403
2404 static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
2405 {
2406         if (dev->features & NETIF_F_TSO) {
2407                 u32 mss = skb_shinfo(skb)->gso_size;
2408
2409                 if (mss)
2410                         return LargeSend | ((mss & MSSMask) << MSSShift);
2411         }
2412         if (skb->ip_summed == CHECKSUM_PARTIAL) {
2413                 const struct iphdr *ip = ip_hdr(skb);
2414
2415                 if (ip->protocol == IPPROTO_TCP)
2416                         return IPCS | TCPCS;
2417                 else if (ip->protocol == IPPROTO_UDP)
2418                         return IPCS | UDPCS;
2419                 WARN_ON(1);     /* we need a WARN() */
2420         }
2421         return 0;
2422 }
2423
2424 static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev)
2425 {
2426         struct rtl8169_private *tp = netdev_priv(dev);
2427         unsigned int frags, entry = tp->cur_tx % NUM_TX_DESC;
2428         struct TxDesc *txd = tp->TxDescArray + entry;
2429         void __iomem *ioaddr = tp->mmio_addr;
2430         dma_addr_t mapping;
2431         u32 status, len;
2432         u32 opts1;
2433         int ret = NETDEV_TX_OK;
2434
2435         if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
2436                 if (netif_msg_drv(tp)) {
2437                         printk(KERN_ERR
2438                                "%s: BUG! Tx Ring full when queue awake!\n",
2439                                dev->name);
2440                 }
2441                 goto err_stop;
2442         }
2443
2444         if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
2445                 goto err_stop;
2446
2447         opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
2448
2449         frags = rtl8169_xmit_frags(tp, skb, opts1);
2450         if (frags) {
2451                 len = skb_headlen(skb);
2452                 opts1 |= FirstFrag;
2453         } else {
2454                 len = skb->len;
2455
2456                 if (unlikely(len < ETH_ZLEN)) {
2457                         if (skb_padto(skb, ETH_ZLEN))
2458                                 goto err_update_stats;
2459                         len = ETH_ZLEN;
2460                 }
2461
2462                 opts1 |= FirstFrag | LastFrag;
2463                 tp->tx_skb[entry].skb = skb;
2464         }
2465
2466         mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
2467
2468         tp->tx_skb[entry].len = len;
2469         txd->addr = cpu_to_le64(mapping);
2470         txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
2471
2472         wmb();
2473
2474         /* anti gcc 2.95.3 bugware (sic) */
2475         status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
2476         txd->opts1 = cpu_to_le32(status);
2477
2478         dev->trans_start = jiffies;
2479
2480         tp->cur_tx += frags + 1;
2481
2482         smp_wmb();
2483
2484         RTL_W8(TxPoll, NPQ);    /* set polling bit */
2485
2486         if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
2487                 netif_stop_queue(dev);
2488                 smp_rmb();
2489                 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
2490                         netif_wake_queue(dev);
2491         }
2492
2493 out:
2494         return ret;
2495
2496 err_stop:
2497         netif_stop_queue(dev);
2498         ret = NETDEV_TX_BUSY;
2499 err_update_stats:
2500         tp->stats.tx_dropped++;
2501         goto out;
2502 }
2503
2504 static void rtl8169_pcierr_interrupt(struct net_device *dev)
2505 {
2506         struct rtl8169_private *tp = netdev_priv(dev);
2507         struct pci_dev *pdev = tp->pci_dev;
2508         void __iomem *ioaddr = tp->mmio_addr;
2509         u16 pci_status, pci_cmd;
2510
2511         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2512         pci_read_config_word(pdev, PCI_STATUS, &pci_status);
2513
2514         if (netif_msg_intr(tp)) {
2515                 printk(KERN_ERR
2516                        "%s: PCI error (cmd = 0x%04x, status = 0x%04x).\n",
2517                        dev->name, pci_cmd, pci_status);
2518         }
2519
2520         /*
2521          * The recovery sequence below admits a very elaborated explanation:
2522          * - it seems to work;
2523          * - I did not see what else could be done;
2524          * - it makes iop3xx happy.
2525          *
2526          * Feel free to adjust to your needs.
2527          */
2528         if (pdev->broken_parity_status)
2529                 pci_cmd &= ~PCI_COMMAND_PARITY;
2530         else
2531                 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
2532
2533         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
2534
2535         pci_write_config_word(pdev, PCI_STATUS,
2536                 pci_status & (PCI_STATUS_DETECTED_PARITY |
2537                 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
2538                 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
2539
2540         /* The infamous DAC f*ckup only happens at boot time */
2541         if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
2542                 if (netif_msg_intr(tp))
2543                         printk(KERN_INFO "%s: disabling PCI DAC.\n", dev->name);
2544                 tp->cp_cmd &= ~PCIDAC;
2545                 RTL_W16(CPlusCmd, tp->cp_cmd);
2546                 dev->features &= ~NETIF_F_HIGHDMA;
2547         }
2548
2549         rtl8169_hw_reset(ioaddr);
2550
2551         rtl8169_schedule_work(dev, rtl8169_reinit_task);
2552 }
2553
2554 static void rtl8169_tx_interrupt(struct net_device *dev,
2555                                  struct rtl8169_private *tp,
2556                                  void __iomem *ioaddr)
2557 {
2558         unsigned int dirty_tx, tx_left;
2559
2560         dirty_tx = tp->dirty_tx;
2561         smp_rmb();
2562         tx_left = tp->cur_tx - dirty_tx;
2563
2564         while (tx_left > 0) {
2565                 unsigned int entry = dirty_tx % NUM_TX_DESC;
2566                 struct ring_info *tx_skb = tp->tx_skb + entry;
2567                 u32 len = tx_skb->len;
2568                 u32 status;
2569
2570                 rmb();
2571                 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
2572                 if (status & DescOwn)
2573                         break;
2574
2575                 tp->stats.tx_bytes += len;
2576                 tp->stats.tx_packets++;
2577
2578                 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, tp->TxDescArray + entry);
2579
2580                 if (status & LastFrag) {
2581                         dev_kfree_skb_irq(tx_skb->skb);
2582                         tx_skb->skb = NULL;
2583                 }
2584                 dirty_tx++;
2585                 tx_left--;
2586         }
2587
2588         if (tp->dirty_tx != dirty_tx) {
2589                 tp->dirty_tx = dirty_tx;
2590                 smp_wmb();
2591                 if (netif_queue_stopped(dev) &&
2592                     (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
2593                         netif_wake_queue(dev);
2594                 }
2595                 /*
2596                  * 8168 hack: TxPoll requests are lost when the Tx packets are
2597                  * too close. Let's kick an extra TxPoll request when a burst
2598                  * of start_xmit activity is detected (if it is not detected,
2599                  * it is slow enough). -- FR
2600                  */
2601                 smp_rmb();
2602                 if (tp->cur_tx != dirty_tx)
2603                         RTL_W8(TxPoll, NPQ);
2604         }
2605 }
2606
2607 static inline int rtl8169_fragmented_frame(u32 status)
2608 {
2609         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
2610 }
2611
2612 static inline void rtl8169_rx_csum(struct sk_buff *skb, struct RxDesc *desc)
2613 {
2614         u32 opts1 = le32_to_cpu(desc->opts1);
2615         u32 status = opts1 & RxProtoMask;
2616
2617         if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
2618             ((status == RxProtoUDP) && !(opts1 & UDPFail)) ||
2619             ((status == RxProtoIP) && !(opts1 & IPFail)))
2620                 skb->ip_summed = CHECKSUM_UNNECESSARY;
2621         else
2622                 skb->ip_summed = CHECKSUM_NONE;
2623 }
2624
2625 static inline bool rtl8169_try_rx_copy(struct sk_buff **sk_buff,
2626                                        struct rtl8169_private *tp, int pkt_size,
2627                                        dma_addr_t addr)
2628 {
2629         struct sk_buff *skb;
2630         bool done = false;
2631
2632         if (pkt_size >= rx_copybreak)
2633                 goto out;
2634
2635         skb = netdev_alloc_skb(tp->dev, pkt_size + NET_IP_ALIGN);
2636         if (!skb)
2637                 goto out;
2638
2639         pci_dma_sync_single_for_cpu(tp->pci_dev, addr, pkt_size,
2640                                     PCI_DMA_FROMDEVICE);
2641         skb_reserve(skb, NET_IP_ALIGN);
2642         skb_copy_from_linear_data(*sk_buff, skb->data, pkt_size);
2643         *sk_buff = skb;
2644         done = true;
2645 out:
2646         return done;
2647 }
2648
2649 static int rtl8169_rx_interrupt(struct net_device *dev,
2650                                 struct rtl8169_private *tp,
2651                                 void __iomem *ioaddr, u32 budget)
2652 {
2653         unsigned int cur_rx, rx_left;
2654         unsigned int delta, count;
2655
2656         cur_rx = tp->cur_rx;
2657         rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
2658         rx_left = rtl8169_rx_quota(rx_left, budget);
2659
2660         for (; rx_left > 0; rx_left--, cur_rx++) {
2661                 unsigned int entry = cur_rx % NUM_RX_DESC;
2662                 struct RxDesc *desc = tp->RxDescArray + entry;
2663                 u32 status;
2664
2665                 rmb();
2666                 status = le32_to_cpu(desc->opts1);
2667
2668                 if (status & DescOwn)
2669                         break;
2670                 if (unlikely(status & RxRES)) {
2671                         if (netif_msg_rx_err(tp)) {
2672                                 printk(KERN_INFO
2673                                        "%s: Rx ERROR. status = %08x\n",
2674                                        dev->name, status);
2675                         }
2676                         tp->stats.rx_errors++;
2677                         if (status & (RxRWT | RxRUNT))
2678                                 tp->stats.rx_length_errors++;
2679                         if (status & RxCRC)
2680                                 tp->stats.rx_crc_errors++;
2681                         if (status & RxFOVF) {
2682                                 rtl8169_schedule_work(dev, rtl8169_reset_task);
2683                                 tp->stats.rx_fifo_errors++;
2684                         }
2685                         rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
2686                 } else {
2687                         struct sk_buff *skb = tp->Rx_skbuff[entry];
2688                         dma_addr_t addr = le64_to_cpu(desc->addr);
2689                         int pkt_size = (status & 0x00001FFF) - 4;
2690                         struct pci_dev *pdev = tp->pci_dev;
2691
2692                         /*
2693                          * The driver does not support incoming fragmented
2694                          * frames. They are seen as a symptom of over-mtu
2695                          * sized frames.
2696                          */
2697                         if (unlikely(rtl8169_fragmented_frame(status))) {
2698                                 tp->stats.rx_dropped++;
2699                                 tp->stats.rx_length_errors++;
2700                                 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
2701                                 continue;
2702                         }
2703
2704                         rtl8169_rx_csum(skb, desc);
2705
2706                         if (rtl8169_try_rx_copy(&skb, tp, pkt_size, addr)) {
2707                                 pci_dma_sync_single_for_device(pdev, addr,
2708                                         pkt_size, PCI_DMA_FROMDEVICE);
2709                                 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
2710                         } else {
2711                                 pci_unmap_single(pdev, addr, pkt_size,
2712                                                  PCI_DMA_FROMDEVICE);
2713                                 tp->Rx_skbuff[entry] = NULL;
2714                         }
2715
2716                         skb_put(skb, pkt_size);
2717                         skb->protocol = eth_type_trans(skb, dev);
2718
2719                         if (rtl8169_rx_vlan_skb(tp, desc, skb) < 0)
2720                                 rtl8169_rx_skb(skb);
2721
2722                         dev->last_rx = jiffies;
2723                         tp->stats.rx_bytes += pkt_size;
2724                         tp->stats.rx_packets++;
2725                 }
2726
2727                 /* Work around for AMD plateform. */
2728                 if ((desc->opts2 & 0xfffe000) &&
2729                     (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
2730                         desc->opts2 = 0;
2731                         cur_rx++;
2732                 }
2733         }
2734
2735         count = cur_rx - tp->cur_rx;
2736         tp->cur_rx = cur_rx;
2737
2738         delta = rtl8169_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx);
2739         if (!delta && count && netif_msg_intr(tp))
2740                 printk(KERN_INFO "%s: no Rx buffer allocated\n", dev->name);
2741         tp->dirty_rx += delta;
2742
2743         /*
2744          * FIXME: until there is periodic timer to try and refill the ring,
2745          * a temporary shortage may definitely kill the Rx process.
2746          * - disable the asic to try and avoid an overflow and kick it again
2747          *   after refill ?
2748          * - how do others driver handle this condition (Uh oh...).
2749          */
2750         if ((tp->dirty_rx + NUM_RX_DESC == tp->cur_rx) && netif_msg_intr(tp))
2751                 printk(KERN_EMERG "%s: Rx buffers exhausted\n", dev->name);
2752
2753         return count;
2754 }
2755
2756 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
2757 {
2758         struct net_device *dev = dev_instance;
2759         struct rtl8169_private *tp = netdev_priv(dev);
2760         int boguscnt = max_interrupt_work;
2761         void __iomem *ioaddr = tp->mmio_addr;
2762         int status;
2763         int handled = 0;
2764
2765         do {
2766                 status = RTL_R16(IntrStatus);
2767
2768                 /* hotplug/major error/no more work/shared irq */
2769                 if ((status == 0xFFFF) || !status)
2770                         break;
2771
2772                 handled = 1;
2773
2774                 if (unlikely(!netif_running(dev))) {
2775                         rtl8169_asic_down(ioaddr);
2776                         goto out;
2777                 }
2778
2779                 status &= tp->intr_mask;
2780                 RTL_W16(IntrStatus,
2781                         (status & RxFIFOOver) ? (status | RxOverflow) : status);
2782
2783                 if (!(status & tp->intr_event))
2784                         break;
2785
2786                 /* Work around for rx fifo overflow */
2787                 if (unlikely(status & RxFIFOOver) &&
2788                     (tp->mac_version == RTL_GIGA_MAC_VER_11)) {
2789                         netif_stop_queue(dev);
2790                         rtl8169_tx_timeout(dev);
2791                         break;
2792                 }
2793
2794                 if (unlikely(status & SYSErr)) {
2795                         rtl8169_pcierr_interrupt(dev);
2796                         break;
2797                 }
2798
2799                 if (status & LinkChg)
2800                         rtl8169_check_link_status(dev, tp, ioaddr);
2801
2802 #ifdef CONFIG_R8169_NAPI
2803                 if (status & tp->napi_event) {
2804                         RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
2805                         tp->intr_mask = ~tp->napi_event;
2806
2807                 if (likely(netif_rx_schedule_prep(dev, &tp->napi)))
2808                         __netif_rx_schedule(dev, &tp->napi);
2809                         else if (netif_msg_intr(tp)) {
2810                                 printk(KERN_INFO "%s: interrupt %04x in poll\n",
2811                                        dev->name, status);
2812                         }
2813                 }
2814                 break;
2815 #else
2816                 /* Rx interrupt */
2817                 if (status & (RxOK | RxOverflow | RxFIFOOver))
2818                         rtl8169_rx_interrupt(dev, tp, ioaddr, ~(u32)0);
2819
2820                 /* Tx interrupt */
2821                 if (status & (TxOK | TxErr))
2822                         rtl8169_tx_interrupt(dev, tp, ioaddr);
2823 #endif
2824
2825                 boguscnt--;
2826         } while (boguscnt > 0);
2827
2828         if (boguscnt <= 0) {
2829                 if (netif_msg_intr(tp) && net_ratelimit() ) {
2830                         printk(KERN_WARNING
2831                                "%s: Too much work at interrupt!\n", dev->name);
2832                 }
2833                 /* Clear all interrupt sources. */
2834                 RTL_W16(IntrStatus, 0xffff);
2835         }
2836 out:
2837         return IRQ_RETVAL(handled);
2838 }
2839
2840 #ifdef CONFIG_R8169_NAPI
2841 static int rtl8169_poll(struct napi_struct *napi, int budget)
2842 {
2843         struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
2844         struct net_device *dev = tp->dev;
2845         void __iomem *ioaddr = tp->mmio_addr;
2846         int work_done;
2847
2848         work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
2849         rtl8169_tx_interrupt(dev, tp, ioaddr);
2850
2851         if (work_done < budget) {
2852                 netif_rx_complete(dev, napi);
2853                 tp->intr_mask = 0xffff;
2854                 /*
2855                  * 20040426: the barrier is not strictly required but the
2856                  * behavior of the irq handler could be less predictable
2857                  * without it. Btw, the lack of flush for the posted pci
2858                  * write is safe - FR
2859                  */
2860                 smp_wmb();
2861                 RTL_W16(IntrMask, tp->intr_event);
2862         }
2863
2864         return work_done;
2865 }
2866 #endif
2867
2868 static void rtl8169_down(struct net_device *dev)
2869 {
2870         struct rtl8169_private *tp = netdev_priv(dev);
2871         void __iomem *ioaddr = tp->mmio_addr;
2872         unsigned int poll_locked = 0;
2873         unsigned int intrmask;
2874
2875         rtl8169_delete_timer(dev);
2876
2877         netif_stop_queue(dev);
2878
2879 core_down:
2880         spin_lock_irq(&tp->lock);
2881
2882         rtl8169_asic_down(ioaddr);
2883
2884         /* Update the error counts. */
2885         tp->stats.rx_missed_errors += RTL_R32(RxMissed);
2886         RTL_W32(RxMissed, 0);
2887
2888         spin_unlock_irq(&tp->lock);
2889
2890         synchronize_irq(dev->irq);
2891
2892         if (!poll_locked) {
2893                 napi_disable(&tp->napi);
2894                 poll_locked++;
2895         }
2896
2897         /* Give a racing hard_start_xmit a few cycles to complete. */
2898         synchronize_sched();  /* FIXME: should this be synchronize_irq()? */
2899
2900         /*
2901          * And now for the 50k$ question: are IRQ disabled or not ?
2902          *
2903          * Two paths lead here:
2904          * 1) dev->close
2905          *    -> netif_running() is available to sync the current code and the
2906          *       IRQ handler. See rtl8169_interrupt for details.
2907          * 2) dev->change_mtu
2908          *    -> rtl8169_poll can not be issued again and re-enable the
2909          *       interruptions. Let's simply issue the IRQ down sequence again.
2910          *
2911          * No loop if hotpluged or major error (0xffff).
2912          */
2913         intrmask = RTL_R16(IntrMask);
2914         if (intrmask && (intrmask != 0xffff))
2915                 goto core_down;
2916
2917         rtl8169_tx_clear(tp);
2918
2919         rtl8169_rx_clear(tp);
2920 }
2921
2922 static int rtl8169_close(struct net_device *dev)
2923 {
2924         struct rtl8169_private *tp = netdev_priv(dev);
2925         struct pci_dev *pdev = tp->pci_dev;
2926
2927         rtl8169_down(dev);
2928
2929         free_irq(dev->irq, dev);
2930
2931         pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
2932                             tp->RxPhyAddr);
2933         pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
2934                             tp->TxPhyAddr);
2935         tp->TxDescArray = NULL;
2936         tp->RxDescArray = NULL;
2937
2938         return 0;
2939 }
2940
2941 static void rtl_set_rx_mode(struct net_device *dev)
2942 {
2943         struct rtl8169_private *tp = netdev_priv(dev);
2944         void __iomem *ioaddr = tp->mmio_addr;
2945         unsigned long flags;
2946         u32 mc_filter[2];       /* Multicast hash filter */
2947         int rx_mode;
2948         u32 tmp = 0;
2949
2950         if (dev->flags & IFF_PROMISC) {
2951                 /* Unconditionally log net taps. */
2952                 if (netif_msg_link(tp)) {
2953                         printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n",
2954                                dev->name);
2955                 }
2956                 rx_mode =
2957                     AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
2958                     AcceptAllPhys;
2959                 mc_filter[1] = mc_filter[0] = 0xffffffff;
2960         } else if ((dev->mc_count > multicast_filter_limit)
2961                    || (dev->flags & IFF_ALLMULTI)) {
2962                 /* Too many to filter perfectly -- accept all multicasts. */
2963                 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
2964                 mc_filter[1] = mc_filter[0] = 0xffffffff;
2965         } else {
2966                 struct dev_mc_list *mclist;
2967                 unsigned int i;
2968
2969                 rx_mode = AcceptBroadcast | AcceptMyPhys;
2970                 mc_filter[1] = mc_filter[0] = 0;
2971                 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
2972                      i++, mclist = mclist->next) {
2973                         int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
2974                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2975                         rx_mode |= AcceptMulticast;
2976                 }
2977         }
2978
2979         spin_lock_irqsave(&tp->lock, flags);
2980
2981         tmp = rtl8169_rx_config | rx_mode |
2982               (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
2983
2984         if ((tp->mac_version == RTL_GIGA_MAC_VER_11) ||
2985             (tp->mac_version == RTL_GIGA_MAC_VER_12) ||
2986             (tp->mac_version == RTL_GIGA_MAC_VER_13) ||
2987             (tp->mac_version == RTL_GIGA_MAC_VER_14) ||
2988             (tp->mac_version == RTL_GIGA_MAC_VER_15)) {
2989                 mc_filter[0] = 0xffffffff;
2990                 mc_filter[1] = 0xffffffff;
2991         }
2992
2993         RTL_W32(MAR0 + 0, mc_filter[0]);
2994         RTL_W32(MAR0 + 4, mc_filter[1]);
2995
2996         RTL_W32(RxConfig, tmp);
2997
2998         spin_unlock_irqrestore(&tp->lock, flags);
2999 }
3000
3001 /**
3002  *  rtl8169_get_stats - Get rtl8169 read/write statistics
3003  *  @dev: The Ethernet Device to get statistics for
3004  *
3005  *  Get TX/RX statistics for rtl8169
3006  */
3007 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
3008 {
3009         struct rtl8169_private *tp = netdev_priv(dev);
3010         void __iomem *ioaddr = tp->mmio_addr;
3011         unsigned long flags;
3012
3013         if (netif_running(dev)) {
3014                 spin_lock_irqsave(&tp->lock, flags);
3015                 tp->stats.rx_missed_errors += RTL_R32(RxMissed);
3016                 RTL_W32(RxMissed, 0);
3017                 spin_unlock_irqrestore(&tp->lock, flags);
3018         }
3019
3020         return &tp->stats;
3021 }
3022
3023 #ifdef CONFIG_PM
3024
3025 static int rtl8169_suspend(struct pci_dev *pdev, pm_message_t state)
3026 {
3027         struct net_device *dev = pci_get_drvdata(pdev);
3028         struct rtl8169_private *tp = netdev_priv(dev);
3029         void __iomem *ioaddr = tp->mmio_addr;
3030
3031         if (!netif_running(dev))
3032                 goto out_pci_suspend;
3033
3034         netif_device_detach(dev);
3035         netif_stop_queue(dev);
3036
3037         spin_lock_irq(&tp->lock);
3038
3039         rtl8169_asic_down(ioaddr);
3040
3041         tp->stats.rx_missed_errors += RTL_R32(RxMissed);
3042         RTL_W32(RxMissed, 0);
3043
3044         spin_unlock_irq(&tp->lock);
3045
3046 out_pci_suspend:
3047         pci_save_state(pdev);
3048         pci_enable_wake(pdev, pci_choose_state(pdev, state), tp->wol_enabled);
3049         pci_set_power_state(pdev, pci_choose_state(pdev, state));
3050
3051         return 0;
3052 }
3053
3054 static int rtl8169_resume(struct pci_dev *pdev)
3055 {
3056         struct net_device *dev = pci_get_drvdata(pdev);
3057
3058         pci_set_power_state(pdev, PCI_D0);
3059         pci_restore_state(pdev);
3060         pci_enable_wake(pdev, PCI_D0, 0);
3061
3062         if (!netif_running(dev))
3063                 goto out;
3064
3065         netif_device_attach(dev);
3066
3067         rtl8169_schedule_work(dev, rtl8169_reset_task);
3068 out:
3069         return 0;
3070 }
3071
3072 #endif /* CONFIG_PM */
3073
3074 static struct pci_driver rtl8169_pci_driver = {
3075         .name           = MODULENAME,
3076         .id_table       = rtl8169_pci_tbl,
3077         .probe          = rtl8169_init_one,
3078         .remove         = __devexit_p(rtl8169_remove_one),
3079 #ifdef CONFIG_PM
3080         .suspend        = rtl8169_suspend,
3081         .resume         = rtl8169_resume,
3082 #endif
3083 };
3084
3085 static int __init rtl8169_init_module(void)
3086 {
3087         return pci_register_driver(&rtl8169_pci_driver);
3088 }
3089
3090 static void __exit rtl8169_cleanup_module(void)
3091 {
3092         pci_unregister_driver(&rtl8169_pci_driver);
3093 }
3094
3095 module_init(rtl8169_init_module);
3096 module_exit(rtl8169_cleanup_module);