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   1 /*
   2  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
   3  *
   4  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
   5  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
   6  * Copyright (c) a lot of people too. Please respect their work.
   7  *
   8  * See MAINTAINERS file for support contact information.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/moduleparam.h>
  13 #include <linux/pci.h>
  14 #include <linux/netdevice.h>
  15 #include <linux/etherdevice.h>
  16 #include <linux/delay.h>
  17 #include <linux/ethtool.h>
  18 #include <linux/mii.h>
  19 #include <linux/if_vlan.h>
  20 #include <linux/crc32.h>
  21 #include <linux/in.h>
  22 #include <linux/ip.h>
  23 #include <linux/tcp.h>
  24 #include <linux/init.h>
  25 #include <linux/dma-mapping.h>
  26
  27 #include <asm/system.h>
  28 #include <asm/io.h>
  29 #include <asm/irq.h>
  30
  31 #ifdef CONFIG_R8169_NAPI
  32 #define NAPI_SUFFIX     "-NAPI"
  33 #else
  34 #define NAPI_SUFFIX     ""
  35 #endif
  36
  37 #define RTL8169_VERSION "2.2LK" NAPI_SUFFIX
  38 #define MODULENAME "r8169"
  39 #define PFX MODULENAME ": "
  40
  41 #ifdef RTL8169_DEBUG
  42 #define assert(expr) \
  43         if (!(expr)) {                                  \
  44                 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
  45                 #expr,__FILE__,__FUNCTION__,__LINE__);          \
  46         }
  47 #define dprintk(fmt, args...)   do { printk(PFX fmt, ## args); } while (0)
  48 #else
  49 #define assert(expr) do {} while (0)
  50 #define dprintk(fmt, args...)   do {} while (0)
  51 #endif /* RTL8169_DEBUG */
  52
  53 #define R8169_MSG_DEFAULT \
  54         (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
  55
  56 #define TX_BUFFS_AVAIL(tp) \
  57         (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
  58
  59 #ifdef CONFIG_R8169_NAPI
  60 #define rtl8169_rx_skb                  netif_receive_skb
  61 #define rtl8169_rx_hwaccel_skb          vlan_hwaccel_receive_skb
  62 #define rtl8169_rx_quota(count, quota)  min(count, quota)
  63 #else
  64 #define rtl8169_rx_skb                  netif_rx
  65 #define rtl8169_rx_hwaccel_skb          vlan_hwaccel_rx
  66 #define rtl8169_rx_quota(count, quota)  count
  67 #endif
  68
  69 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
  70 static const int max_interrupt_work = 20;
  71
  72 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  73    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
  74 static const int multicast_filter_limit = 32;
  75
  76 /* MAC address length */
  77 #define MAC_ADDR_LEN    6
  78
  79 #define RX_FIFO_THRESH  7       /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
  80 #define RX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
  81 #define TX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
  82 #define EarlyTxThld     0x3F    /* 0x3F means NO early transmit */
  83 #define RxPacketMaxSize 0x3FE8  /* 16K - 1 - ETH_HLEN - VLAN - CRC... */
  84 #define SafeMtu         0x1c20  /* ... actually life sucks beyond ~7k */
  85 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
  86
  87 #define R8169_REGS_SIZE         256
  88 #define R8169_NAPI_WEIGHT       64
  89 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
  90 #define NUM_RX_DESC     256     /* Number of Rx descriptor registers */
  91 #define RX_BUF_SIZE     1536    /* Rx Buffer size */
  92 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
  93 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
  94
  95 #define RTL8169_TX_TIMEOUT      (6*HZ)
  96 #define RTL8169_PHY_TIMEOUT     (10*HZ)
  97
  98 /* write/read MMIO register */
  99 #define RTL_W8(reg, val8)       writeb ((val8), ioaddr + (reg))
 100 #define RTL_W16(reg, val16)     writew ((val16), ioaddr + (reg))
 101 #define RTL_W32(reg, val32)     writel ((val32), ioaddr + (reg))
 102 #define RTL_R8(reg)             readb (ioaddr + (reg))
 103 #define RTL_R16(reg)            readw (ioaddr + (reg))
 104 #define RTL_R32(reg)            ((unsigned long) readl (ioaddr + (reg)))
 105
 106 enum mac_version {
 107         RTL_GIGA_MAC_VER_01 = 0x01, // 8169
 108         RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
 109         RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
 110         RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
 111         RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
 112         RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
 113         RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
 114         RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be 8168Bf
 115         RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb 8101Ec
 116         RTL_GIGA_MAC_VER_14 = 0x0e, // 8101
 117         RTL_GIGA_MAC_VER_15 = 0x0f  // 8101
 118 };
 119
 120 enum phy_version {
 121         RTL_GIGA_PHY_VER_C = 0x03, /* PHY Reg 0x03 bit0-3 == 0x0000 */
 122         RTL_GIGA_PHY_VER_D = 0x04, /* PHY Reg 0x03 bit0-3 == 0x0000 */
 123         RTL_GIGA_PHY_VER_E = 0x05, /* PHY Reg 0x03 bit0-3 == 0x0000 */
 124         RTL_GIGA_PHY_VER_F = 0x06, /* PHY Reg 0x03 bit0-3 == 0x0001 */
 125         RTL_GIGA_PHY_VER_G = 0x07, /* PHY Reg 0x03 bit0-3 == 0x0002 */
 126         RTL_GIGA_PHY_VER_H = 0x08, /* PHY Reg 0x03 bit0-3 == 0x0003 */
 127 };
 128
 129 #define _R(NAME,MAC,MASK) \
 130         { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
 131
 132 static const struct {
 133         const char *name;
 134         u8 mac_version;
 135         u32 RxConfigMask;       /* Clears the bits supported by this chip */
 136 } rtl_chip_info[] = {
 137         _R("RTL8169",           RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
 138         _R("RTL8169s",          RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
 139         _R("RTL8110s",          RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
 140         _R("RTL8169sb/8110sb",  RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
 141         _R("RTL8169sc/8110sc",  RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
 142         _R("RTL8169sc/8110sc",  RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
 143         _R("RTL8168b/8111b",    RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
 144         _R("RTL8168b/8111b",    RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
 145         _R("RTL8101e",          RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
 146         _R("RTL8100e",          RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
 147         _R("RTL8100e",          RTL_GIGA_MAC_VER_15, 0xff7e1880)  // PCI-E 8139
 148 };
 149 #undef _R
 150
 151 enum cfg_version {
 152         RTL_CFG_0 = 0x00,
 153         RTL_CFG_1,
 154         RTL_CFG_2
 155 };
 156
 157 static void rtl_hw_start_8169(struct net_device *);
 158 static void rtl_hw_start_8168(struct net_device *);
 159 static void rtl_hw_start_8101(struct net_device *);
 160
 161 static struct pci_device_id rtl8169_pci_tbl[] = {
 162         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8129), 0, 0, RTL_CFG_0 },
 163         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8136), 0, 0, RTL_CFG_2 },
 164         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8167), 0, 0, RTL_CFG_0 },
 165         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8168), 0, 0, RTL_CFG_1 },
 166         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8169), 0, 0, RTL_CFG_0 },
 167         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4300), 0, 0, RTL_CFG_0 },
 168         { PCI_DEVICE(0x1259,                    0xc107), 0, 0, RTL_CFG_0 },
 169         { PCI_DEVICE(0x16ec,                    0x0116), 0, 0, RTL_CFG_0 },
 170         { PCI_VENDOR_ID_LINKSYS,                0x1032,
 171                 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
 172         {0,},
 173 };
 174
 175 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
 176
 177 static int rx_copybreak = 200;
 178 static int use_dac;
 179 static struct {
 180         u32 msg_enable;
 181 } debug = { -1 };
 182
 183 enum rtl_registers {
 184         MAC0            = 0,    /* Ethernet hardware address. */
 185         MAC4            = 4,
 186         MAR0            = 8,    /* Multicast filter. */
 187         CounterAddrLow          = 0x10,
 188         CounterAddrHigh         = 0x14,
 189         TxDescStartAddrLow      = 0x20,
 190         TxDescStartAddrHigh     = 0x24,
 191         TxHDescStartAddrLow     = 0x28,
 192         TxHDescStartAddrHigh    = 0x2c,
 193         FLASH           = 0x30,
 194         ERSR            = 0x36,
 195         ChipCmd         = 0x37,
 196         TxPoll          = 0x38,
 197         IntrMask        = 0x3c,
 198         IntrStatus      = 0x3e,
 199         TxConfig        = 0x40,
 200         RxConfig        = 0x44,
 201         RxMissed        = 0x4c,
 202         Cfg9346         = 0x50,
 203         Config0         = 0x51,
 204         Config1         = 0x52,
 205         Config2         = 0x53,
 206         Config3         = 0x54,
 207         Config4         = 0x55,
 208         Config5         = 0x56,
 209         MultiIntr       = 0x5c,
 210         PHYAR           = 0x60,
 211         TBICSR          = 0x64,
 212         TBI_ANAR        = 0x68,
 213         TBI_LPAR        = 0x6a,
 214         PHYstatus       = 0x6c,
 215         RxMaxSize       = 0xda,
 216         CPlusCmd        = 0xe0,
 217         IntrMitigate    = 0xe2,
 218         RxDescAddrLow   = 0xe4,
 219         RxDescAddrHigh  = 0xe8,
 220         EarlyTxThres    = 0xec,
 221         FuncEvent       = 0xf0,
 222         FuncEventMask   = 0xf4,
 223         FuncPresetState = 0xf8,
 224         FuncForceEvent  = 0xfc,
 225 };
 226
 227 enum rtl_register_content {
 228         /* InterruptStatusBits */
 229         SYSErr          = 0x8000,
 230         PCSTimeout      = 0x4000,
 231         SWInt           = 0x0100,
 232         TxDescUnavail   = 0x0080,
 233         RxFIFOOver      = 0x0040,
 234         LinkChg         = 0x0020,
 235         RxOverflow      = 0x0010,
 236         TxErr           = 0x0008,
 237         TxOK            = 0x0004,
 238         RxErr           = 0x0002,
 239         RxOK            = 0x0001,
 240
 241         /* RxStatusDesc */
 242         RxFOVF  = (1 << 23),
 243         RxRWT   = (1 << 22),
 244         RxRES   = (1 << 21),
 245         RxRUNT  = (1 << 20),
 246         RxCRC   = (1 << 19),
 247
 248         /* ChipCmdBits */
 249         CmdReset        = 0x10,
 250         CmdRxEnb        = 0x08,
 251         CmdTxEnb        = 0x04,
 252         RxBufEmpty      = 0x01,
 253
 254         /* TXPoll register p.5 */
 255         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
 256         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
 257         FSWInt          = 0x01,         /* Forced software interrupt */
 258
 259         /* Cfg9346Bits */
 260         Cfg9346_Lock    = 0x00,
 261         Cfg9346_Unlock  = 0xc0,
 262
 263         /* rx_mode_bits */
 264         AcceptErr       = 0x20,
 265         AcceptRunt      = 0x10,
 266         AcceptBroadcast = 0x08,
 267         AcceptMulticast = 0x04,
 268         AcceptMyPhys    = 0x02,
 269         AcceptAllPhys   = 0x01,
 270
 271         /* RxConfigBits */
 272         RxCfgFIFOShift  = 13,
 273         RxCfgDMAShift   =  8,
 274
 275         /* TxConfigBits */
 276         TxInterFrameGapShift = 24,
 277         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
 278
 279         /* Config1 register p.24 */
 280         PMEnable        = (1 << 0),     /* Power Management Enable */
 281
 282         /* Config2 register p. 25 */
 283         PCI_Clock_66MHz = 0x01,
 284         PCI_Clock_33MHz = 0x00,
 285
 286         /* Config3 register p.25 */
 287         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
 288         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
 289
 290         /* Config5 register p.27 */
 291         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
 292         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
 293         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
 294         LanWake         = (1 << 1),     /* LanWake enable/disable */
 295         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
 296
 297         /* TBICSR p.28 */
 298         TBIReset        = 0x80000000,
 299         TBILoopback     = 0x40000000,
 300         TBINwEnable     = 0x20000000,
 301         TBINwRestart    = 0x10000000,
 302         TBILinkOk       = 0x02000000,
 303         TBINwComplete   = 0x01000000,
 304
 305         /* CPlusCmd p.31 */
 306         PktCntrDisable  = (1 << 7),     // 8168
 307         RxVlan          = (1 << 6),
 308         RxChkSum        = (1 << 5),
 309         PCIDAC          = (1 << 4),
 310         PCIMulRW        = (1 << 3),
 311         INTT_0          = 0x0000,       // 8168
 312         INTT_1          = 0x0001,       // 8168
 313         INTT_2          = 0x0002,       // 8168
 314         INTT_3          = 0x0003,       // 8168
 315
 316         /* rtl8169_PHYstatus */
 317         TBI_Enable      = 0x80,
 318         TxFlowCtrl      = 0x40,
 319         RxFlowCtrl      = 0x20,
 320         _1000bpsF       = 0x10,
 321         _100bps         = 0x08,
 322         _10bps          = 0x04,
 323         LinkStatus      = 0x02,
 324         FullDup         = 0x01,
 325
 326         /* _TBICSRBit */
 327         TBILinkOK       = 0x02000000,
 328
 329         /* DumpCounterCommand */
 330         CounterDump     = 0x8,
 331 };
 332
 333 enum desc_status_bit {
 334         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
 335         RingEnd         = (1 << 30), /* End of descriptor ring */
 336         FirstFrag       = (1 << 29), /* First segment of a packet */
 337         LastFrag        = (1 << 28), /* Final segment of a packet */
 338
 339         /* Tx private */
 340         LargeSend       = (1 << 27), /* TCP Large Send Offload (TSO) */
 341         MSSShift        = 16,        /* MSS value position */
 342         MSSMask         = 0xfff,     /* MSS value + LargeSend bit: 12 bits */
 343         IPCS            = (1 << 18), /* Calculate IP checksum */
 344         UDPCS           = (1 << 17), /* Calculate UDP/IP checksum */
 345         TCPCS           = (1 << 16), /* Calculate TCP/IP checksum */
 346         TxVlanTag       = (1 << 17), /* Add VLAN tag */
 347
 348         /* Rx private */
 349         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
 350         PID0            = (1 << 17), /* Protocol ID bit 2/2 */
 351
 352 #define RxProtoUDP      (PID1)
 353 #define RxProtoTCP      (PID0)
 354 #define RxProtoIP       (PID1 | PID0)
 355 #define RxProtoMask     RxProtoIP
 356
 357         IPFail          = (1 << 16), /* IP checksum failed */
 358         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
 359         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
 360         RxVlanTag       = (1 << 16), /* VLAN tag available */
 361 };
 362
 363 #define RsvdMask        0x3fffc000
 364
 365 struct TxDesc {
 366         __le32 opts1;
 367         __le32 opts2;
 368         __le64 addr;
 369 };
 370
 371 struct RxDesc {
 372         __le32 opts1;
 373         __le32 opts2;
 374         __le64 addr;
 375 };
 376
 377 struct ring_info {
 378         struct sk_buff  *skb;
 379         u32             len;
 380         u8              __pad[sizeof(void *) - sizeof(u32)];
 381 };
 382
 383 struct rtl8169_private {
 384         void __iomem *mmio_addr;        /* memory map physical address */
 385         struct pci_dev *pci_dev;        /* Index of PCI device */
 386         struct net_device *dev;
 387         struct napi_struct napi;
 388         struct net_device_stats stats;  /* statistics of net device */
 389         spinlock_t lock;                /* spin lock flag */
 390         u32 msg_enable;
 391         int chipset;
 392         int mac_version;
 393         int phy_version;
 394         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
 395         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
 396         u32 dirty_rx;
 397         u32 dirty_tx;
 398         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
 399         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
 400         dma_addr_t TxPhyAddr;
 401         dma_addr_t RxPhyAddr;
 402         struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */
 403         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
 404         unsigned align;
 405         unsigned rx_buf_sz;
 406         struct timer_list timer;
 407         u16 cp_cmd;
 408         u16 intr_event;
 409         u16 napi_event;
 410         u16 intr_mask;
 411         int phy_auto_nego_reg;
 412         int phy_1000_ctrl_reg;
 413 #ifdef CONFIG_R8169_VLAN
 414         struct vlan_group *vlgrp;
 415 #endif
 416         int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
 417         void (*get_settings)(struct net_device *, struct ethtool_cmd *);
 418         void (*phy_reset_enable)(void __iomem *);
 419         void (*hw_start)(struct net_device *);
 420         unsigned int (*phy_reset_pending)(void __iomem *);
 421         unsigned int (*link_ok)(void __iomem *);
 422         struct delayed_work task;
 423         unsigned wol_enabled : 1;
 424 };
 425
 426 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
 427 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
 428 module_param(rx_copybreak, int, 0);
 429 MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
 430 module_param(use_dac, int, 0);
 431 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
 432 module_param_named(debug, debug.msg_enable, int, 0);
 433 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
 434 MODULE_LICENSE("GPL");
 435 MODULE_VERSION(RTL8169_VERSION);
 436
 437 static int rtl8169_open(struct net_device *dev);
 438 static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev);
 439 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
 440 static int rtl8169_init_ring(struct net_device *dev);
 441 static void rtl_hw_start(struct net_device *dev);
 442 static int rtl8169_close(struct net_device *dev);
 443 static void rtl_set_rx_mode(struct net_device *dev);
 444 static void rtl8169_tx_timeout(struct net_device *dev);
 445 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
 446 static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
 447                                 void __iomem *, u32 budget);
 448 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
 449 static void rtl8169_down(struct net_device *dev);
 450 static void rtl8169_rx_clear(struct rtl8169_private *tp);
 451
 452 #ifdef CONFIG_R8169_NAPI
 453 static int rtl8169_poll(struct napi_struct *napi, int budget);
 454 #endif
 455
 456 static const unsigned int rtl8169_rx_config =
 457         (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
 458
 459 static void mdio_write(void __iomem *ioaddr, int reg_addr, int value)
 460 {
 461         int i;
 462
 463         RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0xFF) << 16 | value);
 464
 465         for (i = 20; i > 0; i--) {
 466                 /*
 467                  * Check if the RTL8169 has completed writing to the specified
 468                  * MII register.
 469                  */
 470                 if (!(RTL_R32(PHYAR) & 0x80000000))
 471                         break;
 472                 udelay(25);
 473         }
 474 }
 475
 476 static int mdio_read(void __iomem *ioaddr, int reg_addr)
 477 {
 478         int i, value = -1;
 479
 480         RTL_W32(PHYAR, 0x0 | (reg_addr & 0xFF) << 16);
 481
 482         for (i = 20; i > 0; i--) {
 483                 /*
 484                  * Check if the RTL8169 has completed retrieving data from
 485                  * the specified MII register.
 486                  */
 487                 if (RTL_R32(PHYAR) & 0x80000000) {
 488                         value = (int) (RTL_R32(PHYAR) & 0xFFFF);
 489                         break;
 490                 }
 491                 udelay(25);
 492         }
 493         return value;
 494 }
 495
 496 static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
 497 {
 498         RTL_W16(IntrMask, 0x0000);
 499
 500         RTL_W16(IntrStatus, 0xffff);
 501 }
 502
 503 static void rtl8169_asic_down(void __iomem *ioaddr)
 504 {
 505         RTL_W8(ChipCmd, 0x00);
 506         rtl8169_irq_mask_and_ack(ioaddr);
 507         RTL_R16(CPlusCmd);
 508 }
 509
 510 static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr)
 511 {
 512         return RTL_R32(TBICSR) & TBIReset;
 513 }
 514
 515 static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr)
 516 {
 517         return mdio_read(ioaddr, MII_BMCR) & BMCR_RESET;
 518 }
 519
 520 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
 521 {
 522         return RTL_R32(TBICSR) & TBILinkOk;
 523 }
 524
 525 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
 526 {
 527         return RTL_R8(PHYstatus) & LinkStatus;
 528 }
 529
 530 static void rtl8169_tbi_reset_enable(void __iomem *ioaddr)
 531 {
 532         RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
 533 }
 534
 535 static void rtl8169_xmii_reset_enable(void __iomem *ioaddr)
 536 {
 537         unsigned int val;
 538
 539         val = mdio_read(ioaddr, MII_BMCR) | BMCR_RESET;
 540         mdio_write(ioaddr, MII_BMCR, val & 0xffff);
 541 }
 542
 543 static void rtl8169_check_link_status(struct net_device *dev,
 544                                       struct rtl8169_private *tp,
 545                                       void __iomem *ioaddr)
 546 {
 547         unsigned long flags;
 548
 549         spin_lock_irqsave(&tp->lock, flags);
 550         if (tp->link_ok(ioaddr)) {
 551                 netif_carrier_on(dev);
 552                 if (netif_msg_ifup(tp))
 553                         printk(KERN_INFO PFX "%s: link up\n", dev->name);
 554         } else {
 555                 if (netif_msg_ifdown(tp))
 556                         printk(KERN_INFO PFX "%s: link down\n", dev->name);
 557                 netif_carrier_off(dev);
 558         }
 559         spin_unlock_irqrestore(&tp->lock, flags);
 560 }
 561
 562 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
 563 {
 564         struct rtl8169_private *tp = netdev_priv(dev);
 565         void __iomem *ioaddr = tp->mmio_addr;
 566         u8 options;
 567
 568         wol->wolopts = 0;
 569
 570 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
 571         wol->supported = WAKE_ANY;
 572
 573         spin_lock_irq(&tp->lock);
 574
 575         options = RTL_R8(Config1);
 576         if (!(options & PMEnable))
 577                 goto out_unlock;
 578
 579         options = RTL_R8(Config3);
 580         if (options & LinkUp)
 581                 wol->wolopts |= WAKE_PHY;
 582         if (options & MagicPacket)
 583                 wol->wolopts |= WAKE_MAGIC;
 584
 585         options = RTL_R8(Config5);
 586         if (options & UWF)
 587                 wol->wolopts |= WAKE_UCAST;
 588         if (options & BWF)
 589                 wol->wolopts |= WAKE_BCAST;
 590         if (options & MWF)
 591                 wol->wolopts |= WAKE_MCAST;
 592
 593 out_unlock:
 594         spin_unlock_irq(&tp->lock);
 595 }
 596
 597 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
 598 {
 599         struct rtl8169_private *tp = netdev_priv(dev);
 600         void __iomem *ioaddr = tp->mmio_addr;
 601         unsigned int i;
 602         static struct {
 603                 u32 opt;
 604                 u16 reg;
 605                 u8  mask;
 606         } cfg[] = {
 607                 { WAKE_ANY,   Config1, PMEnable },
 608                 { WAKE_PHY,   Config3, LinkUp },
 609                 { WAKE_MAGIC, Config3, MagicPacket },
 610                 { WAKE_UCAST, Config5, UWF },
 611                 { WAKE_BCAST, Config5, BWF },
 612                 { WAKE_MCAST, Config5, MWF },
 613                 { WAKE_ANY,   Config5, LanWake }
 614         };
 615
 616         spin_lock_irq(&tp->lock);
 617
 618         RTL_W8(Cfg9346, Cfg9346_Unlock);
 619
 620         for (i = 0; i < ARRAY_SIZE(cfg); i++) {
 621                 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
 622                 if (wol->wolopts & cfg[i].opt)
 623                         options |= cfg[i].mask;
 624                 RTL_W8(cfg[i].reg, options);
 625         }
 626
 627         RTL_W8(Cfg9346, Cfg9346_Lock);
 628
 629         tp->wol_enabled = (wol->wolopts) ? 1 : 0;
 630
 631         spin_unlock_irq(&tp->lock);
 632
 633         return 0;
 634 }
 635
 636 static void rtl8169_get_drvinfo(struct net_device *dev,
 637                                 struct ethtool_drvinfo *info)
 638 {
 639         struct rtl8169_private *tp = netdev_priv(dev);
 640
 641         strcpy(info->driver, MODULENAME);
 642         strcpy(info->version, RTL8169_VERSION);
 643         strcpy(info->bus_info, pci_name(tp->pci_dev));
 644 }
 645
 646 static int rtl8169_get_regs_len(struct net_device *dev)
 647 {
 648         return R8169_REGS_SIZE;
 649 }
 650
 651 static int rtl8169_set_speed_tbi(struct net_device *dev,
 652                                  u8 autoneg, u16 speed, u8 duplex)
 653 {
 654         struct rtl8169_private *tp = netdev_priv(dev);
 655         void __iomem *ioaddr = tp->mmio_addr;
 656         int ret = 0;
 657         u32 reg;
 658
 659         reg = RTL_R32(TBICSR);
 660         if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
 661             (duplex == DUPLEX_FULL)) {
 662                 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
 663         } else if (autoneg == AUTONEG_ENABLE)
 664                 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
 665         else {
 666                 if (netif_msg_link(tp)) {
 667                         printk(KERN_WARNING "%s: "
 668                                "incorrect speed setting refused in TBI mode\n",
 669                                dev->name);
 670                 }
 671                 ret = -EOPNOTSUPP;
 672         }
 673
 674         return ret;
 675 }
 676
 677 static int rtl8169_set_speed_xmii(struct net_device *dev,
 678                                   u8 autoneg, u16 speed, u8 duplex)
 679 {
 680         struct rtl8169_private *tp = netdev_priv(dev);
 681         void __iomem *ioaddr = tp->mmio_addr;
 682         int auto_nego, giga_ctrl;
 683
 684         auto_nego = mdio_read(ioaddr, MII_ADVERTISE);
 685         auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
 686                        ADVERTISE_100HALF | ADVERTISE_100FULL);
 687         giga_ctrl = mdio_read(ioaddr, MII_CTRL1000);
 688         giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
 689
 690         if (autoneg == AUTONEG_ENABLE) {
 691                 auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
 692                               ADVERTISE_100HALF | ADVERTISE_100FULL);
 693                 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
 694         } else {
 695                 if (speed == SPEED_10)
 696                         auto_nego |= ADVERTISE_10HALF | ADVERTISE_10FULL;
 697                 else if (speed == SPEED_100)
 698                         auto_nego |= ADVERTISE_100HALF | ADVERTISE_100FULL;
 699                 else if (speed == SPEED_1000)
 700                         giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
 701
 702                 if (duplex == DUPLEX_HALF)
 703                         auto_nego &= ~(ADVERTISE_10FULL | ADVERTISE_100FULL);
 704
 705                 if (duplex == DUPLEX_FULL)
 706                         auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_100HALF);
 707
 708                 /* This tweak comes straight from Realtek's driver. */
 709                 if ((speed == SPEED_100) && (duplex == DUPLEX_HALF) &&
 710                     (tp->mac_version == RTL_GIGA_MAC_VER_13)) {
 711                         auto_nego = ADVERTISE_100HALF | ADVERTISE_CSMA;
 712                 }
 713         }
 714
 715         /* The 8100e/8101e do Fast Ethernet only. */
 716         if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
 717             (tp->mac_version == RTL_GIGA_MAC_VER_14) ||
 718             (tp->mac_version == RTL_GIGA_MAC_VER_15)) {
 719                 if ((giga_ctrl & (ADVERTISE_1000FULL | ADVERTISE_1000HALF)) &&
 720                     netif_msg_link(tp)) {
 721                         printk(KERN_INFO "%s: PHY does not support 1000Mbps.\n",
 722                                dev->name);
 723                 }
 724                 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
 725         }
 726
 727         auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
 728
 729         if (tp->mac_version == RTL_GIGA_MAC_VER_12) {
 730                 /* Vendor specific (0x1f) and reserved (0x0e) MII registers. */
 731                 mdio_write(ioaddr, 0x1f, 0x0000);
 732                 mdio_write(ioaddr, 0x0e, 0x0000);
 733         }
 734
 735         tp->phy_auto_nego_reg = auto_nego;
 736         tp->phy_1000_ctrl_reg = giga_ctrl;
 737
 738         mdio_write(ioaddr, MII_ADVERTISE, auto_nego);
 739         mdio_write(ioaddr, MII_CTRL1000, giga_ctrl);
 740         mdio_write(ioaddr, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART);
 741         return 0;
 742 }
 743
 744 static int rtl8169_set_speed(struct net_device *dev,
 745                              u8 autoneg, u16 speed, u8 duplex)
 746 {
 747         struct rtl8169_private *tp = netdev_priv(dev);
 748         int ret;
 749
 750         ret = tp->set_speed(dev, autoneg, speed, duplex);
 751
 752         if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
 753                 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
 754
 755         return ret;
 756 }
 757
 758 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 759 {
 760         struct rtl8169_private *tp = netdev_priv(dev);
 761         unsigned long flags;
 762         int ret;
 763
 764         spin_lock_irqsave(&tp->lock, flags);
 765         ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
 766         spin_unlock_irqrestore(&tp->lock, flags);
 767
 768         return ret;
 769 }
 770
 771 static u32 rtl8169_get_rx_csum(struct net_device *dev)
 772 {
 773         struct rtl8169_private *tp = netdev_priv(dev);
 774
 775         return tp->cp_cmd & RxChkSum;
 776 }
 777
 778 static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
 779 {
 780         struct rtl8169_private *tp = netdev_priv(dev);
 781         void __iomem *ioaddr = tp->mmio_addr;
 782         unsigned long flags;
 783
 784         spin_lock_irqsave(&tp->lock, flags);
 785
 786         if (data)
 787                 tp->cp_cmd |= RxChkSum;
 788         else
 789                 tp->cp_cmd &= ~RxChkSum;
 790
 791         RTL_W16(CPlusCmd, tp->cp_cmd);
 792         RTL_R16(CPlusCmd);
 793
 794         spin_unlock_irqrestore(&tp->lock, flags);
 795
 796         return 0;
 797 }
 798
 799 #ifdef CONFIG_R8169_VLAN
 800
 801 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
 802                                       struct sk_buff *skb)
 803 {
 804         return (tp->vlgrp && vlan_tx_tag_present(skb)) ?
 805                 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
 806 }
 807
 808 static void rtl8169_vlan_rx_register(struct net_device *dev,
 809                                      struct vlan_group *grp)
 810 {
 811         struct rtl8169_private *tp = netdev_priv(dev);
 812         void __iomem *ioaddr = tp->mmio_addr;
 813         unsigned long flags;
 814
 815         spin_lock_irqsave(&tp->lock, flags);
 816         tp->vlgrp = grp;
 817         if (tp->vlgrp)
 818                 tp->cp_cmd |= RxVlan;
 819         else
 820                 tp->cp_cmd &= ~RxVlan;
 821         RTL_W16(CPlusCmd, tp->cp_cmd);
 822         RTL_R16(CPlusCmd);
 823         spin_unlock_irqrestore(&tp->lock, flags);
 824 }
 825
 826 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
 827                                struct sk_buff *skb)
 828 {
 829         u32 opts2 = le32_to_cpu(desc->opts2);
 830         int ret;
 831
 832         if (tp->vlgrp && (opts2 & RxVlanTag)) {
 833                 rtl8169_rx_hwaccel_skb(skb, tp->vlgrp, swab16(opts2 & 0xffff));
 834                 ret = 0;
 835         } else
 836                 ret = -1;
 837         desc->opts2 = 0;
 838         return ret;
 839 }
 840
 841 #else /* !CONFIG_R8169_VLAN */
 842
 843 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
 844                                       struct sk_buff *skb)
 845 {
 846         return 0;
 847 }
 848
 849 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
 850                                struct sk_buff *skb)
 851 {
 852         return -1;
 853 }
 854
 855 #endif
 856
 857 static void rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
 858 {
 859         struct rtl8169_private *tp = netdev_priv(dev);
 860         void __iomem *ioaddr = tp->mmio_addr;
 861         u32 status;
 862
 863         cmd->supported =
 864                 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
 865         cmd->port = PORT_FIBRE;
 866         cmd->transceiver = XCVR_INTERNAL;
 867
 868         status = RTL_R32(TBICSR);
 869         cmd->advertising = (status & TBINwEnable) ?  ADVERTISED_Autoneg : 0;
 870         cmd->autoneg = !!(status & TBINwEnable);
 871
 872         cmd->speed = SPEED_1000;
 873         cmd->duplex = DUPLEX_FULL; /* Always set */
 874 }
 875
 876 static void rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
 877 {
 878         struct rtl8169_private *tp = netdev_priv(dev);
 879         void __iomem *ioaddr = tp->mmio_addr;
 880         u8 status;
 881
 882         cmd->supported = SUPPORTED_10baseT_Half |
 883                          SUPPORTED_10baseT_Full |
 884                          SUPPORTED_100baseT_Half |
 885                          SUPPORTED_100baseT_Full |
 886                          SUPPORTED_1000baseT_Full |
 887                          SUPPORTED_Autoneg |
 888                          SUPPORTED_TP;
 889
 890         cmd->autoneg = 1;
 891         cmd->advertising = ADVERTISED_TP | ADVERTISED_Autoneg;
 892
 893         if (tp->phy_auto_nego_reg & ADVERTISE_10HALF)
 894                 cmd->advertising |= ADVERTISED_10baseT_Half;
 895         if (tp->phy_auto_nego_reg & ADVERTISE_10FULL)
 896                 cmd->advertising |= ADVERTISED_10baseT_Full;
 897         if (tp->phy_auto_nego_reg & ADVERTISE_100HALF)
 898                 cmd->advertising |= ADVERTISED_100baseT_Half;
 899         if (tp->phy_auto_nego_reg & ADVERTISE_100FULL)
 900                 cmd->advertising |= ADVERTISED_100baseT_Full;
 901         if (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL)
 902                 cmd->advertising |= ADVERTISED_1000baseT_Full;
 903
 904         status = RTL_R8(PHYstatus);
 905
 906         if (status & _1000bpsF)
 907                 cmd->speed = SPEED_1000;
 908         else if (status & _100bps)
 909                 cmd->speed = SPEED_100;
 910         else if (status & _10bps)
 911                 cmd->speed = SPEED_10;
 912
 913         if (status & TxFlowCtrl)
 914                 cmd->advertising |= ADVERTISED_Asym_Pause;
 915         if (status & RxFlowCtrl)
 916                 cmd->advertising |= ADVERTISED_Pause;
 917
 918         cmd->duplex = ((status & _1000bpsF) || (status & FullDup)) ?
 919                       DUPLEX_FULL : DUPLEX_HALF;
 920 }
 921
 922 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 923 {
 924         struct rtl8169_private *tp = netdev_priv(dev);
 925         unsigned long flags;
 926
 927         spin_lock_irqsave(&tp->lock, flags);
 928
 929         tp->get_settings(dev, cmd);
 930
 931         spin_unlock_irqrestore(&tp->lock, flags);
 932         return 0;
 933 }
 934
 935 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
 936                              void *p)
 937 {
 938         struct rtl8169_private *tp = netdev_priv(dev);
 939         unsigned long flags;
 940
 941         if (regs->len > R8169_REGS_SIZE)
 942                 regs->len = R8169_REGS_SIZE;
 943
 944         spin_lock_irqsave(&tp->lock, flags);
 945         memcpy_fromio(p, tp->mmio_addr, regs->len);
 946         spin_unlock_irqrestore(&tp->lock, flags);
 947 }
 948
 949 static u32 rtl8169_get_msglevel(struct net_device *dev)
 950 {
 951         struct rtl8169_private *tp = netdev_priv(dev);
 952
 953         return tp->msg_enable;
 954 }
 955
 956 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
 957 {
 958         struct rtl8169_private *tp = netdev_priv(dev);
 959
 960         tp->msg_enable = value;
 961 }
 962
 963 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
 964         "tx_packets",
 965         "rx_packets",
 966         "tx_errors",
 967         "rx_errors",
 968         "rx_missed",
 969         "align_errors",
 970         "tx_single_collisions",
 971         "tx_multi_collisions",
 972         "unicast",
 973         "broadcast",
 974         "multicast",
 975         "tx_aborted",
 976         "tx_underrun",
 977 };
 978
 979 struct rtl8169_counters {
 980         u64     tx_packets;
 981         u64     rx_packets;
 982         u64     tx_errors;
 983         u32     rx_errors;
 984         u16     rx_missed;
 985         u16     align_errors;
 986         u32     tx_one_collision;
 987         u32     tx_multi_collision;
 988         u64     rx_unicast;
 989         u64     rx_broadcast;
 990         u32     rx_multicast;
 991         u16     tx_aborted;
 992         u16     tx_underun;
 993 };
 994
 995 static int rtl8169_get_stats_count(struct net_device *dev)
 996 {
 997         return ARRAY_SIZE(rtl8169_gstrings);
 998 }
 999
1000 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1001                                       struct ethtool_stats *stats, u64 *data)
1002 {
1003         struct rtl8169_private *tp = netdev_priv(dev);
1004         void __iomem *ioaddr = tp->mmio_addr;
1005         struct rtl8169_counters *counters;
1006         dma_addr_t paddr;
1007         u32 cmd;
1008
1009         ASSERT_RTNL();
1010
1011         counters = pci_alloc_consistent(tp->pci_dev, sizeof(*counters), &paddr);
1012         if (!counters)
1013                 return;
1014
1015         RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1016         cmd = (u64)paddr & DMA_32BIT_MASK;
1017         RTL_W32(CounterAddrLow, cmd);
1018         RTL_W32(CounterAddrLow, cmd | CounterDump);
1019
1020         while (RTL_R32(CounterAddrLow) & CounterDump) {
1021                 if (msleep_interruptible(1))
1022                         break;
1023         }
1024
1025         RTL_W32(CounterAddrLow, 0);
1026         RTL_W32(CounterAddrHigh, 0);
1027
1028         data[0] = le64_to_cpu(counters->tx_packets);
1029         data[1] = le64_to_cpu(counters->rx_packets);
1030         data[2] = le64_to_cpu(counters->tx_errors);
1031         data[3] = le32_to_cpu(counters->rx_errors);
1032         data[4] = le16_to_cpu(counters->rx_missed);
1033         data[5] = le16_to_cpu(counters->align_errors);
1034         data[6] = le32_to_cpu(counters->tx_one_collision);
1035         data[7] = le32_to_cpu(counters->tx_multi_collision);
1036         data[8] = le64_to_cpu(counters->rx_unicast);
1037         data[9] = le64_to_cpu(counters->rx_broadcast);
1038         data[10] = le32_to_cpu(counters->rx_multicast);
1039         data[11] = le16_to_cpu(counters->tx_aborted);
1040         data[12] = le16_to_cpu(counters->tx_underun);
1041
1042         pci_free_consistent(tp->pci_dev, sizeof(*counters), counters, paddr);
1043 }
1044
1045 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1046 {
1047         switch(stringset) {
1048         case ETH_SS_STATS:
1049                 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1050                 break;
1051         }
1052 }
1053
1054 static const struct ethtool_ops rtl8169_ethtool_ops = {
1055         .get_drvinfo            = rtl8169_get_drvinfo,
1056         .get_regs_len           = rtl8169_get_regs_len,
1057         .get_link               = ethtool_op_get_link,
1058         .get_settings           = rtl8169_get_settings,
1059         .set_settings           = rtl8169_set_settings,
1060         .get_msglevel           = rtl8169_get_msglevel,
1061         .set_msglevel           = rtl8169_set_msglevel,
1062         .get_rx_csum            = rtl8169_get_rx_csum,
1063         .set_rx_csum            = rtl8169_set_rx_csum,
1064         .get_tx_csum            = ethtool_op_get_tx_csum,
1065         .set_tx_csum            = ethtool_op_set_tx_csum,
1066         .get_sg                 = ethtool_op_get_sg,
1067         .set_sg                 = ethtool_op_set_sg,
1068         .get_tso                = ethtool_op_get_tso,
1069         .set_tso                = ethtool_op_set_tso,
1070         .get_regs               = rtl8169_get_regs,
1071         .get_wol                = rtl8169_get_wol,
1072         .set_wol                = rtl8169_set_wol,
1073         .get_strings            = rtl8169_get_strings,
1074         .get_stats_count        = rtl8169_get_stats_count,
1075         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
1076 };
1077
1078 static void rtl8169_write_gmii_reg_bit(void __iomem *ioaddr, int reg,
1079                                        int bitnum, int bitval)
1080 {
1081         int val;
1082
1083         val = mdio_read(ioaddr, reg);
1084         val = (bitval == 1) ?
1085                 val | (bitval << bitnum) :  val & ~(0x0001 << bitnum);
1086         mdio_write(ioaddr, reg, val & 0xffff);
1087 }
1088
1089 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1090                                     void __iomem *ioaddr)
1091 {
1092         /*
1093          * The driver currently handles the 8168Bf and the 8168Be identically
1094          * but they can be identified more specifically through the test below
1095          * if needed:
1096          *
1097          * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1098          *
1099          * Same thing for the 8101Eb and the 8101Ec:
1100          *
1101          * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1102          */
1103         const struct {
1104                 u32 mask;
1105                 int mac_version;
1106         } mac_info[] = {
1107                 { 0x38800000,   RTL_GIGA_MAC_VER_15 },
1108                 { 0x38000000,   RTL_GIGA_MAC_VER_12 },
1109                 { 0x34000000,   RTL_GIGA_MAC_VER_13 },
1110                 { 0x30800000,   RTL_GIGA_MAC_VER_14 },
1111                 { 0x30000000,   RTL_GIGA_MAC_VER_11 },
1112                 { 0x98000000,   RTL_GIGA_MAC_VER_06 },
1113                 { 0x18000000,   RTL_GIGA_MAC_VER_05 },
1114                 { 0x10000000,   RTL_GIGA_MAC_VER_04 },
1115                 { 0x04000000,   RTL_GIGA_MAC_VER_03 },
1116                 { 0x00800000,   RTL_GIGA_MAC_VER_02 },
1117                 { 0x00000000,   RTL_GIGA_MAC_VER_01 }   /* Catch-all */
1118         }, *p = mac_info;
1119         u32 reg;
1120
1121         reg = RTL_R32(TxConfig) & 0xfc800000;
1122         while ((reg & p->mask) != p->mask)
1123                 p++;
1124         tp->mac_version = p->mac_version;
1125 }
1126
1127 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1128 {
1129         dprintk("mac_version = 0x%02x\n", tp->mac_version);
1130 }
1131
1132 static void rtl8169_get_phy_version(struct rtl8169_private *tp,
1133                                     void __iomem *ioaddr)
1134 {
1135         const struct {
1136                 u16 mask;
1137                 u16 set;
1138                 int phy_version;
1139         } phy_info[] = {
1140                 { 0x000f, 0x0002, RTL_GIGA_PHY_VER_G },
1141                 { 0x000f, 0x0001, RTL_GIGA_PHY_VER_F },
1142                 { 0x000f, 0x0000, RTL_GIGA_PHY_VER_E },
1143                 { 0x0000, 0x0000, RTL_GIGA_PHY_VER_D } /* Catch-all */
1144         }, *p = phy_info;
1145         u16 reg;
1146
1147         reg = mdio_read(ioaddr, MII_PHYSID2) & 0xffff;
1148         while ((reg & p->mask) != p->set)
1149                 p++;
1150         tp->phy_version = p->phy_version;
1151 }
1152
1153 static void rtl8169_print_phy_version(struct rtl8169_private *tp)
1154 {
1155         struct {
1156                 int version;
1157                 char *msg;
1158                 u32 reg;
1159         } phy_print[] = {
1160                 { RTL_GIGA_PHY_VER_G, "RTL_GIGA_PHY_VER_G", 0x0002 },
1161                 { RTL_GIGA_PHY_VER_F, "RTL_GIGA_PHY_VER_F", 0x0001 },
1162                 { RTL_GIGA_PHY_VER_E, "RTL_GIGA_PHY_VER_E", 0x0000 },
1163                 { RTL_GIGA_PHY_VER_D, "RTL_GIGA_PHY_VER_D", 0x0000 },
1164                 { 0, NULL, 0x0000 }
1165         }, *p;
1166
1167         for (p = phy_print; p->msg; p++) {
1168                 if (tp->phy_version == p->version) {
1169                         dprintk("phy_version == %s (%04x)\n", p->msg, p->reg);
1170                         return;
1171                 }
1172         }
1173         dprintk("phy_version == Unknown\n");
1174 }
1175
1176 static void rtl8169_hw_phy_config(struct net_device *dev)
1177 {
1178         struct rtl8169_private *tp = netdev_priv(dev);
1179         void __iomem *ioaddr = tp->mmio_addr;
1180         struct {
1181                 u16 regs[5]; /* Beware of bit-sign propagation */
1182         } phy_magic[5] = { {
1183                 { 0x0000,       //w 4 15 12 0
1184                   0x00a1,       //w 3 15 0 00a1
1185                   0x0008,       //w 2 15 0 0008
1186                   0x1020,       //w 1 15 0 1020
1187                   0x1000 } },{  //w 0 15 0 1000
1188                 { 0x7000,       //w 4 15 12 7
1189                   0xff41,       //w 3 15 0 ff41
1190                   0xde60,       //w 2 15 0 de60
1191                   0x0140,       //w 1 15 0 0140
1192                   0x0077 } },{  //w 0 15 0 0077
1193                 { 0xa000,       //w 4 15 12 a
1194                   0xdf01,       //w 3 15 0 df01
1195                   0xdf20,       //w 2 15 0 df20
1196                   0xff95,       //w 1 15 0 ff95
1197                   0xfa00 } },{  //w 0 15 0 fa00
1198                 { 0xb000,       //w 4 15 12 b
1199                   0xff41,       //w 3 15 0 ff41
1200                   0xde20,       //w 2 15 0 de20
1201                   0x0140,       //w 1 15 0 0140
1202                   0x00bb } },{  //w 0 15 0 00bb
1203                 { 0xf000,       //w 4 15 12 f
1204                   0xdf01,       //w 3 15 0 df01
1205                   0xdf20,       //w 2 15 0 df20
1206                   0xff95,       //w 1 15 0 ff95
1207                   0xbf00 }      //w 0 15 0 bf00
1208                 }
1209         }, *p = phy_magic;
1210         unsigned int i;
1211
1212         rtl8169_print_mac_version(tp);
1213         rtl8169_print_phy_version(tp);
1214
1215         if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1216                 return;
1217         if (tp->phy_version >= RTL_GIGA_PHY_VER_H)
1218                 return;
1219
1220         dprintk("MAC version != 0 && PHY version == 0 or 1\n");
1221         dprintk("Do final_reg2.cfg\n");
1222
1223         /* Shazam ! */
1224
1225         if (tp->mac_version == RTL_GIGA_MAC_VER_04) {
1226                 mdio_write(ioaddr, 31, 0x0002);
1227                 mdio_write(ioaddr,  1, 0x90d0);
1228                 mdio_write(ioaddr, 31, 0x0000);
1229                 return;
1230         }
1231
1232         if ((tp->mac_version != RTL_GIGA_MAC_VER_02) &&
1233             (tp->mac_version != RTL_GIGA_MAC_VER_03))
1234                 return;
1235
1236         mdio_write(ioaddr, 31, 0x0001);                 //w 31 2 0 1
1237         mdio_write(ioaddr, 21, 0x1000);                 //w 21 15 0 1000
1238         mdio_write(ioaddr, 24, 0x65c7);                 //w 24 15 0 65c7
1239         rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0);   //w 4 11 11 0
1240
1241         for (i = 0; i < ARRAY_SIZE(phy_magic); i++, p++) {
1242                 int val, pos = 4;
1243
1244                 val = (mdio_read(ioaddr, pos) & 0x0fff) | (p->regs[0] & 0xffff);
1245                 mdio_write(ioaddr, pos, val);
1246                 while (--pos >= 0)
1247                         mdio_write(ioaddr, pos, p->regs[4 - pos] & 0xffff);
1248                 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 1); //w 4 11 11 1
1249                 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1250         }
1251         mdio_write(ioaddr, 31, 0x0000); //w 31 2 0 0
1252 }
1253
1254 static void rtl8169_phy_timer(unsigned long __opaque)
1255 {
1256         struct net_device *dev = (struct net_device *)__opaque;
1257         struct rtl8169_private *tp = netdev_priv(dev);
1258         struct timer_list *timer = &tp->timer;
1259         void __iomem *ioaddr = tp->mmio_addr;
1260         unsigned long timeout = RTL8169_PHY_TIMEOUT;
1261
1262         assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1263         assert(tp->phy_version < RTL_GIGA_PHY_VER_H);
1264
1265         if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1266                 return;
1267
1268         spin_lock_irq(&tp->lock);
1269
1270         if (tp->phy_reset_pending(ioaddr)) {
1271                 /*
1272                  * A busy loop could burn quite a few cycles on nowadays CPU.
1273                  * Let's delay the execution of the timer for a few ticks.
1274                  */
1275                 timeout = HZ/10;
1276                 goto out_mod_timer;
1277         }
1278
1279         if (tp->link_ok(ioaddr))
1280                 goto out_unlock;
1281
1282         if (netif_msg_link(tp))
1283                 printk(KERN_WARNING "%s: PHY reset until link up\n", dev->name);
1284
1285         tp->phy_reset_enable(ioaddr);
1286
1287 out_mod_timer:
1288         mod_timer(timer, jiffies + timeout);
1289 out_unlock:
1290         spin_unlock_irq(&tp->lock);
1291 }
1292
1293 static inline void rtl8169_delete_timer(struct net_device *dev)
1294 {
1295         struct rtl8169_private *tp = netdev_priv(dev);
1296         struct timer_list *timer = &tp->timer;
1297
1298         if ((tp->mac_version <= RTL_GIGA_MAC_VER_01) ||
1299             (tp->phy_version >= RTL_GIGA_PHY_VER_H))
1300                 return;
1301
1302         del_timer_sync(timer);
1303 }
1304
1305 static inline void rtl8169_request_timer(struct net_device *dev)
1306 {
1307         struct rtl8169_private *tp = netdev_priv(dev);
1308         struct timer_list *timer = &tp->timer;
1309
1310         if ((tp->mac_version <= RTL_GIGA_MAC_VER_01) ||
1311             (tp->phy_version >= RTL_GIGA_PHY_VER_H))
1312                 return;
1313
1314         mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
1315 }
1316
1317 #ifdef CONFIG_NET_POLL_CONTROLLER
1318 /*
1319  * Polling 'interrupt' - used by things like netconsole to send skbs
1320  * without having to re-enable interrupts. It's not called while
1321  * the interrupt routine is executing.
1322  */
1323 static void rtl8169_netpoll(struct net_device *dev)
1324 {
1325         struct rtl8169_private *tp = netdev_priv(dev);
1326         struct pci_dev *pdev = tp->pci_dev;
1327
1328         disable_irq(pdev->irq);
1329         rtl8169_interrupt(pdev->irq, dev);
1330         enable_irq(pdev->irq);
1331 }
1332 #endif
1333
1334 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
1335                                   void __iomem *ioaddr)
1336 {
1337         iounmap(ioaddr);
1338         pci_release_regions(pdev);
1339         pci_disable_device(pdev);
1340         free_netdev(dev);
1341 }
1342
1343 static void rtl8169_phy_reset(struct net_device *dev,
1344                               struct rtl8169_private *tp)
1345 {
1346         void __iomem *ioaddr = tp->mmio_addr;
1347         unsigned int i;
1348
1349         tp->phy_reset_enable(ioaddr);
1350         for (i = 0; i < 100; i++) {
1351                 if (!tp->phy_reset_pending(ioaddr))
1352                         return;
1353                 msleep(1);
1354         }
1355         if (netif_msg_link(tp))
1356                 printk(KERN_ERR "%s: PHY reset failed.\n", dev->name);
1357 }
1358
1359 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
1360 {
1361         void __iomem *ioaddr = tp->mmio_addr;
1362
1363         rtl8169_hw_phy_config(dev);
1364
1365         dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1366         RTL_W8(0x82, 0x01);
1367
1368         pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
1369
1370         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
1371                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
1372
1373         if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
1374                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1375                 RTL_W8(0x82, 0x01);
1376                 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
1377                 mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0
1378         }
1379
1380         rtl8169_phy_reset(dev, tp);
1381
1382         /*
1383          * rtl8169_set_speed_xmii takes good care of the Fast Ethernet
1384          * only 8101. Don't panic.
1385          */
1386         rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL);
1387
1388         if ((RTL_R8(PHYstatus) & TBI_Enable) && netif_msg_link(tp))
1389                 printk(KERN_INFO PFX "%s: TBI auto-negotiating\n", dev->name);
1390 }
1391
1392 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
1393 {
1394         void __iomem *ioaddr = tp->mmio_addr;
1395         u32 high;
1396         u32 low;
1397
1398         low  = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
1399         high = addr[4] | (addr[5] << 8);
1400
1401         spin_lock_irq(&tp->lock);
1402
1403         RTL_W8(Cfg9346, Cfg9346_Unlock);
1404         RTL_W32(MAC0, low);
1405         RTL_W32(MAC4, high);
1406         RTL_W8(Cfg9346, Cfg9346_Lock);
1407
1408         spin_unlock_irq(&tp->lock);
1409 }
1410
1411 static int rtl_set_mac_address(struct net_device *dev, void *p)
1412 {
1413         struct rtl8169_private *tp = netdev_priv(dev);
1414         struct sockaddr *addr = p;
1415
1416         if (!is_valid_ether_addr(addr->sa_data))
1417                 return -EADDRNOTAVAIL;
1418
1419         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1420
1421         rtl_rar_set(tp, dev->dev_addr);
1422
1423         return 0;
1424 }
1425
1426 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1427 {
1428         struct rtl8169_private *tp = netdev_priv(dev);
1429         struct mii_ioctl_data *data = if_mii(ifr);
1430
1431         if (!netif_running(dev))
1432                 return -ENODEV;
1433
1434         switch (cmd) {
1435         case SIOCGMIIPHY:
1436                 data->phy_id = 32; /* Internal PHY */
1437                 return 0;
1438
1439         case SIOCGMIIREG:
1440                 data->val_out = mdio_read(tp->mmio_addr, data->reg_num & 0x1f);
1441                 return 0;
1442
1443         case SIOCSMIIREG:
1444                 if (!capable(CAP_NET_ADMIN))
1445                         return -EPERM;
1446                 mdio_write(tp->mmio_addr, data->reg_num & 0x1f, data->val_in);
1447                 return 0;
1448         }
1449         return -EOPNOTSUPP;
1450 }
1451
1452 static const struct rtl_cfg_info {
1453         void (*hw_start)(struct net_device *);
1454         unsigned int region;
1455         unsigned int align;
1456         u16 intr_event;
1457         u16 napi_event;
1458 } rtl_cfg_infos [] = {
1459         [RTL_CFG_0] = {
1460                 .hw_start       = rtl_hw_start_8169,
1461                 .region         = 1,
1462                 .align          = 0,
1463                 .intr_event     = SYSErr | LinkChg | RxOverflow |
1464                                   RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
1465                 .napi_event     = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow
1466         },
1467         [RTL_CFG_1] = {
1468                 .hw_start       = rtl_hw_start_8168,
1469                 .region         = 2,
1470                 .align          = 8,
1471                 .intr_event     = SYSErr | LinkChg | RxOverflow |
1472                                   TxErr | TxOK | RxOK | RxErr,
1473                 .napi_event     = TxErr | TxOK | RxOK | RxOverflow
1474         },
1475         [RTL_CFG_2] = {
1476                 .hw_start       = rtl_hw_start_8101,
1477                 .region         = 2,
1478                 .align          = 8,
1479                 .intr_event     = SYSErr | LinkChg | RxOverflow | PCSTimeout |
1480                                   RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
1481                 .napi_event     = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow
1482         }
1483 };
1484
1485 static int __devinit
1486 rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1487 {
1488         const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
1489         const unsigned int region = cfg->region;
1490         struct rtl8169_private *tp;
1491         struct net_device *dev;
1492         void __iomem *ioaddr;
1493         unsigned int i;
1494         int rc;
1495
1496         if (netif_msg_drv(&debug)) {
1497                 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
1498                        MODULENAME, RTL8169_VERSION);
1499         }
1500
1501         dev = alloc_etherdev(sizeof (*tp));
1502         if (!dev) {
1503                 if (netif_msg_drv(&debug))
1504                         dev_err(&pdev->dev, "unable to alloc new ethernet\n");
1505                 rc = -ENOMEM;
1506                 goto out;
1507         }
1508
1509         SET_NETDEV_DEV(dev, &pdev->dev);
1510         tp = netdev_priv(dev);
1511         tp->dev = dev;
1512         tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
1513
1514         /* enable device (incl. PCI PM wakeup and hotplug setup) */
1515         rc = pci_enable_device(pdev);
1516         if (rc < 0) {
1517                 if (netif_msg_probe(tp))
1518                         dev_err(&pdev->dev, "enable failure\n");
1519                 goto err_out_free_dev_1;
1520         }
1521
1522         rc = pci_set_mwi(pdev);
1523         if (rc < 0)
1524                 goto err_out_disable_2;
1525
1526         /* make sure PCI base addr 1 is MMIO */
1527         if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
1528                 if (netif_msg_probe(tp)) {
1529                         dev_err(&pdev->dev,
1530                                 "region #%d not an MMIO resource, aborting\n",
1531                                 region);
1532                 }
1533                 rc = -ENODEV;
1534                 goto err_out_mwi_3;
1535         }
1536
1537         /* check for weird/broken PCI region reporting */
1538         if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
1539                 if (netif_msg_probe(tp)) {
1540                         dev_err(&pdev->dev,
1541                                 "Invalid PCI region size(s), aborting\n");
1542                 }
1543                 rc = -ENODEV;
1544                 goto err_out_mwi_3;
1545         }
1546
1547         rc = pci_request_regions(pdev, MODULENAME);
1548         if (rc < 0) {
1549                 if (netif_msg_probe(tp))
1550                         dev_err(&pdev->dev, "could not request regions.\n");
1551                 goto err_out_mwi_3;
1552         }
1553
1554         tp->cp_cmd = PCIMulRW | RxChkSum;
1555
1556         if ((sizeof(dma_addr_t) > 4) &&
1557             !pci_set_dma_mask(pdev, DMA_64BIT_MASK) && use_dac) {
1558                 tp->cp_cmd |= PCIDAC;
1559                 dev->features |= NETIF_F_HIGHDMA;
1560         } else {
1561                 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1562                 if (rc < 0) {
1563                         if (netif_msg_probe(tp)) {
1564                                 dev_err(&pdev->dev,
1565                                         "DMA configuration failed.\n");
1566                         }
1567                         goto err_out_free_res_4;
1568                 }
1569         }
1570
1571         pci_set_master(pdev);
1572
1573         /* ioremap MMIO region */
1574         ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
1575         if (!ioaddr) {
1576                 if (netif_msg_probe(tp))
1577                         dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
1578                 rc = -EIO;
1579                 goto err_out_free_res_4;
1580         }
1581
1582         /* Unneeded ? Don't mess with Mrs. Murphy. */
1583         rtl8169_irq_mask_and_ack(ioaddr);
1584
1585         /* Soft reset the chip. */
1586         RTL_W8(ChipCmd, CmdReset);
1587
1588         /* Check that the chip has finished the reset. */
1589         for (i = 0; i < 100; i++) {
1590                 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1591                         break;
1592                 msleep_interruptible(1);
1593         }
1594
1595         /* Identify chip attached to board */
1596         rtl8169_get_mac_version(tp, ioaddr);
1597         rtl8169_get_phy_version(tp, ioaddr);
1598
1599         rtl8169_print_mac_version(tp);
1600         rtl8169_print_phy_version(tp);
1601
1602         for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--) {
1603                 if (tp->mac_version == rtl_chip_info[i].mac_version)
1604                         break;
1605         }
1606         if (i < 0) {
1607                 /* Unknown chip: assume array element #0, original RTL-8169 */
1608                 if (netif_msg_probe(tp)) {
1609                         dev_printk(KERN_DEBUG, &pdev->dev,
1610                                 "unknown chip version, assuming %s\n",
1611                                 rtl_chip_info[0].name);
1612                 }
1613                 i++;
1614         }
1615         tp->chipset = i;
1616
1617         RTL_W8(Cfg9346, Cfg9346_Unlock);
1618         RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
1619         RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
1620         RTL_W8(Cfg9346, Cfg9346_Lock);
1621
1622         if (RTL_R8(PHYstatus) & TBI_Enable) {
1623                 tp->set_speed = rtl8169_set_speed_tbi;
1624                 tp->get_settings = rtl8169_gset_tbi;
1625                 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
1626                 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
1627                 tp->link_ok = rtl8169_tbi_link_ok;
1628
1629                 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
1630         } else {
1631                 tp->set_speed = rtl8169_set_speed_xmii;
1632                 tp->get_settings = rtl8169_gset_xmii;
1633                 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
1634                 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
1635                 tp->link_ok = rtl8169_xmii_link_ok;
1636
1637                 dev->do_ioctl = rtl8169_ioctl;
1638         }
1639
1640         /* Get MAC address.  FIXME: read EEPROM */
1641         for (i = 0; i < MAC_ADDR_LEN; i++)
1642                 dev->dev_addr[i] = RTL_R8(MAC0 + i);
1643         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1644
1645         dev->open = rtl8169_open;
1646         dev->hard_start_xmit = rtl8169_start_xmit;
1647         dev->get_stats = rtl8169_get_stats;
1648         SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
1649         dev->stop = rtl8169_close;
1650         dev->tx_timeout = rtl8169_tx_timeout;
1651         dev->set_multicast_list = rtl_set_rx_mode;
1652         dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
1653         dev->irq = pdev->irq;
1654         dev->base_addr = (unsigned long) ioaddr;
1655         dev->change_mtu = rtl8169_change_mtu;
1656         dev->set_mac_address = rtl_set_mac_address;
1657
1658 #ifdef CONFIG_R8169_NAPI
1659         netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
1660 #endif
1661
1662 #ifdef CONFIG_R8169_VLAN
1663         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1664         dev->vlan_rx_register = rtl8169_vlan_rx_register;
1665 #endif
1666
1667 #ifdef CONFIG_NET_POLL_CONTROLLER
1668         dev->poll_controller = rtl8169_netpoll;
1669 #endif
1670
1671         tp->intr_mask = 0xffff;
1672         tp->pci_dev = pdev;
1673         tp->mmio_addr = ioaddr;
1674         tp->align = cfg->align;
1675         tp->hw_start = cfg->hw_start;
1676         tp->intr_event = cfg->intr_event;
1677         tp->napi_event = cfg->napi_event;
1678
1679         init_timer(&tp->timer);
1680         tp->timer.data = (unsigned long) dev;
1681         tp->timer.function = rtl8169_phy_timer;
1682
1683         spin_lock_init(&tp->lock);
1684
1685         rc = register_netdev(dev);
1686         if (rc < 0)
1687                 goto err_out_unmap_5;
1688
1689         pci_set_drvdata(pdev, dev);
1690
1691         if (netif_msg_probe(tp)) {
1692                 u32 xid = RTL_R32(TxConfig) & 0x7cf0f8ff;
1693
1694                 printk(KERN_INFO "%s: %s at 0x%lx, "
1695                        "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
1696                        "XID %08x IRQ %d\n",
1697                        dev->name,
1698                        rtl_chip_info[tp->chipset].name,
1699                        dev->base_addr,
1700                        dev->dev_addr[0], dev->dev_addr[1],
1701                        dev->dev_addr[2], dev->dev_addr[3],
1702                        dev->dev_addr[4], dev->dev_addr[5], xid, dev->irq);
1703         }
1704
1705         rtl8169_init_phy(dev, tp);
1706
1707 out:
1708         return rc;
1709
1710 err_out_unmap_5:
1711         iounmap(ioaddr);
1712 err_out_free_res_4:
1713         pci_release_regions(pdev);
1714 err_out_mwi_3:
1715         pci_clear_mwi(pdev);
1716 err_out_disable_2:
1717         pci_disable_device(pdev);
1718 err_out_free_dev_1:
1719         free_netdev(dev);
1720         goto out;
1721 }
1722
1723 static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
1724 {
1725         struct net_device *dev = pci_get_drvdata(pdev);
1726         struct rtl8169_private *tp = netdev_priv(dev);
1727
1728         flush_scheduled_work();
1729
1730         unregister_netdev(dev);
1731         rtl8169_release_board(pdev, dev, tp->mmio_addr);
1732         pci_set_drvdata(pdev, NULL);
1733 }
1734
1735 static void rtl8169_set_rxbufsize(struct rtl8169_private *tp,
1736                                   struct net_device *dev)
1737 {
1738         unsigned int mtu = dev->mtu;
1739
1740         tp->rx_buf_sz = (mtu > RX_BUF_SIZE) ? mtu + ETH_HLEN + 8 : RX_BUF_SIZE;
1741 }
1742
1743 static int rtl8169_open(struct net_device *dev)
1744 {
1745         struct rtl8169_private *tp = netdev_priv(dev);
1746         struct pci_dev *pdev = tp->pci_dev;
1747         int retval = -ENOMEM;
1748
1749
1750         rtl8169_set_rxbufsize(tp, dev);
1751
1752         /*
1753          * Rx and Tx desscriptors needs 256 bytes alignment.
1754          * pci_alloc_consistent provides more.
1755          */
1756         tp->TxDescArray = pci_alloc_consistent(pdev, R8169_TX_RING_BYTES,
1757                                                &tp->TxPhyAddr);
1758         if (!tp->TxDescArray)
1759                 goto out;
1760
1761         tp->RxDescArray = pci_alloc_consistent(pdev, R8169_RX_RING_BYTES,
1762                                                &tp->RxPhyAddr);
1763         if (!tp->RxDescArray)
1764                 goto err_free_tx_0;
1765
1766         retval = rtl8169_init_ring(dev);
1767         if (retval < 0)
1768                 goto err_free_rx_1;
1769
1770         INIT_DELAYED_WORK(&tp->task, NULL);
1771
1772         smp_mb();
1773
1774         retval = request_irq(dev->irq, rtl8169_interrupt, IRQF_SHARED,
1775                              dev->name, dev);
1776         if (retval < 0)
1777                 goto err_release_ring_2;
1778
1779 #ifdef CONFIG_R8169_NAPI
1780         napi_enable(&tp->napi);
1781 #endif
1782
1783         rtl_hw_start(dev);
1784
1785         rtl8169_request_timer(dev);
1786
1787         rtl8169_check_link_status(dev, tp, tp->mmio_addr);
1788 out:
1789         return retval;
1790
1791 err_release_ring_2:
1792         rtl8169_rx_clear(tp);
1793 err_free_rx_1:
1794         pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
1795                             tp->RxPhyAddr);
1796 err_free_tx_0:
1797         pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
1798                             tp->TxPhyAddr);
1799         goto out;
1800 }
1801
1802 static void rtl8169_hw_reset(void __iomem *ioaddr)
1803 {
1804         /* Disable interrupts */
1805         rtl8169_irq_mask_and_ack(ioaddr);
1806
1807         /* Reset the chipset */
1808         RTL_W8(ChipCmd, CmdReset);
1809
1810         /* PCI commit */
1811         RTL_R8(ChipCmd);
1812 }
1813
1814 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
1815 {
1816         void __iomem *ioaddr = tp->mmio_addr;
1817         u32 cfg = rtl8169_rx_config;
1818
1819         cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
1820         RTL_W32(RxConfig, cfg);
1821
1822         /* Set DMA burst size and Interframe Gap Time */
1823         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
1824                 (InterFrameGap << TxInterFrameGapShift));
1825 }
1826
1827 static void rtl_hw_start(struct net_device *dev)
1828 {
1829         struct rtl8169_private *tp = netdev_priv(dev);
1830         void __iomem *ioaddr = tp->mmio_addr;
1831         unsigned int i;
1832
1833         /* Soft reset the chip. */
1834         RTL_W8(ChipCmd, CmdReset);
1835
1836         /* Check that the chip has finished the reset. */
1837         for (i = 0; i < 100; i++) {
1838                 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1839                         break;
1840                 msleep_interruptible(1);
1841         }
1842
1843         tp->hw_start(dev);
1844
1845         netif_start_queue(dev);
1846 }
1847
1848
1849 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
1850                                          void __iomem *ioaddr)
1851 {
1852         /*
1853          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
1854          * register to be written before TxDescAddrLow to work.
1855          * Switching from MMIO to I/O access fixes the issue as well.
1856          */
1857         RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
1858         RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_32BIT_MASK);
1859         RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
1860         RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_32BIT_MASK);
1861 }
1862
1863 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
1864 {
1865         u16 cmd;
1866
1867         cmd = RTL_R16(CPlusCmd);
1868         RTL_W16(CPlusCmd, cmd);
1869         return cmd;
1870 }
1871
1872 static void rtl_set_rx_max_size(void __iomem *ioaddr)
1873 {
1874         /* Low hurts. Let's disable the filtering. */
1875         RTL_W16(RxMaxSize, 16383);
1876 }
1877
1878 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
1879 {
1880         struct {
1881                 u32 mac_version;
1882                 u32 clk;
1883                 u32 val;
1884         } cfg2_info [] = {
1885                 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
1886                 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
1887                 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
1888                 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
1889         }, *p = cfg2_info;
1890         unsigned int i;
1891         u32 clk;
1892
1893         clk = RTL_R8(Config2) & PCI_Clock_66MHz;
1894         for (i = 0; i < ARRAY_SIZE(cfg2_info); i++) {
1895                 if ((p->mac_version == mac_version) && (p->clk == clk)) {
1896                         RTL_W32(0x7c, p->val);
1897                         break;
1898                 }
1899         }
1900 }
1901
1902 static void rtl_hw_start_8169(struct net_device *dev)
1903 {
1904         struct rtl8169_private *tp = netdev_priv(dev);
1905         void __iomem *ioaddr = tp->mmio_addr;
1906         struct pci_dev *pdev = tp->pci_dev;
1907
1908         if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
1909                 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
1910                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
1911         }
1912
1913         RTL_W8(Cfg9346, Cfg9346_Unlock);
1914         if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
1915             (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
1916             (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
1917             (tp->mac_version == RTL_GIGA_MAC_VER_04))
1918                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
1919
1920         RTL_W8(EarlyTxThres, EarlyTxThld);
1921
1922         rtl_set_rx_max_size(ioaddr);
1923
1924         if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
1925             (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
1926             (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
1927             (tp->mac_version == RTL_GIGA_MAC_VER_04))
1928                 rtl_set_rx_tx_config_registers(tp);
1929
1930         tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
1931
1932         if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
1933             (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
1934                 dprintk(KERN_INFO PFX "Set MAC Reg C+CR Offset 0xE0. "
1935                         "Bit-3 and bit-14 MUST be 1\n");
1936                 tp->cp_cmd |= (1 << 14);
1937         }
1938
1939         RTL_W16(CPlusCmd, tp->cp_cmd);
1940
1941         rtl8169_set_magic_reg(ioaddr, tp->mac_version);
1942
1943         /*
1944          * Undocumented corner. Supposedly:
1945          * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
1946          */
1947         RTL_W16(IntrMitigate, 0x0000);
1948
1949         rtl_set_rx_tx_desc_registers(tp, ioaddr);
1950
1951         if ((tp->mac_version != RTL_GIGA_MAC_VER_01) &&
1952             (tp->mac_version != RTL_GIGA_MAC_VER_02) &&
1953             (tp->mac_version != RTL_GIGA_MAC_VER_03) &&
1954             (tp->mac_version != RTL_GIGA_MAC_VER_04)) {
1955                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
1956                 rtl_set_rx_tx_config_registers(tp);
1957         }
1958
1959         RTL_W8(Cfg9346, Cfg9346_Lock);
1960
1961         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
1962         RTL_R8(IntrMask);
1963
1964         RTL_W32(RxMissed, 0);
1965
1966         rtl_set_rx_mode(dev);
1967
1968         /* no early-rx interrupts */
1969         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
1970
1971         /* Enable all known interrupts by setting the interrupt mask. */
1972         RTL_W16(IntrMask, tp->intr_event);
1973 }
1974
1975 static void rtl_hw_start_8168(struct net_device *dev)
1976 {
1977         struct rtl8169_private *tp = netdev_priv(dev);
1978         void __iomem *ioaddr = tp->mmio_addr;
1979         struct pci_dev *pdev = tp->pci_dev;
1980         u8 ctl;
1981
1982         RTL_W8(Cfg9346, Cfg9346_Unlock);
1983
1984         RTL_W8(EarlyTxThres, EarlyTxThld);
1985
1986         rtl_set_rx_max_size(ioaddr);
1987
1988         rtl_set_rx_tx_config_registers(tp);
1989
1990         tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
1991
1992         RTL_W16(CPlusCmd, tp->cp_cmd);
1993
1994         /* Tx performance tweak. */
1995         pci_read_config_byte(pdev, 0x69, &ctl);
1996         ctl = (ctl & ~0x70) | 0x50;
1997         pci_write_config_byte(pdev, 0x69, ctl);
1998
1999         RTL_W16(IntrMitigate, 0x5151);
2000
2001         /* Work around for RxFIFO overflow. */
2002         if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
2003                 tp->intr_event |= RxFIFOOver | PCSTimeout;
2004                 tp->intr_event &= ~RxOverflow;
2005         }
2006
2007         rtl_set_rx_tx_desc_registers(tp, ioaddr);
2008
2009         RTL_W8(Cfg9346, Cfg9346_Lock);
2010
2011         RTL_R8(IntrMask);
2012
2013         RTL_W32(RxMissed, 0);
2014
2015         rtl_set_rx_mode(dev);
2016
2017         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2018
2019         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
2020
2021         RTL_W16(IntrMask, tp->intr_event);
2022 }
2023
2024 static void rtl_hw_start_8101(struct net_device *dev)
2025 {
2026         struct rtl8169_private *tp = netdev_priv(dev);
2027         void __iomem *ioaddr = tp->mmio_addr;
2028         struct pci_dev *pdev = tp->pci_dev;
2029
2030         if (tp->mac_version == RTL_GIGA_MAC_VER_13) {
2031                 pci_write_config_word(pdev, 0x68, 0x00);
2032                 pci_write_config_word(pdev, 0x69, 0x08);
2033         }
2034
2035         RTL_W8(Cfg9346, Cfg9346_Unlock);
2036
2037         RTL_W8(EarlyTxThres, EarlyTxThld);
2038
2039         rtl_set_rx_max_size(ioaddr);
2040
2041         tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
2042
2043         RTL_W16(CPlusCmd, tp->cp_cmd);
2044
2045         RTL_W16(IntrMitigate, 0x0000);
2046
2047         rtl_set_rx_tx_desc_registers(tp, ioaddr);
2048
2049         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2050         rtl_set_rx_tx_config_registers(tp);
2051
2052         RTL_W8(Cfg9346, Cfg9346_Lock);
2053
2054         RTL_R8(IntrMask);
2055
2056         RTL_W32(RxMissed, 0);
2057
2058         rtl_set_rx_mode(dev);
2059
2060         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2061
2062         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
2063
2064         RTL_W16(IntrMask, tp->intr_event);
2065 }
2066
2067 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
2068 {
2069         struct rtl8169_private *tp = netdev_priv(dev);
2070         int ret = 0;
2071
2072         if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
2073                 return -EINVAL;
2074
2075         dev->mtu = new_mtu;
2076
2077         if (!netif_running(dev))
2078                 goto out;
2079
2080         rtl8169_down(dev);
2081
2082         rtl8169_set_rxbufsize(tp, dev);
2083
2084         ret = rtl8169_init_ring(dev);
2085         if (ret < 0)
2086                 goto out;
2087
2088 #ifdef CONFIG_R8169_NAPI
2089         napi_enable(&tp->napi);
2090 #endif
2091
2092         rtl_hw_start(dev);
2093
2094         rtl8169_request_timer(dev);
2095
2096 out:
2097         return ret;
2098 }
2099
2100 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
2101 {
2102         desc->addr = 0x0badbadbadbadbadull;
2103         desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
2104 }
2105
2106 static void rtl8169_free_rx_skb(struct rtl8169_private *tp,
2107                                 struct sk_buff **sk_buff, struct RxDesc *desc)
2108 {
2109         struct pci_dev *pdev = tp->pci_dev;
2110
2111         pci_unmap_single(pdev, le64_to_cpu(desc->addr), tp->rx_buf_sz,
2112                          PCI_DMA_FROMDEVICE);
2113         dev_kfree_skb(*sk_buff);
2114         *sk_buff = NULL;
2115         rtl8169_make_unusable_by_asic(desc);
2116 }
2117
2118 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
2119 {
2120         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
2121
2122         desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
2123 }
2124
2125 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
2126                                        u32 rx_buf_sz)
2127 {
2128         desc->addr = cpu_to_le64(mapping);
2129         wmb();
2130         rtl8169_mark_to_asic(desc, rx_buf_sz);
2131 }
2132
2133 static struct sk_buff *rtl8169_alloc_rx_skb(struct pci_dev *pdev,
2134                                             struct net_device *dev,
2135                                             struct RxDesc *desc, int rx_buf_sz,
2136                                             unsigned int align)
2137 {
2138         struct sk_buff *skb;
2139         dma_addr_t mapping;
2140         unsigned int pad;
2141
2142         pad = align ? align : NET_IP_ALIGN;
2143
2144         skb = netdev_alloc_skb(dev, rx_buf_sz + pad);
2145         if (!skb)
2146                 goto err_out;
2147
2148         skb_reserve(skb, align ? ((pad - 1) & (unsigned long)skb->data) : pad);
2149
2150         mapping = pci_map_single(pdev, skb->data, rx_buf_sz,
2151                                  PCI_DMA_FROMDEVICE);
2152
2153         rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
2154 out:
2155         return skb;
2156
2157 err_out:
2158         rtl8169_make_unusable_by_asic(desc);
2159         goto out;
2160 }
2161
2162 static void rtl8169_rx_clear(struct rtl8169_private *tp)
2163 {
2164         unsigned int i;
2165
2166         for (i = 0; i < NUM_RX_DESC; i++) {
2167                 if (tp->Rx_skbuff[i]) {
2168                         rtl8169_free_rx_skb(tp, tp->Rx_skbuff + i,
2169                                             tp->RxDescArray + i);
2170                 }
2171         }
2172 }
2173
2174 static u32 rtl8169_rx_fill(struct rtl8169_private *tp, struct net_device *dev,
2175                            u32 start, u32 end)
2176 {
2177         u32 cur;
2178
2179         for (cur = start; end - cur != 0; cur++) {
2180                 struct sk_buff *skb;
2181                 unsigned int i = cur % NUM_RX_DESC;
2182
2183                 WARN_ON((s32)(end - cur) < 0);
2184
2185                 if (tp->Rx_skbuff[i])
2186                         continue;
2187
2188                 skb = rtl8169_alloc_rx_skb(tp->pci_dev, dev,
2189                                            tp->RxDescArray + i,
2190                                            tp->rx_buf_sz, tp->align);
2191                 if (!skb)
2192                         break;
2193
2194                 tp->Rx_skbuff[i] = skb;
2195         }
2196         return cur - start;
2197 }
2198
2199 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
2200 {
2201         desc->opts1 |= cpu_to_le32(RingEnd);
2202 }
2203
2204 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
2205 {
2206         tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
2207 }
2208
2209 static int rtl8169_init_ring(struct net_device *dev)
2210 {
2211         struct rtl8169_private *tp = netdev_priv(dev);
2212
2213         rtl8169_init_ring_indexes(tp);
2214
2215         memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
2216         memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));
2217
2218         if (rtl8169_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC)
2219                 goto err_out;
2220
2221         rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
2222
2223         return 0;
2224
2225 err_out:
2226         rtl8169_rx_clear(tp);
2227         return -ENOMEM;
2228 }
2229
2230 static void rtl8169_unmap_tx_skb(struct pci_dev *pdev, struct ring_info *tx_skb,
2231                                  struct TxDesc *desc)
2232 {
2233         unsigned int len = tx_skb->len;
2234
2235         pci_unmap_single(pdev, le64_to_cpu(desc->addr), len, PCI_DMA_TODEVICE);
2236         desc->opts1 = 0x00;
2237         desc->opts2 = 0x00;
2238         desc->addr = 0x00;
2239         tx_skb->len = 0;
2240 }
2241
2242 static void rtl8169_tx_clear(struct rtl8169_private *tp)
2243 {
2244         unsigned int i;
2245
2246         for (i = tp->dirty_tx; i < tp->dirty_tx + NUM_TX_DESC; i++) {
2247                 unsigned int entry = i % NUM_TX_DESC;
2248                 struct ring_info *tx_skb = tp->tx_skb + entry;
2249                 unsigned int len = tx_skb->len;
2250
2251                 if (len) {
2252                         struct sk_buff *skb = tx_skb->skb;
2253
2254                         rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb,
2255                                              tp->TxDescArray + entry);
2256                         if (skb) {
2257                                 dev_kfree_skb(skb);
2258                                 tx_skb->skb = NULL;
2259                         }
2260                         tp->stats.tx_dropped++;
2261                 }
2262         }
2263         tp->cur_tx = tp->dirty_tx = 0;
2264 }
2265
2266 static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
2267 {
2268         struct rtl8169_private *tp = netdev_priv(dev);
2269
2270         PREPARE_DELAYED_WORK(&tp->task, task);
2271         schedule_delayed_work(&tp->task, 4);
2272 }
2273
2274 static void rtl8169_wait_for_quiescence(struct net_device *dev)
2275 {
2276         struct rtl8169_private *tp = netdev_priv(dev);
2277         void __iomem *ioaddr = tp->mmio_addr;
2278
2279         synchronize_irq(dev->irq);
2280
2281         /* Wait for any pending NAPI task to complete */
2282 #ifdef CONFIG_R8169_NAPI
2283         napi_disable(&tp->napi);
2284 #endif
2285
2286         rtl8169_irq_mask_and_ack(ioaddr);
2287
2288 #ifdef CONFIG_R8169_NAPI
2289         napi_enable(&tp->napi);
2290 #endif
2291 }
2292
2293 static void rtl8169_reinit_task(struct work_struct *work)
2294 {
2295         struct rtl8169_private *tp =
2296                 container_of(work, struct rtl8169_private, task.work);
2297         struct net_device *dev = tp->dev;
2298         int ret;
2299
2300         rtnl_lock();
2301
2302         if (!netif_running(dev))
2303                 goto out_unlock;
2304
2305         rtl8169_wait_for_quiescence(dev);
2306         rtl8169_close(dev);
2307
2308         ret = rtl8169_open(dev);
2309         if (unlikely(ret < 0)) {
2310                 if (net_ratelimit() && netif_msg_drv(tp)) {
2311                         printk(PFX KERN_ERR "%s: reinit failure (status = %d)."
2312                                " Rescheduling.\n", dev->name, ret);
2313                 }
2314                 rtl8169_schedule_work(dev, rtl8169_reinit_task);
2315         }
2316
2317 out_unlock:
2318         rtnl_unlock();
2319 }
2320
2321 static void rtl8169_reset_task(struct work_struct *work)
2322 {
2323         struct rtl8169_private *tp =
2324                 container_of(work, struct rtl8169_private, task.work);
2325         struct net_device *dev = tp->dev;
2326
2327         rtnl_lock();
2328
2329         if (!netif_running(dev))
2330                 goto out_unlock;
2331
2332         rtl8169_wait_for_quiescence(dev);
2333
2334         rtl8169_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0);
2335         rtl8169_tx_clear(tp);
2336
2337         if (tp->dirty_rx == tp->cur_rx) {
2338                 rtl8169_init_ring_indexes(tp);
2339                 rtl_hw_start(dev);
2340                 netif_wake_queue(dev);
2341         } else {
2342                 if (net_ratelimit() && netif_msg_intr(tp)) {
2343                         printk(PFX KERN_EMERG "%s: Rx buffers shortage\n",
2344                                dev->name);
2345                 }
2346                 rtl8169_schedule_work(dev, rtl8169_reset_task);
2347         }
2348
2349 out_unlock:
2350         rtnl_unlock();
2351 }
2352
2353 static void rtl8169_tx_timeout(struct net_device *dev)
2354 {
2355         struct rtl8169_private *tp = netdev_priv(dev);
2356
2357         rtl8169_hw_reset(tp->mmio_addr);
2358
2359         /* Let's wait a bit while any (async) irq lands on */
2360         rtl8169_schedule_work(dev, rtl8169_reset_task);
2361 }
2362
2363 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
2364                               u32 opts1)
2365 {
2366         struct skb_shared_info *info = skb_shinfo(skb);
2367         unsigned int cur_frag, entry;
2368         struct TxDesc * uninitialized_var(txd);
2369
2370         entry = tp->cur_tx;
2371         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
2372                 skb_frag_t *frag = info->frags + cur_frag;
2373                 dma_addr_t mapping;
2374                 u32 status, len;
2375                 void *addr;
2376
2377                 entry = (entry + 1) % NUM_TX_DESC;
2378
2379                 txd = tp->TxDescArray + entry;
2380                 len = frag->size;
2381                 addr = ((void *) page_address(frag->page)) + frag->page_offset;
2382                 mapping = pci_map_single(tp->pci_dev, addr, len, PCI_DMA_TODEVICE);
2383
2384                 /* anti gcc 2.95.3 bugware (sic) */
2385                 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
2386
2387                 txd->opts1 = cpu_to_le32(status);
2388                 txd->addr = cpu_to_le64(mapping);
2389
2390                 tp->tx_skb[entry].len = len;
2391         }
2392
2393         if (cur_frag) {
2394                 tp->tx_skb[entry].skb = skb;
2395                 txd->opts1 |= cpu_to_le32(LastFrag);
2396         }
2397
2398         return cur_frag;
2399 }
2400
2401 static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
2402 {
2403         if (dev->features & NETIF_F_TSO) {
2404                 u32 mss = skb_shinfo(skb)->gso_size;
2405
2406                 if (mss)
2407                         return LargeSend | ((mss & MSSMask) << MSSShift);
2408         }
2409         if (skb->ip_summed == CHECKSUM_PARTIAL) {
2410                 const struct iphdr *ip = ip_hdr(skb);
2411
2412                 if (ip->protocol == IPPROTO_TCP)
2413                         return IPCS | TCPCS;
2414                 else if (ip->protocol == IPPROTO_UDP)
2415                         return IPCS | UDPCS;
2416                 WARN_ON(1);     /* we need a WARN() */
2417         }
2418         return 0;
2419 }
2420
2421 static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev)
2422 {
2423         struct rtl8169_private *tp = netdev_priv(dev);
2424         unsigned int frags, entry = tp->cur_tx % NUM_TX_DESC;
2425         struct TxDesc *txd = tp->TxDescArray + entry;
2426         void __iomem *ioaddr = tp->mmio_addr;
2427         dma_addr_t mapping;
2428         u32 status, len;
2429         u32 opts1;
2430         int ret = NETDEV_TX_OK;
2431
2432         if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
2433                 if (netif_msg_drv(tp)) {
2434                         printk(KERN_ERR
2435                                "%s: BUG! Tx Ring full when queue awake!\n",
2436                                dev->name);
2437                 }
2438                 goto err_stop;
2439         }
2440
2441         if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
2442                 goto err_stop;
2443
2444         opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
2445
2446         frags = rtl8169_xmit_frags(tp, skb, opts1);
2447         if (frags) {
2448                 len = skb_headlen(skb);
2449                 opts1 |= FirstFrag;
2450         } else {
2451                 len = skb->len;
2452
2453                 if (unlikely(len < ETH_ZLEN)) {
2454                         if (skb_padto(skb, ETH_ZLEN))
2455                                 goto err_update_stats;
2456                         len = ETH_ZLEN;
2457                 }
2458
2459                 opts1 |= FirstFrag | LastFrag;
2460                 tp->tx_skb[entry].skb = skb;
2461         }
2462
2463         mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
2464
2465         tp->tx_skb[entry].len = len;
2466         txd->addr = cpu_to_le64(mapping);
2467         txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
2468
2469         wmb();
2470
2471         /* anti gcc 2.95.3 bugware (sic) */
2472         status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
2473         txd->opts1 = cpu_to_le32(status);
2474
2475         dev->trans_start = jiffies;
2476
2477         tp->cur_tx += frags + 1;
2478
2479         smp_wmb();
2480
2481         RTL_W8(TxPoll, NPQ);    /* set polling bit */
2482
2483         if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
2484                 netif_stop_queue(dev);
2485                 smp_rmb();
2486                 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
2487                         netif_wake_queue(dev);
2488         }
2489
2490 out:
2491         return ret;
2492
2493 err_stop:
2494         netif_stop_queue(dev);
2495         ret = NETDEV_TX_BUSY;
2496 err_update_stats:
2497         tp->stats.tx_dropped++;
2498         goto out;
2499 }
2500
2501 static void rtl8169_pcierr_interrupt(struct net_device *dev)
2502 {
2503         struct rtl8169_private *tp = netdev_priv(dev);
2504         struct pci_dev *pdev = tp->pci_dev;
2505         void __iomem *ioaddr = tp->mmio_addr;
2506         u16 pci_status, pci_cmd;
2507
2508         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2509         pci_read_config_word(pdev, PCI_STATUS, &pci_status);
2510
2511         if (netif_msg_intr(tp)) {
2512                 printk(KERN_ERR
2513                        "%s: PCI error (cmd = 0x%04x, status = 0x%04x).\n",
2514                        dev->name, pci_cmd, pci_status);
2515         }
2516
2517         /*
2518          * The recovery sequence below admits a very elaborated explanation:
2519          * - it seems to work;
2520          * - I did not see what else could be done;
2521          * - it makes iop3xx happy.
2522          *
2523          * Feel free to adjust to your needs.
2524          */
2525         if (pdev->broken_parity_status)
2526                 pci_cmd &= ~PCI_COMMAND_PARITY;
2527         else
2528                 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
2529
2530         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
2531
2532         pci_write_config_word(pdev, PCI_STATUS,
2533                 pci_status & (PCI_STATUS_DETECTED_PARITY |
2534                 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
2535                 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
2536
2537         /* The infamous DAC f*ckup only happens at boot time */
2538         if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
2539                 if (netif_msg_intr(tp))
2540                         printk(KERN_INFO "%s: disabling PCI DAC.\n", dev->name);
2541                 tp->cp_cmd &= ~PCIDAC;
2542                 RTL_W16(CPlusCmd, tp->cp_cmd);
2543                 dev->features &= ~NETIF_F_HIGHDMA;
2544         }
2545
2546         rtl8169_hw_reset(ioaddr);
2547
2548         rtl8169_schedule_work(dev, rtl8169_reinit_task);
2549 }
2550
2551 static void rtl8169_tx_interrupt(struct net_device *dev,
2552                                  struct rtl8169_private *tp,
2553                                  void __iomem *ioaddr)
2554 {
2555         unsigned int dirty_tx, tx_left;
2556
2557         dirty_tx = tp->dirty_tx;
2558         smp_rmb();
2559         tx_left = tp->cur_tx - dirty_tx;
2560
2561         while (tx_left > 0) {
2562                 unsigned int entry = dirty_tx % NUM_TX_DESC;
2563                 struct ring_info *tx_skb = tp->tx_skb + entry;
2564                 u32 len = tx_skb->len;
2565                 u32 status;
2566
2567                 rmb();
2568                 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
2569                 if (status & DescOwn)
2570                         break;
2571
2572                 tp->stats.tx_bytes += len;
2573                 tp->stats.tx_packets++;
2574
2575                 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, tp->TxDescArray + entry);
2576
2577                 if (status & LastFrag) {
2578                         dev_kfree_skb_irq(tx_skb->skb);
2579                         tx_skb->skb = NULL;
2580                 }
2581                 dirty_tx++;
2582                 tx_left--;
2583         }
2584
2585         if (tp->dirty_tx != dirty_tx) {
2586                 tp->dirty_tx = dirty_tx;
2587                 smp_wmb();
2588                 if (netif_queue_stopped(dev) &&
2589                     (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
2590                         netif_wake_queue(dev);
2591                 }
2592                 /*
2593                  * 8168 hack: TxPoll requests are lost when the Tx packets are
2594                  * too close. Let's kick an extra TxPoll request when a burst
2595                  * of start_xmit activity is detected (if it is not detected,
2596                  * it is slow enough). -- FR
2597                  */
2598                 smp_rmb();
2599                 if (tp->cur_tx != dirty_tx)
2600                         RTL_W8(TxPoll, NPQ);
2601         }
2602 }
2603
2604 static inline int rtl8169_fragmented_frame(u32 status)
2605 {
2606         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
2607 }
2608
2609 static inline void rtl8169_rx_csum(struct sk_buff *skb, struct RxDesc *desc)
2610 {
2611         u32 opts1 = le32_to_cpu(desc->opts1);
2612         u32 status = opts1 & RxProtoMask;
2613
2614         if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
2615             ((status == RxProtoUDP) && !(opts1 & UDPFail)) ||
2616             ((status == RxProtoIP) && !(opts1 & IPFail)))
2617                 skb->ip_summed = CHECKSUM_UNNECESSARY;
2618         else
2619                 skb->ip_summed = CHECKSUM_NONE;
2620 }
2621
2622 static inline bool rtl8169_try_rx_copy(struct sk_buff **sk_buff,
2623                                        struct rtl8169_private *tp, int pkt_size,
2624                                        dma_addr_t addr)
2625 {
2626         struct sk_buff *skb;
2627         bool done = false;
2628
2629         if (pkt_size >= rx_copybreak)
2630                 goto out;
2631
2632         skb = netdev_alloc_skb(tp->dev, pkt_size + NET_IP_ALIGN);
2633         if (!skb)
2634                 goto out;
2635
2636         pci_dma_sync_single_for_cpu(tp->pci_dev, addr, pkt_size,
2637                                     PCI_DMA_FROMDEVICE);
2638         skb_reserve(skb, NET_IP_ALIGN);
2639         skb_copy_from_linear_data(*sk_buff, skb->data, pkt_size);
2640         *sk_buff = skb;
2641         done = true;
2642 out:
2643         return done;
2644 }
2645
2646 static int rtl8169_rx_interrupt(struct net_device *dev,
2647                                 struct rtl8169_private *tp,
2648                                 void __iomem *ioaddr, u32 budget)
2649 {
2650         unsigned int cur_rx, rx_left;
2651         unsigned int delta, count;
2652
2653         cur_rx = tp->cur_rx;
2654         rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
2655         rx_left = rtl8169_rx_quota(rx_left, budget);
2656
2657         for (; rx_left > 0; rx_left--, cur_rx++) {
2658                 unsigned int entry = cur_rx % NUM_RX_DESC;
2659                 struct RxDesc *desc = tp->RxDescArray + entry;
2660                 u32 status;
2661
2662                 rmb();
2663                 status = le32_to_cpu(desc->opts1);
2664
2665                 if (status & DescOwn)
2666                         break;
2667                 if (unlikely(status & RxRES)) {
2668                         if (netif_msg_rx_err(tp)) {
2669                                 printk(KERN_INFO
2670                                        "%s: Rx ERROR. status = %08x\n",
2671                                        dev->name, status);
2672                         }
2673                         tp->stats.rx_errors++;
2674                         if (status & (RxRWT | RxRUNT))
2675                                 tp->stats.rx_length_errors++;
2676                         if (status & RxCRC)
2677                                 tp->stats.rx_crc_errors++;
2678                         if (status & RxFOVF) {
2679                                 rtl8169_schedule_work(dev, rtl8169_reset_task);
2680                                 tp->stats.rx_fifo_errors++;
2681                         }
2682                         rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
2683                 } else {
2684                         struct sk_buff *skb = tp->Rx_skbuff[entry];
2685                         dma_addr_t addr = le64_to_cpu(desc->addr);
2686                         int pkt_size = (status & 0x00001FFF) - 4;
2687                         struct pci_dev *pdev = tp->pci_dev;
2688
2689                         /*
2690                          * The driver does not support incoming fragmented
2691                          * frames. They are seen as a symptom of over-mtu
2692                          * sized frames.
2693                          */
2694                         if (unlikely(rtl8169_fragmented_frame(status))) {
2695                                 tp->stats.rx_dropped++;
2696                                 tp->stats.rx_length_errors++;
2697                                 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
2698                                 continue;
2699                         }
2700
2701                         rtl8169_rx_csum(skb, desc);
2702
2703                         if (rtl8169_try_rx_copy(&skb, tp, pkt_size, addr)) {
2704                                 pci_dma_sync_single_for_device(pdev, addr,
2705                                         pkt_size, PCI_DMA_FROMDEVICE);
2706                                 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
2707                         } else {
2708                                 pci_unmap_single(pdev, addr, pkt_size,
2709                                                  PCI_DMA_FROMDEVICE);
2710                                 tp->Rx_skbuff[entry] = NULL;
2711                         }
2712
2713                         skb_put(skb, pkt_size);
2714                         skb->protocol = eth_type_trans(skb, dev);
2715
2716                         if (rtl8169_rx_vlan_skb(tp, desc, skb) < 0)
2717                                 rtl8169_rx_skb(skb);
2718
2719                         dev->last_rx = jiffies;
2720                         tp->stats.rx_bytes += pkt_size;
2721                         tp->stats.rx_packets++;
2722                 }
2723
2724                 /* Work around for AMD plateform. */
2725                 if ((desc->opts2 & 0xfffe000) &&
2726                     (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
2727                         desc->opts2 = 0;
2728                         cur_rx++;
2729                 }
2730         }
2731
2732         count = cur_rx - tp->cur_rx;
2733         tp->cur_rx = cur_rx;
2734
2735         delta = rtl8169_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx);
2736         if (!delta && count && netif_msg_intr(tp))
2737                 printk(KERN_INFO "%s: no Rx buffer allocated\n", dev->name);
2738         tp->dirty_rx += delta;
2739
2740         /*
2741          * FIXME: until there is periodic timer to try and refill the ring,
2742          * a temporary shortage may definitely kill the Rx process.
2743          * - disable the asic to try and avoid an overflow and kick it again
2744          *   after refill ?
2745          * - how do others driver handle this condition (Uh oh...).
2746          */
2747         if ((tp->dirty_rx + NUM_RX_DESC == tp->cur_rx) && netif_msg_intr(tp))
2748                 printk(KERN_EMERG "%s: Rx buffers exhausted\n", dev->name);
2749
2750         return count;
2751 }
2752
2753 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
2754 {
2755         struct net_device *dev = dev_instance;
2756         struct rtl8169_private *tp = netdev_priv(dev);
2757         int boguscnt = max_interrupt_work;
2758         void __iomem *ioaddr = tp->mmio_addr;
2759         int status;
2760         int handled = 0;
2761
2762         do {
2763                 status = RTL_R16(IntrStatus);
2764
2765                 /* hotplug/major error/no more work/shared irq */
2766                 if ((status == 0xFFFF) || !status)
2767                         break;
2768
2769                 handled = 1;
2770
2771                 if (unlikely(!netif_running(dev))) {
2772                         rtl8169_asic_down(ioaddr);
2773                         goto out;
2774                 }
2775
2776                 status &= tp->intr_mask;
2777                 RTL_W16(IntrStatus,
2778                         (status & RxFIFOOver) ? (status | RxOverflow) : status);
2779
2780                 if (!(status & tp->intr_event))
2781                         break;
2782
2783                 /* Work around for rx fifo overflow */
2784                 if (unlikely(status & RxFIFOOver) &&
2785                     (tp->mac_version == RTL_GIGA_MAC_VER_11)) {
2786                         netif_stop_queue(dev);
2787                         rtl8169_tx_timeout(dev);
2788                         break;
2789                 }
2790
2791                 if (unlikely(status & SYSErr)) {
2792                         rtl8169_pcierr_interrupt(dev);
2793                         break;
2794                 }
2795
2796                 if (status & LinkChg)
2797                         rtl8169_check_link_status(dev, tp, ioaddr);
2798
2799 #ifdef CONFIG_R8169_NAPI
2800                 if (status & tp->napi_event) {
2801                         RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
2802                         tp->intr_mask = ~tp->napi_event;
2803
2804                 if (likely(netif_rx_schedule_prep(dev, &tp->napi)))
2805                         __netif_rx_schedule(dev, &tp->napi);
2806                         else if (netif_msg_intr(tp)) {
2807                                 printk(KERN_INFO "%s: interrupt %04x in poll\n",
2808                                        dev->name, status);
2809                         }
2810                 }
2811                 break;
2812 #else
2813                 /* Rx interrupt */
2814                 if (status & (RxOK | RxOverflow | RxFIFOOver))
2815                         rtl8169_rx_interrupt(dev, tp, ioaddr, ~(u32)0);
2816
2817                 /* Tx interrupt */
2818                 if (status & (TxOK | TxErr))
2819                         rtl8169_tx_interrupt(dev, tp, ioaddr);
2820 #endif
2821
2822                 boguscnt--;
2823         } while (boguscnt > 0);
2824
2825         if (boguscnt <= 0) {
2826                 if (netif_msg_intr(tp) && net_ratelimit() ) {
2827                         printk(KERN_WARNING
2828                                "%s: Too much work at interrupt!\n", dev->name);
2829                 }
2830                 /* Clear all interrupt sources. */
2831                 RTL_W16(IntrStatus, 0xffff);
2832         }
2833 out:
2834         return IRQ_RETVAL(handled);
2835 }
2836
2837 #ifdef CONFIG_R8169_NAPI
2838 static int rtl8169_poll(struct napi_struct *napi, int budget)
2839 {
2840         struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
2841         struct net_device *dev = tp->dev;
2842         void __iomem *ioaddr = tp->mmio_addr;
2843         int work_done;
2844
2845         work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
2846         rtl8169_tx_interrupt(dev, tp, ioaddr);
2847
2848         if (work_done < budget) {
2849                 netif_rx_complete(dev, napi);
2850                 tp->intr_mask = 0xffff;
2851                 /*
2852                  * 20040426: the barrier is not strictly required but the
2853                  * behavior of the irq handler could be less predictable
2854                  * without it. Btw, the lack of flush for the posted pci
2855                  * write is safe - FR
2856                  */
2857                 smp_wmb();
2858                 RTL_W16(IntrMask, tp->intr_event);
2859         }
2860
2861         return work_done;
2862 }
2863 #endif
2864
2865 static void rtl8169_down(struct net_device *dev)
2866 {
2867         struct rtl8169_private *tp = netdev_priv(dev);
2868         void __iomem *ioaddr = tp->mmio_addr;
2869         unsigned int poll_locked = 0;
2870         unsigned int intrmask;
2871
2872         rtl8169_delete_timer(dev);
2873
2874         netif_stop_queue(dev);
2875
2876 core_down:
2877         spin_lock_irq(&tp->lock);
2878
2879         rtl8169_asic_down(ioaddr);
2880
2881         /* Update the error counts. */
2882         tp->stats.rx_missed_errors += RTL_R32(RxMissed);
2883         RTL_W32(RxMissed, 0);
2884
2885         spin_unlock_irq(&tp->lock);
2886
2887         synchronize_irq(dev->irq);
2888
2889         if (!poll_locked) {
2890                 napi_disable(&tp->napi);
2891                 poll_locked++;
2892         }
2893
2894         /* Give a racing hard_start_xmit a few cycles to complete. */
2895         synchronize_sched();  /* FIXME: should this be synchronize_irq()? */
2896
2897         /*
2898          * And now for the 50k$ question: are IRQ disabled or not ?
2899          *
2900          * Two paths lead here:
2901          * 1) dev->close
2902          *    -> netif_running() is available to sync the current code and the
2903          *       IRQ handler. See rtl8169_interrupt for details.
2904          * 2) dev->change_mtu
2905          *    -> rtl8169_poll can not be issued again and re-enable the
2906          *       interruptions. Let's simply issue the IRQ down sequence again.
2907          *
2908          * No loop if hotpluged or major error (0xffff).
2909          */
2910         intrmask = RTL_R16(IntrMask);
2911         if (intrmask && (intrmask != 0xffff))
2912                 goto core_down;
2913
2914         rtl8169_tx_clear(tp);
2915
2916         rtl8169_rx_clear(tp);
2917 }
2918
2919 static int rtl8169_close(struct net_device *dev)
2920 {
2921         struct rtl8169_private *tp = netdev_priv(dev);
2922         struct pci_dev *pdev = tp->pci_dev;
2923
2924         rtl8169_down(dev);
2925
2926         free_irq(dev->irq, dev);
2927
2928         pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
2929                             tp->RxPhyAddr);
2930         pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
2931                             tp->TxPhyAddr);
2932         tp->TxDescArray = NULL;
2933         tp->RxDescArray = NULL;
2934
2935         return 0;
2936 }
2937
2938 static void rtl_set_rx_mode(struct net_device *dev)
2939 {
2940         struct rtl8169_private *tp = netdev_priv(dev);
2941         void __iomem *ioaddr = tp->mmio_addr;
2942         unsigned long flags;
2943         u32 mc_filter[2];       /* Multicast hash filter */
2944         int rx_mode;
2945         u32 tmp = 0;
2946
2947         if (dev->flags & IFF_PROMISC) {
2948                 /* Unconditionally log net taps. */
2949                 if (netif_msg_link(tp)) {
2950                         printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n",
2951                                dev->name);
2952                 }
2953                 rx_mode =
2954                     AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
2955                     AcceptAllPhys;
2956                 mc_filter[1] = mc_filter[0] = 0xffffffff;
2957         } else if ((dev->mc_count > multicast_filter_limit)
2958                    || (dev->flags & IFF_ALLMULTI)) {
2959                 /* Too many to filter perfectly -- accept all multicasts. */
2960                 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
2961                 mc_filter[1] = mc_filter[0] = 0xffffffff;
2962         } else {
2963                 struct dev_mc_list *mclist;
2964                 unsigned int i;
2965
2966                 rx_mode = AcceptBroadcast | AcceptMyPhys;
2967                 mc_filter[1] = mc_filter[0] = 0;
2968                 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
2969                      i++, mclist = mclist->next) {
2970                         int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
2971                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2972                         rx_mode |= AcceptMulticast;
2973                 }
2974         }
2975
2976         spin_lock_irqsave(&tp->lock, flags);
2977
2978         tmp = rtl8169_rx_config | rx_mode |
2979               (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
2980
2981         if ((tp->mac_version == RTL_GIGA_MAC_VER_11) ||
2982             (tp->mac_version == RTL_GIGA_MAC_VER_12) ||
2983             (tp->mac_version == RTL_GIGA_MAC_VER_13) ||
2984             (tp->mac_version == RTL_GIGA_MAC_VER_14) ||
2985             (tp->mac_version == RTL_GIGA_MAC_VER_15)) {
2986                 mc_filter[0] = 0xffffffff;
2987                 mc_filter[1] = 0xffffffff;
2988         }
2989
2990         RTL_W32(MAR0 + 0, mc_filter[0]);
2991         RTL_W32(MAR0 + 4, mc_filter[1]);
2992
2993         RTL_W32(RxConfig, tmp);
2994
2995         spin_unlock_irqrestore(&tp->lock, flags);
2996 }
2997
2998 /**
2999  *  rtl8169_get_stats - Get rtl8169 read/write statistics
3000  *  @dev: The Ethernet Device to get statistics for
3001  *
3002  *  Get TX/RX statistics for rtl8169
3003  */
3004 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
3005 {
3006         struct rtl8169_private *tp = netdev_priv(dev);
3007         void __iomem *ioaddr = tp->mmio_addr;
3008         unsigned long flags;
3009
3010         if (netif_running(dev)) {
3011                 spin_lock_irqsave(&tp->lock, flags);
3012                 tp->stats.rx_missed_errors += RTL_R32(RxMissed);
3013                 RTL_W32(RxMissed, 0);
3014                 spin_unlock_irqrestore(&tp->lock, flags);
3015         }
3016
3017         return &tp->stats;
3018 }
3019
3020 #ifdef CONFIG_PM
3021
3022 static int rtl8169_suspend(struct pci_dev *pdev, pm_message_t state)
3023 {
3024         struct net_device *dev = pci_get_drvdata(pdev);
3025         struct rtl8169_private *tp = netdev_priv(dev);
3026         void __iomem *ioaddr = tp->mmio_addr;
3027
3028         if (!netif_running(dev))
3029                 goto out_pci_suspend;
3030
3031         netif_device_detach(dev);
3032         netif_stop_queue(dev);
3033
3034         spin_lock_irq(&tp->lock);
3035
3036         rtl8169_asic_down(ioaddr);
3037
3038         tp->stats.rx_missed_errors += RTL_R32(RxMissed);
3039         RTL_W32(RxMissed, 0);
3040
3041         spin_unlock_irq(&tp->lock);
3042
3043 out_pci_suspend:
3044         pci_save_state(pdev);
3045         pci_enable_wake(pdev, pci_choose_state(pdev, state), tp->wol_enabled);
3046         pci_set_power_state(pdev, pci_choose_state(pdev, state));
3047
3048         return 0;
3049 }
3050
3051 static int rtl8169_resume(struct pci_dev *pdev)
3052 {
3053         struct net_device *dev = pci_get_drvdata(pdev);
3054
3055         pci_set_power_state(pdev, PCI_D0);
3056         pci_restore_state(pdev);
3057         pci_enable_wake(pdev, PCI_D0, 0);
3058
3059         if (!netif_running(dev))
3060                 goto out;
3061
3062         netif_device_attach(dev);
3063
3064         rtl8169_schedule_work(dev, rtl8169_reset_task);
3065 out:
3066         return 0;
3067 }
3068
3069 #endif /* CONFIG_PM */
3070
3071 static struct pci_driver rtl8169_pci_driver = {
3072         .name           = MODULENAME,
3073         .id_table       = rtl8169_pci_tbl,
3074         .probe          = rtl8169_init_one,
3075         .remove         = __devexit_p(rtl8169_remove_one),
3076 #ifdef CONFIG_PM
3077         .suspend        = rtl8169_suspend,
3078         .resume         = rtl8169_resume,
3079 #endif
3080 };
3081
3082 static int __init rtl8169_init_module(void)
3083 {
3084         return pci_register_driver(&rtl8169_pci_driver);
3085 }
3086
3087 static void __exit rtl8169_cleanup_module(void)
3088 {
3089         pci_unregister_driver(&rtl8169_pci_driver);
3090 }
3091
3092 module_init(rtl8169_init_module);
3093 module_exit(rtl8169_cleanup_module);