2 * QLogic qlge NIC HBA Driver
3 * Copyright (c) 2003-2008 QLogic Corporation
4 * See LICENSE.qlge for copyright and licensing details.
5 * Author: Linux qlge network device driver by
6 * Ron Mercer <ron.mercer@qlogic.com>
8 #include <linux/kernel.h>
9 #include <linux/init.h>
10 #include <linux/types.h>
11 #include <linux/module.h>
12 #include <linux/list.h>
13 #include <linux/pci.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/pagemap.h>
16 #include <linux/sched.h>
17 #include <linux/slab.h>
18 #include <linux/dmapool.h>
19 #include <linux/mempool.h>
20 #include <linux/spinlock.h>
21 #include <linux/kthread.h>
22 #include <linux/interrupt.h>
23 #include <linux/errno.h>
24 #include <linux/ioport.h>
27 #include <linux/ipv6.h>
29 #include <linux/tcp.h>
30 #include <linux/udp.h>
31 #include <linux/if_arp.h>
32 #include <linux/if_ether.h>
33 #include <linux/netdevice.h>
34 #include <linux/etherdevice.h>
35 #include <linux/ethtool.h>
36 #include <linux/skbuff.h>
37 #include <linux/rtnetlink.h>
38 #include <linux/if_vlan.h>
39 #include <linux/delay.h>
41 #include <linux/vmalloc.h>
42 #include <net/ip6_checksum.h>
46 char qlge_driver_name[] = DRV_NAME;
47 const char qlge_driver_version[] = DRV_VERSION;
49 MODULE_AUTHOR("Ron Mercer <ron.mercer@qlogic.com>");
50 MODULE_DESCRIPTION(DRV_STRING " ");
51 MODULE_LICENSE("GPL");
52 MODULE_VERSION(DRV_VERSION);
54 static const u32 default_msg =
55 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK |
56 /* NETIF_MSG_TIMER | */
61 /* NETIF_MSG_TX_QUEUED | */
62 /* NETIF_MSG_INTR | NETIF_MSG_TX_DONE | NETIF_MSG_RX_STATUS | */
63 /* NETIF_MSG_PKTDATA | */
64 NETIF_MSG_HW | NETIF_MSG_WOL | 0;
66 static int debug = 0x00007fff; /* defaults above */
67 module_param(debug, int, 0);
68 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
73 static int irq_type = MSIX_IRQ;
74 module_param(irq_type, int, MSIX_IRQ);
75 MODULE_PARM_DESC(irq_type, "0 = MSI-X, 1 = MSI, 2 = Legacy.");
77 static struct pci_device_id qlge_pci_tbl[] __devinitdata = {
78 {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QLGE_DEVICE_ID_8012)},
79 {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QLGE_DEVICE_ID_8000)},
80 /* required last entry */
84 MODULE_DEVICE_TABLE(pci, qlge_pci_tbl);
86 /* This hardware semaphore causes exclusive access to
87 * resources shared between the NIC driver, MPI firmware,
88 * FCOE firmware and the FC driver.
90 static int ql_sem_trylock(struct ql_adapter *qdev, u32 sem_mask)
96 sem_bits = SEM_SET << SEM_XGMAC0_SHIFT;
99 sem_bits = SEM_SET << SEM_XGMAC1_SHIFT;
102 sem_bits = SEM_SET << SEM_ICB_SHIFT;
104 case SEM_MAC_ADDR_MASK:
105 sem_bits = SEM_SET << SEM_MAC_ADDR_SHIFT;
108 sem_bits = SEM_SET << SEM_FLASH_SHIFT;
111 sem_bits = SEM_SET << SEM_PROBE_SHIFT;
113 case SEM_RT_IDX_MASK:
114 sem_bits = SEM_SET << SEM_RT_IDX_SHIFT;
116 case SEM_PROC_REG_MASK:
117 sem_bits = SEM_SET << SEM_PROC_REG_SHIFT;
120 QPRINTK(qdev, PROBE, ALERT, "Bad Semaphore mask!.\n");
124 ql_write32(qdev, SEM, sem_bits | sem_mask);
125 return !(ql_read32(qdev, SEM) & sem_bits);
128 int ql_sem_spinlock(struct ql_adapter *qdev, u32 sem_mask)
130 unsigned int wait_count = 30;
132 if (!ql_sem_trylock(qdev, sem_mask))
135 } while (--wait_count);
139 void ql_sem_unlock(struct ql_adapter *qdev, u32 sem_mask)
141 ql_write32(qdev, SEM, sem_mask);
142 ql_read32(qdev, SEM); /* flush */
145 /* This function waits for a specific bit to come ready
146 * in a given register. It is used mostly by the initialize
147 * process, but is also used in kernel thread API such as
148 * netdev->set_multi, netdev->set_mac_address, netdev->vlan_rx_add_vid.
150 int ql_wait_reg_rdy(struct ql_adapter *qdev, u32 reg, u32 bit, u32 err_bit)
153 int count = UDELAY_COUNT;
156 temp = ql_read32(qdev, reg);
158 /* check for errors */
159 if (temp & err_bit) {
160 QPRINTK(qdev, PROBE, ALERT,
161 "register 0x%.08x access error, value = 0x%.08x!.\n",
164 } else if (temp & bit)
166 udelay(UDELAY_DELAY);
169 QPRINTK(qdev, PROBE, ALERT,
170 "Timed out waiting for reg %x to come ready.\n", reg);
174 /* The CFG register is used to download TX and RX control blocks
175 * to the chip. This function waits for an operation to complete.
177 static int ql_wait_cfg(struct ql_adapter *qdev, u32 bit)
179 int count = UDELAY_COUNT;
183 temp = ql_read32(qdev, CFG);
188 udelay(UDELAY_DELAY);
195 /* Used to issue init control blocks to hw. Maps control block,
196 * sets address, triggers download, waits for completion.
198 int ql_write_cfg(struct ql_adapter *qdev, void *ptr, int size, u32 bit,
208 (bit & (CFG_LRQ | CFG_LR | CFG_LCQ)) ? PCI_DMA_TODEVICE :
211 map = pci_map_single(qdev->pdev, ptr, size, direction);
212 if (pci_dma_mapping_error(qdev->pdev, map)) {
213 QPRINTK(qdev, IFUP, ERR, "Couldn't map DMA area.\n");
217 status = ql_wait_cfg(qdev, bit);
219 QPRINTK(qdev, IFUP, ERR,
220 "Timed out waiting for CFG to come ready.\n");
224 status = ql_sem_spinlock(qdev, SEM_ICB_MASK);
227 ql_write32(qdev, ICB_L, (u32) map);
228 ql_write32(qdev, ICB_H, (u32) (map >> 32));
229 ql_sem_unlock(qdev, SEM_ICB_MASK); /* does flush too */
231 mask = CFG_Q_MASK | (bit << 16);
232 value = bit | (q_id << CFG_Q_SHIFT);
233 ql_write32(qdev, CFG, (mask | value));
236 * Wait for the bit to clear after signaling hw.
238 status = ql_wait_cfg(qdev, bit);
240 pci_unmap_single(qdev->pdev, map, size, direction);
244 /* Get a specific MAC address from the CAM. Used for debug and reg dump. */
245 int ql_get_mac_addr_reg(struct ql_adapter *qdev, u32 type, u16 index,
252 case MAC_ADDR_TYPE_MULTI_MAC:
253 case MAC_ADDR_TYPE_CAM_MAC:
256 ql_wait_reg_rdy(qdev,
257 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
260 ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
261 (index << MAC_ADDR_IDX_SHIFT) | /* index */
262 MAC_ADDR_ADR | MAC_ADDR_RS | type); /* type */
264 ql_wait_reg_rdy(qdev,
265 MAC_ADDR_IDX, MAC_ADDR_MR, 0);
268 *value++ = ql_read32(qdev, MAC_ADDR_DATA);
270 ql_wait_reg_rdy(qdev,
271 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
274 ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
275 (index << MAC_ADDR_IDX_SHIFT) | /* index */
276 MAC_ADDR_ADR | MAC_ADDR_RS | type); /* type */
278 ql_wait_reg_rdy(qdev,
279 MAC_ADDR_IDX, MAC_ADDR_MR, 0);
282 *value++ = ql_read32(qdev, MAC_ADDR_DATA);
283 if (type == MAC_ADDR_TYPE_CAM_MAC) {
285 ql_wait_reg_rdy(qdev,
286 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
289 ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
290 (index << MAC_ADDR_IDX_SHIFT) | /* index */
291 MAC_ADDR_ADR | MAC_ADDR_RS | type); /* type */
293 ql_wait_reg_rdy(qdev, MAC_ADDR_IDX,
297 *value++ = ql_read32(qdev, MAC_ADDR_DATA);
301 case MAC_ADDR_TYPE_VLAN:
302 case MAC_ADDR_TYPE_MULTI_FLTR:
304 QPRINTK(qdev, IFUP, CRIT,
305 "Address type %d not yet supported.\n", type);
312 /* Set up a MAC, multicast or VLAN address for the
313 * inbound frame matching.
315 static int ql_set_mac_addr_reg(struct ql_adapter *qdev, u8 *addr, u32 type,
322 case MAC_ADDR_TYPE_MULTI_MAC:
323 case MAC_ADDR_TYPE_CAM_MAC:
326 u32 upper = (addr[0] << 8) | addr[1];
328 (addr[2] << 24) | (addr[3] << 16) | (addr[4] << 8) |
331 QPRINTK(qdev, IFUP, DEBUG,
332 "Adding %s address %pM"
333 " at index %d in the CAM.\n",
335 MAC_ADDR_TYPE_MULTI_MAC) ? "MULTICAST" :
336 "UNICAST"), addr, index);
339 ql_wait_reg_rdy(qdev,
340 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
343 ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
344 (index << MAC_ADDR_IDX_SHIFT) | /* index */
346 ql_write32(qdev, MAC_ADDR_DATA, lower);
348 ql_wait_reg_rdy(qdev,
349 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
352 ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
353 (index << MAC_ADDR_IDX_SHIFT) | /* index */
355 ql_write32(qdev, MAC_ADDR_DATA, upper);
357 ql_wait_reg_rdy(qdev,
358 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
361 ql_write32(qdev, MAC_ADDR_IDX, (offset) | /* offset */
362 (index << MAC_ADDR_IDX_SHIFT) | /* index */
364 /* This field should also include the queue id
365 and possibly the function id. Right now we hardcode
366 the route field to NIC core.
368 if (type == MAC_ADDR_TYPE_CAM_MAC) {
369 cam_output = (CAM_OUT_ROUTE_NIC |
371 func << CAM_OUT_FUNC_SHIFT) |
373 rss_ring_first_cq_id <<
374 CAM_OUT_CQ_ID_SHIFT));
376 cam_output |= CAM_OUT_RV;
377 /* route to NIC core */
378 ql_write32(qdev, MAC_ADDR_DATA, cam_output);
382 case MAC_ADDR_TYPE_VLAN:
384 u32 enable_bit = *((u32 *) &addr[0]);
385 /* For VLAN, the addr actually holds a bit that
386 * either enables or disables the vlan id we are
387 * addressing. It's either MAC_ADDR_E on or off.
388 * That's bit-27 we're talking about.
390 QPRINTK(qdev, IFUP, INFO, "%s VLAN ID %d %s the CAM.\n",
391 (enable_bit ? "Adding" : "Removing"),
392 index, (enable_bit ? "to" : "from"));
395 ql_wait_reg_rdy(qdev,
396 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
399 ql_write32(qdev, MAC_ADDR_IDX, offset | /* offset */
400 (index << MAC_ADDR_IDX_SHIFT) | /* index */
402 enable_bit); /* enable/disable */
405 case MAC_ADDR_TYPE_MULTI_FLTR:
407 QPRINTK(qdev, IFUP, CRIT,
408 "Address type %d not yet supported.\n", type);
415 /* Get a specific frame routing value from the CAM.
416 * Used for debug and reg dump.
418 int ql_get_routing_reg(struct ql_adapter *qdev, u32 index, u32 *value)
422 status = ql_wait_reg_rdy(qdev, RT_IDX, RT_IDX_MW, 0);
426 ql_write32(qdev, RT_IDX,
427 RT_IDX_TYPE_NICQ | RT_IDX_RS | (index << RT_IDX_IDX_SHIFT));
428 status = ql_wait_reg_rdy(qdev, RT_IDX, RT_IDX_MR, 0);
431 *value = ql_read32(qdev, RT_DATA);
436 /* The NIC function for this chip has 16 routing indexes. Each one can be used
437 * to route different frame types to various inbound queues. We send broadcast/
438 * multicast/error frames to the default queue for slow handling,
439 * and CAM hit/RSS frames to the fast handling queues.
441 static int ql_set_routing_reg(struct ql_adapter *qdev, u32 index, u32 mask,
444 int status = -EINVAL; /* Return error if no mask match. */
447 QPRINTK(qdev, IFUP, DEBUG,
448 "%s %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s mask %s the routing reg.\n",
449 (enable ? "Adding" : "Removing"),
450 ((index == RT_IDX_ALL_ERR_SLOT) ? "MAC ERROR/ALL ERROR" : ""),
451 ((index == RT_IDX_IP_CSUM_ERR_SLOT) ? "IP CSUM ERROR" : ""),
453 RT_IDX_TCP_UDP_CSUM_ERR_SLOT) ? "TCP/UDP CSUM ERROR" : ""),
454 ((index == RT_IDX_BCAST_SLOT) ? "BROADCAST" : ""),
455 ((index == RT_IDX_MCAST_MATCH_SLOT) ? "MULTICAST MATCH" : ""),
456 ((index == RT_IDX_ALLMULTI_SLOT) ? "ALL MULTICAST MATCH" : ""),
457 ((index == RT_IDX_UNUSED6_SLOT) ? "UNUSED6" : ""),
458 ((index == RT_IDX_UNUSED7_SLOT) ? "UNUSED7" : ""),
459 ((index == RT_IDX_RSS_MATCH_SLOT) ? "RSS ALL/IPV4 MATCH" : ""),
460 ((index == RT_IDX_RSS_IPV6_SLOT) ? "RSS IPV6" : ""),
461 ((index == RT_IDX_RSS_TCP4_SLOT) ? "RSS TCP4" : ""),
462 ((index == RT_IDX_RSS_TCP6_SLOT) ? "RSS TCP6" : ""),
463 ((index == RT_IDX_CAM_HIT_SLOT) ? "CAM HIT" : ""),
464 ((index == RT_IDX_UNUSED013) ? "UNUSED13" : ""),
465 ((index == RT_IDX_UNUSED014) ? "UNUSED14" : ""),
466 ((index == RT_IDX_PROMISCUOUS_SLOT) ? "PROMISCUOUS" : ""),
467 (enable ? "to" : "from"));
472 value = RT_IDX_DST_CAM_Q | /* dest */
473 RT_IDX_TYPE_NICQ | /* type */
474 (RT_IDX_CAM_HIT_SLOT << RT_IDX_IDX_SHIFT);/* index */
477 case RT_IDX_VALID: /* Promiscuous Mode frames. */
479 value = RT_IDX_DST_DFLT_Q | /* dest */
480 RT_IDX_TYPE_NICQ | /* type */
481 (RT_IDX_PROMISCUOUS_SLOT << RT_IDX_IDX_SHIFT);/* index */
484 case RT_IDX_ERR: /* Pass up MAC,IP,TCP/UDP error frames. */
486 value = RT_IDX_DST_DFLT_Q | /* dest */
487 RT_IDX_TYPE_NICQ | /* type */
488 (RT_IDX_ALL_ERR_SLOT << RT_IDX_IDX_SHIFT);/* index */
491 case RT_IDX_BCAST: /* Pass up Broadcast frames to default Q. */
493 value = RT_IDX_DST_DFLT_Q | /* dest */
494 RT_IDX_TYPE_NICQ | /* type */
495 (RT_IDX_BCAST_SLOT << RT_IDX_IDX_SHIFT);/* index */
498 case RT_IDX_MCAST: /* Pass up All Multicast frames. */
500 value = RT_IDX_DST_CAM_Q | /* dest */
501 RT_IDX_TYPE_NICQ | /* type */
502 (RT_IDX_ALLMULTI_SLOT << RT_IDX_IDX_SHIFT);/* index */
505 case RT_IDX_MCAST_MATCH: /* Pass up matched Multicast frames. */
507 value = RT_IDX_DST_CAM_Q | /* dest */
508 RT_IDX_TYPE_NICQ | /* type */
509 (RT_IDX_MCAST_MATCH_SLOT << RT_IDX_IDX_SHIFT);/* index */
512 case RT_IDX_RSS_MATCH: /* Pass up matched RSS frames. */
514 value = RT_IDX_DST_RSS | /* dest */
515 RT_IDX_TYPE_NICQ | /* type */
516 (RT_IDX_RSS_MATCH_SLOT << RT_IDX_IDX_SHIFT);/* index */
519 case 0: /* Clear the E-bit on an entry. */
521 value = RT_IDX_DST_DFLT_Q | /* dest */
522 RT_IDX_TYPE_NICQ | /* type */
523 (index << RT_IDX_IDX_SHIFT);/* index */
527 QPRINTK(qdev, IFUP, ERR, "Mask type %d not yet supported.\n",
534 status = ql_wait_reg_rdy(qdev, RT_IDX, RT_IDX_MW, 0);
537 value |= (enable ? RT_IDX_E : 0);
538 ql_write32(qdev, RT_IDX, value);
539 ql_write32(qdev, RT_DATA, enable ? mask : 0);
545 static void ql_enable_interrupts(struct ql_adapter *qdev)
547 ql_write32(qdev, INTR_EN, (INTR_EN_EI << 16) | INTR_EN_EI);
550 static void ql_disable_interrupts(struct ql_adapter *qdev)
552 ql_write32(qdev, INTR_EN, (INTR_EN_EI << 16));
555 /* If we're running with multiple MSI-X vectors then we enable on the fly.
556 * Otherwise, we may have multiple outstanding workers and don't want to
557 * enable until the last one finishes. In this case, the irq_cnt gets
558 * incremented everytime we queue a worker and decremented everytime
559 * a worker finishes. Once it hits zero we enable the interrupt.
561 u32 ql_enable_completion_interrupt(struct ql_adapter *qdev, u32 intr)
564 unsigned long hw_flags = 0;
565 struct intr_context *ctx = qdev->intr_context + intr;
567 if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags) && intr)) {
568 /* Always enable if we're MSIX multi interrupts and
569 * it's not the default (zeroeth) interrupt.
571 ql_write32(qdev, INTR_EN,
573 var = ql_read32(qdev, STS);
577 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
578 if (atomic_dec_and_test(&ctx->irq_cnt)) {
579 ql_write32(qdev, INTR_EN,
581 var = ql_read32(qdev, STS);
583 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
587 static u32 ql_disable_completion_interrupt(struct ql_adapter *qdev, u32 intr)
590 struct intr_context *ctx;
592 /* HW disables for us if we're MSIX multi interrupts and
593 * it's not the default (zeroeth) interrupt.
595 if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags) && intr))
598 ctx = qdev->intr_context + intr;
599 spin_lock(&qdev->hw_lock);
600 if (!atomic_read(&ctx->irq_cnt)) {
601 ql_write32(qdev, INTR_EN,
603 var = ql_read32(qdev, STS);
605 atomic_inc(&ctx->irq_cnt);
606 spin_unlock(&qdev->hw_lock);
610 static void ql_enable_all_completion_interrupts(struct ql_adapter *qdev)
613 for (i = 0; i < qdev->intr_count; i++) {
614 /* The enable call does a atomic_dec_and_test
615 * and enables only if the result is zero.
616 * So we precharge it here.
618 if (unlikely(!test_bit(QL_MSIX_ENABLED, &qdev->flags) ||
620 atomic_set(&qdev->intr_context[i].irq_cnt, 1);
621 ql_enable_completion_interrupt(qdev, i);
626 static int ql_validate_flash(struct ql_adapter *qdev, u32 size, const char *str)
630 __le16 *flash = (__le16 *)&qdev->flash;
632 status = strncmp((char *)&qdev->flash, str, 4);
634 QPRINTK(qdev, IFUP, ERR, "Invalid flash signature.\n");
638 for (i = 0; i < size; i++)
639 csum += le16_to_cpu(*flash++);
642 QPRINTK(qdev, IFUP, ERR,
643 "Invalid flash checksum, csum = 0x%.04x.\n", csum);
648 static int ql_read_flash_word(struct ql_adapter *qdev, int offset, __le32 *data)
651 /* wait for reg to come ready */
652 status = ql_wait_reg_rdy(qdev,
653 FLASH_ADDR, FLASH_ADDR_RDY, FLASH_ADDR_ERR);
656 /* set up for reg read */
657 ql_write32(qdev, FLASH_ADDR, FLASH_ADDR_R | offset);
658 /* wait for reg to come ready */
659 status = ql_wait_reg_rdy(qdev,
660 FLASH_ADDR, FLASH_ADDR_RDY, FLASH_ADDR_ERR);
663 /* This data is stored on flash as an array of
664 * __le32. Since ql_read32() returns cpu endian
665 * we need to swap it back.
667 *data = cpu_to_le32(ql_read32(qdev, FLASH_DATA));
672 static int ql_get_8000_flash_params(struct ql_adapter *qdev)
676 __le32 *p = (__le32 *)&qdev->flash;
679 /* Get flash offset for function and adjust
683 offset = FUNC0_FLASH_OFFSET / sizeof(u32);
685 offset = FUNC1_FLASH_OFFSET / sizeof(u32);
687 if (ql_sem_spinlock(qdev, SEM_FLASH_MASK))
690 size = sizeof(struct flash_params_8000) / sizeof(u32);
691 for (i = 0; i < size; i++, p++) {
692 status = ql_read_flash_word(qdev, i+offset, p);
694 QPRINTK(qdev, IFUP, ERR, "Error reading flash.\n");
699 status = ql_validate_flash(qdev,
700 sizeof(struct flash_params_8000) / sizeof(u16),
703 QPRINTK(qdev, IFUP, ERR, "Invalid flash.\n");
708 if (!is_valid_ether_addr(qdev->flash.flash_params_8000.mac_addr)) {
709 QPRINTK(qdev, IFUP, ERR, "Invalid MAC address.\n");
714 memcpy(qdev->ndev->dev_addr,
715 qdev->flash.flash_params_8000.mac_addr,
716 qdev->ndev->addr_len);
719 ql_sem_unlock(qdev, SEM_FLASH_MASK);
723 static int ql_get_8012_flash_params(struct ql_adapter *qdev)
727 __le32 *p = (__le32 *)&qdev->flash;
729 u32 size = sizeof(struct flash_params_8012) / sizeof(u32);
731 /* Second function's parameters follow the first
737 if (ql_sem_spinlock(qdev, SEM_FLASH_MASK))
740 for (i = 0; i < size; i++, p++) {
741 status = ql_read_flash_word(qdev, i+offset, p);
743 QPRINTK(qdev, IFUP, ERR, "Error reading flash.\n");
749 status = ql_validate_flash(qdev,
750 sizeof(struct flash_params_8012) / sizeof(u16),
753 QPRINTK(qdev, IFUP, ERR, "Invalid flash.\n");
758 if (!is_valid_ether_addr(qdev->flash.flash_params_8012.mac_addr)) {
763 memcpy(qdev->ndev->dev_addr,
764 qdev->flash.flash_params_8012.mac_addr,
765 qdev->ndev->addr_len);
768 ql_sem_unlock(qdev, SEM_FLASH_MASK);
772 /* xgmac register are located behind the xgmac_addr and xgmac_data
773 * register pair. Each read/write requires us to wait for the ready
774 * bit before reading/writing the data.
776 static int ql_write_xgmac_reg(struct ql_adapter *qdev, u32 reg, u32 data)
779 /* wait for reg to come ready */
780 status = ql_wait_reg_rdy(qdev,
781 XGMAC_ADDR, XGMAC_ADDR_RDY, XGMAC_ADDR_XME);
784 /* write the data to the data reg */
785 ql_write32(qdev, XGMAC_DATA, data);
786 /* trigger the write */
787 ql_write32(qdev, XGMAC_ADDR, reg);
791 /* xgmac register are located behind the xgmac_addr and xgmac_data
792 * register pair. Each read/write requires us to wait for the ready
793 * bit before reading/writing the data.
795 int ql_read_xgmac_reg(struct ql_adapter *qdev, u32 reg, u32 *data)
798 /* wait for reg to come ready */
799 status = ql_wait_reg_rdy(qdev,
800 XGMAC_ADDR, XGMAC_ADDR_RDY, XGMAC_ADDR_XME);
803 /* set up for reg read */
804 ql_write32(qdev, XGMAC_ADDR, reg | XGMAC_ADDR_R);
805 /* wait for reg to come ready */
806 status = ql_wait_reg_rdy(qdev,
807 XGMAC_ADDR, XGMAC_ADDR_RDY, XGMAC_ADDR_XME);
811 *data = ql_read32(qdev, XGMAC_DATA);
816 /* This is used for reading the 64-bit statistics regs. */
817 int ql_read_xgmac_reg64(struct ql_adapter *qdev, u32 reg, u64 *data)
823 status = ql_read_xgmac_reg(qdev, reg, &lo);
827 status = ql_read_xgmac_reg(qdev, reg + 4, &hi);
831 *data = (u64) lo | ((u64) hi << 32);
837 static int ql_8000_port_initialize(struct ql_adapter *qdev)
840 status = ql_mb_get_fw_state(qdev);
843 /* Wake up a worker to get/set the TX/RX frame sizes. */
844 queue_delayed_work(qdev->workqueue, &qdev->mpi_port_cfg_work, 0);
849 /* Take the MAC Core out of reset.
850 * Enable statistics counting.
851 * Take the transmitter/receiver out of reset.
852 * This functionality may be done in the MPI firmware at a
855 static int ql_8012_port_initialize(struct ql_adapter *qdev)
860 if (ql_sem_trylock(qdev, qdev->xg_sem_mask)) {
861 /* Another function has the semaphore, so
862 * wait for the port init bit to come ready.
864 QPRINTK(qdev, LINK, INFO,
865 "Another function has the semaphore, so wait for the port init bit to come ready.\n");
866 status = ql_wait_reg_rdy(qdev, STS, qdev->port_init, 0);
868 QPRINTK(qdev, LINK, CRIT,
869 "Port initialize timed out.\n");
874 QPRINTK(qdev, LINK, INFO, "Got xgmac semaphore!.\n");
875 /* Set the core reset. */
876 status = ql_read_xgmac_reg(qdev, GLOBAL_CFG, &data);
879 data |= GLOBAL_CFG_RESET;
880 status = ql_write_xgmac_reg(qdev, GLOBAL_CFG, data);
884 /* Clear the core reset and turn on jumbo for receiver. */
885 data &= ~GLOBAL_CFG_RESET; /* Clear core reset. */
886 data |= GLOBAL_CFG_JUMBO; /* Turn on jumbo. */
887 data |= GLOBAL_CFG_TX_STAT_EN;
888 data |= GLOBAL_CFG_RX_STAT_EN;
889 status = ql_write_xgmac_reg(qdev, GLOBAL_CFG, data);
893 /* Enable transmitter, and clear it's reset. */
894 status = ql_read_xgmac_reg(qdev, TX_CFG, &data);
897 data &= ~TX_CFG_RESET; /* Clear the TX MAC reset. */
898 data |= TX_CFG_EN; /* Enable the transmitter. */
899 status = ql_write_xgmac_reg(qdev, TX_CFG, data);
903 /* Enable receiver and clear it's reset. */
904 status = ql_read_xgmac_reg(qdev, RX_CFG, &data);
907 data &= ~RX_CFG_RESET; /* Clear the RX MAC reset. */
908 data |= RX_CFG_EN; /* Enable the receiver. */
909 status = ql_write_xgmac_reg(qdev, RX_CFG, data);
915 ql_write_xgmac_reg(qdev, MAC_TX_PARAMS, MAC_TX_PARAMS_JUMBO | (0x2580 << 16));
919 ql_write_xgmac_reg(qdev, MAC_RX_PARAMS, 0x2580);
923 /* Signal to the world that the port is enabled. */
924 ql_write32(qdev, STS, ((qdev->port_init << 16) | qdev->port_init));
926 ql_sem_unlock(qdev, qdev->xg_sem_mask);
930 /* Get the next large buffer. */
931 static struct bq_desc *ql_get_curr_lbuf(struct rx_ring *rx_ring)
933 struct bq_desc *lbq_desc = &rx_ring->lbq[rx_ring->lbq_curr_idx];
934 rx_ring->lbq_curr_idx++;
935 if (rx_ring->lbq_curr_idx == rx_ring->lbq_len)
936 rx_ring->lbq_curr_idx = 0;
937 rx_ring->lbq_free_cnt++;
941 /* Get the next small buffer. */
942 static struct bq_desc *ql_get_curr_sbuf(struct rx_ring *rx_ring)
944 struct bq_desc *sbq_desc = &rx_ring->sbq[rx_ring->sbq_curr_idx];
945 rx_ring->sbq_curr_idx++;
946 if (rx_ring->sbq_curr_idx == rx_ring->sbq_len)
947 rx_ring->sbq_curr_idx = 0;
948 rx_ring->sbq_free_cnt++;
952 /* Update an rx ring index. */
953 static void ql_update_cq(struct rx_ring *rx_ring)
955 rx_ring->cnsmr_idx++;
956 rx_ring->curr_entry++;
957 if (unlikely(rx_ring->cnsmr_idx == rx_ring->cq_len)) {
958 rx_ring->cnsmr_idx = 0;
959 rx_ring->curr_entry = rx_ring->cq_base;
963 static void ql_write_cq_idx(struct rx_ring *rx_ring)
965 ql_write_db_reg(rx_ring->cnsmr_idx, rx_ring->cnsmr_idx_db_reg);
968 /* Process (refill) a large buffer queue. */
969 static void ql_update_lbq(struct ql_adapter *qdev, struct rx_ring *rx_ring)
971 u32 clean_idx = rx_ring->lbq_clean_idx;
972 u32 start_idx = clean_idx;
973 struct bq_desc *lbq_desc;
977 while (rx_ring->lbq_free_cnt > 16) {
978 for (i = 0; i < 16; i++) {
979 QPRINTK(qdev, RX_STATUS, DEBUG,
980 "lbq: try cleaning clean_idx = %d.\n",
982 lbq_desc = &rx_ring->lbq[clean_idx];
983 if (lbq_desc->p.lbq_page == NULL) {
984 QPRINTK(qdev, RX_STATUS, DEBUG,
985 "lbq: getting new page for index %d.\n",
987 lbq_desc->p.lbq_page = alloc_page(GFP_ATOMIC);
988 if (lbq_desc->p.lbq_page == NULL) {
989 rx_ring->lbq_clean_idx = clean_idx;
990 QPRINTK(qdev, RX_STATUS, ERR,
991 "Couldn't get a page.\n");
994 map = pci_map_page(qdev->pdev,
995 lbq_desc->p.lbq_page,
998 if (pci_dma_mapping_error(qdev->pdev, map)) {
999 rx_ring->lbq_clean_idx = clean_idx;
1000 put_page(lbq_desc->p.lbq_page);
1001 lbq_desc->p.lbq_page = NULL;
1002 QPRINTK(qdev, RX_STATUS, ERR,
1003 "PCI mapping failed.\n");
1006 pci_unmap_addr_set(lbq_desc, mapaddr, map);
1007 pci_unmap_len_set(lbq_desc, maplen, PAGE_SIZE);
1008 *lbq_desc->addr = cpu_to_le64(map);
1011 if (clean_idx == rx_ring->lbq_len)
1015 rx_ring->lbq_clean_idx = clean_idx;
1016 rx_ring->lbq_prod_idx += 16;
1017 if (rx_ring->lbq_prod_idx == rx_ring->lbq_len)
1018 rx_ring->lbq_prod_idx = 0;
1019 rx_ring->lbq_free_cnt -= 16;
1022 if (start_idx != clean_idx) {
1023 QPRINTK(qdev, RX_STATUS, DEBUG,
1024 "lbq: updating prod idx = %d.\n",
1025 rx_ring->lbq_prod_idx);
1026 ql_write_db_reg(rx_ring->lbq_prod_idx,
1027 rx_ring->lbq_prod_idx_db_reg);
1031 /* Process (refill) a small buffer queue. */
1032 static void ql_update_sbq(struct ql_adapter *qdev, struct rx_ring *rx_ring)
1034 u32 clean_idx = rx_ring->sbq_clean_idx;
1035 u32 start_idx = clean_idx;
1036 struct bq_desc *sbq_desc;
1040 while (rx_ring->sbq_free_cnt > 16) {
1041 for (i = 0; i < 16; i++) {
1042 sbq_desc = &rx_ring->sbq[clean_idx];
1043 QPRINTK(qdev, RX_STATUS, DEBUG,
1044 "sbq: try cleaning clean_idx = %d.\n",
1046 if (sbq_desc->p.skb == NULL) {
1047 QPRINTK(qdev, RX_STATUS, DEBUG,
1048 "sbq: getting new skb for index %d.\n",
1051 netdev_alloc_skb(qdev->ndev,
1052 rx_ring->sbq_buf_size);
1053 if (sbq_desc->p.skb == NULL) {
1054 QPRINTK(qdev, PROBE, ERR,
1055 "Couldn't get an skb.\n");
1056 rx_ring->sbq_clean_idx = clean_idx;
1059 skb_reserve(sbq_desc->p.skb, QLGE_SB_PAD);
1060 map = pci_map_single(qdev->pdev,
1061 sbq_desc->p.skb->data,
1062 rx_ring->sbq_buf_size /
1063 2, PCI_DMA_FROMDEVICE);
1064 if (pci_dma_mapping_error(qdev->pdev, map)) {
1065 QPRINTK(qdev, IFUP, ERR, "PCI mapping failed.\n");
1066 rx_ring->sbq_clean_idx = clean_idx;
1067 dev_kfree_skb_any(sbq_desc->p.skb);
1068 sbq_desc->p.skb = NULL;
1071 pci_unmap_addr_set(sbq_desc, mapaddr, map);
1072 pci_unmap_len_set(sbq_desc, maplen,
1073 rx_ring->sbq_buf_size / 2);
1074 *sbq_desc->addr = cpu_to_le64(map);
1078 if (clean_idx == rx_ring->sbq_len)
1081 rx_ring->sbq_clean_idx = clean_idx;
1082 rx_ring->sbq_prod_idx += 16;
1083 if (rx_ring->sbq_prod_idx == rx_ring->sbq_len)
1084 rx_ring->sbq_prod_idx = 0;
1085 rx_ring->sbq_free_cnt -= 16;
1088 if (start_idx != clean_idx) {
1089 QPRINTK(qdev, RX_STATUS, DEBUG,
1090 "sbq: updating prod idx = %d.\n",
1091 rx_ring->sbq_prod_idx);
1092 ql_write_db_reg(rx_ring->sbq_prod_idx,
1093 rx_ring->sbq_prod_idx_db_reg);
1097 static void ql_update_buffer_queues(struct ql_adapter *qdev,
1098 struct rx_ring *rx_ring)
1100 ql_update_sbq(qdev, rx_ring);
1101 ql_update_lbq(qdev, rx_ring);
1104 /* Unmaps tx buffers. Can be called from send() if a pci mapping
1105 * fails at some stage, or from the interrupt when a tx completes.
1107 static void ql_unmap_send(struct ql_adapter *qdev,
1108 struct tx_ring_desc *tx_ring_desc, int mapped)
1111 for (i = 0; i < mapped; i++) {
1112 if (i == 0 || (i == 7 && mapped > 7)) {
1114 * Unmap the skb->data area, or the
1115 * external sglist (AKA the Outbound
1116 * Address List (OAL)).
1117 * If its the zeroeth element, then it's
1118 * the skb->data area. If it's the 7th
1119 * element and there is more than 6 frags,
1123 QPRINTK(qdev, TX_DONE, DEBUG,
1124 "unmapping OAL area.\n");
1126 pci_unmap_single(qdev->pdev,
1127 pci_unmap_addr(&tx_ring_desc->map[i],
1129 pci_unmap_len(&tx_ring_desc->map[i],
1133 QPRINTK(qdev, TX_DONE, DEBUG, "unmapping frag %d.\n",
1135 pci_unmap_page(qdev->pdev,
1136 pci_unmap_addr(&tx_ring_desc->map[i],
1138 pci_unmap_len(&tx_ring_desc->map[i],
1139 maplen), PCI_DMA_TODEVICE);
1145 /* Map the buffers for this transmit. This will return
1146 * NETDEV_TX_BUSY or NETDEV_TX_OK based on success.
1148 static int ql_map_send(struct ql_adapter *qdev,
1149 struct ob_mac_iocb_req *mac_iocb_ptr,
1150 struct sk_buff *skb, struct tx_ring_desc *tx_ring_desc)
1152 int len = skb_headlen(skb);
1154 int frag_idx, err, map_idx = 0;
1155 struct tx_buf_desc *tbd = mac_iocb_ptr->tbd;
1156 int frag_cnt = skb_shinfo(skb)->nr_frags;
1159 QPRINTK(qdev, TX_QUEUED, DEBUG, "frag_cnt = %d.\n", frag_cnt);
1162 * Map the skb buffer first.
1164 map = pci_map_single(qdev->pdev, skb->data, len, PCI_DMA_TODEVICE);
1166 err = pci_dma_mapping_error(qdev->pdev, map);
1168 QPRINTK(qdev, TX_QUEUED, ERR,
1169 "PCI mapping failed with error: %d\n", err);
1171 return NETDEV_TX_BUSY;
1174 tbd->len = cpu_to_le32(len);
1175 tbd->addr = cpu_to_le64(map);
1176 pci_unmap_addr_set(&tx_ring_desc->map[map_idx], mapaddr, map);
1177 pci_unmap_len_set(&tx_ring_desc->map[map_idx], maplen, len);
1181 * This loop fills the remainder of the 8 address descriptors
1182 * in the IOCB. If there are more than 7 fragments, then the
1183 * eighth address desc will point to an external list (OAL).
1184 * When this happens, the remainder of the frags will be stored
1187 for (frag_idx = 0; frag_idx < frag_cnt; frag_idx++, map_idx++) {
1188 skb_frag_t *frag = &skb_shinfo(skb)->frags[frag_idx];
1190 if (frag_idx == 6 && frag_cnt > 7) {
1191 /* Let's tack on an sglist.
1192 * Our control block will now
1194 * iocb->seg[0] = skb->data
1195 * iocb->seg[1] = frag[0]
1196 * iocb->seg[2] = frag[1]
1197 * iocb->seg[3] = frag[2]
1198 * iocb->seg[4] = frag[3]
1199 * iocb->seg[5] = frag[4]
1200 * iocb->seg[6] = frag[5]
1201 * iocb->seg[7] = ptr to OAL (external sglist)
1202 * oal->seg[0] = frag[6]
1203 * oal->seg[1] = frag[7]
1204 * oal->seg[2] = frag[8]
1205 * oal->seg[3] = frag[9]
1206 * oal->seg[4] = frag[10]
1209 /* Tack on the OAL in the eighth segment of IOCB. */
1210 map = pci_map_single(qdev->pdev, &tx_ring_desc->oal,
1213 err = pci_dma_mapping_error(qdev->pdev, map);
1215 QPRINTK(qdev, TX_QUEUED, ERR,
1216 "PCI mapping outbound address list with error: %d\n",
1221 tbd->addr = cpu_to_le64(map);
1223 * The length is the number of fragments
1224 * that remain to be mapped times the length
1225 * of our sglist (OAL).
1228 cpu_to_le32((sizeof(struct tx_buf_desc) *
1229 (frag_cnt - frag_idx)) | TX_DESC_C);
1230 pci_unmap_addr_set(&tx_ring_desc->map[map_idx], mapaddr,
1232 pci_unmap_len_set(&tx_ring_desc->map[map_idx], maplen,
1233 sizeof(struct oal));
1234 tbd = (struct tx_buf_desc *)&tx_ring_desc->oal;
1239 pci_map_page(qdev->pdev, frag->page,
1240 frag->page_offset, frag->size,
1243 err = pci_dma_mapping_error(qdev->pdev, map);
1245 QPRINTK(qdev, TX_QUEUED, ERR,
1246 "PCI mapping frags failed with error: %d.\n",
1251 tbd->addr = cpu_to_le64(map);
1252 tbd->len = cpu_to_le32(frag->size);
1253 pci_unmap_addr_set(&tx_ring_desc->map[map_idx], mapaddr, map);
1254 pci_unmap_len_set(&tx_ring_desc->map[map_idx], maplen,
1258 /* Save the number of segments we've mapped. */
1259 tx_ring_desc->map_cnt = map_idx;
1260 /* Terminate the last segment. */
1261 tbd->len = cpu_to_le32(le32_to_cpu(tbd->len) | TX_DESC_E);
1262 return NETDEV_TX_OK;
1266 * If the first frag mapping failed, then i will be zero.
1267 * This causes the unmap of the skb->data area. Otherwise
1268 * we pass in the number of frags that mapped successfully
1269 * so they can be umapped.
1271 ql_unmap_send(qdev, tx_ring_desc, map_idx);
1272 return NETDEV_TX_BUSY;
1275 static void ql_realign_skb(struct sk_buff *skb, int len)
1277 void *temp_addr = skb->data;
1279 /* Undo the skb_reserve(skb,32) we did before
1280 * giving to hardware, and realign data on
1281 * a 2-byte boundary.
1283 skb->data -= QLGE_SB_PAD - NET_IP_ALIGN;
1284 skb->tail -= QLGE_SB_PAD - NET_IP_ALIGN;
1285 skb_copy_to_linear_data(skb, temp_addr,
1290 * This function builds an skb for the given inbound
1291 * completion. It will be rewritten for readability in the near
1292 * future, but for not it works well.
1294 static struct sk_buff *ql_build_rx_skb(struct ql_adapter *qdev,
1295 struct rx_ring *rx_ring,
1296 struct ib_mac_iocb_rsp *ib_mac_rsp)
1298 struct bq_desc *lbq_desc;
1299 struct bq_desc *sbq_desc;
1300 struct sk_buff *skb = NULL;
1301 u32 length = le32_to_cpu(ib_mac_rsp->data_len);
1302 u32 hdr_len = le32_to_cpu(ib_mac_rsp->hdr_len);
1305 * Handle the header buffer if present.
1307 if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HV &&
1308 ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS) {
1309 QPRINTK(qdev, RX_STATUS, DEBUG, "Header of %d bytes in small buffer.\n", hdr_len);
1311 * Headers fit nicely into a small buffer.
1313 sbq_desc = ql_get_curr_sbuf(rx_ring);
1314 pci_unmap_single(qdev->pdev,
1315 pci_unmap_addr(sbq_desc, mapaddr),
1316 pci_unmap_len(sbq_desc, maplen),
1317 PCI_DMA_FROMDEVICE);
1318 skb = sbq_desc->p.skb;
1319 ql_realign_skb(skb, hdr_len);
1320 skb_put(skb, hdr_len);
1321 sbq_desc->p.skb = NULL;
1325 * Handle the data buffer(s).
1327 if (unlikely(!length)) { /* Is there data too? */
1328 QPRINTK(qdev, RX_STATUS, DEBUG,
1329 "No Data buffer in this packet.\n");
1333 if (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_DS) {
1334 if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS) {
1335 QPRINTK(qdev, RX_STATUS, DEBUG,
1336 "Headers in small, data of %d bytes in small, combine them.\n", length);
1338 * Data is less than small buffer size so it's
1339 * stuffed in a small buffer.
1340 * For this case we append the data
1341 * from the "data" small buffer to the "header" small
1344 sbq_desc = ql_get_curr_sbuf(rx_ring);
1345 pci_dma_sync_single_for_cpu(qdev->pdev,
1347 (sbq_desc, mapaddr),
1350 PCI_DMA_FROMDEVICE);
1351 memcpy(skb_put(skb, length),
1352 sbq_desc->p.skb->data, length);
1353 pci_dma_sync_single_for_device(qdev->pdev,
1360 PCI_DMA_FROMDEVICE);
1362 QPRINTK(qdev, RX_STATUS, DEBUG,
1363 "%d bytes in a single small buffer.\n", length);
1364 sbq_desc = ql_get_curr_sbuf(rx_ring);
1365 skb = sbq_desc->p.skb;
1366 ql_realign_skb(skb, length);
1367 skb_put(skb, length);
1368 pci_unmap_single(qdev->pdev,
1369 pci_unmap_addr(sbq_desc,
1371 pci_unmap_len(sbq_desc,
1373 PCI_DMA_FROMDEVICE);
1374 sbq_desc->p.skb = NULL;
1376 } else if (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_DL) {
1377 if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS) {
1378 QPRINTK(qdev, RX_STATUS, DEBUG,
1379 "Header in small, %d bytes in large. Chain large to small!\n", length);
1381 * The data is in a single large buffer. We
1382 * chain it to the header buffer's skb and let
1385 lbq_desc = ql_get_curr_lbuf(rx_ring);
1386 pci_unmap_page(qdev->pdev,
1387 pci_unmap_addr(lbq_desc,
1389 pci_unmap_len(lbq_desc, maplen),
1390 PCI_DMA_FROMDEVICE);
1391 QPRINTK(qdev, RX_STATUS, DEBUG,
1392 "Chaining page to skb.\n");
1393 skb_fill_page_desc(skb, 0, lbq_desc->p.lbq_page,
1396 skb->data_len += length;
1397 skb->truesize += length;
1398 lbq_desc->p.lbq_page = NULL;
1401 * The headers and data are in a single large buffer. We
1402 * copy it to a new skb and let it go. This can happen with
1403 * jumbo mtu on a non-TCP/UDP frame.
1405 lbq_desc = ql_get_curr_lbuf(rx_ring);
1406 skb = netdev_alloc_skb(qdev->ndev, length);
1408 QPRINTK(qdev, PROBE, DEBUG,
1409 "No skb available, drop the packet.\n");
1412 pci_unmap_page(qdev->pdev,
1413 pci_unmap_addr(lbq_desc,
1415 pci_unmap_len(lbq_desc, maplen),
1416 PCI_DMA_FROMDEVICE);
1417 skb_reserve(skb, NET_IP_ALIGN);
1418 QPRINTK(qdev, RX_STATUS, DEBUG,
1419 "%d bytes of headers and data in large. Chain page to new skb and pull tail.\n", length);
1420 skb_fill_page_desc(skb, 0, lbq_desc->p.lbq_page,
1423 skb->data_len += length;
1424 skb->truesize += length;
1426 lbq_desc->p.lbq_page = NULL;
1427 __pskb_pull_tail(skb,
1428 (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V) ?
1429 VLAN_ETH_HLEN : ETH_HLEN);
1433 * The data is in a chain of large buffers
1434 * pointed to by a small buffer. We loop
1435 * thru and chain them to the our small header
1437 * frags: There are 18 max frags and our small
1438 * buffer will hold 32 of them. The thing is,
1439 * we'll use 3 max for our 9000 byte jumbo
1440 * frames. If the MTU goes up we could
1441 * eventually be in trouble.
1443 int size, offset, i = 0;
1444 __le64 *bq, bq_array[8];
1445 sbq_desc = ql_get_curr_sbuf(rx_ring);
1446 pci_unmap_single(qdev->pdev,
1447 pci_unmap_addr(sbq_desc, mapaddr),
1448 pci_unmap_len(sbq_desc, maplen),
1449 PCI_DMA_FROMDEVICE);
1450 if (!(ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS)) {
1452 * This is an non TCP/UDP IP frame, so
1453 * the headers aren't split into a small
1454 * buffer. We have to use the small buffer
1455 * that contains our sg list as our skb to
1456 * send upstairs. Copy the sg list here to
1457 * a local buffer and use it to find the
1460 QPRINTK(qdev, RX_STATUS, DEBUG,
1461 "%d bytes of headers & data in chain of large.\n", length);
1462 skb = sbq_desc->p.skb;
1464 memcpy(bq, skb->data, sizeof(bq_array));
1465 sbq_desc->p.skb = NULL;
1466 skb_reserve(skb, NET_IP_ALIGN);
1468 QPRINTK(qdev, RX_STATUS, DEBUG,
1469 "Headers in small, %d bytes of data in chain of large.\n", length);
1470 bq = (__le64 *)sbq_desc->p.skb->data;
1472 while (length > 0) {
1473 lbq_desc = ql_get_curr_lbuf(rx_ring);
1474 pci_unmap_page(qdev->pdev,
1475 pci_unmap_addr(lbq_desc,
1477 pci_unmap_len(lbq_desc,
1479 PCI_DMA_FROMDEVICE);
1480 size = (length < PAGE_SIZE) ? length : PAGE_SIZE;
1483 QPRINTK(qdev, RX_STATUS, DEBUG,
1484 "Adding page %d to skb for %d bytes.\n",
1486 skb_fill_page_desc(skb, i, lbq_desc->p.lbq_page,
1489 skb->data_len += size;
1490 skb->truesize += size;
1492 lbq_desc->p.lbq_page = NULL;
1496 __pskb_pull_tail(skb, (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V) ?
1497 VLAN_ETH_HLEN : ETH_HLEN);
1502 /* Process an inbound completion from an rx ring. */
1503 static void ql_process_mac_rx_intr(struct ql_adapter *qdev,
1504 struct rx_ring *rx_ring,
1505 struct ib_mac_iocb_rsp *ib_mac_rsp)
1507 struct net_device *ndev = qdev->ndev;
1508 struct sk_buff *skb = NULL;
1509 u16 vlan_id = (le16_to_cpu(ib_mac_rsp->vlan_id) &
1510 IB_MAC_IOCB_RSP_VLAN_MASK)
1512 QL_DUMP_IB_MAC_RSP(ib_mac_rsp);
1514 skb = ql_build_rx_skb(qdev, rx_ring, ib_mac_rsp);
1515 if (unlikely(!skb)) {
1516 QPRINTK(qdev, RX_STATUS, DEBUG,
1517 "No skb available, drop packet.\n");
1521 prefetch(skb->data);
1523 if (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) {
1524 QPRINTK(qdev, RX_STATUS, DEBUG, "%s%s%s Multicast.\n",
1525 (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
1526 IB_MAC_IOCB_RSP_M_HASH ? "Hash" : "",
1527 (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
1528 IB_MAC_IOCB_RSP_M_REG ? "Registered" : "",
1529 (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
1530 IB_MAC_IOCB_RSP_M_PROM ? "Promiscuous" : "");
1532 if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_P) {
1533 QPRINTK(qdev, RX_STATUS, DEBUG, "Promiscuous Packet.\n");
1537 skb->protocol = eth_type_trans(skb, ndev);
1538 skb->ip_summed = CHECKSUM_NONE;
1540 /* If rx checksum is on, and there are no
1541 * csum or frame errors.
1543 if (qdev->rx_csum &&
1544 !(ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_ERR_MASK) &&
1545 !(ib_mac_rsp->flags1 & IB_MAC_CSUM_ERR_MASK)) {
1547 if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_T) {
1548 QPRINTK(qdev, RX_STATUS, DEBUG,
1549 "TCP checksum done!\n");
1550 skb->ip_summed = CHECKSUM_UNNECESSARY;
1551 } else if ((ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_U) &&
1552 (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_V4)) {
1553 /* Unfragmented ipv4 UDP frame. */
1554 struct iphdr *iph = (struct iphdr *) skb->data;
1555 if (!(iph->frag_off &
1556 cpu_to_be16(IP_MF|IP_OFFSET))) {
1557 skb->ip_summed = CHECKSUM_UNNECESSARY;
1558 QPRINTK(qdev, RX_STATUS, DEBUG,
1559 "TCP checksum done!\n");
1564 qdev->stats.rx_packets++;
1565 qdev->stats.rx_bytes += skb->len;
1566 skb_record_rx_queue(skb,
1567 rx_ring->cq_id - qdev->rss_ring_first_cq_id);
1568 if (skb->ip_summed == CHECKSUM_UNNECESSARY) {
1570 (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V) &&
1572 vlan_gro_receive(&rx_ring->napi, qdev->vlgrp,
1575 napi_gro_receive(&rx_ring->napi, skb);
1578 (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V) &&
1580 vlan_hwaccel_receive_skb(skb, qdev->vlgrp, vlan_id);
1582 netif_receive_skb(skb);
1586 /* Process an outbound completion from an rx ring. */
1587 static void ql_process_mac_tx_intr(struct ql_adapter *qdev,
1588 struct ob_mac_iocb_rsp *mac_rsp)
1590 struct tx_ring *tx_ring;
1591 struct tx_ring_desc *tx_ring_desc;
1593 QL_DUMP_OB_MAC_RSP(mac_rsp);
1594 tx_ring = &qdev->tx_ring[mac_rsp->txq_idx];
1595 tx_ring_desc = &tx_ring->q[mac_rsp->tid];
1596 ql_unmap_send(qdev, tx_ring_desc, tx_ring_desc->map_cnt);
1597 qdev->stats.tx_bytes += tx_ring_desc->map_cnt;
1598 qdev->stats.tx_packets++;
1599 dev_kfree_skb(tx_ring_desc->skb);
1600 tx_ring_desc->skb = NULL;
1602 if (unlikely(mac_rsp->flags1 & (OB_MAC_IOCB_RSP_E |
1605 OB_MAC_IOCB_RSP_P | OB_MAC_IOCB_RSP_B))) {
1606 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_E) {
1607 QPRINTK(qdev, TX_DONE, WARNING,
1608 "Total descriptor length did not match transfer length.\n");
1610 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_S) {
1611 QPRINTK(qdev, TX_DONE, WARNING,
1612 "Frame too short to be legal, not sent.\n");
1614 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_L) {
1615 QPRINTK(qdev, TX_DONE, WARNING,
1616 "Frame too long, but sent anyway.\n");
1618 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_B) {
1619 QPRINTK(qdev, TX_DONE, WARNING,
1620 "PCI backplane error. Frame not sent.\n");
1623 atomic_inc(&tx_ring->tx_count);
1626 /* Fire up a handler to reset the MPI processor. */
1627 void ql_queue_fw_error(struct ql_adapter *qdev)
1629 netif_carrier_off(qdev->ndev);
1630 queue_delayed_work(qdev->workqueue, &qdev->mpi_reset_work, 0);
1633 void ql_queue_asic_error(struct ql_adapter *qdev)
1635 netif_carrier_off(qdev->ndev);
1636 ql_disable_interrupts(qdev);
1637 /* Clear adapter up bit to signal the recovery
1638 * process that it shouldn't kill the reset worker
1641 clear_bit(QL_ADAPTER_UP, &qdev->flags);
1642 queue_delayed_work(qdev->workqueue, &qdev->asic_reset_work, 0);
1645 static void ql_process_chip_ae_intr(struct ql_adapter *qdev,
1646 struct ib_ae_iocb_rsp *ib_ae_rsp)
1648 switch (ib_ae_rsp->event) {
1649 case MGMT_ERR_EVENT:
1650 QPRINTK(qdev, RX_ERR, ERR,
1651 "Management Processor Fatal Error.\n");
1652 ql_queue_fw_error(qdev);
1655 case CAM_LOOKUP_ERR_EVENT:
1656 QPRINTK(qdev, LINK, ERR,
1657 "Multiple CAM hits lookup occurred.\n");
1658 QPRINTK(qdev, DRV, ERR, "This event shouldn't occur.\n");
1659 ql_queue_asic_error(qdev);
1662 case SOFT_ECC_ERROR_EVENT:
1663 QPRINTK(qdev, RX_ERR, ERR, "Soft ECC error detected.\n");
1664 ql_queue_asic_error(qdev);
1667 case PCI_ERR_ANON_BUF_RD:
1668 QPRINTK(qdev, RX_ERR, ERR,
1669 "PCI error occurred when reading anonymous buffers from rx_ring %d.\n",
1671 ql_queue_asic_error(qdev);
1675 QPRINTK(qdev, DRV, ERR, "Unexpected event %d.\n",
1677 ql_queue_asic_error(qdev);
1682 static int ql_clean_outbound_rx_ring(struct rx_ring *rx_ring)
1684 struct ql_adapter *qdev = rx_ring->qdev;
1685 u32 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
1686 struct ob_mac_iocb_rsp *net_rsp = NULL;
1689 struct tx_ring *tx_ring;
1690 /* While there are entries in the completion queue. */
1691 while (prod != rx_ring->cnsmr_idx) {
1693 QPRINTK(qdev, RX_STATUS, DEBUG,
1694 "cq_id = %d, prod = %d, cnsmr = %d.\n.", rx_ring->cq_id,
1695 prod, rx_ring->cnsmr_idx);
1697 net_rsp = (struct ob_mac_iocb_rsp *)rx_ring->curr_entry;
1699 switch (net_rsp->opcode) {
1701 case OPCODE_OB_MAC_TSO_IOCB:
1702 case OPCODE_OB_MAC_IOCB:
1703 ql_process_mac_tx_intr(qdev, net_rsp);
1706 QPRINTK(qdev, RX_STATUS, DEBUG,
1707 "Hit default case, not handled! dropping the packet, opcode = %x.\n",
1711 ql_update_cq(rx_ring);
1712 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
1714 ql_write_cq_idx(rx_ring);
1715 tx_ring = &qdev->tx_ring[net_rsp->txq_idx];
1716 if (__netif_subqueue_stopped(qdev->ndev, tx_ring->wq_id) &&
1718 if (atomic_read(&tx_ring->queue_stopped) &&
1719 (atomic_read(&tx_ring->tx_count) > (tx_ring->wq_len / 4)))
1721 * The queue got stopped because the tx_ring was full.
1722 * Wake it up, because it's now at least 25% empty.
1724 netif_wake_subqueue(qdev->ndev, tx_ring->wq_id);
1730 static int ql_clean_inbound_rx_ring(struct rx_ring *rx_ring, int budget)
1732 struct ql_adapter *qdev = rx_ring->qdev;
1733 u32 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
1734 struct ql_net_rsp_iocb *net_rsp;
1737 /* While there are entries in the completion queue. */
1738 while (prod != rx_ring->cnsmr_idx) {
1740 QPRINTK(qdev, RX_STATUS, DEBUG,
1741 "cq_id = %d, prod = %d, cnsmr = %d.\n.", rx_ring->cq_id,
1742 prod, rx_ring->cnsmr_idx);
1744 net_rsp = rx_ring->curr_entry;
1746 switch (net_rsp->opcode) {
1747 case OPCODE_IB_MAC_IOCB:
1748 ql_process_mac_rx_intr(qdev, rx_ring,
1749 (struct ib_mac_iocb_rsp *)
1753 case OPCODE_IB_AE_IOCB:
1754 ql_process_chip_ae_intr(qdev, (struct ib_ae_iocb_rsp *)
1759 QPRINTK(qdev, RX_STATUS, DEBUG,
1760 "Hit default case, not handled! dropping the packet, opcode = %x.\n",
1765 ql_update_cq(rx_ring);
1766 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
1767 if (count == budget)
1770 ql_update_buffer_queues(qdev, rx_ring);
1771 ql_write_cq_idx(rx_ring);
1775 static int ql_napi_poll_msix(struct napi_struct *napi, int budget)
1777 struct rx_ring *rx_ring = container_of(napi, struct rx_ring, napi);
1778 struct ql_adapter *qdev = rx_ring->qdev;
1779 int work_done = ql_clean_inbound_rx_ring(rx_ring, budget);
1781 QPRINTK(qdev, RX_STATUS, DEBUG, "Enter, NAPI POLL cq_id = %d.\n",
1784 if (work_done < budget) {
1785 napi_complete(napi);
1786 ql_enable_completion_interrupt(qdev, rx_ring->irq);
1791 static void ql_vlan_rx_register(struct net_device *ndev, struct vlan_group *grp)
1793 struct ql_adapter *qdev = netdev_priv(ndev);
1797 QPRINTK(qdev, IFUP, DEBUG, "Turning on VLAN in NIC_RCV_CFG.\n");
1798 ql_write32(qdev, NIC_RCV_CFG, NIC_RCV_CFG_VLAN_MASK |
1799 NIC_RCV_CFG_VLAN_MATCH_AND_NON);
1801 QPRINTK(qdev, IFUP, DEBUG,
1802 "Turning off VLAN in NIC_RCV_CFG.\n");
1803 ql_write32(qdev, NIC_RCV_CFG, NIC_RCV_CFG_VLAN_MASK);
1807 static void ql_vlan_rx_add_vid(struct net_device *ndev, u16 vid)
1809 struct ql_adapter *qdev = netdev_priv(ndev);
1810 u32 enable_bit = MAC_ADDR_E;
1813 status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
1816 spin_lock(&qdev->hw_lock);
1817 if (ql_set_mac_addr_reg
1818 (qdev, (u8 *) &enable_bit, MAC_ADDR_TYPE_VLAN, vid)) {
1819 QPRINTK(qdev, IFUP, ERR, "Failed to init vlan address.\n");
1821 spin_unlock(&qdev->hw_lock);
1822 ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
1825 static void ql_vlan_rx_kill_vid(struct net_device *ndev, u16 vid)
1827 struct ql_adapter *qdev = netdev_priv(ndev);
1831 status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
1835 spin_lock(&qdev->hw_lock);
1836 if (ql_set_mac_addr_reg
1837 (qdev, (u8 *) &enable_bit, MAC_ADDR_TYPE_VLAN, vid)) {
1838 QPRINTK(qdev, IFUP, ERR, "Failed to clear vlan address.\n");
1840 spin_unlock(&qdev->hw_lock);
1841 ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
1845 /* Worker thread to process a given rx_ring that is dedicated
1846 * to outbound completions.
1848 static void ql_tx_clean(struct work_struct *work)
1850 struct rx_ring *rx_ring =
1851 container_of(work, struct rx_ring, rx_work.work);
1852 ql_clean_outbound_rx_ring(rx_ring);
1853 ql_enable_completion_interrupt(rx_ring->qdev, rx_ring->irq);
1857 /* Worker thread to process a given rx_ring that is dedicated
1858 * to inbound completions.
1860 static void ql_rx_clean(struct work_struct *work)
1862 struct rx_ring *rx_ring =
1863 container_of(work, struct rx_ring, rx_work.work);
1864 ql_clean_inbound_rx_ring(rx_ring, 64);
1865 ql_enable_completion_interrupt(rx_ring->qdev, rx_ring->irq);
1868 /* MSI-X Multiple Vector Interrupt Handler for outbound completions. */
1869 static irqreturn_t qlge_msix_tx_isr(int irq, void *dev_id)
1871 struct rx_ring *rx_ring = dev_id;
1872 queue_delayed_work_on(rx_ring->cpu, rx_ring->qdev->q_workqueue,
1873 &rx_ring->rx_work, 0);
1877 /* MSI-X Multiple Vector Interrupt Handler for inbound completions. */
1878 static irqreturn_t qlge_msix_rx_isr(int irq, void *dev_id)
1880 struct rx_ring *rx_ring = dev_id;
1881 napi_schedule(&rx_ring->napi);
1885 /* This handles a fatal error, MPI activity, and the default
1886 * rx_ring in an MSI-X multiple vector environment.
1887 * In MSI/Legacy environment it also process the rest of
1890 static irqreturn_t qlge_isr(int irq, void *dev_id)
1892 struct rx_ring *rx_ring = dev_id;
1893 struct ql_adapter *qdev = rx_ring->qdev;
1894 struct intr_context *intr_context = &qdev->intr_context[0];
1899 spin_lock(&qdev->hw_lock);
1900 if (atomic_read(&qdev->intr_context[0].irq_cnt)) {
1901 QPRINTK(qdev, INTR, DEBUG, "Shared Interrupt, Not ours!\n");
1902 spin_unlock(&qdev->hw_lock);
1905 spin_unlock(&qdev->hw_lock);
1907 var = ql_disable_completion_interrupt(qdev, intr_context->intr);
1910 * Check for fatal error.
1913 ql_queue_asic_error(qdev);
1914 QPRINTK(qdev, INTR, ERR, "Got fatal error, STS = %x.\n", var);
1915 var = ql_read32(qdev, ERR_STS);
1916 QPRINTK(qdev, INTR, ERR,
1917 "Resetting chip. Error Status Register = 0x%x\n", var);
1922 * Check MPI processor activity.
1926 * We've got an async event or mailbox completion.
1927 * Handle it and clear the source of the interrupt.
1929 QPRINTK(qdev, INTR, ERR, "Got MPI processor interrupt.\n");
1930 ql_disable_completion_interrupt(qdev, intr_context->intr);
1931 queue_delayed_work_on(smp_processor_id(), qdev->workqueue,
1932 &qdev->mpi_work, 0);
1937 * Check the default queue and wake handler if active.
1939 rx_ring = &qdev->rx_ring[0];
1940 if (ql_read_sh_reg(rx_ring->prod_idx_sh_reg) != rx_ring->cnsmr_idx) {
1941 QPRINTK(qdev, INTR, INFO, "Waking handler for rx_ring[0].\n");
1942 ql_disable_completion_interrupt(qdev, intr_context->intr);
1943 queue_delayed_work_on(smp_processor_id(), qdev->q_workqueue,
1944 &rx_ring->rx_work, 0);
1948 if (!test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
1950 * Start the DPC for each active queue.
1952 for (i = 1; i < qdev->rx_ring_count; i++) {
1953 rx_ring = &qdev->rx_ring[i];
1954 if (ql_read_sh_reg(rx_ring->prod_idx_sh_reg) !=
1955 rx_ring->cnsmr_idx) {
1956 QPRINTK(qdev, INTR, INFO,
1957 "Waking handler for rx_ring[%d].\n", i);
1958 ql_disable_completion_interrupt(qdev,
1961 if (i < qdev->rss_ring_first_cq_id)
1962 queue_delayed_work_on(rx_ring->cpu,
1967 napi_schedule(&rx_ring->napi);
1972 ql_enable_completion_interrupt(qdev, intr_context->intr);
1973 return work_done ? IRQ_HANDLED : IRQ_NONE;
1976 static int ql_tso(struct sk_buff *skb, struct ob_mac_tso_iocb_req *mac_iocb_ptr)
1979 if (skb_is_gso(skb)) {
1981 if (skb_header_cloned(skb)) {
1982 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
1987 mac_iocb_ptr->opcode = OPCODE_OB_MAC_TSO_IOCB;
1988 mac_iocb_ptr->flags3 |= OB_MAC_TSO_IOCB_IC;
1989 mac_iocb_ptr->frame_len = cpu_to_le32((u32) skb->len);
1990 mac_iocb_ptr->total_hdrs_len =
1991 cpu_to_le16(skb_transport_offset(skb) + tcp_hdrlen(skb));
1992 mac_iocb_ptr->net_trans_offset =
1993 cpu_to_le16(skb_network_offset(skb) |
1994 skb_transport_offset(skb)
1995 << OB_MAC_TRANSPORT_HDR_SHIFT);
1996 mac_iocb_ptr->mss = cpu_to_le16(skb_shinfo(skb)->gso_size);
1997 mac_iocb_ptr->flags2 |= OB_MAC_TSO_IOCB_LSO;
1998 if (likely(skb->protocol == htons(ETH_P_IP))) {
1999 struct iphdr *iph = ip_hdr(skb);
2001 mac_iocb_ptr->flags1 |= OB_MAC_TSO_IOCB_IP4;
2002 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
2006 } else if (skb->protocol == htons(ETH_P_IPV6)) {
2007 mac_iocb_ptr->flags1 |= OB_MAC_TSO_IOCB_IP6;
2008 tcp_hdr(skb)->check =
2009 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
2010 &ipv6_hdr(skb)->daddr,
2018 static void ql_hw_csum_setup(struct sk_buff *skb,
2019 struct ob_mac_tso_iocb_req *mac_iocb_ptr)
2022 struct iphdr *iph = ip_hdr(skb);
2024 mac_iocb_ptr->opcode = OPCODE_OB_MAC_TSO_IOCB;
2025 mac_iocb_ptr->frame_len = cpu_to_le32((u32) skb->len);
2026 mac_iocb_ptr->net_trans_offset =
2027 cpu_to_le16(skb_network_offset(skb) |
2028 skb_transport_offset(skb) << OB_MAC_TRANSPORT_HDR_SHIFT);
2030 mac_iocb_ptr->flags1 |= OB_MAC_TSO_IOCB_IP4;
2031 len = (ntohs(iph->tot_len) - (iph->ihl << 2));
2032 if (likely(iph->protocol == IPPROTO_TCP)) {
2033 check = &(tcp_hdr(skb)->check);
2034 mac_iocb_ptr->flags2 |= OB_MAC_TSO_IOCB_TC;
2035 mac_iocb_ptr->total_hdrs_len =
2036 cpu_to_le16(skb_transport_offset(skb) +
2037 (tcp_hdr(skb)->doff << 2));
2039 check = &(udp_hdr(skb)->check);
2040 mac_iocb_ptr->flags2 |= OB_MAC_TSO_IOCB_UC;
2041 mac_iocb_ptr->total_hdrs_len =
2042 cpu_to_le16(skb_transport_offset(skb) +
2043 sizeof(struct udphdr));
2045 *check = ~csum_tcpudp_magic(iph->saddr,
2046 iph->daddr, len, iph->protocol, 0);
2049 static int qlge_send(struct sk_buff *skb, struct net_device *ndev)
2051 struct tx_ring_desc *tx_ring_desc;
2052 struct ob_mac_iocb_req *mac_iocb_ptr;
2053 struct ql_adapter *qdev = netdev_priv(ndev);
2055 struct tx_ring *tx_ring;
2056 u32 tx_ring_idx = (u32) skb->queue_mapping;
2058 tx_ring = &qdev->tx_ring[tx_ring_idx];
2060 if (skb_padto(skb, ETH_ZLEN))
2061 return NETDEV_TX_OK;
2063 if (unlikely(atomic_read(&tx_ring->tx_count) < 2)) {
2064 QPRINTK(qdev, TX_QUEUED, INFO,
2065 "%s: shutting down tx queue %d du to lack of resources.\n",
2066 __func__, tx_ring_idx);
2067 netif_stop_subqueue(ndev, tx_ring->wq_id);
2068 atomic_inc(&tx_ring->queue_stopped);
2069 return NETDEV_TX_BUSY;
2071 tx_ring_desc = &tx_ring->q[tx_ring->prod_idx];
2072 mac_iocb_ptr = tx_ring_desc->queue_entry;
2073 memset((void *)mac_iocb_ptr, 0, sizeof(mac_iocb_ptr));
2075 mac_iocb_ptr->opcode = OPCODE_OB_MAC_IOCB;
2076 mac_iocb_ptr->tid = tx_ring_desc->index;
2077 /* We use the upper 32-bits to store the tx queue for this IO.
2078 * When we get the completion we can use it to establish the context.
2080 mac_iocb_ptr->txq_idx = tx_ring_idx;
2081 tx_ring_desc->skb = skb;
2083 mac_iocb_ptr->frame_len = cpu_to_le16((u16) skb->len);
2085 if (qdev->vlgrp && vlan_tx_tag_present(skb)) {
2086 QPRINTK(qdev, TX_QUEUED, DEBUG, "Adding a vlan tag %d.\n",
2087 vlan_tx_tag_get(skb));
2088 mac_iocb_ptr->flags3 |= OB_MAC_IOCB_V;
2089 mac_iocb_ptr->vlan_tci = cpu_to_le16(vlan_tx_tag_get(skb));
2091 tso = ql_tso(skb, (struct ob_mac_tso_iocb_req *)mac_iocb_ptr);
2093 dev_kfree_skb_any(skb);
2094 return NETDEV_TX_OK;
2095 } else if (unlikely(!tso) && (skb->ip_summed == CHECKSUM_PARTIAL)) {
2096 ql_hw_csum_setup(skb,
2097 (struct ob_mac_tso_iocb_req *)mac_iocb_ptr);
2099 if (ql_map_send(qdev, mac_iocb_ptr, skb, tx_ring_desc) !=
2101 QPRINTK(qdev, TX_QUEUED, ERR,
2102 "Could not map the segments.\n");
2103 return NETDEV_TX_BUSY;
2105 QL_DUMP_OB_MAC_IOCB(mac_iocb_ptr);
2106 tx_ring->prod_idx++;
2107 if (tx_ring->prod_idx == tx_ring->wq_len)
2108 tx_ring->prod_idx = 0;
2111 ql_write_db_reg(tx_ring->prod_idx, tx_ring->prod_idx_db_reg);
2112 ndev->trans_start = jiffies;
2113 QPRINTK(qdev, TX_QUEUED, DEBUG, "tx queued, slot %d, len %d\n",
2114 tx_ring->prod_idx, skb->len);
2116 atomic_dec(&tx_ring->tx_count);
2117 return NETDEV_TX_OK;
2120 static void ql_free_shadow_space(struct ql_adapter *qdev)
2122 if (qdev->rx_ring_shadow_reg_area) {
2123 pci_free_consistent(qdev->pdev,
2125 qdev->rx_ring_shadow_reg_area,
2126 qdev->rx_ring_shadow_reg_dma);
2127 qdev->rx_ring_shadow_reg_area = NULL;
2129 if (qdev->tx_ring_shadow_reg_area) {
2130 pci_free_consistent(qdev->pdev,
2132 qdev->tx_ring_shadow_reg_area,
2133 qdev->tx_ring_shadow_reg_dma);
2134 qdev->tx_ring_shadow_reg_area = NULL;
2138 static int ql_alloc_shadow_space(struct ql_adapter *qdev)
2140 qdev->rx_ring_shadow_reg_area =
2141 pci_alloc_consistent(qdev->pdev,
2142 PAGE_SIZE, &qdev->rx_ring_shadow_reg_dma);
2143 if (qdev->rx_ring_shadow_reg_area == NULL) {
2144 QPRINTK(qdev, IFUP, ERR,
2145 "Allocation of RX shadow space failed.\n");
2148 memset(qdev->rx_ring_shadow_reg_area, 0, PAGE_SIZE);
2149 qdev->tx_ring_shadow_reg_area =
2150 pci_alloc_consistent(qdev->pdev, PAGE_SIZE,
2151 &qdev->tx_ring_shadow_reg_dma);
2152 if (qdev->tx_ring_shadow_reg_area == NULL) {
2153 QPRINTK(qdev, IFUP, ERR,
2154 "Allocation of TX shadow space failed.\n");
2155 goto err_wqp_sh_area;
2157 memset(qdev->tx_ring_shadow_reg_area, 0, PAGE_SIZE);
2161 pci_free_consistent(qdev->pdev,
2163 qdev->rx_ring_shadow_reg_area,
2164 qdev->rx_ring_shadow_reg_dma);
2168 static void ql_init_tx_ring(struct ql_adapter *qdev, struct tx_ring *tx_ring)
2170 struct tx_ring_desc *tx_ring_desc;
2172 struct ob_mac_iocb_req *mac_iocb_ptr;
2174 mac_iocb_ptr = tx_ring->wq_base;
2175 tx_ring_desc = tx_ring->q;
2176 for (i = 0; i < tx_ring->wq_len; i++) {
2177 tx_ring_desc->index = i;
2178 tx_ring_desc->skb = NULL;
2179 tx_ring_desc->queue_entry = mac_iocb_ptr;
2183 atomic_set(&tx_ring->tx_count, tx_ring->wq_len);
2184 atomic_set(&tx_ring->queue_stopped, 0);
2187 static void ql_free_tx_resources(struct ql_adapter *qdev,
2188 struct tx_ring *tx_ring)
2190 if (tx_ring->wq_base) {
2191 pci_free_consistent(qdev->pdev, tx_ring->wq_size,
2192 tx_ring->wq_base, tx_ring->wq_base_dma);
2193 tx_ring->wq_base = NULL;
2199 static int ql_alloc_tx_resources(struct ql_adapter *qdev,
2200 struct tx_ring *tx_ring)
2203 pci_alloc_consistent(qdev->pdev, tx_ring->wq_size,
2204 &tx_ring->wq_base_dma);
2206 if ((tx_ring->wq_base == NULL)
2207 || tx_ring->wq_base_dma & (tx_ring->wq_size - 1)) {
2208 QPRINTK(qdev, IFUP, ERR, "tx_ring alloc failed.\n");
2212 kmalloc(tx_ring->wq_len * sizeof(struct tx_ring_desc), GFP_KERNEL);
2213 if (tx_ring->q == NULL)
2218 pci_free_consistent(qdev->pdev, tx_ring->wq_size,
2219 tx_ring->wq_base, tx_ring->wq_base_dma);
2223 static void ql_free_lbq_buffers(struct ql_adapter *qdev, struct rx_ring *rx_ring)
2226 struct bq_desc *lbq_desc;
2228 for (i = 0; i < rx_ring->lbq_len; i++) {
2229 lbq_desc = &rx_ring->lbq[i];
2230 if (lbq_desc->p.lbq_page) {
2231 pci_unmap_page(qdev->pdev,
2232 pci_unmap_addr(lbq_desc, mapaddr),
2233 pci_unmap_len(lbq_desc, maplen),
2234 PCI_DMA_FROMDEVICE);
2236 put_page(lbq_desc->p.lbq_page);
2237 lbq_desc->p.lbq_page = NULL;
2242 static void ql_free_sbq_buffers(struct ql_adapter *qdev, struct rx_ring *rx_ring)
2245 struct bq_desc *sbq_desc;
2247 for (i = 0; i < rx_ring->sbq_len; i++) {
2248 sbq_desc = &rx_ring->sbq[i];
2249 if (sbq_desc == NULL) {
2250 QPRINTK(qdev, IFUP, ERR, "sbq_desc %d is NULL.\n", i);
2253 if (sbq_desc->p.skb) {
2254 pci_unmap_single(qdev->pdev,
2255 pci_unmap_addr(sbq_desc, mapaddr),
2256 pci_unmap_len(sbq_desc, maplen),
2257 PCI_DMA_FROMDEVICE);
2258 dev_kfree_skb(sbq_desc->p.skb);
2259 sbq_desc->p.skb = NULL;
2264 /* Free all large and small rx buffers associated
2265 * with the completion queues for this device.
2267 static void ql_free_rx_buffers(struct ql_adapter *qdev)
2270 struct rx_ring *rx_ring;
2272 for (i = 0; i < qdev->rx_ring_count; i++) {
2273 rx_ring = &qdev->rx_ring[i];
2275 ql_free_lbq_buffers(qdev, rx_ring);
2277 ql_free_sbq_buffers(qdev, rx_ring);
2281 static void ql_alloc_rx_buffers(struct ql_adapter *qdev)
2283 struct rx_ring *rx_ring;
2286 for (i = 0; i < qdev->rx_ring_count; i++) {
2287 rx_ring = &qdev->rx_ring[i];
2288 if (rx_ring->type != TX_Q)
2289 ql_update_buffer_queues(qdev, rx_ring);
2293 static void ql_init_lbq_ring(struct ql_adapter *qdev,
2294 struct rx_ring *rx_ring)
2297 struct bq_desc *lbq_desc;
2298 __le64 *bq = rx_ring->lbq_base;
2300 memset(rx_ring->lbq, 0, rx_ring->lbq_len * sizeof(struct bq_desc));
2301 for (i = 0; i < rx_ring->lbq_len; i++) {
2302 lbq_desc = &rx_ring->lbq[i];
2303 memset(lbq_desc, 0, sizeof(*lbq_desc));
2304 lbq_desc->index = i;
2305 lbq_desc->addr = bq;
2310 static void ql_init_sbq_ring(struct ql_adapter *qdev,
2311 struct rx_ring *rx_ring)
2314 struct bq_desc *sbq_desc;
2315 __le64 *bq = rx_ring->sbq_base;
2317 memset(rx_ring->sbq, 0, rx_ring->sbq_len * sizeof(struct bq_desc));
2318 for (i = 0; i < rx_ring->sbq_len; i++) {
2319 sbq_desc = &rx_ring->sbq[i];
2320 memset(sbq_desc, 0, sizeof(*sbq_desc));
2321 sbq_desc->index = i;
2322 sbq_desc->addr = bq;
2327 static void ql_free_rx_resources(struct ql_adapter *qdev,
2328 struct rx_ring *rx_ring)
2330 /* Free the small buffer queue. */
2331 if (rx_ring->sbq_base) {
2332 pci_free_consistent(qdev->pdev,
2334 rx_ring->sbq_base, rx_ring->sbq_base_dma);
2335 rx_ring->sbq_base = NULL;
2338 /* Free the small buffer queue control blocks. */
2339 kfree(rx_ring->sbq);
2340 rx_ring->sbq = NULL;
2342 /* Free the large buffer queue. */
2343 if (rx_ring->lbq_base) {
2344 pci_free_consistent(qdev->pdev,
2346 rx_ring->lbq_base, rx_ring->lbq_base_dma);
2347 rx_ring->lbq_base = NULL;
2350 /* Free the large buffer queue control blocks. */
2351 kfree(rx_ring->lbq);
2352 rx_ring->lbq = NULL;
2354 /* Free the rx queue. */
2355 if (rx_ring->cq_base) {
2356 pci_free_consistent(qdev->pdev,
2358 rx_ring->cq_base, rx_ring->cq_base_dma);
2359 rx_ring->cq_base = NULL;
2363 /* Allocate queues and buffers for this completions queue based
2364 * on the values in the parameter structure. */
2365 static int ql_alloc_rx_resources(struct ql_adapter *qdev,
2366 struct rx_ring *rx_ring)
2370 * Allocate the completion queue for this rx_ring.
2373 pci_alloc_consistent(qdev->pdev, rx_ring->cq_size,
2374 &rx_ring->cq_base_dma);
2376 if (rx_ring->cq_base == NULL) {
2377 QPRINTK(qdev, IFUP, ERR, "rx_ring alloc failed.\n");
2381 if (rx_ring->sbq_len) {
2383 * Allocate small buffer queue.
2386 pci_alloc_consistent(qdev->pdev, rx_ring->sbq_size,
2387 &rx_ring->sbq_base_dma);
2389 if (rx_ring->sbq_base == NULL) {
2390 QPRINTK(qdev, IFUP, ERR,
2391 "Small buffer queue allocation failed.\n");
2396 * Allocate small buffer queue control blocks.
2399 kmalloc(rx_ring->sbq_len * sizeof(struct bq_desc),
2401 if (rx_ring->sbq == NULL) {
2402 QPRINTK(qdev, IFUP, ERR,
2403 "Small buffer queue control block allocation failed.\n");
2407 ql_init_sbq_ring(qdev, rx_ring);
2410 if (rx_ring->lbq_len) {
2412 * Allocate large buffer queue.
2415 pci_alloc_consistent(qdev->pdev, rx_ring->lbq_size,
2416 &rx_ring->lbq_base_dma);
2418 if (rx_ring->lbq_base == NULL) {
2419 QPRINTK(qdev, IFUP, ERR,
2420 "Large buffer queue allocation failed.\n");
2424 * Allocate large buffer queue control blocks.
2427 kmalloc(rx_ring->lbq_len * sizeof(struct bq_desc),
2429 if (rx_ring->lbq == NULL) {
2430 QPRINTK(qdev, IFUP, ERR,
2431 "Large buffer queue control block allocation failed.\n");
2435 ql_init_lbq_ring(qdev, rx_ring);
2441 ql_free_rx_resources(qdev, rx_ring);
2445 static void ql_tx_ring_clean(struct ql_adapter *qdev)
2447 struct tx_ring *tx_ring;
2448 struct tx_ring_desc *tx_ring_desc;
2452 * Loop through all queues and free
2455 for (j = 0; j < qdev->tx_ring_count; j++) {
2456 tx_ring = &qdev->tx_ring[j];
2457 for (i = 0; i < tx_ring->wq_len; i++) {
2458 tx_ring_desc = &tx_ring->q[i];
2459 if (tx_ring_desc && tx_ring_desc->skb) {
2460 QPRINTK(qdev, IFDOWN, ERR,
2461 "Freeing lost SKB %p, from queue %d, index %d.\n",
2462 tx_ring_desc->skb, j,
2463 tx_ring_desc->index);
2464 ql_unmap_send(qdev, tx_ring_desc,
2465 tx_ring_desc->map_cnt);
2466 dev_kfree_skb(tx_ring_desc->skb);
2467 tx_ring_desc->skb = NULL;
2473 static void ql_free_mem_resources(struct ql_adapter *qdev)
2477 for (i = 0; i < qdev->tx_ring_count; i++)
2478 ql_free_tx_resources(qdev, &qdev->tx_ring[i]);
2479 for (i = 0; i < qdev->rx_ring_count; i++)
2480 ql_free_rx_resources(qdev, &qdev->rx_ring[i]);
2481 ql_free_shadow_space(qdev);
2484 static int ql_alloc_mem_resources(struct ql_adapter *qdev)
2488 /* Allocate space for our shadow registers and such. */
2489 if (ql_alloc_shadow_space(qdev))
2492 for (i = 0; i < qdev->rx_ring_count; i++) {
2493 if (ql_alloc_rx_resources(qdev, &qdev->rx_ring[i]) != 0) {
2494 QPRINTK(qdev, IFUP, ERR,
2495 "RX resource allocation failed.\n");
2499 /* Allocate tx queue resources */
2500 for (i = 0; i < qdev->tx_ring_count; i++) {
2501 if (ql_alloc_tx_resources(qdev, &qdev->tx_ring[i]) != 0) {
2502 QPRINTK(qdev, IFUP, ERR,
2503 "TX resource allocation failed.\n");
2510 ql_free_mem_resources(qdev);
2514 /* Set up the rx ring control block and pass it to the chip.
2515 * The control block is defined as
2516 * "Completion Queue Initialization Control Block", or cqicb.
2518 static int ql_start_rx_ring(struct ql_adapter *qdev, struct rx_ring *rx_ring)
2520 struct cqicb *cqicb = &rx_ring->cqicb;
2521 void *shadow_reg = qdev->rx_ring_shadow_reg_area +
2522 (rx_ring->cq_id * sizeof(u64) * 4);
2523 u64 shadow_reg_dma = qdev->rx_ring_shadow_reg_dma +
2524 (rx_ring->cq_id * sizeof(u64) * 4);
2525 void __iomem *doorbell_area =
2526 qdev->doorbell_area + (DB_PAGE_SIZE * (128 + rx_ring->cq_id));
2531 /* Set up the shadow registers for this ring. */
2532 rx_ring->prod_idx_sh_reg = shadow_reg;
2533 rx_ring->prod_idx_sh_reg_dma = shadow_reg_dma;
2534 shadow_reg += sizeof(u64);
2535 shadow_reg_dma += sizeof(u64);
2536 rx_ring->lbq_base_indirect = shadow_reg;
2537 rx_ring->lbq_base_indirect_dma = shadow_reg_dma;
2538 shadow_reg += sizeof(u64);
2539 shadow_reg_dma += sizeof(u64);
2540 rx_ring->sbq_base_indirect = shadow_reg;
2541 rx_ring->sbq_base_indirect_dma = shadow_reg_dma;
2543 /* PCI doorbell mem area + 0x00 for consumer index register */
2544 rx_ring->cnsmr_idx_db_reg = (u32 __iomem *) doorbell_area;
2545 rx_ring->cnsmr_idx = 0;
2546 rx_ring->curr_entry = rx_ring->cq_base;
2548 /* PCI doorbell mem area + 0x04 for valid register */
2549 rx_ring->valid_db_reg = doorbell_area + 0x04;
2551 /* PCI doorbell mem area + 0x18 for large buffer consumer */
2552 rx_ring->lbq_prod_idx_db_reg = (u32 __iomem *) (doorbell_area + 0x18);
2554 /* PCI doorbell mem area + 0x1c */
2555 rx_ring->sbq_prod_idx_db_reg = (u32 __iomem *) (doorbell_area + 0x1c);
2557 memset((void *)cqicb, 0, sizeof(struct cqicb));
2558 cqicb->msix_vect = rx_ring->irq;
2560 bq_len = (rx_ring->cq_len == 65536) ? 0 : (u16) rx_ring->cq_len;
2561 cqicb->len = cpu_to_le16(bq_len | LEN_V | LEN_CPP_CONT);
2563 cqicb->addr = cpu_to_le64(rx_ring->cq_base_dma);
2565 cqicb->prod_idx_addr = cpu_to_le64(rx_ring->prod_idx_sh_reg_dma);
2568 * Set up the control block load flags.
2570 cqicb->flags = FLAGS_LC | /* Load queue base address */
2571 FLAGS_LV | /* Load MSI-X vector */
2572 FLAGS_LI; /* Load irq delay values */
2573 if (rx_ring->lbq_len) {
2574 cqicb->flags |= FLAGS_LL; /* Load lbq values */
2575 tmp = (u64)rx_ring->lbq_base_dma;;
2576 *((__le64 *) rx_ring->lbq_base_indirect) = cpu_to_le64(tmp);
2578 cpu_to_le64(rx_ring->lbq_base_indirect_dma);
2579 bq_len = (rx_ring->lbq_buf_size == 65536) ? 0 :
2580 (u16) rx_ring->lbq_buf_size;
2581 cqicb->lbq_buf_size = cpu_to_le16(bq_len);
2582 bq_len = (rx_ring->lbq_len == 65536) ? 0 :
2583 (u16) rx_ring->lbq_len;
2584 cqicb->lbq_len = cpu_to_le16(bq_len);
2585 rx_ring->lbq_prod_idx = 0;
2586 rx_ring->lbq_curr_idx = 0;
2587 rx_ring->lbq_clean_idx = 0;
2588 rx_ring->lbq_free_cnt = rx_ring->lbq_len;
2590 if (rx_ring->sbq_len) {
2591 cqicb->flags |= FLAGS_LS; /* Load sbq values */
2592 tmp = (u64)rx_ring->sbq_base_dma;;
2593 *((__le64 *) rx_ring->sbq_base_indirect) = cpu_to_le64(tmp);
2595 cpu_to_le64(rx_ring->sbq_base_indirect_dma);
2596 cqicb->sbq_buf_size =
2597 cpu_to_le16((u16)(rx_ring->sbq_buf_size/2));
2598 bq_len = (rx_ring->sbq_len == 65536) ? 0 :
2599 (u16) rx_ring->sbq_len;
2600 cqicb->sbq_len = cpu_to_le16(bq_len);
2601 rx_ring->sbq_prod_idx = 0;
2602 rx_ring->sbq_curr_idx = 0;
2603 rx_ring->sbq_clean_idx = 0;
2604 rx_ring->sbq_free_cnt = rx_ring->sbq_len;
2606 switch (rx_ring->type) {
2608 /* If there's only one interrupt, then we use
2609 * worker threads to process the outbound
2610 * completion handling rx_rings. We do this so
2611 * they can be run on multiple CPUs. There is
2612 * room to play with this more where we would only
2613 * run in a worker if there are more than x number
2614 * of outbound completions on the queue and more
2615 * than one queue active. Some threshold that
2616 * would indicate a benefit in spite of the cost
2617 * of a context switch.
2618 * If there's more than one interrupt, then the
2619 * outbound completions are processed in the ISR.
2621 if (!test_bit(QL_MSIX_ENABLED, &qdev->flags))
2622 INIT_DELAYED_WORK(&rx_ring->rx_work, ql_tx_clean);
2624 /* With all debug warnings on we see a WARN_ON message
2625 * when we free the skb in the interrupt context.
2627 INIT_DELAYED_WORK(&rx_ring->rx_work, ql_tx_clean);
2629 cqicb->irq_delay = cpu_to_le16(qdev->tx_coalesce_usecs);
2630 cqicb->pkt_delay = cpu_to_le16(qdev->tx_max_coalesced_frames);
2633 INIT_DELAYED_WORK(&rx_ring->rx_work, ql_rx_clean);
2634 cqicb->irq_delay = 0;
2635 cqicb->pkt_delay = 0;
2638 /* Inbound completion handling rx_rings run in
2639 * separate NAPI contexts.
2641 netif_napi_add(qdev->ndev, &rx_ring->napi, ql_napi_poll_msix,
2643 cqicb->irq_delay = cpu_to_le16(qdev->rx_coalesce_usecs);
2644 cqicb->pkt_delay = cpu_to_le16(qdev->rx_max_coalesced_frames);
2647 QPRINTK(qdev, IFUP, DEBUG, "Invalid rx_ring->type = %d.\n",
2650 QPRINTK(qdev, IFUP, DEBUG, "Initializing rx work queue.\n");
2651 err = ql_write_cfg(qdev, cqicb, sizeof(struct cqicb),
2652 CFG_LCQ, rx_ring->cq_id);
2654 QPRINTK(qdev, IFUP, ERR, "Failed to load CQICB.\n");
2660 static int ql_start_tx_ring(struct ql_adapter *qdev, struct tx_ring *tx_ring)
2662 struct wqicb *wqicb = (struct wqicb *)tx_ring;
2663 void __iomem *doorbell_area =
2664 qdev->doorbell_area + (DB_PAGE_SIZE * tx_ring->wq_id);
2665 void *shadow_reg = qdev->tx_ring_shadow_reg_area +
2666 (tx_ring->wq_id * sizeof(u64));
2667 u64 shadow_reg_dma = qdev->tx_ring_shadow_reg_dma +
2668 (tx_ring->wq_id * sizeof(u64));
2672 * Assign doorbell registers for this tx_ring.
2674 /* TX PCI doorbell mem area for tx producer index */
2675 tx_ring->prod_idx_db_reg = (u32 __iomem *) doorbell_area;
2676 tx_ring->prod_idx = 0;
2677 /* TX PCI doorbell mem area + 0x04 */
2678 tx_ring->valid_db_reg = doorbell_area + 0x04;
2681 * Assign shadow registers for this tx_ring.
2683 tx_ring->cnsmr_idx_sh_reg = shadow_reg;
2684 tx_ring->cnsmr_idx_sh_reg_dma = shadow_reg_dma;
2686 wqicb->len = cpu_to_le16(tx_ring->wq_len | Q_LEN_V | Q_LEN_CPP_CONT);
2687 wqicb->flags = cpu_to_le16(Q_FLAGS_LC |
2688 Q_FLAGS_LB | Q_FLAGS_LI | Q_FLAGS_LO);
2689 wqicb->cq_id_rss = cpu_to_le16(tx_ring->cq_id);
2691 wqicb->addr = cpu_to_le64(tx_ring->wq_base_dma);
2693 wqicb->cnsmr_idx_addr = cpu_to_le64(tx_ring->cnsmr_idx_sh_reg_dma);
2695 ql_init_tx_ring(qdev, tx_ring);
2697 err = ql_write_cfg(qdev, wqicb, sizeof(wqicb), CFG_LRQ,
2698 (u16) tx_ring->wq_id);
2700 QPRINTK(qdev, IFUP, ERR, "Failed to load tx_ring.\n");
2703 QPRINTK(qdev, IFUP, DEBUG, "Successfully loaded WQICB.\n");
2707 static void ql_disable_msix(struct ql_adapter *qdev)
2709 if (test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
2710 pci_disable_msix(qdev->pdev);
2711 clear_bit(QL_MSIX_ENABLED, &qdev->flags);
2712 kfree(qdev->msi_x_entry);
2713 qdev->msi_x_entry = NULL;
2714 } else if (test_bit(QL_MSI_ENABLED, &qdev->flags)) {
2715 pci_disable_msi(qdev->pdev);
2716 clear_bit(QL_MSI_ENABLED, &qdev->flags);
2720 static void ql_enable_msix(struct ql_adapter *qdev)
2724 qdev->intr_count = 1;
2725 /* Get the MSIX vectors. */
2726 if (irq_type == MSIX_IRQ) {
2727 /* Try to alloc space for the msix struct,
2728 * if it fails then go to MSI/legacy.
2730 qdev->msi_x_entry = kcalloc(qdev->rx_ring_count,
2731 sizeof(struct msix_entry),
2733 if (!qdev->msi_x_entry) {
2738 for (i = 0; i < qdev->rx_ring_count; i++)
2739 qdev->msi_x_entry[i].entry = i;
2741 if (!pci_enable_msix
2742 (qdev->pdev, qdev->msi_x_entry, qdev->rx_ring_count)) {
2743 set_bit(QL_MSIX_ENABLED, &qdev->flags);
2744 qdev->intr_count = qdev->rx_ring_count;
2745 QPRINTK(qdev, IFUP, DEBUG,
2746 "MSI-X Enabled, got %d vectors.\n",
2750 kfree(qdev->msi_x_entry);
2751 qdev->msi_x_entry = NULL;
2752 QPRINTK(qdev, IFUP, WARNING,
2753 "MSI-X Enable failed, trying MSI.\n");
2758 if (irq_type == MSI_IRQ) {
2759 if (!pci_enable_msi(qdev->pdev)) {
2760 set_bit(QL_MSI_ENABLED, &qdev->flags);
2761 QPRINTK(qdev, IFUP, INFO,
2762 "Running with MSI interrupts.\n");
2767 QPRINTK(qdev, IFUP, DEBUG, "Running with legacy interrupts.\n");
2771 * Here we build the intr_context structures based on
2772 * our rx_ring count and intr vector count.
2773 * The intr_context structure is used to hook each vector
2774 * to possibly different handlers.
2776 static void ql_resolve_queues_to_irqs(struct ql_adapter *qdev)
2779 struct intr_context *intr_context = &qdev->intr_context[0];
2781 ql_enable_msix(qdev);
2783 if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags))) {
2784 /* Each rx_ring has it's
2785 * own intr_context since we have separate
2786 * vectors for each queue.
2787 * This only true when MSI-X is enabled.
2789 for (i = 0; i < qdev->intr_count; i++, intr_context++) {
2790 qdev->rx_ring[i].irq = i;
2791 intr_context->intr = i;
2792 intr_context->qdev = qdev;
2794 * We set up each vectors enable/disable/read bits so
2795 * there's no bit/mask calculations in the critical path.
2797 intr_context->intr_en_mask =
2798 INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
2799 INTR_EN_TYPE_ENABLE | INTR_EN_IHD_MASK | INTR_EN_IHD
2801 intr_context->intr_dis_mask =
2802 INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
2803 INTR_EN_TYPE_DISABLE | INTR_EN_IHD_MASK |
2805 intr_context->intr_read_mask =
2806 INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
2807 INTR_EN_TYPE_READ | INTR_EN_IHD_MASK | INTR_EN_IHD |
2812 * Default queue handles bcast/mcast plus
2813 * async events. Needs buffers.
2815 intr_context->handler = qlge_isr;
2816 sprintf(intr_context->name, "%s-default-queue",
2818 } else if (i < qdev->rss_ring_first_cq_id) {
2820 * Outbound queue is for outbound completions only.
2822 intr_context->handler = qlge_msix_tx_isr;
2823 sprintf(intr_context->name, "%s-tx-%d",
2824 qdev->ndev->name, i);
2827 * Inbound queues handle unicast frames only.
2829 intr_context->handler = qlge_msix_rx_isr;
2830 sprintf(intr_context->name, "%s-rx-%d",
2831 qdev->ndev->name, i);
2836 * All rx_rings use the same intr_context since
2837 * there is only one vector.
2839 intr_context->intr = 0;
2840 intr_context->qdev = qdev;
2842 * We set up each vectors enable/disable/read bits so
2843 * there's no bit/mask calculations in the critical path.
2845 intr_context->intr_en_mask =
2846 INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK | INTR_EN_TYPE_ENABLE;
2847 intr_context->intr_dis_mask =
2848 INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
2849 INTR_EN_TYPE_DISABLE;
2850 intr_context->intr_read_mask =
2851 INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK | INTR_EN_TYPE_READ;
2853 * Single interrupt means one handler for all rings.
2855 intr_context->handler = qlge_isr;
2856 sprintf(intr_context->name, "%s-single_irq", qdev->ndev->name);
2857 for (i = 0; i < qdev->rx_ring_count; i++)
2858 qdev->rx_ring[i].irq = 0;
2862 static void ql_free_irq(struct ql_adapter *qdev)
2865 struct intr_context *intr_context = &qdev->intr_context[0];
2867 for (i = 0; i < qdev->intr_count; i++, intr_context++) {
2868 if (intr_context->hooked) {
2869 if (test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
2870 free_irq(qdev->msi_x_entry[i].vector,
2872 QPRINTK(qdev, IFDOWN, DEBUG,
2873 "freeing msix interrupt %d.\n", i);
2875 free_irq(qdev->pdev->irq, &qdev->rx_ring[0]);
2876 QPRINTK(qdev, IFDOWN, DEBUG,
2877 "freeing msi interrupt %d.\n", i);
2881 ql_disable_msix(qdev);
2884 static int ql_request_irq(struct ql_adapter *qdev)
2888 struct pci_dev *pdev = qdev->pdev;
2889 struct intr_context *intr_context = &qdev->intr_context[0];
2891 ql_resolve_queues_to_irqs(qdev);
2893 for (i = 0; i < qdev->intr_count; i++, intr_context++) {
2894 atomic_set(&intr_context->irq_cnt, 0);
2895 if (test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
2896 status = request_irq(qdev->msi_x_entry[i].vector,
2897 intr_context->handler,
2902 QPRINTK(qdev, IFUP, ERR,
2903 "Failed request for MSIX interrupt %d.\n",
2907 QPRINTK(qdev, IFUP, DEBUG,
2908 "Hooked intr %d, queue type %s%s%s, with name %s.\n",
2910 qdev->rx_ring[i].type ==
2911 DEFAULT_Q ? "DEFAULT_Q" : "",
2912 qdev->rx_ring[i].type ==
2914 qdev->rx_ring[i].type ==
2915 RX_Q ? "RX_Q" : "", intr_context->name);
2918 QPRINTK(qdev, IFUP, DEBUG,
2919 "trying msi or legacy interrupts.\n");
2920 QPRINTK(qdev, IFUP, DEBUG,
2921 "%s: irq = %d.\n", __func__, pdev->irq);
2922 QPRINTK(qdev, IFUP, DEBUG,
2923 "%s: context->name = %s.\n", __func__,
2924 intr_context->name);
2925 QPRINTK(qdev, IFUP, DEBUG,
2926 "%s: dev_id = 0x%p.\n", __func__,
2929 request_irq(pdev->irq, qlge_isr,
2930 test_bit(QL_MSI_ENABLED,
2932 flags) ? 0 : IRQF_SHARED,
2933 intr_context->name, &qdev->rx_ring[0]);
2937 QPRINTK(qdev, IFUP, ERR,
2938 "Hooked intr %d, queue type %s%s%s, with name %s.\n",
2940 qdev->rx_ring[0].type ==
2941 DEFAULT_Q ? "DEFAULT_Q" : "",
2942 qdev->rx_ring[0].type == TX_Q ? "TX_Q" : "",
2943 qdev->rx_ring[0].type == RX_Q ? "RX_Q" : "",
2944 intr_context->name);
2946 intr_context->hooked = 1;
2950 QPRINTK(qdev, IFUP, ERR, "Failed to get the interrupts!!!/n");
2955 static int ql_start_rss(struct ql_adapter *qdev)
2957 struct ricb *ricb = &qdev->ricb;
2960 u8 *hash_id = (u8 *) ricb->hash_cq_id;
2962 memset((void *)ricb, 0, sizeof(ricb));
2964 ricb->base_cq = qdev->rss_ring_first_cq_id | RSS_L4K;
2966 (RSS_L6K | RSS_LI | RSS_LB | RSS_LM | RSS_RI4 | RSS_RI6 | RSS_RT4 |
2968 ricb->mask = cpu_to_le16(qdev->rss_ring_count - 1);
2971 * Fill out the Indirection Table.
2973 for (i = 0; i < 256; i++)
2974 hash_id[i] = i & (qdev->rss_ring_count - 1);
2977 * Random values for the IPv6 and IPv4 Hash Keys.
2979 get_random_bytes((void *)&ricb->ipv6_hash_key[0], 40);
2980 get_random_bytes((void *)&ricb->ipv4_hash_key[0], 16);
2982 QPRINTK(qdev, IFUP, DEBUG, "Initializing RSS.\n");
2984 status = ql_write_cfg(qdev, ricb, sizeof(ricb), CFG_LR, 0);
2986 QPRINTK(qdev, IFUP, ERR, "Failed to load RICB.\n");
2989 QPRINTK(qdev, IFUP, DEBUG, "Successfully loaded RICB.\n");
2993 /* Initialize the frame-to-queue routing. */
2994 static int ql_route_initialize(struct ql_adapter *qdev)
2999 status = ql_sem_spinlock(qdev, SEM_RT_IDX_MASK);
3003 /* Clear all the entries in the routing table. */
3004 for (i = 0; i < 16; i++) {
3005 status = ql_set_routing_reg(qdev, i, 0, 0);
3007 QPRINTK(qdev, IFUP, ERR,
3008 "Failed to init routing register for CAM packets.\n");
3013 status = ql_set_routing_reg(qdev, RT_IDX_ALL_ERR_SLOT, RT_IDX_ERR, 1);
3015 QPRINTK(qdev, IFUP, ERR,
3016 "Failed to init routing register for error packets.\n");
3019 status = ql_set_routing_reg(qdev, RT_IDX_BCAST_SLOT, RT_IDX_BCAST, 1);
3021 QPRINTK(qdev, IFUP, ERR,
3022 "Failed to init routing register for broadcast packets.\n");
3025 /* If we have more than one inbound queue, then turn on RSS in the
3028 if (qdev->rss_ring_count > 1) {
3029 status = ql_set_routing_reg(qdev, RT_IDX_RSS_MATCH_SLOT,
3030 RT_IDX_RSS_MATCH, 1);
3032 QPRINTK(qdev, IFUP, ERR,
3033 "Failed to init routing register for MATCH RSS packets.\n");
3038 status = ql_set_routing_reg(qdev, RT_IDX_CAM_HIT_SLOT,
3041 QPRINTK(qdev, IFUP, ERR,
3042 "Failed to init routing register for CAM packets.\n");
3044 ql_sem_unlock(qdev, SEM_RT_IDX_MASK);
3048 int ql_cam_route_initialize(struct ql_adapter *qdev)
3052 status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
3055 status = ql_set_mac_addr_reg(qdev, (u8 *) qdev->ndev->perm_addr,
3056 MAC_ADDR_TYPE_CAM_MAC, qdev->func * MAX_CQ);
3057 ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
3059 QPRINTK(qdev, IFUP, ERR, "Failed to init mac address.\n");
3063 status = ql_route_initialize(qdev);
3065 QPRINTK(qdev, IFUP, ERR, "Failed to init routing table.\n");
3070 static int ql_adapter_initialize(struct ql_adapter *qdev)
3077 * Set up the System register to halt on errors.
3079 value = SYS_EFE | SYS_FAE;
3081 ql_write32(qdev, SYS, mask | value);
3083 /* Set the default queue, and VLAN behavior. */
3084 value = NIC_RCV_CFG_DFQ | NIC_RCV_CFG_RV;
3085 mask = NIC_RCV_CFG_DFQ_MASK | (NIC_RCV_CFG_RV << 16);
3086 ql_write32(qdev, NIC_RCV_CFG, (mask | value));
3088 /* Set the MPI interrupt to enabled. */
3089 ql_write32(qdev, INTR_MASK, (INTR_MASK_PI << 16) | INTR_MASK_PI);
3091 /* Enable the function, set pagesize, enable error checking. */
3092 value = FSC_FE | FSC_EPC_INBOUND | FSC_EPC_OUTBOUND |
3093 FSC_EC | FSC_VM_PAGE_4K | FSC_SH;
3095 /* Set/clear header splitting. */
3096 mask = FSC_VM_PAGESIZE_MASK |
3097 FSC_DBL_MASK | FSC_DBRST_MASK | (value << 16);
3098 ql_write32(qdev, FSC, mask | value);
3100 ql_write32(qdev, SPLT_HDR, SPLT_HDR_EP |
3101 min(SMALL_BUFFER_SIZE, MAX_SPLIT_SIZE));
3103 /* Start up the rx queues. */
3104 for (i = 0; i < qdev->rx_ring_count; i++) {
3105 status = ql_start_rx_ring(qdev, &qdev->rx_ring[i]);
3107 QPRINTK(qdev, IFUP, ERR,
3108 "Failed to start rx ring[%d].\n", i);
3113 /* If there is more than one inbound completion queue
3114 * then download a RICB to configure RSS.
3116 if (qdev->rss_ring_count > 1) {
3117 status = ql_start_rss(qdev);
3119 QPRINTK(qdev, IFUP, ERR, "Failed to start RSS.\n");
3124 /* Start up the tx queues. */
3125 for (i = 0; i < qdev->tx_ring_count; i++) {
3126 status = ql_start_tx_ring(qdev, &qdev->tx_ring[i]);
3128 QPRINTK(qdev, IFUP, ERR,
3129 "Failed to start tx ring[%d].\n", i);
3134 /* Initialize the port and set the max framesize. */
3135 status = qdev->nic_ops->port_initialize(qdev);
3137 QPRINTK(qdev, IFUP, ERR, "Failed to start port.\n");
3141 /* Set up the MAC address and frame routing filter. */
3142 status = ql_cam_route_initialize(qdev);
3144 QPRINTK(qdev, IFUP, ERR,
3145 "Failed to init CAM/Routing tables.\n");
3149 /* Start NAPI for the RSS queues. */
3150 for (i = qdev->rss_ring_first_cq_id; i < qdev->rx_ring_count; i++) {
3151 QPRINTK(qdev, IFUP, DEBUG, "Enabling NAPI for rx_ring[%d].\n",
3153 napi_enable(&qdev->rx_ring[i].napi);
3159 /* Issue soft reset to chip. */
3160 static int ql_adapter_reset(struct ql_adapter *qdev)
3164 unsigned long end_jiffies = jiffies +
3165 max((unsigned long)1, usecs_to_jiffies(30));
3167 ql_write32(qdev, RST_FO, (RST_FO_FR << 16) | RST_FO_FR);
3170 value = ql_read32(qdev, RST_FO);
3171 if ((value & RST_FO_FR) == 0)
3174 } while (time_before(jiffies, end_jiffies));
3176 if (value & RST_FO_FR) {
3177 QPRINTK(qdev, IFDOWN, ERR,
3178 "ETIMEOUT!!! errored out of resetting the chip!\n");
3179 status = -ETIMEDOUT;
3185 static void ql_display_dev_info(struct net_device *ndev)
3187 struct ql_adapter *qdev = (struct ql_adapter *)netdev_priv(ndev);
3189 QPRINTK(qdev, PROBE, INFO,
3190 "Function #%d, NIC Roll %d, NIC Rev = %d, "
3191 "XG Roll = %d, XG Rev = %d.\n",
3193 qdev->chip_rev_id & 0x0000000f,
3194 qdev->chip_rev_id >> 4 & 0x0000000f,
3195 qdev->chip_rev_id >> 8 & 0x0000000f,
3196 qdev->chip_rev_id >> 12 & 0x0000000f);
3197 QPRINTK(qdev, PROBE, INFO, "MAC address %pM\n", ndev->dev_addr);
3200 static int ql_adapter_down(struct ql_adapter *qdev)
3203 struct rx_ring *rx_ring;
3205 netif_carrier_off(qdev->ndev);
3207 /* Don't kill the reset worker thread if we
3208 * are in the process of recovery.
3210 if (test_bit(QL_ADAPTER_UP, &qdev->flags))
3211 cancel_delayed_work_sync(&qdev->asic_reset_work);
3212 cancel_delayed_work_sync(&qdev->mpi_reset_work);
3213 cancel_delayed_work_sync(&qdev->mpi_work);
3214 cancel_delayed_work_sync(&qdev->mpi_idc_work);
3215 cancel_delayed_work_sync(&qdev->mpi_port_cfg_work);
3217 /* The default queue at index 0 is always processed in
3220 cancel_delayed_work_sync(&qdev->rx_ring[0].rx_work);
3222 /* The rest of the rx_rings are processed in
3223 * a workqueue only if it's a single interrupt
3224 * environment (MSI/Legacy).
3226 for (i = 1; i < qdev->rx_ring_count; i++) {
3227 rx_ring = &qdev->rx_ring[i];
3228 /* Only the RSS rings use NAPI on multi irq
3229 * environment. Outbound completion processing
3230 * is done in interrupt context.
3232 if (i >= qdev->rss_ring_first_cq_id) {
3233 napi_disable(&rx_ring->napi);
3235 cancel_delayed_work_sync(&rx_ring->rx_work);
3239 clear_bit(QL_ADAPTER_UP, &qdev->flags);
3241 ql_disable_interrupts(qdev);
3243 ql_tx_ring_clean(qdev);
3245 /* Call netif_napi_del() from common point.
3247 for (i = qdev->rss_ring_first_cq_id; i < qdev->rx_ring_count; i++)
3248 netif_napi_del(&qdev->rx_ring[i].napi);
3250 ql_free_rx_buffers(qdev);
3251 spin_lock(&qdev->hw_lock);
3252 status = ql_adapter_reset(qdev);
3254 QPRINTK(qdev, IFDOWN, ERR, "reset(func #%d) FAILED!\n",
3256 spin_unlock(&qdev->hw_lock);
3260 static int ql_adapter_up(struct ql_adapter *qdev)
3264 err = ql_adapter_initialize(qdev);
3266 QPRINTK(qdev, IFUP, INFO, "Unable to initialize adapter.\n");
3267 spin_unlock(&qdev->hw_lock);
3270 set_bit(QL_ADAPTER_UP, &qdev->flags);
3271 ql_alloc_rx_buffers(qdev);
3272 if ((ql_read32(qdev, STS) & qdev->port_init))
3273 netif_carrier_on(qdev->ndev);
3274 ql_enable_interrupts(qdev);
3275 ql_enable_all_completion_interrupts(qdev);
3276 netif_tx_start_all_queues(qdev->ndev);
3280 ql_adapter_reset(qdev);
3284 static void ql_release_adapter_resources(struct ql_adapter *qdev)
3286 ql_free_mem_resources(qdev);
3290 static int ql_get_adapter_resources(struct ql_adapter *qdev)
3294 if (ql_alloc_mem_resources(qdev)) {
3295 QPRINTK(qdev, IFUP, ERR, "Unable to allocate memory.\n");
3298 status = ql_request_irq(qdev);
3303 ql_free_mem_resources(qdev);
3307 static int qlge_close(struct net_device *ndev)
3309 struct ql_adapter *qdev = netdev_priv(ndev);
3312 * Wait for device to recover from a reset.
3313 * (Rarely happens, but possible.)
3315 while (!test_bit(QL_ADAPTER_UP, &qdev->flags))
3317 ql_adapter_down(qdev);
3318 ql_release_adapter_resources(qdev);
3322 static int ql_configure_rings(struct ql_adapter *qdev)
3325 struct rx_ring *rx_ring;
3326 struct tx_ring *tx_ring;
3327 int cpu_cnt = num_online_cpus();
3330 * For each processor present we allocate one
3331 * rx_ring for outbound completions, and one
3332 * rx_ring for inbound completions. Plus there is
3333 * always the one default queue. For the CPU
3334 * counts we end up with the following rx_rings:
3336 * one default queue +
3337 * (CPU count * outbound completion rx_ring) +
3338 * (CPU count * inbound (RSS) completion rx_ring)
3339 * To keep it simple we limit the total number of
3340 * queues to < 32, so we truncate CPU to 8.
3341 * This limitation can be removed when requested.
3344 if (cpu_cnt > MAX_CPUS)
3348 * rx_ring[0] is always the default queue.
3350 /* Allocate outbound completion ring for each CPU. */
3351 qdev->tx_ring_count = cpu_cnt;
3352 /* Allocate inbound completion (RSS) ring for each CPU. */
3353 qdev->rss_ring_count = cpu_cnt;
3354 /* cq_id for the first inbound ring handler. */
3355 qdev->rss_ring_first_cq_id = cpu_cnt + 1;
3357 * qdev->rx_ring_count:
3358 * Total number of rx_rings. This includes the one
3359 * default queue, a number of outbound completion
3360 * handler rx_rings, and the number of inbound
3361 * completion handler rx_rings.
3363 qdev->rx_ring_count = qdev->tx_ring_count + qdev->rss_ring_count + 1;
3364 netif_set_gso_max_size(qdev->ndev, 65536);
3366 for (i = 0; i < qdev->tx_ring_count; i++) {
3367 tx_ring = &qdev->tx_ring[i];
3368 memset((void *)tx_ring, 0, sizeof(tx_ring));
3369 tx_ring->qdev = qdev;
3371 tx_ring->wq_len = qdev->tx_ring_size;
3373 tx_ring->wq_len * sizeof(struct ob_mac_iocb_req);
3376 * The completion queue ID for the tx rings start
3377 * immediately after the default Q ID, which is zero.
3379 tx_ring->cq_id = i + 1;
3382 for (i = 0; i < qdev->rx_ring_count; i++) {
3383 rx_ring = &qdev->rx_ring[i];
3384 memset((void *)rx_ring, 0, sizeof(rx_ring));
3385 rx_ring->qdev = qdev;
3387 rx_ring->cpu = i % cpu_cnt; /* CPU to run handler on. */
3388 if (i == 0) { /* Default queue at index 0. */
3390 * Default queue handles bcast/mcast plus
3391 * async events. Needs buffers.
3393 rx_ring->cq_len = qdev->rx_ring_size;
3395 rx_ring->cq_len * sizeof(struct ql_net_rsp_iocb);
3396 rx_ring->lbq_len = NUM_LARGE_BUFFERS;
3398 rx_ring->lbq_len * sizeof(__le64);
3399 rx_ring->lbq_buf_size = LARGE_BUFFER_SIZE;
3400 rx_ring->sbq_len = NUM_SMALL_BUFFERS;
3402 rx_ring->sbq_len * sizeof(__le64);
3403 rx_ring->sbq_buf_size = SMALL_BUFFER_SIZE * 2;
3404 rx_ring->type = DEFAULT_Q;
3405 } else if (i < qdev->rss_ring_first_cq_id) {
3407 * Outbound queue handles outbound completions only.
3409 /* outbound cq is same size as tx_ring it services. */
3410 rx_ring->cq_len = qdev->tx_ring_size;
3412 rx_ring->cq_len * sizeof(struct ql_net_rsp_iocb);
3413 rx_ring->lbq_len = 0;
3414 rx_ring->lbq_size = 0;
3415 rx_ring->lbq_buf_size = 0;
3416 rx_ring->sbq_len = 0;
3417 rx_ring->sbq_size = 0;
3418 rx_ring->sbq_buf_size = 0;
3419 rx_ring->type = TX_Q;
3420 } else { /* Inbound completions (RSS) queues */
3422 * Inbound queues handle unicast frames only.
3424 rx_ring->cq_len = qdev->rx_ring_size;
3426 rx_ring->cq_len * sizeof(struct ql_net_rsp_iocb);
3427 rx_ring->lbq_len = NUM_LARGE_BUFFERS;
3429 rx_ring->lbq_len * sizeof(__le64);
3430 rx_ring->lbq_buf_size = LARGE_BUFFER_SIZE;
3431 rx_ring->sbq_len = NUM_SMALL_BUFFERS;
3433 rx_ring->sbq_len * sizeof(__le64);
3434 rx_ring->sbq_buf_size = SMALL_BUFFER_SIZE * 2;
3435 rx_ring->type = RX_Q;
3441 static int qlge_open(struct net_device *ndev)
3444 struct ql_adapter *qdev = netdev_priv(ndev);
3446 err = ql_configure_rings(qdev);
3450 err = ql_get_adapter_resources(qdev);
3454 err = ql_adapter_up(qdev);
3461 ql_release_adapter_resources(qdev);
3465 static int qlge_change_mtu(struct net_device *ndev, int new_mtu)
3467 struct ql_adapter *qdev = netdev_priv(ndev);
3469 if (ndev->mtu == 1500 && new_mtu == 9000) {
3470 QPRINTK(qdev, IFUP, ERR, "Changing to jumbo MTU.\n");
3471 queue_delayed_work(qdev->workqueue,
3472 &qdev->mpi_port_cfg_work, 0);
3473 } else if (ndev->mtu == 9000 && new_mtu == 1500) {
3474 QPRINTK(qdev, IFUP, ERR, "Changing to normal MTU.\n");
3475 } else if ((ndev->mtu == 1500 && new_mtu == 1500) ||
3476 (ndev->mtu == 9000 && new_mtu == 9000)) {
3480 ndev->mtu = new_mtu;
3484 static struct net_device_stats *qlge_get_stats(struct net_device
3487 struct ql_adapter *qdev = netdev_priv(ndev);
3488 return &qdev->stats;
3491 static void qlge_set_multicast_list(struct net_device *ndev)
3493 struct ql_adapter *qdev = (struct ql_adapter *)netdev_priv(ndev);
3494 struct dev_mc_list *mc_ptr;
3497 status = ql_sem_spinlock(qdev, SEM_RT_IDX_MASK);
3500 spin_lock(&qdev->hw_lock);
3502 * Set or clear promiscuous mode if a
3503 * transition is taking place.
3505 if (ndev->flags & IFF_PROMISC) {
3506 if (!test_bit(QL_PROMISCUOUS, &qdev->flags)) {
3507 if (ql_set_routing_reg
3508 (qdev, RT_IDX_PROMISCUOUS_SLOT, RT_IDX_VALID, 1)) {
3509 QPRINTK(qdev, HW, ERR,
3510 "Failed to set promiscous mode.\n");
3512 set_bit(QL_PROMISCUOUS, &qdev->flags);
3516 if (test_bit(QL_PROMISCUOUS, &qdev->flags)) {
3517 if (ql_set_routing_reg
3518 (qdev, RT_IDX_PROMISCUOUS_SLOT, RT_IDX_VALID, 0)) {
3519 QPRINTK(qdev, HW, ERR,
3520 "Failed to clear promiscous mode.\n");
3522 clear_bit(QL_PROMISCUOUS, &qdev->flags);
3528 * Set or clear all multicast mode if a
3529 * transition is taking place.
3531 if ((ndev->flags & IFF_ALLMULTI) ||
3532 (ndev->mc_count > MAX_MULTICAST_ENTRIES)) {
3533 if (!test_bit(QL_ALLMULTI, &qdev->flags)) {
3534 if (ql_set_routing_reg
3535 (qdev, RT_IDX_ALLMULTI_SLOT, RT_IDX_MCAST, 1)) {
3536 QPRINTK(qdev, HW, ERR,
3537 "Failed to set all-multi mode.\n");
3539 set_bit(QL_ALLMULTI, &qdev->flags);
3543 if (test_bit(QL_ALLMULTI, &qdev->flags)) {
3544 if (ql_set_routing_reg
3545 (qdev, RT_IDX_ALLMULTI_SLOT, RT_IDX_MCAST, 0)) {
3546 QPRINTK(qdev, HW, ERR,
3547 "Failed to clear all-multi mode.\n");
3549 clear_bit(QL_ALLMULTI, &qdev->flags);
3554 if (ndev->mc_count) {
3555 status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
3558 for (i = 0, mc_ptr = ndev->mc_list; mc_ptr;
3559 i++, mc_ptr = mc_ptr->next)
3560 if (ql_set_mac_addr_reg(qdev, (u8 *) mc_ptr->dmi_addr,
3561 MAC_ADDR_TYPE_MULTI_MAC, i)) {
3562 QPRINTK(qdev, HW, ERR,
3563 "Failed to loadmulticast address.\n");
3564 ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
3567 ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
3568 if (ql_set_routing_reg
3569 (qdev, RT_IDX_MCAST_MATCH_SLOT, RT_IDX_MCAST_MATCH, 1)) {
3570 QPRINTK(qdev, HW, ERR,
3571 "Failed to set multicast match mode.\n");
3573 set_bit(QL_ALLMULTI, &qdev->flags);
3577 spin_unlock(&qdev->hw_lock);
3578 ql_sem_unlock(qdev, SEM_RT_IDX_MASK);
3581 static int qlge_set_mac_address(struct net_device *ndev, void *p)
3583 struct ql_adapter *qdev = (struct ql_adapter *)netdev_priv(ndev);
3584 struct sockaddr *addr = p;
3587 if (netif_running(ndev))
3590 if (!is_valid_ether_addr(addr->sa_data))
3591 return -EADDRNOTAVAIL;
3592 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
3594 status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
3597 spin_lock(&qdev->hw_lock);
3598 status = ql_set_mac_addr_reg(qdev, (u8 *) ndev->dev_addr,
3599 MAC_ADDR_TYPE_CAM_MAC, qdev->func * MAX_CQ);
3600 spin_unlock(&qdev->hw_lock);
3602 QPRINTK(qdev, HW, ERR, "Failed to load MAC address.\n");
3603 ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
3607 static void qlge_tx_timeout(struct net_device *ndev)
3609 struct ql_adapter *qdev = (struct ql_adapter *)netdev_priv(ndev);
3610 ql_queue_asic_error(qdev);
3613 static void ql_asic_reset_work(struct work_struct *work)
3615 struct ql_adapter *qdev =
3616 container_of(work, struct ql_adapter, asic_reset_work.work);
3619 status = ql_adapter_down(qdev);
3623 status = ql_adapter_up(qdev);
3629 QPRINTK(qdev, IFUP, ALERT,
3630 "Driver up/down cycle failed, closing device\n");
3632 set_bit(QL_ADAPTER_UP, &qdev->flags);
3633 dev_close(qdev->ndev);
3637 static struct nic_operations qla8012_nic_ops = {
3638 .get_flash = ql_get_8012_flash_params,
3639 .port_initialize = ql_8012_port_initialize,
3642 static struct nic_operations qla8000_nic_ops = {
3643 .get_flash = ql_get_8000_flash_params,
3644 .port_initialize = ql_8000_port_initialize,
3648 static void ql_get_board_info(struct ql_adapter *qdev)
3651 (ql_read32(qdev, STS) & STS_FUNC_ID_MASK) >> STS_FUNC_ID_SHIFT;
3653 qdev->xg_sem_mask = SEM_XGMAC1_MASK;
3654 qdev->port_link_up = STS_PL1;
3655 qdev->port_init = STS_PI1;
3656 qdev->mailbox_in = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC2_MBI;
3657 qdev->mailbox_out = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC2_MBO;
3659 qdev->xg_sem_mask = SEM_XGMAC0_MASK;
3660 qdev->port_link_up = STS_PL0;
3661 qdev->port_init = STS_PI0;
3662 qdev->mailbox_in = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC0_MBI;
3663 qdev->mailbox_out = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC0_MBO;
3665 qdev->chip_rev_id = ql_read32(qdev, REV_ID);
3666 qdev->device_id = qdev->pdev->device;
3667 if (qdev->device_id == QLGE_DEVICE_ID_8012)
3668 qdev->nic_ops = &qla8012_nic_ops;
3669 else if (qdev->device_id == QLGE_DEVICE_ID_8000)
3670 qdev->nic_ops = &qla8000_nic_ops;
3673 static void ql_release_all(struct pci_dev *pdev)
3675 struct net_device *ndev = pci_get_drvdata(pdev);
3676 struct ql_adapter *qdev = netdev_priv(ndev);
3678 if (qdev->workqueue) {
3679 destroy_workqueue(qdev->workqueue);
3680 qdev->workqueue = NULL;
3682 if (qdev->q_workqueue) {
3683 destroy_workqueue(qdev->q_workqueue);
3684 qdev->q_workqueue = NULL;
3687 iounmap(qdev->reg_base);
3688 if (qdev->doorbell_area)
3689 iounmap(qdev->doorbell_area);
3690 pci_release_regions(pdev);
3691 pci_set_drvdata(pdev, NULL);
3694 static int __devinit ql_init_device(struct pci_dev *pdev,
3695 struct net_device *ndev, int cards_found)
3697 struct ql_adapter *qdev = netdev_priv(ndev);
3701 memset((void *)qdev, 0, sizeof(qdev));
3702 err = pci_enable_device(pdev);
3704 dev_err(&pdev->dev, "PCI device enable failed.\n");
3708 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3710 dev_err(&pdev->dev, PFX "Cannot find PCI Express capability, "
3714 pci_read_config_word(pdev, pos + PCI_EXP_DEVCTL, &val16);
3715 val16 &= ~PCI_EXP_DEVCTL_NOSNOOP_EN;
3716 val16 |= (PCI_EXP_DEVCTL_CERE |
3717 PCI_EXP_DEVCTL_NFERE |
3718 PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE);
3719 pci_write_config_word(pdev, pos + PCI_EXP_DEVCTL, val16);
3722 err = pci_request_regions(pdev, DRV_NAME);
3724 dev_err(&pdev->dev, "PCI region request failed.\n");
3728 pci_set_master(pdev);
3729 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
3730 set_bit(QL_DMA64, &qdev->flags);
3731 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3733 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3735 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3739 dev_err(&pdev->dev, "No usable DMA configuration.\n");
3743 pci_set_drvdata(pdev, ndev);
3745 ioremap_nocache(pci_resource_start(pdev, 1),
3746 pci_resource_len(pdev, 1));
3747 if (!qdev->reg_base) {
3748 dev_err(&pdev->dev, "Register mapping failed.\n");
3753 qdev->doorbell_area_size = pci_resource_len(pdev, 3);
3754 qdev->doorbell_area =
3755 ioremap_nocache(pci_resource_start(pdev, 3),
3756 pci_resource_len(pdev, 3));
3757 if (!qdev->doorbell_area) {
3758 dev_err(&pdev->dev, "Doorbell register mapping failed.\n");
3765 ql_get_board_info(qdev);
3766 qdev->msg_enable = netif_msg_init(debug, default_msg);
3767 spin_lock_init(&qdev->hw_lock);
3768 spin_lock_init(&qdev->stats_lock);
3770 /* make sure the EEPROM is good */
3771 err = qdev->nic_ops->get_flash(qdev);
3773 dev_err(&pdev->dev, "Invalid FLASH.\n");
3777 memcpy(ndev->perm_addr, ndev->dev_addr, ndev->addr_len);
3779 /* Set up the default ring sizes. */
3780 qdev->tx_ring_size = NUM_TX_RING_ENTRIES;
3781 qdev->rx_ring_size = NUM_RX_RING_ENTRIES;
3783 /* Set up the coalescing parameters. */
3784 qdev->rx_coalesce_usecs = DFLT_COALESCE_WAIT;
3785 qdev->tx_coalesce_usecs = DFLT_COALESCE_WAIT;
3786 qdev->rx_max_coalesced_frames = DFLT_INTER_FRAME_WAIT;
3787 qdev->tx_max_coalesced_frames = DFLT_INTER_FRAME_WAIT;
3790 * Set up the operating parameters.
3794 qdev->q_workqueue = create_workqueue(ndev->name);
3795 qdev->workqueue = create_singlethread_workqueue(ndev->name);
3796 INIT_DELAYED_WORK(&qdev->asic_reset_work, ql_asic_reset_work);
3797 INIT_DELAYED_WORK(&qdev->mpi_reset_work, ql_mpi_reset_work);
3798 INIT_DELAYED_WORK(&qdev->mpi_work, ql_mpi_work);
3799 INIT_DELAYED_WORK(&qdev->mpi_port_cfg_work, ql_mpi_port_cfg_work);
3800 INIT_DELAYED_WORK(&qdev->mpi_idc_work, ql_mpi_idc_work);
3801 mutex_init(&qdev->mpi_mutex);
3802 init_completion(&qdev->ide_completion);
3805 dev_info(&pdev->dev, "%s\n", DRV_STRING);
3806 dev_info(&pdev->dev, "Driver name: %s, Version: %s.\n",
3807 DRV_NAME, DRV_VERSION);
3811 ql_release_all(pdev);
3812 pci_disable_device(pdev);
3817 static const struct net_device_ops qlge_netdev_ops = {
3818 .ndo_open = qlge_open,
3819 .ndo_stop = qlge_close,
3820 .ndo_start_xmit = qlge_send,
3821 .ndo_change_mtu = qlge_change_mtu,
3822 .ndo_get_stats = qlge_get_stats,
3823 .ndo_set_multicast_list = qlge_set_multicast_list,
3824 .ndo_set_mac_address = qlge_set_mac_address,
3825 .ndo_validate_addr = eth_validate_addr,
3826 .ndo_tx_timeout = qlge_tx_timeout,
3827 .ndo_vlan_rx_register = ql_vlan_rx_register,
3828 .ndo_vlan_rx_add_vid = ql_vlan_rx_add_vid,
3829 .ndo_vlan_rx_kill_vid = ql_vlan_rx_kill_vid,
3832 static int __devinit qlge_probe(struct pci_dev *pdev,
3833 const struct pci_device_id *pci_entry)
3835 struct net_device *ndev = NULL;
3836 struct ql_adapter *qdev = NULL;
3837 static int cards_found = 0;
3840 ndev = alloc_etherdev_mq(sizeof(struct ql_adapter),
3841 min(MAX_CPUS, (int)num_online_cpus()));
3845 err = ql_init_device(pdev, ndev, cards_found);
3851 qdev = netdev_priv(ndev);
3852 SET_NETDEV_DEV(ndev, &pdev->dev);
3859 | NETIF_F_HW_VLAN_TX
3860 | NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_FILTER);
3861 ndev->features |= NETIF_F_GRO;
3863 if (test_bit(QL_DMA64, &qdev->flags))
3864 ndev->features |= NETIF_F_HIGHDMA;
3867 * Set up net_device structure.
3869 ndev->tx_queue_len = qdev->tx_ring_size;
3870 ndev->irq = pdev->irq;
3872 ndev->netdev_ops = &qlge_netdev_ops;
3873 SET_ETHTOOL_OPS(ndev, &qlge_ethtool_ops);
3874 ndev->watchdog_timeo = 10 * HZ;
3876 err = register_netdev(ndev);
3878 dev_err(&pdev->dev, "net device registration failed.\n");
3879 ql_release_all(pdev);
3880 pci_disable_device(pdev);
3883 netif_carrier_off(ndev);
3884 ql_display_dev_info(ndev);
3889 static void __devexit qlge_remove(struct pci_dev *pdev)
3891 struct net_device *ndev = pci_get_drvdata(pdev);
3892 unregister_netdev(ndev);
3893 ql_release_all(pdev);
3894 pci_disable_device(pdev);
3899 * This callback is called by the PCI subsystem whenever
3900 * a PCI bus error is detected.
3902 static pci_ers_result_t qlge_io_error_detected(struct pci_dev *pdev,
3903 enum pci_channel_state state)
3905 struct net_device *ndev = pci_get_drvdata(pdev);
3906 struct ql_adapter *qdev = netdev_priv(ndev);
3908 if (netif_running(ndev))
3909 ql_adapter_down(qdev);
3911 pci_disable_device(pdev);
3913 /* Request a slot reset. */
3914 return PCI_ERS_RESULT_NEED_RESET;
3918 * This callback is called after the PCI buss has been reset.
3919 * Basically, this tries to restart the card from scratch.
3920 * This is a shortened version of the device probe/discovery code,
3921 * it resembles the first-half of the () routine.
3923 static pci_ers_result_t qlge_io_slot_reset(struct pci_dev *pdev)
3925 struct net_device *ndev = pci_get_drvdata(pdev);
3926 struct ql_adapter *qdev = netdev_priv(ndev);
3928 if (pci_enable_device(pdev)) {
3929 QPRINTK(qdev, IFUP, ERR,
3930 "Cannot re-enable PCI device after reset.\n");
3931 return PCI_ERS_RESULT_DISCONNECT;
3934 pci_set_master(pdev);
3936 netif_carrier_off(ndev);
3937 ql_adapter_reset(qdev);
3939 /* Make sure the EEPROM is good */
3940 memcpy(ndev->perm_addr, ndev->dev_addr, ndev->addr_len);
3942 if (!is_valid_ether_addr(ndev->perm_addr)) {
3943 QPRINTK(qdev, IFUP, ERR, "After reset, invalid MAC address.\n");
3944 return PCI_ERS_RESULT_DISCONNECT;
3947 return PCI_ERS_RESULT_RECOVERED;
3950 static void qlge_io_resume(struct pci_dev *pdev)
3952 struct net_device *ndev = pci_get_drvdata(pdev);
3953 struct ql_adapter *qdev = netdev_priv(ndev);
3955 pci_set_master(pdev);
3957 if (netif_running(ndev)) {
3958 if (ql_adapter_up(qdev)) {
3959 QPRINTK(qdev, IFUP, ERR,
3960 "Device initialization failed after reset.\n");
3965 netif_device_attach(ndev);
3968 static struct pci_error_handlers qlge_err_handler = {
3969 .error_detected = qlge_io_error_detected,
3970 .slot_reset = qlge_io_slot_reset,
3971 .resume = qlge_io_resume,
3974 static int qlge_suspend(struct pci_dev *pdev, pm_message_t state)
3976 struct net_device *ndev = pci_get_drvdata(pdev);
3977 struct ql_adapter *qdev = netdev_priv(ndev);
3980 netif_device_detach(ndev);
3982 if (netif_running(ndev)) {
3983 err = ql_adapter_down(qdev);
3988 err = pci_save_state(pdev);
3992 pci_disable_device(pdev);
3994 pci_set_power_state(pdev, pci_choose_state(pdev, state));
4000 static int qlge_resume(struct pci_dev *pdev)
4002 struct net_device *ndev = pci_get_drvdata(pdev);
4003 struct ql_adapter *qdev = netdev_priv(ndev);
4006 pci_set_power_state(pdev, PCI_D0);
4007 pci_restore_state(pdev);
4008 err = pci_enable_device(pdev);
4010 QPRINTK(qdev, IFUP, ERR, "Cannot enable PCI device from suspend\n");
4013 pci_set_master(pdev);
4015 pci_enable_wake(pdev, PCI_D3hot, 0);
4016 pci_enable_wake(pdev, PCI_D3cold, 0);
4018 if (netif_running(ndev)) {
4019 err = ql_adapter_up(qdev);
4024 netif_device_attach(ndev);
4028 #endif /* CONFIG_PM */
4030 static void qlge_shutdown(struct pci_dev *pdev)
4032 qlge_suspend(pdev, PMSG_SUSPEND);
4035 static struct pci_driver qlge_driver = {
4037 .id_table = qlge_pci_tbl,
4038 .probe = qlge_probe,
4039 .remove = __devexit_p(qlge_remove),
4041 .suspend = qlge_suspend,
4042 .resume = qlge_resume,
4044 .shutdown = qlge_shutdown,
4045 .err_handler = &qlge_err_handler
4048 static int __init qlge_init_module(void)
4050 return pci_register_driver(&qlge_driver);
4053 static void __exit qlge_exit(void)
4055 pci_unregister_driver(&qlge_driver);
4058 module_init(qlge_init_module);
4059 module_exit(qlge_exit);