SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/net/qlcnic/qlcnic_hw.c

   1 /*
   2  * Copyright (C) 2009 - QLogic Corporation.
   3  * All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License
   7  * as published by the Free Software Foundation; either version 2
   8  * of the License, or (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful, but
  11  * WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
  18  * MA  02111-1307, USA.
  19  *
  20  * The full GNU General Public License is included in this distribution
  21  * in the file called "COPYING".
  22  *
  23  */
  24
  25 #include "qlcnic.h"
  26
  27 #include <linux/slab.h>
  28 #include <net/ip.h>
  29
  30 #define MASK(n) ((1ULL<<(n))-1)
  31 #define OCM_WIN_P3P(addr) (addr & 0xffc0000)
  32
  33 #define GET_MEM_OFFS_2M(addr) (addr & MASK(18))
  34
  35 #define CRB_BLK(off)    ((off >> 20) & 0x3f)
  36 #define CRB_SUBBLK(off) ((off >> 16) & 0xf)
  37 #define CRB_WINDOW_2M   (0x130060)
  38 #define CRB_HI(off)     ((crb_hub_agt[CRB_BLK(off)] << 20) | ((off) & 0xf0000))
  39 #define CRB_INDIRECT_2M (0x1e0000UL)
  40
  41
  42 #ifndef readq
  43 static inline u64 readq(void __iomem *addr)
  44 {
  45         return readl(addr) | (((u64) readl(addr + 4)) << 32LL);
  46 }
  47 #endif
  48
  49 #ifndef writeq
  50 static inline void writeq(u64 val, void __iomem *addr)
  51 {
  52         writel(((u32) (val)), (addr));
  53         writel(((u32) (val >> 32)), (addr + 4));
  54 }
  55 #endif
  56
  57 #define ADDR_IN_RANGE(addr, low, high)  \
  58         (((addr) < (high)) && ((addr) >= (low)))
  59
  60 #define PCI_OFFSET_FIRST_RANGE(adapter, off)    \
  61         ((adapter)->ahw.pci_base0 + (off))
  62
  63 static void __iomem *pci_base_offset(struct qlcnic_adapter *adapter,
  64                                             unsigned long off)
  65 {
  66         if (ADDR_IN_RANGE(off, FIRST_PAGE_GROUP_START, FIRST_PAGE_GROUP_END))
  67                 return PCI_OFFSET_FIRST_RANGE(adapter, off);
  68
  69         return NULL;
  70 }
  71
  72 static const struct crb_128M_2M_block_map
  73 crb_128M_2M_map[64] __cacheline_aligned_in_smp = {
  74     {{{0, 0,         0,         0} } },         /* 0: PCI */
  75     {{{1, 0x0100000, 0x0102000, 0x120000},      /* 1: PCIE */
  76           {1, 0x0110000, 0x0120000, 0x130000},
  77           {1, 0x0120000, 0x0122000, 0x124000},
  78           {1, 0x0130000, 0x0132000, 0x126000},
  79           {1, 0x0140000, 0x0142000, 0x128000},
  80           {1, 0x0150000, 0x0152000, 0x12a000},
  81           {1, 0x0160000, 0x0170000, 0x110000},
  82           {1, 0x0170000, 0x0172000, 0x12e000},
  83           {0, 0x0000000, 0x0000000, 0x000000},
  84           {0, 0x0000000, 0x0000000, 0x000000},
  85           {0, 0x0000000, 0x0000000, 0x000000},
  86           {0, 0x0000000, 0x0000000, 0x000000},
  87           {0, 0x0000000, 0x0000000, 0x000000},
  88           {0, 0x0000000, 0x0000000, 0x000000},
  89           {1, 0x01e0000, 0x01e0800, 0x122000},
  90           {0, 0x0000000, 0x0000000, 0x000000} } },
  91         {{{1, 0x0200000, 0x0210000, 0x180000} } },/* 2: MN */
  92     {{{0, 0,         0,         0} } },     /* 3: */
  93     {{{1, 0x0400000, 0x0401000, 0x169000} } },/* 4: P2NR1 */
  94     {{{1, 0x0500000, 0x0510000, 0x140000} } },/* 5: SRE   */
  95     {{{1, 0x0600000, 0x0610000, 0x1c0000} } },/* 6: NIU   */
  96     {{{1, 0x0700000, 0x0704000, 0x1b8000} } },/* 7: QM    */
  97     {{{1, 0x0800000, 0x0802000, 0x170000},  /* 8: SQM0  */
  98       {0, 0x0000000, 0x0000000, 0x000000},
  99       {0, 0x0000000, 0x0000000, 0x000000},
 100       {0, 0x0000000, 0x0000000, 0x000000},
 101       {0, 0x0000000, 0x0000000, 0x000000},
 102       {0, 0x0000000, 0x0000000, 0x000000},
 103       {0, 0x0000000, 0x0000000, 0x000000},
 104       {0, 0x0000000, 0x0000000, 0x000000},
 105       {0, 0x0000000, 0x0000000, 0x000000},
 106       {0, 0x0000000, 0x0000000, 0x000000},
 107       {0, 0x0000000, 0x0000000, 0x000000},
 108       {0, 0x0000000, 0x0000000, 0x000000},
 109       {0, 0x0000000, 0x0000000, 0x000000},
 110       {0, 0x0000000, 0x0000000, 0x000000},
 111       {0, 0x0000000, 0x0000000, 0x000000},
 112       {1, 0x08f0000, 0x08f2000, 0x172000} } },
 113     {{{1, 0x0900000, 0x0902000, 0x174000},      /* 9: SQM1*/
 114       {0, 0x0000000, 0x0000000, 0x000000},
 115       {0, 0x0000000, 0x0000000, 0x000000},
 116       {0, 0x0000000, 0x0000000, 0x000000},
 117       {0, 0x0000000, 0x0000000, 0x000000},
 118       {0, 0x0000000, 0x0000000, 0x000000},
 119       {0, 0x0000000, 0x0000000, 0x000000},
 120       {0, 0x0000000, 0x0000000, 0x000000},
 121       {0, 0x0000000, 0x0000000, 0x000000},
 122       {0, 0x0000000, 0x0000000, 0x000000},
 123       {0, 0x0000000, 0x0000000, 0x000000},
 124       {0, 0x0000000, 0x0000000, 0x000000},
 125       {0, 0x0000000, 0x0000000, 0x000000},
 126       {0, 0x0000000, 0x0000000, 0x000000},
 127       {0, 0x0000000, 0x0000000, 0x000000},
 128       {1, 0x09f0000, 0x09f2000, 0x176000} } },
 129     {{{0, 0x0a00000, 0x0a02000, 0x178000},      /* 10: SQM2*/
 130       {0, 0x0000000, 0x0000000, 0x000000},
 131       {0, 0x0000000, 0x0000000, 0x000000},
 132       {0, 0x0000000, 0x0000000, 0x000000},
 133       {0, 0x0000000, 0x0000000, 0x000000},
 134       {0, 0x0000000, 0x0000000, 0x000000},
 135       {0, 0x0000000, 0x0000000, 0x000000},
 136       {0, 0x0000000, 0x0000000, 0x000000},
 137       {0, 0x0000000, 0x0000000, 0x000000},
 138       {0, 0x0000000, 0x0000000, 0x000000},
 139       {0, 0x0000000, 0x0000000, 0x000000},
 140       {0, 0x0000000, 0x0000000, 0x000000},
 141       {0, 0x0000000, 0x0000000, 0x000000},
 142       {0, 0x0000000, 0x0000000, 0x000000},
 143       {0, 0x0000000, 0x0000000, 0x000000},
 144       {1, 0x0af0000, 0x0af2000, 0x17a000} } },
 145     {{{0, 0x0b00000, 0x0b02000, 0x17c000},      /* 11: SQM3*/
 146       {0, 0x0000000, 0x0000000, 0x000000},
 147       {0, 0x0000000, 0x0000000, 0x000000},
 148       {0, 0x0000000, 0x0000000, 0x000000},
 149       {0, 0x0000000, 0x0000000, 0x000000},
 150       {0, 0x0000000, 0x0000000, 0x000000},
 151       {0, 0x0000000, 0x0000000, 0x000000},
 152       {0, 0x0000000, 0x0000000, 0x000000},
 153       {0, 0x0000000, 0x0000000, 0x000000},
 154       {0, 0x0000000, 0x0000000, 0x000000},
 155       {0, 0x0000000, 0x0000000, 0x000000},
 156       {0, 0x0000000, 0x0000000, 0x000000},
 157       {0, 0x0000000, 0x0000000, 0x000000},
 158       {0, 0x0000000, 0x0000000, 0x000000},
 159       {0, 0x0000000, 0x0000000, 0x000000},
 160       {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
 161         {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },/* 12: I2Q */
 162         {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },/* 13: TMR */
 163         {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },/* 14: ROMUSB */
 164         {{{1, 0x0f00000, 0x0f01000, 0x164000} } },/* 15: PEG4 */
 165         {{{0, 0x1000000, 0x1004000, 0x1a8000} } },/* 16: XDMA */
 166         {{{1, 0x1100000, 0x1101000, 0x160000} } },/* 17: PEG0 */
 167         {{{1, 0x1200000, 0x1201000, 0x161000} } },/* 18: PEG1 */
 168         {{{1, 0x1300000, 0x1301000, 0x162000} } },/* 19: PEG2 */
 169         {{{1, 0x1400000, 0x1401000, 0x163000} } },/* 20: PEG3 */
 170         {{{1, 0x1500000, 0x1501000, 0x165000} } },/* 21: P2ND */
 171         {{{1, 0x1600000, 0x1601000, 0x166000} } },/* 22: P2NI */
 172         {{{0, 0,         0,         0} } },     /* 23: */
 173         {{{0, 0,         0,         0} } },     /* 24: */
 174         {{{0, 0,         0,         0} } },     /* 25: */
 175         {{{0, 0,         0,         0} } },     /* 26: */
 176         {{{0, 0,         0,         0} } },     /* 27: */
 177         {{{0, 0,         0,         0} } },     /* 28: */
 178         {{{1, 0x1d00000, 0x1d10000, 0x190000} } },/* 29: MS */
 179     {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },/* 30: P2NR2 */
 180     {{{1, 0x1f00000, 0x1f10000, 0x150000} } },/* 31: EPG */
 181         {{{0} } },                              /* 32: PCI */
 182         {{{1, 0x2100000, 0x2102000, 0x120000},  /* 33: PCIE */
 183           {1, 0x2110000, 0x2120000, 0x130000},
 184           {1, 0x2120000, 0x2122000, 0x124000},
 185           {1, 0x2130000, 0x2132000, 0x126000},
 186           {1, 0x2140000, 0x2142000, 0x128000},
 187           {1, 0x2150000, 0x2152000, 0x12a000},
 188           {1, 0x2160000, 0x2170000, 0x110000},
 189           {1, 0x2170000, 0x2172000, 0x12e000},
 190           {0, 0x0000000, 0x0000000, 0x000000},
 191           {0, 0x0000000, 0x0000000, 0x000000},
 192           {0, 0x0000000, 0x0000000, 0x000000},
 193           {0, 0x0000000, 0x0000000, 0x000000},
 194           {0, 0x0000000, 0x0000000, 0x000000},
 195           {0, 0x0000000, 0x0000000, 0x000000},
 196           {0, 0x0000000, 0x0000000, 0x000000},
 197           {0, 0x0000000, 0x0000000, 0x000000} } },
 198         {{{1, 0x2200000, 0x2204000, 0x1b0000} } },/* 34: CAM */
 199         {{{0} } },                              /* 35: */
 200         {{{0} } },                              /* 36: */
 201         {{{0} } },                              /* 37: */
 202         {{{0} } },                              /* 38: */
 203         {{{0} } },                              /* 39: */
 204         {{{1, 0x2800000, 0x2804000, 0x1a4000} } },/* 40: TMR */
 205         {{{1, 0x2900000, 0x2901000, 0x16b000} } },/* 41: P2NR3 */
 206         {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },/* 42: RPMX1 */
 207         {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },/* 43: RPMX2 */
 208         {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },/* 44: RPMX3 */
 209         {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },/* 45: RPMX4 */
 210         {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },/* 46: RPMX5 */
 211         {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },/* 47: RPMX6 */
 212         {{{1, 0x3000000, 0x3000400, 0x1adc00} } },/* 48: RPMX7 */
 213         {{{0, 0x3100000, 0x3104000, 0x1a8000} } },/* 49: XDMA */
 214         {{{1, 0x3200000, 0x3204000, 0x1d4000} } },/* 50: I2Q */
 215         {{{1, 0x3300000, 0x3304000, 0x1a0000} } },/* 51: ROMUSB */
 216         {{{0} } },                              /* 52: */
 217         {{{1, 0x3500000, 0x3500400, 0x1ac000} } },/* 53: RPMX0 */
 218         {{{1, 0x3600000, 0x3600400, 0x1ae000} } },/* 54: RPMX8 */
 219         {{{1, 0x3700000, 0x3700400, 0x1ae400} } },/* 55: RPMX9 */
 220         {{{1, 0x3800000, 0x3804000, 0x1d0000} } },/* 56: OCM0 */
 221         {{{1, 0x3900000, 0x3904000, 0x1b4000} } },/* 57: CRYPTO */
 222         {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },/* 58: SMB */
 223         {{{0} } },                              /* 59: I2C0 */
 224         {{{0} } },                              /* 60: I2C1 */
 225         {{{1, 0x3d00000, 0x3d04000, 0x1d8000} } },/* 61: LPC */
 226         {{{1, 0x3e00000, 0x3e01000, 0x167000} } },/* 62: P2NC */
 227         {{{1, 0x3f00000, 0x3f01000, 0x168000} } }       /* 63: P2NR0 */
 228 };
 229
 230 /*
 231  * top 12 bits of crb internal address (hub, agent)
 232  */
 233 static const unsigned crb_hub_agt[64] = {
 234         0,
 235         QLCNIC_HW_CRB_HUB_AGT_ADR_PS,
 236         QLCNIC_HW_CRB_HUB_AGT_ADR_MN,
 237         QLCNIC_HW_CRB_HUB_AGT_ADR_MS,
 238         0,
 239         QLCNIC_HW_CRB_HUB_AGT_ADR_SRE,
 240         QLCNIC_HW_CRB_HUB_AGT_ADR_NIU,
 241         QLCNIC_HW_CRB_HUB_AGT_ADR_QMN,
 242         QLCNIC_HW_CRB_HUB_AGT_ADR_SQN0,
 243         QLCNIC_HW_CRB_HUB_AGT_ADR_SQN1,
 244         QLCNIC_HW_CRB_HUB_AGT_ADR_SQN2,
 245         QLCNIC_HW_CRB_HUB_AGT_ADR_SQN3,
 246         QLCNIC_HW_CRB_HUB_AGT_ADR_I2Q,
 247         QLCNIC_HW_CRB_HUB_AGT_ADR_TIMR,
 248         QLCNIC_HW_CRB_HUB_AGT_ADR_ROMUSB,
 249         QLCNIC_HW_CRB_HUB_AGT_ADR_PGN4,
 250         QLCNIC_HW_CRB_HUB_AGT_ADR_XDMA,
 251         QLCNIC_HW_CRB_HUB_AGT_ADR_PGN0,
 252         QLCNIC_HW_CRB_HUB_AGT_ADR_PGN1,
 253         QLCNIC_HW_CRB_HUB_AGT_ADR_PGN2,
 254         QLCNIC_HW_CRB_HUB_AGT_ADR_PGN3,
 255         QLCNIC_HW_CRB_HUB_AGT_ADR_PGND,
 256         QLCNIC_HW_CRB_HUB_AGT_ADR_PGNI,
 257         QLCNIC_HW_CRB_HUB_AGT_ADR_PGS0,
 258         QLCNIC_HW_CRB_HUB_AGT_ADR_PGS1,
 259         QLCNIC_HW_CRB_HUB_AGT_ADR_PGS2,
 260         QLCNIC_HW_CRB_HUB_AGT_ADR_PGS3,
 261         0,
 262         QLCNIC_HW_CRB_HUB_AGT_ADR_PGSI,
 263         QLCNIC_HW_CRB_HUB_AGT_ADR_SN,
 264         0,
 265         QLCNIC_HW_CRB_HUB_AGT_ADR_EG,
 266         0,
 267         QLCNIC_HW_CRB_HUB_AGT_ADR_PS,
 268         QLCNIC_HW_CRB_HUB_AGT_ADR_CAM,
 269         0,
 270         0,
 271         0,
 272         0,
 273         0,
 274         QLCNIC_HW_CRB_HUB_AGT_ADR_TIMR,
 275         0,
 276         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX1,
 277         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX2,
 278         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX3,
 279         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX4,
 280         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX5,
 281         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX6,
 282         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX7,
 283         QLCNIC_HW_CRB_HUB_AGT_ADR_XDMA,
 284         QLCNIC_HW_CRB_HUB_AGT_ADR_I2Q,
 285         QLCNIC_HW_CRB_HUB_AGT_ADR_ROMUSB,
 286         0,
 287         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX0,
 288         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX8,
 289         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX9,
 290         QLCNIC_HW_CRB_HUB_AGT_ADR_OCM0,
 291         0,
 292         QLCNIC_HW_CRB_HUB_AGT_ADR_SMB,
 293         QLCNIC_HW_CRB_HUB_AGT_ADR_I2C0,
 294         QLCNIC_HW_CRB_HUB_AGT_ADR_I2C1,
 295         0,
 296         QLCNIC_HW_CRB_HUB_AGT_ADR_PGNC,
 297         0,
 298 };
 299
 300 /*  PCI Windowing for DDR regions.  */
 301
 302 #define QLCNIC_PCIE_SEM_TIMEOUT 10000
 303
 304 int
 305 qlcnic_pcie_sem_lock(struct qlcnic_adapter *adapter, int sem, u32 id_reg)
 306 {
 307         int done = 0, timeout = 0;
 308
 309         while (!done) {
 310                 done = QLCRD32(adapter, QLCNIC_PCIE_REG(PCIE_SEM_LOCK(sem)));
 311                 if (done == 1)
 312                         break;
 313                 if (++timeout >= QLCNIC_PCIE_SEM_TIMEOUT)
 314                         return -EIO;
 315                 msleep(1);
 316         }
 317
 318         if (id_reg)
 319                 QLCWR32(adapter, id_reg, adapter->portnum);
 320
 321         return 0;
 322 }
 323
 324 void
 325 qlcnic_pcie_sem_unlock(struct qlcnic_adapter *adapter, int sem)
 326 {
 327         QLCRD32(adapter, QLCNIC_PCIE_REG(PCIE_SEM_UNLOCK(sem)));
 328 }
 329
 330 static int
 331 qlcnic_send_cmd_descs(struct qlcnic_adapter *adapter,
 332                 struct cmd_desc_type0 *cmd_desc_arr, int nr_desc)
 333 {
 334         u32 i, producer, consumer;
 335         struct qlcnic_cmd_buffer *pbuf;
 336         struct cmd_desc_type0 *cmd_desc;
 337         struct qlcnic_host_tx_ring *tx_ring;
 338
 339         i = 0;
 340
 341         if (adapter->is_up != QLCNIC_ADAPTER_UP_MAGIC)
 342                 return -EIO;
 343
 344         tx_ring = adapter->tx_ring;
 345         __netif_tx_lock_bh(tx_ring->txq);
 346
 347         producer = tx_ring->producer;
 348         consumer = tx_ring->sw_consumer;
 349
 350         if (nr_desc >= qlcnic_tx_avail(tx_ring)) {
 351                 netif_tx_stop_queue(tx_ring->txq);
 352                 __netif_tx_unlock_bh(tx_ring->txq);
 353                 adapter->stats.xmit_off++;
 354                 return -EBUSY;
 355         }
 356
 357         do {
 358                 cmd_desc = &cmd_desc_arr[i];
 359
 360                 pbuf = &tx_ring->cmd_buf_arr[producer];
 361                 pbuf->skb = NULL;
 362                 pbuf->frag_count = 0;
 363
 364                 memcpy(&tx_ring->desc_head[producer],
 365                         &cmd_desc_arr[i], sizeof(struct cmd_desc_type0));
 366
 367                 producer = get_next_index(producer, tx_ring->num_desc);
 368                 i++;
 369
 370         } while (i != nr_desc);
 371
 372         tx_ring->producer = producer;
 373
 374         qlcnic_update_cmd_producer(adapter, tx_ring);
 375
 376         __netif_tx_unlock_bh(tx_ring->txq);
 377
 378         return 0;
 379 }
 380
 381 static int
 382 qlcnic_sre_macaddr_change(struct qlcnic_adapter *adapter, u8 *addr,
 383                                 unsigned op)
 384 {
 385         struct qlcnic_nic_req req;
 386         struct qlcnic_mac_req *mac_req;
 387         u64 word;
 388
 389         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 390         req.qhdr = cpu_to_le64(QLCNIC_REQUEST << 23);
 391
 392         word = QLCNIC_MAC_EVENT | ((u64)adapter->portnum << 16);
 393         req.req_hdr = cpu_to_le64(word);
 394
 395         mac_req = (struct qlcnic_mac_req *)&req.words[0];
 396         mac_req->op = op;
 397         memcpy(mac_req->mac_addr, addr, 6);
 398
 399         return qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
 400 }
 401
 402 static int qlcnic_nic_add_mac(struct qlcnic_adapter *adapter, u8 *addr)
 403 {
 404         struct list_head *head;
 405         struct qlcnic_mac_list_s *cur;
 406
 407         /* look up if already exists */
 408         list_for_each(head, &adapter->mac_list) {
 409                 cur = list_entry(head, struct qlcnic_mac_list_s, list);
 410                 if (memcmp(addr, cur->mac_addr, ETH_ALEN) == 0)
 411                         return 0;
 412         }
 413
 414         cur = kzalloc(sizeof(struct qlcnic_mac_list_s), GFP_ATOMIC);
 415         if (cur == NULL) {
 416                 dev_err(&adapter->netdev->dev,
 417                         "failed to add mac address filter\n");
 418                 return -ENOMEM;
 419         }
 420         memcpy(cur->mac_addr, addr, ETH_ALEN);
 421         list_add_tail(&cur->list, &adapter->mac_list);
 422
 423         return qlcnic_sre_macaddr_change(adapter,
 424                                 cur->mac_addr, QLCNIC_MAC_ADD);
 425 }
 426
 427 void qlcnic_set_multi(struct net_device *netdev)
 428 {
 429         struct qlcnic_adapter *adapter = netdev_priv(netdev);
 430         struct dev_mc_list *mc_ptr;
 431         u8 bcast_addr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
 432         u32 mode = VPORT_MISS_MODE_DROP;
 433
 434         qlcnic_nic_add_mac(adapter, adapter->mac_addr);
 435         qlcnic_nic_add_mac(adapter, bcast_addr);
 436
 437         if (netdev->flags & IFF_PROMISC) {
 438                 mode = VPORT_MISS_MODE_ACCEPT_ALL;
 439                 goto send_fw_cmd;
 440         }
 441
 442         if ((netdev->flags & IFF_ALLMULTI) ||
 443             (netdev_mc_count(netdev) > adapter->max_mc_count)) {
 444                 mode = VPORT_MISS_MODE_ACCEPT_MULTI;
 445                 goto send_fw_cmd;
 446         }
 447
 448         if (!netdev_mc_empty(netdev)) {
 449                 netdev_for_each_mc_addr(mc_ptr, netdev) {
 450                         qlcnic_nic_add_mac(adapter, mc_ptr->dmi_addr);
 451                 }
 452         }
 453
 454 send_fw_cmd:
 455         qlcnic_nic_set_promisc(adapter, mode);
 456 }
 457
 458 int qlcnic_nic_set_promisc(struct qlcnic_adapter *adapter, u32 mode)
 459 {
 460         struct qlcnic_nic_req req;
 461         u64 word;
 462
 463         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 464
 465         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
 466
 467         word = QLCNIC_H2C_OPCODE_PROXY_SET_VPORT_MISS_MODE |
 468                         ((u64)adapter->portnum << 16);
 469         req.req_hdr = cpu_to_le64(word);
 470
 471         req.words[0] = cpu_to_le64(mode);
 472
 473         return qlcnic_send_cmd_descs(adapter,
 474                                 (struct cmd_desc_type0 *)&req, 1);
 475 }
 476
 477 void qlcnic_free_mac_list(struct qlcnic_adapter *adapter)
 478 {
 479         struct qlcnic_mac_list_s *cur;
 480         struct list_head *head = &adapter->mac_list;
 481
 482         while (!list_empty(head)) {
 483                 cur = list_entry(head->next, struct qlcnic_mac_list_s, list);
 484                 qlcnic_sre_macaddr_change(adapter,
 485                                 cur->mac_addr, QLCNIC_MAC_DEL);
 486                 list_del(&cur->list);
 487                 kfree(cur);
 488         }
 489 }
 490
 491 #define QLCNIC_CONFIG_INTR_COALESCE     3
 492
 493 /*
 494  * Send the interrupt coalescing parameter set by ethtool to the card.
 495  */
 496 int qlcnic_config_intr_coalesce(struct qlcnic_adapter *adapter)
 497 {
 498         struct qlcnic_nic_req req;
 499         u64 word[6];
 500         int rv, i;
 501
 502         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 503
 504         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
 505
 506         word[0] = QLCNIC_CONFIG_INTR_COALESCE | ((u64)adapter->portnum << 16);
 507         req.req_hdr = cpu_to_le64(word[0]);
 508
 509         memcpy(&word[0], &adapter->coal, sizeof(adapter->coal));
 510         for (i = 0; i < 6; i++)
 511                 req.words[i] = cpu_to_le64(word[i]);
 512
 513         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
 514         if (rv != 0)
 515                 dev_err(&adapter->netdev->dev,
 516                         "Could not send interrupt coalescing parameters\n");
 517
 518         return rv;
 519 }
 520
 521 int qlcnic_config_hw_lro(struct qlcnic_adapter *adapter, int enable)
 522 {
 523         struct qlcnic_nic_req req;
 524         u64 word;
 525         int rv;
 526
 527         if ((adapter->flags & QLCNIC_LRO_ENABLED) == enable)
 528                 return 0;
 529
 530         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 531
 532         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
 533
 534         word = QLCNIC_H2C_OPCODE_CONFIG_HW_LRO | ((u64)adapter->portnum << 16);
 535         req.req_hdr = cpu_to_le64(word);
 536
 537         req.words[0] = cpu_to_le64(enable);
 538
 539         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
 540         if (rv != 0)
 541                 dev_err(&adapter->netdev->dev,
 542                         "Could not send configure hw lro request\n");
 543
 544         adapter->flags ^= QLCNIC_LRO_ENABLED;
 545
 546         return rv;
 547 }
 548
 549 int qlcnic_config_bridged_mode(struct qlcnic_adapter *adapter, int enable)
 550 {
 551         struct qlcnic_nic_req req;
 552         u64 word;
 553         int rv;
 554
 555         if (!!(adapter->flags & QLCNIC_BRIDGE_ENABLED) == enable)
 556                 return 0;
 557
 558         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 559
 560         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
 561
 562         word = QLCNIC_H2C_OPCODE_CONFIG_BRIDGING |
 563                 ((u64)adapter->portnum << 16);
 564         req.req_hdr = cpu_to_le64(word);
 565
 566         req.words[0] = cpu_to_le64(enable);
 567
 568         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
 569         if (rv != 0)
 570                 dev_err(&adapter->netdev->dev,
 571                         "Could not send configure bridge mode request\n");
 572
 573         adapter->flags ^= QLCNIC_BRIDGE_ENABLED;
 574
 575         return rv;
 576 }
 577
 578
 579 #define RSS_HASHTYPE_IP_TCP     0x3
 580
 581 int qlcnic_config_rss(struct qlcnic_adapter *adapter, int enable)
 582 {
 583         struct qlcnic_nic_req req;
 584         u64 word;
 585         int i, rv;
 586
 587         const u64 key[] = { 0xbeac01fa6a42b73bULL, 0x8030f20c77cb2da3ULL,
 588                         0xae7b30b4d0ca2bcbULL, 0x43a38fb04167253dULL,
 589                         0x255b0ec26d5a56daULL };
 590
 591
 592         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 593         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
 594
 595         word = QLCNIC_H2C_OPCODE_CONFIG_RSS | ((u64)adapter->portnum << 16);
 596         req.req_hdr = cpu_to_le64(word);
 597
 598         /*
 599          * RSS request:
 600          * bits 3-0: hash_method
 601          *      5-4: hash_type_ipv4
 602          *      7-6: hash_type_ipv6
 603          *        8: enable
 604          *        9: use indirection table
 605          *    47-10: reserved
 606          *    63-48: indirection table mask
 607          */
 608         word =  ((u64)(RSS_HASHTYPE_IP_TCP & 0x3) << 4) |
 609                 ((u64)(RSS_HASHTYPE_IP_TCP & 0x3) << 6) |
 610                 ((u64)(enable & 0x1) << 8) |
 611                 ((0x7ULL) << 48);
 612         req.words[0] = cpu_to_le64(word);
 613         for (i = 0; i < 5; i++)
 614                 req.words[i+1] = cpu_to_le64(key[i]);
 615
 616         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
 617         if (rv != 0)
 618                 dev_err(&adapter->netdev->dev, "could not configure RSS\n");
 619
 620         return rv;
 621 }
 622
 623 int qlcnic_config_ipaddr(struct qlcnic_adapter *adapter, u32 ip, int cmd)
 624 {
 625         struct qlcnic_nic_req req;
 626         u64 word;
 627         int rv;
 628
 629         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 630         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
 631
 632         word = QLCNIC_H2C_OPCODE_CONFIG_IPADDR | ((u64)adapter->portnum << 16);
 633         req.req_hdr = cpu_to_le64(word);
 634
 635         req.words[0] = cpu_to_le64(cmd);
 636         req.words[1] = cpu_to_le64(ip);
 637
 638         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
 639         if (rv != 0)
 640                 dev_err(&adapter->netdev->dev,
 641                                 "could not notify %s IP 0x%x reuqest\n",
 642                                 (cmd == QLCNIC_IP_UP) ? "Add" : "Remove", ip);
 643
 644         return rv;
 645 }
 646
 647 int qlcnic_linkevent_request(struct qlcnic_adapter *adapter, int enable)
 648 {
 649         struct qlcnic_nic_req req;
 650         u64 word;
 651         int rv;
 652
 653         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 654         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
 655
 656         word = QLCNIC_H2C_OPCODE_GET_LINKEVENT | ((u64)adapter->portnum << 16);
 657         req.req_hdr = cpu_to_le64(word);
 658         req.words[0] = cpu_to_le64(enable | (enable << 8));
 659
 660         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
 661         if (rv != 0)
 662                 dev_err(&adapter->netdev->dev,
 663                                 "could not configure link notification\n");
 664
 665         return rv;
 666 }
 667
 668 int qlcnic_send_lro_cleanup(struct qlcnic_adapter *adapter)
 669 {
 670         struct qlcnic_nic_req req;
 671         u64 word;
 672         int rv;
 673
 674         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 675         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
 676
 677         word = QLCNIC_H2C_OPCODE_LRO_REQUEST |
 678                 ((u64)adapter->portnum << 16) |
 679                 ((u64)QLCNIC_LRO_REQUEST_CLEANUP << 56) ;
 680
 681         req.req_hdr = cpu_to_le64(word);
 682
 683         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
 684         if (rv != 0)
 685                 dev_err(&adapter->netdev->dev,
 686                                  "could not cleanup lro flows\n");
 687
 688         return rv;
 689 }
 690
 691 /*
 692  * qlcnic_change_mtu - Change the Maximum Transfer Unit
 693  * @returns 0 on success, negative on failure
 694  */
 695
 696 int qlcnic_change_mtu(struct net_device *netdev, int mtu)
 697 {
 698         struct qlcnic_adapter *adapter = netdev_priv(netdev);
 699         int rc = 0;
 700
 701         if (mtu > P3_MAX_MTU) {
 702                 dev_err(&adapter->netdev->dev, "mtu > %d bytes unsupported\n",
 703                                                 P3_MAX_MTU);
 704                 return -EINVAL;
 705         }
 706
 707         rc = qlcnic_fw_cmd_set_mtu(adapter, mtu);
 708
 709         if (!rc)
 710                 netdev->mtu = mtu;
 711
 712         return rc;
 713 }
 714
 715 int qlcnic_get_mac_addr(struct qlcnic_adapter *adapter, u64 *mac)
 716 {
 717         u32 crbaddr, mac_hi, mac_lo;
 718         int pci_func = adapter->ahw.pci_func;
 719
 720         crbaddr = CRB_MAC_BLOCK_START +
 721                 (4 * ((pci_func/2) * 3)) + (4 * (pci_func & 1));
 722
 723         mac_lo = QLCRD32(adapter, crbaddr);
 724         mac_hi = QLCRD32(adapter, crbaddr+4);
 725
 726         if (pci_func & 1)
 727                 *mac = le64_to_cpu((mac_lo >> 16) | ((u64)mac_hi << 16));
 728         else
 729                 *mac = le64_to_cpu((u64)mac_lo | ((u64)mac_hi << 32));
 730
 731         return 0;
 732 }
 733
 734 /*
 735  * Changes the CRB window to the specified window.
 736  */
 737  /* Returns < 0 if off is not valid,
 738  *       1 if window access is needed. 'off' is set to offset from
 739  *         CRB space in 128M pci map
 740  *       0 if no window access is needed. 'off' is set to 2M addr
 741  * In: 'off' is offset from base in 128M pci map
 742  */
 743 static int
 744 qlcnic_pci_get_crb_addr_2M(struct qlcnic_adapter *adapter,
 745                 ulong off, void __iomem **addr)
 746 {
 747         const struct crb_128M_2M_sub_block_map *m;
 748
 749         if ((off >= QLCNIC_CRB_MAX) || (off < QLCNIC_PCI_CRBSPACE))
 750                 return -EINVAL;
 751
 752         off -= QLCNIC_PCI_CRBSPACE;
 753
 754         /*
 755          * Try direct map
 756          */
 757         m = &crb_128M_2M_map[CRB_BLK(off)].sub_block[CRB_SUBBLK(off)];
 758
 759         if (m->valid && (m->start_128M <= off) && (m->end_128M > off)) {
 760                 *addr = adapter->ahw.pci_base0 + m->start_2M +
 761                         (off - m->start_128M);
 762                 return 0;
 763         }
 764
 765         /*
 766          * Not in direct map, use crb window
 767          */
 768         *addr = adapter->ahw.pci_base0 + CRB_INDIRECT_2M + (off & MASK(16));
 769         return 1;
 770 }
 771
 772 /*
 773  * In: 'off' is offset from CRB space in 128M pci map
 774  * Out: 'off' is 2M pci map addr
 775  * side effect: lock crb window
 776  */
 777 static void
 778 qlcnic_pci_set_crbwindow_2M(struct qlcnic_adapter *adapter, ulong off)
 779 {
 780         u32 window;
 781         void __iomem *addr = adapter->ahw.pci_base0 + CRB_WINDOW_2M;
 782
 783         off -= QLCNIC_PCI_CRBSPACE;
 784
 785         window = CRB_HI(off);
 786
 787         if (adapter->ahw.crb_win == window)
 788                 return;
 789
 790         writel(window, addr);
 791         if (readl(addr) != window) {
 792                 if (printk_ratelimit())
 793                         dev_warn(&adapter->pdev->dev,
 794                                 "failed to set CRB window to %d off 0x%lx\n",
 795                                 window, off);
 796         }
 797         adapter->ahw.crb_win = window;
 798 }
 799
 800 int
 801 qlcnic_hw_write_wx_2M(struct qlcnic_adapter *adapter, ulong off, u32 data)
 802 {
 803         unsigned long flags;
 804         int rv;
 805         void __iomem *addr = NULL;
 806
 807         rv = qlcnic_pci_get_crb_addr_2M(adapter, off, &addr);
 808
 809         if (rv == 0) {
 810                 writel(data, addr);
 811                 return 0;
 812         }
 813
 814         if (rv > 0) {
 815                 /* indirect access */
 816                 write_lock_irqsave(&adapter->ahw.crb_lock, flags);
 817                 crb_win_lock(adapter);
 818                 qlcnic_pci_set_crbwindow_2M(adapter, off);
 819                 writel(data, addr);
 820                 crb_win_unlock(adapter);
 821                 write_unlock_irqrestore(&adapter->ahw.crb_lock, flags);
 822                 return 0;
 823         }
 824
 825         dev_err(&adapter->pdev->dev,
 826                         "%s: invalid offset: 0x%016lx\n", __func__, off);
 827         dump_stack();
 828         return -EIO;
 829 }
 830
 831 u32
 832 qlcnic_hw_read_wx_2M(struct qlcnic_adapter *adapter, ulong off)
 833 {
 834         unsigned long flags;
 835         int rv;
 836         u32 data;
 837         void __iomem *addr = NULL;
 838
 839         rv = qlcnic_pci_get_crb_addr_2M(adapter, off, &addr);
 840
 841         if (rv == 0)
 842                 return readl(addr);
 843
 844         if (rv > 0) {
 845                 /* indirect access */
 846                 write_lock_irqsave(&adapter->ahw.crb_lock, flags);
 847                 crb_win_lock(adapter);
 848                 qlcnic_pci_set_crbwindow_2M(adapter, off);
 849                 data = readl(addr);
 850                 crb_win_unlock(adapter);
 851                 write_unlock_irqrestore(&adapter->ahw.crb_lock, flags);
 852                 return data;
 853         }
 854
 855         dev_err(&adapter->pdev->dev,
 856                         "%s: invalid offset: 0x%016lx\n", __func__, off);
 857         dump_stack();
 858         return -1;
 859 }
 860
 861
 862 void __iomem *
 863 qlcnic_get_ioaddr(struct qlcnic_adapter *adapter, u32 offset)
 864 {
 865         void __iomem *addr = NULL;
 866
 867         WARN_ON(qlcnic_pci_get_crb_addr_2M(adapter, offset, &addr));
 868
 869         return addr;
 870 }
 871
 872
 873 static int
 874 qlcnic_pci_set_window_2M(struct qlcnic_adapter *adapter,
 875                 u64 addr, u32 *start)
 876 {
 877         u32 window;
 878         struct pci_dev *pdev = adapter->pdev;
 879
 880         if ((addr & 0x00ff800) == 0xff800) {
 881                 if (printk_ratelimit())
 882                         dev_warn(&pdev->dev, "QM access not handled\n");
 883                 return -EIO;
 884         }
 885
 886         window = OCM_WIN_P3P(addr);
 887
 888         writel(window, adapter->ahw.ocm_win_crb);
 889         /* read back to flush */
 890         readl(adapter->ahw.ocm_win_crb);
 891
 892         adapter->ahw.ocm_win = window;
 893         *start = QLCNIC_PCI_OCM0_2M + GET_MEM_OFFS_2M(addr);
 894         return 0;
 895 }
 896
 897 static int
 898 qlcnic_pci_mem_access_direct(struct qlcnic_adapter *adapter, u64 off,
 899                 u64 *data, int op)
 900 {
 901         void __iomem *addr, *mem_ptr = NULL;
 902         resource_size_t mem_base;
 903         int ret;
 904         u32 start;
 905
 906         mutex_lock(&adapter->ahw.mem_lock);
 907
 908         ret = qlcnic_pci_set_window_2M(adapter, off, &start);
 909         if (ret != 0)
 910                 goto unlock;
 911
 912         addr = pci_base_offset(adapter, start);
 913         if (addr)
 914                 goto noremap;
 915
 916         mem_base = pci_resource_start(adapter->pdev, 0) + (start & PAGE_MASK);
 917
 918         mem_ptr = ioremap(mem_base, PAGE_SIZE);
 919         if (mem_ptr == NULL) {
 920                 ret = -EIO;
 921                 goto unlock;
 922         }
 923
 924         addr = mem_ptr + (start & (PAGE_SIZE - 1));
 925
 926 noremap:
 927         if (op == 0)    /* read */
 928                 *data = readq(addr);
 929         else            /* write */
 930                 writeq(*data, addr);
 931
 932 unlock:
 933         mutex_unlock(&adapter->ahw.mem_lock);
 934
 935         if (mem_ptr)
 936                 iounmap(mem_ptr);
 937         return ret;
 938 }
 939
 940 #define MAX_CTL_CHECK   1000
 941
 942 int
 943 qlcnic_pci_mem_write_2M(struct qlcnic_adapter *adapter,
 944                 u64 off, u64 data)
 945 {
 946         int i, j, ret;
 947         u32 temp, off8;
 948         u64 stride;
 949         void __iomem *mem_crb;
 950
 951         /* Only 64-bit aligned access */
 952         if (off & 7)
 953                 return -EIO;
 954
 955         /* P3 onward, test agent base for MIU and SIU is same */
 956         if (ADDR_IN_RANGE(off, QLCNIC_ADDR_QDR_NET,
 957                                 QLCNIC_ADDR_QDR_NET_MAX_P3)) {
 958                 mem_crb = qlcnic_get_ioaddr(adapter,
 959                                 QLCNIC_CRB_QDR_NET+MIU_TEST_AGT_BASE);
 960                 goto correct;
 961         }
 962
 963         if (ADDR_IN_RANGE(off, QLCNIC_ADDR_DDR_NET, QLCNIC_ADDR_DDR_NET_MAX)) {
 964                 mem_crb = qlcnic_get_ioaddr(adapter,
 965                                 QLCNIC_CRB_DDR_NET+MIU_TEST_AGT_BASE);
 966                 goto correct;
 967         }
 968
 969         if (ADDR_IN_RANGE(off, QLCNIC_ADDR_OCM0, QLCNIC_ADDR_OCM0_MAX))
 970                 return qlcnic_pci_mem_access_direct(adapter, off, &data, 1);
 971
 972         return -EIO;
 973
 974 correct:
 975         stride = QLCNIC_IS_REVISION_P3P(adapter->ahw.revision_id) ? 16 : 8;
 976
 977         off8 = off & ~(stride-1);
 978
 979         mutex_lock(&adapter->ahw.mem_lock);
 980
 981         writel(off8, (mem_crb + MIU_TEST_AGT_ADDR_LO));
 982         writel(0, (mem_crb + MIU_TEST_AGT_ADDR_HI));
 983
 984         i = 0;
 985         if (stride == 16) {
 986                 writel(TA_CTL_ENABLE, (mem_crb + TEST_AGT_CTRL));
 987                 writel((TA_CTL_START | TA_CTL_ENABLE),
 988                                 (mem_crb + TEST_AGT_CTRL));
 989
 990                 for (j = 0; j < MAX_CTL_CHECK; j++) {
 991                         temp = readl(mem_crb + TEST_AGT_CTRL);
 992                         if ((temp & TA_CTL_BUSY) == 0)
 993                                 break;
 994                 }
 995
 996                 if (j >= MAX_CTL_CHECK) {
 997                         ret = -EIO;
 998                         goto done;
 999                 }
1000
1001                 i = (off & 0xf) ? 0 : 2;
1002                 writel(readl(mem_crb + MIU_TEST_AGT_RDDATA(i)),
1003                                 mem_crb + MIU_TEST_AGT_WRDATA(i));
1004                 writel(readl(mem_crb + MIU_TEST_AGT_RDDATA(i+1)),
1005                                 mem_crb + MIU_TEST_AGT_WRDATA(i+1));
1006                 i = (off & 0xf) ? 2 : 0;
1007         }
1008
1009         writel(data & 0xffffffff,
1010                         mem_crb + MIU_TEST_AGT_WRDATA(i));
1011         writel((data >> 32) & 0xffffffff,
1012                         mem_crb + MIU_TEST_AGT_WRDATA(i+1));
1013
1014         writel((TA_CTL_ENABLE | TA_CTL_WRITE), (mem_crb + TEST_AGT_CTRL));
1015         writel((TA_CTL_START | TA_CTL_ENABLE | TA_CTL_WRITE),
1016                         (mem_crb + TEST_AGT_CTRL));
1017
1018         for (j = 0; j < MAX_CTL_CHECK; j++) {
1019                 temp = readl(mem_crb + TEST_AGT_CTRL);
1020                 if ((temp & TA_CTL_BUSY) == 0)
1021                         break;
1022         }
1023
1024         if (j >= MAX_CTL_CHECK) {
1025                 if (printk_ratelimit())
1026                         dev_err(&adapter->pdev->dev,
1027                                         "failed to write through agent\n");
1028                 ret = -EIO;
1029         } else
1030                 ret = 0;
1031
1032 done:
1033         mutex_unlock(&adapter->ahw.mem_lock);
1034
1035         return ret;
1036 }
1037
1038 int
1039 qlcnic_pci_mem_read_2M(struct qlcnic_adapter *adapter,
1040                 u64 off, u64 *data)
1041 {
1042         int j, ret;
1043         u32 temp, off8;
1044         u64 val, stride;
1045         void __iomem *mem_crb;
1046
1047         /* Only 64-bit aligned access */
1048         if (off & 7)
1049                 return -EIO;
1050
1051         /* P3 onward, test agent base for MIU and SIU is same */
1052         if (ADDR_IN_RANGE(off, QLCNIC_ADDR_QDR_NET,
1053                                 QLCNIC_ADDR_QDR_NET_MAX_P3)) {
1054                 mem_crb = qlcnic_get_ioaddr(adapter,
1055                                 QLCNIC_CRB_QDR_NET+MIU_TEST_AGT_BASE);
1056                 goto correct;
1057         }
1058
1059         if (ADDR_IN_RANGE(off, QLCNIC_ADDR_DDR_NET, QLCNIC_ADDR_DDR_NET_MAX)) {
1060                 mem_crb = qlcnic_get_ioaddr(adapter,
1061                                 QLCNIC_CRB_DDR_NET+MIU_TEST_AGT_BASE);
1062                 goto correct;
1063         }
1064
1065         if (ADDR_IN_RANGE(off, QLCNIC_ADDR_OCM0, QLCNIC_ADDR_OCM0_MAX)) {
1066                 return qlcnic_pci_mem_access_direct(adapter,
1067                                 off, data, 0);
1068         }
1069
1070         return -EIO;
1071
1072 correct:
1073         stride = QLCNIC_IS_REVISION_P3P(adapter->ahw.revision_id) ? 16 : 8;
1074
1075         off8 = off & ~(stride-1);
1076
1077         mutex_lock(&adapter->ahw.mem_lock);
1078
1079         writel(off8, (mem_crb + MIU_TEST_AGT_ADDR_LO));
1080         writel(0, (mem_crb + MIU_TEST_AGT_ADDR_HI));
1081         writel(TA_CTL_ENABLE, (mem_crb + TEST_AGT_CTRL));
1082         writel((TA_CTL_START | TA_CTL_ENABLE), (mem_crb + TEST_AGT_CTRL));
1083
1084         for (j = 0; j < MAX_CTL_CHECK; j++) {
1085                 temp = readl(mem_crb + TEST_AGT_CTRL);
1086                 if ((temp & TA_CTL_BUSY) == 0)
1087                         break;
1088         }
1089
1090         if (j >= MAX_CTL_CHECK) {
1091                 if (printk_ratelimit())
1092                         dev_err(&adapter->pdev->dev,
1093                                         "failed to read through agent\n");
1094                 ret = -EIO;
1095         } else {
1096                 off8 = MIU_TEST_AGT_RDDATA_LO;
1097                 if ((stride == 16) && (off & 0xf))
1098                         off8 = MIU_TEST_AGT_RDDATA_UPPER_LO;
1099
1100                 temp = readl(mem_crb + off8 + 4);
1101                 val = (u64)temp << 32;
1102                 val |= readl(mem_crb + off8);
1103                 *data = val;
1104                 ret = 0;
1105         }
1106
1107         mutex_unlock(&adapter->ahw.mem_lock);
1108
1109         return ret;
1110 }
1111
1112 int qlcnic_get_board_info(struct qlcnic_adapter *adapter)
1113 {
1114         int offset, board_type, magic;
1115         struct pci_dev *pdev = adapter->pdev;
1116
1117         offset = QLCNIC_FW_MAGIC_OFFSET;
1118         if (qlcnic_rom_fast_read(adapter, offset, &magic))
1119                 return -EIO;
1120
1121         if (magic != QLCNIC_BDINFO_MAGIC) {
1122                 dev_err(&pdev->dev, "invalid board config, magic=%08x\n",
1123                         magic);
1124                 return -EIO;
1125         }
1126
1127         offset = QLCNIC_BRDTYPE_OFFSET;
1128         if (qlcnic_rom_fast_read(adapter, offset, &board_type))
1129                 return -EIO;
1130
1131         adapter->ahw.board_type = board_type;
1132
1133         if (board_type == QLCNIC_BRDTYPE_P3_4_GB_MM) {
1134                 u32 gpio = QLCRD32(adapter, QLCNIC_ROMUSB_GLB_PAD_GPIO_I);
1135                 if ((gpio & 0x8000) == 0)
1136                         board_type = QLCNIC_BRDTYPE_P3_10G_TP;
1137         }
1138
1139         switch (board_type) {
1140         case QLCNIC_BRDTYPE_P3_HMEZ:
1141         case QLCNIC_BRDTYPE_P3_XG_LOM:
1142         case QLCNIC_BRDTYPE_P3_10G_CX4:
1143         case QLCNIC_BRDTYPE_P3_10G_CX4_LP:
1144         case QLCNIC_BRDTYPE_P3_IMEZ:
1145         case QLCNIC_BRDTYPE_P3_10G_SFP_PLUS:
1146         case QLCNIC_BRDTYPE_P3_10G_SFP_CT:
1147         case QLCNIC_BRDTYPE_P3_10G_SFP_QT:
1148         case QLCNIC_BRDTYPE_P3_10G_XFP:
1149         case QLCNIC_BRDTYPE_P3_10000_BASE_T:
1150                 adapter->ahw.port_type = QLCNIC_XGBE;
1151                 break;
1152         case QLCNIC_BRDTYPE_P3_REF_QG:
1153         case QLCNIC_BRDTYPE_P3_4_GB:
1154         case QLCNIC_BRDTYPE_P3_4_GB_MM:
1155                 adapter->ahw.port_type = QLCNIC_GBE;
1156                 break;
1157         case QLCNIC_BRDTYPE_P3_10G_TP:
1158                 adapter->ahw.port_type = (adapter->portnum < 2) ?
1159                         QLCNIC_XGBE : QLCNIC_GBE;
1160                 break;
1161         default:
1162                 dev_err(&pdev->dev, "unknown board type %x\n", board_type);
1163                 adapter->ahw.port_type = QLCNIC_XGBE;
1164                 break;
1165         }
1166
1167         return 0;
1168 }
1169
1170 int
1171 qlcnic_wol_supported(struct qlcnic_adapter *adapter)
1172 {
1173         u32 wol_cfg;
1174
1175         wol_cfg = QLCRD32(adapter, QLCNIC_WOL_CONFIG_NV);
1176         if (wol_cfg & (1UL << adapter->portnum)) {
1177                 wol_cfg = QLCRD32(adapter, QLCNIC_WOL_CONFIG);
1178                 if (wol_cfg & (1 << adapter->portnum))
1179                         return 1;
1180         }
1181
1182         return 0;
1183 }
1184
1185 int qlcnic_config_led(struct qlcnic_adapter *adapter, u32 state, u32 rate)
1186 {
1187         struct qlcnic_nic_req   req;
1188         int rv;
1189         u64 word;
1190
1191         memset(&req, 0, sizeof(struct qlcnic_nic_req));
1192         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
1193
1194         word = QLCNIC_H2C_OPCODE_CONFIG_LED | ((u64)adapter->portnum << 16);
1195         req.req_hdr = cpu_to_le64(word);
1196
1197         req.words[0] = cpu_to_le64((u64)rate << 32);
1198         req.words[1] = cpu_to_le64(state);
1199
1200         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
1201         if (rv)
1202                 dev_err(&adapter->pdev->dev, "LED configuration failed.\n");
1203
1204         return rv;
1205 }
1206
1207 static int qlcnic_set_fw_loopback(struct qlcnic_adapter *adapter, u32 flag)
1208 {
1209         struct qlcnic_nic_req   req;
1210         int                     rv;
1211         u64                     word;
1212
1213         memset(&req, 0, sizeof(struct qlcnic_nic_req));
1214         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
1215
1216         word = QLCNIC_H2C_OPCODE_CONFIG_LOOPBACK |
1217                         ((u64)adapter->portnum << 16);
1218         req.req_hdr = cpu_to_le64(word);
1219         req.words[0] = cpu_to_le64(flag);
1220
1221         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
1222         if (rv)
1223                 dev_err(&adapter->pdev->dev,
1224                         "%sting loopback mode failed.\n",
1225                                         flag ? "Set" : "Reset");
1226         return rv;
1227 }
1228
1229 int qlcnic_set_ilb_mode(struct qlcnic_adapter *adapter)
1230 {
1231         if (qlcnic_set_fw_loopback(adapter, 1))
1232                 return -EIO;
1233
1234         if (qlcnic_nic_set_promisc(adapter,
1235                                 VPORT_MISS_MODE_ACCEPT_ALL)) {
1236                 qlcnic_set_fw_loopback(adapter, 0);
1237                 return -EIO;
1238         }
1239
1240         msleep(1000);
1241         return 0;
1242 }
1243
1244 void qlcnic_clear_ilb_mode(struct qlcnic_adapter *adapter)
1245 {
1246         int mode = VPORT_MISS_MODE_DROP;
1247         struct net_device *netdev = adapter->netdev;
1248
1249         qlcnic_set_fw_loopback(adapter, 0);
1250
1251         if (netdev->flags & IFF_PROMISC)
1252                 mode = VPORT_MISS_MODE_ACCEPT_ALL;
1253         else if (netdev->flags & IFF_ALLMULTI)
1254                 mode = VPORT_MISS_MODE_ACCEPT_MULTI;
1255
1256         qlcnic_nic_set_promisc(adapter, mode);
1257 }