SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/net/niu.c

   1 /* niu.c: Neptune ethernet driver.
   2  *
   3  * Copyright (C) 2007, 2008 David S. Miller (davem@davemloft.net)
   4  */
   5
   6 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
   7
   8 #include <linux/module.h>
   9 #include <linux/init.h>
  10 #include <linux/pci.h>
  11 #include <linux/dma-mapping.h>
  12 #include <linux/netdevice.h>
  13 #include <linux/ethtool.h>
  14 #include <linux/etherdevice.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/delay.h>
  17 #include <linux/bitops.h>
  18 #include <linux/mii.h>
  19 #include <linux/if_ether.h>
  20 #include <linux/if_vlan.h>
  21 #include <linux/ip.h>
  22 #include <linux/in.h>
  23 #include <linux/ipv6.h>
  24 #include <linux/log2.h>
  25 #include <linux/jiffies.h>
  26 #include <linux/crc32.h>
  27 #include <linux/list.h>
  28
  29 #include <linux/io.h>
  30
  31 #ifdef CONFIG_SPARC64
  32 #include <linux/of_device.h>
  33 #endif
  34
  35 #include "niu.h"
  36
  37 #define DRV_MODULE_NAME         "niu"
  38 #define DRV_MODULE_VERSION      "1.0"
  39 #define DRV_MODULE_RELDATE      "Nov 14, 2008"
  40
  41 static char version[] __devinitdata =
  42         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
  43
  44 MODULE_AUTHOR("David S. Miller (davem@davemloft.net)");
  45 MODULE_DESCRIPTION("NIU ethernet driver");
  46 MODULE_LICENSE("GPL");
  47 MODULE_VERSION(DRV_MODULE_VERSION);
  48
  49 #ifndef readq
  50 static u64 readq(void __iomem *reg)
  51 {
  52         return ((u64) readl(reg)) | (((u64) readl(reg + 4UL)) << 32);
  53 }
  54
  55 static void writeq(u64 val, void __iomem *reg)
  56 {
  57         writel(val & 0xffffffff, reg);
  58         writel(val >> 32, reg + 0x4UL);
  59 }
  60 #endif
  61
  62 static DEFINE_PCI_DEVICE_TABLE(niu_pci_tbl) = {
  63         {PCI_DEVICE(PCI_VENDOR_ID_SUN, 0xabcd)},
  64         {}
  65 };
  66
  67 MODULE_DEVICE_TABLE(pci, niu_pci_tbl);
  68
  69 #define NIU_TX_TIMEOUT                  (5 * HZ)
  70
  71 #define nr64(reg)               readq(np->regs + (reg))
  72 #define nw64(reg, val)          writeq((val), np->regs + (reg))
  73
  74 #define nr64_mac(reg)           readq(np->mac_regs + (reg))
  75 #define nw64_mac(reg, val)      writeq((val), np->mac_regs + (reg))
  76
  77 #define nr64_ipp(reg)           readq(np->regs + np->ipp_off + (reg))
  78 #define nw64_ipp(reg, val)      writeq((val), np->regs + np->ipp_off + (reg))
  79
  80 #define nr64_pcs(reg)           readq(np->regs + np->pcs_off + (reg))
  81 #define nw64_pcs(reg, val)      writeq((val), np->regs + np->pcs_off + (reg))
  82
  83 #define nr64_xpcs(reg)          readq(np->regs + np->xpcs_off + (reg))
  84 #define nw64_xpcs(reg, val)     writeq((val), np->regs + np->xpcs_off + (reg))
  85
  86 #define NIU_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
  87
  88 static int niu_debug;
  89 static int debug = -1;
  90 module_param(debug, int, 0);
  91 MODULE_PARM_DESC(debug, "NIU debug level");
  92
  93 #define niu_lock_parent(np, flags) \
  94         spin_lock_irqsave(&np->parent->lock, flags)
  95 #define niu_unlock_parent(np, flags) \
  96         spin_unlock_irqrestore(&np->parent->lock, flags)
  97
  98 static int serdes_init_10g_serdes(struct niu *np);
  99
 100 static int __niu_wait_bits_clear_mac(struct niu *np, unsigned long reg,
 101                                      u64 bits, int limit, int delay)
 102 {
 103         while (--limit >= 0) {
 104                 u64 val = nr64_mac(reg);
 105
 106                 if (!(val & bits))
 107                         break;
 108                 udelay(delay);
 109         }
 110         if (limit < 0)
 111                 return -ENODEV;
 112         return 0;
 113 }
 114
 115 static int __niu_set_and_wait_clear_mac(struct niu *np, unsigned long reg,
 116                                         u64 bits, int limit, int delay,
 117                                         const char *reg_name)
 118 {
 119         int err;
 120
 121         nw64_mac(reg, bits);
 122         err = __niu_wait_bits_clear_mac(np, reg, bits, limit, delay);
 123         if (err)
 124                 netdev_err(np->dev, "bits (%llx) of register %s would not clear, val[%llx]\n",
 125                            (unsigned long long)bits, reg_name,
 126                            (unsigned long long)nr64_mac(reg));
 127         return err;
 128 }
 129
 130 #define niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
 131 ({      BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
 132         __niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
 133 })
 134
 135 static int __niu_wait_bits_clear_ipp(struct niu *np, unsigned long reg,
 136                                      u64 bits, int limit, int delay)
 137 {
 138         while (--limit >= 0) {
 139                 u64 val = nr64_ipp(reg);
 140
 141                 if (!(val & bits))
 142                         break;
 143                 udelay(delay);
 144         }
 145         if (limit < 0)
 146                 return -ENODEV;
 147         return 0;
 148 }
 149
 150 static int __niu_set_and_wait_clear_ipp(struct niu *np, unsigned long reg,
 151                                         u64 bits, int limit, int delay,
 152                                         const char *reg_name)
 153 {
 154         int err;
 155         u64 val;
 156
 157         val = nr64_ipp(reg);
 158         val |= bits;
 159         nw64_ipp(reg, val);
 160
 161         err = __niu_wait_bits_clear_ipp(np, reg, bits, limit, delay);
 162         if (err)
 163                 netdev_err(np->dev, "bits (%llx) of register %s would not clear, val[%llx]\n",
 164                            (unsigned long long)bits, reg_name,
 165                            (unsigned long long)nr64_ipp(reg));
 166         return err;
 167 }
 168
 169 #define niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
 170 ({      BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
 171         __niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
 172 })
 173
 174 static int __niu_wait_bits_clear(struct niu *np, unsigned long reg,
 175                                  u64 bits, int limit, int delay)
 176 {
 177         while (--limit >= 0) {
 178                 u64 val = nr64(reg);
 179
 180                 if (!(val & bits))
 181                         break;
 182                 udelay(delay);
 183         }
 184         if (limit < 0)
 185                 return -ENODEV;
 186         return 0;
 187 }
 188
 189 #define niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY) \
 190 ({      BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
 191         __niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY); \
 192 })
 193
 194 static int __niu_set_and_wait_clear(struct niu *np, unsigned long reg,
 195                                     u64 bits, int limit, int delay,
 196                                     const char *reg_name)
 197 {
 198         int err;
 199
 200         nw64(reg, bits);
 201         err = __niu_wait_bits_clear(np, reg, bits, limit, delay);
 202         if (err)
 203                 netdev_err(np->dev, "bits (%llx) of register %s would not clear, val[%llx]\n",
 204                            (unsigned long long)bits, reg_name,
 205                            (unsigned long long)nr64(reg));
 206         return err;
 207 }
 208
 209 #define niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
 210 ({      BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
 211         __niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
 212 })
 213
 214 static void niu_ldg_rearm(struct niu *np, struct niu_ldg *lp, int on)
 215 {
 216         u64 val = (u64) lp->timer;
 217
 218         if (on)
 219                 val |= LDG_IMGMT_ARM;
 220
 221         nw64(LDG_IMGMT(lp->ldg_num), val);
 222 }
 223
 224 static int niu_ldn_irq_enable(struct niu *np, int ldn, int on)
 225 {
 226         unsigned long mask_reg, bits;
 227         u64 val;
 228
 229         if (ldn < 0 || ldn > LDN_MAX)
 230                 return -EINVAL;
 231
 232         if (ldn < 64) {
 233                 mask_reg = LD_IM0(ldn);
 234                 bits = LD_IM0_MASK;
 235         } else {
 236                 mask_reg = LD_IM1(ldn - 64);
 237                 bits = LD_IM1_MASK;
 238         }
 239
 240         val = nr64(mask_reg);
 241         if (on)
 242                 val &= ~bits;
 243         else
 244                 val |= bits;
 245         nw64(mask_reg, val);
 246
 247         return 0;
 248 }
 249
 250 static int niu_enable_ldn_in_ldg(struct niu *np, struct niu_ldg *lp, int on)
 251 {
 252         struct niu_parent *parent = np->parent;
 253         int i;
 254
 255         for (i = 0; i <= LDN_MAX; i++) {
 256                 int err;
 257
 258                 if (parent->ldg_map[i] != lp->ldg_num)
 259                         continue;
 260
 261                 err = niu_ldn_irq_enable(np, i, on);
 262                 if (err)
 263                         return err;
 264         }
 265         return 0;
 266 }
 267
 268 static int niu_enable_interrupts(struct niu *np, int on)
 269 {
 270         int i;
 271
 272         for (i = 0; i < np->num_ldg; i++) {
 273                 struct niu_ldg *lp = &np->ldg[i];
 274                 int err;
 275
 276                 err = niu_enable_ldn_in_ldg(np, lp, on);
 277                 if (err)
 278                         return err;
 279         }
 280         for (i = 0; i < np->num_ldg; i++)
 281                 niu_ldg_rearm(np, &np->ldg[i], on);
 282
 283         return 0;
 284 }
 285
 286 static u32 phy_encode(u32 type, int port)
 287 {
 288         return (type << (port * 2));
 289 }
 290
 291 static u32 phy_decode(u32 val, int port)
 292 {
 293         return (val >> (port * 2)) & PORT_TYPE_MASK;
 294 }
 295
 296 static int mdio_wait(struct niu *np)
 297 {
 298         int limit = 1000;
 299         u64 val;
 300
 301         while (--limit > 0) {
 302                 val = nr64(MIF_FRAME_OUTPUT);
 303                 if ((val >> MIF_FRAME_OUTPUT_TA_SHIFT) & 0x1)
 304                         return val & MIF_FRAME_OUTPUT_DATA;
 305
 306                 udelay(10);
 307         }
 308
 309         return -ENODEV;
 310 }
 311
 312 static int mdio_read(struct niu *np, int port, int dev, int reg)
 313 {
 314         int err;
 315
 316         nw64(MIF_FRAME_OUTPUT, MDIO_ADDR_OP(port, dev, reg));
 317         err = mdio_wait(np);
 318         if (err < 0)
 319                 return err;
 320
 321         nw64(MIF_FRAME_OUTPUT, MDIO_READ_OP(port, dev));
 322         return mdio_wait(np);
 323 }
 324
 325 static int mdio_write(struct niu *np, int port, int dev, int reg, int data)
 326 {
 327         int err;
 328
 329         nw64(MIF_FRAME_OUTPUT, MDIO_ADDR_OP(port, dev, reg));
 330         err = mdio_wait(np);
 331         if (err < 0)
 332                 return err;
 333
 334         nw64(MIF_FRAME_OUTPUT, MDIO_WRITE_OP(port, dev, data));
 335         err = mdio_wait(np);
 336         if (err < 0)
 337                 return err;
 338
 339         return 0;
 340 }
 341
 342 static int mii_read(struct niu *np, int port, int reg)
 343 {
 344         nw64(MIF_FRAME_OUTPUT, MII_READ_OP(port, reg));
 345         return mdio_wait(np);
 346 }
 347
 348 static int mii_write(struct niu *np, int port, int reg, int data)
 349 {
 350         int err;
 351
 352         nw64(MIF_FRAME_OUTPUT, MII_WRITE_OP(port, reg, data));
 353         err = mdio_wait(np);
 354         if (err < 0)
 355                 return err;
 356
 357         return 0;
 358 }
 359
 360 static int esr2_set_tx_cfg(struct niu *np, unsigned long channel, u32 val)
 361 {
 362         int err;
 363
 364         err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
 365                          ESR2_TI_PLL_TX_CFG_L(channel),
 366                          val & 0xffff);
 367         if (!err)
 368                 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
 369                                  ESR2_TI_PLL_TX_CFG_H(channel),
 370                                  val >> 16);
 371         return err;
 372 }
 373
 374 static int esr2_set_rx_cfg(struct niu *np, unsigned long channel, u32 val)
 375 {
 376         int err;
 377
 378         err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
 379                          ESR2_TI_PLL_RX_CFG_L(channel),
 380                          val & 0xffff);
 381         if (!err)
 382                 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
 383                                  ESR2_TI_PLL_RX_CFG_H(channel),
 384                                  val >> 16);
 385         return err;
 386 }
 387
 388 /* Mode is always 10G fiber.  */
 389 static int serdes_init_niu_10g_fiber(struct niu *np)
 390 {
 391         struct niu_link_config *lp = &np->link_config;
 392         u32 tx_cfg, rx_cfg;
 393         unsigned long i;
 394
 395         tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV);
 396         rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT |
 397                   PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH |
 398                   PLL_RX_CFG_EQ_LP_ADAPTIVE);
 399
 400         if (lp->loopback_mode == LOOPBACK_PHY) {
 401                 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS;
 402
 403                 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
 404                            ESR2_TI_PLL_TEST_CFG_L, test_cfg);
 405
 406                 tx_cfg |= PLL_TX_CFG_ENTEST;
 407                 rx_cfg |= PLL_RX_CFG_ENTEST;
 408         }
 409
 410         /* Initialize all 4 lanes of the SERDES.  */
 411         for (i = 0; i < 4; i++) {
 412                 int err = esr2_set_tx_cfg(np, i, tx_cfg);
 413                 if (err)
 414                         return err;
 415         }
 416
 417         for (i = 0; i < 4; i++) {
 418                 int err = esr2_set_rx_cfg(np, i, rx_cfg);
 419                 if (err)
 420                         return err;
 421         }
 422
 423         return 0;
 424 }
 425
 426 static int serdes_init_niu_1g_serdes(struct niu *np)
 427 {
 428         struct niu_link_config *lp = &np->link_config;
 429         u16 pll_cfg, pll_sts;
 430         int max_retry = 100;
 431         u64 uninitialized_var(sig), mask, val;
 432         u32 tx_cfg, rx_cfg;
 433         unsigned long i;
 434         int err;
 435
 436         tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV |
 437                   PLL_TX_CFG_RATE_HALF);
 438         rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT |
 439                   PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH |
 440                   PLL_RX_CFG_RATE_HALF);
 441
 442         if (np->port == 0)
 443                 rx_cfg |= PLL_RX_CFG_EQ_LP_ADAPTIVE;
 444
 445         if (lp->loopback_mode == LOOPBACK_PHY) {
 446                 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS;
 447
 448                 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
 449                            ESR2_TI_PLL_TEST_CFG_L, test_cfg);
 450
 451                 tx_cfg |= PLL_TX_CFG_ENTEST;
 452                 rx_cfg |= PLL_RX_CFG_ENTEST;
 453         }
 454
 455         /* Initialize PLL for 1G */
 456         pll_cfg = (PLL_CFG_ENPLL | PLL_CFG_MPY_8X);
 457
 458         err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
 459                          ESR2_TI_PLL_CFG_L, pll_cfg);
 460         if (err) {
 461                 netdev_err(np->dev, "NIU Port %d %s() mdio write to ESR2_TI_PLL_CFG_L failed\n",
 462                            np->port, __func__);
 463                 return err;
 464         }
 465
 466         pll_sts = PLL_CFG_ENPLL;
 467
 468         err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
 469                          ESR2_TI_PLL_STS_L, pll_sts);
 470         if (err) {
 471                 netdev_err(np->dev, "NIU Port %d %s() mdio write to ESR2_TI_PLL_STS_L failed\n",
 472                            np->port, __func__);
 473                 return err;
 474         }
 475
 476         udelay(200);
 477
 478         /* Initialize all 4 lanes of the SERDES.  */
 479         for (i = 0; i < 4; i++) {
 480                 err = esr2_set_tx_cfg(np, i, tx_cfg);
 481                 if (err)
 482                         return err;
 483         }
 484
 485         for (i = 0; i < 4; i++) {
 486                 err = esr2_set_rx_cfg(np, i, rx_cfg);
 487                 if (err)
 488                         return err;
 489         }
 490
 491         switch (np->port) {
 492         case 0:
 493                 val = (ESR_INT_SRDY0_P0 | ESR_INT_DET0_P0);
 494                 mask = val;
 495                 break;
 496
 497         case 1:
 498                 val = (ESR_INT_SRDY0_P1 | ESR_INT_DET0_P1);
 499                 mask = val;
 500                 break;
 501
 502         default:
 503                 return -EINVAL;
 504         }
 505
 506         while (max_retry--) {
 507                 sig = nr64(ESR_INT_SIGNALS);
 508                 if ((sig & mask) == val)
 509                         break;
 510
 511                 mdelay(500);
 512         }
 513
 514         if ((sig & mask) != val) {
 515                 netdev_err(np->dev, "Port %u signal bits [%08x] are not [%08x]\n",
 516                            np->port, (int)(sig & mask), (int)val);
 517                 return -ENODEV;
 518         }
 519
 520         return 0;
 521 }
 522
 523 static int serdes_init_niu_10g_serdes(struct niu *np)
 524 {
 525         struct niu_link_config *lp = &np->link_config;
 526         u32 tx_cfg, rx_cfg, pll_cfg, pll_sts;
 527         int max_retry = 100;
 528         u64 uninitialized_var(sig), mask, val;
 529         unsigned long i;
 530         int err;
 531
 532         tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV);
 533         rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT |
 534                   PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH |
 535                   PLL_RX_CFG_EQ_LP_ADAPTIVE);
 536
 537         if (lp->loopback_mode == LOOPBACK_PHY) {
 538                 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS;
 539
 540                 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
 541                            ESR2_TI_PLL_TEST_CFG_L, test_cfg);
 542
 543                 tx_cfg |= PLL_TX_CFG_ENTEST;
 544                 rx_cfg |= PLL_RX_CFG_ENTEST;
 545         }
 546
 547         /* Initialize PLL for 10G */
 548         pll_cfg = (PLL_CFG_ENPLL | PLL_CFG_MPY_10X);
 549
 550         err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
 551                          ESR2_TI_PLL_CFG_L, pll_cfg & 0xffff);
 552         if (err) {
 553                 netdev_err(np->dev, "NIU Port %d %s() mdio write to ESR2_TI_PLL_CFG_L failed\n",
 554                            np->port, __func__);
 555                 return err;
 556         }
 557
 558         pll_sts = PLL_CFG_ENPLL;
 559
 560         err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
 561                          ESR2_TI_PLL_STS_L, pll_sts & 0xffff);
 562         if (err) {
 563                 netdev_err(np->dev, "NIU Port %d %s() mdio write to ESR2_TI_PLL_STS_L failed\n",
 564                            np->port, __func__);
 565                 return err;
 566         }
 567
 568         udelay(200);
 569
 570         /* Initialize all 4 lanes of the SERDES.  */
 571         for (i = 0; i < 4; i++) {
 572                 err = esr2_set_tx_cfg(np, i, tx_cfg);
 573                 if (err)
 574                         return err;
 575         }
 576
 577         for (i = 0; i < 4; i++) {
 578                 err = esr2_set_rx_cfg(np, i, rx_cfg);
 579                 if (err)
 580                         return err;
 581         }
 582
 583         /* check if serdes is ready */
 584
 585         switch (np->port) {
 586         case 0:
 587                 mask = ESR_INT_SIGNALS_P0_BITS;
 588                 val = (ESR_INT_SRDY0_P0 |
 589                        ESR_INT_DET0_P0 |
 590                        ESR_INT_XSRDY_P0 |
 591                        ESR_INT_XDP_P0_CH3 |
 592                        ESR_INT_XDP_P0_CH2 |
 593                        ESR_INT_XDP_P0_CH1 |
 594                        ESR_INT_XDP_P0_CH0);
 595                 break;
 596
 597         case 1:
 598                 mask = ESR_INT_SIGNALS_P1_BITS;
 599                 val = (ESR_INT_SRDY0_P1 |
 600                        ESR_INT_DET0_P1 |
 601                        ESR_INT_XSRDY_P1 |
 602                        ESR_INT_XDP_P1_CH3 |
 603                        ESR_INT_XDP_P1_CH2 |
 604                        ESR_INT_XDP_P1_CH1 |
 605                        ESR_INT_XDP_P1_CH0);
 606                 break;
 607
 608         default:
 609                 return -EINVAL;
 610         }
 611
 612         while (max_retry--) {
 613                 sig = nr64(ESR_INT_SIGNALS);
 614                 if ((sig & mask) == val)
 615                         break;
 616
 617                 mdelay(500);
 618         }
 619
 620         if ((sig & mask) != val) {
 621                 pr_info("NIU Port %u signal bits [%08x] are not [%08x] for 10G...trying 1G\n",
 622                         np->port, (int)(sig & mask), (int)val);
 623
 624                 /* 10G failed, try initializing at 1G */
 625                 err = serdes_init_niu_1g_serdes(np);
 626                 if (!err) {
 627                         np->flags &= ~NIU_FLAGS_10G;
 628                         np->mac_xcvr = MAC_XCVR_PCS;
 629                 }  else {
 630                         netdev_err(np->dev, "Port %u 10G/1G SERDES Link Failed\n",
 631                                    np->port);
 632                         return -ENODEV;
 633                 }
 634         }
 635         return 0;
 636 }
 637
 638 static int esr_read_rxtx_ctrl(struct niu *np, unsigned long chan, u32 *val)
 639 {
 640         int err;
 641
 642         err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR, ESR_RXTX_CTRL_L(chan));
 643         if (err >= 0) {
 644                 *val = (err & 0xffff);
 645                 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
 646                                 ESR_RXTX_CTRL_H(chan));
 647                 if (err >= 0)
 648                         *val |= ((err & 0xffff) << 16);
 649                 err = 0;
 650         }
 651         return err;
 652 }
 653
 654 static int esr_read_glue0(struct niu *np, unsigned long chan, u32 *val)
 655 {
 656         int err;
 657
 658         err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
 659                         ESR_GLUE_CTRL0_L(chan));
 660         if (err >= 0) {
 661                 *val = (err & 0xffff);
 662                 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
 663                                 ESR_GLUE_CTRL0_H(chan));
 664                 if (err >= 0) {
 665                         *val |= ((err & 0xffff) << 16);
 666                         err = 0;
 667                 }
 668         }
 669         return err;
 670 }
 671
 672 static int esr_read_reset(struct niu *np, u32 *val)
 673 {
 674         int err;
 675
 676         err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
 677                         ESR_RXTX_RESET_CTRL_L);
 678         if (err >= 0) {
 679                 *val = (err & 0xffff);
 680                 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
 681                                 ESR_RXTX_RESET_CTRL_H);
 682                 if (err >= 0) {
 683                         *val |= ((err & 0xffff) << 16);
 684                         err = 0;
 685                 }
 686         }
 687         return err;
 688 }
 689
 690 static int esr_write_rxtx_ctrl(struct niu *np, unsigned long chan, u32 val)
 691 {
 692         int err;
 693
 694         err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
 695                          ESR_RXTX_CTRL_L(chan), val & 0xffff);
 696         if (!err)
 697                 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
 698                                  ESR_RXTX_CTRL_H(chan), (val >> 16));
 699         return err;
 700 }
 701
 702 static int esr_write_glue0(struct niu *np, unsigned long chan, u32 val)
 703 {
 704         int err;
 705
 706         err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
 707                         ESR_GLUE_CTRL0_L(chan), val & 0xffff);
 708         if (!err)
 709                 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
 710                                  ESR_GLUE_CTRL0_H(chan), (val >> 16));
 711         return err;
 712 }
 713
 714 static int esr_reset(struct niu *np)
 715 {
 716         u32 uninitialized_var(reset);
 717         int err;
 718
 719         err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
 720                          ESR_RXTX_RESET_CTRL_L, 0x0000);
 721         if (err)
 722                 return err;
 723         err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
 724                          ESR_RXTX_RESET_CTRL_H, 0xffff);
 725         if (err)
 726                 return err;
 727         udelay(200);
 728
 729         err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
 730                          ESR_RXTX_RESET_CTRL_L, 0xffff);
 731         if (err)
 732                 return err;
 733         udelay(200);
 734
 735         err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
 736                          ESR_RXTX_RESET_CTRL_H, 0x0000);
 737         if (err)
 738                 return err;
 739         udelay(200);
 740
 741         err = esr_read_reset(np, &reset);
 742         if (err)
 743                 return err;
 744         if (reset != 0) {
 745                 netdev_err(np->dev, "Port %u ESR_RESET did not clear [%08x]\n",
 746                            np->port, reset);
 747                 return -ENODEV;
 748         }
 749
 750         return 0;
 751 }
 752
 753 static int serdes_init_10g(struct niu *np)
 754 {
 755         struct niu_link_config *lp = &np->link_config;
 756         unsigned long ctrl_reg, test_cfg_reg, i;
 757         u64 ctrl_val, test_cfg_val, sig, mask, val;
 758         int err;
 759
 760         switch (np->port) {
 761         case 0:
 762                 ctrl_reg = ENET_SERDES_0_CTRL_CFG;
 763                 test_cfg_reg = ENET_SERDES_0_TEST_CFG;
 764                 break;
 765         case 1:
 766                 ctrl_reg = ENET_SERDES_1_CTRL_CFG;
 767                 test_cfg_reg = ENET_SERDES_1_TEST_CFG;
 768                 break;
 769
 770         default:
 771                 return -EINVAL;
 772         }
 773         ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
 774                     ENET_SERDES_CTRL_SDET_1 |
 775                     ENET_SERDES_CTRL_SDET_2 |
 776                     ENET_SERDES_CTRL_SDET_3 |
 777                     (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
 778                     (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
 779                     (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
 780                     (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
 781                     (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
 782                     (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
 783                     (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
 784                     (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
 785         test_cfg_val = 0;
 786
 787         if (lp->loopback_mode == LOOPBACK_PHY) {
 788                 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
 789                                   ENET_SERDES_TEST_MD_0_SHIFT) |
 790                                  (ENET_TEST_MD_PAD_LOOPBACK <<
 791                                   ENET_SERDES_TEST_MD_1_SHIFT) |
 792                                  (ENET_TEST_MD_PAD_LOOPBACK <<
 793                                   ENET_SERDES_TEST_MD_2_SHIFT) |
 794                                  (ENET_TEST_MD_PAD_LOOPBACK <<
 795                                   ENET_SERDES_TEST_MD_3_SHIFT));
 796         }
 797
 798         nw64(ctrl_reg, ctrl_val);
 799         nw64(test_cfg_reg, test_cfg_val);
 800
 801         /* Initialize all 4 lanes of the SERDES.  */
 802         for (i = 0; i < 4; i++) {
 803                 u32 rxtx_ctrl, glue0;
 804
 805                 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
 806                 if (err)
 807                         return err;
 808                 err = esr_read_glue0(np, i, &glue0);
 809                 if (err)
 810                         return err;
 811
 812                 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
 813                 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
 814                               (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
 815
 816                 glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
 817                            ESR_GLUE_CTRL0_THCNT |
 818                            ESR_GLUE_CTRL0_BLTIME);
 819                 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
 820                           (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
 821                           (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
 822                           (BLTIME_300_CYCLES <<
 823                            ESR_GLUE_CTRL0_BLTIME_SHIFT));
 824
 825                 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
 826                 if (err)
 827                         return err;
 828                 err = esr_write_glue0(np, i, glue0);
 829                 if (err)
 830                         return err;
 831         }
 832
 833         err = esr_reset(np);
 834         if (err)
 835                 return err;
 836
 837         sig = nr64(ESR_INT_SIGNALS);
 838         switch (np->port) {
 839         case 0:
 840                 mask = ESR_INT_SIGNALS_P0_BITS;
 841                 val = (ESR_INT_SRDY0_P0 |
 842                        ESR_INT_DET0_P0 |
 843                        ESR_INT_XSRDY_P0 |
 844                        ESR_INT_XDP_P0_CH3 |
 845                        ESR_INT_XDP_P0_CH2 |
 846                        ESR_INT_XDP_P0_CH1 |
 847                        ESR_INT_XDP_P0_CH0);
 848                 break;
 849
 850         case 1:
 851                 mask = ESR_INT_SIGNALS_P1_BITS;
 852                 val = (ESR_INT_SRDY0_P1 |
 853                        ESR_INT_DET0_P1 |
 854                        ESR_INT_XSRDY_P1 |
 855                        ESR_INT_XDP_P1_CH3 |
 856                        ESR_INT_XDP_P1_CH2 |
 857                        ESR_INT_XDP_P1_CH1 |
 858                        ESR_INT_XDP_P1_CH0);
 859                 break;
 860
 861         default:
 862                 return -EINVAL;
 863         }
 864
 865         if ((sig & mask) != val) {
 866                 if (np->flags & NIU_FLAGS_HOTPLUG_PHY) {
 867                         np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT;
 868                         return 0;
 869                 }
 870                 netdev_err(np->dev, "Port %u signal bits [%08x] are not [%08x]\n",
 871                            np->port, (int)(sig & mask), (int)val);
 872                 return -ENODEV;
 873         }
 874         if (np->flags & NIU_FLAGS_HOTPLUG_PHY)
 875                 np->flags |= NIU_FLAGS_HOTPLUG_PHY_PRESENT;
 876         return 0;
 877 }
 878
 879 static int serdes_init_1g(struct niu *np)
 880 {
 881         u64 val;
 882
 883         val = nr64(ENET_SERDES_1_PLL_CFG);
 884         val &= ~ENET_SERDES_PLL_FBDIV2;
 885         switch (np->port) {
 886         case 0:
 887                 val |= ENET_SERDES_PLL_HRATE0;
 888                 break;
 889         case 1:
 890                 val |= ENET_SERDES_PLL_HRATE1;
 891                 break;
 892         case 2:
 893                 val |= ENET_SERDES_PLL_HRATE2;
 894                 break;
 895         case 3:
 896                 val |= ENET_SERDES_PLL_HRATE3;
 897                 break;
 898         default:
 899                 return -EINVAL;
 900         }
 901         nw64(ENET_SERDES_1_PLL_CFG, val);
 902
 903         return 0;
 904 }
 905
 906 static int serdes_init_1g_serdes(struct niu *np)
 907 {
 908         struct niu_link_config *lp = &np->link_config;
 909         unsigned long ctrl_reg, test_cfg_reg, pll_cfg, i;
 910         u64 ctrl_val, test_cfg_val, sig, mask, val;
 911         int err;
 912         u64 reset_val, val_rd;
 913
 914         val = ENET_SERDES_PLL_HRATE0 | ENET_SERDES_PLL_HRATE1 |
 915                 ENET_SERDES_PLL_HRATE2 | ENET_SERDES_PLL_HRATE3 |
 916                 ENET_SERDES_PLL_FBDIV0;
 917         switch (np->port) {
 918         case 0:
 919                 reset_val =  ENET_SERDES_RESET_0;
 920                 ctrl_reg = ENET_SERDES_0_CTRL_CFG;
 921                 test_cfg_reg = ENET_SERDES_0_TEST_CFG;
 922                 pll_cfg = ENET_SERDES_0_PLL_CFG;
 923                 break;
 924         case 1:
 925                 reset_val =  ENET_SERDES_RESET_1;
 926                 ctrl_reg = ENET_SERDES_1_CTRL_CFG;
 927                 test_cfg_reg = ENET_SERDES_1_TEST_CFG;
 928                 pll_cfg = ENET_SERDES_1_PLL_CFG;
 929                 break;
 930
 931         default:
 932                 return -EINVAL;
 933         }
 934         ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
 935                     ENET_SERDES_CTRL_SDET_1 |
 936                     ENET_SERDES_CTRL_SDET_2 |
 937                     ENET_SERDES_CTRL_SDET_3 |
 938                     (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
 939                     (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
 940                     (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
 941                     (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
 942                     (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
 943                     (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
 944                     (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
 945                     (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
 946         test_cfg_val = 0;
 947
 948         if (lp->loopback_mode == LOOPBACK_PHY) {
 949                 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
 950                                   ENET_SERDES_TEST_MD_0_SHIFT) |
 951                                  (ENET_TEST_MD_PAD_LOOPBACK <<
 952                                   ENET_SERDES_TEST_MD_1_SHIFT) |
 953                                  (ENET_TEST_MD_PAD_LOOPBACK <<
 954                                   ENET_SERDES_TEST_MD_2_SHIFT) |
 955                                  (ENET_TEST_MD_PAD_LOOPBACK <<
 956                                   ENET_SERDES_TEST_MD_3_SHIFT));
 957         }
 958
 959         nw64(ENET_SERDES_RESET, reset_val);
 960         mdelay(20);
 961         val_rd = nr64(ENET_SERDES_RESET);
 962         val_rd &= ~reset_val;
 963         nw64(pll_cfg, val);
 964         nw64(ctrl_reg, ctrl_val);
 965         nw64(test_cfg_reg, test_cfg_val);
 966         nw64(ENET_SERDES_RESET, val_rd);
 967         mdelay(2000);
 968
 969         /* Initialize all 4 lanes of the SERDES.  */
 970         for (i = 0; i < 4; i++) {
 971                 u32 rxtx_ctrl, glue0;
 972
 973                 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
 974                 if (err)
 975                         return err;
 976                 err = esr_read_glue0(np, i, &glue0);
 977                 if (err)
 978                         return err;
 979
 980                 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
 981                 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
 982                               (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
 983
 984                 glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
 985                            ESR_GLUE_CTRL0_THCNT |
 986                            ESR_GLUE_CTRL0_BLTIME);
 987                 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
 988                           (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
 989                           (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
 990                           (BLTIME_300_CYCLES <<
 991                            ESR_GLUE_CTRL0_BLTIME_SHIFT));
 992
 993                 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
 994                 if (err)
 995                         return err;
 996                 err = esr_write_glue0(np, i, glue0);
 997                 if (err)
 998                         return err;
 999         }
1000
1001
1002         sig = nr64(ESR_INT_SIGNALS);
1003         switch (np->port) {
1004         case 0:
1005                 val = (ESR_INT_SRDY0_P0 | ESR_INT_DET0_P0);
1006                 mask = val;
1007                 break;
1008
1009         case 1:
1010                 val = (ESR_INT_SRDY0_P1 | ESR_INT_DET0_P1);
1011                 mask = val;
1012                 break;
1013
1014         default:
1015                 return -EINVAL;
1016         }
1017
1018         if ((sig & mask) != val) {
1019                 netdev_err(np->dev, "Port %u signal bits [%08x] are not [%08x]\n",
1020                            np->port, (int)(sig & mask), (int)val);
1021                 return -ENODEV;
1022         }
1023
1024         return 0;
1025 }
1026
1027 static int link_status_1g_serdes(struct niu *np, int *link_up_p)
1028 {
1029         struct niu_link_config *lp = &np->link_config;
1030         int link_up;
1031         u64 val;
1032         u16 current_speed;
1033         unsigned long flags;
1034         u8 current_duplex;
1035
1036         link_up = 0;
1037         current_speed = SPEED_INVALID;
1038         current_duplex = DUPLEX_INVALID;
1039
1040         spin_lock_irqsave(&np->lock, flags);
1041
1042         val = nr64_pcs(PCS_MII_STAT);
1043
1044         if (val & PCS_MII_STAT_LINK_STATUS) {
1045                 link_up = 1;
1046                 current_speed = SPEED_1000;
1047                 current_duplex = DUPLEX_FULL;
1048         }
1049
1050         lp->active_speed = current_speed;
1051         lp->active_duplex = current_duplex;
1052         spin_unlock_irqrestore(&np->lock, flags);
1053
1054         *link_up_p = link_up;
1055         return 0;
1056 }
1057
1058 static int link_status_10g_serdes(struct niu *np, int *link_up_p)
1059 {
1060         unsigned long flags;
1061         struct niu_link_config *lp = &np->link_config;
1062         int link_up = 0;
1063         int link_ok = 1;
1064         u64 val, val2;
1065         u16 current_speed;
1066         u8 current_duplex;
1067
1068         if (!(np->flags & NIU_FLAGS_10G))
1069                 return link_status_1g_serdes(np, link_up_p);
1070
1071         current_speed = SPEED_INVALID;
1072         current_duplex = DUPLEX_INVALID;
1073         spin_lock_irqsave(&np->lock, flags);
1074
1075         val = nr64_xpcs(XPCS_STATUS(0));
1076         val2 = nr64_mac(XMAC_INTER2);
1077         if (val2 & 0x01000000)
1078                 link_ok = 0;
1079
1080         if ((val & 0x1000ULL) && link_ok) {
1081                 link_up = 1;
1082                 current_speed = SPEED_10000;
1083                 current_duplex = DUPLEX_FULL;
1084         }
1085         lp->active_speed = current_speed;
1086         lp->active_duplex = current_duplex;
1087         spin_unlock_irqrestore(&np->lock, flags);
1088         *link_up_p = link_up;
1089         return 0;
1090 }
1091
1092 static int link_status_mii(struct niu *np, int *link_up_p)
1093 {
1094         struct niu_link_config *lp = &np->link_config;
1095         int err;
1096         int bmsr, advert, ctrl1000, stat1000, lpa, bmcr, estatus;
1097         int supported, advertising, active_speed, active_duplex;
1098
1099         err = mii_read(np, np->phy_addr, MII_BMCR);
1100         if (unlikely(err < 0))
1101                 return err;
1102         bmcr = err;
1103
1104         err = mii_read(np, np->phy_addr, MII_BMSR);
1105         if (unlikely(err < 0))
1106                 return err;
1107         bmsr = err;
1108
1109         err = mii_read(np, np->phy_addr, MII_ADVERTISE);
1110         if (unlikely(err < 0))
1111                 return err;
1112         advert = err;
1113
1114         err = mii_read(np, np->phy_addr, MII_LPA);
1115         if (unlikely(err < 0))
1116                 return err;
1117         lpa = err;
1118
1119         if (likely(bmsr & BMSR_ESTATEN)) {
1120                 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1121                 if (unlikely(err < 0))
1122                         return err;
1123                 estatus = err;
1124
1125                 err = mii_read(np, np->phy_addr, MII_CTRL1000);
1126                 if (unlikely(err < 0))
1127                         return err;
1128                 ctrl1000 = err;
1129
1130                 err = mii_read(np, np->phy_addr, MII_STAT1000);
1131                 if (unlikely(err < 0))
1132                         return err;
1133                 stat1000 = err;
1134         } else
1135                 estatus = ctrl1000 = stat1000 = 0;
1136
1137         supported = 0;
1138         if (bmsr & BMSR_ANEGCAPABLE)
1139                 supported |= SUPPORTED_Autoneg;
1140         if (bmsr & BMSR_10HALF)
1141                 supported |= SUPPORTED_10baseT_Half;
1142         if (bmsr & BMSR_10FULL)
1143                 supported |= SUPPORTED_10baseT_Full;
1144         if (bmsr & BMSR_100HALF)
1145                 supported |= SUPPORTED_100baseT_Half;
1146         if (bmsr & BMSR_100FULL)
1147                 supported |= SUPPORTED_100baseT_Full;
1148         if (estatus & ESTATUS_1000_THALF)
1149                 supported |= SUPPORTED_1000baseT_Half;
1150         if (estatus & ESTATUS_1000_TFULL)
1151                 supported |= SUPPORTED_1000baseT_Full;
1152         lp->supported = supported;
1153
1154         advertising = 0;
1155         if (advert & ADVERTISE_10HALF)
1156                 advertising |= ADVERTISED_10baseT_Half;
1157         if (advert & ADVERTISE_10FULL)
1158                 advertising |= ADVERTISED_10baseT_Full;
1159         if (advert & ADVERTISE_100HALF)
1160                 advertising |= ADVERTISED_100baseT_Half;
1161         if (advert & ADVERTISE_100FULL)
1162                 advertising |= ADVERTISED_100baseT_Full;
1163         if (ctrl1000 & ADVERTISE_1000HALF)
1164                 advertising |= ADVERTISED_1000baseT_Half;
1165         if (ctrl1000 & ADVERTISE_1000FULL)
1166                 advertising |= ADVERTISED_1000baseT_Full;
1167
1168         if (bmcr & BMCR_ANENABLE) {
1169                 int neg, neg1000;
1170
1171                 lp->active_autoneg = 1;
1172                 advertising |= ADVERTISED_Autoneg;
1173
1174                 neg = advert & lpa;
1175                 neg1000 = (ctrl1000 << 2) & stat1000;
1176
1177                 if (neg1000 & (LPA_1000FULL | LPA_1000HALF))
1178                         active_speed = SPEED_1000;
1179                 else if (neg & LPA_100)
1180                         active_speed = SPEED_100;
1181                 else if (neg & (LPA_10HALF | LPA_10FULL))
1182                         active_speed = SPEED_10;
1183                 else
1184                         active_speed = SPEED_INVALID;
1185
1186                 if ((neg1000 & LPA_1000FULL) || (neg & LPA_DUPLEX))
1187                         active_duplex = DUPLEX_FULL;
1188                 else if (active_speed != SPEED_INVALID)
1189                         active_duplex = DUPLEX_HALF;
1190                 else
1191                         active_duplex = DUPLEX_INVALID;
1192         } else {
1193                 lp->active_autoneg = 0;
1194
1195                 if ((bmcr & BMCR_SPEED1000) && !(bmcr & BMCR_SPEED100))
1196                         active_speed = SPEED_1000;
1197                 else if (bmcr & BMCR_SPEED100)
1198                         active_speed = SPEED_100;
1199                 else
1200                         active_speed = SPEED_10;
1201
1202                 if (bmcr & BMCR_FULLDPLX)
1203                         active_duplex = DUPLEX_FULL;
1204                 else
1205                         active_duplex = DUPLEX_HALF;
1206         }
1207
1208         lp->active_advertising = advertising;
1209         lp->active_speed = active_speed;
1210         lp->active_duplex = active_duplex;
1211         *link_up_p = !!(bmsr & BMSR_LSTATUS);
1212
1213         return 0;
1214 }
1215
1216 static int link_status_1g_rgmii(struct niu *np, int *link_up_p)
1217 {
1218         struct niu_link_config *lp = &np->link_config;
1219         u16 current_speed, bmsr;
1220         unsigned long flags;
1221         u8 current_duplex;
1222         int err, link_up;
1223
1224         link_up = 0;
1225         current_speed = SPEED_INVALID;
1226         current_duplex = DUPLEX_INVALID;
1227
1228         spin_lock_irqsave(&np->lock, flags);
1229
1230         err = -EINVAL;
1231
1232         err = mii_read(np, np->phy_addr, MII_BMSR);
1233         if (err < 0)
1234                 goto out;
1235
1236         bmsr = err;
1237         if (bmsr & BMSR_LSTATUS) {
1238                 u16 adv, lpa, common, estat;
1239
1240                 err = mii_read(np, np->phy_addr, MII_ADVERTISE);
1241                 if (err < 0)
1242                         goto out;
1243                 adv = err;
1244
1245                 err = mii_read(np, np->phy_addr, MII_LPA);
1246                 if (err < 0)
1247                         goto out;
1248                 lpa = err;
1249
1250                 common = adv & lpa;
1251
1252                 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1253                 if (err < 0)
1254                         goto out;
1255                 estat = err;
1256                 link_up = 1;
1257                 current_speed = SPEED_1000;
1258                 current_duplex = DUPLEX_FULL;
1259
1260         }
1261         lp->active_speed = current_speed;
1262         lp->active_duplex = current_duplex;
1263         err = 0;
1264
1265 out:
1266         spin_unlock_irqrestore(&np->lock, flags);
1267
1268         *link_up_p = link_up;
1269         return err;
1270 }
1271
1272 static int link_status_1g(struct niu *np, int *link_up_p)
1273 {
1274         struct niu_link_config *lp = &np->link_config;
1275         unsigned long flags;
1276         int err;
1277
1278         spin_lock_irqsave(&np->lock, flags);
1279
1280         err = link_status_mii(np, link_up_p);
1281         lp->supported |= SUPPORTED_TP;
1282         lp->active_advertising |= ADVERTISED_TP;
1283
1284         spin_unlock_irqrestore(&np->lock, flags);
1285         return err;
1286 }
1287
1288 static int bcm8704_reset(struct niu *np)
1289 {
1290         int err, limit;
1291
1292         err = mdio_read(np, np->phy_addr,
1293                         BCM8704_PHYXS_DEV_ADDR, MII_BMCR);
1294         if (err < 0 || err == 0xffff)
1295                 return err;
1296         err |= BMCR_RESET;
1297         err = mdio_write(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
1298                          MII_BMCR, err);
1299         if (err)
1300                 return err;
1301
1302         limit = 1000;
1303         while (--limit >= 0) {
1304                 err = mdio_read(np, np->phy_addr,
1305                                 BCM8704_PHYXS_DEV_ADDR, MII_BMCR);
1306                 if (err < 0)
1307                         return err;
1308                 if (!(err & BMCR_RESET))
1309                         break;
1310         }
1311         if (limit < 0) {
1312                 netdev_err(np->dev, "Port %u PHY will not reset (bmcr=%04x)\n",
1313                            np->port, (err & 0xffff));
1314                 return -ENODEV;
1315         }
1316         return 0;
1317 }
1318
1319 /* When written, certain PHY registers need to be read back twice
1320  * in order for the bits to settle properly.
1321  */
1322 static int bcm8704_user_dev3_readback(struct niu *np, int reg)
1323 {
1324         int err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, reg);
1325         if (err < 0)
1326                 return err;
1327         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, reg);
1328         if (err < 0)
1329                 return err;
1330         return 0;
1331 }
1332
1333 static int bcm8706_init_user_dev3(struct niu *np)
1334 {
1335         int err;
1336
1337
1338         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1339                         BCM8704_USER_OPT_DIGITAL_CTRL);
1340         if (err < 0)
1341                 return err;
1342         err &= ~USER_ODIG_CTRL_GPIOS;
1343         err |= (0x3 << USER_ODIG_CTRL_GPIOS_SHIFT);
1344         err |=  USER_ODIG_CTRL_RESV2;
1345         err = mdio_write(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1346                          BCM8704_USER_OPT_DIGITAL_CTRL, err);
1347         if (err)
1348                 return err;
1349
1350         mdelay(1000);
1351
1352         return 0;
1353 }
1354
1355 static int bcm8704_init_user_dev3(struct niu *np)
1356 {
1357         int err;
1358
1359         err = mdio_write(np, np->phy_addr,
1360                          BCM8704_USER_DEV3_ADDR, BCM8704_USER_CONTROL,
1361                          (USER_CONTROL_OPTXRST_LVL |
1362                           USER_CONTROL_OPBIASFLT_LVL |
1363                           USER_CONTROL_OBTMPFLT_LVL |
1364                           USER_CONTROL_OPPRFLT_LVL |
1365                           USER_CONTROL_OPTXFLT_LVL |
1366                           USER_CONTROL_OPRXLOS_LVL |
1367                           USER_CONTROL_OPRXFLT_LVL |
1368                           USER_CONTROL_OPTXON_LVL |
1369                           (0x3f << USER_CONTROL_RES1_SHIFT)));
1370         if (err)
1371                 return err;
1372
1373         err = mdio_write(np, np->phy_addr,
1374                          BCM8704_USER_DEV3_ADDR, BCM8704_USER_PMD_TX_CONTROL,
1375                          (USER_PMD_TX_CTL_XFP_CLKEN |
1376                           (1 << USER_PMD_TX_CTL_TX_DAC_TXD_SH) |
1377                           (2 << USER_PMD_TX_CTL_TX_DAC_TXCK_SH) |
1378                           USER_PMD_TX_CTL_TSCK_LPWREN));
1379         if (err)
1380                 return err;
1381
1382         err = bcm8704_user_dev3_readback(np, BCM8704_USER_CONTROL);
1383         if (err)
1384                 return err;
1385         err = bcm8704_user_dev3_readback(np, BCM8704_USER_PMD_TX_CONTROL);
1386         if (err)
1387                 return err;
1388
1389         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1390                         BCM8704_USER_OPT_DIGITAL_CTRL);
1391         if (err < 0)
1392                 return err;
1393         err &= ~USER_ODIG_CTRL_GPIOS;
1394         err |= (0x3 << USER_ODIG_CTRL_GPIOS_SHIFT);
1395         err = mdio_write(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1396                          BCM8704_USER_OPT_DIGITAL_CTRL, err);
1397         if (err)
1398                 return err;
1399
1400         mdelay(1000);
1401
1402         return 0;
1403 }
1404
1405 static int mrvl88x2011_act_led(struct niu *np, int val)
1406 {
1407         int     err;
1408
1409         err  = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1410                 MRVL88X2011_LED_8_TO_11_CTL);
1411         if (err < 0)
1412                 return err;
1413
1414         err &= ~MRVL88X2011_LED(MRVL88X2011_LED_ACT,MRVL88X2011_LED_CTL_MASK);
1415         err |=  MRVL88X2011_LED(MRVL88X2011_LED_ACT,val);
1416
1417         return mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1418                           MRVL88X2011_LED_8_TO_11_CTL, err);
1419 }
1420
1421 static int mrvl88x2011_led_blink_rate(struct niu *np, int rate)
1422 {
1423         int     err;
1424
1425         err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1426                         MRVL88X2011_LED_BLINK_CTL);
1427         if (err >= 0) {
1428                 err &= ~MRVL88X2011_LED_BLKRATE_MASK;
1429                 err |= (rate << 4);
1430
1431                 err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1432                                  MRVL88X2011_LED_BLINK_CTL, err);
1433         }
1434
1435         return err;
1436 }
1437
1438 static int xcvr_init_10g_mrvl88x2011(struct niu *np)
1439 {
1440         int     err;
1441
1442         /* Set LED functions */
1443         err = mrvl88x2011_led_blink_rate(np, MRVL88X2011_LED_BLKRATE_134MS);
1444         if (err)
1445                 return err;
1446
1447         /* led activity */
1448         err = mrvl88x2011_act_led(np, MRVL88X2011_LED_CTL_OFF);
1449         if (err)
1450                 return err;
1451
1452         err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1453                         MRVL88X2011_GENERAL_CTL);
1454         if (err < 0)
1455                 return err;
1456
1457         err |= MRVL88X2011_ENA_XFPREFCLK;
1458
1459         err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1460                          MRVL88X2011_GENERAL_CTL, err);
1461         if (err < 0)
1462                 return err;
1463
1464         err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1465                         MRVL88X2011_PMA_PMD_CTL_1);
1466         if (err < 0)
1467                 return err;
1468
1469         if (np->link_config.loopback_mode == LOOPBACK_MAC)
1470                 err |= MRVL88X2011_LOOPBACK;
1471         else
1472                 err &= ~MRVL88X2011_LOOPBACK;
1473
1474         err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1475                          MRVL88X2011_PMA_PMD_CTL_1, err);
1476         if (err < 0)
1477                 return err;
1478
1479         /* Enable PMD  */
1480         return mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1481                           MRVL88X2011_10G_PMD_TX_DIS, MRVL88X2011_ENA_PMDTX);
1482 }
1483
1484
1485 static int xcvr_diag_bcm870x(struct niu *np)
1486 {
1487         u16 analog_stat0, tx_alarm_status;
1488         int err = 0;
1489
1490 #if 1
1491         err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
1492                         MII_STAT1000);
1493         if (err < 0)
1494                 return err;
1495         pr_info("Port %u PMA_PMD(MII_STAT1000) [%04x]\n", np->port, err);
1496
1497         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, 0x20);
1498         if (err < 0)
1499                 return err;
1500         pr_info("Port %u USER_DEV3(0x20) [%04x]\n", np->port, err);
1501
1502         err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
1503                         MII_NWAYTEST);
1504         if (err < 0)
1505                 return err;
1506         pr_info("Port %u PHYXS(MII_NWAYTEST) [%04x]\n", np->port, err);
1507 #endif
1508
1509         /* XXX dig this out it might not be so useful XXX */
1510         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1511                         BCM8704_USER_ANALOG_STATUS0);
1512         if (err < 0)
1513                 return err;
1514         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1515                         BCM8704_USER_ANALOG_STATUS0);
1516         if (err < 0)
1517                 return err;
1518         analog_stat0 = err;
1519
1520         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1521                         BCM8704_USER_TX_ALARM_STATUS);
1522         if (err < 0)
1523                 return err;
1524         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1525                         BCM8704_USER_TX_ALARM_STATUS);
1526         if (err < 0)
1527                 return err;
1528         tx_alarm_status = err;
1529
1530         if (analog_stat0 != 0x03fc) {
1531                 if ((analog_stat0 == 0x43bc) && (tx_alarm_status != 0)) {
1532                         pr_info("Port %u cable not connected or bad cable\n",
1533                                 np->port);
1534                 } else if (analog_stat0 == 0x639c) {
1535                         pr_info("Port %u optical module is bad or missing\n",
1536                                 np->port);
1537                 }
1538         }
1539
1540         return 0;
1541 }
1542
1543 static int xcvr_10g_set_lb_bcm870x(struct niu *np)
1544 {
1545         struct niu_link_config *lp = &np->link_config;
1546         int err;
1547
1548         err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
1549                         MII_BMCR);
1550         if (err < 0)
1551                 return err;
1552
1553         err &= ~BMCR_LOOPBACK;
1554
1555         if (lp->loopback_mode == LOOPBACK_MAC)
1556                 err |= BMCR_LOOPBACK;
1557
1558         err = mdio_write(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
1559                          MII_BMCR, err);
1560         if (err)
1561                 return err;
1562
1563         return 0;
1564 }
1565
1566 static int xcvr_init_10g_bcm8706(struct niu *np)
1567 {
1568         int err = 0;
1569         u64 val;
1570
1571         if ((np->flags & NIU_FLAGS_HOTPLUG_PHY) &&
1572             (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) == 0)
1573                         return err;
1574
1575         val = nr64_mac(XMAC_CONFIG);
1576         val &= ~XMAC_CONFIG_LED_POLARITY;
1577         val |= XMAC_CONFIG_FORCE_LED_ON;
1578         nw64_mac(XMAC_CONFIG, val);
1579
1580         val = nr64(MIF_CONFIG);
1581         val |= MIF_CONFIG_INDIRECT_MODE;
1582         nw64(MIF_CONFIG, val);
1583
1584         err = bcm8704_reset(np);
1585         if (err)
1586                 return err;
1587
1588         err = xcvr_10g_set_lb_bcm870x(np);
1589         if (err)
1590                 return err;
1591
1592         err = bcm8706_init_user_dev3(np);
1593         if (err)
1594                 return err;
1595
1596         err = xcvr_diag_bcm870x(np);
1597         if (err)
1598                 return err;
1599
1600         return 0;
1601 }
1602
1603 static int xcvr_init_10g_bcm8704(struct niu *np)
1604 {
1605         int err;
1606
1607         err = bcm8704_reset(np);
1608         if (err)
1609                 return err;
1610
1611         err = bcm8704_init_user_dev3(np);
1612         if (err)
1613                 return err;
1614
1615         err = xcvr_10g_set_lb_bcm870x(np);
1616         if (err)
1617                 return err;
1618
1619         err =  xcvr_diag_bcm870x(np);
1620         if (err)
1621                 return err;
1622
1623         return 0;
1624 }
1625
1626 static int xcvr_init_10g(struct niu *np)
1627 {
1628         int phy_id, err;
1629         u64 val;
1630
1631         val = nr64_mac(XMAC_CONFIG);
1632         val &= ~XMAC_CONFIG_LED_POLARITY;
1633         val |= XMAC_CONFIG_FORCE_LED_ON;
1634         nw64_mac(XMAC_CONFIG, val);
1635
1636         /* XXX shared resource, lock parent XXX */
1637         val = nr64(MIF_CONFIG);
1638         val |= MIF_CONFIG_INDIRECT_MODE;
1639         nw64(MIF_CONFIG, val);
1640
1641         phy_id = phy_decode(np->parent->port_phy, np->port);
1642         phy_id = np->parent->phy_probe_info.phy_id[phy_id][np->port];
1643
1644         /* handle different phy types */
1645         switch (phy_id & NIU_PHY_ID_MASK) {
1646         case NIU_PHY_ID_MRVL88X2011:
1647                 err = xcvr_init_10g_mrvl88x2011(np);
1648                 break;
1649
1650         default: /* bcom 8704 */
1651                 err = xcvr_init_10g_bcm8704(np);
1652                 break;
1653         }
1654
1655         return 0;
1656 }
1657
1658 static int mii_reset(struct niu *np)
1659 {
1660         int limit, err;
1661
1662         err = mii_write(np, np->phy_addr, MII_BMCR, BMCR_RESET);
1663         if (err)
1664                 return err;
1665
1666         limit = 1000;
1667         while (--limit >= 0) {
1668                 udelay(500);
1669                 err = mii_read(np, np->phy_addr, MII_BMCR);
1670                 if (err < 0)
1671                         return err;
1672                 if (!(err & BMCR_RESET))
1673                         break;
1674         }
1675         if (limit < 0) {
1676                 netdev_err(np->dev, "Port %u MII would not reset, bmcr[%04x]\n",
1677                            np->port, err);
1678                 return -ENODEV;
1679         }
1680
1681         return 0;
1682 }
1683
1684 static int xcvr_init_1g_rgmii(struct niu *np)
1685 {
1686         int err;
1687         u64 val;
1688         u16 bmcr, bmsr, estat;
1689
1690         val = nr64(MIF_CONFIG);
1691         val &= ~MIF_CONFIG_INDIRECT_MODE;
1692         nw64(MIF_CONFIG, val);
1693
1694         err = mii_reset(np);
1695         if (err)
1696                 return err;
1697
1698         err = mii_read(np, np->phy_addr, MII_BMSR);
1699         if (err < 0)
1700                 return err;
1701         bmsr = err;
1702
1703         estat = 0;
1704         if (bmsr & BMSR_ESTATEN) {
1705                 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1706                 if (err < 0)
1707                         return err;
1708                 estat = err;
1709         }
1710
1711         bmcr = 0;
1712         err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1713         if (err)
1714                 return err;
1715
1716         if (bmsr & BMSR_ESTATEN) {
1717                 u16 ctrl1000 = 0;
1718
1719                 if (estat & ESTATUS_1000_TFULL)
1720                         ctrl1000 |= ADVERTISE_1000FULL;
1721                 err = mii_write(np, np->phy_addr, MII_CTRL1000, ctrl1000);
1722                 if (err)
1723                         return err;
1724         }
1725
1726         bmcr = (BMCR_SPEED1000 | BMCR_FULLDPLX);
1727
1728         err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1729         if (err)
1730                 return err;
1731
1732         err = mii_read(np, np->phy_addr, MII_BMCR);
1733         if (err < 0)
1734                 return err;
1735         bmcr = mii_read(np, np->phy_addr, MII_BMCR);
1736
1737         err = mii_read(np, np->phy_addr, MII_BMSR);
1738         if (err < 0)
1739                 return err;
1740
1741         return 0;
1742 }
1743
1744 static int mii_init_common(struct niu *np)
1745 {
1746         struct niu_link_config *lp = &np->link_config;
1747         u16 bmcr, bmsr, adv, estat;
1748         int err;
1749
1750         err = mii_reset(np);
1751         if (err)
1752                 return err;
1753
1754         err = mii_read(np, np->phy_addr, MII_BMSR);
1755         if (err < 0)
1756                 return err;
1757         bmsr = err;
1758
1759         estat = 0;
1760         if (bmsr & BMSR_ESTATEN) {
1761                 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1762                 if (err < 0)
1763                         return err;
1764                 estat = err;
1765         }
1766
1767         bmcr = 0;
1768         err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1769         if (err)
1770                 return err;
1771
1772         if (lp->loopback_mode == LOOPBACK_MAC) {
1773                 bmcr |= BMCR_LOOPBACK;
1774                 if (lp->active_speed == SPEED_1000)
1775                         bmcr |= BMCR_SPEED1000;
1776                 if (lp->active_duplex == DUPLEX_FULL)
1777                         bmcr |= BMCR_FULLDPLX;
1778         }
1779
1780         if (lp->loopback_mode == LOOPBACK_PHY) {
1781                 u16 aux;
1782
1783                 aux = (BCM5464R_AUX_CTL_EXT_LB |
1784                        BCM5464R_AUX_CTL_WRITE_1);
1785                 err = mii_write(np, np->phy_addr, BCM5464R_AUX_CTL, aux);
1786                 if (err)
1787                         return err;
1788         }
1789
1790         if (lp->autoneg) {
1791                 u16 ctrl1000;
1792
1793                 adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1794                 if ((bmsr & BMSR_10HALF) &&
1795                         (lp->advertising & ADVERTISED_10baseT_Half))
1796                         adv |= ADVERTISE_10HALF;
1797                 if ((bmsr & BMSR_10FULL) &&
1798                         (lp->advertising & ADVERTISED_10baseT_Full))
1799                         adv |= ADVERTISE_10FULL;
1800                 if ((bmsr & BMSR_100HALF) &&
1801                         (lp->advertising & ADVERTISED_100baseT_Half))
1802                         adv |= ADVERTISE_100HALF;
1803                 if ((bmsr & BMSR_100FULL) &&
1804                         (lp->advertising & ADVERTISED_100baseT_Full))
1805                         adv |= ADVERTISE_100FULL;
1806                 err = mii_write(np, np->phy_addr, MII_ADVERTISE, adv);
1807                 if (err)
1808                         return err;
1809
1810                 if (likely(bmsr & BMSR_ESTATEN)) {
1811                         ctrl1000 = 0;
1812                         if ((estat & ESTATUS_1000_THALF) &&
1813                                 (lp->advertising & ADVERTISED_1000baseT_Half))
1814                                 ctrl1000 |= ADVERTISE_1000HALF;
1815                         if ((estat & ESTATUS_1000_TFULL) &&
1816                                 (lp->advertising & ADVERTISED_1000baseT_Full))
1817                                 ctrl1000 |= ADVERTISE_1000FULL;
1818                         err = mii_write(np, np->phy_addr,
1819                                         MII_CTRL1000, ctrl1000);
1820                         if (err)
1821                                 return err;
1822                 }
1823
1824                 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1825         } else {
1826                 /* !lp->autoneg */
1827                 int fulldpx;
1828
1829                 if (lp->duplex == DUPLEX_FULL) {
1830                         bmcr |= BMCR_FULLDPLX;
1831                         fulldpx = 1;
1832                 } else if (lp->duplex == DUPLEX_HALF)
1833                         fulldpx = 0;
1834                 else
1835                         return -EINVAL;
1836
1837                 if (lp->speed == SPEED_1000) {
1838                         /* if X-full requested while not supported, or
1839                            X-half requested while not supported... */
1840                         if ((fulldpx && !(estat & ESTATUS_1000_TFULL)) ||
1841                                 (!fulldpx && !(estat & ESTATUS_1000_THALF)))
1842                                 return -EINVAL;
1843                         bmcr |= BMCR_SPEED1000;
1844                 } else if (lp->speed == SPEED_100) {
1845                         if ((fulldpx && !(bmsr & BMSR_100FULL)) ||
1846                                 (!fulldpx && !(bmsr & BMSR_100HALF)))
1847                                 return -EINVAL;
1848                         bmcr |= BMCR_SPEED100;
1849                 } else if (lp->speed == SPEED_10) {
1850                         if ((fulldpx && !(bmsr & BMSR_10FULL)) ||
1851                                 (!fulldpx && !(bmsr & BMSR_10HALF)))
1852                                 return -EINVAL;
1853                 } else
1854                         return -EINVAL;
1855         }
1856
1857         err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1858         if (err)
1859                 return err;
1860
1861 #if 0
1862         err = mii_read(np, np->phy_addr, MII_BMCR);
1863         if (err < 0)
1864                 return err;
1865         bmcr = err;
1866
1867         err = mii_read(np, np->phy_addr, MII_BMSR);
1868         if (err < 0)
1869                 return err;
1870         bmsr = err;
1871
1872         pr_info("Port %u after MII init bmcr[%04x] bmsr[%04x]\n",
1873                 np->port, bmcr, bmsr);
1874 #endif
1875
1876         return 0;
1877 }
1878
1879 static int xcvr_init_1g(struct niu *np)
1880 {
1881         u64 val;
1882
1883         /* XXX shared resource, lock parent XXX */
1884         val = nr64(MIF_CONFIG);
1885         val &= ~MIF_CONFIG_INDIRECT_MODE;
1886         nw64(MIF_CONFIG, val);
1887
1888         return mii_init_common(np);
1889 }
1890
1891 static int niu_xcvr_init(struct niu *np)
1892 {
1893         const struct niu_phy_ops *ops = np->phy_ops;
1894         int err;
1895
1896         err = 0;
1897         if (ops->xcvr_init)
1898                 err = ops->xcvr_init(np);
1899
1900         return err;
1901 }
1902
1903 static int niu_serdes_init(struct niu *np)
1904 {
1905         const struct niu_phy_ops *ops = np->phy_ops;
1906         int err;
1907
1908         err = 0;
1909         if (ops->serdes_init)
1910                 err = ops->serdes_init(np);
1911
1912         return err;
1913 }
1914
1915 static void niu_init_xif(struct niu *);
1916 static void niu_handle_led(struct niu *, int status);
1917
1918 static int niu_link_status_common(struct niu *np, int link_up)
1919 {
1920         struct niu_link_config *lp = &np->link_config;
1921         struct net_device *dev = np->dev;
1922         unsigned long flags;
1923
1924         if (!netif_carrier_ok(dev) && link_up) {
1925                 netif_info(np, link, dev, "Link is up at %s, %s duplex\n",
1926                            lp->active_speed == SPEED_10000 ? "10Gb/sec" :
1927                            lp->active_speed == SPEED_1000 ? "1Gb/sec" :
1928                            lp->active_speed == SPEED_100 ? "100Mbit/sec" :
1929                            "10Mbit/sec",
1930                            lp->active_duplex == DUPLEX_FULL ? "full" : "half");
1931
1932                 spin_lock_irqsave(&np->lock, flags);
1933                 niu_init_xif(np);
1934                 niu_handle_led(np, 1);
1935                 spin_unlock_irqrestore(&np->lock, flags);
1936
1937                 netif_carrier_on(dev);
1938         } else if (netif_carrier_ok(dev) && !link_up) {
1939                 netif_warn(np, link, dev, "Link is down\n");
1940                 spin_lock_irqsave(&np->lock, flags);
1941                 niu_handle_led(np, 0);
1942                 spin_unlock_irqrestore(&np->lock, flags);
1943                 netif_carrier_off(dev);
1944         }
1945
1946         return 0;
1947 }
1948
1949 static int link_status_10g_mrvl(struct niu *np, int *link_up_p)
1950 {
1951         int err, link_up, pma_status, pcs_status;
1952
1953         link_up = 0;
1954
1955         err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1956                         MRVL88X2011_10G_PMD_STATUS_2);
1957         if (err < 0)
1958                 goto out;
1959
1960         /* Check PMA/PMD Register: 1.0001.2 == 1 */
1961         err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1962                         MRVL88X2011_PMA_PMD_STATUS_1);
1963         if (err < 0)
1964                 goto out;
1965
1966         pma_status = ((err & MRVL88X2011_LNK_STATUS_OK) ? 1 : 0);
1967
1968         /* Check PMC Register : 3.0001.2 == 1: read twice */
1969         err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1970                         MRVL88X2011_PMA_PMD_STATUS_1);
1971         if (err < 0)
1972                 goto out;
1973
1974         err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1975                         MRVL88X2011_PMA_PMD_STATUS_1);
1976         if (err < 0)
1977                 goto out;
1978
1979         pcs_status = ((err & MRVL88X2011_LNK_STATUS_OK) ? 1 : 0);
1980
1981         /* Check XGXS Register : 4.0018.[0-3,12] */
1982         err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV4_ADDR,
1983                         MRVL88X2011_10G_XGXS_LANE_STAT);
1984         if (err < 0)
1985                 goto out;
1986
1987         if (err == (PHYXS_XGXS_LANE_STAT_ALINGED | PHYXS_XGXS_LANE_STAT_LANE3 |
1988                     PHYXS_XGXS_LANE_STAT_LANE2 | PHYXS_XGXS_LANE_STAT_LANE1 |
1989                     PHYXS_XGXS_LANE_STAT_LANE0 | PHYXS_XGXS_LANE_STAT_MAGIC |
1990                     0x800))
1991                 link_up = (pma_status && pcs_status) ? 1 : 0;
1992
1993         np->link_config.active_speed = SPEED_10000;
1994         np->link_config.active_duplex = DUPLEX_FULL;
1995         err = 0;
1996 out:
1997         mrvl88x2011_act_led(np, (link_up ?
1998                                  MRVL88X2011_LED_CTL_PCS_ACT :
1999                                  MRVL88X2011_LED_CTL_OFF));
2000
2001         *link_up_p = link_up;
2002         return err;
2003 }
2004
2005 static int link_status_10g_bcm8706(struct niu *np, int *link_up_p)
2006 {
2007         int err, link_up;
2008         link_up = 0;
2009
2010         err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
2011                         BCM8704_PMD_RCV_SIGDET);
2012         if (err < 0 || err == 0xffff)
2013                 goto out;
2014         if (!(err & PMD_RCV_SIGDET_GLOBAL)) {
2015                 err = 0;
2016                 goto out;
2017         }
2018
2019         err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
2020                         BCM8704_PCS_10G_R_STATUS);
2021         if (err < 0)
2022                 goto out;
2023
2024         if (!(err & PCS_10G_R_STATUS_BLK_LOCK)) {
2025                 err = 0;
2026                 goto out;
2027         }
2028
2029         err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
2030                         BCM8704_PHYXS_XGXS_LANE_STAT);
2031         if (err < 0)
2032                 goto out;
2033         if (err != (PHYXS_XGXS_LANE_STAT_ALINGED |
2034                     PHYXS_XGXS_LANE_STAT_MAGIC |
2035                     PHYXS_XGXS_LANE_STAT_PATTEST |
2036                     PHYXS_XGXS_LANE_STAT_LANE3 |
2037                     PHYXS_XGXS_LANE_STAT_LANE2 |
2038                     PHYXS_XGXS_LANE_STAT_LANE1 |
2039                     PHYXS_XGXS_LANE_STAT_LANE0)) {
2040                 err = 0;
2041                 np->link_config.active_speed = SPEED_INVALID;
2042                 np->link_config.active_duplex = DUPLEX_INVALID;
2043                 goto out;
2044         }
2045
2046         link_up = 1;
2047         np->link_config.active_speed = SPEED_10000;
2048         np->link_config.active_duplex = DUPLEX_FULL;
2049         err = 0;
2050
2051 out:
2052         *link_up_p = link_up;
2053         return err;
2054 }
2055
2056 static int link_status_10g_bcom(struct niu *np, int *link_up_p)
2057 {
2058         int err, link_up;
2059
2060         link_up = 0;
2061
2062         err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
2063                         BCM8704_PMD_RCV_SIGDET);
2064         if (err < 0)
2065                 goto out;
2066         if (!(err & PMD_RCV_SIGDET_GLOBAL)) {
2067                 err = 0;
2068                 goto out;
2069         }
2070
2071         err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
2072                         BCM8704_PCS_10G_R_STATUS);
2073         if (err < 0)
2074                 goto out;
2075         if (!(err & PCS_10G_R_STATUS_BLK_LOCK)) {
2076                 err = 0;
2077                 goto out;
2078         }
2079
2080         err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
2081                         BCM8704_PHYXS_XGXS_LANE_STAT);
2082         if (err < 0)
2083                 goto out;
2084
2085         if (err != (PHYXS_XGXS_LANE_STAT_ALINGED |
2086                     PHYXS_XGXS_LANE_STAT_MAGIC |
2087                     PHYXS_XGXS_LANE_STAT_LANE3 |
2088                     PHYXS_XGXS_LANE_STAT_LANE2 |
2089                     PHYXS_XGXS_LANE_STAT_LANE1 |
2090                     PHYXS_XGXS_LANE_STAT_LANE0)) {
2091                 err = 0;
2092                 goto out;
2093         }
2094
2095         link_up = 1;
2096         np->link_config.active_speed = SPEED_10000;
2097         np->link_config.active_duplex = DUPLEX_FULL;
2098         err = 0;
2099
2100 out:
2101         *link_up_p = link_up;
2102         return err;
2103 }
2104
2105 static int link_status_10g(struct niu *np, int *link_up_p)
2106 {
2107         unsigned long flags;
2108         int err = -EINVAL;
2109
2110         spin_lock_irqsave(&np->lock, flags);
2111
2112         if (np->link_config.loopback_mode == LOOPBACK_DISABLED) {
2113                 int phy_id;
2114
2115                 phy_id = phy_decode(np->parent->port_phy, np->port);
2116                 phy_id = np->parent->phy_probe_info.phy_id[phy_id][np->port];
2117
2118                 /* handle different phy types */
2119                 switch (phy_id & NIU_PHY_ID_MASK) {
2120                 case NIU_PHY_ID_MRVL88X2011:
2121                         err = link_status_10g_mrvl(np, link_up_p);
2122                         break;
2123
2124                 default: /* bcom 8704 */
2125                         err = link_status_10g_bcom(np, link_up_p);
2126                         break;
2127                 }
2128         }
2129
2130         spin_unlock_irqrestore(&np->lock, flags);
2131
2132         return err;
2133 }
2134
2135 static int niu_10g_phy_present(struct niu *np)
2136 {
2137         u64 sig, mask, val;
2138
2139         sig = nr64(ESR_INT_SIGNALS);
2140         switch (np->port) {
2141         case 0:
2142                 mask = ESR_INT_SIGNALS_P0_BITS;
2143                 val = (ESR_INT_SRDY0_P0 |
2144                        ESR_INT_DET0_P0 |
2145                        ESR_INT_XSRDY_P0 |
2146                        ESR_INT_XDP_P0_CH3 |
2147                        ESR_INT_XDP_P0_CH2 |
2148                        ESR_INT_XDP_P0_CH1 |
2149                        ESR_INT_XDP_P0_CH0);
2150                 break;
2151
2152         case 1:
2153                 mask = ESR_INT_SIGNALS_P1_BITS;
2154                 val = (ESR_INT_SRDY0_P1 |
2155                        ESR_INT_DET0_P1 |
2156                        ESR_INT_XSRDY_P1 |
2157                        ESR_INT_XDP_P1_CH3 |
2158                        ESR_INT_XDP_P1_CH2 |
2159                        ESR_INT_XDP_P1_CH1 |
2160                        ESR_INT_XDP_P1_CH0);
2161                 break;
2162
2163         default:
2164                 return 0;
2165         }
2166
2167         if ((sig & mask) != val)
2168                 return 0;
2169         return 1;
2170 }
2171
2172 static int link_status_10g_hotplug(struct niu *np, int *link_up_p)
2173 {
2174         unsigned long flags;
2175         int err = 0;
2176         int phy_present;
2177         int phy_present_prev;
2178
2179         spin_lock_irqsave(&np->lock, flags);
2180
2181         if (np->link_config.loopback_mode == LOOPBACK_DISABLED) {
2182                 phy_present_prev = (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) ?
2183                         1 : 0;
2184                 phy_present = niu_10g_phy_present(np);
2185                 if (phy_present != phy_present_prev) {
2186                         /* state change */
2187                         if (phy_present) {
2188                                 /* A NEM was just plugged in */
2189                                 np->flags |= NIU_FLAGS_HOTPLUG_PHY_PRESENT;
2190                                 if (np->phy_ops->xcvr_init)
2191                                         err = np->phy_ops->xcvr_init(np);
2192                                 if (err) {
2193                                         err = mdio_read(np, np->phy_addr,
2194                                                 BCM8704_PHYXS_DEV_ADDR, MII_BMCR);
2195                                         if (err == 0xffff) {
2196                                                 /* No mdio, back-to-back XAUI */
2197                                                 goto out;
2198                                         }
2199                                         /* debounce */
2200                                         np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT;
2201                                 }
2202                         } else {
2203                                 np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT;
2204                                 *link_up_p = 0;
2205                                 netif_warn(np, link, np->dev,
2206                                            "Hotplug PHY Removed\n");
2207                         }
2208                 }
2209 out:
2210                 if (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) {
2211                         err = link_status_10g_bcm8706(np, link_up_p);
2212                         if (err == 0xffff) {
2213                                 /* No mdio, back-to-back XAUI: it is C10NEM */
2214                                 *link_up_p = 1;
2215                                 np->link_config.active_speed = SPEED_10000;
2216                                 np->link_config.active_duplex = DUPLEX_FULL;
2217                         }
2218                 }
2219         }
2220
2221         spin_unlock_irqrestore(&np->lock, flags);
2222
2223         return 0;
2224 }
2225
2226 static int niu_link_status(struct niu *np, int *link_up_p)
2227 {
2228         const struct niu_phy_ops *ops = np->phy_ops;
2229         int err;
2230
2231         err = 0;
2232         if (ops->link_status)
2233                 err = ops->link_status(np, link_up_p);
2234
2235         return err;
2236 }
2237
2238 static void niu_timer(unsigned long __opaque)
2239 {
2240         struct niu *np = (struct niu *) __opaque;
2241         unsigned long off;
2242         int err, link_up;
2243
2244         err = niu_link_status(np, &link_up);
2245         if (!err)
2246                 niu_link_status_common(np, link_up);
2247
2248         if (netif_carrier_ok(np->dev))
2249                 off = 5 * HZ;
2250         else
2251                 off = 1 * HZ;
2252         np->timer.expires = jiffies + off;
2253
2254         add_timer(&np->timer);
2255 }
2256
2257 static const struct niu_phy_ops phy_ops_10g_serdes = {
2258         .serdes_init            = serdes_init_10g_serdes,
2259         .link_status            = link_status_10g_serdes,
2260 };
2261
2262 static const struct niu_phy_ops phy_ops_10g_serdes_niu = {
2263         .serdes_init            = serdes_init_niu_10g_serdes,
2264         .link_status            = link_status_10g_serdes,
2265 };
2266
2267 static const struct niu_phy_ops phy_ops_1g_serdes_niu = {
2268         .serdes_init            = serdes_init_niu_1g_serdes,
2269         .link_status            = link_status_1g_serdes,
2270 };
2271
2272 static const struct niu_phy_ops phy_ops_1g_rgmii = {
2273         .xcvr_init              = xcvr_init_1g_rgmii,
2274         .link_status            = link_status_1g_rgmii,
2275 };
2276
2277 static const struct niu_phy_ops phy_ops_10g_fiber_niu = {
2278         .serdes_init            = serdes_init_niu_10g_fiber,
2279         .xcvr_init              = xcvr_init_10g,
2280         .link_status            = link_status_10g,
2281 };
2282
2283 static const struct niu_phy_ops phy_ops_10g_fiber = {
2284         .serdes_init            = serdes_init_10g,
2285         .xcvr_init              = xcvr_init_10g,
2286         .link_status            = link_status_10g,
2287 };
2288
2289 static const struct niu_phy_ops phy_ops_10g_fiber_hotplug = {
2290         .serdes_init            = serdes_init_10g,
2291         .xcvr_init              = xcvr_init_10g_bcm8706,
2292         .link_status            = link_status_10g_hotplug,
2293 };
2294
2295 static const struct niu_phy_ops phy_ops_niu_10g_hotplug = {
2296         .serdes_init            = serdes_init_niu_10g_fiber,
2297         .xcvr_init              = xcvr_init_10g_bcm8706,
2298         .link_status            = link_status_10g_hotplug,
2299 };
2300
2301 static const struct niu_phy_ops phy_ops_10g_copper = {
2302         .serdes_init            = serdes_init_10g,
2303         .link_status            = link_status_10g, /* XXX */
2304 };
2305
2306 static const struct niu_phy_ops phy_ops_1g_fiber = {
2307         .serdes_init            = serdes_init_1g,
2308         .xcvr_init              = xcvr_init_1g,
2309         .link_status            = link_status_1g,
2310 };
2311
2312 static const struct niu_phy_ops phy_ops_1g_copper = {
2313         .xcvr_init              = xcvr_init_1g,
2314         .link_status            = link_status_1g,
2315 };
2316
2317 struct niu_phy_template {
2318         const struct niu_phy_ops        *ops;
2319         u32                             phy_addr_base;
2320 };
2321
2322 static const struct niu_phy_template phy_template_niu_10g_fiber = {
2323         .ops            = &phy_ops_10g_fiber_niu,
2324         .phy_addr_base  = 16,
2325 };
2326
2327 static const struct niu_phy_template phy_template_niu_10g_serdes = {
2328         .ops            = &phy_ops_10g_serdes_niu,
2329         .phy_addr_base  = 0,
2330 };
2331
2332 static const struct niu_phy_template phy_template_niu_1g_serdes = {
2333         .ops            = &phy_ops_1g_serdes_niu,
2334         .phy_addr_base  = 0,
2335 };
2336
2337 static const struct niu_phy_template phy_template_10g_fiber = {
2338         .ops            = &phy_ops_10g_fiber,
2339         .phy_addr_base  = 8,
2340 };
2341
2342 static const struct niu_phy_template phy_template_10g_fiber_hotplug = {
2343         .ops            = &phy_ops_10g_fiber_hotplug,
2344         .phy_addr_base  = 8,
2345 };
2346
2347 static const struct niu_phy_template phy_template_niu_10g_hotplug = {
2348         .ops            = &phy_ops_niu_10g_hotplug,
2349         .phy_addr_base  = 8,
2350 };
2351
2352 static const struct niu_phy_template phy_template_10g_copper = {
2353         .ops            = &phy_ops_10g_copper,
2354         .phy_addr_base  = 10,
2355 };
2356
2357 static const struct niu_phy_template phy_template_1g_fiber = {
2358         .ops            = &phy_ops_1g_fiber,
2359         .phy_addr_base  = 0,
2360 };
2361
2362 static const struct niu_phy_template phy_template_1g_copper = {
2363         .ops            = &phy_ops_1g_copper,
2364         .phy_addr_base  = 0,
2365 };
2366
2367 static const struct niu_phy_template phy_template_1g_rgmii = {
2368         .ops            = &phy_ops_1g_rgmii,
2369         .phy_addr_base  = 0,
2370 };
2371
2372 static const struct niu_phy_template phy_template_10g_serdes = {
2373         .ops            = &phy_ops_10g_serdes,
2374         .phy_addr_base  = 0,
2375 };
2376
2377 static int niu_atca_port_num[4] = {
2378         0, 0,  11, 10
2379 };
2380
2381 static int serdes_init_10g_serdes(struct niu *np)
2382 {
2383         struct niu_link_config *lp = &np->link_config;
2384         unsigned long ctrl_reg, test_cfg_reg, pll_cfg, i;
2385         u64 ctrl_val, test_cfg_val, sig, mask, val;
2386         u64 reset_val;
2387
2388         switch (np->port) {
2389         case 0:
2390                 reset_val =  ENET_SERDES_RESET_0;
2391                 ctrl_reg = ENET_SERDES_0_CTRL_CFG;
2392                 test_cfg_reg = ENET_SERDES_0_TEST_CFG;
2393                 pll_cfg = ENET_SERDES_0_PLL_CFG;
2394                 break;
2395         case 1:
2396                 reset_val =  ENET_SERDES_RESET_1;
2397                 ctrl_reg = ENET_SERDES_1_CTRL_CFG;
2398                 test_cfg_reg = ENET_SERDES_1_TEST_CFG;
2399                 pll_cfg = ENET_SERDES_1_PLL_CFG;
2400                 break;
2401
2402         default:
2403                 return -EINVAL;
2404         }
2405         ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
2406                     ENET_SERDES_CTRL_SDET_1 |
2407                     ENET_SERDES_CTRL_SDET_2 |
2408                     ENET_SERDES_CTRL_SDET_3 |
2409                     (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
2410                     (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
2411                     (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
2412                     (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
2413                     (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
2414                     (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
2415                     (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
2416                     (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
2417         test_cfg_val = 0;
2418
2419         if (lp->loopback_mode == LOOPBACK_PHY) {
2420                 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
2421                                   ENET_SERDES_TEST_MD_0_SHIFT) |
2422                                  (ENET_TEST_MD_PAD_LOOPBACK <<
2423                                   ENET_SERDES_TEST_MD_1_SHIFT) |
2424                                  (ENET_TEST_MD_PAD_LOOPBACK <<
2425                                   ENET_SERDES_TEST_MD_2_SHIFT) |
2426                                  (ENET_TEST_MD_PAD_LOOPBACK <<
2427                                   ENET_SERDES_TEST_MD_3_SHIFT));
2428         }
2429
2430         esr_reset(np);
2431         nw64(pll_cfg, ENET_SERDES_PLL_FBDIV2);
2432         nw64(ctrl_reg, ctrl_val);
2433         nw64(test_cfg_reg, test_cfg_val);
2434
2435         /* Initialize all 4 lanes of the SERDES.  */
2436         for (i = 0; i < 4; i++) {
2437                 u32 rxtx_ctrl, glue0;
2438                 int err;
2439
2440                 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
2441                 if (err)
2442                         return err;
2443                 err = esr_read_glue0(np, i, &glue0);
2444                 if (err)
2445                         return err;
2446
2447                 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
2448                 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
2449                               (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
2450
2451                 glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
2452                            ESR_GLUE_CTRL0_THCNT |
2453                            ESR_GLUE_CTRL0_BLTIME);
2454                 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
2455                           (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
2456                           (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
2457                           (BLTIME_300_CYCLES <<
2458                            ESR_GLUE_CTRL0_BLTIME_SHIFT));
2459
2460                 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
2461                 if (err)
2462                         return err;
2463                 err = esr_write_glue0(np, i, glue0);
2464                 if (err)
2465                         return err;
2466         }
2467
2468
2469         sig = nr64(ESR_INT_SIGNALS);
2470         switch (np->port) {
2471         case 0:
2472                 mask = ESR_INT_SIGNALS_P0_BITS;
2473                 val = (ESR_INT_SRDY0_P0 |
2474                        ESR_INT_DET0_P0 |
2475                        ESR_INT_XSRDY_P0 |
2476                        ESR_INT_XDP_P0_CH3 |
2477                        ESR_INT_XDP_P0_CH2 |
2478                        ESR_INT_XDP_P0_CH1 |
2479                        ESR_INT_XDP_P0_CH0);
2480                 break;
2481
2482         case 1:
2483                 mask = ESR_INT_SIGNALS_P1_BITS;
2484                 val = (ESR_INT_SRDY0_P1 |
2485                        ESR_INT_DET0_P1 |
2486                        ESR_INT_XSRDY_P1 |
2487                        ESR_INT_XDP_P1_CH3 |
2488                        ESR_INT_XDP_P1_CH2 |
2489                        ESR_INT_XDP_P1_CH1 |
2490                        ESR_INT_XDP_P1_CH0);
2491                 break;
2492
2493         default:
2494                 return -EINVAL;
2495         }
2496
2497         if ((sig & mask) != val) {
2498                 int err;
2499                 err = serdes_init_1g_serdes(np);
2500                 if (!err) {
2501                         np->flags &= ~NIU_FLAGS_10G;
2502                         np->mac_xcvr = MAC_XCVR_PCS;
2503                 }  else {
2504                         netdev_err(np->dev, "Port %u 10G/1G SERDES Link Failed\n",
2505                                    np->port);
2506                         return -ENODEV;
2507                 }
2508         }
2509
2510         return 0;
2511 }
2512
2513 static int niu_determine_phy_disposition(struct niu *np)
2514 {
2515         struct niu_parent *parent = np->parent;
2516         u8 plat_type = parent->plat_type;
2517         const struct niu_phy_template *tp;
2518         u32 phy_addr_off = 0;
2519
2520         if (plat_type == PLAT_TYPE_NIU) {
2521                 switch (np->flags &
2522                         (NIU_FLAGS_10G |
2523                          NIU_FLAGS_FIBER |
2524                          NIU_FLAGS_XCVR_SERDES)) {
2525                 case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES:
2526                         /* 10G Serdes */
2527                         tp = &phy_template_niu_10g_serdes;
2528                         break;
2529                 case NIU_FLAGS_XCVR_SERDES:
2530                         /* 1G Serdes */
2531                         tp = &phy_template_niu_1g_serdes;
2532                         break;
2533                 case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
2534                         /* 10G Fiber */
2535                 default:
2536                         if (np->flags & NIU_FLAGS_HOTPLUG_PHY) {
2537                                 tp = &phy_template_niu_10g_hotplug;
2538                                 if (np->port == 0)
2539                                         phy_addr_off = 8;
2540                                 if (np->port == 1)
2541                                         phy_addr_off = 12;
2542                         } else {
2543                                 tp = &phy_template_niu_10g_fiber;
2544                                 phy_addr_off += np->port;
2545                         }
2546                         break;
2547                 }
2548         } else {
2549                 switch (np->flags &
2550                         (NIU_FLAGS_10G |
2551                          NIU_FLAGS_FIBER |
2552                          NIU_FLAGS_XCVR_SERDES)) {
2553                 case 0:
2554                         /* 1G copper */
2555                         tp = &phy_template_1g_copper;
2556                         if (plat_type == PLAT_TYPE_VF_P0)
2557                                 phy_addr_off = 10;
2558                         else if (plat_type == PLAT_TYPE_VF_P1)
2559                                 phy_addr_off = 26;
2560
2561                         phy_addr_off += (np->port ^ 0x3);
2562                         break;
2563
2564                 case NIU_FLAGS_10G:
2565                         /* 10G copper */
2566                         tp = &phy_template_10g_copper;
2567                         break;
2568
2569                 case NIU_FLAGS_FIBER:
2570                         /* 1G fiber */
2571                         tp = &phy_template_1g_fiber;
2572                         break;
2573
2574                 case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
2575                         /* 10G fiber */
2576                         tp = &phy_template_10g_fiber;
2577                         if (plat_type == PLAT_TYPE_VF_P0 ||
2578                             plat_type == PLAT_TYPE_VF_P1)
2579                                 phy_addr_off = 8;
2580                         phy_addr_off += np->port;
2581                         if (np->flags & NIU_FLAGS_HOTPLUG_PHY) {
2582                                 tp = &phy_template_10g_fiber_hotplug;
2583                                 if (np->port == 0)
2584                                         phy_addr_off = 8;
2585                                 if (np->port == 1)
2586                                         phy_addr_off = 12;
2587                         }
2588                         break;
2589
2590                 case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES:
2591                 case NIU_FLAGS_XCVR_SERDES | NIU_FLAGS_FIBER:
2592                 case NIU_FLAGS_XCVR_SERDES:
2593                         switch(np->port) {
2594                         case 0:
2595                         case 1:
2596                                 tp = &phy_template_10g_serdes;
2597                                 break;
2598                         case 2:
2599                         case 3:
2600                                 tp = &phy_template_1g_rgmii;
2601                                 break;
2602                         default:
2603                                 return -EINVAL;
2604                                 break;
2605                         }
2606                         phy_addr_off = niu_atca_port_num[np->port];
2607                         break;
2608
2609                 default:
2610                         return -EINVAL;
2611                 }
2612         }
2613
2614         np->phy_ops = tp->ops;
2615         np->phy_addr = tp->phy_addr_base + phy_addr_off;
2616
2617         return 0;
2618 }
2619
2620 static int niu_init_link(struct niu *np)
2621 {
2622         struct niu_parent *parent = np->parent;
2623         int err, ignore;
2624
2625         if (parent->plat_type == PLAT_TYPE_NIU) {
2626                 err = niu_xcvr_init(np);
2627                 if (err)
2628                         return err;
2629                 msleep(200);
2630         }
2631         err = niu_serdes_init(np);
2632         if (err && !(np->flags & NIU_FLAGS_HOTPLUG_PHY))
2633                 return err;
2634         msleep(200);
2635         err = niu_xcvr_init(np);
2636         if (!err || (np->flags & NIU_FLAGS_HOTPLUG_PHY))
2637                 niu_link_status(np, &ignore);
2638         return 0;
2639 }
2640
2641 static void niu_set_primary_mac(struct niu *np, unsigned char *addr)
2642 {
2643         u16 reg0 = addr[4] << 8 | addr[5];
2644         u16 reg1 = addr[2] << 8 | addr[3];
2645         u16 reg2 = addr[0] << 8 | addr[1];
2646
2647         if (np->flags & NIU_FLAGS_XMAC) {
2648                 nw64_mac(XMAC_ADDR0, reg0);
2649                 nw64_mac(XMAC_ADDR1, reg1);
2650                 nw64_mac(XMAC_ADDR2, reg2);
2651         } else {
2652                 nw64_mac(BMAC_ADDR0, reg0);
2653                 nw64_mac(BMAC_ADDR1, reg1);
2654                 nw64_mac(BMAC_ADDR2, reg2);
2655         }
2656 }
2657
2658 static int niu_num_alt_addr(struct niu *np)
2659 {
2660         if (np->flags & NIU_FLAGS_XMAC)
2661                 return XMAC_NUM_ALT_ADDR;
2662         else
2663                 return BMAC_NUM_ALT_ADDR;
2664 }
2665
2666 static int niu_set_alt_mac(struct niu *np, int index, unsigned char *addr)
2667 {
2668         u16 reg0 = addr[4] << 8 | addr[5];
2669         u16 reg1 = addr[2] << 8 | addr[3];
2670         u16 reg2 = addr[0] << 8 | addr[1];
2671
2672         if (index >= niu_num_alt_addr(np))
2673                 return -EINVAL;
2674
2675         if (np->flags & NIU_FLAGS_XMAC) {
2676                 nw64_mac(XMAC_ALT_ADDR0(index), reg0);
2677                 nw64_mac(XMAC_ALT_ADDR1(index), reg1);
2678                 nw64_mac(XMAC_ALT_ADDR2(index), reg2);
2679         } else {
2680                 nw64_mac(BMAC_ALT_ADDR0(index), reg0);
2681                 nw64_mac(BMAC_ALT_ADDR1(index), reg1);
2682                 nw64_mac(BMAC_ALT_ADDR2(index), reg2);
2683         }
2684
2685         return 0;
2686 }
2687
2688 static int niu_enable_alt_mac(struct niu *np, int index, int on)
2689 {
2690         unsigned long reg;
2691         u64 val, mask;
2692
2693         if (index >= niu_num_alt_addr(np))
2694                 return -EINVAL;
2695
2696         if (np->flags & NIU_FLAGS_XMAC) {
2697                 reg = XMAC_ADDR_CMPEN;
2698                 mask = 1 << index;
2699         } else {
2700                 reg = BMAC_ADDR_CMPEN;
2701                 mask = 1 << (index + 1);
2702         }
2703
2704         val = nr64_mac(reg);
2705         if (on)
2706                 val |= mask;
2707         else
2708                 val &= ~mask;
2709         nw64_mac(reg, val);
2710
2711         return 0;
2712 }
2713
2714 static void __set_rdc_table_num_hw(struct niu *np, unsigned long reg,
2715                                    int num, int mac_pref)
2716 {
2717         u64 val = nr64_mac(reg);
2718         val &= ~(HOST_INFO_MACRDCTBLN | HOST_INFO_MPR);
2719         val |= num;
2720         if (mac_pref)
2721                 val |= HOST_INFO_MPR;
2722         nw64_mac(reg, val);
2723 }
2724
2725 static int __set_rdc_table_num(struct niu *np,
2726                                int xmac_index, int bmac_index,
2727                                int rdc_table_num, int mac_pref)
2728 {
2729         unsigned long reg;
2730
2731         if (rdc_table_num & ~HOST_INFO_MACRDCTBLN)
2732                 return -EINVAL;
2733         if (np->flags & NIU_FLAGS_XMAC)
2734                 reg = XMAC_HOST_INFO(xmac_index);
2735         else
2736                 reg = BMAC_HOST_INFO(bmac_index);
2737         __set_rdc_table_num_hw(np, reg, rdc_table_num, mac_pref);
2738         return 0;
2739 }
2740
2741 static int niu_set_primary_mac_rdc_table(struct niu *np, int table_num,
2742                                          int mac_pref)
2743 {
2744         return __set_rdc_table_num(np, 17, 0, table_num, mac_pref);
2745 }
2746
2747 static int niu_set_multicast_mac_rdc_table(struct niu *np, int table_num,
2748                                            int mac_pref)
2749 {
2750         return __set_rdc_table_num(np, 16, 8, table_num, mac_pref);
2751 }
2752
2753 static int niu_set_alt_mac_rdc_table(struct niu *np, int idx,
2754                                      int table_num, int mac_pref)
2755 {
2756         if (idx >= niu_num_alt_addr(np))
2757                 return -EINVAL;
2758         return __set_rdc_table_num(np, idx, idx + 1, table_num, mac_pref);
2759 }
2760
2761 static u64 vlan_entry_set_parity(u64 reg_val)
2762 {
2763         u64 port01_mask;
2764         u64 port23_mask;
2765
2766         port01_mask = 0x00ff;
2767         port23_mask = 0xff00;
2768
2769         if (hweight64(reg_val & port01_mask) & 1)
2770                 reg_val |= ENET_VLAN_TBL_PARITY0;
2771         else
2772                 reg_val &= ~ENET_VLAN_TBL_PARITY0;
2773
2774         if (hweight64(reg_val & port23_mask) & 1)
2775                 reg_val |= ENET_VLAN_TBL_PARITY1;
2776         else
2777                 reg_val &= ~ENET_VLAN_TBL_PARITY1;
2778
2779         return reg_val;
2780 }
2781
2782 static void vlan_tbl_write(struct niu *np, unsigned long index,
2783                            int port, int vpr, int rdc_table)
2784 {
2785         u64 reg_val = nr64(ENET_VLAN_TBL(index));
2786
2787         reg_val &= ~((ENET_VLAN_TBL_VPR |
2788                       ENET_VLAN_TBL_VLANRDCTBLN) <<
2789                      ENET_VLAN_TBL_SHIFT(port));
2790         if (vpr)
2791                 reg_val |= (ENET_VLAN_TBL_VPR <<
2792                             ENET_VLAN_TBL_SHIFT(port));
2793         reg_val |= (rdc_table << ENET_VLAN_TBL_SHIFT(port));
2794
2795         reg_val = vlan_entry_set_parity(reg_val);
2796
2797         nw64(ENET_VLAN_TBL(index), reg_val);
2798 }
2799
2800 static void vlan_tbl_clear(struct niu *np)
2801 {
2802         int i;
2803
2804         for (i = 0; i < ENET_VLAN_TBL_NUM_ENTRIES; i++)
2805                 nw64(ENET_VLAN_TBL(i), 0);
2806 }
2807
2808 static int tcam_wait_bit(struct niu *np, u64 bit)
2809 {
2810         int limit = 1000;
2811
2812         while (--limit > 0) {
2813                 if (nr64(TCAM_CTL) & bit)
2814                         break;
2815                 udelay(1);
2816         }
2817         if (limit <= 0)
2818                 return -ENODEV;
2819
2820         return 0;
2821 }
2822
2823 static int tcam_flush(struct niu *np, int index)
2824 {
2825         nw64(TCAM_KEY_0, 0x00);
2826         nw64(TCAM_KEY_MASK_0, 0xff);
2827         nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_WRITE | index));
2828
2829         return tcam_wait_bit(np, TCAM_CTL_STAT);
2830 }
2831
2832 #if 0
2833 static int tcam_read(struct niu *np, int index,
2834                      u64 *key, u64 *mask)
2835 {
2836         int err;
2837
2838         nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_READ | index));
2839         err = tcam_wait_bit(np, TCAM_CTL_STAT);
2840         if (!err) {
2841                 key[0] = nr64(TCAM_KEY_0);
2842                 key[1] = nr64(TCAM_KEY_1);
2843                 key[2] = nr64(TCAM_KEY_2);
2844                 key[3] = nr64(TCAM_KEY_3);
2845                 mask[0] = nr64(TCAM_KEY_MASK_0);
2846                 mask[1] = nr64(TCAM_KEY_MASK_1);
2847                 mask[2] = nr64(TCAM_KEY_MASK_2);
2848                 mask[3] = nr64(TCAM_KEY_MASK_3);
2849         }
2850         return err;
2851 }
2852 #endif
2853
2854 static int tcam_write(struct niu *np, int index,
2855                       u64 *key, u64 *mask)
2856 {
2857         nw64(TCAM_KEY_0, key[0]);
2858         nw64(TCAM_KEY_1, key[1]);
2859         nw64(TCAM_KEY_2, key[2]);
2860         nw64(TCAM_KEY_3, key[3]);
2861         nw64(TCAM_KEY_MASK_0, mask[0]);
2862         nw64(TCAM_KEY_MASK_1, mask[1]);
2863         nw64(TCAM_KEY_MASK_2, mask[2]);
2864         nw64(TCAM_KEY_MASK_3, mask[3]);
2865         nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_WRITE | index));
2866
2867         return tcam_wait_bit(np, TCAM_CTL_STAT);
2868 }
2869
2870 #if 0
2871 static int tcam_assoc_read(struct niu *np, int index, u64 *data)
2872 {
2873         int err;
2874
2875         nw64(TCAM_CTL, (TCAM_CTL_RWC_RAM_READ | index));
2876         err = tcam_wait_bit(np, TCAM_CTL_STAT);
2877         if (!err)
2878                 *data = nr64(TCAM_KEY_1);
2879
2880         return err;
2881 }
2882 #endif
2883
2884 static int tcam_assoc_write(struct niu *np, int index, u64 assoc_data)
2885 {
2886         nw64(TCAM_KEY_1, assoc_data);
2887         nw64(TCAM_CTL, (TCAM_CTL_RWC_RAM_WRITE | index));
2888
2889         return tcam_wait_bit(np, TCAM_CTL_STAT);
2890 }
2891
2892 static void tcam_enable(struct niu *np, int on)
2893 {
2894         u64 val = nr64(FFLP_CFG_1);
2895
2896         if (on)
2897                 val &= ~FFLP_CFG_1_TCAM_DIS;
2898         else
2899                 val |= FFLP_CFG_1_TCAM_DIS;
2900         nw64(FFLP_CFG_1, val);
2901 }
2902
2903 static void tcam_set_lat_and_ratio(struct niu *np, u64 latency, u64 ratio)
2904 {
2905         u64 val = nr64(FFLP_CFG_1);
2906
2907         val &= ~(FFLP_CFG_1_FFLPINITDONE |
2908                  FFLP_CFG_1_CAMLAT |
2909                  FFLP_CFG_1_CAMRATIO);
2910         val |= (latency << FFLP_CFG_1_CAMLAT_SHIFT);
2911         val |= (ratio << FFLP_CFG_1_CAMRATIO_SHIFT);
2912         nw64(FFLP_CFG_1, val);
2913
2914         val = nr64(FFLP_CFG_1);
2915         val |= FFLP_CFG_1_FFLPINITDONE;
2916         nw64(FFLP_CFG_1, val);
2917 }
2918
2919 static int tcam_user_eth_class_enable(struct niu *np, unsigned long class,
2920                                       int on)
2921 {
2922         unsigned long reg;
2923         u64 val;
2924
2925         if (class < CLASS_CODE_ETHERTYPE1 ||
2926             class > CLASS_CODE_ETHERTYPE2)
2927                 return -EINVAL;
2928
2929         reg = L2_CLS(class - CLASS_CODE_ETHERTYPE1);
2930         val = nr64(reg);
2931         if (on)
2932                 val |= L2_CLS_VLD;
2933         else
2934                 val &= ~L2_CLS_VLD;
2935         nw64(reg, val);
2936
2937         return 0;
2938 }
2939
2940 #if 0
2941 static int tcam_user_eth_class_set(struct niu *np, unsigned long class,
2942                                    u64 ether_type)
2943 {
2944         unsigned long reg;
2945         u64 val;
2946
2947         if (class < CLASS_CODE_ETHERTYPE1 ||
2948             class > CLASS_CODE_ETHERTYPE2 ||
2949             (ether_type & ~(u64)0xffff) != 0)
2950                 return -EINVAL;
2951
2952         reg = L2_CLS(class - CLASS_CODE_ETHERTYPE1);
2953         val = nr64(reg);
2954         val &= ~L2_CLS_ETYPE;
2955         val |= (ether_type << L2_CLS_ETYPE_SHIFT);
2956         nw64(reg, val);
2957
2958         return 0;
2959 }
2960 #endif
2961
2962 static int tcam_user_ip_class_enable(struct niu *np, unsigned long class,
2963                                      int on)
2964 {
2965         unsigned long reg;
2966         u64 val;
2967
2968         if (class < CLASS_CODE_USER_PROG1 ||
2969             class > CLASS_CODE_USER_PROG4)
2970                 return -EINVAL;
2971
2972         reg = L3_CLS(class - CLASS_CODE_USER_PROG1);
2973         val = nr64(reg);
2974         if (on)
2975                 val |= L3_CLS_VALID;
2976         else
2977                 val &= ~L3_CLS_VALID;
2978         nw64(reg, val);
2979
2980         return 0;
2981 }
2982
2983 static int tcam_user_ip_class_set(struct niu *np, unsigned long class,
2984                                   int ipv6, u64 protocol_id,
2985                                   u64 tos_mask, u64 tos_val)
2986 {
2987         unsigned long reg;
2988         u64 val;
2989
2990         if (class < CLASS_CODE_USER_PROG1 ||
2991             class > CLASS_CODE_USER_PROG4 ||
2992             (protocol_id & ~(u64)0xff) != 0 ||
2993             (tos_mask & ~(u64)0xff) != 0 ||
2994             (tos_val & ~(u64)0xff) != 0)
2995                 return -EINVAL;
2996
2997         reg = L3_CLS(class - CLASS_CODE_USER_PROG1);
2998         val = nr64(reg);
2999         val &= ~(L3_CLS_IPVER | L3_CLS_PID |
3000                  L3_CLS_TOSMASK | L3_CLS_TOS);
3001         if (ipv6)
3002                 val |= L3_CLS_IPVER;
3003         val |= (protocol_id << L3_CLS_PID_SHIFT);
3004         val |= (tos_mask << L3_CLS_TOSMASK_SHIFT);
3005         val |= (tos_val << L3_CLS_TOS_SHIFT);
3006         nw64(reg, val);
3007
3008         return 0;
3009 }
3010
3011 static int tcam_early_init(struct niu *np)
3012 {
3013         unsigned long i;
3014         int err;
3015
3016         tcam_enable(np, 0);
3017         tcam_set_lat_and_ratio(np,
3018                                DEFAULT_TCAM_LATENCY,
3019                                DEFAULT_TCAM_ACCESS_RATIO);
3020         for (i = CLASS_CODE_ETHERTYPE1; i <= CLASS_CODE_ETHERTYPE2; i++) {
3021                 err = tcam_user_eth_class_enable(np, i, 0);
3022                 if (err)
3023                         return err;
3024         }
3025         for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_USER_PROG4; i++) {
3026                 err = tcam_user_ip_class_enable(np, i, 0);
3027                 if (err)
3028                         return err;
3029         }
3030
3031         return 0;
3032 }
3033
3034 static int tcam_flush_all(struct niu *np)
3035 {
3036         unsigned long i;
3037
3038         for (i = 0; i < np->parent->tcam_num_entries; i++) {
3039                 int err = tcam_flush(np, i);
3040                 if (err)
3041                         return err;
3042         }
3043         return 0;
3044 }
3045
3046 static u64 hash_addr_regval(unsigned long index, unsigned long num_entries)
3047 {
3048         return ((u64)index | (num_entries == 1 ?
3049                               HASH_TBL_ADDR_AUTOINC : 0));
3050 }
3051
3052 #if 0
3053 static int hash_read(struct niu *np, unsigned long partition,
3054                      unsigned long index, unsigned long num_entries,
3055                      u64 *data)
3056 {
3057         u64 val = hash_addr_regval(index, num_entries);
3058         unsigned long i;
3059
3060         if (partition >= FCRAM_NUM_PARTITIONS ||
3061             index + num_entries > FCRAM_SIZE)
3062                 return -EINVAL;
3063
3064         nw64(HASH_TBL_ADDR(partition), val);
3065         for (i = 0; i < num_entries; i++)
3066                 data[i] = nr64(HASH_TBL_DATA(partition));
3067
3068         return 0;
3069 }
3070 #endif
3071
3072 static int hash_write(struct niu *np, unsigned long partition,
3073                       unsigned long index, unsigned long num_entries,
3074                       u64 *data)
3075 {
3076         u64 val = hash_addr_regval(index, num_entries);
3077         unsigned long i;
3078
3079         if (partition >= FCRAM_NUM_PARTITIONS ||
3080             index + (num_entries * 8) > FCRAM_SIZE)
3081                 return -EINVAL;
3082
3083         nw64(HASH_TBL_ADDR(partition), val);
3084         for (i = 0; i < num_entries; i++)
3085                 nw64(HASH_TBL_DATA(partition), data[i]);
3086
3087         return 0;
3088 }
3089
3090 static void fflp_reset(struct niu *np)
3091 {
3092         u64 val;
3093
3094         nw64(FFLP_CFG_1, FFLP_CFG_1_PIO_FIO_RST);
3095         udelay(10);
3096         nw64(FFLP_CFG_1, 0);
3097
3098         val = FFLP_CFG_1_FCRAMOUTDR_NORMAL | FFLP_CFG_1_FFLPINITDONE;
3099         nw64(FFLP_CFG_1, val);
3100 }
3101
3102 static void fflp_set_timings(struct niu *np)
3103 {
3104         u64 val = nr64(FFLP_CFG_1);
3105
3106         val &= ~FFLP_CFG_1_FFLPINITDONE;
3107         val |= (DEFAULT_FCRAMRATIO << FFLP_CFG_1_FCRAMRATIO_SHIFT);
3108         nw64(FFLP_CFG_1, val);
3109
3110         val = nr64(FFLP_CFG_1);
3111         val |= FFLP_CFG_1_FFLPINITDONE;
3112         nw64(FFLP_CFG_1, val);
3113
3114         val = nr64(FCRAM_REF_TMR);
3115         val &= ~(FCRAM_REF_TMR_MAX | FCRAM_REF_TMR_MIN);
3116         val |= (DEFAULT_FCRAM_REFRESH_MAX << FCRAM_REF_TMR_MAX_SHIFT);
3117         val |= (DEFAULT_FCRAM_REFRESH_MIN << FCRAM_REF_TMR_MIN_SHIFT);
3118         nw64(FCRAM_REF_TMR, val);
3119 }
3120
3121 static int fflp_set_partition(struct niu *np, u64 partition,
3122                               u64 mask, u64 base, int enable)
3123 {
3124         unsigned long reg;
3125         u64 val;
3126
3127         if (partition >= FCRAM_NUM_PARTITIONS ||
3128             (mask & ~(u64)0x1f) != 0 ||
3129             (base & ~(u64)0x1f) != 0)
3130                 return -EINVAL;
3131
3132         reg = FLW_PRT_SEL(partition);
3133
3134         val = nr64(reg);
3135         val &= ~(FLW_PRT_SEL_EXT | FLW_PRT_SEL_MASK | FLW_PRT_SEL_BASE);
3136         val |= (mask << FLW_PRT_SEL_MASK_SHIFT);
3137         val |= (base << FLW_PRT_SEL_BASE_SHIFT);
3138         if (enable)
3139                 val |= FLW_PRT_SEL_EXT;
3140         nw64(reg, val);
3141
3142         return 0;
3143 }
3144
3145 static int fflp_disable_all_partitions(struct niu *np)
3146 {
3147         unsigned long i;
3148
3149         for (i = 0; i < FCRAM_NUM_PARTITIONS; i++) {
3150                 int err = fflp_set_partition(np, 0, 0, 0, 0);
3151                 if (err)
3152                         return err;
3153         }
3154         return 0;
3155 }
3156
3157 static void fflp_llcsnap_enable(struct niu *np, int on)
3158 {
3159         u64 val = nr64(FFLP_CFG_1);
3160
3161         if (on)
3162                 val |= FFLP_CFG_1_LLCSNAP;
3163         else
3164                 val &= ~FFLP_CFG_1_LLCSNAP;
3165         nw64(FFLP_CFG_1, val);
3166 }
3167
3168 static void fflp_errors_enable(struct niu *np, int on)
3169 {
3170         u64 val = nr64(FFLP_CFG_1);
3171
3172         if (on)
3173                 val &= ~FFLP_CFG_1_ERRORDIS;
3174         else
3175                 val |= FFLP_CFG_1_ERRORDIS;
3176         nw64(FFLP_CFG_1, val);
3177 }
3178
3179 static int fflp_hash_clear(struct niu *np)
3180 {
3181         struct fcram_hash_ipv4 ent;
3182         unsigned long i;
3183
3184         /* IPV4 hash entry with valid bit clear, rest is don't care.  */
3185         memset(&ent, 0, sizeof(ent));
3186         ent.header = HASH_HEADER_EXT;
3187
3188         for (i = 0; i < FCRAM_SIZE; i += sizeof(ent)) {
3189                 int err = hash_write(np, 0, i, 1, (u64 *) &ent);
3190                 if (err)
3191                         return err;
3192         }
3193         return 0;
3194 }
3195
3196 static int fflp_early_init(struct niu *np)
3197 {
3198         struct niu_parent *parent;
3199         unsigned long flags;
3200         int err;
3201
3202         niu_lock_parent(np, flags);
3203
3204         parent = np->parent;
3205         err = 0;
3206         if (!(parent->flags & PARENT_FLGS_CLS_HWINIT)) {
3207                 if (np->parent->plat_type != PLAT_TYPE_NIU) {
3208                         fflp_reset(np);
3209                         fflp_set_timings(np);
3210                         err = fflp_disable_all_partitions(np);
3211                         if (err) {
3212                                 netif_printk(np, probe, KERN_DEBUG, np->dev,
3213                                              "fflp_disable_all_partitions failed, err=%d\n",
3214                                              err);
3215                                 goto out;
3216                         }
3217                 }
3218
3219                 err = tcam_early_init(np);
3220                 if (err) {
3221                         netif_printk(np, probe, KERN_DEBUG, np->dev,
3222                                      "tcam_early_init failed, err=%d\n", err);
3223                         goto out;
3224                 }
3225                 fflp_llcsnap_enable(np, 1);
3226                 fflp_errors_enable(np, 0);
3227                 nw64(H1POLY, 0);
3228                 nw64(H2POLY, 0);
3229
3230                 err = tcam_flush_all(np);
3231                 if (err) {
3232                         netif_printk(np, probe, KERN_DEBUG, np->dev,
3233                                      "tcam_flush_all failed, err=%d\n", err);
3234                         goto out;
3235                 }
3236                 if (np->parent->plat_type != PLAT_TYPE_NIU) {
3237                         err = fflp_hash_clear(np);
3238                         if (err) {
3239                                 netif_printk(np, probe, KERN_DEBUG, np->dev,
3240                                              "fflp_hash_clear failed, err=%d\n",
3241                                              err);
3242                                 goto out;
3243                         }
3244                 }
3245
3246                 vlan_tbl_clear(np);
3247
3248                 parent->flags |= PARENT_FLGS_CLS_HWINIT;
3249         }
3250 out:
3251         niu_unlock_parent(np, flags);
3252         return err;
3253 }
3254
3255 static int niu_set_flow_key(struct niu *np, unsigned long class_code, u64 key)
3256 {
3257         if (class_code < CLASS_CODE_USER_PROG1 ||
3258             class_code > CLASS_CODE_SCTP_IPV6)
3259                 return -EINVAL;
3260
3261         nw64(FLOW_KEY(class_code - CLASS_CODE_USER_PROG1), key);
3262         return 0;
3263 }
3264
3265 static int niu_set_tcam_key(struct niu *np, unsigned long class_code, u64 key)
3266 {
3267         if (class_code < CLASS_CODE_USER_PROG1 ||
3268             class_code > CLASS_CODE_SCTP_IPV6)
3269                 return -EINVAL;
3270
3271         nw64(TCAM_KEY(class_code - CLASS_CODE_USER_PROG1), key);
3272         return 0;
3273 }
3274
3275 /* Entries for the ports are interleaved in the TCAM */
3276 static u16 tcam_get_index(struct niu *np, u16 idx)
3277 {
3278         /* One entry reserved for IP fragment rule */
3279         if (idx >= (np->clas.tcam_sz - 1))
3280                 idx = 0;
3281         return (np->clas.tcam_top + ((idx+1) * np->parent->num_ports));
3282 }
3283
3284 static u16 tcam_get_size(struct niu *np)
3285 {
3286         /* One entry reserved for IP fragment rule */
3287         return np->clas.tcam_sz - 1;
3288 }
3289
3290 static u16 tcam_get_valid_entry_cnt(struct niu *np)
3291 {
3292         /* One entry reserved for IP fragment rule */
3293         return np->clas.tcam_valid_entries - 1;
3294 }
3295
3296 static void niu_rx_skb_append(struct sk_buff *skb, struct page *page,
3297                               u32 offset, u32 size)
3298 {
3299         int i = skb_shinfo(skb)->nr_frags;
3300         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3301
3302         frag->page = page;
3303         frag->page_offset = offset;
3304         frag->size = size;
3305
3306         skb->len += size;
3307         skb->data_len += size;
3308         skb->truesize += size;
3309
3310         skb_shinfo(skb)->nr_frags = i + 1;
3311 }
3312
3313 static unsigned int niu_hash_rxaddr(struct rx_ring_info *rp, u64 a)
3314 {
3315         a >>= PAGE_SHIFT;
3316         a ^= (a >> ilog2(MAX_RBR_RING_SIZE));
3317
3318         return (a & (MAX_RBR_RING_SIZE - 1));
3319 }
3320
3321 static struct page *niu_find_rxpage(struct rx_ring_info *rp, u64 addr,
3322                                     struct page ***link)
3323 {
3324         unsigned int h = niu_hash_rxaddr(rp, addr);
3325         struct page *p, **pp;
3326
3327         addr &= PAGE_MASK;
3328         pp = &rp->rxhash[h];
3329         for (; (p = *pp) != NULL; pp = (struct page **) &p->mapping) {
3330                 if (p->index == addr) {
3331                         *link = pp;
3332                         break;
3333                 }
3334         }
3335
3336         return p;
3337 }
3338
3339 static void niu_hash_page(struct rx_ring_info *rp, struct page *page, u64 base)
3340 {
3341         unsigned int h = niu_hash_rxaddr(rp, base);
3342
3343         page->index = base;
3344         page->mapping = (struct address_space *) rp->rxhash[h];
3345         rp->rxhash[h] = page;
3346 }
3347
3348 static int niu_rbr_add_page(struct niu *np, struct rx_ring_info *rp,
3349                             gfp_t mask, int start_index)
3350 {
3351         struct page *page;
3352         u64 addr;
3353         int i;
3354
3355         page = alloc_page(mask);
3356         if (!page)
3357                 return -ENOMEM;
3358
3359         addr = np->ops->map_page(np->device, page, 0,
3360                                  PAGE_SIZE, DMA_FROM_DEVICE);
3361
3362         niu_hash_page(rp, page, addr);
3363         if (rp->rbr_blocks_per_page > 1)
3364                 atomic_add(rp->rbr_blocks_per_page - 1,
3365                            &compound_head(page)->_count);
3366
3367         for (i = 0; i < rp->rbr_blocks_per_page; i++) {
3368                 __le32 *rbr = &rp->rbr[start_index + i];
3369
3370                 *rbr = cpu_to_le32(addr >> RBR_DESCR_ADDR_SHIFT);
3371                 addr += rp->rbr_block_size;
3372         }
3373
3374         return 0;
3375 }
3376
3377 static void niu_rbr_refill(struct niu *np, struct rx_ring_info *rp, gfp_t mask)
3378 {
3379         int index = rp->rbr_index;
3380
3381         rp->rbr_pending++;
3382         if ((rp->rbr_pending % rp->rbr_blocks_per_page) == 0) {
3383                 int err = niu_rbr_add_page(np, rp, mask, index);
3384
3385                 if (unlikely(err)) {
3386                         rp->rbr_pending--;
3387                         return;
3388                 }
3389
3390                 rp->rbr_index += rp->rbr_blocks_per_page;
3391                 BUG_ON(rp->rbr_index > rp->rbr_table_size);
3392                 if (rp->rbr_index == rp->rbr_table_size)
3393                         rp->rbr_index = 0;
3394
3395                 if (rp->rbr_pending >= rp->rbr_kick_thresh) {
3396                         nw64(RBR_KICK(rp->rx_channel), rp->rbr_pending);
3397                         rp->rbr_pending = 0;
3398                 }
3399         }
3400 }
3401
3402 static int niu_rx_pkt_ignore(struct niu *np, struct rx_ring_info *rp)
3403 {
3404         unsigned int index = rp->rcr_index;
3405         int num_rcr = 0;
3406
3407         rp->rx_dropped++;
3408         while (1) {
3409                 struct page *page, **link;
3410                 u64 addr, val;
3411                 u32 rcr_size;
3412
3413                 num_rcr++;
3414
3415                 val = le64_to_cpup(&rp->rcr[index]);
3416                 addr = (val & RCR_ENTRY_PKT_BUF_ADDR) <<
3417                         RCR_ENTRY_PKT_BUF_ADDR_SHIFT;
3418                 page = niu_find_rxpage(rp, addr, &link);
3419
3420                 rcr_size = rp->rbr_sizes[(val & RCR_ENTRY_PKTBUFSZ) >>
3421                                          RCR_ENTRY_PKTBUFSZ_SHIFT];
3422                 if ((page->index + PAGE_SIZE) - rcr_size == addr) {
3423                         *link = (struct page *) page->mapping;
3424                         np->ops->unmap_page(np->device, page->index,
3425                                             PAGE_SIZE, DMA_FROM_DEVICE);
3426                         page->index = 0;
3427                         page->mapping = NULL;
3428                         __free_page(page);
3429                         rp->rbr_refill_pending++;
3430                 }
3431
3432                 index = NEXT_RCR(rp, index);
3433                 if (!(val & RCR_ENTRY_MULTI))
3434                         break;
3435
3436         }
3437         rp->rcr_index = index;
3438
3439         return num_rcr;
3440 }
3441
3442 static int niu_process_rx_pkt(struct napi_struct *napi, struct niu *np,
3443                               struct rx_ring_info *rp)
3444 {
3445         unsigned int index = rp->rcr_index;
3446         struct sk_buff *skb;
3447         int len, num_rcr;
3448
3449         skb = netdev_alloc_skb(np->dev, RX_SKB_ALLOC_SIZE);
3450         if (unlikely(!skb))
3451                 return niu_rx_pkt_ignore(np, rp);
3452
3453         num_rcr = 0;
3454         while (1) {
3455                 struct page *page, **link;
3456                 u32 rcr_size, append_size;
3457                 u64 addr, val, off;
3458
3459                 num_rcr++;
3460
3461                 val = le64_to_cpup(&rp->rcr[index]);
3462
3463                 len = (val & RCR_ENTRY_L2_LEN) >>
3464                         RCR_ENTRY_L2_LEN_SHIFT;
3465                 len -= ETH_FCS_LEN;
3466
3467                 addr = (val & RCR_ENTRY_PKT_BUF_ADDR) <<
3468                         RCR_ENTRY_PKT_BUF_ADDR_SHIFT;
3469                 page = niu_find_rxpage(rp, addr, &link);
3470
3471                 rcr_size = rp->rbr_sizes[(val & RCR_ENTRY_PKTBUFSZ) >>
3472                                          RCR_ENTRY_PKTBUFSZ_SHIFT];
3473
3474                 off = addr & ~PAGE_MASK;
3475                 append_size = rcr_size;
3476                 if (num_rcr == 1) {
3477                         int ptype;
3478
3479                         off += 2;
3480                         append_size -= 2;
3481
3482                         ptype = (val >> RCR_ENTRY_PKT_TYPE_SHIFT);
3483                         if ((ptype == RCR_PKT_TYPE_TCP ||
3484                              ptype == RCR_PKT_TYPE_UDP) &&
3485                             !(val & (RCR_ENTRY_NOPORT |
3486                                      RCR_ENTRY_ERROR)))
3487                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
3488                         else
3489                                 skb->ip_summed = CHECKSUM_NONE;
3490                 }
3491                 if (!(val & RCR_ENTRY_MULTI))
3492                         append_size = len - skb->len;
3493
3494                 niu_rx_skb_append(skb, page, off, append_size);
3495                 if ((page->index + rp->rbr_block_size) - rcr_size == addr) {
3496                         *link = (struct page *) page->mapping;
3497                         np->ops->unmap_page(np->device, page->index,
3498                                             PAGE_SIZE, DMA_FROM_DEVICE);
3499                         page->index = 0;
3500                         page->mapping = NULL;
3501                         rp->rbr_refill_pending++;
3502                 } else
3503                         get_page(page);
3504
3505                 index = NEXT_RCR(rp, index);
3506                 if (!(val & RCR_ENTRY_MULTI))
3507                         break;
3508
3509         }
3510         rp->rcr_index = index;
3511
3512         skb_reserve(skb, NET_IP_ALIGN);
3513         __pskb_pull_tail(skb, min(len, VLAN_ETH_HLEN));
3514
3515         rp->rx_packets++;
3516         rp->rx_bytes += skb->len;
3517
3518         skb->protocol = eth_type_trans(skb, np->dev);
3519         skb_record_rx_queue(skb, rp->rx_channel);
3520         napi_gro_receive(napi, skb);
3521
3522         return num_rcr;
3523 }
3524
3525 static int niu_rbr_fill(struct niu *np, struct rx_ring_info *rp, gfp_t mask)
3526 {
3527         int blocks_per_page = rp->rbr_blocks_per_page;
3528         int err, index = rp->rbr_index;
3529
3530         err = 0;
3531         while (index < (rp->rbr_table_size - blocks_per_page)) {
3532                 err = niu_rbr_add_page(np, rp, mask, index);
3533                 if (err)
3534                         break;
3535
3536                 index += blocks_per_page;
3537         }
3538
3539         rp->rbr_index = index;
3540         return err;
3541 }
3542
3543 static void niu_rbr_free(struct niu *np, struct rx_ring_info *rp)
3544 {
3545         int i;
3546
3547         for (i = 0; i < MAX_RBR_RING_SIZE; i++) {
3548                 struct page *page;
3549
3550                 page = rp->rxhash[i];
3551                 while (page) {
3552                         struct page *next = (struct page *) page->mapping;
3553                         u64 base = page->index;
3554
3555                         np->ops->unmap_page(np->device, base, PAGE_SIZE,
3556                                             DMA_FROM_DEVICE);
3557                         page->index = 0;
3558                         page->mapping = NULL;
3559
3560                         __free_page(page);
3561
3562                         page = next;
3563                 }
3564         }
3565
3566         for (i = 0; i < rp->rbr_table_size; i++)
3567                 rp->rbr[i] = cpu_to_le32(0);
3568         rp->rbr_index = 0;
3569 }
3570
3571 static int release_tx_packet(struct niu *np, struct tx_ring_info *rp, int idx)
3572 {
3573         struct tx_buff_info *tb = &rp->tx_buffs[idx];
3574         struct sk_buff *skb = tb->skb;
3575         struct tx_pkt_hdr *tp;
3576         u64 tx_flags;
3577         int i, len;
3578
3579         tp = (struct tx_pkt_hdr *) skb->data;
3580         tx_flags = le64_to_cpup(&tp->flags);
3581
3582         rp->tx_packets++;
3583         rp->tx_bytes += (((tx_flags & TXHDR_LEN) >> TXHDR_LEN_SHIFT) -
3584                          ((tx_flags & TXHDR_PAD) / 2));
3585
3586         len = skb_headlen(skb);
3587         np->ops->unmap_single(np->device, tb->mapping,
3588                               len, DMA_TO_DEVICE);
3589
3590         if (le64_to_cpu(rp->descr[idx]) & TX_DESC_MARK)
3591                 rp->mark_pending--;
3592
3593         tb->skb = NULL;
3594         do {
3595                 idx = NEXT_TX(rp, idx);
3596                 len -= MAX_TX_DESC_LEN;
3597         } while (len > 0);
3598
3599         for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
3600                 tb = &rp->tx_buffs[idx];
3601                 BUG_ON(tb->skb != NULL);
3602                 np->ops->unmap_page(np->device, tb->mapping,
3603                                     skb_shinfo(skb)->frags[i].size,
3604                                     DMA_TO_DEVICE);
3605                 idx = NEXT_TX(rp, idx);
3606         }
3607
3608         dev_kfree_skb(skb);
3609
3610         return idx;
3611 }
3612
3613 #define NIU_TX_WAKEUP_THRESH(rp)                ((rp)->pending / 4)
3614
3615 static void niu_tx_work(struct niu *np, struct tx_ring_info *rp)
3616 {
3617         struct netdev_queue *txq;
3618         u16 pkt_cnt, tmp;
3619         int cons, index;
3620         u64 cs;
3621
3622         index = (rp - np->tx_rings);
3623         txq = netdev_get_tx_queue(np->dev, index);
3624
3625         cs = rp->tx_cs;
3626         if (unlikely(!(cs & (TX_CS_MK | TX_CS_MMK))))
3627                 goto out;
3628
3629         tmp = pkt_cnt = (cs & TX_CS_PKT_CNT) >> TX_CS_PKT_CNT_SHIFT;
3630         pkt_cnt = (pkt_cnt - rp->last_pkt_cnt) &
3631                 (TX_CS_PKT_CNT >> TX_CS_PKT_CNT_SHIFT);
3632
3633         rp->last_pkt_cnt = tmp;
3634
3635         cons = rp->cons;
3636
3637         netif_printk(np, tx_done, KERN_DEBUG, np->dev,
3638                      "%s() pkt_cnt[%u] cons[%d]\n", __func__, pkt_cnt, cons);
3639
3640         while (pkt_cnt--)
3641                 cons = release_tx_packet(np, rp, cons);
3642
3643         rp->cons = cons;
3644         smp_mb();
3645
3646 out:
3647         if (unlikely(netif_tx_queue_stopped(txq) &&
3648                      (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp)))) {
3649                 __netif_tx_lock(txq, smp_processor_id());
3650                 if (netif_tx_queue_stopped(txq) &&
3651                     (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp)))
3652                         netif_tx_wake_queue(txq);
3653                 __netif_tx_unlock(txq);
3654         }
3655 }
3656
3657 static inline void niu_sync_rx_discard_stats(struct niu *np,
3658                                              struct rx_ring_info *rp,
3659                                              const int limit)
3660 {
3661         /* This elaborate scheme is needed for reading the RX discard
3662          * counters, as they are only 16-bit and can overflow quickly,
3663          * and because the overflow indication bit is not usable as
3664          * the counter value does not wrap, but remains at max value
3665          * 0xFFFF.
3666          *
3667          * In theory and in practice counters can be lost in between
3668          * reading nr64() and clearing the counter nw64().  For this
3669          * reason, the number of counter clearings nw64() is
3670          * limited/reduced though the limit parameter.
3671          */
3672         int rx_channel = rp->rx_channel;
3673         u32 misc, wred;
3674
3675         /* RXMISC (Receive Miscellaneous Discard Count), covers the
3676          * following discard events: IPP (Input Port Process),
3677          * FFLP/TCAM, Full RCR (Receive Completion Ring) RBR (Receive
3678          * Block Ring) prefetch buffer is empty.
3679          */
3680         misc = nr64(RXMISC(rx_channel));
3681         if (unlikely((misc & RXMISC_COUNT) > limit)) {
3682                 nw64(RXMISC(rx_channel), 0);
3683                 rp->rx_errors += misc & RXMISC_COUNT;
3684
3685                 if (unlikely(misc & RXMISC_OFLOW))
3686                         dev_err(np->device, "rx-%d: Counter overflow RXMISC discard\n",
3687                                 rx_channel);
3688
3689                 netif_printk(np, rx_err, KERN_DEBUG, np->dev,
3690                              "rx-%d: MISC drop=%u over=%u\n",
3691                              rx_channel, misc, misc-limit);
3692         }
3693
3694         /* WRED (Weighted Random Early Discard) by hardware */
3695         wred = nr64(RED_DIS_CNT(rx_channel));
3696         if (unlikely((wred & RED_DIS_CNT_COUNT) > limit)) {
3697                 nw64(RED_DIS_CNT(rx_channel), 0);
3698                 rp->rx_dropped += wred & RED_DIS_CNT_COUNT;
3699
3700                 if (unlikely(wred & RED_DIS_CNT_OFLOW))
3701                         dev_err(np->device, "rx-%d: Counter overflow WRED discard\n", rx_channel);
3702
3703                 netif_printk(np, rx_err, KERN_DEBUG, np->dev,
3704                              "rx-%d: WRED drop=%u over=%u\n",
3705                              rx_channel, wred, wred-limit);
3706         }
3707 }
3708
3709 static int niu_rx_work(struct napi_struct *napi, struct niu *np,
3710                        struct rx_ring_info *rp, int budget)
3711 {
3712         int qlen, rcr_done = 0, work_done = 0;
3713         struct rxdma_mailbox *mbox = rp->mbox;
3714         u64 stat;
3715
3716 #if 1
3717         stat = nr64(RX_DMA_CTL_STAT(rp->rx_channel));
3718         qlen = nr64(RCRSTAT_A(rp->rx_channel)) & RCRSTAT_A_QLEN;
3719 #else
3720         stat = le64_to_cpup(&mbox->rx_dma_ctl_stat);
3721         qlen = (le64_to_cpup(&mbox->rcrstat_a) & RCRSTAT_A_QLEN);
3722 #endif
3723         mbox->rx_dma_ctl_stat = 0;
3724         mbox->rcrstat_a = 0;
3725
3726         netif_printk(np, rx_status, KERN_DEBUG, np->dev,
3727                      "%s(chan[%d]), stat[%llx] qlen=%d\n",
3728                      __func__, rp->rx_channel, (unsigned long long)stat, qlen);
3729
3730         rcr_done = work_done = 0;
3731         qlen = min(qlen, budget);
3732         while (work_done < qlen) {
3733                 rcr_done += niu_process_rx_pkt(napi, np, rp);
3734                 work_done++;
3735         }
3736
3737         if (rp->rbr_refill_pending >= rp->rbr_kick_thresh) {
3738                 unsigned int i;
3739
3740                 for (i = 0; i < rp->rbr_refill_pending; i++)
3741                         niu_rbr_refill(np, rp, GFP_ATOMIC);
3742                 rp->rbr_refill_pending = 0;
3743         }
3744
3745         stat = (RX_DMA_CTL_STAT_MEX |
3746                 ((u64)work_done << RX_DMA_CTL_STAT_PKTREAD_SHIFT) |
3747                 ((u64)rcr_done << RX_DMA_CTL_STAT_PTRREAD_SHIFT));
3748
3749         nw64(RX_DMA_CTL_STAT(rp->rx_channel), stat);
3750
3751         /* Only sync discards stats when qlen indicate potential for drops */
3752         if (qlen > 10)
3753                 niu_sync_rx_discard_stats(np, rp, 0x7FFF);
3754
3755         return work_done;
3756 }
3757
3758 static int niu_poll_core(struct niu *np, struct niu_ldg *lp, int budget)
3759 {
3760         u64 v0 = lp->v0;
3761         u32 tx_vec = (v0 >> 32);
3762         u32 rx_vec = (v0 & 0xffffffff);
3763         int i, work_done = 0;
3764
3765         netif_printk(np, intr, KERN_DEBUG, np->dev,
3766                      "%s() v0[%016llx]\n", __func__, (unsigned long long)v0);
3767
3768         for (i = 0; i < np->num_tx_rings; i++) {
3769                 struct tx_ring_info *rp = &np->tx_rings[i];
3770                 if (tx_vec & (1 << rp->tx_channel))
3771                         niu_tx_work(np, rp);
3772                 nw64(LD_IM0(LDN_TXDMA(rp->tx_channel)), 0);
3773         }
3774
3775         for (i = 0; i < np->num_rx_rings; i++) {
3776                 struct rx_ring_info *rp = &np->rx_rings[i];
3777
3778                 if (rx_vec & (1 << rp->rx_channel)) {
3779                         int this_work_done;
3780
3781                         this_work_done = niu_rx_work(&lp->napi, np, rp,
3782                                                      budget);
3783
3784                         budget -= this_work_done;
3785                         work_done += this_work_done;
3786                 }
3787                 nw64(LD_IM0(LDN_RXDMA(rp->rx_channel)), 0);
3788         }
3789
3790         return work_done;
3791 }
3792
3793 static int niu_poll(struct napi_struct *napi, int budget)
3794 {
3795         struct niu_ldg *lp = container_of(napi, struct niu_ldg, napi);
3796         struct niu *np = lp->np;
3797         int work_done;
3798
3799         work_done = niu_poll_core(np, lp, budget);
3800
3801         if (work_done < budget) {
3802                 napi_complete(napi);
3803                 niu_ldg_rearm(np, lp, 1);
3804         }
3805         return work_done;
3806 }
3807
3808 static void niu_log_rxchan_errors(struct niu *np, struct rx_ring_info *rp,
3809                                   u64 stat)
3810 {
3811         netdev_err(np->dev, "RX channel %u errors ( ", rp->rx_channel);
3812
3813         if (stat & RX_DMA_CTL_STAT_RBR_TMOUT)
3814                 pr_cont("RBR_TMOUT ");
3815         if (stat & RX_DMA_CTL_STAT_RSP_CNT_ERR)
3816                 pr_cont("RSP_CNT ");
3817         if (stat & RX_DMA_CTL_STAT_BYTE_EN_BUS)
3818                 pr_cont("BYTE_EN_BUS ");
3819         if (stat & RX_DMA_CTL_STAT_RSP_DAT_ERR)
3820                 pr_cont("RSP_DAT ");
3821         if (stat & RX_DMA_CTL_STAT_RCR_ACK_ERR)
3822                 pr_cont("RCR_ACK ");
3823         if (stat & RX_DMA_CTL_STAT_RCR_SHA_PAR)
3824                 pr_cont("RCR_SHA_PAR ");
3825         if (stat & RX_DMA_CTL_STAT_RBR_PRE_PAR)
3826                 pr_cont("RBR_PRE_PAR ");
3827         if (stat & RX_DMA_CTL_STAT_CONFIG_ERR)
3828                 pr_cont("CONFIG ");
3829         if (stat & RX_DMA_CTL_STAT_RCRINCON)
3830                 pr_cont("RCRINCON ");
3831         if (stat & RX_DMA_CTL_STAT_RCRFULL)
3832                 pr_cont("RCRFULL ");
3833         if (stat & RX_DMA_CTL_STAT_RBRFULL)
3834                 pr_cont("RBRFULL ");
3835         if (stat & RX_DMA_CTL_STAT_RBRLOGPAGE)
3836                 pr_cont("RBRLOGPAGE ");
3837         if (stat & RX_DMA_CTL_STAT_CFIGLOGPAGE)
3838                 pr_cont("CFIGLOGPAGE ");
3839         if (stat & RX_DMA_CTL_STAT_DC_FIFO_ERR)
3840                 pr_cont("DC_FIDO ");
3841
3842         pr_cont(")\n");
3843 }
3844
3845 static int niu_rx_error(struct niu *np, struct rx_ring_info *rp)
3846 {
3847         u64 stat = nr64(RX_DMA_CTL_STAT(rp->rx_channel));
3848         int err = 0;
3849
3850
3851         if (stat & (RX_DMA_CTL_STAT_CHAN_FATAL |
3852                     RX_DMA_CTL_STAT_PORT_FATAL))
3853                 err = -EINVAL;
3854
3855         if (err) {
3856                 netdev_err(np->dev, "RX channel %u error, stat[%llx]\n",
3857                            rp->rx_channel,
3858                            (unsigned long long) stat);
3859
3860                 niu_log_rxchan_errors(np, rp, stat);
3861         }
3862
3863         nw64(RX_DMA_CTL_STAT(rp->rx_channel),
3864              stat & RX_DMA_CTL_WRITE_CLEAR_ERRS);
3865
3866         return err;
3867 }
3868
3869 static void niu_log_txchan_errors(struct niu *np, struct tx_ring_info *rp,
3870                                   u64 cs)
3871 {
3872         netdev_err(np->dev, "TX channel %u errors ( ", rp->tx_channel);
3873
3874         if (cs & TX_CS_MBOX_ERR)
3875                 pr_cont("MBOX ");
3876         if (cs & TX_CS_PKT_SIZE_ERR)
3877                 pr_cont("PKT_SIZE ");
3878         if (cs & TX_CS_TX_RING_OFLOW)
3879                 pr_cont("TX_RING_OFLOW ");
3880         if (cs & TX_CS_PREF_BUF_PAR_ERR)
3881                 pr_cont("PREF_BUF_PAR ");
3882         if (cs & TX_CS_NACK_PREF)
3883                 pr_cont("NACK_PREF ");
3884         if (cs & TX_CS_NACK_PKT_RD)
3885                 pr_cont("NACK_PKT_RD ");
3886         if (cs & TX_CS_CONF_PART_ERR)
3887                 pr_cont("CONF_PART ");
3888         if (cs & TX_CS_PKT_PRT_ERR)
3889                 pr_cont("PKT_PTR ");
3890
3891         pr_cont(")\n");
3892 }
3893
3894 static int niu_tx_error(struct niu *np, struct tx_ring_info *rp)
3895 {
3896         u64 cs, logh, logl;
3897
3898         cs = nr64(TX_CS(rp->tx_channel));
3899         logh = nr64(TX_RNG_ERR_LOGH(rp->tx_channel));
3900         logl = nr64(TX_RNG_ERR_LOGL(rp->tx_channel));
3901
3902         netdev_err(np->dev, "TX channel %u error, cs[%llx] logh[%llx] logl[%llx]\n",
3903                    rp->tx_channel,
3904                    (unsigned long long)cs,
3905                    (unsigned long long)logh,
3906                    (unsigned long long)logl);
3907
3908         niu_log_txchan_errors(np, rp, cs);
3909
3910         return -ENODEV;
3911 }
3912
3913 static int niu_mif_interrupt(struct niu *np)
3914 {
3915         u64 mif_status = nr64(MIF_STATUS);
3916         int phy_mdint = 0;
3917
3918         if (np->flags & NIU_FLAGS_XMAC) {
3919                 u64 xrxmac_stat = nr64_mac(XRXMAC_STATUS);
3920
3921                 if (xrxmac_stat & XRXMAC_STATUS_PHY_MDINT)
3922                         phy_mdint = 1;
3923         }
3924
3925         netdev_err(np->dev, "MIF interrupt, stat[%llx] phy_mdint(%d)\n",
3926                    (unsigned long long)mif_status, phy_mdint);
3927
3928         return -ENODEV;
3929 }
3930
3931 static void niu_xmac_interrupt(struct niu *np)
3932 {
3933         struct niu_xmac_stats *mp = &np->mac_stats.xmac;
3934         u64 val;
3935
3936         val = nr64_mac(XTXMAC_STATUS);
3937         if (val & XTXMAC_STATUS_FRAME_CNT_EXP)
3938                 mp->tx_frames += TXMAC_FRM_CNT_COUNT;
3939         if (val & XTXMAC_STATUS_BYTE_CNT_EXP)
3940                 mp->tx_bytes += TXMAC_BYTE_CNT_COUNT;
3941         if (val & XTXMAC_STATUS_TXFIFO_XFR_ERR)
3942                 mp->tx_fifo_errors++;
3943         if (val & XTXMAC_STATUS_TXMAC_OFLOW)
3944                 mp->tx_overflow_errors++;
3945         if (val & XTXMAC_STATUS_MAX_PSIZE_ERR)
3946                 mp->tx_max_pkt_size_errors++;
3947         if (val & XTXMAC_STATUS_TXMAC_UFLOW)
3948                 mp->tx_underflow_errors++;
3949
3950         val = nr64_mac(XRXMAC_STATUS);
3951         if (val & XRXMAC_STATUS_LCL_FLT_STATUS)
3952                 mp->rx_local_faults++;
3953         if (val & XRXMAC_STATUS_RFLT_DET)
3954                 mp->rx_remote_faults++;
3955         if (val & XRXMAC_STATUS_LFLT_CNT_EXP)
3956                 mp->rx_link_faults += LINK_FAULT_CNT_COUNT;
3957         if (val & XRXMAC_STATUS_ALIGNERR_CNT_EXP)
3958                 mp->rx_align_errors += RXMAC_ALIGN_ERR_CNT_COUNT;
3959         if (val & XRXMAC_STATUS_RXFRAG_CNT_EXP)
3960                 mp->rx_frags += RXMAC_FRAG_CNT_COUNT;
3961         if (val & XRXMAC_STATUS_RXMULTF_CNT_EXP)
3962                 mp->rx_mcasts += RXMAC_MC_FRM_CNT_COUNT;
3963         if (val & XRXMAC_STATUS_RXBCAST_CNT_EXP)
3964                 mp->rx_bcasts += RXMAC_BC_FRM_CNT_COUNT;
3965         if (val & XRXMAC_STATUS_RXBCAST_CNT_EXP)
3966                 mp->rx_bcasts += RXMAC_BC_FRM_CNT_COUNT;
3967         if (val & XRXMAC_STATUS_RXHIST1_CNT_EXP)
3968                 mp->rx_hist_cnt1 += RXMAC_HIST_CNT1_COUNT;
3969         if (val & XRXMAC_STATUS_RXHIST2_CNT_EXP)
3970                 mp->rx_hist_cnt2 += RXMAC_HIST_CNT2_COUNT;
3971         if (val & XRXMAC_STATUS_RXHIST3_CNT_EXP)
3972                 mp->rx_hist_cnt3 += RXMAC_HIST_CNT3_COUNT;
3973         if (val & XRXMAC_STATUS_RXHIST4_CNT_EXP)
3974                 mp->rx_hist_cnt4 += RXMAC_HIST_CNT4_COUNT;
3975         if (val & XRXMAC_STATUS_RXHIST5_CNT_EXP)
3976                 mp->rx_hist_cnt5 += RXMAC_HIST_CNT5_COUNT;
3977         if (val & XRXMAC_STATUS_RXHIST6_CNT_EXP)
3978                 mp->rx_hist_cnt6 += RXMAC_HIST_CNT6_COUNT;
3979         if (val & XRXMAC_STATUS_RXHIST7_CNT_EXP)
3980                 mp->rx_hist_cnt7 += RXMAC_HIST_CNT7_COUNT;
3981         if (val & XRXMAC_STATUS_RXOCTET_CNT_EXP)
3982                 mp->rx_octets += RXMAC_BT_CNT_COUNT;
3983         if (val & XRXMAC_STATUS_CVIOLERR_CNT_EXP)
3984                 mp->rx_code_violations += RXMAC_CD_VIO_CNT_COUNT;
3985         if (val & XRXMAC_STATUS_LENERR_CNT_EXP)
3986                 mp->rx_len_errors += RXMAC_MPSZER_CNT_COUNT;
3987         if (val & XRXMAC_STATUS_CRCERR_CNT_EXP)
3988                 mp->rx_crc_errors += RXMAC_CRC_ER_CNT_COUNT;
3989         if (val & XRXMAC_STATUS_RXUFLOW)
3990                 mp->rx_underflows++;
3991         if (val & XRXMAC_STATUS_RXOFLOW)
3992                 mp->rx_overflows++;
3993
3994         val = nr64_mac(XMAC_FC_STAT);
3995         if (val & XMAC_FC_STAT_TX_MAC_NPAUSE)
3996                 mp->pause_off_state++;
3997         if (val & XMAC_FC_STAT_TX_MAC_PAUSE)
3998                 mp->pause_on_state++;
3999         if (val & XMAC_FC_STAT_RX_MAC_RPAUSE)
4000                 mp->pause_received++;
4001 }
4002
4003 static void niu_bmac_interrupt(struct niu *np)
4004 {
4005         struct niu_bmac_stats *mp = &np->mac_stats.bmac;
4006         u64 val;
4007
4008         val = nr64_mac(BTXMAC_STATUS);
4009         if (val & BTXMAC_STATUS_UNDERRUN)
4010                 mp->tx_underflow_errors++;
4011         if (val & BTXMAC_STATUS_MAX_PKT_ERR)
4012                 mp->tx_max_pkt_size_errors++;
4013         if (val & BTXMAC_STATUS_BYTE_CNT_EXP)
4014                 mp->tx_bytes += BTXMAC_BYTE_CNT_COUNT;
4015         if (val & BTXMAC_STATUS_FRAME_CNT_EXP)
4016                 mp->tx_frames += BTXMAC_FRM_CNT_COUNT;
4017
4018         val = nr64_mac(BRXMAC_STATUS);
4019         if (val & BRXMAC_STATUS_OVERFLOW)
4020                 mp->rx_overflows++;
4021         if (val & BRXMAC_STATUS_FRAME_CNT_EXP)
4022                 mp->rx_frames += BRXMAC_FRAME_CNT_COUNT;
4023         if (val & BRXMAC_STATUS_ALIGN_ERR_EXP)
4024                 mp->rx_align_errors += BRXMAC_ALIGN_ERR_CNT_COUNT;
4025         if (val & BRXMAC_STATUS_CRC_ERR_EXP)
4026                 mp->rx_crc_errors += BRXMAC_ALIGN_ERR_CNT_COUNT;
4027         if (val & BRXMAC_STATUS_LEN_ERR_EXP)
4028                 mp->rx_len_errors += BRXMAC_CODE_VIOL_ERR_CNT_COUNT;
4029
4030         val = nr64_mac(BMAC_CTRL_STATUS);
4031         if (val & BMAC_CTRL_STATUS_NOPAUSE)
4032                 mp->pause_off_state++;
4033         if (val & BMAC_CTRL_STATUS_PAUSE)
4034                 mp->pause_on_state++;
4035         if (val & BMAC_CTRL_STATUS_PAUSE_RECV)
4036                 mp->pause_received++;
4037 }
4038
4039 static int niu_mac_interrupt(struct niu *np)
4040 {
4041         if (np->flags & NIU_FLAGS_XMAC)
4042                 niu_xmac_interrupt(np);
4043         else
4044                 niu_bmac_interrupt(np);
4045
4046         return 0;
4047 }
4048
4049 static void niu_log_device_error(struct niu *np, u64 stat)
4050 {
4051         netdev_err(np->dev, "Core device errors ( ");
4052
4053         if (stat & SYS_ERR_MASK_META2)
4054                 pr_cont("META2 ");
4055         if (stat & SYS_ERR_MASK_META1)
4056                 pr_cont("META1 ");
4057         if (stat & SYS_ERR_MASK_PEU)
4058                 pr_cont("PEU ");
4059         if (stat & SYS_ERR_MASK_TXC)
4060                 pr_cont("TXC ");
4061         if (stat & SYS_ERR_MASK_RDMC)
4062                 pr_cont("RDMC ");
4063         if (stat & SYS_ERR_MASK_TDMC)
4064                 pr_cont("TDMC ");
4065         if (stat & SYS_ERR_MASK_ZCP)
4066                 pr_cont("ZCP ");
4067         if (stat & SYS_ERR_MASK_FFLP)
4068                 pr_cont("FFLP ");
4069         if (stat & SYS_ERR_MASK_IPP)
4070                 pr_cont("IPP ");
4071         if (stat & SYS_ERR_MASK_MAC)
4072                 pr_cont("MAC ");
4073         if (stat & SYS_ERR_MASK_SMX)
4074                 pr_cont("SMX ");
4075
4076         pr_cont(")\n");
4077 }
4078
4079 static int niu_device_error(struct niu *np)
4080 {
4081         u64 stat = nr64(SYS_ERR_STAT);
4082
4083         netdev_err(np->dev, "Core device error, stat[%llx]\n",
4084                    (unsigned long long)stat);
4085
4086         niu_log_device_error(np, stat);
4087
4088         return -ENODEV;
4089 }
4090
4091 static int niu_slowpath_interrupt(struct niu *np, struct niu_ldg *lp,
4092                               u64 v0, u64 v1, u64 v2)
4093 {
4094
4095         int i, err = 0;
4096
4097         lp->v0 = v0;
4098         lp->v1 = v1;
4099         lp->v2 = v2;
4100
4101         if (v1 & 0x00000000ffffffffULL) {
4102                 u32 rx_vec = (v1 & 0xffffffff);
4103
4104                 for (i = 0; i < np->num_rx_rings; i++) {
4105                         struct rx_ring_info *rp = &np->rx_rings[i];
4106
4107                         if (rx_vec & (1 << rp->rx_channel)) {
4108                                 int r = niu_rx_error(np, rp);
4109                                 if (r) {
4110                                         err = r;
4111                                 } else {
4112                                         if (!v0)
4113                                                 nw64(RX_DMA_CTL_STAT(rp->rx_channel),
4114                                                      RX_DMA_CTL_STAT_MEX);
4115                                 }
4116                         }
4117                 }
4118         }
4119         if (v1 & 0x7fffffff00000000ULL) {
4120                 u32 tx_vec = (v1 >> 32) & 0x7fffffff;
4121
4122                 for (i = 0; i < np->num_tx_rings; i++) {
4123                         struct tx_ring_info *rp = &np->tx_rings[i];
4124
4125                         if (tx_vec & (1 << rp->tx_channel)) {
4126                                 int r = niu_tx_error(np, rp);
4127                                 if (r)
4128                                         err = r;
4129                         }
4130                 }
4131         }
4132         if ((v0 | v1) & 0x8000000000000000ULL) {
4133                 int r = niu_mif_interrupt(np);
4134                 if (r)
4135                         err = r;
4136         }
4137         if (v2) {
4138                 if (v2 & 0x01ef) {
4139                         int r = niu_mac_interrupt(np);
4140                         if (r)
4141                                 err = r;
4142                 }
4143                 if (v2 & 0x0210) {
4144                         int r = niu_device_error(np);
4145                         if (r)
4146                                 err = r;
4147                 }
4148         }
4149
4150         if (err)
4151                 niu_enable_interrupts(np, 0);
4152
4153         return err;
4154 }
4155
4156 static void niu_rxchan_intr(struct niu *np, struct rx_ring_info *rp,
4157                             int ldn)
4158 {
4159         struct rxdma_mailbox *mbox = rp->mbox;
4160         u64 stat_write, stat = le64_to_cpup(&mbox->rx_dma_ctl_stat);
4161
4162         stat_write = (RX_DMA_CTL_STAT_RCRTHRES |
4163                       RX_DMA_CTL_STAT_RCRTO);
4164         nw64(RX_DMA_CTL_STAT(rp->rx_channel), stat_write);
4165
4166         netif_printk(np, intr, KERN_DEBUG, np->dev,
4167                      "%s() stat[%llx]\n", __func__, (unsigned long long)stat);
4168 }
4169
4170 static void niu_txchan_intr(struct niu *np, struct tx_ring_info *rp,
4171                             int ldn)
4172 {
4173         rp->tx_cs = nr64(TX_CS(rp->tx_channel));
4174
4175         netif_printk(np, intr, KERN_DEBUG, np->dev,
4176                      "%s() cs[%llx]\n", __func__, (unsigned long long)rp->tx_cs);
4177 }
4178
4179 static void __niu_fastpath_interrupt(struct niu *np, int ldg, u64 v0)
4180 {
4181         struct niu_parent *parent = np->parent;
4182         u32 rx_vec, tx_vec;
4183         int i;
4184
4185         tx_vec = (v0 >> 32);
4186         rx_vec = (v0 & 0xffffffff);
4187
4188         for (i = 0; i < np->num_rx_rings; i++) {
4189                 struct rx_ring_info *rp = &np->rx_rings[i];
4190                 int ldn = LDN_RXDMA(rp->rx_channel);
4191
4192                 if (parent->ldg_map[ldn] != ldg)
4193                         continue;
4194
4195                 nw64(LD_IM0(ldn), LD_IM0_MASK);
4196                 if (rx_vec & (1 << rp->rx_channel))
4197                         niu_rxchan_intr(np, rp, ldn);
4198         }
4199
4200         for (i = 0; i < np->num_tx_rings; i++) {
4201                 struct tx_ring_info *rp = &np->tx_rings[i];
4202                 int ldn = LDN_TXDMA(rp->tx_channel);
4203
4204                 if (parent->ldg_map[ldn] != ldg)
4205                         continue;
4206
4207                 nw64(LD_IM0(ldn), LD_IM0_MASK);
4208                 if (tx_vec & (1 << rp->tx_channel))
4209                         niu_txchan_intr(np, rp, ldn);
4210         }
4211 }
4212
4213 static void niu_schedule_napi(struct niu *np, struct niu_ldg *lp,
4214                               u64 v0, u64 v1, u64 v2)
4215 {
4216         if (likely(napi_schedule_prep(&lp->napi))) {
4217                 lp->v0 = v0;
4218                 lp->v1 = v1;
4219                 lp->v2 = v2;
4220                 __niu_fastpath_interrupt(np, lp->ldg_num, v0);
4221                 __napi_schedule(&lp->napi);
4222         }
4223 }
4224
4225 static irqreturn_t niu_interrupt(int irq, void *dev_id)
4226 {
4227         struct niu_ldg *lp = dev_id;
4228         struct niu *np = lp->np;
4229         int ldg = lp->ldg_num;
4230         unsigned long flags;
4231         u64 v0, v1, v2;
4232
4233         if (netif_msg_intr(np))
4234                 printk(KERN_DEBUG KBUILD_MODNAME ": " "%s() ldg[%p](%d)",
4235                        __func__, lp, ldg);
4236
4237         spin_lock_irqsave(&np->lock, flags);
4238
4239         v0 = nr64(LDSV0(ldg));
4240         v1 = nr64(LDSV1(ldg));
4241         v2 = nr64(LDSV2(ldg));
4242
4243         if (netif_msg_intr(np))
4244                 pr_cont(" v0[%llx] v1[%llx] v2[%llx]\n",
4245                        (unsigned long long) v0,
4246                        (unsigned long long) v1,
4247                        (unsigned long long) v2);
4248
4249         if (unlikely(!v0 && !v1 && !v2)) {
4250                 spin_unlock_irqrestore(&np->lock, flags);
4251                 return IRQ_NONE;
4252         }
4253
4254         if (unlikely((v0 & ((u64)1 << LDN_MIF)) || v1 || v2)) {
4255                 int err = niu_slowpath_interrupt(np, lp, v0, v1, v2);
4256                 if (err)
4257                         goto out;
4258         }
4259         if (likely(v0 & ~((u64)1 << LDN_MIF)))
4260                 niu_schedule_napi(np, lp, v0, v1, v2);
4261         else
4262                 niu_ldg_rearm(np, lp, 1);
4263 out:
4264         spin_unlock_irqrestore(&np->lock, flags);
4265
4266         return IRQ_HANDLED;
4267 }
4268
4269 static void niu_free_rx_ring_info(struct niu *np, struct rx_ring_info *rp)
4270 {
4271         if (rp->mbox) {
4272                 np->ops->free_coherent(np->device,
4273                                        sizeof(struct rxdma_mailbox),
4274                                        rp->mbox, rp->mbox_dma);
4275                 rp->mbox = NULL;
4276         }
4277         if (rp->rcr) {
4278                 np->ops->free_coherent(np->device,
4279                                        MAX_RCR_RING_SIZE * sizeof(__le64),
4280                                        rp->rcr, rp->rcr_dma);
4281                 rp->rcr = NULL;
4282                 rp->rcr_table_size = 0;
4283                 rp->rcr_index = 0;
4284         }
4285         if (rp->rbr) {
4286                 niu_rbr_free(np, rp);
4287
4288                 np->ops->free_coherent(np->device,
4289                                        MAX_RBR_RING_SIZE * sizeof(__le32),
4290                                        rp->rbr, rp->rbr_dma);
4291                 rp->rbr = NULL;
4292                 rp->rbr_table_size = 0;
4293                 rp->rbr_index = 0;
4294         }
4295         kfree(rp->rxhash);
4296         rp->rxhash = NULL;
4297 }
4298
4299 static void niu_free_tx_ring_info(struct niu *np, struct tx_ring_info *rp)
4300 {
4301         if (rp->mbox) {
4302                 np->ops->free_coherent(np->device,
4303                                        sizeof(struct txdma_mailbox),
4304                                        rp->mbox, rp->mbox_dma);
4305                 rp->mbox = NULL;
4306         }
4307         if (rp->descr) {
4308                 int i;
4309
4310                 for (i = 0; i < MAX_TX_RING_SIZE; i++) {
4311                         if (rp->tx_buffs[i].skb)
4312                                 (void) release_tx_packet(np, rp, i);
4313                 }
4314
4315                 np->ops->free_coherent(np->device,
4316                                        MAX_TX_RING_SIZE * sizeof(__le64),
4317                                        rp->descr, rp->descr_dma);
4318                 rp->descr = NULL;
4319                 rp->pending = 0;
4320                 rp->prod = 0;
4321                 rp->cons = 0;
4322                 rp->wrap_bit = 0;
4323         }
4324 }
4325
4326 static void niu_free_channels(struct niu *np)
4327 {
4328         int i;
4329
4330         if (np->rx_rings) {
4331                 for (i = 0; i < np->num_rx_rings; i++) {
4332                         struct rx_ring_info *rp = &np->rx_rings[i];
4333
4334                         niu_free_rx_ring_info(np, rp);
4335                 }
4336                 kfree(np->rx_rings);
4337                 np->rx_rings = NULL;
4338                 np->num_rx_rings = 0;
4339         }
4340
4341         if (np->tx_rings) {
4342                 for (i = 0; i < np->num_tx_rings; i++) {
4343                         struct tx_ring_info *rp = &np->tx_rings[i];
4344
4345                         niu_free_tx_ring_info(np, rp);
4346                 }
4347                 kfree(np->tx_rings);
4348                 np->tx_rings = NULL;
4349                 np->num_tx_rings = 0;
4350         }
4351 }
4352
4353 static int niu_alloc_rx_ring_info(struct niu *np,
4354                                   struct rx_ring_info *rp)
4355 {
4356         BUILD_BUG_ON(sizeof(struct rxdma_mailbox) != 64);
4357
4358         rp->rxhash = kzalloc(MAX_RBR_RING_SIZE * sizeof(struct page *),
4359                              GFP_KERNEL);
4360         if (!rp->rxhash)
4361                 return -ENOMEM;
4362
4363         rp->mbox = np->ops->alloc_coherent(np->device,
4364                                            sizeof(struct rxdma_mailbox),
4365                                            &rp->mbox_dma, GFP_KERNEL);
4366         if (!rp->mbox)
4367                 return -ENOMEM;
4368         if ((unsigned long)rp->mbox & (64UL - 1)) {
4369                 netdev_err(np->dev, "Coherent alloc gives misaligned RXDMA mailbox %p\n",
4370                            rp->mbox);
4371                 return -EINVAL;
4372         }
4373
4374         rp->rcr = np->ops->alloc_coherent(np->device,
4375                                           MAX_RCR_RING_SIZE * sizeof(__le64),
4376                                           &rp->rcr_dma, GFP_KERNEL);
4377         if (!rp->rcr)
4378                 return -ENOMEM;
4379         if ((unsigned long)rp->rcr & (64UL - 1)) {
4380                 netdev_err(np->dev, "Coherent alloc gives misaligned RXDMA RCR table %p\n",
4381                            rp->rcr);
4382                 return -EINVAL;
4383         }
4384         rp->rcr_table_size = MAX_RCR_RING_SIZE;
4385         rp->rcr_index = 0;
4386
4387         rp->rbr = np->ops->alloc_coherent(np->device,
4388                                           MAX_RBR_RING_SIZE * sizeof(__le32),
4389                                           &rp->rbr_dma, GFP_KERNEL);
4390         if (!rp->rbr)
4391                 return -ENOMEM;
4392         if ((unsigned long)rp->rbr & (64UL - 1)) {
4393                 netdev_err(np->dev, "Coherent alloc gives misaligned RXDMA RBR table %p\n",
4394                            rp->rbr);
4395                 return -EINVAL;
4396         }
4397         rp->rbr_table_size = MAX_RBR_RING_SIZE;
4398         rp->rbr_index = 0;
4399         rp->rbr_pending = 0;
4400
4401         return 0;
4402 }
4403
4404 static void niu_set_max_burst(struct niu *np, struct tx_ring_info *rp)
4405 {
4406         int mtu = np->dev->mtu;
4407
4408         /* These values are recommended by the HW designers for fair
4409          * utilization of DRR amongst the rings.
4410          */
4411         rp->max_burst = mtu + 32;
4412         if (rp->max_burst > 4096)
4413                 rp->max_burst = 4096;
4414 }
4415
4416 static int niu_alloc_tx_ring_info(struct niu *np,
4417                                   struct tx_ring_info *rp)
4418 {
4419         BUILD_BUG_ON(sizeof(struct txdma_mailbox) != 64);
4420
4421         rp->mbox = np->ops->alloc_coherent(np->device,
4422                                            sizeof(struct txdma_mailbox),
4423                                            &rp->mbox_dma, GFP_KERNEL);
4424         if (!rp->mbox)
4425                 return -ENOMEM;
4426         if ((unsigned long)rp->mbox & (64UL - 1)) {
4427                 netdev_err(np->dev, "Coherent alloc gives misaligned TXDMA mailbox %p\n",
4428                            rp->mbox);
4429                 return -EINVAL;
4430         }
4431
4432         rp->descr = np->ops->alloc_coherent(np->device,
4433                                             MAX_TX_RING_SIZE * sizeof(__le64),
4434                                             &rp->descr_dma, GFP_KERNEL);
4435         if (!rp->descr)
4436                 return -ENOMEM;
4437         if ((unsigned long)rp->descr & (64UL - 1)) {
4438                 netdev_err(np->dev, "Coherent alloc gives misaligned TXDMA descr table %p\n",
4439                            rp->descr);
4440                 return -EINVAL;
4441         }
4442
4443         rp->pending = MAX_TX_RING_SIZE;
4444         rp->prod = 0;
4445         rp->cons = 0;
4446         rp->wrap_bit = 0;
4447
4448         /* XXX make these configurable... XXX */
4449         rp->mark_freq = rp->pending / 4;
4450
4451         niu_set_max_burst(np, rp);
4452
4453         return 0;
4454 }
4455
4456 static void niu_size_rbr(struct niu *np, struct rx_ring_info *rp)
4457 {
4458         u16 bss;
4459
4460         bss = min(PAGE_SHIFT, 15);
4461
4462         rp->rbr_block_size = 1 << bss;
4463         rp->rbr_blocks_per_page = 1 << (PAGE_SHIFT-bss);
4464
4465         rp->rbr_sizes[0] = 256;
4466         rp->rbr_sizes[1] = 1024;
4467         if (np->dev->mtu > ETH_DATA_LEN) {
4468                 switch (PAGE_SIZE) {
4469                 case 4 * 1024:
4470                         rp->rbr_sizes[2] = 4096;
4471                         break;
4472
4473                 default:
4474                         rp->rbr_sizes[2] = 8192;
4475                         break;
4476                 }
4477         } else {
4478                 rp->rbr_sizes[2] = 2048;
4479         }
4480         rp->rbr_sizes[3] = rp->rbr_block_size;
4481 }
4482
4483 static int niu_alloc_channels(struct niu *np)
4484 {
4485         struct niu_parent *parent = np->parent;
4486         int first_rx_channel, first_tx_channel;
4487         int i, port, err;
4488
4489         port = np->port;
4490         first_rx_channel = first_tx_channel = 0;
4491         for (i = 0; i < port; i++) {
4492                 first_rx_channel += parent->rxchan_per_port[i];
4493                 first_tx_channel += parent->txchan_per_port[i];
4494         }
4495
4496         np->num_rx_rings = parent->rxchan_per_port[port];
4497         np->num_tx_rings = parent->txchan_per_port[port];
4498
4499         np->dev->real_num_tx_queues = np->num_tx_rings;
4500
4501         np->rx_rings = kzalloc(np->num_rx_rings * sizeof(struct rx_ring_info),
4502                                GFP_KERNEL);
4503         err = -ENOMEM;
4504         if (!np->rx_rings)
4505                 goto out_err;
4506
4507         for (i = 0; i < np->num_rx_rings; i++) {
4508                 struct rx_ring_info *rp = &np->rx_rings[i];
4509
4510                 rp->np = np;
4511                 rp->rx_channel = first_rx_channel + i;
4512
4513                 err = niu_alloc_rx_ring_info(np, rp);
4514                 if (err)
4515                         goto out_err;
4516
4517                 niu_size_rbr(np, rp);
4518
4519                 /* XXX better defaults, configurable, etc... XXX */
4520                 rp->nonsyn_window = 64;
4521                 rp->nonsyn_threshold = rp->rcr_table_size - 64;
4522                 rp->syn_window = 64;
4523                 rp->syn_threshold = rp->rcr_table_size - 64;
4524                 rp->rcr_pkt_threshold = 16;
4525                 rp->rcr_timeout = 8;
4526                 rp->rbr_kick_thresh = RBR_REFILL_MIN;
4527                 if (rp->rbr_kick_thresh < rp->rbr_blocks_per_page)
4528                         rp->rbr_kick_thresh = rp->rbr_blocks_per_page;
4529
4530                 err = niu_rbr_fill(np, rp, GFP_KERNEL);
4531                 if (err)
4532                         return err;
4533         }
4534
4535         np->tx_rings = kzalloc(np->num_tx_rings * sizeof(struct tx_ring_info),
4536                                GFP_KERNEL);
4537         err = -ENOMEM;
4538         if (!np->tx_rings)
4539                 goto out_err;
4540
4541         for (i = 0; i < np->num_tx_rings; i++) {
4542                 struct tx_ring_info *rp = &np->tx_rings[i];
4543
4544                 rp->np = np;
4545                 rp->tx_channel = first_tx_channel + i;
4546
4547                 err = niu_alloc_tx_ring_info(np, rp);
4548                 if (err)
4549                         goto out_err;
4550         }
4551
4552         return 0;
4553
4554 out_err:
4555         niu_free_channels(np);
4556         return err;
4557 }
4558
4559 static int niu_tx_cs_sng_poll(struct niu *np, int channel)
4560 {
4561         int limit = 1000;
4562
4563         while (--limit > 0) {
4564                 u64 val = nr64(TX_CS(channel));
4565                 if (val & TX_CS_SNG_STATE)
4566                         return 0;
4567         }
4568         return -ENODEV;
4569 }
4570
4571 static int niu_tx_channel_stop(struct niu *np, int channel)
4572 {
4573         u64 val = nr64(TX_CS(channel));
4574
4575         val |= TX_CS_STOP_N_GO;
4576         nw64(TX_CS(channel), val);
4577
4578         return niu_tx_cs_sng_poll(np, channel);
4579 }
4580
4581 static int niu_tx_cs_reset_poll(struct niu *np, int channel)
4582 {
4583         int limit = 1000;
4584
4585         while (--limit > 0) {
4586                 u64 val = nr64(TX_CS(channel));
4587                 if (!(val & TX_CS_RST))
4588                         return 0;
4589         }
4590         return -ENODEV;
4591 }
4592
4593 static int niu_tx_channel_reset(struct niu *np, int channel)
4594 {
4595         u64 val = nr64(TX_CS(channel));
4596         int err;
4597
4598         val |= TX_CS_RST;
4599         nw64(TX_CS(channel), val);
4600
4601         err = niu_tx_cs_reset_poll(np, channel);
4602         if (!err)
4603                 nw64(TX_RING_KICK(channel), 0);
4604
4605         return err;
4606 }
4607
4608 static int niu_tx_channel_lpage_init(struct niu *np, int channel)
4609 {
4610         u64 val;
4611
4612         nw64(TX_LOG_MASK1(channel), 0);
4613         nw64(TX_LOG_VAL1(channel), 0);
4614         nw64(TX_LOG_MASK2(channel), 0);
4615         nw64(TX_LOG_VAL2(channel), 0);
4616         nw64(TX_LOG_PAGE_RELO1(channel), 0);
4617         nw64(TX_LOG_PAGE_RELO2(channel), 0);
4618         nw64(TX_LOG_PAGE_HDL(channel), 0);
4619
4620         val  = (u64)np->port << TX_LOG_PAGE_VLD_FUNC_SHIFT;
4621         val |= (TX_LOG_PAGE_VLD_PAGE0 | TX_LOG_PAGE_VLD_PAGE1);
4622         nw64(TX_LOG_PAGE_VLD(channel), val);
4623
4624         /* XXX TXDMA 32bit mode? XXX */
4625
4626         return 0;
4627 }
4628
4629 static void niu_txc_enable_port(struct niu *np, int on)
4630 {
4631         unsigned long flags;
4632         u64 val, mask;
4633
4634         niu_lock_parent(np, flags);
4635         val = nr64(TXC_CONTROL);
4636         mask = (u64)1 << np->port;
4637         if (on) {
4638                 val |= TXC_CONTROL_ENABLE | mask;
4639         } else {
4640                 val &= ~mask;
4641                 if ((val & ~TXC_CONTROL_ENABLE) == 0)
4642                         val &= ~TXC_CONTROL_ENABLE;
4643         }
4644         nw64(TXC_CONTROL, val);
4645         niu_unlock_parent(np, flags);
4646 }
4647
4648 static void niu_txc_set_imask(struct niu *np, u64 imask)
4649 {
4650         unsigned long flags;
4651         u64 val;
4652
4653         niu_lock_parent(np, flags);
4654         val = nr64(TXC_INT_MASK);
4655         val &= ~TXC_INT_MASK_VAL(np->port);
4656         val |= (imask << TXC_INT_MASK_VAL_SHIFT(np->port));
4657         niu_unlock_parent(np, flags);
4658 }
4659
4660 static void niu_txc_port_dma_enable(struct niu *np, int on)
4661 {
4662         u64 val = 0;
4663
4664         if (on) {
4665                 int i;
4666
4667                 for (i = 0; i < np->num_tx_rings; i++)
4668                         val |= (1 << np->tx_rings[i].tx_channel);
4669         }
4670         nw64(TXC_PORT_DMA(np->port), val);
4671 }
4672
4673 static int niu_init_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
4674 {
4675         int err, channel = rp->tx_channel;
4676         u64 val, ring_len;
4677
4678         err = niu_tx_channel_stop(np, channel);
4679         if (err)
4680                 return err;
4681
4682         err = niu_tx_channel_reset(np, channel);
4683         if (err)
4684                 return err;
4685
4686         err = niu_tx_channel_lpage_init(np, channel);
4687         if (err)
4688                 return err;
4689
4690         nw64(TXC_DMA_MAX(channel), rp->max_burst);
4691         nw64(TX_ENT_MSK(channel), 0);
4692
4693         if (rp->descr_dma & ~(TX_RNG_CFIG_STADDR_BASE |
4694                               TX_RNG_CFIG_STADDR)) {
4695                 netdev_err(np->dev, "TX ring channel %d DMA addr (%llx) is not aligned\n",
4696                            channel, (unsigned long long)rp->descr_dma);
4697                 return -EINVAL;
4698         }
4699
4700         /* The length field in TX_RNG_CFIG is measured in 64-byte
4701          * blocks.  rp->pending is the number of TX descriptors in
4702          * our ring, 8 bytes each, thus we divide by 8 bytes more
4703          * to get the proper value the chip wants.
4704          */
4705         ring_len = (rp->pending / 8);
4706
4707         val = ((ring_len << TX_RNG_CFIG_LEN_SHIFT) |
4708                rp->descr_dma);
4709         nw64(TX_RNG_CFIG(channel), val);
4710
4711         if (((rp->mbox_dma >> 32) & ~TXDMA_MBH_MBADDR) ||
4712             ((u32)rp->mbox_dma & ~TXDMA_MBL_MBADDR)) {
4713                 netdev_err(np->dev, "TX ring channel %d MBOX addr (%llx) has invalid bits\n",
4714                             channel, (unsigned long long)rp->mbox_dma);
4715                 return -EINVAL;
4716         }
4717         nw64(TXDMA_MBH(channel), rp->mbox_dma >> 32);
4718         nw64(TXDMA_MBL(channel), rp->mbox_dma & TXDMA_MBL_MBADDR);
4719
4720         nw64(TX_CS(channel), 0);
4721
4722         rp->last_pkt_cnt = 0;
4723
4724         return 0;
4725 }
4726
4727 static void niu_init_rdc_groups(struct niu *np)
4728 {
4729         struct niu_rdc_tables *tp = &np->parent->rdc_group_cfg[np->port];
4730         int i, first_table_num = tp->first_table_num;
4731
4732         for (i = 0; i < tp->num_tables; i++) {
4733                 struct rdc_table *tbl = &tp->tables[i];
4734                 int this_table = first_table_num + i;
4735                 int slot;
4736
4737                 for (slot = 0; slot < NIU_RDC_TABLE_SLOTS; slot++)
4738                         nw64(RDC_TBL(this_table, slot),
4739                              tbl->rxdma_channel[slot]);
4740         }
4741
4742         nw64(DEF_RDC(np->port), np->parent->rdc_default[np->port]);
4743 }
4744
4745 static void niu_init_drr_weight(struct niu *np)
4746 {
4747         int type = phy_decode(np->parent->port_phy, np->port);
4748         u64 val;
4749
4750         switch (type) {
4751         case PORT_TYPE_10G:
4752                 val = PT_DRR_WEIGHT_DEFAULT_10G;
4753                 break;
4754
4755         case PORT_TYPE_1G:
4756         default:
4757                 val = PT_DRR_WEIGHT_DEFAULT_1G;
4758                 break;
4759         }
4760         nw64(PT_DRR_WT(np->port), val);
4761 }
4762
4763 static int niu_init_hostinfo(struct niu *np)
4764 {
4765         struct niu_parent *parent = np->parent;
4766         struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
4767         int i, err, num_alt = niu_num_alt_addr(np);
4768         int first_rdc_table = tp->first_table_num;
4769
4770         err = niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
4771         if (err)
4772                 return err;
4773
4774         err = niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
4775         if (err)
4776                 return err;
4777
4778         for (i = 0; i < num_alt; i++) {
4779                 err = niu_set_alt_mac_rdc_table(np, i, first_rdc_table, 1);
4780                 if (err)
4781                         return err;
4782         }
4783
4784         return 0;
4785 }
4786
4787 static int niu_rx_channel_reset(struct niu *np, int channel)
4788 {
4789         return niu_set_and_wait_clear(np, RXDMA_CFIG1(channel),
4790                                       RXDMA_CFIG1_RST, 1000, 10,
4791                                       "RXDMA_CFIG1");
4792 }
4793
4794 static int niu_rx_channel_lpage_init(struct niu *np, int channel)
4795 {
4796         u64 val;
4797
4798         nw64(RX_LOG_MASK1(channel), 0);
4799         nw64(RX_LOG_VAL1(channel), 0);
4800         nw64(RX_LOG_MASK2(channel), 0);
4801         nw64(RX_LOG_VAL2(channel), 0);
4802         nw64(RX_LOG_PAGE_RELO1(channel), 0);
4803         nw64(RX_LOG_PAGE_RELO2(channel), 0);
4804         nw64(RX_LOG_PAGE_HDL(channel), 0);
4805
4806         val  = (u64)np->port << RX_LOG_PAGE_VLD_FUNC_SHIFT;
4807         val |= (RX_LOG_PAGE_VLD_PAGE0 | RX_LOG_PAGE_VLD_PAGE1);
4808         nw64(RX_LOG_PAGE_VLD(channel), val);
4809
4810         return 0;
4811 }
4812
4813 static void niu_rx_channel_wred_init(struct niu *np, struct rx_ring_info *rp)
4814 {
4815         u64 val;
4816
4817         val = (((u64)rp->nonsyn_window << RDC_RED_PARA_WIN_SHIFT) |
4818                ((u64)rp->nonsyn_threshold << RDC_RED_PARA_THRE_SHIFT) |
4819                ((u64)rp->syn_window << RDC_RED_PARA_WIN_SYN_SHIFT) |
4820                ((u64)rp->syn_threshold << RDC_RED_PARA_THRE_SYN_SHIFT));
4821         nw64(RDC_RED_PARA(rp->rx_channel), val);
4822 }
4823
4824 static int niu_compute_rbr_cfig_b(struct rx_ring_info *rp, u64 *ret)
4825 {
4826         u64 val = 0;
4827
4828         *ret = 0;
4829         switch (rp->rbr_block_size) {
4830         case 4 * 1024:
4831                 val |= (RBR_BLKSIZE_4K << RBR_CFIG_B_BLKSIZE_SHIFT);
4832                 break;
4833         case 8 * 1024:
4834                 val |= (RBR_BLKSIZE_8K << RBR_CFIG_B_BLKSIZE_SHIFT);
4835                 break;
4836         case 16 * 1024:
4837                 val |= (RBR_BLKSIZE_16K << RBR_CFIG_B_BLKSIZE_SHIFT);
4838                 break;
4839         case 32 * 1024:
4840                 val |= (RBR_BLKSIZE_32K << RBR_CFIG_B_BLKSIZE_SHIFT);
4841                 break;
4842         default:
4843                 return -EINVAL;
4844         }
4845         val |= RBR_CFIG_B_VLD2;
4846         switch (rp->rbr_sizes[2]) {
4847         case 2 * 1024:
4848                 val |= (RBR_BUFSZ2_2K << RBR_CFIG_B_BUFSZ2_SHIFT);
4849                 break;
4850         case 4 * 1024:
4851                 val |= (RBR_BUFSZ2_4K << RBR_CFIG_B_BUFSZ2_SHIFT);
4852                 break;
4853         case 8 * 1024:
4854                 val |= (RBR_BUFSZ2_8K << RBR_CFIG_B_BUFSZ2_SHIFT);
4855                 break;
4856         case 16 * 1024:
4857                 val |= (RBR_BUFSZ2_16K << RBR_CFIG_B_BUFSZ2_SHIFT);
4858                 break;
4859
4860         default:
4861                 return -EINVAL;
4862         }
4863         val |= RBR_CFIG_B_VLD1;
4864         switch (rp->rbr_sizes[1]) {
4865         case 1 * 1024:
4866                 val |= (RBR_BUFSZ1_1K << RBR_CFIG_B_BUFSZ1_SHIFT);
4867                 break;
4868         case 2 * 1024:
4869                 val |= (RBR_BUFSZ1_2K << RBR_CFIG_B_BUFSZ1_SHIFT);
4870                 break;
4871         case 4 * 1024:
4872                 val |= (RBR_BUFSZ1_4K << RBR_CFIG_B_BUFSZ1_SHIFT);
4873                 break;
4874         case 8 * 1024:
4875                 val |= (RBR_BUFSZ1_8K << RBR_CFIG_B_BUFSZ1_SHIFT);
4876                 break;
4877
4878         default:
4879                 return -EINVAL;
4880         }
4881         val |= RBR_CFIG_B_VLD0;
4882         switch (rp->rbr_sizes[0]) {
4883         case 256:
4884                 val |= (RBR_BUFSZ0_256 << RBR_CFIG_B_BUFSZ0_SHIFT);
4885                 break;
4886         case 512:
4887                 val |= (RBR_BUFSZ0_512 << RBR_CFIG_B_BUFSZ0_SHIFT);
4888                 break;
4889         case 1 * 1024:
4890                 val |= (RBR_BUFSZ0_1K << RBR_CFIG_B_BUFSZ0_SHIFT);
4891                 break;
4892         case 2 * 1024:
4893                 val |= (RBR_BUFSZ0_2K << RBR_CFIG_B_BUFSZ0_SHIFT);
4894                 break;
4895
4896         default:
4897                 return -EINVAL;
4898         }
4899
4900         *ret = val;
4901         return 0;
4902 }
4903
4904 static int niu_enable_rx_channel(struct niu *np, int channel, int on)
4905 {
4906         u64 val = nr64(RXDMA_CFIG1(channel));
4907         int limit;
4908
4909         if (on)
4910                 val |= RXDMA_CFIG1_EN;
4911         else
4912                 val &= ~RXDMA_CFIG1_EN;
4913         nw64(RXDMA_CFIG1(channel), val);
4914
4915         limit = 1000;
4916         while (--limit > 0) {
4917                 if (nr64(RXDMA_CFIG1(channel)) & RXDMA_CFIG1_QST)
4918                         break;
4919                 udelay(10);
4920         }
4921         if (limit <= 0)
4922                 return -ENODEV;
4923         return 0;
4924 }
4925
4926 static int niu_init_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
4927 {
4928         int err, channel = rp->rx_channel;
4929         u64 val;
4930
4931         err = niu_rx_channel_reset(np, channel);
4932         if (err)
4933                 return err;
4934
4935         err = niu_rx_channel_lpage_init(np, channel);
4936         if (err)
4937                 return err;
4938
4939         niu_rx_channel_wred_init(np, rp);
4940
4941         nw64(RX_DMA_ENT_MSK(channel), RX_DMA_ENT_MSK_RBR_EMPTY);
4942         nw64(RX_DMA_CTL_STAT(channel),
4943              (RX_DMA_CTL_STAT_MEX |
4944               RX_DMA_CTL_STAT_RCRTHRES |
4945               RX_DMA_CTL_STAT_RCRTO |
4946               RX_DMA_CTL_STAT_RBR_EMPTY));
4947         nw64(RXDMA_CFIG1(channel), rp->mbox_dma >> 32);
4948         nw64(RXDMA_CFIG2(channel), (rp->mbox_dma & 0x00000000ffffffc0));
4949         nw64(RBR_CFIG_A(channel),
4950              ((u64)rp->rbr_table_size << RBR_CFIG_A_LEN_SHIFT) |
4951              (rp->rbr_dma & (RBR_CFIG_A_STADDR_BASE | RBR_CFIG_A_STADDR)));
4952         err = niu_compute_rbr_cfig_b(rp, &val);
4953         if (err)
4954                 return err;
4955         nw64(RBR_CFIG_B(channel), val);
4956         nw64(RCRCFIG_A(channel),
4957              ((u64)rp->rcr_table_size << RCRCFIG_A_LEN_SHIFT) |
4958              (rp->rcr_dma & (RCRCFIG_A_STADDR_BASE | RCRCFIG_A_STADDR)));
4959         nw64(RCRCFIG_B(channel),
4960              ((u64)rp->rcr_pkt_threshold << RCRCFIG_B_PTHRES_SHIFT) |
4961              RCRCFIG_B_ENTOUT |
4962              ((u64)rp->rcr_timeout << RCRCFIG_B_TIMEOUT_SHIFT));
4963
4964         err = niu_enable_rx_channel(np, channel, 1);
4965         if (err)
4966                 return err;
4967
4968         nw64(RBR_KICK(channel), rp->rbr_index);
4969
4970         val = nr64(RX_DMA_CTL_STAT(channel));
4971         val |= RX_DMA_CTL_STAT_RBR_EMPTY;
4972         nw64(RX_DMA_CTL_STAT(channel), val);
4973
4974         return 0;
4975 }
4976
4977 static int niu_init_rx_channels(struct niu *np)
4978 {
4979         unsigned long flags;
4980         u64 seed = jiffies_64;
4981         int err, i;
4982
4983         niu_lock_parent(np, flags);
4984         nw64(RX_DMA_CK_DIV, np->parent->rxdma_clock_divider);
4985         nw64(RED_RAN_INIT, RED_RAN_INIT_OPMODE | (seed & RED_RAN_INIT_VAL));
4986         niu_unlock_parent(np, flags);
4987
4988         /* XXX RXDMA 32bit mode? XXX */
4989
4990         niu_init_rdc_groups(np);
4991         niu_init_drr_weight(np);
4992
4993         err = niu_init_hostinfo(np);
4994         if (err)
4995                 return err;
4996
4997         for (i = 0; i < np->num_rx_rings; i++) {
4998                 struct rx_ring_info *rp = &np->rx_rings[i];
4999
5000                 err = niu_init_one_rx_channel(np, rp);
5001                 if (err)
5002                         return err;
5003         }
5004
5005         return 0;
5006 }
5007
5008 static int niu_set_ip_frag_rule(struct niu *np)
5009 {
5010         struct niu_parent *parent = np->parent;
5011         struct niu_classifier *cp = &np->clas;
5012         struct niu_tcam_entry *tp;
5013         int index, err;
5014
5015         index = cp->tcam_top;
5016         tp = &parent->tcam[index];
5017
5018         /* Note that the noport bit is the same in both ipv4 and
5019          * ipv6 format TCAM entries.
5020          */
5021         memset(tp, 0, sizeof(*tp));
5022         tp->key[1] = TCAM_V4KEY1_NOPORT;
5023         tp->key_mask[1] = TCAM_V4KEY1_NOPORT;
5024         tp->assoc_data = (TCAM_ASSOCDATA_TRES_USE_OFFSET |
5025                           ((u64)0 << TCAM_ASSOCDATA_OFFSET_SHIFT));
5026         err = tcam_write(np, index, tp->key, tp->key_mask);
5027         if (err)
5028                 return err;
5029         err = tcam_assoc_write(np, index, tp->assoc_data);
5030         if (err)
5031                 return err;
5032         tp->valid = 1;
5033         cp->tcam_valid_entries++;
5034
5035         return 0;
5036 }
5037
5038 static int niu_init_classifier_hw(struct niu *np)
5039 {
5040         struct niu_parent *parent = np->parent;
5041         struct niu_classifier *cp = &np->clas;
5042         int i, err;
5043
5044         nw64(H1POLY, cp->h1_init);
5045         nw64(H2POLY, cp->h2_init);
5046
5047         err = niu_init_hostinfo(np);
5048         if (err)
5049                 return err;
5050
5051         for (i = 0; i < ENET_VLAN_TBL_NUM_ENTRIES; i++) {
5052                 struct niu_vlan_rdc *vp = &cp->vlan_mappings[i];
5053
5054                 vlan_tbl_write(np, i, np->port,
5055                                vp->vlan_pref, vp->rdc_num);
5056         }
5057
5058         for (i = 0; i < cp->num_alt_mac_mappings; i++) {
5059                 struct niu_altmac_rdc *ap = &cp->alt_mac_mappings[i];
5060
5061                 err = niu_set_alt_mac_rdc_table(np, ap->alt_mac_num,
5062                                                 ap->rdc_num, ap->mac_pref);
5063                 if (err)
5064                         return err;
5065         }
5066
5067         for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_SCTP_IPV6; i++) {
5068                 int index = i - CLASS_CODE_USER_PROG1;
5069
5070                 err = niu_set_tcam_key(np, i, parent->tcam_key[index]);
5071                 if (err)
5072                         return err;
5073                 err = niu_set_flow_key(np, i, parent->flow_key[index]);
5074                 if (err)
5075                         return err;
5076         }
5077
5078         err = niu_set_ip_frag_rule(np);
5079         if (err)
5080                 return err;
5081
5082         tcam_enable(np, 1);
5083
5084         return 0;
5085 }
5086
5087 static int niu_zcp_write(struct niu *np, int index, u64 *data)
5088 {
5089         nw64(ZCP_RAM_DATA0, data[0]);
5090         nw64(ZCP_RAM_DATA1, data[1]);
5091         nw64(ZCP_RAM_DATA2, data[2]);
5092         nw64(ZCP_RAM_DATA3, data[3]);
5093         nw64(ZCP_RAM_DATA4, data[4]);
5094         nw64(ZCP_RAM_BE, ZCP_RAM_BE_VAL);
5095         nw64(ZCP_RAM_ACC,
5096              (ZCP_RAM_ACC_WRITE |
5097               (0 << ZCP_RAM_ACC_ZFCID_SHIFT) |
5098               (ZCP_RAM_SEL_CFIFO(np->port) << ZCP_RAM_ACC_RAM_SEL_SHIFT)));
5099
5100         return niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
5101                                    1000, 100);
5102 }
5103
5104 static int niu_zcp_read(struct niu *np, int index, u64 *data)
5105 {
5106         int err;
5107
5108         err = niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
5109                                   1000, 100);
5110         if (err) {
5111                 netdev_err(np->dev, "ZCP read busy won't clear, ZCP_RAM_ACC[%llx]\n",
5112                            (unsigned long long)nr64(ZCP_RAM_ACC));
5113                 return err;
5114         }
5115
5116         nw64(ZCP_RAM_ACC,
5117              (ZCP_RAM_ACC_READ |
5118               (0 << ZCP_RAM_ACC_ZFCID_SHIFT) |
5119               (ZCP_RAM_SEL_CFIFO(np->port) << ZCP_RAM_ACC_RAM_SEL_SHIFT)));
5120
5121         err = niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
5122                                   1000, 100);
5123         if (err) {
5124                 netdev_err(np->dev, "ZCP read busy2 won't clear, ZCP_RAM_ACC[%llx]\n",
5125                            (unsigned long long)nr64(ZCP_RAM_ACC));
5126                 return err;
5127         }
5128
5129         data[0] = nr64(ZCP_RAM_DATA0);
5130         data[1] = nr64(ZCP_RAM_DATA1);
5131         data[2] = nr64(ZCP_RAM_DATA2);
5132         data[3] = nr64(ZCP_RAM_DATA3);
5133         data[4] = nr64(ZCP_RAM_DATA4);
5134
5135         return 0;
5136 }
5137
5138 static void niu_zcp_cfifo_reset(struct niu *np)
5139 {
5140         u64 val = nr64(RESET_CFIFO);
5141
5142         val |= RESET_CFIFO_RST(np->port);
5143         nw64(RESET_CFIFO, val);
5144         udelay(10);
5145
5146         val &= ~RESET_CFIFO_RST(np->port);
5147         nw64(RESET_CFIFO, val);
5148 }
5149
5150 static int niu_init_zcp(struct niu *np)
5151 {
5152         u64 data[5], rbuf[5];
5153         int i, max, err;
5154
5155         if (np->parent->plat_type != PLAT_TYPE_NIU) {
5156                 if (np->port == 0 || np->port == 1)
5157                         max = ATLAS_P0_P1_CFIFO_ENTRIES;
5158                 else
5159                         max = ATLAS_P2_P3_CFIFO_ENTRIES;
5160         } else
5161                 max = NIU_CFIFO_ENTRIES;
5162
5163         data[0] = 0;
5164         data[1] = 0;
5165         data[2] = 0;
5166         data[3] = 0;
5167         data[4] = 0;
5168
5169         for (i = 0; i < max; i++) {
5170                 err = niu_zcp_write(np, i, data);
5171                 if (err)
5172                         return err;
5173                 err = niu_zcp_read(np, i, rbuf);
5174                 if (err)
5175                         return err;
5176         }
5177
5178         niu_zcp_cfifo_reset(np);
5179         nw64(CFIFO_ECC(np->port), 0);
5180         nw64(ZCP_INT_STAT, ZCP_INT_STAT_ALL);
5181         (void) nr64(ZCP_INT_STAT);
5182         nw64(ZCP_INT_MASK, ZCP_INT_MASK_ALL);
5183
5184         return 0;
5185 }
5186
5187 static void niu_ipp_write(struct niu *np, int index, u64 *data)
5188 {
5189         u64 val = nr64_ipp(IPP_CFIG);
5190
5191         nw64_ipp(IPP_CFIG, val | IPP_CFIG_DFIFO_PIO_W);
5192         nw64_ipp(IPP_DFIFO_WR_PTR, index);
5193         nw64_ipp(IPP_DFIFO_WR0, data[0]);
5194         nw64_ipp(IPP_DFIFO_WR1, data[1]);
5195         nw64_ipp(IPP_DFIFO_WR2, data[2]);
5196         nw64_ipp(IPP_DFIFO_WR3, data[3]);
5197         nw64_ipp(IPP_DFIFO_WR4, data[4]);
5198         nw64_ipp(IPP_CFIG, val & ~IPP_CFIG_DFIFO_PIO_W);
5199 }
5200
5201 static void niu_ipp_read(struct niu *np, int index, u64 *data)
5202 {
5203         nw64_ipp(IPP_DFIFO_RD_PTR, index);
5204         data[0] = nr64_ipp(IPP_DFIFO_RD0);
5205         data[1] = nr64_ipp(IPP_DFIFO_RD1);
5206         data[2] = nr64_ipp(IPP_DFIFO_RD2);
5207         data[3] = nr64_ipp(IPP_DFIFO_RD3);
5208         data[4] = nr64_ipp(IPP_DFIFO_RD4);
5209 }
5210
5211 static int niu_ipp_reset(struct niu *np)
5212 {
5213         return niu_set_and_wait_clear_ipp(np, IPP_CFIG, IPP_CFIG_SOFT_RST,
5214                                           1000, 100, "IPP_CFIG");
5215 }
5216
5217 static int niu_init_ipp(struct niu *np)
5218 {
5219         u64 data[5], rbuf[5], val;
5220         int i, max, err;
5221
5222         if (np->parent->plat_type != PLAT_TYPE_NIU) {
5223                 if (np->port == 0 || np->port == 1)
5224                         max = ATLAS_P0_P1_DFIFO_ENTRIES;
5225                 else
5226                         max = ATLAS_P2_P3_DFIFO_ENTRIES;
5227         } else
5228                 max = NIU_DFIFO_ENTRIES;
5229
5230         data[0] = 0;
5231         data[1] = 0;
5232         data[2] = 0;
5233         data[3] = 0;
5234         data[4] = 0;
5235
5236         for (i = 0; i < max; i++) {
5237                 niu_ipp_write(np, i, data);
5238                 niu_ipp_read(np, i, rbuf);
5239         }
5240
5241         (void) nr64_ipp(IPP_INT_STAT);
5242         (void) nr64_ipp(IPP_INT_STAT);
5243
5244         err = niu_ipp_reset(np);
5245         if (err)
5246                 return err;
5247
5248         (void) nr64_ipp(IPP_PKT_DIS);
5249         (void) nr64_ipp(IPP_BAD_CS_CNT);
5250         (void) nr64_ipp(IPP_ECC);
5251
5252         (void) nr64_ipp(IPP_INT_STAT);
5253
5254         nw64_ipp(IPP_MSK, ~IPP_MSK_ALL);
5255
5256         val = nr64_ipp(IPP_CFIG);
5257         val &= ~IPP_CFIG_IP_MAX_PKT;
5258         val |= (IPP_CFIG_IPP_ENABLE |
5259                 IPP_CFIG_DFIFO_ECC_EN |
5260                 IPP_CFIG_DROP_BAD_CRC |
5261                 IPP_CFIG_CKSUM_EN |
5262                 (0x1ffff << IPP_CFIG_IP_MAX_PKT_SHIFT));
5263         nw64_ipp(IPP_CFIG, val);
5264
5265         return 0;
5266 }
5267
5268 static void niu_handle_led(struct niu *np, int status)
5269 {
5270         u64 val;
5271         val = nr64_mac(XMAC_CONFIG);
5272
5273         if ((np->flags & NIU_FLAGS_10G) != 0 &&
5274             (np->flags & NIU_FLAGS_FIBER) != 0) {
5275                 if (status) {
5276                         val |= XMAC_CONFIG_LED_POLARITY;
5277                         val &= ~XMAC_CONFIG_FORCE_LED_ON;
5278                 } else {
5279                         val |= XMAC_CONFIG_FORCE_LED_ON;
5280                         val &= ~XMAC_CONFIG_LED_POLARITY;
5281                 }
5282         }
5283
5284         nw64_mac(XMAC_CONFIG, val);
5285 }
5286
5287 static void niu_init_xif_xmac(struct niu *np)
5288 {
5289         struct niu_link_config *lp = &np->link_config;
5290         u64 val;
5291
5292         if (np->flags & NIU_FLAGS_XCVR_SERDES) {
5293                 val = nr64(MIF_CONFIG);
5294                 val |= MIF_CONFIG_ATCA_GE;
5295                 nw64(MIF_CONFIG, val);
5296         }
5297
5298         val = nr64_mac(XMAC_CONFIG);
5299         val &= ~XMAC_CONFIG_SEL_POR_CLK_SRC;
5300
5301         val |= XMAC_CONFIG_TX_OUTPUT_EN;
5302
5303         if (lp->loopback_mode == LOOPBACK_MAC) {
5304                 val &= ~XMAC_CONFIG_SEL_POR_CLK_SRC;
5305                 val |= XMAC_CONFIG_LOOPBACK;
5306         } else {
5307                 val &= ~XMAC_CONFIG_LOOPBACK;
5308         }
5309
5310         if (np->flags & NIU_FLAGS_10G) {
5311                 val &= ~XMAC_CONFIG_LFS_DISABLE;
5312         } else {
5313                 val |= XMAC_CONFIG_LFS_DISABLE;
5314                 if (!(np->flags & NIU_FLAGS_FIBER) &&
5315                     !(np->flags & NIU_FLAGS_XCVR_SERDES))
5316                         val |= XMAC_CONFIG_1G_PCS_BYPASS;
5317                 else
5318                         val &= ~XMAC_CONFIG_1G_PCS_BYPASS;
5319         }
5320
5321         val &= ~XMAC_CONFIG_10G_XPCS_BYPASS;
5322
5323         if (lp->active_speed == SPEED_100)
5324                 val |= XMAC_CONFIG_SEL_CLK_25MHZ;
5325         else
5326                 val &= ~XMAC_CONFIG_SEL_CLK_25MHZ;
5327
5328         nw64_mac(XMAC_CONFIG, val);
5329
5330         val = nr64_mac(XMAC_CONFIG);
5331         val &= ~XMAC_CONFIG_MODE_MASK;
5332         if (np->flags & NIU_FLAGS_10G) {
5333                 val |= XMAC_CONFIG_MODE_XGMII;
5334         } else {
5335                 if (lp->active_speed == SPEED_1000)
5336                         val |= XMAC_CONFIG_MODE_GMII;
5337                 else
5338                         val |= XMAC_CONFIG_MODE_MII;
5339         }
5340
5341         nw64_mac(XMAC_CONFIG, val);
5342 }
5343
5344 static void niu_init_xif_bmac(struct niu *np)
5345 {
5346         struct niu_link_config *lp = &np->link_config;
5347         u64 val;
5348
5349         val = BMAC_XIF_CONFIG_TX_OUTPUT_EN;
5350
5351         if (lp->loopback_mode == LOOPBACK_MAC)
5352                 val |= BMAC_XIF_CONFIG_MII_LOOPBACK;
5353         else
5354                 val &= ~BMAC_XIF_CONFIG_MII_LOOPBACK;
5355
5356         if (lp->active_speed == SPEED_1000)
5357                 val |= BMAC_XIF_CONFIG_GMII_MODE;
5358         else
5359                 val &= ~BMAC_XIF_CONFIG_GMII_MODE;
5360
5361         val &= ~(BMAC_XIF_CONFIG_LINK_LED |
5362                  BMAC_XIF_CONFIG_LED_POLARITY);
5363
5364         if (!(np->flags & NIU_FLAGS_10G) &&
5365             !(np->flags & NIU_FLAGS_FIBER) &&
5366             lp->active_speed == SPEED_100)
5367                 val |= BMAC_XIF_CONFIG_25MHZ_CLOCK;
5368         else
5369                 val &= ~BMAC_XIF_CONFIG_25MHZ_CLOCK;
5370
5371         nw64_mac(BMAC_XIF_CONFIG, val);
5372 }
5373
5374 static void niu_init_xif(struct niu *np)
5375 {
5376         if (np->flags & NIU_FLAGS_XMAC)
5377                 niu_init_xif_xmac(np);
5378         else
5379                 niu_init_xif_bmac(np);
5380 }
5381
5382 static void niu_pcs_mii_reset(struct niu *np)
5383 {
5384         int limit = 1000;
5385         u64 val = nr64_pcs(PCS_MII_CTL);
5386         val |= PCS_MII_CTL_RST;
5387         nw64_pcs(PCS_MII_CTL, val);
5388         while ((--limit >= 0) && (val & PCS_MII_CTL_RST)) {
5389                 udelay(100);
5390                 val = nr64_pcs(PCS_MII_CTL);
5391         }
5392 }
5393
5394 static void niu_xpcs_reset(struct niu *np)
5395 {
5396         int limit = 1000;
5397         u64 val = nr64_xpcs(XPCS_CONTROL1);
5398         val |= XPCS_CONTROL1_RESET;
5399         nw64_xpcs(XPCS_CONTROL1, val);
5400         while ((--limit >= 0) && (val & XPCS_CONTROL1_RESET)) {
5401                 udelay(100);
5402                 val = nr64_xpcs(XPCS_CONTROL1);
5403         }
5404 }
5405
5406 static int niu_init_pcs(struct niu *np)
5407 {
5408         struct niu_link_config *lp = &np->link_config;
5409         u64 val;
5410
5411         switch (np->flags & (NIU_FLAGS_10G |
5412                              NIU_FLAGS_FIBER |
5413                              NIU_FLAGS_XCVR_SERDES)) {
5414         case NIU_FLAGS_FIBER:
5415                 /* 1G fiber */
5416                 nw64_pcs(PCS_CONF, PCS_CONF_MASK | PCS_CONF_ENABLE);
5417                 nw64_pcs(PCS_DPATH_MODE, 0);
5418                 niu_pcs_mii_reset(np);
5419                 break;
5420
5421         case NIU_FLAGS_10G:
5422         case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
5423         case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES:
5424                 /* 10G SERDES */
5425                 if (!(np->flags & NIU_FLAGS_XMAC))
5426                         return -EINVAL;
5427
5428                 /* 10G copper or fiber */
5429                 val = nr64_mac(XMAC_CONFIG);
5430                 val &= ~XMAC_CONFIG_10G_XPCS_BYPASS;
5431                 nw64_mac(XMAC_CONFIG, val);
5432
5433                 niu_xpcs_reset(np);
5434
5435                 val = nr64_xpcs(XPCS_CONTROL1);
5436                 if (lp->loopback_mode == LOOPBACK_PHY)
5437                         val |= XPCS_CONTROL1_LOOPBACK;
5438                 else
5439                         val &= ~XPCS_CONTROL1_LOOPBACK;
5440                 nw64_xpcs(XPCS_CONTROL1, val);
5441
5442                 nw64_xpcs(XPCS_DESKEW_ERR_CNT, 0);
5443                 (void) nr64_xpcs(XPCS_SYMERR_CNT01);
5444                 (void) nr64_xpcs(XPCS_SYMERR_CNT23);
5445                 break;
5446
5447
5448         case NIU_FLAGS_XCVR_SERDES:
5449                 /* 1G SERDES */
5450                 niu_pcs_mii_reset(np);
5451                 nw64_pcs(PCS_CONF, PCS_CONF_MASK | PCS_CONF_ENABLE);
5452                 nw64_pcs(PCS_DPATH_MODE, 0);
5453                 break;
5454
5455         case 0:
5456                 /* 1G copper */
5457         case NIU_FLAGS_XCVR_SERDES | NIU_FLAGS_FIBER:
5458                 /* 1G RGMII FIBER */
5459                 nw64_pcs(PCS_DPATH_MODE, PCS_DPATH_MODE_MII);
5460                 niu_pcs_mii_reset(np);
5461                 break;
5462
5463         default:
5464                 return -EINVAL;
5465         }
5466
5467         return 0;
5468 }
5469
5470 static int niu_reset_tx_xmac(struct niu *np)
5471 {
5472         return niu_set_and_wait_clear_mac(np, XTXMAC_SW_RST,
5473                                           (XTXMAC_SW_RST_REG_RS |
5474                                            XTXMAC_SW_RST_SOFT_RST),
5475                                           1000, 100, "XTXMAC_SW_RST");
5476 }
5477
5478 static int niu_reset_tx_bmac(struct niu *np)
5479 {
5480         int limit;
5481
5482         nw64_mac(BTXMAC_SW_RST, BTXMAC_SW_RST_RESET);
5483         limit = 1000;
5484         while (--limit >= 0) {
5485                 if (!(nr64_mac(BTXMAC_SW_RST) & BTXMAC_SW_RST_RESET))
5486                         break;
5487                 udelay(100);
5488         }
5489         if (limit < 0) {
5490                 dev_err(np->device, "Port %u TX BMAC would not reset, BTXMAC_SW_RST[%llx]\n",
5491                         np->port,
5492                         (unsigned long long) nr64_mac(BTXMAC_SW_RST));
5493                 return -ENODEV;
5494         }
5495
5496         return 0;
5497 }
5498
5499 static int niu_reset_tx_mac(struct niu *np)
5500 {
5501         if (np->flags & NIU_FLAGS_XMAC)
5502                 return niu_reset_tx_xmac(np);
5503         else
5504                 return niu_reset_tx_bmac(np);
5505 }
5506
5507 static void niu_init_tx_xmac(struct niu *np, u64 min, u64 max)
5508 {
5509         u64 val;
5510
5511         val = nr64_mac(XMAC_MIN);
5512         val &= ~(XMAC_MIN_TX_MIN_PKT_SIZE |
5513                  XMAC_MIN_RX_MIN_PKT_SIZE);
5514         val |= (min << XMAC_MIN_RX_MIN_PKT_SIZE_SHFT);
5515         val |= (min << XMAC_MIN_TX_MIN_PKT_SIZE_SHFT);
5516         nw64_mac(XMAC_MIN, val);
5517
5518         nw64_mac(XMAC_MAX, max);
5519
5520         nw64_mac(XTXMAC_STAT_MSK, ~(u64)0);
5521
5522         val = nr64_mac(XMAC_IPG);
5523         if (np->flags & NIU_FLAGS_10G) {
5524                 val &= ~XMAC_IPG_IPG_XGMII;
5525                 val |= (IPG_12_15_XGMII << XMAC_IPG_IPG_XGMII_SHIFT);
5526         } else {
5527                 val &= ~XMAC_IPG_IPG_MII_GMII;
5528                 val |= (IPG_12_MII_GMII << XMAC_IPG_IPG_MII_GMII_SHIFT);
5529         }
5530         nw64_mac(XMAC_IPG, val);
5531
5532         val = nr64_mac(XMAC_CONFIG);
5533         val &= ~(XMAC_CONFIG_ALWAYS_NO_CRC |
5534                  XMAC_CONFIG_STRETCH_MODE |
5535                  XMAC_CONFIG_VAR_MIN_IPG_EN |
5536                  XMAC_CONFIG_TX_ENABLE);
5537         nw64_mac(XMAC_CONFIG, val);
5538
5539         nw64_mac(TXMAC_FRM_CNT, 0);
5540         nw64_mac(TXMAC_BYTE_CNT, 0);
5541 }
5542
5543 static void niu_init_tx_bmac(struct niu *np, u64 min, u64 max)
5544 {
5545         u64 val;
5546
5547         nw64_mac(BMAC_MIN_FRAME, min);
5548         nw64_mac(BMAC_MAX_FRAME, max);
5549
5550         nw64_mac(BTXMAC_STATUS_MASK, ~(u64)0);
5551         nw64_mac(BMAC_CTRL_TYPE, 0x8808);
5552         nw64_mac(BMAC_PREAMBLE_SIZE, 7);
5553
5554         val = nr64_mac(BTXMAC_CONFIG);
5555         val &= ~(BTXMAC_CONFIG_FCS_DISABLE |
5556                  BTXMAC_CONFIG_ENABLE);
5557         nw64_mac(BTXMAC_CONFIG, val);
5558 }
5559
5560 static void niu_init_tx_mac(struct niu *np)
5561 {
5562         u64 min, max;
5563
5564         min = 64;
5565         if (np->dev->mtu > ETH_DATA_LEN)
5566                 max = 9216;
5567         else
5568                 max = 1522;
5569
5570         /* The XMAC_MIN register only accepts values for TX min which
5571          * have the low 3 bits cleared.
5572          */
5573         BUG_ON(min & 0x7);
5574
5575         if (np->flags & NIU_FLAGS_XMAC)
5576                 niu_init_tx_xmac(np, min, max);
5577         else
5578                 niu_init_tx_bmac(np, min, max);
5579 }
5580
5581 static int niu_reset_rx_xmac(struct niu *np)
5582 {
5583         int limit;
5584
5585         nw64_mac(XRXMAC_SW_RST,
5586                  XRXMAC_SW_RST_REG_RS | XRXMAC_SW_RST_SOFT_RST);
5587         limit = 1000;
5588         while (--limit >= 0) {
5589                 if (!(nr64_mac(XRXMAC_SW_RST) & (XRXMAC_SW_RST_REG_RS |
5590                                                  XRXMAC_SW_RST_SOFT_RST)))
5591                         break;
5592                 udelay(100);
5593         }
5594         if (limit < 0) {
5595                 dev_err(np->device, "Port %u RX XMAC would not reset, XRXMAC_SW_RST[%llx]\n",
5596                         np->port,
5597                         (unsigned long long) nr64_mac(XRXMAC_SW_RST));
5598                 return -ENODEV;
5599         }
5600
5601         return 0;
5602 }
5603
5604 static int niu_reset_rx_bmac(struct niu *np)
5605 {
5606         int limit;
5607
5608         nw64_mac(BRXMAC_SW_RST, BRXMAC_SW_RST_RESET);
5609         limit = 1000;
5610         while (--limit >= 0) {
5611                 if (!(nr64_mac(BRXMAC_SW_RST) & BRXMAC_SW_RST_RESET))
5612                         break;
5613                 udelay(100);
5614         }
5615         if (limit < 0) {
5616                 dev_err(np->device, "Port %u RX BMAC would not reset, BRXMAC_SW_RST[%llx]\n",
5617                         np->port,
5618                         (unsigned long long) nr64_mac(BRXMAC_SW_RST));
5619                 return -ENODEV;
5620         }
5621
5622         return 0;
5623 }
5624
5625 static int niu_reset_rx_mac(struct niu *np)
5626 {
5627         if (np->flags & NIU_FLAGS_XMAC)
5628                 return niu_reset_rx_xmac(np);
5629         else
5630                 return niu_reset_rx_bmac(np);
5631 }
5632
5633 static void niu_init_rx_xmac(struct niu *np)
5634 {
5635         struct niu_parent *parent = np->parent;
5636         struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
5637         int first_rdc_table = tp->first_table_num;
5638         unsigned long i;
5639         u64 val;
5640
5641         nw64_mac(XMAC_ADD_FILT0, 0);
5642         nw64_mac(XMAC_ADD_FILT1, 0);
5643         nw64_mac(XMAC_ADD_FILT2, 0);
5644         nw64_mac(XMAC_ADD_FILT12_MASK, 0);
5645         nw64_mac(XMAC_ADD_FILT00_MASK, 0);
5646         for (i = 0; i < MAC_NUM_HASH; i++)
5647                 nw64_mac(XMAC_HASH_TBL(i), 0);
5648         nw64_mac(XRXMAC_STAT_MSK, ~(u64)0);
5649         niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
5650         niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
5651
5652         val = nr64_mac(XMAC_CONFIG);
5653         val &= ~(XMAC_CONFIG_RX_MAC_ENABLE |
5654                  XMAC_CONFIG_PROMISCUOUS |
5655                  XMAC_CONFIG_PROMISC_GROUP |
5656                  XMAC_CONFIG_ERR_CHK_DIS |
5657                  XMAC_CONFIG_RX_CRC_CHK_DIS |
5658                  XMAC_CONFIG_RESERVED_MULTICAST |
5659                  XMAC_CONFIG_RX_CODEV_CHK_DIS |
5660                  XMAC_CONFIG_ADDR_FILTER_EN |
5661                  XMAC_CONFIG_RCV_PAUSE_ENABLE |
5662                  XMAC_CONFIG_STRIP_CRC |
5663                  XMAC_CONFIG_PASS_FLOW_CTRL |
5664                  XMAC_CONFIG_MAC2IPP_PKT_CNT_EN);
5665         val |= (XMAC_CONFIG_HASH_FILTER_EN);
5666         nw64_mac(XMAC_CONFIG, val);
5667
5668         nw64_mac(RXMAC_BT_CNT, 0);
5669         nw64_mac(RXMAC_BC_FRM_CNT, 0);
5670         nw64_mac(RXMAC_MC_FRM_CNT, 0);
5671         nw64_mac(RXMAC_FRAG_CNT, 0);
5672         nw64_mac(RXMAC_HIST_CNT1, 0);
5673         nw64_mac(RXMAC_HIST_CNT2, 0);
5674         nw64_mac(RXMAC_HIST_CNT3, 0);
5675         nw64_mac(RXMAC_HIST_CNT4, 0);
5676         nw64_mac(RXMAC_HIST_CNT5, 0);
5677         nw64_mac(RXMAC_HIST_CNT6, 0);
5678         nw64_mac(RXMAC_HIST_CNT7, 0);
5679         nw64_mac(RXMAC_MPSZER_CNT, 0);
5680         nw64_mac(RXMAC_CRC_ER_CNT, 0);
5681         nw64_mac(RXMAC_CD_VIO_CNT, 0);
5682         nw64_mac(LINK_FAULT_CNT, 0);
5683 }
5684
5685 static void niu_init_rx_bmac(struct niu *np)
5686 {
5687         struct niu_parent *parent = np->parent;
5688         struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
5689         int first_rdc_table = tp->first_table_num;
5690         unsigned long i;
5691         u64 val;
5692
5693         nw64_mac(BMAC_ADD_FILT0, 0);
5694         nw64_mac(BMAC_ADD_FILT1, 0);
5695         nw64_mac(BMAC_ADD_FILT2, 0);
5696         nw64_mac(BMAC_ADD_FILT12_MASK, 0);
5697         nw64_mac(BMAC_ADD_FILT00_MASK, 0);
5698         for (i = 0; i < MAC_NUM_HASH; i++)
5699                 nw64_mac(BMAC_HASH_TBL(i), 0);
5700         niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
5701         niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
5702         nw64_mac(BRXMAC_STATUS_MASK, ~(u64)0);
5703
5704         val = nr64_mac(BRXMAC_CONFIG);
5705         val &= ~(BRXMAC_CONFIG_ENABLE |
5706                  BRXMAC_CONFIG_STRIP_PAD |
5707                  BRXMAC_CONFIG_STRIP_FCS |
5708                  BRXMAC_CONFIG_PROMISC |
5709                  BRXMAC_CONFIG_PROMISC_GRP |
5710                  BRXMAC_CONFIG_ADDR_FILT_EN |
5711                  BRXMAC_CONFIG_DISCARD_DIS);
5712         val |= (BRXMAC_CONFIG_HASH_FILT_EN);
5713         nw64_mac(BRXMAC_CONFIG, val);
5714
5715         val = nr64_mac(BMAC_ADDR_CMPEN);
5716         val |= BMAC_ADDR_CMPEN_EN0;
5717         nw64_mac(BMAC_ADDR_CMPEN, val);
5718 }
5719
5720 static void niu_init_rx_mac(struct niu *np)
5721 {
5722         niu_set_primary_mac(np, np->dev->dev_addr);
5723
5724         if (np->flags & NIU_FLAGS_XMAC)
5725                 niu_init_rx_xmac(np);
5726         else
5727                 niu_init_rx_bmac(np);
5728 }
5729
5730 static void niu_enable_tx_xmac(struct niu *np, int on)
5731 {
5732         u64 val = nr64_mac(XMAC_CONFIG);
5733
5734         if (on)
5735                 val |= XMAC_CONFIG_TX_ENABLE;
5736         else
5737                 val &= ~XMAC_CONFIG_TX_ENABLE;
5738         nw64_mac(XMAC_CONFIG, val);
5739 }
5740
5741 static void niu_enable_tx_bmac(struct niu *np, int on)
5742 {
5743         u64 val = nr64_mac(BTXMAC_CONFIG);
5744
5745         if (on)
5746                 val |= BTXMAC_CONFIG_ENABLE;
5747         else
5748                 val &= ~BTXMAC_CONFIG_ENABLE;
5749         nw64_mac(BTXMAC_CONFIG, val);
5750 }
5751
5752 static void niu_enable_tx_mac(struct niu *np, int on)
5753 {
5754         if (np->flags & NIU_FLAGS_XMAC)
5755                 niu_enable_tx_xmac(np, on);
5756         else
5757                 niu_enable_tx_bmac(np, on);
5758 }
5759
5760 static void niu_enable_rx_xmac(struct niu *np, int on)
5761 {
5762         u64 val = nr64_mac(XMAC_CONFIG);
5763
5764         val &= ~(XMAC_CONFIG_HASH_FILTER_EN |
5765                  XMAC_CONFIG_PROMISCUOUS);
5766
5767         if (np->flags & NIU_FLAGS_MCAST)
5768                 val |= XMAC_CONFIG_HASH_FILTER_EN;
5769         if (np->flags & NIU_FLAGS_PROMISC)
5770                 val |= XMAC_CONFIG_PROMISCUOUS;
5771
5772         if (on)
5773                 val |= XMAC_CONFIG_RX_MAC_ENABLE;
5774         else
5775                 val &= ~XMAC_CONFIG_RX_MAC_ENABLE;
5776         nw64_mac(XMAC_CONFIG, val);
5777 }
5778
5779 static void niu_enable_rx_bmac(struct niu *np, int on)
5780 {
5781         u64 val = nr64_mac(BRXMAC_CONFIG);
5782
5783         val &= ~(BRXMAC_CONFIG_HASH_FILT_EN |
5784                  BRXMAC_CONFIG_PROMISC);
5785
5786         if (np->flags & NIU_FLAGS_MCAST)
5787                 val |= BRXMAC_CONFIG_HASH_FILT_EN;
5788         if (np->flags & NIU_FLAGS_PROMISC)
5789                 val |= BRXMAC_CONFIG_PROMISC;
5790
5791         if (on)
5792                 val |= BRXMAC_CONFIG_ENABLE;
5793         else
5794                 val &= ~BRXMAC_CONFIG_ENABLE;
5795         nw64_mac(BRXMAC_CONFIG, val);
5796 }
5797
5798 static void niu_enable_rx_mac(struct niu *np, int on)
5799 {
5800         if (np->flags & NIU_FLAGS_XMAC)
5801                 niu_enable_rx_xmac(np, on);
5802         else
5803                 niu_enable_rx_bmac(np, on);
5804 }
5805
5806 static int niu_init_mac(struct niu *np)
5807 {
5808         int err;
5809
5810         niu_init_xif(np);
5811         err = niu_init_pcs(np);
5812         if (err)
5813                 return err;
5814
5815         err = niu_reset_tx_mac(np);
5816         if (err)
5817                 return err;
5818         niu_init_tx_mac(np);
5819         err = niu_reset_rx_mac(np);
5820         if (err)
5821                 return err;
5822         niu_init_rx_mac(np);
5823
5824         /* This looks hookey but the RX MAC reset we just did will
5825          * undo some of the state we setup in niu_init_tx_mac() so we
5826          * have to call it again.  In particular, the RX MAC reset will
5827          * set the XMAC_MAX register back to it's default value.
5828          */
5829         niu_init_tx_mac(np);
5830         niu_enable_tx_mac(np, 1);
5831
5832         niu_enable_rx_mac(np, 1);
5833
5834         return 0;
5835 }
5836
5837 static void niu_stop_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
5838 {
5839         (void) niu_tx_channel_stop(np, rp->tx_channel);
5840 }
5841
5842 static void niu_stop_tx_channels(struct niu *np)
5843 {
5844         int i;
5845
5846         for (i = 0; i < np->num_tx_rings; i++) {
5847                 struct tx_ring_info *rp = &np->tx_rings[i];
5848
5849                 niu_stop_one_tx_channel(np, rp);
5850         }
5851 }
5852
5853 static void niu_reset_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
5854 {
5855         (void) niu_tx_channel_reset(np, rp->tx_channel);
5856 }
5857
5858 static void niu_reset_tx_channels(struct niu *np)
5859 {
5860         int i;
5861
5862         for (i = 0; i < np->num_tx_rings; i++) {
5863                 struct tx_ring_info *rp = &np->tx_rings[i];
5864
5865                 niu_reset_one_tx_channel(np, rp);
5866         }
5867 }
5868
5869 static void niu_stop_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
5870 {
5871         (void) niu_enable_rx_channel(np, rp->rx_channel, 0);
5872 }
5873
5874 static void niu_stop_rx_channels(struct niu *np)
5875 {
5876         int i;
5877
5878         for (i = 0; i < np->num_rx_rings; i++) {
5879                 struct rx_ring_info *rp = &np->rx_rings[i];
5880
5881                 niu_stop_one_rx_channel(np, rp);
5882         }
5883 }
5884
5885 static void niu_reset_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
5886 {
5887         int channel = rp->rx_channel;
5888
5889         (void) niu_rx_channel_reset(np, channel);
5890         nw64(RX_DMA_ENT_MSK(channel), RX_DMA_ENT_MSK_ALL);
5891         nw64(RX_DMA_CTL_STAT(channel), 0);
5892         (void) niu_enable_rx_channel(np, channel, 0);
5893 }
5894
5895 static void niu_reset_rx_channels(struct niu *np)
5896 {
5897         int i;
5898
5899         for (i = 0; i < np->num_rx_rings; i++) {
5900                 struct rx_ring_info *rp = &np->rx_rings[i];
5901
5902                 niu_reset_one_rx_channel(np, rp);
5903         }
5904 }
5905
5906 static void niu_disable_ipp(struct niu *np)
5907 {
5908         u64 rd, wr, val;
5909         int limit;
5910
5911         rd = nr64_ipp(IPP_DFIFO_RD_PTR);
5912         wr = nr64_ipp(IPP_DFIFO_WR_PTR);
5913         limit = 100;
5914         while (--limit >= 0 && (rd != wr)) {
5915                 rd = nr64_ipp(IPP_DFIFO_RD_PTR);
5916                 wr = nr64_ipp(IPP_DFIFO_WR_PTR);
5917         }
5918         if (limit < 0 &&
5919             (rd != 0 && wr != 1)) {
5920                 netdev_err(np->dev, "IPP would not quiesce, rd_ptr[%llx] wr_ptr[%llx]\n",
5921                            (unsigned long long)nr64_ipp(IPP_DFIFO_RD_PTR),
5922                            (unsigned long long)nr64_ipp(IPP_DFIFO_WR_PTR));
5923         }
5924
5925         val = nr64_ipp(IPP_CFIG);
5926         val &= ~(IPP_CFIG_IPP_ENABLE |
5927                  IPP_CFIG_DFIFO_ECC_EN |
5928                  IPP_CFIG_DROP_BAD_CRC |
5929                  IPP_CFIG_CKSUM_EN);
5930         nw64_ipp(IPP_CFIG, val);
5931
5932         (void) niu_ipp_reset(np);
5933 }
5934
5935 static int niu_init_hw(struct niu *np)
5936 {
5937         int i, err;
5938
5939         netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize TXC\n");
5940         niu_txc_enable_port(np, 1);
5941         niu_txc_port_dma_enable(np, 1);
5942         niu_txc_set_imask(np, 0);
5943
5944         netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize TX channels\n");
5945         for (i = 0; i < np->num_tx_rings; i++) {
5946                 struct tx_ring_info *rp = &np->tx_rings[i];
5947
5948                 err = niu_init_one_tx_channel(np, rp);
5949                 if (err)
5950                         return err;
5951         }
5952
5953         netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize RX channels\n");
5954         err = niu_init_rx_channels(np);
5955         if (err)
5956                 goto out_uninit_tx_channels;
5957
5958         netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize classifier\n");
5959         err = niu_init_classifier_hw(np);
5960         if (err)
5961                 goto out_uninit_rx_channels;
5962
5963         netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize ZCP\n");
5964         err = niu_init_zcp(np);
5965         if (err)
5966                 goto out_uninit_rx_channels;
5967
5968         netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize IPP\n");
5969         err = niu_init_ipp(np);
5970         if (err)
5971                 goto out_uninit_rx_channels;
5972
5973         netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize MAC\n");
5974         err = niu_init_mac(np);
5975         if (err)
5976                 goto out_uninit_ipp;
5977
5978         return 0;
5979
5980 out_uninit_ipp:
5981         netif_printk(np, ifup, KERN_DEBUG, np->dev, "Uninit IPP\n");
5982         niu_disable_ipp(np);
5983
5984 out_uninit_rx_channels:
5985         netif_printk(np, ifup, KERN_DEBUG, np->dev, "Uninit RX channels\n");
5986         niu_stop_rx_channels(np);
5987         niu_reset_rx_channels(np);
5988
5989 out_uninit_tx_channels:
5990         netif_printk(np, ifup, KERN_DEBUG, np->dev, "Uninit TX channels\n");
5991         niu_stop_tx_channels(np);
5992         niu_reset_tx_channels(np);
5993
5994         return err;
5995 }
5996
5997 static void niu_stop_hw(struct niu *np)
5998 {
5999         netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Disable interrupts\n");
6000         niu_enable_interrupts(np, 0);
6001
6002         netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Disable RX MAC\n");
6003         niu_enable_rx_mac(np, 0);
6004
6005         netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Disable IPP\n");
6006         niu_disable_ipp(np);
6007
6008         netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Stop TX channels\n");
6009         niu_stop_tx_channels(np);
6010
6011         netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Stop RX channels\n");
6012         niu_stop_rx_channels(np);
6013
6014         netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Reset TX channels\n");
6015         niu_reset_tx_channels(np);
6016
6017         netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Reset RX channels\n");
6018         niu_reset_rx_channels(np);
6019 }
6020
6021 static void niu_set_irq_name(struct niu *np)
6022 {
6023         int port = np->port;
6024         int i, j = 1;
6025
6026         sprintf(np->irq_name[0], "%s:MAC", np->dev->name);
6027
6028         if (port == 0) {
6029                 sprintf(np->irq_name[1], "%s:MIF", np->dev->name);
6030                 sprintf(np->irq_name[2], "%s:SYSERR", np->dev->name);
6031                 j = 3;
6032         }
6033
6034         for (i = 0; i < np->num_ldg - j; i++) {
6035                 if (i < np->num_rx_rings)
6036                         sprintf(np->irq_name[i+j], "%s-rx-%d",
6037                                 np->dev->name, i);
6038                 else if (i < np->num_tx_rings + np->num_rx_rings)
6039                         sprintf(np->irq_name[i+j], "%s-tx-%d", np->dev->name,
6040                                 i - np->num_rx_rings);
6041         }
6042 }
6043
6044 static int niu_request_irq(struct niu *np)
6045 {
6046         int i, j, err;
6047
6048         niu_set_irq_name(np);
6049
6050         err = 0;
6051         for (i = 0; i < np->num_ldg; i++) {
6052                 struct niu_ldg *lp = &np->ldg[i];
6053
6054                 err = request_irq(lp->irq, niu_interrupt,
6055                                   IRQF_SHARED | IRQF_SAMPLE_RANDOM,
6056                                   np->irq_name[i], lp);
6057                 if (err)
6058                         goto out_free_irqs;
6059
6060         }
6061
6062         return 0;
6063
6064 out_free_irqs:
6065         for (j = 0; j < i; j++) {
6066                 struct niu_ldg *lp = &np->ldg[j];
6067
6068                 free_irq(lp->irq, lp);
6069         }
6070         return err;
6071 }
6072
6073 static void niu_free_irq(struct niu *np)
6074 {
6075         int i;
6076
6077         for (i = 0; i < np->num_ldg; i++) {
6078                 struct niu_ldg *lp = &np->ldg[i];
6079
6080                 free_irq(lp->irq, lp);
6081         }
6082 }
6083
6084 static void niu_enable_napi(struct niu *np)
6085 {
6086         int i;
6087
6088         for (i = 0; i < np->num_ldg; i++)
6089                 napi_enable(&np->ldg[i].napi);
6090 }
6091
6092 static void niu_disable_napi(struct niu *np)
6093 {
6094         int i;
6095
6096         for (i = 0; i < np->num_ldg; i++)
6097                 napi_disable(&np->ldg[i].napi);
6098 }
6099
6100 static int niu_open(struct net_device *dev)
6101 {
6102         struct niu *np = netdev_priv(dev);
6103         int err;
6104
6105         netif_carrier_off(dev);
6106
6107         err = niu_alloc_channels(np);
6108         if (err)
6109                 goto out_err;
6110
6111         err = niu_enable_interrupts(np, 0);
6112         if (err)
6113                 goto out_free_channels;
6114
6115         err = niu_request_irq(np);
6116         if (err)
6117                 goto out_free_channels;
6118
6119         niu_enable_napi(np);
6120
6121         spin_lock_irq(&np->lock);
6122
6123         err = niu_init_hw(np);
6124         if (!err) {
6125                 init_timer(&np->timer);
6126                 np->timer.expires = jiffies + HZ;
6127                 np->timer.data = (unsigned long) np;
6128                 np->timer.function = niu_timer;
6129
6130                 err = niu_enable_interrupts(np, 1);
6131                 if (err)
6132                         niu_stop_hw(np);
6133         }
6134
6135         spin_unlock_irq(&np->lock);
6136
6137         if (err) {
6138                 niu_disable_napi(np);
6139                 goto out_free_irq;
6140         }
6141
6142         netif_tx_start_all_queues(dev);
6143
6144         if (np->link_config.loopback_mode != LOOPBACK_DISABLED)
6145                 netif_carrier_on(dev);
6146
6147         add_timer(&np->timer);
6148
6149         return 0;
6150
6151 out_free_irq:
6152         niu_free_irq(np);
6153
6154 out_free_channels:
6155         niu_free_channels(np);
6156
6157 out_err:
6158         return err;
6159 }
6160
6161 static void niu_full_shutdown(struct niu *np, struct net_device *dev)
6162 {
6163         cancel_work_sync(&np->reset_task);
6164
6165         niu_disable_napi(np);
6166         netif_tx_stop_all_queues(dev);
6167
6168         del_timer_sync(&np->timer);
6169
6170         spin_lock_irq(&np->lock);
6171
6172         niu_stop_hw(np);
6173
6174         spin_unlock_irq(&np->lock);
6175 }
6176
6177 static int niu_close(struct net_device *dev)
6178 {
6179         struct niu *np = netdev_priv(dev);
6180
6181         niu_full_shutdown(np, dev);
6182
6183         niu_free_irq(np);
6184
6185         niu_free_channels(np);
6186
6187         niu_handle_led(np, 0);
6188
6189         return 0;
6190 }
6191
6192 static void niu_sync_xmac_stats(struct niu *np)
6193 {
6194         struct niu_xmac_stats *mp = &np->mac_stats.xmac;
6195
6196         mp->tx_frames += nr64_mac(TXMAC_FRM_CNT);
6197         mp->tx_bytes += nr64_mac(TXMAC_BYTE_CNT);
6198
6199         mp->rx_link_faults += nr64_mac(LINK_FAULT_CNT);
6200         mp->rx_align_errors += nr64_mac(RXMAC_ALIGN_ERR_CNT);
6201         mp->rx_frags += nr64_mac(RXMAC_FRAG_CNT);
6202         mp->rx_mcasts += nr64_mac(RXMAC_MC_FRM_CNT);
6203         mp->rx_bcasts += nr64_mac(RXMAC_BC_FRM_CNT);
6204         mp->rx_hist_cnt1 += nr64_mac(RXMAC_HIST_CNT1);
6205         mp->rx_hist_cnt2 += nr64_mac(RXMAC_HIST_CNT2);
6206         mp->rx_hist_cnt3 += nr64_mac(RXMAC_HIST_CNT3);
6207         mp->rx_hist_cnt4 += nr64_mac(RXMAC_HIST_CNT4);
6208         mp->rx_hist_cnt5 += nr64_mac(RXMAC_HIST_CNT5);
6209         mp->rx_hist_cnt6 += nr64_mac(RXMAC_HIST_CNT6);
6210         mp->rx_hist_cnt7 += nr64_mac(RXMAC_HIST_CNT7);
6211         mp->rx_octets += nr64_mac(RXMAC_BT_CNT);
6212         mp->rx_code_violations += nr64_mac(RXMAC_CD_VIO_CNT);
6213         mp->rx_len_errors += nr64_mac(RXMAC_MPSZER_CNT);
6214         mp->rx_crc_errors += nr64_mac(RXMAC_CRC_ER_CNT);
6215 }
6216
6217 static void niu_sync_bmac_stats(struct niu *np)
6218 {
6219         struct niu_bmac_stats *mp = &np->mac_stats.bmac;
6220
6221         mp->tx_bytes += nr64_mac(BTXMAC_BYTE_CNT);
6222         mp->tx_frames += nr64_mac(BTXMAC_FRM_CNT);
6223
6224         mp->rx_frames += nr64_mac(BRXMAC_FRAME_CNT);
6225         mp->rx_align_errors += nr64_mac(BRXMAC_ALIGN_ERR_CNT);
6226         mp->rx_crc_errors += nr64_mac(BRXMAC_ALIGN_ERR_CNT);
6227         mp->rx_len_errors += nr64_mac(BRXMAC_CODE_VIOL_ERR_CNT);
6228 }
6229
6230 static void niu_sync_mac_stats(struct niu *np)
6231 {
6232         if (np->flags & NIU_FLAGS_XMAC)
6233                 niu_sync_xmac_stats(np);
6234         else
6235                 niu_sync_bmac_stats(np);
6236 }
6237
6238 static void niu_get_rx_stats(struct niu *np)
6239 {
6240         unsigned long pkts, dropped, errors, bytes;
6241         int i;
6242
6243         pkts = dropped = errors = bytes = 0;
6244         for (i = 0; i < np->num_rx_rings; i++) {
6245                 struct rx_ring_info *rp = &np->rx_rings[i];
6246
6247                 niu_sync_rx_discard_stats(np, rp, 0);
6248
6249                 pkts += rp->rx_packets;
6250                 bytes += rp->rx_bytes;
6251                 dropped += rp->rx_dropped;
6252                 errors += rp->rx_errors;
6253         }
6254         np->dev->stats.rx_packets = pkts;
6255         np->dev->stats.rx_bytes = bytes;
6256         np->dev->stats.rx_dropped = dropped;
6257         np->dev->stats.rx_errors = errors;
6258 }
6259
6260 static void niu_get_tx_stats(struct niu *np)
6261 {
6262         unsigned long pkts, errors, bytes;
6263         int i;
6264
6265         pkts = errors = bytes = 0;
6266         for (i = 0; i < np->num_tx_rings; i++) {
6267                 struct tx_ring_info *rp = &np->tx_rings[i];
6268
6269                 pkts += rp->tx_packets;
6270                 bytes += rp->tx_bytes;
6271                 errors += rp->tx_errors;
6272         }
6273         np->dev->stats.tx_packets = pkts;
6274         np->dev->stats.tx_bytes = bytes;
6275         np->dev->stats.tx_errors = errors;
6276 }
6277
6278 static struct net_device_stats *niu_get_stats(struct net_device *dev)
6279 {
6280         struct niu *np = netdev_priv(dev);
6281
6282         niu_get_rx_stats(np);
6283         niu_get_tx_stats(np);
6284
6285         return &dev->stats;
6286 }
6287
6288 static void niu_load_hash_xmac(struct niu *np, u16 *hash)
6289 {
6290         int i;
6291
6292         for (i = 0; i < 16; i++)
6293                 nw64_mac(XMAC_HASH_TBL(i), hash[i]);
6294 }
6295
6296 static void niu_load_hash_bmac(struct niu *np, u16 *hash)
6297 {
6298         int i;
6299
6300         for (i = 0; i < 16; i++)
6301                 nw64_mac(BMAC_HASH_TBL(i), hash[i]);
6302 }
6303
6304 static void niu_load_hash(struct niu *np, u16 *hash)
6305 {
6306         if (np->flags & NIU_FLAGS_XMAC)
6307                 niu_load_hash_xmac(np, hash);
6308         else
6309                 niu_load_hash_bmac(np, hash);
6310 }
6311
6312 static void niu_set_rx_mode(struct net_device *dev)
6313 {
6314         struct niu *np = netdev_priv(dev);
6315         int i, alt_cnt, err;
6316         struct dev_addr_list *addr;
6317         struct netdev_hw_addr *ha;
6318         unsigned long flags;
6319         u16 hash[16] = { 0, };
6320
6321         spin_lock_irqsave(&np->lock, flags);
6322         niu_enable_rx_mac(np, 0);
6323
6324         np->flags &= ~(NIU_FLAGS_MCAST | NIU_FLAGS_PROMISC);
6325         if (dev->flags & IFF_PROMISC)
6326                 np->flags |= NIU_FLAGS_PROMISC;
6327         if ((dev->flags & IFF_ALLMULTI) || (!netdev_mc_empty(dev)))
6328                 np->flags |= NIU_FLAGS_MCAST;
6329
6330         alt_cnt = netdev_uc_count(dev);
6331         if (alt_cnt > niu_num_alt_addr(np)) {
6332                 alt_cnt = 0;
6333                 np->flags |= NIU_FLAGS_PROMISC;
6334         }
6335
6336         if (alt_cnt) {
6337                 int index = 0;
6338
6339                 netdev_for_each_uc_addr(ha, dev) {
6340                         err = niu_set_alt_mac(np, index, ha->addr);
6341                         if (err)
6342                                 netdev_warn(dev, "Error %d adding alt mac %d\n",
6343                                             err, index);
6344                         err = niu_enable_alt_mac(np, index, 1);
6345                         if (err)
6346                                 netdev_warn(dev, "Error %d enabling alt mac %d\n",
6347                                             err, index);
6348
6349                         index++;
6350                 }
6351         } else {
6352                 int alt_start;
6353                 if (np->flags & NIU_FLAGS_XMAC)
6354                         alt_start = 0;
6355                 else
6356                         alt_start = 1;
6357                 for (i = alt_start; i < niu_num_alt_addr(np); i++) {
6358                         err = niu_enable_alt_mac(np, i, 0);
6359                         if (err)
6360                                 netdev_warn(dev, "Error %d disabling alt mac %d\n",
6361                                             err, i);
6362                 }
6363         }
6364         if (dev->flags & IFF_ALLMULTI) {
6365                 for (i = 0; i < 16; i++)
6366                         hash[i] = 0xffff;
6367         } else if (!netdev_mc_empty(dev)) {
6368                 for (addr = dev->mc_list; addr; addr = addr->next) {
6369                         u32 crc = ether_crc_le(ETH_ALEN, addr->da_addr);
6370
6371                         crc >>= 24;
6372                         hash[crc >> 4] |= (1 << (15 - (crc & 0xf)));
6373                 }
6374         }
6375
6376         if (np->flags & NIU_FLAGS_MCAST)
6377                 niu_load_hash(np, hash);
6378
6379         niu_enable_rx_mac(np, 1);
6380         spin_unlock_irqrestore(&np->lock, flags);
6381 }
6382
6383 static int niu_set_mac_addr(struct net_device *dev, void *p)
6384 {
6385         struct niu *np = netdev_priv(dev);
6386         struct sockaddr *addr = p;
6387         unsigned long flags;
6388
6389         if (!is_valid_ether_addr(addr->sa_data))
6390                 return -EINVAL;
6391
6392         memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
6393
6394         if (!netif_running(dev))
6395                 return 0;
6396
6397         spin_lock_irqsave(&np->lock, flags);
6398         niu_enable_rx_mac(np, 0);
6399         niu_set_primary_mac(np, dev->dev_addr);
6400         niu_enable_rx_mac(np, 1);
6401         spin_unlock_irqrestore(&np->lock, flags);
6402
6403         return 0;
6404 }
6405
6406 static int niu_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
6407 {
6408         return -EOPNOTSUPP;
6409 }
6410
6411 static void niu_netif_stop(struct niu *np)
6412 {
6413         np->dev->trans_start = jiffies; /* prevent tx timeout */
6414
6415         niu_disable_napi(np);
6416
6417         netif_tx_disable(np->dev);
6418 }
6419
6420 static void niu_netif_start(struct niu *np)
6421 {
6422         /* NOTE: unconditional netif_wake_queue is only appropriate
6423          * so long as all callers are assured to have free tx slots
6424          * (such as after niu_init_hw).
6425          */
6426         netif_tx_wake_all_queues(np->dev);
6427
6428         niu_enable_napi(np);
6429
6430         niu_enable_interrupts(np, 1);
6431 }
6432
6433 static void niu_reset_buffers(struct niu *np)
6434 {
6435         int i, j, k, err;
6436
6437         if (np->rx_rings) {
6438                 for (i = 0; i < np->num_rx_rings; i++) {
6439                         struct rx_ring_info *rp = &np->rx_rings[i];
6440
6441                         for (j = 0, k = 0; j < MAX_RBR_RING_SIZE; j++) {
6442                                 struct page *page;
6443
6444                                 page = rp->rxhash[j];
6445                                 while (page) {
6446                                         struct page *next =
6447                                                 (struct page *) page->mapping;
6448                                         u64 base = page->index;
6449                                         base = base >> RBR_DESCR_ADDR_SHIFT;
6450                                         rp->rbr[k++] = cpu_to_le32(base);
6451                                         page = next;
6452                                 }
6453                         }
6454                         for (; k < MAX_RBR_RING_SIZE; k++) {
6455                                 err = niu_rbr_add_page(np, rp, GFP_ATOMIC, k);
6456                                 if (unlikely(err))
6457                                         break;
6458                         }
6459
6460                         rp->rbr_index = rp->rbr_table_size - 1;
6461                         rp->rcr_index = 0;
6462                         rp->rbr_pending = 0;
6463                         rp->rbr_refill_pending = 0;
6464                 }
6465         }
6466         if (np->tx_rings) {
6467                 for (i = 0; i < np->num_tx_rings; i++) {
6468                         struct tx_ring_info *rp = &np->tx_rings[i];
6469
6470                         for (j = 0; j < MAX_TX_RING_SIZE; j++) {
6471                                 if (rp->tx_buffs[j].skb)
6472                                         (void) release_tx_packet(np, rp, j);
6473                         }
6474
6475                         rp->pending = MAX_TX_RING_SIZE;
6476                         rp->prod = 0;
6477                         rp->cons = 0;
6478                         rp->wrap_bit = 0;
6479                 }
6480         }
6481 }
6482
6483 static void niu_reset_task(struct work_struct *work)
6484 {
6485         struct niu *np = container_of(work, struct niu, reset_task);
6486         unsigned long flags;
6487         int err;
6488
6489         spin_lock_irqsave(&np->lock, flags);
6490         if (!netif_running(np->dev)) {
6491                 spin_unlock_irqrestore(&np->lock, flags);
6492                 return;
6493         }
6494
6495         spin_unlock_irqrestore(&np->lock, flags);
6496
6497         del_timer_sync(&np->timer);
6498
6499         niu_netif_stop(np);
6500
6501         spin_lock_irqsave(&np->lock, flags);
6502
6503         niu_stop_hw(np);
6504
6505         spin_unlock_irqrestore(&np->lock, flags);
6506
6507         niu_reset_buffers(np);
6508
6509         spin_lock_irqsave(&np->lock, flags);
6510
6511         err = niu_init_hw(np);
6512         if (!err) {
6513                 np->timer.expires = jiffies + HZ;
6514                 add_timer(&np->timer);
6515                 niu_netif_start(np);
6516         }
6517
6518         spin_unlock_irqrestore(&np->lock, flags);
6519 }
6520
6521 static void niu_tx_timeout(struct net_device *dev)
6522 {
6523         struct niu *np = netdev_priv(dev);
6524
6525         dev_err(np->device, "%s: Transmit timed out, resetting\n",
6526                 dev->name);
6527
6528         schedule_work(&np->reset_task);
6529 }
6530
6531 static void niu_set_txd(struct tx_ring_info *rp, int index,
6532                         u64 mapping, u64 len, u64 mark,
6533                         u64 n_frags)
6534 {
6535         __le64 *desc = &rp->descr[index];
6536
6537         *desc = cpu_to_le64(mark |
6538                             (n_frags << TX_DESC_NUM_PTR_SHIFT) |
6539                             (len << TX_DESC_TR_LEN_SHIFT) |
6540                             (mapping & TX_DESC_SAD));
6541 }
6542
6543 static u64 niu_compute_tx_flags(struct sk_buff *skb, struct ethhdr *ehdr,
6544                                 u64 pad_bytes, u64 len)
6545 {
6546         u16 eth_proto, eth_proto_inner;
6547         u64 csum_bits, l3off, ihl, ret;
6548         u8 ip_proto;
6549         int ipv6;
6550
6551         eth_proto = be16_to_cpu(ehdr->h_proto);
6552         eth_proto_inner = eth_proto;
6553         if (eth_proto == ETH_P_8021Q) {
6554                 struct vlan_ethhdr *vp = (struct vlan_ethhdr *) ehdr;
6555                 __be16 val = vp->h_vlan_encapsulated_proto;
6556
6557                 eth_proto_inner = be16_to_cpu(val);
6558         }
6559
6560         ipv6 = ihl = 0;
6561         switch (skb->protocol) {
6562         case cpu_to_be16(ETH_P_IP):
6563                 ip_proto = ip_hdr(skb)->protocol;
6564                 ihl = ip_hdr(skb)->ihl;
6565                 break;
6566         case cpu_to_be16(ETH_P_IPV6):
6567                 ip_proto = ipv6_hdr(skb)->nexthdr;
6568                 ihl = (40 >> 2);
6569                 ipv6 = 1;
6570                 break;
6571         default:
6572                 ip_proto = ihl = 0;
6573                 break;
6574         }
6575
6576         csum_bits = TXHDR_CSUM_NONE;
6577         if (skb->ip_summed == CHECKSUM_PARTIAL) {
6578                 u64 start, stuff;
6579
6580                 csum_bits = (ip_proto == IPPROTO_TCP ?
6581                              TXHDR_CSUM_TCP :
6582                              (ip_proto == IPPROTO_UDP ?
6583                               TXHDR_CSUM_UDP : TXHDR_CSUM_SCTP));
6584
6585                 start = skb_transport_offset(skb) -
6586                         (pad_bytes + sizeof(struct tx_pkt_hdr));
6587                 stuff = start + skb->csum_offset;
6588
6589                 csum_bits |= (start / 2) << TXHDR_L4START_SHIFT;
6590                 csum_bits |= (stuff / 2) << TXHDR_L4STUFF_SHIFT;
6591         }
6592
6593         l3off = skb_network_offset(skb) -
6594                 (pad_bytes + sizeof(struct tx_pkt_hdr));
6595
6596         ret = (((pad_bytes / 2) << TXHDR_PAD_SHIFT) |
6597                (len << TXHDR_LEN_SHIFT) |
6598                ((l3off / 2) << TXHDR_L3START_SHIFT) |
6599                (ihl << TXHDR_IHL_SHIFT) |
6600                ((eth_proto_inner < 1536) ? TXHDR_LLC : 0) |
6601                ((eth_proto == ETH_P_8021Q) ? TXHDR_VLAN : 0) |
6602                (ipv6 ? TXHDR_IP_VER : 0) |
6603                csum_bits);
6604
6605         return ret;
6606 }
6607
6608 static netdev_tx_t niu_start_xmit(struct sk_buff *skb,
6609                                   struct net_device *dev)
6610 {
6611         struct niu *np = netdev_priv(dev);
6612         unsigned long align, headroom;
6613         struct netdev_queue *txq;
6614         struct tx_ring_info *rp;
6615         struct tx_pkt_hdr *tp;
6616         unsigned int len, nfg;
6617         struct ethhdr *ehdr;
6618         int prod, i, tlen;
6619         u64 mapping, mrk;
6620
6621         i = skb_get_queue_mapping(skb);
6622         rp = &np->tx_rings[i];
6623         txq = netdev_get_tx_queue(dev, i);
6624
6625         if (niu_tx_avail(rp) <= (skb_shinfo(skb)->nr_frags + 1)) {
6626                 netif_tx_stop_queue(txq);
6627                 dev_err(np->device, "%s: BUG! Tx ring full when queue awake!\n", dev->name);
6628                 rp->tx_errors++;
6629                 return NETDEV_TX_BUSY;
6630         }
6631
6632         if (skb->len < ETH_ZLEN) {
6633                 unsigned int pad_bytes = ETH_ZLEN - skb->len;
6634
6635                 if (skb_pad(skb, pad_bytes))
6636                         goto out;
6637                 skb_put(skb, pad_bytes);
6638         }
6639
6640         len = sizeof(struct tx_pkt_hdr) + 15;
6641         if (skb_headroom(skb) < len) {
6642                 struct sk_buff *skb_new;
6643
6644                 skb_new = skb_realloc_headroom(skb, len);
6645                 if (!skb_new) {
6646                         rp->tx_errors++;
6647                         goto out_drop;
6648                 }
6649                 kfree_skb(skb);
6650                 skb = skb_new;
6651         } else
6652                 skb_orphan(skb);
6653
6654         align = ((unsigned long) skb->data & (16 - 1));
6655         headroom = align + sizeof(struct tx_pkt_hdr);
6656
6657         ehdr = (struct ethhdr *) skb->data;
6658         tp = (struct tx_pkt_hdr *) skb_push(skb, headroom);
6659
6660         len = skb->len - sizeof(struct tx_pkt_hdr);
6661         tp->flags = cpu_to_le64(niu_compute_tx_flags(skb, ehdr, align, len));
6662         tp->resv = 0;
6663
6664         len = skb_headlen(skb);
6665         mapping = np->ops->map_single(np->device, skb->data,
6666                                       len, DMA_TO_DEVICE);
6667
6668         prod = rp->prod;
6669
6670         rp->tx_buffs[prod].skb = skb;
6671         rp->tx_buffs[prod].mapping = mapping;
6672
6673         mrk = TX_DESC_SOP;
6674         if (++rp->mark_counter == rp->mark_freq) {
6675                 rp->mark_counter = 0;
6676                 mrk |= TX_DESC_MARK;
6677                 rp->mark_pending++;
6678         }
6679
6680         tlen = len;
6681         nfg = skb_shinfo(skb)->nr_frags;
6682         while (tlen > 0) {
6683                 tlen -= MAX_TX_DESC_LEN;
6684                 nfg++;
6685         }
6686
6687         while (len > 0) {
6688                 unsigned int this_len = len;
6689
6690                 if (this_len > MAX_TX_DESC_LEN)
6691                         this_len = MAX_TX_DESC_LEN;
6692
6693                 niu_set_txd(rp, prod, mapping, this_len, mrk, nfg);
6694                 mrk = nfg = 0;
6695
6696                 prod = NEXT_TX(rp, prod);
6697                 mapping += this_len;
6698                 len -= this_len;
6699         }
6700
6701         for (i = 0; i <  skb_shinfo(skb)->nr_frags; i++) {
6702                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6703
6704                 len = frag->size;
6705                 mapping = np->ops->map_page(np->device, frag->page,
6706                                             frag->page_offset, len,
6707                                             DMA_TO_DEVICE);
6708
6709                 rp->tx_buffs[prod].skb = NULL;
6710                 rp->tx_buffs[prod].mapping = mapping;
6711
6712                 niu_set_txd(rp, prod, mapping, len, 0, 0);
6713
6714                 prod = NEXT_TX(rp, prod);
6715         }
6716
6717         if (prod < rp->prod)
6718                 rp->wrap_bit ^= TX_RING_KICK_WRAP;
6719         rp->prod = prod;
6720
6721         nw64(TX_RING_KICK(rp->tx_channel), rp->wrap_bit | (prod << 3));
6722
6723         if (unlikely(niu_tx_avail(rp) <= (MAX_SKB_FRAGS + 1))) {
6724                 netif_tx_stop_queue(txq);
6725                 if (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp))
6726                         netif_tx_wake_queue(txq);
6727         }
6728
6729 out:
6730         return NETDEV_TX_OK;
6731
6732 out_drop:
6733         rp->tx_errors++;
6734         kfree_skb(skb);
6735         goto out;
6736 }
6737
6738 static int niu_change_mtu(struct net_device *dev, int new_mtu)
6739 {
6740         struct niu *np = netdev_priv(dev);
6741         int err, orig_jumbo, new_jumbo;
6742
6743         if (new_mtu < 68 || new_mtu > NIU_MAX_MTU)
6744                 return -EINVAL;
6745
6746         orig_jumbo = (dev->mtu > ETH_DATA_LEN);
6747         new_jumbo = (new_mtu > ETH_DATA_LEN);
6748
6749         dev->mtu = new_mtu;
6750
6751         if (!netif_running(dev) ||
6752             (orig_jumbo == new_jumbo))
6753                 return 0;
6754
6755         niu_full_shutdown(np, dev);
6756
6757         niu_free_channels(np);
6758
6759         niu_enable_napi(np);
6760
6761         err = niu_alloc_channels(np);
6762         if (err)
6763                 return err;
6764
6765         spin_lock_irq(&np->lock);
6766
6767         err = niu_init_hw(np);
6768         if (!err) {
6769                 init_timer(&np->timer);
6770                 np->timer.expires = jiffies + HZ;
6771                 np->timer.data = (unsigned long) np;
6772                 np->timer.function = niu_timer;
6773
6774                 err = niu_enable_interrupts(np, 1);
6775                 if (err)
6776                         niu_stop_hw(np);
6777         }
6778
6779         spin_unlock_irq(&np->lock);
6780
6781         if (!err) {
6782                 netif_tx_start_all_queues(dev);
6783                 if (np->link_config.loopback_mode != LOOPBACK_DISABLED)
6784                         netif_carrier_on(dev);
6785
6786                 add_timer(&np->timer);
6787         }
6788
6789         return err;
6790 }
6791
6792 static void niu_get_drvinfo(struct net_device *dev,
6793                             struct ethtool_drvinfo *info)
6794 {
6795         struct niu *np = netdev_priv(dev);
6796         struct niu_vpd *vpd = &np->vpd;
6797
6798         strcpy(info->driver, DRV_MODULE_NAME);
6799         strcpy(info->version, DRV_MODULE_VERSION);
6800         sprintf(info->fw_version, "%d.%d",
6801                 vpd->fcode_major, vpd->fcode_minor);
6802         if (np->parent->plat_type != PLAT_TYPE_NIU)
6803                 strcpy(info->bus_info, pci_name(np->pdev));
6804 }
6805
6806 static int niu_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6807 {
6808         struct niu *np = netdev_priv(dev);
6809         struct niu_link_config *lp;
6810
6811         lp = &np->link_config;
6812
6813         memset(cmd, 0, sizeof(*cmd));
6814         cmd->phy_address = np->phy_addr;
6815         cmd->supported = lp->supported;
6816         cmd->advertising = lp->active_advertising;
6817         cmd->autoneg = lp->active_autoneg;
6818         cmd->speed = lp->active_speed;
6819         cmd->duplex = lp->active_duplex;
6820         cmd->port = (np->flags & NIU_FLAGS_FIBER) ? PORT_FIBRE : PORT_TP;
6821         cmd->transceiver = (np->flags & NIU_FLAGS_XCVR_SERDES) ?
6822                 XCVR_EXTERNAL : XCVR_INTERNAL;
6823
6824         return 0;
6825 }
6826
6827 static int niu_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6828 {
6829         struct niu *np = netdev_priv(dev);
6830         struct niu_link_config *lp = &np->link_config;
6831
6832         lp->advertising = cmd->advertising;
6833         lp->speed = cmd->speed;
6834         lp->duplex = cmd->duplex;
6835         lp->autoneg = cmd->autoneg;
6836         return niu_init_link(np);
6837 }
6838
6839 static u32 niu_get_msglevel(struct net_device *dev)
6840 {
6841         struct niu *np = netdev_priv(dev);
6842         return np->msg_enable;
6843 }
6844
6845 static void niu_set_msglevel(struct net_device *dev, u32 value)
6846 {
6847         struct niu *np = netdev_priv(dev);
6848         np->msg_enable = value;
6849 }
6850
6851 static int niu_nway_reset(struct net_device *dev)
6852 {
6853         struct niu *np = netdev_priv(dev);
6854
6855         if (np->link_config.autoneg)
6856                 return niu_init_link(np);
6857
6858         return 0;
6859 }
6860
6861 static int niu_get_eeprom_len(struct net_device *dev)
6862 {
6863         struct niu *np = netdev_priv(dev);
6864
6865         return np->eeprom_len;
6866 }
6867
6868 static int niu_get_eeprom(struct net_device *dev,
6869                           struct ethtool_eeprom *eeprom, u8 *data)
6870 {
6871         struct niu *np = netdev_priv(dev);
6872         u32 offset, len, val;
6873
6874         offset = eeprom->offset;
6875         len = eeprom->len;
6876
6877         if (offset + len < offset)
6878                 return -EINVAL;
6879         if (offset >= np->eeprom_len)
6880                 return -EINVAL;
6881         if (offset + len > np->eeprom_len)
6882                 len = eeprom->len = np->eeprom_len - offset;
6883
6884         if (offset & 3) {
6885                 u32 b_offset, b_count;
6886
6887                 b_offset = offset & 3;
6888                 b_count = 4 - b_offset;
6889                 if (b_count > len)
6890                         b_count = len;
6891
6892                 val = nr64(ESPC_NCR((offset - b_offset) / 4));
6893                 memcpy(data, ((char *)&val) + b_offset, b_count);
6894                 data += b_count;
6895                 len -= b_count;
6896                 offset += b_count;
6897         }
6898         while (len >= 4) {
6899                 val = nr64(ESPC_NCR(offset / 4));
6900                 memcpy(data, &val, 4);
6901                 data += 4;
6902                 len -= 4;
6903                 offset += 4;
6904         }
6905         if (len) {
6906                 val = nr64(ESPC_NCR(offset / 4));
6907                 memcpy(data, &val, len);
6908         }
6909         return 0;
6910 }
6911
6912 static void niu_ethflow_to_l3proto(int flow_type, u8 *pid)
6913 {
6914         switch (flow_type) {
6915         case TCP_V4_FLOW:
6916         case TCP_V6_FLOW:
6917                 *pid = IPPROTO_TCP;
6918                 break;
6919         case UDP_V4_FLOW:
6920         case UDP_V6_FLOW:
6921                 *pid = IPPROTO_UDP;
6922                 break;
6923         case SCTP_V4_FLOW:
6924         case SCTP_V6_FLOW:
6925                 *pid = IPPROTO_SCTP;
6926                 break;
6927         case AH_V4_FLOW:
6928         case AH_V6_FLOW:
6929                 *pid = IPPROTO_AH;
6930                 break;
6931         case ESP_V4_FLOW:
6932         case ESP_V6_FLOW:
6933                 *pid = IPPROTO_ESP;
6934                 break;
6935         default:
6936                 *pid = 0;
6937                 break;
6938         }
6939 }
6940
6941 static int niu_class_to_ethflow(u64 class, int *flow_type)
6942 {
6943         switch (class) {
6944         case CLASS_CODE_TCP_IPV4:
6945                 *flow_type = TCP_V4_FLOW;
6946                 break;
6947         case CLASS_CODE_UDP_IPV4:
6948                 *flow_type = UDP_V4_FLOW;
6949                 break;
6950         case CLASS_CODE_AH_ESP_IPV4:
6951                 *flow_type = AH_V4_FLOW;
6952                 break;
6953         case CLASS_CODE_SCTP_IPV4:
6954                 *flow_type = SCTP_V4_FLOW;
6955                 break;
6956         case CLASS_CODE_TCP_IPV6:
6957                 *flow_type = TCP_V6_FLOW;
6958                 break;
6959         case CLASS_CODE_UDP_IPV6:
6960                 *flow_type = UDP_V6_FLOW;
6961                 break;
6962         case CLASS_CODE_AH_ESP_IPV6:
6963                 *flow_type = AH_V6_FLOW;
6964                 break;
6965         case CLASS_CODE_SCTP_IPV6:
6966                 *flow_type = SCTP_V6_FLOW;
6967                 break;
6968         case CLASS_CODE_USER_PROG1:
6969         case CLASS_CODE_USER_PROG2:
6970         case CLASS_CODE_USER_PROG3:
6971         case CLASS_CODE_USER_PROG4:
6972                 *flow_type = IP_USER_FLOW;
6973                 break;
6974         default:
6975                 return 0;
6976         }
6977
6978         return 1;
6979 }
6980
6981 static int niu_ethflow_to_class(int flow_type, u64 *class)
6982 {
6983         switch (flow_type) {
6984         case TCP_V4_FLOW:
6985                 *class = CLASS_CODE_TCP_IPV4;
6986                 break;
6987         case UDP_V4_FLOW:
6988                 *class = CLASS_CODE_UDP_IPV4;
6989                 break;
6990         case AH_V4_FLOW:
6991         case ESP_V4_FLOW:
6992                 *class = CLASS_CODE_AH_ESP_IPV4;
6993                 break;
6994         case SCTP_V4_FLOW:
6995                 *class = CLASS_CODE_SCTP_IPV4;
6996                 break;
6997         case TCP_V6_FLOW:
6998                 *class = CLASS_CODE_TCP_IPV6;
6999                 break;
7000         case UDP_V6_FLOW:
7001                 *class = CLASS_CODE_UDP_IPV6;
7002                 break;
7003         case AH_V6_FLOW:
7004         case ESP_V6_FLOW:
7005                 *class = CLASS_CODE_AH_ESP_IPV6;
7006                 break;
7007         case SCTP_V6_FLOW:
7008                 *class = CLASS_CODE_SCTP_IPV6;
7009                 break;
7010         default:
7011                 return 0;
7012         }
7013
7014         return 1;
7015 }
7016
7017 static u64 niu_flowkey_to_ethflow(u64 flow_key)
7018 {
7019         u64 ethflow = 0;
7020
7021         if (flow_key & FLOW_KEY_L2DA)
7022                 ethflow |= RXH_L2DA;
7023         if (flow_key & FLOW_KEY_VLAN)
7024                 ethflow |= RXH_VLAN;
7025         if (flow_key & FLOW_KEY_IPSA)
7026                 ethflow |= RXH_IP_SRC;
7027         if (flow_key & FLOW_KEY_IPDA)
7028                 ethflow |= RXH_IP_DST;
7029         if (flow_key & FLOW_KEY_PROTO)
7030                 ethflow |= RXH_L3_PROTO;
7031         if (flow_key & (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_0_SHIFT))
7032                 ethflow |= RXH_L4_B_0_1;
7033         if (flow_key & (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_1_SHIFT))
7034                 ethflow |= RXH_L4_B_2_3;
7035
7036         return ethflow;
7037
7038 }
7039
7040 static int niu_ethflow_to_flowkey(u64 ethflow, u64 *flow_key)
7041 {
7042         u64 key = 0;
7043
7044         if (ethflow & RXH_L2DA)
7045                 key |= FLOW_KEY_L2DA;
7046         if (ethflow & RXH_VLAN)
7047                 key |= FLOW_KEY_VLAN;
7048         if (ethflow & RXH_IP_SRC)
7049                 key |= FLOW_KEY_IPSA;
7050         if (ethflow & RXH_IP_DST)
7051                 key |= FLOW_KEY_IPDA;
7052         if (ethflow & RXH_L3_PROTO)
7053                 key |= FLOW_KEY_PROTO;
7054         if (ethflow & RXH_L4_B_0_1)
7055                 key |= (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_0_SHIFT);
7056         if (ethflow & RXH_L4_B_2_3)
7057                 key |= (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_1_SHIFT);
7058
7059         *flow_key = key;
7060
7061         return 1;
7062
7063 }
7064
7065 static int niu_get_hash_opts(struct niu *np, struct ethtool_rxnfc *nfc)
7066 {
7067         u64 class;
7068
7069         nfc->data = 0;
7070
7071         if (!niu_ethflow_to_class(nfc->flow_type, &class))
7072                 return -EINVAL;
7073
7074         if (np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] &
7075             TCAM_KEY_DISC)
7076                 nfc->data = RXH_DISCARD;
7077         else
7078                 nfc->data = niu_flowkey_to_ethflow(np->parent->flow_key[class -
7079                                                       CLASS_CODE_USER_PROG1]);
7080         return 0;
7081 }
7082
7083 static void niu_get_ip4fs_from_tcam_key(struct niu_tcam_entry *tp,
7084                                         struct ethtool_rx_flow_spec *fsp)
7085 {
7086
7087         fsp->h_u.tcp_ip4_spec.ip4src = (tp->key[3] & TCAM_V4KEY3_SADDR) >>
7088                 TCAM_V4KEY3_SADDR_SHIFT;
7089         fsp->h_u.tcp_ip4_spec.ip4dst = (tp->key[3] & TCAM_V4KEY3_DADDR) >>
7090                 TCAM_V4KEY3_DADDR_SHIFT;
7091         fsp->m_u.tcp_ip4_spec.ip4src = (tp->key_mask[3] & TCAM_V4KEY3_SADDR) >>
7092                 TCAM_V4KEY3_SADDR_SHIFT;
7093         fsp->m_u.tcp_ip4_spec.ip4dst = (tp->key_mask[3] & TCAM_V4KEY3_DADDR) >>
7094                 TCAM_V4KEY3_DADDR_SHIFT;
7095
7096         fsp->h_u.tcp_ip4_spec.ip4src =
7097                 cpu_to_be32(fsp->h_u.tcp_ip4_spec.ip4src);
7098         fsp->m_u.tcp_ip4_spec.ip4src =
7099                 cpu_to_be32(fsp->m_u.tcp_ip4_spec.ip4src);
7100         fsp->h_u.tcp_ip4_spec.ip4dst =
7101                 cpu_to_be32(fsp->h_u.tcp_ip4_spec.ip4dst);
7102         fsp->m_u.tcp_ip4_spec.ip4dst =
7103                 cpu_to_be32(fsp->m_u.tcp_ip4_spec.ip4dst);
7104
7105         fsp->h_u.tcp_ip4_spec.tos = (tp->key[2] & TCAM_V4KEY2_TOS) >>
7106                 TCAM_V4KEY2_TOS_SHIFT;
7107         fsp->m_u.tcp_ip4_spec.tos = (tp->key_mask[2] & TCAM_V4KEY2_TOS) >>
7108                 TCAM_V4KEY2_TOS_SHIFT;
7109
7110         switch (fsp->flow_type) {
7111         case TCP_V4_FLOW:
7112         case UDP_V4_FLOW:
7113         case SCTP_V4_FLOW:
7114                 fsp->h_u.tcp_ip4_spec.psrc =
7115                         ((tp->key[2] & TCAM_V4KEY2_PORT_SPI) >>
7116                          TCAM_V4KEY2_PORT_SPI_SHIFT) >> 16;
7117                 fsp->h_u.tcp_ip4_spec.pdst =
7118                         ((tp->key[2] & TCAM_V4KEY2_PORT_SPI) >>
7119                          TCAM_V4KEY2_PORT_SPI_SHIFT) & 0xffff;
7120                 fsp->m_u.tcp_ip4_spec.psrc =
7121                         ((tp->key_mask[2] & TCAM_V4KEY2_PORT_SPI) >>
7122                          TCAM_V4KEY2_PORT_SPI_SHIFT) >> 16;
7123                 fsp->m_u.tcp_ip4_spec.pdst =
7124                         ((tp->key_mask[2] & TCAM_V4KEY2_PORT_SPI) >>
7125                          TCAM_V4KEY2_PORT_SPI_SHIFT) & 0xffff;
7126
7127                 fsp->h_u.tcp_ip4_spec.psrc =
7128                         cpu_to_be16(fsp->h_u.tcp_ip4_spec.psrc);
7129                 fsp->h_u.tcp_ip4_spec.pdst =
7130                         cpu_to_be16(fsp->h_u.tcp_ip4_spec.pdst);
7131                 fsp->m_u.tcp_ip4_spec.psrc =
7132                         cpu_to_be16(fsp->m_u.tcp_ip4_spec.psrc);
7133                 fsp->m_u.tcp_ip4_spec.pdst =
7134                         cpu_to_be16(fsp->m_u.tcp_ip4_spec.pdst);
7135                 break;
7136         case AH_V4_FLOW:
7137         case ESP_V4_FLOW:
7138                 fsp->h_u.ah_ip4_spec.spi =
7139                         (tp->key[2] & TCAM_V4KEY2_PORT_SPI) >>
7140                         TCAM_V4KEY2_PORT_SPI_SHIFT;
7141                 fsp->m_u.ah_ip4_spec.spi =
7142                         (tp->key_mask[2] & TCAM_V4KEY2_PORT_SPI) >>
7143                         TCAM_V4KEY2_PORT_SPI_SHIFT;
7144
7145                 fsp->h_u.ah_ip4_spec.spi =
7146                         cpu_to_be32(fsp->h_u.ah_ip4_spec.spi);
7147                 fsp->m_u.ah_ip4_spec.spi =
7148                         cpu_to_be32(fsp->m_u.ah_ip4_spec.spi);
7149                 break;
7150         case IP_USER_FLOW:
7151                 fsp->h_u.usr_ip4_spec.l4_4_bytes =
7152                         (tp->key[2] & TCAM_V4KEY2_PORT_SPI) >>
7153                         TCAM_V4KEY2_PORT_SPI_SHIFT;
7154                 fsp->m_u.usr_ip4_spec.l4_4_bytes =
7155                         (tp->key_mask[2] & TCAM_V4KEY2_PORT_SPI) >>
7156                         TCAM_V4KEY2_PORT_SPI_SHIFT;
7157
7158                 fsp->h_u.usr_ip4_spec.l4_4_bytes =
7159                         cpu_to_be32(fsp->h_u.usr_ip4_spec.l4_4_bytes);
7160                 fsp->m_u.usr_ip4_spec.l4_4_bytes =
7161                         cpu_to_be32(fsp->m_u.usr_ip4_spec.l4_4_bytes);
7162
7163                 fsp->h_u.usr_ip4_spec.proto =
7164                         (tp->key[2] & TCAM_V4KEY2_PROTO) >>
7165                         TCAM_V4KEY2_PROTO_SHIFT;
7166                 fsp->m_u.usr_ip4_spec.proto =
7167                         (tp->key_mask[2] & TCAM_V4KEY2_PROTO) >>
7168                         TCAM_V4KEY2_PROTO_SHIFT;
7169
7170                 fsp->h_u.usr_ip4_spec.ip_ver = ETH_RX_NFC_IP4;
7171                 break;
7172         default:
7173                 break;
7174         }
7175 }
7176
7177 static int niu_get_ethtool_tcam_entry(struct niu *np,
7178                                       struct ethtool_rxnfc *nfc)
7179 {
7180         struct niu_parent *parent = np->parent;
7181         struct niu_tcam_entry *tp;
7182         struct ethtool_rx_flow_spec *fsp = &nfc->fs;
7183         u16 idx;
7184         u64 class;
7185         int ret = 0;
7186
7187         idx = tcam_get_index(np, (u16)nfc->fs.location);
7188
7189         tp = &parent->tcam[idx];
7190         if (!tp->valid) {
7191                 netdev_info(np->dev, "niu%d: entry [%d] invalid for idx[%d]\n",
7192                             parent->index, (u16)nfc->fs.location, idx);
7193                 return -EINVAL;
7194         }
7195
7196         /* fill the flow spec entry */
7197         class = (tp->key[0] & TCAM_V4KEY0_CLASS_CODE) >>
7198                 TCAM_V4KEY0_CLASS_CODE_SHIFT;
7199         ret = niu_class_to_ethflow(class, &fsp->flow_type);
7200
7201         if (ret < 0) {
7202                 netdev_info(np->dev, "niu%d: niu_class_to_ethflow failed\n",
7203                             parent->index);
7204                 ret = -EINVAL;
7205                 goto out;
7206         }
7207
7208         if (fsp->flow_type == AH_V4_FLOW || fsp->flow_type == AH_V6_FLOW) {
7209                 u32 proto = (tp->key[2] & TCAM_V4KEY2_PROTO) >>
7210                         TCAM_V4KEY2_PROTO_SHIFT;
7211                 if (proto == IPPROTO_ESP) {
7212                         if (fsp->flow_type == AH_V4_FLOW)
7213                                 fsp->flow_type = ESP_V4_FLOW;
7214                         else
7215                                 fsp->flow_type = ESP_V6_FLOW;
7216                 }
7217         }
7218
7219         switch (fsp->flow_type) {
7220         case TCP_V4_FLOW:
7221         case UDP_V4_FLOW:
7222         case SCTP_V4_FLOW:
7223         case AH_V4_FLOW:
7224         case ESP_V4_FLOW:
7225                 niu_get_ip4fs_from_tcam_key(tp, fsp);
7226                 break;
7227         case TCP_V6_FLOW:
7228         case UDP_V6_FLOW:
7229         case SCTP_V6_FLOW:
7230         case AH_V6_FLOW:
7231         case ESP_V6_FLOW:
7232                 /* Not yet implemented */
7233                 ret = -EINVAL;
7234                 break;
7235         case IP_USER_FLOW:
7236                 niu_get_ip4fs_from_tcam_key(tp, fsp);
7237                 break;
7238         default:
7239                 ret = -EINVAL;
7240                 break;
7241         }
7242
7243         if (ret < 0)
7244                 goto out;
7245
7246         if (tp->assoc_data & TCAM_ASSOCDATA_DISC)
7247                 fsp->ring_cookie = RX_CLS_FLOW_DISC;
7248         else
7249                 fsp->ring_cookie = (tp->assoc_data & TCAM_ASSOCDATA_OFFSET) >>
7250                         TCAM_ASSOCDATA_OFFSET_SHIFT;
7251
7252         /* put the tcam size here */
7253         nfc->data = tcam_get_size(np);
7254 out:
7255         return ret;
7256 }
7257
7258 static int niu_get_ethtool_tcam_all(struct niu *np,
7259                                     struct ethtool_rxnfc *nfc,
7260                                     u32 *rule_locs)
7261 {
7262         struct niu_parent *parent = np->parent;
7263         struct niu_tcam_entry *tp;
7264         int i, idx, cnt;
7265         u16 n_entries;
7266         unsigned long flags;
7267
7268
7269         /* put the tcam size here */
7270         nfc->data = tcam_get_size(np);
7271
7272         niu_lock_parent(np, flags);
7273         n_entries = nfc->rule_cnt;
7274         for (cnt = 0, i = 0; i < nfc->data; i++) {
7275                 idx = tcam_get_index(np, i);
7276                 tp = &parent->tcam[idx];
7277                 if (!tp->valid)
7278                         continue;
7279                 rule_locs[cnt] = i;
7280                 cnt++;
7281         }
7282         niu_unlock_parent(np, flags);
7283
7284         if (n_entries != cnt) {
7285                 /* print warning, this should not happen */
7286                 netdev_info(np->dev, "niu%d: In %s(): n_entries[%d] != cnt[%d]!!!\n",
7287                             np->parent->index, __func__, n_entries, cnt);
7288         }
7289
7290         return 0;
7291 }
7292
7293 static int niu_get_nfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
7294                        void *rule_locs)
7295 {
7296         struct niu *np = netdev_priv(dev);
7297         int ret = 0;
7298
7299         switch (cmd->cmd) {
7300         case ETHTOOL_GRXFH:
7301                 ret = niu_get_hash_opts(np, cmd);
7302                 break;
7303         case ETHTOOL_GRXRINGS:
7304                 cmd->data = np->num_rx_rings;
7305                 break;
7306         case ETHTOOL_GRXCLSRLCNT:
7307                 cmd->rule_cnt = tcam_get_valid_entry_cnt(np);
7308                 break;
7309         case ETHTOOL_GRXCLSRULE:
7310                 ret = niu_get_ethtool_tcam_entry(np, cmd);
7311                 break;
7312         case ETHTOOL_GRXCLSRLALL:
7313                 ret = niu_get_ethtool_tcam_all(np, cmd, (u32 *)rule_locs);
7314                 break;
7315         default:
7316                 ret = -EINVAL;
7317                 break;
7318         }
7319
7320         return ret;
7321 }
7322
7323 static int niu_set_hash_opts(struct niu *np, struct ethtool_rxnfc *nfc)
7324 {
7325         u64 class;
7326         u64 flow_key = 0;
7327         unsigned long flags;
7328
7329         if (!niu_ethflow_to_class(nfc->flow_type, &class))
7330                 return -EINVAL;
7331
7332         if (class < CLASS_CODE_USER_PROG1 ||
7333             class > CLASS_CODE_SCTP_IPV6)
7334                 return -EINVAL;
7335
7336         if (nfc->data & RXH_DISCARD) {
7337                 niu_lock_parent(np, flags);
7338                 flow_key = np->parent->tcam_key[class -
7339                                                CLASS_CODE_USER_PROG1];
7340                 flow_key |= TCAM_KEY_DISC;
7341                 nw64(TCAM_KEY(class - CLASS_CODE_USER_PROG1), flow_key);
7342                 np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] = flow_key;
7343                 niu_unlock_parent(np, flags);
7344                 return 0;
7345         } else {
7346                 /* Discard was set before, but is not set now */
7347                 if (np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] &
7348                     TCAM_KEY_DISC) {
7349                         niu_lock_parent(np, flags);
7350                         flow_key = np->parent->tcam_key[class -
7351                                                CLASS_CODE_USER_PROG1];
7352                         flow_key &= ~TCAM_KEY_DISC;
7353                         nw64(TCAM_KEY(class - CLASS_CODE_USER_PROG1),
7354                              flow_key);
7355                         np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] =
7356                                 flow_key;
7357                         niu_unlock_parent(np, flags);
7358                 }
7359         }
7360
7361         if (!niu_ethflow_to_flowkey(nfc->data, &flow_key))
7362                 return -EINVAL;
7363
7364         niu_lock_parent(np, flags);
7365         nw64(FLOW_KEY(class - CLASS_CODE_USER_PROG1), flow_key);
7366         np->parent->flow_key[class - CLASS_CODE_USER_PROG1] = flow_key;
7367         niu_unlock_parent(np, flags);
7368
7369         return 0;
7370 }
7371
7372 static void niu_get_tcamkey_from_ip4fs(struct ethtool_rx_flow_spec *fsp,
7373                                        struct niu_tcam_entry *tp,
7374                                        int l2_rdc_tab, u64 class)
7375 {
7376         u8 pid = 0;
7377         u32 sip, dip, sipm, dipm, spi, spim;
7378         u16 sport, dport, spm, dpm;
7379
7380         sip = be32_to_cpu(fsp->h_u.tcp_ip4_spec.ip4src);
7381         sipm = be32_to_cpu(fsp->m_u.tcp_ip4_spec.ip4src);
7382         dip = be32_to_cpu(fsp->h_u.tcp_ip4_spec.ip4dst);
7383         dipm = be32_to_cpu(fsp->m_u.tcp_ip4_spec.ip4dst);
7384
7385         tp->key[0] = class << TCAM_V4KEY0_CLASS_CODE_SHIFT;
7386         tp->key_mask[0] = TCAM_V4KEY0_CLASS_CODE;
7387         tp->key[1] = (u64)l2_rdc_tab << TCAM_V4KEY1_L2RDCNUM_SHIFT;
7388         tp->key_mask[1] = TCAM_V4KEY1_L2RDCNUM;
7389
7390         tp->key[3] = (u64)sip << TCAM_V4KEY3_SADDR_SHIFT;
7391         tp->key[3] |= dip;
7392
7393         tp->key_mask[3] = (u64)sipm << TCAM_V4KEY3_SADDR_SHIFT;
7394         tp->key_mask[3] |= dipm;
7395
7396         tp->key[2] |= ((u64)fsp->h_u.tcp_ip4_spec.tos <<
7397                        TCAM_V4KEY2_TOS_SHIFT);
7398         tp->key_mask[2] |= ((u64)fsp->m_u.tcp_ip4_spec.tos <<
7399                             TCAM_V4KEY2_TOS_SHIFT);
7400         switch (fsp->flow_type) {
7401         case TCP_V4_FLOW:
7402         case UDP_V4_FLOW:
7403         case SCTP_V4_FLOW:
7404                 sport = be16_to_cpu(fsp->h_u.tcp_ip4_spec.psrc);
7405                 spm = be16_to_cpu(fsp->m_u.tcp_ip4_spec.psrc);
7406                 dport = be16_to_cpu(fsp->h_u.tcp_ip4_spec.pdst);
7407                 dpm = be16_to_cpu(fsp->m_u.tcp_ip4_spec.pdst);
7408
7409                 tp->key[2] |= (((u64)sport << 16) | dport);
7410                 tp->key_mask[2] |= (((u64)spm << 16) | dpm);
7411                 niu_ethflow_to_l3proto(fsp->flow_type, &pid);
7412                 break;
7413         case AH_V4_FLOW:
7414         case ESP_V4_FLOW:
7415                 spi = be32_to_cpu(fsp->h_u.ah_ip4_spec.spi);
7416                 spim = be32_to_cpu(fsp->m_u.ah_ip4_spec.spi);
7417
7418                 tp->key[2] |= spi;
7419                 tp->key_mask[2] |= spim;
7420                 niu_ethflow_to_l3proto(fsp->flow_type, &pid);
7421                 break;
7422         case IP_USER_FLOW:
7423                 spi = be32_to_cpu(fsp->h_u.usr_ip4_spec.l4_4_bytes);
7424                 spim = be32_to_cpu(fsp->m_u.usr_ip4_spec.l4_4_bytes);
7425
7426                 tp->key[2] |= spi;
7427                 tp->key_mask[2] |= spim;
7428                 pid = fsp->h_u.usr_ip4_spec.proto;
7429                 break;
7430         default:
7431                 break;
7432         }
7433
7434         tp->key[2] |= ((u64)pid << TCAM_V4KEY2_PROTO_SHIFT);
7435         if (pid) {
7436                 tp->key_mask[2] |= TCAM_V4KEY2_PROTO;
7437         }
7438 }
7439
7440 static int niu_add_ethtool_tcam_entry(struct niu *np,
7441                                       struct ethtool_rxnfc *nfc)
7442 {
7443         struct niu_parent *parent = np->parent;
7444         struct niu_tcam_entry *tp;
7445         struct ethtool_rx_flow_spec *fsp = &nfc->fs;
7446         struct niu_rdc_tables *rdc_table = &parent->rdc_group_cfg[np->port];
7447         int l2_rdc_table = rdc_table->first_table_num;
7448         u16 idx;
7449         u64 class;
7450         unsigned long flags;
7451         int err, ret;
7452
7453         ret = 0;
7454
7455         idx = nfc->fs.location;
7456         if (idx >= tcam_get_size(np))
7457                 return -EINVAL;
7458
7459         if (fsp->flow_type == IP_USER_FLOW) {
7460                 int i;
7461                 int add_usr_cls = 0;
7462                 int ipv6 = 0;
7463                 struct ethtool_usrip4_spec *uspec = &fsp->h_u.usr_ip4_spec;
7464                 struct ethtool_usrip4_spec *umask = &fsp->m_u.usr_ip4_spec;
7465
7466                 niu_lock_parent(np, flags);
7467
7468                 for (i = 0; i < NIU_L3_PROG_CLS; i++) {
7469                         if (parent->l3_cls[i]) {
7470                                 if (uspec->proto == parent->l3_cls_pid[i]) {
7471                                         class = parent->l3_cls[i];
7472                                         parent->l3_cls_refcnt[i]++;
7473                                         add_usr_cls = 1;
7474                                         break;
7475                                 }
7476                         } else {
7477                                 /* Program new user IP class */
7478                                 switch (i) {
7479                                 case 0:
7480                                         class = CLASS_CODE_USER_PROG1;
7481                                         break;
7482                                 case 1:
7483                                         class = CLASS_CODE_USER_PROG2;
7484                                         break;
7485                                 case 2:
7486                                         class = CLASS_CODE_USER_PROG3;
7487                                         break;
7488                                 case 3:
7489                                         class = CLASS_CODE_USER_PROG4;
7490                                         break;
7491                                 default:
7492                                         break;
7493                                 }
7494                                 if (uspec->ip_ver == ETH_RX_NFC_IP6)
7495                                         ipv6 = 1;
7496                                 ret = tcam_user_ip_class_set(np, class, ipv6,
7497                                                              uspec->proto,
7498                                                              uspec->tos,
7499                                                              umask->tos);
7500                                 if (ret)
7501                                         goto out;
7502
7503                                 ret = tcam_user_ip_class_enable(np, class, 1);
7504                                 if (ret)
7505                                         goto out;
7506                                 parent->l3_cls[i] = class;
7507                                 parent->l3_cls_pid[i] = uspec->proto;
7508                                 parent->l3_cls_refcnt[i]++;
7509                                 add_usr_cls = 1;
7510                                 break;
7511                         }
7512                 }
7513                 if (!add_usr_cls) {
7514                         netdev_info(np->dev, "niu%d: %s(): Could not find/insert class for pid %d\n",
7515                                     parent->index, __func__, uspec->proto);
7516                         ret = -EINVAL;
7517                         goto out;
7518                 }
7519                 niu_unlock_parent(np, flags);
7520         } else {
7521                 if (!niu_ethflow_to_class(fsp->flow_type, &class)) {
7522                         return -EINVAL;
7523                 }
7524         }
7525
7526         niu_lock_parent(np, flags);
7527
7528         idx = tcam_get_index(np, idx);
7529         tp = &parent->tcam[idx];
7530
7531         memset(tp, 0, sizeof(*tp));
7532
7533         /* fill in the tcam key and mask */
7534         switch (fsp->flow_type) {
7535         case TCP_V4_FLOW:
7536         case UDP_V4_FLOW:
7537         case SCTP_V4_FLOW:
7538         case AH_V4_FLOW:
7539         case ESP_V4_FLOW:
7540                 niu_get_tcamkey_from_ip4fs(fsp, tp, l2_rdc_table, class);
7541                 break;
7542         case TCP_V6_FLOW:
7543         case UDP_V6_FLOW:
7544         case SCTP_V6_FLOW:
7545         case AH_V6_FLOW:
7546         case ESP_V6_FLOW:
7547                 /* Not yet implemented */
7548                 netdev_info(np->dev, "niu%d: In %s(): flow %d for IPv6 not implemented\n",
7549                             parent->index, __func__, fsp->flow_type);
7550                 ret = -EINVAL;
7551                 goto out;
7552         case IP_USER_FLOW:
7553                 if (fsp->h_u.usr_ip4_spec.ip_ver == ETH_RX_NFC_IP4) {
7554                         niu_get_tcamkey_from_ip4fs(fsp, tp, l2_rdc_table,
7555                                                    class);
7556                 } else {
7557                         /* Not yet implemented */
7558                         netdev_info(np->dev, "niu%d: In %s(): usr flow for IPv6 not implemented\n",
7559                                     parent->index, __func__);
7560                         ret = -EINVAL;
7561                         goto out;
7562                 }
7563                 break;
7564         default:
7565                 netdev_info(np->dev, "niu%d: In %s(): Unknown flow type %d\n",
7566                             parent->index, __func__, fsp->flow_type);
7567                 ret = -EINVAL;
7568                 goto out;
7569         }
7570
7571         /* fill in the assoc data */
7572         if (fsp->ring_cookie == RX_CLS_FLOW_DISC) {
7573                 tp->assoc_data = TCAM_ASSOCDATA_DISC;
7574         } else {
7575                 if (fsp->ring_cookie >= np->num_rx_rings) {
7576                         netdev_info(np->dev, "niu%d: In %s(): Invalid RX ring %lld\n",
7577                                     parent->index, __func__,
7578                                     (long long)fsp->ring_cookie);
7579                         ret = -EINVAL;
7580                         goto out;
7581                 }
7582                 tp->assoc_data = (TCAM_ASSOCDATA_TRES_USE_OFFSET |
7583                                   (fsp->ring_cookie <<
7584                                    TCAM_ASSOCDATA_OFFSET_SHIFT));
7585         }
7586
7587         err = tcam_write(np, idx, tp->key, tp->key_mask);
7588         if (err) {
7589                 ret = -EINVAL;
7590                 goto out;
7591         }
7592         err = tcam_assoc_write(np, idx, tp->assoc_data);
7593         if (err) {
7594                 ret = -EINVAL;
7595                 goto out;
7596         }
7597
7598         /* validate the entry */
7599         tp->valid = 1;
7600         np->clas.tcam_valid_entries++;
7601 out:
7602         niu_unlock_parent(np, flags);
7603
7604         return ret;
7605 }
7606
7607 static int niu_del_ethtool_tcam_entry(struct niu *np, u32 loc)
7608 {
7609         struct niu_parent *parent = np->parent;
7610         struct niu_tcam_entry *tp;
7611         u16 idx;
7612         unsigned long flags;
7613         u64 class;
7614         int ret = 0;
7615
7616         if (loc >= tcam_get_size(np))
7617                 return -EINVAL;
7618
7619         niu_lock_parent(np, flags);
7620
7621         idx = tcam_get_index(np, loc);
7622         tp = &parent->tcam[idx];
7623
7624         /* if the entry is of a user defined class, then update*/
7625         class = (tp->key[0] & TCAM_V4KEY0_CLASS_CODE) >>
7626                 TCAM_V4KEY0_CLASS_CODE_SHIFT;
7627
7628         if (class >= CLASS_CODE_USER_PROG1 && class <= CLASS_CODE_USER_PROG4) {
7629                 int i;
7630                 for (i = 0; i < NIU_L3_PROG_CLS; i++) {
7631                         if (parent->l3_cls[i] == class) {
7632                                 parent->l3_cls_refcnt[i]--;
7633                                 if (!parent->l3_cls_refcnt[i]) {
7634                                         /* disable class */
7635                                         ret = tcam_user_ip_class_enable(np,
7636                                                                         class,
7637                                                                         0);
7638                                         if (ret)
7639                                                 goto out;
7640                                         parent->l3_cls[i] = 0;
7641                                         parent->l3_cls_pid[i] = 0;
7642                                 }
7643                                 break;
7644                         }
7645                 }
7646                 if (i == NIU_L3_PROG_CLS) {
7647                         netdev_info(np->dev, "niu%d: In %s(): Usr class 0x%llx not found\n",
7648                                     parent->index, __func__,
7649                                     (unsigned long long)class);
7650                         ret = -EINVAL;
7651                         goto out;
7652                 }
7653         }
7654
7655         ret = tcam_flush(np, idx);
7656         if (ret)
7657                 goto out;
7658
7659         /* invalidate the entry */
7660         tp->valid = 0;
7661         np->clas.tcam_valid_entries--;
7662 out:
7663         niu_unlock_parent(np, flags);
7664
7665         return ret;
7666 }
7667
7668 static int niu_set_nfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
7669 {
7670         struct niu *np = netdev_priv(dev);
7671         int ret = 0;
7672
7673         switch (cmd->cmd) {
7674         case ETHTOOL_SRXFH:
7675                 ret = niu_set_hash_opts(np, cmd);
7676                 break;
7677         case ETHTOOL_SRXCLSRLINS:
7678                 ret = niu_add_ethtool_tcam_entry(np, cmd);
7679                 break;
7680         case ETHTOOL_SRXCLSRLDEL:
7681                 ret = niu_del_ethtool_tcam_entry(np, cmd->fs.location);
7682                 break;
7683         default:
7684                 ret = -EINVAL;
7685                 break;
7686         }
7687
7688         return ret;
7689 }
7690
7691 static const struct {
7692         const char string[ETH_GSTRING_LEN];
7693 } niu_xmac_stat_keys[] = {
7694         { "tx_frames" },
7695         { "tx_bytes" },
7696         { "tx_fifo_errors" },
7697         { "tx_overflow_errors" },
7698         { "tx_max_pkt_size_errors" },
7699         { "tx_underflow_errors" },
7700         { "rx_local_faults" },
7701         { "rx_remote_faults" },
7702         { "rx_link_faults" },
7703         { "rx_align_errors" },
7704         { "rx_frags" },
7705         { "rx_mcasts" },
7706         { "rx_bcasts" },
7707         { "rx_hist_cnt1" },
7708         { "rx_hist_cnt2" },
7709         { "rx_hist_cnt3" },
7710         { "rx_hist_cnt4" },
7711         { "rx_hist_cnt5" },
7712         { "rx_hist_cnt6" },
7713         { "rx_hist_cnt7" },
7714         { "rx_octets" },
7715         { "rx_code_violations" },
7716         { "rx_len_errors" },
7717         { "rx_crc_errors" },
7718         { "rx_underflows" },
7719         { "rx_overflows" },
7720         { "pause_off_state" },
7721         { "pause_on_state" },
7722         { "pause_received" },
7723 };
7724
7725 #define NUM_XMAC_STAT_KEYS      ARRAY_SIZE(niu_xmac_stat_keys)
7726
7727 static const struct {
7728         const char string[ETH_GSTRING_LEN];
7729 } niu_bmac_stat_keys[] = {
7730         { "tx_underflow_errors" },
7731         { "tx_max_pkt_size_errors" },
7732         { "tx_bytes" },
7733         { "tx_frames" },
7734         { "rx_overflows" },
7735         { "rx_frames" },
7736         { "rx_align_errors" },
7737         { "rx_crc_errors" },
7738         { "rx_len_errors" },
7739         { "pause_off_state" },
7740         { "pause_on_state" },
7741         { "pause_received" },
7742 };
7743
7744 #define NUM_BMAC_STAT_KEYS      ARRAY_SIZE(niu_bmac_stat_keys)
7745
7746 static const struct {
7747         const char string[ETH_GSTRING_LEN];
7748 } niu_rxchan_stat_keys[] = {
7749         { "rx_channel" },
7750         { "rx_packets" },
7751         { "rx_bytes" },
7752         { "rx_dropped" },
7753         { "rx_errors" },
7754 };
7755
7756 #define NUM_RXCHAN_STAT_KEYS    ARRAY_SIZE(niu_rxchan_stat_keys)
7757
7758 static const struct {
7759         const char string[ETH_GSTRING_LEN];
7760 } niu_txchan_stat_keys[] = {
7761         { "tx_channel" },
7762         { "tx_packets" },
7763         { "tx_bytes" },
7764         { "tx_errors" },
7765 };
7766
7767 #define NUM_TXCHAN_STAT_KEYS    ARRAY_SIZE(niu_txchan_stat_keys)
7768
7769 static void niu_get_strings(struct net_device *dev, u32 stringset, u8 *data)
7770 {
7771         struct niu *np = netdev_priv(dev);
7772         int i;
7773
7774         if (stringset != ETH_SS_STATS)
7775                 return;
7776
7777         if (np->flags & NIU_FLAGS_XMAC) {
7778                 memcpy(data, niu_xmac_stat_keys,
7779                        sizeof(niu_xmac_stat_keys));
7780                 data += sizeof(niu_xmac_stat_keys);
7781         } else {
7782                 memcpy(data, niu_bmac_stat_keys,
7783                        sizeof(niu_bmac_stat_keys));
7784                 data += sizeof(niu_bmac_stat_keys);
7785         }
7786         for (i = 0; i < np->num_rx_rings; i++) {
7787                 memcpy(data, niu_rxchan_stat_keys,
7788                        sizeof(niu_rxchan_stat_keys));
7789                 data += sizeof(niu_rxchan_stat_keys);
7790         }
7791         for (i = 0; i < np->num_tx_rings; i++) {
7792                 memcpy(data, niu_txchan_stat_keys,
7793                        sizeof(niu_txchan_stat_keys));
7794                 data += sizeof(niu_txchan_stat_keys);
7795         }
7796 }
7797
7798 static int niu_get_sset_count(struct net_device *dev, int stringset)
7799 {
7800         struct niu *np = netdev_priv(dev);
7801
7802         if (stringset != ETH_SS_STATS)
7803                 return -EINVAL;
7804
7805         return ((np->flags & NIU_FLAGS_XMAC ?
7806                  NUM_XMAC_STAT_KEYS :
7807                  NUM_BMAC_STAT_KEYS) +
7808                 (np->num_rx_rings * NUM_RXCHAN_STAT_KEYS) +
7809                 (np->num_tx_rings * NUM_TXCHAN_STAT_KEYS));
7810 }
7811
7812 static void niu_get_ethtool_stats(struct net_device *dev,
7813                                   struct ethtool_stats *stats, u64 *data)
7814 {
7815         struct niu *np = netdev_priv(dev);
7816         int i;
7817
7818         niu_sync_mac_stats(np);
7819         if (np->flags & NIU_FLAGS_XMAC) {
7820                 memcpy(data, &np->mac_stats.xmac,
7821                        sizeof(struct niu_xmac_stats));
7822                 data += (sizeof(struct niu_xmac_stats) / sizeof(u64));
7823         } else {
7824                 memcpy(data, &np->mac_stats.bmac,
7825                        sizeof(struct niu_bmac_stats));
7826                 data += (sizeof(struct niu_bmac_stats) / sizeof(u64));
7827         }
7828         for (i = 0; i < np->num_rx_rings; i++) {
7829                 struct rx_ring_info *rp = &np->rx_rings[i];
7830
7831                 niu_sync_rx_discard_stats(np, rp, 0);
7832
7833                 data[0] = rp->rx_channel;
7834                 data[1] = rp->rx_packets;
7835                 data[2] = rp->rx_bytes;
7836                 data[3] = rp->rx_dropped;
7837                 data[4] = rp->rx_errors;
7838                 data += 5;
7839         }
7840         for (i = 0; i < np->num_tx_rings; i++) {
7841                 struct tx_ring_info *rp = &np->tx_rings[i];
7842
7843                 data[0] = rp->tx_channel;
7844                 data[1] = rp->tx_packets;
7845                 data[2] = rp->tx_bytes;
7846                 data[3] = rp->tx_errors;
7847                 data += 4;
7848         }
7849 }
7850
7851 static u64 niu_led_state_save(struct niu *np)
7852 {
7853         if (np->flags & NIU_FLAGS_XMAC)
7854                 return nr64_mac(XMAC_CONFIG);
7855         else
7856                 return nr64_mac(BMAC_XIF_CONFIG);
7857 }
7858
7859 static void niu_led_state_restore(struct niu *np, u64 val)
7860 {
7861         if (np->flags & NIU_FLAGS_XMAC)
7862                 nw64_mac(XMAC_CONFIG, val);
7863         else
7864                 nw64_mac(BMAC_XIF_CONFIG, val);
7865 }
7866
7867 static void niu_force_led(struct niu *np, int on)
7868 {
7869         u64 val, reg, bit;
7870
7871         if (np->flags & NIU_FLAGS_XMAC) {
7872                 reg = XMAC_CONFIG;
7873                 bit = XMAC_CONFIG_FORCE_LED_ON;
7874         } else {
7875                 reg = BMAC_XIF_CONFIG;
7876                 bit = BMAC_XIF_CONFIG_LINK_LED;
7877         }
7878
7879         val = nr64_mac(reg);
7880         if (on)
7881                 val |= bit;
7882         else
7883                 val &= ~bit;
7884         nw64_mac(reg, val);
7885 }
7886
7887 static int niu_phys_id(struct net_device *dev, u32 data)
7888 {
7889         struct niu *np = netdev_priv(dev);
7890         u64 orig_led_state;
7891         int i;
7892
7893         if (!netif_running(dev))
7894                 return -EAGAIN;
7895
7896         if (data == 0)
7897                 data = 2;
7898
7899         orig_led_state = niu_led_state_save(np);
7900         for (i = 0; i < (data * 2); i++) {
7901                 int on = ((i % 2) == 0);
7902
7903                 niu_force_led(np, on);
7904
7905                 if (msleep_interruptible(500))
7906                         break;
7907         }
7908         niu_led_state_restore(np, orig_led_state);
7909
7910         return 0;
7911 }
7912
7913 static const struct ethtool_ops niu_ethtool_ops = {
7914         .get_drvinfo            = niu_get_drvinfo,
7915         .get_link               = ethtool_op_get_link,
7916         .get_msglevel           = niu_get_msglevel,
7917         .set_msglevel           = niu_set_msglevel,
7918         .nway_reset             = niu_nway_reset,
7919         .get_eeprom_len         = niu_get_eeprom_len,
7920         .get_eeprom             = niu_get_eeprom,
7921         .get_settings           = niu_get_settings,
7922         .set_settings           = niu_set_settings,
7923         .get_strings            = niu_get_strings,
7924         .get_sset_count         = niu_get_sset_count,
7925         .get_ethtool_stats      = niu_get_ethtool_stats,
7926         .phys_id                = niu_phys_id,
7927         .get_rxnfc              = niu_get_nfc,
7928         .set_rxnfc              = niu_set_nfc,
7929 };
7930
7931 static int niu_ldg_assign_ldn(struct niu *np, struct niu_parent *parent,
7932                               int ldg, int ldn)
7933 {
7934         if (ldg < NIU_LDG_MIN || ldg > NIU_LDG_MAX)
7935                 return -EINVAL;
7936         if (ldn < 0 || ldn > LDN_MAX)
7937                 return -EINVAL;
7938
7939         parent->ldg_map[ldn] = ldg;
7940
7941         if (np->parent->plat_type == PLAT_TYPE_NIU) {
7942                 /* On N2 NIU, the ldn-->ldg assignments are setup and fixed by
7943                  * the firmware, and we're not supposed to change them.
7944                  * Validate the mapping, because if it's wrong we probably
7945                  * won't get any interrupts and that's painful to debug.
7946                  */
7947                 if (nr64(LDG_NUM(ldn)) != ldg) {
7948                         dev_err(np->device, "Port %u, mis-matched LDG assignment for ldn %d, should be %d is %llu\n",
7949                                 np->port, ldn, ldg,
7950                                 (unsigned long long) nr64(LDG_NUM(ldn)));
7951                         return -EINVAL;
7952                 }
7953         } else
7954                 nw64(LDG_NUM(ldn), ldg);
7955
7956         return 0;
7957 }
7958
7959 static int niu_set_ldg_timer_res(struct niu *np, int res)
7960 {
7961         if (res < 0 || res > LDG_TIMER_RES_VAL)
7962                 return -EINVAL;
7963
7964
7965         nw64(LDG_TIMER_RES, res);
7966
7967         return 0;
7968 }
7969
7970 static int niu_set_ldg_sid(struct niu *np, int ldg, int func, int vector)
7971 {
7972         if ((ldg < NIU_LDG_MIN || ldg > NIU_LDG_MAX) ||
7973             (func < 0 || func > 3) ||
7974             (vector < 0 || vector > 0x1f))
7975                 return -EINVAL;
7976
7977         nw64(SID(ldg), (func << SID_FUNC_SHIFT) | vector);
7978
7979         return 0;
7980 }
7981
7982 static int __devinit niu_pci_eeprom_read(struct niu *np, u32 addr)
7983 {
7984         u64 frame, frame_base = (ESPC_PIO_STAT_READ_START |
7985                                  (addr << ESPC_PIO_STAT_ADDR_SHIFT));
7986         int limit;
7987
7988         if (addr > (ESPC_PIO_STAT_ADDR >> ESPC_PIO_STAT_ADDR_SHIFT))
7989                 return -EINVAL;
7990
7991         frame = frame_base;
7992         nw64(ESPC_PIO_STAT, frame);
7993         limit = 64;
7994         do {
7995                 udelay(5);
7996                 frame = nr64(ESPC_PIO_STAT);
7997                 if (frame & ESPC_PIO_STAT_READ_END)
7998                         break;
7999         } while (limit--);
8000         if (!(frame & ESPC_PIO_STAT_READ_END)) {
8001                 dev_err(np->device, "EEPROM read timeout frame[%llx]\n",
8002                         (unsigned long long) frame);
8003                 return -ENODEV;
8004         }
8005
8006         frame = frame_base;
8007         nw64(ESPC_PIO_STAT, frame);
8008         limit = 64;
8009         do {
8010                 udelay(5);
8011                 frame = nr64(ESPC_PIO_STAT);
8012                 if (frame & ESPC_PIO_STAT_READ_END)
8013                         break;
8014         } while (limit--);
8015         if (!(frame & ESPC_PIO_STAT_READ_END)) {
8016                 dev_err(np->device, "EEPROM read timeout frame[%llx]\n",
8017                         (unsigned long long) frame);
8018                 return -ENODEV;
8019         }
8020
8021         frame = nr64(ESPC_PIO_STAT);
8022         return (frame & ESPC_PIO_STAT_DATA) >> ESPC_PIO_STAT_DATA_SHIFT;
8023 }
8024
8025 static int __devinit niu_pci_eeprom_read16(struct niu *np, u32 off)
8026 {
8027         int err = niu_pci_eeprom_read(np, off);
8028         u16 val;
8029
8030         if (err < 0)
8031                 return err;
8032         val = (err << 8);
8033         err = niu_pci_eeprom_read(np, off + 1);
8034         if (err < 0)
8035                 return err;
8036         val |= (err & 0xff);
8037
8038         return val;
8039 }
8040
8041 static int __devinit niu_pci_eeprom_read16_swp(struct niu *np, u32 off)
8042 {
8043         int err = niu_pci_eeprom_read(np, off);
8044         u16 val;
8045
8046         if (err < 0)
8047                 return err;
8048
8049         val = (err & 0xff);
8050         err = niu_pci_eeprom_read(np, off + 1);
8051         if (err < 0)
8052                 return err;
8053
8054         val |= (err & 0xff) << 8;
8055
8056         return val;
8057 }
8058
8059 static int __devinit niu_pci_vpd_get_propname(struct niu *np,
8060                                               u32 off,
8061                                               char *namebuf,
8062                                               int namebuf_len)
8063 {
8064         int i;
8065
8066         for (i = 0; i < namebuf_len; i++) {
8067                 int err = niu_pci_eeprom_read(np, off + i);
8068                 if (err < 0)
8069                         return err;
8070                 *namebuf++ = err;
8071                 if (!err)
8072                         break;
8073         }
8074         if (i >= namebuf_len)
8075                 return -EINVAL;
8076
8077         return i + 1;
8078 }
8079
8080 static void __devinit niu_vpd_parse_version(struct niu *np)
8081 {
8082         struct niu_vpd *vpd = &np->vpd;
8083         int len = strlen(vpd->version) + 1;
8084         const char *s = vpd->version;
8085         int i;
8086
8087         for (i = 0; i < len - 5; i++) {
8088                 if (!strncmp(s + i, "FCode ", 6))
8089                         break;
8090         }
8091         if (i >= len - 5)
8092                 return;
8093
8094         s += i + 5;
8095         sscanf(s, "%d.%d", &vpd->fcode_major, &vpd->fcode_minor);
8096
8097         netif_printk(np, probe, KERN_DEBUG, np->dev,
8098                      "VPD_SCAN: FCODE major(%d) minor(%d)\n",
8099                      vpd->fcode_major, vpd->fcode_minor);
8100         if (vpd->fcode_major > NIU_VPD_MIN_MAJOR ||
8101             (vpd->fcode_major == NIU_VPD_MIN_MAJOR &&
8102              vpd->fcode_minor >= NIU_VPD_MIN_MINOR))
8103                 np->flags |= NIU_FLAGS_VPD_VALID;
8104 }
8105
8106 /* ESPC_PIO_EN_ENABLE must be set */
8107 static int __devinit niu_pci_vpd_scan_props(struct niu *np,
8108                                             u32 start, u32 end)
8109 {
8110         unsigned int found_mask = 0;
8111 #define FOUND_MASK_MODEL        0x00000001
8112 #define FOUND_MASK_BMODEL       0x00000002
8113 #define FOUND_MASK_VERS         0x00000004
8114 #define FOUND_MASK_MAC          0x00000008
8115 #define FOUND_MASK_NMAC         0x00000010
8116 #define FOUND_MASK_PHY          0x00000020
8117 #define FOUND_MASK_ALL          0x0000003f
8118
8119         netif_printk(np, probe, KERN_DEBUG, np->dev,
8120                      "VPD_SCAN: start[%x] end[%x]\n", start, end);
8121         while (start < end) {
8122                 int len, err, instance, type, prop_len;
8123                 char namebuf[64];
8124                 u8 *prop_buf;
8125                 int max_len;
8126
8127                 if (found_mask == FOUND_MASK_ALL) {
8128                         niu_vpd_parse_version(np);
8129                         return 1;
8130                 }
8131
8132                 err = niu_pci_eeprom_read(np, start + 2);
8133                 if (err < 0)
8134                         return err;
8135                 len = err;
8136                 start += 3;
8137
8138                 instance = niu_pci_eeprom_read(np, start);
8139                 type = niu_pci_eeprom_read(np, start + 3);
8140                 prop_len = niu_pci_eeprom_read(np, start + 4);
8141                 err = niu_pci_vpd_get_propname(np, start + 5, namebuf, 64);
8142                 if (err < 0)
8143                         return err;
8144
8145                 prop_buf = NULL;
8146                 max_len = 0;
8147                 if (!strcmp(namebuf, "model")) {
8148                         prop_buf = np->vpd.model;
8149                         max_len = NIU_VPD_MODEL_MAX;
8150                         found_mask |= FOUND_MASK_MODEL;
8151                 } else if (!strcmp(namebuf, "board-model")) {
8152                         prop_buf = np->vpd.board_model;
8153                         max_len = NIU_VPD_BD_MODEL_MAX;
8154                         found_mask |= FOUND_MASK_BMODEL;
8155                 } else if (!strcmp(namebuf, "version")) {
8156                         prop_buf = np->vpd.version;
8157                         max_len = NIU_VPD_VERSION_MAX;
8158                         found_mask |= FOUND_MASK_VERS;
8159                 } else if (!strcmp(namebuf, "local-mac-address")) {
8160                         prop_buf = np->vpd.local_mac;
8161                         max_len = ETH_ALEN;
8162                         found_mask |= FOUND_MASK_MAC;
8163                 } else if (!strcmp(namebuf, "num-mac-addresses")) {
8164                         prop_buf = &np->vpd.mac_num;
8165                         max_len = 1;
8166                         found_mask |= FOUND_MASK_NMAC;
8167                 } else if (!strcmp(namebuf, "phy-type")) {
8168                         prop_buf = np->vpd.phy_type;
8169                         max_len = NIU_VPD_PHY_TYPE_MAX;
8170                         found_mask |= FOUND_MASK_PHY;
8171                 }
8172
8173                 if (max_len && prop_len > max_len) {
8174                         dev_err(np->device, "Property '%s' length (%d) is too long\n", namebuf, prop_len);
8175                         return -EINVAL;
8176                 }
8177
8178                 if (prop_buf) {
8179                         u32 off = start + 5 + err;
8180                         int i;
8181
8182                         netif_printk(np, probe, KERN_DEBUG, np->dev,
8183                                      "VPD_SCAN: Reading in property [%s] len[%d]\n",
8184                                      namebuf, prop_len);
8185                         for (i = 0; i < prop_len; i++)
8186                                 *prop_buf++ = niu_pci_eeprom_read(np, off + i);
8187                 }
8188
8189                 start += len;
8190         }
8191
8192         return 0;
8193 }
8194
8195 /* ESPC_PIO_EN_ENABLE must be set */
8196 static void __devinit niu_pci_vpd_fetch(struct niu *np, u32 start)
8197 {
8198         u32 offset;
8199         int err;
8200
8201         err = niu_pci_eeprom_read16_swp(np, start + 1);
8202         if (err < 0)
8203                 return;
8204
8205         offset = err + 3;
8206
8207         while (start + offset < ESPC_EEPROM_SIZE) {
8208                 u32 here = start + offset;
8209                 u32 end;
8210
8211                 err = niu_pci_eeprom_read(np, here);
8212                 if (err != 0x90)
8213                         return;
8214
8215                 err = niu_pci_eeprom_read16_swp(np, here + 1);
8216                 if (err < 0)
8217                         return;
8218
8219                 here = start + offset + 3;
8220                 end = start + offset + err;
8221
8222                 offset += err;
8223
8224                 err = niu_pci_vpd_scan_props(np, here, end);
8225                 if (err < 0 || err == 1)
8226                         return;
8227         }
8228 }
8229
8230 /* ESPC_PIO_EN_ENABLE must be set */
8231 static u32 __devinit niu_pci_vpd_offset(struct niu *np)
8232 {
8233         u32 start = 0, end = ESPC_EEPROM_SIZE, ret;
8234         int err;
8235
8236         while (start < end) {
8237                 ret = start;
8238
8239                 /* ROM header signature?  */
8240                 err = niu_pci_eeprom_read16(np, start +  0);
8241                 if (err != 0x55aa)
8242                         return 0;
8243
8244                 /* Apply offset to PCI data structure.  */
8245                 err = niu_pci_eeprom_read16(np, start + 23);
8246                 if (err < 0)
8247                         return 0;
8248                 start += err;
8249
8250                 /* Check for "PCIR" signature.  */
8251                 err = niu_pci_eeprom_read16(np, start +  0);
8252                 if (err != 0x5043)
8253                         return 0;
8254                 err = niu_pci_eeprom_read16(np, start +  2);
8255                 if (err != 0x4952)
8256                         return 0;
8257
8258                 /* Check for OBP image type.  */
8259                 err = niu_pci_eeprom_read(np, start + 20);
8260                 if (err < 0)
8261                         return 0;
8262                 if (err != 0x01) {
8263                         err = niu_pci_eeprom_read(np, ret + 2);
8264                         if (err < 0)
8265                                 return 0;
8266
8267                         start = ret + (err * 512);
8268                         continue;
8269                 }
8270
8271                 err = niu_pci_eeprom_read16_swp(np, start + 8);
8272                 if (err < 0)
8273                         return err;
8274                 ret += err;
8275
8276                 err = niu_pci_eeprom_read(np, ret + 0);
8277                 if (err != 0x82)
8278                         return 0;
8279
8280                 return ret;
8281         }
8282
8283         return 0;
8284 }
8285
8286 static int __devinit niu_phy_type_prop_decode(struct niu *np,
8287                                               const char *phy_prop)
8288 {
8289         if (!strcmp(phy_prop, "mif")) {
8290                 /* 1G copper, MII */
8291                 np->flags &= ~(NIU_FLAGS_FIBER |
8292                                NIU_FLAGS_10G);
8293                 np->mac_xcvr = MAC_XCVR_MII;
8294         } else if (!strcmp(phy_prop, "xgf")) {
8295                 /* 10G fiber, XPCS */
8296                 np->flags |= (NIU_FLAGS_10G |
8297                               NIU_FLAGS_FIBER);
8298                 np->mac_xcvr = MAC_XCVR_XPCS;
8299         } else if (!strcmp(phy_prop, "pcs")) {
8300                 /* 1G fiber, PCS */
8301                 np->flags &= ~NIU_FLAGS_10G;
8302                 np->flags |= NIU_FLAGS_FIBER;
8303                 np->mac_xcvr = MAC_XCVR_PCS;
8304         } else if (!strcmp(phy_prop, "xgc")) {
8305                 /* 10G copper, XPCS */
8306                 np->flags |= NIU_FLAGS_10G;
8307                 np->flags &= ~NIU_FLAGS_FIBER;
8308                 np->mac_xcvr = MAC_XCVR_XPCS;
8309         } else if (!strcmp(phy_prop, "xgsd") || !strcmp(phy_prop, "gsd")) {
8310                 /* 10G Serdes or 1G Serdes, default to 10G */
8311                 np->flags |= NIU_FLAGS_10G;
8312                 np->flags &= ~NIU_FLAGS_FIBER;
8313                 np->flags |= NIU_FLAGS_XCVR_SERDES;
8314                 np->mac_xcvr = MAC_XCVR_XPCS;
8315         } else {
8316                 return -EINVAL;
8317         }
8318         return 0;
8319 }
8320
8321 static int niu_pci_vpd_get_nports(struct niu *np)
8322 {
8323         int ports = 0;
8324
8325         if ((!strcmp(np->vpd.model, NIU_QGC_LP_MDL_STR)) ||
8326             (!strcmp(np->vpd.model, NIU_QGC_PEM_MDL_STR)) ||
8327             (!strcmp(np->vpd.model, NIU_MARAMBA_MDL_STR)) ||
8328             (!strcmp(np->vpd.model, NIU_KIMI_MDL_STR)) ||
8329             (!strcmp(np->vpd.model, NIU_ALONSO_MDL_STR))) {
8330                 ports = 4;
8331         } else if ((!strcmp(np->vpd.model, NIU_2XGF_LP_MDL_STR)) ||
8332                    (!strcmp(np->vpd.model, NIU_2XGF_PEM_MDL_STR)) ||
8333                    (!strcmp(np->vpd.model, NIU_FOXXY_MDL_STR)) ||
8334                    (!strcmp(np->vpd.model, NIU_2XGF_MRVL_MDL_STR))) {
8335                 ports = 2;
8336         }
8337
8338         return ports;
8339 }
8340
8341 static void __devinit niu_pci_vpd_validate(struct niu *np)
8342 {
8343         struct net_device *dev = np->dev;
8344         struct niu_vpd *vpd = &np->vpd;
8345         u8 val8;
8346
8347         if (!is_valid_ether_addr(&vpd->local_mac[0])) {
8348                 dev_err(np->device, "VPD MAC invalid, falling back to SPROM\n");
8349
8350                 np->flags &= ~NIU_FLAGS_VPD_VALID;
8351                 return;
8352         }
8353
8354         if (!strcmp(np->vpd.model, NIU_ALONSO_MDL_STR) ||
8355             !strcmp(np->vpd.model, NIU_KIMI_MDL_STR)) {
8356                 np->flags |= NIU_FLAGS_10G;
8357                 np->flags &= ~NIU_FLAGS_FIBER;
8358                 np->flags |= NIU_FLAGS_XCVR_SERDES;
8359                 np->mac_xcvr = MAC_XCVR_PCS;
8360                 if (np->port > 1) {
8361                         np->flags |= NIU_FLAGS_FIBER;
8362                         np->flags &= ~NIU_FLAGS_10G;
8363                 }
8364                 if (np->flags & NIU_FLAGS_10G)
8365                         np->mac_xcvr = MAC_XCVR_XPCS;
8366         } else if (!strcmp(np->vpd.model, NIU_FOXXY_MDL_STR)) {
8367                 np->flags |= (NIU_FLAGS_10G | NIU_FLAGS_FIBER |
8368                               NIU_FLAGS_HOTPLUG_PHY);
8369         } else if (niu_phy_type_prop_decode(np, np->vpd.phy_type)) {
8370                 dev_err(np->device, "Illegal phy string [%s]\n",
8371                         np->vpd.phy_type);
8372                 dev_err(np->device, "Falling back to SPROM\n");
8373                 np->flags &= ~NIU_FLAGS_VPD_VALID;
8374                 return;
8375         }
8376
8377         memcpy(dev->perm_addr, vpd->local_mac, ETH_ALEN);
8378
8379         val8 = dev->perm_addr[5];
8380         dev->perm_addr[5] += np->port;
8381         if (dev->perm_addr[5] < val8)
8382                 dev->perm_addr[4]++;
8383
8384         memcpy(dev->dev_addr, dev->perm_addr, dev->addr_len);
8385 }
8386
8387 static int __devinit niu_pci_probe_sprom(struct niu *np)
8388 {
8389         struct net_device *dev = np->dev;
8390         int len, i;
8391         u64 val, sum;
8392         u8 val8;
8393
8394         val = (nr64(ESPC_VER_IMGSZ) & ESPC_VER_IMGSZ_IMGSZ);
8395         val >>= ESPC_VER_IMGSZ_IMGSZ_SHIFT;
8396         len = val / 4;
8397
8398         np->eeprom_len = len;
8399
8400         netif_printk(np, probe, KERN_DEBUG, np->dev,
8401                      "SPROM: Image size %llu\n", (unsigned long long)val);
8402
8403         sum = 0;
8404         for (i = 0; i < len; i++) {
8405                 val = nr64(ESPC_NCR(i));
8406                 sum += (val >>  0) & 0xff;
8407                 sum += (val >>  8) & 0xff;
8408                 sum += (val >> 16) & 0xff;
8409                 sum += (val >> 24) & 0xff;
8410         }
8411         netif_printk(np, probe, KERN_DEBUG, np->dev,
8412                      "SPROM: Checksum %x\n", (int)(sum & 0xff));
8413         if ((sum & 0xff) != 0xab) {
8414                 dev_err(np->device, "Bad SPROM checksum (%x, should be 0xab)\n", (int)(sum & 0xff));
8415                 return -EINVAL;
8416         }
8417
8418         val = nr64(ESPC_PHY_TYPE);
8419         switch (np->port) {
8420         case 0:
8421                 val8 = (val & ESPC_PHY_TYPE_PORT0) >>
8422                         ESPC_PHY_TYPE_PORT0_SHIFT;
8423                 break;
8424         case 1:
8425                 val8 = (val & ESPC_PHY_TYPE_PORT1) >>
8426                         ESPC_PHY_TYPE_PORT1_SHIFT;
8427                 break;
8428         case 2:
8429                 val8 = (val & ESPC_PHY_TYPE_PORT2) >>
8430                         ESPC_PHY_TYPE_PORT2_SHIFT;
8431                 break;
8432         case 3:
8433                 val8 = (val & ESPC_PHY_TYPE_PORT3) >>
8434                         ESPC_PHY_TYPE_PORT3_SHIFT;
8435                 break;
8436         default:
8437                 dev_err(np->device, "Bogus port number %u\n",
8438                         np->port);
8439                 return -EINVAL;
8440         }
8441         netif_printk(np, probe, KERN_DEBUG, np->dev,
8442                      "SPROM: PHY type %x\n", val8);
8443
8444         switch (val8) {
8445         case ESPC_PHY_TYPE_1G_COPPER:
8446                 /* 1G copper, MII */
8447                 np->flags &= ~(NIU_FLAGS_FIBER |
8448                                NIU_FLAGS_10G);
8449                 np->mac_xcvr = MAC_XCVR_MII;
8450                 break;
8451
8452         case ESPC_PHY_TYPE_1G_FIBER:
8453                 /* 1G fiber, PCS */
8454                 np->flags &= ~NIU_FLAGS_10G;
8455                 np->flags |= NIU_FLAGS_FIBER;
8456                 np->mac_xcvr = MAC_XCVR_PCS;
8457                 break;
8458
8459         case ESPC_PHY_TYPE_10G_COPPER:
8460                 /* 10G copper, XPCS */
8461                 np->flags |= NIU_FLAGS_10G;
8462                 np->flags &= ~NIU_FLAGS_FIBER;
8463                 np->mac_xcvr = MAC_XCVR_XPCS;
8464                 break;
8465
8466         case ESPC_PHY_TYPE_10G_FIBER:
8467                 /* 10G fiber, XPCS */
8468                 np->flags |= (NIU_FLAGS_10G |
8469                               NIU_FLAGS_FIBER);
8470                 np->mac_xcvr = MAC_XCVR_XPCS;
8471                 break;
8472
8473         default:
8474                 dev_err(np->device, "Bogus SPROM phy type %u\n", val8);
8475                 return -EINVAL;
8476         }
8477
8478         val = nr64(ESPC_MAC_ADDR0);
8479         netif_printk(np, probe, KERN_DEBUG, np->dev,
8480                      "SPROM: MAC_ADDR0[%08llx]\n", (unsigned long long)val);
8481         dev->perm_addr[0] = (val >>  0) & 0xff;
8482         dev->perm_addr[1] = (val >>  8) & 0xff;
8483         dev->perm_addr[2] = (val >> 16) & 0xff;
8484         dev->perm_addr[3] = (val >> 24) & 0xff;
8485
8486         val = nr64(ESPC_MAC_ADDR1);
8487         netif_printk(np, probe, KERN_DEBUG, np->dev,
8488                      "SPROM: MAC_ADDR1[%08llx]\n", (unsigned long long)val);
8489         dev->perm_addr[4] = (val >>  0) & 0xff;
8490         dev->perm_addr[5] = (val >>  8) & 0xff;
8491
8492         if (!is_valid_ether_addr(&dev->perm_addr[0])) {
8493                 dev_err(np->device, "SPROM MAC address invalid [ %pM ]\n",
8494                         dev->perm_addr);
8495                 return -EINVAL;
8496         }
8497
8498         val8 = dev->perm_addr[5];
8499         dev->perm_addr[5] += np->port;
8500         if (dev->perm_addr[5] < val8)
8501                 dev->perm_addr[4]++;
8502
8503         memcpy(dev->dev_addr, dev->perm_addr, dev->addr_len);
8504
8505         val = nr64(ESPC_MOD_STR_LEN);
8506         netif_printk(np, probe, KERN_DEBUG, np->dev,
8507                      "SPROM: MOD_STR_LEN[%llu]\n", (unsigned long long)val);
8508         if (val >= 8 * 4)
8509                 return -EINVAL;
8510
8511         for (i = 0; i < val; i += 4) {
8512                 u64 tmp = nr64(ESPC_NCR(5 + (i / 4)));
8513
8514                 np->vpd.model[i + 3] = (tmp >>  0) & 0xff;
8515                 np->vpd.model[i + 2] = (tmp >>  8) & 0xff;
8516                 np->vpd.model[i + 1] = (tmp >> 16) & 0xff;
8517                 np->vpd.model[i + 0] = (tmp >> 24) & 0xff;
8518         }
8519         np->vpd.model[val] = '\0';
8520
8521         val = nr64(ESPC_BD_MOD_STR_LEN);
8522         netif_printk(np, probe, KERN_DEBUG, np->dev,
8523                      "SPROM: BD_MOD_STR_LEN[%llu]\n", (unsigned long long)val);
8524         if (val >= 4 * 4)
8525                 return -EINVAL;
8526
8527         for (i = 0; i < val; i += 4) {
8528                 u64 tmp = nr64(ESPC_NCR(14 + (i / 4)));
8529
8530                 np->vpd.board_model[i + 3] = (tmp >>  0) & 0xff;
8531                 np->vpd.board_model[i + 2] = (tmp >>  8) & 0xff;
8532                 np->vpd.board_model[i + 1] = (tmp >> 16) & 0xff;
8533                 np->vpd.board_model[i + 0] = (tmp >> 24) & 0xff;
8534         }
8535         np->vpd.board_model[val] = '\0';
8536
8537         np->vpd.mac_num =
8538                 nr64(ESPC_NUM_PORTS_MACS) & ESPC_NUM_PORTS_MACS_VAL;
8539         netif_printk(np, probe, KERN_DEBUG, np->dev,
8540                      "SPROM: NUM_PORTS_MACS[%d]\n", np->vpd.mac_num);
8541
8542         return 0;
8543 }
8544
8545 static int __devinit niu_get_and_validate_port(struct niu *np)
8546 {
8547         struct niu_parent *parent = np->parent;
8548
8549         if (np->port <= 1)
8550                 np->flags |= NIU_FLAGS_XMAC;
8551
8552         if (!parent->num_ports) {
8553                 if (parent->plat_type == PLAT_TYPE_NIU) {
8554                         parent->num_ports = 2;
8555                 } else {
8556                         parent->num_ports = niu_pci_vpd_get_nports(np);
8557                         if (!parent->num_ports) {
8558                                 /* Fall back to SPROM as last resort.
8559                                  * This will fail on most cards.
8560                                  */
8561                                 parent->num_ports = nr64(ESPC_NUM_PORTS_MACS) &
8562                                         ESPC_NUM_PORTS_MACS_VAL;
8563
8564                                 /* All of the current probing methods fail on
8565                                  * Maramba on-board parts.
8566                                  */
8567                                 if (!parent->num_ports)
8568                                         parent->num_ports = 4;
8569                         }
8570                 }
8571         }
8572
8573         if (np->port >= parent->num_ports)
8574                 return -ENODEV;
8575
8576         return 0;
8577 }
8578
8579 static int __devinit phy_record(struct niu_parent *parent,
8580                                 struct phy_probe_info *p,
8581                                 int dev_id_1, int dev_id_2, u8 phy_port,
8582                                 int type)
8583 {
8584         u32 id = (dev_id_1 << 16) | dev_id_2;
8585         u8 idx;
8586
8587         if (dev_id_1 < 0 || dev_id_2 < 0)
8588                 return 0;
8589         if (type == PHY_TYPE_PMA_PMD || type == PHY_TYPE_PCS) {
8590                 if (((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM8704) &&
8591                     ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_MRVL88X2011) &&
8592                     ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM8706))
8593                         return 0;
8594         } else {
8595                 if ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM5464R)
8596                         return 0;
8597         }
8598
8599         pr_info("niu%d: Found PHY %08x type %s at phy_port %u\n",
8600                 parent->index, id,
8601                 type == PHY_TYPE_PMA_PMD ? "PMA/PMD" :
8602                 type == PHY_TYPE_PCS ? "PCS" : "MII",
8603                 phy_port);
8604
8605         if (p->cur[type] >= NIU_MAX_PORTS) {
8606                 pr_err("Too many PHY ports\n");
8607                 return -EINVAL;
8608         }
8609         idx = p->cur[type];
8610         p->phy_id[type][idx] = id;
8611         p->phy_port[type][idx] = phy_port;
8612         p->cur[type] = idx + 1;
8613         return 0;
8614 }
8615
8616 static int __devinit port_has_10g(struct phy_probe_info *p, int port)
8617 {
8618         int i;
8619
8620         for (i = 0; i < p->cur[PHY_TYPE_PMA_PMD]; i++) {
8621                 if (p->phy_port[PHY_TYPE_PMA_PMD][i] == port)
8622                         return 1;
8623         }
8624         for (i = 0; i < p->cur[PHY_TYPE_PCS]; i++) {
8625                 if (p->phy_port[PHY_TYPE_PCS][i] == port)
8626                         return 1;
8627         }
8628
8629         return 0;
8630 }
8631
8632 static int __devinit count_10g_ports(struct phy_probe_info *p, int *lowest)
8633 {
8634         int port, cnt;
8635
8636         cnt = 0;
8637         *lowest = 32;
8638         for (port = 8; port < 32; port++) {
8639                 if (port_has_10g(p, port)) {
8640                         if (!cnt)
8641                                 *lowest = port;
8642                         cnt++;
8643                 }
8644         }
8645
8646         return cnt;
8647 }
8648
8649 static int __devinit count_1g_ports(struct phy_probe_info *p, int *lowest)
8650 {
8651         *lowest = 32;
8652         if (p->cur[PHY_TYPE_MII])
8653                 *lowest = p->phy_port[PHY_TYPE_MII][0];
8654
8655         return p->cur[PHY_TYPE_MII];
8656 }
8657
8658 static void __devinit niu_n2_divide_channels(struct niu_parent *parent)
8659 {
8660         int num_ports = parent->num_ports;
8661         int i;
8662
8663         for (i = 0; i < num_ports; i++) {
8664                 parent->rxchan_per_port[i] = (16 / num_ports);
8665                 parent->txchan_per_port[i] = (16 / num_ports);
8666
8667                 pr_info("niu%d: Port %u [%u RX chans] [%u TX chans]\n",
8668                         parent->index, i,
8669                         parent->rxchan_per_port[i],
8670                         parent->txchan_per_port[i]);
8671         }
8672 }
8673
8674 static void __devinit niu_divide_channels(struct niu_parent *parent,
8675                                           int num_10g, int num_1g)
8676 {
8677         int num_ports = parent->num_ports;
8678         int rx_chans_per_10g, rx_chans_per_1g;
8679         int tx_chans_per_10g, tx_chans_per_1g;
8680         int i, tot_rx, tot_tx;
8681
8682         if (!num_10g || !num_1g) {
8683                 rx_chans_per_10g = rx_chans_per_1g =
8684                         (NIU_NUM_RXCHAN / num_ports);
8685                 tx_chans_per_10g = tx_chans_per_1g =
8686                         (NIU_NUM_TXCHAN / num_ports);
8687         } else {
8688                 rx_chans_per_1g = NIU_NUM_RXCHAN / 8;
8689                 rx_chans_per_10g = (NIU_NUM_RXCHAN -
8690                                     (rx_chans_per_1g * num_1g)) /
8691                         num_10g;
8692
8693                 tx_chans_per_1g = NIU_NUM_TXCHAN / 6;
8694                 tx_chans_per_10g = (NIU_NUM_TXCHAN -
8695                                     (tx_chans_per_1g * num_1g)) /
8696                         num_10g;
8697         }
8698
8699         tot_rx = tot_tx = 0;
8700         for (i = 0; i < num_ports; i++) {
8701                 int type = phy_decode(parent->port_phy, i);
8702
8703                 if (type == PORT_TYPE_10G) {
8704                         parent->rxchan_per_port[i] = rx_chans_per_10g;
8705                         parent->txchan_per_port[i] = tx_chans_per_10g;
8706                 } else {
8707                         parent->rxchan_per_port[i] = rx_chans_per_1g;
8708                         parent->txchan_per_port[i] = tx_chans_per_1g;
8709                 }
8710                 pr_info("niu%d: Port %u [%u RX chans] [%u TX chans]\n",
8711                         parent->index, i,
8712                         parent->rxchan_per_port[i],
8713                         parent->txchan_per_port[i]);
8714                 tot_rx += parent->rxchan_per_port[i];
8715                 tot_tx += parent->txchan_per_port[i];
8716         }
8717
8718         if (tot_rx > NIU_NUM_RXCHAN) {
8719                 pr_err("niu%d: Too many RX channels (%d), resetting to one per port\n",
8720                        parent->index, tot_rx);
8721                 for (i = 0; i < num_ports; i++)
8722                         parent->rxchan_per_port[i] = 1;
8723         }
8724         if (tot_tx > NIU_NUM_TXCHAN) {
8725                 pr_err("niu%d: Too many TX channels (%d), resetting to one per port\n",
8726                        parent->index, tot_tx);
8727                 for (i = 0; i < num_ports; i++)
8728                         parent->txchan_per_port[i] = 1;
8729         }
8730         if (tot_rx < NIU_NUM_RXCHAN || tot_tx < NIU_NUM_TXCHAN) {
8731                 pr_warning("niu%d: Driver bug, wasted channels, RX[%d] TX[%d]\n",
8732                            parent->index, tot_rx, tot_tx);
8733         }
8734 }
8735
8736 static void __devinit niu_divide_rdc_groups(struct niu_parent *parent,
8737                                             int num_10g, int num_1g)
8738 {
8739         int i, num_ports = parent->num_ports;
8740         int rdc_group, rdc_groups_per_port;
8741         int rdc_channel_base;
8742
8743         rdc_group = 0;
8744         rdc_groups_per_port = NIU_NUM_RDC_TABLES / num_ports;
8745
8746         rdc_channel_base = 0;
8747
8748         for (i = 0; i < num_ports; i++) {
8749                 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[i];
8750                 int grp, num_channels = parent->rxchan_per_port[i];
8751                 int this_channel_offset;
8752
8753                 tp->first_table_num = rdc_group;
8754                 tp->num_tables = rdc_groups_per_port;
8755                 this_channel_offset = 0;
8756                 for (grp = 0; grp < tp->num_tables; grp++) {
8757                         struct rdc_table *rt = &tp->tables[grp];
8758                         int slot;
8759
8760                         pr_info("niu%d: Port %d RDC tbl(%d) [ ",
8761                                 parent->index, i, tp->first_table_num + grp);
8762                         for (slot = 0; slot < NIU_RDC_TABLE_SLOTS; slot++) {
8763                                 rt->rxdma_channel[slot] =
8764                                         rdc_channel_base + this_channel_offset;
8765
8766                                 pr_cont("%d ", rt->rxdma_channel[slot]);
8767
8768                                 if (++this_channel_offset == num_channels)
8769                                         this_channel_offset = 0;
8770                         }
8771                         pr_cont("]\n");
8772                 }
8773
8774                 parent->rdc_default[i] = rdc_channel_base;
8775
8776                 rdc_channel_base += num_channels;
8777                 rdc_group += rdc_groups_per_port;
8778         }
8779 }
8780
8781 static int __devinit fill_phy_probe_info(struct niu *np,
8782                                          struct niu_parent *parent,
8783                                          struct phy_probe_info *info)
8784 {
8785         unsigned long flags;
8786         int port, err;
8787
8788         memset(info, 0, sizeof(*info));
8789
8790         /* Port 0 to 7 are reserved for onboard Serdes, probe the rest.  */
8791         niu_lock_parent(np, flags);
8792         err = 0;
8793         for (port = 8; port < 32; port++) {
8794                 int dev_id_1, dev_id_2;
8795
8796                 dev_id_1 = mdio_read(np, port,
8797                                      NIU_PMA_PMD_DEV_ADDR, MII_PHYSID1);
8798                 dev_id_2 = mdio_read(np, port,
8799                                      NIU_PMA_PMD_DEV_ADDR, MII_PHYSID2);
8800                 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
8801                                  PHY_TYPE_PMA_PMD);
8802                 if (err)
8803                         break;
8804                 dev_id_1 = mdio_read(np, port,
8805                                      NIU_PCS_DEV_ADDR, MII_PHYSID1);
8806                 dev_id_2 = mdio_read(np, port,
8807                                      NIU_PCS_DEV_ADDR, MII_PHYSID2);
8808                 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
8809                                  PHY_TYPE_PCS);
8810                 if (err)
8811                         break;
8812                 dev_id_1 = mii_read(np, port, MII_PHYSID1);
8813                 dev_id_2 = mii_read(np, port, MII_PHYSID2);
8814                 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
8815                                  PHY_TYPE_MII);
8816                 if (err)
8817                         break;
8818         }
8819         niu_unlock_parent(np, flags);
8820
8821         return err;
8822 }
8823
8824 static int __devinit walk_phys(struct niu *np, struct niu_parent *parent)
8825 {
8826         struct phy_probe_info *info = &parent->phy_probe_info;
8827         int lowest_10g, lowest_1g;
8828         int num_10g, num_1g;
8829         u32 val;
8830         int err;
8831
8832         num_10g = num_1g = 0;
8833
8834         if (!strcmp(np->vpd.model, NIU_ALONSO_MDL_STR) ||
8835             !strcmp(np->vpd.model, NIU_KIMI_MDL_STR)) {
8836                 num_10g = 0;
8837                 num_1g = 2;
8838                 parent->plat_type = PLAT_TYPE_ATCA_CP3220;
8839                 parent->num_ports = 4;
8840                 val = (phy_encode(PORT_TYPE_1G, 0) |
8841                        phy_encode(PORT_TYPE_1G, 1) |
8842                        phy_encode(PORT_TYPE_1G, 2) |
8843                        phy_encode(PORT_TYPE_1G, 3));
8844         } else if (!strcmp(np->vpd.model, NIU_FOXXY_MDL_STR)) {
8845                 num_10g = 2;
8846                 num_1g = 0;
8847                 parent->num_ports = 2;
8848                 val = (phy_encode(PORT_TYPE_10G, 0) |
8849                        phy_encode(PORT_TYPE_10G, 1));
8850         } else if ((np->flags & NIU_FLAGS_XCVR_SERDES) &&
8851                    (parent->plat_type == PLAT_TYPE_NIU)) {
8852                 /* this is the Monza case */
8853                 if (np->flags & NIU_FLAGS_10G) {
8854                         val = (phy_encode(PORT_TYPE_10G, 0) |
8855                                phy_encode(PORT_TYPE_10G, 1));
8856                 } else {
8857                         val = (phy_encode(PORT_TYPE_1G, 0) |
8858                                phy_encode(PORT_TYPE_1G, 1));
8859                 }
8860         } else {
8861                 err = fill_phy_probe_info(np, parent, info);
8862                 if (err)
8863                         return err;
8864
8865                 num_10g = count_10g_ports(info, &lowest_10g);
8866                 num_1g = count_1g_ports(info, &lowest_1g);
8867
8868                 switch ((num_10g << 4) | num_1g) {
8869                 case 0x24:
8870                         if (lowest_1g == 10)
8871                                 parent->plat_type = PLAT_TYPE_VF_P0;
8872                         else if (lowest_1g == 26)
8873                                 parent->plat_type = PLAT_TYPE_VF_P1;
8874                         else
8875                                 goto unknown_vg_1g_port;
8876
8877                         /* fallthru */
8878                 case 0x22:
8879                         val = (phy_encode(PORT_TYPE_10G, 0) |
8880                                phy_encode(PORT_TYPE_10G, 1) |
8881                                phy_encode(PORT_TYPE_1G, 2) |
8882                                phy_encode(PORT_TYPE_1G, 3));
8883                         break;
8884
8885                 case 0x20:
8886                         val = (phy_encode(PORT_TYPE_10G, 0) |
8887                                phy_encode(PORT_TYPE_10G, 1));
8888                         break;
8889
8890                 case 0x10:
8891                         val = phy_encode(PORT_TYPE_10G, np->port);
8892                         break;
8893
8894                 case 0x14:
8895                         if (lowest_1g == 10)
8896                                 parent->plat_type = PLAT_TYPE_VF_P0;
8897                         else if (lowest_1g == 26)
8898                                 parent->plat_type = PLAT_TYPE_VF_P1;
8899                         else
8900                                 goto unknown_vg_1g_port;
8901
8902                         /* fallthru */
8903                 case 0x13:
8904                         if ((lowest_10g & 0x7) == 0)
8905                                 val = (phy_encode(PORT_TYPE_10G, 0) |
8906                                        phy_encode(PORT_TYPE_1G, 1) |
8907                                        phy_encode(PORT_TYPE_1G, 2) |
8908                                        phy_encode(PORT_TYPE_1G, 3));
8909                         else
8910                                 val = (phy_encode(PORT_TYPE_1G, 0) |
8911                                        phy_encode(PORT_TYPE_10G, 1) |
8912                                        phy_encode(PORT_TYPE_1G, 2) |
8913                                        phy_encode(PORT_TYPE_1G, 3));
8914                         break;
8915
8916                 case 0x04:
8917                         if (lowest_1g == 10)
8918                                 parent->plat_type = PLAT_TYPE_VF_P0;
8919                         else if (lowest_1g == 26)
8920                                 parent->plat_type = PLAT_TYPE_VF_P1;
8921                         else
8922                                 goto unknown_vg_1g_port;
8923
8924                         val = (phy_encode(PORT_TYPE_1G, 0) |
8925                                phy_encode(PORT_TYPE_1G, 1) |
8926                                phy_encode(PORT_TYPE_1G, 2) |
8927                                phy_encode(PORT_TYPE_1G, 3));
8928                         break;
8929
8930                 default:
8931                         pr_err("Unsupported port config 10G[%d] 1G[%d]\n",
8932                                num_10g, num_1g);
8933                         return -EINVAL;
8934                 }
8935         }
8936
8937         parent->port_phy = val;
8938
8939         if (parent->plat_type == PLAT_TYPE_NIU)
8940                 niu_n2_divide_channels(parent);
8941         else
8942                 niu_divide_channels(parent, num_10g, num_1g);
8943
8944         niu_divide_rdc_groups(parent, num_10g, num_1g);
8945
8946         return 0;
8947
8948 unknown_vg_1g_port:
8949         pr_err("Cannot identify platform type, 1gport=%d\n", lowest_1g);
8950         return -EINVAL;
8951 }
8952
8953 static int __devinit niu_probe_ports(struct niu *np)
8954 {
8955         struct niu_parent *parent = np->parent;
8956         int err, i;
8957
8958         if (parent->port_phy == PORT_PHY_UNKNOWN) {
8959                 err = walk_phys(np, parent);
8960                 if (err)
8961                         return err;
8962
8963                 niu_set_ldg_timer_res(np, 2);
8964                 for (i = 0; i <= LDN_MAX; i++)
8965                         niu_ldn_irq_enable(np, i, 0);
8966         }
8967
8968         if (parent->port_phy == PORT_PHY_INVALID)
8969                 return -EINVAL;
8970
8971         return 0;
8972 }
8973
8974 static int __devinit niu_classifier_swstate_init(struct niu *np)
8975 {
8976         struct niu_classifier *cp = &np->clas;
8977
8978         cp->tcam_top = (u16) np->port;
8979         cp->tcam_sz = np->parent->tcam_num_entries / np->parent->num_ports;
8980         cp->h1_init = 0xffffffff;
8981         cp->h2_init = 0xffff;
8982
8983         return fflp_early_init(np);
8984 }
8985
8986 static void __devinit niu_link_config_init(struct niu *np)
8987 {
8988         struct niu_link_config *lp = &np->link_config;
8989
8990         lp->advertising = (ADVERTISED_10baseT_Half |
8991                            ADVERTISED_10baseT_Full |
8992                            ADVERTISED_100baseT_Half |
8993                            ADVERTISED_100baseT_Full |
8994                            ADVERTISED_1000baseT_Half |
8995                            ADVERTISED_1000baseT_Full |
8996                            ADVERTISED_10000baseT_Full |
8997                            ADVERTISED_Autoneg);
8998         lp->speed = lp->active_speed = SPEED_INVALID;
8999         lp->duplex = DUPLEX_FULL;
9000         lp->active_duplex = DUPLEX_INVALID;
9001         lp->autoneg = 1;
9002 #if 0
9003         lp->loopback_mode = LOOPBACK_MAC;
9004         lp->active_speed = SPEED_10000;
9005         lp->active_duplex = DUPLEX_FULL;
9006 #else
9007         lp->loopback_mode = LOOPBACK_DISABLED;
9008 #endif
9009 }
9010
9011 static int __devinit niu_init_mac_ipp_pcs_base(struct niu *np)
9012 {
9013         switch (np->port) {
9014         case 0:
9015                 np->mac_regs = np->regs + XMAC_PORT0_OFF;
9016                 np->ipp_off  = 0x00000;
9017                 np->pcs_off  = 0x04000;
9018                 np->xpcs_off = 0x02000;
9019                 break;
9020
9021         case 1:
9022                 np->mac_regs = np->regs + XMAC_PORT1_OFF;
9023                 np->ipp_off  = 0x08000;
9024                 np->pcs_off  = 0x0a000;
9025                 np->xpcs_off = 0x08000;
9026                 break;
9027
9028         case 2:
9029                 np->mac_regs = np->regs + BMAC_PORT2_OFF;
9030                 np->ipp_off  = 0x04000;
9031                 np->pcs_off  = 0x0e000;
9032                 np->xpcs_off = ~0UL;
9033                 break;
9034
9035         case 3:
9036                 np->mac_regs = np->regs + BMAC_PORT3_OFF;
9037                 np->ipp_off  = 0x0c000;
9038                 np->pcs_off  = 0x12000;
9039                 np->xpcs_off = ~0UL;
9040                 break;
9041
9042         default:
9043                 dev_err(np->device, "Port %u is invalid, cannot compute MAC block offset\n", np->port);
9044                 return -EINVAL;
9045         }
9046
9047         return 0;
9048 }
9049
9050 static void __devinit niu_try_msix(struct niu *np, u8 *ldg_num_map)
9051 {
9052         struct msix_entry msi_vec[NIU_NUM_LDG];
9053         struct niu_parent *parent = np->parent;
9054         struct pci_dev *pdev = np->pdev;
9055         int i, num_irqs, err;
9056         u8 first_ldg;
9057
9058         first_ldg = (NIU_NUM_LDG / parent->num_ports) * np->port;
9059         for (i = 0; i < (NIU_NUM_LDG / parent->num_ports); i++)
9060                 ldg_num_map[i] = first_ldg + i;
9061
9062         num_irqs = (parent->rxchan_per_port[np->port] +
9063                     parent->txchan_per_port[np->port] +
9064                     (np->port == 0 ? 3 : 1));
9065         BUG_ON(num_irqs > (NIU_NUM_LDG / parent->num_ports));
9066
9067 retry:
9068         for (i = 0; i < num_irqs; i++) {
9069                 msi_vec[i].vector = 0;
9070                 msi_vec[i].entry = i;
9071         }
9072
9073         err = pci_enable_msix(pdev, msi_vec, num_irqs);
9074         if (err < 0) {
9075                 np->flags &= ~NIU_FLAGS_MSIX;
9076                 return;
9077         }
9078         if (err > 0) {
9079                 num_irqs = err;
9080                 goto retry;
9081         }
9082
9083         np->flags |= NIU_FLAGS_MSIX;
9084         for (i = 0; i < num_irqs; i++)
9085                 np->ldg[i].irq = msi_vec[i].vector;
9086         np->num_ldg = num_irqs;
9087 }
9088
9089 static int __devinit niu_n2_irq_init(struct niu *np, u8 *ldg_num_map)
9090 {
9091 #ifdef CONFIG_SPARC64
9092         struct of_device *op = np->op;
9093         const u32 *int_prop;
9094         int i;
9095
9096         int_prop = of_get_property(op->node, "interrupts", NULL);
9097         if (!int_prop)
9098                 return -ENODEV;
9099
9100         for (i = 0; i < op->num_irqs; i++) {
9101                 ldg_num_map[i] = int_prop[i];
9102                 np->ldg[i].irq = op->irqs[i];
9103         }
9104
9105         np->num_ldg = op->num_irqs;
9106
9107         return 0;
9108 #else
9109         return -EINVAL;
9110 #endif
9111 }
9112
9113 static int __devinit niu_ldg_init(struct niu *np)
9114 {
9115         struct niu_parent *parent = np->parent;
9116         u8 ldg_num_map[NIU_NUM_LDG];
9117         int first_chan, num_chan;
9118         int i, err, ldg_rotor;
9119         u8 port;
9120
9121         np->num_ldg = 1;
9122         np->ldg[0].irq = np->dev->irq;
9123         if (parent->plat_type == PLAT_TYPE_NIU) {
9124                 err = niu_n2_irq_init(np, ldg_num_map);
9125                 if (err)
9126                         return err;
9127         } else
9128                 niu_try_msix(np, ldg_num_map);
9129
9130         port = np->port;
9131         for (i = 0; i < np->num_ldg; i++) {
9132                 struct niu_ldg *lp = &np->ldg[i];
9133
9134                 netif_napi_add(np->dev, &lp->napi, niu_poll, 64);
9135
9136                 lp->np = np;
9137                 lp->ldg_num = ldg_num_map[i];
9138                 lp->timer = 2; /* XXX */
9139
9140                 /* On N2 NIU the firmware has setup the SID mappings so they go
9141                  * to the correct values that will route the LDG to the proper
9142                  * interrupt in the NCU interrupt table.
9143                  */
9144                 if (np->parent->plat_type != PLAT_TYPE_NIU) {
9145                         err = niu_set_ldg_sid(np, lp->ldg_num, port, i);
9146                         if (err)
9147                                 return err;
9148                 }
9149         }
9150
9151         /* We adopt the LDG assignment ordering used by the N2 NIU
9152          * 'interrupt' properties because that simplifies a lot of
9153          * things.  This ordering is:
9154          *
9155          *      MAC
9156          *      MIF     (if port zero)
9157          *      SYSERR  (if port zero)
9158          *      RX channels
9159          *      TX channels
9160          */
9161
9162         ldg_rotor = 0;
9163
9164         err = niu_ldg_assign_ldn(np, parent, ldg_num_map[ldg_rotor],
9165                                   LDN_MAC(port));
9166         if (err)
9167                 return err;
9168
9169         ldg_rotor++;
9170         if (ldg_rotor == np->num_ldg)
9171                 ldg_rotor = 0;
9172
9173         if (port == 0) {
9174                 err = niu_ldg_assign_ldn(np, parent,
9175                                          ldg_num_map[ldg_rotor],
9176                                          LDN_MIF);
9177                 if (err)
9178                         return err;
9179
9180                 ldg_rotor++;
9181                 if (ldg_rotor == np->num_ldg)
9182                         ldg_rotor = 0;
9183
9184                 err = niu_ldg_assign_ldn(np, parent,
9185                                          ldg_num_map[ldg_rotor],
9186                                          LDN_DEVICE_ERROR);
9187                 if (err)
9188                         return err;
9189
9190                 ldg_rotor++;
9191                 if (ldg_rotor == np->num_ldg)
9192                         ldg_rotor = 0;
9193
9194         }
9195
9196         first_chan = 0;
9197         for (i = 0; i < port; i++)
9198                 first_chan += parent->rxchan_per_port[port];
9199         num_chan = parent->rxchan_per_port[port];
9200
9201         for (i = first_chan; i < (first_chan + num_chan); i++) {
9202                 err = niu_ldg_assign_ldn(np, parent,
9203                                          ldg_num_map[ldg_rotor],
9204                                          LDN_RXDMA(i));
9205                 if (err)
9206                         return err;
9207                 ldg_rotor++;
9208                 if (ldg_rotor == np->num_ldg)
9209                         ldg_rotor = 0;
9210         }
9211
9212         first_chan = 0;
9213         for (i = 0; i < port; i++)
9214                 first_chan += parent->txchan_per_port[port];
9215         num_chan = parent->txchan_per_port[port];
9216         for (i = first_chan; i < (first_chan + num_chan); i++) {
9217                 err = niu_ldg_assign_ldn(np, parent,
9218                                          ldg_num_map[ldg_rotor],
9219                                          LDN_TXDMA(i));
9220                 if (err)
9221                         return err;
9222                 ldg_rotor++;
9223                 if (ldg_rotor == np->num_ldg)
9224                         ldg_rotor = 0;
9225         }
9226
9227         return 0;
9228 }
9229
9230 static void __devexit niu_ldg_free(struct niu *np)
9231 {
9232         if (np->flags & NIU_FLAGS_MSIX)
9233                 pci_disable_msix(np->pdev);
9234 }
9235
9236 static int __devinit niu_get_of_props(struct niu *np)
9237 {
9238 #ifdef CONFIG_SPARC64
9239         struct net_device *dev = np->dev;
9240         struct device_node *dp;
9241         const char *phy_type;
9242         const u8 *mac_addr;
9243         const char *model;
9244         int prop_len;
9245
9246         if (np->parent->plat_type == PLAT_TYPE_NIU)
9247                 dp = np->op->node;
9248         else
9249                 dp = pci_device_to_OF_node(np->pdev);
9250
9251         phy_type = of_get_property(dp, "phy-type", &prop_len);
9252         if (!phy_type) {
9253                 netdev_err(dev, "%s: OF node lacks phy-type property\n",
9254                            dp->full_name);
9255                 return -EINVAL;
9256         }
9257
9258         if (!strcmp(phy_type, "none"))
9259                 return -ENODEV;
9260
9261         strcpy(np->vpd.phy_type, phy_type);
9262
9263         if (niu_phy_type_prop_decode(np, np->vpd.phy_type)) {
9264                 netdev_err(dev, "%s: Illegal phy string [%s]\n",
9265                            dp->full_name, np->vpd.phy_type);
9266                 return -EINVAL;
9267         }
9268
9269         mac_addr = of_get_property(dp, "local-mac-address", &prop_len);
9270         if (!mac_addr) {
9271                 netdev_err(dev, "%s: OF node lacks local-mac-address property\n",
9272                            dp->full_name);
9273                 return -EINVAL;
9274         }
9275         if (prop_len != dev->addr_len) {
9276                 netdev_err(dev, "%s: OF MAC address prop len (%d) is wrong\n",
9277                            dp->full_name, prop_len);
9278         }
9279         memcpy(dev->perm_addr, mac_addr, dev->addr_len);
9280         if (!is_valid_ether_addr(&dev->perm_addr[0])) {
9281                 netdev_err(dev, "%s: OF MAC address is invalid\n",
9282                            dp->full_name);
9283                 netdev_err(dev, "%s: [ %pM ]\n", dp->full_name, dev->perm_addr);
9284                 return -EINVAL;
9285         }
9286
9287         memcpy(dev->dev_addr, dev->perm_addr, dev->addr_len);
9288
9289         model = of_get_property(dp, "model", &prop_len);
9290
9291         if (model)
9292                 strcpy(np->vpd.model, model);
9293
9294         if (of_find_property(dp, "hot-swappable-phy", &prop_len)) {
9295                 np->flags |= (NIU_FLAGS_10G | NIU_FLAGS_FIBER |
9296                         NIU_FLAGS_HOTPLUG_PHY);
9297         }
9298
9299         return 0;
9300 #else
9301         return -EINVAL;
9302 #endif
9303 }
9304
9305 static int __devinit niu_get_invariants(struct niu *np)
9306 {
9307         int err, have_props;
9308         u32 offset;
9309
9310         err = niu_get_of_props(np);
9311         if (err == -ENODEV)
9312                 return err;
9313
9314         have_props = !err;
9315
9316         err = niu_init_mac_ipp_pcs_base(np);
9317         if (err)
9318                 return err;
9319
9320         if (have_props) {
9321                 err = niu_get_and_validate_port(np);
9322                 if (err)
9323                         return err;
9324
9325         } else  {
9326                 if (np->parent->plat_type == PLAT_TYPE_NIU)
9327                         return -EINVAL;
9328
9329                 nw64(ESPC_PIO_EN, ESPC_PIO_EN_ENABLE);
9330                 offset = niu_pci_vpd_offset(np);
9331                 netif_printk(np, probe, KERN_DEBUG, np->dev,
9332                              "%s() VPD offset [%08x]\n", __func__, offset);
9333                 if (offset)
9334                         niu_pci_vpd_fetch(np, offset);
9335                 nw64(ESPC_PIO_EN, 0);
9336
9337                 if (np->flags & NIU_FLAGS_VPD_VALID) {
9338                         niu_pci_vpd_validate(np);
9339                         err = niu_get_and_validate_port(np);
9340                         if (err)
9341                                 return err;
9342                 }
9343
9344                 if (!(np->flags & NIU_FLAGS_VPD_VALID)) {
9345                         err = niu_get_and_validate_port(np);
9346                         if (err)
9347                                 return err;
9348                         err = niu_pci_probe_sprom(np);
9349                         if (err)
9350                                 return err;
9351                 }
9352         }
9353
9354         err = niu_probe_ports(np);
9355         if (err)
9356                 return err;
9357
9358         niu_ldg_init(np);
9359
9360         niu_classifier_swstate_init(np);
9361         niu_link_config_init(np);
9362
9363         err = niu_determine_phy_disposition(np);
9364         if (!err)
9365                 err = niu_init_link(np);
9366
9367         return err;
9368 }
9369
9370 static LIST_HEAD(niu_parent_list);
9371 static DEFINE_MUTEX(niu_parent_lock);
9372 static int niu_parent_index;
9373
9374 static ssize_t show_port_phy(struct device *dev,
9375                              struct device_attribute *attr, char *buf)
9376 {
9377         struct platform_device *plat_dev = to_platform_device(dev);
9378         struct niu_parent *p = plat_dev->dev.platform_data;
9379         u32 port_phy = p->port_phy;
9380         char *orig_buf = buf;
9381         int i;
9382
9383         if (port_phy == PORT_PHY_UNKNOWN ||
9384             port_phy == PORT_PHY_INVALID)
9385                 return 0;
9386
9387         for (i = 0; i < p->num_ports; i++) {
9388                 const char *type_str;
9389                 int type;
9390
9391                 type = phy_decode(port_phy, i);
9392                 if (type == PORT_TYPE_10G)
9393                         type_str = "10G";
9394                 else
9395                         type_str = "1G";
9396                 buf += sprintf(buf,
9397                                (i == 0) ? "%s" : " %s",
9398                                type_str);
9399         }
9400         buf += sprintf(buf, "\n");
9401         return buf - orig_buf;
9402 }
9403
9404 static ssize_t show_plat_type(struct device *dev,
9405                               struct device_attribute *attr, char *buf)
9406 {
9407         struct platform_device *plat_dev = to_platform_device(dev);
9408         struct niu_parent *p = plat_dev->dev.platform_data;
9409         const char *type_str;
9410
9411         switch (p->plat_type) {
9412         case PLAT_TYPE_ATLAS:
9413                 type_str = "atlas";
9414                 break;
9415         case PLAT_TYPE_NIU:
9416                 type_str = "niu";
9417                 break;
9418         case PLAT_TYPE_VF_P0:
9419                 type_str = "vf_p0";
9420                 break;
9421         case PLAT_TYPE_VF_P1:
9422                 type_str = "vf_p1";
9423                 break;
9424         default:
9425                 type_str = "unknown";
9426                 break;
9427         }
9428
9429         return sprintf(buf, "%s\n", type_str);
9430 }
9431
9432 static ssize_t __show_chan_per_port(struct device *dev,
9433                                     struct device_attribute *attr, char *buf,
9434                                     int rx)
9435 {
9436         struct platform_device *plat_dev = to_platform_device(dev);
9437         struct niu_parent *p = plat_dev->dev.platform_data;
9438         char *orig_buf = buf;
9439         u8 *arr;
9440         int i;
9441
9442         arr = (rx ? p->rxchan_per_port : p->txchan_per_port);
9443
9444         for (i = 0; i < p->num_ports; i++) {
9445                 buf += sprintf(buf,
9446                                (i == 0) ? "%d" : " %d",
9447                                arr[i]);
9448         }
9449         buf += sprintf(buf, "\n");
9450
9451         return buf - orig_buf;
9452 }
9453
9454 static ssize_t show_rxchan_per_port(struct device *dev,
9455                                     struct device_attribute *attr, char *buf)
9456 {
9457         return __show_chan_per_port(dev, attr, buf, 1);
9458 }
9459
9460 static ssize_t show_txchan_per_port(struct device *dev,
9461                                     struct device_attribute *attr, char *buf)
9462 {
9463         return __show_chan_per_port(dev, attr, buf, 1);
9464 }
9465
9466 static ssize_t show_num_ports(struct device *dev,
9467                               struct device_attribute *attr, char *buf)
9468 {
9469         struct platform_device *plat_dev = to_platform_device(dev);
9470         struct niu_parent *p = plat_dev->dev.platform_data;
9471
9472         return sprintf(buf, "%d\n", p->num_ports);
9473 }
9474
9475 static struct device_attribute niu_parent_attributes[] = {
9476         __ATTR(port_phy, S_IRUGO, show_port_phy, NULL),
9477         __ATTR(plat_type, S_IRUGO, show_plat_type, NULL),
9478         __ATTR(rxchan_per_port, S_IRUGO, show_rxchan_per_port, NULL),
9479         __ATTR(txchan_per_port, S_IRUGO, show_txchan_per_port, NULL),
9480         __ATTR(num_ports, S_IRUGO, show_num_ports, NULL),
9481         {}
9482 };
9483
9484 static struct niu_parent * __devinit niu_new_parent(struct niu *np,
9485                                                     union niu_parent_id *id,
9486                                                     u8 ptype)
9487 {
9488         struct platform_device *plat_dev;
9489         struct niu_parent *p;
9490         int i;
9491
9492         plat_dev = platform_device_register_simple("niu", niu_parent_index,
9493                                                    NULL, 0);
9494         if (IS_ERR(plat_dev))
9495                 return NULL;
9496
9497         for (i = 0; attr_name(niu_parent_attributes[i]); i++) {
9498                 int err = device_create_file(&plat_dev->dev,
9499                                              &niu_parent_attributes[i]);
9500                 if (err)
9501                         goto fail_unregister;
9502         }
9503
9504         p = kzalloc(sizeof(*p), GFP_KERNEL);
9505         if (!p)
9506                 goto fail_unregister;
9507
9508         p->index = niu_parent_index++;
9509
9510         plat_dev->dev.platform_data = p;
9511         p->plat_dev = plat_dev;
9512
9513         memcpy(&p->id, id, sizeof(*id));
9514         p->plat_type = ptype;
9515         INIT_LIST_HEAD(&p->list);
9516         atomic_set(&p->refcnt, 0);
9517         list_add(&p->list, &niu_parent_list);
9518         spin_lock_init(&p->lock);
9519
9520         p->rxdma_clock_divider = 7500;
9521
9522         p->tcam_num_entries = NIU_PCI_TCAM_ENTRIES;
9523         if (p->plat_type == PLAT_TYPE_NIU)
9524                 p->tcam_num_entries = NIU_NONPCI_TCAM_ENTRIES;
9525
9526         for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_SCTP_IPV6; i++) {
9527                 int index = i - CLASS_CODE_USER_PROG1;
9528
9529                 p->tcam_key[index] = TCAM_KEY_TSEL;
9530                 p->flow_key[index] = (FLOW_KEY_IPSA |
9531                                       FLOW_KEY_IPDA |
9532                                       FLOW_KEY_PROTO |
9533                                       (FLOW_KEY_L4_BYTE12 <<
9534                                        FLOW_KEY_L4_0_SHIFT) |
9535                                       (FLOW_KEY_L4_BYTE12 <<
9536                                        FLOW_KEY_L4_1_SHIFT));
9537         }
9538
9539         for (i = 0; i < LDN_MAX + 1; i++)
9540                 p->ldg_map[i] = LDG_INVALID;
9541
9542         return p;
9543
9544 fail_unregister:
9545         platform_device_unregister(plat_dev);
9546         return NULL;
9547 }
9548
9549 static struct niu_parent * __devinit niu_get_parent(struct niu *np,
9550                                                     union niu_parent_id *id,
9551                                                     u8 ptype)
9552 {
9553         struct niu_parent *p, *tmp;
9554         int port = np->port;
9555
9556         mutex_lock(&niu_parent_lock);
9557         p = NULL;
9558         list_for_each_entry(tmp, &niu_parent_list, list) {
9559                 if (!memcmp(id, &tmp->id, sizeof(*id))) {
9560                         p = tmp;
9561                         break;
9562                 }
9563         }
9564         if (!p)
9565                 p = niu_new_parent(np, id, ptype);
9566
9567         if (p) {
9568                 char port_name[6];
9569                 int err;
9570
9571                 sprintf(port_name, "port%d", port);
9572                 err = sysfs_create_link(&p->plat_dev->dev.kobj,
9573                                         &np->device->kobj,
9574                                         port_name);
9575                 if (!err) {
9576                         p->ports[port] = np;
9577                         atomic_inc(&p->refcnt);
9578                 }
9579         }
9580         mutex_unlock(&niu_parent_lock);
9581
9582         return p;
9583 }
9584
9585 static void niu_put_parent(struct niu *np)
9586 {
9587         struct niu_parent *p = np->parent;
9588         u8 port = np->port;
9589         char port_name[6];
9590
9591         BUG_ON(!p || p->ports[port] != np);
9592
9593         netif_printk(np, probe, KERN_DEBUG, np->dev,
9594                      "%s() port[%u]\n", __func__, port);
9595
9596         sprintf(port_name, "port%d", port);
9597
9598         mutex_lock(&niu_parent_lock);
9599
9600         sysfs_remove_link(&p->plat_dev->dev.kobj, port_name);
9601
9602         p->ports[port] = NULL;
9603         np->parent = NULL;
9604
9605         if (atomic_dec_and_test(&p->refcnt)) {
9606                 list_del(&p->list);
9607                 platform_device_unregister(p->plat_dev);
9608         }
9609
9610         mutex_unlock(&niu_parent_lock);
9611 }
9612
9613 static void *niu_pci_alloc_coherent(struct device *dev, size_t size,
9614                                     u64 *handle, gfp_t flag)
9615 {
9616         dma_addr_t dh;
9617         void *ret;
9618
9619         ret = dma_alloc_coherent(dev, size, &dh, flag);
9620         if (ret)
9621                 *handle = dh;
9622         return ret;
9623 }
9624
9625 static void niu_pci_free_coherent(struct device *dev, size_t size,
9626                                   void *cpu_addr, u64 handle)
9627 {
9628         dma_free_coherent(dev, size, cpu_addr, handle);
9629 }
9630
9631 static u64 niu_pci_map_page(struct device *dev, struct page *page,
9632                             unsigned long offset, size_t size,
9633                             enum dma_data_direction direction)
9634 {
9635         return dma_map_page(dev, page, offset, size, direction);
9636 }
9637
9638 static void niu_pci_unmap_page(struct device *dev, u64 dma_address,
9639                                size_t size, enum dma_data_direction direction)
9640 {
9641         dma_unmap_page(dev, dma_address, size, direction);
9642 }
9643
9644 static u64 niu_pci_map_single(struct device *dev, void *cpu_addr,
9645                               size_t size,
9646                               enum dma_data_direction direction)
9647 {
9648         return dma_map_single(dev, cpu_addr, size, direction);
9649 }
9650
9651 static void niu_pci_unmap_single(struct device *dev, u64 dma_address,
9652                                  size_t size,
9653                                  enum dma_data_direction direction)
9654 {
9655         dma_unmap_single(dev, dma_address, size, direction);
9656 }
9657
9658 static const struct niu_ops niu_pci_ops = {
9659         .alloc_coherent = niu_pci_alloc_coherent,
9660         .free_coherent  = niu_pci_free_coherent,
9661         .map_page       = niu_pci_map_page,
9662         .unmap_page     = niu_pci_unmap_page,
9663         .map_single     = niu_pci_map_single,
9664         .unmap_single   = niu_pci_unmap_single,
9665 };
9666
9667 static void __devinit niu_driver_version(void)
9668 {
9669         static int niu_version_printed;
9670
9671         if (niu_version_printed++ == 0)
9672                 pr_info("%s", version);
9673 }
9674
9675 static struct net_device * __devinit niu_alloc_and_init(
9676         struct device *gen_dev, struct pci_dev *pdev,
9677         struct of_device *op, const struct niu_ops *ops,
9678         u8 port)
9679 {
9680         struct net_device *dev;
9681         struct niu *np;
9682
9683         dev = alloc_etherdev_mq(sizeof(struct niu), NIU_NUM_TXCHAN);
9684         if (!dev) {
9685                 dev_err(gen_dev, "Etherdev alloc failed, aborting\n");
9686                 return NULL;
9687         }
9688
9689         SET_NETDEV_DEV(dev, gen_dev);
9690
9691         np = netdev_priv(dev);
9692         np->dev = dev;
9693         np->pdev = pdev;
9694         np->op = op;
9695         np->device = gen_dev;
9696         np->ops = ops;
9697
9698         np->msg_enable = niu_debug;
9699
9700         spin_lock_init(&np->lock);
9701         INIT_WORK(&np->reset_task, niu_reset_task);
9702
9703         np->port = port;
9704
9705         return dev;
9706 }
9707
9708 static const struct net_device_ops niu_netdev_ops = {
9709         .ndo_open               = niu_open,
9710         .ndo_stop               = niu_close,
9711         .ndo_start_xmit         = niu_start_xmit,
9712         .ndo_get_stats          = niu_get_stats,
9713         .ndo_set_multicast_list = niu_set_rx_mode,
9714         .ndo_validate_addr      = eth_validate_addr,
9715         .ndo_set_mac_address    = niu_set_mac_addr,
9716         .ndo_do_ioctl           = niu_ioctl,
9717         .ndo_tx_timeout         = niu_tx_timeout,
9718         .ndo_change_mtu         = niu_change_mtu,
9719 };
9720
9721 static void __devinit niu_assign_netdev_ops(struct net_device *dev)
9722 {
9723         dev->netdev_ops = &niu_netdev_ops;
9724         dev->ethtool_ops = &niu_ethtool_ops;
9725         dev->watchdog_timeo = NIU_TX_TIMEOUT;
9726 }
9727
9728 static void __devinit niu_device_announce(struct niu *np)
9729 {
9730         struct net_device *dev = np->dev;
9731
9732         pr_info("%s: NIU Ethernet %pM\n", dev->name, dev->dev_addr);
9733
9734         if (np->parent->plat_type == PLAT_TYPE_ATCA_CP3220) {
9735                 pr_info("%s: Port type[%s] mode[%s:%s] XCVR[%s] phy[%s]\n",
9736                                 dev->name,
9737                                 (np->flags & NIU_FLAGS_XMAC ? "XMAC" : "BMAC"),
9738                                 (np->flags & NIU_FLAGS_10G ? "10G" : "1G"),
9739                                 (np->flags & NIU_FLAGS_FIBER ? "RGMII FIBER" : "SERDES"),
9740                                 (np->mac_xcvr == MAC_XCVR_MII ? "MII" :
9741                                  (np->mac_xcvr == MAC_XCVR_PCS ? "PCS" : "XPCS")),
9742                                 np->vpd.phy_type);
9743         } else {
9744                 pr_info("%s: Port type[%s] mode[%s:%s] XCVR[%s] phy[%s]\n",
9745                                 dev->name,
9746                                 (np->flags & NIU_FLAGS_XMAC ? "XMAC" : "BMAC"),
9747                                 (np->flags & NIU_FLAGS_10G ? "10G" : "1G"),
9748                                 (np->flags & NIU_FLAGS_FIBER ? "FIBER" :
9749                                  (np->flags & NIU_FLAGS_XCVR_SERDES ? "SERDES" :
9750                                   "COPPER")),
9751                                 (np->mac_xcvr == MAC_XCVR_MII ? "MII" :
9752                                  (np->mac_xcvr == MAC_XCVR_PCS ? "PCS" : "XPCS")),
9753                                 np->vpd.phy_type);
9754         }
9755 }
9756
9757 static int __devinit niu_pci_init_one(struct pci_dev *pdev,
9758                                       const struct pci_device_id *ent)
9759 {
9760         union niu_parent_id parent_id;
9761         struct net_device *dev;
9762         struct niu *np;
9763         int err, pos;
9764         u64 dma_mask;
9765         u16 val16;
9766
9767         niu_driver_version();
9768
9769         err = pci_enable_device(pdev);
9770         if (err) {
9771                 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
9772                 return err;
9773         }
9774
9775         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM) ||
9776             !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
9777                 dev_err(&pdev->dev, "Cannot find proper PCI device base addresses, aborting\n");
9778                 err = -ENODEV;
9779                 goto err_out_disable_pdev;
9780         }
9781
9782         err = pci_request_regions(pdev, DRV_MODULE_NAME);
9783         if (err) {
9784                 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
9785                 goto err_out_disable_pdev;
9786         }
9787
9788         pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
9789         if (pos <= 0) {
9790                 dev_err(&pdev->dev, "Cannot find PCI Express capability, aborting\n");
9791                 goto err_out_free_res;
9792         }
9793
9794         dev = niu_alloc_and_init(&pdev->dev, pdev, NULL,
9795                                  &niu_pci_ops, PCI_FUNC(pdev->devfn));
9796         if (!dev) {
9797                 err = -ENOMEM;
9798                 goto err_out_free_res;
9799         }
9800         np = netdev_priv(dev);
9801
9802         memset(&parent_id, 0, sizeof(parent_id));
9803         parent_id.pci.domain = pci_domain_nr(pdev->bus);
9804         parent_id.pci.bus = pdev->bus->number;
9805         parent_id.pci.device = PCI_SLOT(pdev->devfn);
9806
9807         np->parent = niu_get_parent(np, &parent_id,
9808                                     PLAT_TYPE_ATLAS);
9809         if (!np->parent) {
9810                 err = -ENOMEM;
9811                 goto err_out_free_dev;
9812         }
9813
9814         pci_read_config_word(pdev, pos + PCI_EXP_DEVCTL, &val16);
9815         val16 &= ~PCI_EXP_DEVCTL_NOSNOOP_EN;
9816         val16 |= (PCI_EXP_DEVCTL_CERE |
9817                   PCI_EXP_DEVCTL_NFERE |
9818                   PCI_EXP_DEVCTL_FERE |
9819                   PCI_EXP_DEVCTL_URRE |
9820                   PCI_EXP_DEVCTL_RELAX_EN);
9821         pci_write_config_word(pdev, pos + PCI_EXP_DEVCTL, val16);
9822
9823         dma_mask = DMA_BIT_MASK(44);
9824         err = pci_set_dma_mask(pdev, dma_mask);
9825         if (!err) {
9826                 dev->features |= NETIF_F_HIGHDMA;
9827                 err = pci_set_consistent_dma_mask(pdev, dma_mask);
9828                 if (err) {
9829                         dev_err(&pdev->dev, "Unable to obtain 44 bit DMA for consistent allocations, aborting\n");
9830                         goto err_out_release_parent;
9831                 }
9832         }
9833         if (err || dma_mask == DMA_BIT_MASK(32)) {
9834                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
9835                 if (err) {
9836                         dev_err(&pdev->dev, "No usable DMA configuration, aborting\n");
9837                         goto err_out_release_parent;
9838                 }
9839         }
9840
9841         dev->features |= (NETIF_F_SG | NETIF_F_HW_CSUM);
9842
9843         np->regs = pci_ioremap_bar(pdev, 0);
9844         if (!np->regs) {
9845                 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
9846                 err = -ENOMEM;
9847                 goto err_out_release_parent;
9848         }
9849
9850         pci_set_master(pdev);
9851         pci_save_state(pdev);
9852
9853         dev->irq = pdev->irq;
9854
9855         niu_assign_netdev_ops(dev);
9856
9857         err = niu_get_invariants(np);
9858         if (err) {
9859                 if (err != -ENODEV)
9860                         dev_err(&pdev->dev, "Problem fetching invariants of chip, aborting\n");
9861                 goto err_out_iounmap;
9862         }
9863
9864         err = register_netdev(dev);
9865         if (err) {
9866                 dev_err(&pdev->dev, "Cannot register net device, aborting\n");
9867                 goto err_out_iounmap;
9868         }
9869
9870         pci_set_drvdata(pdev, dev);
9871
9872         niu_device_announce(np);
9873
9874         return 0;
9875
9876 err_out_iounmap:
9877         if (np->regs) {
9878                 iounmap(np->regs);
9879                 np->regs = NULL;
9880         }
9881
9882 err_out_release_parent:
9883         niu_put_parent(np);
9884
9885 err_out_free_dev:
9886         free_netdev(dev);
9887
9888 err_out_free_res:
9889         pci_release_regions(pdev);
9890
9891 err_out_disable_pdev:
9892         pci_disable_device(pdev);
9893         pci_set_drvdata(pdev, NULL);
9894
9895         return err;
9896 }
9897
9898 static void __devexit niu_pci_remove_one(struct pci_dev *pdev)
9899 {
9900         struct net_device *dev = pci_get_drvdata(pdev);
9901
9902         if (dev) {
9903                 struct niu *np = netdev_priv(dev);
9904
9905                 unregister_netdev(dev);
9906                 if (np->regs) {
9907                         iounmap(np->regs);
9908                         np->regs = NULL;
9909                 }
9910
9911                 niu_ldg_free(np);
9912
9913                 niu_put_parent(np);
9914
9915                 free_netdev(dev);
9916                 pci_release_regions(pdev);
9917                 pci_disable_device(pdev);
9918                 pci_set_drvdata(pdev, NULL);
9919         }
9920 }
9921
9922 static int niu_suspend(struct pci_dev *pdev, pm_message_t state)
9923 {
9924         struct net_device *dev = pci_get_drvdata(pdev);
9925         struct niu *np = netdev_priv(dev);
9926         unsigned long flags;
9927
9928         if (!netif_running(dev))
9929                 return 0;
9930
9931         flush_scheduled_work();
9932         niu_netif_stop(np);
9933
9934         del_timer_sync(&np->timer);
9935
9936         spin_lock_irqsave(&np->lock, flags);
9937         niu_enable_interrupts(np, 0);
9938         spin_unlock_irqrestore(&np->lock, flags);
9939
9940         netif_device_detach(dev);
9941
9942         spin_lock_irqsave(&np->lock, flags);
9943         niu_stop_hw(np);
9944         spin_unlock_irqrestore(&np->lock, flags);
9945
9946         pci_save_state(pdev);
9947
9948         return 0;
9949 }
9950
9951 static int niu_resume(struct pci_dev *pdev)
9952 {
9953         struct net_device *dev = pci_get_drvdata(pdev);
9954         struct niu *np = netdev_priv(dev);
9955         unsigned long flags;
9956         int err;
9957
9958         if (!netif_running(dev))
9959                 return 0;
9960
9961         pci_restore_state(pdev);
9962
9963         netif_device_attach(dev);
9964
9965         spin_lock_irqsave(&np->lock, flags);
9966
9967         err = niu_init_hw(np);
9968         if (!err) {
9969                 np->timer.expires = jiffies + HZ;
9970                 add_timer(&np->timer);
9971                 niu_netif_start(np);
9972         }
9973
9974         spin_unlock_irqrestore(&np->lock, flags);
9975
9976         return err;
9977 }
9978
9979 static struct pci_driver niu_pci_driver = {
9980         .name           = DRV_MODULE_NAME,
9981         .id_table       = niu_pci_tbl,
9982         .probe          = niu_pci_init_one,
9983         .remove         = __devexit_p(niu_pci_remove_one),
9984         .suspend        = niu_suspend,
9985         .resume         = niu_resume,
9986 };
9987
9988 #ifdef CONFIG_SPARC64
9989 static void *niu_phys_alloc_coherent(struct device *dev, size_t size,
9990                                      u64 *dma_addr, gfp_t flag)
9991 {
9992         unsigned long order = get_order(size);
9993         unsigned long page = __get_free_pages(flag, order);
9994
9995         if (page == 0UL)
9996                 return NULL;
9997         memset((char *)page, 0, PAGE_SIZE << order);
9998         *dma_addr = __pa(page);
9999
10000         return (void *) page;
10001 }
10002
10003 static void niu_phys_free_coherent(struct device *dev, size_t size,
10004                                    void *cpu_addr, u64 handle)
10005 {
10006         unsigned long order = get_order(size);
10007
10008         free_pages((unsigned long) cpu_addr, order);
10009 }
10010
10011 static u64 niu_phys_map_page(struct device *dev, struct page *page,
10012                              unsigned long offset, size_t size,
10013                              enum dma_data_direction direction)
10014 {
10015         return page_to_phys(page) + offset;
10016 }
10017
10018 static void niu_phys_unmap_page(struct device *dev, u64 dma_address,
10019                                 size_t size, enum dma_data_direction direction)
10020 {
10021         /* Nothing to do.  */
10022 }
10023
10024 static u64 niu_phys_map_single(struct device *dev, void *cpu_addr,
10025                                size_t size,
10026                                enum dma_data_direction direction)
10027 {
10028         return __pa(cpu_addr);
10029 }
10030
10031 static void niu_phys_unmap_single(struct device *dev, u64 dma_address,
10032                                   size_t size,
10033                                   enum dma_data_direction direction)
10034 {
10035         /* Nothing to do.  */
10036 }
10037
10038 static const struct niu_ops niu_phys_ops = {
10039         .alloc_coherent = niu_phys_alloc_coherent,
10040         .free_coherent  = niu_phys_free_coherent,
10041         .map_page       = niu_phys_map_page,
10042         .unmap_page     = niu_phys_unmap_page,
10043         .map_single     = niu_phys_map_single,
10044         .unmap_single   = niu_phys_unmap_single,
10045 };
10046
10047 static int __devinit niu_of_probe(struct of_device *op,
10048                                   const struct of_device_id *match)
10049 {
10050         union niu_parent_id parent_id;
10051         struct net_device *dev;
10052         struct niu *np;
10053         const u32 *reg;
10054         int err;
10055
10056         niu_driver_version();
10057
10058         reg = of_get_property(op->node, "reg", NULL);
10059         if (!reg) {
10060                 dev_err(&op->dev, "%s: No 'reg' property, aborting\n",
10061                         op->node->full_name);
10062                 return -ENODEV;
10063         }
10064
10065         dev = niu_alloc_and_init(&op->dev, NULL, op,
10066                                  &niu_phys_ops, reg[0] & 0x1);
10067         if (!dev) {
10068                 err = -ENOMEM;
10069                 goto err_out;
10070         }
10071         np = netdev_priv(dev);
10072
10073         memset(&parent_id, 0, sizeof(parent_id));
10074         parent_id.of = of_get_parent(op->node);
10075
10076         np->parent = niu_get_parent(np, &parent_id,
10077                                     PLAT_TYPE_NIU);
10078         if (!np->parent) {
10079                 err = -ENOMEM;
10080                 goto err_out_free_dev;
10081         }
10082
10083         dev->features |= (NETIF_F_SG | NETIF_F_HW_CSUM);
10084
10085         np->regs = of_ioremap(&op->resource[1], 0,
10086                               resource_size(&op->resource[1]),
10087                               "niu regs");
10088         if (!np->regs) {
10089                 dev_err(&op->dev, "Cannot map device registers, aborting\n");
10090                 err = -ENOMEM;
10091                 goto err_out_release_parent;
10092         }
10093
10094         np->vir_regs_1 = of_ioremap(&op->resource[2], 0,
10095                                     resource_size(&op->resource[2]),
10096                                     "niu vregs-1");
10097         if (!np->vir_regs_1) {
10098                 dev_err(&op->dev, "Cannot map device vir registers 1, aborting\n");
10099                 err = -ENOMEM;
10100                 goto err_out_iounmap;
10101         }
10102
10103         np->vir_regs_2 = of_ioremap(&op->resource[3], 0,
10104                                     resource_size(&op->resource[3]),
10105                                     "niu vregs-2");
10106         if (!np->vir_regs_2) {
10107                 dev_err(&op->dev, "Cannot map device vir registers 2, aborting\n");
10108                 err = -ENOMEM;
10109                 goto err_out_iounmap;
10110         }
10111
10112         niu_assign_netdev_ops(dev);
10113
10114         err = niu_get_invariants(np);
10115         if (err) {
10116                 if (err != -ENODEV)
10117                         dev_err(&op->dev, "Problem fetching invariants of chip, aborting\n");
10118                 goto err_out_iounmap;
10119         }
10120
10121         err = register_netdev(dev);
10122         if (err) {
10123                 dev_err(&op->dev, "Cannot register net device, aborting\n");
10124                 goto err_out_iounmap;
10125         }
10126
10127         dev_set_drvdata(&op->dev, dev);
10128
10129         niu_device_announce(np);
10130
10131         return 0;
10132
10133 err_out_iounmap:
10134         if (np->vir_regs_1) {
10135                 of_iounmap(&op->resource[2], np->vir_regs_1,
10136                            resource_size(&op->resource[2]));
10137                 np->vir_regs_1 = NULL;
10138         }
10139
10140         if (np->vir_regs_2) {
10141                 of_iounmap(&op->resource[3], np->vir_regs_2,
10142                            resource_size(&op->resource[3]));
10143                 np->vir_regs_2 = NULL;
10144         }
10145
10146         if (np->regs) {
10147                 of_iounmap(&op->resource[1], np->regs,
10148                            resource_size(&op->resource[1]));
10149                 np->regs = NULL;
10150         }
10151
10152 err_out_release_parent:
10153         niu_put_parent(np);
10154
10155 err_out_free_dev:
10156         free_netdev(dev);
10157
10158 err_out:
10159         return err;
10160 }
10161
10162 static int __devexit niu_of_remove(struct of_device *op)
10163 {
10164         struct net_device *dev = dev_get_drvdata(&op->dev);
10165
10166         if (dev) {
10167                 struct niu *np = netdev_priv(dev);
10168
10169                 unregister_netdev(dev);
10170
10171                 if (np->vir_regs_1) {
10172                         of_iounmap(&op->resource[2], np->vir_regs_1,
10173                                    resource_size(&op->resource[2]));
10174                         np->vir_regs_1 = NULL;
10175                 }
10176
10177                 if (np->vir_regs_2) {
10178                         of_iounmap(&op->resource[3], np->vir_regs_2,
10179                                    resource_size(&op->resource[3]));
10180                         np->vir_regs_2 = NULL;
10181                 }
10182
10183                 if (np->regs) {
10184                         of_iounmap(&op->resource[1], np->regs,
10185                                    resource_size(&op->resource[1]));
10186                         np->regs = NULL;
10187                 }
10188
10189                 niu_ldg_free(np);
10190
10191                 niu_put_parent(np);
10192
10193                 free_netdev(dev);
10194                 dev_set_drvdata(&op->dev, NULL);
10195         }
10196         return 0;
10197 }
10198
10199 static const struct of_device_id niu_match[] = {
10200         {
10201                 .name = "network",
10202                 .compatible = "SUNW,niusl",
10203         },
10204         {},
10205 };
10206 MODULE_DEVICE_TABLE(of, niu_match);
10207
10208 static struct of_platform_driver niu_of_driver = {
10209         .name           = "niu",
10210         .match_table    = niu_match,
10211         .probe          = niu_of_probe,
10212         .remove         = __devexit_p(niu_of_remove),
10213 };
10214
10215 #endif /* CONFIG_SPARC64 */
10216
10217 static int __init niu_init(void)
10218 {
10219         int err = 0;
10220
10221         BUILD_BUG_ON(PAGE_SIZE < 4 * 1024);
10222
10223         niu_debug = netif_msg_init(debug, NIU_MSG_DEFAULT);
10224
10225 #ifdef CONFIG_SPARC64
10226         err = of_register_driver(&niu_of_driver, &of_bus_type);
10227 #endif
10228
10229         if (!err) {
10230                 err = pci_register_driver(&niu_pci_driver);
10231 #ifdef CONFIG_SPARC64
10232                 if (err)
10233                         of_unregister_driver(&niu_of_driver);
10234 #endif
10235         }
10236
10237         return err;
10238 }
10239
10240 static void __exit niu_exit(void)
10241 {
10242         pci_unregister_driver(&niu_pci_driver);
10243 #ifdef CONFIG_SPARC64
10244         of_unregister_driver(&niu_of_driver);
10245 #endif
10246 }
10247
10248 module_init(niu_init);
10249 module_exit(niu_exit);