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   1 /*************************************************************************
   2  * myri10ge.c: Myricom Myri-10G Ethernet driver.
   3  *
   4  * Copyright (C) 2005 - 2009 Myricom, Inc.
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  * 3. Neither the name of Myricom, Inc. nor the names of its contributors
  16  *    may be used to endorse or promote products derived from this software
  17  *    without specific prior written permission.
  18  *
  19  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  20  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  22  * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  23  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  29  * POSSIBILITY OF SUCH DAMAGE.
  30  *
  31  *
  32  * If the eeprom on your board is not recent enough, you will need to get a
  33  * newer firmware image at:
  34  *   http://www.myri.com/scs/download-Myri10GE.html
  35  *
  36  * Contact Information:
  37  *   <help@myri.com>
  38  *   Myricom, Inc., 325N Santa Anita Avenue, Arcadia, CA 91006
  39  *************************************************************************/
  40
  41 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  42
  43 #include <linux/tcp.h>
  44 #include <linux/netdevice.h>
  45 #include <linux/skbuff.h>
  46 #include <linux/string.h>
  47 #include <linux/module.h>
  48 #include <linux/pci.h>
  49 #include <linux/dma-mapping.h>
  50 #include <linux/etherdevice.h>
  51 #include <linux/if_ether.h>
  52 #include <linux/if_vlan.h>
  53 #include <linux/inet_lro.h>
  54 #include <linux/dca.h>
  55 #include <linux/ip.h>
  56 #include <linux/inet.h>
  57 #include <linux/in.h>
  58 #include <linux/ethtool.h>
  59 #include <linux/firmware.h>
  60 #include <linux/delay.h>
  61 #include <linux/timer.h>
  62 #include <linux/vmalloc.h>
  63 #include <linux/crc32.h>
  64 #include <linux/moduleparam.h>
  65 #include <linux/io.h>
  66 #include <linux/log2.h>
  67 #include <linux/slab.h>
  68 #include <net/checksum.h>
  69 #include <net/ip.h>
  70 #include <net/tcp.h>
  71 #include <asm/byteorder.h>
  72 #include <asm/io.h>
  73 #include <asm/processor.h>
  74 #ifdef CONFIG_MTRR
  75 #include <asm/mtrr.h>
  76 #endif
  77
  78 #include "myri10ge_mcp.h"
  79 #include "myri10ge_mcp_gen_header.h"
  80
  81 #define MYRI10GE_VERSION_STR "1.5.2-1.459"
  82
  83 MODULE_DESCRIPTION("Myricom 10G driver (10GbE)");
  84 MODULE_AUTHOR("Maintainer: help@myri.com");
  85 MODULE_VERSION(MYRI10GE_VERSION_STR);
  86 MODULE_LICENSE("Dual BSD/GPL");
  87
  88 #define MYRI10GE_MAX_ETHER_MTU 9014
  89
  90 #define MYRI10GE_ETH_STOPPED 0
  91 #define MYRI10GE_ETH_STOPPING 1
  92 #define MYRI10GE_ETH_STARTING 2
  93 #define MYRI10GE_ETH_RUNNING 3
  94 #define MYRI10GE_ETH_OPEN_FAILED 4
  95
  96 #define MYRI10GE_EEPROM_STRINGS_SIZE 256
  97 #define MYRI10GE_MAX_SEND_DESC_TSO ((65536 / 2048) * 2)
  98 #define MYRI10GE_MAX_LRO_DESCRIPTORS 8
  99 #define MYRI10GE_LRO_MAX_PKTS 64
 100
 101 #define MYRI10GE_NO_CONFIRM_DATA htonl(0xffffffff)
 102 #define MYRI10GE_NO_RESPONSE_RESULT 0xffffffff
 103
 104 #define MYRI10GE_ALLOC_ORDER 0
 105 #define MYRI10GE_ALLOC_SIZE ((1 << MYRI10GE_ALLOC_ORDER) * PAGE_SIZE)
 106 #define MYRI10GE_MAX_FRAGS_PER_FRAME (MYRI10GE_MAX_ETHER_MTU/MYRI10GE_ALLOC_SIZE + 1)
 107
 108 #define MYRI10GE_MAX_SLICES 32
 109
 110 struct myri10ge_rx_buffer_state {
 111         struct page *page;
 112         int page_offset;
 113          DECLARE_PCI_UNMAP_ADDR(bus)
 114          DECLARE_PCI_UNMAP_LEN(len)
 115 };
 116
 117 struct myri10ge_tx_buffer_state {
 118         struct sk_buff *skb;
 119         int last;
 120          DECLARE_PCI_UNMAP_ADDR(bus)
 121          DECLARE_PCI_UNMAP_LEN(len)
 122 };
 123
 124 struct myri10ge_cmd {
 125         u32 data0;
 126         u32 data1;
 127         u32 data2;
 128 };
 129
 130 struct myri10ge_rx_buf {
 131         struct mcp_kreq_ether_recv __iomem *lanai;      /* lanai ptr for recv ring */
 132         struct mcp_kreq_ether_recv *shadow;     /* host shadow of recv ring */
 133         struct myri10ge_rx_buffer_state *info;
 134         struct page *page;
 135         dma_addr_t bus;
 136         int page_offset;
 137         int cnt;
 138         int fill_cnt;
 139         int alloc_fail;
 140         int mask;               /* number of rx slots -1 */
 141         int watchdog_needed;
 142 };
 143
 144 struct myri10ge_tx_buf {
 145         struct mcp_kreq_ether_send __iomem *lanai;      /* lanai ptr for sendq */
 146         __be32 __iomem *send_go;        /* "go" doorbell ptr */
 147         __be32 __iomem *send_stop;      /* "stop" doorbell ptr */
 148         struct mcp_kreq_ether_send *req_list;   /* host shadow of sendq */
 149         char *req_bytes;
 150         struct myri10ge_tx_buffer_state *info;
 151         int mask;               /* number of transmit slots -1  */
 152         int req ____cacheline_aligned;  /* transmit slots submitted     */
 153         int pkt_start;          /* packets started */
 154         int stop_queue;
 155         int linearized;
 156         int done ____cacheline_aligned; /* transmit slots completed     */
 157         int pkt_done;           /* packets completed */
 158         int wake_queue;
 159         int queue_active;
 160 };
 161
 162 struct myri10ge_rx_done {
 163         struct mcp_slot *entry;
 164         dma_addr_t bus;
 165         int cnt;
 166         int idx;
 167         struct net_lro_mgr lro_mgr;
 168         struct net_lro_desc lro_desc[MYRI10GE_MAX_LRO_DESCRIPTORS];
 169 };
 170
 171 struct myri10ge_slice_netstats {
 172         unsigned long rx_packets;
 173         unsigned long tx_packets;
 174         unsigned long rx_bytes;
 175         unsigned long tx_bytes;
 176         unsigned long rx_dropped;
 177         unsigned long tx_dropped;
 178 };
 179
 180 struct myri10ge_slice_state {
 181         struct myri10ge_tx_buf tx;      /* transmit ring        */
 182         struct myri10ge_rx_buf rx_small;
 183         struct myri10ge_rx_buf rx_big;
 184         struct myri10ge_rx_done rx_done;
 185         struct net_device *dev;
 186         struct napi_struct napi;
 187         struct myri10ge_priv *mgp;
 188         struct myri10ge_slice_netstats stats;
 189         __be32 __iomem *irq_claim;
 190         struct mcp_irq_data *fw_stats;
 191         dma_addr_t fw_stats_bus;
 192         int watchdog_tx_done;
 193         int watchdog_tx_req;
 194         int watchdog_rx_done;
 195 #ifdef CONFIG_MYRI10GE_DCA
 196         int cached_dca_tag;
 197         int cpu;
 198         __be32 __iomem *dca_tag;
 199 #endif
 200         char irq_desc[32];
 201 };
 202
 203 struct myri10ge_priv {
 204         struct myri10ge_slice_state *ss;
 205         int tx_boundary;        /* boundary transmits cannot cross */
 206         int num_slices;
 207         int running;            /* running?             */
 208         int csum_flag;          /* rx_csums?            */
 209         int small_bytes;
 210         int big_bytes;
 211         int max_intr_slots;
 212         struct net_device *dev;
 213         spinlock_t stats_lock;
 214         u8 __iomem *sram;
 215         int sram_size;
 216         unsigned long board_span;
 217         unsigned long iomem_base;
 218         __be32 __iomem *irq_deassert;
 219         char *mac_addr_string;
 220         struct mcp_cmd_response *cmd;
 221         dma_addr_t cmd_bus;
 222         struct pci_dev *pdev;
 223         int msi_enabled;
 224         int msix_enabled;
 225         struct msix_entry *msix_vectors;
 226 #ifdef CONFIG_MYRI10GE_DCA
 227         int dca_enabled;
 228 #endif
 229         u32 link_state;
 230         unsigned int rdma_tags_available;
 231         int intr_coal_delay;
 232         __be32 __iomem *intr_coal_delay_ptr;
 233         int mtrr;
 234         int wc_enabled;
 235         int down_cnt;
 236         wait_queue_head_t down_wq;
 237         struct work_struct watchdog_work;
 238         struct timer_list watchdog_timer;
 239         int watchdog_resets;
 240         int watchdog_pause;
 241         int pause;
 242         char *fw_name;
 243         char eeprom_strings[MYRI10GE_EEPROM_STRINGS_SIZE];
 244         char *product_code_string;
 245         char fw_version[128];
 246         int fw_ver_major;
 247         int fw_ver_minor;
 248         int fw_ver_tiny;
 249         int adopted_rx_filter_bug;
 250         u8 mac_addr[6];         /* eeprom mac address */
 251         unsigned long serial_number;
 252         int vendor_specific_offset;
 253         int fw_multicast_support;
 254         unsigned long features;
 255         u32 max_tso6;
 256         u32 read_dma;
 257         u32 write_dma;
 258         u32 read_write_dma;
 259         u32 link_changes;
 260         u32 msg_enable;
 261         unsigned int board_number;
 262         int rebooted;
 263 };
 264
 265 static char *myri10ge_fw_unaligned = "myri10ge_ethp_z8e.dat";
 266 static char *myri10ge_fw_aligned = "myri10ge_eth_z8e.dat";
 267 static char *myri10ge_fw_rss_unaligned = "myri10ge_rss_ethp_z8e.dat";
 268 static char *myri10ge_fw_rss_aligned = "myri10ge_rss_eth_z8e.dat";
 269 MODULE_FIRMWARE("myri10ge_ethp_z8e.dat");
 270 MODULE_FIRMWARE("myri10ge_eth_z8e.dat");
 271 MODULE_FIRMWARE("myri10ge_rss_ethp_z8e.dat");
 272 MODULE_FIRMWARE("myri10ge_rss_eth_z8e.dat");
 273
 274 static char *myri10ge_fw_name = NULL;
 275 module_param(myri10ge_fw_name, charp, S_IRUGO | S_IWUSR);
 276 MODULE_PARM_DESC(myri10ge_fw_name, "Firmware image name");
 277
 278 #define MYRI10GE_MAX_BOARDS 8
 279 static char *myri10ge_fw_names[MYRI10GE_MAX_BOARDS] =
 280     {[0 ... (MYRI10GE_MAX_BOARDS - 1)] = NULL };
 281 module_param_array_named(myri10ge_fw_names, myri10ge_fw_names, charp, NULL,
 282                          0444);
 283 MODULE_PARM_DESC(myri10ge_fw_name, "Firmware image names per board");
 284
 285 static int myri10ge_ecrc_enable = 1;
 286 module_param(myri10ge_ecrc_enable, int, S_IRUGO);
 287 MODULE_PARM_DESC(myri10ge_ecrc_enable, "Enable Extended CRC on PCI-E");
 288
 289 static int myri10ge_small_bytes = -1;   /* -1 == auto */
 290 module_param(myri10ge_small_bytes, int, S_IRUGO | S_IWUSR);
 291 MODULE_PARM_DESC(myri10ge_small_bytes, "Threshold of small packets");
 292
 293 static int myri10ge_msi = 1;    /* enable msi by default */
 294 module_param(myri10ge_msi, int, S_IRUGO | S_IWUSR);
 295 MODULE_PARM_DESC(myri10ge_msi, "Enable Message Signalled Interrupts");
 296
 297 static int myri10ge_intr_coal_delay = 75;
 298 module_param(myri10ge_intr_coal_delay, int, S_IRUGO);
 299 MODULE_PARM_DESC(myri10ge_intr_coal_delay, "Interrupt coalescing delay");
 300
 301 static int myri10ge_flow_control = 1;
 302 module_param(myri10ge_flow_control, int, S_IRUGO);
 303 MODULE_PARM_DESC(myri10ge_flow_control, "Pause parameter");
 304
 305 static int myri10ge_deassert_wait = 1;
 306 module_param(myri10ge_deassert_wait, int, S_IRUGO | S_IWUSR);
 307 MODULE_PARM_DESC(myri10ge_deassert_wait,
 308                  "Wait when deasserting legacy interrupts");
 309
 310 static int myri10ge_force_firmware = 0;
 311 module_param(myri10ge_force_firmware, int, S_IRUGO);
 312 MODULE_PARM_DESC(myri10ge_force_firmware,
 313                  "Force firmware to assume aligned completions");
 314
 315 static int myri10ge_initial_mtu = MYRI10GE_MAX_ETHER_MTU - ETH_HLEN;
 316 module_param(myri10ge_initial_mtu, int, S_IRUGO);
 317 MODULE_PARM_DESC(myri10ge_initial_mtu, "Initial MTU");
 318
 319 static int myri10ge_napi_weight = 64;
 320 module_param(myri10ge_napi_weight, int, S_IRUGO);
 321 MODULE_PARM_DESC(myri10ge_napi_weight, "Set NAPI weight");
 322
 323 static int myri10ge_watchdog_timeout = 1;
 324 module_param(myri10ge_watchdog_timeout, int, S_IRUGO);
 325 MODULE_PARM_DESC(myri10ge_watchdog_timeout, "Set watchdog timeout");
 326
 327 static int myri10ge_max_irq_loops = 1048576;
 328 module_param(myri10ge_max_irq_loops, int, S_IRUGO);
 329 MODULE_PARM_DESC(myri10ge_max_irq_loops,
 330                  "Set stuck legacy IRQ detection threshold");
 331
 332 #define MYRI10GE_MSG_DEFAULT NETIF_MSG_LINK
 333
 334 static int myri10ge_debug = -1; /* defaults above */
 335 module_param(myri10ge_debug, int, 0);
 336 MODULE_PARM_DESC(myri10ge_debug, "Debug level (0=none,...,16=all)");
 337
 338 static int myri10ge_lro_max_pkts = MYRI10GE_LRO_MAX_PKTS;
 339 module_param(myri10ge_lro_max_pkts, int, S_IRUGO);
 340 MODULE_PARM_DESC(myri10ge_lro_max_pkts,
 341                  "Number of LRO packets to be aggregated");
 342
 343 static int myri10ge_fill_thresh = 256;
 344 module_param(myri10ge_fill_thresh, int, S_IRUGO | S_IWUSR);
 345 MODULE_PARM_DESC(myri10ge_fill_thresh, "Number of empty rx slots allowed");
 346
 347 static int myri10ge_reset_recover = 1;
 348
 349 static int myri10ge_max_slices = 1;
 350 module_param(myri10ge_max_slices, int, S_IRUGO);
 351 MODULE_PARM_DESC(myri10ge_max_slices, "Max tx/rx queues");
 352
 353 static int myri10ge_rss_hash = MXGEFW_RSS_HASH_TYPE_SRC_DST_PORT;
 354 module_param(myri10ge_rss_hash, int, S_IRUGO);
 355 MODULE_PARM_DESC(myri10ge_rss_hash, "Type of RSS hashing to do");
 356
 357 static int myri10ge_dca = 1;
 358 module_param(myri10ge_dca, int, S_IRUGO);
 359 MODULE_PARM_DESC(myri10ge_dca, "Enable DCA if possible");
 360
 361 #define MYRI10GE_FW_OFFSET 1024*1024
 362 #define MYRI10GE_HIGHPART_TO_U32(X) \
 363 (sizeof (X) == 8) ? ((u32)((u64)(X) >> 32)) : (0)
 364 #define MYRI10GE_LOWPART_TO_U32(X) ((u32)(X))
 365
 366 #define myri10ge_pio_copy(to,from,size) __iowrite64_copy(to,from,size/8)
 367
 368 static void myri10ge_set_multicast_list(struct net_device *dev);
 369 static netdev_tx_t myri10ge_sw_tso(struct sk_buff *skb,
 370                                          struct net_device *dev);
 371
 372 static inline void put_be32(__be32 val, __be32 __iomem * p)
 373 {
 374         __raw_writel((__force __u32) val, (__force void __iomem *)p);
 375 }
 376
 377 static struct net_device_stats *myri10ge_get_stats(struct net_device *dev);
 378
 379 static int
 380 myri10ge_send_cmd(struct myri10ge_priv *mgp, u32 cmd,
 381                   struct myri10ge_cmd *data, int atomic)
 382 {
 383         struct mcp_cmd *buf;
 384         char buf_bytes[sizeof(*buf) + 8];
 385         struct mcp_cmd_response *response = mgp->cmd;
 386         char __iomem *cmd_addr = mgp->sram + MXGEFW_ETH_CMD;
 387         u32 dma_low, dma_high, result, value;
 388         int sleep_total = 0;
 389
 390         /* ensure buf is aligned to 8 bytes */
 391         buf = (struct mcp_cmd *)ALIGN((unsigned long)buf_bytes, 8);
 392
 393         buf->data0 = htonl(data->data0);
 394         buf->data1 = htonl(data->data1);
 395         buf->data2 = htonl(data->data2);
 396         buf->cmd = htonl(cmd);
 397         dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
 398         dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
 399
 400         buf->response_addr.low = htonl(dma_low);
 401         buf->response_addr.high = htonl(dma_high);
 402         response->result = htonl(MYRI10GE_NO_RESPONSE_RESULT);
 403         mb();
 404         myri10ge_pio_copy(cmd_addr, buf, sizeof(*buf));
 405
 406         /* wait up to 15ms. Longest command is the DMA benchmark,
 407          * which is capped at 5ms, but runs from a timeout handler
 408          * that runs every 7.8ms. So a 15ms timeout leaves us with
 409          * a 2.2ms margin
 410          */
 411         if (atomic) {
 412                 /* if atomic is set, do not sleep,
 413                  * and try to get the completion quickly
 414                  * (1ms will be enough for those commands) */
 415                 for (sleep_total = 0;
 416                      sleep_total < 1000 &&
 417                      response->result == htonl(MYRI10GE_NO_RESPONSE_RESULT);
 418                      sleep_total += 10) {
 419                         udelay(10);
 420                         mb();
 421                 }
 422         } else {
 423                 /* use msleep for most command */
 424                 for (sleep_total = 0;
 425                      sleep_total < 15 &&
 426                      response->result == htonl(MYRI10GE_NO_RESPONSE_RESULT);
 427                      sleep_total++)
 428                         msleep(1);
 429         }
 430
 431         result = ntohl(response->result);
 432         value = ntohl(response->data);
 433         if (result != MYRI10GE_NO_RESPONSE_RESULT) {
 434                 if (result == 0) {
 435                         data->data0 = value;
 436                         return 0;
 437                 } else if (result == MXGEFW_CMD_UNKNOWN) {
 438                         return -ENOSYS;
 439                 } else if (result == MXGEFW_CMD_ERROR_UNALIGNED) {
 440                         return -E2BIG;
 441                 } else if (result == MXGEFW_CMD_ERROR_RANGE &&
 442                            cmd == MXGEFW_CMD_ENABLE_RSS_QUEUES &&
 443                            (data->
 444                             data1 & MXGEFW_SLICE_ENABLE_MULTIPLE_TX_QUEUES) !=
 445                            0) {
 446                         return -ERANGE;
 447                 } else {
 448                         dev_err(&mgp->pdev->dev,
 449                                 "command %d failed, result = %d\n",
 450                                 cmd, result);
 451                         return -ENXIO;
 452                 }
 453         }
 454
 455         dev_err(&mgp->pdev->dev, "command %d timed out, result = %d\n",
 456                 cmd, result);
 457         return -EAGAIN;
 458 }
 459
 460 /*
 461  * The eeprom strings on the lanaiX have the format
 462  * SN=x\0
 463  * MAC=x:x:x:x:x:x\0
 464  * PT:ddd mmm xx xx:xx:xx xx\0
 465  * PV:ddd mmm xx xx:xx:xx xx\0
 466  */
 467 static int myri10ge_read_mac_addr(struct myri10ge_priv *mgp)
 468 {
 469         char *ptr, *limit;
 470         int i;
 471
 472         ptr = mgp->eeprom_strings;
 473         limit = mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE;
 474
 475         while (*ptr != '\0' && ptr < limit) {
 476                 if (memcmp(ptr, "MAC=", 4) == 0) {
 477                         ptr += 4;
 478                         mgp->mac_addr_string = ptr;
 479                         for (i = 0; i < 6; i++) {
 480                                 if ((ptr + 2) > limit)
 481                                         goto abort;
 482                                 mgp->mac_addr[i] =
 483                                     simple_strtoul(ptr, &ptr, 16);
 484                                 ptr += 1;
 485                         }
 486                 }
 487                 if (memcmp(ptr, "PC=", 3) == 0) {
 488                         ptr += 3;
 489                         mgp->product_code_string = ptr;
 490                 }
 491                 if (memcmp((const void *)ptr, "SN=", 3) == 0) {
 492                         ptr += 3;
 493                         mgp->serial_number = simple_strtoul(ptr, &ptr, 10);
 494                 }
 495                 while (ptr < limit && *ptr++) ;
 496         }
 497
 498         return 0;
 499
 500 abort:
 501         dev_err(&mgp->pdev->dev, "failed to parse eeprom_strings\n");
 502         return -ENXIO;
 503 }
 504
 505 /*
 506  * Enable or disable periodic RDMAs from the host to make certain
 507  * chipsets resend dropped PCIe messages
 508  */
 509
 510 static void myri10ge_dummy_rdma(struct myri10ge_priv *mgp, int enable)
 511 {
 512         char __iomem *submit;
 513         __be32 buf[16] __attribute__ ((__aligned__(8)));
 514         u32 dma_low, dma_high;
 515         int i;
 516
 517         /* clear confirmation addr */
 518         mgp->cmd->data = 0;
 519         mb();
 520
 521         /* send a rdma command to the PCIe engine, and wait for the
 522          * response in the confirmation address.  The firmware should
 523          * write a -1 there to indicate it is alive and well
 524          */
 525         dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
 526         dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
 527
 528         buf[0] = htonl(dma_high);       /* confirm addr MSW */
 529         buf[1] = htonl(dma_low);        /* confirm addr LSW */
 530         buf[2] = MYRI10GE_NO_CONFIRM_DATA;      /* confirm data */
 531         buf[3] = htonl(dma_high);       /* dummy addr MSW */
 532         buf[4] = htonl(dma_low);        /* dummy addr LSW */
 533         buf[5] = htonl(enable); /* enable? */
 534
 535         submit = mgp->sram + MXGEFW_BOOT_DUMMY_RDMA;
 536
 537         myri10ge_pio_copy(submit, &buf, sizeof(buf));
 538         for (i = 0; mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 20; i++)
 539                 msleep(1);
 540         if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA)
 541                 dev_err(&mgp->pdev->dev, "dummy rdma %s failed\n",
 542                         (enable ? "enable" : "disable"));
 543 }
 544
 545 static int
 546 myri10ge_validate_firmware(struct myri10ge_priv *mgp,
 547                            struct mcp_gen_header *hdr)
 548 {
 549         struct device *dev = &mgp->pdev->dev;
 550
 551         /* check firmware type */
 552         if (ntohl(hdr->mcp_type) != MCP_TYPE_ETH) {
 553                 dev_err(dev, "Bad firmware type: 0x%x\n", ntohl(hdr->mcp_type));
 554                 return -EINVAL;
 555         }
 556
 557         /* save firmware version for ethtool */
 558         strncpy(mgp->fw_version, hdr->version, sizeof(mgp->fw_version));
 559
 560         sscanf(mgp->fw_version, "%d.%d.%d", &mgp->fw_ver_major,
 561                &mgp->fw_ver_minor, &mgp->fw_ver_tiny);
 562
 563         if (!(mgp->fw_ver_major == MXGEFW_VERSION_MAJOR &&
 564               mgp->fw_ver_minor == MXGEFW_VERSION_MINOR)) {
 565                 dev_err(dev, "Found firmware version %s\n", mgp->fw_version);
 566                 dev_err(dev, "Driver needs %d.%d\n", MXGEFW_VERSION_MAJOR,
 567                         MXGEFW_VERSION_MINOR);
 568                 return -EINVAL;
 569         }
 570         return 0;
 571 }
 572
 573 static int myri10ge_load_hotplug_firmware(struct myri10ge_priv *mgp, u32 * size)
 574 {
 575         unsigned crc, reread_crc;
 576         const struct firmware *fw;
 577         struct device *dev = &mgp->pdev->dev;
 578         unsigned char *fw_readback;
 579         struct mcp_gen_header *hdr;
 580         size_t hdr_offset;
 581         int status;
 582         unsigned i;
 583
 584         if ((status = request_firmware(&fw, mgp->fw_name, dev)) < 0) {
 585                 dev_err(dev, "Unable to load %s firmware image via hotplug\n",
 586                         mgp->fw_name);
 587                 status = -EINVAL;
 588                 goto abort_with_nothing;
 589         }
 590
 591         /* check size */
 592
 593         if (fw->size >= mgp->sram_size - MYRI10GE_FW_OFFSET ||
 594             fw->size < MCP_HEADER_PTR_OFFSET + 4) {
 595                 dev_err(dev, "Firmware size invalid:%d\n", (int)fw->size);
 596                 status = -EINVAL;
 597                 goto abort_with_fw;
 598         }
 599
 600         /* check id */
 601         hdr_offset = ntohl(*(__be32 *) (fw->data + MCP_HEADER_PTR_OFFSET));
 602         if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > fw->size) {
 603                 dev_err(dev, "Bad firmware file\n");
 604                 status = -EINVAL;
 605                 goto abort_with_fw;
 606         }
 607         hdr = (void *)(fw->data + hdr_offset);
 608
 609         status = myri10ge_validate_firmware(mgp, hdr);
 610         if (status != 0)
 611                 goto abort_with_fw;
 612
 613         crc = crc32(~0, fw->data, fw->size);
 614         for (i = 0; i < fw->size; i += 256) {
 615                 myri10ge_pio_copy(mgp->sram + MYRI10GE_FW_OFFSET + i,
 616                                   fw->data + i,
 617                                   min(256U, (unsigned)(fw->size - i)));
 618                 mb();
 619                 readb(mgp->sram);
 620         }
 621         fw_readback = vmalloc(fw->size);
 622         if (!fw_readback) {
 623                 status = -ENOMEM;
 624                 goto abort_with_fw;
 625         }
 626         /* corruption checking is good for parity recovery and buggy chipset */
 627         memcpy_fromio(fw_readback, mgp->sram + MYRI10GE_FW_OFFSET, fw->size);
 628         reread_crc = crc32(~0, fw_readback, fw->size);
 629         vfree(fw_readback);
 630         if (crc != reread_crc) {
 631                 dev_err(dev, "CRC failed(fw-len=%u), got 0x%x (expect 0x%x)\n",
 632                         (unsigned)fw->size, reread_crc, crc);
 633                 status = -EIO;
 634                 goto abort_with_fw;
 635         }
 636         *size = (u32) fw->size;
 637
 638 abort_with_fw:
 639         release_firmware(fw);
 640
 641 abort_with_nothing:
 642         return status;
 643 }
 644
 645 static int myri10ge_adopt_running_firmware(struct myri10ge_priv *mgp)
 646 {
 647         struct mcp_gen_header *hdr;
 648         struct device *dev = &mgp->pdev->dev;
 649         const size_t bytes = sizeof(struct mcp_gen_header);
 650         size_t hdr_offset;
 651         int status;
 652
 653         /* find running firmware header */
 654         hdr_offset = swab32(readl(mgp->sram + MCP_HEADER_PTR_OFFSET));
 655
 656         if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > mgp->sram_size) {
 657                 dev_err(dev, "Running firmware has bad header offset (%d)\n",
 658                         (int)hdr_offset);
 659                 return -EIO;
 660         }
 661
 662         /* copy header of running firmware from SRAM to host memory to
 663          * validate firmware */
 664         hdr = kmalloc(bytes, GFP_KERNEL);
 665         if (hdr == NULL) {
 666                 dev_err(dev, "could not malloc firmware hdr\n");
 667                 return -ENOMEM;
 668         }
 669         memcpy_fromio(hdr, mgp->sram + hdr_offset, bytes);
 670         status = myri10ge_validate_firmware(mgp, hdr);
 671         kfree(hdr);
 672
 673         /* check to see if adopted firmware has bug where adopting
 674          * it will cause broadcasts to be filtered unless the NIC
 675          * is kept in ALLMULTI mode */
 676         if (mgp->fw_ver_major == 1 && mgp->fw_ver_minor == 4 &&
 677             mgp->fw_ver_tiny >= 4 && mgp->fw_ver_tiny <= 11) {
 678                 mgp->adopted_rx_filter_bug = 1;
 679                 dev_warn(dev, "Adopting fw %d.%d.%d: "
 680                          "working around rx filter bug\n",
 681                          mgp->fw_ver_major, mgp->fw_ver_minor,
 682                          mgp->fw_ver_tiny);
 683         }
 684         return status;
 685 }
 686
 687 static int myri10ge_get_firmware_capabilities(struct myri10ge_priv *mgp)
 688 {
 689         struct myri10ge_cmd cmd;
 690         int status;
 691
 692         /* probe for IPv6 TSO support */
 693         mgp->features = NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_TSO;
 694         status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_MAX_TSO6_HDR_SIZE,
 695                                    &cmd, 0);
 696         if (status == 0) {
 697                 mgp->max_tso6 = cmd.data0;
 698                 mgp->features |= NETIF_F_TSO6;
 699         }
 700
 701         status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_RX_RING_SIZE, &cmd, 0);
 702         if (status != 0) {
 703                 dev_err(&mgp->pdev->dev,
 704                         "failed MXGEFW_CMD_GET_RX_RING_SIZE\n");
 705                 return -ENXIO;
 706         }
 707
 708         mgp->max_intr_slots = 2 * (cmd.data0 / sizeof(struct mcp_dma_addr));
 709
 710         return 0;
 711 }
 712
 713 static int myri10ge_load_firmware(struct myri10ge_priv *mgp, int adopt)
 714 {
 715         char __iomem *submit;
 716         __be32 buf[16] __attribute__ ((__aligned__(8)));
 717         u32 dma_low, dma_high, size;
 718         int status, i;
 719
 720         size = 0;
 721         status = myri10ge_load_hotplug_firmware(mgp, &size);
 722         if (status) {
 723                 if (!adopt)
 724                         return status;
 725                 dev_warn(&mgp->pdev->dev, "hotplug firmware loading failed\n");
 726
 727                 /* Do not attempt to adopt firmware if there
 728                  * was a bad crc */
 729                 if (status == -EIO)
 730                         return status;
 731
 732                 status = myri10ge_adopt_running_firmware(mgp);
 733                 if (status != 0) {
 734                         dev_err(&mgp->pdev->dev,
 735                                 "failed to adopt running firmware\n");
 736                         return status;
 737                 }
 738                 dev_info(&mgp->pdev->dev,
 739                          "Successfully adopted running firmware\n");
 740                 if (mgp->tx_boundary == 4096) {
 741                         dev_warn(&mgp->pdev->dev,
 742                                  "Using firmware currently running on NIC"
 743                                  ".  For optimal\n");
 744                         dev_warn(&mgp->pdev->dev,
 745                                  "performance consider loading optimized "
 746                                  "firmware\n");
 747                         dev_warn(&mgp->pdev->dev, "via hotplug\n");
 748                 }
 749
 750                 mgp->fw_name = "adopted";
 751                 mgp->tx_boundary = 2048;
 752                 myri10ge_dummy_rdma(mgp, 1);
 753                 status = myri10ge_get_firmware_capabilities(mgp);
 754                 return status;
 755         }
 756
 757         /* clear confirmation addr */
 758         mgp->cmd->data = 0;
 759         mb();
 760
 761         /* send a reload command to the bootstrap MCP, and wait for the
 762          *  response in the confirmation address.  The firmware should
 763          * write a -1 there to indicate it is alive and well
 764          */
 765         dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
 766         dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
 767
 768         buf[0] = htonl(dma_high);       /* confirm addr MSW */
 769         buf[1] = htonl(dma_low);        /* confirm addr LSW */
 770         buf[2] = MYRI10GE_NO_CONFIRM_DATA;      /* confirm data */
 771
 772         /* FIX: All newest firmware should un-protect the bottom of
 773          * the sram before handoff. However, the very first interfaces
 774          * do not. Therefore the handoff copy must skip the first 8 bytes
 775          */
 776         buf[3] = htonl(MYRI10GE_FW_OFFSET + 8); /* where the code starts */
 777         buf[4] = htonl(size - 8);       /* length of code */
 778         buf[5] = htonl(8);      /* where to copy to */
 779         buf[6] = htonl(0);      /* where to jump to */
 780
 781         submit = mgp->sram + MXGEFW_BOOT_HANDOFF;
 782
 783         myri10ge_pio_copy(submit, &buf, sizeof(buf));
 784         mb();
 785         msleep(1);
 786         mb();
 787         i = 0;
 788         while (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 9) {
 789                 msleep(1 << i);
 790                 i++;
 791         }
 792         if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA) {
 793                 dev_err(&mgp->pdev->dev, "handoff failed\n");
 794                 return -ENXIO;
 795         }
 796         myri10ge_dummy_rdma(mgp, 1);
 797         status = myri10ge_get_firmware_capabilities(mgp);
 798
 799         return status;
 800 }
 801
 802 static int myri10ge_update_mac_address(struct myri10ge_priv *mgp, u8 * addr)
 803 {
 804         struct myri10ge_cmd cmd;
 805         int status;
 806
 807         cmd.data0 = ((addr[0] << 24) | (addr[1] << 16)
 808                      | (addr[2] << 8) | addr[3]);
 809
 810         cmd.data1 = ((addr[4] << 8) | (addr[5]));
 811
 812         status = myri10ge_send_cmd(mgp, MXGEFW_SET_MAC_ADDRESS, &cmd, 0);
 813         return status;
 814 }
 815
 816 static int myri10ge_change_pause(struct myri10ge_priv *mgp, int pause)
 817 {
 818         struct myri10ge_cmd cmd;
 819         int status, ctl;
 820
 821         ctl = pause ? MXGEFW_ENABLE_FLOW_CONTROL : MXGEFW_DISABLE_FLOW_CONTROL;
 822         status = myri10ge_send_cmd(mgp, ctl, &cmd, 0);
 823
 824         if (status) {
 825                 netdev_err(mgp->dev, "Failed to set flow control mode\n");
 826                 return status;
 827         }
 828         mgp->pause = pause;
 829         return 0;
 830 }
 831
 832 static void
 833 myri10ge_change_promisc(struct myri10ge_priv *mgp, int promisc, int atomic)
 834 {
 835         struct myri10ge_cmd cmd;
 836         int status, ctl;
 837
 838         ctl = promisc ? MXGEFW_ENABLE_PROMISC : MXGEFW_DISABLE_PROMISC;
 839         status = myri10ge_send_cmd(mgp, ctl, &cmd, atomic);
 840         if (status)
 841                 netdev_err(mgp->dev, "Failed to set promisc mode\n");
 842 }
 843
 844 static int myri10ge_dma_test(struct myri10ge_priv *mgp, int test_type)
 845 {
 846         struct myri10ge_cmd cmd;
 847         int status;
 848         u32 len;
 849         struct page *dmatest_page;
 850         dma_addr_t dmatest_bus;
 851         char *test = " ";
 852
 853         dmatest_page = alloc_page(GFP_KERNEL);
 854         if (!dmatest_page)
 855                 return -ENOMEM;
 856         dmatest_bus = pci_map_page(mgp->pdev, dmatest_page, 0, PAGE_SIZE,
 857                                    DMA_BIDIRECTIONAL);
 858
 859         /* Run a small DMA test.
 860          * The magic multipliers to the length tell the firmware
 861          * to do DMA read, write, or read+write tests.  The
 862          * results are returned in cmd.data0.  The upper 16
 863          * bits or the return is the number of transfers completed.
 864          * The lower 16 bits is the time in 0.5us ticks that the
 865          * transfers took to complete.
 866          */
 867
 868         len = mgp->tx_boundary;
 869
 870         cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
 871         cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
 872         cmd.data2 = len * 0x10000;
 873         status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
 874         if (status != 0) {
 875                 test = "read";
 876                 goto abort;
 877         }
 878         mgp->read_dma = ((cmd.data0 >> 16) * len * 2) / (cmd.data0 & 0xffff);
 879         cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
 880         cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
 881         cmd.data2 = len * 0x1;
 882         status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
 883         if (status != 0) {
 884                 test = "write";
 885                 goto abort;
 886         }
 887         mgp->write_dma = ((cmd.data0 >> 16) * len * 2) / (cmd.data0 & 0xffff);
 888
 889         cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
 890         cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
 891         cmd.data2 = len * 0x10001;
 892         status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
 893         if (status != 0) {
 894                 test = "read/write";
 895                 goto abort;
 896         }
 897         mgp->read_write_dma = ((cmd.data0 >> 16) * len * 2 * 2) /
 898             (cmd.data0 & 0xffff);
 899
 900 abort:
 901         pci_unmap_page(mgp->pdev, dmatest_bus, PAGE_SIZE, DMA_BIDIRECTIONAL);
 902         put_page(dmatest_page);
 903
 904         if (status != 0 && test_type != MXGEFW_CMD_UNALIGNED_TEST)
 905                 dev_warn(&mgp->pdev->dev, "DMA %s benchmark failed: %d\n",
 906                          test, status);
 907
 908         return status;
 909 }
 910
 911 static int myri10ge_reset(struct myri10ge_priv *mgp)
 912 {
 913         struct myri10ge_cmd cmd;
 914         struct myri10ge_slice_state *ss;
 915         int i, status;
 916         size_t bytes;
 917 #ifdef CONFIG_MYRI10GE_DCA
 918         unsigned long dca_tag_off;
 919 #endif
 920
 921         /* try to send a reset command to the card to see if it
 922          * is alive */
 923         memset(&cmd, 0, sizeof(cmd));
 924         status = myri10ge_send_cmd(mgp, MXGEFW_CMD_RESET, &cmd, 0);
 925         if (status != 0) {
 926                 dev_err(&mgp->pdev->dev, "failed reset\n");
 927                 return -ENXIO;
 928         }
 929
 930         (void)myri10ge_dma_test(mgp, MXGEFW_DMA_TEST);
 931         /*
 932          * Use non-ndis mcp_slot (eg, 4 bytes total,
 933          * no toeplitz hash value returned.  Older firmware will
 934          * not understand this command, but will use the correct
 935          * sized mcp_slot, so we ignore error returns
 936          */
 937         cmd.data0 = MXGEFW_RSS_MCP_SLOT_TYPE_MIN;
 938         (void)myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_RSS_MCP_SLOT_TYPE, &cmd, 0);
 939
 940         /* Now exchange information about interrupts  */
 941
 942         bytes = mgp->max_intr_slots * sizeof(*mgp->ss[0].rx_done.entry);
 943         cmd.data0 = (u32) bytes;
 944         status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_SIZE, &cmd, 0);
 945
 946         /*
 947          * Even though we already know how many slices are supported
 948          * via myri10ge_probe_slices() MXGEFW_CMD_GET_MAX_RSS_QUEUES
 949          * has magic side effects, and must be called after a reset.
 950          * It must be called prior to calling any RSS related cmds,
 951          * including assigning an interrupt queue for anything but
 952          * slice 0.  It must also be called *after*
 953          * MXGEFW_CMD_SET_INTRQ_SIZE, since the intrq size is used by
 954          * the firmware to compute offsets.
 955          */
 956
 957         if (mgp->num_slices > 1) {
 958
 959                 /* ask the maximum number of slices it supports */
 960                 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_MAX_RSS_QUEUES,
 961                                            &cmd, 0);
 962                 if (status != 0) {
 963                         dev_err(&mgp->pdev->dev,
 964                                 "failed to get number of slices\n");
 965                 }
 966
 967                 /*
 968                  * MXGEFW_CMD_ENABLE_RSS_QUEUES must be called prior
 969                  * to setting up the interrupt queue DMA
 970                  */
 971
 972                 cmd.data0 = mgp->num_slices;
 973                 cmd.data1 = MXGEFW_SLICE_INTR_MODE_ONE_PER_SLICE;
 974                 if (mgp->dev->real_num_tx_queues > 1)
 975                         cmd.data1 |= MXGEFW_SLICE_ENABLE_MULTIPLE_TX_QUEUES;
 976                 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ENABLE_RSS_QUEUES,
 977                                            &cmd, 0);
 978
 979                 /* Firmware older than 1.4.32 only supports multiple
 980                  * RX queues, so if we get an error, first retry using a
 981                  * single TX queue before giving up */
 982                 if (status != 0 && mgp->dev->real_num_tx_queues > 1) {
 983                         mgp->dev->real_num_tx_queues = 1;
 984                         cmd.data0 = mgp->num_slices;
 985                         cmd.data1 = MXGEFW_SLICE_INTR_MODE_ONE_PER_SLICE;
 986                         status = myri10ge_send_cmd(mgp,
 987                                                    MXGEFW_CMD_ENABLE_RSS_QUEUES,
 988                                                    &cmd, 0);
 989                 }
 990
 991                 if (status != 0) {
 992                         dev_err(&mgp->pdev->dev,
 993                                 "failed to set number of slices\n");
 994
 995                         return status;
 996                 }
 997         }
 998         for (i = 0; i < mgp->num_slices; i++) {
 999                 ss = &mgp->ss[i];
1000                 cmd.data0 = MYRI10GE_LOWPART_TO_U32(ss->rx_done.bus);
1001                 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(ss->rx_done.bus);
1002                 cmd.data2 = i;
1003                 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_DMA,
1004                                             &cmd, 0);
1005         };
1006
1007         status |=
1008             myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_ACK_OFFSET, &cmd, 0);
1009         for (i = 0; i < mgp->num_slices; i++) {
1010                 ss = &mgp->ss[i];
1011                 ss->irq_claim =
1012                     (__iomem __be32 *) (mgp->sram + cmd.data0 + 8 * i);
1013         }
1014         status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_DEASSERT_OFFSET,
1015                                     &cmd, 0);
1016         mgp->irq_deassert = (__iomem __be32 *) (mgp->sram + cmd.data0);
1017
1018         status |= myri10ge_send_cmd
1019             (mgp, MXGEFW_CMD_GET_INTR_COAL_DELAY_OFFSET, &cmd, 0);
1020         mgp->intr_coal_delay_ptr = (__iomem __be32 *) (mgp->sram + cmd.data0);
1021         if (status != 0) {
1022                 dev_err(&mgp->pdev->dev, "failed set interrupt parameters\n");
1023                 return status;
1024         }
1025         put_be32(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
1026
1027 #ifdef CONFIG_MYRI10GE_DCA
1028         status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_DCA_OFFSET, &cmd, 0);
1029         dca_tag_off = cmd.data0;
1030         for (i = 0; i < mgp->num_slices; i++) {
1031                 ss = &mgp->ss[i];
1032                 if (status == 0) {
1033                         ss->dca_tag = (__iomem __be32 *)
1034                             (mgp->sram + dca_tag_off + 4 * i);
1035                 } else {
1036                         ss->dca_tag = NULL;
1037                 }
1038         }
1039 #endif                          /* CONFIG_MYRI10GE_DCA */
1040
1041         /* reset mcp/driver shared state back to 0 */
1042
1043         mgp->link_changes = 0;
1044         for (i = 0; i < mgp->num_slices; i++) {
1045                 ss = &mgp->ss[i];
1046
1047                 memset(ss->rx_done.entry, 0, bytes);
1048                 ss->tx.req = 0;
1049                 ss->tx.done = 0;
1050                 ss->tx.pkt_start = 0;
1051                 ss->tx.pkt_done = 0;
1052                 ss->rx_big.cnt = 0;
1053                 ss->rx_small.cnt = 0;
1054                 ss->rx_done.idx = 0;
1055                 ss->rx_done.cnt = 0;
1056                 ss->tx.wake_queue = 0;
1057                 ss->tx.stop_queue = 0;
1058         }
1059
1060         status = myri10ge_update_mac_address(mgp, mgp->dev->dev_addr);
1061         myri10ge_change_pause(mgp, mgp->pause);
1062         myri10ge_set_multicast_list(mgp->dev);
1063         return status;
1064 }
1065
1066 #ifdef CONFIG_MYRI10GE_DCA
1067 static void
1068 myri10ge_write_dca(struct myri10ge_slice_state *ss, int cpu, int tag)
1069 {
1070         ss->cpu = cpu;
1071         ss->cached_dca_tag = tag;
1072         put_be32(htonl(tag), ss->dca_tag);
1073 }
1074
1075 static inline void myri10ge_update_dca(struct myri10ge_slice_state *ss)
1076 {
1077         int cpu = get_cpu();
1078         int tag;
1079
1080         if (cpu != ss->cpu) {
1081                 tag = dca_get_tag(cpu);
1082                 if (ss->cached_dca_tag != tag)
1083                         myri10ge_write_dca(ss, cpu, tag);
1084         }
1085         put_cpu();
1086 }
1087
1088 static void myri10ge_setup_dca(struct myri10ge_priv *mgp)
1089 {
1090         int err, i;
1091         struct pci_dev *pdev = mgp->pdev;
1092
1093         if (mgp->ss[0].dca_tag == NULL || mgp->dca_enabled)
1094                 return;
1095         if (!myri10ge_dca) {
1096                 dev_err(&pdev->dev, "dca disabled by administrator\n");
1097                 return;
1098         }
1099         err = dca_add_requester(&pdev->dev);
1100         if (err) {
1101                 if (err != -ENODEV)
1102                         dev_err(&pdev->dev,
1103                                 "dca_add_requester() failed, err=%d\n", err);
1104                 return;
1105         }
1106         mgp->dca_enabled = 1;
1107         for (i = 0; i < mgp->num_slices; i++)
1108                 myri10ge_write_dca(&mgp->ss[i], -1, 0);
1109 }
1110
1111 static void myri10ge_teardown_dca(struct myri10ge_priv *mgp)
1112 {
1113         struct pci_dev *pdev = mgp->pdev;
1114         int err;
1115
1116         if (!mgp->dca_enabled)
1117                 return;
1118         mgp->dca_enabled = 0;
1119         err = dca_remove_requester(&pdev->dev);
1120 }
1121
1122 static int myri10ge_notify_dca_device(struct device *dev, void *data)
1123 {
1124         struct myri10ge_priv *mgp;
1125         unsigned long event;
1126
1127         mgp = dev_get_drvdata(dev);
1128         event = *(unsigned long *)data;
1129
1130         if (event == DCA_PROVIDER_ADD)
1131                 myri10ge_setup_dca(mgp);
1132         else if (event == DCA_PROVIDER_REMOVE)
1133                 myri10ge_teardown_dca(mgp);
1134         return 0;
1135 }
1136 #endif                          /* CONFIG_MYRI10GE_DCA */
1137
1138 static inline void
1139 myri10ge_submit_8rx(struct mcp_kreq_ether_recv __iomem * dst,
1140                     struct mcp_kreq_ether_recv *src)
1141 {
1142         __be32 low;
1143
1144         low = src->addr_low;
1145         src->addr_low = htonl(DMA_BIT_MASK(32));
1146         myri10ge_pio_copy(dst, src, 4 * sizeof(*src));
1147         mb();
1148         myri10ge_pio_copy(dst + 4, src + 4, 4 * sizeof(*src));
1149         mb();
1150         src->addr_low = low;
1151         put_be32(low, &dst->addr_low);
1152         mb();
1153 }
1154
1155 static inline void myri10ge_vlan_ip_csum(struct sk_buff *skb, __wsum hw_csum)
1156 {
1157         struct vlan_hdr *vh = (struct vlan_hdr *)(skb->data);
1158
1159         if ((skb->protocol == htons(ETH_P_8021Q)) &&
1160             (vh->h_vlan_encapsulated_proto == htons(ETH_P_IP) ||
1161              vh->h_vlan_encapsulated_proto == htons(ETH_P_IPV6))) {
1162                 skb->csum = hw_csum;
1163                 skb->ip_summed = CHECKSUM_COMPLETE;
1164         }
1165 }
1166
1167 static inline void
1168 myri10ge_rx_skb_build(struct sk_buff *skb, u8 * va,
1169                       struct skb_frag_struct *rx_frags, int len, int hlen)
1170 {
1171         struct skb_frag_struct *skb_frags;
1172
1173         skb->len = skb->data_len = len;
1174         skb->truesize = len + sizeof(struct sk_buff);
1175         /* attach the page(s) */
1176
1177         skb_frags = skb_shinfo(skb)->frags;
1178         while (len > 0) {
1179                 memcpy(skb_frags, rx_frags, sizeof(*skb_frags));
1180                 len -= rx_frags->size;
1181                 skb_frags++;
1182                 rx_frags++;
1183                 skb_shinfo(skb)->nr_frags++;
1184         }
1185
1186         /* pskb_may_pull is not available in irq context, but
1187          * skb_pull() (for ether_pad and eth_type_trans()) requires
1188          * the beginning of the packet in skb_headlen(), move it
1189          * manually */
1190         skb_copy_to_linear_data(skb, va, hlen);
1191         skb_shinfo(skb)->frags[0].page_offset += hlen;
1192         skb_shinfo(skb)->frags[0].size -= hlen;
1193         skb->data_len -= hlen;
1194         skb->tail += hlen;
1195         skb_pull(skb, MXGEFW_PAD);
1196 }
1197
1198 static void
1199 myri10ge_alloc_rx_pages(struct myri10ge_priv *mgp, struct myri10ge_rx_buf *rx,
1200                         int bytes, int watchdog)
1201 {
1202         struct page *page;
1203         int idx;
1204 #if MYRI10GE_ALLOC_SIZE > 4096
1205         int end_offset;
1206 #endif
1207
1208         if (unlikely(rx->watchdog_needed && !watchdog))
1209                 return;
1210
1211         /* try to refill entire ring */
1212         while (rx->fill_cnt != (rx->cnt + rx->mask + 1)) {
1213                 idx = rx->fill_cnt & rx->mask;
1214                 if (rx->page_offset + bytes <= MYRI10GE_ALLOC_SIZE) {
1215                         /* we can use part of previous page */
1216                         get_page(rx->page);
1217                 } else {
1218                         /* we need a new page */
1219                         page =
1220                             alloc_pages(GFP_ATOMIC | __GFP_COMP,
1221                                         MYRI10GE_ALLOC_ORDER);
1222                         if (unlikely(page == NULL)) {
1223                                 if (rx->fill_cnt - rx->cnt < 16)
1224                                         rx->watchdog_needed = 1;
1225                                 return;
1226                         }
1227                         rx->page = page;
1228                         rx->page_offset = 0;
1229                         rx->bus = pci_map_page(mgp->pdev, page, 0,
1230                                                MYRI10GE_ALLOC_SIZE,
1231                                                PCI_DMA_FROMDEVICE);
1232                 }
1233                 rx->info[idx].page = rx->page;
1234                 rx->info[idx].page_offset = rx->page_offset;
1235                 /* note that this is the address of the start of the
1236                  * page */
1237                 pci_unmap_addr_set(&rx->info[idx], bus, rx->bus);
1238                 rx->shadow[idx].addr_low =
1239                     htonl(MYRI10GE_LOWPART_TO_U32(rx->bus) + rx->page_offset);
1240                 rx->shadow[idx].addr_high =
1241                     htonl(MYRI10GE_HIGHPART_TO_U32(rx->bus));
1242
1243                 /* start next packet on a cacheline boundary */
1244                 rx->page_offset += SKB_DATA_ALIGN(bytes);
1245
1246 #if MYRI10GE_ALLOC_SIZE > 4096
1247                 /* don't cross a 4KB boundary */
1248                 end_offset = rx->page_offset + bytes - 1;
1249                 if ((unsigned)(rx->page_offset ^ end_offset) > 4095)
1250                         rx->page_offset = end_offset & ~4095;
1251 #endif
1252                 rx->fill_cnt++;
1253
1254                 /* copy 8 descriptors to the firmware at a time */
1255                 if ((idx & 7) == 7) {
1256                         myri10ge_submit_8rx(&rx->lanai[idx - 7],
1257                                             &rx->shadow[idx - 7]);
1258                 }
1259         }
1260 }
1261
1262 static inline void
1263 myri10ge_unmap_rx_page(struct pci_dev *pdev,
1264                        struct myri10ge_rx_buffer_state *info, int bytes)
1265 {
1266         /* unmap the recvd page if we're the only or last user of it */
1267         if (bytes >= MYRI10GE_ALLOC_SIZE / 2 ||
1268             (info->page_offset + 2 * bytes) > MYRI10GE_ALLOC_SIZE) {
1269                 pci_unmap_page(pdev, (pci_unmap_addr(info, bus)
1270                                       & ~(MYRI10GE_ALLOC_SIZE - 1)),
1271                                MYRI10GE_ALLOC_SIZE, PCI_DMA_FROMDEVICE);
1272         }
1273 }
1274
1275 #define MYRI10GE_HLEN 64        /* The number of bytes to copy from a
1276                                  * page into an skb */
1277
1278 static inline int
1279 myri10ge_rx_done(struct myri10ge_slice_state *ss, struct myri10ge_rx_buf *rx,
1280                  int bytes, int len, __wsum csum)
1281 {
1282         struct myri10ge_priv *mgp = ss->mgp;
1283         struct sk_buff *skb;
1284         struct skb_frag_struct rx_frags[MYRI10GE_MAX_FRAGS_PER_FRAME];
1285         int i, idx, hlen, remainder;
1286         struct pci_dev *pdev = mgp->pdev;
1287         struct net_device *dev = mgp->dev;
1288         u8 *va;
1289
1290         len += MXGEFW_PAD;
1291         idx = rx->cnt & rx->mask;
1292         va = page_address(rx->info[idx].page) + rx->info[idx].page_offset;
1293         prefetch(va);
1294         /* Fill skb_frag_struct(s) with data from our receive */
1295         for (i = 0, remainder = len; remainder > 0; i++) {
1296                 myri10ge_unmap_rx_page(pdev, &rx->info[idx], bytes);
1297                 rx_frags[i].page = rx->info[idx].page;
1298                 rx_frags[i].page_offset = rx->info[idx].page_offset;
1299                 if (remainder < MYRI10GE_ALLOC_SIZE)
1300                         rx_frags[i].size = remainder;
1301                 else
1302                         rx_frags[i].size = MYRI10GE_ALLOC_SIZE;
1303                 rx->cnt++;
1304                 idx = rx->cnt & rx->mask;
1305                 remainder -= MYRI10GE_ALLOC_SIZE;
1306         }
1307
1308         if (dev->features & NETIF_F_LRO) {
1309                 rx_frags[0].page_offset += MXGEFW_PAD;
1310                 rx_frags[0].size -= MXGEFW_PAD;
1311                 len -= MXGEFW_PAD;
1312                 lro_receive_frags(&ss->rx_done.lro_mgr, rx_frags,
1313                                   /* opaque, will come back in get_frag_header */
1314                                   len, len,
1315                                   (void *)(__force unsigned long)csum, csum);
1316
1317                 return 1;
1318         }
1319
1320         hlen = MYRI10GE_HLEN > len ? len : MYRI10GE_HLEN;
1321
1322         /* allocate an skb to attach the page(s) to. This is done
1323          * after trying LRO, so as to avoid skb allocation overheads */
1324
1325         skb = netdev_alloc_skb(dev, MYRI10GE_HLEN + 16);
1326         if (unlikely(skb == NULL)) {
1327                 ss->stats.rx_dropped++;
1328                 do {
1329                         i--;
1330                         put_page(rx_frags[i].page);
1331                 } while (i != 0);
1332                 return 0;
1333         }
1334
1335         /* Attach the pages to the skb, and trim off any padding */
1336         myri10ge_rx_skb_build(skb, va, rx_frags, len, hlen);
1337         if (skb_shinfo(skb)->frags[0].size <= 0) {
1338                 put_page(skb_shinfo(skb)->frags[0].page);
1339                 skb_shinfo(skb)->nr_frags = 0;
1340         }
1341         skb->protocol = eth_type_trans(skb, dev);
1342         skb_record_rx_queue(skb, ss - &mgp->ss[0]);
1343
1344         if (mgp->csum_flag) {
1345                 if ((skb->protocol == htons(ETH_P_IP)) ||
1346                     (skb->protocol == htons(ETH_P_IPV6))) {
1347                         skb->csum = csum;
1348                         skb->ip_summed = CHECKSUM_COMPLETE;
1349                 } else
1350                         myri10ge_vlan_ip_csum(skb, csum);
1351         }
1352         netif_receive_skb(skb);
1353         return 1;
1354 }
1355
1356 static inline void
1357 myri10ge_tx_done(struct myri10ge_slice_state *ss, int mcp_index)
1358 {
1359         struct pci_dev *pdev = ss->mgp->pdev;
1360         struct myri10ge_tx_buf *tx = &ss->tx;
1361         struct netdev_queue *dev_queue;
1362         struct sk_buff *skb;
1363         int idx, len;
1364
1365         while (tx->pkt_done != mcp_index) {
1366                 idx = tx->done & tx->mask;
1367                 skb = tx->info[idx].skb;
1368
1369                 /* Mark as free */
1370                 tx->info[idx].skb = NULL;
1371                 if (tx->info[idx].last) {
1372                         tx->pkt_done++;
1373                         tx->info[idx].last = 0;
1374                 }
1375                 tx->done++;
1376                 len = pci_unmap_len(&tx->info[idx], len);
1377                 pci_unmap_len_set(&tx->info[idx], len, 0);
1378                 if (skb) {
1379                         ss->stats.tx_bytes += skb->len;
1380                         ss->stats.tx_packets++;
1381                         dev_kfree_skb_irq(skb);
1382                         if (len)
1383                                 pci_unmap_single(pdev,
1384                                                  pci_unmap_addr(&tx->info[idx],
1385                                                                 bus), len,
1386                                                  PCI_DMA_TODEVICE);
1387                 } else {
1388                         if (len)
1389                                 pci_unmap_page(pdev,
1390                                                pci_unmap_addr(&tx->info[idx],
1391                                                               bus), len,
1392                                                PCI_DMA_TODEVICE);
1393                 }
1394         }
1395
1396         dev_queue = netdev_get_tx_queue(ss->dev, ss - ss->mgp->ss);
1397         /*
1398          * Make a minimal effort to prevent the NIC from polling an
1399          * idle tx queue.  If we can't get the lock we leave the queue
1400          * active. In this case, either a thread was about to start
1401          * using the queue anyway, or we lost a race and the NIC will
1402          * waste some of its resources polling an inactive queue for a
1403          * while.
1404          */
1405
1406         if ((ss->mgp->dev->real_num_tx_queues > 1) &&
1407             __netif_tx_trylock(dev_queue)) {
1408                 if (tx->req == tx->done) {
1409                         tx->queue_active = 0;
1410                         put_be32(htonl(1), tx->send_stop);
1411                         mb();
1412                         mmiowb();
1413                 }
1414                 __netif_tx_unlock(dev_queue);
1415         }
1416
1417         /* start the queue if we've stopped it */
1418         if (netif_tx_queue_stopped(dev_queue) &&
1419             tx->req - tx->done < (tx->mask >> 1)) {
1420                 tx->wake_queue++;
1421                 netif_tx_wake_queue(dev_queue);
1422         }
1423 }
1424
1425 static inline int
1426 myri10ge_clean_rx_done(struct myri10ge_slice_state *ss, int budget)
1427 {
1428         struct myri10ge_rx_done *rx_done = &ss->rx_done;
1429         struct myri10ge_priv *mgp = ss->mgp;
1430         struct net_device *netdev = mgp->dev;
1431         unsigned long rx_bytes = 0;
1432         unsigned long rx_packets = 0;
1433         unsigned long rx_ok;
1434
1435         int idx = rx_done->idx;
1436         int cnt = rx_done->cnt;
1437         int work_done = 0;
1438         u16 length;
1439         __wsum checksum;
1440
1441         while (rx_done->entry[idx].length != 0 && work_done < budget) {
1442                 length = ntohs(rx_done->entry[idx].length);
1443                 rx_done->entry[idx].length = 0;
1444                 checksum = csum_unfold(rx_done->entry[idx].checksum);
1445                 if (length <= mgp->small_bytes)
1446                         rx_ok = myri10ge_rx_done(ss, &ss->rx_small,
1447                                                  mgp->small_bytes,
1448                                                  length, checksum);
1449                 else
1450                         rx_ok = myri10ge_rx_done(ss, &ss->rx_big,
1451                                                  mgp->big_bytes,
1452                                                  length, checksum);
1453                 rx_packets += rx_ok;
1454                 rx_bytes += rx_ok * (unsigned long)length;
1455                 cnt++;
1456                 idx = cnt & (mgp->max_intr_slots - 1);
1457                 work_done++;
1458         }
1459         rx_done->idx = idx;
1460         rx_done->cnt = cnt;
1461         ss->stats.rx_packets += rx_packets;
1462         ss->stats.rx_bytes += rx_bytes;
1463
1464         if (netdev->features & NETIF_F_LRO)
1465                 lro_flush_all(&rx_done->lro_mgr);
1466
1467         /* restock receive rings if needed */
1468         if (ss->rx_small.fill_cnt - ss->rx_small.cnt < myri10ge_fill_thresh)
1469                 myri10ge_alloc_rx_pages(mgp, &ss->rx_small,
1470                                         mgp->small_bytes + MXGEFW_PAD, 0);
1471         if (ss->rx_big.fill_cnt - ss->rx_big.cnt < myri10ge_fill_thresh)
1472                 myri10ge_alloc_rx_pages(mgp, &ss->rx_big, mgp->big_bytes, 0);
1473
1474         return work_done;
1475 }
1476
1477 static inline void myri10ge_check_statblock(struct myri10ge_priv *mgp)
1478 {
1479         struct mcp_irq_data *stats = mgp->ss[0].fw_stats;
1480
1481         if (unlikely(stats->stats_updated)) {
1482                 unsigned link_up = ntohl(stats->link_up);
1483                 if (mgp->link_state != link_up) {
1484                         mgp->link_state = link_up;
1485
1486                         if (mgp->link_state == MXGEFW_LINK_UP) {
1487                                 if (netif_msg_link(mgp))
1488                                         netdev_info(mgp->dev, "link up\n");
1489                                 netif_carrier_on(mgp->dev);
1490                                 mgp->link_changes++;
1491                         } else {
1492                                 if (netif_msg_link(mgp))
1493                                         netdev_info(mgp->dev, "link %s\n",
1494                                             link_up == MXGEFW_LINK_MYRINET ?
1495                                             "mismatch (Myrinet detected)" :
1496                                             "down");
1497                                 netif_carrier_off(mgp->dev);
1498                                 mgp->link_changes++;
1499                         }
1500                 }
1501                 if (mgp->rdma_tags_available !=
1502                     ntohl(stats->rdma_tags_available)) {
1503                         mgp->rdma_tags_available =
1504                             ntohl(stats->rdma_tags_available);
1505                         netdev_warn(mgp->dev, "RDMA timed out! %d tags left\n",
1506                                     mgp->rdma_tags_available);
1507                 }
1508                 mgp->down_cnt += stats->link_down;
1509                 if (stats->link_down)
1510                         wake_up(&mgp->down_wq);
1511         }
1512 }
1513
1514 static int myri10ge_poll(struct napi_struct *napi, int budget)
1515 {
1516         struct myri10ge_slice_state *ss =
1517             container_of(napi, struct myri10ge_slice_state, napi);
1518         int work_done;
1519
1520 #ifdef CONFIG_MYRI10GE_DCA
1521         if (ss->mgp->dca_enabled)
1522                 myri10ge_update_dca(ss);
1523 #endif
1524
1525         /* process as many rx events as NAPI will allow */
1526         work_done = myri10ge_clean_rx_done(ss, budget);
1527
1528         if (work_done < budget) {
1529                 napi_complete(napi);
1530                 put_be32(htonl(3), ss->irq_claim);
1531         }
1532         return work_done;
1533 }
1534
1535 static irqreturn_t myri10ge_intr(int irq, void *arg)
1536 {
1537         struct myri10ge_slice_state *ss = arg;
1538         struct myri10ge_priv *mgp = ss->mgp;
1539         struct mcp_irq_data *stats = ss->fw_stats;
1540         struct myri10ge_tx_buf *tx = &ss->tx;
1541         u32 send_done_count;
1542         int i;
1543
1544         /* an interrupt on a non-zero receive-only slice is implicitly
1545          * valid  since MSI-X irqs are not shared */
1546         if ((mgp->dev->real_num_tx_queues == 1) && (ss != mgp->ss)) {
1547                 napi_schedule(&ss->napi);
1548                 return (IRQ_HANDLED);
1549         }
1550
1551         /* make sure it is our IRQ, and that the DMA has finished */
1552         if (unlikely(!stats->valid))
1553                 return (IRQ_NONE);
1554
1555         /* low bit indicates receives are present, so schedule
1556          * napi poll handler */
1557         if (stats->valid & 1)
1558                 napi_schedule(&ss->napi);
1559
1560         if (!mgp->msi_enabled && !mgp->msix_enabled) {
1561                 put_be32(0, mgp->irq_deassert);
1562                 if (!myri10ge_deassert_wait)
1563                         stats->valid = 0;
1564                 mb();
1565         } else
1566                 stats->valid = 0;
1567
1568         /* Wait for IRQ line to go low, if using INTx */
1569         i = 0;
1570         while (1) {
1571                 i++;
1572                 /* check for transmit completes and receives */
1573                 send_done_count = ntohl(stats->send_done_count);
1574                 if (send_done_count != tx->pkt_done)
1575                         myri10ge_tx_done(ss, (int)send_done_count);
1576                 if (unlikely(i > myri10ge_max_irq_loops)) {
1577                         netdev_err(mgp->dev, "irq stuck?\n");
1578                         stats->valid = 0;
1579                         schedule_work(&mgp->watchdog_work);
1580                 }
1581                 if (likely(stats->valid == 0))
1582                         break;
1583                 cpu_relax();
1584                 barrier();
1585         }
1586
1587         /* Only slice 0 updates stats */
1588         if (ss == mgp->ss)
1589                 myri10ge_check_statblock(mgp);
1590
1591         put_be32(htonl(3), ss->irq_claim + 1);
1592         return (IRQ_HANDLED);
1593 }
1594
1595 static int
1596 myri10ge_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
1597 {
1598         struct myri10ge_priv *mgp = netdev_priv(netdev);
1599         char *ptr;
1600         int i;
1601
1602         cmd->autoneg = AUTONEG_DISABLE;
1603         cmd->speed = SPEED_10000;
1604         cmd->duplex = DUPLEX_FULL;
1605
1606         /*
1607          * parse the product code to deterimine the interface type
1608          * (CX4, XFP, Quad Ribbon Fiber) by looking at the character
1609          * after the 3rd dash in the driver's cached copy of the
1610          * EEPROM's product code string.
1611          */
1612         ptr = mgp->product_code_string;
1613         if (ptr == NULL) {
1614                 netdev_err(netdev, "Missing product code\n");
1615                 return 0;
1616         }
1617         for (i = 0; i < 3; i++, ptr++) {
1618                 ptr = strchr(ptr, '-');
1619                 if (ptr == NULL) {
1620                         netdev_err(netdev, "Invalid product code %s\n",
1621                                    mgp->product_code_string);
1622                         return 0;
1623                 }
1624         }
1625         if (*ptr == '2')
1626                 ptr++;
1627         if (*ptr == 'R' || *ptr == 'Q' || *ptr == 'S') {
1628                 /* We've found either an XFP, quad ribbon fiber, or SFP+ */
1629                 cmd->port = PORT_FIBRE;
1630                 cmd->supported |= SUPPORTED_FIBRE;
1631                 cmd->advertising |= ADVERTISED_FIBRE;
1632         } else {
1633                 cmd->port = PORT_OTHER;
1634         }
1635         if (*ptr == 'R' || *ptr == 'S')
1636                 cmd->transceiver = XCVR_EXTERNAL;
1637         else
1638                 cmd->transceiver = XCVR_INTERNAL;
1639
1640         return 0;
1641 }
1642
1643 static void
1644 myri10ge_get_drvinfo(struct net_device *netdev, struct ethtool_drvinfo *info)
1645 {
1646         struct myri10ge_priv *mgp = netdev_priv(netdev);
1647
1648         strlcpy(info->driver, "myri10ge", sizeof(info->driver));
1649         strlcpy(info->version, MYRI10GE_VERSION_STR, sizeof(info->version));
1650         strlcpy(info->fw_version, mgp->fw_version, sizeof(info->fw_version));
1651         strlcpy(info->bus_info, pci_name(mgp->pdev), sizeof(info->bus_info));
1652 }
1653
1654 static int
1655 myri10ge_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *coal)
1656 {
1657         struct myri10ge_priv *mgp = netdev_priv(netdev);
1658
1659         coal->rx_coalesce_usecs = mgp->intr_coal_delay;
1660         return 0;
1661 }
1662
1663 static int
1664 myri10ge_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *coal)
1665 {
1666         struct myri10ge_priv *mgp = netdev_priv(netdev);
1667
1668         mgp->intr_coal_delay = coal->rx_coalesce_usecs;
1669         put_be32(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
1670         return 0;
1671 }
1672
1673 static void
1674 myri10ge_get_pauseparam(struct net_device *netdev,
1675                         struct ethtool_pauseparam *pause)
1676 {
1677         struct myri10ge_priv *mgp = netdev_priv(netdev);
1678
1679         pause->autoneg = 0;
1680         pause->rx_pause = mgp->pause;
1681         pause->tx_pause = mgp->pause;
1682 }
1683
1684 static int
1685 myri10ge_set_pauseparam(struct net_device *netdev,
1686                         struct ethtool_pauseparam *pause)
1687 {
1688         struct myri10ge_priv *mgp = netdev_priv(netdev);
1689
1690         if (pause->tx_pause != mgp->pause)
1691                 return myri10ge_change_pause(mgp, pause->tx_pause);
1692         if (pause->rx_pause != mgp->pause)
1693                 return myri10ge_change_pause(mgp, pause->rx_pause);
1694         if (pause->autoneg != 0)
1695                 return -EINVAL;
1696         return 0;
1697 }
1698
1699 static void
1700 myri10ge_get_ringparam(struct net_device *netdev,
1701                        struct ethtool_ringparam *ring)
1702 {
1703         struct myri10ge_priv *mgp = netdev_priv(netdev);
1704
1705         ring->rx_mini_max_pending = mgp->ss[0].rx_small.mask + 1;
1706         ring->rx_max_pending = mgp->ss[0].rx_big.mask + 1;
1707         ring->rx_jumbo_max_pending = 0;
1708         ring->tx_max_pending = mgp->ss[0].tx.mask + 1;
1709         ring->rx_mini_pending = ring->rx_mini_max_pending;
1710         ring->rx_pending = ring->rx_max_pending;
1711         ring->rx_jumbo_pending = ring->rx_jumbo_max_pending;
1712         ring->tx_pending = ring->tx_max_pending;
1713 }
1714
1715 static u32 myri10ge_get_rx_csum(struct net_device *netdev)
1716 {
1717         struct myri10ge_priv *mgp = netdev_priv(netdev);
1718
1719         if (mgp->csum_flag)
1720                 return 1;
1721         else
1722                 return 0;
1723 }
1724
1725 static int myri10ge_set_rx_csum(struct net_device *netdev, u32 csum_enabled)
1726 {
1727         struct myri10ge_priv *mgp = netdev_priv(netdev);
1728         int err = 0;
1729
1730         if (csum_enabled)
1731                 mgp->csum_flag = MXGEFW_FLAGS_CKSUM;
1732         else {
1733                 u32 flags = ethtool_op_get_flags(netdev);
1734                 err = ethtool_op_set_flags(netdev, (flags & ~ETH_FLAG_LRO));
1735                 mgp->csum_flag = 0;
1736
1737         }
1738         return err;
1739 }
1740
1741 static int myri10ge_set_tso(struct net_device *netdev, u32 tso_enabled)
1742 {
1743         struct myri10ge_priv *mgp = netdev_priv(netdev);
1744         unsigned long flags = mgp->features & (NETIF_F_TSO6 | NETIF_F_TSO);
1745
1746         if (tso_enabled)
1747                 netdev->features |= flags;
1748         else
1749                 netdev->features &= ~flags;
1750         return 0;
1751 }
1752
1753 static const char myri10ge_gstrings_main_stats[][ETH_GSTRING_LEN] = {
1754         "rx_packets", "tx_packets", "rx_bytes", "tx_bytes", "rx_errors",
1755         "tx_errors", "rx_dropped", "tx_dropped", "multicast", "collisions",
1756         "rx_length_errors", "rx_over_errors", "rx_crc_errors",
1757         "rx_frame_errors", "rx_fifo_errors", "rx_missed_errors",
1758         "tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors",
1759         "tx_heartbeat_errors", "tx_window_errors",
1760         /* device-specific stats */
1761         "tx_boundary", "WC", "irq", "MSI", "MSIX",
1762         "read_dma_bw_MBs", "write_dma_bw_MBs", "read_write_dma_bw_MBs",
1763         "serial_number", "watchdog_resets",
1764 #ifdef CONFIG_MYRI10GE_DCA
1765         "dca_capable_firmware", "dca_device_present",
1766 #endif
1767         "link_changes", "link_up", "dropped_link_overflow",
1768         "dropped_link_error_or_filtered",
1769         "dropped_pause", "dropped_bad_phy", "dropped_bad_crc32",
1770         "dropped_unicast_filtered", "dropped_multicast_filtered",
1771         "dropped_runt", "dropped_overrun", "dropped_no_small_buffer",
1772         "dropped_no_big_buffer"
1773 };
1774
1775 static const char myri10ge_gstrings_slice_stats[][ETH_GSTRING_LEN] = {
1776         "----------- slice ---------",
1777         "tx_pkt_start", "tx_pkt_done", "tx_req", "tx_done",
1778         "rx_small_cnt", "rx_big_cnt",
1779         "wake_queue", "stop_queue", "tx_linearized", "LRO aggregated",
1780             "LRO flushed",
1781         "LRO avg aggr", "LRO no_desc"
1782 };
1783
1784 #define MYRI10GE_NET_STATS_LEN      21
1785 #define MYRI10GE_MAIN_STATS_LEN  ARRAY_SIZE(myri10ge_gstrings_main_stats)
1786 #define MYRI10GE_SLICE_STATS_LEN  ARRAY_SIZE(myri10ge_gstrings_slice_stats)
1787
1788 static void
1789 myri10ge_get_strings(struct net_device *netdev, u32 stringset, u8 * data)
1790 {
1791         struct myri10ge_priv *mgp = netdev_priv(netdev);
1792         int i;
1793
1794         switch (stringset) {
1795         case ETH_SS_STATS:
1796                 memcpy(data, *myri10ge_gstrings_main_stats,
1797                        sizeof(myri10ge_gstrings_main_stats));
1798                 data += sizeof(myri10ge_gstrings_main_stats);
1799                 for (i = 0; i < mgp->num_slices; i++) {
1800                         memcpy(data, *myri10ge_gstrings_slice_stats,
1801                                sizeof(myri10ge_gstrings_slice_stats));
1802                         data += sizeof(myri10ge_gstrings_slice_stats);
1803                 }
1804                 break;
1805         }
1806 }
1807
1808 static int myri10ge_get_sset_count(struct net_device *netdev, int sset)
1809 {
1810         struct myri10ge_priv *mgp = netdev_priv(netdev);
1811
1812         switch (sset) {
1813         case ETH_SS_STATS:
1814                 return MYRI10GE_MAIN_STATS_LEN +
1815                     mgp->num_slices * MYRI10GE_SLICE_STATS_LEN;
1816         default:
1817                 return -EOPNOTSUPP;
1818         }
1819 }
1820
1821 static void
1822 myri10ge_get_ethtool_stats(struct net_device *netdev,
1823                            struct ethtool_stats *stats, u64 * data)
1824 {
1825         struct myri10ge_priv *mgp = netdev_priv(netdev);
1826         struct myri10ge_slice_state *ss;
1827         int slice;
1828         int i;
1829
1830         /* force stats update */
1831         (void)myri10ge_get_stats(netdev);
1832         for (i = 0; i < MYRI10GE_NET_STATS_LEN; i++)
1833                 data[i] = ((unsigned long *)&netdev->stats)[i];
1834
1835         data[i++] = (unsigned int)mgp->tx_boundary;
1836         data[i++] = (unsigned int)mgp->wc_enabled;
1837         data[i++] = (unsigned int)mgp->pdev->irq;
1838         data[i++] = (unsigned int)mgp->msi_enabled;
1839         data[i++] = (unsigned int)mgp->msix_enabled;
1840         data[i++] = (unsigned int)mgp->read_dma;
1841         data[i++] = (unsigned int)mgp->write_dma;
1842         data[i++] = (unsigned int)mgp->read_write_dma;
1843         data[i++] = (unsigned int)mgp->serial_number;
1844         data[i++] = (unsigned int)mgp->watchdog_resets;
1845 #ifdef CONFIG_MYRI10GE_DCA
1846         data[i++] = (unsigned int)(mgp->ss[0].dca_tag != NULL);
1847         data[i++] = (unsigned int)(mgp->dca_enabled);
1848 #endif
1849         data[i++] = (unsigned int)mgp->link_changes;
1850
1851         /* firmware stats are useful only in the first slice */
1852         ss = &mgp->ss[0];
1853         data[i++] = (unsigned int)ntohl(ss->fw_stats->link_up);
1854         data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_link_overflow);
1855         data[i++] =
1856             (unsigned int)ntohl(ss->fw_stats->dropped_link_error_or_filtered);
1857         data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_pause);
1858         data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_bad_phy);
1859         data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_bad_crc32);
1860         data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_unicast_filtered);
1861         data[i++] =
1862             (unsigned int)ntohl(ss->fw_stats->dropped_multicast_filtered);
1863         data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_runt);
1864         data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_overrun);
1865         data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_no_small_buffer);
1866         data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_no_big_buffer);
1867
1868         for (slice = 0; slice < mgp->num_slices; slice++) {
1869                 ss = &mgp->ss[slice];
1870                 data[i++] = slice;
1871                 data[i++] = (unsigned int)ss->tx.pkt_start;
1872                 data[i++] = (unsigned int)ss->tx.pkt_done;
1873                 data[i++] = (unsigned int)ss->tx.req;
1874                 data[i++] = (unsigned int)ss->tx.done;
1875                 data[i++] = (unsigned int)ss->rx_small.cnt;
1876                 data[i++] = (unsigned int)ss->rx_big.cnt;
1877                 data[i++] = (unsigned int)ss->tx.wake_queue;
1878                 data[i++] = (unsigned int)ss->tx.stop_queue;
1879                 data[i++] = (unsigned int)ss->tx.linearized;
1880                 data[i++] = ss->rx_done.lro_mgr.stats.aggregated;
1881                 data[i++] = ss->rx_done.lro_mgr.stats.flushed;
1882                 if (ss->rx_done.lro_mgr.stats.flushed)
1883                         data[i++] = ss->rx_done.lro_mgr.stats.aggregated /
1884                             ss->rx_done.lro_mgr.stats.flushed;
1885                 else
1886                         data[i++] = 0;
1887                 data[i++] = ss->rx_done.lro_mgr.stats.no_desc;
1888         }
1889 }
1890
1891 static void myri10ge_set_msglevel(struct net_device *netdev, u32 value)
1892 {
1893         struct myri10ge_priv *mgp = netdev_priv(netdev);
1894         mgp->msg_enable = value;
1895 }
1896
1897 static u32 myri10ge_get_msglevel(struct net_device *netdev)
1898 {
1899         struct myri10ge_priv *mgp = netdev_priv(netdev);
1900         return mgp->msg_enable;
1901 }
1902
1903 static const struct ethtool_ops myri10ge_ethtool_ops = {
1904         .get_settings = myri10ge_get_settings,
1905         .get_drvinfo = myri10ge_get_drvinfo,
1906         .get_coalesce = myri10ge_get_coalesce,
1907         .set_coalesce = myri10ge_set_coalesce,
1908         .get_pauseparam = myri10ge_get_pauseparam,
1909         .set_pauseparam = myri10ge_set_pauseparam,
1910         .get_ringparam = myri10ge_get_ringparam,
1911         .get_rx_csum = myri10ge_get_rx_csum,
1912         .set_rx_csum = myri10ge_set_rx_csum,
1913         .set_tx_csum = ethtool_op_set_tx_hw_csum,
1914         .set_sg = ethtool_op_set_sg,
1915         .set_tso = myri10ge_set_tso,
1916         .get_link = ethtool_op_get_link,
1917         .get_strings = myri10ge_get_strings,
1918         .get_sset_count = myri10ge_get_sset_count,
1919         .get_ethtool_stats = myri10ge_get_ethtool_stats,
1920         .set_msglevel = myri10ge_set_msglevel,
1921         .get_msglevel = myri10ge_get_msglevel,
1922         .get_flags = ethtool_op_get_flags,
1923         .set_flags = ethtool_op_set_flags
1924 };
1925
1926 static int myri10ge_allocate_rings(struct myri10ge_slice_state *ss)
1927 {
1928         struct myri10ge_priv *mgp = ss->mgp;
1929         struct myri10ge_cmd cmd;
1930         struct net_device *dev = mgp->dev;
1931         int tx_ring_size, rx_ring_size;
1932         int tx_ring_entries, rx_ring_entries;
1933         int i, slice, status;
1934         size_t bytes;
1935
1936         /* get ring sizes */
1937         slice = ss - mgp->ss;
1938         cmd.data0 = slice;
1939         status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_RING_SIZE, &cmd, 0);
1940         tx_ring_size = cmd.data0;
1941         cmd.data0 = slice;
1942         status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_RX_RING_SIZE, &cmd, 0);
1943         if (status != 0)
1944                 return status;
1945         rx_ring_size = cmd.data0;
1946
1947         tx_ring_entries = tx_ring_size / sizeof(struct mcp_kreq_ether_send);
1948         rx_ring_entries = rx_ring_size / sizeof(struct mcp_dma_addr);
1949         ss->tx.mask = tx_ring_entries - 1;
1950         ss->rx_small.mask = ss->rx_big.mask = rx_ring_entries - 1;
1951
1952         status = -ENOMEM;
1953
1954         /* allocate the host shadow rings */
1955
1956         bytes = 8 + (MYRI10GE_MAX_SEND_DESC_TSO + 4)
1957             * sizeof(*ss->tx.req_list);
1958         ss->tx.req_bytes = kzalloc(bytes, GFP_KERNEL);
1959         if (ss->tx.req_bytes == NULL)
1960                 goto abort_with_nothing;
1961
1962         /* ensure req_list entries are aligned to 8 bytes */
1963         ss->tx.req_list = (struct mcp_kreq_ether_send *)
1964             ALIGN((unsigned long)ss->tx.req_bytes, 8);
1965         ss->tx.queue_active = 0;
1966
1967         bytes = rx_ring_entries * sizeof(*ss->rx_small.shadow);
1968         ss->rx_small.shadow = kzalloc(bytes, GFP_KERNEL);
1969         if (ss->rx_small.shadow == NULL)
1970                 goto abort_with_tx_req_bytes;
1971
1972         bytes = rx_ring_entries * sizeof(*ss->rx_big.shadow);
1973         ss->rx_big.shadow = kzalloc(bytes, GFP_KERNEL);
1974         if (ss->rx_big.shadow == NULL)
1975                 goto abort_with_rx_small_shadow;
1976
1977         /* allocate the host info rings */
1978
1979         bytes = tx_ring_entries * sizeof(*ss->tx.info);
1980         ss->tx.info = kzalloc(bytes, GFP_KERNEL);
1981         if (ss->tx.info == NULL)
1982                 goto abort_with_rx_big_shadow;
1983
1984         bytes = rx_ring_entries * sizeof(*ss->rx_small.info);
1985         ss->rx_small.info = kzalloc(bytes, GFP_KERNEL);
1986         if (ss->rx_small.info == NULL)
1987                 goto abort_with_tx_info;
1988
1989         bytes = rx_ring_entries * sizeof(*ss->rx_big.info);
1990         ss->rx_big.info = kzalloc(bytes, GFP_KERNEL);
1991         if (ss->rx_big.info == NULL)
1992                 goto abort_with_rx_small_info;
1993
1994         /* Fill the receive rings */
1995         ss->rx_big.cnt = 0;
1996         ss->rx_small.cnt = 0;
1997         ss->rx_big.fill_cnt = 0;
1998         ss->rx_small.fill_cnt = 0;
1999         ss->rx_small.page_offset = MYRI10GE_ALLOC_SIZE;
2000         ss->rx_big.page_offset = MYRI10GE_ALLOC_SIZE;
2001         ss->rx_small.watchdog_needed = 0;
2002         ss->rx_big.watchdog_needed = 0;
2003         myri10ge_alloc_rx_pages(mgp, &ss->rx_small,
2004                                 mgp->small_bytes + MXGEFW_PAD, 0);
2005
2006         if (ss->rx_small.fill_cnt < ss->rx_small.mask + 1) {
2007                 netdev_err(dev, "slice-%d: alloced only %d small bufs\n",
2008                            slice, ss->rx_small.fill_cnt);
2009                 goto abort_with_rx_small_ring;
2010         }
2011
2012         myri10ge_alloc_rx_pages(mgp, &ss->rx_big, mgp->big_bytes, 0);
2013         if (ss->rx_big.fill_cnt < ss->rx_big.mask + 1) {
2014                 netdev_err(dev, "slice-%d: alloced only %d big bufs\n",
2015                            slice, ss->rx_big.fill_cnt);
2016                 goto abort_with_rx_big_ring;
2017         }
2018
2019         return 0;
2020
2021 abort_with_rx_big_ring:
2022         for (i = ss->rx_big.cnt; i < ss->rx_big.fill_cnt; i++) {
2023                 int idx = i & ss->rx_big.mask;
2024                 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_big.info[idx],
2025                                        mgp->big_bytes);
2026                 put_page(ss->rx_big.info[idx].page);
2027         }
2028
2029 abort_with_rx_small_ring:
2030         for (i = ss->rx_small.cnt; i < ss->rx_small.fill_cnt; i++) {
2031                 int idx = i & ss->rx_small.mask;
2032                 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_small.info[idx],
2033                                        mgp->small_bytes + MXGEFW_PAD);
2034                 put_page(ss->rx_small.info[idx].page);
2035         }
2036
2037         kfree(ss->rx_big.info);
2038
2039 abort_with_rx_small_info:
2040         kfree(ss->rx_small.info);
2041
2042 abort_with_tx_info:
2043         kfree(ss->tx.info);
2044
2045 abort_with_rx_big_shadow:
2046         kfree(ss->rx_big.shadow);
2047
2048 abort_with_rx_small_shadow:
2049         kfree(ss->rx_small.shadow);
2050
2051 abort_with_tx_req_bytes:
2052         kfree(ss->tx.req_bytes);
2053         ss->tx.req_bytes = NULL;
2054         ss->tx.req_list = NULL;
2055
2056 abort_with_nothing:
2057         return status;
2058 }
2059
2060 static void myri10ge_free_rings(struct myri10ge_slice_state *ss)
2061 {
2062         struct myri10ge_priv *mgp = ss->mgp;
2063         struct sk_buff *skb;
2064         struct myri10ge_tx_buf *tx;
2065         int i, len, idx;
2066
2067         /* If not allocated, skip it */
2068         if (ss->tx.req_list == NULL)
2069                 return;
2070
2071         for (i = ss->rx_big.cnt; i < ss->rx_big.fill_cnt; i++) {
2072                 idx = i & ss->rx_big.mask;
2073                 if (i == ss->rx_big.fill_cnt - 1)
2074                         ss->rx_big.info[idx].page_offset = MYRI10GE_ALLOC_SIZE;
2075                 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_big.info[idx],
2076                                        mgp->big_bytes);
2077                 put_page(ss->rx_big.info[idx].page);
2078         }
2079
2080         for (i = ss->rx_small.cnt; i < ss->rx_small.fill_cnt; i++) {
2081                 idx = i & ss->rx_small.mask;
2082                 if (i == ss->rx_small.fill_cnt - 1)
2083                         ss->rx_small.info[idx].page_offset =
2084                             MYRI10GE_ALLOC_SIZE;
2085                 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_small.info[idx],
2086                                        mgp->small_bytes + MXGEFW_PAD);
2087                 put_page(ss->rx_small.info[idx].page);
2088         }
2089         tx = &ss->tx;
2090         while (tx->done != tx->req) {
2091                 idx = tx->done & tx->mask;
2092                 skb = tx->info[idx].skb;
2093
2094                 /* Mark as free */
2095                 tx->info[idx].skb = NULL;
2096                 tx->done++;
2097                 len = pci_unmap_len(&tx->info[idx], len);
2098                 pci_unmap_len_set(&tx->info[idx], len, 0);
2099                 if (skb) {
2100                         ss->stats.tx_dropped++;
2101                         dev_kfree_skb_any(skb);
2102                         if (len)
2103                                 pci_unmap_single(mgp->pdev,
2104                                                  pci_unmap_addr(&tx->info[idx],
2105                                                                 bus), len,
2106                                                  PCI_DMA_TODEVICE);
2107                 } else {
2108                         if (len)
2109                                 pci_unmap_page(mgp->pdev,
2110                                                pci_unmap_addr(&tx->info[idx],
2111                                                               bus), len,
2112                                                PCI_DMA_TODEVICE);
2113                 }
2114         }
2115         kfree(ss->rx_big.info);
2116
2117         kfree(ss->rx_small.info);
2118
2119         kfree(ss->tx.info);
2120
2121         kfree(ss->rx_big.shadow);
2122
2123         kfree(ss->rx_small.shadow);
2124
2125         kfree(ss->tx.req_bytes);
2126         ss->tx.req_bytes = NULL;
2127         ss->tx.req_list = NULL;
2128 }
2129
2130 static int myri10ge_request_irq(struct myri10ge_priv *mgp)
2131 {
2132         struct pci_dev *pdev = mgp->pdev;
2133         struct myri10ge_slice_state *ss;
2134         struct net_device *netdev = mgp->dev;
2135         int i;
2136         int status;
2137
2138         mgp->msi_enabled = 0;
2139         mgp->msix_enabled = 0;
2140         status = 0;
2141         if (myri10ge_msi) {
2142                 if (mgp->num_slices > 1) {
2143                         status =
2144                             pci_enable_msix(pdev, mgp->msix_vectors,
2145                                             mgp->num_slices);
2146                         if (status == 0) {
2147                                 mgp->msix_enabled = 1;
2148                         } else {
2149                                 dev_err(&pdev->dev,
2150                                         "Error %d setting up MSI-X\n", status);
2151                                 return status;
2152                         }
2153                 }
2154                 if (mgp->msix_enabled == 0) {
2155                         status = pci_enable_msi(pdev);
2156                         if (status != 0) {
2157                                 dev_err(&pdev->dev,
2158                                         "Error %d setting up MSI; falling back to xPIC\n",
2159                                         status);
2160                         } else {
2161                                 mgp->msi_enabled = 1;
2162                         }
2163                 }
2164         }
2165         if (mgp->msix_enabled) {
2166                 for (i = 0; i < mgp->num_slices; i++) {
2167                         ss = &mgp->ss[i];
2168                         snprintf(ss->irq_desc, sizeof(ss->irq_desc),
2169                                  "%s:slice-%d", netdev->name, i);
2170                         status = request_irq(mgp->msix_vectors[i].vector,
2171                                              myri10ge_intr, 0, ss->irq_desc,
2172                                              ss);
2173                         if (status != 0) {
2174                                 dev_err(&pdev->dev,
2175                                         "slice %d failed to allocate IRQ\n", i);
2176                                 i--;
2177                                 while (i >= 0) {
2178                                         free_irq(mgp->msix_vectors[i].vector,
2179                                                  &mgp->ss[i]);
2180                                         i--;
2181                                 }
2182                                 pci_disable_msix(pdev);
2183                                 return status;
2184                         }
2185                 }
2186         } else {
2187                 status = request_irq(pdev->irq, myri10ge_intr, IRQF_SHARED,
2188                                      mgp->dev->name, &mgp->ss[0]);
2189                 if (status != 0) {
2190                         dev_err(&pdev->dev, "failed to allocate IRQ\n");
2191                         if (mgp->msi_enabled)
2192                                 pci_disable_msi(pdev);
2193                 }
2194         }
2195         return status;
2196 }
2197
2198 static void myri10ge_free_irq(struct myri10ge_priv *mgp)
2199 {
2200         struct pci_dev *pdev = mgp->pdev;
2201         int i;
2202
2203         if (mgp->msix_enabled) {
2204                 for (i = 0; i < mgp->num_slices; i++)
2205                         free_irq(mgp->msix_vectors[i].vector, &mgp->ss[i]);
2206         } else {
2207                 free_irq(pdev->irq, &mgp->ss[0]);
2208         }
2209         if (mgp->msi_enabled)
2210                 pci_disable_msi(pdev);
2211         if (mgp->msix_enabled)
2212                 pci_disable_msix(pdev);
2213 }
2214
2215 static int
2216 myri10ge_get_frag_header(struct skb_frag_struct *frag, void **mac_hdr,
2217                          void **ip_hdr, void **tcpudp_hdr,
2218                          u64 * hdr_flags, void *priv)
2219 {
2220         struct ethhdr *eh;
2221         struct vlan_ethhdr *veh;
2222         struct iphdr *iph;
2223         u8 *va = page_address(frag->page) + frag->page_offset;
2224         unsigned long ll_hlen;
2225         /* passed opaque through lro_receive_frags() */
2226         __wsum csum = (__force __wsum) (unsigned long)priv;
2227
2228         /* find the mac header, aborting if not IPv4 */
2229
2230         eh = (struct ethhdr *)va;
2231         *mac_hdr = eh;
2232         ll_hlen = ETH_HLEN;
2233         if (eh->h_proto != htons(ETH_P_IP)) {
2234                 if (eh->h_proto == htons(ETH_P_8021Q)) {
2235                         veh = (struct vlan_ethhdr *)va;
2236                         if (veh->h_vlan_encapsulated_proto != htons(ETH_P_IP))
2237                                 return -1;
2238
2239                         ll_hlen += VLAN_HLEN;
2240
2241                         /*
2242                          *  HW checksum starts ETH_HLEN bytes into
2243                          *  frame, so we must subtract off the VLAN
2244                          *  header's checksum before csum can be used
2245                          */
2246                         csum = csum_sub(csum, csum_partial(va + ETH_HLEN,
2247                                                            VLAN_HLEN, 0));
2248                 } else {
2249                         return -1;
2250                 }
2251         }
2252         *hdr_flags = LRO_IPV4;
2253
2254         iph = (struct iphdr *)(va + ll_hlen);
2255         *ip_hdr = iph;
2256         if (iph->protocol != IPPROTO_TCP)
2257                 return -1;
2258         if (iph->frag_off & htons(IP_MF | IP_OFFSET))
2259                 return -1;
2260         *hdr_flags |= LRO_TCP;
2261         *tcpudp_hdr = (u8 *) (*ip_hdr) + (iph->ihl << 2);
2262
2263         /* verify the IP checksum */
2264         if (unlikely(ip_fast_csum((u8 *) iph, iph->ihl)))
2265                 return -1;
2266
2267         /* verify the  checksum */
2268         if (unlikely(csum_tcpudp_magic(iph->saddr, iph->daddr,
2269                                        ntohs(iph->tot_len) - (iph->ihl << 2),
2270                                        IPPROTO_TCP, csum)))
2271                 return -1;
2272
2273         return 0;
2274 }
2275
2276 static int myri10ge_get_txrx(struct myri10ge_priv *mgp, int slice)
2277 {
2278         struct myri10ge_cmd cmd;
2279         struct myri10ge_slice_state *ss;
2280         int status;
2281
2282         ss = &mgp->ss[slice];
2283         status = 0;
2284         if (slice == 0 || (mgp->dev->real_num_tx_queues > 1)) {
2285                 cmd.data0 = slice;
2286                 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_OFFSET,
2287                                            &cmd, 0);
2288                 ss->tx.lanai = (struct mcp_kreq_ether_send __iomem *)
2289                     (mgp->sram + cmd.data0);
2290         }
2291         cmd.data0 = slice;
2292         status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SMALL_RX_OFFSET,
2293                                     &cmd, 0);
2294         ss->rx_small.lanai = (struct mcp_kreq_ether_recv __iomem *)
2295             (mgp->sram + cmd.data0);
2296
2297         cmd.data0 = slice;
2298         status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_BIG_RX_OFFSET, &cmd, 0);
2299         ss->rx_big.lanai = (struct mcp_kreq_ether_recv __iomem *)
2300             (mgp->sram + cmd.data0);
2301
2302         ss->tx.send_go = (__iomem __be32 *)
2303             (mgp->sram + MXGEFW_ETH_SEND_GO + 64 * slice);
2304         ss->tx.send_stop = (__iomem __be32 *)
2305             (mgp->sram + MXGEFW_ETH_SEND_STOP + 64 * slice);
2306         return status;
2307
2308 }
2309
2310 static int myri10ge_set_stats(struct myri10ge_priv *mgp, int slice)
2311 {
2312         struct myri10ge_cmd cmd;
2313         struct myri10ge_slice_state *ss;
2314         int status;
2315
2316         ss = &mgp->ss[slice];
2317         cmd.data0 = MYRI10GE_LOWPART_TO_U32(ss->fw_stats_bus);
2318         cmd.data1 = MYRI10GE_HIGHPART_TO_U32(ss->fw_stats_bus);
2319         cmd.data2 = sizeof(struct mcp_irq_data) | (slice << 16);
2320         status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_STATS_DMA_V2, &cmd, 0);
2321         if (status == -ENOSYS) {
2322                 dma_addr_t bus = ss->fw_stats_bus;
2323                 if (slice != 0)
2324                         return -EINVAL;
2325                 bus += offsetof(struct mcp_irq_data, send_done_count);
2326                 cmd.data0 = MYRI10GE_LOWPART_TO_U32(bus);
2327                 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(bus);
2328                 status = myri10ge_send_cmd(mgp,
2329                                            MXGEFW_CMD_SET_STATS_DMA_OBSOLETE,
2330                                            &cmd, 0);
2331                 /* Firmware cannot support multicast without STATS_DMA_V2 */
2332                 mgp->fw_multicast_support = 0;
2333         } else {
2334                 mgp->fw_multicast_support = 1;
2335         }
2336         return 0;
2337 }
2338
2339 static int myri10ge_open(struct net_device *dev)
2340 {
2341         struct myri10ge_slice_state *ss;
2342         struct myri10ge_priv *mgp = netdev_priv(dev);
2343         struct myri10ge_cmd cmd;
2344         int i, status, big_pow2, slice;
2345         u8 *itable;
2346         struct net_lro_mgr *lro_mgr;
2347
2348         if (mgp->running != MYRI10GE_ETH_STOPPED)
2349                 return -EBUSY;
2350
2351         mgp->running = MYRI10GE_ETH_STARTING;
2352         status = myri10ge_reset(mgp);
2353         if (status != 0) {
2354                 netdev_err(dev, "failed reset\n");
2355                 goto abort_with_nothing;
2356         }
2357
2358         if (mgp->num_slices > 1) {
2359                 cmd.data0 = mgp->num_slices;
2360                 cmd.data1 = MXGEFW_SLICE_INTR_MODE_ONE_PER_SLICE;
2361                 if (mgp->dev->real_num_tx_queues > 1)
2362                         cmd.data1 |= MXGEFW_SLICE_ENABLE_MULTIPLE_TX_QUEUES;
2363                 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ENABLE_RSS_QUEUES,
2364                                            &cmd, 0);
2365                 if (status != 0) {
2366                         netdev_err(dev, "failed to set number of slices\n");
2367                         goto abort_with_nothing;
2368                 }
2369                 /* setup the indirection table */
2370                 cmd.data0 = mgp->num_slices;
2371                 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_RSS_TABLE_SIZE,
2372                                            &cmd, 0);
2373
2374                 status |= myri10ge_send_cmd(mgp,
2375                                             MXGEFW_CMD_GET_RSS_TABLE_OFFSET,
2376                                             &cmd, 0);
2377                 if (status != 0) {
2378                         netdev_err(dev, "failed to setup rss tables\n");
2379                         goto abort_with_nothing;
2380                 }
2381
2382                 /* just enable an identity mapping */
2383                 itable = mgp->sram + cmd.data0;
2384                 for (i = 0; i < mgp->num_slices; i++)
2385                         __raw_writeb(i, &itable[i]);
2386
2387                 cmd.data0 = 1;
2388                 cmd.data1 = myri10ge_rss_hash;
2389                 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_RSS_ENABLE,
2390                                            &cmd, 0);
2391                 if (status != 0) {
2392                         netdev_err(dev, "failed to enable slices\n");
2393                         goto abort_with_nothing;
2394                 }
2395         }
2396
2397         status = myri10ge_request_irq(mgp);
2398         if (status != 0)
2399                 goto abort_with_nothing;
2400
2401         /* decide what small buffer size to use.  For good TCP rx
2402          * performance, it is important to not receive 1514 byte
2403          * frames into jumbo buffers, as it confuses the socket buffer
2404          * accounting code, leading to drops and erratic performance.
2405          */
2406
2407         if (dev->mtu <= ETH_DATA_LEN)
2408                 /* enough for a TCP header */
2409                 mgp->small_bytes = (128 > SMP_CACHE_BYTES)
2410                     ? (128 - MXGEFW_PAD)
2411                     : (SMP_CACHE_BYTES - MXGEFW_PAD);
2412         else
2413                 /* enough for a vlan encapsulated ETH_DATA_LEN frame */
2414                 mgp->small_bytes = VLAN_ETH_FRAME_LEN;
2415
2416         /* Override the small buffer size? */
2417         if (myri10ge_small_bytes > 0)
2418                 mgp->small_bytes = myri10ge_small_bytes;
2419
2420         /* Firmware needs the big buff size as a power of 2.  Lie and
2421          * tell him the buffer is larger, because we only use 1
2422          * buffer/pkt, and the mtu will prevent overruns.
2423          */
2424         big_pow2 = dev->mtu + ETH_HLEN + VLAN_HLEN + MXGEFW_PAD;
2425         if (big_pow2 < MYRI10GE_ALLOC_SIZE / 2) {
2426                 while (!is_power_of_2(big_pow2))
2427                         big_pow2++;
2428                 mgp->big_bytes = dev->mtu + ETH_HLEN + VLAN_HLEN + MXGEFW_PAD;
2429         } else {
2430                 big_pow2 = MYRI10GE_ALLOC_SIZE;
2431                 mgp->big_bytes = big_pow2;
2432         }
2433
2434         /* setup the per-slice data structures */
2435         for (slice = 0; slice < mgp->num_slices; slice++) {
2436                 ss = &mgp->ss[slice];
2437
2438                 status = myri10ge_get_txrx(mgp, slice);
2439                 if (status != 0) {
2440                         netdev_err(dev, "failed to get ring sizes or locations\n");
2441                         goto abort_with_rings;
2442                 }
2443                 status = myri10ge_allocate_rings(ss);
2444                 if (status != 0)
2445                         goto abort_with_rings;
2446
2447                 /* only firmware which supports multiple TX queues
2448                  * supports setting up the tx stats on non-zero
2449                  * slices */
2450                 if (slice == 0 || mgp->dev->real_num_tx_queues > 1)
2451                         status = myri10ge_set_stats(mgp, slice);
2452                 if (status) {
2453                         netdev_err(dev, "Couldn't set stats DMA\n");
2454                         goto abort_with_rings;
2455                 }
2456
2457                 lro_mgr = &ss->rx_done.lro_mgr;
2458                 lro_mgr->dev = dev;
2459                 lro_mgr->features = LRO_F_NAPI;
2460                 lro_mgr->ip_summed = CHECKSUM_COMPLETE;
2461                 lro_mgr->ip_summed_aggr = CHECKSUM_UNNECESSARY;
2462                 lro_mgr->max_desc = MYRI10GE_MAX_LRO_DESCRIPTORS;
2463                 lro_mgr->lro_arr = ss->rx_done.lro_desc;
2464                 lro_mgr->get_frag_header = myri10ge_get_frag_header;
2465                 lro_mgr->max_aggr = myri10ge_lro_max_pkts;
2466                 lro_mgr->frag_align_pad = 2;
2467                 if (lro_mgr->max_aggr > MAX_SKB_FRAGS)
2468                         lro_mgr->max_aggr = MAX_SKB_FRAGS;
2469
2470                 /* must happen prior to any irq */
2471                 napi_enable(&(ss)->napi);
2472         }
2473
2474         /* now give firmware buffers sizes, and MTU */
2475         cmd.data0 = dev->mtu + ETH_HLEN + VLAN_HLEN;
2476         status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_MTU, &cmd, 0);
2477         cmd.data0 = mgp->small_bytes;
2478         status |=
2479             myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_SMALL_BUFFER_SIZE, &cmd, 0);
2480         cmd.data0 = big_pow2;
2481         status |=
2482             myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_BIG_BUFFER_SIZE, &cmd, 0);
2483         if (status) {
2484                 netdev_err(dev, "Couldn't set buffer sizes\n");
2485                 goto abort_with_rings;
2486         }
2487
2488         /*
2489          * Set Linux style TSO mode; this is needed only on newer
2490          *  firmware versions.  Older versions default to Linux
2491          *  style TSO
2492          */
2493         cmd.data0 = 0;
2494         status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_TSO_MODE, &cmd, 0);
2495         if (status && status != -ENOSYS) {
2496                 netdev_err(dev, "Couldn't set TSO mode\n");
2497                 goto abort_with_rings;
2498         }
2499
2500         mgp->link_state = ~0U;
2501         mgp->rdma_tags_available = 15;
2502
2503         status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_UP, &cmd, 0);
2504         if (status) {
2505                 netdev_err(dev, "Couldn't bring up link\n");
2506                 goto abort_with_rings;
2507         }
2508
2509         mgp->running = MYRI10GE_ETH_RUNNING;
2510         mgp->watchdog_timer.expires = jiffies + myri10ge_watchdog_timeout * HZ;
2511         add_timer(&mgp->watchdog_timer);
2512         netif_tx_wake_all_queues(dev);
2513
2514         return 0;
2515
2516 abort_with_rings:
2517         while (slice) {
2518                 slice--;
2519                 napi_disable(&mgp->ss[slice].napi);
2520         }
2521         for (i = 0; i < mgp->num_slices; i++)
2522                 myri10ge_free_rings(&mgp->ss[i]);
2523
2524         myri10ge_free_irq(mgp);
2525
2526 abort_with_nothing:
2527         mgp->running = MYRI10GE_ETH_STOPPED;
2528         return -ENOMEM;
2529 }
2530
2531 static int myri10ge_close(struct net_device *dev)
2532 {
2533         struct myri10ge_priv *mgp = netdev_priv(dev);
2534         struct myri10ge_cmd cmd;
2535         int status, old_down_cnt;
2536         int i;
2537
2538         if (mgp->running != MYRI10GE_ETH_RUNNING)
2539                 return 0;
2540
2541         if (mgp->ss[0].tx.req_bytes == NULL)
2542                 return 0;
2543
2544         del_timer_sync(&mgp->watchdog_timer);
2545         mgp->running = MYRI10GE_ETH_STOPPING;
2546         for (i = 0; i < mgp->num_slices; i++) {
2547                 napi_disable(&mgp->ss[i].napi);
2548         }
2549         netif_carrier_off(dev);
2550
2551         netif_tx_stop_all_queues(dev);
2552         if (mgp->rebooted == 0) {
2553                 old_down_cnt = mgp->down_cnt;
2554                 mb();
2555                 status =
2556                     myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_DOWN, &cmd, 0);
2557                 if (status)
2558                         netdev_err(dev, "Couldn't bring down link\n");
2559
2560                 wait_event_timeout(mgp->down_wq, old_down_cnt != mgp->down_cnt,
2561                                    HZ);
2562                 if (old_down_cnt == mgp->down_cnt)
2563                         netdev_err(dev, "never got down irq\n");
2564         }
2565         netif_tx_disable(dev);
2566         myri10ge_free_irq(mgp);
2567         for (i = 0; i < mgp->num_slices; i++)
2568                 myri10ge_free_rings(&mgp->ss[i]);
2569
2570         mgp->running = MYRI10GE_ETH_STOPPED;
2571         return 0;
2572 }
2573
2574 /* copy an array of struct mcp_kreq_ether_send's to the mcp.  Copy
2575  * backwards one at a time and handle ring wraps */
2576
2577 static inline void
2578 myri10ge_submit_req_backwards(struct myri10ge_tx_buf *tx,
2579                               struct mcp_kreq_ether_send *src, int cnt)
2580 {
2581         int idx, starting_slot;
2582         starting_slot = tx->req;
2583         while (cnt > 1) {
2584                 cnt--;
2585                 idx = (starting_slot + cnt) & tx->mask;
2586                 myri10ge_pio_copy(&tx->lanai[idx], &src[cnt], sizeof(*src));
2587                 mb();
2588         }
2589 }
2590
2591 /*
2592  * copy an array of struct mcp_kreq_ether_send's to the mcp.  Copy
2593  * at most 32 bytes at a time, so as to avoid involving the software
2594  * pio handler in the nic.   We re-write the first segment's flags
2595  * to mark them valid only after writing the entire chain.
2596  */
2597
2598 static inline void
2599 myri10ge_submit_req(struct myri10ge_tx_buf *tx, struct mcp_kreq_ether_send *src,
2600                     int cnt)
2601 {
2602         int idx, i;
2603         struct mcp_kreq_ether_send __iomem *dstp, *dst;
2604         struct mcp_kreq_ether_send *srcp;
2605         u8 last_flags;
2606
2607         idx = tx->req & tx->mask;
2608
2609         last_flags = src->flags;
2610         src->flags = 0;
2611         mb();
2612         dst = dstp = &tx->lanai[idx];
2613         srcp = src;
2614
2615         if ((idx + cnt) < tx->mask) {
2616                 for (i = 0; i < (cnt - 1); i += 2) {
2617                         myri10ge_pio_copy(dstp, srcp, 2 * sizeof(*src));
2618                         mb();   /* force write every 32 bytes */
2619                         srcp += 2;
2620                         dstp += 2;
2621                 }
2622         } else {
2623                 /* submit all but the first request, and ensure
2624                  * that it is submitted below */
2625                 myri10ge_submit_req_backwards(tx, src, cnt);
2626                 i = 0;
2627         }
2628         if (i < cnt) {
2629                 /* submit the first request */
2630                 myri10ge_pio_copy(dstp, srcp, sizeof(*src));
2631                 mb();           /* barrier before setting valid flag */
2632         }
2633
2634         /* re-write the last 32-bits with the valid flags */
2635         src->flags = last_flags;
2636         put_be32(*((__be32 *) src + 3), (__be32 __iomem *) dst + 3);
2637         tx->req += cnt;
2638         mb();
2639 }
2640
2641 /*
2642  * Transmit a packet.  We need to split the packet so that a single
2643  * segment does not cross myri10ge->tx_boundary, so this makes segment
2644  * counting tricky.  So rather than try to count segments up front, we
2645  * just give up if there are too few segments to hold a reasonably
2646  * fragmented packet currently available.  If we run
2647  * out of segments while preparing a packet for DMA, we just linearize
2648  * it and try again.
2649  */
2650
2651 static netdev_tx_t myri10ge_xmit(struct sk_buff *skb,
2652                                        struct net_device *dev)
2653 {
2654         struct myri10ge_priv *mgp = netdev_priv(dev);
2655         struct myri10ge_slice_state *ss;
2656         struct mcp_kreq_ether_send *req;
2657         struct myri10ge_tx_buf *tx;
2658         struct skb_frag_struct *frag;
2659         struct netdev_queue *netdev_queue;
2660         dma_addr_t bus;
2661         u32 low;
2662         __be32 high_swapped;
2663         unsigned int len;
2664         int idx, last_idx, avail, frag_cnt, frag_idx, count, mss, max_segments;
2665         u16 pseudo_hdr_offset, cksum_offset, queue;
2666         int cum_len, seglen, boundary, rdma_count;
2667         u8 flags, odd_flag;
2668
2669         queue = skb_get_queue_mapping(skb);
2670         ss = &mgp->ss[queue];
2671         netdev_queue = netdev_get_tx_queue(mgp->dev, queue);
2672         tx = &ss->tx;
2673
2674 again:
2675         req = tx->req_list;
2676         avail = tx->mask - 1 - (tx->req - tx->done);
2677
2678         mss = 0;
2679         max_segments = MXGEFW_MAX_SEND_DESC;
2680
2681         if (skb_is_gso(skb)) {
2682                 mss = skb_shinfo(skb)->gso_size;
2683                 max_segments = MYRI10GE_MAX_SEND_DESC_TSO;
2684         }
2685
2686         if ((unlikely(avail < max_segments))) {
2687                 /* we are out of transmit resources */
2688                 tx->stop_queue++;
2689                 netif_tx_stop_queue(netdev_queue);
2690                 return NETDEV_TX_BUSY;
2691         }
2692
2693         /* Setup checksum offloading, if needed */
2694         cksum_offset = 0;
2695         pseudo_hdr_offset = 0;
2696         odd_flag = 0;
2697         flags = (MXGEFW_FLAGS_NO_TSO | MXGEFW_FLAGS_FIRST);
2698         if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
2699                 cksum_offset = skb_transport_offset(skb);
2700                 pseudo_hdr_offset = cksum_offset + skb->csum_offset;
2701                 /* If the headers are excessively large, then we must
2702                  * fall back to a software checksum */
2703                 if (unlikely(!mss && (cksum_offset > 255 ||
2704                                       pseudo_hdr_offset > 127))) {
2705                         if (skb_checksum_help(skb))
2706                                 goto drop;
2707                         cksum_offset = 0;
2708                         pseudo_hdr_offset = 0;
2709                 } else {
2710                         odd_flag = MXGEFW_FLAGS_ALIGN_ODD;
2711                         flags |= MXGEFW_FLAGS_CKSUM;
2712                 }
2713         }
2714
2715         cum_len = 0;
2716
2717         if (mss) {              /* TSO */
2718                 /* this removes any CKSUM flag from before */
2719                 flags = (MXGEFW_FLAGS_TSO_HDR | MXGEFW_FLAGS_FIRST);
2720
2721                 /* negative cum_len signifies to the
2722                  * send loop that we are still in the
2723                  * header portion of the TSO packet.
2724                  * TSO header can be at most 1KB long */
2725                 cum_len = -(skb_transport_offset(skb) + tcp_hdrlen(skb));
2726
2727                 /* for IPv6 TSO, the checksum offset stores the
2728                  * TCP header length, to save the firmware from
2729                  * the need to parse the headers */
2730                 if (skb_is_gso_v6(skb)) {
2731                         cksum_offset = tcp_hdrlen(skb);
2732                         /* Can only handle headers <= max_tso6 long */
2733                         if (unlikely(-cum_len > mgp->max_tso6))
2734                                 return myri10ge_sw_tso(skb, dev);
2735                 }
2736                 /* for TSO, pseudo_hdr_offset holds mss.
2737                  * The firmware figures out where to put
2738                  * the checksum by parsing the header. */
2739                 pseudo_hdr_offset = mss;
2740         } else
2741                 /* Mark small packets, and pad out tiny packets */
2742         if (skb->len <= MXGEFW_SEND_SMALL_SIZE) {
2743                 flags |= MXGEFW_FLAGS_SMALL;
2744
2745                 /* pad frames to at least ETH_ZLEN bytes */
2746                 if (unlikely(skb->len < ETH_ZLEN)) {
2747                         if (skb_padto(skb, ETH_ZLEN)) {
2748                                 /* The packet is gone, so we must
2749                                  * return 0 */
2750                                 ss->stats.tx_dropped += 1;
2751                                 return NETDEV_TX_OK;
2752                         }
2753                         /* adjust the len to account for the zero pad
2754                          * so that the nic can know how long it is */
2755                         skb->len = ETH_ZLEN;
2756                 }
2757         }
2758
2759         /* map the skb for DMA */
2760         len = skb->len - skb->data_len;
2761         idx = tx->req & tx->mask;
2762         tx->info[idx].skb = skb;
2763         bus = pci_map_single(mgp->pdev, skb->data, len, PCI_DMA_TODEVICE);
2764         pci_unmap_addr_set(&tx->info[idx], bus, bus);
2765         pci_unmap_len_set(&tx->info[idx], len, len);
2766
2767         frag_cnt = skb_shinfo(skb)->nr_frags;
2768         frag_idx = 0;
2769         count = 0;
2770         rdma_count = 0;
2771
2772         /* "rdma_count" is the number of RDMAs belonging to the
2773          * current packet BEFORE the current send request. For
2774          * non-TSO packets, this is equal to "count".
2775          * For TSO packets, rdma_count needs to be reset
2776          * to 0 after a segment cut.
2777          *
2778          * The rdma_count field of the send request is
2779          * the number of RDMAs of the packet starting at
2780          * that request. For TSO send requests with one ore more cuts
2781          * in the middle, this is the number of RDMAs starting
2782          * after the last cut in the request. All previous
2783          * segments before the last cut implicitly have 1 RDMA.
2784          *
2785          * Since the number of RDMAs is not known beforehand,
2786          * it must be filled-in retroactively - after each
2787          * segmentation cut or at the end of the entire packet.
2788          */
2789
2790         while (1) {
2791                 /* Break the SKB or Fragment up into pieces which
2792                  * do not cross mgp->tx_boundary */
2793                 low = MYRI10GE_LOWPART_TO_U32(bus);
2794                 high_swapped = htonl(MYRI10GE_HIGHPART_TO_U32(bus));
2795                 while (len) {
2796                         u8 flags_next;
2797                         int cum_len_next;
2798
2799                         if (unlikely(count == max_segments))
2800                                 goto abort_linearize;
2801
2802                         boundary =
2803                             (low + mgp->tx_boundary) & ~(mgp->tx_boundary - 1);
2804                         seglen = boundary - low;
2805                         if (seglen > len)
2806                                 seglen = len;
2807                         flags_next = flags & ~MXGEFW_FLAGS_FIRST;
2808                         cum_len_next = cum_len + seglen;
2809                         if (mss) {      /* TSO */
2810                                 (req - rdma_count)->rdma_count = rdma_count + 1;
2811
2812                                 if (likely(cum_len >= 0)) {     /* payload */
2813                                         int next_is_first, chop;
2814
2815                                         chop = (cum_len_next > mss);
2816                                         cum_len_next = cum_len_next % mss;
2817                                         next_is_first = (cum_len_next == 0);
2818                                         flags |= chop * MXGEFW_FLAGS_TSO_CHOP;
2819                                         flags_next |= next_is_first *
2820                                             MXGEFW_FLAGS_FIRST;
2821                                         rdma_count |= -(chop | next_is_first);
2822                                         rdma_count += chop & !next_is_first;
2823                                 } else if (likely(cum_len_next >= 0)) { /* header ends */
2824                                         int small;
2825
2826                                         rdma_count = -1;
2827                                         cum_len_next = 0;
2828                                         seglen = -cum_len;
2829                                         small = (mss <= MXGEFW_SEND_SMALL_SIZE);
2830                                         flags_next = MXGEFW_FLAGS_TSO_PLD |
2831                                             MXGEFW_FLAGS_FIRST |
2832                                             (small * MXGEFW_FLAGS_SMALL);
2833                                 }
2834                         }
2835                         req->addr_high = high_swapped;
2836                         req->addr_low = htonl(low);
2837                         req->pseudo_hdr_offset = htons(pseudo_hdr_offset);
2838                         req->pad = 0;   /* complete solid 16-byte block; does this matter? */
2839                         req->rdma_count = 1;
2840                         req->length = htons(seglen);
2841                         req->cksum_offset = cksum_offset;
2842                         req->flags = flags | ((cum_len & 1) * odd_flag);
2843
2844                         low += seglen;
2845                         len -= seglen;
2846                         cum_len = cum_len_next;
2847                         flags = flags_next;
2848                         req++;
2849                         count++;
2850                         rdma_count++;
2851                         if (cksum_offset != 0 && !(mss && skb_is_gso_v6(skb))) {
2852                                 if (unlikely(cksum_offset > seglen))
2853                                         cksum_offset -= seglen;
2854                                 else
2855                                         cksum_offset = 0;
2856                         }
2857                 }
2858                 if (frag_idx == frag_cnt)
2859                         break;
2860
2861                 /* map next fragment for DMA */
2862                 idx = (count + tx->req) & tx->mask;
2863                 frag = &skb_shinfo(skb)->frags[frag_idx];
2864                 frag_idx++;
2865                 len = frag->size;
2866                 bus = pci_map_page(mgp->pdev, frag->page, frag->page_offset,
2867                                    len, PCI_DMA_TODEVICE);
2868                 pci_unmap_addr_set(&tx->info[idx], bus, bus);
2869                 pci_unmap_len_set(&tx->info[idx], len, len);
2870         }
2871
2872         (req - rdma_count)->rdma_count = rdma_count;
2873         if (mss)
2874                 do {
2875                         req--;
2876                         req->flags |= MXGEFW_FLAGS_TSO_LAST;
2877                 } while (!(req->flags & (MXGEFW_FLAGS_TSO_CHOP |
2878                                          MXGEFW_FLAGS_FIRST)));
2879         idx = ((count - 1) + tx->req) & tx->mask;
2880         tx->info[idx].last = 1;
2881         myri10ge_submit_req(tx, tx->req_list, count);
2882         /* if using multiple tx queues, make sure NIC polls the
2883          * current slice */
2884         if ((mgp->dev->real_num_tx_queues > 1) && tx->queue_active == 0) {
2885                 tx->queue_active = 1;
2886                 put_be32(htonl(1), tx->send_go);
2887                 mb();
2888                 mmiowb();
2889         }
2890         tx->pkt_start++;
2891         if ((avail - count) < MXGEFW_MAX_SEND_DESC) {
2892                 tx->stop_queue++;
2893                 netif_tx_stop_queue(netdev_queue);
2894         }
2895         return NETDEV_TX_OK;
2896
2897 abort_linearize:
2898         /* Free any DMA resources we've alloced and clear out the skb
2899          * slot so as to not trip up assertions, and to avoid a
2900          * double-free if linearizing fails */
2901
2902         last_idx = (idx + 1) & tx->mask;
2903         idx = tx->req & tx->mask;
2904         tx->info[idx].skb = NULL;
2905         do {
2906                 len = pci_unmap_len(&tx->info[idx], len);
2907                 if (len) {
2908                         if (tx->info[idx].skb != NULL)
2909                                 pci_unmap_single(mgp->pdev,
2910                                                  pci_unmap_addr(&tx->info[idx],
2911                                                                 bus), len,
2912                                                  PCI_DMA_TODEVICE);
2913                         else
2914                                 pci_unmap_page(mgp->pdev,
2915                                                pci_unmap_addr(&tx->info[idx],
2916                                                               bus), len,
2917                                                PCI_DMA_TODEVICE);
2918                         pci_unmap_len_set(&tx->info[idx], len, 0);
2919                         tx->info[idx].skb = NULL;
2920                 }
2921                 idx = (idx + 1) & tx->mask;
2922         } while (idx != last_idx);
2923         if (skb_is_gso(skb)) {
2924                 netdev_err(mgp->dev, "TSO but wanted to linearize?!?!?\n");
2925                 goto drop;
2926         }
2927
2928         if (skb_linearize(skb))
2929                 goto drop;
2930
2931         tx->linearized++;
2932         goto again;
2933
2934 drop:
2935         dev_kfree_skb_any(skb);
2936         ss->stats.tx_dropped += 1;
2937         return NETDEV_TX_OK;
2938
2939 }
2940
2941 static netdev_tx_t myri10ge_sw_tso(struct sk_buff *skb,
2942                                          struct net_device *dev)
2943 {
2944         struct sk_buff *segs, *curr;
2945         struct myri10ge_priv *mgp = netdev_priv(dev);
2946         struct myri10ge_slice_state *ss;
2947         netdev_tx_t status;
2948
2949         segs = skb_gso_segment(skb, dev->features & ~NETIF_F_TSO6);
2950         if (IS_ERR(segs))
2951                 goto drop;
2952
2953         while (segs) {
2954                 curr = segs;
2955                 segs = segs->next;
2956                 curr->next = NULL;
2957                 status = myri10ge_xmit(curr, dev);
2958                 if (status != 0) {
2959                         dev_kfree_skb_any(curr);
2960                         if (segs != NULL) {
2961                                 curr = segs;
2962                                 segs = segs->next;
2963                                 curr->next = NULL;
2964                                 dev_kfree_skb_any(segs);
2965                         }
2966                         goto drop;
2967                 }
2968         }
2969         dev_kfree_skb_any(skb);
2970         return NETDEV_TX_OK;
2971
2972 drop:
2973         ss = &mgp->ss[skb_get_queue_mapping(skb)];
2974         dev_kfree_skb_any(skb);
2975         ss->stats.tx_dropped += 1;
2976         return NETDEV_TX_OK;
2977 }
2978
2979 static struct net_device_stats *myri10ge_get_stats(struct net_device *dev)
2980 {
2981         struct myri10ge_priv *mgp = netdev_priv(dev);
2982         struct myri10ge_slice_netstats *slice_stats;
2983         struct net_device_stats *stats = &dev->stats;
2984         int i;
2985
2986         spin_lock(&mgp->stats_lock);
2987         memset(stats, 0, sizeof(*stats));
2988         for (i = 0; i < mgp->num_slices; i++) {
2989                 slice_stats = &mgp->ss[i].stats;
2990                 stats->rx_packets += slice_stats->rx_packets;
2991                 stats->tx_packets += slice_stats->tx_packets;
2992                 stats->rx_bytes += slice_stats->rx_bytes;
2993                 stats->tx_bytes += slice_stats->tx_bytes;
2994                 stats->rx_dropped += slice_stats->rx_dropped;
2995                 stats->tx_dropped += slice_stats->tx_dropped;
2996         }
2997         spin_unlock(&mgp->stats_lock);
2998         return stats;
2999 }
3000
3001 static void myri10ge_set_multicast_list(struct net_device *dev)
3002 {
3003         struct myri10ge_priv *mgp = netdev_priv(dev);
3004         struct myri10ge_cmd cmd;
3005         struct dev_mc_list *mc_list;
3006         __be32 data[2] = { 0, 0 };
3007         int err;
3008
3009         /* can be called from atomic contexts,
3010          * pass 1 to force atomicity in myri10ge_send_cmd() */
3011         myri10ge_change_promisc(mgp, dev->flags & IFF_PROMISC, 1);
3012
3013         /* This firmware is known to not support multicast */
3014         if (!mgp->fw_multicast_support)
3015                 return;
3016
3017         /* Disable multicast filtering */
3018
3019         err = myri10ge_send_cmd(mgp, MXGEFW_ENABLE_ALLMULTI, &cmd, 1);
3020         if (err != 0) {
3021                 netdev_err(dev, "Failed MXGEFW_ENABLE_ALLMULTI, error status: %d\n",
3022                            err);
3023                 goto abort;
3024         }
3025
3026         if ((dev->flags & IFF_ALLMULTI) || mgp->adopted_rx_filter_bug) {
3027                 /* request to disable multicast filtering, so quit here */
3028                 return;
3029         }
3030
3031         /* Flush the filters */
3032
3033         err = myri10ge_send_cmd(mgp, MXGEFW_LEAVE_ALL_MULTICAST_GROUPS,
3034                                 &cmd, 1);
3035         if (err != 0) {
3036                 netdev_err(dev, "Failed MXGEFW_LEAVE_ALL_MULTICAST_GROUPS, error status: %d\n",
3037                            err);
3038                 goto abort;
3039         }
3040
3041         /* Walk the multicast list, and add each address */
3042         netdev_for_each_mc_addr(mc_list, dev) {
3043                 memcpy(data, &mc_list->dmi_addr, 6);
3044                 cmd.data0 = ntohl(data[0]);
3045                 cmd.data1 = ntohl(data[1]);
3046                 err = myri10ge_send_cmd(mgp, MXGEFW_JOIN_MULTICAST_GROUP,
3047                                         &cmd, 1);
3048
3049                 if (err != 0) {
3050                         netdev_err(dev, "Failed MXGEFW_JOIN_MULTICAST_GROUP, error status:%d %pM\n",
3051                                    err, mc_list->dmi_addr);
3052                         goto abort;
3053                 }
3054         }
3055         /* Enable multicast filtering */
3056         err = myri10ge_send_cmd(mgp, MXGEFW_DISABLE_ALLMULTI, &cmd, 1);
3057         if (err != 0) {
3058                 netdev_err(dev, "Failed MXGEFW_DISABLE_ALLMULTI, error status: %d\n",
3059                            err);
3060                 goto abort;
3061         }
3062
3063         return;
3064
3065 abort:
3066         return;
3067 }
3068
3069 static int myri10ge_set_mac_address(struct net_device *dev, void *addr)
3070 {
3071         struct sockaddr *sa = addr;
3072         struct myri10ge_priv *mgp = netdev_priv(dev);
3073         int status;
3074
3075         if (!is_valid_ether_addr(sa->sa_data))
3076                 return -EADDRNOTAVAIL;
3077
3078         status = myri10ge_update_mac_address(mgp, sa->sa_data);
3079         if (status != 0) {
3080                 netdev_err(dev, "changing mac address failed with %d\n",
3081                            status);
3082                 return status;
3083         }
3084
3085         /* change the dev structure */
3086         memcpy(dev->dev_addr, sa->sa_data, 6);
3087         return 0;
3088 }
3089
3090 static int myri10ge_change_mtu(struct net_device *dev, int new_mtu)
3091 {
3092         struct myri10ge_priv *mgp = netdev_priv(dev);
3093         int error = 0;
3094
3095         if ((new_mtu < 68) || (ETH_HLEN + new_mtu > MYRI10GE_MAX_ETHER_MTU)) {
3096                 netdev_err(dev, "new mtu (%d) is not valid\n", new_mtu);
3097                 return -EINVAL;
3098         }
3099         netdev_info(dev, "changing mtu from %d to %d\n", dev->mtu, new_mtu);
3100         if (mgp->running) {
3101                 /* if we change the mtu on an active device, we must
3102                  * reset the device so the firmware sees the change */
3103                 myri10ge_close(dev);
3104                 dev->mtu = new_mtu;
3105                 myri10ge_open(dev);
3106         } else
3107                 dev->mtu = new_mtu;
3108
3109         return error;
3110 }
3111
3112 /*
3113  * Enable ECRC to align PCI-E Completion packets on an 8-byte boundary.
3114  * Only do it if the bridge is a root port since we don't want to disturb
3115  * any other device, except if forced with myri10ge_ecrc_enable > 1.
3116  */
3117
3118 static void myri10ge_enable_ecrc(struct myri10ge_priv *mgp)
3119 {
3120         struct pci_dev *bridge = mgp->pdev->bus->self;
3121         struct device *dev = &mgp->pdev->dev;
3122         unsigned cap;
3123         unsigned err_cap;
3124         u16 val;
3125         u8 ext_type;
3126         int ret;
3127
3128         if (!myri10ge_ecrc_enable || !bridge)
3129                 return;
3130
3131         /* check that the bridge is a root port */
3132         cap = pci_find_capability(bridge, PCI_CAP_ID_EXP);
3133         pci_read_config_word(bridge, cap + PCI_CAP_FLAGS, &val);
3134         ext_type = (val & PCI_EXP_FLAGS_TYPE) >> 4;
3135         if (ext_type != PCI_EXP_TYPE_ROOT_PORT) {
3136                 if (myri10ge_ecrc_enable > 1) {
3137                         struct pci_dev *prev_bridge, *old_bridge = bridge;
3138
3139                         /* Walk the hierarchy up to the root port
3140                          * where ECRC has to be enabled */
3141                         do {
3142                                 prev_bridge = bridge;
3143                                 bridge = bridge->bus->self;
3144                                 if (!bridge || prev_bridge == bridge) {
3145                                         dev_err(dev,
3146                                                 "Failed to find root port"
3147                                                 " to force ECRC\n");
3148                                         return;
3149                                 }
3150                                 cap =
3151                                     pci_find_capability(bridge, PCI_CAP_ID_EXP);
3152                                 pci_read_config_word(bridge,
3153                                                      cap + PCI_CAP_FLAGS, &val);
3154                                 ext_type = (val & PCI_EXP_FLAGS_TYPE) >> 4;
3155                         } while (ext_type != PCI_EXP_TYPE_ROOT_PORT);
3156
3157                         dev_info(dev,
3158                                  "Forcing ECRC on non-root port %s"
3159                                  " (enabling on root port %s)\n",
3160                                  pci_name(old_bridge), pci_name(bridge));
3161                 } else {
3162                         dev_err(dev,
3163                                 "Not enabling ECRC on non-root port %s\n",
3164                                 pci_name(bridge));
3165                         return;
3166                 }
3167         }
3168
3169         cap = pci_find_ext_capability(bridge, PCI_EXT_CAP_ID_ERR);
3170         if (!cap)
3171                 return;
3172
3173         ret = pci_read_config_dword(bridge, cap + PCI_ERR_CAP, &err_cap);
3174         if (ret) {
3175                 dev_err(dev, "failed reading ext-conf-space of %s\n",
3176                         pci_name(bridge));
3177                 dev_err(dev, "\t pci=nommconf in use? "
3178                         "or buggy/incomplete/absent ACPI MCFG attr?\n");
3179                 return;
3180         }
3181         if (!(err_cap & PCI_ERR_CAP_ECRC_GENC))
3182                 return;
3183
3184         err_cap |= PCI_ERR_CAP_ECRC_GENE;
3185         pci_write_config_dword(bridge, cap + PCI_ERR_CAP, err_cap);
3186         dev_info(dev, "Enabled ECRC on upstream bridge %s\n", pci_name(bridge));
3187 }
3188
3189 /*
3190  * The Lanai Z8E PCI-E interface achieves higher Read-DMA throughput
3191  * when the PCI-E Completion packets are aligned on an 8-byte
3192  * boundary.  Some PCI-E chip sets always align Completion packets; on
3193  * the ones that do not, the alignment can be enforced by enabling
3194  * ECRC generation (if supported).
3195  *
3196  * When PCI-E Completion packets are not aligned, it is actually more
3197  * efficient to limit Read-DMA transactions to 2KB, rather than 4KB.
3198  *
3199  * If the driver can neither enable ECRC nor verify that it has
3200  * already been enabled, then it must use a firmware image which works
3201  * around unaligned completion packets (myri10ge_rss_ethp_z8e.dat), and it
3202  * should also ensure that it never gives the device a Read-DMA which is
3203  * larger than 2KB by setting the tx_boundary to 2KB.  If ECRC is
3204  * enabled, then the driver should use the aligned (myri10ge_rss_eth_z8e.dat)
3205  * firmware image, and set tx_boundary to 4KB.
3206  */
3207
3208 static void myri10ge_firmware_probe(struct myri10ge_priv *mgp)
3209 {
3210         struct pci_dev *pdev = mgp->pdev;
3211         struct device *dev = &pdev->dev;
3212         int status;
3213
3214         mgp->tx_boundary = 4096;
3215         /*
3216          * Verify the max read request size was set to 4KB
3217          * before trying the test with 4KB.
3218          */
3219         status = pcie_get_readrq(pdev);
3220         if (status < 0) {
3221                 dev_err(dev, "Couldn't read max read req size: %d\n", status);
3222                 goto abort;
3223         }
3224         if (status != 4096) {
3225                 dev_warn(dev, "Max Read Request size != 4096 (%d)\n", status);
3226                 mgp->tx_boundary = 2048;
3227         }
3228         /*
3229          * load the optimized firmware (which assumes aligned PCIe
3230          * completions) in order to see if it works on this host.
3231          */
3232         mgp->fw_name = myri10ge_fw_aligned;
3233         status = myri10ge_load_firmware(mgp, 1);
3234         if (status != 0) {
3235                 goto abort;
3236         }
3237
3238         /*
3239          * Enable ECRC if possible
3240          */
3241         myri10ge_enable_ecrc(mgp);
3242
3243         /*
3244          * Run a DMA test which watches for unaligned completions and
3245          * aborts on the first one seen.
3246          */
3247
3248         status = myri10ge_dma_test(mgp, MXGEFW_CMD_UNALIGNED_TEST);
3249         if (status == 0)
3250                 return;         /* keep the aligned firmware */
3251
3252         if (status != -E2BIG)
3253                 dev_warn(dev, "DMA test failed: %d\n", status);
3254         if (status == -ENOSYS)
3255                 dev_warn(dev, "Falling back to ethp! "
3256                          "Please install up to date fw\n");
3257 abort:
3258         /* fall back to using the unaligned firmware */
3259         mgp->tx_boundary = 2048;
3260         mgp->fw_name = myri10ge_fw_unaligned;
3261
3262 }
3263
3264 static void myri10ge_select_firmware(struct myri10ge_priv *mgp)
3265 {
3266         int overridden = 0;
3267
3268         if (myri10ge_force_firmware == 0) {
3269                 int link_width, exp_cap;
3270                 u16 lnk;
3271
3272                 exp_cap = pci_find_capability(mgp->pdev, PCI_CAP_ID_EXP);
3273                 pci_read_config_word(mgp->pdev, exp_cap + PCI_EXP_LNKSTA, &lnk);
3274                 link_width = (lnk >> 4) & 0x3f;
3275
3276                 /* Check to see if Link is less than 8 or if the
3277                  * upstream bridge is known to provide aligned
3278                  * completions */
3279                 if (link_width < 8) {
3280                         dev_info(&mgp->pdev->dev, "PCIE x%d Link\n",
3281                                  link_width);
3282                         mgp->tx_boundary = 4096;
3283                         mgp->fw_name = myri10ge_fw_aligned;
3284                 } else {
3285                         myri10ge_firmware_probe(mgp);
3286                 }
3287         } else {
3288                 if (myri10ge_force_firmware == 1) {
3289                         dev_info(&mgp->pdev->dev,
3290                                  "Assuming aligned completions (forced)\n");
3291                         mgp->tx_boundary = 4096;
3292                         mgp->fw_name = myri10ge_fw_aligned;
3293                 } else {
3294                         dev_info(&mgp->pdev->dev,
3295                                  "Assuming unaligned completions (forced)\n");
3296                         mgp->tx_boundary = 2048;
3297                         mgp->fw_name = myri10ge_fw_unaligned;
3298                 }
3299         }
3300         if (myri10ge_fw_name != NULL) {
3301                 overridden = 1;
3302                 mgp->fw_name = myri10ge_fw_name;
3303         }
3304         if (mgp->board_number < MYRI10GE_MAX_BOARDS &&
3305             myri10ge_fw_names[mgp->board_number] != NULL &&
3306             strlen(myri10ge_fw_names[mgp->board_number])) {
3307                 mgp->fw_name = myri10ge_fw_names[mgp->board_number];
3308                 overridden = 1;
3309         }
3310         if (overridden)
3311                 dev_info(&mgp->pdev->dev, "overriding firmware to %s\n",
3312                          mgp->fw_name);
3313 }
3314
3315 #ifdef CONFIG_PM
3316 static int myri10ge_suspend(struct pci_dev *pdev, pm_message_t state)
3317 {
3318         struct myri10ge_priv *mgp;
3319         struct net_device *netdev;
3320
3321         mgp = pci_get_drvdata(pdev);
3322         if (mgp == NULL)
3323                 return -EINVAL;
3324         netdev = mgp->dev;
3325
3326         netif_device_detach(netdev);
3327         if (netif_running(netdev)) {
3328                 netdev_info(netdev, "closing\n");
3329                 rtnl_lock();
3330                 myri10ge_close(netdev);
3331                 rtnl_unlock();
3332         }
3333         myri10ge_dummy_rdma(mgp, 0);
3334         pci_save_state(pdev);
3335         pci_disable_device(pdev);
3336
3337         return pci_set_power_state(pdev, pci_choose_state(pdev, state));
3338 }
3339
3340 static int myri10ge_resume(struct pci_dev *pdev)
3341 {
3342         struct myri10ge_priv *mgp;
3343         struct net_device *netdev;
3344         int status;
3345         u16 vendor;
3346
3347         mgp = pci_get_drvdata(pdev);
3348         if (mgp == NULL)
3349                 return -EINVAL;
3350         netdev = mgp->dev;
3351         pci_set_power_state(pdev, 0);   /* zeros conf space as a side effect */
3352         msleep(5);              /* give card time to respond */
3353         pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor);
3354         if (vendor == 0xffff) {
3355                 netdev_err(mgp->dev, "device disappeared!\n");
3356                 return -EIO;
3357         }
3358
3359         status = pci_restore_state(pdev);
3360         if (status)
3361                 return status;
3362
3363         status = pci_enable_device(pdev);
3364         if (status) {
3365                 dev_err(&pdev->dev, "failed to enable device\n");
3366                 return status;
3367         }
3368
3369         pci_set_master(pdev);
3370
3371         myri10ge_reset(mgp);
3372         myri10ge_dummy_rdma(mgp, 1);
3373
3374         /* Save configuration space to be restored if the
3375          * nic resets due to a parity error */
3376         pci_save_state(pdev);
3377
3378         if (netif_running(netdev)) {
3379                 rtnl_lock();
3380                 status = myri10ge_open(netdev);
3381                 rtnl_unlock();
3382                 if (status != 0)
3383                         goto abort_with_enabled;
3384
3385         }
3386         netif_device_attach(netdev);
3387
3388         return 0;
3389
3390 abort_with_enabled:
3391         pci_disable_device(pdev);
3392         return -EIO;
3393
3394 }
3395 #endif                          /* CONFIG_PM */
3396
3397 static u32 myri10ge_read_reboot(struct myri10ge_priv *mgp)
3398 {
3399         struct pci_dev *pdev = mgp->pdev;
3400         int vs = mgp->vendor_specific_offset;
3401         u32 reboot;
3402
3403         /*enter read32 mode */
3404         pci_write_config_byte(pdev, vs + 0x10, 0x3);
3405
3406         /*read REBOOT_STATUS (0xfffffff0) */
3407         pci_write_config_dword(pdev, vs + 0x18, 0xfffffff0);
3408         pci_read_config_dword(pdev, vs + 0x14, &reboot);
3409         return reboot;
3410 }
3411
3412 /*
3413  * This watchdog is used to check whether the board has suffered
3414  * from a parity error and needs to be recovered.
3415  */
3416 static void myri10ge_watchdog(struct work_struct *work)
3417 {
3418         struct myri10ge_priv *mgp =
3419             container_of(work, struct myri10ge_priv, watchdog_work);
3420         struct myri10ge_tx_buf *tx;
3421         u32 reboot;
3422         int status, rebooted;
3423         int i;
3424         u16 cmd, vendor;
3425
3426         mgp->watchdog_resets++;
3427         pci_read_config_word(mgp->pdev, PCI_COMMAND, &cmd);
3428         rebooted = 0;
3429         if ((cmd & PCI_COMMAND_MASTER) == 0) {
3430                 /* Bus master DMA disabled?  Check to see
3431                  * if the card rebooted due to a parity error
3432                  * For now, just report it */
3433                 reboot = myri10ge_read_reboot(mgp);
3434                 netdev_err(mgp->dev, "NIC rebooted (0x%x),%s resetting\n",
3435                            reboot,
3436                            myri10ge_reset_recover ? "" : " not");
3437                 if (myri10ge_reset_recover == 0)
3438                         return;
3439                 rtnl_lock();
3440                 mgp->rebooted = 1;
3441                 rebooted = 1;
3442                 myri10ge_close(mgp->dev);
3443                 myri10ge_reset_recover--;
3444                 mgp->rebooted = 0;
3445                 /*
3446                  * A rebooted nic will come back with config space as
3447                  * it was after power was applied to PCIe bus.
3448                  * Attempt to restore config space which was saved
3449                  * when the driver was loaded, or the last time the
3450                  * nic was resumed from power saving mode.
3451                  */
3452                 pci_restore_state(mgp->pdev);
3453
3454                 /* save state again for accounting reasons */
3455                 pci_save_state(mgp->pdev);
3456
3457         } else {
3458                 /* if we get back -1's from our slot, perhaps somebody
3459                  * powered off our card.  Don't try to reset it in
3460                  * this case */
3461                 if (cmd == 0xffff) {
3462                         pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor);
3463                         if (vendor == 0xffff) {
3464                                 netdev_err(mgp->dev, "device disappeared!\n");
3465                                 return;
3466                         }
3467                 }
3468                 /* Perhaps it is a software error.  Try to reset */
3469
3470                 netdev_err(mgp->dev, "device timeout, resetting\n");
3471                 for (i = 0; i < mgp->num_slices; i++) {
3472                         tx = &mgp->ss[i].tx;
3473                         netdev_err(mgp->dev, "(%d): %d %d %d %d %d %d\n",
3474                                    i, tx->queue_active, tx->req,
3475                                    tx->done, tx->pkt_start, tx->pkt_done,
3476                                    (int)ntohl(mgp->ss[i].fw_stats->
3477                                               send_done_count));
3478                         msleep(2000);
3479                         netdev_info(mgp->dev, "(%d): %d %d %d %d %d %d\n",
3480                                     i, tx->queue_active, tx->req,
3481                                     tx->done, tx->pkt_start, tx->pkt_done,
3482                                     (int)ntohl(mgp->ss[i].fw_stats->
3483                                                send_done_count));
3484                 }
3485         }
3486
3487         if (!rebooted) {
3488                 rtnl_lock();
3489                 myri10ge_close(mgp->dev);
3490         }
3491         status = myri10ge_load_firmware(mgp, 1);
3492         if (status != 0)
3493                 netdev_err(mgp->dev, "failed to load firmware\n");
3494         else
3495                 myri10ge_open(mgp->dev);
3496         rtnl_unlock();
3497 }
3498
3499 /*
3500  * We use our own timer routine rather than relying upon
3501  * netdev->tx_timeout because we have a very large hardware transmit
3502  * queue.  Due to the large queue, the netdev->tx_timeout function
3503  * cannot detect a NIC with a parity error in a timely fashion if the
3504  * NIC is lightly loaded.
3505  */
3506 static void myri10ge_watchdog_timer(unsigned long arg)
3507 {
3508         struct myri10ge_priv *mgp;
3509         struct myri10ge_slice_state *ss;
3510         int i, reset_needed, busy_slice_cnt;
3511         u32 rx_pause_cnt;
3512         u16 cmd;
3513
3514         mgp = (struct myri10ge_priv *)arg;
3515
3516         rx_pause_cnt = ntohl(mgp->ss[0].fw_stats->dropped_pause);
3517         busy_slice_cnt = 0;
3518         for (i = 0, reset_needed = 0;
3519              i < mgp->num_slices && reset_needed == 0; ++i) {
3520
3521                 ss = &mgp->ss[i];
3522                 if (ss->rx_small.watchdog_needed) {
3523                         myri10ge_alloc_rx_pages(mgp, &ss->rx_small,
3524                                                 mgp->small_bytes + MXGEFW_PAD,
3525                                                 1);
3526                         if (ss->rx_small.fill_cnt - ss->rx_small.cnt >=
3527                             myri10ge_fill_thresh)
3528                                 ss->rx_small.watchdog_needed = 0;
3529                 }
3530                 if (ss->rx_big.watchdog_needed) {
3531                         myri10ge_alloc_rx_pages(mgp, &ss->rx_big,
3532                                                 mgp->big_bytes, 1);
3533                         if (ss->rx_big.fill_cnt - ss->rx_big.cnt >=
3534                             myri10ge_fill_thresh)
3535                                 ss->rx_big.watchdog_needed = 0;
3536                 }
3537
3538                 if (ss->tx.req != ss->tx.done &&
3539                     ss->tx.done == ss->watchdog_tx_done &&
3540                     ss->watchdog_tx_req != ss->watchdog_tx_done) {
3541                         /* nic seems like it might be stuck.. */
3542                         if (rx_pause_cnt != mgp->watchdog_pause) {
3543                                 if (net_ratelimit())
3544                                         netdev_err(mgp->dev, "slice %d: TX paused, check link partner\n",
3545                                                    i);
3546                         } else {
3547                                 netdev_warn(mgp->dev, "slice %d stuck:", i);
3548                                 reset_needed = 1;
3549                         }
3550                 }
3551                 if (ss->watchdog_tx_done != ss->tx.done ||
3552                     ss->watchdog_rx_done != ss->rx_done.cnt) {
3553                         busy_slice_cnt++;
3554                 }
3555                 ss->watchdog_tx_done = ss->tx.done;
3556                 ss->watchdog_tx_req = ss->tx.req;
3557                 ss->watchdog_rx_done = ss->rx_done.cnt;
3558         }
3559         /* if we've sent or received no traffic, poll the NIC to
3560          * ensure it is still there.  Otherwise, we risk not noticing
3561          * an error in a timely fashion */
3562         if (busy_slice_cnt == 0) {
3563                 pci_read_config_word(mgp->pdev, PCI_COMMAND, &cmd);
3564                 if ((cmd & PCI_COMMAND_MASTER) == 0) {
3565                         reset_needed = 1;
3566                 }
3567         }
3568         mgp->watchdog_pause = rx_pause_cnt;
3569
3570         if (reset_needed) {
3571                 schedule_work(&mgp->watchdog_work);
3572         } else {
3573                 /* rearm timer */
3574                 mod_timer(&mgp->watchdog_timer,
3575                           jiffies + myri10ge_watchdog_timeout * HZ);
3576         }
3577 }
3578
3579 static void myri10ge_free_slices(struct myri10ge_priv *mgp)
3580 {
3581         struct myri10ge_slice_state *ss;
3582         struct pci_dev *pdev = mgp->pdev;
3583         size_t bytes;
3584         int i;
3585
3586         if (mgp->ss == NULL)
3587                 return;
3588
3589         for (i = 0; i < mgp->num_slices; i++) {
3590                 ss = &mgp->ss[i];
3591                 if (ss->rx_done.entry != NULL) {
3592                         bytes = mgp->max_intr_slots *
3593                             sizeof(*ss->rx_done.entry);
3594                         dma_free_coherent(&pdev->dev, bytes,
3595                                           ss->rx_done.entry, ss->rx_done.bus);
3596                         ss->rx_done.entry = NULL;
3597                 }
3598                 if (ss->fw_stats != NULL) {
3599                         bytes = sizeof(*ss->fw_stats);
3600                         dma_free_coherent(&pdev->dev, bytes,
3601                                           ss->fw_stats, ss->fw_stats_bus);
3602                         ss->fw_stats = NULL;
3603                 }
3604         }
3605         kfree(mgp->ss);
3606         mgp->ss = NULL;
3607 }
3608
3609 static int myri10ge_alloc_slices(struct myri10ge_priv *mgp)
3610 {
3611         struct myri10ge_slice_state *ss;
3612         struct pci_dev *pdev = mgp->pdev;
3613         size_t bytes;
3614         int i;
3615
3616         bytes = sizeof(*mgp->ss) * mgp->num_slices;
3617         mgp->ss = kzalloc(bytes, GFP_KERNEL);
3618         if (mgp->ss == NULL) {
3619                 return -ENOMEM;
3620         }
3621
3622         for (i = 0; i < mgp->num_slices; i++) {
3623                 ss = &mgp->ss[i];
3624                 bytes = mgp->max_intr_slots * sizeof(*ss->rx_done.entry);
3625                 ss->rx_done.entry = dma_alloc_coherent(&pdev->dev, bytes,
3626                                                        &ss->rx_done.bus,
3627                                                        GFP_KERNEL);
3628                 if (ss->rx_done.entry == NULL)
3629                         goto abort;
3630                 memset(ss->rx_done.entry, 0, bytes);
3631                 bytes = sizeof(*ss->fw_stats);
3632                 ss->fw_stats = dma_alloc_coherent(&pdev->dev, bytes,
3633                                                   &ss->fw_stats_bus,
3634                                                   GFP_KERNEL);
3635                 if (ss->fw_stats == NULL)
3636                         goto abort;
3637                 ss->mgp = mgp;
3638                 ss->dev = mgp->dev;
3639                 netif_napi_add(ss->dev, &ss->napi, myri10ge_poll,
3640                                myri10ge_napi_weight);
3641         }
3642         return 0;
3643 abort:
3644         myri10ge_free_slices(mgp);
3645         return -ENOMEM;
3646 }
3647
3648 /*
3649  * This function determines the number of slices supported.
3650  * The number slices is the minumum of the number of CPUS,
3651  * the number of MSI-X irqs supported, the number of slices
3652  * supported by the firmware
3653  */
3654 static void myri10ge_probe_slices(struct myri10ge_priv *mgp)
3655 {
3656         struct myri10ge_cmd cmd;
3657         struct pci_dev *pdev = mgp->pdev;
3658         char *old_fw;
3659         int i, status, ncpus, msix_cap;
3660
3661         mgp->num_slices = 1;
3662         msix_cap = pci_find_capability(pdev, PCI_CAP_ID_MSIX);
3663         ncpus = num_online_cpus();
3664
3665         if (myri10ge_max_slices == 1 || msix_cap == 0 ||
3666             (myri10ge_max_slices == -1 && ncpus < 2))
3667                 return;
3668
3669         /* try to load the slice aware rss firmware */
3670         old_fw = mgp->fw_name;
3671         if (myri10ge_fw_name != NULL) {
3672                 dev_info(&mgp->pdev->dev, "overriding rss firmware to %s\n",
3673                          myri10ge_fw_name);
3674                 mgp->fw_name = myri10ge_fw_name;
3675         } else if (old_fw == myri10ge_fw_aligned)
3676                 mgp->fw_name = myri10ge_fw_rss_aligned;
3677         else
3678                 mgp->fw_name = myri10ge_fw_rss_unaligned;
3679         status = myri10ge_load_firmware(mgp, 0);
3680         if (status != 0) {
3681                 dev_info(&pdev->dev, "Rss firmware not found\n");
3682                 return;
3683         }
3684
3685         /* hit the board with a reset to ensure it is alive */
3686         memset(&cmd, 0, sizeof(cmd));
3687         status = myri10ge_send_cmd(mgp, MXGEFW_CMD_RESET, &cmd, 0);
3688         if (status != 0) {
3689                 dev_err(&mgp->pdev->dev, "failed reset\n");
3690                 goto abort_with_fw;
3691         }
3692
3693         mgp->max_intr_slots = cmd.data0 / sizeof(struct mcp_slot);
3694
3695         /* tell it the size of the interrupt queues */
3696         cmd.data0 = mgp->max_intr_slots * sizeof(struct mcp_slot);
3697         status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_SIZE, &cmd, 0);
3698         if (status != 0) {
3699                 dev_err(&mgp->pdev->dev, "failed MXGEFW_CMD_SET_INTRQ_SIZE\n");
3700                 goto abort_with_fw;
3701         }
3702
3703         /* ask the maximum number of slices it supports */
3704         status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_MAX_RSS_QUEUES, &cmd, 0);
3705         if (status != 0)
3706                 goto abort_with_fw;
3707         else
3708                 mgp->num_slices = cmd.data0;
3709
3710         /* Only allow multiple slices if MSI-X is usable */
3711         if (!myri10ge_msi) {
3712                 goto abort_with_fw;
3713         }
3714
3715         /* if the admin did not specify a limit to how many
3716          * slices we should use, cap it automatically to the
3717          * number of CPUs currently online */
3718         if (myri10ge_max_slices == -1)
3719                 myri10ge_max_slices = ncpus;
3720
3721         if (mgp->num_slices > myri10ge_max_slices)
3722                 mgp->num_slices = myri10ge_max_slices;
3723
3724         /* Now try to allocate as many MSI-X vectors as we have
3725          * slices. We give up on MSI-X if we can only get a single
3726          * vector. */
3727
3728         mgp->msix_vectors = kzalloc(mgp->num_slices *
3729                                     sizeof(*mgp->msix_vectors), GFP_KERNEL);
3730         if (mgp->msix_vectors == NULL)
3731                 goto disable_msix;
3732         for (i = 0; i < mgp->num_slices; i++) {
3733                 mgp->msix_vectors[i].entry = i;
3734         }
3735
3736         while (mgp->num_slices > 1) {
3737                 /* make sure it is a power of two */
3738                 while (!is_power_of_2(mgp->num_slices))
3739                         mgp->num_slices--;
3740                 if (mgp->num_slices == 1)
3741                         goto disable_msix;
3742                 status = pci_enable_msix(pdev, mgp->msix_vectors,
3743                                          mgp->num_slices);
3744                 if (status == 0) {
3745                         pci_disable_msix(pdev);
3746                         return;
3747                 }
3748                 if (status > 0)
3749                         mgp->num_slices = status;
3750                 else
3751                         goto disable_msix;
3752         }
3753
3754 disable_msix:
3755         if (mgp->msix_vectors != NULL) {
3756                 kfree(mgp->msix_vectors);
3757                 mgp->msix_vectors = NULL;
3758         }
3759
3760 abort_with_fw:
3761         mgp->num_slices = 1;
3762         mgp->fw_name = old_fw;
3763         myri10ge_load_firmware(mgp, 0);
3764 }
3765
3766 static const struct net_device_ops myri10ge_netdev_ops = {
3767         .ndo_open               = myri10ge_open,
3768         .ndo_stop               = myri10ge_close,
3769         .ndo_start_xmit         = myri10ge_xmit,
3770         .ndo_get_stats          = myri10ge_get_stats,
3771         .ndo_validate_addr      = eth_validate_addr,
3772         .ndo_change_mtu         = myri10ge_change_mtu,
3773         .ndo_set_multicast_list = myri10ge_set_multicast_list,
3774         .ndo_set_mac_address    = myri10ge_set_mac_address,
3775 };
3776
3777 static int myri10ge_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3778 {
3779         struct net_device *netdev;
3780         struct myri10ge_priv *mgp;
3781         struct device *dev = &pdev->dev;
3782         int i;
3783         int status = -ENXIO;
3784         int dac_enabled;
3785         unsigned hdr_offset, ss_offset;
3786         static int board_number;
3787
3788         netdev = alloc_etherdev_mq(sizeof(*mgp), MYRI10GE_MAX_SLICES);
3789         if (netdev == NULL) {
3790                 dev_err(dev, "Could not allocate ethernet device\n");
3791                 return -ENOMEM;
3792         }
3793
3794         SET_NETDEV_DEV(netdev, &pdev->dev);
3795
3796         mgp = netdev_priv(netdev);
3797         mgp->dev = netdev;
3798         mgp->pdev = pdev;
3799         mgp->csum_flag = MXGEFW_FLAGS_CKSUM;
3800         mgp->pause = myri10ge_flow_control;
3801         mgp->intr_coal_delay = myri10ge_intr_coal_delay;
3802         mgp->msg_enable = netif_msg_init(myri10ge_debug, MYRI10GE_MSG_DEFAULT);
3803         mgp->board_number = board_number;
3804         init_waitqueue_head(&mgp->down_wq);
3805
3806         if (pci_enable_device(pdev)) {
3807                 dev_err(&pdev->dev, "pci_enable_device call failed\n");
3808                 status = -ENODEV;
3809                 goto abort_with_netdev;
3810         }
3811
3812         /* Find the vendor-specific cap so we can check
3813          * the reboot register later on */
3814         mgp->vendor_specific_offset
3815             = pci_find_capability(pdev, PCI_CAP_ID_VNDR);
3816
3817         /* Set our max read request to 4KB */
3818         status = pcie_set_readrq(pdev, 4096);
3819         if (status != 0) {
3820                 dev_err(&pdev->dev, "Error %d writing PCI_EXP_DEVCTL\n",
3821                         status);
3822                 goto abort_with_enabled;
3823         }
3824
3825         pci_set_master(pdev);
3826         dac_enabled = 1;
3827         status = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
3828         if (status != 0) {
3829                 dac_enabled = 0;
3830                 dev_err(&pdev->dev,
3831                         "64-bit pci address mask was refused, "
3832                         "trying 32-bit\n");
3833                 status = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3834         }
3835         if (status != 0) {
3836                 dev_err(&pdev->dev, "Error %d setting DMA mask\n", status);
3837                 goto abort_with_enabled;
3838         }
3839         (void)pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
3840         mgp->cmd = dma_alloc_coherent(&pdev->dev, sizeof(*mgp->cmd),
3841                                       &mgp->cmd_bus, GFP_KERNEL);
3842         if (mgp->cmd == NULL)
3843                 goto abort_with_enabled;
3844
3845         mgp->board_span = pci_resource_len(pdev, 0);
3846         mgp->iomem_base = pci_resource_start(pdev, 0);
3847         mgp->mtrr = -1;
3848         mgp->wc_enabled = 0;
3849 #ifdef CONFIG_MTRR
3850         mgp->mtrr = mtrr_add(mgp->iomem_base, mgp->board_span,
3851                              MTRR_TYPE_WRCOMB, 1);
3852         if (mgp->mtrr >= 0)
3853                 mgp->wc_enabled = 1;
3854 #endif
3855         mgp->sram = ioremap_wc(mgp->iomem_base, mgp->board_span);
3856         if (mgp->sram == NULL) {
3857                 dev_err(&pdev->dev, "ioremap failed for %ld bytes at 0x%lx\n",
3858                         mgp->board_span, mgp->iomem_base);
3859                 status = -ENXIO;
3860                 goto abort_with_mtrr;
3861         }
3862         hdr_offset =
3863             ntohl(__raw_readl(mgp->sram + MCP_HEADER_PTR_OFFSET)) & 0xffffc;
3864         ss_offset = hdr_offset + offsetof(struct mcp_gen_header, string_specs);
3865         mgp->sram_size = ntohl(__raw_readl(mgp->sram + ss_offset));
3866         if (mgp->sram_size > mgp->board_span ||
3867             mgp->sram_size <= MYRI10GE_FW_OFFSET) {
3868                 dev_err(&pdev->dev,
3869                         "invalid sram_size %dB or board span %ldB\n",
3870                         mgp->sram_size, mgp->board_span);
3871                 goto abort_with_ioremap;
3872         }
3873         memcpy_fromio(mgp->eeprom_strings,
3874                       mgp->sram + mgp->sram_size, MYRI10GE_EEPROM_STRINGS_SIZE);
3875         memset(mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE - 2, 0, 2);
3876         status = myri10ge_read_mac_addr(mgp);
3877         if (status)
3878                 goto abort_with_ioremap;
3879
3880         for (i = 0; i < ETH_ALEN; i++)
3881                 netdev->dev_addr[i] = mgp->mac_addr[i];
3882
3883         myri10ge_select_firmware(mgp);
3884
3885         status = myri10ge_load_firmware(mgp, 1);
3886         if (status != 0) {
3887                 dev_err(&pdev->dev, "failed to load firmware\n");
3888                 goto abort_with_ioremap;
3889         }
3890         myri10ge_probe_slices(mgp);
3891         status = myri10ge_alloc_slices(mgp);
3892         if (status != 0) {
3893                 dev_err(&pdev->dev, "failed to alloc slice state\n");
3894                 goto abort_with_firmware;
3895         }
3896         netdev->real_num_tx_queues = mgp->num_slices;
3897         status = myri10ge_reset(mgp);
3898         if (status != 0) {
3899                 dev_err(&pdev->dev, "failed reset\n");
3900                 goto abort_with_slices;
3901         }
3902 #ifdef CONFIG_MYRI10GE_DCA
3903         myri10ge_setup_dca(mgp);
3904 #endif
3905         pci_set_drvdata(pdev, mgp);
3906         if ((myri10ge_initial_mtu + ETH_HLEN) > MYRI10GE_MAX_ETHER_MTU)
3907                 myri10ge_initial_mtu = MYRI10GE_MAX_ETHER_MTU - ETH_HLEN;
3908         if ((myri10ge_initial_mtu + ETH_HLEN) < 68)
3909                 myri10ge_initial_mtu = 68;
3910
3911         netdev->netdev_ops = &myri10ge_netdev_ops;
3912         netdev->mtu = myri10ge_initial_mtu;
3913         netdev->base_addr = mgp->iomem_base;
3914         netdev->features = mgp->features;
3915
3916         if (dac_enabled)
3917                 netdev->features |= NETIF_F_HIGHDMA;
3918         netdev->features |= NETIF_F_LRO;
3919
3920         netdev->vlan_features |= mgp->features;
3921         if (mgp->fw_ver_tiny < 37)
3922                 netdev->vlan_features &= ~NETIF_F_TSO6;
3923         if (mgp->fw_ver_tiny < 32)
3924                 netdev->vlan_features &= ~NETIF_F_TSO;
3925
3926         /* make sure we can get an irq, and that MSI can be
3927          * setup (if available).  Also ensure netdev->irq
3928          * is set to correct value if MSI is enabled */
3929         status = myri10ge_request_irq(mgp);
3930         if (status != 0)
3931                 goto abort_with_firmware;
3932         netdev->irq = pdev->irq;
3933         myri10ge_free_irq(mgp);
3934
3935         /* Save configuration space to be restored if the
3936          * nic resets due to a parity error */
3937         pci_save_state(pdev);
3938
3939         /* Setup the watchdog timer */
3940         setup_timer(&mgp->watchdog_timer, myri10ge_watchdog_timer,
3941                     (unsigned long)mgp);
3942
3943         spin_lock_init(&mgp->stats_lock);
3944         SET_ETHTOOL_OPS(netdev, &myri10ge_ethtool_ops);
3945         INIT_WORK(&mgp->watchdog_work, myri10ge_watchdog);
3946         status = register_netdev(netdev);
3947         if (status != 0) {
3948                 dev_err(&pdev->dev, "register_netdev failed: %d\n", status);
3949                 goto abort_with_state;
3950         }
3951         if (mgp->msix_enabled)
3952                 dev_info(dev, "%d MSI-X IRQs, tx bndry %d, fw %s, WC %s\n",
3953                          mgp->num_slices, mgp->tx_boundary, mgp->fw_name,
3954                          (mgp->wc_enabled ? "Enabled" : "Disabled"));
3955         else
3956                 dev_info(dev, "%s IRQ %d, tx bndry %d, fw %s, WC %s\n",
3957                          mgp->msi_enabled ? "MSI" : "xPIC",
3958                          netdev->irq, mgp->tx_boundary, mgp->fw_name,
3959                          (mgp->wc_enabled ? "Enabled" : "Disabled"));
3960
3961         board_number++;
3962         return 0;
3963
3964 abort_with_state:
3965         pci_restore_state(pdev);
3966
3967 abort_with_slices:
3968         myri10ge_free_slices(mgp);
3969
3970 abort_with_firmware:
3971         myri10ge_dummy_rdma(mgp, 0);
3972
3973 abort_with_ioremap:
3974         if (mgp->mac_addr_string != NULL)
3975                 dev_err(&pdev->dev,
3976                         "myri10ge_probe() failed: MAC=%s, SN=%ld\n",
3977                         mgp->mac_addr_string, mgp->serial_number);
3978         iounmap(mgp->sram);
3979
3980 abort_with_mtrr:
3981 #ifdef CONFIG_MTRR
3982         if (mgp->mtrr >= 0)
3983                 mtrr_del(mgp->mtrr, mgp->iomem_base, mgp->board_span);
3984 #endif
3985         dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd),
3986                           mgp->cmd, mgp->cmd_bus);
3987
3988 abort_with_enabled:
3989         pci_disable_device(pdev);
3990
3991 abort_with_netdev:
3992         free_netdev(netdev);
3993         return status;
3994 }
3995
3996 /*
3997  * myri10ge_remove
3998  *
3999  * Does what is necessary to shutdown one Myrinet device. Called
4000  *   once for each Myrinet card by the kernel when a module is
4001  *   unloaded.
4002  */
4003 static void myri10ge_remove(struct pci_dev *pdev)
4004 {
4005         struct myri10ge_priv *mgp;
4006         struct net_device *netdev;
4007
4008         mgp = pci_get_drvdata(pdev);
4009         if (mgp == NULL)
4010                 return;
4011
4012         flush_scheduled_work();
4013         netdev = mgp->dev;
4014         unregister_netdev(netdev);
4015
4016 #ifdef CONFIG_MYRI10GE_DCA
4017         myri10ge_teardown_dca(mgp);
4018 #endif
4019         myri10ge_dummy_rdma(mgp, 0);
4020
4021         /* avoid a memory leak */
4022         pci_restore_state(pdev);
4023
4024         iounmap(mgp->sram);
4025
4026 #ifdef CONFIG_MTRR
4027         if (mgp->mtrr >= 0)
4028                 mtrr_del(mgp->mtrr, mgp->iomem_base, mgp->board_span);
4029 #endif
4030         myri10ge_free_slices(mgp);
4031         if (mgp->msix_vectors != NULL)
4032                 kfree(mgp->msix_vectors);
4033         dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd),
4034                           mgp->cmd, mgp->cmd_bus);
4035
4036         free_netdev(netdev);
4037         pci_disable_device(pdev);
4038         pci_set_drvdata(pdev, NULL);
4039 }
4040
4041 #define PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E      0x0008
4042 #define PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E_9    0x0009
4043
4044 static DEFINE_PCI_DEVICE_TABLE(myri10ge_pci_tbl) = {
4045         {PCI_DEVICE(PCI_VENDOR_ID_MYRICOM, PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E)},
4046         {PCI_DEVICE
4047          (PCI_VENDOR_ID_MYRICOM, PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E_9)},
4048         {0},
4049 };
4050
4051 MODULE_DEVICE_TABLE(pci, myri10ge_pci_tbl);
4052
4053 static struct pci_driver myri10ge_driver = {
4054         .name = "myri10ge",
4055         .probe = myri10ge_probe,
4056         .remove = myri10ge_remove,
4057         .id_table = myri10ge_pci_tbl,
4058 #ifdef CONFIG_PM
4059         .suspend = myri10ge_suspend,
4060         .resume = myri10ge_resume,
4061 #endif
4062 };
4063
4064 #ifdef CONFIG_MYRI10GE_DCA
4065 static int
4066 myri10ge_notify_dca(struct notifier_block *nb, unsigned long event, void *p)
4067 {
4068         int err = driver_for_each_device(&myri10ge_driver.driver,
4069                                          NULL, &event,
4070                                          myri10ge_notify_dca_device);
4071
4072         if (err)
4073                 return NOTIFY_BAD;
4074         return NOTIFY_DONE;
4075 }
4076
4077 static struct notifier_block myri10ge_dca_notifier = {
4078         .notifier_call = myri10ge_notify_dca,
4079         .next = NULL,
4080         .priority = 0,
4081 };
4082 #endif                          /* CONFIG_MYRI10GE_DCA */
4083
4084 static __init int myri10ge_init_module(void)
4085 {
4086         pr_info("Version %s\n", MYRI10GE_VERSION_STR);
4087
4088         if (myri10ge_rss_hash > MXGEFW_RSS_HASH_TYPE_MAX) {
4089                 pr_err("Illegal rssh hash type %d, defaulting to source port\n",
4090                        myri10ge_rss_hash);
4091                 myri10ge_rss_hash = MXGEFW_RSS_HASH_TYPE_SRC_PORT;
4092         }
4093 #ifdef CONFIG_MYRI10GE_DCA
4094         dca_register_notify(&myri10ge_dca_notifier);
4095 #endif
4096         if (myri10ge_max_slices > MYRI10GE_MAX_SLICES)
4097                 myri10ge_max_slices = MYRI10GE_MAX_SLICES;
4098
4099         return pci_register_driver(&myri10ge_driver);
4100 }
4101
4102 module_init(myri10ge_init_module);
4103
4104 static __exit void myri10ge_cleanup_module(void)
4105 {
4106 #ifdef CONFIG_MYRI10GE_DCA
4107         dca_unregister_notify(&myri10ge_dca_notifier);
4108 #endif
4109         pci_unregister_driver(&myri10ge_driver);
4110 }
4111
4112 module_exit(myri10ge_cleanup_module);