2 * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports
3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
5 * Based on the 64360 driver from:
6 * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il>
7 * Rabeeh Khoury <rabeeh@marvell.com>
9 * Copyright (C) 2003 PMC-Sierra, Inc.,
10 * written by Manish Lachwani
12 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
14 * Copyright (C) 2004-2006 MontaVista Software, Inc.
15 * Dale Farnsworth <dale@farnsworth.org>
17 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
18 * <sjhill@realitydiluted.com>
20 * Copyright (C) 2007-2008 Marvell Semiconductor
21 * Lennert Buytenhek <buytenh@marvell.com>
23 * This program is free software; you can redistribute it and/or
24 * modify it under the terms of the GNU General Public License
25 * as published by the Free Software Foundation; either version 2
26 * of the License, or (at your option) any later version.
28 * This program is distributed in the hope that it will be useful,
29 * but WITHOUT ANY WARRANTY; without even the implied warranty of
30 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
31 * GNU General Public License for more details.
33 * You should have received a copy of the GNU General Public License
34 * along with this program; if not, write to the Free Software
35 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
38 #include <linux/init.h>
39 #include <linux/dma-mapping.h>
41 #include <linux/tcp.h>
42 #include <linux/udp.h>
43 #include <linux/etherdevice.h>
44 #include <linux/delay.h>
45 #include <linux/ethtool.h>
46 #include <linux/platform_device.h>
47 #include <linux/module.h>
48 #include <linux/kernel.h>
49 #include <linux/spinlock.h>
50 #include <linux/workqueue.h>
51 #include <linux/mii.h>
52 #include <linux/mv643xx_eth.h>
54 #include <asm/types.h>
55 #include <asm/system.h>
57 static char mv643xx_eth_driver_name[] = "mv643xx_eth";
58 static char mv643xx_eth_driver_version[] = "1.1";
60 #define MV643XX_ETH_CHECKSUM_OFFLOAD_TX
61 #define MV643XX_ETH_NAPI
62 #define MV643XX_ETH_TX_FAST_REFILL
64 #ifdef MV643XX_ETH_CHECKSUM_OFFLOAD_TX
65 #define MAX_DESCS_PER_SKB (MAX_SKB_FRAGS + 1)
67 #define MAX_DESCS_PER_SKB 1
71 * Registers shared between all ports.
73 #define PHY_ADDR 0x0000
74 #define SMI_REG 0x0004
75 #define WINDOW_BASE(w) (0x0200 + ((w) << 3))
76 #define WINDOW_SIZE(w) (0x0204 + ((w) << 3))
77 #define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2))
78 #define WINDOW_BAR_ENABLE 0x0290
79 #define WINDOW_PROTECT(w) (0x0294 + ((w) << 4))
84 #define PORT_CONFIG(p) (0x0400 + ((p) << 10))
85 #define UNICAST_PROMISCUOUS_MODE 0x00000001
86 #define PORT_CONFIG_EXT(p) (0x0404 + ((p) << 10))
87 #define MAC_ADDR_LOW(p) (0x0414 + ((p) << 10))
88 #define MAC_ADDR_HIGH(p) (0x0418 + ((p) << 10))
89 #define SDMA_CONFIG(p) (0x041c + ((p) << 10))
90 #define PORT_SERIAL_CONTROL(p) (0x043c + ((p) << 10))
91 #define PORT_STATUS(p) (0x0444 + ((p) << 10))
92 #define TX_FIFO_EMPTY 0x00000400
93 #define TXQ_COMMAND(p) (0x0448 + ((p) << 10))
94 #define TXQ_FIX_PRIO_CONF(p) (0x044c + ((p) << 10))
95 #define TX_BW_RATE(p) (0x0450 + ((p) << 10))
96 #define TX_BW_MTU(p) (0x0458 + ((p) << 10))
97 #define TX_BW_BURST(p) (0x045c + ((p) << 10))
98 #define INT_CAUSE(p) (0x0460 + ((p) << 10))
99 #define INT_TX_END_0 0x00080000
100 #define INT_TX_END 0x07f80000
101 #define INT_RX 0x0007fbfc
102 #define INT_EXT 0x00000002
103 #define INT_CAUSE_EXT(p) (0x0464 + ((p) << 10))
104 #define INT_EXT_LINK 0x00100000
105 #define INT_EXT_PHY 0x00010000
106 #define INT_EXT_TX_ERROR_0 0x00000100
107 #define INT_EXT_TX_0 0x00000001
108 #define INT_EXT_TX 0x0000ffff
109 #define INT_MASK(p) (0x0468 + ((p) << 10))
110 #define INT_MASK_EXT(p) (0x046c + ((p) << 10))
111 #define TX_FIFO_URGENT_THRESHOLD(p) (0x0474 + ((p) << 10))
112 #define TXQ_FIX_PRIO_CONF_MOVED(p) (0x04dc + ((p) << 10))
113 #define TX_BW_RATE_MOVED(p) (0x04e0 + ((p) << 10))
114 #define TX_BW_MTU_MOVED(p) (0x04e8 + ((p) << 10))
115 #define TX_BW_BURST_MOVED(p) (0x04ec + ((p) << 10))
116 #define RXQ_CURRENT_DESC_PTR(p, q) (0x060c + ((p) << 10) + ((q) << 4))
117 #define RXQ_COMMAND(p) (0x0680 + ((p) << 10))
118 #define TXQ_CURRENT_DESC_PTR(p, q) (0x06c0 + ((p) << 10) + ((q) << 2))
119 #define TXQ_BW_TOKENS(p, q) (0x0700 + ((p) << 10) + ((q) << 4))
120 #define TXQ_BW_CONF(p, q) (0x0704 + ((p) << 10) + ((q) << 4))
121 #define TXQ_BW_WRR_CONF(p, q) (0x0708 + ((p) << 10) + ((q) << 4))
122 #define MIB_COUNTERS(p) (0x1000 + ((p) << 7))
123 #define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10))
124 #define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10))
125 #define UNICAST_TABLE(p) (0x1600 + ((p) << 10))
129 * SDMA configuration register.
131 #define RX_BURST_SIZE_4_64BIT (2 << 1)
132 #define BLM_RX_NO_SWAP (1 << 4)
133 #define BLM_TX_NO_SWAP (1 << 5)
134 #define TX_BURST_SIZE_4_64BIT (2 << 22)
136 #if defined(__BIG_ENDIAN)
137 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
138 RX_BURST_SIZE_4_64BIT | \
139 TX_BURST_SIZE_4_64BIT
140 #elif defined(__LITTLE_ENDIAN)
141 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
142 RX_BURST_SIZE_4_64BIT | \
145 TX_BURST_SIZE_4_64BIT
147 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
152 * Port serial control register.
154 #define SET_MII_SPEED_TO_100 (1 << 24)
155 #define SET_GMII_SPEED_TO_1000 (1 << 23)
156 #define SET_FULL_DUPLEX_MODE (1 << 21)
157 #define MAX_RX_PACKET_1522BYTE (1 << 17)
158 #define MAX_RX_PACKET_9700BYTE (5 << 17)
159 #define MAX_RX_PACKET_MASK (7 << 17)
160 #define DISABLE_AUTO_NEG_SPEED_GMII (1 << 13)
161 #define DO_NOT_FORCE_LINK_FAIL (1 << 10)
162 #define SERIAL_PORT_CONTROL_RESERVED (1 << 9)
163 #define DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1 << 3)
164 #define DISABLE_AUTO_NEG_FOR_DUPLEX (1 << 2)
165 #define FORCE_LINK_PASS (1 << 1)
166 #define SERIAL_PORT_ENABLE (1 << 0)
168 #define DEFAULT_RX_QUEUE_SIZE 400
169 #define DEFAULT_TX_QUEUE_SIZE 800
175 #if defined(__BIG_ENDIAN)
177 u16 byte_cnt; /* Descriptor buffer byte count */
178 u16 buf_size; /* Buffer size */
179 u32 cmd_sts; /* Descriptor command status */
180 u32 next_desc_ptr; /* Next descriptor pointer */
181 u32 buf_ptr; /* Descriptor buffer pointer */
185 u16 byte_cnt; /* buffer byte count */
186 u16 l4i_chk; /* CPU provided TCP checksum */
187 u32 cmd_sts; /* Command/status field */
188 u32 next_desc_ptr; /* Pointer to next descriptor */
189 u32 buf_ptr; /* pointer to buffer for this descriptor*/
191 #elif defined(__LITTLE_ENDIAN)
193 u32 cmd_sts; /* Descriptor command status */
194 u16 buf_size; /* Buffer size */
195 u16 byte_cnt; /* Descriptor buffer byte count */
196 u32 buf_ptr; /* Descriptor buffer pointer */
197 u32 next_desc_ptr; /* Next descriptor pointer */
201 u32 cmd_sts; /* Command/status field */
202 u16 l4i_chk; /* CPU provided TCP checksum */
203 u16 byte_cnt; /* buffer byte count */
204 u32 buf_ptr; /* pointer to buffer for this descriptor*/
205 u32 next_desc_ptr; /* Pointer to next descriptor */
208 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
211 /* RX & TX descriptor command */
212 #define BUFFER_OWNED_BY_DMA 0x80000000
214 /* RX & TX descriptor status */
215 #define ERROR_SUMMARY 0x00000001
217 /* RX descriptor status */
218 #define LAYER_4_CHECKSUM_OK 0x40000000
219 #define RX_ENABLE_INTERRUPT 0x20000000
220 #define RX_FIRST_DESC 0x08000000
221 #define RX_LAST_DESC 0x04000000
223 /* TX descriptor command */
224 #define TX_ENABLE_INTERRUPT 0x00800000
225 #define GEN_CRC 0x00400000
226 #define TX_FIRST_DESC 0x00200000
227 #define TX_LAST_DESC 0x00100000
228 #define ZERO_PADDING 0x00080000
229 #define GEN_IP_V4_CHECKSUM 0x00040000
230 #define GEN_TCP_UDP_CHECKSUM 0x00020000
231 #define UDP_FRAME 0x00010000
233 #define TX_IHL_SHIFT 11
236 /* global *******************************************************************/
237 struct mv643xx_eth_shared_private {
239 * Ethernet controller base address.
244 * Protects access to SMI_REG, which is shared between ports.
249 * Per-port MBUS window access register value.
254 * Hardware-specific parameters.
257 int extended_rx_coal_limit;
258 int tx_bw_control_moved;
262 /* per-port *****************************************************************/
263 struct mib_counters {
264 u64 good_octets_received;
265 u32 bad_octets_received;
266 u32 internal_mac_transmit_err;
267 u32 good_frames_received;
268 u32 bad_frames_received;
269 u32 broadcast_frames_received;
270 u32 multicast_frames_received;
271 u32 frames_64_octets;
272 u32 frames_65_to_127_octets;
273 u32 frames_128_to_255_octets;
274 u32 frames_256_to_511_octets;
275 u32 frames_512_to_1023_octets;
276 u32 frames_1024_to_max_octets;
277 u64 good_octets_sent;
278 u32 good_frames_sent;
279 u32 excessive_collision;
280 u32 multicast_frames_sent;
281 u32 broadcast_frames_sent;
282 u32 unrec_mac_control_received;
284 u32 good_fc_received;
286 u32 undersize_received;
287 u32 fragments_received;
288 u32 oversize_received;
290 u32 mac_receive_error;
305 struct rx_desc *rx_desc_area;
306 dma_addr_t rx_desc_dma;
307 int rx_desc_area_size;
308 struct sk_buff **rx_skb;
310 struct timer_list rx_oom;
322 struct tx_desc *tx_desc_area;
323 dma_addr_t tx_desc_dma;
324 int tx_desc_area_size;
325 struct sk_buff **tx_skb;
328 struct mv643xx_eth_private {
329 struct mv643xx_eth_shared_private *shared;
332 struct net_device *dev;
334 struct mv643xx_eth_shared_private *shared_smi;
339 struct mib_counters mib_counters;
340 struct work_struct tx_timeout_task;
341 struct mii_if_info mii;
346 int default_rx_ring_size;
347 unsigned long rx_desc_sram_addr;
348 int rx_desc_sram_size;
351 struct napi_struct napi;
352 struct rx_queue rxq[8];
357 int default_tx_ring_size;
358 unsigned long tx_desc_sram_addr;
359 int tx_desc_sram_size;
362 struct tx_queue txq[8];
363 #ifdef MV643XX_ETH_TX_FAST_REFILL
364 int tx_clean_threshold;
369 /* port register accessors **************************************************/
370 static inline u32 rdl(struct mv643xx_eth_private *mp, int offset)
372 return readl(mp->shared->base + offset);
375 static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data)
377 writel(data, mp->shared->base + offset);
381 /* rxq/txq helper functions *************************************************/
382 static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq)
384 return container_of(rxq, struct mv643xx_eth_private, rxq[rxq->index]);
387 static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq)
389 return container_of(txq, struct mv643xx_eth_private, txq[txq->index]);
392 static void rxq_enable(struct rx_queue *rxq)
394 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
395 wrl(mp, RXQ_COMMAND(mp->port_num), 1 << rxq->index);
398 static void rxq_disable(struct rx_queue *rxq)
400 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
401 u8 mask = 1 << rxq->index;
403 wrl(mp, RXQ_COMMAND(mp->port_num), mask << 8);
404 while (rdl(mp, RXQ_COMMAND(mp->port_num)) & mask)
408 static void txq_enable(struct tx_queue *txq)
410 struct mv643xx_eth_private *mp = txq_to_mp(txq);
411 wrl(mp, TXQ_COMMAND(mp->port_num), 1 << txq->index);
414 static void txq_disable(struct tx_queue *txq)
416 struct mv643xx_eth_private *mp = txq_to_mp(txq);
417 u8 mask = 1 << txq->index;
419 wrl(mp, TXQ_COMMAND(mp->port_num), mask << 8);
420 while (rdl(mp, TXQ_COMMAND(mp->port_num)) & mask)
424 static void __txq_maybe_wake(struct tx_queue *txq)
426 struct mv643xx_eth_private *mp = txq_to_mp(txq);
429 * netif_{stop,wake}_queue() flow control only applies to
432 BUG_ON(txq->index != mp->txq_primary);
434 if (txq->tx_ring_size - txq->tx_desc_count >= MAX_DESCS_PER_SKB)
435 netif_wake_queue(mp->dev);
439 /* rx ***********************************************************************/
440 static void txq_reclaim(struct tx_queue *txq, int force);
442 static void rxq_refill(struct rx_queue *rxq)
444 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
447 spin_lock_irqsave(&mp->lock, flags);
449 while (rxq->rx_desc_count < rxq->rx_ring_size) {
456 * Reserve 2+14 bytes for an ethernet header (the
457 * hardware automatically prepends 2 bytes of dummy
458 * data to each received packet), 4 bytes for a VLAN
459 * header, and 4 bytes for the trailing FCS -- 24
462 skb_size = mp->dev->mtu + 24;
464 skb = dev_alloc_skb(skb_size + dma_get_cache_alignment() - 1);
468 unaligned = (u32)skb->data & (dma_get_cache_alignment() - 1);
470 skb_reserve(skb, dma_get_cache_alignment() - unaligned);
472 rxq->rx_desc_count++;
473 rx = rxq->rx_used_desc;
474 rxq->rx_used_desc = (rx + 1) % rxq->rx_ring_size;
476 rxq->rx_desc_area[rx].buf_ptr = dma_map_single(NULL, skb->data,
477 skb_size, DMA_FROM_DEVICE);
478 rxq->rx_desc_area[rx].buf_size = skb_size;
479 rxq->rx_skb[rx] = skb;
481 rxq->rx_desc_area[rx].cmd_sts = BUFFER_OWNED_BY_DMA |
486 * The hardware automatically prepends 2 bytes of
487 * dummy data to each received packet, so that the
488 * IP header ends up 16-byte aligned.
493 if (rxq->rx_desc_count != rxq->rx_ring_size) {
494 rxq->rx_oom.expires = jiffies + (HZ / 10);
495 add_timer(&rxq->rx_oom);
498 spin_unlock_irqrestore(&mp->lock, flags);
501 static inline void rxq_refill_timer_wrapper(unsigned long data)
503 rxq_refill((struct rx_queue *)data);
506 static int rxq_process(struct rx_queue *rxq, int budget)
508 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
509 struct net_device_stats *stats = &mp->dev->stats;
513 while (rx < budget) {
514 struct rx_desc *rx_desc;
515 unsigned int cmd_sts;
519 spin_lock_irqsave(&mp->lock, flags);
521 rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc];
523 cmd_sts = rx_desc->cmd_sts;
524 if (cmd_sts & BUFFER_OWNED_BY_DMA) {
525 spin_unlock_irqrestore(&mp->lock, flags);
530 skb = rxq->rx_skb[rxq->rx_curr_desc];
531 rxq->rx_skb[rxq->rx_curr_desc] = NULL;
533 rxq->rx_curr_desc = (rxq->rx_curr_desc + 1) % rxq->rx_ring_size;
535 spin_unlock_irqrestore(&mp->lock, flags);
537 dma_unmap_single(NULL, rx_desc->buf_ptr + 2,
538 mp->dev->mtu + 24, DMA_FROM_DEVICE);
539 rxq->rx_desc_count--;
545 * Note that the descriptor byte count includes 2 dummy
546 * bytes automatically inserted by the hardware at the
547 * start of the packet (which we don't count), and a 4
548 * byte CRC at the end of the packet (which we do count).
551 stats->rx_bytes += rx_desc->byte_cnt - 2;
554 * In case we received a packet without first / last bits
555 * on, or the error summary bit is set, the packet needs
558 if (((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
559 (RX_FIRST_DESC | RX_LAST_DESC))
560 || (cmd_sts & ERROR_SUMMARY)) {
563 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
564 (RX_FIRST_DESC | RX_LAST_DESC)) {
566 dev_printk(KERN_ERR, &mp->dev->dev,
567 "received packet spanning "
568 "multiple descriptors\n");
571 if (cmd_sts & ERROR_SUMMARY)
574 dev_kfree_skb_irq(skb);
577 * The -4 is for the CRC in the trailer of the
580 skb_put(skb, rx_desc->byte_cnt - 2 - 4);
582 if (cmd_sts & LAYER_4_CHECKSUM_OK) {
583 skb->ip_summed = CHECKSUM_UNNECESSARY;
585 (cmd_sts & 0x0007fff8) >> 3);
587 skb->protocol = eth_type_trans(skb, mp->dev);
588 #ifdef MV643XX_ETH_NAPI
589 netif_receive_skb(skb);
595 mp->dev->last_rx = jiffies;
603 #ifdef MV643XX_ETH_NAPI
604 static int mv643xx_eth_poll(struct napi_struct *napi, int budget)
606 struct mv643xx_eth_private *mp;
610 mp = container_of(napi, struct mv643xx_eth_private, napi);
612 #ifdef MV643XX_ETH_TX_FAST_REFILL
613 if (++mp->tx_clean_threshold > 5) {
614 mp->tx_clean_threshold = 0;
615 for (i = 0; i < 8; i++)
616 if (mp->txq_mask & (1 << i))
617 txq_reclaim(mp->txq + i, 0);
622 for (i = 7; rx < budget && i >= 0; i--)
623 if (mp->rxq_mask & (1 << i))
624 rx += rxq_process(mp->rxq + i, budget - rx);
627 netif_rx_complete(mp->dev, napi);
628 wrl(mp, INT_CAUSE(mp->port_num), 0);
629 wrl(mp, INT_CAUSE_EXT(mp->port_num), 0);
630 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
638 /* tx ***********************************************************************/
639 static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
643 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
644 skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
645 if (fragp->size <= 8 && fragp->page_offset & 7)
652 static int txq_alloc_desc_index(struct tx_queue *txq)
656 BUG_ON(txq->tx_desc_count >= txq->tx_ring_size);
658 tx_desc_curr = txq->tx_curr_desc;
659 txq->tx_curr_desc = (tx_desc_curr + 1) % txq->tx_ring_size;
661 BUG_ON(txq->tx_curr_desc == txq->tx_used_desc);
666 static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb)
668 int nr_frags = skb_shinfo(skb)->nr_frags;
671 for (frag = 0; frag < nr_frags; frag++) {
672 skb_frag_t *this_frag;
674 struct tx_desc *desc;
676 this_frag = &skb_shinfo(skb)->frags[frag];
677 tx_index = txq_alloc_desc_index(txq);
678 desc = &txq->tx_desc_area[tx_index];
681 * The last fragment will generate an interrupt
682 * which will free the skb on TX completion.
684 if (frag == nr_frags - 1) {
685 desc->cmd_sts = BUFFER_OWNED_BY_DMA |
686 ZERO_PADDING | TX_LAST_DESC |
688 txq->tx_skb[tx_index] = skb;
690 desc->cmd_sts = BUFFER_OWNED_BY_DMA;
691 txq->tx_skb[tx_index] = NULL;
695 desc->byte_cnt = this_frag->size;
696 desc->buf_ptr = dma_map_page(NULL, this_frag->page,
697 this_frag->page_offset,
703 static inline __be16 sum16_as_be(__sum16 sum)
705 return (__force __be16)sum;
708 static void txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb)
710 struct mv643xx_eth_private *mp = txq_to_mp(txq);
711 int nr_frags = skb_shinfo(skb)->nr_frags;
713 struct tx_desc *desc;
717 cmd_sts = TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA;
719 tx_index = txq_alloc_desc_index(txq);
720 desc = &txq->tx_desc_area[tx_index];
723 txq_submit_frag_skb(txq, skb);
725 length = skb_headlen(skb);
726 txq->tx_skb[tx_index] = NULL;
728 cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT;
730 txq->tx_skb[tx_index] = skb;
733 desc->byte_cnt = length;
734 desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE);
736 if (skb->ip_summed == CHECKSUM_PARTIAL) {
737 BUG_ON(skb->protocol != htons(ETH_P_IP));
739 cmd_sts |= GEN_TCP_UDP_CHECKSUM |
741 ip_hdr(skb)->ihl << TX_IHL_SHIFT;
743 switch (ip_hdr(skb)->protocol) {
745 cmd_sts |= UDP_FRAME;
746 desc->l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check));
749 desc->l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check));
755 /* Errata BTS #50, IHL must be 5 if no HW checksum */
756 cmd_sts |= 5 << TX_IHL_SHIFT;
760 /* ensure all other descriptors are written before first cmd_sts */
762 desc->cmd_sts = cmd_sts;
764 /* clear TX_END interrupt status */
765 wrl(mp, INT_CAUSE(mp->port_num), ~(INT_TX_END_0 << txq->index));
766 rdl(mp, INT_CAUSE(mp->port_num));
768 /* ensure all descriptors are written before poking hardware */
772 txq->tx_desc_count += nr_frags + 1;
775 static int mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev)
777 struct mv643xx_eth_private *mp = netdev_priv(dev);
778 struct net_device_stats *stats = &dev->stats;
779 struct tx_queue *txq;
782 if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) {
784 dev_printk(KERN_DEBUG, &dev->dev,
785 "failed to linearize skb with tiny "
786 "unaligned fragment\n");
787 return NETDEV_TX_BUSY;
790 spin_lock_irqsave(&mp->lock, flags);
792 txq = mp->txq + mp->txq_primary;
794 if (txq->tx_ring_size - txq->tx_desc_count < MAX_DESCS_PER_SKB) {
795 spin_unlock_irqrestore(&mp->lock, flags);
796 if (txq->index == mp->txq_primary && net_ratelimit())
797 dev_printk(KERN_ERR, &dev->dev,
798 "primary tx queue full?!\n");
803 txq_submit_skb(txq, skb);
804 stats->tx_bytes += skb->len;
806 dev->trans_start = jiffies;
808 if (txq->index == mp->txq_primary) {
811 entries_left = txq->tx_ring_size - txq->tx_desc_count;
812 if (entries_left < MAX_DESCS_PER_SKB)
813 netif_stop_queue(dev);
816 spin_unlock_irqrestore(&mp->lock, flags);
822 /* tx rate control **********************************************************/
824 * Set total maximum TX rate (shared by all TX queues for this port)
825 * to 'rate' bits per second, with a maximum burst of 'burst' bytes.
827 static void tx_set_rate(struct mv643xx_eth_private *mp, int rate, int burst)
833 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
834 if (token_rate > 1023)
837 mtu = (mp->dev->mtu + 255) >> 8;
841 bucket_size = (burst + 255) >> 8;
842 if (bucket_size > 65535)
845 if (mp->shared->tx_bw_control_moved) {
846 wrl(mp, TX_BW_RATE_MOVED(mp->port_num), token_rate);
847 wrl(mp, TX_BW_MTU_MOVED(mp->port_num), mtu);
848 wrl(mp, TX_BW_BURST_MOVED(mp->port_num), bucket_size);
850 wrl(mp, TX_BW_RATE(mp->port_num), token_rate);
851 wrl(mp, TX_BW_MTU(mp->port_num), mtu);
852 wrl(mp, TX_BW_BURST(mp->port_num), bucket_size);
856 static void txq_set_rate(struct tx_queue *txq, int rate, int burst)
858 struct mv643xx_eth_private *mp = txq_to_mp(txq);
862 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
863 if (token_rate > 1023)
866 bucket_size = (burst + 255) >> 8;
867 if (bucket_size > 65535)
870 wrl(mp, TXQ_BW_TOKENS(mp->port_num, txq->index), token_rate << 14);
871 wrl(mp, TXQ_BW_CONF(mp->port_num, txq->index),
872 (bucket_size << 10) | token_rate);
875 static void txq_set_fixed_prio_mode(struct tx_queue *txq)
877 struct mv643xx_eth_private *mp = txq_to_mp(txq);
882 * Turn on fixed priority mode.
884 if (mp->shared->tx_bw_control_moved)
885 off = TXQ_FIX_PRIO_CONF_MOVED(mp->port_num);
887 off = TXQ_FIX_PRIO_CONF(mp->port_num);
890 val |= 1 << txq->index;
894 static void txq_set_wrr(struct tx_queue *txq, int weight)
896 struct mv643xx_eth_private *mp = txq_to_mp(txq);
901 * Turn off fixed priority mode.
903 if (mp->shared->tx_bw_control_moved)
904 off = TXQ_FIX_PRIO_CONF_MOVED(mp->port_num);
906 off = TXQ_FIX_PRIO_CONF(mp->port_num);
909 val &= ~(1 << txq->index);
913 * Configure WRR weight for this queue.
915 off = TXQ_BW_WRR_CONF(mp->port_num, txq->index);
918 val = (val & ~0xff) | (weight & 0xff);
923 /* mii management interface *************************************************/
924 #define SMI_BUSY 0x10000000
925 #define SMI_READ_VALID 0x08000000
926 #define SMI_OPCODE_READ 0x04000000
927 #define SMI_OPCODE_WRITE 0x00000000
929 static void smi_reg_read(struct mv643xx_eth_private *mp, unsigned int addr,
930 unsigned int reg, unsigned int *value)
932 void __iomem *smi_reg = mp->shared_smi->base + SMI_REG;
936 /* the SMI register is a shared resource */
937 spin_lock_irqsave(&mp->shared_smi->phy_lock, flags);
939 /* wait for the SMI register to become available */
940 for (i = 0; readl(smi_reg) & SMI_BUSY; i++) {
942 printk("%s: PHY busy timeout\n", mp->dev->name);
948 writel(SMI_OPCODE_READ | (reg << 21) | (addr << 16), smi_reg);
950 /* now wait for the data to be valid */
951 for (i = 0; !(readl(smi_reg) & SMI_READ_VALID); i++) {
953 printk("%s: PHY read timeout\n", mp->dev->name);
959 *value = readl(smi_reg) & 0xffff;
961 spin_unlock_irqrestore(&mp->shared_smi->phy_lock, flags);
964 static void smi_reg_write(struct mv643xx_eth_private *mp,
966 unsigned int reg, unsigned int value)
968 void __iomem *smi_reg = mp->shared_smi->base + SMI_REG;
972 /* the SMI register is a shared resource */
973 spin_lock_irqsave(&mp->shared_smi->phy_lock, flags);
975 /* wait for the SMI register to become available */
976 for (i = 0; readl(smi_reg) & SMI_BUSY; i++) {
978 printk("%s: PHY busy timeout\n", mp->dev->name);
984 writel(SMI_OPCODE_WRITE | (reg << 21) |
985 (addr << 16) | (value & 0xffff), smi_reg);
987 spin_unlock_irqrestore(&mp->shared_smi->phy_lock, flags);
991 /* mib counters *************************************************************/
992 static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset)
994 return rdl(mp, MIB_COUNTERS(mp->port_num) + offset);
997 static void mib_counters_clear(struct mv643xx_eth_private *mp)
1001 for (i = 0; i < 0x80; i += 4)
1005 static void mib_counters_update(struct mv643xx_eth_private *mp)
1007 struct mib_counters *p = &mp->mib_counters;
1009 p->good_octets_received += mib_read(mp, 0x00);
1010 p->good_octets_received += (u64)mib_read(mp, 0x04) << 32;
1011 p->bad_octets_received += mib_read(mp, 0x08);
1012 p->internal_mac_transmit_err += mib_read(mp, 0x0c);
1013 p->good_frames_received += mib_read(mp, 0x10);
1014 p->bad_frames_received += mib_read(mp, 0x14);
1015 p->broadcast_frames_received += mib_read(mp, 0x18);
1016 p->multicast_frames_received += mib_read(mp, 0x1c);
1017 p->frames_64_octets += mib_read(mp, 0x20);
1018 p->frames_65_to_127_octets += mib_read(mp, 0x24);
1019 p->frames_128_to_255_octets += mib_read(mp, 0x28);
1020 p->frames_256_to_511_octets += mib_read(mp, 0x2c);
1021 p->frames_512_to_1023_octets += mib_read(mp, 0x30);
1022 p->frames_1024_to_max_octets += mib_read(mp, 0x34);
1023 p->good_octets_sent += mib_read(mp, 0x38);
1024 p->good_octets_sent += (u64)mib_read(mp, 0x3c) << 32;
1025 p->good_frames_sent += mib_read(mp, 0x40);
1026 p->excessive_collision += mib_read(mp, 0x44);
1027 p->multicast_frames_sent += mib_read(mp, 0x48);
1028 p->broadcast_frames_sent += mib_read(mp, 0x4c);
1029 p->unrec_mac_control_received += mib_read(mp, 0x50);
1030 p->fc_sent += mib_read(mp, 0x54);
1031 p->good_fc_received += mib_read(mp, 0x58);
1032 p->bad_fc_received += mib_read(mp, 0x5c);
1033 p->undersize_received += mib_read(mp, 0x60);
1034 p->fragments_received += mib_read(mp, 0x64);
1035 p->oversize_received += mib_read(mp, 0x68);
1036 p->jabber_received += mib_read(mp, 0x6c);
1037 p->mac_receive_error += mib_read(mp, 0x70);
1038 p->bad_crc_event += mib_read(mp, 0x74);
1039 p->collision += mib_read(mp, 0x78);
1040 p->late_collision += mib_read(mp, 0x7c);
1044 /* ethtool ******************************************************************/
1045 struct mv643xx_eth_stats {
1046 char stat_string[ETH_GSTRING_LEN];
1053 { #m, FIELD_SIZEOF(struct net_device_stats, m), \
1054 offsetof(struct net_device, stats.m), -1 }
1056 #define MIBSTAT(m) \
1057 { #m, FIELD_SIZEOF(struct mib_counters, m), \
1058 -1, offsetof(struct mv643xx_eth_private, mib_counters.m) }
1060 static const struct mv643xx_eth_stats mv643xx_eth_stats[] = {
1069 MIBSTAT(good_octets_received),
1070 MIBSTAT(bad_octets_received),
1071 MIBSTAT(internal_mac_transmit_err),
1072 MIBSTAT(good_frames_received),
1073 MIBSTAT(bad_frames_received),
1074 MIBSTAT(broadcast_frames_received),
1075 MIBSTAT(multicast_frames_received),
1076 MIBSTAT(frames_64_octets),
1077 MIBSTAT(frames_65_to_127_octets),
1078 MIBSTAT(frames_128_to_255_octets),
1079 MIBSTAT(frames_256_to_511_octets),
1080 MIBSTAT(frames_512_to_1023_octets),
1081 MIBSTAT(frames_1024_to_max_octets),
1082 MIBSTAT(good_octets_sent),
1083 MIBSTAT(good_frames_sent),
1084 MIBSTAT(excessive_collision),
1085 MIBSTAT(multicast_frames_sent),
1086 MIBSTAT(broadcast_frames_sent),
1087 MIBSTAT(unrec_mac_control_received),
1089 MIBSTAT(good_fc_received),
1090 MIBSTAT(bad_fc_received),
1091 MIBSTAT(undersize_received),
1092 MIBSTAT(fragments_received),
1093 MIBSTAT(oversize_received),
1094 MIBSTAT(jabber_received),
1095 MIBSTAT(mac_receive_error),
1096 MIBSTAT(bad_crc_event),
1098 MIBSTAT(late_collision),
1101 static int mv643xx_eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1103 struct mv643xx_eth_private *mp = netdev_priv(dev);
1106 spin_lock_irq(&mp->lock);
1107 err = mii_ethtool_gset(&mp->mii, cmd);
1108 spin_unlock_irq(&mp->lock);
1111 * The MAC does not support 1000baseT_Half.
1113 cmd->supported &= ~SUPPORTED_1000baseT_Half;
1114 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1119 static int mv643xx_eth_get_settings_phyless(struct net_device *dev, struct ethtool_cmd *cmd)
1121 cmd->supported = SUPPORTED_MII;
1122 cmd->advertising = ADVERTISED_MII;
1123 cmd->speed = SPEED_1000;
1124 cmd->duplex = DUPLEX_FULL;
1125 cmd->port = PORT_MII;
1126 cmd->phy_address = 0;
1127 cmd->transceiver = XCVR_INTERNAL;
1128 cmd->autoneg = AUTONEG_DISABLE;
1135 static int mv643xx_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1137 struct mv643xx_eth_private *mp = netdev_priv(dev);
1141 * The MAC does not support 1000baseT_Half.
1143 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1145 spin_lock_irq(&mp->lock);
1146 err = mii_ethtool_sset(&mp->mii, cmd);
1147 spin_unlock_irq(&mp->lock);
1152 static int mv643xx_eth_set_settings_phyless(struct net_device *dev, struct ethtool_cmd *cmd)
1157 static void mv643xx_eth_get_drvinfo(struct net_device *dev,
1158 struct ethtool_drvinfo *drvinfo)
1160 strncpy(drvinfo->driver, mv643xx_eth_driver_name, 32);
1161 strncpy(drvinfo->version, mv643xx_eth_driver_version, 32);
1162 strncpy(drvinfo->fw_version, "N/A", 32);
1163 strncpy(drvinfo->bus_info, "platform", 32);
1164 drvinfo->n_stats = ARRAY_SIZE(mv643xx_eth_stats);
1167 static int mv643xx_eth_nway_reset(struct net_device *dev)
1169 struct mv643xx_eth_private *mp = netdev_priv(dev);
1171 return mii_nway_restart(&mp->mii);
1174 static int mv643xx_eth_nway_reset_phyless(struct net_device *dev)
1179 static u32 mv643xx_eth_get_link(struct net_device *dev)
1181 struct mv643xx_eth_private *mp = netdev_priv(dev);
1183 return mii_link_ok(&mp->mii);
1186 static u32 mv643xx_eth_get_link_phyless(struct net_device *dev)
1191 static void mv643xx_eth_get_strings(struct net_device *dev,
1192 uint32_t stringset, uint8_t *data)
1196 if (stringset == ETH_SS_STATS) {
1197 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1198 memcpy(data + i * ETH_GSTRING_LEN,
1199 mv643xx_eth_stats[i].stat_string,
1205 static void mv643xx_eth_get_ethtool_stats(struct net_device *dev,
1206 struct ethtool_stats *stats,
1209 struct mv643xx_eth_private *mp = dev->priv;
1212 mib_counters_update(mp);
1214 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1215 const struct mv643xx_eth_stats *stat;
1218 stat = mv643xx_eth_stats + i;
1220 if (stat->netdev_off >= 0)
1221 p = ((void *)mp->dev) + stat->netdev_off;
1223 p = ((void *)mp) + stat->mp_off;
1225 data[i] = (stat->sizeof_stat == 8) ?
1226 *(uint64_t *)p : *(uint32_t *)p;
1230 static int mv643xx_eth_get_sset_count(struct net_device *dev, int sset)
1232 if (sset == ETH_SS_STATS)
1233 return ARRAY_SIZE(mv643xx_eth_stats);
1238 static const struct ethtool_ops mv643xx_eth_ethtool_ops = {
1239 .get_settings = mv643xx_eth_get_settings,
1240 .set_settings = mv643xx_eth_set_settings,
1241 .get_drvinfo = mv643xx_eth_get_drvinfo,
1242 .nway_reset = mv643xx_eth_nway_reset,
1243 .get_link = mv643xx_eth_get_link,
1244 .set_sg = ethtool_op_set_sg,
1245 .get_strings = mv643xx_eth_get_strings,
1246 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
1247 .get_sset_count = mv643xx_eth_get_sset_count,
1250 static const struct ethtool_ops mv643xx_eth_ethtool_ops_phyless = {
1251 .get_settings = mv643xx_eth_get_settings_phyless,
1252 .set_settings = mv643xx_eth_set_settings_phyless,
1253 .get_drvinfo = mv643xx_eth_get_drvinfo,
1254 .nway_reset = mv643xx_eth_nway_reset_phyless,
1255 .get_link = mv643xx_eth_get_link_phyless,
1256 .set_sg = ethtool_op_set_sg,
1257 .get_strings = mv643xx_eth_get_strings,
1258 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
1259 .get_sset_count = mv643xx_eth_get_sset_count,
1263 /* address handling *********************************************************/
1264 static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr)
1269 mac_h = rdl(mp, MAC_ADDR_HIGH(mp->port_num));
1270 mac_l = rdl(mp, MAC_ADDR_LOW(mp->port_num));
1272 addr[0] = (mac_h >> 24) & 0xff;
1273 addr[1] = (mac_h >> 16) & 0xff;
1274 addr[2] = (mac_h >> 8) & 0xff;
1275 addr[3] = mac_h & 0xff;
1276 addr[4] = (mac_l >> 8) & 0xff;
1277 addr[5] = mac_l & 0xff;
1280 static void init_mac_tables(struct mv643xx_eth_private *mp)
1284 for (i = 0; i < 0x100; i += 4) {
1285 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, 0);
1286 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, 0);
1289 for (i = 0; i < 0x10; i += 4)
1290 wrl(mp, UNICAST_TABLE(mp->port_num) + i, 0);
1293 static void set_filter_table_entry(struct mv643xx_eth_private *mp,
1294 int table, unsigned char entry)
1296 unsigned int table_reg;
1298 /* Set "accepts frame bit" at specified table entry */
1299 table_reg = rdl(mp, table + (entry & 0xfc));
1300 table_reg |= 0x01 << (8 * (entry & 3));
1301 wrl(mp, table + (entry & 0xfc), table_reg);
1304 static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr)
1310 mac_l = (addr[4] << 8) | addr[5];
1311 mac_h = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
1313 wrl(mp, MAC_ADDR_LOW(mp->port_num), mac_l);
1314 wrl(mp, MAC_ADDR_HIGH(mp->port_num), mac_h);
1316 table = UNICAST_TABLE(mp->port_num);
1317 set_filter_table_entry(mp, table, addr[5] & 0x0f);
1320 static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
1322 struct mv643xx_eth_private *mp = netdev_priv(dev);
1324 /* +2 is for the offset of the HW addr type */
1325 memcpy(dev->dev_addr, addr + 2, 6);
1327 init_mac_tables(mp);
1328 uc_addr_set(mp, dev->dev_addr);
1333 static int addr_crc(unsigned char *addr)
1338 for (i = 0; i < 6; i++) {
1341 crc = (crc ^ addr[i]) << 8;
1342 for (j = 7; j >= 0; j--) {
1343 if (crc & (0x100 << j))
1351 static void mv643xx_eth_set_rx_mode(struct net_device *dev)
1353 struct mv643xx_eth_private *mp = netdev_priv(dev);
1355 struct dev_addr_list *addr;
1358 port_config = rdl(mp, PORT_CONFIG(mp->port_num));
1359 if (dev->flags & IFF_PROMISC)
1360 port_config |= UNICAST_PROMISCUOUS_MODE;
1362 port_config &= ~UNICAST_PROMISCUOUS_MODE;
1363 wrl(mp, PORT_CONFIG(mp->port_num), port_config);
1365 if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) {
1366 int port_num = mp->port_num;
1367 u32 accept = 0x01010101;
1369 for (i = 0; i < 0x100; i += 4) {
1370 wrl(mp, SPECIAL_MCAST_TABLE(port_num) + i, accept);
1371 wrl(mp, OTHER_MCAST_TABLE(port_num) + i, accept);
1376 for (i = 0; i < 0x100; i += 4) {
1377 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, 0);
1378 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, 0);
1381 for (addr = dev->mc_list; addr != NULL; addr = addr->next) {
1382 u8 *a = addr->da_addr;
1385 if (addr->da_addrlen != 6)
1388 if (memcmp(a, "\x01\x00\x5e\x00\x00", 5) == 0) {
1389 table = SPECIAL_MCAST_TABLE(mp->port_num);
1390 set_filter_table_entry(mp, table, a[5]);
1392 int crc = addr_crc(a);
1394 table = OTHER_MCAST_TABLE(mp->port_num);
1395 set_filter_table_entry(mp, table, crc);
1401 /* rx/tx queue initialisation ***********************************************/
1402 static int rxq_init(struct mv643xx_eth_private *mp, int index)
1404 struct rx_queue *rxq = mp->rxq + index;
1405 struct rx_desc *rx_desc;
1411 rxq->rx_ring_size = mp->default_rx_ring_size;
1413 rxq->rx_desc_count = 0;
1414 rxq->rx_curr_desc = 0;
1415 rxq->rx_used_desc = 0;
1417 size = rxq->rx_ring_size * sizeof(struct rx_desc);
1419 if (index == mp->rxq_primary && size <= mp->rx_desc_sram_size) {
1420 rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr,
1421 mp->rx_desc_sram_size);
1422 rxq->rx_desc_dma = mp->rx_desc_sram_addr;
1424 rxq->rx_desc_area = dma_alloc_coherent(NULL, size,
1429 if (rxq->rx_desc_area == NULL) {
1430 dev_printk(KERN_ERR, &mp->dev->dev,
1431 "can't allocate rx ring (%d bytes)\n", size);
1434 memset(rxq->rx_desc_area, 0, size);
1436 rxq->rx_desc_area_size = size;
1437 rxq->rx_skb = kmalloc(rxq->rx_ring_size * sizeof(*rxq->rx_skb),
1439 if (rxq->rx_skb == NULL) {
1440 dev_printk(KERN_ERR, &mp->dev->dev,
1441 "can't allocate rx skb ring\n");
1445 rx_desc = (struct rx_desc *)rxq->rx_desc_area;
1446 for (i = 0; i < rxq->rx_ring_size; i++) {
1447 int nexti = (i + 1) % rxq->rx_ring_size;
1448 rx_desc[i].next_desc_ptr = rxq->rx_desc_dma +
1449 nexti * sizeof(struct rx_desc);
1452 init_timer(&rxq->rx_oom);
1453 rxq->rx_oom.data = (unsigned long)rxq;
1454 rxq->rx_oom.function = rxq_refill_timer_wrapper;
1460 if (index == mp->rxq_primary && size <= mp->rx_desc_sram_size)
1461 iounmap(rxq->rx_desc_area);
1463 dma_free_coherent(NULL, size,
1471 static void rxq_deinit(struct rx_queue *rxq)
1473 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
1478 del_timer_sync(&rxq->rx_oom);
1480 for (i = 0; i < rxq->rx_ring_size; i++) {
1481 if (rxq->rx_skb[i]) {
1482 dev_kfree_skb(rxq->rx_skb[i]);
1483 rxq->rx_desc_count--;
1487 if (rxq->rx_desc_count) {
1488 dev_printk(KERN_ERR, &mp->dev->dev,
1489 "error freeing rx ring -- %d skbs stuck\n",
1490 rxq->rx_desc_count);
1493 if (rxq->index == mp->rxq_primary &&
1494 rxq->rx_desc_area_size <= mp->rx_desc_sram_size)
1495 iounmap(rxq->rx_desc_area);
1497 dma_free_coherent(NULL, rxq->rx_desc_area_size,
1498 rxq->rx_desc_area, rxq->rx_desc_dma);
1503 static int txq_init(struct mv643xx_eth_private *mp, int index)
1505 struct tx_queue *txq = mp->txq + index;
1506 struct tx_desc *tx_desc;
1512 txq->tx_ring_size = mp->default_tx_ring_size;
1514 txq->tx_desc_count = 0;
1515 txq->tx_curr_desc = 0;
1516 txq->tx_used_desc = 0;
1518 size = txq->tx_ring_size * sizeof(struct tx_desc);
1520 if (index == mp->txq_primary && size <= mp->tx_desc_sram_size) {
1521 txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr,
1522 mp->tx_desc_sram_size);
1523 txq->tx_desc_dma = mp->tx_desc_sram_addr;
1525 txq->tx_desc_area = dma_alloc_coherent(NULL, size,
1530 if (txq->tx_desc_area == NULL) {
1531 dev_printk(KERN_ERR, &mp->dev->dev,
1532 "can't allocate tx ring (%d bytes)\n", size);
1535 memset(txq->tx_desc_area, 0, size);
1537 txq->tx_desc_area_size = size;
1538 txq->tx_skb = kmalloc(txq->tx_ring_size * sizeof(*txq->tx_skb),
1540 if (txq->tx_skb == NULL) {
1541 dev_printk(KERN_ERR, &mp->dev->dev,
1542 "can't allocate tx skb ring\n");
1546 tx_desc = (struct tx_desc *)txq->tx_desc_area;
1547 for (i = 0; i < txq->tx_ring_size; i++) {
1548 int nexti = (i + 1) % txq->tx_ring_size;
1549 tx_desc[i].next_desc_ptr = txq->tx_desc_dma +
1550 nexti * sizeof(struct tx_desc);
1557 if (index == mp->txq_primary && size <= mp->tx_desc_sram_size)
1558 iounmap(txq->tx_desc_area);
1560 dma_free_coherent(NULL, size,
1568 static void txq_reclaim(struct tx_queue *txq, int force)
1570 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1571 unsigned long flags;
1573 spin_lock_irqsave(&mp->lock, flags);
1574 while (txq->tx_desc_count > 0) {
1576 struct tx_desc *desc;
1578 struct sk_buff *skb;
1582 tx_index = txq->tx_used_desc;
1583 desc = &txq->tx_desc_area[tx_index];
1584 cmd_sts = desc->cmd_sts;
1586 if (!force && (cmd_sts & BUFFER_OWNED_BY_DMA))
1589 txq->tx_used_desc = (tx_index + 1) % txq->tx_ring_size;
1590 txq->tx_desc_count--;
1592 addr = desc->buf_ptr;
1593 count = desc->byte_cnt;
1594 skb = txq->tx_skb[tx_index];
1595 txq->tx_skb[tx_index] = NULL;
1597 if (cmd_sts & ERROR_SUMMARY) {
1598 dev_printk(KERN_INFO, &mp->dev->dev, "tx error\n");
1599 mp->dev->stats.tx_errors++;
1603 * Drop mp->lock while we free the skb.
1605 spin_unlock_irqrestore(&mp->lock, flags);
1607 if (cmd_sts & TX_FIRST_DESC)
1608 dma_unmap_single(NULL, addr, count, DMA_TO_DEVICE);
1610 dma_unmap_page(NULL, addr, count, DMA_TO_DEVICE);
1613 dev_kfree_skb_irq(skb);
1615 spin_lock_irqsave(&mp->lock, flags);
1617 spin_unlock_irqrestore(&mp->lock, flags);
1620 static void txq_deinit(struct tx_queue *txq)
1622 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1625 txq_reclaim(txq, 1);
1627 BUG_ON(txq->tx_used_desc != txq->tx_curr_desc);
1629 if (txq->index == mp->txq_primary &&
1630 txq->tx_desc_area_size <= mp->tx_desc_sram_size)
1631 iounmap(txq->tx_desc_area);
1633 dma_free_coherent(NULL, txq->tx_desc_area_size,
1634 txq->tx_desc_area, txq->tx_desc_dma);
1640 /* netdev ops and related ***************************************************/
1641 static void update_pscr(struct mv643xx_eth_private *mp, int speed, int duplex)
1646 pscr_o = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
1648 /* clear speed, duplex and rx buffer size fields */
1649 pscr_n = pscr_o & ~(SET_MII_SPEED_TO_100 |
1650 SET_GMII_SPEED_TO_1000 |
1651 SET_FULL_DUPLEX_MODE |
1652 MAX_RX_PACKET_MASK);
1654 if (speed == SPEED_1000) {
1655 pscr_n |= SET_GMII_SPEED_TO_1000 | MAX_RX_PACKET_9700BYTE;
1657 if (speed == SPEED_100)
1658 pscr_n |= SET_MII_SPEED_TO_100;
1659 pscr_n |= MAX_RX_PACKET_1522BYTE;
1662 if (duplex == DUPLEX_FULL)
1663 pscr_n |= SET_FULL_DUPLEX_MODE;
1665 if (pscr_n != pscr_o) {
1666 if ((pscr_o & SERIAL_PORT_ENABLE) == 0)
1667 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr_n);
1671 for (i = 0; i < 8; i++)
1672 if (mp->txq_mask & (1 << i))
1673 txq_disable(mp->txq + i);
1675 pscr_o &= ~SERIAL_PORT_ENABLE;
1676 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr_o);
1677 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr_n);
1678 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr_n);
1680 for (i = 0; i < 8; i++)
1681 if (mp->txq_mask & (1 << i))
1682 txq_enable(mp->txq + i);
1687 static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id)
1689 struct net_device *dev = (struct net_device *)dev_id;
1690 struct mv643xx_eth_private *mp = netdev_priv(dev);
1694 int_cause = rdl(mp, INT_CAUSE(mp->port_num)) &
1695 (INT_TX_END | INT_RX | INT_EXT);
1700 if (int_cause & INT_EXT) {
1701 int_cause_ext = rdl(mp, INT_CAUSE_EXT(mp->port_num))
1702 & (INT_EXT_LINK | INT_EXT_PHY | INT_EXT_TX);
1703 wrl(mp, INT_CAUSE_EXT(mp->port_num), ~int_cause_ext);
1706 if (int_cause_ext & (INT_EXT_PHY | INT_EXT_LINK)) {
1707 if (mp->phy_addr == -1 || mii_link_ok(&mp->mii)) {
1710 if (mp->phy_addr != -1) {
1711 struct ethtool_cmd cmd;
1713 mii_ethtool_gset(&mp->mii, &cmd);
1714 update_pscr(mp, cmd.speed, cmd.duplex);
1717 for (i = 0; i < 8; i++)
1718 if (mp->txq_mask & (1 << i))
1719 txq_enable(mp->txq + i);
1721 if (!netif_carrier_ok(dev)) {
1722 netif_carrier_on(dev);
1723 __txq_maybe_wake(mp->txq + mp->txq_primary);
1725 } else if (netif_carrier_ok(dev)) {
1726 netif_stop_queue(dev);
1727 netif_carrier_off(dev);
1732 * RxBuffer or RxError set for any of the 8 queues?
1734 #ifdef MV643XX_ETH_NAPI
1735 if (int_cause & INT_RX) {
1736 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
1737 rdl(mp, INT_MASK(mp->port_num));
1739 netif_rx_schedule(dev, &mp->napi);
1742 if (int_cause & INT_RX) {
1745 for (i = 7; i >= 0; i--)
1746 if (mp->rxq_mask & (1 << i))
1747 rxq_process(mp->rxq + i, INT_MAX);
1752 * TxBuffer or TxError set for any of the 8 queues?
1754 if (int_cause_ext & INT_EXT_TX) {
1757 for (i = 0; i < 8; i++)
1758 if (mp->txq_mask & (1 << i))
1759 txq_reclaim(mp->txq + i, 0);
1762 * Enough space again in the primary TX queue for a
1765 spin_lock(&mp->lock);
1766 __txq_maybe_wake(mp->txq + mp->txq_primary);
1767 spin_unlock(&mp->lock);
1771 * Any TxEnd interrupts?
1773 if (int_cause & INT_TX_END) {
1776 wrl(mp, INT_CAUSE(mp->port_num), ~(int_cause & INT_TX_END));
1778 spin_lock(&mp->lock);
1779 for (i = 0; i < 8; i++) {
1780 struct tx_queue *txq = mp->txq + i;
1784 if ((int_cause & (INT_TX_END_0 << i)) == 0)
1788 rdl(mp, TXQ_CURRENT_DESC_PTR(mp->port_num, i));
1789 expected_ptr = (u32)txq->tx_desc_dma +
1790 txq->tx_curr_desc * sizeof(struct tx_desc);
1792 if (hw_desc_ptr != expected_ptr)
1795 spin_unlock(&mp->lock);
1801 static void phy_reset(struct mv643xx_eth_private *mp)
1805 smi_reg_read(mp, mp->phy_addr, 0, &data);
1807 smi_reg_write(mp, mp->phy_addr, 0, data);
1811 smi_reg_read(mp, mp->phy_addr, 0, &data);
1812 } while (data & 0x8000);
1815 static void port_start(struct mv643xx_eth_private *mp)
1821 * Configure basic link parameters.
1823 pscr = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
1824 pscr &= ~(SERIAL_PORT_ENABLE | FORCE_LINK_PASS);
1825 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
1826 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL |
1827 DISABLE_AUTO_NEG_SPEED_GMII |
1828 DISABLE_AUTO_NEG_FOR_DUPLEX |
1829 DO_NOT_FORCE_LINK_FAIL |
1830 SERIAL_PORT_CONTROL_RESERVED;
1831 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
1832 pscr |= SERIAL_PORT_ENABLE;
1833 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
1835 wrl(mp, SDMA_CONFIG(mp->port_num), PORT_SDMA_CONFIG_DEFAULT_VALUE);
1838 * Perform PHY reset, if there is a PHY.
1840 if (mp->phy_addr != -1) {
1841 struct ethtool_cmd cmd;
1843 mv643xx_eth_get_settings(mp->dev, &cmd);
1845 mv643xx_eth_set_settings(mp->dev, &cmd);
1849 * Configure TX path and queues.
1851 tx_set_rate(mp, 1000000000, 16777216);
1852 for (i = 0; i < 8; i++) {
1853 struct tx_queue *txq = mp->txq + i;
1854 int off = TXQ_CURRENT_DESC_PTR(mp->port_num, i);
1857 if ((mp->txq_mask & (1 << i)) == 0)
1860 addr = (u32)txq->tx_desc_dma;
1861 addr += txq->tx_curr_desc * sizeof(struct tx_desc);
1864 txq_set_rate(txq, 1000000000, 16777216);
1865 txq_set_fixed_prio_mode(txq);
1869 * Add configured unicast address to address filter table.
1871 uc_addr_set(mp, mp->dev->dev_addr);
1874 * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast
1875 * frames to RX queue #0.
1877 wrl(mp, PORT_CONFIG(mp->port_num), 0x00000000);
1880 * Treat BPDUs as normal multicasts, and disable partition mode.
1882 wrl(mp, PORT_CONFIG_EXT(mp->port_num), 0x00000000);
1885 * Enable the receive queues.
1887 for (i = 0; i < 8; i++) {
1888 struct rx_queue *rxq = mp->rxq + i;
1889 int off = RXQ_CURRENT_DESC_PTR(mp->port_num, i);
1892 if ((mp->rxq_mask & (1 << i)) == 0)
1895 addr = (u32)rxq->rx_desc_dma;
1896 addr += rxq->rx_curr_desc * sizeof(struct rx_desc);
1903 static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int delay)
1905 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
1908 val = rdl(mp, SDMA_CONFIG(mp->port_num));
1909 if (mp->shared->extended_rx_coal_limit) {
1913 val |= (coal & 0x8000) << 10;
1914 val |= (coal & 0x7fff) << 7;
1919 val |= (coal & 0x3fff) << 8;
1921 wrl(mp, SDMA_CONFIG(mp->port_num), val);
1924 static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int delay)
1926 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
1930 wrl(mp, TX_FIFO_URGENT_THRESHOLD(mp->port_num), (coal & 0x3fff) << 4);
1933 static int mv643xx_eth_open(struct net_device *dev)
1935 struct mv643xx_eth_private *mp = netdev_priv(dev);
1939 wrl(mp, INT_CAUSE(mp->port_num), 0);
1940 wrl(mp, INT_CAUSE_EXT(mp->port_num), 0);
1941 rdl(mp, INT_CAUSE_EXT(mp->port_num));
1943 err = request_irq(dev->irq, mv643xx_eth_irq,
1944 IRQF_SHARED | IRQF_SAMPLE_RANDOM,
1947 dev_printk(KERN_ERR, &dev->dev, "can't assign irq\n");
1951 init_mac_tables(mp);
1953 for (i = 0; i < 8; i++) {
1954 if ((mp->rxq_mask & (1 << i)) == 0)
1957 err = rxq_init(mp, i);
1960 if (mp->rxq_mask & (1 << i))
1961 rxq_deinit(mp->rxq + i);
1965 rxq_refill(mp->rxq + i);
1968 for (i = 0; i < 8; i++) {
1969 if ((mp->txq_mask & (1 << i)) == 0)
1972 err = txq_init(mp, i);
1975 if (mp->txq_mask & (1 << i))
1976 txq_deinit(mp->txq + i);
1981 #ifdef MV643XX_ETH_NAPI
1982 napi_enable(&mp->napi);
1990 wrl(mp, INT_MASK_EXT(mp->port_num),
1991 INT_EXT_LINK | INT_EXT_PHY | INT_EXT_TX);
1993 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
1999 for (i = 0; i < 8; i++)
2000 if (mp->rxq_mask & (1 << i))
2001 rxq_deinit(mp->rxq + i);
2003 free_irq(dev->irq, dev);
2008 static void port_reset(struct mv643xx_eth_private *mp)
2013 for (i = 0; i < 8; i++) {
2014 if (mp->rxq_mask & (1 << i))
2015 rxq_disable(mp->rxq + i);
2016 if (mp->txq_mask & (1 << i))
2017 txq_disable(mp->txq + i);
2019 while (!(rdl(mp, PORT_STATUS(mp->port_num)) & TX_FIFO_EMPTY))
2022 /* Reset the Enable bit in the Configuration Register */
2023 data = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
2024 data &= ~(SERIAL_PORT_ENABLE |
2025 DO_NOT_FORCE_LINK_FAIL |
2027 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), data);
2030 static int mv643xx_eth_stop(struct net_device *dev)
2032 struct mv643xx_eth_private *mp = netdev_priv(dev);
2035 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
2036 rdl(mp, INT_MASK(mp->port_num));
2038 #ifdef MV643XX_ETH_NAPI
2039 napi_disable(&mp->napi);
2041 netif_carrier_off(dev);
2042 netif_stop_queue(dev);
2044 free_irq(dev->irq, dev);
2047 mib_counters_update(mp);
2049 for (i = 0; i < 8; i++) {
2050 if (mp->rxq_mask & (1 << i))
2051 rxq_deinit(mp->rxq + i);
2052 if (mp->txq_mask & (1 << i))
2053 txq_deinit(mp->txq + i);
2059 static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2061 struct mv643xx_eth_private *mp = netdev_priv(dev);
2063 if (mp->phy_addr != -1)
2064 return generic_mii_ioctl(&mp->mii, if_mii(ifr), cmd, NULL);
2069 static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
2071 struct mv643xx_eth_private *mp = netdev_priv(dev);
2073 if (new_mtu < 64 || new_mtu > 9500)
2077 tx_set_rate(mp, 1000000000, 16777216);
2079 if (!netif_running(dev))
2083 * Stop and then re-open the interface. This will allocate RX
2084 * skbs of the new MTU.
2085 * There is a possible danger that the open will not succeed,
2086 * due to memory being full.
2088 mv643xx_eth_stop(dev);
2089 if (mv643xx_eth_open(dev)) {
2090 dev_printk(KERN_ERR, &dev->dev,
2091 "fatal error on re-opening device after "
2098 static void tx_timeout_task(struct work_struct *ugly)
2100 struct mv643xx_eth_private *mp;
2102 mp = container_of(ugly, struct mv643xx_eth_private, tx_timeout_task);
2103 if (netif_running(mp->dev)) {
2104 netif_stop_queue(mp->dev);
2109 __txq_maybe_wake(mp->txq + mp->txq_primary);
2113 static void mv643xx_eth_tx_timeout(struct net_device *dev)
2115 struct mv643xx_eth_private *mp = netdev_priv(dev);
2117 dev_printk(KERN_INFO, &dev->dev, "tx timeout\n");
2119 schedule_work(&mp->tx_timeout_task);
2122 #ifdef CONFIG_NET_POLL_CONTROLLER
2123 static void mv643xx_eth_netpoll(struct net_device *dev)
2125 struct mv643xx_eth_private *mp = netdev_priv(dev);
2127 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
2128 rdl(mp, INT_MASK(mp->port_num));
2130 mv643xx_eth_irq(dev->irq, dev);
2132 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
2136 static int mv643xx_eth_mdio_read(struct net_device *dev, int addr, int reg)
2138 struct mv643xx_eth_private *mp = netdev_priv(dev);
2141 smi_reg_read(mp, addr, reg, &val);
2146 static void mv643xx_eth_mdio_write(struct net_device *dev, int addr, int reg, int val)
2148 struct mv643xx_eth_private *mp = netdev_priv(dev);
2149 smi_reg_write(mp, addr, reg, val);
2153 /* platform glue ************************************************************/
2155 mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp,
2156 struct mbus_dram_target_info *dram)
2158 void __iomem *base = msp->base;
2163 for (i = 0; i < 6; i++) {
2164 writel(0, base + WINDOW_BASE(i));
2165 writel(0, base + WINDOW_SIZE(i));
2167 writel(0, base + WINDOW_REMAP_HIGH(i));
2173 for (i = 0; i < dram->num_cs; i++) {
2174 struct mbus_dram_window *cs = dram->cs + i;
2176 writel((cs->base & 0xffff0000) |
2177 (cs->mbus_attr << 8) |
2178 dram->mbus_dram_target_id, base + WINDOW_BASE(i));
2179 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
2181 win_enable &= ~(1 << i);
2182 win_protect |= 3 << (2 * i);
2185 writel(win_enable, base + WINDOW_BAR_ENABLE);
2186 msp->win_protect = win_protect;
2189 static void infer_hw_params(struct mv643xx_eth_shared_private *msp)
2192 * Check whether we have a 14-bit coal limit field in bits
2193 * [21:8], or a 16-bit coal limit in bits [25,21:7] of the
2194 * SDMA config register.
2196 writel(0x02000000, msp->base + SDMA_CONFIG(0));
2197 if (readl(msp->base + SDMA_CONFIG(0)) & 0x02000000)
2198 msp->extended_rx_coal_limit = 1;
2200 msp->extended_rx_coal_limit = 0;
2203 * Check whether the TX rate control registers are in the
2204 * old or the new place.
2206 writel(1, msp->base + TX_BW_MTU_MOVED(0));
2207 if (readl(msp->base + TX_BW_MTU_MOVED(0)) & 1)
2208 msp->tx_bw_control_moved = 1;
2210 msp->tx_bw_control_moved = 0;
2213 static int mv643xx_eth_shared_probe(struct platform_device *pdev)
2215 static int mv643xx_eth_version_printed = 0;
2216 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
2217 struct mv643xx_eth_shared_private *msp;
2218 struct resource *res;
2221 if (!mv643xx_eth_version_printed++)
2222 printk(KERN_NOTICE "MV-643xx 10/100/1000 Ethernet Driver\n");
2225 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2230 msp = kmalloc(sizeof(*msp), GFP_KERNEL);
2233 memset(msp, 0, sizeof(*msp));
2235 msp->base = ioremap(res->start, res->end - res->start + 1);
2236 if (msp->base == NULL)
2239 spin_lock_init(&msp->phy_lock);
2242 * (Re-)program MBUS remapping windows if we are asked to.
2244 if (pd != NULL && pd->dram != NULL)
2245 mv643xx_eth_conf_mbus_windows(msp, pd->dram);
2248 * Detect hardware parameters.
2250 msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk : 133000000;
2251 infer_hw_params(msp);
2253 platform_set_drvdata(pdev, msp);
2263 static int mv643xx_eth_shared_remove(struct platform_device *pdev)
2265 struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev);
2273 static struct platform_driver mv643xx_eth_shared_driver = {
2274 .probe = mv643xx_eth_shared_probe,
2275 .remove = mv643xx_eth_shared_remove,
2277 .name = MV643XX_ETH_SHARED_NAME,
2278 .owner = THIS_MODULE,
2282 static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr)
2284 int addr_shift = 5 * mp->port_num;
2287 data = rdl(mp, PHY_ADDR);
2288 data &= ~(0x1f << addr_shift);
2289 data |= (phy_addr & 0x1f) << addr_shift;
2290 wrl(mp, PHY_ADDR, data);
2293 static int phy_addr_get(struct mv643xx_eth_private *mp)
2297 data = rdl(mp, PHY_ADDR);
2299 return (data >> (5 * mp->port_num)) & 0x1f;
2302 static void set_params(struct mv643xx_eth_private *mp,
2303 struct mv643xx_eth_platform_data *pd)
2305 struct net_device *dev = mp->dev;
2307 if (is_valid_ether_addr(pd->mac_addr))
2308 memcpy(dev->dev_addr, pd->mac_addr, 6);
2310 uc_addr_get(mp, dev->dev_addr);
2312 if (pd->phy_addr == -1) {
2313 mp->shared_smi = NULL;
2316 mp->shared_smi = mp->shared;
2317 if (pd->shared_smi != NULL)
2318 mp->shared_smi = platform_get_drvdata(pd->shared_smi);
2320 if (pd->force_phy_addr || pd->phy_addr) {
2321 mp->phy_addr = pd->phy_addr & 0x3f;
2322 phy_addr_set(mp, mp->phy_addr);
2324 mp->phy_addr = phy_addr_get(mp);
2328 mp->default_rx_ring_size = DEFAULT_RX_QUEUE_SIZE;
2329 if (pd->rx_queue_size)
2330 mp->default_rx_ring_size = pd->rx_queue_size;
2331 mp->rx_desc_sram_addr = pd->rx_sram_addr;
2332 mp->rx_desc_sram_size = pd->rx_sram_size;
2334 if (pd->rx_queue_mask)
2335 mp->rxq_mask = pd->rx_queue_mask;
2337 mp->rxq_mask = 0x01;
2338 mp->rxq_primary = fls(mp->rxq_mask) - 1;
2340 mp->default_tx_ring_size = DEFAULT_TX_QUEUE_SIZE;
2341 if (pd->tx_queue_size)
2342 mp->default_tx_ring_size = pd->tx_queue_size;
2343 mp->tx_desc_sram_addr = pd->tx_sram_addr;
2344 mp->tx_desc_sram_size = pd->tx_sram_size;
2346 if (pd->tx_queue_mask)
2347 mp->txq_mask = pd->tx_queue_mask;
2349 mp->txq_mask = 0x01;
2350 mp->txq_primary = fls(mp->txq_mask) - 1;
2353 static int phy_detect(struct mv643xx_eth_private *mp)
2358 smi_reg_read(mp, mp->phy_addr, 0, &data);
2359 smi_reg_write(mp, mp->phy_addr, 0, data ^ 0x1000);
2361 smi_reg_read(mp, mp->phy_addr, 0, &data2);
2362 if (((data ^ data2) & 0x1000) == 0)
2365 smi_reg_write(mp, mp->phy_addr, 0, data);
2370 static int phy_init(struct mv643xx_eth_private *mp,
2371 struct mv643xx_eth_platform_data *pd)
2373 struct ethtool_cmd cmd;
2376 err = phy_detect(mp);
2378 dev_printk(KERN_INFO, &mp->dev->dev,
2379 "no PHY detected at addr %d\n", mp->phy_addr);
2384 mp->mii.phy_id = mp->phy_addr;
2385 mp->mii.phy_id_mask = 0x3f;
2386 mp->mii.reg_num_mask = 0x1f;
2387 mp->mii.dev = mp->dev;
2388 mp->mii.mdio_read = mv643xx_eth_mdio_read;
2389 mp->mii.mdio_write = mv643xx_eth_mdio_write;
2391 mp->mii.supports_gmii = mii_check_gmii_support(&mp->mii);
2393 memset(&cmd, 0, sizeof(cmd));
2395 cmd.port = PORT_MII;
2396 cmd.transceiver = XCVR_INTERNAL;
2397 cmd.phy_address = mp->phy_addr;
2398 if (pd->speed == 0) {
2399 cmd.autoneg = AUTONEG_ENABLE;
2400 cmd.speed = SPEED_100;
2401 cmd.advertising = ADVERTISED_10baseT_Half |
2402 ADVERTISED_10baseT_Full |
2403 ADVERTISED_100baseT_Half |
2404 ADVERTISED_100baseT_Full;
2405 if (mp->mii.supports_gmii)
2406 cmd.advertising |= ADVERTISED_1000baseT_Full;
2408 cmd.autoneg = AUTONEG_DISABLE;
2409 cmd.speed = pd->speed;
2410 cmd.duplex = pd->duplex;
2413 update_pscr(mp, cmd.speed, cmd.duplex);
2414 mv643xx_eth_set_settings(mp->dev, &cmd);
2419 static int mv643xx_eth_probe(struct platform_device *pdev)
2421 struct mv643xx_eth_platform_data *pd;
2422 struct mv643xx_eth_private *mp;
2423 struct net_device *dev;
2424 struct resource *res;
2425 DECLARE_MAC_BUF(mac);
2428 pd = pdev->dev.platform_data;
2430 dev_printk(KERN_ERR, &pdev->dev,
2431 "no mv643xx_eth_platform_data\n");
2435 if (pd->shared == NULL) {
2436 dev_printk(KERN_ERR, &pdev->dev,
2437 "no mv643xx_eth_platform_data->shared\n");
2441 dev = alloc_etherdev(sizeof(struct mv643xx_eth_private));
2445 mp = netdev_priv(dev);
2446 platform_set_drvdata(pdev, mp);
2448 mp->shared = platform_get_drvdata(pd->shared);
2449 mp->port_num = pd->port_number;
2452 #ifdef MV643XX_ETH_NAPI
2453 netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, 64);
2458 spin_lock_init(&mp->lock);
2460 mib_counters_clear(mp);
2461 INIT_WORK(&mp->tx_timeout_task, tx_timeout_task);
2463 if (mp->phy_addr != -1) {
2464 err = phy_init(mp, pd);
2468 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops);
2470 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops_phyless);
2474 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2476 dev->irq = res->start;
2478 dev->hard_start_xmit = mv643xx_eth_xmit;
2479 dev->open = mv643xx_eth_open;
2480 dev->stop = mv643xx_eth_stop;
2481 dev->set_multicast_list = mv643xx_eth_set_rx_mode;
2482 dev->set_mac_address = mv643xx_eth_set_mac_address;
2483 dev->do_ioctl = mv643xx_eth_ioctl;
2484 dev->change_mtu = mv643xx_eth_change_mtu;
2485 dev->tx_timeout = mv643xx_eth_tx_timeout;
2486 #ifdef CONFIG_NET_POLL_CONTROLLER
2487 dev->poll_controller = mv643xx_eth_netpoll;
2489 dev->watchdog_timeo = 2 * HZ;
2492 #ifdef MV643XX_ETH_CHECKSUM_OFFLOAD_TX
2494 * Zero copy can only work if we use Discovery II memory. Else, we will
2495 * have to map the buffers to ISA memory which is only 16 MB
2497 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM;
2500 SET_NETDEV_DEV(dev, &pdev->dev);
2502 if (mp->shared->win_protect)
2503 wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect);
2505 err = register_netdev(dev);
2509 dev_printk(KERN_NOTICE, &dev->dev, "port %d with MAC address %s\n",
2510 mp->port_num, print_mac(mac, dev->dev_addr));
2512 if (dev->features & NETIF_F_SG)
2513 dev_printk(KERN_NOTICE, &dev->dev, "scatter/gather enabled\n");
2515 if (dev->features & NETIF_F_IP_CSUM)
2516 dev_printk(KERN_NOTICE, &dev->dev, "tx checksum offload\n");
2518 #ifdef MV643XX_ETH_NAPI
2519 dev_printk(KERN_NOTICE, &dev->dev, "napi enabled\n");
2522 if (mp->tx_desc_sram_size > 0)
2523 dev_printk(KERN_NOTICE, &dev->dev, "configured with sram\n");
2533 static int mv643xx_eth_remove(struct platform_device *pdev)
2535 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
2537 unregister_netdev(mp->dev);
2538 flush_scheduled_work();
2539 free_netdev(mp->dev);
2541 platform_set_drvdata(pdev, NULL);
2546 static void mv643xx_eth_shutdown(struct platform_device *pdev)
2548 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
2550 /* Mask all interrupts on ethernet port */
2551 wrl(mp, INT_MASK(mp->port_num), 0);
2552 rdl(mp, INT_MASK(mp->port_num));
2554 if (netif_running(mp->dev))
2558 static struct platform_driver mv643xx_eth_driver = {
2559 .probe = mv643xx_eth_probe,
2560 .remove = mv643xx_eth_remove,
2561 .shutdown = mv643xx_eth_shutdown,
2563 .name = MV643XX_ETH_NAME,
2564 .owner = THIS_MODULE,
2568 static int __init mv643xx_eth_init_module(void)
2572 rc = platform_driver_register(&mv643xx_eth_shared_driver);
2574 rc = platform_driver_register(&mv643xx_eth_driver);
2576 platform_driver_unregister(&mv643xx_eth_shared_driver);
2581 module_init(mv643xx_eth_init_module);
2583 static void __exit mv643xx_eth_cleanup_module(void)
2585 platform_driver_unregister(&mv643xx_eth_driver);
2586 platform_driver_unregister(&mv643xx_eth_shared_driver);
2588 module_exit(mv643xx_eth_cleanup_module);
2590 MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, "
2591 "Manish Lachwani, Dale Farnsworth and Lennert Buytenhek");
2592 MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
2593 MODULE_LICENSE("GPL");
2594 MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME);
2595 MODULE_ALIAS("platform:" MV643XX_ETH_NAME);