2 * Driver for Xilinx TEMAC Ethernet device
4 * Copyright (c) 2008 Nissin Systems Co., Ltd., Yoshio Kashiwagi
5 * Copyright (c) 2005-2008 DLA Systems, David H. Lynch Jr. <dhlii@dlasys.net>
6 * Copyright (c) 2008-2009 Secret Lab Technologies Ltd.
8 * This is a driver for the Xilinx ll_temac ipcore which is often used
9 * in the Virtex and Spartan series of chips.
12 * - The ll_temac hardware uses indirect access for many of the TEMAC
13 * registers, include the MDIO bus. However, indirect access to MDIO
14 * registers take considerably more clock cycles than to TEMAC registers.
15 * MDIO accesses are long, so threads doing them should probably sleep
16 * rather than busywait. However, since only one indirect access can be
17 * in progress at any given time, that means that *all* indirect accesses
18 * could end up sleeping (to wait for an MDIO access to complete).
19 * Fortunately none of the indirect accesses are on the 'hot' path for tx
20 * or rx, so this should be okay.
23 * - Factor out locallink DMA code into separate driver
24 * - Fix multicast assignment.
25 * - Fix support for hardware checksumming.
26 * - Testing. Lots and lots of testing.
30 #include <linux/delay.h>
31 #include <linux/etherdevice.h>
32 #include <linux/init.h>
33 #include <linux/mii.h>
34 #include <linux/module.h>
35 #include <linux/mutex.h>
36 #include <linux/netdevice.h>
38 #include <linux/of_device.h>
39 #include <linux/of_mdio.h>
40 #include <linux/of_platform.h>
41 #include <linux/skbuff.h>
42 #include <linux/spinlock.h>
43 #include <linux/tcp.h> /* needed for sizeof(tcphdr) */
44 #include <linux/udp.h> /* needed for sizeof(udphdr) */
45 #include <linux/phy.h>
55 /* ---------------------------------------------------------------------
56 * Low level register access functions
59 u32 temac_ior(struct temac_local *lp, int offset)
61 return in_be32((u32 *)(lp->regs + offset));
64 void temac_iow(struct temac_local *lp, int offset, u32 value)
66 out_be32((u32 *) (lp->regs + offset), value);
69 int temac_indirect_busywait(struct temac_local *lp)
71 long end = jiffies + 2;
73 while (!(temac_ior(lp, XTE_RDY0_OFFSET) & XTE_RDY0_HARD_ACS_RDY_MASK)) {
74 if (end - jiffies <= 0) {
86 * lp->indirect_mutex must be held when calling this function
88 u32 temac_indirect_in32(struct temac_local *lp, int reg)
92 if (temac_indirect_busywait(lp))
94 temac_iow(lp, XTE_CTL0_OFFSET, reg);
95 if (temac_indirect_busywait(lp))
97 val = temac_ior(lp, XTE_LSW0_OFFSET);
103 * temac_indirect_out32
105 * lp->indirect_mutex must be held when calling this function
107 void temac_indirect_out32(struct temac_local *lp, int reg, u32 value)
109 if (temac_indirect_busywait(lp))
111 temac_iow(lp, XTE_LSW0_OFFSET, value);
112 temac_iow(lp, XTE_CTL0_OFFSET, CNTLREG_WRITE_ENABLE_MASK | reg);
116 * temac_dma_in32 - Memory mapped DMA read, this function expects a
117 * register input that is based on DCR word addresses which
118 * are then converted to memory mapped byte addresses
120 static u32 temac_dma_in32(struct temac_local *lp, int reg)
122 return in_be32((u32 *)(lp->sdma_regs + (reg << 2)));
126 * temac_dma_out32 - Memory mapped DMA read, this function expects a
127 * register input that is based on DCR word addresses which
128 * are then converted to memory mapped byte addresses
130 static void temac_dma_out32(struct temac_local *lp, int reg, u32 value)
132 out_be32((u32 *)(lp->sdma_regs + (reg << 2)), value);
135 /* DMA register access functions can be DCR based or memory mapped.
136 * The PowerPC 440 is DCR based, the PowerPC 405 and MicroBlaze are both
139 #ifdef CONFIG_PPC_DCR
142 * temac_dma_dcr_in32 - DCR based DMA read
144 static u32 temac_dma_dcr_in(struct temac_local *lp, int reg)
146 return dcr_read(lp->sdma_dcrs, reg);
150 * temac_dma_dcr_out32 - DCR based DMA write
152 static void temac_dma_dcr_out(struct temac_local *lp, int reg, u32 value)
154 dcr_write(lp->sdma_dcrs, reg, value);
158 * temac_dcr_setup - If the DMA is DCR based, then setup the address and
161 static int temac_dcr_setup(struct temac_local *lp, struct of_device *op,
162 struct device_node *np)
166 /* setup the dcr address mapping if it's in the device tree */
168 dcrs = dcr_resource_start(np, 0);
170 lp->sdma_dcrs = dcr_map(np, dcrs, dcr_resource_len(np, 0));
171 lp->dma_in = temac_dma_dcr_in;
172 lp->dma_out = temac_dma_dcr_out;
173 dev_dbg(&op->dev, "DCR base: %x\n", dcrs);
176 /* no DCR in the device tree, indicate a failure */
183 * temac_dcr_setup - This is a stub for when DCR is not supported,
184 * such as with MicroBlaze
186 static int temac_dcr_setup(struct temac_local *lp, struct of_device *op,
187 struct device_node *np)
195 * temac_dma_bd_init - Setup buffer descriptor rings
197 static int temac_dma_bd_init(struct net_device *ndev)
199 struct temac_local *lp = netdev_priv(ndev);
203 lp->rx_skb = kzalloc(sizeof(*lp->rx_skb) * RX_BD_NUM, GFP_KERNEL);
204 /* allocate the tx and rx ring buffer descriptors. */
205 /* returns a virtual addres and a physical address. */
206 lp->tx_bd_v = dma_alloc_coherent(ndev->dev.parent,
207 sizeof(*lp->tx_bd_v) * TX_BD_NUM,
208 &lp->tx_bd_p, GFP_KERNEL);
209 lp->rx_bd_v = dma_alloc_coherent(ndev->dev.parent,
210 sizeof(*lp->rx_bd_v) * RX_BD_NUM,
211 &lp->rx_bd_p, GFP_KERNEL);
213 memset(lp->tx_bd_v, 0, sizeof(*lp->tx_bd_v) * TX_BD_NUM);
214 for (i = 0; i < TX_BD_NUM; i++) {
215 lp->tx_bd_v[i].next = lp->tx_bd_p +
216 sizeof(*lp->tx_bd_v) * ((i + 1) % TX_BD_NUM);
219 memset(lp->rx_bd_v, 0, sizeof(*lp->rx_bd_v) * RX_BD_NUM);
220 for (i = 0; i < RX_BD_NUM; i++) {
221 lp->rx_bd_v[i].next = lp->rx_bd_p +
222 sizeof(*lp->rx_bd_v) * ((i + 1) % RX_BD_NUM);
224 skb = netdev_alloc_skb_ip_align(ndev,
225 XTE_MAX_JUMBO_FRAME_SIZE);
228 dev_err(&ndev->dev, "alloc_skb error %d\n", i);
232 /* returns physical address of skb->data */
233 lp->rx_bd_v[i].phys = dma_map_single(ndev->dev.parent,
235 XTE_MAX_JUMBO_FRAME_SIZE,
237 lp->rx_bd_v[i].len = XTE_MAX_JUMBO_FRAME_SIZE;
238 lp->rx_bd_v[i].app0 = STS_CTRL_APP0_IRQONEND;
241 lp->dma_out(lp, TX_CHNL_CTRL, 0x10220400 |
243 CHNL_CTRL_IRQ_DLY_EN |
244 CHNL_CTRL_IRQ_COAL_EN);
247 lp->dma_out(lp, RX_CHNL_CTRL, 0xff010000 |
249 CHNL_CTRL_IRQ_DLY_EN |
250 CHNL_CTRL_IRQ_COAL_EN |
254 lp->dma_out(lp, RX_CURDESC_PTR, lp->rx_bd_p);
255 lp->dma_out(lp, RX_TAILDESC_PTR,
256 lp->rx_bd_p + (sizeof(*lp->rx_bd_v) * (RX_BD_NUM - 1)));
257 lp->dma_out(lp, TX_CURDESC_PTR, lp->tx_bd_p);
262 /* ---------------------------------------------------------------------
266 static int temac_set_mac_address(struct net_device *ndev, void *address)
268 struct temac_local *lp = netdev_priv(ndev);
271 memcpy(ndev->dev_addr, address, ETH_ALEN);
273 if (!is_valid_ether_addr(ndev->dev_addr))
274 random_ether_addr(ndev->dev_addr);
276 /* set up unicast MAC address filter set its mac address */
277 mutex_lock(&lp->indirect_mutex);
278 temac_indirect_out32(lp, XTE_UAW0_OFFSET,
279 (ndev->dev_addr[0]) |
280 (ndev->dev_addr[1] << 8) |
281 (ndev->dev_addr[2] << 16) |
282 (ndev->dev_addr[3] << 24));
283 /* There are reserved bits in EUAW1
284 * so don't affect them Set MAC bits [47:32] in EUAW1 */
285 temac_indirect_out32(lp, XTE_UAW1_OFFSET,
286 (ndev->dev_addr[4] & 0x000000ff) |
287 (ndev->dev_addr[5] << 8));
288 mutex_unlock(&lp->indirect_mutex);
293 static int netdev_set_mac_address(struct net_device *ndev, void *p)
295 struct sockaddr *addr = p;
297 return temac_set_mac_address(ndev, addr->sa_data);
300 static void temac_set_multicast_list(struct net_device *ndev)
302 struct temac_local *lp = netdev_priv(ndev);
303 u32 multi_addr_msw, multi_addr_lsw, val;
306 mutex_lock(&lp->indirect_mutex);
307 if (ndev->flags & (IFF_ALLMULTI | IFF_PROMISC) ||
308 netdev_mc_count(ndev) > MULTICAST_CAM_TABLE_NUM) {
310 * We must make the kernel realise we had to move
311 * into promisc mode or we start all out war on
312 * the cable. If it was a promisc request the
313 * flag is already set. If not we assert it.
315 ndev->flags |= IFF_PROMISC;
316 temac_indirect_out32(lp, XTE_AFM_OFFSET, XTE_AFM_EPPRM_MASK);
317 dev_info(&ndev->dev, "Promiscuous mode enabled.\n");
318 } else if (!netdev_mc_empty(ndev)) {
319 struct netdev_hw_addr *ha;
322 netdev_for_each_mc_addr(ha, ndev) {
323 if (i >= MULTICAST_CAM_TABLE_NUM)
325 multi_addr_msw = ((ha->addr[3] << 24) |
326 (ha->addr[2] << 16) |
329 temac_indirect_out32(lp, XTE_MAW0_OFFSET,
331 multi_addr_lsw = ((ha->addr[5] << 8) |
332 (ha->addr[4]) | (i << 16));
333 temac_indirect_out32(lp, XTE_MAW1_OFFSET,
338 val = temac_indirect_in32(lp, XTE_AFM_OFFSET);
339 temac_indirect_out32(lp, XTE_AFM_OFFSET,
340 val & ~XTE_AFM_EPPRM_MASK);
341 temac_indirect_out32(lp, XTE_MAW0_OFFSET, 0);
342 temac_indirect_out32(lp, XTE_MAW1_OFFSET, 0);
343 dev_info(&ndev->dev, "Promiscuous mode disabled.\n");
345 mutex_unlock(&lp->indirect_mutex);
348 struct temac_option {
354 } temac_options[] = {
355 /* Turn on jumbo packet support for both Rx and Tx */
357 .opt = XTE_OPTION_JUMBO,
358 .reg = XTE_TXC_OFFSET,
359 .m_or = XTE_TXC_TXJMBO_MASK,
362 .opt = XTE_OPTION_JUMBO,
363 .reg = XTE_RXC1_OFFSET,
364 .m_or =XTE_RXC1_RXJMBO_MASK,
366 /* Turn on VLAN packet support for both Rx and Tx */
368 .opt = XTE_OPTION_VLAN,
369 .reg = XTE_TXC_OFFSET,
370 .m_or =XTE_TXC_TXVLAN_MASK,
373 .opt = XTE_OPTION_VLAN,
374 .reg = XTE_RXC1_OFFSET,
375 .m_or =XTE_RXC1_RXVLAN_MASK,
377 /* Turn on FCS stripping on receive packets */
379 .opt = XTE_OPTION_FCS_STRIP,
380 .reg = XTE_RXC1_OFFSET,
381 .m_or =XTE_RXC1_RXFCS_MASK,
383 /* Turn on FCS insertion on transmit packets */
385 .opt = XTE_OPTION_FCS_INSERT,
386 .reg = XTE_TXC_OFFSET,
387 .m_or =XTE_TXC_TXFCS_MASK,
389 /* Turn on length/type field checking on receive packets */
391 .opt = XTE_OPTION_LENTYPE_ERR,
392 .reg = XTE_RXC1_OFFSET,
393 .m_or =XTE_RXC1_RXLT_MASK,
395 /* Turn on flow control */
397 .opt = XTE_OPTION_FLOW_CONTROL,
398 .reg = XTE_FCC_OFFSET,
399 .m_or =XTE_FCC_RXFLO_MASK,
401 /* Turn on flow control */
403 .opt = XTE_OPTION_FLOW_CONTROL,
404 .reg = XTE_FCC_OFFSET,
405 .m_or =XTE_FCC_TXFLO_MASK,
407 /* Turn on promiscuous frame filtering (all frames are received ) */
409 .opt = XTE_OPTION_PROMISC,
410 .reg = XTE_AFM_OFFSET,
411 .m_or =XTE_AFM_EPPRM_MASK,
413 /* Enable transmitter if not already enabled */
415 .opt = XTE_OPTION_TXEN,
416 .reg = XTE_TXC_OFFSET,
417 .m_or =XTE_TXC_TXEN_MASK,
419 /* Enable receiver? */
421 .opt = XTE_OPTION_RXEN,
422 .reg = XTE_RXC1_OFFSET,
423 .m_or =XTE_RXC1_RXEN_MASK,
431 static u32 temac_setoptions(struct net_device *ndev, u32 options)
433 struct temac_local *lp = netdev_priv(ndev);
434 struct temac_option *tp = &temac_options[0];
437 mutex_lock(&lp->indirect_mutex);
439 reg = temac_indirect_in32(lp, tp->reg) & ~tp->m_or;
440 if (options & tp->opt)
442 temac_indirect_out32(lp, tp->reg, reg);
445 lp->options |= options;
446 mutex_unlock(&lp->indirect_mutex);
451 /* Initilize temac */
452 static void temac_device_reset(struct net_device *ndev)
454 struct temac_local *lp = netdev_priv(ndev);
458 /* Perform a software reset */
460 /* 0x300 host enable bit ? */
461 /* reset PHY through control register ?:1 */
463 dev_dbg(&ndev->dev, "%s()\n", __func__);
465 mutex_lock(&lp->indirect_mutex);
466 /* Reset the receiver and wait for it to finish reset */
467 temac_indirect_out32(lp, XTE_RXC1_OFFSET, XTE_RXC1_RXRST_MASK);
469 while (temac_indirect_in32(lp, XTE_RXC1_OFFSET) & XTE_RXC1_RXRST_MASK) {
471 if (--timeout == 0) {
473 "temac_device_reset RX reset timeout!!\n");
478 /* Reset the transmitter and wait for it to finish reset */
479 temac_indirect_out32(lp, XTE_TXC_OFFSET, XTE_TXC_TXRST_MASK);
481 while (temac_indirect_in32(lp, XTE_TXC_OFFSET) & XTE_TXC_TXRST_MASK) {
483 if (--timeout == 0) {
485 "temac_device_reset TX reset timeout!!\n");
490 /* Disable the receiver */
491 val = temac_indirect_in32(lp, XTE_RXC1_OFFSET);
492 temac_indirect_out32(lp, XTE_RXC1_OFFSET, val & ~XTE_RXC1_RXEN_MASK);
494 /* Reset Local Link (DMA) */
495 lp->dma_out(lp, DMA_CONTROL_REG, DMA_CONTROL_RST);
497 while (lp->dma_in(lp, DMA_CONTROL_REG) & DMA_CONTROL_RST) {
499 if (--timeout == 0) {
501 "temac_device_reset DMA reset timeout!!\n");
505 lp->dma_out(lp, DMA_CONTROL_REG, DMA_TAIL_ENABLE);
507 temac_dma_bd_init(ndev);
509 temac_indirect_out32(lp, XTE_RXC0_OFFSET, 0);
510 temac_indirect_out32(lp, XTE_RXC1_OFFSET, 0);
511 temac_indirect_out32(lp, XTE_TXC_OFFSET, 0);
512 temac_indirect_out32(lp, XTE_FCC_OFFSET, XTE_FCC_RXFLO_MASK);
514 mutex_unlock(&lp->indirect_mutex);
516 /* Sync default options with HW
517 * but leave receiver and transmitter disabled. */
518 temac_setoptions(ndev,
519 lp->options & ~(XTE_OPTION_TXEN | XTE_OPTION_RXEN));
521 temac_set_mac_address(ndev, NULL);
523 /* Set address filter table */
524 temac_set_multicast_list(ndev);
525 if (temac_setoptions(ndev, lp->options))
526 dev_err(&ndev->dev, "Error setting TEMAC options\n");
528 /* Init Driver variable */
529 ndev->trans_start = 0;
532 void temac_adjust_link(struct net_device *ndev)
534 struct temac_local *lp = netdev_priv(ndev);
535 struct phy_device *phy = lp->phy_dev;
539 /* hash together the state values to decide if something has changed */
540 link_state = phy->speed | (phy->duplex << 1) | phy->link;
542 mutex_lock(&lp->indirect_mutex);
543 if (lp->last_link != link_state) {
544 mii_speed = temac_indirect_in32(lp, XTE_EMCFG_OFFSET);
545 mii_speed &= ~XTE_EMCFG_LINKSPD_MASK;
547 switch (phy->speed) {
548 case SPEED_1000: mii_speed |= XTE_EMCFG_LINKSPD_1000; break;
549 case SPEED_100: mii_speed |= XTE_EMCFG_LINKSPD_100; break;
550 case SPEED_10: mii_speed |= XTE_EMCFG_LINKSPD_10; break;
553 /* Write new speed setting out to TEMAC */
554 temac_indirect_out32(lp, XTE_EMCFG_OFFSET, mii_speed);
555 lp->last_link = link_state;
556 phy_print_status(phy);
558 mutex_unlock(&lp->indirect_mutex);
561 static void temac_start_xmit_done(struct net_device *ndev)
563 struct temac_local *lp = netdev_priv(ndev);
564 struct cdmac_bd *cur_p;
565 unsigned int stat = 0;
567 cur_p = &lp->tx_bd_v[lp->tx_bd_ci];
570 while (stat & STS_CTRL_APP0_CMPLT) {
571 dma_unmap_single(ndev->dev.parent, cur_p->phys, cur_p->len,
574 dev_kfree_skb_irq((struct sk_buff *)cur_p->app4);
577 ndev->stats.tx_packets++;
578 ndev->stats.tx_bytes += cur_p->len;
581 if (lp->tx_bd_ci >= TX_BD_NUM)
584 cur_p = &lp->tx_bd_v[lp->tx_bd_ci];
588 netif_wake_queue(ndev);
591 static int temac_start_xmit(struct sk_buff *skb, struct net_device *ndev)
593 struct temac_local *lp = netdev_priv(ndev);
594 struct cdmac_bd *cur_p;
595 dma_addr_t start_p, tail_p;
597 unsigned long num_frag;
600 num_frag = skb_shinfo(skb)->nr_frags;
601 frag = &skb_shinfo(skb)->frags[0];
602 start_p = lp->tx_bd_p + sizeof(*lp->tx_bd_v) * lp->tx_bd_tail;
603 cur_p = &lp->tx_bd_v[lp->tx_bd_tail];
605 if (cur_p->app0 & STS_CTRL_APP0_CMPLT) {
606 if (!netif_queue_stopped(ndev)) {
607 netif_stop_queue(ndev);
608 return NETDEV_TX_BUSY;
610 return NETDEV_TX_BUSY;
614 if (skb->ip_summed == CHECKSUM_PARTIAL) {
615 const struct iphdr *ip = ip_hdr(skb);
616 int length = 0, start = 0, insert = 0;
618 switch (ip->protocol) {
620 start = sizeof(struct iphdr) + ETH_HLEN;
621 insert = sizeof(struct iphdr) + ETH_HLEN + 16;
622 length = ip->tot_len - sizeof(struct iphdr);
625 start = sizeof(struct iphdr) + ETH_HLEN;
626 insert = sizeof(struct iphdr) + ETH_HLEN + 6;
627 length = ip->tot_len - sizeof(struct iphdr);
632 cur_p->app1 = ((start << 16) | insert);
633 cur_p->app2 = csum_tcpudp_magic(ip->saddr, ip->daddr,
634 length, ip->protocol, 0);
635 skb->data[insert] = 0;
636 skb->data[insert + 1] = 0;
638 cur_p->app0 |= STS_CTRL_APP0_SOP;
639 cur_p->len = skb_headlen(skb);
640 cur_p->phys = dma_map_single(ndev->dev.parent, skb->data, skb->len,
642 cur_p->app4 = (unsigned long)skb;
644 for (ii = 0; ii < num_frag; ii++) {
646 if (lp->tx_bd_tail >= TX_BD_NUM)
649 cur_p = &lp->tx_bd_v[lp->tx_bd_tail];
650 cur_p->phys = dma_map_single(ndev->dev.parent,
651 (void *)page_address(frag->page) +
653 frag->size, DMA_TO_DEVICE);
654 cur_p->len = frag->size;
658 cur_p->app0 |= STS_CTRL_APP0_EOP;
660 tail_p = lp->tx_bd_p + sizeof(*lp->tx_bd_v) * lp->tx_bd_tail;
662 if (lp->tx_bd_tail >= TX_BD_NUM)
665 /* Kick off the transfer */
666 lp->dma_out(lp, TX_TAILDESC_PTR, tail_p); /* DMA start */
672 static void ll_temac_recv(struct net_device *ndev)
674 struct temac_local *lp = netdev_priv(ndev);
675 struct sk_buff *skb, *new_skb;
677 struct cdmac_bd *cur_p;
680 unsigned long skb_vaddr;
683 spin_lock_irqsave(&lp->rx_lock, flags);
685 tail_p = lp->rx_bd_p + sizeof(*lp->rx_bd_v) * lp->rx_bd_ci;
686 cur_p = &lp->rx_bd_v[lp->rx_bd_ci];
688 bdstat = cur_p->app0;
689 while ((bdstat & STS_CTRL_APP0_CMPLT)) {
691 skb = lp->rx_skb[lp->rx_bd_ci];
692 length = cur_p->app4 & 0x3FFF;
694 skb_vaddr = virt_to_bus(skb->data);
695 dma_unmap_single(ndev->dev.parent, skb_vaddr, length,
698 skb_put(skb, length);
700 skb->protocol = eth_type_trans(skb, ndev);
701 skb->ip_summed = CHECKSUM_NONE;
705 ndev->stats.rx_packets++;
706 ndev->stats.rx_bytes += length;
708 new_skb = netdev_alloc_skb_ip_align(ndev,
709 XTE_MAX_JUMBO_FRAME_SIZE);
712 dev_err(&ndev->dev, "no memory for new sk_buff\n");
713 spin_unlock_irqrestore(&lp->rx_lock, flags);
717 cur_p->app0 = STS_CTRL_APP0_IRQONEND;
718 cur_p->phys = dma_map_single(ndev->dev.parent, new_skb->data,
719 XTE_MAX_JUMBO_FRAME_SIZE,
721 cur_p->len = XTE_MAX_JUMBO_FRAME_SIZE;
722 lp->rx_skb[lp->rx_bd_ci] = new_skb;
725 if (lp->rx_bd_ci >= RX_BD_NUM)
728 cur_p = &lp->rx_bd_v[lp->rx_bd_ci];
729 bdstat = cur_p->app0;
731 lp->dma_out(lp, RX_TAILDESC_PTR, tail_p);
733 spin_unlock_irqrestore(&lp->rx_lock, flags);
736 static irqreturn_t ll_temac_tx_irq(int irq, void *_ndev)
738 struct net_device *ndev = _ndev;
739 struct temac_local *lp = netdev_priv(ndev);
742 status = lp->dma_in(lp, TX_IRQ_REG);
743 lp->dma_out(lp, TX_IRQ_REG, status);
745 if (status & (IRQ_COAL | IRQ_DLY))
746 temac_start_xmit_done(lp->ndev);
748 dev_err(&ndev->dev, "DMA error 0x%x\n", status);
753 static irqreturn_t ll_temac_rx_irq(int irq, void *_ndev)
755 struct net_device *ndev = _ndev;
756 struct temac_local *lp = netdev_priv(ndev);
759 /* Read and clear the status registers */
760 status = lp->dma_in(lp, RX_IRQ_REG);
761 lp->dma_out(lp, RX_IRQ_REG, status);
763 if (status & (IRQ_COAL | IRQ_DLY))
764 ll_temac_recv(lp->ndev);
769 static int temac_open(struct net_device *ndev)
771 struct temac_local *lp = netdev_priv(ndev);
774 dev_dbg(&ndev->dev, "temac_open()\n");
777 lp->phy_dev = of_phy_connect(lp->ndev, lp->phy_node,
778 temac_adjust_link, 0, 0);
780 dev_err(lp->dev, "of_phy_connect() failed\n");
784 phy_start(lp->phy_dev);
787 rc = request_irq(lp->tx_irq, ll_temac_tx_irq, 0, ndev->name, ndev);
790 rc = request_irq(lp->rx_irq, ll_temac_rx_irq, 0, ndev->name, ndev);
794 temac_device_reset(ndev);
798 free_irq(lp->tx_irq, ndev);
801 phy_disconnect(lp->phy_dev);
803 dev_err(lp->dev, "request_irq() failed\n");
807 static int temac_stop(struct net_device *ndev)
809 struct temac_local *lp = netdev_priv(ndev);
811 dev_dbg(&ndev->dev, "temac_close()\n");
813 free_irq(lp->tx_irq, ndev);
814 free_irq(lp->rx_irq, ndev);
817 phy_disconnect(lp->phy_dev);
823 #ifdef CONFIG_NET_POLL_CONTROLLER
825 temac_poll_controller(struct net_device *ndev)
827 struct temac_local *lp = netdev_priv(ndev);
829 disable_irq(lp->tx_irq);
830 disable_irq(lp->rx_irq);
832 ll_temac_rx_irq(lp->tx_irq, lp);
833 ll_temac_tx_irq(lp->rx_irq, lp);
835 enable_irq(lp->tx_irq);
836 enable_irq(lp->rx_irq);
840 static const struct net_device_ops temac_netdev_ops = {
841 .ndo_open = temac_open,
842 .ndo_stop = temac_stop,
843 .ndo_start_xmit = temac_start_xmit,
844 .ndo_set_mac_address = netdev_set_mac_address,
845 //.ndo_set_multicast_list = temac_set_multicast_list,
846 #ifdef CONFIG_NET_POLL_CONTROLLER
847 .ndo_poll_controller = temac_poll_controller,
851 /* ---------------------------------------------------------------------
852 * SYSFS device attributes
854 static ssize_t temac_show_llink_regs(struct device *dev,
855 struct device_attribute *attr, char *buf)
857 struct net_device *ndev = dev_get_drvdata(dev);
858 struct temac_local *lp = netdev_priv(ndev);
861 for (i = 0; i < 0x11; i++)
862 len += sprintf(buf + len, "%.8x%s", lp->dma_in(lp, i),
863 (i % 8) == 7 ? "\n" : " ");
864 len += sprintf(buf + len, "\n");
869 static DEVICE_ATTR(llink_regs, 0440, temac_show_llink_regs, NULL);
871 static struct attribute *temac_device_attrs[] = {
872 &dev_attr_llink_regs.attr,
876 static const struct attribute_group temac_attr_group = {
877 .attrs = temac_device_attrs,
881 temac_of_probe(struct of_device *op, const struct of_device_id *match)
883 struct device_node *np;
884 struct temac_local *lp;
885 struct net_device *ndev;
889 /* Init network device structure */
890 ndev = alloc_etherdev(sizeof(*lp));
892 dev_err(&op->dev, "could not allocate device.\n");
896 dev_set_drvdata(&op->dev, ndev);
897 SET_NETDEV_DEV(ndev, &op->dev);
898 ndev->flags &= ~IFF_MULTICAST; /* clear multicast */
899 ndev->features = NETIF_F_SG | NETIF_F_FRAGLIST;
900 ndev->netdev_ops = &temac_netdev_ops;
902 ndev->features |= NETIF_F_IP_CSUM; /* Can checksum TCP/UDP over IPv4. */
903 ndev->features |= NETIF_F_HW_CSUM; /* Can checksum all the packets. */
904 ndev->features |= NETIF_F_IPV6_CSUM; /* Can checksum IPV6 TCP/UDP */
905 ndev->features |= NETIF_F_HIGHDMA; /* Can DMA to high memory. */
906 ndev->features |= NETIF_F_HW_VLAN_TX; /* Transmit VLAN hw accel */
907 ndev->features |= NETIF_F_HW_VLAN_RX; /* Receive VLAN hw acceleration */
908 ndev->features |= NETIF_F_HW_VLAN_FILTER; /* Receive VLAN filtering */
909 ndev->features |= NETIF_F_VLAN_CHALLENGED; /* cannot handle VLAN pkts */
910 ndev->features |= NETIF_F_GSO; /* Enable software GSO. */
911 ndev->features |= NETIF_F_MULTI_QUEUE; /* Has multiple TX/RX queues */
912 ndev->features |= NETIF_F_LRO; /* large receive offload */
915 /* setup temac private info structure */
916 lp = netdev_priv(ndev);
919 lp->options = XTE_OPTION_DEFAULTS;
920 spin_lock_init(&lp->rx_lock);
921 mutex_init(&lp->indirect_mutex);
923 /* map device registers */
924 lp->regs = of_iomap(op->node, 0);
926 dev_err(&op->dev, "could not map temac regs.\n");
930 /* Find the DMA node, map the DMA registers, and decode the DMA IRQs */
931 np = of_parse_phandle(op->node, "llink-connected", 0);
933 dev_err(&op->dev, "could not find DMA node\n");
937 /* Setup the DMA register accesses, could be DCR or memory mapped */
938 if (temac_dcr_setup(lp, op, np)) {
940 /* no DCR in the device tree, try non-DCR */
941 lp->sdma_regs = of_iomap(np, 0);
943 lp->dma_in = temac_dma_in32;
944 lp->dma_out = temac_dma_out32;
945 dev_dbg(&op->dev, "MEM base: %p\n", lp->sdma_regs);
947 dev_err(&op->dev, "unable to map DMA registers\n");
952 lp->rx_irq = irq_of_parse_and_map(np, 0);
953 lp->tx_irq = irq_of_parse_and_map(np, 1);
954 if (!lp->rx_irq || !lp->tx_irq) {
955 dev_err(&op->dev, "could not determine irqs\n");
960 of_node_put(np); /* Finished with the DMA node; drop the reference */
962 /* Retrieve the MAC address */
963 addr = of_get_property(op->node, "local-mac-address", &size);
964 if ((!addr) || (size != 6)) {
965 dev_err(&op->dev, "could not find MAC address\n");
969 temac_set_mac_address(ndev, (void *)addr);
971 rc = temac_mdio_setup(lp, op->node);
973 dev_warn(&op->dev, "error registering MDIO bus\n");
975 lp->phy_node = of_parse_phandle(op->node, "phy-handle", 0);
977 dev_dbg(lp->dev, "using PHY node %s (%p)\n", np->full_name, np);
979 /* Add the device attributes */
980 rc = sysfs_create_group(&lp->dev->kobj, &temac_attr_group);
982 dev_err(lp->dev, "Error creating sysfs files\n");
986 rc = register_netdev(lp->ndev);
988 dev_err(lp->dev, "register_netdev() error (%i)\n", rc);
989 goto err_register_ndev;
995 sysfs_remove_group(&lp->dev->kobj, &temac_attr_group);
1002 static int __devexit temac_of_remove(struct of_device *op)
1004 struct net_device *ndev = dev_get_drvdata(&op->dev);
1005 struct temac_local *lp = netdev_priv(ndev);
1007 temac_mdio_teardown(lp);
1008 unregister_netdev(ndev);
1009 sysfs_remove_group(&lp->dev->kobj, &temac_attr_group);
1011 of_node_put(lp->phy_node);
1012 lp->phy_node = NULL;
1013 dev_set_drvdata(&op->dev, NULL);
1018 static struct of_device_id temac_of_match[] __devinitdata = {
1019 { .compatible = "xlnx,xps-ll-temac-1.01.b", },
1020 { .compatible = "xlnx,xps-ll-temac-2.00.a", },
1021 { .compatible = "xlnx,xps-ll-temac-2.02.a", },
1022 { .compatible = "xlnx,xps-ll-temac-2.03.a", },
1025 MODULE_DEVICE_TABLE(of, temac_of_match);
1027 static struct of_platform_driver temac_of_driver = {
1028 .match_table = temac_of_match,
1029 .probe = temac_of_probe,
1030 .remove = __devexit_p(temac_of_remove),
1032 .owner = THIS_MODULE,
1033 .name = "xilinx_temac",
1037 static int __init temac_init(void)
1039 return of_register_platform_driver(&temac_of_driver);
1041 module_init(temac_init);
1043 static void __exit temac_exit(void)
1045 of_unregister_platform_driver(&temac_of_driver);
1047 module_exit(temac_exit);
1049 MODULE_DESCRIPTION("Xilinx LL_TEMAC Ethernet driver");
1050 MODULE_AUTHOR("Yoshio Kashiwagi");
1051 MODULE_LICENSE("GPL");