SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/net/ixgbe/ixgbe_main.c

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2009 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #include <linux/types.h>
  29 #include <linux/module.h>
  30 #include <linux/pci.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/vmalloc.h>
  33 #include <linux/string.h>
  34 #include <linux/in.h>
  35 #include <linux/ip.h>
  36 #include <linux/tcp.h>
  37 #include <linux/pkt_sched.h>
  38 #include <linux/ipv6.h>
  39 #include <net/checksum.h>
  40 #include <net/ip6_checksum.h>
  41 #include <linux/ethtool.h>
  42 #include <linux/if_vlan.h>
  43 #include <scsi/fc/fc_fcoe.h>
  44
  45 #include "ixgbe.h"
  46 #include "ixgbe_common.h"
  47 #include "ixgbe_dcb_82599.h"
  48
  49 char ixgbe_driver_name[] = "ixgbe";
  50 static const char ixgbe_driver_string[] =
  51                               "Intel(R) 10 Gigabit PCI Express Network Driver";
  52
  53 #define DRV_VERSION "2.0.44-k2"
  54 const char ixgbe_driver_version[] = DRV_VERSION;
  55 static char ixgbe_copyright[] = "Copyright (c) 1999-2009 Intel Corporation.";
  56
  57 static const struct ixgbe_info *ixgbe_info_tbl[] = {
  58         [board_82598] = &ixgbe_82598_info,
  59         [board_82599] = &ixgbe_82599_info,
  60 };
  61
  62 /* ixgbe_pci_tbl - PCI Device ID Table
  63  *
  64  * Wildcard entries (PCI_ANY_ID) should come last
  65  * Last entry must be all 0s
  66  *
  67  * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
  68  *   Class, Class Mask, private data (not used) }
  69  */
  70 static struct pci_device_id ixgbe_pci_tbl[] = {
  71         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
  72          board_82598 },
  73         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
  74          board_82598 },
  75         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
  76          board_82598 },
  77         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
  78          board_82598 },
  79         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
  80          board_82598 },
  81         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
  82          board_82598 },
  83         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
  84          board_82598 },
  85         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
  86          board_82598 },
  87         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
  88          board_82598 },
  89         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
  90          board_82598 },
  91         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
  92          board_82598 },
  93         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
  94          board_82598 },
  95         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
  96          board_82599 },
  97         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
  98          board_82599 },
  99         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
 100          board_82599 },
 101         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM),
 102          board_82599 },
 103         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ),
 104          board_82599 },
 105         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
 106          board_82599 },
 107         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE),
 108          board_82599 },
 109
 110         /* required last entry */
 111         {0, }
 112 };
 113 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
 114
 115 #ifdef CONFIG_IXGBE_DCA
 116 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
 117                             void *p);
 118 static struct notifier_block dca_notifier = {
 119         .notifier_call = ixgbe_notify_dca,
 120         .next          = NULL,
 121         .priority      = 0
 122 };
 123 #endif
 124
 125 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
 126 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
 127 MODULE_LICENSE("GPL");
 128 MODULE_VERSION(DRV_VERSION);
 129
 130 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
 131
 132 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
 133 {
 134         u32 ctrl_ext;
 135
 136         /* Let firmware take over control of h/w */
 137         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 138         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 139                         ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
 140 }
 141
 142 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
 143 {
 144         u32 ctrl_ext;
 145
 146         /* Let firmware know the driver has taken over */
 147         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 148         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 149                         ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
 150 }
 151
 152 /*
 153  * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
 154  * @adapter: pointer to adapter struct
 155  * @direction: 0 for Rx, 1 for Tx, -1 for other causes
 156  * @queue: queue to map the corresponding interrupt to
 157  * @msix_vector: the vector to map to the corresponding queue
 158  *
 159  */
 160 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
 161                            u8 queue, u8 msix_vector)
 162 {
 163         u32 ivar, index;
 164         struct ixgbe_hw *hw = &adapter->hw;
 165         switch (hw->mac.type) {
 166         case ixgbe_mac_82598EB:
 167                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 168                 if (direction == -1)
 169                         direction = 0;
 170                 index = (((direction * 64) + queue) >> 2) & 0x1F;
 171                 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
 172                 ivar &= ~(0xFF << (8 * (queue & 0x3)));
 173                 ivar |= (msix_vector << (8 * (queue & 0x3)));
 174                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
 175                 break;
 176         case ixgbe_mac_82599EB:
 177                 if (direction == -1) {
 178                         /* other causes */
 179                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 180                         index = ((queue & 1) * 8);
 181                         ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
 182                         ivar &= ~(0xFF << index);
 183                         ivar |= (msix_vector << index);
 184                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
 185                         break;
 186                 } else {
 187                         /* tx or rx causes */
 188                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 189                         index = ((16 * (queue & 1)) + (8 * direction));
 190                         ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
 191                         ivar &= ~(0xFF << index);
 192                         ivar |= (msix_vector << index);
 193                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
 194                         break;
 195                 }
 196         default:
 197                 break;
 198         }
 199 }
 200
 201 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
 202                                           u64 qmask)
 203 {
 204         u32 mask;
 205
 206         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 207                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
 208                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
 209         } else {
 210                 mask = (qmask & 0xFFFFFFFF);
 211                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
 212                 mask = (qmask >> 32);
 213                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
 214         }
 215 }
 216
 217 static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
 218                                              struct ixgbe_tx_buffer
 219                                              *tx_buffer_info)
 220 {
 221         tx_buffer_info->dma = 0;
 222         if (tx_buffer_info->skb) {
 223                 skb_dma_unmap(&adapter->pdev->dev, tx_buffer_info->skb,
 224                               DMA_TO_DEVICE);
 225                 dev_kfree_skb_any(tx_buffer_info->skb);
 226                 tx_buffer_info->skb = NULL;
 227         }
 228         tx_buffer_info->time_stamp = 0;
 229         /* tx_buffer_info must be completely set up in the transmit path */
 230 }
 231
 232 /**
 233  * ixgbe_tx_is_paused - check if the tx ring is paused
 234  * @adapter: the ixgbe adapter
 235  * @tx_ring: the corresponding tx_ring
 236  *
 237  * If not in DCB mode, checks TFCS.TXOFF, otherwise, find out the
 238  * corresponding TC of this tx_ring when checking TFCS.
 239  *
 240  * Returns : true if paused
 241  */
 242 static inline bool ixgbe_tx_is_paused(struct ixgbe_adapter *adapter,
 243                                       struct ixgbe_ring *tx_ring)
 244 {
 245         int tc;
 246         u32 txoff = IXGBE_TFCS_TXOFF;
 247
 248 #ifdef CONFIG_IXGBE_DCB
 249         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
 250                 int reg_idx = tx_ring->reg_idx;
 251                 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
 252
 253                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 254                         tc = reg_idx >> 2;
 255                         txoff = IXGBE_TFCS_TXOFF0;
 256                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
 257                         tc = 0;
 258                         txoff = IXGBE_TFCS_TXOFF;
 259                         if (dcb_i == 8) {
 260                                 /* TC0, TC1 */
 261                                 tc = reg_idx >> 5;
 262                                 if (tc == 2) /* TC2, TC3 */
 263                                         tc += (reg_idx - 64) >> 4;
 264                                 else if (tc == 3) /* TC4, TC5, TC6, TC7 */
 265                                         tc += 1 + ((reg_idx - 96) >> 3);
 266                         } else if (dcb_i == 4) {
 267                                 /* TC0, TC1 */
 268                                 tc = reg_idx >> 6;
 269                                 if (tc == 1) {
 270                                         tc += (reg_idx - 64) >> 5;
 271                                         if (tc == 2) /* TC2, TC3 */
 272                                                 tc += (reg_idx - 96) >> 4;
 273                                 }
 274                         }
 275                 }
 276                 txoff <<= tc;
 277         }
 278 #endif
 279         return IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & txoff;
 280 }
 281
 282 static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
 283                                        struct ixgbe_ring *tx_ring,
 284                                        unsigned int eop)
 285 {
 286         struct ixgbe_hw *hw = &adapter->hw;
 287
 288         /* Detect a transmit hang in hardware, this serializes the
 289          * check with the clearing of time_stamp and movement of eop */
 290         adapter->detect_tx_hung = false;
 291         if (tx_ring->tx_buffer_info[eop].time_stamp &&
 292             time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
 293             !ixgbe_tx_is_paused(adapter, tx_ring)) {
 294                 /* detected Tx unit hang */
 295                 union ixgbe_adv_tx_desc *tx_desc;
 296                 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
 297                 DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
 298                         "  Tx Queue             <%d>\n"
 299                         "  TDH, TDT             <%x>, <%x>\n"
 300                         "  next_to_use          <%x>\n"
 301                         "  next_to_clean        <%x>\n"
 302                         "tx_buffer_info[next_to_clean]\n"
 303                         "  time_stamp           <%lx>\n"
 304                         "  jiffies              <%lx>\n",
 305                         tx_ring->queue_index,
 306                         IXGBE_READ_REG(hw, tx_ring->head),
 307                         IXGBE_READ_REG(hw, tx_ring->tail),
 308                         tx_ring->next_to_use, eop,
 309                         tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
 310                 return true;
 311         }
 312
 313         return false;
 314 }
 315
 316 #define IXGBE_MAX_TXD_PWR       14
 317 #define IXGBE_MAX_DATA_PER_TXD  (1 << IXGBE_MAX_TXD_PWR)
 318
 319 /* Tx Descriptors needed, worst case */
 320 #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
 321                          (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
 322 #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
 323         MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
 324
 325 static void ixgbe_tx_timeout(struct net_device *netdev);
 326
 327 /**
 328  * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
 329  * @q_vector: structure containing interrupt and ring information
 330  * @tx_ring: tx ring to clean
 331  **/
 332 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
 333                                struct ixgbe_ring *tx_ring)
 334 {
 335         struct ixgbe_adapter *adapter = q_vector->adapter;
 336         struct net_device *netdev = adapter->netdev;
 337         union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
 338         struct ixgbe_tx_buffer *tx_buffer_info;
 339         unsigned int i, eop, count = 0;
 340         unsigned int total_bytes = 0, total_packets = 0;
 341
 342         i = tx_ring->next_to_clean;
 343         eop = tx_ring->tx_buffer_info[i].next_to_watch;
 344         eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
 345
 346         while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
 347                (count < tx_ring->work_limit)) {
 348                 bool cleaned = false;
 349                 for ( ; !cleaned; count++) {
 350                         struct sk_buff *skb;
 351                         tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
 352                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
 353                         cleaned = (i == eop);
 354                         skb = tx_buffer_info->skb;
 355
 356                         if (cleaned && skb) {
 357                                 unsigned int segs, bytecount;
 358                                 unsigned int hlen = skb_headlen(skb);
 359
 360                                 /* gso_segs is currently only valid for tcp */
 361                                 segs = skb_shinfo(skb)->gso_segs ?: 1;
 362 #ifdef IXGBE_FCOE
 363                                 /* adjust for FCoE Sequence Offload */
 364                                 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
 365                                     && (skb->protocol == htons(ETH_P_FCOE)) &&
 366                                     skb_is_gso(skb)) {
 367                                         hlen = skb_transport_offset(skb) +
 368                                                 sizeof(struct fc_frame_header) +
 369                                                 sizeof(struct fcoe_crc_eof);
 370                                         segs = DIV_ROUND_UP(skb->len - hlen,
 371                                                 skb_shinfo(skb)->gso_size);
 372                                 }
 373 #endif /* IXGBE_FCOE */
 374                                 /* multiply data chunks by size of headers */
 375                                 bytecount = ((segs - 1) * hlen) + skb->len;
 376                                 total_packets += segs;
 377                                 total_bytes += bytecount;
 378                         }
 379
 380                         ixgbe_unmap_and_free_tx_resource(adapter,
 381                                                          tx_buffer_info);
 382
 383                         tx_desc->wb.status = 0;
 384
 385                         i++;
 386                         if (i == tx_ring->count)
 387                                 i = 0;
 388                 }
 389
 390                 eop = tx_ring->tx_buffer_info[i].next_to_watch;
 391                 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
 392         }
 393
 394         tx_ring->next_to_clean = i;
 395
 396 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
 397         if (unlikely(count && netif_carrier_ok(netdev) &&
 398                      (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
 399                 /* Make sure that anybody stopping the queue after this
 400                  * sees the new next_to_clean.
 401                  */
 402                 smp_mb();
 403                 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
 404                     !test_bit(__IXGBE_DOWN, &adapter->state)) {
 405                         netif_wake_subqueue(netdev, tx_ring->queue_index);
 406                         ++adapter->restart_queue;
 407                 }
 408         }
 409
 410         if (adapter->detect_tx_hung) {
 411                 if (ixgbe_check_tx_hang(adapter, tx_ring, i)) {
 412                         /* schedule immediate reset if we believe we hung */
 413                         DPRINTK(PROBE, INFO,
 414                                 "tx hang %d detected, resetting adapter\n",
 415                                 adapter->tx_timeout_count + 1);
 416                         ixgbe_tx_timeout(adapter->netdev);
 417                 }
 418         }
 419
 420         /* re-arm the interrupt */
 421         if (count >= tx_ring->work_limit)
 422                 ixgbe_irq_rearm_queues(adapter, ((u64)1 << q_vector->v_idx));
 423
 424         tx_ring->total_bytes += total_bytes;
 425         tx_ring->total_packets += total_packets;
 426         tx_ring->stats.packets += total_packets;
 427         tx_ring->stats.bytes += total_bytes;
 428         netdev->stats.tx_bytes += total_bytes;
 429         netdev->stats.tx_packets += total_packets;
 430         return (count < tx_ring->work_limit);
 431 }
 432
 433 #ifdef CONFIG_IXGBE_DCA
 434 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
 435                                 struct ixgbe_ring *rx_ring)
 436 {
 437         u32 rxctrl;
 438         int cpu = get_cpu();
 439         int q = rx_ring - adapter->rx_ring;
 440
 441         if (rx_ring->cpu != cpu) {
 442                 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
 443                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 444                         rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
 445                         rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 446                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
 447                         rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
 448                         rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
 449                                    IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
 450                 }
 451                 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
 452                 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
 453                 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
 454                 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
 455                             IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
 456                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
 457                 rx_ring->cpu = cpu;
 458         }
 459         put_cpu();
 460 }
 461
 462 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
 463                                 struct ixgbe_ring *tx_ring)
 464 {
 465         u32 txctrl;
 466         int cpu = get_cpu();
 467         int q = tx_ring - adapter->tx_ring;
 468         struct ixgbe_hw *hw = &adapter->hw;
 469
 470         if (tx_ring->cpu != cpu) {
 471                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 472                         txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(q));
 473                         txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
 474                         txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 475                         txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
 476                         IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(q), txctrl);
 477                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
 478                         txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(q));
 479                         txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
 480                         txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
 481                                   IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
 482                         txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
 483                         IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(q), txctrl);
 484                 }
 485                 tx_ring->cpu = cpu;
 486         }
 487         put_cpu();
 488 }
 489
 490 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
 491 {
 492         int i;
 493
 494         if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
 495                 return;
 496
 497         /* always use CB2 mode, difference is masked in the CB driver */
 498         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
 499
 500         for (i = 0; i < adapter->num_tx_queues; i++) {
 501                 adapter->tx_ring[i].cpu = -1;
 502                 ixgbe_update_tx_dca(adapter, &adapter->tx_ring[i]);
 503         }
 504         for (i = 0; i < adapter->num_rx_queues; i++) {
 505                 adapter->rx_ring[i].cpu = -1;
 506                 ixgbe_update_rx_dca(adapter, &adapter->rx_ring[i]);
 507         }
 508 }
 509
 510 static int __ixgbe_notify_dca(struct device *dev, void *data)
 511 {
 512         struct net_device *netdev = dev_get_drvdata(dev);
 513         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 514         unsigned long event = *(unsigned long *)data;
 515
 516         switch (event) {
 517         case DCA_PROVIDER_ADD:
 518                 /* if we're already enabled, don't do it again */
 519                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
 520                         break;
 521                 if (dca_add_requester(dev) == 0) {
 522                         adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
 523                         ixgbe_setup_dca(adapter);
 524                         break;
 525                 }
 526                 /* Fall Through since DCA is disabled. */
 527         case DCA_PROVIDER_REMOVE:
 528                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
 529                         dca_remove_requester(dev);
 530                         adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
 531                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
 532                 }
 533                 break;
 534         }
 535
 536         return 0;
 537 }
 538
 539 #endif /* CONFIG_IXGBE_DCA */
 540 /**
 541  * ixgbe_receive_skb - Send a completed packet up the stack
 542  * @adapter: board private structure
 543  * @skb: packet to send up
 544  * @status: hardware indication of status of receive
 545  * @rx_ring: rx descriptor ring (for a specific queue) to setup
 546  * @rx_desc: rx descriptor
 547  **/
 548 static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
 549                               struct sk_buff *skb, u8 status,
 550                               struct ixgbe_ring *ring,
 551                               union ixgbe_adv_rx_desc *rx_desc)
 552 {
 553         struct ixgbe_adapter *adapter = q_vector->adapter;
 554         struct napi_struct *napi = &q_vector->napi;
 555         bool is_vlan = (status & IXGBE_RXD_STAT_VP);
 556         u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
 557
 558         skb_record_rx_queue(skb, ring->queue_index);
 559         if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) {
 560                 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
 561                         vlan_gro_receive(napi, adapter->vlgrp, tag, skb);
 562                 else
 563                         napi_gro_receive(napi, skb);
 564         } else {
 565                 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
 566                         vlan_hwaccel_rx(skb, adapter->vlgrp, tag);
 567                 else
 568                         netif_rx(skb);
 569         }
 570 }
 571
 572 /**
 573  * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
 574  * @adapter: address of board private structure
 575  * @status_err: hardware indication of status of receive
 576  * @skb: skb currently being received and modified
 577  **/
 578 static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
 579                                      union ixgbe_adv_rx_desc *rx_desc,
 580                                      struct sk_buff *skb)
 581 {
 582         u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error);
 583
 584         skb->ip_summed = CHECKSUM_NONE;
 585
 586         /* Rx csum disabled */
 587         if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
 588                 return;
 589
 590         /* if IP and error */
 591         if ((status_err & IXGBE_RXD_STAT_IPCS) &&
 592             (status_err & IXGBE_RXDADV_ERR_IPE)) {
 593                 adapter->hw_csum_rx_error++;
 594                 return;
 595         }
 596
 597         if (!(status_err & IXGBE_RXD_STAT_L4CS))
 598                 return;
 599
 600         if (status_err & IXGBE_RXDADV_ERR_TCPE) {
 601                 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
 602
 603                 /*
 604                  * 82599 errata, UDP frames with a 0 checksum can be marked as
 605                  * checksum errors.
 606                  */
 607                 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
 608                     (adapter->hw.mac.type == ixgbe_mac_82599EB))
 609                         return;
 610
 611                 adapter->hw_csum_rx_error++;
 612                 return;
 613         }
 614
 615         /* It must be a TCP or UDP packet with a valid checksum */
 616         skb->ip_summed = CHECKSUM_UNNECESSARY;
 617         adapter->hw_csum_rx_good++;
 618 }
 619
 620 static inline void ixgbe_release_rx_desc(struct ixgbe_hw *hw,
 621                                          struct ixgbe_ring *rx_ring, u32 val)
 622 {
 623         /*
 624          * Force memory writes to complete before letting h/w
 625          * know there are new descriptors to fetch.  (Only
 626          * applicable for weak-ordered memory model archs,
 627          * such as IA-64).
 628          */
 629         wmb();
 630         IXGBE_WRITE_REG(hw, IXGBE_RDT(rx_ring->reg_idx), val);
 631 }
 632
 633 /**
 634  * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
 635  * @adapter: address of board private structure
 636  **/
 637 static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
 638                                    struct ixgbe_ring *rx_ring,
 639                                    int cleaned_count)
 640 {
 641         struct pci_dev *pdev = adapter->pdev;
 642         union ixgbe_adv_rx_desc *rx_desc;
 643         struct ixgbe_rx_buffer *bi;
 644         unsigned int i;
 645
 646         i = rx_ring->next_to_use;
 647         bi = &rx_ring->rx_buffer_info[i];
 648
 649         while (cleaned_count--) {
 650                 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
 651
 652                 if (!bi->page_dma &&
 653                     (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)) {
 654                         if (!bi->page) {
 655                                 bi->page = alloc_page(GFP_ATOMIC);
 656                                 if (!bi->page) {
 657                                         adapter->alloc_rx_page_failed++;
 658                                         goto no_buffers;
 659                                 }
 660                                 bi->page_offset = 0;
 661                         } else {
 662                                 /* use a half page if we're re-using */
 663                                 bi->page_offset ^= (PAGE_SIZE / 2);
 664                         }
 665
 666                         bi->page_dma = pci_map_page(pdev, bi->page,
 667                                                     bi->page_offset,
 668                                                     (PAGE_SIZE / 2),
 669                                                     PCI_DMA_FROMDEVICE);
 670                 }
 671
 672                 if (!bi->skb) {
 673                         struct sk_buff *skb;
 674                         skb = netdev_alloc_skb_ip_align(adapter->netdev,
 675                                                         rx_ring->rx_buf_len);
 676
 677                         if (!skb) {
 678                                 adapter->alloc_rx_buff_failed++;
 679                                 goto no_buffers;
 680                         }
 681
 682                         bi->skb = skb;
 683                         bi->dma = pci_map_single(pdev, skb->data,
 684                                                  rx_ring->rx_buf_len,
 685                                                  PCI_DMA_FROMDEVICE);
 686                 }
 687                 /* Refresh the desc even if buffer_addrs didn't change because
 688                  * each write-back erases this info. */
 689                 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
 690                         rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
 691                         rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
 692                 } else {
 693                         rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
 694                 }
 695
 696                 i++;
 697                 if (i == rx_ring->count)
 698                         i = 0;
 699                 bi = &rx_ring->rx_buffer_info[i];
 700         }
 701
 702 no_buffers:
 703         if (rx_ring->next_to_use != i) {
 704                 rx_ring->next_to_use = i;
 705                 if (i-- == 0)
 706                         i = (rx_ring->count - 1);
 707
 708                 ixgbe_release_rx_desc(&adapter->hw, rx_ring, i);
 709         }
 710 }
 711
 712 static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
 713 {
 714         return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
 715 }
 716
 717 static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
 718 {
 719         return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
 720 }
 721
 722 static inline u32 ixgbe_get_rsc_count(union ixgbe_adv_rx_desc *rx_desc)
 723 {
 724         return (le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
 725                 IXGBE_RXDADV_RSCCNT_MASK) >>
 726                 IXGBE_RXDADV_RSCCNT_SHIFT;
 727 }
 728
 729 /**
 730  * ixgbe_transform_rsc_queue - change rsc queue into a full packet
 731  * @skb: pointer to the last skb in the rsc queue
 732  * @count: pointer to number of packets coalesced in this context
 733  *
 734  * This function changes a queue full of hw rsc buffers into a completed
 735  * packet.  It uses the ->prev pointers to find the first packet and then
 736  * turns it into the frag list owner.
 737  **/
 738 static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb,
 739                                                         u64 *count)
 740 {
 741         unsigned int frag_list_size = 0;
 742
 743         while (skb->prev) {
 744                 struct sk_buff *prev = skb->prev;
 745                 frag_list_size += skb->len;
 746                 skb->prev = NULL;
 747                 skb = prev;
 748                 *count += 1;
 749         }
 750
 751         skb_shinfo(skb)->frag_list = skb->next;
 752         skb->next = NULL;
 753         skb->len += frag_list_size;
 754         skb->data_len += frag_list_size;
 755         skb->truesize += frag_list_size;
 756         return skb;
 757 }
 758
 759 static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
 760                                struct ixgbe_ring *rx_ring,
 761                                int *work_done, int work_to_do)
 762 {
 763         struct ixgbe_adapter *adapter = q_vector->adapter;
 764         struct net_device *netdev = adapter->netdev;
 765         struct pci_dev *pdev = adapter->pdev;
 766         union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
 767         struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
 768         struct sk_buff *skb;
 769         unsigned int i, rsc_count = 0;
 770         u32 len, staterr;
 771         u16 hdr_info;
 772         bool cleaned = false;
 773         int cleaned_count = 0;
 774         unsigned int total_rx_bytes = 0, total_rx_packets = 0;
 775 #ifdef IXGBE_FCOE
 776         int ddp_bytes = 0;
 777 #endif /* IXGBE_FCOE */
 778
 779         i = rx_ring->next_to_clean;
 780         rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
 781         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
 782         rx_buffer_info = &rx_ring->rx_buffer_info[i];
 783
 784         while (staterr & IXGBE_RXD_STAT_DD) {
 785                 u32 upper_len = 0;
 786                 if (*work_done >= work_to_do)
 787                         break;
 788                 (*work_done)++;
 789
 790                 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
 791                         hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
 792                         len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
 793                                IXGBE_RXDADV_HDRBUFLEN_SHIFT;
 794                         if (hdr_info & IXGBE_RXDADV_SPH)
 795                                 adapter->rx_hdr_split++;
 796                         if (len > IXGBE_RX_HDR_SIZE)
 797                                 len = IXGBE_RX_HDR_SIZE;
 798                         upper_len = le16_to_cpu(rx_desc->wb.upper.length);
 799                 } else {
 800                         len = le16_to_cpu(rx_desc->wb.upper.length);
 801                 }
 802
 803                 cleaned = true;
 804                 skb = rx_buffer_info->skb;
 805                 prefetch(skb->data - NET_IP_ALIGN);
 806                 rx_buffer_info->skb = NULL;
 807
 808                 if (rx_buffer_info->dma) {
 809                         pci_unmap_single(pdev, rx_buffer_info->dma,
 810                                          rx_ring->rx_buf_len,
 811                                          PCI_DMA_FROMDEVICE);
 812                         rx_buffer_info->dma = 0;
 813                         skb_put(skb, len);
 814                 }
 815
 816                 if (upper_len) {
 817                         pci_unmap_page(pdev, rx_buffer_info->page_dma,
 818                                        PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
 819                         rx_buffer_info->page_dma = 0;
 820                         skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
 821                                            rx_buffer_info->page,
 822                                            rx_buffer_info->page_offset,
 823                                            upper_len);
 824
 825                         if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
 826                             (page_count(rx_buffer_info->page) != 1))
 827                                 rx_buffer_info->page = NULL;
 828                         else
 829                                 get_page(rx_buffer_info->page);
 830
 831                         skb->len += upper_len;
 832                         skb->data_len += upper_len;
 833                         skb->truesize += upper_len;
 834                 }
 835
 836                 i++;
 837                 if (i == rx_ring->count)
 838                         i = 0;
 839
 840                 next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i);
 841                 prefetch(next_rxd);
 842                 cleaned_count++;
 843
 844                 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
 845                         rsc_count = ixgbe_get_rsc_count(rx_desc);
 846
 847                 if (rsc_count) {
 848                         u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
 849                                      IXGBE_RXDADV_NEXTP_SHIFT;
 850                         next_buffer = &rx_ring->rx_buffer_info[nextp];
 851                 } else {
 852                         next_buffer = &rx_ring->rx_buffer_info[i];
 853                 }
 854
 855                 if (staterr & IXGBE_RXD_STAT_EOP) {
 856                         if (skb->prev)
 857                                 skb = ixgbe_transform_rsc_queue(skb, &(rx_ring->rsc_count));
 858                         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
 859                                 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)
 860                                         rx_ring->rsc_count += skb_shinfo(skb)->nr_frags;
 861                                 else
 862                                         rx_ring->rsc_count++;
 863                                 rx_ring->rsc_flush++;
 864                         }
 865                         rx_ring->stats.packets++;
 866                         rx_ring->stats.bytes += skb->len;
 867                 } else {
 868                         if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
 869                                 rx_buffer_info->skb = next_buffer->skb;
 870                                 rx_buffer_info->dma = next_buffer->dma;
 871                                 next_buffer->skb = skb;
 872                                 next_buffer->dma = 0;
 873                         } else {
 874                                 skb->next = next_buffer->skb;
 875                                 skb->next->prev = skb;
 876                         }
 877                         adapter->non_eop_descs++;
 878                         goto next_desc;
 879                 }
 880
 881                 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
 882                         dev_kfree_skb_irq(skb);
 883                         goto next_desc;
 884                 }
 885
 886                 ixgbe_rx_checksum(adapter, rx_desc, skb);
 887
 888                 /* probably a little skewed due to removing CRC */
 889                 total_rx_bytes += skb->len;
 890                 total_rx_packets++;
 891
 892                 skb->protocol = eth_type_trans(skb, adapter->netdev);
 893 #ifdef IXGBE_FCOE
 894                 /* if ddp, not passing to ULD unless for FCP_RSP or error */
 895                 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
 896                         ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
 897                         if (!ddp_bytes)
 898                                 goto next_desc;
 899                 }
 900 #endif /* IXGBE_FCOE */
 901                 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
 902
 903 next_desc:
 904                 rx_desc->wb.upper.status_error = 0;
 905
 906                 /* return some buffers to hardware, one at a time is too slow */
 907                 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
 908                         ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
 909                         cleaned_count = 0;
 910                 }
 911
 912                 /* use prefetched values */
 913                 rx_desc = next_rxd;
 914                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
 915
 916                 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
 917         }
 918
 919         rx_ring->next_to_clean = i;
 920         cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
 921
 922         if (cleaned_count)
 923                 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
 924
 925 #ifdef IXGBE_FCOE
 926         /* include DDPed FCoE data */
 927         if (ddp_bytes > 0) {
 928                 unsigned int mss;
 929
 930                 mss = adapter->netdev->mtu - sizeof(struct fcoe_hdr) -
 931                         sizeof(struct fc_frame_header) -
 932                         sizeof(struct fcoe_crc_eof);
 933                 if (mss > 512)
 934                         mss &= ~511;
 935                 total_rx_bytes += ddp_bytes;
 936                 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
 937         }
 938 #endif /* IXGBE_FCOE */
 939
 940         rx_ring->total_packets += total_rx_packets;
 941         rx_ring->total_bytes += total_rx_bytes;
 942         netdev->stats.rx_bytes += total_rx_bytes;
 943         netdev->stats.rx_packets += total_rx_packets;
 944
 945         return cleaned;
 946 }
 947
 948 static int ixgbe_clean_rxonly(struct napi_struct *, int);
 949 /**
 950  * ixgbe_configure_msix - Configure MSI-X hardware
 951  * @adapter: board private structure
 952  *
 953  * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
 954  * interrupts.
 955  **/
 956 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
 957 {
 958         struct ixgbe_q_vector *q_vector;
 959         int i, j, q_vectors, v_idx, r_idx;
 960         u32 mask;
 961
 962         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
 963
 964         /*
 965          * Populate the IVAR table and set the ITR values to the
 966          * corresponding register.
 967          */
 968         for (v_idx = 0; v_idx < q_vectors; v_idx++) {
 969                 q_vector = adapter->q_vector[v_idx];
 970                 /* XXX for_each_bit(...) */
 971                 r_idx = find_first_bit(q_vector->rxr_idx,
 972                                        adapter->num_rx_queues);
 973
 974                 for (i = 0; i < q_vector->rxr_count; i++) {
 975                         j = adapter->rx_ring[r_idx].reg_idx;
 976                         ixgbe_set_ivar(adapter, 0, j, v_idx);
 977                         r_idx = find_next_bit(q_vector->rxr_idx,
 978                                               adapter->num_rx_queues,
 979                                               r_idx + 1);
 980                 }
 981                 r_idx = find_first_bit(q_vector->txr_idx,
 982                                        adapter->num_tx_queues);
 983
 984                 for (i = 0; i < q_vector->txr_count; i++) {
 985                         j = adapter->tx_ring[r_idx].reg_idx;
 986                         ixgbe_set_ivar(adapter, 1, j, v_idx);
 987                         r_idx = find_next_bit(q_vector->txr_idx,
 988                                               adapter->num_tx_queues,
 989                                               r_idx + 1);
 990                 }
 991
 992                 if (q_vector->txr_count && !q_vector->rxr_count)
 993                         /* tx only */
 994                         q_vector->eitr = adapter->tx_eitr_param;
 995                 else if (q_vector->rxr_count)
 996                         /* rx or mixed */
 997                         q_vector->eitr = adapter->rx_eitr_param;
 998
 999                 ixgbe_write_eitr(q_vector);
1000         }
1001
1002         if (adapter->hw.mac.type == ixgbe_mac_82598EB)
1003                 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
1004                                v_idx);
1005         else if (adapter->hw.mac.type == ixgbe_mac_82599EB)
1006                 ixgbe_set_ivar(adapter, -1, 1, v_idx);
1007         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1008
1009         /* set up to autoclear timer, and the vectors */
1010         mask = IXGBE_EIMS_ENABLE_MASK;
1011         mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
1012         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
1013 }
1014
1015 enum latency_range {
1016         lowest_latency = 0,
1017         low_latency = 1,
1018         bulk_latency = 2,
1019         latency_invalid = 255
1020 };
1021
1022 /**
1023  * ixgbe_update_itr - update the dynamic ITR value based on statistics
1024  * @adapter: pointer to adapter
1025  * @eitr: eitr setting (ints per sec) to give last timeslice
1026  * @itr_setting: current throttle rate in ints/second
1027  * @packets: the number of packets during this measurement interval
1028  * @bytes: the number of bytes during this measurement interval
1029  *
1030  *      Stores a new ITR value based on packets and byte
1031  *      counts during the last interrupt.  The advantage of per interrupt
1032  *      computation is faster updates and more accurate ITR for the current
1033  *      traffic pattern.  Constants in this function were computed
1034  *      based on theoretical maximum wire speed and thresholds were set based
1035  *      on testing data as well as attempting to minimize response time
1036  *      while increasing bulk throughput.
1037  *      this functionality is controlled by the InterruptThrottleRate module
1038  *      parameter (see ixgbe_param.c)
1039  **/
1040 static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
1041                            u32 eitr, u8 itr_setting,
1042                            int packets, int bytes)
1043 {
1044         unsigned int retval = itr_setting;
1045         u32 timepassed_us;
1046         u64 bytes_perint;
1047
1048         if (packets == 0)
1049                 goto update_itr_done;
1050
1051
1052         /* simple throttlerate management
1053          *    0-20MB/s lowest (100000 ints/s)
1054          *   20-100MB/s low   (20000 ints/s)
1055          *  100-1249MB/s bulk (8000 ints/s)
1056          */
1057         /* what was last interrupt timeslice? */
1058         timepassed_us = 1000000/eitr;
1059         bytes_perint = bytes / timepassed_us; /* bytes/usec */
1060
1061         switch (itr_setting) {
1062         case lowest_latency:
1063                 if (bytes_perint > adapter->eitr_low)
1064                         retval = low_latency;
1065                 break;
1066         case low_latency:
1067                 if (bytes_perint > adapter->eitr_high)
1068                         retval = bulk_latency;
1069                 else if (bytes_perint <= adapter->eitr_low)
1070                         retval = lowest_latency;
1071                 break;
1072         case bulk_latency:
1073                 if (bytes_perint <= adapter->eitr_high)
1074                         retval = low_latency;
1075                 break;
1076         }
1077
1078 update_itr_done:
1079         return retval;
1080 }
1081
1082 /**
1083  * ixgbe_write_eitr - write EITR register in hardware specific way
1084  * @q_vector: structure containing interrupt and ring information
1085  *
1086  * This function is made to be called by ethtool and by the driver
1087  * when it needs to update EITR registers at runtime.  Hardware
1088  * specific quirks/differences are taken care of here.
1089  */
1090 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
1091 {
1092         struct ixgbe_adapter *adapter = q_vector->adapter;
1093         struct ixgbe_hw *hw = &adapter->hw;
1094         int v_idx = q_vector->v_idx;
1095         u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1096
1097         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1098                 /* must write high and low 16 bits to reset counter */
1099                 itr_reg |= (itr_reg << 16);
1100         } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1101                 /*
1102                  * set the WDIS bit to not clear the timer bits and cause an
1103                  * immediate assertion of the interrupt
1104                  */
1105                 itr_reg |= IXGBE_EITR_CNT_WDIS;
1106         }
1107         IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1108 }
1109
1110 static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
1111 {
1112         struct ixgbe_adapter *adapter = q_vector->adapter;
1113         u32 new_itr;
1114         u8 current_itr, ret_itr;
1115         int i, r_idx;
1116         struct ixgbe_ring *rx_ring, *tx_ring;
1117
1118         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1119         for (i = 0; i < q_vector->txr_count; i++) {
1120                 tx_ring = &(adapter->tx_ring[r_idx]);
1121                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1122                                            q_vector->tx_itr,
1123                                            tx_ring->total_packets,
1124                                            tx_ring->total_bytes);
1125                 /* if the result for this queue would decrease interrupt
1126                  * rate for this vector then use that result */
1127                 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
1128                                     q_vector->tx_itr - 1 : ret_itr);
1129                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1130                                       r_idx + 1);
1131         }
1132
1133         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1134         for (i = 0; i < q_vector->rxr_count; i++) {
1135                 rx_ring = &(adapter->rx_ring[r_idx]);
1136                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1137                                            q_vector->rx_itr,
1138                                            rx_ring->total_packets,
1139                                            rx_ring->total_bytes);
1140                 /* if the result for this queue would decrease interrupt
1141                  * rate for this vector then use that result */
1142                 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
1143                                     q_vector->rx_itr - 1 : ret_itr);
1144                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1145                                       r_idx + 1);
1146         }
1147
1148         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1149
1150         switch (current_itr) {
1151         /* counts and packets in update_itr are dependent on these numbers */
1152         case lowest_latency:
1153                 new_itr = 100000;
1154                 break;
1155         case low_latency:
1156                 new_itr = 20000; /* aka hwitr = ~200 */
1157                 break;
1158         case bulk_latency:
1159         default:
1160                 new_itr = 8000;
1161                 break;
1162         }
1163
1164         if (new_itr != q_vector->eitr) {
1165                 /* do an exponential smoothing */
1166                 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1167
1168                 /* save the algorithm value here, not the smoothed one */
1169                 q_vector->eitr = new_itr;
1170
1171                 ixgbe_write_eitr(q_vector);
1172         }
1173
1174         return;
1175 }
1176
1177 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1178 {
1179         struct ixgbe_hw *hw = &adapter->hw;
1180
1181         if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1182             (eicr & IXGBE_EICR_GPI_SDP1)) {
1183                 DPRINTK(PROBE, CRIT, "Fan has stopped, replace the adapter\n");
1184                 /* write to clear the interrupt */
1185                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1186         }
1187 }
1188
1189 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1190 {
1191         struct ixgbe_hw *hw = &adapter->hw;
1192
1193         if (eicr & IXGBE_EICR_GPI_SDP1) {
1194                 /* Clear the interrupt */
1195                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1196                 schedule_work(&adapter->multispeed_fiber_task);
1197         } else if (eicr & IXGBE_EICR_GPI_SDP2) {
1198                 /* Clear the interrupt */
1199                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1200                 schedule_work(&adapter->sfp_config_module_task);
1201         } else {
1202                 /* Interrupt isn't for us... */
1203                 return;
1204         }
1205 }
1206
1207 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1208 {
1209         struct ixgbe_hw *hw = &adapter->hw;
1210
1211         adapter->lsc_int++;
1212         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1213         adapter->link_check_timeout = jiffies;
1214         if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1215                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1216                 IXGBE_WRITE_FLUSH(hw);
1217                 schedule_work(&adapter->watchdog_task);
1218         }
1219 }
1220
1221 static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1222 {
1223         struct net_device *netdev = data;
1224         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1225         struct ixgbe_hw *hw = &adapter->hw;
1226         u32 eicr;
1227
1228         /*
1229          * Workaround for Silicon errata.  Use clear-by-write instead
1230          * of clear-by-read.  Reading with EICS will return the
1231          * interrupt causes without clearing, which later be done
1232          * with the write to EICR.
1233          */
1234         eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1235         IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
1236
1237         if (eicr & IXGBE_EICR_LSC)
1238                 ixgbe_check_lsc(adapter);
1239
1240         if (hw->mac.type == ixgbe_mac_82598EB)
1241                 ixgbe_check_fan_failure(adapter, eicr);
1242
1243         if (hw->mac.type == ixgbe_mac_82599EB) {
1244                 ixgbe_check_sfp_event(adapter, eicr);
1245
1246                 /* Handle Flow Director Full threshold interrupt */
1247                 if (eicr & IXGBE_EICR_FLOW_DIR) {
1248                         int i;
1249                         IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR);
1250                         /* Disable transmits before FDIR Re-initialization */
1251                         netif_tx_stop_all_queues(netdev);
1252                         for (i = 0; i < adapter->num_tx_queues; i++) {
1253                                 struct ixgbe_ring *tx_ring =
1254                                                            &adapter->tx_ring[i];
1255                                 if (test_and_clear_bit(__IXGBE_FDIR_INIT_DONE,
1256                                                        &tx_ring->reinit_state))
1257                                         schedule_work(&adapter->fdir_reinit_task);
1258                         }
1259                 }
1260         }
1261         if (!test_bit(__IXGBE_DOWN, &adapter->state))
1262                 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
1263
1264         return IRQ_HANDLED;
1265 }
1266
1267 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1268                                            u64 qmask)
1269 {
1270         u32 mask;
1271
1272         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1273                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1274                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1275         } else {
1276                 mask = (qmask & 0xFFFFFFFF);
1277                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(0), mask);
1278                 mask = (qmask >> 32);
1279                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1), mask);
1280         }
1281         /* skip the flush */
1282 }
1283
1284 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
1285                                             u64 qmask)
1286 {
1287         u32 mask;
1288
1289         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1290                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1291                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, mask);
1292         } else {
1293                 mask = (qmask & 0xFFFFFFFF);
1294                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), mask);
1295                 mask = (qmask >> 32);
1296                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), mask);
1297         }
1298         /* skip the flush */
1299 }
1300
1301 static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1302 {
1303         struct ixgbe_q_vector *q_vector = data;
1304         struct ixgbe_adapter  *adapter = q_vector->adapter;
1305         struct ixgbe_ring     *tx_ring;
1306         int i, r_idx;
1307
1308         if (!q_vector->txr_count)
1309                 return IRQ_HANDLED;
1310
1311         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1312         for (i = 0; i < q_vector->txr_count; i++) {
1313                 tx_ring = &(adapter->tx_ring[r_idx]);
1314                 tx_ring->total_bytes = 0;
1315                 tx_ring->total_packets = 0;
1316                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1317                                       r_idx + 1);
1318         }
1319
1320         /* disable interrupts on this vector only */
1321         ixgbe_irq_disable_queues(adapter, ((u64)1 << q_vector->v_idx));
1322         napi_schedule(&q_vector->napi);
1323
1324         return IRQ_HANDLED;
1325 }
1326
1327 /**
1328  * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1329  * @irq: unused
1330  * @data: pointer to our q_vector struct for this interrupt vector
1331  **/
1332 static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
1333 {
1334         struct ixgbe_q_vector *q_vector = data;
1335         struct ixgbe_adapter  *adapter = q_vector->adapter;
1336         struct ixgbe_ring  *rx_ring;
1337         int r_idx;
1338         int i;
1339
1340         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1341         for (i = 0;  i < q_vector->rxr_count; i++) {
1342                 rx_ring = &(adapter->rx_ring[r_idx]);
1343                 rx_ring->total_bytes = 0;
1344                 rx_ring->total_packets = 0;
1345                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1346                                       r_idx + 1);
1347         }
1348
1349         if (!q_vector->rxr_count)
1350                 return IRQ_HANDLED;
1351
1352         /* disable interrupts on this vector only */
1353         ixgbe_irq_disable_queues(adapter, ((u64)1 << q_vector->v_idx));
1354         napi_schedule(&q_vector->napi);
1355
1356         return IRQ_HANDLED;
1357 }
1358
1359 static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1360 {
1361         struct ixgbe_q_vector *q_vector = data;
1362         struct ixgbe_adapter  *adapter = q_vector->adapter;
1363         struct ixgbe_ring  *ring;
1364         int r_idx;
1365         int i;
1366
1367         if (!q_vector->txr_count && !q_vector->rxr_count)
1368                 return IRQ_HANDLED;
1369
1370         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1371         for (i = 0; i < q_vector->txr_count; i++) {
1372                 ring = &(adapter->tx_ring[r_idx]);
1373                 ring->total_bytes = 0;
1374                 ring->total_packets = 0;
1375                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1376                                       r_idx + 1);
1377         }
1378
1379         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1380         for (i = 0; i < q_vector->rxr_count; i++) {
1381                 ring = &(adapter->rx_ring[r_idx]);
1382                 ring->total_bytes = 0;
1383                 ring->total_packets = 0;
1384                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1385                                       r_idx + 1);
1386         }
1387
1388         /* disable interrupts on this vector only */
1389         ixgbe_irq_disable_queues(adapter, ((u64)1 << q_vector->v_idx));
1390         napi_schedule(&q_vector->napi);
1391
1392         return IRQ_HANDLED;
1393 }
1394
1395 /**
1396  * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1397  * @napi: napi struct with our devices info in it
1398  * @budget: amount of work driver is allowed to do this pass, in packets
1399  *
1400  * This function is optimized for cleaning one queue only on a single
1401  * q_vector!!!
1402  **/
1403 static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1404 {
1405         struct ixgbe_q_vector *q_vector =
1406                                container_of(napi, struct ixgbe_q_vector, napi);
1407         struct ixgbe_adapter *adapter = q_vector->adapter;
1408         struct ixgbe_ring *rx_ring = NULL;
1409         int work_done = 0;
1410         long r_idx;
1411
1412         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1413         rx_ring = &(adapter->rx_ring[r_idx]);
1414 #ifdef CONFIG_IXGBE_DCA
1415         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1416                 ixgbe_update_rx_dca(adapter, rx_ring);
1417 #endif
1418
1419         ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
1420
1421         /* If all Rx work done, exit the polling mode */
1422         if (work_done < budget) {
1423                 napi_complete(napi);
1424                 if (adapter->rx_itr_setting & 1)
1425                         ixgbe_set_itr_msix(q_vector);
1426                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1427                         ixgbe_irq_enable_queues(adapter,
1428                                                 ((u64)1 << q_vector->v_idx));
1429         }
1430
1431         return work_done;
1432 }
1433
1434 /**
1435  * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
1436  * @napi: napi struct with our devices info in it
1437  * @budget: amount of work driver is allowed to do this pass, in packets
1438  *
1439  * This function will clean more than one rx queue associated with a
1440  * q_vector.
1441  **/
1442 static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
1443 {
1444         struct ixgbe_q_vector *q_vector =
1445                                container_of(napi, struct ixgbe_q_vector, napi);
1446         struct ixgbe_adapter *adapter = q_vector->adapter;
1447         struct ixgbe_ring *ring = NULL;
1448         int work_done = 0, i;
1449         long r_idx;
1450         bool tx_clean_complete = true;
1451
1452         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1453         for (i = 0; i < q_vector->txr_count; i++) {
1454                 ring = &(adapter->tx_ring[r_idx]);
1455 #ifdef CONFIG_IXGBE_DCA
1456                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1457                         ixgbe_update_tx_dca(adapter, ring);
1458 #endif
1459                 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
1460                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1461                                       r_idx + 1);
1462         }
1463
1464         /* attempt to distribute budget to each queue fairly, but don't allow
1465          * the budget to go below 1 because we'll exit polling */
1466         budget /= (q_vector->rxr_count ?: 1);
1467         budget = max(budget, 1);
1468         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1469         for (i = 0; i < q_vector->rxr_count; i++) {
1470                 ring = &(adapter->rx_ring[r_idx]);
1471 #ifdef CONFIG_IXGBE_DCA
1472                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1473                         ixgbe_update_rx_dca(adapter, ring);
1474 #endif
1475                 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
1476                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1477                                       r_idx + 1);
1478         }
1479
1480         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1481         ring = &(adapter->rx_ring[r_idx]);
1482         /* If all Rx work done, exit the polling mode */
1483         if (work_done < budget) {
1484                 napi_complete(napi);
1485                 if (adapter->rx_itr_setting & 1)
1486                         ixgbe_set_itr_msix(q_vector);
1487                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1488                         ixgbe_irq_enable_queues(adapter,
1489                                                 ((u64)1 << q_vector->v_idx));
1490                 return 0;
1491         }
1492
1493         return work_done;
1494 }
1495
1496 /**
1497  * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
1498  * @napi: napi struct with our devices info in it
1499  * @budget: amount of work driver is allowed to do this pass, in packets
1500  *
1501  * This function is optimized for cleaning one queue only on a single
1502  * q_vector!!!
1503  **/
1504 static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
1505 {
1506         struct ixgbe_q_vector *q_vector =
1507                                container_of(napi, struct ixgbe_q_vector, napi);
1508         struct ixgbe_adapter *adapter = q_vector->adapter;
1509         struct ixgbe_ring *tx_ring = NULL;
1510         int work_done = 0;
1511         long r_idx;
1512
1513         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1514         tx_ring = &(adapter->tx_ring[r_idx]);
1515 #ifdef CONFIG_IXGBE_DCA
1516         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1517                 ixgbe_update_tx_dca(adapter, tx_ring);
1518 #endif
1519
1520         if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
1521                 work_done = budget;
1522
1523         /* If all Tx work done, exit the polling mode */
1524         if (work_done < budget) {
1525                 napi_complete(napi);
1526                 if (adapter->tx_itr_setting & 1)
1527                         ixgbe_set_itr_msix(q_vector);
1528                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1529                         ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
1530         }
1531
1532         return work_done;
1533 }
1534
1535 static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
1536                                      int r_idx)
1537 {
1538         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1539
1540         set_bit(r_idx, q_vector->rxr_idx);
1541         q_vector->rxr_count++;
1542 }
1543
1544 static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
1545                                      int t_idx)
1546 {
1547         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1548
1549         set_bit(t_idx, q_vector->txr_idx);
1550         q_vector->txr_count++;
1551 }
1552
1553 /**
1554  * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
1555  * @adapter: board private structure to initialize
1556  * @vectors: allotted vector count for descriptor rings
1557  *
1558  * This function maps descriptor rings to the queue-specific vectors
1559  * we were allotted through the MSI-X enabling code.  Ideally, we'd have
1560  * one vector per ring/queue, but on a constrained vector budget, we
1561  * group the rings as "efficiently" as possible.  You would add new
1562  * mapping configurations in here.
1563  **/
1564 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
1565                                       int vectors)
1566 {
1567         int v_start = 0;
1568         int rxr_idx = 0, txr_idx = 0;
1569         int rxr_remaining = adapter->num_rx_queues;
1570         int txr_remaining = adapter->num_tx_queues;
1571         int i, j;
1572         int rqpv, tqpv;
1573         int err = 0;
1574
1575         /* No mapping required if MSI-X is disabled. */
1576         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1577                 goto out;
1578
1579         /*
1580          * The ideal configuration...
1581          * We have enough vectors to map one per queue.
1582          */
1583         if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
1584                 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
1585                         map_vector_to_rxq(adapter, v_start, rxr_idx);
1586
1587                 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
1588                         map_vector_to_txq(adapter, v_start, txr_idx);
1589
1590                 goto out;
1591         }
1592
1593         /*
1594          * If we don't have enough vectors for a 1-to-1
1595          * mapping, we'll have to group them so there are
1596          * multiple queues per vector.
1597          */
1598         /* Re-adjusting *qpv takes care of the remainder. */
1599         for (i = v_start; i < vectors; i++) {
1600                 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
1601                 for (j = 0; j < rqpv; j++) {
1602                         map_vector_to_rxq(adapter, i, rxr_idx);
1603                         rxr_idx++;
1604                         rxr_remaining--;
1605                 }
1606         }
1607         for (i = v_start; i < vectors; i++) {
1608                 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
1609                 for (j = 0; j < tqpv; j++) {
1610                         map_vector_to_txq(adapter, i, txr_idx);
1611                         txr_idx++;
1612                         txr_remaining--;
1613                 }
1614         }
1615
1616 out:
1617         return err;
1618 }
1619
1620 /**
1621  * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
1622  * @adapter: board private structure
1623  *
1624  * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
1625  * interrupts from the kernel.
1626  **/
1627 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
1628 {
1629         struct net_device *netdev = adapter->netdev;
1630         irqreturn_t (*handler)(int, void *);
1631         int i, vector, q_vectors, err;
1632         int ri=0, ti=0;
1633
1634         /* Decrement for Other and TCP Timer vectors */
1635         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1636
1637         /* Map the Tx/Rx rings to the vectors we were allotted. */
1638         err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
1639         if (err)
1640                 goto out;
1641
1642 #define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
1643                          (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
1644                          &ixgbe_msix_clean_many)
1645         for (vector = 0; vector < q_vectors; vector++) {
1646                 handler = SET_HANDLER(adapter->q_vector[vector]);
1647
1648                 if(handler == &ixgbe_msix_clean_rx) {
1649                         sprintf(adapter->name[vector], "%s-%s-%d",
1650                                 netdev->name, "rx", ri++);
1651                 }
1652                 else if(handler == &ixgbe_msix_clean_tx) {
1653                         sprintf(adapter->name[vector], "%s-%s-%d",
1654                                 netdev->name, "tx", ti++);
1655                 }
1656                 else
1657                         sprintf(adapter->name[vector], "%s-%s-%d",
1658                                 netdev->name, "TxRx", vector);
1659
1660                 err = request_irq(adapter->msix_entries[vector].vector,
1661                                   handler, 0, adapter->name[vector],
1662                                   adapter->q_vector[vector]);
1663                 if (err) {
1664                         DPRINTK(PROBE, ERR,
1665                                 "request_irq failed for MSIX interrupt "
1666                                 "Error: %d\n", err);
1667                         goto free_queue_irqs;
1668                 }
1669         }
1670
1671         sprintf(adapter->name[vector], "%s:lsc", netdev->name);
1672         err = request_irq(adapter->msix_entries[vector].vector,
1673                           ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
1674         if (err) {
1675                 DPRINTK(PROBE, ERR,
1676                         "request_irq for msix_lsc failed: %d\n", err);
1677                 goto free_queue_irqs;
1678         }
1679
1680         return 0;
1681
1682 free_queue_irqs:
1683         for (i = vector - 1; i >= 0; i--)
1684                 free_irq(adapter->msix_entries[--vector].vector,
1685                          adapter->q_vector[i]);
1686         adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
1687         pci_disable_msix(adapter->pdev);
1688         kfree(adapter->msix_entries);
1689         adapter->msix_entries = NULL;
1690 out:
1691         return err;
1692 }
1693
1694 static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
1695 {
1696         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
1697         u8 current_itr;
1698         u32 new_itr = q_vector->eitr;
1699         struct ixgbe_ring *rx_ring = &adapter->rx_ring[0];
1700         struct ixgbe_ring *tx_ring = &adapter->tx_ring[0];
1701
1702         q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
1703                                             q_vector->tx_itr,
1704                                             tx_ring->total_packets,
1705                                             tx_ring->total_bytes);
1706         q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
1707                                             q_vector->rx_itr,
1708                                             rx_ring->total_packets,
1709                                             rx_ring->total_bytes);
1710
1711         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1712
1713         switch (current_itr) {
1714         /* counts and packets in update_itr are dependent on these numbers */
1715         case lowest_latency:
1716                 new_itr = 100000;
1717                 break;
1718         case low_latency:
1719                 new_itr = 20000; /* aka hwitr = ~200 */
1720                 break;
1721         case bulk_latency:
1722                 new_itr = 8000;
1723                 break;
1724         default:
1725                 break;
1726         }
1727
1728         if (new_itr != q_vector->eitr) {
1729                 /* do an exponential smoothing */
1730                 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1731
1732                 /* save the algorithm value here, not the smoothed one */
1733                 q_vector->eitr = new_itr;
1734
1735                 ixgbe_write_eitr(q_vector);
1736         }
1737
1738         return;
1739 }
1740
1741 /**
1742  * ixgbe_irq_enable - Enable default interrupt generation settings
1743  * @adapter: board private structure
1744  **/
1745 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter)
1746 {
1747         u32 mask;
1748
1749         mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
1750         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
1751                 mask |= IXGBE_EIMS_GPI_SDP1;
1752         if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1753                 mask |= IXGBE_EIMS_ECC;
1754                 mask |= IXGBE_EIMS_GPI_SDP1;
1755                 mask |= IXGBE_EIMS_GPI_SDP2;
1756         }
1757         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
1758             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
1759                 mask |= IXGBE_EIMS_FLOW_DIR;
1760
1761         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1762         ixgbe_irq_enable_queues(adapter, ~0);
1763         IXGBE_WRITE_FLUSH(&adapter->hw);
1764 }
1765
1766 /**
1767  * ixgbe_intr - legacy mode Interrupt Handler
1768  * @irq: interrupt number
1769  * @data: pointer to a network interface device structure
1770  **/
1771 static irqreturn_t ixgbe_intr(int irq, void *data)
1772 {
1773         struct net_device *netdev = data;
1774         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1775         struct ixgbe_hw *hw = &adapter->hw;
1776         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
1777         u32 eicr;
1778
1779         /*
1780          * Workaround for silicon errata.  Mask the interrupts
1781          * before the read of EICR.
1782          */
1783         IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
1784
1785         /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
1786          * therefore no explict interrupt disable is necessary */
1787         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
1788         if (!eicr) {
1789                 /* shared interrupt alert!
1790                  * make sure interrupts are enabled because the read will
1791                  * have disabled interrupts due to EIAM */
1792                 ixgbe_irq_enable(adapter);
1793                 return IRQ_NONE;        /* Not our interrupt */
1794         }
1795
1796         if (eicr & IXGBE_EICR_LSC)
1797                 ixgbe_check_lsc(adapter);
1798
1799         if (hw->mac.type == ixgbe_mac_82599EB)
1800                 ixgbe_check_sfp_event(adapter, eicr);
1801
1802         ixgbe_check_fan_failure(adapter, eicr);
1803
1804         if (napi_schedule_prep(&(q_vector->napi))) {
1805                 adapter->tx_ring[0].total_packets = 0;
1806                 adapter->tx_ring[0].total_bytes = 0;
1807                 adapter->rx_ring[0].total_packets = 0;
1808                 adapter->rx_ring[0].total_bytes = 0;
1809                 /* would disable interrupts here but EIAM disabled it */
1810                 __napi_schedule(&(q_vector->napi));
1811         }
1812
1813         return IRQ_HANDLED;
1814 }
1815
1816 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
1817 {
1818         int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1819
1820         for (i = 0; i < q_vectors; i++) {
1821                 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
1822                 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
1823                 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
1824                 q_vector->rxr_count = 0;
1825                 q_vector->txr_count = 0;
1826         }
1827 }
1828
1829 /**
1830  * ixgbe_request_irq - initialize interrupts
1831  * @adapter: board private structure
1832  *
1833  * Attempts to configure interrupts using the best available
1834  * capabilities of the hardware and kernel.
1835  **/
1836 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
1837 {
1838         struct net_device *netdev = adapter->netdev;
1839         int err;
1840
1841         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1842                 err = ixgbe_request_msix_irqs(adapter);
1843         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1844                 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
1845                                   netdev->name, netdev);
1846         } else {
1847                 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
1848                                   netdev->name, netdev);
1849         }
1850
1851         if (err)
1852                 DPRINTK(PROBE, ERR, "request_irq failed, Error %d\n", err);
1853
1854         return err;
1855 }
1856
1857 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
1858 {
1859         struct net_device *netdev = adapter->netdev;
1860
1861         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1862                 int i, q_vectors;
1863
1864                 q_vectors = adapter->num_msix_vectors;
1865
1866                 i = q_vectors - 1;
1867                 free_irq(adapter->msix_entries[i].vector, netdev);
1868
1869                 i--;
1870                 for (; i >= 0; i--) {
1871                         free_irq(adapter->msix_entries[i].vector,
1872                                  adapter->q_vector[i]);
1873                 }
1874
1875                 ixgbe_reset_q_vectors(adapter);
1876         } else {
1877                 free_irq(adapter->pdev->irq, netdev);
1878         }
1879 }
1880
1881 /**
1882  * ixgbe_irq_disable - Mask off interrupt generation on the NIC
1883  * @adapter: board private structure
1884  **/
1885 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
1886 {
1887         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1888                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
1889         } else {
1890                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
1891                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
1892                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
1893         }
1894         IXGBE_WRITE_FLUSH(&adapter->hw);
1895         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1896                 int i;
1897                 for (i = 0; i < adapter->num_msix_vectors; i++)
1898                         synchronize_irq(adapter->msix_entries[i].vector);
1899         } else {
1900                 synchronize_irq(adapter->pdev->irq);
1901         }
1902 }
1903
1904 /**
1905  * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
1906  *
1907  **/
1908 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
1909 {
1910         struct ixgbe_hw *hw = &adapter->hw;
1911
1912         IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
1913                         EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
1914
1915         ixgbe_set_ivar(adapter, 0, 0, 0);
1916         ixgbe_set_ivar(adapter, 1, 0, 0);
1917
1918         map_vector_to_rxq(adapter, 0, 0);
1919         map_vector_to_txq(adapter, 0, 0);
1920
1921         DPRINTK(HW, INFO, "Legacy interrupt IVAR setup done\n");
1922 }
1923
1924 /**
1925  * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
1926  * @adapter: board private structure
1927  *
1928  * Configure the Tx unit of the MAC after a reset.
1929  **/
1930 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
1931 {
1932         u64 tdba;
1933         struct ixgbe_hw *hw = &adapter->hw;
1934         u32 i, j, tdlen, txctrl;
1935
1936         /* Setup the HW Tx Head and Tail descriptor pointers */
1937         for (i = 0; i < adapter->num_tx_queues; i++) {
1938                 struct ixgbe_ring *ring = &adapter->tx_ring[i];
1939                 j = ring->reg_idx;
1940                 tdba = ring->dma;
1941                 tdlen = ring->count * sizeof(union ixgbe_adv_tx_desc);
1942                 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j),
1943                                 (tdba & DMA_BIT_MASK(32)));
1944                 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32));
1945                 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), tdlen);
1946                 IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0);
1947                 IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0);
1948                 adapter->tx_ring[i].head = IXGBE_TDH(j);
1949                 adapter->tx_ring[i].tail = IXGBE_TDT(j);
1950                 /*
1951                  * Disable Tx Head Writeback RO bit, since this hoses
1952                  * bookkeeping if things aren't delivered in order.
1953                  */
1954                 switch (hw->mac.type) {
1955                 case ixgbe_mac_82598EB:
1956                         txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j));
1957                         break;
1958                 case ixgbe_mac_82599EB:
1959                 default:
1960                         txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(j));
1961                         break;
1962                 }
1963                 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
1964                 switch (hw->mac.type) {
1965                 case ixgbe_mac_82598EB:
1966                         IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl);
1967                         break;
1968                 case ixgbe_mac_82599EB:
1969                 default:
1970                         IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(j), txctrl);
1971                         break;
1972                 }
1973         }
1974
1975         if (hw->mac.type == ixgbe_mac_82599EB) {
1976                 u32 rttdcs;
1977
1978                 /* disable the arbiter while setting MTQC */
1979                 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
1980                 rttdcs |= IXGBE_RTTDCS_ARBDIS;
1981                 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
1982
1983                 /* We enable 8 traffic classes, DCB only */
1984                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
1985                         IXGBE_WRITE_REG(hw, IXGBE_MTQC, (IXGBE_MTQC_RT_ENA |
1986                                         IXGBE_MTQC_8TC_8TQ));
1987                 else
1988                         IXGBE_WRITE_REG(hw, IXGBE_MTQC, IXGBE_MTQC_64Q_1PB);
1989
1990                 /* re-eable the arbiter */
1991                 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
1992                 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
1993         }
1994 }
1995
1996 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
1997
1998 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
1999                                    struct ixgbe_ring *rx_ring)
2000 {
2001         u32 srrctl;
2002         int index;
2003         struct ixgbe_ring_feature *feature = adapter->ring_feature;
2004
2005         index = rx_ring->reg_idx;
2006         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2007                 unsigned long mask;
2008                 mask = (unsigned long) feature[RING_F_RSS].mask;
2009                 index = index & mask;
2010         }
2011         srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
2012
2013         srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2014         srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
2015
2016         srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2017                   IXGBE_SRRCTL_BSIZEHDR_MASK;
2018
2019         if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
2020 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2021                 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2022 #else
2023                 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2024 #endif
2025                 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2026         } else {
2027                 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2028                           IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2029                 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
2030         }
2031
2032         IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
2033 }
2034
2035 static u32 ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
2036 {
2037         u32 mrqc = 0;
2038         int mask;
2039
2040         if (!(adapter->hw.mac.type == ixgbe_mac_82599EB))
2041                 return mrqc;
2042
2043         mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2044 #ifdef CONFIG_IXGBE_DCB
2045                                  | IXGBE_FLAG_DCB_ENABLED
2046 #endif
2047                                 );
2048
2049         switch (mask) {
2050         case (IXGBE_FLAG_RSS_ENABLED):
2051                 mrqc = IXGBE_MRQC_RSSEN;
2052                 break;
2053 #ifdef CONFIG_IXGBE_DCB
2054         case (IXGBE_FLAG_DCB_ENABLED):
2055                 mrqc = IXGBE_MRQC_RT8TCEN;
2056                 break;
2057 #endif /* CONFIG_IXGBE_DCB */
2058         default:
2059                 break;
2060         }
2061
2062         return mrqc;
2063 }
2064
2065 /**
2066  * ixgbe_configure_rscctl - enable RSC for the indicated ring
2067  * @adapter:    address of board private structure
2068  * @index:      index of ring to set
2069  **/
2070 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter, int index)
2071 {
2072         struct ixgbe_ring *rx_ring;
2073         struct ixgbe_hw *hw = &adapter->hw;
2074         int j;
2075         u32 rscctrl;
2076         int rx_buf_len;
2077
2078         rx_ring = &adapter->rx_ring[index];
2079         j = rx_ring->reg_idx;
2080         rx_buf_len = rx_ring->rx_buf_len;
2081         rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(j));
2082         rscctrl |= IXGBE_RSCCTL_RSCEN;
2083         /*
2084          * we must limit the number of descriptors so that the
2085          * total size of max desc * buf_len is not greater
2086          * than 65535
2087          */
2088         if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
2089 #if (MAX_SKB_FRAGS > 16)
2090                 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2091 #elif (MAX_SKB_FRAGS > 8)
2092                 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2093 #elif (MAX_SKB_FRAGS > 4)
2094                 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2095 #else
2096                 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2097 #endif
2098         } else {
2099                 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2100                         rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2101                 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2102                         rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2103                 else
2104                         rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2105         }
2106         IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(j), rscctrl);
2107 }
2108
2109 /**
2110  * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
2111  * @adapter: board private structure
2112  *
2113  * Configure the Rx unit of the MAC after a reset.
2114  **/
2115 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
2116 {
2117         u64 rdba;
2118         struct ixgbe_hw *hw = &adapter->hw;
2119         struct ixgbe_ring *rx_ring;
2120         struct net_device *netdev = adapter->netdev;
2121         int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2122         int i, j;
2123         u32 rdlen, rxctrl, rxcsum;
2124         static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2125                           0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2126                           0x6A3E67EA, 0x14364D17, 0x3BED200D};
2127         u32 fctrl, hlreg0;
2128         u32 reta = 0, mrqc = 0;
2129         u32 rdrxctl;
2130         int rx_buf_len;
2131
2132         /* Decide whether to use packet split mode or not */
2133         adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
2134
2135         /* Set the RX buffer length according to the mode */
2136         if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
2137                 rx_buf_len = IXGBE_RX_HDR_SIZE;
2138                 if (hw->mac.type == ixgbe_mac_82599EB) {
2139                         /* PSRTYPE must be initialized in 82599 */
2140                         u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
2141                                       IXGBE_PSRTYPE_UDPHDR |
2142                                       IXGBE_PSRTYPE_IPV4HDR |
2143                                       IXGBE_PSRTYPE_IPV6HDR |
2144                                       IXGBE_PSRTYPE_L2HDR;
2145                         IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(0), psrtype);
2146                 }
2147         } else {
2148                 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
2149                     (netdev->mtu <= ETH_DATA_LEN))
2150                         rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
2151                 else
2152                         rx_buf_len = ALIGN(max_frame, 1024);
2153         }
2154
2155         fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
2156         fctrl |= IXGBE_FCTRL_BAM;
2157         fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
2158         fctrl |= IXGBE_FCTRL_PMCF;
2159         IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, fctrl);
2160
2161         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2162         if (adapter->netdev->mtu <= ETH_DATA_LEN)
2163                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
2164         else
2165                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2166 #ifdef IXGBE_FCOE
2167         if (netdev->features & NETIF_F_FCOE_MTU)
2168                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2169 #endif
2170         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2171
2172         rdlen = adapter->rx_ring[0].count * sizeof(union ixgbe_adv_rx_desc);
2173         /* disable receives while setting up the descriptors */
2174         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2175         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
2176
2177         /*
2178          * Setup the HW Rx Head and Tail Descriptor Pointers and
2179          * the Base and Length of the Rx Descriptor Ring
2180          */
2181         for (i = 0; i < adapter->num_rx_queues; i++) {
2182                 rx_ring = &adapter->rx_ring[i];
2183                 rdba = rx_ring->dma;
2184                 j = rx_ring->reg_idx;
2185                 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j), (rdba & DMA_BIT_MASK(32)));
2186                 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32));
2187                 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j), rdlen);
2188                 IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0);
2189                 IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0);
2190                 rx_ring->head = IXGBE_RDH(j);
2191                 rx_ring->tail = IXGBE_RDT(j);
2192                 rx_ring->rx_buf_len = rx_buf_len;
2193
2194                 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
2195                         rx_ring->flags |= IXGBE_RING_RX_PS_ENABLED;
2196                 else
2197                         rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
2198
2199 #ifdef IXGBE_FCOE
2200                 if (netdev->features & NETIF_F_FCOE_MTU) {
2201                         struct ixgbe_ring_feature *f;
2202                         f = &adapter->ring_feature[RING_F_FCOE];
2203                         if ((i >= f->mask) && (i < f->mask + f->indices)) {
2204                                 rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
2205                                 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
2206                                         rx_ring->rx_buf_len =
2207                                                 IXGBE_FCOE_JUMBO_FRAME_SIZE;
2208                         }
2209                 }
2210
2211 #endif /* IXGBE_FCOE */
2212                 ixgbe_configure_srrctl(adapter, rx_ring);
2213         }
2214
2215         if (hw->mac.type == ixgbe_mac_82598EB) {
2216                 /*
2217                  * For VMDq support of different descriptor types or
2218                  * buffer sizes through the use of multiple SRRCTL
2219                  * registers, RDRXCTL.MVMEN must be set to 1
2220                  *
2221                  * also, the manual doesn't mention it clearly but DCA hints
2222                  * will only use queue 0's tags unless this bit is set.  Side
2223                  * effects of setting this bit are only that SRRCTL must be
2224                  * fully programmed [0..15]
2225                  */
2226                 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2227                 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
2228                 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2229         }
2230
2231         /* Program MRQC for the distribution of queues */
2232         mrqc = ixgbe_setup_mrqc(adapter);
2233
2234         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
2235                 /* Fill out redirection table */
2236                 for (i = 0, j = 0; i < 128; i++, j++) {
2237                         if (j == adapter->ring_feature[RING_F_RSS].indices)
2238                                 j = 0;
2239                         /* reta = 4-byte sliding window of
2240                          * 0x00..(indices-1)(indices-1)00..etc. */
2241                         reta = (reta << 8) | (j * 0x11);
2242                         if ((i & 3) == 3)
2243                                 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2244                 }
2245
2246                 /* Fill out hash function seeds */
2247                 for (i = 0; i < 10; i++)
2248                         IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2249
2250                 if (hw->mac.type == ixgbe_mac_82598EB)
2251                         mrqc |= IXGBE_MRQC_RSSEN;
2252                     /* Perform hash on these packet types */
2253                 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2254                       | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2255                       | IXGBE_MRQC_RSS_FIELD_IPV4_UDP
2256                       | IXGBE_MRQC_RSS_FIELD_IPV6
2257                       | IXGBE_MRQC_RSS_FIELD_IPV6_TCP
2258                       | IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
2259         }
2260         IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2261
2262         rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2263
2264         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED ||
2265             adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED) {
2266                 /* Disable indicating checksum in descriptor, enables
2267                  * RSS hash */
2268                 rxcsum |= IXGBE_RXCSUM_PCSD;
2269         }
2270         if (!(rxcsum & IXGBE_RXCSUM_PCSD)) {
2271                 /* Enable IPv4 payload checksum for UDP fragments
2272                  * if PCSD is not set */
2273                 rxcsum |= IXGBE_RXCSUM_IPPCSE;
2274         }
2275
2276         IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2277
2278         if (hw->mac.type == ixgbe_mac_82599EB) {
2279                 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2280                 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
2281                 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
2282                 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2283         }
2284
2285         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
2286                 /* Enable 82599 HW-RSC */
2287                 for (i = 0; i < adapter->num_rx_queues; i++)
2288                         ixgbe_configure_rscctl(adapter, i);
2289
2290                 /* Disable RSC for ACK packets */
2291                 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
2292                    (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
2293         }
2294 }
2295
2296 static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
2297 {
2298         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2299         struct ixgbe_hw *hw = &adapter->hw;
2300
2301         /* add VID to filter table */
2302         hw->mac.ops.set_vfta(&adapter->hw, vid, 0, true);
2303 }
2304
2305 static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
2306 {
2307         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2308         struct ixgbe_hw *hw = &adapter->hw;
2309
2310         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2311                 ixgbe_irq_disable(adapter);
2312
2313         vlan_group_set_device(adapter->vlgrp, vid, NULL);
2314
2315         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2316                 ixgbe_irq_enable(adapter);
2317
2318         /* remove VID from filter table */
2319         hw->mac.ops.set_vfta(&adapter->hw, vid, 0, false);
2320 }
2321
2322 static void ixgbe_vlan_rx_register(struct net_device *netdev,
2323                                    struct vlan_group *grp)
2324 {
2325         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2326         u32 ctrl;
2327         int i, j;
2328
2329         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2330                 ixgbe_irq_disable(adapter);
2331         adapter->vlgrp = grp;
2332
2333         /*
2334          * For a DCB driver, always enable VLAN tag stripping so we can
2335          * still receive traffic from a DCB-enabled host even if we're
2336          * not in DCB mode.
2337          */
2338         ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
2339
2340         /* Disable CFI check */
2341         ctrl &= ~IXGBE_VLNCTRL_CFIEN;
2342
2343         /* enable VLAN tag stripping */
2344         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2345                 ctrl |= IXGBE_VLNCTRL_VME;
2346         } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2347                 for (i = 0; i < adapter->num_rx_queues; i++) {
2348                         u32 ctrl;
2349                         j = adapter->rx_ring[i].reg_idx;
2350                         ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXDCTL(j));
2351                         ctrl |= IXGBE_RXDCTL_VME;
2352                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXDCTL(j), ctrl);
2353                 }
2354         }
2355
2356         IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
2357
2358         ixgbe_vlan_rx_add_vid(netdev, 0);
2359
2360         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2361                 ixgbe_irq_enable(adapter);
2362 }
2363
2364 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
2365 {
2366         ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp);
2367
2368         if (adapter->vlgrp) {
2369                 u16 vid;
2370                 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
2371                         if (!vlan_group_get_device(adapter->vlgrp, vid))
2372                                 continue;
2373                         ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
2374                 }
2375         }
2376 }
2377
2378 static u8 *ixgbe_addr_list_itr(struct ixgbe_hw *hw, u8 **mc_addr_ptr, u32 *vmdq)
2379 {
2380         struct dev_mc_list *mc_ptr;
2381         u8 *addr = *mc_addr_ptr;
2382         *vmdq = 0;
2383
2384         mc_ptr = container_of(addr, struct dev_mc_list, dmi_addr[0]);
2385         if (mc_ptr->next)
2386                 *mc_addr_ptr = mc_ptr->next->dmi_addr;
2387         else
2388                 *mc_addr_ptr = NULL;
2389
2390         return addr;
2391 }
2392
2393 /**
2394  * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
2395  * @netdev: network interface device structure
2396  *
2397  * The set_rx_method entry point is called whenever the unicast/multicast
2398  * address list or the network interface flags are updated.  This routine is
2399  * responsible for configuring the hardware for proper unicast, multicast and
2400  * promiscuous mode.
2401  **/
2402 static void ixgbe_set_rx_mode(struct net_device *netdev)
2403 {
2404         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2405         struct ixgbe_hw *hw = &adapter->hw;
2406         u32 fctrl, vlnctrl;
2407         u8 *addr_list = NULL;
2408         int addr_count = 0;
2409
2410         /* Check for Promiscuous and All Multicast modes */
2411
2412         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2413         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2414
2415         if (netdev->flags & IFF_PROMISC) {
2416                 hw->addr_ctrl.user_set_promisc = 1;
2417                 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2418                 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
2419         } else {
2420                 if (netdev->flags & IFF_ALLMULTI) {
2421                         fctrl |= IXGBE_FCTRL_MPE;
2422                         fctrl &= ~IXGBE_FCTRL_UPE;
2423                 } else {
2424                         fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2425                 }
2426                 vlnctrl |= IXGBE_VLNCTRL_VFE;
2427                 hw->addr_ctrl.user_set_promisc = 0;
2428         }
2429
2430         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2431         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2432
2433         /* reprogram secondary unicast list */
2434         hw->mac.ops.update_uc_addr_list(hw, &netdev->uc.list);
2435
2436         /* reprogram multicast list */
2437         addr_count = netdev->mc_count;
2438         if (addr_count)
2439                 addr_list = netdev->mc_list->dmi_addr;
2440         hw->mac.ops.update_mc_addr_list(hw, addr_list, addr_count,
2441                                         ixgbe_addr_list_itr);
2442 }
2443
2444 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
2445 {
2446         int q_idx;
2447         struct ixgbe_q_vector *q_vector;
2448         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2449
2450         /* legacy and MSI only use one vector */
2451         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2452                 q_vectors = 1;
2453
2454         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
2455                 struct napi_struct *napi;
2456                 q_vector = adapter->q_vector[q_idx];
2457                 napi = &q_vector->napi;
2458                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2459                         if (!q_vector->rxr_count || !q_vector->txr_count) {
2460                                 if (q_vector->txr_count == 1)
2461                                         napi->poll = &ixgbe_clean_txonly;
2462                                 else if (q_vector->rxr_count == 1)
2463                                         napi->poll = &ixgbe_clean_rxonly;
2464                         }
2465                 }
2466
2467                 napi_enable(napi);
2468         }
2469 }
2470
2471 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
2472 {
2473         int q_idx;
2474         struct ixgbe_q_vector *q_vector;
2475         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2476
2477         /* legacy and MSI only use one vector */
2478         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2479                 q_vectors = 1;
2480
2481         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
2482                 q_vector = adapter->q_vector[q_idx];
2483                 napi_disable(&q_vector->napi);
2484         }
2485 }
2486
2487 #ifdef CONFIG_IXGBE_DCB
2488 /*
2489  * ixgbe_configure_dcb - Configure DCB hardware
2490  * @adapter: ixgbe adapter struct
2491  *
2492  * This is called by the driver on open to configure the DCB hardware.
2493  * This is also called by the gennetlink interface when reconfiguring
2494  * the DCB state.
2495  */
2496 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
2497 {
2498         struct ixgbe_hw *hw = &adapter->hw;
2499         u32 txdctl, vlnctrl;
2500         int i, j;
2501
2502         ixgbe_dcb_check_config(&adapter->dcb_cfg);
2503         ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_TX_CONFIG);
2504         ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_RX_CONFIG);
2505
2506         /* reconfigure the hardware */
2507         ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg);
2508
2509         for (i = 0; i < adapter->num_tx_queues; i++) {
2510                 j = adapter->tx_ring[i].reg_idx;
2511                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2512                 /* PThresh workaround for Tx hang with DFP enabled. */
2513                 txdctl |= 32;
2514                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2515         }
2516         /* Enable VLAN tag insert/strip */
2517         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2518         if (hw->mac.type == ixgbe_mac_82598EB) {
2519                 vlnctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2520                 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2521                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2522         } else if (hw->mac.type == ixgbe_mac_82599EB) {
2523                 vlnctrl |= IXGBE_VLNCTRL_VFE;
2524                 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2525                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2526                 for (i = 0; i < adapter->num_rx_queues; i++) {
2527                         j = adapter->rx_ring[i].reg_idx;
2528                         vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2529                         vlnctrl |= IXGBE_RXDCTL_VME;
2530                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
2531                 }
2532         }
2533         hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
2534 }
2535
2536 #endif
2537 static void ixgbe_configure(struct ixgbe_adapter *adapter)
2538 {
2539         struct net_device *netdev = adapter->netdev;
2540         struct ixgbe_hw *hw = &adapter->hw;
2541         int i;
2542
2543         ixgbe_set_rx_mode(netdev);
2544
2545         ixgbe_restore_vlan(adapter);
2546 #ifdef CONFIG_IXGBE_DCB
2547         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2548                 if (hw->mac.type == ixgbe_mac_82598EB)
2549                         netif_set_gso_max_size(netdev, 32768);
2550                 else
2551                         netif_set_gso_max_size(netdev, 65536);
2552                 ixgbe_configure_dcb(adapter);
2553         } else {
2554                 netif_set_gso_max_size(netdev, 65536);
2555         }
2556 #else
2557         netif_set_gso_max_size(netdev, 65536);
2558 #endif
2559
2560 #ifdef IXGBE_FCOE
2561         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
2562                 ixgbe_configure_fcoe(adapter);
2563
2564 #endif /* IXGBE_FCOE */
2565         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2566                 for (i = 0; i < adapter->num_tx_queues; i++)
2567                         adapter->tx_ring[i].atr_sample_rate =
2568                                                        adapter->atr_sample_rate;
2569                 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
2570         } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
2571                 ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc);
2572         }
2573
2574         ixgbe_configure_tx(adapter);
2575         ixgbe_configure_rx(adapter);
2576         for (i = 0; i < adapter->num_rx_queues; i++)
2577                 ixgbe_alloc_rx_buffers(adapter, &adapter->rx_ring[i],
2578                                        (adapter->rx_ring[i].count - 1));
2579 }
2580
2581 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
2582 {
2583         switch (hw->phy.type) {
2584         case ixgbe_phy_sfp_avago:
2585         case ixgbe_phy_sfp_ftl:
2586         case ixgbe_phy_sfp_intel:
2587         case ixgbe_phy_sfp_unknown:
2588         case ixgbe_phy_tw_tyco:
2589         case ixgbe_phy_tw_unknown:
2590                 return true;
2591         default:
2592                 return false;
2593         }
2594 }
2595
2596 /**
2597  * ixgbe_sfp_link_config - set up SFP+ link
2598  * @adapter: pointer to private adapter struct
2599  **/
2600 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
2601 {
2602         struct ixgbe_hw *hw = &adapter->hw;
2603
2604                 if (hw->phy.multispeed_fiber) {
2605                         /*
2606                          * In multispeed fiber setups, the device may not have
2607                          * had a physical connection when the driver loaded.
2608                          * If that's the case, the initial link configuration
2609                          * couldn't get the MAC into 10G or 1G mode, so we'll
2610                          * never have a link status change interrupt fire.
2611                          * We need to try and force an autonegotiation
2612                          * session, then bring up link.
2613                          */
2614                         hw->mac.ops.setup_sfp(hw);
2615                         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
2616                                 schedule_work(&adapter->multispeed_fiber_task);
2617                 } else {
2618                         /*
2619                          * Direct Attach Cu and non-multispeed fiber modules
2620                          * still need to be configured properly prior to
2621                          * attempting link.
2622                          */
2623                         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
2624                                 schedule_work(&adapter->sfp_config_module_task);
2625                 }
2626 }
2627
2628 /**
2629  * ixgbe_non_sfp_link_config - set up non-SFP+ link
2630  * @hw: pointer to private hardware struct
2631  *
2632  * Returns 0 on success, negative on failure
2633  **/
2634 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
2635 {
2636         u32 autoneg;
2637         bool negotiation, link_up = false;
2638         u32 ret = IXGBE_ERR_LINK_SETUP;
2639
2640         if (hw->mac.ops.check_link)
2641                 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
2642
2643         if (ret)
2644                 goto link_cfg_out;
2645
2646         if (hw->mac.ops.get_link_capabilities)
2647                 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
2648         if (ret)
2649                 goto link_cfg_out;
2650
2651         if (hw->mac.ops.setup_link)
2652                 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
2653 link_cfg_out:
2654         return ret;
2655 }
2656
2657 #define IXGBE_MAX_RX_DESC_POLL 10
2658 static inline void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2659                                               int rxr)
2660 {
2661         int j = adapter->rx_ring[rxr].reg_idx;
2662         int k;
2663
2664         for (k = 0; k < IXGBE_MAX_RX_DESC_POLL; k++) {
2665                 if (IXGBE_READ_REG(&adapter->hw,
2666                                    IXGBE_RXDCTL(j)) & IXGBE_RXDCTL_ENABLE)
2667                         break;
2668                 else
2669                         msleep(1);
2670         }
2671         if (k >= IXGBE_MAX_RX_DESC_POLL) {
2672                 DPRINTK(DRV, ERR, "RXDCTL.ENABLE on Rx queue %d "
2673                         "not set within the polling period\n", rxr);
2674         }
2675         ixgbe_release_rx_desc(&adapter->hw, &adapter->rx_ring[rxr],
2676                               (adapter->rx_ring[rxr].count - 1));
2677 }
2678
2679 static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
2680 {
2681         struct net_device *netdev = adapter->netdev;
2682         struct ixgbe_hw *hw = &adapter->hw;
2683         int i, j = 0;
2684         int num_rx_rings = adapter->num_rx_queues;
2685         int err;
2686         int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2687         u32 txdctl, rxdctl, mhadd;
2688         u32 dmatxctl;
2689         u32 gpie;
2690
2691         ixgbe_get_hw_control(adapter);
2692
2693         if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) ||
2694             (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) {
2695                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2696                         gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME |
2697                                 IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD);
2698                 } else {
2699                         /* MSI only */
2700                         gpie = 0;
2701                 }
2702                 /* XXX: to interrupt immediately for EICS writes, enable this */
2703                 /* gpie |= IXGBE_GPIE_EIMEN; */
2704                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2705         }
2706
2707         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2708                 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
2709                  * specifically only auto mask tx and rx interrupts */
2710                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
2711         }
2712
2713         /* Enable fan failure interrupt if media type is copper */
2714         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2715                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2716                 gpie |= IXGBE_SDP1_GPIEN;
2717                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2718         }
2719
2720         if (hw->mac.type == ixgbe_mac_82599EB) {
2721                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2722                 gpie |= IXGBE_SDP1_GPIEN;
2723                 gpie |= IXGBE_SDP2_GPIEN;
2724                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2725         }
2726
2727 #ifdef IXGBE_FCOE
2728         /* adjust max frame to be able to do baby jumbo for FCoE */
2729         if ((netdev->features & NETIF_F_FCOE_MTU) &&
2730             (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
2731                 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
2732
2733 #endif /* IXGBE_FCOE */
2734         mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
2735         if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
2736                 mhadd &= ~IXGBE_MHADD_MFS_MASK;
2737                 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
2738
2739                 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
2740         }
2741
2742         for (i = 0; i < adapter->num_tx_queues; i++) {
2743                 j = adapter->tx_ring[i].reg_idx;
2744                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2745                 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2746                 txdctl |= (8 << 16);
2747                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2748         }
2749
2750         if (hw->mac.type == ixgbe_mac_82599EB) {
2751                 /* DMATXCTL.EN must be set after all Tx queue config is done */
2752                 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2753                 dmatxctl |= IXGBE_DMATXCTL_TE;
2754                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2755         }
2756         for (i = 0; i < adapter->num_tx_queues; i++) {
2757                 j = adapter->tx_ring[i].reg_idx;
2758                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2759                 txdctl |= IXGBE_TXDCTL_ENABLE;
2760                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2761         }
2762
2763         for (i = 0; i < num_rx_rings; i++) {
2764                 j = adapter->rx_ring[i].reg_idx;
2765                 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2766                 /* enable PTHRESH=32 descriptors (half the internal cache)
2767                  * and HTHRESH=0 descriptors (to minimize latency on fetch),
2768                  * this also removes a pesky rx_no_buffer_count increment */
2769                 rxdctl |= 0x0020;
2770                 rxdctl |= IXGBE_RXDCTL_ENABLE;
2771                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl);
2772                 if (hw->mac.type == ixgbe_mac_82599EB)
2773                         ixgbe_rx_desc_queue_enable(adapter, i);
2774         }
2775         /* enable all receives */
2776         rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2777         if (hw->mac.type == ixgbe_mac_82598EB)
2778                 rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN);
2779         else
2780                 rxdctl |= IXGBE_RXCTRL_RXEN;
2781         hw->mac.ops.enable_rx_dma(hw, rxdctl);
2782
2783         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2784                 ixgbe_configure_msix(adapter);
2785         else
2786                 ixgbe_configure_msi_and_legacy(adapter);
2787
2788         clear_bit(__IXGBE_DOWN, &adapter->state);
2789         ixgbe_napi_enable_all(adapter);
2790
2791         /* clear any pending interrupts, may auto mask */
2792         IXGBE_READ_REG(hw, IXGBE_EICR);
2793
2794         ixgbe_irq_enable(adapter);
2795
2796         /*
2797          * If this adapter has a fan, check to see if we had a failure
2798          * before we enabled the interrupt.
2799          */
2800         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2801                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2802                 if (esdp & IXGBE_ESDP_SDP1)
2803                         DPRINTK(DRV, CRIT,
2804                                 "Fan has stopped, replace the adapter\n");
2805         }
2806
2807         /*
2808          * For hot-pluggable SFP+ devices, a new SFP+ module may have
2809          * arrived before interrupts were enabled but after probe.  Such
2810          * devices wouldn't have their type identified yet. We need to
2811          * kick off the SFP+ module setup first, then try to bring up link.
2812          * If we're not hot-pluggable SFP+, we just need to configure link
2813          * and bring it up.
2814          */
2815         if (hw->phy.type == ixgbe_phy_unknown) {
2816                 err = hw->phy.ops.identify(hw);
2817                 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
2818                         /*
2819                          * Take the device down and schedule the sfp tasklet
2820                          * which will unregister_netdev and log it.
2821                          */
2822                         ixgbe_down(adapter);
2823                         schedule_work(&adapter->sfp_config_module_task);
2824                         return err;
2825                 }
2826         }
2827
2828         if (ixgbe_is_sfp(hw)) {
2829                 ixgbe_sfp_link_config(adapter);
2830         } else {
2831                 err = ixgbe_non_sfp_link_config(hw);
2832                 if (err)
2833                         DPRINTK(PROBE, ERR, "link_config FAILED %d\n", err);
2834         }
2835
2836         for (i = 0; i < adapter->num_tx_queues; i++)
2837                 set_bit(__IXGBE_FDIR_INIT_DONE,
2838                         &(adapter->tx_ring[i].reinit_state));
2839
2840         /* enable transmits */
2841         netif_tx_start_all_queues(netdev);
2842
2843         /* bring the link up in the watchdog, this could race with our first
2844          * link up interrupt but shouldn't be a problem */
2845         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2846         adapter->link_check_timeout = jiffies;
2847         mod_timer(&adapter->watchdog_timer, jiffies);
2848         return 0;
2849 }
2850
2851 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
2852 {
2853         WARN_ON(in_interrupt());
2854         while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
2855                 msleep(1);
2856         ixgbe_down(adapter);
2857         ixgbe_up(adapter);
2858         clear_bit(__IXGBE_RESETTING, &adapter->state);
2859 }
2860
2861 int ixgbe_up(struct ixgbe_adapter *adapter)
2862 {
2863         /* hardware has been reset, we need to reload some things */
2864         ixgbe_configure(adapter);
2865
2866         return ixgbe_up_complete(adapter);
2867 }
2868
2869 void ixgbe_reset(struct ixgbe_adapter *adapter)
2870 {
2871         struct ixgbe_hw *hw = &adapter->hw;
2872         int err;
2873
2874         err = hw->mac.ops.init_hw(hw);
2875         switch (err) {
2876         case 0:
2877         case IXGBE_ERR_SFP_NOT_PRESENT:
2878                 break;
2879         case IXGBE_ERR_MASTER_REQUESTS_PENDING:
2880                 dev_err(&adapter->pdev->dev, "master disable timed out\n");
2881                 break;
2882         case IXGBE_ERR_EEPROM_VERSION:
2883                 /* We are running on a pre-production device, log a warning */
2884                 dev_warn(&adapter->pdev->dev, "This device is a pre-production "
2885                          "adapter/LOM.  Please be aware there may be issues "
2886                          "associated with your hardware.  If you are "
2887                          "experiencing problems please contact your Intel or "
2888                          "hardware representative who provided you with this "
2889                          "hardware.\n");
2890                 break;
2891         default:
2892                 dev_err(&adapter->pdev->dev, "Hardware Error: %d\n", err);
2893         }
2894
2895         /* reprogram the RAR[0] in case user changed it. */
2896         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2897 }
2898
2899 /**
2900  * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
2901  * @adapter: board private structure
2902  * @rx_ring: ring to free buffers from
2903  **/
2904 static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
2905                                 struct ixgbe_ring *rx_ring)
2906 {
2907         struct pci_dev *pdev = adapter->pdev;
2908         unsigned long size;
2909         unsigned int i;
2910
2911         /* Free all the Rx ring sk_buffs */
2912
2913         for (i = 0; i < rx_ring->count; i++) {
2914                 struct ixgbe_rx_buffer *rx_buffer_info;
2915
2916                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
2917                 if (rx_buffer_info->dma) {
2918                         pci_unmap_single(pdev, rx_buffer_info->dma,
2919                                          rx_ring->rx_buf_len,
2920                                          PCI_DMA_FROMDEVICE);
2921                         rx_buffer_info->dma = 0;
2922                 }
2923                 if (rx_buffer_info->skb) {
2924                         struct sk_buff *skb = rx_buffer_info->skb;
2925                         rx_buffer_info->skb = NULL;
2926                         do {
2927                                 struct sk_buff *this = skb;
2928                                 skb = skb->prev;
2929                                 dev_kfree_skb(this);
2930                         } while (skb);
2931                 }
2932                 if (!rx_buffer_info->page)
2933                         continue;
2934                 if (rx_buffer_info->page_dma) {
2935                         pci_unmap_page(pdev, rx_buffer_info->page_dma,
2936                                        PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
2937                         rx_buffer_info->page_dma = 0;
2938                 }
2939                 put_page(rx_buffer_info->page);
2940                 rx_buffer_info->page = NULL;
2941                 rx_buffer_info->page_offset = 0;
2942         }
2943
2944         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
2945         memset(rx_ring->rx_buffer_info, 0, size);
2946
2947         /* Zero out the descriptor ring */
2948         memset(rx_ring->desc, 0, rx_ring->size);
2949
2950         rx_ring->next_to_clean = 0;
2951         rx_ring->next_to_use = 0;
2952
2953         if (rx_ring->head)
2954                 writel(0, adapter->hw.hw_addr + rx_ring->head);
2955         if (rx_ring->tail)
2956                 writel(0, adapter->hw.hw_addr + rx_ring->tail);
2957 }
2958
2959 /**
2960  * ixgbe_clean_tx_ring - Free Tx Buffers
2961  * @adapter: board private structure
2962  * @tx_ring: ring to be cleaned
2963  **/
2964 static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
2965                                 struct ixgbe_ring *tx_ring)
2966 {
2967         struct ixgbe_tx_buffer *tx_buffer_info;
2968         unsigned long size;
2969         unsigned int i;
2970
2971         /* Free all the Tx ring sk_buffs */
2972
2973         for (i = 0; i < tx_ring->count; i++) {
2974                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
2975                 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
2976         }
2977
2978         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
2979         memset(tx_ring->tx_buffer_info, 0, size);
2980
2981         /* Zero out the descriptor ring */
2982         memset(tx_ring->desc, 0, tx_ring->size);
2983
2984         tx_ring->next_to_use = 0;
2985         tx_ring->next_to_clean = 0;
2986
2987         if (tx_ring->head)
2988                 writel(0, adapter->hw.hw_addr + tx_ring->head);
2989         if (tx_ring->tail)
2990                 writel(0, adapter->hw.hw_addr + tx_ring->tail);
2991 }
2992
2993 /**
2994  * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
2995  * @adapter: board private structure
2996  **/
2997 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
2998 {
2999         int i;
3000
3001         for (i = 0; i < adapter->num_rx_queues; i++)
3002                 ixgbe_clean_rx_ring(adapter, &adapter->rx_ring[i]);
3003 }
3004
3005 /**
3006  * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
3007  * @adapter: board private structure
3008  **/
3009 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
3010 {
3011         int i;
3012
3013         for (i = 0; i < adapter->num_tx_queues; i++)
3014                 ixgbe_clean_tx_ring(adapter, &adapter->tx_ring[i]);
3015 }
3016
3017 void ixgbe_down(struct ixgbe_adapter *adapter)
3018 {
3019         struct net_device *netdev = adapter->netdev;
3020         struct ixgbe_hw *hw = &adapter->hw;
3021         u32 rxctrl;
3022         u32 txdctl;
3023         int i, j;
3024
3025         /* signal that we are down to the interrupt handler */
3026         set_bit(__IXGBE_DOWN, &adapter->state);
3027
3028         /* disable receives */
3029         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3030         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3031
3032         netif_tx_disable(netdev);
3033
3034         IXGBE_WRITE_FLUSH(hw);
3035         msleep(10);
3036
3037         netif_tx_stop_all_queues(netdev);
3038
3039         ixgbe_irq_disable(adapter);
3040
3041         ixgbe_napi_disable_all(adapter);
3042
3043         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
3044         del_timer_sync(&adapter->sfp_timer);
3045         del_timer_sync(&adapter->watchdog_timer);
3046         cancel_work_sync(&adapter->watchdog_task);
3047
3048         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3049             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
3050                 cancel_work_sync(&adapter->fdir_reinit_task);
3051
3052         /* disable transmits in the hardware now that interrupts are off */
3053         for (i = 0; i < adapter->num_tx_queues; i++) {
3054                 j = adapter->tx_ring[i].reg_idx;
3055                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3056                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j),
3057                                 (txdctl & ~IXGBE_TXDCTL_ENABLE));
3058         }
3059         /* Disable the Tx DMA engine on 82599 */
3060         if (hw->mac.type == ixgbe_mac_82599EB)
3061                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
3062                                 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
3063                                  ~IXGBE_DMATXCTL_TE));
3064
3065         netif_carrier_off(netdev);
3066
3067         if (!pci_channel_offline(adapter->pdev))
3068                 ixgbe_reset(adapter);
3069         ixgbe_clean_all_tx_rings(adapter);
3070         ixgbe_clean_all_rx_rings(adapter);
3071
3072 #ifdef CONFIG_IXGBE_DCA
3073         /* since we reset the hardware DCA settings were cleared */
3074         ixgbe_setup_dca(adapter);
3075 #endif
3076 }
3077
3078 /**
3079  * ixgbe_poll - NAPI Rx polling callback
3080  * @napi: structure for representing this polling device
3081  * @budget: how many packets driver is allowed to clean
3082  *
3083  * This function is used for legacy and MSI, NAPI mode
3084  **/
3085 static int ixgbe_poll(struct napi_struct *napi, int budget)
3086 {
3087         struct ixgbe_q_vector *q_vector =
3088                                 container_of(napi, struct ixgbe_q_vector, napi);
3089         struct ixgbe_adapter *adapter = q_vector->adapter;
3090         int tx_clean_complete, work_done = 0;
3091
3092 #ifdef CONFIG_IXGBE_DCA
3093         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
3094                 ixgbe_update_tx_dca(adapter, adapter->tx_ring);
3095                 ixgbe_update_rx_dca(adapter, adapter->rx_ring);
3096         }
3097 #endif
3098
3099         tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring);
3100         ixgbe_clean_rx_irq(q_vector, adapter->rx_ring, &work_done, budget);
3101
3102         if (!tx_clean_complete)
3103                 work_done = budget;
3104
3105         /* If budget not fully consumed, exit the polling mode */
3106         if (work_done < budget) {
3107                 napi_complete(napi);
3108                 if (adapter->rx_itr_setting & 1)
3109                         ixgbe_set_itr(adapter);
3110                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
3111                         ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
3112         }
3113         return work_done;
3114 }
3115
3116 /**
3117  * ixgbe_tx_timeout - Respond to a Tx Hang
3118  * @netdev: network interface device structure
3119  **/
3120 static void ixgbe_tx_timeout(struct net_device *netdev)
3121 {
3122         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3123
3124         /* Do the reset outside of interrupt context */
3125         schedule_work(&adapter->reset_task);
3126 }
3127
3128 static void ixgbe_reset_task(struct work_struct *work)
3129 {
3130         struct ixgbe_adapter *adapter;
3131         adapter = container_of(work, struct ixgbe_adapter, reset_task);
3132
3133         /* If we're already down or resetting, just bail */
3134         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
3135             test_bit(__IXGBE_RESETTING, &adapter->state))
3136                 return;
3137
3138         adapter->tx_timeout_count++;
3139
3140         ixgbe_reinit_locked(adapter);
3141 }
3142
3143 #ifdef CONFIG_IXGBE_DCB
3144 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
3145 {
3146         bool ret = false;
3147         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB];
3148
3149         if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
3150                 return ret;
3151
3152         f->mask = 0x7 << 3;
3153         adapter->num_rx_queues = f->indices;
3154         adapter->num_tx_queues = f->indices;
3155         ret = true;
3156
3157         return ret;
3158 }
3159 #endif
3160
3161 /**
3162  * ixgbe_set_rss_queues: Allocate queues for RSS
3163  * @adapter: board private structure to initialize
3164  *
3165  * This is our "base" multiqueue mode.  RSS (Receive Side Scaling) will try
3166  * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
3167  *
3168  **/
3169 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
3170 {
3171         bool ret = false;
3172         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
3173
3174         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3175                 f->mask = 0xF;
3176                 adapter->num_rx_queues = f->indices;
3177                 adapter->num_tx_queues = f->indices;
3178                 ret = true;
3179         } else {
3180                 ret = false;
3181         }
3182
3183         return ret;
3184 }
3185
3186 /**
3187  * ixgbe_set_fdir_queues: Allocate queues for Flow Director
3188  * @adapter: board private structure to initialize
3189  *
3190  * Flow Director is an advanced Rx filter, attempting to get Rx flows back
3191  * to the original CPU that initiated the Tx session.  This runs in addition
3192  * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
3193  * Rx load across CPUs using RSS.
3194  *
3195  **/
3196 static bool inline ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
3197 {
3198         bool ret = false;
3199         struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
3200
3201         f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
3202         f_fdir->mask = 0;
3203
3204         /* Flow Director must have RSS enabled */
3205         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
3206             ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3207              (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) {
3208                 adapter->num_tx_queues = f_fdir->indices;
3209                 adapter->num_rx_queues = f_fdir->indices;
3210                 ret = true;
3211         } else {
3212                 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
3213                 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
3214         }
3215         return ret;
3216 }
3217
3218 #ifdef IXGBE_FCOE
3219 /**
3220  * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
3221  * @adapter: board private structure to initialize
3222  *
3223  * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
3224  * The ring feature mask is not used as a mask for FCoE, as it can take any 8
3225  * rx queues out of the max number of rx queues, instead, it is used as the
3226  * index of the first rx queue used by FCoE.
3227  *
3228  **/
3229 static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
3230 {
3231         bool ret = false;
3232         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
3233
3234         f->indices = min((int)num_online_cpus(), f->indices);
3235         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
3236                 adapter->num_rx_queues = 1;
3237                 adapter->num_tx_queues = 1;
3238 #ifdef CONFIG_IXGBE_DCB
3239                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3240                         DPRINTK(PROBE, INFO, "FCoE enabled with DCB \n");
3241                         ixgbe_set_dcb_queues(adapter);
3242                 }
3243 #endif
3244                 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3245                         DPRINTK(PROBE, INFO, "FCoE enabled with RSS \n");
3246                         if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3247                             (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
3248                                 ixgbe_set_fdir_queues(adapter);
3249                         else
3250                                 ixgbe_set_rss_queues(adapter);
3251                 }
3252                 /* adding FCoE rx rings to the end */
3253                 f->mask = adapter->num_rx_queues;
3254                 adapter->num_rx_queues += f->indices;
3255                 adapter->num_tx_queues += f->indices;
3256
3257                 ret = true;
3258         }
3259
3260         return ret;
3261 }
3262
3263 #endif /* IXGBE_FCOE */
3264 /*
3265  * ixgbe_set_num_queues: Allocate queues for device, feature dependant
3266  * @adapter: board private structure to initialize
3267  *
3268  * This is the top level queue allocation routine.  The order here is very
3269  * important, starting with the "most" number of features turned on at once,
3270  * and ending with the smallest set of features.  This way large combinations
3271  * can be allocated if they're turned on, and smaller combinations are the
3272  * fallthrough conditions.
3273  *
3274  **/
3275 static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
3276 {
3277 #ifdef IXGBE_FCOE
3278         if (ixgbe_set_fcoe_queues(adapter))
3279                 goto done;
3280
3281 #endif /* IXGBE_FCOE */
3282 #ifdef CONFIG_IXGBE_DCB
3283         if (ixgbe_set_dcb_queues(adapter))
3284                 goto done;
3285
3286 #endif
3287         if (ixgbe_set_fdir_queues(adapter))
3288                 goto done;
3289
3290         if (ixgbe_set_rss_queues(adapter))
3291                 goto done;
3292
3293         /* fallback to base case */
3294         adapter->num_rx_queues = 1;
3295         adapter->num_tx_queues = 1;
3296
3297 done:
3298         /* Notify the stack of the (possibly) reduced Tx Queue count. */
3299         adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
3300 }
3301
3302 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
3303                                        int vectors)
3304 {
3305         int err, vector_threshold;
3306
3307         /* We'll want at least 3 (vector_threshold):
3308          * 1) TxQ[0] Cleanup
3309          * 2) RxQ[0] Cleanup
3310          * 3) Other (Link Status Change, etc.)
3311          * 4) TCP Timer (optional)
3312          */
3313         vector_threshold = MIN_MSIX_COUNT;
3314
3315         /* The more we get, the more we will assign to Tx/Rx Cleanup
3316          * for the separate queues...where Rx Cleanup >= Tx Cleanup.
3317          * Right now, we simply care about how many we'll get; we'll
3318          * set them up later while requesting irq's.
3319          */
3320         while (vectors >= vector_threshold) {
3321                 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
3322                                       vectors);
3323                 if (!err) /* Success in acquiring all requested vectors. */
3324                         break;
3325                 else if (err < 0)
3326                         vectors = 0; /* Nasty failure, quit now */
3327                 else /* err == number of vectors we should try again with */
3328                         vectors = err;
3329         }
3330
3331         if (vectors < vector_threshold) {
3332                 /* Can't allocate enough MSI-X interrupts?  Oh well.
3333                  * This just means we'll go with either a single MSI
3334                  * vector or fall back to legacy interrupts.
3335                  */
3336                 DPRINTK(HW, DEBUG, "Unable to allocate MSI-X interrupts\n");
3337                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
3338                 kfree(adapter->msix_entries);
3339                 adapter->msix_entries = NULL;
3340         } else {
3341                 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
3342                 /*
3343                  * Adjust for only the vectors we'll use, which is minimum
3344                  * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
3345                  * vectors we were allocated.
3346                  */
3347                 adapter->num_msix_vectors = min(vectors,
3348                                    adapter->max_msix_q_vectors + NON_Q_VECTORS);
3349         }
3350 }
3351
3352 /**
3353  * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
3354  * @adapter: board private structure to initialize
3355  *
3356  * Cache the descriptor ring offsets for RSS to the assigned rings.
3357  *
3358  **/
3359 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
3360 {
3361         int i;
3362         bool ret = false;
3363
3364         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3365                 for (i = 0; i < adapter->num_rx_queues; i++)
3366                         adapter->rx_ring[i].reg_idx = i;
3367                 for (i = 0; i < adapter->num_tx_queues; i++)
3368                         adapter->tx_ring[i].reg_idx = i;
3369                 ret = true;
3370         } else {
3371                 ret = false;
3372         }
3373
3374         return ret;
3375 }
3376
3377 #ifdef CONFIG_IXGBE_DCB
3378 /**
3379  * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
3380  * @adapter: board private structure to initialize
3381  *
3382  * Cache the descriptor ring offsets for DCB to the assigned rings.
3383  *
3384  **/
3385 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
3386 {
3387         int i;
3388         bool ret = false;
3389         int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
3390
3391         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3392                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
3393                         /* the number of queues is assumed to be symmetric */
3394                         for (i = 0; i < dcb_i; i++) {
3395                                 adapter->rx_ring[i].reg_idx = i << 3;
3396                                 adapter->tx_ring[i].reg_idx = i << 2;
3397                         }
3398                         ret = true;
3399                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
3400                         if (dcb_i == 8) {
3401                                 /*
3402                                  * Tx TC0 starts at: descriptor queue 0
3403                                  * Tx TC1 starts at: descriptor queue 32
3404                                  * Tx TC2 starts at: descriptor queue 64
3405                                  * Tx TC3 starts at: descriptor queue 80
3406                                  * Tx TC4 starts at: descriptor queue 96
3407                                  * Tx TC5 starts at: descriptor queue 104
3408                                  * Tx TC6 starts at: descriptor queue 112
3409                                  * Tx TC7 starts at: descriptor queue 120
3410                                  *
3411                                  * Rx TC0-TC7 are offset by 16 queues each
3412                                  */
3413                                 for (i = 0; i < 3; i++) {
3414                                         adapter->tx_ring[i].reg_idx = i << 5;
3415                                         adapter->rx_ring[i].reg_idx = i << 4;
3416                                 }
3417                                 for ( ; i < 5; i++) {
3418                                         adapter->tx_ring[i].reg_idx =
3419                                                                  ((i + 2) << 4);
3420                                         adapter->rx_ring[i].reg_idx = i << 4;
3421                                 }
3422                                 for ( ; i < dcb_i; i++) {
3423                                         adapter->tx_ring[i].reg_idx =
3424                                                                  ((i + 8) << 3);
3425                                         adapter->rx_ring[i].reg_idx = i << 4;
3426                                 }
3427
3428                                 ret = true;
3429                         } else if (dcb_i == 4) {
3430                                 /*
3431                                  * Tx TC0 starts at: descriptor queue 0
3432                                  * Tx TC1 starts at: descriptor queue 64
3433                                  * Tx TC2 starts at: descriptor queue 96
3434                                  * Tx TC3 starts at: descriptor queue 112
3435                                  *
3436                                  * Rx TC0-TC3 are offset by 32 queues each
3437                                  */
3438                                 adapter->tx_ring[0].reg_idx = 0;
3439                                 adapter->tx_ring[1].reg_idx = 64;
3440                                 adapter->tx_ring[2].reg_idx = 96;
3441                                 adapter->tx_ring[3].reg_idx = 112;
3442                                 for (i = 0 ; i < dcb_i; i++)
3443                                         adapter->rx_ring[i].reg_idx = i << 5;
3444
3445                                 ret = true;
3446                         } else {
3447                                 ret = false;
3448                         }
3449                 } else {
3450                         ret = false;
3451                 }
3452         } else {
3453                 ret = false;
3454         }
3455
3456         return ret;
3457 }
3458 #endif
3459
3460 /**
3461  * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
3462  * @adapter: board private structure to initialize
3463  *
3464  * Cache the descriptor ring offsets for Flow Director to the assigned rings.
3465  *
3466  **/
3467 static bool inline ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
3468 {
3469         int i;
3470         bool ret = false;
3471
3472         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
3473             ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3474              (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) {
3475                 for (i = 0; i < adapter->num_rx_queues; i++)
3476                         adapter->rx_ring[i].reg_idx = i;
3477                 for (i = 0; i < adapter->num_tx_queues; i++)
3478                         adapter->tx_ring[i].reg_idx = i;
3479                 ret = true;
3480         }
3481
3482         return ret;
3483 }
3484
3485 #ifdef IXGBE_FCOE
3486 /**
3487  * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
3488  * @adapter: board private structure to initialize
3489  *
3490  * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
3491  *
3492  */
3493 static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
3494 {
3495         int i, fcoe_rx_i = 0, fcoe_tx_i = 0;
3496         bool ret = false;
3497         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
3498
3499         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
3500 #ifdef CONFIG_IXGBE_DCB
3501                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3502                         struct ixgbe_fcoe *fcoe = &adapter->fcoe;
3503
3504                         ixgbe_cache_ring_dcb(adapter);
3505                         /* find out queues in TC for FCoE */
3506                         fcoe_rx_i = adapter->rx_ring[fcoe->tc].reg_idx + 1;
3507                         fcoe_tx_i = adapter->tx_ring[fcoe->tc].reg_idx + 1;
3508                         /*
3509                          * In 82599, the number of Tx queues for each traffic
3510                          * class for both 8-TC and 4-TC modes are:
3511                          * TCs  : TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7
3512                          * 8 TCs:  32  32  16  16   8   8   8   8
3513                          * 4 TCs:  64  64  32  32
3514                          * We have max 8 queues for FCoE, where 8 the is
3515                          * FCoE redirection table size. If TC for FCoE is
3516                          * less than or equal to TC3, we have enough queues
3517                          * to add max of 8 queues for FCoE, so we start FCoE
3518                          * tx descriptor from the next one, i.e., reg_idx + 1.
3519                          * If TC for FCoE is above TC3, implying 8 TC mode,
3520                          * and we need 8 for FCoE, we have to take all queues
3521                          * in that traffic class for FCoE.
3522                          */
3523                         if ((f->indices == IXGBE_FCRETA_SIZE) && (fcoe->tc > 3))
3524                                 fcoe_tx_i--;
3525                 }
3526 #endif /* CONFIG_IXGBE_DCB */
3527                 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3528                         if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3529                             (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
3530                                 ixgbe_cache_ring_fdir(adapter);
3531                         else
3532                                 ixgbe_cache_ring_rss(adapter);
3533
3534                         fcoe_rx_i = f->mask;
3535                         fcoe_tx_i = f->mask;
3536                 }
3537                 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
3538                         adapter->rx_ring[f->mask + i].reg_idx = fcoe_rx_i;
3539                         adapter->tx_ring[f->mask + i].reg_idx = fcoe_tx_i;
3540                 }
3541                 ret = true;
3542         }
3543         return ret;
3544 }
3545
3546 #endif /* IXGBE_FCOE */
3547 /**
3548  * ixgbe_cache_ring_register - Descriptor ring to register mapping
3549  * @adapter: board private structure to initialize
3550  *
3551  * Once we know the feature-set enabled for the device, we'll cache
3552  * the register offset the descriptor ring is assigned to.
3553  *
3554  * Note, the order the various feature calls is important.  It must start with
3555  * the "most" features enabled at the same time, then trickle down to the
3556  * least amount of features turned on at once.
3557  **/
3558 static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
3559 {
3560         /* start with default case */
3561         adapter->rx_ring[0].reg_idx = 0;
3562         adapter->tx_ring[0].reg_idx = 0;
3563
3564 #ifdef IXGBE_FCOE
3565         if (ixgbe_cache_ring_fcoe(adapter))
3566                 return;
3567
3568 #endif /* IXGBE_FCOE */
3569 #ifdef CONFIG_IXGBE_DCB
3570         if (ixgbe_cache_ring_dcb(adapter))
3571                 return;
3572
3573 #endif
3574         if (ixgbe_cache_ring_fdir(adapter))
3575                 return;
3576
3577         if (ixgbe_cache_ring_rss(adapter))
3578                 return;
3579 }
3580
3581 /**
3582  * ixgbe_alloc_queues - Allocate memory for all rings
3583  * @adapter: board private structure to initialize
3584  *
3585  * We allocate one ring per queue at run-time since we don't know the
3586  * number of queues at compile-time.  The polling_netdev array is
3587  * intended for Multiqueue, but should work fine with a single queue.
3588  **/
3589 static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
3590 {
3591         int i;
3592
3593         adapter->tx_ring = kcalloc(adapter->num_tx_queues,
3594                                    sizeof(struct ixgbe_ring), GFP_KERNEL);
3595         if (!adapter->tx_ring)
3596                 goto err_tx_ring_allocation;
3597
3598         adapter->rx_ring = kcalloc(adapter->num_rx_queues,
3599                                    sizeof(struct ixgbe_ring), GFP_KERNEL);
3600         if (!adapter->rx_ring)
3601                 goto err_rx_ring_allocation;
3602
3603         for (i = 0; i < adapter->num_tx_queues; i++) {
3604                 adapter->tx_ring[i].count = adapter->tx_ring_count;
3605                 adapter->tx_ring[i].queue_index = i;
3606         }
3607
3608         for (i = 0; i < adapter->num_rx_queues; i++) {
3609                 adapter->rx_ring[i].count = adapter->rx_ring_count;
3610                 adapter->rx_ring[i].queue_index = i;
3611         }
3612
3613         ixgbe_cache_ring_register(adapter);
3614
3615         return 0;
3616
3617 err_rx_ring_allocation:
3618         kfree(adapter->tx_ring);
3619 err_tx_ring_allocation:
3620         return -ENOMEM;
3621 }
3622
3623 /**
3624  * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
3625  * @adapter: board private structure to initialize
3626  *
3627  * Attempt to configure the interrupts using the best available
3628  * capabilities of the hardware and the kernel.
3629  **/
3630 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
3631 {
3632         struct ixgbe_hw *hw = &adapter->hw;
3633         int err = 0;
3634         int vector, v_budget;
3635
3636         /*
3637          * It's easy to be greedy for MSI-X vectors, but it really
3638          * doesn't do us much good if we have a lot more vectors
3639          * than CPU's.  So let's be conservative and only ask for
3640          * (roughly) the same number of vectors as there are CPU's.
3641          */
3642         v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
3643                        (int)num_online_cpus()) + NON_Q_VECTORS;
3644
3645         /*
3646          * At the same time, hardware can only support a maximum of
3647          * hw.mac->max_msix_vectors vectors.  With features
3648          * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
3649          * descriptor queues supported by our device.  Thus, we cap it off in
3650          * those rare cases where the cpu count also exceeds our vector limit.
3651          */
3652         v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
3653
3654         /* A failure in MSI-X entry allocation isn't fatal, but it does
3655          * mean we disable MSI-X capabilities of the adapter. */
3656         adapter->msix_entries = kcalloc(v_budget,
3657                                         sizeof(struct msix_entry), GFP_KERNEL);
3658         if (adapter->msix_entries) {
3659                 for (vector = 0; vector < v_budget; vector++)
3660                         adapter->msix_entries[vector].entry = vector;
3661
3662                 ixgbe_acquire_msix_vectors(adapter, v_budget);
3663
3664                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3665                         goto out;
3666         }
3667
3668         adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
3669         adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
3670         adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
3671         adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
3672         adapter->atr_sample_rate = 0;
3673         ixgbe_set_num_queues(adapter);
3674
3675         err = pci_enable_msi(adapter->pdev);
3676         if (!err) {
3677                 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
3678         } else {
3679                 DPRINTK(HW, DEBUG, "Unable to allocate MSI interrupt, "
3680                         "falling back to legacy.  Error: %d\n", err);
3681                 /* reset err */
3682                 err = 0;
3683         }
3684
3685 out:
3686         return err;
3687 }
3688
3689 /**
3690  * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
3691  * @adapter: board private structure to initialize
3692  *
3693  * We allocate one q_vector per queue interrupt.  If allocation fails we
3694  * return -ENOMEM.
3695  **/
3696 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
3697 {
3698         int q_idx, num_q_vectors;
3699         struct ixgbe_q_vector *q_vector;
3700         int napi_vectors;
3701         int (*poll)(struct napi_struct *, int);
3702
3703         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3704                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3705                 napi_vectors = adapter->num_rx_queues;
3706                 poll = &ixgbe_clean_rxtx_many;
3707         } else {
3708                 num_q_vectors = 1;
3709                 napi_vectors = 1;
3710                 poll = &ixgbe_poll;
3711         }
3712
3713         for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
3714                 q_vector = kzalloc(sizeof(struct ixgbe_q_vector), GFP_KERNEL);
3715                 if (!q_vector)
3716                         goto err_out;
3717                 q_vector->adapter = adapter;
3718                 if (q_vector->txr_count && !q_vector->rxr_count)
3719                         q_vector->eitr = adapter->tx_eitr_param;
3720                 else
3721                         q_vector->eitr = adapter->rx_eitr_param;
3722                 q_vector->v_idx = q_idx;
3723                 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
3724                 adapter->q_vector[q_idx] = q_vector;
3725         }
3726
3727         return 0;
3728
3729 err_out:
3730         while (q_idx) {
3731                 q_idx--;
3732                 q_vector = adapter->q_vector[q_idx];
3733                 netif_napi_del(&q_vector->napi);
3734                 kfree(q_vector);
3735                 adapter->q_vector[q_idx] = NULL;
3736         }
3737         return -ENOMEM;
3738 }
3739
3740 /**
3741  * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
3742  * @adapter: board private structure to initialize
3743  *
3744  * This function frees the memory allocated to the q_vectors.  In addition if
3745  * NAPI is enabled it will delete any references to the NAPI struct prior
3746  * to freeing the q_vector.
3747  **/
3748 static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
3749 {
3750         int q_idx, num_q_vectors;
3751
3752         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3753                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3754         else
3755                 num_q_vectors = 1;
3756
3757         for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
3758                 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
3759                 adapter->q_vector[q_idx] = NULL;
3760                 netif_napi_del(&q_vector->napi);
3761                 kfree(q_vector);
3762         }
3763 }
3764
3765 static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
3766 {
3767         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3768                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
3769                 pci_disable_msix(adapter->pdev);
3770                 kfree(adapter->msix_entries);
3771                 adapter->msix_entries = NULL;
3772         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
3773                 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
3774                 pci_disable_msi(adapter->pdev);
3775         }
3776         return;
3777 }
3778
3779 /**
3780  * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
3781  * @adapter: board private structure to initialize
3782  *
3783  * We determine which interrupt scheme to use based on...
3784  * - Kernel support (MSI, MSI-X)
3785  *   - which can be user-defined (via MODULE_PARAM)
3786  * - Hardware queue count (num_*_queues)
3787  *   - defined by miscellaneous hardware support/features (RSS, etc.)
3788  **/
3789 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
3790 {
3791         int err;
3792
3793         /* Number of supported queues */
3794         ixgbe_set_num_queues(adapter);
3795
3796         err = ixgbe_set_interrupt_capability(adapter);
3797         if (err) {
3798                 DPRINTK(PROBE, ERR, "Unable to setup interrupt capabilities\n");
3799                 goto err_set_interrupt;
3800         }
3801
3802         err = ixgbe_alloc_q_vectors(adapter);
3803         if (err) {
3804                 DPRINTK(PROBE, ERR, "Unable to allocate memory for queue "
3805                         "vectors\n");
3806                 goto err_alloc_q_vectors;
3807         }
3808
3809         err = ixgbe_alloc_queues(adapter);
3810         if (err) {
3811                 DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n");
3812                 goto err_alloc_queues;
3813         }
3814
3815         DPRINTK(DRV, INFO, "Multiqueue %s: Rx Queue count = %u, "
3816                 "Tx Queue count = %u\n",
3817                 (adapter->num_rx_queues > 1) ? "Enabled" :
3818                 "Disabled", adapter->num_rx_queues, adapter->num_tx_queues);
3819
3820         set_bit(__IXGBE_DOWN, &adapter->state);
3821
3822         return 0;
3823
3824 err_alloc_queues:
3825         ixgbe_free_q_vectors(adapter);
3826 err_alloc_q_vectors:
3827         ixgbe_reset_interrupt_capability(adapter);
3828 err_set_interrupt:
3829         return err;
3830 }
3831
3832 /**
3833  * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
3834  * @adapter: board private structure to clear interrupt scheme on
3835  *
3836  * We go through and clear interrupt specific resources and reset the structure
3837  * to pre-load conditions
3838  **/
3839 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
3840 {
3841         kfree(adapter->tx_ring);
3842         kfree(adapter->rx_ring);
3843         adapter->tx_ring = NULL;
3844         adapter->rx_ring = NULL;
3845
3846         ixgbe_free_q_vectors(adapter);
3847         ixgbe_reset_interrupt_capability(adapter);
3848 }
3849
3850 /**
3851  * ixgbe_sfp_timer - worker thread to find a missing module
3852  * @data: pointer to our adapter struct
3853  **/
3854 static void ixgbe_sfp_timer(unsigned long data)
3855 {
3856         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
3857
3858         /*
3859          * Do the sfp_timer outside of interrupt context due to the
3860          * delays that sfp+ detection requires
3861          */
3862         schedule_work(&adapter->sfp_task);
3863 }
3864
3865 /**
3866  * ixgbe_sfp_task - worker thread to find a missing module
3867  * @work: pointer to work_struct containing our data
3868  **/
3869 static void ixgbe_sfp_task(struct work_struct *work)
3870 {
3871         struct ixgbe_adapter *adapter = container_of(work,
3872                                                      struct ixgbe_adapter,
3873                                                      sfp_task);
3874         struct ixgbe_hw *hw = &adapter->hw;
3875
3876         if ((hw->phy.type == ixgbe_phy_nl) &&
3877             (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
3878                 s32 ret = hw->phy.ops.identify_sfp(hw);
3879                 if (ret == IXGBE_ERR_SFP_NOT_PRESENT)
3880                         goto reschedule;
3881                 ret = hw->phy.ops.reset(hw);
3882                 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
3883                         dev_err(&adapter->pdev->dev, "failed to initialize "
3884                                 "because an unsupported SFP+ module type "
3885                                 "was detected.\n"
3886                                 "Reload the driver after installing a "
3887                                 "supported module.\n");
3888                         unregister_netdev(adapter->netdev);
3889                 } else {
3890                         DPRINTK(PROBE, INFO, "detected SFP+: %d\n",
3891                                 hw->phy.sfp_type);
3892                 }
3893                 /* don't need this routine any more */
3894                 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
3895         }
3896         return;
3897 reschedule:
3898         if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
3899                 mod_timer(&adapter->sfp_timer,
3900                           round_jiffies(jiffies + (2 * HZ)));
3901 }
3902
3903 /**
3904  * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
3905  * @adapter: board private structure to initialize
3906  *
3907  * ixgbe_sw_init initializes the Adapter private data structure.
3908  * Fields are initialized based on PCI device information and
3909  * OS network device settings (MTU size).
3910  **/
3911 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
3912 {
3913         struct ixgbe_hw *hw = &adapter->hw;
3914         struct pci_dev *pdev = adapter->pdev;
3915         unsigned int rss;
3916 #ifdef CONFIG_IXGBE_DCB
3917         int j;
3918         struct tc_configuration *tc;
3919 #endif
3920
3921         /* PCI config space info */
3922
3923         hw->vendor_id = pdev->vendor;
3924         hw->device_id = pdev->device;
3925         hw->revision_id = pdev->revision;
3926         hw->subsystem_vendor_id = pdev->subsystem_vendor;
3927         hw->subsystem_device_id = pdev->subsystem_device;
3928
3929         /* Set capability flags */
3930         rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
3931         adapter->ring_feature[RING_F_RSS].indices = rss;
3932         adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
3933         adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
3934         if (hw->mac.type == ixgbe_mac_82598EB) {
3935                 if (hw->device_id == IXGBE_DEV_ID_82598AT)
3936                         adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
3937                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
3938         } else if (hw->mac.type == ixgbe_mac_82599EB) {
3939                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
3940                 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
3941                 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
3942                 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
3943                 adapter->ring_feature[RING_F_FDIR].indices =
3944                                                          IXGBE_MAX_FDIR_INDICES;
3945                 adapter->atr_sample_rate = 20;
3946                 adapter->fdir_pballoc = 0;
3947 #ifdef IXGBE_FCOE
3948                 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
3949                 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
3950                 adapter->ring_feature[RING_F_FCOE].indices = 0;
3951                 /* Default traffic class to use for FCoE */
3952                 adapter->fcoe.tc = IXGBE_FCOE_DEFTC;
3953 #endif /* IXGBE_FCOE */
3954         }
3955
3956 #ifdef CONFIG_IXGBE_DCB
3957         /* Configure DCB traffic classes */
3958         for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
3959                 tc = &adapter->dcb_cfg.tc_config[j];
3960                 tc->path[DCB_TX_CONFIG].bwg_id = 0;
3961                 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
3962                 tc->path[DCB_RX_CONFIG].bwg_id = 0;
3963                 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
3964                 tc->dcb_pfc = pfc_disabled;
3965         }
3966         adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
3967         adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
3968         adapter->dcb_cfg.rx_pba_cfg = pba_equal;
3969         adapter->dcb_cfg.pfc_mode_enable = false;
3970         adapter->dcb_cfg.round_robin_enable = false;
3971         adapter->dcb_set_bitmap = 0x00;
3972         ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
3973                            adapter->ring_feature[RING_F_DCB].indices);
3974
3975 #endif
3976
3977         /* default flow control settings */
3978         hw->fc.requested_mode = ixgbe_fc_full;
3979         hw->fc.current_mode = ixgbe_fc_full;    /* init for ethtool output */
3980 #ifdef CONFIG_DCB
3981         adapter->last_lfc_mode = hw->fc.current_mode;
3982 #endif
3983         hw->fc.high_water = IXGBE_DEFAULT_FCRTH;
3984         hw->fc.low_water = IXGBE_DEFAULT_FCRTL;
3985         hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
3986         hw->fc.send_xon = true;
3987         hw->fc.disable_fc_autoneg = false;
3988
3989         /* enable itr by default in dynamic mode */
3990         adapter->rx_itr_setting = 1;
3991         adapter->rx_eitr_param = 20000;
3992         adapter->tx_itr_setting = 1;
3993         adapter->tx_eitr_param = 10000;
3994
3995         /* set defaults for eitr in MegaBytes */
3996         adapter->eitr_low = 10;
3997         adapter->eitr_high = 20;
3998
3999         /* set default ring sizes */
4000         adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
4001         adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
4002
4003         /* initialize eeprom parameters */
4004         if (ixgbe_init_eeprom_params_generic(hw)) {
4005                 dev_err(&pdev->dev, "EEPROM initialization failed\n");
4006                 return -EIO;
4007         }
4008
4009         /* enable rx csum by default */
4010         adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
4011
4012         set_bit(__IXGBE_DOWN, &adapter->state);
4013
4014         return 0;
4015 }
4016
4017 /**
4018  * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
4019  * @adapter: board private structure
4020  * @tx_ring:    tx descriptor ring (for a specific queue) to setup
4021  *
4022  * Return 0 on success, negative on failure
4023  **/
4024 int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
4025                              struct ixgbe_ring *tx_ring)
4026 {
4027         struct pci_dev *pdev = adapter->pdev;
4028         int size;
4029
4030         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4031         tx_ring->tx_buffer_info = vmalloc(size);
4032         if (!tx_ring->tx_buffer_info)
4033                 goto err;
4034         memset(tx_ring->tx_buffer_info, 0, size);
4035
4036         /* round up to nearest 4K */
4037         tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
4038         tx_ring->size = ALIGN(tx_ring->size, 4096);
4039
4040         tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
4041                                              &tx_ring->dma);
4042         if (!tx_ring->desc)
4043                 goto err;
4044
4045         tx_ring->next_to_use = 0;
4046         tx_ring->next_to_clean = 0;
4047         tx_ring->work_limit = tx_ring->count;
4048         return 0;
4049
4050 err:
4051         vfree(tx_ring->tx_buffer_info);
4052         tx_ring->tx_buffer_info = NULL;
4053         DPRINTK(PROBE, ERR, "Unable to allocate memory for the transmit "
4054                             "descriptor ring\n");
4055         return -ENOMEM;
4056 }
4057
4058 /**
4059  * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
4060  * @adapter: board private structure
4061  *
4062  * If this function returns with an error, then it's possible one or
4063  * more of the rings is populated (while the rest are not).  It is the
4064  * callers duty to clean those orphaned rings.
4065  *
4066  * Return 0 on success, negative on failure
4067  **/
4068 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
4069 {
4070         int i, err = 0;
4071
4072         for (i = 0; i < adapter->num_tx_queues; i++) {
4073                 err = ixgbe_setup_tx_resources(adapter, &adapter->tx_ring[i]);
4074                 if (!err)
4075                         continue;
4076                 DPRINTK(PROBE, ERR, "Allocation for Tx Queue %u failed\n", i);
4077                 break;
4078         }
4079
4080         return err;
4081 }
4082
4083 /**
4084  * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
4085  * @adapter: board private structure
4086  * @rx_ring:    rx descriptor ring (for a specific queue) to setup
4087  *
4088  * Returns 0 on success, negative on failure
4089  **/
4090 int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
4091                              struct ixgbe_ring *rx_ring)
4092 {
4093         struct pci_dev *pdev = adapter->pdev;
4094         int size;
4095
4096         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4097         rx_ring->rx_buffer_info = vmalloc(size);
4098         if (!rx_ring->rx_buffer_info) {
4099                 DPRINTK(PROBE, ERR,
4100                         "vmalloc allocation failed for the rx desc ring\n");
4101                 goto alloc_failed;
4102         }
4103         memset(rx_ring->rx_buffer_info, 0, size);
4104
4105         /* Round up to nearest 4K */
4106         rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
4107         rx_ring->size = ALIGN(rx_ring->size, 4096);
4108
4109         rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size, &rx_ring->dma);
4110
4111         if (!rx_ring->desc) {
4112                 DPRINTK(PROBE, ERR,
4113                         "Memory allocation failed for the rx desc ring\n");
4114                 vfree(rx_ring->rx_buffer_info);
4115                 goto alloc_failed;
4116         }
4117
4118         rx_ring->next_to_clean = 0;
4119         rx_ring->next_to_use = 0;
4120
4121         return 0;
4122
4123 alloc_failed:
4124         return -ENOMEM;
4125 }
4126
4127 /**
4128  * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
4129  * @adapter: board private structure
4130  *
4131  * If this function returns with an error, then it's possible one or
4132  * more of the rings is populated (while the rest are not).  It is the
4133  * callers duty to clean those orphaned rings.
4134  *
4135  * Return 0 on success, negative on failure
4136  **/
4137
4138 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
4139 {
4140         int i, err = 0;
4141
4142         for (i = 0; i < adapter->num_rx_queues; i++) {
4143                 err = ixgbe_setup_rx_resources(adapter, &adapter->rx_ring[i]);
4144                 if (!err)
4145                         continue;
4146                 DPRINTK(PROBE, ERR, "Allocation for Rx Queue %u failed\n", i);
4147                 break;
4148         }
4149
4150         return err;
4151 }
4152
4153 /**
4154  * ixgbe_free_tx_resources - Free Tx Resources per Queue
4155  * @adapter: board private structure
4156  * @tx_ring: Tx descriptor ring for a specific queue
4157  *
4158  * Free all transmit software resources
4159  **/
4160 void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter,
4161                              struct ixgbe_ring *tx_ring)
4162 {
4163         struct pci_dev *pdev = adapter->pdev;
4164
4165         ixgbe_clean_tx_ring(adapter, tx_ring);
4166
4167         vfree(tx_ring->tx_buffer_info);
4168         tx_ring->tx_buffer_info = NULL;
4169
4170         pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
4171
4172         tx_ring->desc = NULL;
4173 }
4174
4175 /**
4176  * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
4177  * @adapter: board private structure
4178  *
4179  * Free all transmit software resources
4180  **/
4181 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
4182 {
4183         int i;
4184
4185         for (i = 0; i < adapter->num_tx_queues; i++)
4186                 if (adapter->tx_ring[i].desc)
4187                         ixgbe_free_tx_resources(adapter, &adapter->tx_ring[i]);
4188 }
4189
4190 /**
4191  * ixgbe_free_rx_resources - Free Rx Resources
4192  * @adapter: board private structure
4193  * @rx_ring: ring to clean the resources from
4194  *
4195  * Free all receive software resources
4196  **/
4197 void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
4198                              struct ixgbe_ring *rx_ring)
4199 {
4200         struct pci_dev *pdev = adapter->pdev;
4201
4202         ixgbe_clean_rx_ring(adapter, rx_ring);
4203
4204         vfree(rx_ring->rx_buffer_info);
4205         rx_ring->rx_buffer_info = NULL;
4206
4207         pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
4208
4209         rx_ring->desc = NULL;
4210 }
4211
4212 /**
4213  * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
4214  * @adapter: board private structure
4215  *
4216  * Free all receive software resources
4217  **/
4218 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
4219 {
4220         int i;
4221
4222         for (i = 0; i < adapter->num_rx_queues; i++)
4223                 if (adapter->rx_ring[i].desc)
4224                         ixgbe_free_rx_resources(adapter, &adapter->rx_ring[i]);
4225 }
4226
4227 /**
4228  * ixgbe_change_mtu - Change the Maximum Transfer Unit
4229  * @netdev: network interface device structure
4230  * @new_mtu: new value for maximum frame size
4231  *
4232  * Returns 0 on success, negative on failure
4233  **/
4234 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
4235 {
4236         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4237         int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
4238
4239         /* MTU < 68 is an error and causes problems on some kernels */
4240         if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
4241                 return -EINVAL;
4242
4243         DPRINTK(PROBE, INFO, "changing MTU from %d to %d\n",
4244                 netdev->mtu, new_mtu);
4245         /* must set new MTU before calling down or up */
4246         netdev->mtu = new_mtu;
4247
4248         if (netif_running(netdev))
4249                 ixgbe_reinit_locked(adapter);
4250
4251         return 0;
4252 }
4253
4254 /**
4255  * ixgbe_open - Called when a network interface is made active
4256  * @netdev: network interface device structure
4257  *
4258  * Returns 0 on success, negative value on failure
4259  *
4260  * The open entry point is called when a network interface is made
4261  * active by the system (IFF_UP).  At this point all resources needed
4262  * for transmit and receive operations are allocated, the interrupt
4263  * handler is registered with the OS, the watchdog timer is started,
4264  * and the stack is notified that the interface is ready.
4265  **/
4266 static int ixgbe_open(struct net_device *netdev)
4267 {
4268         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4269         int err;
4270
4271         /* disallow open during test */
4272         if (test_bit(__IXGBE_TESTING, &adapter->state))
4273                 return -EBUSY;
4274
4275         netif_carrier_off(netdev);
4276
4277         /* allocate transmit descriptors */
4278         err = ixgbe_setup_all_tx_resources(adapter);
4279         if (err)
4280                 goto err_setup_tx;
4281
4282         /* allocate receive descriptors */
4283         err = ixgbe_setup_all_rx_resources(adapter);
4284         if (err)
4285                 goto err_setup_rx;
4286
4287         ixgbe_configure(adapter);
4288
4289         err = ixgbe_request_irq(adapter);
4290         if (err)
4291                 goto err_req_irq;
4292
4293         err = ixgbe_up_complete(adapter);
4294         if (err)
4295                 goto err_up;
4296
4297         netif_tx_start_all_queues(netdev);
4298
4299         return 0;
4300
4301 err_up:
4302         ixgbe_release_hw_control(adapter);
4303         ixgbe_free_irq(adapter);
4304 err_req_irq:
4305 err_setup_rx:
4306         ixgbe_free_all_rx_resources(adapter);
4307 err_setup_tx:
4308         ixgbe_free_all_tx_resources(adapter);
4309         ixgbe_reset(adapter);
4310
4311         return err;
4312 }
4313
4314 /**
4315  * ixgbe_close - Disables a network interface
4316  * @netdev: network interface device structure
4317  *
4318  * Returns 0, this is not allowed to fail
4319  *
4320  * The close entry point is called when an interface is de-activated
4321  * by the OS.  The hardware is still under the drivers control, but
4322  * needs to be disabled.  A global MAC reset is issued to stop the
4323  * hardware, and all transmit and receive resources are freed.
4324  **/
4325 static int ixgbe_close(struct net_device *netdev)
4326 {
4327         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4328
4329         ixgbe_down(adapter);
4330         ixgbe_free_irq(adapter);
4331
4332         ixgbe_free_all_tx_resources(adapter);
4333         ixgbe_free_all_rx_resources(adapter);
4334
4335         ixgbe_release_hw_control(adapter);
4336
4337         return 0;
4338 }
4339
4340 #ifdef CONFIG_PM
4341 static int ixgbe_resume(struct pci_dev *pdev)
4342 {
4343         struct net_device *netdev = pci_get_drvdata(pdev);
4344         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4345         u32 err;
4346
4347         pci_set_power_state(pdev, PCI_D0);
4348         pci_restore_state(pdev);
4349
4350         err = pci_enable_device_mem(pdev);
4351         if (err) {
4352                 printk(KERN_ERR "ixgbe: Cannot enable PCI device from "
4353                                 "suspend\n");
4354                 return err;
4355         }
4356         pci_set_master(pdev);
4357
4358         pci_wake_from_d3(pdev, false);
4359
4360         err = ixgbe_init_interrupt_scheme(adapter);
4361         if (err) {
4362                 printk(KERN_ERR "ixgbe: Cannot initialize interrupts for "
4363                                 "device\n");
4364                 return err;
4365         }
4366
4367         ixgbe_reset(adapter);
4368
4369         IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
4370
4371         if (netif_running(netdev)) {
4372                 err = ixgbe_open(adapter->netdev);
4373                 if (err)
4374                         return err;
4375         }
4376
4377         netif_device_attach(netdev);
4378
4379         return 0;
4380 }
4381 #endif /* CONFIG_PM */
4382
4383 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
4384 {
4385         struct net_device *netdev = pci_get_drvdata(pdev);
4386         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4387         struct ixgbe_hw *hw = &adapter->hw;
4388         u32 ctrl, fctrl;
4389         u32 wufc = adapter->wol;
4390 #ifdef CONFIG_PM
4391         int retval = 0;
4392 #endif
4393
4394         netif_device_detach(netdev);
4395
4396         if (netif_running(netdev)) {
4397                 ixgbe_down(adapter);
4398                 ixgbe_free_irq(adapter);
4399                 ixgbe_free_all_tx_resources(adapter);
4400                 ixgbe_free_all_rx_resources(adapter);
4401         }
4402         ixgbe_clear_interrupt_scheme(adapter);
4403
4404 #ifdef CONFIG_PM
4405         retval = pci_save_state(pdev);
4406         if (retval)
4407                 return retval;
4408
4409 #endif
4410         if (wufc) {
4411                 ixgbe_set_rx_mode(netdev);
4412
4413                 /* turn on all-multi mode if wake on multicast is enabled */
4414                 if (wufc & IXGBE_WUFC_MC) {
4415                         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4416                         fctrl |= IXGBE_FCTRL_MPE;
4417                         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4418                 }
4419
4420                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
4421                 ctrl |= IXGBE_CTRL_GIO_DIS;
4422                 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
4423
4424                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
4425         } else {
4426                 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
4427                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
4428         }
4429
4430         if (wufc && hw->mac.type == ixgbe_mac_82599EB)
4431                 pci_wake_from_d3(pdev, true);
4432         else
4433                 pci_wake_from_d3(pdev, false);
4434
4435         *enable_wake = !!wufc;
4436
4437         ixgbe_release_hw_control(adapter);
4438
4439         pci_disable_device(pdev);
4440
4441         return 0;
4442 }
4443
4444 #ifdef CONFIG_PM
4445 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
4446 {
4447         int retval;
4448         bool wake;
4449
4450         retval = __ixgbe_shutdown(pdev, &wake);
4451         if (retval)
4452                 return retval;
4453
4454         if (wake) {
4455                 pci_prepare_to_sleep(pdev);
4456         } else {
4457                 pci_wake_from_d3(pdev, false);
4458                 pci_set_power_state(pdev, PCI_D3hot);
4459         }
4460
4461         return 0;
4462 }
4463 #endif /* CONFIG_PM */
4464
4465 static void ixgbe_shutdown(struct pci_dev *pdev)
4466 {
4467         bool wake;
4468
4469         __ixgbe_shutdown(pdev, &wake);
4470
4471         if (system_state == SYSTEM_POWER_OFF) {
4472                 pci_wake_from_d3(pdev, wake);
4473                 pci_set_power_state(pdev, PCI_D3hot);
4474         }
4475 }
4476
4477 /**
4478  * ixgbe_update_stats - Update the board statistics counters.
4479  * @adapter: board private structure
4480  **/
4481 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
4482 {
4483         struct net_device *netdev = adapter->netdev;
4484         struct ixgbe_hw *hw = &adapter->hw;
4485         u64 total_mpc = 0;
4486         u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
4487
4488         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
4489                 u64 rsc_count = 0;
4490                 u64 rsc_flush = 0;
4491                 for (i = 0; i < 16; i++)
4492                         adapter->hw_rx_no_dma_resources +=
4493                                              IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
4494                 for (i = 0; i < adapter->num_rx_queues; i++) {
4495                         rsc_count += adapter->rx_ring[i].rsc_count;
4496                         rsc_flush += adapter->rx_ring[i].rsc_flush;
4497                 }
4498                 adapter->rsc_total_count = rsc_count;
4499                 adapter->rsc_total_flush = rsc_flush;
4500         }
4501
4502         adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
4503         for (i = 0; i < 8; i++) {
4504                 /* for packet buffers not used, the register should read 0 */
4505                 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
4506                 missed_rx += mpc;
4507                 adapter->stats.mpc[i] += mpc;
4508                 total_mpc += adapter->stats.mpc[i];
4509                 if (hw->mac.type == ixgbe_mac_82598EB)
4510                         adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
4511                 adapter->stats.qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
4512                 adapter->stats.qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
4513                 adapter->stats.qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
4514                 adapter->stats.qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
4515                 if (hw->mac.type == ixgbe_mac_82599EB) {
4516                         adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
4517                                                             IXGBE_PXONRXCNT(i));
4518                         adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
4519                                                            IXGBE_PXOFFRXCNT(i));
4520                         adapter->stats.qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
4521                 } else {
4522                         adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
4523                                                               IXGBE_PXONRXC(i));
4524                         adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
4525                                                              IXGBE_PXOFFRXC(i));
4526                 }
4527                 adapter->stats.pxontxc[i] += IXGBE_READ_REG(hw,
4528                                                             IXGBE_PXONTXC(i));
4529                 adapter->stats.pxofftxc[i] += IXGBE_READ_REG(hw,
4530                                                              IXGBE_PXOFFTXC(i));
4531         }
4532         adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
4533         /* work around hardware counting issue */
4534         adapter->stats.gprc -= missed_rx;
4535
4536         /* 82598 hardware only has a 32 bit counter in the high register */
4537         if (hw->mac.type == ixgbe_mac_82599EB) {
4538                 u64 tmp;
4539                 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
4540                 tmp = IXGBE_READ_REG(hw, IXGBE_GORCH) & 0xF; /* 4 high bits of GORC */
4541                 adapter->stats.gorc += (tmp << 32);
4542                 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
4543                 tmp = IXGBE_READ_REG(hw, IXGBE_GOTCH) & 0xF; /* 4 high bits of GOTC */
4544                 adapter->stats.gotc += (tmp << 32);
4545                 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORL);
4546                 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
4547                 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
4548                 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
4549                 adapter->stats.fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
4550                 adapter->stats.fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
4551 #ifdef IXGBE_FCOE
4552                 adapter->stats.fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
4553                 adapter->stats.fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
4554                 adapter->stats.fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
4555                 adapter->stats.fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
4556                 adapter->stats.fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
4557                 adapter->stats.fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
4558 #endif /* IXGBE_FCOE */
4559         } else {
4560                 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
4561                 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
4562                 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
4563                 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
4564                 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH);
4565         }
4566         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
4567         adapter->stats.bprc += bprc;
4568         adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
4569         if (hw->mac.type == ixgbe_mac_82598EB)
4570                 adapter->stats.mprc -= bprc;
4571         adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC);
4572         adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
4573         adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
4574         adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
4575         adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
4576         adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
4577         adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
4578         adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
4579         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
4580         adapter->stats.lxontxc += lxon;
4581         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
4582         adapter->stats.lxofftxc += lxoff;
4583         adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
4584         adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
4585         adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
4586         /*
4587          * 82598 errata - tx of flow control packets is included in tx counters
4588          */
4589         xon_off_tot = lxon + lxoff;
4590         adapter->stats.gptc -= xon_off_tot;
4591         adapter->stats.mptc -= xon_off_tot;
4592         adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
4593         adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
4594         adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
4595         adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
4596         adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
4597         adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
4598         adapter->stats.ptc64 -= xon_off_tot;
4599         adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
4600         adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
4601         adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
4602         adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
4603         adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
4604         adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
4605
4606         /* Fill out the OS statistics structure */
4607         netdev->stats.multicast = adapter->stats.mprc;
4608
4609         /* Rx Errors */
4610         netdev->stats.rx_errors = adapter->stats.crcerrs +
4611                                        adapter->stats.rlec;
4612         netdev->stats.rx_dropped = 0;
4613         netdev->stats.rx_length_errors = adapter->stats.rlec;
4614         netdev->stats.rx_crc_errors = adapter->stats.crcerrs;
4615         netdev->stats.rx_missed_errors = total_mpc;
4616 }
4617
4618 /**
4619  * ixgbe_watchdog - Timer Call-back
4620  * @data: pointer to adapter cast into an unsigned long
4621  **/
4622 static void ixgbe_watchdog(unsigned long data)
4623 {
4624         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
4625         struct ixgbe_hw *hw = &adapter->hw;
4626         u64 eics = 0;
4627         int i;
4628
4629         /*
4630          *  Do the watchdog outside of interrupt context due to the lovely
4631          * delays that some of the newer hardware requires
4632          */
4633
4634         if (test_bit(__IXGBE_DOWN, &adapter->state))
4635                 goto watchdog_short_circuit;
4636
4637         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
4638                 /*
4639                  * for legacy and MSI interrupts don't set any bits
4640                  * that are enabled for EIAM, because this operation
4641                  * would set *both* EIMS and EICS for any bit in EIAM
4642                  */
4643                 IXGBE_WRITE_REG(hw, IXGBE_EICS,
4644                         (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
4645                 goto watchdog_reschedule;
4646         }
4647
4648         /* get one bit for every active tx/rx interrupt vector */
4649         for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
4650                 struct ixgbe_q_vector *qv = adapter->q_vector[i];
4651                 if (qv->rxr_count || qv->txr_count)
4652                         eics |= ((u64)1 << i);
4653         }
4654
4655         /* Cause software interrupt to ensure rx rings are cleaned */
4656         ixgbe_irq_rearm_queues(adapter, eics);
4657
4658 watchdog_reschedule:
4659         /* Reset the timer */
4660         mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ));
4661
4662 watchdog_short_circuit:
4663         schedule_work(&adapter->watchdog_task);
4664 }
4665
4666 /**
4667  * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
4668  * @work: pointer to work_struct containing our data
4669  **/
4670 static void ixgbe_multispeed_fiber_task(struct work_struct *work)
4671 {
4672         struct ixgbe_adapter *adapter = container_of(work,
4673                                                      struct ixgbe_adapter,
4674                                                      multispeed_fiber_task);
4675         struct ixgbe_hw *hw = &adapter->hw;
4676         u32 autoneg;
4677         bool negotiation;
4678
4679         adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
4680         autoneg = hw->phy.autoneg_advertised;
4681         if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
4682                 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
4683         if (hw->mac.ops.setup_link)
4684                 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
4685         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4686         adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
4687 }
4688
4689 /**
4690  * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
4691  * @work: pointer to work_struct containing our data
4692  **/
4693 static void ixgbe_sfp_config_module_task(struct work_struct *work)
4694 {
4695         struct ixgbe_adapter *adapter = container_of(work,
4696                                                      struct ixgbe_adapter,
4697                                                      sfp_config_module_task);
4698         struct ixgbe_hw *hw = &adapter->hw;
4699         u32 err;
4700
4701         adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
4702
4703         /* Time for electrical oscillations to settle down */
4704         msleep(100);
4705         err = hw->phy.ops.identify_sfp(hw);
4706
4707         if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
4708                 dev_err(&adapter->pdev->dev, "failed to initialize because "
4709                         "an unsupported SFP+ module type was detected.\n"
4710                         "Reload the driver after installing a supported "
4711                         "module.\n");
4712                 unregister_netdev(adapter->netdev);
4713                 return;
4714         }
4715         hw->mac.ops.setup_sfp(hw);
4716
4717         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
4718                 /* This will also work for DA Twinax connections */
4719                 schedule_work(&adapter->multispeed_fiber_task);
4720         adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
4721 }
4722
4723 /**
4724  * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table
4725  * @work: pointer to work_struct containing our data
4726  **/
4727 static void ixgbe_fdir_reinit_task(struct work_struct *work)
4728 {
4729         struct ixgbe_adapter *adapter = container_of(work,
4730                                                      struct ixgbe_adapter,
4731                                                      fdir_reinit_task);
4732         struct ixgbe_hw *hw = &adapter->hw;
4733         int i;
4734
4735         if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
4736                 for (i = 0; i < adapter->num_tx_queues; i++)
4737                         set_bit(__IXGBE_FDIR_INIT_DONE,
4738                                 &(adapter->tx_ring[i].reinit_state));
4739         } else {
4740                 DPRINTK(PROBE, ERR, "failed to finish FDIR re-initialization, "
4741                         "ignored adding FDIR ATR filters \n");
4742         }
4743         /* Done FDIR Re-initialization, enable transmits */
4744         netif_tx_start_all_queues(adapter->netdev);
4745 }
4746
4747 /**
4748  * ixgbe_watchdog_task - worker thread to bring link up
4749  * @work: pointer to work_struct containing our data
4750  **/
4751 static void ixgbe_watchdog_task(struct work_struct *work)
4752 {
4753         struct ixgbe_adapter *adapter = container_of(work,
4754                                                      struct ixgbe_adapter,
4755                                                      watchdog_task);
4756         struct net_device *netdev = adapter->netdev;
4757         struct ixgbe_hw *hw = &adapter->hw;
4758         u32 link_speed = adapter->link_speed;
4759         bool link_up = adapter->link_up;
4760         int i;
4761         struct ixgbe_ring *tx_ring;
4762         int some_tx_pending = 0;
4763
4764         adapter->flags |= IXGBE_FLAG_IN_WATCHDOG_TASK;
4765
4766         if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4767                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
4768                 if (link_up) {
4769 #ifdef CONFIG_DCB
4770                         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4771                                 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
4772                                         hw->mac.ops.fc_enable(hw, i);
4773                         } else {
4774                                 hw->mac.ops.fc_enable(hw, 0);
4775                         }
4776 #else
4777                         hw->mac.ops.fc_enable(hw, 0);
4778 #endif
4779                 }
4780
4781                 if (link_up ||
4782                     time_after(jiffies, (adapter->link_check_timeout +
4783                                          IXGBE_TRY_LINK_TIMEOUT))) {
4784                         adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4785                         IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
4786                 }
4787                 adapter->link_up = link_up;
4788                 adapter->link_speed = link_speed;
4789         }
4790
4791         if (link_up) {
4792                 if (!netif_carrier_ok(netdev)) {
4793                         bool flow_rx, flow_tx;
4794
4795                         if (hw->mac.type == ixgbe_mac_82599EB) {
4796                                 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4797                                 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4798                                 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
4799                                 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
4800                         } else {
4801                                 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4802                                 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
4803                                 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
4804                                 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
4805                         }
4806
4807                         printk(KERN_INFO "ixgbe: %s NIC Link is Up %s, "
4808                                "Flow Control: %s\n",
4809                                netdev->name,
4810                                (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
4811                                 "10 Gbps" :
4812                                 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
4813                                  "1 Gbps" : "unknown speed")),
4814                                ((flow_rx && flow_tx) ? "RX/TX" :
4815                                 (flow_rx ? "RX" :
4816                                 (flow_tx ? "TX" : "None"))));
4817
4818                         netif_carrier_on(netdev);
4819                 } else {
4820                         /* Force detection of hung controller */
4821                         adapter->detect_tx_hung = true;
4822                 }
4823         } else {
4824                 adapter->link_up = false;
4825                 adapter->link_speed = 0;
4826                 if (netif_carrier_ok(netdev)) {
4827                         printk(KERN_INFO "ixgbe: %s NIC Link is Down\n",
4828                                netdev->name);
4829                         netif_carrier_off(netdev);
4830                 }
4831         }
4832
4833         if (!netif_carrier_ok(netdev)) {
4834                 for (i = 0; i < adapter->num_tx_queues; i++) {
4835                         tx_ring = &adapter->tx_ring[i];
4836                         if (tx_ring->next_to_use != tx_ring->next_to_clean) {
4837                                 some_tx_pending = 1;
4838                                 break;
4839                         }
4840                 }
4841
4842                 if (some_tx_pending) {
4843                         /* We've lost link, so the controller stops DMA,
4844                          * but we've got queued Tx work that's never going
4845                          * to get done, so reset controller to flush Tx.
4846                          * (Do the reset outside of interrupt context).
4847                          */
4848                          schedule_work(&adapter->reset_task);
4849                 }
4850         }
4851
4852         ixgbe_update_stats(adapter);
4853         adapter->flags &= ~IXGBE_FLAG_IN_WATCHDOG_TASK;
4854 }
4855
4856 static int ixgbe_tso(struct ixgbe_adapter *adapter,
4857                      struct ixgbe_ring *tx_ring, struct sk_buff *skb,
4858                      u32 tx_flags, u8 *hdr_len)
4859 {
4860         struct ixgbe_adv_tx_context_desc *context_desc;
4861         unsigned int i;
4862         int err;
4863         struct ixgbe_tx_buffer *tx_buffer_info;
4864         u32 vlan_macip_lens = 0, type_tucmd_mlhl;
4865         u32 mss_l4len_idx, l4len;
4866
4867         if (skb_is_gso(skb)) {
4868                 if (skb_header_cloned(skb)) {
4869                         err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
4870                         if (err)
4871                                 return err;
4872                 }
4873                 l4len = tcp_hdrlen(skb);
4874                 *hdr_len += l4len;
4875
4876                 if (skb->protocol == htons(ETH_P_IP)) {
4877                         struct iphdr *iph = ip_hdr(skb);
4878                         iph->tot_len = 0;
4879                         iph->check = 0;
4880                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4881                                                                  iph->daddr, 0,
4882                                                                  IPPROTO_TCP,
4883                                                                  0);
4884                         adapter->hw_tso_ctxt++;
4885                 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
4886                         ipv6_hdr(skb)->payload_len = 0;
4887                         tcp_hdr(skb)->check =
4888                             ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
4889                                              &ipv6_hdr(skb)->daddr,
4890                                              0, IPPROTO_TCP, 0);
4891                         adapter->hw_tso6_ctxt++;
4892                 }
4893
4894                 i = tx_ring->next_to_use;
4895
4896                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4897                 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
4898
4899                 /* VLAN MACLEN IPLEN */
4900                 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4901                         vlan_macip_lens |=
4902                             (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
4903                 vlan_macip_lens |= ((skb_network_offset(skb)) <<
4904                                     IXGBE_ADVTXD_MACLEN_SHIFT);
4905                 *hdr_len += skb_network_offset(skb);
4906                 vlan_macip_lens |=
4907                     (skb_transport_header(skb) - skb_network_header(skb));
4908                 *hdr_len +=
4909                     (skb_transport_header(skb) - skb_network_header(skb));
4910                 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4911                 context_desc->seqnum_seed = 0;
4912
4913                 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
4914                 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
4915                                    IXGBE_ADVTXD_DTYP_CTXT);
4916
4917                 if (skb->protocol == htons(ETH_P_IP))
4918                         type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
4919                 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
4920                 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4921
4922                 /* MSS L4LEN IDX */
4923                 mss_l4len_idx =
4924                     (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
4925                 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
4926                 /* use index 1 for TSO */
4927                 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
4928                 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
4929
4930                 tx_buffer_info->time_stamp = jiffies;
4931                 tx_buffer_info->next_to_watch = i;
4932
4933                 i++;
4934                 if (i == tx_ring->count)
4935                         i = 0;
4936                 tx_ring->next_to_use = i;
4937
4938                 return true;
4939         }
4940         return false;
4941 }
4942
4943 static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
4944                           struct ixgbe_ring *tx_ring,
4945                           struct sk_buff *skb, u32 tx_flags)
4946 {
4947         struct ixgbe_adv_tx_context_desc *context_desc;
4948         unsigned int i;
4949         struct ixgbe_tx_buffer *tx_buffer_info;
4950         u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
4951
4952         if (skb->ip_summed == CHECKSUM_PARTIAL ||
4953             (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
4954                 i = tx_ring->next_to_use;
4955                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4956                 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
4957
4958                 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4959                         vlan_macip_lens |=
4960                             (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
4961                 vlan_macip_lens |= (skb_network_offset(skb) <<
4962                                     IXGBE_ADVTXD_MACLEN_SHIFT);
4963                 if (skb->ip_summed == CHECKSUM_PARTIAL)
4964                         vlan_macip_lens |= (skb_transport_header(skb) -
4965                                             skb_network_header(skb));
4966
4967                 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4968                 context_desc->seqnum_seed = 0;
4969
4970                 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
4971                                     IXGBE_ADVTXD_DTYP_CTXT);
4972
4973                 if (skb->ip_summed == CHECKSUM_PARTIAL) {
4974                         switch (skb->protocol) {
4975                         case cpu_to_be16(ETH_P_IP):
4976                                 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
4977                                 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
4978                                         type_tucmd_mlhl |=
4979                                                 IXGBE_ADVTXD_TUCMD_L4T_TCP;
4980                                 else if (ip_hdr(skb)->protocol == IPPROTO_SCTP)
4981                                         type_tucmd_mlhl |=
4982                                                 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
4983                                 break;
4984                         case cpu_to_be16(ETH_P_IPV6):
4985                                 /* XXX what about other V6 headers?? */
4986                                 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
4987                                         type_tucmd_mlhl |=
4988                                                 IXGBE_ADVTXD_TUCMD_L4T_TCP;
4989                                 else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP)
4990                                         type_tucmd_mlhl |=
4991                                                 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
4992                                 break;
4993                         default:
4994                                 if (unlikely(net_ratelimit())) {
4995                                         DPRINTK(PROBE, WARNING,
4996                                          "partial checksum but proto=%x!\n",
4997                                          skb->protocol);
4998                                 }
4999                                 break;
5000                         }
5001                 }
5002
5003                 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
5004                 /* use index zero for tx checksum offload */
5005                 context_desc->mss_l4len_idx = 0;
5006
5007                 tx_buffer_info->time_stamp = jiffies;
5008                 tx_buffer_info->next_to_watch = i;
5009
5010                 adapter->hw_csum_tx_good++;
5011                 i++;
5012                 if (i == tx_ring->count)
5013                         i = 0;
5014                 tx_ring->next_to_use = i;
5015
5016                 return true;
5017         }
5018
5019         return false;
5020 }
5021
5022 static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
5023                         struct ixgbe_ring *tx_ring,
5024                         struct sk_buff *skb, u32 tx_flags,
5025                         unsigned int first)
5026 {
5027         struct ixgbe_tx_buffer *tx_buffer_info;
5028         unsigned int len;
5029         unsigned int total = skb->len;
5030         unsigned int offset = 0, size, count = 0, i;
5031         unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
5032         unsigned int f;
5033         dma_addr_t *map;
5034
5035         i = tx_ring->next_to_use;
5036
5037         if (skb_dma_map(&adapter->pdev->dev, skb, DMA_TO_DEVICE)) {
5038                 dev_err(&adapter->pdev->dev, "TX DMA map failed\n");
5039                 return 0;
5040         }
5041
5042         map = skb_shinfo(skb)->dma_maps;
5043
5044         if (tx_flags & IXGBE_TX_FLAGS_FCOE)
5045                 /* excluding fcoe_crc_eof for FCoE */
5046                 total -= sizeof(struct fcoe_crc_eof);
5047
5048         len = min(skb_headlen(skb), total);
5049         while (len) {
5050                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5051                 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
5052
5053                 tx_buffer_info->length = size;
5054                 tx_buffer_info->dma = skb_shinfo(skb)->dma_head + offset;
5055                 tx_buffer_info->time_stamp = jiffies;
5056                 tx_buffer_info->next_to_watch = i;
5057
5058                 len -= size;
5059                 total -= size;
5060                 offset += size;
5061                 count++;
5062
5063                 if (len) {
5064                         i++;
5065                         if (i == tx_ring->count)
5066                                 i = 0;
5067                 }
5068         }
5069
5070         for (f = 0; f < nr_frags; f++) {
5071                 struct skb_frag_struct *frag;
5072
5073                 frag = &skb_shinfo(skb)->frags[f];
5074                 len = min((unsigned int)frag->size, total);
5075                 offset = 0;
5076
5077                 while (len) {
5078                         i++;
5079                         if (i == tx_ring->count)
5080                                 i = 0;
5081
5082                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
5083                         size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
5084
5085                         tx_buffer_info->length = size;
5086                         tx_buffer_info->dma = map[f] + offset;
5087                         tx_buffer_info->time_stamp = jiffies;
5088                         tx_buffer_info->next_to_watch = i;
5089
5090                         len -= size;
5091                         total -= size;
5092                         offset += size;
5093                         count++;
5094                 }
5095                 if (total == 0)
5096                         break;
5097         }
5098
5099         tx_ring->tx_buffer_info[i].skb = skb;
5100         tx_ring->tx_buffer_info[first].next_to_watch = i;
5101
5102         return count;
5103 }
5104
5105 static void ixgbe_tx_queue(struct ixgbe_adapter *adapter,
5106                            struct ixgbe_ring *tx_ring,
5107                            int tx_flags, int count, u32 paylen, u8 hdr_len)
5108 {
5109         union ixgbe_adv_tx_desc *tx_desc = NULL;
5110         struct ixgbe_tx_buffer *tx_buffer_info;
5111         u32 olinfo_status = 0, cmd_type_len = 0;
5112         unsigned int i;
5113         u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
5114
5115         cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
5116
5117         cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
5118
5119         if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5120                 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
5121
5122         if (tx_flags & IXGBE_TX_FLAGS_TSO) {
5123                 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
5124
5125                 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
5126                                  IXGBE_ADVTXD_POPTS_SHIFT;
5127
5128                 /* use index 1 context for tso */
5129                 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
5130                 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
5131                         olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
5132                                          IXGBE_ADVTXD_POPTS_SHIFT;
5133
5134         } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
5135                 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
5136                                  IXGBE_ADVTXD_POPTS_SHIFT;
5137
5138         if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
5139                 olinfo_status |= IXGBE_ADVTXD_CC;
5140                 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
5141                 if (tx_flags & IXGBE_TX_FLAGS_FSO)
5142                         cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
5143         }
5144
5145         olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
5146
5147         i = tx_ring->next_to_use;
5148         while (count--) {
5149                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5150                 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
5151                 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
5152                 tx_desc->read.cmd_type_len =
5153                         cpu_to_le32(cmd_type_len | tx_buffer_info->length);
5154                 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
5155                 i++;
5156                 if (i == tx_ring->count)
5157                         i = 0;
5158         }
5159
5160         tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
5161
5162         /*
5163          * Force memory writes to complete before letting h/w
5164          * know there are new descriptors to fetch.  (Only
5165          * applicable for weak-ordered memory model archs,
5166          * such as IA-64).
5167          */
5168         wmb();
5169
5170         tx_ring->next_to_use = i;
5171         writel(i, adapter->hw.hw_addr + tx_ring->tail);
5172 }
5173
5174 static void ixgbe_atr(struct ixgbe_adapter *adapter, struct sk_buff *skb,
5175                       int queue, u32 tx_flags)
5176 {
5177         /* Right now, we support IPv4 only */
5178         struct ixgbe_atr_input atr_input;
5179         struct tcphdr *th;
5180         struct iphdr *iph = ip_hdr(skb);
5181         struct ethhdr *eth = (struct ethhdr *)skb->data;
5182         u16 vlan_id, src_port, dst_port, flex_bytes;
5183         u32 src_ipv4_addr, dst_ipv4_addr;
5184         u8 l4type = 0;
5185
5186         /* check if we're UDP or TCP */
5187         if (iph->protocol == IPPROTO_TCP) {
5188                 th = tcp_hdr(skb);
5189                 src_port = th->source;
5190                 dst_port = th->dest;
5191                 l4type |= IXGBE_ATR_L4TYPE_TCP;
5192                 /* l4type IPv4 type is 0, no need to assign */
5193         } else {
5194                 /* Unsupported L4 header, just bail here */
5195                 return;
5196         }
5197
5198         memset(&atr_input, 0, sizeof(struct ixgbe_atr_input));
5199
5200         vlan_id = (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK) >>
5201                    IXGBE_TX_FLAGS_VLAN_SHIFT;
5202         src_ipv4_addr = iph->saddr;
5203         dst_ipv4_addr = iph->daddr;
5204         flex_bytes = eth->h_proto;
5205
5206         ixgbe_atr_set_vlan_id_82599(&atr_input, vlan_id);
5207         ixgbe_atr_set_src_port_82599(&atr_input, dst_port);
5208         ixgbe_atr_set_dst_port_82599(&atr_input, src_port);
5209         ixgbe_atr_set_flex_byte_82599(&atr_input, flex_bytes);
5210         ixgbe_atr_set_l4type_82599(&atr_input, l4type);
5211         /* src and dst are inverted, think how the receiver sees them */
5212         ixgbe_atr_set_src_ipv4_82599(&atr_input, dst_ipv4_addr);
5213         ixgbe_atr_set_dst_ipv4_82599(&atr_input, src_ipv4_addr);
5214
5215         /* This assumes the Rx queue and Tx queue are bound to the same CPU */
5216         ixgbe_fdir_add_signature_filter_82599(&adapter->hw, &atr_input, queue);
5217 }
5218
5219 static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
5220                                  struct ixgbe_ring *tx_ring, int size)
5221 {
5222         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5223
5224         netif_stop_subqueue(netdev, tx_ring->queue_index);
5225         /* Herbert's original patch had:
5226          *  smp_mb__after_netif_stop_queue();
5227          * but since that doesn't exist yet, just open code it. */
5228         smp_mb();
5229
5230         /* We need to check again in a case another CPU has just
5231          * made room available. */
5232         if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
5233                 return -EBUSY;
5234
5235         /* A reprieve! - use start_queue because it doesn't call schedule */
5236         netif_start_subqueue(netdev, tx_ring->queue_index);
5237         ++adapter->restart_queue;
5238         return 0;
5239 }
5240
5241 static int ixgbe_maybe_stop_tx(struct net_device *netdev,
5242                               struct ixgbe_ring *tx_ring, int size)
5243 {
5244         if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
5245                 return 0;
5246         return __ixgbe_maybe_stop_tx(netdev, tx_ring, size);
5247 }
5248
5249 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
5250 {
5251         struct ixgbe_adapter *adapter = netdev_priv(dev);
5252
5253         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
5254                 return smp_processor_id();
5255
5256         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
5257                 return (skb->vlan_tci & IXGBE_TX_FLAGS_VLAN_PRIO_MASK) >> 13;
5258
5259         return skb_tx_hash(dev, skb);
5260 }
5261
5262 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
5263                                     struct net_device *netdev)
5264 {
5265         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5266         struct ixgbe_ring *tx_ring;
5267         unsigned int first;
5268         unsigned int tx_flags = 0;
5269         u8 hdr_len = 0;
5270         int r_idx = 0, tso;
5271         int count = 0;
5272         unsigned int f;
5273
5274         if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
5275                 tx_flags |= vlan_tx_tag_get(skb);
5276                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5277                         tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
5278                         tx_flags |= (skb->queue_mapping << 13);
5279                 }
5280                 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
5281                 tx_flags |= IXGBE_TX_FLAGS_VLAN;
5282         } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5283                 if (skb->priority != TC_PRIO_CONTROL) {
5284                         tx_flags |= (skb->queue_mapping << 13);
5285                         tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
5286                         tx_flags |= IXGBE_TX_FLAGS_VLAN;
5287                 } else {
5288                         skb->queue_mapping =
5289                                 adapter->ring_feature[RING_F_DCB].indices-1;
5290                 }
5291         }
5292
5293         r_idx = skb->queue_mapping;
5294         tx_ring = &adapter->tx_ring[r_idx];
5295
5296         if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
5297             (skb->protocol == htons(ETH_P_FCOE))) {
5298                 tx_flags |= IXGBE_TX_FLAGS_FCOE;
5299 #ifdef IXGBE_FCOE
5300                 r_idx = smp_processor_id();
5301                 r_idx &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
5302                 r_idx += adapter->ring_feature[RING_F_FCOE].mask;
5303                 tx_ring = &adapter->tx_ring[r_idx];
5304 #endif
5305         }
5306         /* four things can cause us to need a context descriptor */
5307         if (skb_is_gso(skb) ||
5308             (skb->ip_summed == CHECKSUM_PARTIAL) ||
5309             (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
5310             (tx_flags & IXGBE_TX_FLAGS_FCOE))
5311                 count++;
5312
5313         count += TXD_USE_COUNT(skb_headlen(skb));
5314         for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
5315                 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
5316
5317         if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) {
5318                 adapter->tx_busy++;
5319                 return NETDEV_TX_BUSY;
5320         }
5321
5322         first = tx_ring->next_to_use;
5323         if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
5324 #ifdef IXGBE_FCOE
5325                 /* setup tx offload for FCoE */
5326                 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
5327                 if (tso < 0) {
5328                         dev_kfree_skb_any(skb);
5329                         return NETDEV_TX_OK;
5330                 }
5331                 if (tso)
5332                         tx_flags |= IXGBE_TX_FLAGS_FSO;
5333 #endif /* IXGBE_FCOE */
5334         } else {
5335                 if (skb->protocol == htons(ETH_P_IP))
5336                         tx_flags |= IXGBE_TX_FLAGS_IPV4;
5337                 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len);
5338                 if (tso < 0) {
5339                         dev_kfree_skb_any(skb);
5340                         return NETDEV_TX_OK;
5341                 }
5342
5343                 if (tso)
5344                         tx_flags |= IXGBE_TX_FLAGS_TSO;
5345                 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) &&
5346                          (skb->ip_summed == CHECKSUM_PARTIAL))
5347                         tx_flags |= IXGBE_TX_FLAGS_CSUM;
5348         }
5349
5350         count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first);
5351         if (count) {
5352                 /* add the ATR filter if ATR is on */
5353                 if (tx_ring->atr_sample_rate) {
5354                         ++tx_ring->atr_count;
5355                         if ((tx_ring->atr_count >= tx_ring->atr_sample_rate) &&
5356                              test_bit(__IXGBE_FDIR_INIT_DONE,
5357                                       &tx_ring->reinit_state)) {
5358                                 ixgbe_atr(adapter, skb, tx_ring->queue_index,
5359                                           tx_flags);
5360                                 tx_ring->atr_count = 0;
5361                         }
5362                 }
5363                 ixgbe_tx_queue(adapter, tx_ring, tx_flags, count, skb->len,
5364                                hdr_len);
5365                 ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
5366
5367         } else {
5368                 dev_kfree_skb_any(skb);
5369                 tx_ring->tx_buffer_info[first].time_stamp = 0;
5370                 tx_ring->next_to_use = first;
5371         }
5372
5373         return NETDEV_TX_OK;
5374 }
5375
5376 /**
5377  * ixgbe_get_stats - Get System Network Statistics
5378  * @netdev: network interface device structure
5379  *
5380  * Returns the address of the device statistics structure.
5381  * The statistics are actually updated from the timer callback.
5382  **/
5383 static struct net_device_stats *ixgbe_get_stats(struct net_device *netdev)
5384 {
5385         /* only return the current stats */
5386         return &netdev->stats;
5387 }
5388
5389 /**
5390  * ixgbe_set_mac - Change the Ethernet Address of the NIC
5391  * @netdev: network interface device structure
5392  * @p: pointer to an address structure
5393  *
5394  * Returns 0 on success, negative on failure
5395  **/
5396 static int ixgbe_set_mac(struct net_device *netdev, void *p)
5397 {
5398         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5399         struct ixgbe_hw *hw = &adapter->hw;
5400         struct sockaddr *addr = p;
5401
5402         if (!is_valid_ether_addr(addr->sa_data))
5403                 return -EADDRNOTAVAIL;
5404
5405         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
5406         memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
5407
5408         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
5409
5410         return 0;
5411 }
5412
5413 static int
5414 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
5415 {
5416         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5417         struct ixgbe_hw *hw = &adapter->hw;
5418         u16 value;
5419         int rc;
5420
5421         if (prtad != hw->phy.mdio.prtad)
5422                 return -EINVAL;
5423         rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
5424         if (!rc)
5425                 rc = value;
5426         return rc;
5427 }
5428
5429 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
5430                             u16 addr, u16 value)
5431 {
5432         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5433         struct ixgbe_hw *hw = &adapter->hw;
5434
5435         if (prtad != hw->phy.mdio.prtad)
5436                 return -EINVAL;
5437         return hw->phy.ops.write_reg(hw, addr, devad, value);
5438 }
5439
5440 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
5441 {
5442         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5443
5444         return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
5445 }
5446
5447 /**
5448  * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
5449  * netdev->dev_addrs
5450  * @netdev: network interface device structure
5451  *
5452  * Returns non-zero on failure
5453  **/
5454 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
5455 {
5456         int err = 0;
5457         struct ixgbe_adapter *adapter = netdev_priv(dev);
5458         struct ixgbe_mac_info *mac = &adapter->hw.mac;
5459
5460         if (is_valid_ether_addr(mac->san_addr)) {
5461                 rtnl_lock();
5462                 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
5463                 rtnl_unlock();
5464         }
5465         return err;
5466 }
5467
5468 /**
5469  * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
5470  * netdev->dev_addrs
5471  * @netdev: network interface device structure
5472  *
5473  * Returns non-zero on failure
5474  **/
5475 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
5476 {
5477         int err = 0;
5478         struct ixgbe_adapter *adapter = netdev_priv(dev);
5479         struct ixgbe_mac_info *mac = &adapter->hw.mac;
5480
5481         if (is_valid_ether_addr(mac->san_addr)) {
5482                 rtnl_lock();
5483                 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
5484                 rtnl_unlock();
5485         }
5486         return err;
5487 }
5488
5489 #ifdef CONFIG_NET_POLL_CONTROLLER
5490 /*
5491  * Polling 'interrupt' - used by things like netconsole to send skbs
5492  * without having to re-enable interrupts. It's not called while
5493  * the interrupt routine is executing.
5494  */
5495 static void ixgbe_netpoll(struct net_device *netdev)
5496 {
5497         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5498         int i;
5499
5500         adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
5501         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
5502                 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
5503                 for (i = 0; i < num_q_vectors; i++) {
5504                         struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
5505                         ixgbe_msix_clean_many(0, q_vector);
5506                 }
5507         } else {
5508                 ixgbe_intr(adapter->pdev->irq, netdev);
5509         }
5510         adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
5511 }
5512 #endif
5513
5514 static const struct net_device_ops ixgbe_netdev_ops = {
5515         .ndo_open               = ixgbe_open,
5516         .ndo_stop               = ixgbe_close,
5517         .ndo_start_xmit         = ixgbe_xmit_frame,
5518         .ndo_select_queue       = ixgbe_select_queue,
5519         .ndo_get_stats          = ixgbe_get_stats,
5520         .ndo_set_rx_mode        = ixgbe_set_rx_mode,
5521         .ndo_set_multicast_list = ixgbe_set_rx_mode,
5522         .ndo_validate_addr      = eth_validate_addr,
5523         .ndo_set_mac_address    = ixgbe_set_mac,
5524         .ndo_change_mtu         = ixgbe_change_mtu,
5525         .ndo_tx_timeout         = ixgbe_tx_timeout,
5526         .ndo_vlan_rx_register   = ixgbe_vlan_rx_register,
5527         .ndo_vlan_rx_add_vid    = ixgbe_vlan_rx_add_vid,
5528         .ndo_vlan_rx_kill_vid   = ixgbe_vlan_rx_kill_vid,
5529         .ndo_do_ioctl           = ixgbe_ioctl,
5530 #ifdef CONFIG_NET_POLL_CONTROLLER
5531         .ndo_poll_controller    = ixgbe_netpoll,
5532 #endif
5533 #ifdef IXGBE_FCOE
5534         .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
5535         .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
5536         .ndo_fcoe_enable = ixgbe_fcoe_enable,
5537         .ndo_fcoe_disable = ixgbe_fcoe_disable,
5538         .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
5539 #endif /* IXGBE_FCOE */
5540 };
5541
5542 /**
5543  * ixgbe_probe - Device Initialization Routine
5544  * @pdev: PCI device information struct
5545  * @ent: entry in ixgbe_pci_tbl
5546  *
5547  * Returns 0 on success, negative on failure
5548  *
5549  * ixgbe_probe initializes an adapter identified by a pci_dev structure.
5550  * The OS initialization, configuring of the adapter private structure,
5551  * and a hardware reset occur.
5552  **/
5553 static int __devinit ixgbe_probe(struct pci_dev *pdev,
5554                                  const struct pci_device_id *ent)
5555 {
5556         struct net_device *netdev;
5557         struct ixgbe_adapter *adapter = NULL;
5558         struct ixgbe_hw *hw;
5559         const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
5560         static int cards_found;
5561         int i, err, pci_using_dac;
5562 #ifdef IXGBE_FCOE
5563         u16 device_caps;
5564 #endif
5565         u32 part_num, eec;
5566
5567         err = pci_enable_device_mem(pdev);
5568         if (err)
5569                 return err;
5570
5571         if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) &&
5572             !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
5573                 pci_using_dac = 1;
5574         } else {
5575                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
5576                 if (err) {
5577                         err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
5578                         if (err) {
5579                                 dev_err(&pdev->dev, "No usable DMA "
5580                                         "configuration, aborting\n");
5581                                 goto err_dma;
5582                         }
5583                 }
5584                 pci_using_dac = 0;
5585         }
5586
5587         err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
5588                                            IORESOURCE_MEM), ixgbe_driver_name);
5589         if (err) {
5590                 dev_err(&pdev->dev,
5591                         "pci_request_selected_regions failed 0x%x\n", err);
5592                 goto err_pci_reg;
5593         }
5594
5595         pci_enable_pcie_error_reporting(pdev);
5596
5597         pci_set_master(pdev);
5598         pci_save_state(pdev);
5599
5600         netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), MAX_TX_QUEUES);
5601         if (!netdev) {
5602                 err = -ENOMEM;
5603                 goto err_alloc_etherdev;
5604         }
5605
5606         SET_NETDEV_DEV(netdev, &pdev->dev);
5607
5608         pci_set_drvdata(pdev, netdev);
5609         adapter = netdev_priv(netdev);
5610
5611         adapter->netdev = netdev;
5612         adapter->pdev = pdev;
5613         hw = &adapter->hw;
5614         hw->back = adapter;
5615         adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
5616
5617         hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
5618                               pci_resource_len(pdev, 0));
5619         if (!hw->hw_addr) {
5620                 err = -EIO;
5621                 goto err_ioremap;
5622         }
5623
5624         for (i = 1; i <= 5; i++) {
5625                 if (pci_resource_len(pdev, i) == 0)
5626                         continue;
5627         }
5628
5629         netdev->netdev_ops = &ixgbe_netdev_ops;
5630         ixgbe_set_ethtool_ops(netdev);
5631         netdev->watchdog_timeo = 5 * HZ;
5632         strcpy(netdev->name, pci_name(pdev));
5633
5634         adapter->bd_number = cards_found;
5635
5636         /* Setup hw api */
5637         memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
5638         hw->mac.type  = ii->mac;
5639
5640         /* EEPROM */
5641         memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
5642         eec = IXGBE_READ_REG(hw, IXGBE_EEC);
5643         /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
5644         if (!(eec & (1 << 8)))
5645                 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
5646
5647         /* PHY */
5648         memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
5649         hw->phy.sfp_type = ixgbe_sfp_type_unknown;
5650         /* ixgbe_identify_phy_generic will set prtad and mmds properly */
5651         hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
5652         hw->phy.mdio.mmds = 0;
5653         hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
5654         hw->phy.mdio.dev = netdev;
5655         hw->phy.mdio.mdio_read = ixgbe_mdio_read;
5656         hw->phy.mdio.mdio_write = ixgbe_mdio_write;
5657
5658         /* set up this timer and work struct before calling get_invariants
5659          * which might start the timer
5660          */
5661         init_timer(&adapter->sfp_timer);
5662         adapter->sfp_timer.function = &ixgbe_sfp_timer;
5663         adapter->sfp_timer.data = (unsigned long) adapter;
5664
5665         INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
5666
5667         /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
5668         INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
5669
5670         /* a new SFP+ module arrival, called from GPI SDP2 context */
5671         INIT_WORK(&adapter->sfp_config_module_task,
5672                   ixgbe_sfp_config_module_task);
5673
5674         ii->get_invariants(hw);
5675
5676         /* setup the private structure */
5677         err = ixgbe_sw_init(adapter);
5678         if (err)
5679                 goto err_sw_init;
5680
5681         /*
5682          * If there is a fan on this device and it has failed log the
5683          * failure.
5684          */
5685         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
5686                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
5687                 if (esdp & IXGBE_ESDP_SDP1)
5688                         DPRINTK(PROBE, CRIT,
5689                                 "Fan has stopped, replace the adapter\n");
5690         }
5691
5692         /* reset_hw fills in the perm_addr as well */
5693         err = hw->mac.ops.reset_hw(hw);
5694         if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
5695             hw->mac.type == ixgbe_mac_82598EB) {
5696                 /*
5697                  * Start a kernel thread to watch for a module to arrive.
5698                  * Only do this for 82598, since 82599 will generate
5699                  * interrupts on module arrival.
5700                  */
5701                 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5702                 mod_timer(&adapter->sfp_timer,
5703                           round_jiffies(jiffies + (2 * HZ)));
5704                 err = 0;
5705         } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
5706                 dev_err(&adapter->pdev->dev, "failed to initialize because "
5707                         "an unsupported SFP+ module type was detected.\n"
5708                         "Reload the driver after installing a supported "
5709                         "module.\n");
5710                 goto err_sw_init;
5711         } else if (err) {
5712                 dev_err(&adapter->pdev->dev, "HW Init failed: %d\n", err);
5713                 goto err_sw_init;
5714         }
5715
5716         netdev->features = NETIF_F_SG |
5717                            NETIF_F_IP_CSUM |
5718                            NETIF_F_HW_VLAN_TX |
5719                            NETIF_F_HW_VLAN_RX |
5720                            NETIF_F_HW_VLAN_FILTER;
5721
5722         netdev->features |= NETIF_F_IPV6_CSUM;
5723         netdev->features |= NETIF_F_TSO;
5724         netdev->features |= NETIF_F_TSO6;
5725         netdev->features |= NETIF_F_GRO;
5726
5727         if (adapter->hw.mac.type == ixgbe_mac_82599EB)
5728                 netdev->features |= NETIF_F_SCTP_CSUM;
5729
5730         netdev->vlan_features |= NETIF_F_TSO;
5731         netdev->vlan_features |= NETIF_F_TSO6;
5732         netdev->vlan_features |= NETIF_F_IP_CSUM;
5733         netdev->vlan_features |= NETIF_F_IPV6_CSUM;
5734         netdev->vlan_features |= NETIF_F_SG;
5735
5736         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
5737                 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
5738
5739 #ifdef CONFIG_IXGBE_DCB
5740         netdev->dcbnl_ops = &dcbnl_ops;
5741 #endif
5742
5743 #ifdef IXGBE_FCOE
5744         if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
5745                 if (hw->mac.ops.get_device_caps) {
5746                         hw->mac.ops.get_device_caps(hw, &device_caps);
5747                         if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
5748                                 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
5749                 }
5750         }
5751 #endif /* IXGBE_FCOE */
5752         if (pci_using_dac)
5753                 netdev->features |= NETIF_F_HIGHDMA;
5754
5755         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
5756                 netdev->features |= NETIF_F_LRO;
5757
5758         /* make sure the EEPROM is good */
5759         if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
5760                 dev_err(&pdev->dev, "The EEPROM Checksum Is Not Valid\n");
5761                 err = -EIO;
5762                 goto err_eeprom;
5763         }
5764
5765         memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
5766         memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
5767
5768         if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
5769                 dev_err(&pdev->dev, "invalid MAC address\n");
5770                 err = -EIO;
5771                 goto err_eeprom;
5772         }
5773
5774         init_timer(&adapter->watchdog_timer);
5775         adapter->watchdog_timer.function = &ixgbe_watchdog;
5776         adapter->watchdog_timer.data = (unsigned long)adapter;
5777
5778         INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
5779         INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
5780
5781         err = ixgbe_init_interrupt_scheme(adapter);
5782         if (err)
5783                 goto err_sw_init;
5784
5785         switch (pdev->device) {
5786         case IXGBE_DEV_ID_82599_KX4:
5787                 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
5788                                 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
5789                 /* Enable ACPI wakeup in GRC */
5790                 IXGBE_WRITE_REG(hw, IXGBE_GRC,
5791                              (IXGBE_READ_REG(hw, IXGBE_GRC) & ~IXGBE_GRC_APME));
5792                 break;
5793         default:
5794                 adapter->wol = 0;
5795                 break;
5796         }
5797         device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
5798
5799         /* pick up the PCI bus settings for reporting later */
5800         hw->mac.ops.get_bus_info(hw);
5801
5802         /* print bus type/speed/width info */
5803         dev_info(&pdev->dev, "(PCI Express:%s:%s) %pM\n",
5804                 ((hw->bus.speed == ixgbe_bus_speed_5000) ? "5.0Gb/s":
5805                  (hw->bus.speed == ixgbe_bus_speed_2500) ? "2.5Gb/s":"Unknown"),
5806                 ((hw->bus.width == ixgbe_bus_width_pcie_x8) ? "Width x8" :
5807                  (hw->bus.width == ixgbe_bus_width_pcie_x4) ? "Width x4" :
5808                  (hw->bus.width == ixgbe_bus_width_pcie_x1) ? "Width x1" :
5809                  "Unknown"),
5810                 netdev->dev_addr);
5811         ixgbe_read_pba_num_generic(hw, &part_num);
5812         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
5813                 dev_info(&pdev->dev, "MAC: %d, PHY: %d, SFP+: %d, PBA No: %06x-%03x\n",
5814                          hw->mac.type, hw->phy.type, hw->phy.sfp_type,
5815                          (part_num >> 8), (part_num & 0xff));
5816         else
5817                 dev_info(&pdev->dev, "MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
5818                          hw->mac.type, hw->phy.type,
5819                          (part_num >> 8), (part_num & 0xff));
5820
5821         if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
5822                 dev_warn(&pdev->dev, "PCI-Express bandwidth available for "
5823                          "this card is not sufficient for optimal "
5824                          "performance.\n");
5825                 dev_warn(&pdev->dev, "For optimal performance a x8 "
5826                          "PCI-Express slot is required.\n");
5827         }
5828
5829         /* save off EEPROM version number */
5830         hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
5831
5832         /* reset the hardware with the new settings */
5833         err = hw->mac.ops.start_hw(hw);
5834
5835         if (err == IXGBE_ERR_EEPROM_VERSION) {
5836                 /* We are running on a pre-production device, log a warning */
5837                 dev_warn(&pdev->dev, "This device is a pre-production "
5838                          "adapter/LOM.  Please be aware there may be issues "
5839                          "associated with your hardware.  If you are "
5840                          "experiencing problems please contact your Intel or "
5841                          "hardware representative who provided you with this "
5842                          "hardware.\n");
5843         }
5844         strcpy(netdev->name, "eth%d");
5845         err = register_netdev(netdev);
5846         if (err)
5847                 goto err_register;
5848
5849         /* carrier off reporting is important to ethtool even BEFORE open */
5850         netif_carrier_off(netdev);
5851
5852         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
5853             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
5854                 INIT_WORK(&adapter->fdir_reinit_task, ixgbe_fdir_reinit_task);
5855
5856 #ifdef CONFIG_IXGBE_DCA
5857         if (dca_add_requester(&pdev->dev) == 0) {
5858                 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
5859                 ixgbe_setup_dca(adapter);
5860         }
5861 #endif
5862         /* add san mac addr to netdev */
5863         ixgbe_add_sanmac_netdev(netdev);
5864
5865         dev_info(&pdev->dev, "Intel(R) 10 Gigabit Network Connection\n");
5866         cards_found++;
5867         return 0;
5868
5869 err_register:
5870         ixgbe_release_hw_control(adapter);
5871         ixgbe_clear_interrupt_scheme(adapter);
5872 err_sw_init:
5873 err_eeprom:
5874         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5875         del_timer_sync(&adapter->sfp_timer);
5876         cancel_work_sync(&adapter->sfp_task);
5877         cancel_work_sync(&adapter->multispeed_fiber_task);
5878         cancel_work_sync(&adapter->sfp_config_module_task);
5879         iounmap(hw->hw_addr);
5880 err_ioremap:
5881         free_netdev(netdev);
5882 err_alloc_etherdev:
5883         pci_release_selected_regions(pdev, pci_select_bars(pdev,
5884                                      IORESOURCE_MEM));
5885 err_pci_reg:
5886 err_dma:
5887         pci_disable_device(pdev);
5888         return err;
5889 }
5890
5891 /**
5892  * ixgbe_remove - Device Removal Routine
5893  * @pdev: PCI device information struct
5894  *
5895  * ixgbe_remove is called by the PCI subsystem to alert the driver
5896  * that it should release a PCI device.  The could be caused by a
5897  * Hot-Plug event, or because the driver is going to be removed from
5898  * memory.
5899  **/
5900 static void __devexit ixgbe_remove(struct pci_dev *pdev)
5901 {
5902         struct net_device *netdev = pci_get_drvdata(pdev);
5903         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5904
5905         set_bit(__IXGBE_DOWN, &adapter->state);
5906         /* clear the module not found bit to make sure the worker won't
5907          * reschedule
5908          */
5909         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5910         del_timer_sync(&adapter->watchdog_timer);
5911
5912         del_timer_sync(&adapter->sfp_timer);
5913         cancel_work_sync(&adapter->watchdog_task);
5914         cancel_work_sync(&adapter->sfp_task);
5915         cancel_work_sync(&adapter->multispeed_fiber_task);
5916         cancel_work_sync(&adapter->sfp_config_module_task);
5917         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
5918             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
5919                 cancel_work_sync(&adapter->fdir_reinit_task);
5920         flush_scheduled_work();
5921
5922 #ifdef CONFIG_IXGBE_DCA
5923         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
5924                 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
5925                 dca_remove_requester(&pdev->dev);
5926                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
5927         }
5928
5929 #endif
5930 #ifdef IXGBE_FCOE
5931         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
5932                 ixgbe_cleanup_fcoe(adapter);
5933
5934 #endif /* IXGBE_FCOE */
5935
5936         /* remove the added san mac */
5937         ixgbe_del_sanmac_netdev(netdev);
5938
5939         if (netdev->reg_state == NETREG_REGISTERED)
5940                 unregister_netdev(netdev);
5941
5942         ixgbe_clear_interrupt_scheme(adapter);
5943
5944         ixgbe_release_hw_control(adapter);
5945
5946         iounmap(adapter->hw.hw_addr);
5947         pci_release_selected_regions(pdev, pci_select_bars(pdev,
5948                                      IORESOURCE_MEM));
5949
5950         DPRINTK(PROBE, INFO, "complete\n");
5951
5952         free_netdev(netdev);
5953
5954         pci_disable_pcie_error_reporting(pdev);
5955
5956         pci_disable_device(pdev);
5957 }
5958
5959 /**
5960  * ixgbe_io_error_detected - called when PCI error is detected
5961  * @pdev: Pointer to PCI device
5962  * @state: The current pci connection state
5963  *
5964  * This function is called after a PCI bus error affecting
5965  * this device has been detected.
5966  */
5967 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
5968                                                 pci_channel_state_t state)
5969 {
5970         struct net_device *netdev = pci_get_drvdata(pdev);
5971         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5972
5973         netif_device_detach(netdev);
5974
5975         if (state == pci_channel_io_perm_failure)
5976                 return PCI_ERS_RESULT_DISCONNECT;
5977
5978         if (netif_running(netdev))
5979                 ixgbe_down(adapter);
5980         pci_disable_device(pdev);
5981
5982         /* Request a slot reset. */
5983         return PCI_ERS_RESULT_NEED_RESET;
5984 }
5985
5986 /**
5987  * ixgbe_io_slot_reset - called after the pci bus has been reset.
5988  * @pdev: Pointer to PCI device
5989  *
5990  * Restart the card from scratch, as if from a cold-boot.
5991  */
5992 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
5993 {
5994         struct net_device *netdev = pci_get_drvdata(pdev);
5995         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5996         pci_ers_result_t result;
5997         int err;
5998
5999         if (pci_enable_device_mem(pdev)) {
6000                 DPRINTK(PROBE, ERR,
6001                         "Cannot re-enable PCI device after reset.\n");
6002                 result = PCI_ERS_RESULT_DISCONNECT;
6003         } else {
6004                 pci_set_master(pdev);
6005                 pci_restore_state(pdev);
6006                 pci_save_state(pdev);
6007
6008                 pci_wake_from_d3(pdev, false);
6009
6010                 ixgbe_reset(adapter);
6011                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6012                 result = PCI_ERS_RESULT_RECOVERED;
6013         }
6014
6015         err = pci_cleanup_aer_uncorrect_error_status(pdev);
6016         if (err) {
6017                 dev_err(&pdev->dev,
6018                   "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", err);
6019                 /* non-fatal, continue */
6020         }
6021
6022         return result;
6023 }
6024
6025 /**
6026  * ixgbe_io_resume - called when traffic can start flowing again.
6027  * @pdev: Pointer to PCI device
6028  *
6029  * This callback is called when the error recovery driver tells us that
6030  * its OK to resume normal operation.
6031  */
6032 static void ixgbe_io_resume(struct pci_dev *pdev)
6033 {
6034         struct net_device *netdev = pci_get_drvdata(pdev);
6035         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6036
6037         if (netif_running(netdev)) {
6038                 if (ixgbe_up(adapter)) {
6039                         DPRINTK(PROBE, INFO, "ixgbe_up failed after reset\n");
6040                         return;
6041                 }
6042         }
6043
6044         netif_device_attach(netdev);
6045 }
6046
6047 static struct pci_error_handlers ixgbe_err_handler = {
6048         .error_detected = ixgbe_io_error_detected,
6049         .slot_reset = ixgbe_io_slot_reset,
6050         .resume = ixgbe_io_resume,
6051 };
6052
6053 static struct pci_driver ixgbe_driver = {
6054         .name     = ixgbe_driver_name,
6055         .id_table = ixgbe_pci_tbl,
6056         .probe    = ixgbe_probe,
6057         .remove   = __devexit_p(ixgbe_remove),
6058 #ifdef CONFIG_PM
6059         .suspend  = ixgbe_suspend,
6060         .resume   = ixgbe_resume,
6061 #endif
6062         .shutdown = ixgbe_shutdown,
6063         .err_handler = &ixgbe_err_handler
6064 };
6065
6066 /**
6067  * ixgbe_init_module - Driver Registration Routine
6068  *
6069  * ixgbe_init_module is the first routine called when the driver is
6070  * loaded. All it does is register with the PCI subsystem.
6071  **/
6072 static int __init ixgbe_init_module(void)
6073 {
6074         int ret;
6075         printk(KERN_INFO "%s: %s - version %s\n", ixgbe_driver_name,
6076                ixgbe_driver_string, ixgbe_driver_version);
6077
6078         printk(KERN_INFO "%s: %s\n", ixgbe_driver_name, ixgbe_copyright);
6079
6080 #ifdef CONFIG_IXGBE_DCA
6081         dca_register_notify(&dca_notifier);
6082 #endif
6083
6084         ret = pci_register_driver(&ixgbe_driver);
6085         return ret;
6086 }
6087
6088 module_init(ixgbe_init_module);
6089
6090 /**
6091  * ixgbe_exit_module - Driver Exit Cleanup Routine
6092  *
6093  * ixgbe_exit_module is called just before the driver is removed
6094  * from memory.
6095  **/
6096 static void __exit ixgbe_exit_module(void)
6097 {
6098 #ifdef CONFIG_IXGBE_DCA
6099         dca_unregister_notify(&dca_notifier);
6100 #endif
6101         pci_unregister_driver(&ixgbe_driver);
6102 }
6103
6104 #ifdef CONFIG_IXGBE_DCA
6105 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
6106                             void *p)
6107 {
6108         int ret_val;
6109
6110         ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
6111                                          __ixgbe_notify_dca);
6112
6113         return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
6114 }
6115
6116 #endif /* CONFIG_IXGBE_DCA */
6117 #ifdef DEBUG
6118 /**
6119  * ixgbe_get_hw_dev_name - return device name string
6120  * used by hardware layer to print debugging information
6121  **/
6122 char *ixgbe_get_hw_dev_name(struct ixgbe_hw *hw)
6123 {
6124         struct ixgbe_adapter *adapter = hw->back;
6125         return adapter->netdev->name;
6126 }
6127
6128 #endif
6129 module_exit(ixgbe_exit_module);
6130
6131 /* ixgbe_main.c */