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   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2010 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #include <linux/types.h>
  29 #include <linux/module.h>
  30 #include <linux/pci.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/vmalloc.h>
  33 #include <linux/string.h>
  34 #include <linux/in.h>
  35 #include <linux/ip.h>
  36 #include <linux/tcp.h>
  37 #include <linux/pkt_sched.h>
  38 #include <linux/ipv6.h>
  39 #include <linux/slab.h>
  40 #include <net/checksum.h>
  41 #include <net/ip6_checksum.h>
  42 #include <linux/ethtool.h>
  43 #include <linux/if_vlan.h>
  44 #include <scsi/fc/fc_fcoe.h>
  45
  46 #include "ixgbe.h"
  47 #include "ixgbe_common.h"
  48 #include "ixgbe_dcb_82599.h"
  49 #include "ixgbe_sriov.h"
  50
  51 char ixgbe_driver_name[] = "ixgbe";
  52 static const char ixgbe_driver_string[] =
  53                               "Intel(R) 10 Gigabit PCI Express Network Driver";
  54
  55 #define DRV_VERSION "2.0.62-k2"
  56 const char ixgbe_driver_version[] = DRV_VERSION;
  57 static char ixgbe_copyright[] = "Copyright (c) 1999-2010 Intel Corporation.";
  58
  59 static const struct ixgbe_info *ixgbe_info_tbl[] = {
  60         [board_82598] = &ixgbe_82598_info,
  61         [board_82599] = &ixgbe_82599_info,
  62 };
  63
  64 /* ixgbe_pci_tbl - PCI Device ID Table
  65  *
  66  * Wildcard entries (PCI_ANY_ID) should come last
  67  * Last entry must be all 0s
  68  *
  69  * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
  70  *   Class, Class Mask, private data (not used) }
  71  */
  72 static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
  73         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
  74          board_82598 },
  75         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
  76          board_82598 },
  77         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
  78          board_82598 },
  79         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
  80          board_82598 },
  81         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
  82          board_82598 },
  83         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
  84          board_82598 },
  85         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
  86          board_82598 },
  87         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
  88          board_82598 },
  89         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
  90          board_82598 },
  91         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
  92          board_82598 },
  93         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
  94          board_82598 },
  95         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
  96          board_82598 },
  97         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
  98          board_82599 },
  99         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
 100          board_82599 },
 101         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR),
 102          board_82599 },
 103         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
 104          board_82599 },
 105         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM),
 106          board_82599 },
 107         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ),
 108          board_82599 },
 109         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
 110          board_82599 },
 111         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE),
 112          board_82599 },
 113
 114         /* required last entry */
 115         {0, }
 116 };
 117 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
 118
 119 #ifdef CONFIG_IXGBE_DCA
 120 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
 121                             void *p);
 122 static struct notifier_block dca_notifier = {
 123         .notifier_call = ixgbe_notify_dca,
 124         .next          = NULL,
 125         .priority      = 0
 126 };
 127 #endif
 128
 129 #ifdef CONFIG_PCI_IOV
 130 static unsigned int max_vfs;
 131 module_param(max_vfs, uint, 0);
 132 MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate "
 133                  "per physical function");
 134 #endif /* CONFIG_PCI_IOV */
 135
 136 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
 137 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
 138 MODULE_LICENSE("GPL");
 139 MODULE_VERSION(DRV_VERSION);
 140
 141 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
 142
 143 static inline void ixgbe_disable_sriov(struct ixgbe_adapter *adapter)
 144 {
 145         struct ixgbe_hw *hw = &adapter->hw;
 146         u32 gcr;
 147         u32 gpie;
 148         u32 vmdctl;
 149
 150 #ifdef CONFIG_PCI_IOV
 151         /* disable iov and allow time for transactions to clear */
 152         pci_disable_sriov(adapter->pdev);
 153 #endif
 154
 155         /* turn off device IOV mode */
 156         gcr = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
 157         gcr &= ~(IXGBE_GCR_EXT_SRIOV);
 158         IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr);
 159         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
 160         gpie &= ~IXGBE_GPIE_VTMODE_MASK;
 161         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
 162
 163         /* set default pool back to 0 */
 164         vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
 165         vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
 166         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
 167
 168         /* take a breather then clean up driver data */
 169         msleep(100);
 170         if (adapter->vfinfo)
 171                 kfree(adapter->vfinfo);
 172         adapter->vfinfo = NULL;
 173
 174         adapter->num_vfs = 0;
 175         adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
 176 }
 177
 178 struct ixgbe_reg_info {
 179         u32 ofs;
 180         char *name;
 181 };
 182
 183 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
 184
 185         /* General Registers */
 186         {IXGBE_CTRL, "CTRL"},
 187         {IXGBE_STATUS, "STATUS"},
 188         {IXGBE_CTRL_EXT, "CTRL_EXT"},
 189
 190         /* Interrupt Registers */
 191         {IXGBE_EICR, "EICR"},
 192
 193         /* RX Registers */
 194         {IXGBE_SRRCTL(0), "SRRCTL"},
 195         {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
 196         {IXGBE_RDLEN(0), "RDLEN"},
 197         {IXGBE_RDH(0), "RDH"},
 198         {IXGBE_RDT(0), "RDT"},
 199         {IXGBE_RXDCTL(0), "RXDCTL"},
 200         {IXGBE_RDBAL(0), "RDBAL"},
 201         {IXGBE_RDBAH(0), "RDBAH"},
 202
 203         /* TX Registers */
 204         {IXGBE_TDBAL(0), "TDBAL"},
 205         {IXGBE_TDBAH(0), "TDBAH"},
 206         {IXGBE_TDLEN(0), "TDLEN"},
 207         {IXGBE_TDH(0), "TDH"},
 208         {IXGBE_TDT(0), "TDT"},
 209         {IXGBE_TXDCTL(0), "TXDCTL"},
 210
 211         /* List Terminator */
 212         {}
 213 };
 214
 215
 216 /*
 217  * ixgbe_regdump - register printout routine
 218  */
 219 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
 220 {
 221         int i = 0, j = 0;
 222         char rname[16];
 223         u32 regs[64];
 224
 225         switch (reginfo->ofs) {
 226         case IXGBE_SRRCTL(0):
 227                 for (i = 0; i < 64; i++)
 228                         regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
 229                 break;
 230         case IXGBE_DCA_RXCTRL(0):
 231                 for (i = 0; i < 64; i++)
 232                         regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
 233                 break;
 234         case IXGBE_RDLEN(0):
 235                 for (i = 0; i < 64; i++)
 236                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
 237                 break;
 238         case IXGBE_RDH(0):
 239                 for (i = 0; i < 64; i++)
 240                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
 241                 break;
 242         case IXGBE_RDT(0):
 243                 for (i = 0; i < 64; i++)
 244                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
 245                 break;
 246         case IXGBE_RXDCTL(0):
 247                 for (i = 0; i < 64; i++)
 248                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
 249                 break;
 250         case IXGBE_RDBAL(0):
 251                 for (i = 0; i < 64; i++)
 252                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
 253                 break;
 254         case IXGBE_RDBAH(0):
 255                 for (i = 0; i < 64; i++)
 256                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
 257                 break;
 258         case IXGBE_TDBAL(0):
 259                 for (i = 0; i < 64; i++)
 260                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
 261                 break;
 262         case IXGBE_TDBAH(0):
 263                 for (i = 0; i < 64; i++)
 264                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
 265                 break;
 266         case IXGBE_TDLEN(0):
 267                 for (i = 0; i < 64; i++)
 268                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
 269                 break;
 270         case IXGBE_TDH(0):
 271                 for (i = 0; i < 64; i++)
 272                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
 273                 break;
 274         case IXGBE_TDT(0):
 275                 for (i = 0; i < 64; i++)
 276                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
 277                 break;
 278         case IXGBE_TXDCTL(0):
 279                 for (i = 0; i < 64; i++)
 280                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
 281                 break;
 282         default:
 283                 printk(KERN_INFO "%-15s %08x\n", reginfo->name,
 284                         IXGBE_READ_REG(hw, reginfo->ofs));
 285                 return;
 286         }
 287
 288         for (i = 0; i < 8; i++) {
 289                 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
 290                 printk(KERN_ERR "%-15s ", rname);
 291                 for (j = 0; j < 8; j++)
 292                         printk(KERN_CONT "%08x ", regs[i*8+j]);
 293                 printk(KERN_CONT "\n");
 294         }
 295
 296 }
 297
 298 /*
 299  * ixgbe_dump - Print registers, tx-rings and rx-rings
 300  */
 301 static void ixgbe_dump(struct ixgbe_adapter *adapter)
 302 {
 303         struct net_device *netdev = adapter->netdev;
 304         struct ixgbe_hw *hw = &adapter->hw;
 305         struct ixgbe_reg_info *reginfo;
 306         int n = 0;
 307         struct ixgbe_ring *tx_ring;
 308         struct ixgbe_tx_buffer *tx_buffer_info;
 309         union ixgbe_adv_tx_desc *tx_desc;
 310         struct my_u0 { u64 a; u64 b; } *u0;
 311         struct ixgbe_ring *rx_ring;
 312         union ixgbe_adv_rx_desc *rx_desc;
 313         struct ixgbe_rx_buffer *rx_buffer_info;
 314         u32 staterr;
 315         int i = 0;
 316
 317         if (!netif_msg_hw(adapter))
 318                 return;
 319
 320         /* Print netdevice Info */
 321         if (netdev) {
 322                 dev_info(&adapter->pdev->dev, "Net device Info\n");
 323                 printk(KERN_INFO "Device Name     state            "
 324                         "trans_start      last_rx\n");
 325                 printk(KERN_INFO "%-15s %016lX %016lX %016lX\n",
 326                 netdev->name,
 327                 netdev->state,
 328                 netdev->trans_start,
 329                 netdev->last_rx);
 330         }
 331
 332         /* Print Registers */
 333         dev_info(&adapter->pdev->dev, "Register Dump\n");
 334         printk(KERN_INFO " Register Name   Value\n");
 335         for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
 336              reginfo->name; reginfo++) {
 337                 ixgbe_regdump(hw, reginfo);
 338         }
 339
 340         /* Print TX Ring Summary */
 341         if (!netdev || !netif_running(netdev))
 342                 goto exit;
 343
 344         dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
 345         printk(KERN_INFO "Queue [NTU] [NTC] [bi(ntc)->dma  ] "
 346                 "leng ntw timestamp\n");
 347         for (n = 0; n < adapter->num_tx_queues; n++) {
 348                 tx_ring = adapter->tx_ring[n];
 349                 tx_buffer_info =
 350                         &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
 351                 printk(KERN_INFO " %5d %5X %5X %016llX %04X %3X %016llX\n",
 352                            n, tx_ring->next_to_use, tx_ring->next_to_clean,
 353                            (u64)tx_buffer_info->dma,
 354                            tx_buffer_info->length,
 355                            tx_buffer_info->next_to_watch,
 356                            (u64)tx_buffer_info->time_stamp);
 357         }
 358
 359         /* Print TX Rings */
 360         if (!netif_msg_tx_done(adapter))
 361                 goto rx_ring_summary;
 362
 363         dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
 364
 365         /* Transmit Descriptor Formats
 366          *
 367          * Advanced Transmit Descriptor
 368          *   +--------------------------------------------------------------+
 369          * 0 |         Buffer Address [63:0]                                |
 370          *   +--------------------------------------------------------------+
 371          * 8 |  PAYLEN  | PORTS  | IDX | STA | DCMD  |DTYP |  RSV |  DTALEN |
 372          *   +--------------------------------------------------------------+
 373          *   63       46 45    40 39 36 35 32 31   24 23 20 19              0
 374          */
 375
 376         for (n = 0; n < adapter->num_tx_queues; n++) {
 377                 tx_ring = adapter->tx_ring[n];
 378                 printk(KERN_INFO "------------------------------------\n");
 379                 printk(KERN_INFO "TX QUEUE INDEX = %d\n", tx_ring->queue_index);
 380                 printk(KERN_INFO "------------------------------------\n");
 381                 printk(KERN_INFO "T [desc]     [address 63:0  ] "
 382                         "[PlPOIdStDDt Ln] [bi->dma       ] "
 383                         "leng  ntw timestamp        bi->skb\n");
 384
 385                 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
 386                         tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
 387                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
 388                         u0 = (struct my_u0 *)tx_desc;
 389                         printk(KERN_INFO "T [0x%03X]    %016llX %016llX %016llX"
 390                                 " %04X  %3X %016llX %p", i,
 391                                 le64_to_cpu(u0->a),
 392                                 le64_to_cpu(u0->b),
 393                                 (u64)tx_buffer_info->dma,
 394                                 tx_buffer_info->length,
 395                                 tx_buffer_info->next_to_watch,
 396                                 (u64)tx_buffer_info->time_stamp,
 397                                 tx_buffer_info->skb);
 398                         if (i == tx_ring->next_to_use &&
 399                                 i == tx_ring->next_to_clean)
 400                                 printk(KERN_CONT " NTC/U\n");
 401                         else if (i == tx_ring->next_to_use)
 402                                 printk(KERN_CONT " NTU\n");
 403                         else if (i == tx_ring->next_to_clean)
 404                                 printk(KERN_CONT " NTC\n");
 405                         else
 406                                 printk(KERN_CONT "\n");
 407
 408                         if (netif_msg_pktdata(adapter) &&
 409                                 tx_buffer_info->dma != 0)
 410                                 print_hex_dump(KERN_INFO, "",
 411                                         DUMP_PREFIX_ADDRESS, 16, 1,
 412                                         phys_to_virt(tx_buffer_info->dma),
 413                                         tx_buffer_info->length, true);
 414                 }
 415         }
 416
 417         /* Print RX Rings Summary */
 418 rx_ring_summary:
 419         dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
 420         printk(KERN_INFO "Queue [NTU] [NTC]\n");
 421         for (n = 0; n < adapter->num_rx_queues; n++) {
 422                 rx_ring = adapter->rx_ring[n];
 423                 printk(KERN_INFO "%5d %5X %5X\n", n,
 424                            rx_ring->next_to_use, rx_ring->next_to_clean);
 425         }
 426
 427         /* Print RX Rings */
 428         if (!netif_msg_rx_status(adapter))
 429                 goto exit;
 430
 431         dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
 432
 433         /* Advanced Receive Descriptor (Read) Format
 434          *    63                                           1        0
 435          *    +-----------------------------------------------------+
 436          *  0 |       Packet Buffer Address [63:1]           |A0/NSE|
 437          *    +----------------------------------------------+------+
 438          *  8 |       Header Buffer Address [63:1]           |  DD  |
 439          *    +-----------------------------------------------------+
 440          *
 441          *
 442          * Advanced Receive Descriptor (Write-Back) Format
 443          *
 444          *   63       48 47    32 31  30      21 20 16 15   4 3     0
 445          *   +------------------------------------------------------+
 446          * 0 | Packet     IP     |SPH| HDR_LEN   | RSV|Packet|  RSS |
 447          *   | Checksum   Ident  |   |           |    | Type | Type |
 448          *   +------------------------------------------------------+
 449          * 8 | VLAN Tag | Length | Extended Error | Extended Status |
 450          *   +------------------------------------------------------+
 451          *   63       48 47    32 31            20 19               0
 452          */
 453         for (n = 0; n < adapter->num_rx_queues; n++) {
 454                 rx_ring = adapter->rx_ring[n];
 455                 printk(KERN_INFO "------------------------------------\n");
 456                 printk(KERN_INFO "RX QUEUE INDEX = %d\n", rx_ring->queue_index);
 457                 printk(KERN_INFO "------------------------------------\n");
 458                 printk(KERN_INFO "R  [desc]      [ PktBuf     A0] "
 459                         "[  HeadBuf   DD] [bi->dma       ] [bi->skb] "
 460                         "<-- Adv Rx Read format\n");
 461                 printk(KERN_INFO "RWB[desc]      [PcsmIpSHl PtRs] "
 462                         "[vl er S cks ln] ---------------- [bi->skb] "
 463                         "<-- Adv Rx Write-Back format\n");
 464
 465                 for (i = 0; i < rx_ring->count; i++) {
 466                         rx_buffer_info = &rx_ring->rx_buffer_info[i];
 467                         rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
 468                         u0 = (struct my_u0 *)rx_desc;
 469                         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
 470                         if (staterr & IXGBE_RXD_STAT_DD) {
 471                                 /* Descriptor Done */
 472                                 printk(KERN_INFO "RWB[0x%03X]     %016llX "
 473                                         "%016llX ---------------- %p", i,
 474                                         le64_to_cpu(u0->a),
 475                                         le64_to_cpu(u0->b),
 476                                         rx_buffer_info->skb);
 477                         } else {
 478                                 printk(KERN_INFO "R  [0x%03X]     %016llX "
 479                                         "%016llX %016llX %p", i,
 480                                         le64_to_cpu(u0->a),
 481                                         le64_to_cpu(u0->b),
 482                                         (u64)rx_buffer_info->dma,
 483                                         rx_buffer_info->skb);
 484
 485                                 if (netif_msg_pktdata(adapter)) {
 486                                         print_hex_dump(KERN_INFO, "",
 487                                            DUMP_PREFIX_ADDRESS, 16, 1,
 488                                            phys_to_virt(rx_buffer_info->dma),
 489                                            rx_ring->rx_buf_len, true);
 490
 491                                         if (rx_ring->rx_buf_len
 492                                                 < IXGBE_RXBUFFER_2048)
 493                                                 print_hex_dump(KERN_INFO, "",
 494                                                   DUMP_PREFIX_ADDRESS, 16, 1,
 495                                                   phys_to_virt(
 496                                                     rx_buffer_info->page_dma +
 497                                                     rx_buffer_info->page_offset
 498                                                   ),
 499                                                   PAGE_SIZE/2, true);
 500                                 }
 501                         }
 502
 503                         if (i == rx_ring->next_to_use)
 504                                 printk(KERN_CONT " NTU\n");
 505                         else if (i == rx_ring->next_to_clean)
 506                                 printk(KERN_CONT " NTC\n");
 507                         else
 508                                 printk(KERN_CONT "\n");
 509
 510                 }
 511         }
 512
 513 exit:
 514         return;
 515 }
 516
 517 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
 518 {
 519         u32 ctrl_ext;
 520
 521         /* Let firmware take over control of h/w */
 522         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 523         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 524                         ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
 525 }
 526
 527 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
 528 {
 529         u32 ctrl_ext;
 530
 531         /* Let firmware know the driver has taken over */
 532         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 533         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 534                         ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
 535 }
 536
 537 /*
 538  * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
 539  * @adapter: pointer to adapter struct
 540  * @direction: 0 for Rx, 1 for Tx, -1 for other causes
 541  * @queue: queue to map the corresponding interrupt to
 542  * @msix_vector: the vector to map to the corresponding queue
 543  *
 544  */
 545 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
 546                            u8 queue, u8 msix_vector)
 547 {
 548         u32 ivar, index;
 549         struct ixgbe_hw *hw = &adapter->hw;
 550         switch (hw->mac.type) {
 551         case ixgbe_mac_82598EB:
 552                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 553                 if (direction == -1)
 554                         direction = 0;
 555                 index = (((direction * 64) + queue) >> 2) & 0x1F;
 556                 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
 557                 ivar &= ~(0xFF << (8 * (queue & 0x3)));
 558                 ivar |= (msix_vector << (8 * (queue & 0x3)));
 559                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
 560                 break;
 561         case ixgbe_mac_82599EB:
 562                 if (direction == -1) {
 563                         /* other causes */
 564                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 565                         index = ((queue & 1) * 8);
 566                         ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
 567                         ivar &= ~(0xFF << index);
 568                         ivar |= (msix_vector << index);
 569                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
 570                         break;
 571                 } else {
 572                         /* tx or rx causes */
 573                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 574                         index = ((16 * (queue & 1)) + (8 * direction));
 575                         ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
 576                         ivar &= ~(0xFF << index);
 577                         ivar |= (msix_vector << index);
 578                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
 579                         break;
 580                 }
 581         default:
 582                 break;
 583         }
 584 }
 585
 586 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
 587                                           u64 qmask)
 588 {
 589         u32 mask;
 590
 591         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 592                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
 593                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
 594         } else {
 595                 mask = (qmask & 0xFFFFFFFF);
 596                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
 597                 mask = (qmask >> 32);
 598                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
 599         }
 600 }
 601
 602 static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
 603                                              struct ixgbe_tx_buffer
 604                                              *tx_buffer_info)
 605 {
 606         if (tx_buffer_info->dma) {
 607                 if (tx_buffer_info->mapped_as_page)
 608                         dma_unmap_page(&adapter->pdev->dev,
 609                                        tx_buffer_info->dma,
 610                                        tx_buffer_info->length,
 611                                        DMA_TO_DEVICE);
 612                 else
 613                         dma_unmap_single(&adapter->pdev->dev,
 614                                          tx_buffer_info->dma,
 615                                          tx_buffer_info->length,
 616                                          DMA_TO_DEVICE);
 617                 tx_buffer_info->dma = 0;
 618         }
 619         if (tx_buffer_info->skb) {
 620                 dev_kfree_skb_any(tx_buffer_info->skb);
 621                 tx_buffer_info->skb = NULL;
 622         }
 623         tx_buffer_info->time_stamp = 0;
 624         /* tx_buffer_info must be completely set up in the transmit path */
 625 }
 626
 627 /**
 628  * ixgbe_tx_xon_state - check the tx ring xon state
 629  * @adapter: the ixgbe adapter
 630  * @tx_ring: the corresponding tx_ring
 631  *
 632  * If not in DCB mode, checks TFCS.TXOFF, otherwise, find out the
 633  * corresponding TC of this tx_ring when checking TFCS.
 634  *
 635  * Returns : true if in xon state (currently not paused)
 636  */
 637 static inline bool ixgbe_tx_xon_state(struct ixgbe_adapter *adapter,
 638                                       struct ixgbe_ring *tx_ring)
 639 {
 640         u32 txoff = IXGBE_TFCS_TXOFF;
 641
 642 #ifdef CONFIG_IXGBE_DCB
 643         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
 644                 int tc;
 645                 int reg_idx = tx_ring->reg_idx;
 646                 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
 647
 648                 switch (adapter->hw.mac.type) {
 649                 case ixgbe_mac_82598EB:
 650                         tc = reg_idx >> 2;
 651                         txoff = IXGBE_TFCS_TXOFF0;
 652                         break;
 653                 case ixgbe_mac_82599EB:
 654                         tc = 0;
 655                         txoff = IXGBE_TFCS_TXOFF;
 656                         if (dcb_i == 8) {
 657                                 /* TC0, TC1 */
 658                                 tc = reg_idx >> 5;
 659                                 if (tc == 2) /* TC2, TC3 */
 660                                         tc += (reg_idx - 64) >> 4;
 661                                 else if (tc == 3) /* TC4, TC5, TC6, TC7 */
 662                                         tc += 1 + ((reg_idx - 96) >> 3);
 663                         } else if (dcb_i == 4) {
 664                                 /* TC0, TC1 */
 665                                 tc = reg_idx >> 6;
 666                                 if (tc == 1) {
 667                                         tc += (reg_idx - 64) >> 5;
 668                                         if (tc == 2) /* TC2, TC3 */
 669                                                 tc += (reg_idx - 96) >> 4;
 670                                 }
 671                         }
 672                         break;
 673                 default:
 674                         tc = 0;
 675                 }
 676                 txoff <<= tc;
 677         }
 678 #endif
 679         return IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & txoff;
 680 }
 681
 682 static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
 683                                        struct ixgbe_ring *tx_ring,
 684                                        unsigned int eop)
 685 {
 686         struct ixgbe_hw *hw = &adapter->hw;
 687
 688         /* Detect a transmit hang in hardware, this serializes the
 689          * check with the clearing of time_stamp and movement of eop */
 690         adapter->detect_tx_hung = false;
 691         if (tx_ring->tx_buffer_info[eop].time_stamp &&
 692             time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
 693             ixgbe_tx_xon_state(adapter, tx_ring)) {
 694                 /* detected Tx unit hang */
 695                 union ixgbe_adv_tx_desc *tx_desc;
 696                 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
 697                 DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
 698                         "  Tx Queue             <%d>\n"
 699                         "  TDH, TDT             <%x>, <%x>\n"
 700                         "  next_to_use          <%x>\n"
 701                         "  next_to_clean        <%x>\n"
 702                         "tx_buffer_info[next_to_clean]\n"
 703                         "  time_stamp           <%lx>\n"
 704                         "  jiffies              <%lx>\n",
 705                         tx_ring->queue_index,
 706                         IXGBE_READ_REG(hw, tx_ring->head),
 707                         IXGBE_READ_REG(hw, tx_ring->tail),
 708                         tx_ring->next_to_use, eop,
 709                         tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
 710                 return true;
 711         }
 712
 713         return false;
 714 }
 715
 716 #define IXGBE_MAX_TXD_PWR       14
 717 #define IXGBE_MAX_DATA_PER_TXD  (1 << IXGBE_MAX_TXD_PWR)
 718
 719 /* Tx Descriptors needed, worst case */
 720 #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
 721                          (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
 722 #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
 723         MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
 724
 725 static void ixgbe_tx_timeout(struct net_device *netdev);
 726
 727 /**
 728  * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
 729  * @q_vector: structure containing interrupt and ring information
 730  * @tx_ring: tx ring to clean
 731  **/
 732 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
 733                                struct ixgbe_ring *tx_ring)
 734 {
 735         struct ixgbe_adapter *adapter = q_vector->adapter;
 736         struct net_device *netdev = adapter->netdev;
 737         union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
 738         struct ixgbe_tx_buffer *tx_buffer_info;
 739         unsigned int i, eop, count = 0;
 740         unsigned int total_bytes = 0, total_packets = 0;
 741
 742         i = tx_ring->next_to_clean;
 743         eop = tx_ring->tx_buffer_info[i].next_to_watch;
 744         eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
 745
 746         while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
 747                (count < tx_ring->work_limit)) {
 748                 bool cleaned = false;
 749                 for ( ; !cleaned; count++) {
 750                         struct sk_buff *skb;
 751                         tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
 752                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
 753                         cleaned = (i == eop);
 754                         skb = tx_buffer_info->skb;
 755
 756                         if (cleaned && skb) {
 757                                 unsigned int segs, bytecount;
 758                                 unsigned int hlen = skb_headlen(skb);
 759
 760                                 /* gso_segs is currently only valid for tcp */
 761                                 segs = skb_shinfo(skb)->gso_segs ?: 1;
 762 #ifdef IXGBE_FCOE
 763                                 /* adjust for FCoE Sequence Offload */
 764                                 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
 765                                     && (skb->protocol == htons(ETH_P_FCOE)) &&
 766                                     skb_is_gso(skb)) {
 767                                         hlen = skb_transport_offset(skb) +
 768                                                 sizeof(struct fc_frame_header) +
 769                                                 sizeof(struct fcoe_crc_eof);
 770                                         segs = DIV_ROUND_UP(skb->len - hlen,
 771                                                 skb_shinfo(skb)->gso_size);
 772                                 }
 773 #endif /* IXGBE_FCOE */
 774                                 /* multiply data chunks by size of headers */
 775                                 bytecount = ((segs - 1) * hlen) + skb->len;
 776                                 total_packets += segs;
 777                                 total_bytes += bytecount;
 778                         }
 779
 780                         ixgbe_unmap_and_free_tx_resource(adapter,
 781                                                          tx_buffer_info);
 782
 783                         tx_desc->wb.status = 0;
 784
 785                         i++;
 786                         if (i == tx_ring->count)
 787                                 i = 0;
 788                 }
 789
 790                 eop = tx_ring->tx_buffer_info[i].next_to_watch;
 791                 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
 792         }
 793
 794         tx_ring->next_to_clean = i;
 795
 796 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
 797         if (unlikely(count && netif_carrier_ok(netdev) &&
 798                      (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
 799                 /* Make sure that anybody stopping the queue after this
 800                  * sees the new next_to_clean.
 801                  */
 802                 smp_mb();
 803                 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
 804                     !test_bit(__IXGBE_DOWN, &adapter->state)) {
 805                         netif_wake_subqueue(netdev, tx_ring->queue_index);
 806                         ++tx_ring->restart_queue;
 807                 }
 808         }
 809
 810         if (adapter->detect_tx_hung) {
 811                 if (ixgbe_check_tx_hang(adapter, tx_ring, i)) {
 812                         /* schedule immediate reset if we believe we hung */
 813                         DPRINTK(PROBE, INFO,
 814                                 "tx hang %d detected, resetting adapter\n",
 815                                 adapter->tx_timeout_count + 1);
 816                         ixgbe_tx_timeout(adapter->netdev);
 817                 }
 818         }
 819
 820         /* re-arm the interrupt */
 821         if (count >= tx_ring->work_limit)
 822                 ixgbe_irq_rearm_queues(adapter, ((u64)1 << q_vector->v_idx));
 823
 824         tx_ring->total_bytes += total_bytes;
 825         tx_ring->total_packets += total_packets;
 826         tx_ring->stats.packets += total_packets;
 827         tx_ring->stats.bytes += total_bytes;
 828         return (count < tx_ring->work_limit);
 829 }
 830
 831 #ifdef CONFIG_IXGBE_DCA
 832 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
 833                                 struct ixgbe_ring *rx_ring)
 834 {
 835         u32 rxctrl;
 836         int cpu = get_cpu();
 837         int q = rx_ring->reg_idx;
 838
 839         if (rx_ring->cpu != cpu) {
 840                 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
 841                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 842                         rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
 843                         rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 844                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
 845                         rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
 846                         rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
 847                                    IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
 848                 }
 849                 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
 850                 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
 851                 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
 852                 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
 853                             IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
 854                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
 855                 rx_ring->cpu = cpu;
 856         }
 857         put_cpu();
 858 }
 859
 860 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
 861                                 struct ixgbe_ring *tx_ring)
 862 {
 863         u32 txctrl;
 864         int cpu = get_cpu();
 865         int q = tx_ring->reg_idx;
 866         struct ixgbe_hw *hw = &adapter->hw;
 867
 868         if (tx_ring->cpu != cpu) {
 869                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 870                         txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(q));
 871                         txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
 872                         txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 873                         txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
 874                         IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(q), txctrl);
 875                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
 876                         txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(q));
 877                         txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
 878                         txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
 879                                   IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
 880                         txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
 881                         IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(q), txctrl);
 882                 }
 883                 tx_ring->cpu = cpu;
 884         }
 885         put_cpu();
 886 }
 887
 888 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
 889 {
 890         int i;
 891
 892         if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
 893                 return;
 894
 895         /* always use CB2 mode, difference is masked in the CB driver */
 896         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
 897
 898         for (i = 0; i < adapter->num_tx_queues; i++) {
 899                 adapter->tx_ring[i]->cpu = -1;
 900                 ixgbe_update_tx_dca(adapter, adapter->tx_ring[i]);
 901         }
 902         for (i = 0; i < adapter->num_rx_queues; i++) {
 903                 adapter->rx_ring[i]->cpu = -1;
 904                 ixgbe_update_rx_dca(adapter, adapter->rx_ring[i]);
 905         }
 906 }
 907
 908 static int __ixgbe_notify_dca(struct device *dev, void *data)
 909 {
 910         struct net_device *netdev = dev_get_drvdata(dev);
 911         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 912         unsigned long event = *(unsigned long *)data;
 913
 914         switch (event) {
 915         case DCA_PROVIDER_ADD:
 916                 /* if we're already enabled, don't do it again */
 917                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
 918                         break;
 919                 if (dca_add_requester(dev) == 0) {
 920                         adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
 921                         ixgbe_setup_dca(adapter);
 922                         break;
 923                 }
 924                 /* Fall Through since DCA is disabled. */
 925         case DCA_PROVIDER_REMOVE:
 926                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
 927                         dca_remove_requester(dev);
 928                         adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
 929                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
 930                 }
 931                 break;
 932         }
 933
 934         return 0;
 935 }
 936
 937 #endif /* CONFIG_IXGBE_DCA */
 938 /**
 939  * ixgbe_receive_skb - Send a completed packet up the stack
 940  * @adapter: board private structure
 941  * @skb: packet to send up
 942  * @status: hardware indication of status of receive
 943  * @rx_ring: rx descriptor ring (for a specific queue) to setup
 944  * @rx_desc: rx descriptor
 945  **/
 946 static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
 947                               struct sk_buff *skb, u8 status,
 948                               struct ixgbe_ring *ring,
 949                               union ixgbe_adv_rx_desc *rx_desc)
 950 {
 951         struct ixgbe_adapter *adapter = q_vector->adapter;
 952         struct napi_struct *napi = &q_vector->napi;
 953         bool is_vlan = (status & IXGBE_RXD_STAT_VP);
 954         u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
 955
 956         skb_record_rx_queue(skb, ring->queue_index);
 957         if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) {
 958                 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
 959                         vlan_gro_receive(napi, adapter->vlgrp, tag, skb);
 960                 else
 961                         napi_gro_receive(napi, skb);
 962         } else {
 963                 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
 964                         vlan_hwaccel_rx(skb, adapter->vlgrp, tag);
 965                 else
 966                         netif_rx(skb);
 967         }
 968 }
 969
 970 /**
 971  * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
 972  * @adapter: address of board private structure
 973  * @status_err: hardware indication of status of receive
 974  * @skb: skb currently being received and modified
 975  **/
 976 static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
 977                                      union ixgbe_adv_rx_desc *rx_desc,
 978                                      struct sk_buff *skb)
 979 {
 980         u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error);
 981
 982         skb->ip_summed = CHECKSUM_NONE;
 983
 984         /* Rx csum disabled */
 985         if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
 986                 return;
 987
 988         /* if IP and error */
 989         if ((status_err & IXGBE_RXD_STAT_IPCS) &&
 990             (status_err & IXGBE_RXDADV_ERR_IPE)) {
 991                 adapter->hw_csum_rx_error++;
 992                 return;
 993         }
 994
 995         if (!(status_err & IXGBE_RXD_STAT_L4CS))
 996                 return;
 997
 998         if (status_err & IXGBE_RXDADV_ERR_TCPE) {
 999                 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1000
1001                 /*
1002                  * 82599 errata, UDP frames with a 0 checksum can be marked as
1003                  * checksum errors.
1004                  */
1005                 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
1006                     (adapter->hw.mac.type == ixgbe_mac_82599EB))
1007                         return;
1008
1009                 adapter->hw_csum_rx_error++;
1010                 return;
1011         }
1012
1013         /* It must be a TCP or UDP packet with a valid checksum */
1014         skb->ip_summed = CHECKSUM_UNNECESSARY;
1015 }
1016
1017 static inline void ixgbe_release_rx_desc(struct ixgbe_hw *hw,
1018                                          struct ixgbe_ring *rx_ring, u32 val)
1019 {
1020         /*
1021          * Force memory writes to complete before letting h/w
1022          * know there are new descriptors to fetch.  (Only
1023          * applicable for weak-ordered memory model archs,
1024          * such as IA-64).
1025          */
1026         wmb();
1027         IXGBE_WRITE_REG(hw, IXGBE_RDT(rx_ring->reg_idx), val);
1028 }
1029
1030 /**
1031  * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
1032  * @adapter: address of board private structure
1033  **/
1034 static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
1035                                    struct ixgbe_ring *rx_ring,
1036                                    int cleaned_count)
1037 {
1038         struct pci_dev *pdev = adapter->pdev;
1039         union ixgbe_adv_rx_desc *rx_desc;
1040         struct ixgbe_rx_buffer *bi;
1041         unsigned int i;
1042
1043         i = rx_ring->next_to_use;
1044         bi = &rx_ring->rx_buffer_info[i];
1045
1046         while (cleaned_count--) {
1047                 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
1048
1049                 if (!bi->page_dma &&
1050                     (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)) {
1051                         if (!bi->page) {
1052                                 bi->page = alloc_page(GFP_ATOMIC);
1053                                 if (!bi->page) {
1054                                         adapter->alloc_rx_page_failed++;
1055                                         goto no_buffers;
1056                                 }
1057                                 bi->page_offset = 0;
1058                         } else {
1059                                 /* use a half page if we're re-using */
1060                                 bi->page_offset ^= (PAGE_SIZE / 2);
1061                         }
1062
1063                         bi->page_dma = dma_map_page(&pdev->dev, bi->page,
1064                                                     bi->page_offset,
1065                                                     (PAGE_SIZE / 2),
1066                                                     DMA_FROM_DEVICE);
1067                 }
1068
1069                 if (!bi->skb) {
1070                         struct sk_buff *skb;
1071                         /* netdev_alloc_skb reserves 32 bytes up front!! */
1072                         uint bufsz = rx_ring->rx_buf_len + SMP_CACHE_BYTES;
1073                         skb = netdev_alloc_skb(adapter->netdev, bufsz);
1074
1075                         if (!skb) {
1076                                 adapter->alloc_rx_buff_failed++;
1077                                 goto no_buffers;
1078                         }
1079
1080                         /* advance the data pointer to the next cache line */
1081                         skb_reserve(skb, (PTR_ALIGN(skb->data, SMP_CACHE_BYTES)
1082                                           - skb->data));
1083
1084                         bi->skb = skb;
1085                         bi->dma = dma_map_single(&pdev->dev, skb->data,
1086                                                  rx_ring->rx_buf_len,
1087                                                  DMA_FROM_DEVICE);
1088                 }
1089                 /* Refresh the desc even if buffer_addrs didn't change because
1090                  * each write-back erases this info. */
1091                 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
1092                         rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
1093                         rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
1094                 } else {
1095                         rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
1096                 }
1097
1098                 i++;
1099                 if (i == rx_ring->count)
1100                         i = 0;
1101                 bi = &rx_ring->rx_buffer_info[i];
1102         }
1103
1104 no_buffers:
1105         if (rx_ring->next_to_use != i) {
1106                 rx_ring->next_to_use = i;
1107                 if (i-- == 0)
1108                         i = (rx_ring->count - 1);
1109
1110                 ixgbe_release_rx_desc(&adapter->hw, rx_ring, i);
1111         }
1112 }
1113
1114 static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
1115 {
1116         return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
1117 }
1118
1119 static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
1120 {
1121         return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1122 }
1123
1124 static inline u32 ixgbe_get_rsc_count(union ixgbe_adv_rx_desc *rx_desc)
1125 {
1126         return (le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
1127                 IXGBE_RXDADV_RSCCNT_MASK) >>
1128                 IXGBE_RXDADV_RSCCNT_SHIFT;
1129 }
1130
1131 /**
1132  * ixgbe_transform_rsc_queue - change rsc queue into a full packet
1133  * @skb: pointer to the last skb in the rsc queue
1134  * @count: pointer to number of packets coalesced in this context
1135  *
1136  * This function changes a queue full of hw rsc buffers into a completed
1137  * packet.  It uses the ->prev pointers to find the first packet and then
1138  * turns it into the frag list owner.
1139  **/
1140 static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb,
1141                                                         u64 *count)
1142 {
1143         unsigned int frag_list_size = 0;
1144
1145         while (skb->prev) {
1146                 struct sk_buff *prev = skb->prev;
1147                 frag_list_size += skb->len;
1148                 skb->prev = NULL;
1149                 skb = prev;
1150                 *count += 1;
1151         }
1152
1153         skb_shinfo(skb)->frag_list = skb->next;
1154         skb->next = NULL;
1155         skb->len += frag_list_size;
1156         skb->data_len += frag_list_size;
1157         skb->truesize += frag_list_size;
1158         return skb;
1159 }
1160
1161 struct ixgbe_rsc_cb {
1162         dma_addr_t dma;
1163         bool delay_unmap;
1164 };
1165
1166 #define IXGBE_RSC_CB(skb) ((struct ixgbe_rsc_cb *)(skb)->cb)
1167
1168 static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
1169                                struct ixgbe_ring *rx_ring,
1170                                int *work_done, int work_to_do)
1171 {
1172         struct ixgbe_adapter *adapter = q_vector->adapter;
1173         struct net_device *netdev = adapter->netdev;
1174         struct pci_dev *pdev = adapter->pdev;
1175         union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
1176         struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
1177         struct sk_buff *skb;
1178         unsigned int i, rsc_count = 0;
1179         u32 len, staterr;
1180         u16 hdr_info;
1181         bool cleaned = false;
1182         int cleaned_count = 0;
1183         unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1184 #ifdef IXGBE_FCOE
1185         int ddp_bytes = 0;
1186 #endif /* IXGBE_FCOE */
1187
1188         i = rx_ring->next_to_clean;
1189         rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
1190         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1191         rx_buffer_info = &rx_ring->rx_buffer_info[i];
1192
1193         while (staterr & IXGBE_RXD_STAT_DD) {
1194                 u32 upper_len = 0;
1195                 if (*work_done >= work_to_do)
1196                         break;
1197                 (*work_done)++;
1198
1199                 rmb(); /* read descriptor and rx_buffer_info after status DD */
1200                 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
1201                         hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
1202                         len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
1203                                IXGBE_RXDADV_HDRBUFLEN_SHIFT;
1204                         upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1205                         if ((len > IXGBE_RX_HDR_SIZE) ||
1206                             (upper_len && !(hdr_info & IXGBE_RXDADV_SPH)))
1207                                 len = IXGBE_RX_HDR_SIZE;
1208                 } else {
1209                         len = le16_to_cpu(rx_desc->wb.upper.length);
1210                 }
1211
1212                 cleaned = true;
1213                 skb = rx_buffer_info->skb;
1214                 prefetch(skb->data);
1215                 rx_buffer_info->skb = NULL;
1216
1217                 if (rx_buffer_info->dma) {
1218                         if ((adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
1219                             (!(staterr & IXGBE_RXD_STAT_EOP)) &&
1220                                  (!(skb->prev))) {
1221                                 /*
1222                                  * When HWRSC is enabled, delay unmapping
1223                                  * of the first packet. It carries the
1224                                  * header information, HW may still
1225                                  * access the header after the writeback.
1226                                  * Only unmap it when EOP is reached
1227                                  */
1228                                 IXGBE_RSC_CB(skb)->delay_unmap = true;
1229                                 IXGBE_RSC_CB(skb)->dma = rx_buffer_info->dma;
1230                         } else {
1231                                 dma_unmap_single(&pdev->dev,
1232                                                  rx_buffer_info->dma,
1233                                                  rx_ring->rx_buf_len,
1234                                                  DMA_FROM_DEVICE);
1235                         }
1236                         rx_buffer_info->dma = 0;
1237                         skb_put(skb, len);
1238                 }
1239
1240                 if (upper_len) {
1241                         dma_unmap_page(&pdev->dev, rx_buffer_info->page_dma,
1242                                        PAGE_SIZE / 2, DMA_FROM_DEVICE);
1243                         rx_buffer_info->page_dma = 0;
1244                         skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
1245                                            rx_buffer_info->page,
1246                                            rx_buffer_info->page_offset,
1247                                            upper_len);
1248
1249                         if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
1250                             (page_count(rx_buffer_info->page) != 1))
1251                                 rx_buffer_info->page = NULL;
1252                         else
1253                                 get_page(rx_buffer_info->page);
1254
1255                         skb->len += upper_len;
1256                         skb->data_len += upper_len;
1257                         skb->truesize += upper_len;
1258                 }
1259
1260                 i++;
1261                 if (i == rx_ring->count)
1262                         i = 0;
1263
1264                 next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i);
1265                 prefetch(next_rxd);
1266                 cleaned_count++;
1267
1268                 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
1269                         rsc_count = ixgbe_get_rsc_count(rx_desc);
1270
1271                 if (rsc_count) {
1272                         u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
1273                                      IXGBE_RXDADV_NEXTP_SHIFT;
1274                         next_buffer = &rx_ring->rx_buffer_info[nextp];
1275                 } else {
1276                         next_buffer = &rx_ring->rx_buffer_info[i];
1277                 }
1278
1279                 if (staterr & IXGBE_RXD_STAT_EOP) {
1280                         if (skb->prev)
1281                                 skb = ixgbe_transform_rsc_queue(skb, &(rx_ring->rsc_count));
1282                         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
1283                                 if (IXGBE_RSC_CB(skb)->delay_unmap) {
1284                                         dma_unmap_single(&pdev->dev,
1285                                                          IXGBE_RSC_CB(skb)->dma,
1286                                                          rx_ring->rx_buf_len,
1287                                                          DMA_FROM_DEVICE);
1288                                         IXGBE_RSC_CB(skb)->dma = 0;
1289                                         IXGBE_RSC_CB(skb)->delay_unmap = false;
1290                                 }
1291                                 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)
1292                                         rx_ring->rsc_count += skb_shinfo(skb)->nr_frags;
1293                                 else
1294                                         rx_ring->rsc_count++;
1295                                 rx_ring->rsc_flush++;
1296                         }
1297                         rx_ring->stats.packets++;
1298                         rx_ring->stats.bytes += skb->len;
1299                 } else {
1300                         if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
1301                                 rx_buffer_info->skb = next_buffer->skb;
1302                                 rx_buffer_info->dma = next_buffer->dma;
1303                                 next_buffer->skb = skb;
1304                                 next_buffer->dma = 0;
1305                         } else {
1306                                 skb->next = next_buffer->skb;
1307                                 skb->next->prev = skb;
1308                         }
1309                         rx_ring->non_eop_descs++;
1310                         goto next_desc;
1311                 }
1312
1313                 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
1314                         dev_kfree_skb_irq(skb);
1315                         goto next_desc;
1316                 }
1317
1318                 ixgbe_rx_checksum(adapter, rx_desc, skb);
1319
1320                 /* probably a little skewed due to removing CRC */
1321                 total_rx_bytes += skb->len;
1322                 total_rx_packets++;
1323
1324                 skb->protocol = eth_type_trans(skb, adapter->netdev);
1325 #ifdef IXGBE_FCOE
1326                 /* if ddp, not passing to ULD unless for FCP_RSP or error */
1327                 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
1328                         ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
1329                         if (!ddp_bytes)
1330                                 goto next_desc;
1331                 }
1332 #endif /* IXGBE_FCOE */
1333                 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
1334
1335 next_desc:
1336                 rx_desc->wb.upper.status_error = 0;
1337
1338                 /* return some buffers to hardware, one at a time is too slow */
1339                 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
1340                         ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
1341                         cleaned_count = 0;
1342                 }
1343
1344                 /* use prefetched values */
1345                 rx_desc = next_rxd;
1346                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
1347
1348                 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1349         }
1350
1351         rx_ring->next_to_clean = i;
1352         cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
1353
1354         if (cleaned_count)
1355                 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
1356
1357 #ifdef IXGBE_FCOE
1358         /* include DDPed FCoE data */
1359         if (ddp_bytes > 0) {
1360                 unsigned int mss;
1361
1362                 mss = adapter->netdev->mtu - sizeof(struct fcoe_hdr) -
1363                         sizeof(struct fc_frame_header) -
1364                         sizeof(struct fcoe_crc_eof);
1365                 if (mss > 512)
1366                         mss &= ~511;
1367                 total_rx_bytes += ddp_bytes;
1368                 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1369         }
1370 #endif /* IXGBE_FCOE */
1371
1372         rx_ring->total_packets += total_rx_packets;
1373         rx_ring->total_bytes += total_rx_bytes;
1374         netdev->stats.rx_bytes += total_rx_bytes;
1375         netdev->stats.rx_packets += total_rx_packets;
1376
1377         return cleaned;
1378 }
1379
1380 static int ixgbe_clean_rxonly(struct napi_struct *, int);
1381 /**
1382  * ixgbe_configure_msix - Configure MSI-X hardware
1383  * @adapter: board private structure
1384  *
1385  * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1386  * interrupts.
1387  **/
1388 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1389 {
1390         struct ixgbe_q_vector *q_vector;
1391         int i, j, q_vectors, v_idx, r_idx;
1392         u32 mask;
1393
1394         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1395
1396         /*
1397          * Populate the IVAR table and set the ITR values to the
1398          * corresponding register.
1399          */
1400         for (v_idx = 0; v_idx < q_vectors; v_idx++) {
1401                 q_vector = adapter->q_vector[v_idx];
1402                 /* XXX for_each_set_bit(...) */
1403                 r_idx = find_first_bit(q_vector->rxr_idx,
1404                                        adapter->num_rx_queues);
1405
1406                 for (i = 0; i < q_vector->rxr_count; i++) {
1407                         j = adapter->rx_ring[r_idx]->reg_idx;
1408                         ixgbe_set_ivar(adapter, 0, j, v_idx);
1409                         r_idx = find_next_bit(q_vector->rxr_idx,
1410                                               adapter->num_rx_queues,
1411                                               r_idx + 1);
1412                 }
1413                 r_idx = find_first_bit(q_vector->txr_idx,
1414                                        adapter->num_tx_queues);
1415
1416                 for (i = 0; i < q_vector->txr_count; i++) {
1417                         j = adapter->tx_ring[r_idx]->reg_idx;
1418                         ixgbe_set_ivar(adapter, 1, j, v_idx);
1419                         r_idx = find_next_bit(q_vector->txr_idx,
1420                                               adapter->num_tx_queues,
1421                                               r_idx + 1);
1422                 }
1423
1424                 if (q_vector->txr_count && !q_vector->rxr_count)
1425                         /* tx only */
1426                         q_vector->eitr = adapter->tx_eitr_param;
1427                 else if (q_vector->rxr_count)
1428                         /* rx or mixed */
1429                         q_vector->eitr = adapter->rx_eitr_param;
1430
1431                 ixgbe_write_eitr(q_vector);
1432         }
1433
1434         if (adapter->hw.mac.type == ixgbe_mac_82598EB)
1435                 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
1436                                v_idx);
1437         else if (adapter->hw.mac.type == ixgbe_mac_82599EB)
1438                 ixgbe_set_ivar(adapter, -1, 1, v_idx);
1439         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1440
1441         /* set up to autoclear timer, and the vectors */
1442         mask = IXGBE_EIMS_ENABLE_MASK;
1443         if (adapter->num_vfs)
1444                 mask &= ~(IXGBE_EIMS_OTHER |
1445                           IXGBE_EIMS_MAILBOX |
1446                           IXGBE_EIMS_LSC);
1447         else
1448                 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
1449         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
1450 }
1451
1452 enum latency_range {
1453         lowest_latency = 0,
1454         low_latency = 1,
1455         bulk_latency = 2,
1456         latency_invalid = 255
1457 };
1458
1459 /**
1460  * ixgbe_update_itr - update the dynamic ITR value based on statistics
1461  * @adapter: pointer to adapter
1462  * @eitr: eitr setting (ints per sec) to give last timeslice
1463  * @itr_setting: current throttle rate in ints/second
1464  * @packets: the number of packets during this measurement interval
1465  * @bytes: the number of bytes during this measurement interval
1466  *
1467  *      Stores a new ITR value based on packets and byte
1468  *      counts during the last interrupt.  The advantage of per interrupt
1469  *      computation is faster updates and more accurate ITR for the current
1470  *      traffic pattern.  Constants in this function were computed
1471  *      based on theoretical maximum wire speed and thresholds were set based
1472  *      on testing data as well as attempting to minimize response time
1473  *      while increasing bulk throughput.
1474  *      this functionality is controlled by the InterruptThrottleRate module
1475  *      parameter (see ixgbe_param.c)
1476  **/
1477 static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
1478                            u32 eitr, u8 itr_setting,
1479                            int packets, int bytes)
1480 {
1481         unsigned int retval = itr_setting;
1482         u32 timepassed_us;
1483         u64 bytes_perint;
1484
1485         if (packets == 0)
1486                 goto update_itr_done;
1487
1488
1489         /* simple throttlerate management
1490          *    0-20MB/s lowest (100000 ints/s)
1491          *   20-100MB/s low   (20000 ints/s)
1492          *  100-1249MB/s bulk (8000 ints/s)
1493          */
1494         /* what was last interrupt timeslice? */
1495         timepassed_us = 1000000/eitr;
1496         bytes_perint = bytes / timepassed_us; /* bytes/usec */
1497
1498         switch (itr_setting) {
1499         case lowest_latency:
1500                 if (bytes_perint > adapter->eitr_low)
1501                         retval = low_latency;
1502                 break;
1503         case low_latency:
1504                 if (bytes_perint > adapter->eitr_high)
1505                         retval = bulk_latency;
1506                 else if (bytes_perint <= adapter->eitr_low)
1507                         retval = lowest_latency;
1508                 break;
1509         case bulk_latency:
1510                 if (bytes_perint <= adapter->eitr_high)
1511                         retval = low_latency;
1512                 break;
1513         }
1514
1515 update_itr_done:
1516         return retval;
1517 }
1518
1519 /**
1520  * ixgbe_write_eitr - write EITR register in hardware specific way
1521  * @q_vector: structure containing interrupt and ring information
1522  *
1523  * This function is made to be called by ethtool and by the driver
1524  * when it needs to update EITR registers at runtime.  Hardware
1525  * specific quirks/differences are taken care of here.
1526  */
1527 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
1528 {
1529         struct ixgbe_adapter *adapter = q_vector->adapter;
1530         struct ixgbe_hw *hw = &adapter->hw;
1531         int v_idx = q_vector->v_idx;
1532         u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1533
1534         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1535                 /* must write high and low 16 bits to reset counter */
1536                 itr_reg |= (itr_reg << 16);
1537         } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1538                 /*
1539                  * 82599 can support a value of zero, so allow it for
1540                  * max interrupt rate, but there is an errata where it can
1541                  * not be zero with RSC
1542                  */
1543                 if (itr_reg == 8 &&
1544                     !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
1545                         itr_reg = 0;
1546
1547                 /*
1548                  * set the WDIS bit to not clear the timer bits and cause an
1549                  * immediate assertion of the interrupt
1550                  */
1551                 itr_reg |= IXGBE_EITR_CNT_WDIS;
1552         }
1553         IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1554 }
1555
1556 static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
1557 {
1558         struct ixgbe_adapter *adapter = q_vector->adapter;
1559         u32 new_itr;
1560         u8 current_itr, ret_itr;
1561         int i, r_idx;
1562         struct ixgbe_ring *rx_ring, *tx_ring;
1563
1564         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1565         for (i = 0; i < q_vector->txr_count; i++) {
1566                 tx_ring = adapter->tx_ring[r_idx];
1567                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1568                                            q_vector->tx_itr,
1569                                            tx_ring->total_packets,
1570                                            tx_ring->total_bytes);
1571                 /* if the result for this queue would decrease interrupt
1572                  * rate for this vector then use that result */
1573                 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
1574                                     q_vector->tx_itr - 1 : ret_itr);
1575                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1576                                       r_idx + 1);
1577         }
1578
1579         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1580         for (i = 0; i < q_vector->rxr_count; i++) {
1581                 rx_ring = adapter->rx_ring[r_idx];
1582                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1583                                            q_vector->rx_itr,
1584                                            rx_ring->total_packets,
1585                                            rx_ring->total_bytes);
1586                 /* if the result for this queue would decrease interrupt
1587                  * rate for this vector then use that result */
1588                 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
1589                                     q_vector->rx_itr - 1 : ret_itr);
1590                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1591                                       r_idx + 1);
1592         }
1593
1594         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1595
1596         switch (current_itr) {
1597         /* counts and packets in update_itr are dependent on these numbers */
1598         case lowest_latency:
1599                 new_itr = 100000;
1600                 break;
1601         case low_latency:
1602                 new_itr = 20000; /* aka hwitr = ~200 */
1603                 break;
1604         case bulk_latency:
1605         default:
1606                 new_itr = 8000;
1607                 break;
1608         }
1609
1610         if (new_itr != q_vector->eitr) {
1611                 /* do an exponential smoothing */
1612                 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1613
1614                 /* save the algorithm value here, not the smoothed one */
1615                 q_vector->eitr = new_itr;
1616
1617                 ixgbe_write_eitr(q_vector);
1618         }
1619 }
1620
1621 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1622 {
1623         struct ixgbe_hw *hw = &adapter->hw;
1624
1625         if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1626             (eicr & IXGBE_EICR_GPI_SDP1)) {
1627                 DPRINTK(PROBE, CRIT, "Fan has stopped, replace the adapter\n");
1628                 /* write to clear the interrupt */
1629                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1630         }
1631 }
1632
1633 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1634 {
1635         struct ixgbe_hw *hw = &adapter->hw;
1636
1637         if (eicr & IXGBE_EICR_GPI_SDP1) {
1638                 /* Clear the interrupt */
1639                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1640                 schedule_work(&adapter->multispeed_fiber_task);
1641         } else if (eicr & IXGBE_EICR_GPI_SDP2) {
1642                 /* Clear the interrupt */
1643                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1644                 schedule_work(&adapter->sfp_config_module_task);
1645         } else {
1646                 /* Interrupt isn't for us... */
1647                 return;
1648         }
1649 }
1650
1651 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1652 {
1653         struct ixgbe_hw *hw = &adapter->hw;
1654
1655         adapter->lsc_int++;
1656         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1657         adapter->link_check_timeout = jiffies;
1658         if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1659                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1660                 IXGBE_WRITE_FLUSH(hw);
1661                 schedule_work(&adapter->watchdog_task);
1662         }
1663 }
1664
1665 static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1666 {
1667         struct net_device *netdev = data;
1668         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1669         struct ixgbe_hw *hw = &adapter->hw;
1670         u32 eicr;
1671
1672         /*
1673          * Workaround for Silicon errata.  Use clear-by-write instead
1674          * of clear-by-read.  Reading with EICS will return the
1675          * interrupt causes without clearing, which later be done
1676          * with the write to EICR.
1677          */
1678         eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1679         IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
1680
1681         if (eicr & IXGBE_EICR_LSC)
1682                 ixgbe_check_lsc(adapter);
1683
1684         if (eicr & IXGBE_EICR_MAILBOX)
1685                 ixgbe_msg_task(adapter);
1686
1687         if (hw->mac.type == ixgbe_mac_82598EB)
1688                 ixgbe_check_fan_failure(adapter, eicr);
1689
1690         if (hw->mac.type == ixgbe_mac_82599EB) {
1691                 ixgbe_check_sfp_event(adapter, eicr);
1692
1693                 /* Handle Flow Director Full threshold interrupt */
1694                 if (eicr & IXGBE_EICR_FLOW_DIR) {
1695                         int i;
1696                         IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR);
1697                         /* Disable transmits before FDIR Re-initialization */
1698                         netif_tx_stop_all_queues(netdev);
1699                         for (i = 0; i < adapter->num_tx_queues; i++) {
1700                                 struct ixgbe_ring *tx_ring =
1701                                                             adapter->tx_ring[i];
1702                                 if (test_and_clear_bit(__IXGBE_FDIR_INIT_DONE,
1703                                                        &tx_ring->reinit_state))
1704                                         schedule_work(&adapter->fdir_reinit_task);
1705                         }
1706                 }
1707         }
1708         if (!test_bit(__IXGBE_DOWN, &adapter->state))
1709                 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
1710
1711         return IRQ_HANDLED;
1712 }
1713
1714 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1715                                            u64 qmask)
1716 {
1717         u32 mask;
1718
1719         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1720                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1721                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1722         } else {
1723                 mask = (qmask & 0xFFFFFFFF);
1724                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(0), mask);
1725                 mask = (qmask >> 32);
1726                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1), mask);
1727         }
1728         /* skip the flush */
1729 }
1730
1731 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
1732                                             u64 qmask)
1733 {
1734         u32 mask;
1735
1736         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1737                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1738                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, mask);
1739         } else {
1740                 mask = (qmask & 0xFFFFFFFF);
1741                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), mask);
1742                 mask = (qmask >> 32);
1743                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), mask);
1744         }
1745         /* skip the flush */
1746 }
1747
1748 static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1749 {
1750         struct ixgbe_q_vector *q_vector = data;
1751         struct ixgbe_adapter  *adapter = q_vector->adapter;
1752         struct ixgbe_ring     *tx_ring;
1753         int i, r_idx;
1754
1755         if (!q_vector->txr_count)
1756                 return IRQ_HANDLED;
1757
1758         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1759         for (i = 0; i < q_vector->txr_count; i++) {
1760                 tx_ring = adapter->tx_ring[r_idx];
1761                 tx_ring->total_bytes = 0;
1762                 tx_ring->total_packets = 0;
1763                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1764                                       r_idx + 1);
1765         }
1766
1767         /* EIAM disabled interrupts (on this vector) for us */
1768         napi_schedule(&q_vector->napi);
1769
1770         return IRQ_HANDLED;
1771 }
1772
1773 /**
1774  * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1775  * @irq: unused
1776  * @data: pointer to our q_vector struct for this interrupt vector
1777  **/
1778 static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
1779 {
1780         struct ixgbe_q_vector *q_vector = data;
1781         struct ixgbe_adapter  *adapter = q_vector->adapter;
1782         struct ixgbe_ring  *rx_ring;
1783         int r_idx;
1784         int i;
1785
1786         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1787         for (i = 0;  i < q_vector->rxr_count; i++) {
1788                 rx_ring = adapter->rx_ring[r_idx];
1789                 rx_ring->total_bytes = 0;
1790                 rx_ring->total_packets = 0;
1791                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1792                                       r_idx + 1);
1793         }
1794
1795         if (!q_vector->rxr_count)
1796                 return IRQ_HANDLED;
1797
1798         /* disable interrupts on this vector only */
1799         /* EIAM disabled interrupts (on this vector) for us */
1800         napi_schedule(&q_vector->napi);
1801
1802         return IRQ_HANDLED;
1803 }
1804
1805 static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1806 {
1807         struct ixgbe_q_vector *q_vector = data;
1808         struct ixgbe_adapter  *adapter = q_vector->adapter;
1809         struct ixgbe_ring  *ring;
1810         int r_idx;
1811         int i;
1812
1813         if (!q_vector->txr_count && !q_vector->rxr_count)
1814                 return IRQ_HANDLED;
1815
1816         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1817         for (i = 0; i < q_vector->txr_count; i++) {
1818                 ring = adapter->tx_ring[r_idx];
1819                 ring->total_bytes = 0;
1820                 ring->total_packets = 0;
1821                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1822                                       r_idx + 1);
1823         }
1824
1825         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1826         for (i = 0; i < q_vector->rxr_count; i++) {
1827                 ring = adapter->rx_ring[r_idx];
1828                 ring->total_bytes = 0;
1829                 ring->total_packets = 0;
1830                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1831                                       r_idx + 1);
1832         }
1833
1834         /* EIAM disabled interrupts (on this vector) for us */
1835         napi_schedule(&q_vector->napi);
1836
1837         return IRQ_HANDLED;
1838 }
1839
1840 /**
1841  * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1842  * @napi: napi struct with our devices info in it
1843  * @budget: amount of work driver is allowed to do this pass, in packets
1844  *
1845  * This function is optimized for cleaning one queue only on a single
1846  * q_vector!!!
1847  **/
1848 static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1849 {
1850         struct ixgbe_q_vector *q_vector =
1851                                container_of(napi, struct ixgbe_q_vector, napi);
1852         struct ixgbe_adapter *adapter = q_vector->adapter;
1853         struct ixgbe_ring *rx_ring = NULL;
1854         int work_done = 0;
1855         long r_idx;
1856
1857         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1858         rx_ring = adapter->rx_ring[r_idx];
1859 #ifdef CONFIG_IXGBE_DCA
1860         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1861                 ixgbe_update_rx_dca(adapter, rx_ring);
1862 #endif
1863
1864         ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
1865
1866         /* If all Rx work done, exit the polling mode */
1867         if (work_done < budget) {
1868                 napi_complete(napi);
1869                 if (adapter->rx_itr_setting & 1)
1870                         ixgbe_set_itr_msix(q_vector);
1871                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1872                         ixgbe_irq_enable_queues(adapter,
1873                                                 ((u64)1 << q_vector->v_idx));
1874         }
1875
1876         return work_done;
1877 }
1878
1879 /**
1880  * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
1881  * @napi: napi struct with our devices info in it
1882  * @budget: amount of work driver is allowed to do this pass, in packets
1883  *
1884  * This function will clean more than one rx queue associated with a
1885  * q_vector.
1886  **/
1887 static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
1888 {
1889         struct ixgbe_q_vector *q_vector =
1890                                container_of(napi, struct ixgbe_q_vector, napi);
1891         struct ixgbe_adapter *adapter = q_vector->adapter;
1892         struct ixgbe_ring *ring = NULL;
1893         int work_done = 0, i;
1894         long r_idx;
1895         bool tx_clean_complete = true;
1896
1897         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1898         for (i = 0; i < q_vector->txr_count; i++) {
1899                 ring = adapter->tx_ring[r_idx];
1900 #ifdef CONFIG_IXGBE_DCA
1901                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1902                         ixgbe_update_tx_dca(adapter, ring);
1903 #endif
1904                 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
1905                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1906                                       r_idx + 1);
1907         }
1908
1909         /* attempt to distribute budget to each queue fairly, but don't allow
1910          * the budget to go below 1 because we'll exit polling */
1911         budget /= (q_vector->rxr_count ?: 1);
1912         budget = max(budget, 1);
1913         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1914         for (i = 0; i < q_vector->rxr_count; i++) {
1915                 ring = adapter->rx_ring[r_idx];
1916 #ifdef CONFIG_IXGBE_DCA
1917                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1918                         ixgbe_update_rx_dca(adapter, ring);
1919 #endif
1920                 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
1921                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1922                                       r_idx + 1);
1923         }
1924
1925         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1926         ring = adapter->rx_ring[r_idx];
1927         /* If all Rx work done, exit the polling mode */
1928         if (work_done < budget) {
1929                 napi_complete(napi);
1930                 if (adapter->rx_itr_setting & 1)
1931                         ixgbe_set_itr_msix(q_vector);
1932                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1933                         ixgbe_irq_enable_queues(adapter,
1934                                                 ((u64)1 << q_vector->v_idx));
1935                 return 0;
1936         }
1937
1938         return work_done;
1939 }
1940
1941 /**
1942  * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
1943  * @napi: napi struct with our devices info in it
1944  * @budget: amount of work driver is allowed to do this pass, in packets
1945  *
1946  * This function is optimized for cleaning one queue only on a single
1947  * q_vector!!!
1948  **/
1949 static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
1950 {
1951         struct ixgbe_q_vector *q_vector =
1952                                container_of(napi, struct ixgbe_q_vector, napi);
1953         struct ixgbe_adapter *adapter = q_vector->adapter;
1954         struct ixgbe_ring *tx_ring = NULL;
1955         int work_done = 0;
1956         long r_idx;
1957
1958         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1959         tx_ring = adapter->tx_ring[r_idx];
1960 #ifdef CONFIG_IXGBE_DCA
1961         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1962                 ixgbe_update_tx_dca(adapter, tx_ring);
1963 #endif
1964
1965         if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
1966                 work_done = budget;
1967
1968         /* If all Tx work done, exit the polling mode */
1969         if (work_done < budget) {
1970                 napi_complete(napi);
1971                 if (adapter->tx_itr_setting & 1)
1972                         ixgbe_set_itr_msix(q_vector);
1973                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1974                         ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
1975         }
1976
1977         return work_done;
1978 }
1979
1980 static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
1981                                      int r_idx)
1982 {
1983         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1984
1985         set_bit(r_idx, q_vector->rxr_idx);
1986         q_vector->rxr_count++;
1987 }
1988
1989 static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
1990                                      int t_idx)
1991 {
1992         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1993
1994         set_bit(t_idx, q_vector->txr_idx);
1995         q_vector->txr_count++;
1996 }
1997
1998 /**
1999  * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
2000  * @adapter: board private structure to initialize
2001  * @vectors: allotted vector count for descriptor rings
2002  *
2003  * This function maps descriptor rings to the queue-specific vectors
2004  * we were allotted through the MSI-X enabling code.  Ideally, we'd have
2005  * one vector per ring/queue, but on a constrained vector budget, we
2006  * group the rings as "efficiently" as possible.  You would add new
2007  * mapping configurations in here.
2008  **/
2009 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
2010                                       int vectors)
2011 {
2012         int v_start = 0;
2013         int rxr_idx = 0, txr_idx = 0;
2014         int rxr_remaining = adapter->num_rx_queues;
2015         int txr_remaining = adapter->num_tx_queues;
2016         int i, j;
2017         int rqpv, tqpv;
2018         int err = 0;
2019
2020         /* No mapping required if MSI-X is disabled. */
2021         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2022                 goto out;
2023
2024         /*
2025          * The ideal configuration...
2026          * We have enough vectors to map one per queue.
2027          */
2028         if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
2029                 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
2030                         map_vector_to_rxq(adapter, v_start, rxr_idx);
2031
2032                 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
2033                         map_vector_to_txq(adapter, v_start, txr_idx);
2034
2035                 goto out;
2036         }
2037
2038         /*
2039          * If we don't have enough vectors for a 1-to-1
2040          * mapping, we'll have to group them so there are
2041          * multiple queues per vector.
2042          */
2043         /* Re-adjusting *qpv takes care of the remainder. */
2044         for (i = v_start; i < vectors; i++) {
2045                 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
2046                 for (j = 0; j < rqpv; j++) {
2047                         map_vector_to_rxq(adapter, i, rxr_idx);
2048                         rxr_idx++;
2049                         rxr_remaining--;
2050                 }
2051         }
2052         for (i = v_start; i < vectors; i++) {
2053                 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
2054                 for (j = 0; j < tqpv; j++) {
2055                         map_vector_to_txq(adapter, i, txr_idx);
2056                         txr_idx++;
2057                         txr_remaining--;
2058                 }
2059         }
2060
2061 out:
2062         return err;
2063 }
2064
2065 /**
2066  * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2067  * @adapter: board private structure
2068  *
2069  * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2070  * interrupts from the kernel.
2071  **/
2072 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2073 {
2074         struct net_device *netdev = adapter->netdev;
2075         irqreturn_t (*handler)(int, void *);
2076         int i, vector, q_vectors, err;
2077         int ri=0, ti=0;
2078
2079         /* Decrement for Other and TCP Timer vectors */
2080         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2081
2082         /* Map the Tx/Rx rings to the vectors we were allotted. */
2083         err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
2084         if (err)
2085                 goto out;
2086
2087 #define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
2088                          (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
2089                          &ixgbe_msix_clean_many)
2090         for (vector = 0; vector < q_vectors; vector++) {
2091                 handler = SET_HANDLER(adapter->q_vector[vector]);
2092
2093                 if(handler == &ixgbe_msix_clean_rx) {
2094                         sprintf(adapter->name[vector], "%s-%s-%d",
2095                                 netdev->name, "rx", ri++);
2096                 }
2097                 else if(handler == &ixgbe_msix_clean_tx) {
2098                         sprintf(adapter->name[vector], "%s-%s-%d",
2099                                 netdev->name, "tx", ti++);
2100                 }
2101                 else
2102                         sprintf(adapter->name[vector], "%s-%s-%d",
2103                                 netdev->name, "TxRx", vector);
2104
2105                 err = request_irq(adapter->msix_entries[vector].vector,
2106                                   handler, 0, adapter->name[vector],
2107                                   adapter->q_vector[vector]);
2108                 if (err) {
2109                         DPRINTK(PROBE, ERR,
2110                                 "request_irq failed for MSIX interrupt "
2111                                 "Error: %d\n", err);
2112                         goto free_queue_irqs;
2113                 }
2114         }
2115
2116         sprintf(adapter->name[vector], "%s:lsc", netdev->name);
2117         err = request_irq(adapter->msix_entries[vector].vector,
2118                           ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
2119         if (err) {
2120                 DPRINTK(PROBE, ERR,
2121                         "request_irq for msix_lsc failed: %d\n", err);
2122                 goto free_queue_irqs;
2123         }
2124
2125         return 0;
2126
2127 free_queue_irqs:
2128         for (i = vector - 1; i >= 0; i--)
2129                 free_irq(adapter->msix_entries[--vector].vector,
2130                          adapter->q_vector[i]);
2131         adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2132         pci_disable_msix(adapter->pdev);
2133         kfree(adapter->msix_entries);
2134         adapter->msix_entries = NULL;
2135 out:
2136         return err;
2137 }
2138
2139 static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
2140 {
2141         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2142         u8 current_itr;
2143         u32 new_itr = q_vector->eitr;
2144         struct ixgbe_ring *rx_ring = adapter->rx_ring[0];
2145         struct ixgbe_ring *tx_ring = adapter->tx_ring[0];
2146
2147         q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
2148                                             q_vector->tx_itr,
2149                                             tx_ring->total_packets,
2150                                             tx_ring->total_bytes);
2151         q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
2152                                             q_vector->rx_itr,
2153                                             rx_ring->total_packets,
2154                                             rx_ring->total_bytes);
2155
2156         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
2157
2158         switch (current_itr) {
2159         /* counts and packets in update_itr are dependent on these numbers */
2160         case lowest_latency:
2161                 new_itr = 100000;
2162                 break;
2163         case low_latency:
2164                 new_itr = 20000; /* aka hwitr = ~200 */
2165                 break;
2166         case bulk_latency:
2167                 new_itr = 8000;
2168                 break;
2169         default:
2170                 break;
2171         }
2172
2173         if (new_itr != q_vector->eitr) {
2174                 /* do an exponential smoothing */
2175                 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
2176
2177                 /* save the algorithm value here, not the smoothed one */
2178                 q_vector->eitr = new_itr;
2179
2180                 ixgbe_write_eitr(q_vector);
2181         }
2182 }
2183
2184 /**
2185  * ixgbe_irq_enable - Enable default interrupt generation settings
2186  * @adapter: board private structure
2187  **/
2188 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter)
2189 {
2190         u32 mask;
2191
2192         mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
2193         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2194                 mask |= IXGBE_EIMS_GPI_SDP1;
2195         if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2196                 mask |= IXGBE_EIMS_ECC;
2197                 mask |= IXGBE_EIMS_GPI_SDP1;
2198                 mask |= IXGBE_EIMS_GPI_SDP2;
2199                 if (adapter->num_vfs)
2200                         mask |= IXGBE_EIMS_MAILBOX;
2201         }
2202         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
2203             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
2204                 mask |= IXGBE_EIMS_FLOW_DIR;
2205
2206         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2207         ixgbe_irq_enable_queues(adapter, ~0);
2208         IXGBE_WRITE_FLUSH(&adapter->hw);
2209
2210         if (adapter->num_vfs > 32) {
2211                 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2212                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2213         }
2214 }
2215
2216 /**
2217  * ixgbe_intr - legacy mode Interrupt Handler
2218  * @irq: interrupt number
2219  * @data: pointer to a network interface device structure
2220  **/
2221 static irqreturn_t ixgbe_intr(int irq, void *data)
2222 {
2223         struct net_device *netdev = data;
2224         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2225         struct ixgbe_hw *hw = &adapter->hw;
2226         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2227         u32 eicr;
2228
2229         /*
2230          * Workaround for silicon errata.  Mask the interrupts
2231          * before the read of EICR.
2232          */
2233         IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2234
2235         /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2236          * therefore no explict interrupt disable is necessary */
2237         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2238         if (!eicr) {
2239                 /* shared interrupt alert!
2240                  * make sure interrupts are enabled because the read will
2241                  * have disabled interrupts due to EIAM */
2242                 ixgbe_irq_enable(adapter);
2243                 return IRQ_NONE;        /* Not our interrupt */
2244         }
2245
2246         if (eicr & IXGBE_EICR_LSC)
2247                 ixgbe_check_lsc(adapter);
2248
2249         if (hw->mac.type == ixgbe_mac_82599EB)
2250                 ixgbe_check_sfp_event(adapter, eicr);
2251
2252         ixgbe_check_fan_failure(adapter, eicr);
2253
2254         if (napi_schedule_prep(&(q_vector->napi))) {
2255                 adapter->tx_ring[0]->total_packets = 0;
2256                 adapter->tx_ring[0]->total_bytes = 0;
2257                 adapter->rx_ring[0]->total_packets = 0;
2258                 adapter->rx_ring[0]->total_bytes = 0;
2259                 /* would disable interrupts here but EIAM disabled it */
2260                 __napi_schedule(&(q_vector->napi));
2261         }
2262
2263         return IRQ_HANDLED;
2264 }
2265
2266 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
2267 {
2268         int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2269
2270         for (i = 0; i < q_vectors; i++) {
2271                 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
2272                 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
2273                 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
2274                 q_vector->rxr_count = 0;
2275                 q_vector->txr_count = 0;
2276         }
2277 }
2278
2279 /**
2280  * ixgbe_request_irq - initialize interrupts
2281  * @adapter: board private structure
2282  *
2283  * Attempts to configure interrupts using the best available
2284  * capabilities of the hardware and kernel.
2285  **/
2286 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
2287 {
2288         struct net_device *netdev = adapter->netdev;
2289         int err;
2290
2291         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2292                 err = ixgbe_request_msix_irqs(adapter);
2293         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
2294                 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
2295                                   netdev->name, netdev);
2296         } else {
2297                 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
2298                                   netdev->name, netdev);
2299         }
2300
2301         if (err)
2302                 DPRINTK(PROBE, ERR, "request_irq failed, Error %d\n", err);
2303
2304         return err;
2305 }
2306
2307 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2308 {
2309         struct net_device *netdev = adapter->netdev;
2310
2311         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2312                 int i, q_vectors;
2313
2314                 q_vectors = adapter->num_msix_vectors;
2315
2316                 i = q_vectors - 1;
2317                 free_irq(adapter->msix_entries[i].vector, netdev);
2318
2319                 i--;
2320                 for (; i >= 0; i--) {
2321                         free_irq(adapter->msix_entries[i].vector,
2322                                  adapter->q_vector[i]);
2323                 }
2324
2325                 ixgbe_reset_q_vectors(adapter);
2326         } else {
2327                 free_irq(adapter->pdev->irq, netdev);
2328         }
2329 }
2330
2331 /**
2332  * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2333  * @adapter: board private structure
2334  **/
2335 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2336 {
2337         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2338                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
2339         } else {
2340                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2341                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
2342                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
2343                 if (adapter->num_vfs > 32)
2344                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
2345         }
2346         IXGBE_WRITE_FLUSH(&adapter->hw);
2347         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2348                 int i;
2349                 for (i = 0; i < adapter->num_msix_vectors; i++)
2350                         synchronize_irq(adapter->msix_entries[i].vector);
2351         } else {
2352                 synchronize_irq(adapter->pdev->irq);
2353         }
2354 }
2355
2356 /**
2357  * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2358  *
2359  **/
2360 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2361 {
2362         struct ixgbe_hw *hw = &adapter->hw;
2363
2364         IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
2365                         EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
2366
2367         ixgbe_set_ivar(adapter, 0, 0, 0);
2368         ixgbe_set_ivar(adapter, 1, 0, 0);
2369
2370         map_vector_to_rxq(adapter, 0, 0);
2371         map_vector_to_txq(adapter, 0, 0);
2372
2373         DPRINTK(HW, INFO, "Legacy interrupt IVAR setup done\n");
2374 }
2375
2376 /**
2377  * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
2378  * @adapter: board private structure
2379  *
2380  * Configure the Tx unit of the MAC after a reset.
2381  **/
2382 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2383 {
2384         u64 tdba;
2385         struct ixgbe_hw *hw = &adapter->hw;
2386         u32 i, j, tdlen, txctrl;
2387
2388         /* Setup the HW Tx Head and Tail descriptor pointers */
2389         for (i = 0; i < adapter->num_tx_queues; i++) {
2390                 struct ixgbe_ring *ring = adapter->tx_ring[i];
2391                 j = ring->reg_idx;
2392                 tdba = ring->dma;
2393                 tdlen = ring->count * sizeof(union ixgbe_adv_tx_desc);
2394                 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j),
2395                                 (tdba & DMA_BIT_MASK(32)));
2396                 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32));
2397                 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), tdlen);
2398                 IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0);
2399                 IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0);
2400                 adapter->tx_ring[i]->head = IXGBE_TDH(j);
2401                 adapter->tx_ring[i]->tail = IXGBE_TDT(j);
2402                 /*
2403                  * Disable Tx Head Writeback RO bit, since this hoses
2404                  * bookkeeping if things aren't delivered in order.
2405                  */
2406                 switch (hw->mac.type) {
2407                 case ixgbe_mac_82598EB:
2408                         txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j));
2409                         break;
2410                 case ixgbe_mac_82599EB:
2411                 default:
2412                         txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(j));
2413                         break;
2414                 }
2415                 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
2416                 switch (hw->mac.type) {
2417                 case ixgbe_mac_82598EB:
2418                         IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl);
2419                         break;
2420                 case ixgbe_mac_82599EB:
2421                 default:
2422                         IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(j), txctrl);
2423                         break;
2424                 }
2425         }
2426
2427         if (hw->mac.type == ixgbe_mac_82599EB) {
2428                 u32 rttdcs;
2429                 u32 mask;
2430
2431                 /* disable the arbiter while setting MTQC */
2432                 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2433                 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2434                 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2435
2436                 /* set transmit pool layout */
2437                 mask = (IXGBE_FLAG_SRIOV_ENABLED | IXGBE_FLAG_DCB_ENABLED);
2438                 switch (adapter->flags & mask) {
2439
2440                 case (IXGBE_FLAG_SRIOV_ENABLED):
2441                         IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2442                                         (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2443                         break;
2444
2445                 case (IXGBE_FLAG_DCB_ENABLED):
2446                         /* We enable 8 traffic classes, DCB only */
2447                         IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2448                                       (IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ));
2449                         break;
2450
2451                 default:
2452                         IXGBE_WRITE_REG(hw, IXGBE_MTQC, IXGBE_MTQC_64Q_1PB);
2453                         break;
2454                 }
2455
2456                 /* re-eable the arbiter */
2457                 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2458                 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2459         }
2460 }
2461
2462 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
2463
2464 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
2465                                    struct ixgbe_ring *rx_ring)
2466 {
2467         u32 srrctl;
2468         int index;
2469         struct ixgbe_ring_feature *feature = adapter->ring_feature;
2470
2471         index = rx_ring->reg_idx;
2472         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2473                 unsigned long mask;
2474                 mask = (unsigned long) feature[RING_F_RSS].mask;
2475                 index = index & mask;
2476         }
2477         srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
2478
2479         srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2480         srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
2481
2482         srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2483                   IXGBE_SRRCTL_BSIZEHDR_MASK;
2484
2485         if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
2486 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2487                 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2488 #else
2489                 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2490 #endif
2491                 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2492         } else {
2493                 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2494                           IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2495                 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
2496         }
2497
2498         IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
2499 }
2500
2501 static u32 ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
2502 {
2503         u32 mrqc = 0;
2504         int mask;
2505
2506         if (!(adapter->hw.mac.type == ixgbe_mac_82599EB))
2507                 return mrqc;
2508
2509         mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2510 #ifdef CONFIG_IXGBE_DCB
2511                                  | IXGBE_FLAG_DCB_ENABLED
2512 #endif
2513                                  | IXGBE_FLAG_SRIOV_ENABLED
2514                                 );
2515
2516         switch (mask) {
2517         case (IXGBE_FLAG_RSS_ENABLED):
2518                 mrqc = IXGBE_MRQC_RSSEN;
2519                 break;
2520         case (IXGBE_FLAG_SRIOV_ENABLED):
2521                 mrqc = IXGBE_MRQC_VMDQEN;
2522                 break;
2523 #ifdef CONFIG_IXGBE_DCB
2524         case (IXGBE_FLAG_DCB_ENABLED):
2525                 mrqc = IXGBE_MRQC_RT8TCEN;
2526                 break;
2527 #endif /* CONFIG_IXGBE_DCB */
2528         default:
2529                 break;
2530         }
2531
2532         return mrqc;
2533 }
2534
2535 /**
2536  * ixgbe_configure_rscctl - enable RSC for the indicated ring
2537  * @adapter:    address of board private structure
2538  * @index:      index of ring to set
2539  **/
2540 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter, int index)
2541 {
2542         struct ixgbe_ring *rx_ring;
2543         struct ixgbe_hw *hw = &adapter->hw;
2544         int j;
2545         u32 rscctrl;
2546         int rx_buf_len;
2547
2548         rx_ring = adapter->rx_ring[index];
2549         j = rx_ring->reg_idx;
2550         rx_buf_len = rx_ring->rx_buf_len;
2551         rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(j));
2552         rscctrl |= IXGBE_RSCCTL_RSCEN;
2553         /*
2554          * we must limit the number of descriptors so that the
2555          * total size of max desc * buf_len is not greater
2556          * than 65535
2557          */
2558         if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
2559 #if (MAX_SKB_FRAGS > 16)
2560                 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2561 #elif (MAX_SKB_FRAGS > 8)
2562                 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2563 #elif (MAX_SKB_FRAGS > 4)
2564                 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2565 #else
2566                 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2567 #endif
2568         } else {
2569                 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2570                         rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2571                 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2572                         rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2573                 else
2574                         rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2575         }
2576         IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(j), rscctrl);
2577 }
2578
2579 /**
2580  * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
2581  * @adapter: board private structure
2582  *
2583  * Configure the Rx unit of the MAC after a reset.
2584  **/
2585 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
2586 {
2587         u64 rdba;
2588         struct ixgbe_hw *hw = &adapter->hw;
2589         struct ixgbe_ring *rx_ring;
2590         struct net_device *netdev = adapter->netdev;
2591         int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2592         int i, j;
2593         u32 rdlen, rxctrl, rxcsum;
2594         static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2595                           0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2596                           0x6A3E67EA, 0x14364D17, 0x3BED200D};
2597         u32 fctrl, hlreg0;
2598         u32 reta = 0, mrqc = 0;
2599         u32 rdrxctl;
2600         int rx_buf_len;
2601
2602         /* Decide whether to use packet split mode or not */
2603         /* Do not use packet split if we're in SR-IOV Mode */
2604         if (!adapter->num_vfs)
2605                 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
2606
2607         /* Set the RX buffer length according to the mode */
2608         if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
2609                 rx_buf_len = IXGBE_RX_HDR_SIZE;
2610                 if (hw->mac.type == ixgbe_mac_82599EB) {
2611                         /* PSRTYPE must be initialized in 82599 */
2612                         u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
2613                                       IXGBE_PSRTYPE_UDPHDR |
2614                                       IXGBE_PSRTYPE_IPV4HDR |
2615                                       IXGBE_PSRTYPE_IPV6HDR |
2616                                       IXGBE_PSRTYPE_L2HDR;
2617                         IXGBE_WRITE_REG(hw,
2618                                         IXGBE_PSRTYPE(adapter->num_vfs),
2619                                         psrtype);
2620                 }
2621         } else {
2622                 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
2623                     (netdev->mtu <= ETH_DATA_LEN))
2624                         rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
2625                 else
2626                         rx_buf_len = ALIGN(max_frame, 1024);
2627         }
2628
2629         fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
2630         fctrl |= IXGBE_FCTRL_BAM;
2631         fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
2632         fctrl |= IXGBE_FCTRL_PMCF;
2633         IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, fctrl);
2634
2635         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2636         if (adapter->netdev->mtu <= ETH_DATA_LEN)
2637                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
2638         else
2639                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2640 #ifdef IXGBE_FCOE
2641         if (netdev->features & NETIF_F_FCOE_MTU)
2642                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2643 #endif
2644         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2645
2646         rdlen = adapter->rx_ring[0]->count * sizeof(union ixgbe_adv_rx_desc);
2647         /* disable receives while setting up the descriptors */
2648         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2649         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
2650
2651         /*
2652          * Setup the HW Rx Head and Tail Descriptor Pointers and
2653          * the Base and Length of the Rx Descriptor Ring
2654          */
2655         for (i = 0; i < adapter->num_rx_queues; i++) {
2656                 rx_ring = adapter->rx_ring[i];
2657                 rdba = rx_ring->dma;
2658                 j = rx_ring->reg_idx;
2659                 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j), (rdba & DMA_BIT_MASK(32)));
2660                 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32));
2661                 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j), rdlen);
2662                 IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0);
2663                 IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0);
2664                 rx_ring->head = IXGBE_RDH(j);
2665                 rx_ring->tail = IXGBE_RDT(j);
2666                 rx_ring->rx_buf_len = rx_buf_len;
2667
2668                 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
2669                         rx_ring->flags |= IXGBE_RING_RX_PS_ENABLED;
2670                 else
2671                         rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
2672
2673 #ifdef IXGBE_FCOE
2674                 if (netdev->features & NETIF_F_FCOE_MTU) {
2675                         struct ixgbe_ring_feature *f;
2676                         f = &adapter->ring_feature[RING_F_FCOE];
2677                         if ((i >= f->mask) && (i < f->mask + f->indices)) {
2678                                 rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
2679                                 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
2680                                         rx_ring->rx_buf_len =
2681                                                 IXGBE_FCOE_JUMBO_FRAME_SIZE;
2682                         }
2683                 }
2684
2685 #endif /* IXGBE_FCOE */
2686                 ixgbe_configure_srrctl(adapter, rx_ring);
2687         }
2688
2689         if (hw->mac.type == ixgbe_mac_82598EB) {
2690                 /*
2691                  * For VMDq support of different descriptor types or
2692                  * buffer sizes through the use of multiple SRRCTL
2693                  * registers, RDRXCTL.MVMEN must be set to 1
2694                  *
2695                  * also, the manual doesn't mention it clearly but DCA hints
2696                  * will only use queue 0's tags unless this bit is set.  Side
2697                  * effects of setting this bit are only that SRRCTL must be
2698                  * fully programmed [0..15]
2699                  */
2700                 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2701                 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
2702                 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2703         }
2704
2705         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
2706                 u32 vt_reg_bits;
2707                 u32 reg_offset, vf_shift;
2708                 u32 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2709                 vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN
2710                         | IXGBE_VT_CTL_REPLEN;
2711                 vt_reg_bits |= (adapter->num_vfs <<
2712                                 IXGBE_VT_CTL_POOL_SHIFT);
2713                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
2714                 IXGBE_WRITE_REG(hw, IXGBE_MRQC, 0);
2715
2716                 vf_shift = adapter->num_vfs % 32;
2717                 reg_offset = adapter->num_vfs / 32;
2718                 IXGBE_WRITE_REG(hw, IXGBE_VFRE(0), 0);
2719                 IXGBE_WRITE_REG(hw, IXGBE_VFRE(1), 0);
2720                 IXGBE_WRITE_REG(hw, IXGBE_VFTE(0), 0);
2721                 IXGBE_WRITE_REG(hw, IXGBE_VFTE(1), 0);
2722                 /* Enable only the PF's pool for Tx/Rx */
2723                 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
2724                 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
2725                 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
2726                 ixgbe_set_vmolr(hw, adapter->num_vfs, true);
2727         }
2728
2729         /* Program MRQC for the distribution of queues */
2730         mrqc = ixgbe_setup_mrqc(adapter);
2731
2732         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
2733                 /* Fill out redirection table */
2734                 for (i = 0, j = 0; i < 128; i++, j++) {
2735                         if (j == adapter->ring_feature[RING_F_RSS].indices)
2736                                 j = 0;
2737                         /* reta = 4-byte sliding window of
2738                          * 0x00..(indices-1)(indices-1)00..etc. */
2739                         reta = (reta << 8) | (j * 0x11);
2740                         if ((i & 3) == 3)
2741                                 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2742                 }
2743
2744                 /* Fill out hash function seeds */
2745                 for (i = 0; i < 10; i++)
2746                         IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2747
2748                 if (hw->mac.type == ixgbe_mac_82598EB)
2749                         mrqc |= IXGBE_MRQC_RSSEN;
2750                     /* Perform hash on these packet types */
2751                 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2752                       | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2753                       | IXGBE_MRQC_RSS_FIELD_IPV4_UDP
2754                       | IXGBE_MRQC_RSS_FIELD_IPV6
2755                       | IXGBE_MRQC_RSS_FIELD_IPV6_TCP
2756                       | IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
2757         }
2758         IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2759
2760         if (adapter->num_vfs) {
2761                 u32 reg;
2762
2763                 /* Map PF MAC address in RAR Entry 0 to first pool
2764                  * following VFs */
2765                 hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
2766
2767                 /* Set up VF register offsets for selected VT Mode, i.e.
2768                  * 64 VFs for SR-IOV */
2769                 reg = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
2770                 reg |= IXGBE_GCR_EXT_SRIOV;
2771                 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, reg);
2772         }
2773
2774         rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2775
2776         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED ||
2777             adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED) {
2778                 /* Disable indicating checksum in descriptor, enables
2779                  * RSS hash */
2780                 rxcsum |= IXGBE_RXCSUM_PCSD;
2781         }
2782         if (!(rxcsum & IXGBE_RXCSUM_PCSD)) {
2783                 /* Enable IPv4 payload checksum for UDP fragments
2784                  * if PCSD is not set */
2785                 rxcsum |= IXGBE_RXCSUM_IPPCSE;
2786         }
2787
2788         IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2789
2790         if (hw->mac.type == ixgbe_mac_82599EB) {
2791                 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2792                 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
2793                 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
2794                 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2795         }
2796
2797         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
2798                 /* Enable 82599 HW-RSC */
2799                 for (i = 0; i < adapter->num_rx_queues; i++)
2800                         ixgbe_configure_rscctl(adapter, i);
2801
2802                 /* Disable RSC for ACK packets */
2803                 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
2804                    (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
2805         }
2806 }
2807
2808 static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
2809 {
2810         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2811         struct ixgbe_hw *hw = &adapter->hw;
2812         int pool_ndx = adapter->num_vfs;
2813
2814         /* add VID to filter table */
2815         hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
2816 }
2817
2818 static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
2819 {
2820         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2821         struct ixgbe_hw *hw = &adapter->hw;
2822         int pool_ndx = adapter->num_vfs;
2823
2824         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2825                 ixgbe_irq_disable(adapter);
2826
2827         vlan_group_set_device(adapter->vlgrp, vid, NULL);
2828
2829         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2830                 ixgbe_irq_enable(adapter);
2831
2832         /* remove VID from filter table */
2833         hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
2834 }
2835
2836 /**
2837  * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
2838  * @adapter: driver data
2839  */
2840 static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
2841 {
2842         struct ixgbe_hw *hw = &adapter->hw;
2843         u32 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2844         int i, j;
2845
2846         switch (hw->mac.type) {
2847         case ixgbe_mac_82598EB:
2848                 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
2849 #ifdef CONFIG_IXGBE_DCB
2850                 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
2851                         vlnctrl &= ~IXGBE_VLNCTRL_VME;
2852 #endif
2853                 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2854                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2855                 break;
2856         case ixgbe_mac_82599EB:
2857                 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
2858                 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2859                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2860 #ifdef CONFIG_IXGBE_DCB
2861                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
2862                         break;
2863 #endif
2864                 for (i = 0; i < adapter->num_rx_queues; i++) {
2865                         j = adapter->rx_ring[i]->reg_idx;
2866                         vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2867                         vlnctrl &= ~IXGBE_RXDCTL_VME;
2868                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
2869                 }
2870                 break;
2871         default:
2872                 break;
2873         }
2874 }
2875
2876 /**
2877  * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
2878  * @adapter: driver data
2879  */
2880 static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
2881 {
2882         struct ixgbe_hw *hw = &adapter->hw;
2883         u32 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2884         int i, j;
2885
2886         switch (hw->mac.type) {
2887         case ixgbe_mac_82598EB:
2888                 vlnctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2889                 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2890                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2891                 break;
2892         case ixgbe_mac_82599EB:
2893                 vlnctrl |= IXGBE_VLNCTRL_VFE;
2894                 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2895                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2896                 for (i = 0; i < adapter->num_rx_queues; i++) {
2897                         j = adapter->rx_ring[i]->reg_idx;
2898                         vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2899                         vlnctrl |= IXGBE_RXDCTL_VME;
2900                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
2901                 }
2902                 break;
2903         default:
2904                 break;
2905         }
2906 }
2907
2908 static void ixgbe_vlan_rx_register(struct net_device *netdev,
2909                                    struct vlan_group *grp)
2910 {
2911         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2912
2913         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2914                 ixgbe_irq_disable(adapter);
2915         adapter->vlgrp = grp;
2916
2917         /*
2918          * For a DCB driver, always enable VLAN tag stripping so we can
2919          * still receive traffic from a DCB-enabled host even if we're
2920          * not in DCB mode.
2921          */
2922         ixgbe_vlan_filter_enable(adapter);
2923
2924         ixgbe_vlan_rx_add_vid(netdev, 0);
2925
2926         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2927                 ixgbe_irq_enable(adapter);
2928 }
2929
2930 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
2931 {
2932         ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp);
2933
2934         if (adapter->vlgrp) {
2935                 u16 vid;
2936                 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
2937                         if (!vlan_group_get_device(adapter->vlgrp, vid))
2938                                 continue;
2939                         ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
2940                 }
2941         }
2942 }
2943
2944 /**
2945  * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
2946  * @netdev: network interface device structure
2947  *
2948  * The set_rx_method entry point is called whenever the unicast/multicast
2949  * address list or the network interface flags are updated.  This routine is
2950  * responsible for configuring the hardware for proper unicast, multicast and
2951  * promiscuous mode.
2952  **/
2953 void ixgbe_set_rx_mode(struct net_device *netdev)
2954 {
2955         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2956         struct ixgbe_hw *hw = &adapter->hw;
2957         u32 fctrl;
2958
2959         /* Check for Promiscuous and All Multicast modes */
2960
2961         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2962
2963         if (netdev->flags & IFF_PROMISC) {
2964                 hw->addr_ctrl.user_set_promisc = true;
2965                 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2966                 /* don't hardware filter vlans in promisc mode */
2967                 ixgbe_vlan_filter_disable(adapter);
2968         } else {
2969                 if (netdev->flags & IFF_ALLMULTI) {
2970                         fctrl |= IXGBE_FCTRL_MPE;
2971                         fctrl &= ~IXGBE_FCTRL_UPE;
2972                 } else if (!hw->addr_ctrl.uc_set_promisc) {
2973                         fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2974                 }
2975                 ixgbe_vlan_filter_enable(adapter);
2976                 hw->addr_ctrl.user_set_promisc = false;
2977         }
2978
2979         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2980
2981         /* reprogram secondary unicast list */
2982         hw->mac.ops.update_uc_addr_list(hw, netdev);
2983
2984         /* reprogram multicast list */
2985         hw->mac.ops.update_mc_addr_list(hw, netdev);
2986
2987         if (adapter->num_vfs)
2988                 ixgbe_restore_vf_multicasts(adapter);
2989 }
2990
2991 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
2992 {
2993         int q_idx;
2994         struct ixgbe_q_vector *q_vector;
2995         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2996
2997         /* legacy and MSI only use one vector */
2998         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2999                 q_vectors = 1;
3000
3001         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3002                 struct napi_struct *napi;
3003                 q_vector = adapter->q_vector[q_idx];
3004                 napi = &q_vector->napi;
3005                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3006                         if (!q_vector->rxr_count || !q_vector->txr_count) {
3007                                 if (q_vector->txr_count == 1)
3008                                         napi->poll = &ixgbe_clean_txonly;
3009                                 else if (q_vector->rxr_count == 1)
3010                                         napi->poll = &ixgbe_clean_rxonly;
3011                         }
3012                 }
3013
3014                 napi_enable(napi);
3015         }
3016 }
3017
3018 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3019 {
3020         int q_idx;
3021         struct ixgbe_q_vector *q_vector;
3022         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3023
3024         /* legacy and MSI only use one vector */
3025         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3026                 q_vectors = 1;
3027
3028         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3029                 q_vector = adapter->q_vector[q_idx];
3030                 napi_disable(&q_vector->napi);
3031         }
3032 }
3033
3034 #ifdef CONFIG_IXGBE_DCB
3035 /*
3036  * ixgbe_configure_dcb - Configure DCB hardware
3037  * @adapter: ixgbe adapter struct
3038  *
3039  * This is called by the driver on open to configure the DCB hardware.
3040  * This is also called by the gennetlink interface when reconfiguring
3041  * the DCB state.
3042  */
3043 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3044 {
3045         struct ixgbe_hw *hw = &adapter->hw;
3046         u32 txdctl;
3047         int i, j;
3048
3049         ixgbe_dcb_check_config(&adapter->dcb_cfg);
3050         ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_TX_CONFIG);
3051         ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_RX_CONFIG);
3052
3053         /* reconfigure the hardware */
3054         ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg);
3055
3056         for (i = 0; i < adapter->num_tx_queues; i++) {
3057                 j = adapter->tx_ring[i]->reg_idx;
3058                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3059                 /* PThresh workaround for Tx hang with DFP enabled. */
3060                 txdctl |= 32;
3061                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
3062         }
3063         /* Enable VLAN tag insert/strip */
3064         ixgbe_vlan_filter_enable(adapter);
3065
3066         hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
3067 }
3068
3069 #endif
3070 static void ixgbe_configure(struct ixgbe_adapter *adapter)
3071 {
3072         struct net_device *netdev = adapter->netdev;
3073         struct ixgbe_hw *hw = &adapter->hw;
3074         int i;
3075
3076         ixgbe_set_rx_mode(netdev);
3077
3078         ixgbe_restore_vlan(adapter);
3079 #ifdef CONFIG_IXGBE_DCB
3080         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3081                 if (hw->mac.type == ixgbe_mac_82598EB)
3082                         netif_set_gso_max_size(netdev, 32768);
3083                 else
3084                         netif_set_gso_max_size(netdev, 65536);
3085                 ixgbe_configure_dcb(adapter);
3086         } else {
3087                 netif_set_gso_max_size(netdev, 65536);
3088         }
3089 #else
3090         netif_set_gso_max_size(netdev, 65536);
3091 #endif
3092
3093 #ifdef IXGBE_FCOE
3094         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
3095                 ixgbe_configure_fcoe(adapter);
3096
3097 #endif /* IXGBE_FCOE */
3098         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3099                 for (i = 0; i < adapter->num_tx_queues; i++)
3100                         adapter->tx_ring[i]->atr_sample_rate =
3101                                                        adapter->atr_sample_rate;
3102                 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
3103         } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3104                 ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc);
3105         }
3106
3107         ixgbe_configure_tx(adapter);
3108         ixgbe_configure_rx(adapter);
3109         for (i = 0; i < adapter->num_rx_queues; i++)
3110                 ixgbe_alloc_rx_buffers(adapter, adapter->rx_ring[i],
3111                                        (adapter->rx_ring[i]->count - 1));
3112 }
3113
3114 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3115 {
3116         switch (hw->phy.type) {
3117         case ixgbe_phy_sfp_avago:
3118         case ixgbe_phy_sfp_ftl:
3119         case ixgbe_phy_sfp_intel:
3120         case ixgbe_phy_sfp_unknown:
3121         case ixgbe_phy_sfp_passive_tyco:
3122         case ixgbe_phy_sfp_passive_unknown:
3123         case ixgbe_phy_sfp_active_unknown:
3124         case ixgbe_phy_sfp_ftl_active:
3125                 return true;
3126         default:
3127                 return false;
3128         }
3129 }
3130
3131 /**
3132  * ixgbe_sfp_link_config - set up SFP+ link
3133  * @adapter: pointer to private adapter struct
3134  **/
3135 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3136 {
3137         struct ixgbe_hw *hw = &adapter->hw;
3138
3139                 if (hw->phy.multispeed_fiber) {
3140                         /*
3141                          * In multispeed fiber setups, the device may not have
3142                          * had a physical connection when the driver loaded.
3143                          * If that's the case, the initial link configuration
3144                          * couldn't get the MAC into 10G or 1G mode, so we'll
3145                          * never have a link status change interrupt fire.
3146                          * We need to try and force an autonegotiation
3147                          * session, then bring up link.
3148                          */
3149                         hw->mac.ops.setup_sfp(hw);
3150                         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
3151                                 schedule_work(&adapter->multispeed_fiber_task);
3152                 } else {
3153                         /*
3154                          * Direct Attach Cu and non-multispeed fiber modules
3155                          * still need to be configured properly prior to
3156                          * attempting link.
3157                          */
3158                         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
3159                                 schedule_work(&adapter->sfp_config_module_task);
3160                 }
3161 }
3162
3163 /**
3164  * ixgbe_non_sfp_link_config - set up non-SFP+ link
3165  * @hw: pointer to private hardware struct
3166  *
3167  * Returns 0 on success, negative on failure
3168  **/
3169 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
3170 {
3171         u32 autoneg;
3172         bool negotiation, link_up = false;
3173         u32 ret = IXGBE_ERR_LINK_SETUP;
3174
3175         if (hw->mac.ops.check_link)
3176                 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3177
3178         if (ret)
3179                 goto link_cfg_out;
3180
3181         if (hw->mac.ops.get_link_capabilities)
3182                 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
3183         if (ret)
3184                 goto link_cfg_out;
3185
3186         if (hw->mac.ops.setup_link)
3187                 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
3188 link_cfg_out:
3189         return ret;
3190 }
3191
3192 #define IXGBE_MAX_RX_DESC_POLL 10
3193 static inline void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
3194                                               int rxr)
3195 {
3196         int j = adapter->rx_ring[rxr]->reg_idx;
3197         int k;
3198
3199         for (k = 0; k < IXGBE_MAX_RX_DESC_POLL; k++) {
3200                 if (IXGBE_READ_REG(&adapter->hw,
3201                                    IXGBE_RXDCTL(j)) & IXGBE_RXDCTL_ENABLE)
3202                         break;
3203                 else
3204                         msleep(1);
3205         }
3206         if (k >= IXGBE_MAX_RX_DESC_POLL) {
3207                 DPRINTK(DRV, ERR, "RXDCTL.ENABLE on Rx queue %d "
3208                         "not set within the polling period\n", rxr);
3209         }
3210         ixgbe_release_rx_desc(&adapter->hw, adapter->rx_ring[rxr],
3211                               (adapter->rx_ring[rxr]->count - 1));
3212 }
3213
3214 static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
3215 {
3216         struct net_device *netdev = adapter->netdev;
3217         struct ixgbe_hw *hw = &adapter->hw;
3218         int i, j = 0;
3219         int num_rx_rings = adapter->num_rx_queues;
3220         int err;
3221         int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3222         u32 txdctl, rxdctl, mhadd;
3223         u32 dmatxctl;
3224         u32 gpie;
3225         u32 ctrl_ext;
3226
3227         ixgbe_get_hw_control(adapter);
3228
3229         if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) ||
3230             (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) {
3231                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3232                         gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME |
3233                                 IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD);
3234                 } else {
3235                         /* MSI only */
3236                         gpie = 0;
3237                 }
3238                 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3239                         gpie &= ~IXGBE_GPIE_VTMODE_MASK;
3240                         gpie |= IXGBE_GPIE_VTMODE_64;
3241                 }
3242                 /* XXX: to interrupt immediately for EICS writes, enable this */
3243                 /* gpie |= IXGBE_GPIE_EIMEN; */
3244                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3245         }
3246
3247         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3248                 /*
3249                  * use EIAM to auto-mask when MSI-X interrupt is asserted
3250                  * this saves a register write for every interrupt
3251                  */
3252                 switch (hw->mac.type) {
3253                 case ixgbe_mac_82598EB:
3254                         IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3255                         break;
3256                 default:
3257                 case ixgbe_mac_82599EB:
3258                         IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3259                         IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3260                         break;
3261                 }
3262         } else {
3263                 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3264                  * specifically only auto mask tx and rx interrupts */
3265                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3266         }
3267
3268         /* Enable fan failure interrupt if media type is copper */
3269         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3270                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
3271                 gpie |= IXGBE_SDP1_GPIEN;
3272                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3273         }
3274
3275         if (hw->mac.type == ixgbe_mac_82599EB) {
3276                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
3277                 gpie |= IXGBE_SDP1_GPIEN;
3278                 gpie |= IXGBE_SDP2_GPIEN;
3279                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3280         }
3281
3282 #ifdef IXGBE_FCOE
3283         /* adjust max frame to be able to do baby jumbo for FCoE */
3284         if ((netdev->features & NETIF_F_FCOE_MTU) &&
3285             (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3286                 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3287
3288 #endif /* IXGBE_FCOE */
3289         mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3290         if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3291                 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3292                 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3293
3294                 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3295         }
3296
3297         for (i = 0; i < adapter->num_tx_queues; i++) {
3298                 j = adapter->tx_ring[i]->reg_idx;
3299                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3300                 if (adapter->rx_itr_setting == 0) {
3301                         /* cannot set wthresh when itr==0 */
3302                         txdctl &= ~0x007F0000;
3303                 } else {
3304                         /* enable WTHRESH=8 descriptors, to encourage burst writeback */
3305                         txdctl |= (8 << 16);
3306                 }
3307                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
3308         }
3309
3310         if (hw->mac.type == ixgbe_mac_82599EB) {
3311                 /* DMATXCTL.EN must be set after all Tx queue config is done */
3312                 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
3313                 dmatxctl |= IXGBE_DMATXCTL_TE;
3314                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
3315         }
3316         for (i = 0; i < adapter->num_tx_queues; i++) {
3317                 j = adapter->tx_ring[i]->reg_idx;
3318                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3319                 txdctl |= IXGBE_TXDCTL_ENABLE;
3320                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
3321                 if (hw->mac.type == ixgbe_mac_82599EB) {
3322                         int wait_loop = 10;
3323                         /* poll for Tx Enable ready */
3324                         do {
3325                                 msleep(1);
3326                                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3327                         } while (--wait_loop &&
3328                                  !(txdctl & IXGBE_TXDCTL_ENABLE));
3329                         if (!wait_loop)
3330                                 DPRINTK(DRV, ERR, "Could not enable "
3331                                         "Tx Queue %d\n", j);
3332                 }
3333         }
3334
3335         for (i = 0; i < num_rx_rings; i++) {
3336                 j = adapter->rx_ring[i]->reg_idx;
3337                 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3338                 /* enable PTHRESH=32 descriptors (half the internal cache)
3339                  * and HTHRESH=0 descriptors (to minimize latency on fetch),
3340                  * this also removes a pesky rx_no_buffer_count increment */
3341                 rxdctl |= 0x0020;
3342                 rxdctl |= IXGBE_RXDCTL_ENABLE;
3343                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl);
3344                 if (hw->mac.type == ixgbe_mac_82599EB)
3345                         ixgbe_rx_desc_queue_enable(adapter, i);
3346         }
3347         /* enable all receives */
3348         rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3349         if (hw->mac.type == ixgbe_mac_82598EB)
3350                 rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN);
3351         else
3352                 rxdctl |= IXGBE_RXCTRL_RXEN;
3353         hw->mac.ops.enable_rx_dma(hw, rxdctl);
3354
3355         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3356                 ixgbe_configure_msix(adapter);
3357         else
3358                 ixgbe_configure_msi_and_legacy(adapter);
3359
3360         /* enable the optics */
3361         if (hw->phy.multispeed_fiber)
3362                 hw->mac.ops.enable_tx_laser(hw);
3363
3364         clear_bit(__IXGBE_DOWN, &adapter->state);
3365         ixgbe_napi_enable_all(adapter);
3366
3367         /* clear any pending interrupts, may auto mask */
3368         IXGBE_READ_REG(hw, IXGBE_EICR);
3369
3370         ixgbe_irq_enable(adapter);
3371
3372         /*
3373          * If this adapter has a fan, check to see if we had a failure
3374          * before we enabled the interrupt.
3375          */
3376         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3377                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3378                 if (esdp & IXGBE_ESDP_SDP1)
3379                         DPRINTK(DRV, CRIT,
3380                                 "Fan has stopped, replace the adapter\n");
3381         }
3382
3383         /*
3384          * For hot-pluggable SFP+ devices, a new SFP+ module may have
3385          * arrived before interrupts were enabled but after probe.  Such
3386          * devices wouldn't have their type identified yet. We need to
3387          * kick off the SFP+ module setup first, then try to bring up link.
3388          * If we're not hot-pluggable SFP+, we just need to configure link
3389          * and bring it up.
3390          */
3391         if (hw->phy.type == ixgbe_phy_unknown) {
3392                 err = hw->phy.ops.identify(hw);
3393                 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
3394                         /*
3395                          * Take the device down and schedule the sfp tasklet
3396                          * which will unregister_netdev and log it.
3397                          */
3398                         ixgbe_down(adapter);
3399                         schedule_work(&adapter->sfp_config_module_task);
3400                         return err;
3401                 }
3402         }
3403
3404         if (ixgbe_is_sfp(hw)) {
3405                 ixgbe_sfp_link_config(adapter);
3406         } else {
3407                 err = ixgbe_non_sfp_link_config(hw);
3408                 if (err)
3409                         DPRINTK(PROBE, ERR, "link_config FAILED %d\n", err);
3410         }
3411
3412         for (i = 0; i < adapter->num_tx_queues; i++)
3413                 set_bit(__IXGBE_FDIR_INIT_DONE,
3414                         &(adapter->tx_ring[i]->reinit_state));
3415
3416         /* enable transmits */
3417         netif_tx_start_all_queues(netdev);
3418
3419         /* bring the link up in the watchdog, this could race with our first
3420          * link up interrupt but shouldn't be a problem */
3421         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3422         adapter->link_check_timeout = jiffies;
3423         mod_timer(&adapter->watchdog_timer, jiffies);
3424
3425         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3426         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3427         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
3428         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3429
3430         return 0;
3431 }
3432
3433 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
3434 {
3435         WARN_ON(in_interrupt());
3436         while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
3437                 msleep(1);
3438         ixgbe_down(adapter);
3439         /*
3440          * If SR-IOV enabled then wait a bit before bringing the adapter
3441          * back up to give the VFs time to respond to the reset.  The
3442          * two second wait is based upon the watchdog timer cycle in
3443          * the VF driver.
3444          */
3445         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3446                 msleep(2000);
3447         ixgbe_up(adapter);
3448         clear_bit(__IXGBE_RESETTING, &adapter->state);
3449 }
3450
3451 int ixgbe_up(struct ixgbe_adapter *adapter)
3452 {
3453         /* hardware has been reset, we need to reload some things */
3454         ixgbe_configure(adapter);
3455
3456         return ixgbe_up_complete(adapter);
3457 }
3458
3459 void ixgbe_reset(struct ixgbe_adapter *adapter)
3460 {
3461         struct ixgbe_hw *hw = &adapter->hw;
3462         int err;
3463
3464         err = hw->mac.ops.init_hw(hw);
3465         switch (err) {
3466         case 0:
3467         case IXGBE_ERR_SFP_NOT_PRESENT:
3468                 break;
3469         case IXGBE_ERR_MASTER_REQUESTS_PENDING:
3470                 dev_err(&adapter->pdev->dev, "master disable timed out\n");
3471                 break;
3472         case IXGBE_ERR_EEPROM_VERSION:
3473                 /* We are running on a pre-production device, log a warning */
3474                 dev_warn(&adapter->pdev->dev, "This device is a pre-production "
3475                          "adapter/LOM.  Please be aware there may be issues "
3476                          "associated with your hardware.  If you are "
3477                          "experiencing problems please contact your Intel or "
3478                          "hardware representative who provided you with this "
3479                          "hardware.\n");
3480                 break;
3481         default:
3482                 dev_err(&adapter->pdev->dev, "Hardware Error: %d\n", err);
3483         }
3484
3485         /* reprogram the RAR[0] in case user changed it. */
3486         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
3487                             IXGBE_RAH_AV);
3488 }
3489
3490 /**
3491  * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
3492  * @adapter: board private structure
3493  * @rx_ring: ring to free buffers from
3494  **/
3495 static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
3496                                 struct ixgbe_ring *rx_ring)
3497 {
3498         struct pci_dev *pdev = adapter->pdev;
3499         unsigned long size;
3500         unsigned int i;
3501
3502         /* Free all the Rx ring sk_buffs */
3503
3504         for (i = 0; i < rx_ring->count; i++) {
3505                 struct ixgbe_rx_buffer *rx_buffer_info;
3506
3507                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
3508                 if (rx_buffer_info->dma) {
3509                         dma_unmap_single(&pdev->dev, rx_buffer_info->dma,
3510                                          rx_ring->rx_buf_len,
3511                                          DMA_FROM_DEVICE);
3512                         rx_buffer_info->dma = 0;
3513                 }
3514                 if (rx_buffer_info->skb) {
3515                         struct sk_buff *skb = rx_buffer_info->skb;
3516                         rx_buffer_info->skb = NULL;
3517                         do {
3518                                 struct sk_buff *this = skb;
3519                                 if (IXGBE_RSC_CB(this)->delay_unmap) {
3520                                         dma_unmap_single(&pdev->dev,
3521                                                          IXGBE_RSC_CB(this)->dma,
3522                                                          rx_ring->rx_buf_len,
3523                                                          DMA_FROM_DEVICE);
3524                                         IXGBE_RSC_CB(this)->dma = 0;
3525                                         IXGBE_RSC_CB(skb)->delay_unmap = false;
3526                                 }
3527                                 skb = skb->prev;
3528                                 dev_kfree_skb(this);
3529                         } while (skb);
3530                 }
3531                 if (!rx_buffer_info->page)
3532                         continue;
3533                 if (rx_buffer_info->page_dma) {
3534                         dma_unmap_page(&pdev->dev, rx_buffer_info->page_dma,
3535                                        PAGE_SIZE / 2, DMA_FROM_DEVICE);
3536                         rx_buffer_info->page_dma = 0;
3537                 }
3538                 put_page(rx_buffer_info->page);
3539                 rx_buffer_info->page = NULL;
3540                 rx_buffer_info->page_offset = 0;
3541         }
3542
3543         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
3544         memset(rx_ring->rx_buffer_info, 0, size);
3545
3546         /* Zero out the descriptor ring */
3547         memset(rx_ring->desc, 0, rx_ring->size);
3548
3549         rx_ring->next_to_clean = 0;
3550         rx_ring->next_to_use = 0;
3551
3552         if (rx_ring->head)
3553                 writel(0, adapter->hw.hw_addr + rx_ring->head);
3554         if (rx_ring->tail)
3555                 writel(0, adapter->hw.hw_addr + rx_ring->tail);
3556 }
3557
3558 /**
3559  * ixgbe_clean_tx_ring - Free Tx Buffers
3560  * @adapter: board private structure
3561  * @tx_ring: ring to be cleaned
3562  **/
3563 static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
3564                                 struct ixgbe_ring *tx_ring)
3565 {
3566         struct ixgbe_tx_buffer *tx_buffer_info;
3567         unsigned long size;
3568         unsigned int i;
3569
3570         /* Free all the Tx ring sk_buffs */
3571
3572         for (i = 0; i < tx_ring->count; i++) {
3573                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3574                 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
3575         }
3576
3577         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3578         memset(tx_ring->tx_buffer_info, 0, size);
3579
3580         /* Zero out the descriptor ring */
3581         memset(tx_ring->desc, 0, tx_ring->size);
3582
3583         tx_ring->next_to_use = 0;
3584         tx_ring->next_to_clean = 0;
3585
3586         if (tx_ring->head)
3587                 writel(0, adapter->hw.hw_addr + tx_ring->head);
3588         if (tx_ring->tail)
3589                 writel(0, adapter->hw.hw_addr + tx_ring->tail);
3590 }
3591
3592 /**
3593  * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
3594  * @adapter: board private structure
3595  **/
3596 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
3597 {
3598         int i;
3599
3600         for (i = 0; i < adapter->num_rx_queues; i++)
3601                 ixgbe_clean_rx_ring(adapter, adapter->rx_ring[i]);
3602 }
3603
3604 /**
3605  * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
3606  * @adapter: board private structure
3607  **/
3608 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
3609 {
3610         int i;
3611
3612         for (i = 0; i < adapter->num_tx_queues; i++)
3613                 ixgbe_clean_tx_ring(adapter, adapter->tx_ring[i]);
3614 }
3615
3616 void ixgbe_down(struct ixgbe_adapter *adapter)
3617 {
3618         struct net_device *netdev = adapter->netdev;
3619         struct ixgbe_hw *hw = &adapter->hw;
3620         u32 rxctrl;
3621         u32 txdctl;
3622         int i, j;
3623
3624         /* signal that we are down to the interrupt handler */
3625         set_bit(__IXGBE_DOWN, &adapter->state);
3626
3627         /* power down the optics */
3628         if (hw->phy.multispeed_fiber)
3629                 hw->mac.ops.disable_tx_laser(hw);
3630
3631         /* disable receive for all VFs and wait one second */
3632         if (adapter->num_vfs) {
3633                 /* ping all the active vfs to let them know we are going down */
3634                 ixgbe_ping_all_vfs(adapter);
3635
3636                 /* Disable all VFTE/VFRE TX/RX */
3637                 ixgbe_disable_tx_rx(adapter);
3638
3639                 /* Mark all the VFs as inactive */
3640                 for (i = 0 ; i < adapter->num_vfs; i++)
3641                         adapter->vfinfo[i].clear_to_send = 0;
3642         }
3643
3644         /* disable receives */
3645         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3646         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3647
3648         IXGBE_WRITE_FLUSH(hw);
3649         msleep(10);
3650
3651         netif_tx_stop_all_queues(netdev);
3652
3653         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
3654         del_timer_sync(&adapter->sfp_timer);
3655         del_timer_sync(&adapter->watchdog_timer);
3656         cancel_work_sync(&adapter->watchdog_task);
3657
3658         netif_carrier_off(netdev);
3659         netif_tx_disable(netdev);
3660
3661         ixgbe_irq_disable(adapter);
3662
3663         ixgbe_napi_disable_all(adapter);
3664
3665         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3666             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
3667                 cancel_work_sync(&adapter->fdir_reinit_task);
3668
3669         /* disable transmits in the hardware now that interrupts are off */
3670         for (i = 0; i < adapter->num_tx_queues; i++) {
3671                 j = adapter->tx_ring[i]->reg_idx;
3672                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3673                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j),
3674                                 (txdctl & ~IXGBE_TXDCTL_ENABLE));
3675         }
3676         /* Disable the Tx DMA engine on 82599 */
3677         if (hw->mac.type == ixgbe_mac_82599EB)
3678                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
3679                                 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
3680                                  ~IXGBE_DMATXCTL_TE));
3681
3682         /* clear n-tuple filters that are cached */
3683         ethtool_ntuple_flush(netdev);
3684
3685         if (!pci_channel_offline(adapter->pdev))
3686                 ixgbe_reset(adapter);
3687         ixgbe_clean_all_tx_rings(adapter);
3688         ixgbe_clean_all_rx_rings(adapter);
3689
3690 #ifdef CONFIG_IXGBE_DCA
3691         /* since we reset the hardware DCA settings were cleared */
3692         ixgbe_setup_dca(adapter);
3693 #endif
3694 }
3695
3696 /**
3697  * ixgbe_poll - NAPI Rx polling callback
3698  * @napi: structure for representing this polling device
3699  * @budget: how many packets driver is allowed to clean
3700  *
3701  * This function is used for legacy and MSI, NAPI mode
3702  **/
3703 static int ixgbe_poll(struct napi_struct *napi, int budget)
3704 {
3705         struct ixgbe_q_vector *q_vector =
3706                                 container_of(napi, struct ixgbe_q_vector, napi);
3707         struct ixgbe_adapter *adapter = q_vector->adapter;
3708         int tx_clean_complete, work_done = 0;
3709
3710 #ifdef CONFIG_IXGBE_DCA
3711         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
3712                 ixgbe_update_tx_dca(adapter, adapter->tx_ring[0]);
3713                 ixgbe_update_rx_dca(adapter, adapter->rx_ring[0]);
3714         }
3715 #endif
3716
3717         tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring[0]);
3718         ixgbe_clean_rx_irq(q_vector, adapter->rx_ring[0], &work_done, budget);
3719
3720         if (!tx_clean_complete)
3721                 work_done = budget;
3722
3723         /* If budget not fully consumed, exit the polling mode */
3724         if (work_done < budget) {
3725                 napi_complete(napi);
3726                 if (adapter->rx_itr_setting & 1)
3727                         ixgbe_set_itr(adapter);
3728                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
3729                         ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
3730         }
3731         return work_done;
3732 }
3733
3734 /**
3735  * ixgbe_tx_timeout - Respond to a Tx Hang
3736  * @netdev: network interface device structure
3737  **/
3738 static void ixgbe_tx_timeout(struct net_device *netdev)
3739 {
3740         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3741
3742         /* Do the reset outside of interrupt context */
3743         schedule_work(&adapter->reset_task);
3744 }
3745
3746 static void ixgbe_reset_task(struct work_struct *work)
3747 {
3748         struct ixgbe_adapter *adapter;
3749         adapter = container_of(work, struct ixgbe_adapter, reset_task);
3750
3751         /* If we're already down or resetting, just bail */
3752         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
3753             test_bit(__IXGBE_RESETTING, &adapter->state))
3754                 return;
3755
3756         adapter->tx_timeout_count++;
3757
3758         ixgbe_dump(adapter);
3759         netdev_err(adapter->netdev, "Reset adapter\n");
3760         ixgbe_reinit_locked(adapter);
3761 }
3762
3763 #ifdef CONFIG_IXGBE_DCB
3764 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
3765 {
3766         bool ret = false;
3767         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB];
3768
3769         if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
3770                 return ret;
3771
3772         f->mask = 0x7 << 3;
3773         adapter->num_rx_queues = f->indices;
3774         adapter->num_tx_queues = f->indices;
3775         ret = true;
3776
3777         return ret;
3778 }
3779 #endif
3780
3781 /**
3782  * ixgbe_set_rss_queues: Allocate queues for RSS
3783  * @adapter: board private structure to initialize
3784  *
3785  * This is our "base" multiqueue mode.  RSS (Receive Side Scaling) will try
3786  * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
3787  *
3788  **/
3789 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
3790 {
3791         bool ret = false;
3792         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
3793
3794         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3795                 f->mask = 0xF;
3796                 adapter->num_rx_queues = f->indices;
3797                 adapter->num_tx_queues = f->indices;
3798                 ret = true;
3799         } else {
3800                 ret = false;
3801         }
3802
3803         return ret;
3804 }
3805
3806 /**
3807  * ixgbe_set_fdir_queues: Allocate queues for Flow Director
3808  * @adapter: board private structure to initialize
3809  *
3810  * Flow Director is an advanced Rx filter, attempting to get Rx flows back
3811  * to the original CPU that initiated the Tx session.  This runs in addition
3812  * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
3813  * Rx load across CPUs using RSS.
3814  *
3815  **/
3816 static bool inline ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
3817 {
3818         bool ret = false;
3819         struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
3820
3821         f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
3822         f_fdir->mask = 0;
3823
3824         /* Flow Director must have RSS enabled */
3825         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
3826             ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3827              (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) {
3828                 adapter->num_tx_queues = f_fdir->indices;
3829                 adapter->num_rx_queues = f_fdir->indices;
3830                 ret = true;
3831         } else {
3832                 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
3833                 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
3834         }
3835         return ret;
3836 }
3837
3838 #ifdef IXGBE_FCOE
3839 /**
3840  * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
3841  * @adapter: board private structure to initialize
3842  *
3843  * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
3844  * The ring feature mask is not used as a mask for FCoE, as it can take any 8
3845  * rx queues out of the max number of rx queues, instead, it is used as the
3846  * index of the first rx queue used by FCoE.
3847  *
3848  **/
3849 static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
3850 {
3851         bool ret = false;
3852         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
3853
3854         f->indices = min((int)num_online_cpus(), f->indices);
3855         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
3856                 adapter->num_rx_queues = 1;
3857                 adapter->num_tx_queues = 1;
3858 #ifdef CONFIG_IXGBE_DCB
3859                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3860                         DPRINTK(PROBE, INFO, "FCoE enabled with DCB\n");
3861                         ixgbe_set_dcb_queues(adapter);
3862                 }
3863 #endif
3864                 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3865                         DPRINTK(PROBE, INFO, "FCoE enabled with RSS\n");
3866                         if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3867                             (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
3868                                 ixgbe_set_fdir_queues(adapter);
3869                         else
3870                                 ixgbe_set_rss_queues(adapter);
3871                 }
3872                 /* adding FCoE rx rings to the end */
3873                 f->mask = adapter->num_rx_queues;
3874                 adapter->num_rx_queues += f->indices;
3875                 adapter->num_tx_queues += f->indices;
3876
3877                 ret = true;
3878         }
3879
3880         return ret;
3881 }
3882
3883 #endif /* IXGBE_FCOE */
3884 /**
3885  * ixgbe_set_sriov_queues: Allocate queues for IOV use
3886  * @adapter: board private structure to initialize
3887  *
3888  * IOV doesn't actually use anything, so just NAK the
3889  * request for now and let the other queue routines
3890  * figure out what to do.
3891  */
3892 static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
3893 {
3894         return false;
3895 }
3896
3897 /*
3898  * ixgbe_set_num_queues: Allocate queues for device, feature dependant
3899  * @adapter: board private structure to initialize
3900  *
3901  * This is the top level queue allocation routine.  The order here is very
3902  * important, starting with the "most" number of features turned on at once,
3903  * and ending with the smallest set of features.  This way large combinations
3904  * can be allocated if they're turned on, and smaller combinations are the
3905  * fallthrough conditions.
3906  *
3907  **/
3908 static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
3909 {
3910         /* Start with base case */
3911         adapter->num_rx_queues = 1;
3912         adapter->num_tx_queues = 1;
3913         adapter->num_rx_pools = adapter->num_rx_queues;
3914         adapter->num_rx_queues_per_pool = 1;
3915
3916         if (ixgbe_set_sriov_queues(adapter))
3917                 return;
3918
3919 #ifdef IXGBE_FCOE
3920         if (ixgbe_set_fcoe_queues(adapter))
3921                 goto done;
3922
3923 #endif /* IXGBE_FCOE */
3924 #ifdef CONFIG_IXGBE_DCB
3925         if (ixgbe_set_dcb_queues(adapter))
3926                 goto done;
3927
3928 #endif
3929         if (ixgbe_set_fdir_queues(adapter))
3930                 goto done;
3931
3932         if (ixgbe_set_rss_queues(adapter))
3933                 goto done;
3934
3935         /* fallback to base case */
3936         adapter->num_rx_queues = 1;
3937         adapter->num_tx_queues = 1;
3938
3939 done:
3940         /* Notify the stack of the (possibly) reduced Tx Queue count. */
3941         adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
3942 }
3943
3944 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
3945                                        int vectors)
3946 {
3947         int err, vector_threshold;
3948
3949         /* We'll want at least 3 (vector_threshold):
3950          * 1) TxQ[0] Cleanup
3951          * 2) RxQ[0] Cleanup
3952          * 3) Other (Link Status Change, etc.)
3953          * 4) TCP Timer (optional)
3954          */
3955         vector_threshold = MIN_MSIX_COUNT;
3956
3957         /* The more we get, the more we will assign to Tx/Rx Cleanup
3958          * for the separate queues...where Rx Cleanup >= Tx Cleanup.
3959          * Right now, we simply care about how many we'll get; we'll
3960          * set them up later while requesting irq's.
3961          */
3962         while (vectors >= vector_threshold) {
3963                 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
3964                                       vectors);
3965                 if (!err) /* Success in acquiring all requested vectors. */
3966                         break;
3967                 else if (err < 0)
3968                         vectors = 0; /* Nasty failure, quit now */
3969                 else /* err == number of vectors we should try again with */
3970                         vectors = err;
3971         }
3972
3973         if (vectors < vector_threshold) {
3974                 /* Can't allocate enough MSI-X interrupts?  Oh well.
3975                  * This just means we'll go with either a single MSI
3976                  * vector or fall back to legacy interrupts.
3977                  */
3978                 DPRINTK(HW, DEBUG, "Unable to allocate MSI-X interrupts\n");
3979                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
3980                 kfree(adapter->msix_entries);
3981                 adapter->msix_entries = NULL;
3982         } else {
3983                 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
3984                 /*
3985                  * Adjust for only the vectors we'll use, which is minimum
3986                  * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
3987                  * vectors we were allocated.
3988                  */
3989                 adapter->num_msix_vectors = min(vectors,
3990                                    adapter->max_msix_q_vectors + NON_Q_VECTORS);
3991         }
3992 }
3993
3994 /**
3995  * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
3996  * @adapter: board private structure to initialize
3997  *
3998  * Cache the descriptor ring offsets for RSS to the assigned rings.
3999  *
4000  **/
4001 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
4002 {
4003         int i;
4004         bool ret = false;
4005
4006         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4007                 for (i = 0; i < adapter->num_rx_queues; i++)
4008                         adapter->rx_ring[i]->reg_idx = i;
4009                 for (i = 0; i < adapter->num_tx_queues; i++)
4010                         adapter->tx_ring[i]->reg_idx = i;
4011                 ret = true;
4012         } else {
4013                 ret = false;
4014         }
4015
4016         return ret;
4017 }
4018
4019 #ifdef CONFIG_IXGBE_DCB
4020 /**
4021  * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4022  * @adapter: board private structure to initialize
4023  *
4024  * Cache the descriptor ring offsets for DCB to the assigned rings.
4025  *
4026  **/
4027 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
4028 {
4029         int i;
4030         bool ret = false;
4031         int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
4032
4033         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4034                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
4035                         /* the number of queues is assumed to be symmetric */
4036                         for (i = 0; i < dcb_i; i++) {
4037                                 adapter->rx_ring[i]->reg_idx = i << 3;
4038                                 adapter->tx_ring[i]->reg_idx = i << 2;
4039                         }
4040                         ret = true;
4041                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
4042                         if (dcb_i == 8) {
4043                                 /*
4044                                  * Tx TC0 starts at: descriptor queue 0
4045                                  * Tx TC1 starts at: descriptor queue 32
4046                                  * Tx TC2 starts at: descriptor queue 64
4047                                  * Tx TC3 starts at: descriptor queue 80
4048                                  * Tx TC4 starts at: descriptor queue 96
4049                                  * Tx TC5 starts at: descriptor queue 104
4050                                  * Tx TC6 starts at: descriptor queue 112
4051                                  * Tx TC7 starts at: descriptor queue 120
4052                                  *
4053                                  * Rx TC0-TC7 are offset by 16 queues each
4054                                  */
4055                                 for (i = 0; i < 3; i++) {
4056                                         adapter->tx_ring[i]->reg_idx = i << 5;
4057                                         adapter->rx_ring[i]->reg_idx = i << 4;
4058                                 }
4059                                 for ( ; i < 5; i++) {
4060                                         adapter->tx_ring[i]->reg_idx =
4061                                                                  ((i + 2) << 4);
4062                                         adapter->rx_ring[i]->reg_idx = i << 4;
4063                                 }
4064                                 for ( ; i < dcb_i; i++) {
4065                                         adapter->tx_ring[i]->reg_idx =
4066                                                                  ((i + 8) << 3);
4067                                         adapter->rx_ring[i]->reg_idx = i << 4;
4068                                 }
4069
4070                                 ret = true;
4071                         } else if (dcb_i == 4) {
4072                                 /*
4073                                  * Tx TC0 starts at: descriptor queue 0
4074                                  * Tx TC1 starts at: descriptor queue 64
4075                                  * Tx TC2 starts at: descriptor queue 96
4076                                  * Tx TC3 starts at: descriptor queue 112
4077                                  *
4078                                  * Rx TC0-TC3 are offset by 32 queues each
4079                                  */
4080                                 adapter->tx_ring[0]->reg_idx = 0;
4081                                 adapter->tx_ring[1]->reg_idx = 64;
4082                                 adapter->tx_ring[2]->reg_idx = 96;
4083                                 adapter->tx_ring[3]->reg_idx = 112;
4084                                 for (i = 0 ; i < dcb_i; i++)
4085                                         adapter->rx_ring[i]->reg_idx = i << 5;
4086
4087                                 ret = true;
4088                         } else {
4089                                 ret = false;
4090                         }
4091                 } else {
4092                         ret = false;
4093                 }
4094         } else {
4095                 ret = false;
4096         }
4097
4098         return ret;
4099 }
4100 #endif
4101
4102 /**
4103  * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
4104  * @adapter: board private structure to initialize
4105  *
4106  * Cache the descriptor ring offsets for Flow Director to the assigned rings.
4107  *
4108  **/
4109 static bool inline ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
4110 {
4111         int i;
4112         bool ret = false;
4113
4114         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
4115             ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4116              (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) {
4117                 for (i = 0; i < adapter->num_rx_queues; i++)
4118                         adapter->rx_ring[i]->reg_idx = i;
4119                 for (i = 0; i < adapter->num_tx_queues; i++)
4120                         adapter->tx_ring[i]->reg_idx = i;
4121                 ret = true;
4122         }
4123
4124         return ret;
4125 }
4126
4127 #ifdef IXGBE_FCOE
4128 /**
4129  * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
4130  * @adapter: board private structure to initialize
4131  *
4132  * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
4133  *
4134  */
4135 static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
4136 {
4137         int i, fcoe_rx_i = 0, fcoe_tx_i = 0;
4138         bool ret = false;
4139         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4140
4141         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
4142 #ifdef CONFIG_IXGBE_DCB
4143                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4144                         struct ixgbe_fcoe *fcoe = &adapter->fcoe;
4145
4146                         ixgbe_cache_ring_dcb(adapter);
4147                         /* find out queues in TC for FCoE */
4148                         fcoe_rx_i = adapter->rx_ring[fcoe->tc]->reg_idx + 1;
4149                         fcoe_tx_i = adapter->tx_ring[fcoe->tc]->reg_idx + 1;
4150                         /*
4151                          * In 82599, the number of Tx queues for each traffic
4152                          * class for both 8-TC and 4-TC modes are:
4153                          * TCs  : TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7
4154                          * 8 TCs:  32  32  16  16   8   8   8   8
4155                          * 4 TCs:  64  64  32  32
4156                          * We have max 8 queues for FCoE, where 8 the is
4157                          * FCoE redirection table size. If TC for FCoE is
4158                          * less than or equal to TC3, we have enough queues
4159                          * to add max of 8 queues for FCoE, so we start FCoE
4160                          * tx descriptor from the next one, i.e., reg_idx + 1.
4161                          * If TC for FCoE is above TC3, implying 8 TC mode,
4162                          * and we need 8 for FCoE, we have to take all queues
4163                          * in that traffic class for FCoE.
4164                          */
4165                         if ((f->indices == IXGBE_FCRETA_SIZE) && (fcoe->tc > 3))
4166                                 fcoe_tx_i--;
4167                 }
4168 #endif /* CONFIG_IXGBE_DCB */
4169                 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4170                         if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4171                             (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
4172                                 ixgbe_cache_ring_fdir(adapter);
4173                         else
4174                                 ixgbe_cache_ring_rss(adapter);
4175
4176                         fcoe_rx_i = f->mask;
4177                         fcoe_tx_i = f->mask;
4178                 }
4179                 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
4180                         adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
4181                         adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
4182                 }
4183                 ret = true;
4184         }
4185         return ret;
4186 }
4187
4188 #endif /* IXGBE_FCOE */
4189 /**
4190  * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
4191  * @adapter: board private structure to initialize
4192  *
4193  * SR-IOV doesn't use any descriptor rings but changes the default if
4194  * no other mapping is used.
4195  *
4196  */
4197 static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
4198 {
4199         adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2;
4200         adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2;
4201         if (adapter->num_vfs)
4202                 return true;
4203         else
4204                 return false;
4205 }
4206
4207 /**
4208  * ixgbe_cache_ring_register - Descriptor ring to register mapping
4209  * @adapter: board private structure to initialize
4210  *
4211  * Once we know the feature-set enabled for the device, we'll cache
4212  * the register offset the descriptor ring is assigned to.
4213  *
4214  * Note, the order the various feature calls is important.  It must start with
4215  * the "most" features enabled at the same time, then trickle down to the
4216  * least amount of features turned on at once.
4217  **/
4218 static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
4219 {
4220         /* start with default case */
4221         adapter->rx_ring[0]->reg_idx = 0;
4222         adapter->tx_ring[0]->reg_idx = 0;
4223
4224         if (ixgbe_cache_ring_sriov(adapter))
4225                 return;
4226
4227 #ifdef IXGBE_FCOE
4228         if (ixgbe_cache_ring_fcoe(adapter))
4229                 return;
4230
4231 #endif /* IXGBE_FCOE */
4232 #ifdef CONFIG_IXGBE_DCB
4233         if (ixgbe_cache_ring_dcb(adapter))
4234                 return;
4235
4236 #endif
4237         if (ixgbe_cache_ring_fdir(adapter))
4238                 return;
4239
4240         if (ixgbe_cache_ring_rss(adapter))
4241                 return;
4242 }
4243
4244 /**
4245  * ixgbe_alloc_queues - Allocate memory for all rings
4246  * @adapter: board private structure to initialize
4247  *
4248  * We allocate one ring per queue at run-time since we don't know the
4249  * number of queues at compile-time.  The polling_netdev array is
4250  * intended for Multiqueue, but should work fine with a single queue.
4251  **/
4252 static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
4253 {
4254         int i;
4255         int orig_node = adapter->node;
4256
4257         for (i = 0; i < adapter->num_tx_queues; i++) {
4258                 struct ixgbe_ring *ring = adapter->tx_ring[i];
4259                 if (orig_node == -1) {
4260                         int cur_node = next_online_node(adapter->node);
4261                         if (cur_node == MAX_NUMNODES)
4262                                 cur_node = first_online_node;
4263                         adapter->node = cur_node;
4264                 }
4265                 ring = kzalloc_node(sizeof(struct ixgbe_ring), GFP_KERNEL,
4266                                     adapter->node);
4267                 if (!ring)
4268                         ring = kzalloc(sizeof(struct ixgbe_ring), GFP_KERNEL);
4269                 if (!ring)
4270                         goto err_tx_ring_allocation;
4271                 ring->count = adapter->tx_ring_count;
4272                 ring->queue_index = i;
4273                 ring->numa_node = adapter->node;
4274
4275                 adapter->tx_ring[i] = ring;
4276         }
4277
4278         /* Restore the adapter's original node */
4279         adapter->node = orig_node;
4280
4281         for (i = 0; i < adapter->num_rx_queues; i++) {
4282                 struct ixgbe_ring *ring = adapter->rx_ring[i];
4283                 if (orig_node == -1) {
4284                         int cur_node = next_online_node(adapter->node);
4285                         if (cur_node == MAX_NUMNODES)
4286                                 cur_node = first_online_node;
4287                         adapter->node = cur_node;
4288                 }
4289                 ring = kzalloc_node(sizeof(struct ixgbe_ring), GFP_KERNEL,
4290                                     adapter->node);
4291                 if (!ring)
4292                         ring = kzalloc(sizeof(struct ixgbe_ring), GFP_KERNEL);
4293                 if (!ring)
4294                         goto err_rx_ring_allocation;
4295                 ring->count = adapter->rx_ring_count;
4296                 ring->queue_index = i;
4297                 ring->numa_node = adapter->node;
4298
4299                 adapter->rx_ring[i] = ring;
4300         }
4301
4302         /* Restore the adapter's original node */
4303         adapter->node = orig_node;
4304
4305         ixgbe_cache_ring_register(adapter);
4306
4307         return 0;
4308
4309 err_rx_ring_allocation:
4310         for (i = 0; i < adapter->num_tx_queues; i++)
4311                 kfree(adapter->tx_ring[i]);
4312 err_tx_ring_allocation:
4313         return -ENOMEM;
4314 }
4315
4316 /**
4317  * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
4318  * @adapter: board private structure to initialize
4319  *
4320  * Attempt to configure the interrupts using the best available
4321  * capabilities of the hardware and the kernel.
4322  **/
4323 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
4324 {
4325         struct ixgbe_hw *hw = &adapter->hw;
4326         int err = 0;
4327         int vector, v_budget;
4328
4329         /*
4330          * It's easy to be greedy for MSI-X vectors, but it really
4331          * doesn't do us much good if we have a lot more vectors
4332          * than CPU's.  So let's be conservative and only ask for
4333          * (roughly) the same number of vectors as there are CPU's.
4334          */
4335         v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
4336                        (int)num_online_cpus()) + NON_Q_VECTORS;
4337
4338         /*
4339          * At the same time, hardware can only support a maximum of
4340          * hw.mac->max_msix_vectors vectors.  With features
4341          * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
4342          * descriptor queues supported by our device.  Thus, we cap it off in
4343          * those rare cases where the cpu count also exceeds our vector limit.
4344          */
4345         v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
4346
4347         /* A failure in MSI-X entry allocation isn't fatal, but it does
4348          * mean we disable MSI-X capabilities of the adapter. */
4349         adapter->msix_entries = kcalloc(v_budget,
4350                                         sizeof(struct msix_entry), GFP_KERNEL);
4351         if (adapter->msix_entries) {
4352                 for (vector = 0; vector < v_budget; vector++)
4353                         adapter->msix_entries[vector].entry = vector;
4354
4355                 ixgbe_acquire_msix_vectors(adapter, v_budget);
4356
4357                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4358                         goto out;
4359         }
4360
4361         adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
4362         adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
4363         adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4364         adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4365         adapter->atr_sample_rate = 0;
4366         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4367                 ixgbe_disable_sriov(adapter);
4368
4369         ixgbe_set_num_queues(adapter);
4370
4371         err = pci_enable_msi(adapter->pdev);
4372         if (!err) {
4373                 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
4374         } else {
4375                 DPRINTK(HW, DEBUG, "Unable to allocate MSI interrupt, "
4376                         "falling back to legacy.  Error: %d\n", err);
4377                 /* reset err */
4378                 err = 0;
4379         }
4380
4381 out:
4382         return err;
4383 }
4384
4385 /**
4386  * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4387  * @adapter: board private structure to initialize
4388  *
4389  * We allocate one q_vector per queue interrupt.  If allocation fails we
4390  * return -ENOMEM.
4391  **/
4392 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
4393 {
4394         int q_idx, num_q_vectors;
4395         struct ixgbe_q_vector *q_vector;
4396         int napi_vectors;
4397         int (*poll)(struct napi_struct *, int);
4398
4399         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4400                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4401                 napi_vectors = adapter->num_rx_queues;
4402                 poll = &ixgbe_clean_rxtx_many;
4403         } else {
4404                 num_q_vectors = 1;
4405                 napi_vectors = 1;
4406                 poll = &ixgbe_poll;
4407         }
4408
4409         for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4410                 q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector),
4411                                         GFP_KERNEL, adapter->node);
4412                 if (!q_vector)
4413                         q_vector = kzalloc(sizeof(struct ixgbe_q_vector),
4414                                            GFP_KERNEL);
4415                 if (!q_vector)
4416                         goto err_out;
4417                 q_vector->adapter = adapter;
4418                 if (q_vector->txr_count && !q_vector->rxr_count)
4419                         q_vector->eitr = adapter->tx_eitr_param;
4420                 else
4421                         q_vector->eitr = adapter->rx_eitr_param;
4422                 q_vector->v_idx = q_idx;
4423                 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
4424                 adapter->q_vector[q_idx] = q_vector;
4425         }
4426
4427         return 0;
4428
4429 err_out:
4430         while (q_idx) {
4431                 q_idx--;
4432                 q_vector = adapter->q_vector[q_idx];
4433                 netif_napi_del(&q_vector->napi);
4434                 kfree(q_vector);
4435                 adapter->q_vector[q_idx] = NULL;
4436         }
4437         return -ENOMEM;
4438 }
4439
4440 /**
4441  * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
4442  * @adapter: board private structure to initialize
4443  *
4444  * This function frees the memory allocated to the q_vectors.  In addition if
4445  * NAPI is enabled it will delete any references to the NAPI struct prior
4446  * to freeing the q_vector.
4447  **/
4448 static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
4449 {
4450         int q_idx, num_q_vectors;
4451
4452         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4453                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4454         else
4455                 num_q_vectors = 1;
4456
4457         for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4458                 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
4459                 adapter->q_vector[q_idx] = NULL;
4460                 netif_napi_del(&q_vector->napi);
4461                 kfree(q_vector);
4462         }
4463 }
4464
4465 static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
4466 {
4467         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4468                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4469                 pci_disable_msix(adapter->pdev);
4470                 kfree(adapter->msix_entries);
4471                 adapter->msix_entries = NULL;
4472         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
4473                 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
4474                 pci_disable_msi(adapter->pdev);
4475         }
4476 }
4477
4478 /**
4479  * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
4480  * @adapter: board private structure to initialize
4481  *
4482  * We determine which interrupt scheme to use based on...
4483  * - Kernel support (MSI, MSI-X)
4484  *   - which can be user-defined (via MODULE_PARAM)
4485  * - Hardware queue count (num_*_queues)
4486  *   - defined by miscellaneous hardware support/features (RSS, etc.)
4487  **/
4488 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
4489 {
4490         int err;
4491
4492         /* Number of supported queues */
4493         ixgbe_set_num_queues(adapter);
4494
4495         err = ixgbe_set_interrupt_capability(adapter);
4496         if (err) {
4497                 DPRINTK(PROBE, ERR, "Unable to setup interrupt capabilities\n");
4498                 goto err_set_interrupt;
4499         }
4500
4501         err = ixgbe_alloc_q_vectors(adapter);
4502         if (err) {
4503                 DPRINTK(PROBE, ERR, "Unable to allocate memory for queue "
4504                         "vectors\n");
4505                 goto err_alloc_q_vectors;
4506         }
4507
4508         err = ixgbe_alloc_queues(adapter);
4509         if (err) {
4510                 DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n");
4511                 goto err_alloc_queues;
4512         }
4513
4514         DPRINTK(DRV, INFO, "Multiqueue %s: Rx Queue count = %u, "
4515                 "Tx Queue count = %u\n",
4516                 (adapter->num_rx_queues > 1) ? "Enabled" :
4517                 "Disabled", adapter->num_rx_queues, adapter->num_tx_queues);
4518
4519         set_bit(__IXGBE_DOWN, &adapter->state);
4520
4521         return 0;
4522
4523 err_alloc_queues:
4524         ixgbe_free_q_vectors(adapter);
4525 err_alloc_q_vectors:
4526         ixgbe_reset_interrupt_capability(adapter);
4527 err_set_interrupt:
4528         return err;
4529 }
4530
4531 /**
4532  * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
4533  * @adapter: board private structure to clear interrupt scheme on
4534  *
4535  * We go through and clear interrupt specific resources and reset the structure
4536  * to pre-load conditions
4537  **/
4538 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
4539 {
4540         int i;
4541
4542         for (i = 0; i < adapter->num_tx_queues; i++) {
4543                 kfree(adapter->tx_ring[i]);
4544                 adapter->tx_ring[i] = NULL;
4545         }
4546         for (i = 0; i < adapter->num_rx_queues; i++) {
4547                 kfree(adapter->rx_ring[i]);
4548                 adapter->rx_ring[i] = NULL;
4549         }
4550
4551         ixgbe_free_q_vectors(adapter);
4552         ixgbe_reset_interrupt_capability(adapter);
4553 }
4554
4555 /**
4556  * ixgbe_sfp_timer - worker thread to find a missing module
4557  * @data: pointer to our adapter struct
4558  **/
4559 static void ixgbe_sfp_timer(unsigned long data)
4560 {
4561         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
4562
4563         /*
4564          * Do the sfp_timer outside of interrupt context due to the
4565          * delays that sfp+ detection requires
4566          */
4567         schedule_work(&adapter->sfp_task);
4568 }
4569
4570 /**
4571  * ixgbe_sfp_task - worker thread to find a missing module
4572  * @work: pointer to work_struct containing our data
4573  **/
4574 static void ixgbe_sfp_task(struct work_struct *work)
4575 {
4576         struct ixgbe_adapter *adapter = container_of(work,
4577                                                      struct ixgbe_adapter,
4578                                                      sfp_task);
4579         struct ixgbe_hw *hw = &adapter->hw;
4580
4581         if ((hw->phy.type == ixgbe_phy_nl) &&
4582             (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
4583                 s32 ret = hw->phy.ops.identify_sfp(hw);
4584                 if (ret == IXGBE_ERR_SFP_NOT_PRESENT)
4585                         goto reschedule;
4586                 ret = hw->phy.ops.reset(hw);
4587                 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
4588                         dev_err(&adapter->pdev->dev, "failed to initialize "
4589                                 "because an unsupported SFP+ module type "
4590                                 "was detected.\n"
4591                                 "Reload the driver after installing a "
4592                                 "supported module.\n");
4593                         unregister_netdev(adapter->netdev);
4594                 } else {
4595                         DPRINTK(PROBE, INFO, "detected SFP+: %d\n",
4596                                 hw->phy.sfp_type);
4597                 }
4598                 /* don't need this routine any more */
4599                 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
4600         }
4601         return;
4602 reschedule:
4603         if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
4604                 mod_timer(&adapter->sfp_timer,
4605                           round_jiffies(jiffies + (2 * HZ)));
4606 }
4607
4608 /**
4609  * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4610  * @adapter: board private structure to initialize
4611  *
4612  * ixgbe_sw_init initializes the Adapter private data structure.
4613  * Fields are initialized based on PCI device information and
4614  * OS network device settings (MTU size).
4615  **/
4616 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
4617 {
4618         struct ixgbe_hw *hw = &adapter->hw;
4619         struct pci_dev *pdev = adapter->pdev;
4620         struct net_device *dev = adapter->netdev;
4621         unsigned int rss;
4622 #ifdef CONFIG_IXGBE_DCB
4623         int j;
4624         struct tc_configuration *tc;
4625 #endif
4626
4627         /* PCI config space info */
4628
4629         hw->vendor_id = pdev->vendor;
4630         hw->device_id = pdev->device;
4631         hw->revision_id = pdev->revision;
4632         hw->subsystem_vendor_id = pdev->subsystem_vendor;
4633         hw->subsystem_device_id = pdev->subsystem_device;
4634
4635         /* Set capability flags */
4636         rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
4637         adapter->ring_feature[RING_F_RSS].indices = rss;
4638         adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
4639         adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
4640         if (hw->mac.type == ixgbe_mac_82598EB) {
4641                 if (hw->device_id == IXGBE_DEV_ID_82598AT)
4642                         adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
4643                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
4644         } else if (hw->mac.type == ixgbe_mac_82599EB) {
4645                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
4646                 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
4647                 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
4648                 if (dev->features & NETIF_F_NTUPLE) {
4649                         /* Flow Director perfect filter enabled */
4650                         adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4651                         adapter->atr_sample_rate = 0;
4652                         spin_lock_init(&adapter->fdir_perfect_lock);
4653                 } else {
4654                         /* Flow Director hash filters enabled */
4655                         adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
4656                         adapter->atr_sample_rate = 20;
4657                 }
4658                 adapter->ring_feature[RING_F_FDIR].indices =
4659                                                          IXGBE_MAX_FDIR_INDICES;
4660                 adapter->fdir_pballoc = 0;
4661 #ifdef IXGBE_FCOE
4662                 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
4663                 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
4664                 adapter->ring_feature[RING_F_FCOE].indices = 0;
4665 #ifdef CONFIG_IXGBE_DCB
4666                 /* Default traffic class to use for FCoE */
4667                 adapter->fcoe.tc = IXGBE_FCOE_DEFTC;
4668 #endif
4669 #endif /* IXGBE_FCOE */
4670         }
4671
4672 #ifdef CONFIG_IXGBE_DCB
4673         /* Configure DCB traffic classes */
4674         for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
4675                 tc = &adapter->dcb_cfg.tc_config[j];
4676                 tc->path[DCB_TX_CONFIG].bwg_id = 0;
4677                 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
4678                 tc->path[DCB_RX_CONFIG].bwg_id = 0;
4679                 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
4680                 tc->dcb_pfc = pfc_disabled;
4681         }
4682         adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
4683         adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
4684         adapter->dcb_cfg.rx_pba_cfg = pba_equal;
4685         adapter->dcb_cfg.pfc_mode_enable = false;
4686         adapter->dcb_cfg.round_robin_enable = false;
4687         adapter->dcb_set_bitmap = 0x00;
4688         ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
4689                            adapter->ring_feature[RING_F_DCB].indices);
4690
4691 #endif
4692
4693         /* default flow control settings */
4694         hw->fc.requested_mode = ixgbe_fc_full;
4695         hw->fc.current_mode = ixgbe_fc_full;    /* init for ethtool output */
4696 #ifdef CONFIG_DCB
4697         adapter->last_lfc_mode = hw->fc.current_mode;
4698 #endif
4699         hw->fc.high_water = IXGBE_DEFAULT_FCRTH;
4700         hw->fc.low_water = IXGBE_DEFAULT_FCRTL;
4701         hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
4702         hw->fc.send_xon = true;
4703         hw->fc.disable_fc_autoneg = false;
4704
4705         /* enable itr by default in dynamic mode */
4706         adapter->rx_itr_setting = 1;
4707         adapter->rx_eitr_param = 20000;
4708         adapter->tx_itr_setting = 1;
4709         adapter->tx_eitr_param = 10000;
4710
4711         /* set defaults for eitr in MegaBytes */
4712         adapter->eitr_low = 10;
4713         adapter->eitr_high = 20;
4714
4715         /* set default ring sizes */
4716         adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
4717         adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
4718
4719         /* initialize eeprom parameters */
4720         if (ixgbe_init_eeprom_params_generic(hw)) {
4721                 dev_err(&pdev->dev, "EEPROM initialization failed\n");
4722                 return -EIO;
4723         }
4724
4725         /* enable rx csum by default */
4726         adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
4727
4728         /* get assigned NUMA node */
4729         adapter->node = dev_to_node(&pdev->dev);
4730
4731         set_bit(__IXGBE_DOWN, &adapter->state);
4732
4733         return 0;
4734 }
4735
4736 /**
4737  * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
4738  * @adapter: board private structure
4739  * @tx_ring:    tx descriptor ring (for a specific queue) to setup
4740  *
4741  * Return 0 on success, negative on failure
4742  **/
4743 int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
4744                              struct ixgbe_ring *tx_ring)
4745 {
4746         struct pci_dev *pdev = adapter->pdev;
4747         int size;
4748
4749         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4750         tx_ring->tx_buffer_info = vmalloc_node(size, tx_ring->numa_node);
4751         if (!tx_ring->tx_buffer_info)
4752                 tx_ring->tx_buffer_info = vmalloc(size);
4753         if (!tx_ring->tx_buffer_info)
4754                 goto err;
4755         memset(tx_ring->tx_buffer_info, 0, size);
4756
4757         /* round up to nearest 4K */
4758         tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
4759         tx_ring->size = ALIGN(tx_ring->size, 4096);
4760
4761         tx_ring->desc = dma_alloc_coherent(&pdev->dev, tx_ring->size,
4762                                            &tx_ring->dma, GFP_KERNEL);
4763         if (!tx_ring->desc)
4764                 goto err;
4765
4766         tx_ring->next_to_use = 0;
4767         tx_ring->next_to_clean = 0;
4768         tx_ring->work_limit = tx_ring->count;
4769         return 0;
4770
4771 err:
4772         vfree(tx_ring->tx_buffer_info);
4773         tx_ring->tx_buffer_info = NULL;
4774         DPRINTK(PROBE, ERR, "Unable to allocate memory for the transmit "
4775                             "descriptor ring\n");
4776         return -ENOMEM;
4777 }
4778
4779 /**
4780  * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
4781  * @adapter: board private structure
4782  *
4783  * If this function returns with an error, then it's possible one or
4784  * more of the rings is populated (while the rest are not).  It is the
4785  * callers duty to clean those orphaned rings.
4786  *
4787  * Return 0 on success, negative on failure
4788  **/
4789 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
4790 {
4791         int i, err = 0;
4792
4793         for (i = 0; i < adapter->num_tx_queues; i++) {
4794                 err = ixgbe_setup_tx_resources(adapter, adapter->tx_ring[i]);
4795                 if (!err)
4796                         continue;
4797                 DPRINTK(PROBE, ERR, "Allocation for Tx Queue %u failed\n", i);
4798                 break;
4799         }
4800
4801         return err;
4802 }
4803
4804 /**
4805  * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
4806  * @adapter: board private structure
4807  * @rx_ring:    rx descriptor ring (for a specific queue) to setup
4808  *
4809  * Returns 0 on success, negative on failure
4810  **/
4811 int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
4812                              struct ixgbe_ring *rx_ring)
4813 {
4814         struct pci_dev *pdev = adapter->pdev;
4815         int size;
4816
4817         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4818         rx_ring->rx_buffer_info = vmalloc_node(size, adapter->node);
4819         if (!rx_ring->rx_buffer_info)
4820                 rx_ring->rx_buffer_info = vmalloc(size);
4821         if (!rx_ring->rx_buffer_info) {
4822                 DPRINTK(PROBE, ERR,
4823                         "vmalloc allocation failed for the rx desc ring\n");
4824                 goto alloc_failed;
4825         }
4826         memset(rx_ring->rx_buffer_info, 0, size);
4827
4828         /* Round up to nearest 4K */
4829         rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
4830         rx_ring->size = ALIGN(rx_ring->size, 4096);
4831
4832         rx_ring->desc = dma_alloc_coherent(&pdev->dev, rx_ring->size,
4833                                            &rx_ring->dma, GFP_KERNEL);
4834
4835         if (!rx_ring->desc) {
4836                 DPRINTK(PROBE, ERR,
4837                         "Memory allocation failed for the rx desc ring\n");
4838                 vfree(rx_ring->rx_buffer_info);
4839                 goto alloc_failed;
4840         }
4841
4842         rx_ring->next_to_clean = 0;
4843         rx_ring->next_to_use = 0;
4844
4845         return 0;
4846
4847 alloc_failed:
4848         return -ENOMEM;
4849 }
4850
4851 /**
4852  * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
4853  * @adapter: board private structure
4854  *
4855  * If this function returns with an error, then it's possible one or
4856  * more of the rings is populated (while the rest are not).  It is the
4857  * callers duty to clean those orphaned rings.
4858  *
4859  * Return 0 on success, negative on failure
4860  **/
4861
4862 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
4863 {
4864         int i, err = 0;
4865
4866         for (i = 0; i < adapter->num_rx_queues; i++) {
4867                 err = ixgbe_setup_rx_resources(adapter, adapter->rx_ring[i]);
4868                 if (!err)
4869                         continue;
4870                 DPRINTK(PROBE, ERR, "Allocation for Rx Queue %u failed\n", i);
4871                 break;
4872         }
4873
4874         return err;
4875 }
4876
4877 /**
4878  * ixgbe_free_tx_resources - Free Tx Resources per Queue
4879  * @adapter: board private structure
4880  * @tx_ring: Tx descriptor ring for a specific queue
4881  *
4882  * Free all transmit software resources
4883  **/
4884 void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter,
4885                              struct ixgbe_ring *tx_ring)
4886 {
4887         struct pci_dev *pdev = adapter->pdev;
4888
4889         ixgbe_clean_tx_ring(adapter, tx_ring);
4890
4891         vfree(tx_ring->tx_buffer_info);
4892         tx_ring->tx_buffer_info = NULL;
4893
4894         dma_free_coherent(&pdev->dev, tx_ring->size, tx_ring->desc,
4895                           tx_ring->dma);
4896
4897         tx_ring->desc = NULL;
4898 }
4899
4900 /**
4901  * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
4902  * @adapter: board private structure
4903  *
4904  * Free all transmit software resources
4905  **/
4906 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
4907 {
4908         int i;
4909
4910         for (i = 0; i < adapter->num_tx_queues; i++)
4911                 if (adapter->tx_ring[i]->desc)
4912                         ixgbe_free_tx_resources(adapter, adapter->tx_ring[i]);
4913 }
4914
4915 /**
4916  * ixgbe_free_rx_resources - Free Rx Resources
4917  * @adapter: board private structure
4918  * @rx_ring: ring to clean the resources from
4919  *
4920  * Free all receive software resources
4921  **/
4922 void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
4923                              struct ixgbe_ring *rx_ring)
4924 {
4925         struct pci_dev *pdev = adapter->pdev;
4926
4927         ixgbe_clean_rx_ring(adapter, rx_ring);
4928
4929         vfree(rx_ring->rx_buffer_info);
4930         rx_ring->rx_buffer_info = NULL;
4931
4932         dma_free_coherent(&pdev->dev, rx_ring->size, rx_ring->desc,
4933                           rx_ring->dma);
4934
4935         rx_ring->desc = NULL;
4936 }
4937
4938 /**
4939  * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
4940  * @adapter: board private structure
4941  *
4942  * Free all receive software resources
4943  **/
4944 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
4945 {
4946         int i;
4947
4948         for (i = 0; i < adapter->num_rx_queues; i++)
4949                 if (adapter->rx_ring[i]->desc)
4950                         ixgbe_free_rx_resources(adapter, adapter->rx_ring[i]);
4951 }
4952
4953 /**
4954  * ixgbe_change_mtu - Change the Maximum Transfer Unit
4955  * @netdev: network interface device structure
4956  * @new_mtu: new value for maximum frame size
4957  *
4958  * Returns 0 on success, negative on failure
4959  **/
4960 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
4961 {
4962         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4963         int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
4964
4965         /* MTU < 68 is an error and causes problems on some kernels */
4966         if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
4967                 return -EINVAL;
4968
4969         DPRINTK(PROBE, INFO, "changing MTU from %d to %d\n",
4970                 netdev->mtu, new_mtu);
4971         /* must set new MTU before calling down or up */
4972         netdev->mtu = new_mtu;
4973
4974         if (netif_running(netdev))
4975                 ixgbe_reinit_locked(adapter);
4976
4977         return 0;
4978 }
4979
4980 /**
4981  * ixgbe_open - Called when a network interface is made active
4982  * @netdev: network interface device structure
4983  *
4984  * Returns 0 on success, negative value on failure
4985  *
4986  * The open entry point is called when a network interface is made
4987  * active by the system (IFF_UP).  At this point all resources needed
4988  * for transmit and receive operations are allocated, the interrupt
4989  * handler is registered with the OS, the watchdog timer is started,
4990  * and the stack is notified that the interface is ready.
4991  **/
4992 static int ixgbe_open(struct net_device *netdev)
4993 {
4994         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4995         int err;
4996
4997         /* disallow open during test */
4998         if (test_bit(__IXGBE_TESTING, &adapter->state))
4999                 return -EBUSY;
5000
5001         netif_carrier_off(netdev);
5002
5003         /* allocate transmit descriptors */
5004         err = ixgbe_setup_all_tx_resources(adapter);
5005         if (err)
5006                 goto err_setup_tx;
5007
5008         /* allocate receive descriptors */
5009         err = ixgbe_setup_all_rx_resources(adapter);
5010         if (err)
5011                 goto err_setup_rx;
5012
5013         ixgbe_configure(adapter);
5014
5015         err = ixgbe_request_irq(adapter);
5016         if (err)
5017                 goto err_req_irq;
5018
5019         err = ixgbe_up_complete(adapter);
5020         if (err)
5021                 goto err_up;
5022
5023         netif_tx_start_all_queues(netdev);
5024
5025         return 0;
5026
5027 err_up:
5028         ixgbe_release_hw_control(adapter);
5029         ixgbe_free_irq(adapter);
5030 err_req_irq:
5031 err_setup_rx:
5032         ixgbe_free_all_rx_resources(adapter);
5033 err_setup_tx:
5034         ixgbe_free_all_tx_resources(adapter);
5035         ixgbe_reset(adapter);
5036
5037         return err;
5038 }
5039
5040 /**
5041  * ixgbe_close - Disables a network interface
5042  * @netdev: network interface device structure
5043  *
5044  * Returns 0, this is not allowed to fail
5045  *
5046  * The close entry point is called when an interface is de-activated
5047  * by the OS.  The hardware is still under the drivers control, but
5048  * needs to be disabled.  A global MAC reset is issued to stop the
5049  * hardware, and all transmit and receive resources are freed.
5050  **/
5051 static int ixgbe_close(struct net_device *netdev)
5052 {
5053         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5054
5055         ixgbe_down(adapter);
5056         ixgbe_free_irq(adapter);
5057
5058         ixgbe_free_all_tx_resources(adapter);
5059         ixgbe_free_all_rx_resources(adapter);
5060
5061         ixgbe_release_hw_control(adapter);
5062
5063         return 0;
5064 }
5065
5066 #ifdef CONFIG_PM
5067 static int ixgbe_resume(struct pci_dev *pdev)
5068 {
5069         struct net_device *netdev = pci_get_drvdata(pdev);
5070         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5071         u32 err;
5072
5073         pci_set_power_state(pdev, PCI_D0);
5074         pci_restore_state(pdev);
5075         /*
5076          * pci_restore_state clears dev->state_saved so call
5077          * pci_save_state to restore it.
5078          */
5079         pci_save_state(pdev);
5080
5081         err = pci_enable_device_mem(pdev);
5082         if (err) {
5083                 printk(KERN_ERR "ixgbe: Cannot enable PCI device from "
5084                                 "suspend\n");
5085                 return err;
5086         }
5087         pci_set_master(pdev);
5088
5089         pci_wake_from_d3(pdev, false);
5090
5091         err = ixgbe_init_interrupt_scheme(adapter);
5092         if (err) {
5093                 printk(KERN_ERR "ixgbe: Cannot initialize interrupts for "
5094                                 "device\n");
5095                 return err;
5096         }
5097
5098         ixgbe_reset(adapter);
5099
5100         IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5101
5102         if (netif_running(netdev)) {
5103                 err = ixgbe_open(adapter->netdev);
5104                 if (err)
5105                         return err;
5106         }
5107
5108         netif_device_attach(netdev);
5109
5110         return 0;
5111 }
5112 #endif /* CONFIG_PM */
5113
5114 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
5115 {
5116         struct net_device *netdev = pci_get_drvdata(pdev);
5117         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5118         struct ixgbe_hw *hw = &adapter->hw;
5119         u32 ctrl, fctrl;
5120         u32 wufc = adapter->wol;
5121 #ifdef CONFIG_PM
5122         int retval = 0;
5123 #endif
5124
5125         netif_device_detach(netdev);
5126
5127         if (netif_running(netdev)) {
5128                 ixgbe_down(adapter);
5129                 ixgbe_free_irq(adapter);
5130                 ixgbe_free_all_tx_resources(adapter);
5131                 ixgbe_free_all_rx_resources(adapter);
5132         }
5133         ixgbe_clear_interrupt_scheme(adapter);
5134
5135 #ifdef CONFIG_PM
5136         retval = pci_save_state(pdev);
5137         if (retval)
5138                 return retval;
5139
5140 #endif
5141         if (wufc) {
5142                 ixgbe_set_rx_mode(netdev);
5143
5144                 /* turn on all-multi mode if wake on multicast is enabled */
5145                 if (wufc & IXGBE_WUFC_MC) {
5146                         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5147                         fctrl |= IXGBE_FCTRL_MPE;
5148                         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5149                 }
5150
5151                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5152                 ctrl |= IXGBE_CTRL_GIO_DIS;
5153                 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5154
5155                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5156         } else {
5157                 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5158                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5159         }
5160
5161         if (wufc && hw->mac.type == ixgbe_mac_82599EB)
5162                 pci_wake_from_d3(pdev, true);
5163         else
5164                 pci_wake_from_d3(pdev, false);
5165
5166         *enable_wake = !!wufc;
5167
5168         ixgbe_release_hw_control(adapter);
5169
5170         pci_disable_device(pdev);
5171
5172         return 0;
5173 }
5174
5175 #ifdef CONFIG_PM
5176 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5177 {
5178         int retval;
5179         bool wake;
5180
5181         retval = __ixgbe_shutdown(pdev, &wake);
5182         if (retval)
5183                 return retval;
5184
5185         if (wake) {
5186                 pci_prepare_to_sleep(pdev);
5187         } else {
5188                 pci_wake_from_d3(pdev, false);
5189                 pci_set_power_state(pdev, PCI_D3hot);
5190         }
5191
5192         return 0;
5193 }
5194 #endif /* CONFIG_PM */
5195
5196 static void ixgbe_shutdown(struct pci_dev *pdev)
5197 {
5198         bool wake;
5199
5200         __ixgbe_shutdown(pdev, &wake);
5201
5202         if (system_state == SYSTEM_POWER_OFF) {
5203                 pci_wake_from_d3(pdev, wake);
5204                 pci_set_power_state(pdev, PCI_D3hot);
5205         }
5206 }
5207
5208 /**
5209  * ixgbe_update_stats - Update the board statistics counters.
5210  * @adapter: board private structure
5211  **/
5212 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5213 {
5214         struct net_device *netdev = adapter->netdev;
5215         struct ixgbe_hw *hw = &adapter->hw;
5216         u64 total_mpc = 0;
5217         u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5218         u64 non_eop_descs = 0, restart_queue = 0;
5219
5220         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
5221                 u64 rsc_count = 0;
5222                 u64 rsc_flush = 0;
5223                 for (i = 0; i < 16; i++)
5224                         adapter->hw_rx_no_dma_resources +=
5225                                              IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
5226                 for (i = 0; i < adapter->num_rx_queues; i++) {
5227                         rsc_count += adapter->rx_ring[i]->rsc_count;
5228                         rsc_flush += adapter->rx_ring[i]->rsc_flush;
5229                 }
5230                 adapter->rsc_total_count = rsc_count;
5231                 adapter->rsc_total_flush = rsc_flush;
5232         }
5233
5234         /* gather some stats to the adapter struct that are per queue */
5235         for (i = 0; i < adapter->num_tx_queues; i++)
5236                 restart_queue += adapter->tx_ring[i]->restart_queue;
5237         adapter->restart_queue = restart_queue;
5238
5239         for (i = 0; i < adapter->num_rx_queues; i++)
5240                 non_eop_descs += adapter->rx_ring[i]->non_eop_descs;
5241         adapter->non_eop_descs = non_eop_descs;
5242
5243         adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
5244         for (i = 0; i < 8; i++) {
5245                 /* for packet buffers not used, the register should read 0 */
5246                 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5247                 missed_rx += mpc;
5248                 adapter->stats.mpc[i] += mpc;
5249                 total_mpc += adapter->stats.mpc[i];
5250                 if (hw->mac.type == ixgbe_mac_82598EB)
5251                         adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5252                 adapter->stats.qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5253                 adapter->stats.qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5254                 adapter->stats.qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5255                 adapter->stats.qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
5256                 if (hw->mac.type == ixgbe_mac_82599EB) {
5257                         adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
5258                                                             IXGBE_PXONRXCNT(i));
5259                         adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
5260                                                            IXGBE_PXOFFRXCNT(i));
5261                         adapter->stats.qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
5262                 } else {
5263                         adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
5264                                                               IXGBE_PXONRXC(i));
5265                         adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
5266                                                              IXGBE_PXOFFRXC(i));
5267                 }
5268                 adapter->stats.pxontxc[i] += IXGBE_READ_REG(hw,
5269                                                             IXGBE_PXONTXC(i));
5270                 adapter->stats.pxofftxc[i] += IXGBE_READ_REG(hw,
5271                                                              IXGBE_PXOFFTXC(i));
5272         }
5273         adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
5274         /* work around hardware counting issue */
5275         adapter->stats.gprc -= missed_rx;
5276
5277         /* 82598 hardware only has a 32 bit counter in the high register */
5278         if (hw->mac.type == ixgbe_mac_82599EB) {
5279                 u64 tmp;
5280                 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
5281                 tmp = IXGBE_READ_REG(hw, IXGBE_GORCH) & 0xF; /* 4 high bits of GORC */
5282                 adapter->stats.gorc += (tmp << 32);
5283                 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
5284                 tmp = IXGBE_READ_REG(hw, IXGBE_GOTCH) & 0xF; /* 4 high bits of GOTC */
5285                 adapter->stats.gotc += (tmp << 32);
5286                 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORL);
5287                 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
5288                 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
5289                 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
5290                 adapter->stats.fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5291                 adapter->stats.fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
5292 #ifdef IXGBE_FCOE
5293                 adapter->stats.fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5294                 adapter->stats.fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5295                 adapter->stats.fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5296                 adapter->stats.fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5297                 adapter->stats.fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5298                 adapter->stats.fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
5299 #endif /* IXGBE_FCOE */
5300         } else {
5301                 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
5302                 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
5303                 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5304                 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5305                 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5306         }
5307         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
5308         adapter->stats.bprc += bprc;
5309         adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
5310         if (hw->mac.type == ixgbe_mac_82598EB)
5311                 adapter->stats.mprc -= bprc;
5312         adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5313         adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5314         adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5315         adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5316         adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5317         adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5318         adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5319         adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
5320         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
5321         adapter->stats.lxontxc += lxon;
5322         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
5323         adapter->stats.lxofftxc += lxoff;
5324         adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5325         adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5326         adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
5327         /*
5328          * 82598 errata - tx of flow control packets is included in tx counters
5329          */
5330         xon_off_tot = lxon + lxoff;
5331         adapter->stats.gptc -= xon_off_tot;
5332         adapter->stats.mptc -= xon_off_tot;
5333         adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5334         adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5335         adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5336         adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5337         adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5338         adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5339         adapter->stats.ptc64 -= xon_off_tot;
5340         adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5341         adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5342         adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5343         adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5344         adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5345         adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
5346
5347         /* Fill out the OS statistics structure */
5348         netdev->stats.multicast = adapter->stats.mprc;
5349
5350         /* Rx Errors */
5351         netdev->stats.rx_errors = adapter->stats.crcerrs +
5352                                        adapter->stats.rlec;
5353         netdev->stats.rx_dropped = 0;
5354         netdev->stats.rx_length_errors = adapter->stats.rlec;
5355         netdev->stats.rx_crc_errors = adapter->stats.crcerrs;
5356         netdev->stats.rx_missed_errors = total_mpc;
5357 }
5358
5359 /**
5360  * ixgbe_watchdog - Timer Call-back
5361  * @data: pointer to adapter cast into an unsigned long
5362  **/
5363 static void ixgbe_watchdog(unsigned long data)
5364 {
5365         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
5366         struct ixgbe_hw *hw = &adapter->hw;
5367         u64 eics = 0;
5368         int i;
5369
5370         /*
5371          *  Do the watchdog outside of interrupt context due to the lovely
5372          * delays that some of the newer hardware requires
5373          */
5374
5375         if (test_bit(__IXGBE_DOWN, &adapter->state))
5376                 goto watchdog_short_circuit;
5377
5378         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5379                 /*
5380                  * for legacy and MSI interrupts don't set any bits
5381                  * that are enabled for EIAM, because this operation
5382                  * would set *both* EIMS and EICS for any bit in EIAM
5383                  */
5384                 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5385                         (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
5386                 goto watchdog_reschedule;
5387         }
5388
5389         /* get one bit for every active tx/rx interrupt vector */
5390         for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
5391                 struct ixgbe_q_vector *qv = adapter->q_vector[i];
5392                 if (qv->rxr_count || qv->txr_count)
5393                         eics |= ((u64)1 << i);
5394         }
5395
5396         /* Cause software interrupt to ensure rx rings are cleaned */
5397         ixgbe_irq_rearm_queues(adapter, eics);
5398
5399 watchdog_reschedule:
5400         /* Reset the timer */
5401         mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ));
5402
5403 watchdog_short_circuit:
5404         schedule_work(&adapter->watchdog_task);
5405 }
5406
5407 /**
5408  * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
5409  * @work: pointer to work_struct containing our data
5410  **/
5411 static void ixgbe_multispeed_fiber_task(struct work_struct *work)
5412 {
5413         struct ixgbe_adapter *adapter = container_of(work,
5414                                                      struct ixgbe_adapter,
5415                                                      multispeed_fiber_task);
5416         struct ixgbe_hw *hw = &adapter->hw;
5417         u32 autoneg;
5418         bool negotiation;
5419
5420         adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
5421         autoneg = hw->phy.autoneg_advertised;
5422         if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
5423                 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
5424         hw->mac.autotry_restart = false;
5425         if (hw->mac.ops.setup_link)
5426                 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
5427         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5428         adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
5429 }
5430
5431 /**
5432  * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
5433  * @work: pointer to work_struct containing our data
5434  **/
5435 static void ixgbe_sfp_config_module_task(struct work_struct *work)
5436 {
5437         struct ixgbe_adapter *adapter = container_of(work,
5438                                                      struct ixgbe_adapter,
5439                                                      sfp_config_module_task);
5440         struct ixgbe_hw *hw = &adapter->hw;
5441         u32 err;
5442
5443         adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
5444
5445         /* Time for electrical oscillations to settle down */
5446         msleep(100);
5447         err = hw->phy.ops.identify_sfp(hw);
5448
5449         if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
5450                 dev_err(&adapter->pdev->dev, "failed to initialize because "
5451                         "an unsupported SFP+ module type was detected.\n"
5452                         "Reload the driver after installing a supported "
5453                         "module.\n");
5454                 unregister_netdev(adapter->netdev);
5455                 return;
5456         }
5457         hw->mac.ops.setup_sfp(hw);
5458
5459         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
5460                 /* This will also work for DA Twinax connections */
5461                 schedule_work(&adapter->multispeed_fiber_task);
5462         adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
5463 }
5464
5465 /**
5466  * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table
5467  * @work: pointer to work_struct containing our data
5468  **/
5469 static void ixgbe_fdir_reinit_task(struct work_struct *work)
5470 {
5471         struct ixgbe_adapter *adapter = container_of(work,
5472                                                      struct ixgbe_adapter,
5473                                                      fdir_reinit_task);
5474         struct ixgbe_hw *hw = &adapter->hw;
5475         int i;
5476
5477         if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5478                 for (i = 0; i < adapter->num_tx_queues; i++)
5479                         set_bit(__IXGBE_FDIR_INIT_DONE,
5480                                 &(adapter->tx_ring[i]->reinit_state));
5481         } else {
5482                 DPRINTK(PROBE, ERR, "failed to finish FDIR re-initialization, "
5483                         "ignored adding FDIR ATR filters\n");
5484         }
5485         /* Done FDIR Re-initialization, enable transmits */
5486         netif_tx_start_all_queues(adapter->netdev);
5487 }
5488
5489 static DEFINE_MUTEX(ixgbe_watchdog_lock);
5490
5491 /**
5492  * ixgbe_watchdog_task - worker thread to bring link up
5493  * @work: pointer to work_struct containing our data
5494  **/
5495 static void ixgbe_watchdog_task(struct work_struct *work)
5496 {
5497         struct ixgbe_adapter *adapter = container_of(work,
5498                                                      struct ixgbe_adapter,
5499                                                      watchdog_task);
5500         struct net_device *netdev = adapter->netdev;
5501         struct ixgbe_hw *hw = &adapter->hw;
5502         u32 link_speed;
5503         bool link_up;
5504         int i;
5505         struct ixgbe_ring *tx_ring;
5506         int some_tx_pending = 0;
5507
5508         mutex_lock(&ixgbe_watchdog_lock);
5509
5510         link_up = adapter->link_up;
5511         link_speed = adapter->link_speed;
5512
5513         if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
5514                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
5515                 if (link_up) {
5516 #ifdef CONFIG_DCB
5517                         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5518                                 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
5519                                         hw->mac.ops.fc_enable(hw, i);
5520                         } else {
5521                                 hw->mac.ops.fc_enable(hw, 0);
5522                         }
5523 #else
5524                         hw->mac.ops.fc_enable(hw, 0);
5525 #endif
5526                 }
5527
5528                 if (link_up ||
5529                     time_after(jiffies, (adapter->link_check_timeout +
5530                                          IXGBE_TRY_LINK_TIMEOUT))) {
5531                         adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5532                         IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
5533                 }
5534                 adapter->link_up = link_up;
5535                 adapter->link_speed = link_speed;
5536         }
5537
5538         if (link_up) {
5539                 if (!netif_carrier_ok(netdev)) {
5540                         bool flow_rx, flow_tx;
5541
5542                         if (hw->mac.type == ixgbe_mac_82599EB) {
5543                                 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5544                                 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
5545                                 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5546                                 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
5547                         } else {
5548                                 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5549                                 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
5550                                 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5551                                 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
5552                         }
5553
5554                         printk(KERN_INFO "ixgbe: %s NIC Link is Up %s, "
5555                                "Flow Control: %s\n",
5556                                netdev->name,
5557                                (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
5558                                 "10 Gbps" :
5559                                 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5560                                  "1 Gbps" : "unknown speed")),
5561                                ((flow_rx && flow_tx) ? "RX/TX" :
5562                                 (flow_rx ? "RX" :
5563                                 (flow_tx ? "TX" : "None"))));
5564
5565                         netif_carrier_on(netdev);
5566                 } else {
5567                         /* Force detection of hung controller */
5568                         adapter->detect_tx_hung = true;
5569                 }
5570         } else {
5571                 adapter->link_up = false;
5572                 adapter->link_speed = 0;
5573                 if (netif_carrier_ok(netdev)) {
5574                         printk(KERN_INFO "ixgbe: %s NIC Link is Down\n",
5575                                netdev->name);
5576                         netif_carrier_off(netdev);
5577                 }
5578         }
5579
5580         if (!netif_carrier_ok(netdev)) {
5581                 for (i = 0; i < adapter->num_tx_queues; i++) {
5582                         tx_ring = adapter->tx_ring[i];
5583                         if (tx_ring->next_to_use != tx_ring->next_to_clean) {
5584                                 some_tx_pending = 1;
5585                                 break;
5586                         }
5587                 }
5588
5589                 if (some_tx_pending) {
5590                         /* We've lost link, so the controller stops DMA,
5591                          * but we've got queued Tx work that's never going
5592                          * to get done, so reset controller to flush Tx.
5593                          * (Do the reset outside of interrupt context).
5594                          */
5595                          schedule_work(&adapter->reset_task);
5596                 }
5597         }
5598
5599         ixgbe_update_stats(adapter);
5600         mutex_unlock(&ixgbe_watchdog_lock);
5601 }
5602
5603 static int ixgbe_tso(struct ixgbe_adapter *adapter,
5604                      struct ixgbe_ring *tx_ring, struct sk_buff *skb,
5605                      u32 tx_flags, u8 *hdr_len)
5606 {
5607         struct ixgbe_adv_tx_context_desc *context_desc;
5608         unsigned int i;
5609         int err;
5610         struct ixgbe_tx_buffer *tx_buffer_info;
5611         u32 vlan_macip_lens = 0, type_tucmd_mlhl;
5612         u32 mss_l4len_idx, l4len;
5613
5614         if (skb_is_gso(skb)) {
5615                 if (skb_header_cloned(skb)) {
5616                         err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
5617                         if (err)
5618                                 return err;
5619                 }
5620                 l4len = tcp_hdrlen(skb);
5621                 *hdr_len += l4len;
5622
5623                 if (skb->protocol == htons(ETH_P_IP)) {
5624                         struct iphdr *iph = ip_hdr(skb);
5625                         iph->tot_len = 0;
5626                         iph->check = 0;
5627                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5628                                                                  iph->daddr, 0,
5629                                                                  IPPROTO_TCP,
5630                                                                  0);
5631                 } else if (skb_is_gso_v6(skb)) {
5632                         ipv6_hdr(skb)->payload_len = 0;
5633                         tcp_hdr(skb)->check =
5634                             ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
5635                                              &ipv6_hdr(skb)->daddr,
5636                                              0, IPPROTO_TCP, 0);
5637                 }
5638
5639                 i = tx_ring->next_to_use;
5640
5641                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5642                 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
5643
5644                 /* VLAN MACLEN IPLEN */
5645                 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5646                         vlan_macip_lens |=
5647                             (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
5648                 vlan_macip_lens |= ((skb_network_offset(skb)) <<
5649                                     IXGBE_ADVTXD_MACLEN_SHIFT);
5650                 *hdr_len += skb_network_offset(skb);
5651                 vlan_macip_lens |=
5652                     (skb_transport_header(skb) - skb_network_header(skb));
5653                 *hdr_len +=
5654                     (skb_transport_header(skb) - skb_network_header(skb));
5655                 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
5656                 context_desc->seqnum_seed = 0;
5657
5658                 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
5659                 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
5660                                    IXGBE_ADVTXD_DTYP_CTXT);
5661
5662                 if (skb->protocol == htons(ETH_P_IP))
5663                         type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
5664                 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
5665                 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
5666
5667                 /* MSS L4LEN IDX */
5668                 mss_l4len_idx =
5669                     (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
5670                 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
5671                 /* use index 1 for TSO */
5672                 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
5673                 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
5674
5675                 tx_buffer_info->time_stamp = jiffies;
5676                 tx_buffer_info->next_to_watch = i;
5677
5678                 i++;
5679                 if (i == tx_ring->count)
5680                         i = 0;
5681                 tx_ring->next_to_use = i;
5682
5683                 return true;
5684         }
5685         return false;
5686 }
5687
5688 static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
5689                           struct ixgbe_ring *tx_ring,
5690                           struct sk_buff *skb, u32 tx_flags)
5691 {
5692         struct ixgbe_adv_tx_context_desc *context_desc;
5693         unsigned int i;
5694         struct ixgbe_tx_buffer *tx_buffer_info;
5695         u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
5696
5697         if (skb->ip_summed == CHECKSUM_PARTIAL ||
5698             (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
5699                 i = tx_ring->next_to_use;
5700                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5701                 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
5702
5703                 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5704                         vlan_macip_lens |=
5705                             (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
5706                 vlan_macip_lens |= (skb_network_offset(skb) <<
5707                                     IXGBE_ADVTXD_MACLEN_SHIFT);
5708                 if (skb->ip_summed == CHECKSUM_PARTIAL)
5709                         vlan_macip_lens |= (skb_transport_header(skb) -
5710                                             skb_network_header(skb));
5711
5712                 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
5713                 context_desc->seqnum_seed = 0;
5714
5715                 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
5716                                     IXGBE_ADVTXD_DTYP_CTXT);
5717
5718                 if (skb->ip_summed == CHECKSUM_PARTIAL) {
5719                         __be16 protocol;
5720
5721                         if (skb->protocol == cpu_to_be16(ETH_P_8021Q)) {
5722                                 const struct vlan_ethhdr *vhdr =
5723                                         (const struct vlan_ethhdr *)skb->data;
5724
5725                                 protocol = vhdr->h_vlan_encapsulated_proto;
5726                         } else {
5727                                 protocol = skb->protocol;
5728                         }
5729
5730                         switch (protocol) {
5731                         case cpu_to_be16(ETH_P_IP):
5732                                 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
5733                                 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
5734                                         type_tucmd_mlhl |=
5735                                                 IXGBE_ADVTXD_TUCMD_L4T_TCP;
5736                                 else if (ip_hdr(skb)->protocol == IPPROTO_SCTP)
5737                                         type_tucmd_mlhl |=
5738                                                 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
5739                                 break;
5740                         case cpu_to_be16(ETH_P_IPV6):
5741                                 /* XXX what about other V6 headers?? */
5742                                 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
5743                                         type_tucmd_mlhl |=
5744                                                 IXGBE_ADVTXD_TUCMD_L4T_TCP;
5745                                 else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP)
5746                                         type_tucmd_mlhl |=
5747                                                 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
5748                                 break;
5749                         default:
5750                                 if (unlikely(net_ratelimit())) {
5751                                         DPRINTK(PROBE, WARNING,
5752                                          "partial checksum but proto=%x!\n",
5753                                          skb->protocol);
5754                                 }
5755                                 break;
5756                         }
5757                 }
5758
5759                 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
5760                 /* use index zero for tx checksum offload */
5761                 context_desc->mss_l4len_idx = 0;
5762
5763                 tx_buffer_info->time_stamp = jiffies;
5764                 tx_buffer_info->next_to_watch = i;
5765
5766                 i++;
5767                 if (i == tx_ring->count)
5768                         i = 0;
5769                 tx_ring->next_to_use = i;
5770
5771                 return true;
5772         }
5773
5774         return false;
5775 }
5776
5777 static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
5778                         struct ixgbe_ring *tx_ring,
5779                         struct sk_buff *skb, u32 tx_flags,
5780                         unsigned int first)
5781 {
5782         struct pci_dev *pdev = adapter->pdev;
5783         struct ixgbe_tx_buffer *tx_buffer_info;
5784         unsigned int len;
5785         unsigned int total = skb->len;
5786         unsigned int offset = 0, size, count = 0, i;
5787         unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
5788         unsigned int f;
5789
5790         i = tx_ring->next_to_use;
5791
5792         if (tx_flags & IXGBE_TX_FLAGS_FCOE)
5793                 /* excluding fcoe_crc_eof for FCoE */
5794                 total -= sizeof(struct fcoe_crc_eof);
5795
5796         len = min(skb_headlen(skb), total);
5797         while (len) {
5798                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5799                 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
5800
5801                 tx_buffer_info->length = size;
5802                 tx_buffer_info->mapped_as_page = false;
5803                 tx_buffer_info->dma = dma_map_single(&pdev->dev,
5804                                                      skb->data + offset,
5805                                                      size, DMA_TO_DEVICE);
5806                 if (dma_mapping_error(&pdev->dev, tx_buffer_info->dma))
5807                         goto dma_error;
5808                 tx_buffer_info->time_stamp = jiffies;
5809                 tx_buffer_info->next_to_watch = i;
5810
5811                 len -= size;
5812                 total -= size;
5813                 offset += size;
5814                 count++;
5815
5816                 if (len) {
5817                         i++;
5818                         if (i == tx_ring->count)
5819                                 i = 0;
5820                 }
5821         }
5822
5823         for (f = 0; f < nr_frags; f++) {
5824                 struct skb_frag_struct *frag;
5825
5826                 frag = &skb_shinfo(skb)->frags[f];
5827                 len = min((unsigned int)frag->size, total);
5828                 offset = frag->page_offset;
5829
5830                 while (len) {
5831                         i++;
5832                         if (i == tx_ring->count)
5833                                 i = 0;
5834
5835                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
5836                         size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
5837
5838                         tx_buffer_info->length = size;
5839                         tx_buffer_info->dma = dma_map_page(&adapter->pdev->dev,
5840                                                            frag->page,
5841                                                            offset, size,
5842                                                            DMA_TO_DEVICE);
5843                         tx_buffer_info->mapped_as_page = true;
5844                         if (dma_mapping_error(&pdev->dev, tx_buffer_info->dma))
5845                                 goto dma_error;
5846                         tx_buffer_info->time_stamp = jiffies;
5847                         tx_buffer_info->next_to_watch = i;
5848
5849                         len -= size;
5850                         total -= size;
5851                         offset += size;
5852                         count++;
5853                 }
5854                 if (total == 0)
5855                         break;
5856         }
5857
5858         tx_ring->tx_buffer_info[i].skb = skb;
5859         tx_ring->tx_buffer_info[first].next_to_watch = i;
5860
5861         return count;
5862
5863 dma_error:
5864         dev_err(&pdev->dev, "TX DMA map failed\n");
5865
5866         /* clear timestamp and dma mappings for failed tx_buffer_info map */
5867         tx_buffer_info->dma = 0;
5868         tx_buffer_info->time_stamp = 0;
5869         tx_buffer_info->next_to_watch = 0;
5870         if (count)
5871                 count--;
5872
5873         /* clear timestamp and dma mappings for remaining portion of packet */
5874         while (count--) {
5875                 if (i==0)
5876                         i += tx_ring->count;
5877                 i--;
5878                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5879                 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
5880         }
5881
5882         return 0;
5883 }
5884
5885 static void ixgbe_tx_queue(struct ixgbe_adapter *adapter,
5886                            struct ixgbe_ring *tx_ring,
5887                            int tx_flags, int count, u32 paylen, u8 hdr_len)
5888 {
5889         union ixgbe_adv_tx_desc *tx_desc = NULL;
5890         struct ixgbe_tx_buffer *tx_buffer_info;
5891         u32 olinfo_status = 0, cmd_type_len = 0;
5892         unsigned int i;
5893         u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
5894
5895         cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
5896
5897         cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
5898
5899         if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5900                 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
5901
5902         if (tx_flags & IXGBE_TX_FLAGS_TSO) {
5903                 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
5904
5905                 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
5906                                  IXGBE_ADVTXD_POPTS_SHIFT;
5907
5908                 /* use index 1 context for tso */
5909                 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
5910                 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
5911                         olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
5912                                          IXGBE_ADVTXD_POPTS_SHIFT;
5913
5914         } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
5915                 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
5916                                  IXGBE_ADVTXD_POPTS_SHIFT;
5917
5918         if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
5919                 olinfo_status |= IXGBE_ADVTXD_CC;
5920                 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
5921                 if (tx_flags & IXGBE_TX_FLAGS_FSO)
5922                         cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
5923         }
5924
5925         olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
5926
5927         i = tx_ring->next_to_use;
5928         while (count--) {
5929                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5930                 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
5931                 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
5932                 tx_desc->read.cmd_type_len =
5933                         cpu_to_le32(cmd_type_len | tx_buffer_info->length);
5934                 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
5935                 i++;
5936                 if (i == tx_ring->count)
5937                         i = 0;
5938         }
5939
5940         tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
5941
5942         /*
5943          * Force memory writes to complete before letting h/w
5944          * know there are new descriptors to fetch.  (Only
5945          * applicable for weak-ordered memory model archs,
5946          * such as IA-64).
5947          */
5948         wmb();
5949
5950         tx_ring->next_to_use = i;
5951         writel(i, adapter->hw.hw_addr + tx_ring->tail);
5952 }
5953
5954 static void ixgbe_atr(struct ixgbe_adapter *adapter, struct sk_buff *skb,
5955                       int queue, u32 tx_flags)
5956 {
5957         /* Right now, we support IPv4 only */
5958         struct ixgbe_atr_input atr_input;
5959         struct tcphdr *th;
5960         struct iphdr *iph = ip_hdr(skb);
5961         struct ethhdr *eth = (struct ethhdr *)skb->data;
5962         u16 vlan_id, src_port, dst_port, flex_bytes;
5963         u32 src_ipv4_addr, dst_ipv4_addr;
5964         u8 l4type = 0;
5965
5966         /* check if we're UDP or TCP */
5967         if (iph->protocol == IPPROTO_TCP) {
5968                 th = tcp_hdr(skb);
5969                 src_port = th->source;
5970                 dst_port = th->dest;
5971                 l4type |= IXGBE_ATR_L4TYPE_TCP;
5972                 /* l4type IPv4 type is 0, no need to assign */
5973         } else {
5974                 /* Unsupported L4 header, just bail here */
5975                 return;
5976         }
5977
5978         memset(&atr_input, 0, sizeof(struct ixgbe_atr_input));
5979
5980         vlan_id = (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK) >>
5981                    IXGBE_TX_FLAGS_VLAN_SHIFT;
5982         src_ipv4_addr = iph->saddr;
5983         dst_ipv4_addr = iph->daddr;
5984         flex_bytes = eth->h_proto;
5985
5986         ixgbe_atr_set_vlan_id_82599(&atr_input, vlan_id);
5987         ixgbe_atr_set_src_port_82599(&atr_input, dst_port);
5988         ixgbe_atr_set_dst_port_82599(&atr_input, src_port);
5989         ixgbe_atr_set_flex_byte_82599(&atr_input, flex_bytes);
5990         ixgbe_atr_set_l4type_82599(&atr_input, l4type);
5991         /* src and dst are inverted, think how the receiver sees them */
5992         ixgbe_atr_set_src_ipv4_82599(&atr_input, dst_ipv4_addr);
5993         ixgbe_atr_set_dst_ipv4_82599(&atr_input, src_ipv4_addr);
5994
5995         /* This assumes the Rx queue and Tx queue are bound to the same CPU */
5996         ixgbe_fdir_add_signature_filter_82599(&adapter->hw, &atr_input, queue);
5997 }
5998
5999 static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
6000                                  struct ixgbe_ring *tx_ring, int size)
6001 {
6002         netif_stop_subqueue(netdev, tx_ring->queue_index);
6003         /* Herbert's original patch had:
6004          *  smp_mb__after_netif_stop_queue();
6005          * but since that doesn't exist yet, just open code it. */
6006         smp_mb();
6007
6008         /* We need to check again in a case another CPU has just
6009          * made room available. */
6010         if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
6011                 return -EBUSY;
6012
6013         /* A reprieve! - use start_queue because it doesn't call schedule */
6014         netif_start_subqueue(netdev, tx_ring->queue_index);
6015         ++tx_ring->restart_queue;
6016         return 0;
6017 }
6018
6019 static int ixgbe_maybe_stop_tx(struct net_device *netdev,
6020                               struct ixgbe_ring *tx_ring, int size)
6021 {
6022         if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
6023                 return 0;
6024         return __ixgbe_maybe_stop_tx(netdev, tx_ring, size);
6025 }
6026
6027 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6028 {
6029         struct ixgbe_adapter *adapter = netdev_priv(dev);
6030         int txq = smp_processor_id();
6031
6032         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6033                 while (unlikely(txq >= dev->real_num_tx_queues))
6034                         txq -= dev->real_num_tx_queues;
6035                 return txq;
6036         }
6037
6038 #ifdef IXGBE_FCOE
6039         if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
6040             ((skb->protocol == htons(ETH_P_FCOE)) ||
6041              (skb->protocol == htons(ETH_P_FIP)))) {
6042                 txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
6043                 txq += adapter->ring_feature[RING_F_FCOE].mask;
6044                 return txq;
6045         }
6046 #endif
6047         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6048                 if (skb->priority == TC_PRIO_CONTROL)
6049                         txq = adapter->ring_feature[RING_F_DCB].indices-1;
6050                 else
6051                         txq = (skb->vlan_tci & IXGBE_TX_FLAGS_VLAN_PRIO_MASK)
6052                                >> 13;
6053                 return txq;
6054         }
6055
6056         return skb_tx_hash(dev, skb);
6057 }
6058
6059 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
6060                                     struct net_device *netdev)
6061 {
6062         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6063         struct ixgbe_ring *tx_ring;
6064         struct netdev_queue *txq;
6065         unsigned int first;
6066         unsigned int tx_flags = 0;
6067         u8 hdr_len = 0;
6068         int tso;
6069         int count = 0;
6070         unsigned int f;
6071
6072         if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
6073                 tx_flags |= vlan_tx_tag_get(skb);
6074                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6075                         tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
6076                         tx_flags |= ((skb->queue_mapping & 0x7) << 13);
6077                 }
6078                 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6079                 tx_flags |= IXGBE_TX_FLAGS_VLAN;
6080         } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED &&
6081                    skb->priority != TC_PRIO_CONTROL) {
6082                 tx_flags |= ((skb->queue_mapping & 0x7) << 13);
6083                 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6084                 tx_flags |= IXGBE_TX_FLAGS_VLAN;
6085         }
6086
6087         tx_ring = adapter->tx_ring[skb->queue_mapping];
6088
6089 #ifdef IXGBE_FCOE
6090         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
6091 #ifdef CONFIG_IXGBE_DCB
6092                 /* for FCoE with DCB, we force the priority to what
6093                  * was specified by the switch */
6094                 if ((skb->protocol == htons(ETH_P_FCOE)) ||
6095                     (skb->protocol == htons(ETH_P_FIP))) {
6096                         tx_flags &= ~(IXGBE_TX_FLAGS_VLAN_PRIO_MASK
6097                                       << IXGBE_TX_FLAGS_VLAN_SHIFT);
6098                         tx_flags |= ((adapter->fcoe.up << 13)
6099                                      << IXGBE_TX_FLAGS_VLAN_SHIFT);
6100                 }
6101 #endif
6102                 /* flag for FCoE offloads */
6103                 if (skb->protocol == htons(ETH_P_FCOE))
6104                         tx_flags |= IXGBE_TX_FLAGS_FCOE;
6105         }
6106 #endif
6107
6108         /* four things can cause us to need a context descriptor */
6109         if (skb_is_gso(skb) ||
6110             (skb->ip_summed == CHECKSUM_PARTIAL) ||
6111             (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
6112             (tx_flags & IXGBE_TX_FLAGS_FCOE))
6113                 count++;
6114
6115         count += TXD_USE_COUNT(skb_headlen(skb));
6116         for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6117                 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6118
6119         if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) {
6120                 adapter->tx_busy++;
6121                 return NETDEV_TX_BUSY;
6122         }
6123
6124         first = tx_ring->next_to_use;
6125         if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6126 #ifdef IXGBE_FCOE
6127                 /* setup tx offload for FCoE */
6128                 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
6129                 if (tso < 0) {
6130                         dev_kfree_skb_any(skb);
6131                         return NETDEV_TX_OK;
6132                 }
6133                 if (tso)
6134                         tx_flags |= IXGBE_TX_FLAGS_FSO;
6135 #endif /* IXGBE_FCOE */
6136         } else {
6137                 if (skb->protocol == htons(ETH_P_IP))
6138                         tx_flags |= IXGBE_TX_FLAGS_IPV4;
6139                 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len);
6140                 if (tso < 0) {
6141                         dev_kfree_skb_any(skb);
6142                         return NETDEV_TX_OK;
6143                 }
6144
6145                 if (tso)
6146                         tx_flags |= IXGBE_TX_FLAGS_TSO;
6147                 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) &&
6148                          (skb->ip_summed == CHECKSUM_PARTIAL))
6149                         tx_flags |= IXGBE_TX_FLAGS_CSUM;
6150         }
6151
6152         count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first);
6153         if (count) {
6154                 /* add the ATR filter if ATR is on */
6155                 if (tx_ring->atr_sample_rate) {
6156                         ++tx_ring->atr_count;
6157                         if ((tx_ring->atr_count >= tx_ring->atr_sample_rate) &&
6158                              test_bit(__IXGBE_FDIR_INIT_DONE,
6159                                       &tx_ring->reinit_state)) {
6160                                 ixgbe_atr(adapter, skb, tx_ring->queue_index,
6161                                           tx_flags);
6162                                 tx_ring->atr_count = 0;
6163                         }
6164                 }
6165                 txq = netdev_get_tx_queue(netdev, tx_ring->queue_index);
6166                 txq->tx_bytes += skb->len;
6167                 txq->tx_packets++;
6168                 ixgbe_tx_queue(adapter, tx_ring, tx_flags, count, skb->len,
6169                                hdr_len);
6170                 ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
6171
6172         } else {
6173                 dev_kfree_skb_any(skb);
6174                 tx_ring->tx_buffer_info[first].time_stamp = 0;
6175                 tx_ring->next_to_use = first;
6176         }
6177
6178         return NETDEV_TX_OK;
6179 }
6180
6181 /**
6182  * ixgbe_set_mac - Change the Ethernet Address of the NIC
6183  * @netdev: network interface device structure
6184  * @p: pointer to an address structure
6185  *
6186  * Returns 0 on success, negative on failure
6187  **/
6188 static int ixgbe_set_mac(struct net_device *netdev, void *p)
6189 {
6190         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6191         struct ixgbe_hw *hw = &adapter->hw;
6192         struct sockaddr *addr = p;
6193
6194         if (!is_valid_ether_addr(addr->sa_data))
6195                 return -EADDRNOTAVAIL;
6196
6197         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
6198         memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
6199
6200         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
6201                             IXGBE_RAH_AV);
6202
6203         return 0;
6204 }
6205
6206 static int
6207 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6208 {
6209         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6210         struct ixgbe_hw *hw = &adapter->hw;
6211         u16 value;
6212         int rc;
6213
6214         if (prtad != hw->phy.mdio.prtad)
6215                 return -EINVAL;
6216         rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6217         if (!rc)
6218                 rc = value;
6219         return rc;
6220 }
6221
6222 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6223                             u16 addr, u16 value)
6224 {
6225         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6226         struct ixgbe_hw *hw = &adapter->hw;
6227
6228         if (prtad != hw->phy.mdio.prtad)
6229                 return -EINVAL;
6230         return hw->phy.ops.write_reg(hw, addr, devad, value);
6231 }
6232
6233 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6234 {
6235         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6236
6237         return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6238 }
6239
6240 /**
6241  * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
6242  * netdev->dev_addrs
6243  * @netdev: network interface device structure
6244  *
6245  * Returns non-zero on failure
6246  **/
6247 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6248 {
6249         int err = 0;
6250         struct ixgbe_adapter *adapter = netdev_priv(dev);
6251         struct ixgbe_mac_info *mac = &adapter->hw.mac;
6252
6253         if (is_valid_ether_addr(mac->san_addr)) {
6254                 rtnl_lock();
6255                 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6256                 rtnl_unlock();
6257         }
6258         return err;
6259 }
6260
6261 /**
6262  * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
6263  * netdev->dev_addrs
6264  * @netdev: network interface device structure
6265  *
6266  * Returns non-zero on failure
6267  **/
6268 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6269 {
6270         int err = 0;
6271         struct ixgbe_adapter *adapter = netdev_priv(dev);
6272         struct ixgbe_mac_info *mac = &adapter->hw.mac;
6273
6274         if (is_valid_ether_addr(mac->san_addr)) {
6275                 rtnl_lock();
6276                 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6277                 rtnl_unlock();
6278         }
6279         return err;
6280 }
6281
6282 #ifdef CONFIG_NET_POLL_CONTROLLER
6283 /*
6284  * Polling 'interrupt' - used by things like netconsole to send skbs
6285  * without having to re-enable interrupts. It's not called while
6286  * the interrupt routine is executing.
6287  */
6288 static void ixgbe_netpoll(struct net_device *netdev)
6289 {
6290         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6291         int i;
6292
6293         /* if interface is down do nothing */
6294         if (test_bit(__IXGBE_DOWN, &adapter->state))
6295                 return;
6296
6297         adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
6298         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
6299                 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
6300                 for (i = 0; i < num_q_vectors; i++) {
6301                         struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
6302                         ixgbe_msix_clean_many(0, q_vector);
6303                 }
6304         } else {
6305                 ixgbe_intr(adapter->pdev->irq, netdev);
6306         }
6307         adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
6308 }
6309 #endif
6310
6311 static const struct net_device_ops ixgbe_netdev_ops = {
6312         .ndo_open               = ixgbe_open,
6313         .ndo_stop               = ixgbe_close,
6314         .ndo_start_xmit         = ixgbe_xmit_frame,
6315         .ndo_select_queue       = ixgbe_select_queue,
6316         .ndo_set_rx_mode        = ixgbe_set_rx_mode,
6317         .ndo_set_multicast_list = ixgbe_set_rx_mode,
6318         .ndo_validate_addr      = eth_validate_addr,
6319         .ndo_set_mac_address    = ixgbe_set_mac,
6320         .ndo_change_mtu         = ixgbe_change_mtu,
6321         .ndo_tx_timeout         = ixgbe_tx_timeout,
6322         .ndo_vlan_rx_register   = ixgbe_vlan_rx_register,
6323         .ndo_vlan_rx_add_vid    = ixgbe_vlan_rx_add_vid,
6324         .ndo_vlan_rx_kill_vid   = ixgbe_vlan_rx_kill_vid,
6325         .ndo_do_ioctl           = ixgbe_ioctl,
6326         .ndo_set_vf_mac         = ixgbe_ndo_set_vf_mac,
6327         .ndo_set_vf_vlan        = ixgbe_ndo_set_vf_vlan,
6328         .ndo_set_vf_tx_rate     = ixgbe_ndo_set_vf_bw,
6329         .ndo_get_vf_config      = ixgbe_ndo_get_vf_config,
6330 #ifdef CONFIG_NET_POLL_CONTROLLER
6331         .ndo_poll_controller    = ixgbe_netpoll,
6332 #endif
6333 #ifdef IXGBE_FCOE
6334         .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
6335         .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
6336         .ndo_fcoe_enable = ixgbe_fcoe_enable,
6337         .ndo_fcoe_disable = ixgbe_fcoe_disable,
6338         .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
6339 #endif /* IXGBE_FCOE */
6340 };
6341
6342 static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
6343                            const struct ixgbe_info *ii)
6344 {
6345 #ifdef CONFIG_PCI_IOV
6346         struct ixgbe_hw *hw = &adapter->hw;
6347         int err;
6348
6349         if (hw->mac.type != ixgbe_mac_82599EB || !max_vfs)
6350                 return;
6351
6352         /* The 82599 supports up to 64 VFs per physical function
6353          * but this implementation limits allocation to 63 so that
6354          * basic networking resources are still available to the
6355          * physical function
6356          */
6357         adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
6358         adapter->flags |= IXGBE_FLAG_SRIOV_ENABLED;
6359         err = pci_enable_sriov(adapter->pdev, adapter->num_vfs);
6360         if (err) {
6361                 DPRINTK(PROBE, ERR,
6362                         "Failed to enable PCI sriov: %d\n", err);
6363                 goto err_novfs;
6364         }
6365         /* If call to enable VFs succeeded then allocate memory
6366          * for per VF control structures.
6367          */
6368         adapter->vfinfo =
6369                 kcalloc(adapter->num_vfs,
6370                         sizeof(struct vf_data_storage), GFP_KERNEL);
6371         if (adapter->vfinfo) {
6372                 /* Now that we're sure SR-IOV is enabled
6373                  * and memory allocated set up the mailbox parameters
6374                  */
6375                 ixgbe_init_mbx_params_pf(hw);
6376                 memcpy(&hw->mbx.ops, ii->mbx_ops,
6377                        sizeof(hw->mbx.ops));
6378
6379                 /* Disable RSC when in SR-IOV mode */
6380                 adapter->flags2 &= ~(IXGBE_FLAG2_RSC_CAPABLE |
6381                                      IXGBE_FLAG2_RSC_ENABLED);
6382                 return;
6383         }
6384
6385         /* Oh oh */
6386         DPRINTK(PROBE, ERR,
6387                 "Unable to allocate memory for VF "
6388                 "Data Storage - SRIOV disabled\n");
6389         pci_disable_sriov(adapter->pdev);
6390
6391 err_novfs:
6392         adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
6393         adapter->num_vfs = 0;
6394 #endif /* CONFIG_PCI_IOV */
6395 }
6396
6397 /**
6398  * ixgbe_probe - Device Initialization Routine
6399  * @pdev: PCI device information struct
6400  * @ent: entry in ixgbe_pci_tbl
6401  *
6402  * Returns 0 on success, negative on failure
6403  *
6404  * ixgbe_probe initializes an adapter identified by a pci_dev structure.
6405  * The OS initialization, configuring of the adapter private structure,
6406  * and a hardware reset occur.
6407  **/
6408 static int __devinit ixgbe_probe(struct pci_dev *pdev,
6409                                  const struct pci_device_id *ent)
6410 {
6411         struct net_device *netdev;
6412         struct ixgbe_adapter *adapter = NULL;
6413         struct ixgbe_hw *hw;
6414         const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
6415         static int cards_found;
6416         int i, err, pci_using_dac;
6417         unsigned int indices = num_possible_cpus();
6418 #ifdef IXGBE_FCOE
6419         u16 device_caps;
6420 #endif
6421         u32 part_num, eec;
6422
6423         err = pci_enable_device_mem(pdev);
6424         if (err)
6425                 return err;
6426
6427         if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
6428             !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
6429                 pci_using_dac = 1;
6430         } else {
6431                 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
6432                 if (err) {
6433                         err = dma_set_coherent_mask(&pdev->dev,
6434                                                     DMA_BIT_MASK(32));
6435                         if (err) {
6436                                 dev_err(&pdev->dev, "No usable DMA "
6437                                         "configuration, aborting\n");
6438                                 goto err_dma;
6439                         }
6440                 }
6441                 pci_using_dac = 0;
6442         }
6443
6444         err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
6445                                            IORESOURCE_MEM), ixgbe_driver_name);
6446         if (err) {
6447                 dev_err(&pdev->dev,
6448                         "pci_request_selected_regions failed 0x%x\n", err);
6449                 goto err_pci_reg;
6450         }
6451
6452         pci_enable_pcie_error_reporting(pdev);
6453
6454         pci_set_master(pdev);
6455         pci_save_state(pdev);
6456
6457         if (ii->mac == ixgbe_mac_82598EB)
6458                 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
6459         else
6460                 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
6461
6462         indices = max_t(unsigned int, indices, IXGBE_MAX_DCB_INDICES);
6463 #ifdef IXGBE_FCOE
6464         indices += min_t(unsigned int, num_possible_cpus(),
6465                          IXGBE_MAX_FCOE_INDICES);
6466 #endif
6467         netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
6468         if (!netdev) {
6469                 err = -ENOMEM;
6470                 goto err_alloc_etherdev;
6471         }
6472
6473         SET_NETDEV_DEV(netdev, &pdev->dev);
6474
6475         pci_set_drvdata(pdev, netdev);
6476         adapter = netdev_priv(netdev);
6477
6478         adapter->netdev = netdev;
6479         adapter->pdev = pdev;
6480         hw = &adapter->hw;
6481         hw->back = adapter;
6482         adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
6483
6484         hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
6485                               pci_resource_len(pdev, 0));
6486         if (!hw->hw_addr) {
6487                 err = -EIO;
6488                 goto err_ioremap;
6489         }
6490
6491         for (i = 1; i <= 5; i++) {
6492                 if (pci_resource_len(pdev, i) == 0)
6493                         continue;
6494         }
6495
6496         netdev->netdev_ops = &ixgbe_netdev_ops;
6497         ixgbe_set_ethtool_ops(netdev);
6498         netdev->watchdog_timeo = 5 * HZ;
6499         strcpy(netdev->name, pci_name(pdev));
6500
6501         adapter->bd_number = cards_found;
6502
6503         /* Setup hw api */
6504         memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
6505         hw->mac.type  = ii->mac;
6506
6507         /* EEPROM */
6508         memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
6509         eec = IXGBE_READ_REG(hw, IXGBE_EEC);
6510         /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
6511         if (!(eec & (1 << 8)))
6512                 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
6513
6514         /* PHY */
6515         memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
6516         hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6517         /* ixgbe_identify_phy_generic will set prtad and mmds properly */
6518         hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
6519         hw->phy.mdio.mmds = 0;
6520         hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
6521         hw->phy.mdio.dev = netdev;
6522         hw->phy.mdio.mdio_read = ixgbe_mdio_read;
6523         hw->phy.mdio.mdio_write = ixgbe_mdio_write;
6524
6525         /* set up this timer and work struct before calling get_invariants
6526          * which might start the timer
6527          */
6528         init_timer(&adapter->sfp_timer);
6529         adapter->sfp_timer.function = &ixgbe_sfp_timer;
6530         adapter->sfp_timer.data = (unsigned long) adapter;
6531
6532         INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
6533
6534         /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
6535         INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
6536
6537         /* a new SFP+ module arrival, called from GPI SDP2 context */
6538         INIT_WORK(&adapter->sfp_config_module_task,
6539                   ixgbe_sfp_config_module_task);
6540
6541         ii->get_invariants(hw);
6542
6543         /* setup the private structure */
6544         err = ixgbe_sw_init(adapter);
6545         if (err)
6546                 goto err_sw_init;
6547
6548         /* Make it possible the adapter to be woken up via WOL */
6549         if (adapter->hw.mac.type == ixgbe_mac_82599EB)
6550                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6551
6552         /*
6553          * If there is a fan on this device and it has failed log the
6554          * failure.
6555          */
6556         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
6557                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
6558                 if (esdp & IXGBE_ESDP_SDP1)
6559                         DPRINTK(PROBE, CRIT,
6560                                 "Fan has stopped, replace the adapter\n");
6561         }
6562
6563         /* reset_hw fills in the perm_addr as well */
6564         err = hw->mac.ops.reset_hw(hw);
6565         if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
6566             hw->mac.type == ixgbe_mac_82598EB) {
6567                 /*
6568                  * Start a kernel thread to watch for a module to arrive.
6569                  * Only do this for 82598, since 82599 will generate
6570                  * interrupts on module arrival.
6571                  */
6572                 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
6573                 mod_timer(&adapter->sfp_timer,
6574                           round_jiffies(jiffies + (2 * HZ)));
6575                 err = 0;
6576         } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
6577                 dev_err(&adapter->pdev->dev, "failed to initialize because "
6578                         "an unsupported SFP+ module type was detected.\n"
6579                         "Reload the driver after installing a supported "
6580                         "module.\n");
6581                 goto err_sw_init;
6582         } else if (err) {
6583                 dev_err(&adapter->pdev->dev, "HW Init failed: %d\n", err);
6584                 goto err_sw_init;
6585         }
6586
6587         ixgbe_probe_vf(adapter, ii);
6588
6589         netdev->features = NETIF_F_SG |
6590                            NETIF_F_IP_CSUM |
6591                            NETIF_F_HW_VLAN_TX |
6592                            NETIF_F_HW_VLAN_RX |
6593                            NETIF_F_HW_VLAN_FILTER;
6594
6595         netdev->features |= NETIF_F_IPV6_CSUM;
6596         netdev->features |= NETIF_F_TSO;
6597         netdev->features |= NETIF_F_TSO6;
6598         netdev->features |= NETIF_F_GRO;
6599
6600         if (adapter->hw.mac.type == ixgbe_mac_82599EB)
6601                 netdev->features |= NETIF_F_SCTP_CSUM;
6602
6603         netdev->vlan_features |= NETIF_F_TSO;
6604         netdev->vlan_features |= NETIF_F_TSO6;
6605         netdev->vlan_features |= NETIF_F_IP_CSUM;
6606         netdev->vlan_features |= NETIF_F_IPV6_CSUM;
6607         netdev->vlan_features |= NETIF_F_SG;
6608
6609         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6610                 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
6611                                     IXGBE_FLAG_DCB_ENABLED);
6612         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
6613                 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
6614
6615 #ifdef CONFIG_IXGBE_DCB
6616         netdev->dcbnl_ops = &dcbnl_ops;
6617 #endif
6618
6619 #ifdef IXGBE_FCOE
6620         if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
6621                 if (hw->mac.ops.get_device_caps) {
6622                         hw->mac.ops.get_device_caps(hw, &device_caps);
6623                         if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
6624                                 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
6625                 }
6626         }
6627 #endif /* IXGBE_FCOE */
6628         if (pci_using_dac)
6629                 netdev->features |= NETIF_F_HIGHDMA;
6630
6631         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
6632                 netdev->features |= NETIF_F_LRO;
6633
6634         /* make sure the EEPROM is good */
6635         if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
6636                 dev_err(&pdev->dev, "The EEPROM Checksum Is Not Valid\n");
6637                 err = -EIO;
6638                 goto err_eeprom;
6639         }
6640
6641         memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
6642         memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
6643
6644         if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
6645                 dev_err(&pdev->dev, "invalid MAC address\n");
6646                 err = -EIO;
6647                 goto err_eeprom;
6648         }
6649
6650         /* power down the optics */
6651         if (hw->phy.multispeed_fiber)
6652                 hw->mac.ops.disable_tx_laser(hw);
6653
6654         init_timer(&adapter->watchdog_timer);
6655         adapter->watchdog_timer.function = &ixgbe_watchdog;
6656         adapter->watchdog_timer.data = (unsigned long)adapter;
6657
6658         INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
6659         INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
6660
6661         err = ixgbe_init_interrupt_scheme(adapter);
6662         if (err)
6663                 goto err_sw_init;
6664
6665         switch (pdev->device) {
6666         case IXGBE_DEV_ID_82599_KX4:
6667                 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
6668                                 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
6669                 break;
6670         default:
6671                 adapter->wol = 0;
6672                 break;
6673         }
6674         device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
6675
6676         /* pick up the PCI bus settings for reporting later */
6677         hw->mac.ops.get_bus_info(hw);
6678
6679         /* print bus type/speed/width info */
6680         dev_info(&pdev->dev, "(PCI Express:%s:%s) %pM\n",
6681                 ((hw->bus.speed == ixgbe_bus_speed_5000) ? "5.0Gb/s":
6682                  (hw->bus.speed == ixgbe_bus_speed_2500) ? "2.5Gb/s":"Unknown"),
6683                 ((hw->bus.width == ixgbe_bus_width_pcie_x8) ? "Width x8" :
6684                  (hw->bus.width == ixgbe_bus_width_pcie_x4) ? "Width x4" :
6685                  (hw->bus.width == ixgbe_bus_width_pcie_x1) ? "Width x1" :
6686                  "Unknown"),
6687                 netdev->dev_addr);
6688         ixgbe_read_pba_num_generic(hw, &part_num);
6689         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
6690                 dev_info(&pdev->dev, "MAC: %d, PHY: %d, SFP+: %d, PBA No: %06x-%03x\n",
6691                          hw->mac.type, hw->phy.type, hw->phy.sfp_type,
6692                          (part_num >> 8), (part_num & 0xff));
6693         else
6694                 dev_info(&pdev->dev, "MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
6695                          hw->mac.type, hw->phy.type,
6696                          (part_num >> 8), (part_num & 0xff));
6697
6698         if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
6699                 dev_warn(&pdev->dev, "PCI-Express bandwidth available for "
6700                          "this card is not sufficient for optimal "
6701                          "performance.\n");
6702                 dev_warn(&pdev->dev, "For optimal performance a x8 "
6703                          "PCI-Express slot is required.\n");
6704         }
6705
6706         /* save off EEPROM version number */
6707         hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
6708
6709         /* reset the hardware with the new settings */
6710         err = hw->mac.ops.start_hw(hw);
6711
6712         if (err == IXGBE_ERR_EEPROM_VERSION) {
6713                 /* We are running on a pre-production device, log a warning */
6714                 dev_warn(&pdev->dev, "This device is a pre-production "
6715                          "adapter/LOM.  Please be aware there may be issues "
6716                          "associated with your hardware.  If you are "
6717                          "experiencing problems please contact your Intel or "
6718                          "hardware representative who provided you with this "
6719                          "hardware.\n");
6720         }
6721         strcpy(netdev->name, "eth%d");
6722         err = register_netdev(netdev);
6723         if (err)
6724                 goto err_register;
6725
6726         /* carrier off reporting is important to ethtool even BEFORE open */
6727         netif_carrier_off(netdev);
6728
6729         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
6730             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
6731                 INIT_WORK(&adapter->fdir_reinit_task, ixgbe_fdir_reinit_task);
6732
6733 #ifdef CONFIG_IXGBE_DCA
6734         if (dca_add_requester(&pdev->dev) == 0) {
6735                 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
6736                 ixgbe_setup_dca(adapter);
6737         }
6738 #endif
6739         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
6740                 DPRINTK(PROBE, INFO, "IOV is enabled with %d VFs\n",
6741                         adapter->num_vfs);
6742                 for (i = 0; i < adapter->num_vfs; i++)
6743                         ixgbe_vf_configuration(pdev, (i | 0x10000000));
6744         }
6745
6746         /* add san mac addr to netdev */
6747         ixgbe_add_sanmac_netdev(netdev);
6748
6749         dev_info(&pdev->dev, "Intel(R) 10 Gigabit Network Connection\n");
6750         cards_found++;
6751         return 0;
6752
6753 err_register:
6754         ixgbe_release_hw_control(adapter);
6755         ixgbe_clear_interrupt_scheme(adapter);
6756 err_sw_init:
6757 err_eeprom:
6758         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6759                 ixgbe_disable_sriov(adapter);
6760         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
6761         del_timer_sync(&adapter->sfp_timer);
6762         cancel_work_sync(&adapter->sfp_task);
6763         cancel_work_sync(&adapter->multispeed_fiber_task);
6764         cancel_work_sync(&adapter->sfp_config_module_task);
6765         iounmap(hw->hw_addr);
6766 err_ioremap:
6767         free_netdev(netdev);
6768 err_alloc_etherdev:
6769         pci_release_selected_regions(pdev, pci_select_bars(pdev,
6770                                      IORESOURCE_MEM));
6771 err_pci_reg:
6772 err_dma:
6773         pci_disable_device(pdev);
6774         return err;
6775 }
6776
6777 /**
6778  * ixgbe_remove - Device Removal Routine
6779  * @pdev: PCI device information struct
6780  *
6781  * ixgbe_remove is called by the PCI subsystem to alert the driver
6782  * that it should release a PCI device.  The could be caused by a
6783  * Hot-Plug event, or because the driver is going to be removed from
6784  * memory.
6785  **/
6786 static void __devexit ixgbe_remove(struct pci_dev *pdev)
6787 {
6788         struct net_device *netdev = pci_get_drvdata(pdev);
6789         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6790
6791         set_bit(__IXGBE_DOWN, &adapter->state);
6792         /* clear the module not found bit to make sure the worker won't
6793          * reschedule
6794          */
6795         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
6796         del_timer_sync(&adapter->watchdog_timer);
6797
6798         del_timer_sync(&adapter->sfp_timer);
6799         cancel_work_sync(&adapter->watchdog_task);
6800         cancel_work_sync(&adapter->sfp_task);
6801         cancel_work_sync(&adapter->multispeed_fiber_task);
6802         cancel_work_sync(&adapter->sfp_config_module_task);
6803         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
6804             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
6805                 cancel_work_sync(&adapter->fdir_reinit_task);
6806         flush_scheduled_work();
6807
6808 #ifdef CONFIG_IXGBE_DCA
6809         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
6810                 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
6811                 dca_remove_requester(&pdev->dev);
6812                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
6813         }
6814
6815 #endif
6816 #ifdef IXGBE_FCOE
6817         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
6818                 ixgbe_cleanup_fcoe(adapter);
6819
6820 #endif /* IXGBE_FCOE */
6821
6822         /* remove the added san mac */
6823         ixgbe_del_sanmac_netdev(netdev);
6824
6825         if (netdev->reg_state == NETREG_REGISTERED)
6826                 unregister_netdev(netdev);
6827
6828         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6829                 ixgbe_disable_sriov(adapter);
6830
6831         ixgbe_clear_interrupt_scheme(adapter);
6832
6833         ixgbe_release_hw_control(adapter);
6834
6835         iounmap(adapter->hw.hw_addr);
6836         pci_release_selected_regions(pdev, pci_select_bars(pdev,
6837                                      IORESOURCE_MEM));
6838
6839         DPRINTK(PROBE, INFO, "complete\n");
6840
6841         free_netdev(netdev);
6842
6843         pci_disable_pcie_error_reporting(pdev);
6844
6845         pci_disable_device(pdev);
6846 }
6847
6848 /**
6849  * ixgbe_io_error_detected - called when PCI error is detected
6850  * @pdev: Pointer to PCI device
6851  * @state: The current pci connection state
6852  *
6853  * This function is called after a PCI bus error affecting
6854  * this device has been detected.
6855  */
6856 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
6857                                                 pci_channel_state_t state)
6858 {
6859         struct net_device *netdev = pci_get_drvdata(pdev);
6860         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6861
6862         netif_device_detach(netdev);
6863
6864         if (state == pci_channel_io_perm_failure)
6865                 return PCI_ERS_RESULT_DISCONNECT;
6866
6867         if (netif_running(netdev))
6868                 ixgbe_down(adapter);
6869         pci_disable_device(pdev);
6870
6871         /* Request a slot reset. */
6872         return PCI_ERS_RESULT_NEED_RESET;
6873 }
6874
6875 /**
6876  * ixgbe_io_slot_reset - called after the pci bus has been reset.
6877  * @pdev: Pointer to PCI device
6878  *
6879  * Restart the card from scratch, as if from a cold-boot.
6880  */
6881 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
6882 {
6883         struct net_device *netdev = pci_get_drvdata(pdev);
6884         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6885         pci_ers_result_t result;
6886         int err;
6887
6888         if (pci_enable_device_mem(pdev)) {
6889                 DPRINTK(PROBE, ERR,
6890                         "Cannot re-enable PCI device after reset.\n");
6891                 result = PCI_ERS_RESULT_DISCONNECT;
6892         } else {
6893                 pci_set_master(pdev);
6894                 pci_restore_state(pdev);
6895                 pci_save_state(pdev);
6896
6897                 pci_wake_from_d3(pdev, false);
6898
6899                 ixgbe_reset(adapter);
6900                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6901                 result = PCI_ERS_RESULT_RECOVERED;
6902         }
6903
6904         err = pci_cleanup_aer_uncorrect_error_status(pdev);
6905         if (err) {
6906                 dev_err(&pdev->dev,
6907                   "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", err);
6908                 /* non-fatal, continue */
6909         }
6910
6911         return result;
6912 }
6913
6914 /**
6915  * ixgbe_io_resume - called when traffic can start flowing again.
6916  * @pdev: Pointer to PCI device
6917  *
6918  * This callback is called when the error recovery driver tells us that
6919  * its OK to resume normal operation.
6920  */
6921 static void ixgbe_io_resume(struct pci_dev *pdev)
6922 {
6923         struct net_device *netdev = pci_get_drvdata(pdev);
6924         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6925
6926         if (netif_running(netdev)) {
6927                 if (ixgbe_up(adapter)) {
6928                         DPRINTK(PROBE, INFO, "ixgbe_up failed after reset\n");
6929                         return;
6930                 }
6931         }
6932
6933         netif_device_attach(netdev);
6934 }
6935
6936 static struct pci_error_handlers ixgbe_err_handler = {
6937         .error_detected = ixgbe_io_error_detected,
6938         .slot_reset = ixgbe_io_slot_reset,
6939         .resume = ixgbe_io_resume,
6940 };
6941
6942 static struct pci_driver ixgbe_driver = {
6943         .name     = ixgbe_driver_name,
6944         .id_table = ixgbe_pci_tbl,
6945         .probe    = ixgbe_probe,
6946         .remove   = __devexit_p(ixgbe_remove),
6947 #ifdef CONFIG_PM
6948         .suspend  = ixgbe_suspend,
6949         .resume   = ixgbe_resume,
6950 #endif
6951         .shutdown = ixgbe_shutdown,
6952         .err_handler = &ixgbe_err_handler
6953 };
6954
6955 /**
6956  * ixgbe_init_module - Driver Registration Routine
6957  *
6958  * ixgbe_init_module is the first routine called when the driver is
6959  * loaded. All it does is register with the PCI subsystem.
6960  **/
6961 static int __init ixgbe_init_module(void)
6962 {
6963         int ret;
6964         printk(KERN_INFO "%s: %s - version %s\n", ixgbe_driver_name,
6965                ixgbe_driver_string, ixgbe_driver_version);
6966
6967         printk(KERN_INFO "%s: %s\n", ixgbe_driver_name, ixgbe_copyright);
6968
6969 #ifdef CONFIG_IXGBE_DCA
6970         dca_register_notify(&dca_notifier);
6971 #endif
6972
6973         ret = pci_register_driver(&ixgbe_driver);
6974         return ret;
6975 }
6976
6977 module_init(ixgbe_init_module);
6978
6979 /**
6980  * ixgbe_exit_module - Driver Exit Cleanup Routine
6981  *
6982  * ixgbe_exit_module is called just before the driver is removed
6983  * from memory.
6984  **/
6985 static void __exit ixgbe_exit_module(void)
6986 {
6987 #ifdef CONFIG_IXGBE_DCA
6988         dca_unregister_notify(&dca_notifier);
6989 #endif
6990         pci_unregister_driver(&ixgbe_driver);
6991 }
6992
6993 #ifdef CONFIG_IXGBE_DCA
6994 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
6995                             void *p)
6996 {
6997         int ret_val;
6998
6999         ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
7000                                          __ixgbe_notify_dca);
7001
7002         return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7003 }
7004
7005 #endif /* CONFIG_IXGBE_DCA */
7006 #ifdef DEBUG
7007 /**
7008  * ixgbe_get_hw_dev_name - return device name string
7009  * used by hardware layer to print debugging information
7010  **/
7011 char *ixgbe_get_hw_dev_name(struct ixgbe_hw *hw)
7012 {
7013         struct ixgbe_adapter *adapter = hw->back;
7014         return adapter->netdev->name;
7015 }
7016
7017 #endif
7018 module_exit(ixgbe_exit_module);
7019
7020 /* ixgbe_main.c */