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   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2010 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #include <linux/types.h>
  29 #include <linux/module.h>
  30 #include <linux/pci.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/vmalloc.h>
  33 #include <linux/string.h>
  34 #include <linux/in.h>
  35 #include <linux/ip.h>
  36 #include <linux/tcp.h>
  37 #include <linux/pkt_sched.h>
  38 #include <linux/ipv6.h>
  39 #include <linux/slab.h>
  40 #include <net/checksum.h>
  41 #include <net/ip6_checksum.h>
  42 #include <linux/ethtool.h>
  43 #include <linux/if_vlan.h>
  44 #include <scsi/fc/fc_fcoe.h>
  45
  46 #include "ixgbe.h"
  47 #include "ixgbe_common.h"
  48 #include "ixgbe_dcb_82599.h"
  49 #include "ixgbe_sriov.h"
  50
  51 char ixgbe_driver_name[] = "ixgbe";
  52 static const char ixgbe_driver_string[] =
  53                               "Intel(R) 10 Gigabit PCI Express Network Driver";
  54
  55 #define DRV_VERSION "2.0.62-k2"
  56 const char ixgbe_driver_version[] = DRV_VERSION;
  57 static char ixgbe_copyright[] = "Copyright (c) 1999-2010 Intel Corporation.";
  58
  59 static const struct ixgbe_info *ixgbe_info_tbl[] = {
  60         [board_82598] = &ixgbe_82598_info,
  61         [board_82599] = &ixgbe_82599_info,
  62 };
  63
  64 /* ixgbe_pci_tbl - PCI Device ID Table
  65  *
  66  * Wildcard entries (PCI_ANY_ID) should come last
  67  * Last entry must be all 0s
  68  *
  69  * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
  70  *   Class, Class Mask, private data (not used) }
  71  */
  72 static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
  73         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
  74          board_82598 },
  75         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
  76          board_82598 },
  77         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
  78          board_82598 },
  79         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
  80          board_82598 },
  81         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
  82          board_82598 },
  83         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
  84          board_82598 },
  85         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
  86          board_82598 },
  87         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
  88          board_82598 },
  89         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
  90          board_82598 },
  91         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
  92          board_82598 },
  93         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
  94          board_82598 },
  95         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
  96          board_82598 },
  97         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
  98          board_82599 },
  99         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
 100          board_82599 },
 101         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR),
 102          board_82599 },
 103         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
 104          board_82599 },
 105         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM),
 106          board_82599 },
 107         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ),
 108          board_82599 },
 109         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
 110          board_82599 },
 111         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE),
 112          board_82599 },
 113
 114         /* required last entry */
 115         {0, }
 116 };
 117 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
 118
 119 #ifdef CONFIG_IXGBE_DCA
 120 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
 121                             void *p);
 122 static struct notifier_block dca_notifier = {
 123         .notifier_call = ixgbe_notify_dca,
 124         .next          = NULL,
 125         .priority      = 0
 126 };
 127 #endif
 128
 129 #ifdef CONFIG_PCI_IOV
 130 static unsigned int max_vfs;
 131 module_param(max_vfs, uint, 0);
 132 MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate "
 133                  "per physical function");
 134 #endif /* CONFIG_PCI_IOV */
 135
 136 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
 137 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
 138 MODULE_LICENSE("GPL");
 139 MODULE_VERSION(DRV_VERSION);
 140
 141 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
 142
 143 static inline void ixgbe_disable_sriov(struct ixgbe_adapter *adapter)
 144 {
 145         struct ixgbe_hw *hw = &adapter->hw;
 146         u32 gcr;
 147         u32 gpie;
 148         u32 vmdctl;
 149
 150 #ifdef CONFIG_PCI_IOV
 151         /* disable iov and allow time for transactions to clear */
 152         pci_disable_sriov(adapter->pdev);
 153 #endif
 154
 155         /* turn off device IOV mode */
 156         gcr = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
 157         gcr &= ~(IXGBE_GCR_EXT_SRIOV);
 158         IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr);
 159         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
 160         gpie &= ~IXGBE_GPIE_VTMODE_MASK;
 161         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
 162
 163         /* set default pool back to 0 */
 164         vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
 165         vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
 166         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
 167
 168         /* take a breather then clean up driver data */
 169         msleep(100);
 170         if (adapter->vfinfo)
 171                 kfree(adapter->vfinfo);
 172         adapter->vfinfo = NULL;
 173
 174         adapter->num_vfs = 0;
 175         adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
 176 }
 177
 178 struct ixgbe_reg_info {
 179         u32 ofs;
 180         char *name;
 181 };
 182
 183 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
 184
 185         /* General Registers */
 186         {IXGBE_CTRL, "CTRL"},
 187         {IXGBE_STATUS, "STATUS"},
 188         {IXGBE_CTRL_EXT, "CTRL_EXT"},
 189
 190         /* Interrupt Registers */
 191         {IXGBE_EICR, "EICR"},
 192
 193         /* RX Registers */
 194         {IXGBE_SRRCTL(0), "SRRCTL"},
 195         {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
 196         {IXGBE_RDLEN(0), "RDLEN"},
 197         {IXGBE_RDH(0), "RDH"},
 198         {IXGBE_RDT(0), "RDT"},
 199         {IXGBE_RXDCTL(0), "RXDCTL"},
 200         {IXGBE_RDBAL(0), "RDBAL"},
 201         {IXGBE_RDBAH(0), "RDBAH"},
 202
 203         /* TX Registers */
 204         {IXGBE_TDBAL(0), "TDBAL"},
 205         {IXGBE_TDBAH(0), "TDBAH"},
 206         {IXGBE_TDLEN(0), "TDLEN"},
 207         {IXGBE_TDH(0), "TDH"},
 208         {IXGBE_TDT(0), "TDT"},
 209         {IXGBE_TXDCTL(0), "TXDCTL"},
 210
 211         /* List Terminator */
 212         {}
 213 };
 214
 215
 216 /*
 217  * ixgbe_regdump - register printout routine
 218  */
 219 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
 220 {
 221         int i = 0, j = 0;
 222         char rname[16];
 223         u32 regs[64];
 224
 225         switch (reginfo->ofs) {
 226         case IXGBE_SRRCTL(0):
 227                 for (i = 0; i < 64; i++)
 228                         regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
 229                 break;
 230         case IXGBE_DCA_RXCTRL(0):
 231                 for (i = 0; i < 64; i++)
 232                         regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
 233                 break;
 234         case IXGBE_RDLEN(0):
 235                 for (i = 0; i < 64; i++)
 236                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
 237                 break;
 238         case IXGBE_RDH(0):
 239                 for (i = 0; i < 64; i++)
 240                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
 241                 break;
 242         case IXGBE_RDT(0):
 243                 for (i = 0; i < 64; i++)
 244                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
 245                 break;
 246         case IXGBE_RXDCTL(0):
 247                 for (i = 0; i < 64; i++)
 248                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
 249                 break;
 250         case IXGBE_RDBAL(0):
 251                 for (i = 0; i < 64; i++)
 252                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
 253                 break;
 254         case IXGBE_RDBAH(0):
 255                 for (i = 0; i < 64; i++)
 256                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
 257                 break;
 258         case IXGBE_TDBAL(0):
 259                 for (i = 0; i < 64; i++)
 260                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
 261                 break;
 262         case IXGBE_TDBAH(0):
 263                 for (i = 0; i < 64; i++)
 264                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
 265                 break;
 266         case IXGBE_TDLEN(0):
 267                 for (i = 0; i < 64; i++)
 268                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
 269                 break;
 270         case IXGBE_TDH(0):
 271                 for (i = 0; i < 64; i++)
 272                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
 273                 break;
 274         case IXGBE_TDT(0):
 275                 for (i = 0; i < 64; i++)
 276                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
 277                 break;
 278         case IXGBE_TXDCTL(0):
 279                 for (i = 0; i < 64; i++)
 280                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
 281                 break;
 282         default:
 283                 printk(KERN_INFO "%-15s %08x\n", reginfo->name,
 284                         IXGBE_READ_REG(hw, reginfo->ofs));
 285                 return;
 286         }
 287
 288         for (i = 0; i < 8; i++) {
 289                 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
 290                 printk(KERN_ERR "%-15s ", rname);
 291                 for (j = 0; j < 8; j++)
 292                         printk(KERN_CONT "%08x ", regs[i*8+j]);
 293                 printk(KERN_CONT "\n");
 294         }
 295
 296 }
 297
 298 /*
 299  * ixgbe_dump - Print registers, tx-rings and rx-rings
 300  */
 301 static void ixgbe_dump(struct ixgbe_adapter *adapter)
 302 {
 303         struct net_device *netdev = adapter->netdev;
 304         struct ixgbe_hw *hw = &adapter->hw;
 305         struct ixgbe_reg_info *reginfo;
 306         int n = 0;
 307         struct ixgbe_ring *tx_ring;
 308         struct ixgbe_tx_buffer *tx_buffer_info;
 309         union ixgbe_adv_tx_desc *tx_desc;
 310         struct my_u0 { u64 a; u64 b; } *u0;
 311         struct ixgbe_ring *rx_ring;
 312         union ixgbe_adv_rx_desc *rx_desc;
 313         struct ixgbe_rx_buffer *rx_buffer_info;
 314         u32 staterr;
 315         int i = 0;
 316
 317         if (!netif_msg_hw(adapter))
 318                 return;
 319
 320         /* Print netdevice Info */
 321         if (netdev) {
 322                 dev_info(&adapter->pdev->dev, "Net device Info\n");
 323                 printk(KERN_INFO "Device Name     state            "
 324                         "trans_start      last_rx\n");
 325                 printk(KERN_INFO "%-15s %016lX %016lX %016lX\n",
 326                 netdev->name,
 327                 netdev->state,
 328                 netdev->trans_start,
 329                 netdev->last_rx);
 330         }
 331
 332         /* Print Registers */
 333         dev_info(&adapter->pdev->dev, "Register Dump\n");
 334         printk(KERN_INFO " Register Name   Value\n");
 335         for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
 336              reginfo->name; reginfo++) {
 337                 ixgbe_regdump(hw, reginfo);
 338         }
 339
 340         /* Print TX Ring Summary */
 341         if (!netdev || !netif_running(netdev))
 342                 goto exit;
 343
 344         dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
 345         printk(KERN_INFO "Queue [NTU] [NTC] [bi(ntc)->dma  ] "
 346                 "leng ntw timestamp\n");
 347         for (n = 0; n < adapter->num_tx_queues; n++) {
 348                 tx_ring = adapter->tx_ring[n];
 349                 tx_buffer_info =
 350                         &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
 351                 printk(KERN_INFO " %5d %5X %5X %016llX %04X %3X %016llX\n",
 352                            n, tx_ring->next_to_use, tx_ring->next_to_clean,
 353                            (u64)tx_buffer_info->dma,
 354                            tx_buffer_info->length,
 355                            tx_buffer_info->next_to_watch,
 356                            (u64)tx_buffer_info->time_stamp);
 357         }
 358
 359         /* Print TX Rings */
 360         if (!netif_msg_tx_done(adapter))
 361                 goto rx_ring_summary;
 362
 363         dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
 364
 365         /* Transmit Descriptor Formats
 366          *
 367          * Advanced Transmit Descriptor
 368          *   +--------------------------------------------------------------+
 369          * 0 |         Buffer Address [63:0]                                |
 370          *   +--------------------------------------------------------------+
 371          * 8 |  PAYLEN  | PORTS  | IDX | STA | DCMD  |DTYP |  RSV |  DTALEN |
 372          *   +--------------------------------------------------------------+
 373          *   63       46 45    40 39 36 35 32 31   24 23 20 19              0
 374          */
 375
 376         for (n = 0; n < adapter->num_tx_queues; n++) {
 377                 tx_ring = adapter->tx_ring[n];
 378                 printk(KERN_INFO "------------------------------------\n");
 379                 printk(KERN_INFO "TX QUEUE INDEX = %d\n", tx_ring->queue_index);
 380                 printk(KERN_INFO "------------------------------------\n");
 381                 printk(KERN_INFO "T [desc]     [address 63:0  ] "
 382                         "[PlPOIdStDDt Ln] [bi->dma       ] "
 383                         "leng  ntw timestamp        bi->skb\n");
 384
 385                 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
 386                         tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
 387                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
 388                         u0 = (struct my_u0 *)tx_desc;
 389                         printk(KERN_INFO "T [0x%03X]    %016llX %016llX %016llX"
 390                                 " %04X  %3X %016llX %p", i,
 391                                 le64_to_cpu(u0->a),
 392                                 le64_to_cpu(u0->b),
 393                                 (u64)tx_buffer_info->dma,
 394                                 tx_buffer_info->length,
 395                                 tx_buffer_info->next_to_watch,
 396                                 (u64)tx_buffer_info->time_stamp,
 397                                 tx_buffer_info->skb);
 398                         if (i == tx_ring->next_to_use &&
 399                                 i == tx_ring->next_to_clean)
 400                                 printk(KERN_CONT " NTC/U\n");
 401                         else if (i == tx_ring->next_to_use)
 402                                 printk(KERN_CONT " NTU\n");
 403                         else if (i == tx_ring->next_to_clean)
 404                                 printk(KERN_CONT " NTC\n");
 405                         else
 406                                 printk(KERN_CONT "\n");
 407
 408                         if (netif_msg_pktdata(adapter) &&
 409                                 tx_buffer_info->dma != 0)
 410                                 print_hex_dump(KERN_INFO, "",
 411                                         DUMP_PREFIX_ADDRESS, 16, 1,
 412                                         phys_to_virt(tx_buffer_info->dma),
 413                                         tx_buffer_info->length, true);
 414                 }
 415         }
 416
 417         /* Print RX Rings Summary */
 418 rx_ring_summary:
 419         dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
 420         printk(KERN_INFO "Queue [NTU] [NTC]\n");
 421         for (n = 0; n < adapter->num_rx_queues; n++) {
 422                 rx_ring = adapter->rx_ring[n];
 423                 printk(KERN_INFO "%5d %5X %5X\n", n,
 424                            rx_ring->next_to_use, rx_ring->next_to_clean);
 425         }
 426
 427         /* Print RX Rings */
 428         if (!netif_msg_rx_status(adapter))
 429                 goto exit;
 430
 431         dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
 432
 433         /* Advanced Receive Descriptor (Read) Format
 434          *    63                                           1        0
 435          *    +-----------------------------------------------------+
 436          *  0 |       Packet Buffer Address [63:1]           |A0/NSE|
 437          *    +----------------------------------------------+------+
 438          *  8 |       Header Buffer Address [63:1]           |  DD  |
 439          *    +-----------------------------------------------------+
 440          *
 441          *
 442          * Advanced Receive Descriptor (Write-Back) Format
 443          *
 444          *   63       48 47    32 31  30      21 20 16 15   4 3     0
 445          *   +------------------------------------------------------+
 446          * 0 | Packet     IP     |SPH| HDR_LEN   | RSV|Packet|  RSS |
 447          *   | Checksum   Ident  |   |           |    | Type | Type |
 448          *   +------------------------------------------------------+
 449          * 8 | VLAN Tag | Length | Extended Error | Extended Status |
 450          *   +------------------------------------------------------+
 451          *   63       48 47    32 31            20 19               0
 452          */
 453         for (n = 0; n < adapter->num_rx_queues; n++) {
 454                 rx_ring = adapter->rx_ring[n];
 455                 printk(KERN_INFO "------------------------------------\n");
 456                 printk(KERN_INFO "RX QUEUE INDEX = %d\n", rx_ring->queue_index);
 457                 printk(KERN_INFO "------------------------------------\n");
 458                 printk(KERN_INFO "R  [desc]      [ PktBuf     A0] "
 459                         "[  HeadBuf   DD] [bi->dma       ] [bi->skb] "
 460                         "<-- Adv Rx Read format\n");
 461                 printk(KERN_INFO "RWB[desc]      [PcsmIpSHl PtRs] "
 462                         "[vl er S cks ln] ---------------- [bi->skb] "
 463                         "<-- Adv Rx Write-Back format\n");
 464
 465                 for (i = 0; i < rx_ring->count; i++) {
 466                         rx_buffer_info = &rx_ring->rx_buffer_info[i];
 467                         rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
 468                         u0 = (struct my_u0 *)rx_desc;
 469                         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
 470                         if (staterr & IXGBE_RXD_STAT_DD) {
 471                                 /* Descriptor Done */
 472                                 printk(KERN_INFO "RWB[0x%03X]     %016llX "
 473                                         "%016llX ---------------- %p", i,
 474                                         le64_to_cpu(u0->a),
 475                                         le64_to_cpu(u0->b),
 476                                         rx_buffer_info->skb);
 477                         } else {
 478                                 printk(KERN_INFO "R  [0x%03X]     %016llX "
 479                                         "%016llX %016llX %p", i,
 480                                         le64_to_cpu(u0->a),
 481                                         le64_to_cpu(u0->b),
 482                                         (u64)rx_buffer_info->dma,
 483                                         rx_buffer_info->skb);
 484
 485                                 if (netif_msg_pktdata(adapter)) {
 486                                         print_hex_dump(KERN_INFO, "",
 487                                            DUMP_PREFIX_ADDRESS, 16, 1,
 488                                            phys_to_virt(rx_buffer_info->dma),
 489                                            rx_ring->rx_buf_len, true);
 490
 491                                         if (rx_ring->rx_buf_len
 492                                                 < IXGBE_RXBUFFER_2048)
 493                                                 print_hex_dump(KERN_INFO, "",
 494                                                   DUMP_PREFIX_ADDRESS, 16, 1,
 495                                                   phys_to_virt(
 496                                                     rx_buffer_info->page_dma +
 497                                                     rx_buffer_info->page_offset
 498                                                   ),
 499                                                   PAGE_SIZE/2, true);
 500                                 }
 501                         }
 502
 503                         if (i == rx_ring->next_to_use)
 504                                 printk(KERN_CONT " NTU\n");
 505                         else if (i == rx_ring->next_to_clean)
 506                                 printk(KERN_CONT " NTC\n");
 507                         else
 508                                 printk(KERN_CONT "\n");
 509
 510                 }
 511         }
 512
 513 exit:
 514         return;
 515 }
 516
 517 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
 518 {
 519         u32 ctrl_ext;
 520
 521         /* Let firmware take over control of h/w */
 522         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 523         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 524                         ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
 525 }
 526
 527 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
 528 {
 529         u32 ctrl_ext;
 530
 531         /* Let firmware know the driver has taken over */
 532         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 533         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 534                         ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
 535 }
 536
 537 /*
 538  * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
 539  * @adapter: pointer to adapter struct
 540  * @direction: 0 for Rx, 1 for Tx, -1 for other causes
 541  * @queue: queue to map the corresponding interrupt to
 542  * @msix_vector: the vector to map to the corresponding queue
 543  *
 544  */
 545 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
 546                            u8 queue, u8 msix_vector)
 547 {
 548         u32 ivar, index;
 549         struct ixgbe_hw *hw = &adapter->hw;
 550         switch (hw->mac.type) {
 551         case ixgbe_mac_82598EB:
 552                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 553                 if (direction == -1)
 554                         direction = 0;
 555                 index = (((direction * 64) + queue) >> 2) & 0x1F;
 556                 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
 557                 ivar &= ~(0xFF << (8 * (queue & 0x3)));
 558                 ivar |= (msix_vector << (8 * (queue & 0x3)));
 559                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
 560                 break;
 561         case ixgbe_mac_82599EB:
 562                 if (direction == -1) {
 563                         /* other causes */
 564                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 565                         index = ((queue & 1) * 8);
 566                         ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
 567                         ivar &= ~(0xFF << index);
 568                         ivar |= (msix_vector << index);
 569                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
 570                         break;
 571                 } else {
 572                         /* tx or rx causes */
 573                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 574                         index = ((16 * (queue & 1)) + (8 * direction));
 575                         ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
 576                         ivar &= ~(0xFF << index);
 577                         ivar |= (msix_vector << index);
 578                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
 579                         break;
 580                 }
 581         default:
 582                 break;
 583         }
 584 }
 585
 586 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
 587                                           u64 qmask)
 588 {
 589         u32 mask;
 590
 591         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 592                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
 593                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
 594         } else {
 595                 mask = (qmask & 0xFFFFFFFF);
 596                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
 597                 mask = (qmask >> 32);
 598                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
 599         }
 600 }
 601
 602 static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
 603                                              struct ixgbe_tx_buffer
 604                                              *tx_buffer_info)
 605 {
 606         if (tx_buffer_info->dma) {
 607                 if (tx_buffer_info->mapped_as_page)
 608                         dma_unmap_page(&adapter->pdev->dev,
 609                                        tx_buffer_info->dma,
 610                                        tx_buffer_info->length,
 611                                        DMA_TO_DEVICE);
 612                 else
 613                         dma_unmap_single(&adapter->pdev->dev,
 614                                          tx_buffer_info->dma,
 615                                          tx_buffer_info->length,
 616                                          DMA_TO_DEVICE);
 617                 tx_buffer_info->dma = 0;
 618         }
 619         if (tx_buffer_info->skb) {
 620                 dev_kfree_skb_any(tx_buffer_info->skb);
 621                 tx_buffer_info->skb = NULL;
 622         }
 623         tx_buffer_info->time_stamp = 0;
 624         /* tx_buffer_info must be completely set up in the transmit path */
 625 }
 626
 627 /**
 628  * ixgbe_tx_is_paused - check if the tx ring is paused
 629  * @adapter: the ixgbe adapter
 630  * @tx_ring: the corresponding tx_ring
 631  *
 632  * If not in DCB mode, checks TFCS.TXOFF, otherwise, find out the
 633  * corresponding TC of this tx_ring when checking TFCS.
 634  *
 635  * Returns : true if paused
 636  */
 637 static inline bool ixgbe_tx_is_paused(struct ixgbe_adapter *adapter,
 638                                       struct ixgbe_ring *tx_ring)
 639 {
 640         u32 txoff = IXGBE_TFCS_TXOFF;
 641
 642 #ifdef CONFIG_IXGBE_DCB
 643         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
 644                 int tc;
 645                 int reg_idx = tx_ring->reg_idx;
 646                 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
 647
 648                 switch (adapter->hw.mac.type) {
 649                 case ixgbe_mac_82598EB:
 650                         tc = reg_idx >> 2;
 651                         txoff = IXGBE_TFCS_TXOFF0;
 652                         break;
 653                 case ixgbe_mac_82599EB:
 654                         tc = 0;
 655                         txoff = IXGBE_TFCS_TXOFF;
 656                         if (dcb_i == 8) {
 657                                 /* TC0, TC1 */
 658                                 tc = reg_idx >> 5;
 659                                 if (tc == 2) /* TC2, TC3 */
 660                                         tc += (reg_idx - 64) >> 4;
 661                                 else if (tc == 3) /* TC4, TC5, TC6, TC7 */
 662                                         tc += 1 + ((reg_idx - 96) >> 3);
 663                         } else if (dcb_i == 4) {
 664                                 /* TC0, TC1 */
 665                                 tc = reg_idx >> 6;
 666                                 if (tc == 1) {
 667                                         tc += (reg_idx - 64) >> 5;
 668                                         if (tc == 2) /* TC2, TC3 */
 669                                                 tc += (reg_idx - 96) >> 4;
 670                                 }
 671                         }
 672                         break;
 673                 default:
 674                         tc = 0;
 675                 }
 676                 txoff <<= tc;
 677         }
 678 #endif
 679         return IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & txoff;
 680 }
 681
 682 static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
 683                                        struct ixgbe_ring *tx_ring,
 684                                        unsigned int eop)
 685 {
 686         struct ixgbe_hw *hw = &adapter->hw;
 687
 688         /* Detect a transmit hang in hardware, this serializes the
 689          * check with the clearing of time_stamp and movement of eop */
 690         adapter->detect_tx_hung = false;
 691         if (tx_ring->tx_buffer_info[eop].time_stamp &&
 692             time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
 693             !ixgbe_tx_is_paused(adapter, tx_ring)) {
 694                 /* detected Tx unit hang */
 695                 union ixgbe_adv_tx_desc *tx_desc;
 696                 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
 697                 DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
 698                         "  Tx Queue             <%d>\n"
 699                         "  TDH, TDT             <%x>, <%x>\n"
 700                         "  next_to_use          <%x>\n"
 701                         "  next_to_clean        <%x>\n"
 702                         "tx_buffer_info[next_to_clean]\n"
 703                         "  time_stamp           <%lx>\n"
 704                         "  jiffies              <%lx>\n",
 705                         tx_ring->queue_index,
 706                         IXGBE_READ_REG(hw, tx_ring->head),
 707                         IXGBE_READ_REG(hw, tx_ring->tail),
 708                         tx_ring->next_to_use, eop,
 709                         tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
 710                 return true;
 711         }
 712
 713         return false;
 714 }
 715
 716 #define IXGBE_MAX_TXD_PWR       14
 717 #define IXGBE_MAX_DATA_PER_TXD  (1 << IXGBE_MAX_TXD_PWR)
 718
 719 /* Tx Descriptors needed, worst case */
 720 #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
 721                          (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
 722 #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
 723         MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
 724
 725 static void ixgbe_tx_timeout(struct net_device *netdev);
 726
 727 /**
 728  * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
 729  * @q_vector: structure containing interrupt and ring information
 730  * @tx_ring: tx ring to clean
 731  **/
 732 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
 733                                struct ixgbe_ring *tx_ring)
 734 {
 735         struct ixgbe_adapter *adapter = q_vector->adapter;
 736         struct net_device *netdev = adapter->netdev;
 737         union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
 738         struct ixgbe_tx_buffer *tx_buffer_info;
 739         unsigned int i, eop, count = 0;
 740         unsigned int total_bytes = 0, total_packets = 0;
 741
 742         i = tx_ring->next_to_clean;
 743         eop = tx_ring->tx_buffer_info[i].next_to_watch;
 744         eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
 745
 746         while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
 747                (count < tx_ring->work_limit)) {
 748                 bool cleaned = false;
 749                 for ( ; !cleaned; count++) {
 750                         struct sk_buff *skb;
 751                         tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
 752                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
 753                         cleaned = (i == eop);
 754                         skb = tx_buffer_info->skb;
 755
 756                         if (cleaned && skb) {
 757                                 unsigned int segs, bytecount;
 758                                 unsigned int hlen = skb_headlen(skb);
 759
 760                                 /* gso_segs is currently only valid for tcp */
 761                                 segs = skb_shinfo(skb)->gso_segs ?: 1;
 762 #ifdef IXGBE_FCOE
 763                                 /* adjust for FCoE Sequence Offload */
 764                                 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
 765                                     && (skb->protocol == htons(ETH_P_FCOE)) &&
 766                                     skb_is_gso(skb)) {
 767                                         hlen = skb_transport_offset(skb) +
 768                                                 sizeof(struct fc_frame_header) +
 769                                                 sizeof(struct fcoe_crc_eof);
 770                                         segs = DIV_ROUND_UP(skb->len - hlen,
 771                                                 skb_shinfo(skb)->gso_size);
 772                                 }
 773 #endif /* IXGBE_FCOE */
 774                                 /* multiply data chunks by size of headers */
 775                                 bytecount = ((segs - 1) * hlen) + skb->len;
 776                                 total_packets += segs;
 777                                 total_bytes += bytecount;
 778                         }
 779
 780                         ixgbe_unmap_and_free_tx_resource(adapter,
 781                                                          tx_buffer_info);
 782
 783                         tx_desc->wb.status = 0;
 784
 785                         i++;
 786                         if (i == tx_ring->count)
 787                                 i = 0;
 788                 }
 789
 790                 eop = tx_ring->tx_buffer_info[i].next_to_watch;
 791                 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
 792         }
 793
 794         tx_ring->next_to_clean = i;
 795
 796 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
 797         if (unlikely(count && netif_carrier_ok(netdev) &&
 798                      (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
 799                 /* Make sure that anybody stopping the queue after this
 800                  * sees the new next_to_clean.
 801                  */
 802                 smp_mb();
 803                 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
 804                     !test_bit(__IXGBE_DOWN, &adapter->state)) {
 805                         netif_wake_subqueue(netdev, tx_ring->queue_index);
 806                         ++tx_ring->restart_queue;
 807                 }
 808         }
 809
 810         if (adapter->detect_tx_hung) {
 811                 if (ixgbe_check_tx_hang(adapter, tx_ring, i)) {
 812                         /* schedule immediate reset if we believe we hung */
 813                         DPRINTK(PROBE, INFO,
 814                                 "tx hang %d detected, resetting adapter\n",
 815                                 adapter->tx_timeout_count + 1);
 816                         ixgbe_tx_timeout(adapter->netdev);
 817                 }
 818         }
 819
 820         /* re-arm the interrupt */
 821         if (count >= tx_ring->work_limit)
 822                 ixgbe_irq_rearm_queues(adapter, ((u64)1 << q_vector->v_idx));
 823
 824         tx_ring->total_bytes += total_bytes;
 825         tx_ring->total_packets += total_packets;
 826         tx_ring->stats.packets += total_packets;
 827         tx_ring->stats.bytes += total_bytes;
 828         return (count < tx_ring->work_limit);
 829 }
 830
 831 #ifdef CONFIG_IXGBE_DCA
 832 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
 833                                 struct ixgbe_ring *rx_ring)
 834 {
 835         u32 rxctrl;
 836         int cpu = get_cpu();
 837         int q = rx_ring->reg_idx;
 838
 839         if (rx_ring->cpu != cpu) {
 840                 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
 841                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 842                         rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
 843                         rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 844                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
 845                         rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
 846                         rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
 847                                    IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
 848                 }
 849                 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
 850                 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
 851                 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
 852                 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
 853                             IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
 854                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
 855                 rx_ring->cpu = cpu;
 856         }
 857         put_cpu();
 858 }
 859
 860 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
 861                                 struct ixgbe_ring *tx_ring)
 862 {
 863         u32 txctrl;
 864         int cpu = get_cpu();
 865         int q = tx_ring->reg_idx;
 866         struct ixgbe_hw *hw = &adapter->hw;
 867
 868         if (tx_ring->cpu != cpu) {
 869                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 870                         txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(q));
 871                         txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
 872                         txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 873                         txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
 874                         IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(q), txctrl);
 875                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
 876                         txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(q));
 877                         txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
 878                         txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
 879                                   IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
 880                         txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
 881                         IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(q), txctrl);
 882                 }
 883                 tx_ring->cpu = cpu;
 884         }
 885         put_cpu();
 886 }
 887
 888 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
 889 {
 890         int i;
 891
 892         if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
 893                 return;
 894
 895         /* always use CB2 mode, difference is masked in the CB driver */
 896         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
 897
 898         for (i = 0; i < adapter->num_tx_queues; i++) {
 899                 adapter->tx_ring[i]->cpu = -1;
 900                 ixgbe_update_tx_dca(adapter, adapter->tx_ring[i]);
 901         }
 902         for (i = 0; i < adapter->num_rx_queues; i++) {
 903                 adapter->rx_ring[i]->cpu = -1;
 904                 ixgbe_update_rx_dca(adapter, adapter->rx_ring[i]);
 905         }
 906 }
 907
 908 static int __ixgbe_notify_dca(struct device *dev, void *data)
 909 {
 910         struct net_device *netdev = dev_get_drvdata(dev);
 911         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 912         unsigned long event = *(unsigned long *)data;
 913
 914         switch (event) {
 915         case DCA_PROVIDER_ADD:
 916                 /* if we're already enabled, don't do it again */
 917                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
 918                         break;
 919                 if (dca_add_requester(dev) == 0) {
 920                         adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
 921                         ixgbe_setup_dca(adapter);
 922                         break;
 923                 }
 924                 /* Fall Through since DCA is disabled. */
 925         case DCA_PROVIDER_REMOVE:
 926                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
 927                         dca_remove_requester(dev);
 928                         adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
 929                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
 930                 }
 931                 break;
 932         }
 933
 934         return 0;
 935 }
 936
 937 #endif /* CONFIG_IXGBE_DCA */
 938 /**
 939  * ixgbe_receive_skb - Send a completed packet up the stack
 940  * @adapter: board private structure
 941  * @skb: packet to send up
 942  * @status: hardware indication of status of receive
 943  * @rx_ring: rx descriptor ring (for a specific queue) to setup
 944  * @rx_desc: rx descriptor
 945  **/
 946 static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
 947                               struct sk_buff *skb, u8 status,
 948                               struct ixgbe_ring *ring,
 949                               union ixgbe_adv_rx_desc *rx_desc)
 950 {
 951         struct ixgbe_adapter *adapter = q_vector->adapter;
 952         struct napi_struct *napi = &q_vector->napi;
 953         bool is_vlan = (status & IXGBE_RXD_STAT_VP);
 954         u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
 955
 956         skb_record_rx_queue(skb, ring->queue_index);
 957         if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) {
 958                 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
 959                         vlan_gro_receive(napi, adapter->vlgrp, tag, skb);
 960                 else
 961                         napi_gro_receive(napi, skb);
 962         } else {
 963                 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
 964                         vlan_hwaccel_rx(skb, adapter->vlgrp, tag);
 965                 else
 966                         netif_rx(skb);
 967         }
 968 }
 969
 970 /**
 971  * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
 972  * @adapter: address of board private structure
 973  * @status_err: hardware indication of status of receive
 974  * @skb: skb currently being received and modified
 975  **/
 976 static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
 977                                      union ixgbe_adv_rx_desc *rx_desc,
 978                                      struct sk_buff *skb)
 979 {
 980         u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error);
 981
 982         skb->ip_summed = CHECKSUM_NONE;
 983
 984         /* Rx csum disabled */
 985         if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
 986                 return;
 987
 988         /* if IP and error */
 989         if ((status_err & IXGBE_RXD_STAT_IPCS) &&
 990             (status_err & IXGBE_RXDADV_ERR_IPE)) {
 991                 adapter->hw_csum_rx_error++;
 992                 return;
 993         }
 994
 995         if (!(status_err & IXGBE_RXD_STAT_L4CS))
 996                 return;
 997
 998         if (status_err & IXGBE_RXDADV_ERR_TCPE) {
 999                 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1000
1001                 /*
1002                  * 82599 errata, UDP frames with a 0 checksum can be marked as
1003                  * checksum errors.
1004                  */
1005                 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
1006                     (adapter->hw.mac.type == ixgbe_mac_82599EB))
1007                         return;
1008
1009                 adapter->hw_csum_rx_error++;
1010                 return;
1011         }
1012
1013         /* It must be a TCP or UDP packet with a valid checksum */
1014         skb->ip_summed = CHECKSUM_UNNECESSARY;
1015 }
1016
1017 static inline void ixgbe_release_rx_desc(struct ixgbe_hw *hw,
1018                                          struct ixgbe_ring *rx_ring, u32 val)
1019 {
1020         /*
1021          * Force memory writes to complete before letting h/w
1022          * know there are new descriptors to fetch.  (Only
1023          * applicable for weak-ordered memory model archs,
1024          * such as IA-64).
1025          */
1026         wmb();
1027         IXGBE_WRITE_REG(hw, IXGBE_RDT(rx_ring->reg_idx), val);
1028 }
1029
1030 /**
1031  * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
1032  * @adapter: address of board private structure
1033  **/
1034 static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
1035                                    struct ixgbe_ring *rx_ring,
1036                                    int cleaned_count)
1037 {
1038         struct pci_dev *pdev = adapter->pdev;
1039         union ixgbe_adv_rx_desc *rx_desc;
1040         struct ixgbe_rx_buffer *bi;
1041         unsigned int i;
1042
1043         i = rx_ring->next_to_use;
1044         bi = &rx_ring->rx_buffer_info[i];
1045
1046         while (cleaned_count--) {
1047                 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
1048
1049                 if (!bi->page_dma &&
1050                     (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)) {
1051                         if (!bi->page) {
1052                                 bi->page = alloc_page(GFP_ATOMIC);
1053                                 if (!bi->page) {
1054                                         adapter->alloc_rx_page_failed++;
1055                                         goto no_buffers;
1056                                 }
1057                                 bi->page_offset = 0;
1058                         } else {
1059                                 /* use a half page if we're re-using */
1060                                 bi->page_offset ^= (PAGE_SIZE / 2);
1061                         }
1062
1063                         bi->page_dma = dma_map_page(&pdev->dev, bi->page,
1064                                                     bi->page_offset,
1065                                                     (PAGE_SIZE / 2),
1066                                                     DMA_FROM_DEVICE);
1067                 }
1068
1069                 if (!bi->skb) {
1070                         struct sk_buff *skb;
1071                         /* netdev_alloc_skb reserves 32 bytes up front!! */
1072                         uint bufsz = rx_ring->rx_buf_len + SMP_CACHE_BYTES;
1073                         skb = netdev_alloc_skb(adapter->netdev, bufsz);
1074
1075                         if (!skb) {
1076                                 adapter->alloc_rx_buff_failed++;
1077                                 goto no_buffers;
1078                         }
1079
1080                         /* advance the data pointer to the next cache line */
1081                         skb_reserve(skb, (PTR_ALIGN(skb->data, SMP_CACHE_BYTES)
1082                                           - skb->data));
1083
1084                         bi->skb = skb;
1085                         bi->dma = dma_map_single(&pdev->dev, skb->data,
1086                                                  rx_ring->rx_buf_len,
1087                                                  DMA_FROM_DEVICE);
1088                 }
1089                 /* Refresh the desc even if buffer_addrs didn't change because
1090                  * each write-back erases this info. */
1091                 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
1092                         rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
1093                         rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
1094                 } else {
1095                         rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
1096                 }
1097
1098                 i++;
1099                 if (i == rx_ring->count)
1100                         i = 0;
1101                 bi = &rx_ring->rx_buffer_info[i];
1102         }
1103
1104 no_buffers:
1105         if (rx_ring->next_to_use != i) {
1106                 rx_ring->next_to_use = i;
1107                 if (i-- == 0)
1108                         i = (rx_ring->count - 1);
1109
1110                 ixgbe_release_rx_desc(&adapter->hw, rx_ring, i);
1111         }
1112 }
1113
1114 static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
1115 {
1116         return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
1117 }
1118
1119 static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
1120 {
1121         return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1122 }
1123
1124 static inline u32 ixgbe_get_rsc_count(union ixgbe_adv_rx_desc *rx_desc)
1125 {
1126         return (le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
1127                 IXGBE_RXDADV_RSCCNT_MASK) >>
1128                 IXGBE_RXDADV_RSCCNT_SHIFT;
1129 }
1130
1131 /**
1132  * ixgbe_transform_rsc_queue - change rsc queue into a full packet
1133  * @skb: pointer to the last skb in the rsc queue
1134  * @count: pointer to number of packets coalesced in this context
1135  *
1136  * This function changes a queue full of hw rsc buffers into a completed
1137  * packet.  It uses the ->prev pointers to find the first packet and then
1138  * turns it into the frag list owner.
1139  **/
1140 static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb,
1141                                                         u64 *count)
1142 {
1143         unsigned int frag_list_size = 0;
1144
1145         while (skb->prev) {
1146                 struct sk_buff *prev = skb->prev;
1147                 frag_list_size += skb->len;
1148                 skb->prev = NULL;
1149                 skb = prev;
1150                 *count += 1;
1151         }
1152
1153         skb_shinfo(skb)->frag_list = skb->next;
1154         skb->next = NULL;
1155         skb->len += frag_list_size;
1156         skb->data_len += frag_list_size;
1157         skb->truesize += frag_list_size;
1158         return skb;
1159 }
1160
1161 struct ixgbe_rsc_cb {
1162         dma_addr_t dma;
1163         bool delay_unmap;
1164 };
1165
1166 #define IXGBE_RSC_CB(skb) ((struct ixgbe_rsc_cb *)(skb)->cb)
1167
1168 static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
1169                                struct ixgbe_ring *rx_ring,
1170                                int *work_done, int work_to_do)
1171 {
1172         struct ixgbe_adapter *adapter = q_vector->adapter;
1173         struct net_device *netdev = adapter->netdev;
1174         struct pci_dev *pdev = adapter->pdev;
1175         union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
1176         struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
1177         struct sk_buff *skb;
1178         unsigned int i, rsc_count = 0;
1179         u32 len, staterr;
1180         u16 hdr_info;
1181         bool cleaned = false;
1182         int cleaned_count = 0;
1183         unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1184 #ifdef IXGBE_FCOE
1185         int ddp_bytes = 0;
1186 #endif /* IXGBE_FCOE */
1187
1188         i = rx_ring->next_to_clean;
1189         rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
1190         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1191         rx_buffer_info = &rx_ring->rx_buffer_info[i];
1192
1193         while (staterr & IXGBE_RXD_STAT_DD) {
1194                 u32 upper_len = 0;
1195                 if (*work_done >= work_to_do)
1196                         break;
1197                 (*work_done)++;
1198
1199                 rmb(); /* read descriptor and rx_buffer_info after status DD */
1200                 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
1201                         hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
1202                         len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
1203                                IXGBE_RXDADV_HDRBUFLEN_SHIFT;
1204                         if (len > IXGBE_RX_HDR_SIZE)
1205                                 len = IXGBE_RX_HDR_SIZE;
1206                         upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1207                 } else {
1208                         len = le16_to_cpu(rx_desc->wb.upper.length);
1209                 }
1210
1211                 cleaned = true;
1212                 skb = rx_buffer_info->skb;
1213                 prefetch(skb->data);
1214                 rx_buffer_info->skb = NULL;
1215
1216                 if (rx_buffer_info->dma) {
1217                         if ((adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
1218                             (!(staterr & IXGBE_RXD_STAT_EOP)) &&
1219                                  (!(skb->prev))) {
1220                                 /*
1221                                  * When HWRSC is enabled, delay unmapping
1222                                  * of the first packet. It carries the
1223                                  * header information, HW may still
1224                                  * access the header after the writeback.
1225                                  * Only unmap it when EOP is reached
1226                                  */
1227                                 IXGBE_RSC_CB(skb)->delay_unmap = true;
1228                                 IXGBE_RSC_CB(skb)->dma = rx_buffer_info->dma;
1229                         } else {
1230                                 dma_unmap_single(&pdev->dev,
1231                                                  rx_buffer_info->dma,
1232                                                  rx_ring->rx_buf_len,
1233                                                  DMA_FROM_DEVICE);
1234                         }
1235                         rx_buffer_info->dma = 0;
1236                         skb_put(skb, len);
1237                 }
1238
1239                 if (upper_len) {
1240                         dma_unmap_page(&pdev->dev, rx_buffer_info->page_dma,
1241                                        PAGE_SIZE / 2, DMA_FROM_DEVICE);
1242                         rx_buffer_info->page_dma = 0;
1243                         skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
1244                                            rx_buffer_info->page,
1245                                            rx_buffer_info->page_offset,
1246                                            upper_len);
1247
1248                         if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
1249                             (page_count(rx_buffer_info->page) != 1))
1250                                 rx_buffer_info->page = NULL;
1251                         else
1252                                 get_page(rx_buffer_info->page);
1253
1254                         skb->len += upper_len;
1255                         skb->data_len += upper_len;
1256                         skb->truesize += upper_len;
1257                 }
1258
1259                 i++;
1260                 if (i == rx_ring->count)
1261                         i = 0;
1262
1263                 next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i);
1264                 prefetch(next_rxd);
1265                 cleaned_count++;
1266
1267                 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
1268                         rsc_count = ixgbe_get_rsc_count(rx_desc);
1269
1270                 if (rsc_count) {
1271                         u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
1272                                      IXGBE_RXDADV_NEXTP_SHIFT;
1273                         next_buffer = &rx_ring->rx_buffer_info[nextp];
1274                 } else {
1275                         next_buffer = &rx_ring->rx_buffer_info[i];
1276                 }
1277
1278                 if (staterr & IXGBE_RXD_STAT_EOP) {
1279                         if (skb->prev)
1280                                 skb = ixgbe_transform_rsc_queue(skb, &(rx_ring->rsc_count));
1281                         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
1282                                 if (IXGBE_RSC_CB(skb)->delay_unmap) {
1283                                         dma_unmap_single(&pdev->dev,
1284                                                          IXGBE_RSC_CB(skb)->dma,
1285                                                          rx_ring->rx_buf_len,
1286                                                          DMA_FROM_DEVICE);
1287                                         IXGBE_RSC_CB(skb)->dma = 0;
1288                                         IXGBE_RSC_CB(skb)->delay_unmap = false;
1289                                 }
1290                                 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)
1291                                         rx_ring->rsc_count += skb_shinfo(skb)->nr_frags;
1292                                 else
1293                                         rx_ring->rsc_count++;
1294                                 rx_ring->rsc_flush++;
1295                         }
1296                         rx_ring->stats.packets++;
1297                         rx_ring->stats.bytes += skb->len;
1298                 } else {
1299                         if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
1300                                 rx_buffer_info->skb = next_buffer->skb;
1301                                 rx_buffer_info->dma = next_buffer->dma;
1302                                 next_buffer->skb = skb;
1303                                 next_buffer->dma = 0;
1304                         } else {
1305                                 skb->next = next_buffer->skb;
1306                                 skb->next->prev = skb;
1307                         }
1308                         rx_ring->non_eop_descs++;
1309                         goto next_desc;
1310                 }
1311
1312                 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
1313                         dev_kfree_skb_irq(skb);
1314                         goto next_desc;
1315                 }
1316
1317                 ixgbe_rx_checksum(adapter, rx_desc, skb);
1318
1319                 /* probably a little skewed due to removing CRC */
1320                 total_rx_bytes += skb->len;
1321                 total_rx_packets++;
1322
1323                 skb->protocol = eth_type_trans(skb, adapter->netdev);
1324 #ifdef IXGBE_FCOE
1325                 /* if ddp, not passing to ULD unless for FCP_RSP or error */
1326                 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
1327                         ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
1328                         if (!ddp_bytes)
1329                                 goto next_desc;
1330                 }
1331 #endif /* IXGBE_FCOE */
1332                 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
1333
1334 next_desc:
1335                 rx_desc->wb.upper.status_error = 0;
1336
1337                 /* return some buffers to hardware, one at a time is too slow */
1338                 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
1339                         ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
1340                         cleaned_count = 0;
1341                 }
1342
1343                 /* use prefetched values */
1344                 rx_desc = next_rxd;
1345                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
1346
1347                 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1348         }
1349
1350         rx_ring->next_to_clean = i;
1351         cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
1352
1353         if (cleaned_count)
1354                 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
1355
1356 #ifdef IXGBE_FCOE
1357         /* include DDPed FCoE data */
1358         if (ddp_bytes > 0) {
1359                 unsigned int mss;
1360
1361                 mss = adapter->netdev->mtu - sizeof(struct fcoe_hdr) -
1362                         sizeof(struct fc_frame_header) -
1363                         sizeof(struct fcoe_crc_eof);
1364                 if (mss > 512)
1365                         mss &= ~511;
1366                 total_rx_bytes += ddp_bytes;
1367                 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1368         }
1369 #endif /* IXGBE_FCOE */
1370
1371         rx_ring->total_packets += total_rx_packets;
1372         rx_ring->total_bytes += total_rx_bytes;
1373         netdev->stats.rx_bytes += total_rx_bytes;
1374         netdev->stats.rx_packets += total_rx_packets;
1375
1376         return cleaned;
1377 }
1378
1379 static int ixgbe_clean_rxonly(struct napi_struct *, int);
1380 /**
1381  * ixgbe_configure_msix - Configure MSI-X hardware
1382  * @adapter: board private structure
1383  *
1384  * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1385  * interrupts.
1386  **/
1387 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1388 {
1389         struct ixgbe_q_vector *q_vector;
1390         int i, j, q_vectors, v_idx, r_idx;
1391         u32 mask;
1392
1393         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1394
1395         /*
1396          * Populate the IVAR table and set the ITR values to the
1397          * corresponding register.
1398          */
1399         for (v_idx = 0; v_idx < q_vectors; v_idx++) {
1400                 q_vector = adapter->q_vector[v_idx];
1401                 /* XXX for_each_set_bit(...) */
1402                 r_idx = find_first_bit(q_vector->rxr_idx,
1403                                        adapter->num_rx_queues);
1404
1405                 for (i = 0; i < q_vector->rxr_count; i++) {
1406                         j = adapter->rx_ring[r_idx]->reg_idx;
1407                         ixgbe_set_ivar(adapter, 0, j, v_idx);
1408                         r_idx = find_next_bit(q_vector->rxr_idx,
1409                                               adapter->num_rx_queues,
1410                                               r_idx + 1);
1411                 }
1412                 r_idx = find_first_bit(q_vector->txr_idx,
1413                                        adapter->num_tx_queues);
1414
1415                 for (i = 0; i < q_vector->txr_count; i++) {
1416                         j = adapter->tx_ring[r_idx]->reg_idx;
1417                         ixgbe_set_ivar(adapter, 1, j, v_idx);
1418                         r_idx = find_next_bit(q_vector->txr_idx,
1419                                               adapter->num_tx_queues,
1420                                               r_idx + 1);
1421                 }
1422
1423                 if (q_vector->txr_count && !q_vector->rxr_count)
1424                         /* tx only */
1425                         q_vector->eitr = adapter->tx_eitr_param;
1426                 else if (q_vector->rxr_count)
1427                         /* rx or mixed */
1428                         q_vector->eitr = adapter->rx_eitr_param;
1429
1430                 ixgbe_write_eitr(q_vector);
1431         }
1432
1433         if (adapter->hw.mac.type == ixgbe_mac_82598EB)
1434                 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
1435                                v_idx);
1436         else if (adapter->hw.mac.type == ixgbe_mac_82599EB)
1437                 ixgbe_set_ivar(adapter, -1, 1, v_idx);
1438         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1439
1440         /* set up to autoclear timer, and the vectors */
1441         mask = IXGBE_EIMS_ENABLE_MASK;
1442         if (adapter->num_vfs)
1443                 mask &= ~(IXGBE_EIMS_OTHER |
1444                           IXGBE_EIMS_MAILBOX |
1445                           IXGBE_EIMS_LSC);
1446         else
1447                 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
1448         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
1449 }
1450
1451 enum latency_range {
1452         lowest_latency = 0,
1453         low_latency = 1,
1454         bulk_latency = 2,
1455         latency_invalid = 255
1456 };
1457
1458 /**
1459  * ixgbe_update_itr - update the dynamic ITR value based on statistics
1460  * @adapter: pointer to adapter
1461  * @eitr: eitr setting (ints per sec) to give last timeslice
1462  * @itr_setting: current throttle rate in ints/second
1463  * @packets: the number of packets during this measurement interval
1464  * @bytes: the number of bytes during this measurement interval
1465  *
1466  *      Stores a new ITR value based on packets and byte
1467  *      counts during the last interrupt.  The advantage of per interrupt
1468  *      computation is faster updates and more accurate ITR for the current
1469  *      traffic pattern.  Constants in this function were computed
1470  *      based on theoretical maximum wire speed and thresholds were set based
1471  *      on testing data as well as attempting to minimize response time
1472  *      while increasing bulk throughput.
1473  *      this functionality is controlled by the InterruptThrottleRate module
1474  *      parameter (see ixgbe_param.c)
1475  **/
1476 static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
1477                            u32 eitr, u8 itr_setting,
1478                            int packets, int bytes)
1479 {
1480         unsigned int retval = itr_setting;
1481         u32 timepassed_us;
1482         u64 bytes_perint;
1483
1484         if (packets == 0)
1485                 goto update_itr_done;
1486
1487
1488         /* simple throttlerate management
1489          *    0-20MB/s lowest (100000 ints/s)
1490          *   20-100MB/s low   (20000 ints/s)
1491          *  100-1249MB/s bulk (8000 ints/s)
1492          */
1493         /* what was last interrupt timeslice? */
1494         timepassed_us = 1000000/eitr;
1495         bytes_perint = bytes / timepassed_us; /* bytes/usec */
1496
1497         switch (itr_setting) {
1498         case lowest_latency:
1499                 if (bytes_perint > adapter->eitr_low)
1500                         retval = low_latency;
1501                 break;
1502         case low_latency:
1503                 if (bytes_perint > adapter->eitr_high)
1504                         retval = bulk_latency;
1505                 else if (bytes_perint <= adapter->eitr_low)
1506                         retval = lowest_latency;
1507                 break;
1508         case bulk_latency:
1509                 if (bytes_perint <= adapter->eitr_high)
1510                         retval = low_latency;
1511                 break;
1512         }
1513
1514 update_itr_done:
1515         return retval;
1516 }
1517
1518 /**
1519  * ixgbe_write_eitr - write EITR register in hardware specific way
1520  * @q_vector: structure containing interrupt and ring information
1521  *
1522  * This function is made to be called by ethtool and by the driver
1523  * when it needs to update EITR registers at runtime.  Hardware
1524  * specific quirks/differences are taken care of here.
1525  */
1526 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
1527 {
1528         struct ixgbe_adapter *adapter = q_vector->adapter;
1529         struct ixgbe_hw *hw = &adapter->hw;
1530         int v_idx = q_vector->v_idx;
1531         u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1532
1533         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1534                 /* must write high and low 16 bits to reset counter */
1535                 itr_reg |= (itr_reg << 16);
1536         } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1537                 /*
1538                  * 82599 can support a value of zero, so allow it for
1539                  * max interrupt rate, but there is an errata where it can
1540                  * not be zero with RSC
1541                  */
1542                 if (itr_reg == 8 &&
1543                     !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
1544                         itr_reg = 0;
1545
1546                 /*
1547                  * set the WDIS bit to not clear the timer bits and cause an
1548                  * immediate assertion of the interrupt
1549                  */
1550                 itr_reg |= IXGBE_EITR_CNT_WDIS;
1551         }
1552         IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1553 }
1554
1555 static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
1556 {
1557         struct ixgbe_adapter *adapter = q_vector->adapter;
1558         u32 new_itr;
1559         u8 current_itr, ret_itr;
1560         int i, r_idx;
1561         struct ixgbe_ring *rx_ring, *tx_ring;
1562
1563         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1564         for (i = 0; i < q_vector->txr_count; i++) {
1565                 tx_ring = adapter->tx_ring[r_idx];
1566                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1567                                            q_vector->tx_itr,
1568                                            tx_ring->total_packets,
1569                                            tx_ring->total_bytes);
1570                 /* if the result for this queue would decrease interrupt
1571                  * rate for this vector then use that result */
1572                 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
1573                                     q_vector->tx_itr - 1 : ret_itr);
1574                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1575                                       r_idx + 1);
1576         }
1577
1578         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1579         for (i = 0; i < q_vector->rxr_count; i++) {
1580                 rx_ring = adapter->rx_ring[r_idx];
1581                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1582                                            q_vector->rx_itr,
1583                                            rx_ring->total_packets,
1584                                            rx_ring->total_bytes);
1585                 /* if the result for this queue would decrease interrupt
1586                  * rate for this vector then use that result */
1587                 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
1588                                     q_vector->rx_itr - 1 : ret_itr);
1589                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1590                                       r_idx + 1);
1591         }
1592
1593         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1594
1595         switch (current_itr) {
1596         /* counts and packets in update_itr are dependent on these numbers */
1597         case lowest_latency:
1598                 new_itr = 100000;
1599                 break;
1600         case low_latency:
1601                 new_itr = 20000; /* aka hwitr = ~200 */
1602                 break;
1603         case bulk_latency:
1604         default:
1605                 new_itr = 8000;
1606                 break;
1607         }
1608
1609         if (new_itr != q_vector->eitr) {
1610                 /* do an exponential smoothing */
1611                 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1612
1613                 /* save the algorithm value here, not the smoothed one */
1614                 q_vector->eitr = new_itr;
1615
1616                 ixgbe_write_eitr(q_vector);
1617         }
1618
1619         return;
1620 }
1621
1622 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1623 {
1624         struct ixgbe_hw *hw = &adapter->hw;
1625
1626         if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1627             (eicr & IXGBE_EICR_GPI_SDP1)) {
1628                 DPRINTK(PROBE, CRIT, "Fan has stopped, replace the adapter\n");
1629                 /* write to clear the interrupt */
1630                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1631         }
1632 }
1633
1634 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1635 {
1636         struct ixgbe_hw *hw = &adapter->hw;
1637
1638         if (eicr & IXGBE_EICR_GPI_SDP1) {
1639                 /* Clear the interrupt */
1640                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1641                 schedule_work(&adapter->multispeed_fiber_task);
1642         } else if (eicr & IXGBE_EICR_GPI_SDP2) {
1643                 /* Clear the interrupt */
1644                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1645                 schedule_work(&adapter->sfp_config_module_task);
1646         } else {
1647                 /* Interrupt isn't for us... */
1648                 return;
1649         }
1650 }
1651
1652 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1653 {
1654         struct ixgbe_hw *hw = &adapter->hw;
1655
1656         adapter->lsc_int++;
1657         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1658         adapter->link_check_timeout = jiffies;
1659         if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1660                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1661                 IXGBE_WRITE_FLUSH(hw);
1662                 schedule_work(&adapter->watchdog_task);
1663         }
1664 }
1665
1666 static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1667 {
1668         struct net_device *netdev = data;
1669         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1670         struct ixgbe_hw *hw = &adapter->hw;
1671         u32 eicr;
1672
1673         /*
1674          * Workaround for Silicon errata.  Use clear-by-write instead
1675          * of clear-by-read.  Reading with EICS will return the
1676          * interrupt causes without clearing, which later be done
1677          * with the write to EICR.
1678          */
1679         eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1680         IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
1681
1682         if (eicr & IXGBE_EICR_LSC)
1683                 ixgbe_check_lsc(adapter);
1684
1685         if (eicr & IXGBE_EICR_MAILBOX)
1686                 ixgbe_msg_task(adapter);
1687
1688         if (hw->mac.type == ixgbe_mac_82598EB)
1689                 ixgbe_check_fan_failure(adapter, eicr);
1690
1691         if (hw->mac.type == ixgbe_mac_82599EB) {
1692                 ixgbe_check_sfp_event(adapter, eicr);
1693
1694                 /* Handle Flow Director Full threshold interrupt */
1695                 if (eicr & IXGBE_EICR_FLOW_DIR) {
1696                         int i;
1697                         IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR);
1698                         /* Disable transmits before FDIR Re-initialization */
1699                         netif_tx_stop_all_queues(netdev);
1700                         for (i = 0; i < adapter->num_tx_queues; i++) {
1701                                 struct ixgbe_ring *tx_ring =
1702                                                             adapter->tx_ring[i];
1703                                 if (test_and_clear_bit(__IXGBE_FDIR_INIT_DONE,
1704                                                        &tx_ring->reinit_state))
1705                                         schedule_work(&adapter->fdir_reinit_task);
1706                         }
1707                 }
1708         }
1709         if (!test_bit(__IXGBE_DOWN, &adapter->state))
1710                 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
1711
1712         return IRQ_HANDLED;
1713 }
1714
1715 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1716                                            u64 qmask)
1717 {
1718         u32 mask;
1719
1720         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1721                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1722                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1723         } else {
1724                 mask = (qmask & 0xFFFFFFFF);
1725                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(0), mask);
1726                 mask = (qmask >> 32);
1727                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1), mask);
1728         }
1729         /* skip the flush */
1730 }
1731
1732 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
1733                                             u64 qmask)
1734 {
1735         u32 mask;
1736
1737         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1738                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1739                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, mask);
1740         } else {
1741                 mask = (qmask & 0xFFFFFFFF);
1742                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), mask);
1743                 mask = (qmask >> 32);
1744                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), mask);
1745         }
1746         /* skip the flush */
1747 }
1748
1749 static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1750 {
1751         struct ixgbe_q_vector *q_vector = data;
1752         struct ixgbe_adapter  *adapter = q_vector->adapter;
1753         struct ixgbe_ring     *tx_ring;
1754         int i, r_idx;
1755
1756         if (!q_vector->txr_count)
1757                 return IRQ_HANDLED;
1758
1759         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1760         for (i = 0; i < q_vector->txr_count; i++) {
1761                 tx_ring = adapter->tx_ring[r_idx];
1762                 tx_ring->total_bytes = 0;
1763                 tx_ring->total_packets = 0;
1764                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1765                                       r_idx + 1);
1766         }
1767
1768         /* EIAM disabled interrupts (on this vector) for us */
1769         napi_schedule(&q_vector->napi);
1770
1771         return IRQ_HANDLED;
1772 }
1773
1774 /**
1775  * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1776  * @irq: unused
1777  * @data: pointer to our q_vector struct for this interrupt vector
1778  **/
1779 static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
1780 {
1781         struct ixgbe_q_vector *q_vector = data;
1782         struct ixgbe_adapter  *adapter = q_vector->adapter;
1783         struct ixgbe_ring  *rx_ring;
1784         int r_idx;
1785         int i;
1786
1787         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1788         for (i = 0;  i < q_vector->rxr_count; i++) {
1789                 rx_ring = adapter->rx_ring[r_idx];
1790                 rx_ring->total_bytes = 0;
1791                 rx_ring->total_packets = 0;
1792                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1793                                       r_idx + 1);
1794         }
1795
1796         if (!q_vector->rxr_count)
1797                 return IRQ_HANDLED;
1798
1799         /* disable interrupts on this vector only */
1800         /* EIAM disabled interrupts (on this vector) for us */
1801         napi_schedule(&q_vector->napi);
1802
1803         return IRQ_HANDLED;
1804 }
1805
1806 static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1807 {
1808         struct ixgbe_q_vector *q_vector = data;
1809         struct ixgbe_adapter  *adapter = q_vector->adapter;
1810         struct ixgbe_ring  *ring;
1811         int r_idx;
1812         int i;
1813
1814         if (!q_vector->txr_count && !q_vector->rxr_count)
1815                 return IRQ_HANDLED;
1816
1817         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1818         for (i = 0; i < q_vector->txr_count; i++) {
1819                 ring = adapter->tx_ring[r_idx];
1820                 ring->total_bytes = 0;
1821                 ring->total_packets = 0;
1822                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1823                                       r_idx + 1);
1824         }
1825
1826         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1827         for (i = 0; i < q_vector->rxr_count; i++) {
1828                 ring = adapter->rx_ring[r_idx];
1829                 ring->total_bytes = 0;
1830                 ring->total_packets = 0;
1831                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1832                                       r_idx + 1);
1833         }
1834
1835         /* EIAM disabled interrupts (on this vector) for us */
1836         napi_schedule(&q_vector->napi);
1837
1838         return IRQ_HANDLED;
1839 }
1840
1841 /**
1842  * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1843  * @napi: napi struct with our devices info in it
1844  * @budget: amount of work driver is allowed to do this pass, in packets
1845  *
1846  * This function is optimized for cleaning one queue only on a single
1847  * q_vector!!!
1848  **/
1849 static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1850 {
1851         struct ixgbe_q_vector *q_vector =
1852                                container_of(napi, struct ixgbe_q_vector, napi);
1853         struct ixgbe_adapter *adapter = q_vector->adapter;
1854         struct ixgbe_ring *rx_ring = NULL;
1855         int work_done = 0;
1856         long r_idx;
1857
1858         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1859         rx_ring = adapter->rx_ring[r_idx];
1860 #ifdef CONFIG_IXGBE_DCA
1861         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1862                 ixgbe_update_rx_dca(adapter, rx_ring);
1863 #endif
1864
1865         ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
1866
1867         /* If all Rx work done, exit the polling mode */
1868         if (work_done < budget) {
1869                 napi_complete(napi);
1870                 if (adapter->rx_itr_setting & 1)
1871                         ixgbe_set_itr_msix(q_vector);
1872                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1873                         ixgbe_irq_enable_queues(adapter,
1874                                                 ((u64)1 << q_vector->v_idx));
1875         }
1876
1877         return work_done;
1878 }
1879
1880 /**
1881  * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
1882  * @napi: napi struct with our devices info in it
1883  * @budget: amount of work driver is allowed to do this pass, in packets
1884  *
1885  * This function will clean more than one rx queue associated with a
1886  * q_vector.
1887  **/
1888 static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
1889 {
1890         struct ixgbe_q_vector *q_vector =
1891                                container_of(napi, struct ixgbe_q_vector, napi);
1892         struct ixgbe_adapter *adapter = q_vector->adapter;
1893         struct ixgbe_ring *ring = NULL;
1894         int work_done = 0, i;
1895         long r_idx;
1896         bool tx_clean_complete = true;
1897
1898         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1899         for (i = 0; i < q_vector->txr_count; i++) {
1900                 ring = adapter->tx_ring[r_idx];
1901 #ifdef CONFIG_IXGBE_DCA
1902                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1903                         ixgbe_update_tx_dca(adapter, ring);
1904 #endif
1905                 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
1906                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1907                                       r_idx + 1);
1908         }
1909
1910         /* attempt to distribute budget to each queue fairly, but don't allow
1911          * the budget to go below 1 because we'll exit polling */
1912         budget /= (q_vector->rxr_count ?: 1);
1913         budget = max(budget, 1);
1914         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1915         for (i = 0; i < q_vector->rxr_count; i++) {
1916                 ring = adapter->rx_ring[r_idx];
1917 #ifdef CONFIG_IXGBE_DCA
1918                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1919                         ixgbe_update_rx_dca(adapter, ring);
1920 #endif
1921                 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
1922                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1923                                       r_idx + 1);
1924         }
1925
1926         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1927         ring = adapter->rx_ring[r_idx];
1928         /* If all Rx work done, exit the polling mode */
1929         if (work_done < budget) {
1930                 napi_complete(napi);
1931                 if (adapter->rx_itr_setting & 1)
1932                         ixgbe_set_itr_msix(q_vector);
1933                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1934                         ixgbe_irq_enable_queues(adapter,
1935                                                 ((u64)1 << q_vector->v_idx));
1936                 return 0;
1937         }
1938
1939         return work_done;
1940 }
1941
1942 /**
1943  * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
1944  * @napi: napi struct with our devices info in it
1945  * @budget: amount of work driver is allowed to do this pass, in packets
1946  *
1947  * This function is optimized for cleaning one queue only on a single
1948  * q_vector!!!
1949  **/
1950 static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
1951 {
1952         struct ixgbe_q_vector *q_vector =
1953                                container_of(napi, struct ixgbe_q_vector, napi);
1954         struct ixgbe_adapter *adapter = q_vector->adapter;
1955         struct ixgbe_ring *tx_ring = NULL;
1956         int work_done = 0;
1957         long r_idx;
1958
1959         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1960         tx_ring = adapter->tx_ring[r_idx];
1961 #ifdef CONFIG_IXGBE_DCA
1962         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1963                 ixgbe_update_tx_dca(adapter, tx_ring);
1964 #endif
1965
1966         if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
1967                 work_done = budget;
1968
1969         /* If all Tx work done, exit the polling mode */
1970         if (work_done < budget) {
1971                 napi_complete(napi);
1972                 if (adapter->tx_itr_setting & 1)
1973                         ixgbe_set_itr_msix(q_vector);
1974                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1975                         ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
1976         }
1977
1978         return work_done;
1979 }
1980
1981 static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
1982                                      int r_idx)
1983 {
1984         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1985
1986         set_bit(r_idx, q_vector->rxr_idx);
1987         q_vector->rxr_count++;
1988 }
1989
1990 static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
1991                                      int t_idx)
1992 {
1993         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1994
1995         set_bit(t_idx, q_vector->txr_idx);
1996         q_vector->txr_count++;
1997 }
1998
1999 /**
2000  * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
2001  * @adapter: board private structure to initialize
2002  * @vectors: allotted vector count for descriptor rings
2003  *
2004  * This function maps descriptor rings to the queue-specific vectors
2005  * we were allotted through the MSI-X enabling code.  Ideally, we'd have
2006  * one vector per ring/queue, but on a constrained vector budget, we
2007  * group the rings as "efficiently" as possible.  You would add new
2008  * mapping configurations in here.
2009  **/
2010 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
2011                                       int vectors)
2012 {
2013         int v_start = 0;
2014         int rxr_idx = 0, txr_idx = 0;
2015         int rxr_remaining = adapter->num_rx_queues;
2016         int txr_remaining = adapter->num_tx_queues;
2017         int i, j;
2018         int rqpv, tqpv;
2019         int err = 0;
2020
2021         /* No mapping required if MSI-X is disabled. */
2022         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2023                 goto out;
2024
2025         /*
2026          * The ideal configuration...
2027          * We have enough vectors to map one per queue.
2028          */
2029         if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
2030                 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
2031                         map_vector_to_rxq(adapter, v_start, rxr_idx);
2032
2033                 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
2034                         map_vector_to_txq(adapter, v_start, txr_idx);
2035
2036                 goto out;
2037         }
2038
2039         /*
2040          * If we don't have enough vectors for a 1-to-1
2041          * mapping, we'll have to group them so there are
2042          * multiple queues per vector.
2043          */
2044         /* Re-adjusting *qpv takes care of the remainder. */
2045         for (i = v_start; i < vectors; i++) {
2046                 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
2047                 for (j = 0; j < rqpv; j++) {
2048                         map_vector_to_rxq(adapter, i, rxr_idx);
2049                         rxr_idx++;
2050                         rxr_remaining--;
2051                 }
2052         }
2053         for (i = v_start; i < vectors; i++) {
2054                 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
2055                 for (j = 0; j < tqpv; j++) {
2056                         map_vector_to_txq(adapter, i, txr_idx);
2057                         txr_idx++;
2058                         txr_remaining--;
2059                 }
2060         }
2061
2062 out:
2063         return err;
2064 }
2065
2066 /**
2067  * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2068  * @adapter: board private structure
2069  *
2070  * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2071  * interrupts from the kernel.
2072  **/
2073 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2074 {
2075         struct net_device *netdev = adapter->netdev;
2076         irqreturn_t (*handler)(int, void *);
2077         int i, vector, q_vectors, err;
2078         int ri=0, ti=0;
2079
2080         /* Decrement for Other and TCP Timer vectors */
2081         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2082
2083         /* Map the Tx/Rx rings to the vectors we were allotted. */
2084         err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
2085         if (err)
2086                 goto out;
2087
2088 #define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
2089                          (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
2090                          &ixgbe_msix_clean_many)
2091         for (vector = 0; vector < q_vectors; vector++) {
2092                 handler = SET_HANDLER(adapter->q_vector[vector]);
2093
2094                 if(handler == &ixgbe_msix_clean_rx) {
2095                         sprintf(adapter->name[vector], "%s-%s-%d",
2096                                 netdev->name, "rx", ri++);
2097                 }
2098                 else if(handler == &ixgbe_msix_clean_tx) {
2099                         sprintf(adapter->name[vector], "%s-%s-%d",
2100                                 netdev->name, "tx", ti++);
2101                 }
2102                 else
2103                         sprintf(adapter->name[vector], "%s-%s-%d",
2104                                 netdev->name, "TxRx", vector);
2105
2106                 err = request_irq(adapter->msix_entries[vector].vector,
2107                                   handler, 0, adapter->name[vector],
2108                                   adapter->q_vector[vector]);
2109                 if (err) {
2110                         DPRINTK(PROBE, ERR,
2111                                 "request_irq failed for MSIX interrupt "
2112                                 "Error: %d\n", err);
2113                         goto free_queue_irqs;
2114                 }
2115         }
2116
2117         sprintf(adapter->name[vector], "%s:lsc", netdev->name);
2118         err = request_irq(adapter->msix_entries[vector].vector,
2119                           ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
2120         if (err) {
2121                 DPRINTK(PROBE, ERR,
2122                         "request_irq for msix_lsc failed: %d\n", err);
2123                 goto free_queue_irqs;
2124         }
2125
2126         return 0;
2127
2128 free_queue_irqs:
2129         for (i = vector - 1; i >= 0; i--)
2130                 free_irq(adapter->msix_entries[--vector].vector,
2131                          adapter->q_vector[i]);
2132         adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2133         pci_disable_msix(adapter->pdev);
2134         kfree(adapter->msix_entries);
2135         adapter->msix_entries = NULL;
2136 out:
2137         return err;
2138 }
2139
2140 static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
2141 {
2142         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2143         u8 current_itr;
2144         u32 new_itr = q_vector->eitr;
2145         struct ixgbe_ring *rx_ring = adapter->rx_ring[0];
2146         struct ixgbe_ring *tx_ring = adapter->tx_ring[0];
2147
2148         q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
2149                                             q_vector->tx_itr,
2150                                             tx_ring->total_packets,
2151                                             tx_ring->total_bytes);
2152         q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
2153                                             q_vector->rx_itr,
2154                                             rx_ring->total_packets,
2155                                             rx_ring->total_bytes);
2156
2157         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
2158
2159         switch (current_itr) {
2160         /* counts and packets in update_itr are dependent on these numbers */
2161         case lowest_latency:
2162                 new_itr = 100000;
2163                 break;
2164         case low_latency:
2165                 new_itr = 20000; /* aka hwitr = ~200 */
2166                 break;
2167         case bulk_latency:
2168                 new_itr = 8000;
2169                 break;
2170         default:
2171                 break;
2172         }
2173
2174         if (new_itr != q_vector->eitr) {
2175                 /* do an exponential smoothing */
2176                 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
2177
2178                 /* save the algorithm value here, not the smoothed one */
2179                 q_vector->eitr = new_itr;
2180
2181                 ixgbe_write_eitr(q_vector);
2182         }
2183
2184         return;
2185 }
2186
2187 /**
2188  * ixgbe_irq_enable - Enable default interrupt generation settings
2189  * @adapter: board private structure
2190  **/
2191 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter)
2192 {
2193         u32 mask;
2194
2195         mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
2196         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2197                 mask |= IXGBE_EIMS_GPI_SDP1;
2198         if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2199                 mask |= IXGBE_EIMS_ECC;
2200                 mask |= IXGBE_EIMS_GPI_SDP1;
2201                 mask |= IXGBE_EIMS_GPI_SDP2;
2202                 if (adapter->num_vfs)
2203                         mask |= IXGBE_EIMS_MAILBOX;
2204         }
2205         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
2206             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
2207                 mask |= IXGBE_EIMS_FLOW_DIR;
2208
2209         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2210         ixgbe_irq_enable_queues(adapter, ~0);
2211         IXGBE_WRITE_FLUSH(&adapter->hw);
2212
2213         if (adapter->num_vfs > 32) {
2214                 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2215                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2216         }
2217 }
2218
2219 /**
2220  * ixgbe_intr - legacy mode Interrupt Handler
2221  * @irq: interrupt number
2222  * @data: pointer to a network interface device structure
2223  **/
2224 static irqreturn_t ixgbe_intr(int irq, void *data)
2225 {
2226         struct net_device *netdev = data;
2227         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2228         struct ixgbe_hw *hw = &adapter->hw;
2229         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2230         u32 eicr;
2231
2232         /*
2233          * Workaround for silicon errata.  Mask the interrupts
2234          * before the read of EICR.
2235          */
2236         IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2237
2238         /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2239          * therefore no explict interrupt disable is necessary */
2240         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2241         if (!eicr) {
2242                 /* shared interrupt alert!
2243                  * make sure interrupts are enabled because the read will
2244                  * have disabled interrupts due to EIAM */
2245                 ixgbe_irq_enable(adapter);
2246                 return IRQ_NONE;        /* Not our interrupt */
2247         }
2248
2249         if (eicr & IXGBE_EICR_LSC)
2250                 ixgbe_check_lsc(adapter);
2251
2252         if (hw->mac.type == ixgbe_mac_82599EB)
2253                 ixgbe_check_sfp_event(adapter, eicr);
2254
2255         ixgbe_check_fan_failure(adapter, eicr);
2256
2257         if (napi_schedule_prep(&(q_vector->napi))) {
2258                 adapter->tx_ring[0]->total_packets = 0;
2259                 adapter->tx_ring[0]->total_bytes = 0;
2260                 adapter->rx_ring[0]->total_packets = 0;
2261                 adapter->rx_ring[0]->total_bytes = 0;
2262                 /* would disable interrupts here but EIAM disabled it */
2263                 __napi_schedule(&(q_vector->napi));
2264         }
2265
2266         return IRQ_HANDLED;
2267 }
2268
2269 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
2270 {
2271         int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2272
2273         for (i = 0; i < q_vectors; i++) {
2274                 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
2275                 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
2276                 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
2277                 q_vector->rxr_count = 0;
2278                 q_vector->txr_count = 0;
2279         }
2280 }
2281
2282 /**
2283  * ixgbe_request_irq - initialize interrupts
2284  * @adapter: board private structure
2285  *
2286  * Attempts to configure interrupts using the best available
2287  * capabilities of the hardware and kernel.
2288  **/
2289 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
2290 {
2291         struct net_device *netdev = adapter->netdev;
2292         int err;
2293
2294         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2295                 err = ixgbe_request_msix_irqs(adapter);
2296         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
2297                 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
2298                                   netdev->name, netdev);
2299         } else {
2300                 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
2301                                   netdev->name, netdev);
2302         }
2303
2304         if (err)
2305                 DPRINTK(PROBE, ERR, "request_irq failed, Error %d\n", err);
2306
2307         return err;
2308 }
2309
2310 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2311 {
2312         struct net_device *netdev = adapter->netdev;
2313
2314         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2315                 int i, q_vectors;
2316
2317                 q_vectors = adapter->num_msix_vectors;
2318
2319                 i = q_vectors - 1;
2320                 free_irq(adapter->msix_entries[i].vector, netdev);
2321
2322                 i--;
2323                 for (; i >= 0; i--) {
2324                         free_irq(adapter->msix_entries[i].vector,
2325                                  adapter->q_vector[i]);
2326                 }
2327
2328                 ixgbe_reset_q_vectors(adapter);
2329         } else {
2330                 free_irq(adapter->pdev->irq, netdev);
2331         }
2332 }
2333
2334 /**
2335  * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2336  * @adapter: board private structure
2337  **/
2338 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2339 {
2340         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2341                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
2342         } else {
2343                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2344                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
2345                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
2346                 if (adapter->num_vfs > 32)
2347                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
2348         }
2349         IXGBE_WRITE_FLUSH(&adapter->hw);
2350         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2351                 int i;
2352                 for (i = 0; i < adapter->num_msix_vectors; i++)
2353                         synchronize_irq(adapter->msix_entries[i].vector);
2354         } else {
2355                 synchronize_irq(adapter->pdev->irq);
2356         }
2357 }
2358
2359 /**
2360  * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2361  *
2362  **/
2363 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2364 {
2365         struct ixgbe_hw *hw = &adapter->hw;
2366
2367         IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
2368                         EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
2369
2370         ixgbe_set_ivar(adapter, 0, 0, 0);
2371         ixgbe_set_ivar(adapter, 1, 0, 0);
2372
2373         map_vector_to_rxq(adapter, 0, 0);
2374         map_vector_to_txq(adapter, 0, 0);
2375
2376         DPRINTK(HW, INFO, "Legacy interrupt IVAR setup done\n");
2377 }
2378
2379 /**
2380  * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
2381  * @adapter: board private structure
2382  *
2383  * Configure the Tx unit of the MAC after a reset.
2384  **/
2385 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2386 {
2387         u64 tdba;
2388         struct ixgbe_hw *hw = &adapter->hw;
2389         u32 i, j, tdlen, txctrl;
2390
2391         /* Setup the HW Tx Head and Tail descriptor pointers */
2392         for (i = 0; i < adapter->num_tx_queues; i++) {
2393                 struct ixgbe_ring *ring = adapter->tx_ring[i];
2394                 j = ring->reg_idx;
2395                 tdba = ring->dma;
2396                 tdlen = ring->count * sizeof(union ixgbe_adv_tx_desc);
2397                 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j),
2398                                 (tdba & DMA_BIT_MASK(32)));
2399                 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32));
2400                 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), tdlen);
2401                 IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0);
2402                 IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0);
2403                 adapter->tx_ring[i]->head = IXGBE_TDH(j);
2404                 adapter->tx_ring[i]->tail = IXGBE_TDT(j);
2405                 /*
2406                  * Disable Tx Head Writeback RO bit, since this hoses
2407                  * bookkeeping if things aren't delivered in order.
2408                  */
2409                 switch (hw->mac.type) {
2410                 case ixgbe_mac_82598EB:
2411                         txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j));
2412                         break;
2413                 case ixgbe_mac_82599EB:
2414                 default:
2415                         txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(j));
2416                         break;
2417                 }
2418                 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
2419                 switch (hw->mac.type) {
2420                 case ixgbe_mac_82598EB:
2421                         IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl);
2422                         break;
2423                 case ixgbe_mac_82599EB:
2424                 default:
2425                         IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(j), txctrl);
2426                         break;
2427                 }
2428         }
2429
2430         if (hw->mac.type == ixgbe_mac_82599EB) {
2431                 u32 rttdcs;
2432                 u32 mask;
2433
2434                 /* disable the arbiter while setting MTQC */
2435                 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2436                 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2437                 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2438
2439                 /* set transmit pool layout */
2440                 mask = (IXGBE_FLAG_SRIOV_ENABLED | IXGBE_FLAG_DCB_ENABLED);
2441                 switch (adapter->flags & mask) {
2442
2443                 case (IXGBE_FLAG_SRIOV_ENABLED):
2444                         IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2445                                         (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2446                         break;
2447
2448                 case (IXGBE_FLAG_DCB_ENABLED):
2449                         /* We enable 8 traffic classes, DCB only */
2450                         IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2451                                       (IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ));
2452                         break;
2453
2454                 default:
2455                         IXGBE_WRITE_REG(hw, IXGBE_MTQC, IXGBE_MTQC_64Q_1PB);
2456                         break;
2457                 }
2458
2459                 /* re-eable the arbiter */
2460                 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2461                 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2462         }
2463 }
2464
2465 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
2466
2467 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
2468                                    struct ixgbe_ring *rx_ring)
2469 {
2470         u32 srrctl;
2471         int index;
2472         struct ixgbe_ring_feature *feature = adapter->ring_feature;
2473
2474         index = rx_ring->reg_idx;
2475         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2476                 unsigned long mask;
2477                 mask = (unsigned long) feature[RING_F_RSS].mask;
2478                 index = index & mask;
2479         }
2480         srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
2481
2482         srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2483         srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
2484
2485         srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2486                   IXGBE_SRRCTL_BSIZEHDR_MASK;
2487
2488         if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
2489 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2490                 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2491 #else
2492                 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2493 #endif
2494                 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2495         } else {
2496                 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2497                           IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2498                 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
2499         }
2500
2501         IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
2502 }
2503
2504 static u32 ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
2505 {
2506         u32 mrqc = 0;
2507         int mask;
2508
2509         if (!(adapter->hw.mac.type == ixgbe_mac_82599EB))
2510                 return mrqc;
2511
2512         mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2513 #ifdef CONFIG_IXGBE_DCB
2514                                  | IXGBE_FLAG_DCB_ENABLED
2515 #endif
2516                                  | IXGBE_FLAG_SRIOV_ENABLED
2517                                 );
2518
2519         switch (mask) {
2520         case (IXGBE_FLAG_RSS_ENABLED):
2521                 mrqc = IXGBE_MRQC_RSSEN;
2522                 break;
2523         case (IXGBE_FLAG_SRIOV_ENABLED):
2524                 mrqc = IXGBE_MRQC_VMDQEN;
2525                 break;
2526 #ifdef CONFIG_IXGBE_DCB
2527         case (IXGBE_FLAG_DCB_ENABLED):
2528                 mrqc = IXGBE_MRQC_RT8TCEN;
2529                 break;
2530 #endif /* CONFIG_IXGBE_DCB */
2531         default:
2532                 break;
2533         }
2534
2535         return mrqc;
2536 }
2537
2538 /**
2539  * ixgbe_configure_rscctl - enable RSC for the indicated ring
2540  * @adapter:    address of board private structure
2541  * @index:      index of ring to set
2542  **/
2543 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter, int index)
2544 {
2545         struct ixgbe_ring *rx_ring;
2546         struct ixgbe_hw *hw = &adapter->hw;
2547         int j;
2548         u32 rscctrl;
2549         int rx_buf_len;
2550
2551         rx_ring = adapter->rx_ring[index];
2552         j = rx_ring->reg_idx;
2553         rx_buf_len = rx_ring->rx_buf_len;
2554         rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(j));
2555         rscctrl |= IXGBE_RSCCTL_RSCEN;
2556         /*
2557          * we must limit the number of descriptors so that the
2558          * total size of max desc * buf_len is not greater
2559          * than 65535
2560          */
2561         if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
2562 #if (MAX_SKB_FRAGS > 16)
2563                 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2564 #elif (MAX_SKB_FRAGS > 8)
2565                 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2566 #elif (MAX_SKB_FRAGS > 4)
2567                 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2568 #else
2569                 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2570 #endif
2571         } else {
2572                 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2573                         rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2574                 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2575                         rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2576                 else
2577                         rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2578         }
2579         IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(j), rscctrl);
2580 }
2581
2582 /**
2583  * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
2584  * @adapter: board private structure
2585  *
2586  * Configure the Rx unit of the MAC after a reset.
2587  **/
2588 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
2589 {
2590         u64 rdba;
2591         struct ixgbe_hw *hw = &adapter->hw;
2592         struct ixgbe_ring *rx_ring;
2593         struct net_device *netdev = adapter->netdev;
2594         int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2595         int i, j;
2596         u32 rdlen, rxctrl, rxcsum;
2597         static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2598                           0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2599                           0x6A3E67EA, 0x14364D17, 0x3BED200D};
2600         u32 fctrl, hlreg0;
2601         u32 reta = 0, mrqc = 0;
2602         u32 rdrxctl;
2603         int rx_buf_len;
2604
2605         /* Decide whether to use packet split mode or not */
2606         /* Do not use packet split if we're in SR-IOV Mode */
2607         if (!adapter->num_vfs)
2608                 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
2609
2610         /* Set the RX buffer length according to the mode */
2611         if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
2612                 rx_buf_len = IXGBE_RX_HDR_SIZE;
2613                 if (hw->mac.type == ixgbe_mac_82599EB) {
2614                         /* PSRTYPE must be initialized in 82599 */
2615                         u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
2616                                       IXGBE_PSRTYPE_UDPHDR |
2617                                       IXGBE_PSRTYPE_IPV4HDR |
2618                                       IXGBE_PSRTYPE_IPV6HDR |
2619                                       IXGBE_PSRTYPE_L2HDR;
2620                         IXGBE_WRITE_REG(hw,
2621                                         IXGBE_PSRTYPE(adapter->num_vfs),
2622                                         psrtype);
2623                 }
2624         } else {
2625                 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
2626                     (netdev->mtu <= ETH_DATA_LEN))
2627                         rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
2628                 else
2629                         rx_buf_len = ALIGN(max_frame, 1024);
2630         }
2631
2632         fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
2633         fctrl |= IXGBE_FCTRL_BAM;
2634         fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
2635         fctrl |= IXGBE_FCTRL_PMCF;
2636         IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, fctrl);
2637
2638         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2639         if (adapter->netdev->mtu <= ETH_DATA_LEN)
2640                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
2641         else
2642                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2643 #ifdef IXGBE_FCOE
2644         if (netdev->features & NETIF_F_FCOE_MTU)
2645                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2646 #endif
2647         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2648
2649         rdlen = adapter->rx_ring[0]->count * sizeof(union ixgbe_adv_rx_desc);
2650         /* disable receives while setting up the descriptors */
2651         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2652         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
2653
2654         /*
2655          * Setup the HW Rx Head and Tail Descriptor Pointers and
2656          * the Base and Length of the Rx Descriptor Ring
2657          */
2658         for (i = 0; i < adapter->num_rx_queues; i++) {
2659                 rx_ring = adapter->rx_ring[i];
2660                 rdba = rx_ring->dma;
2661                 j = rx_ring->reg_idx;
2662                 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j), (rdba & DMA_BIT_MASK(32)));
2663                 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32));
2664                 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j), rdlen);
2665                 IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0);
2666                 IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0);
2667                 rx_ring->head = IXGBE_RDH(j);
2668                 rx_ring->tail = IXGBE_RDT(j);
2669                 rx_ring->rx_buf_len = rx_buf_len;
2670
2671                 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
2672                         rx_ring->flags |= IXGBE_RING_RX_PS_ENABLED;
2673                 else
2674                         rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
2675
2676 #ifdef IXGBE_FCOE
2677                 if (netdev->features & NETIF_F_FCOE_MTU) {
2678                         struct ixgbe_ring_feature *f;
2679                         f = &adapter->ring_feature[RING_F_FCOE];
2680                         if ((i >= f->mask) && (i < f->mask + f->indices)) {
2681                                 rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
2682                                 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
2683                                         rx_ring->rx_buf_len =
2684                                                 IXGBE_FCOE_JUMBO_FRAME_SIZE;
2685                         }
2686                 }
2687
2688 #endif /* IXGBE_FCOE */
2689                 ixgbe_configure_srrctl(adapter, rx_ring);
2690         }
2691
2692         if (hw->mac.type == ixgbe_mac_82598EB) {
2693                 /*
2694                  * For VMDq support of different descriptor types or
2695                  * buffer sizes through the use of multiple SRRCTL
2696                  * registers, RDRXCTL.MVMEN must be set to 1
2697                  *
2698                  * also, the manual doesn't mention it clearly but DCA hints
2699                  * will only use queue 0's tags unless this bit is set.  Side
2700                  * effects of setting this bit are only that SRRCTL must be
2701                  * fully programmed [0..15]
2702                  */
2703                 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2704                 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
2705                 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2706         }
2707
2708         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
2709                 u32 vt_reg_bits;
2710                 u32 reg_offset, vf_shift;
2711                 u32 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2712                 vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN
2713                         | IXGBE_VT_CTL_REPLEN;
2714                 vt_reg_bits |= (adapter->num_vfs <<
2715                                 IXGBE_VT_CTL_POOL_SHIFT);
2716                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
2717                 IXGBE_WRITE_REG(hw, IXGBE_MRQC, 0);
2718
2719                 vf_shift = adapter->num_vfs % 32;
2720                 reg_offset = adapter->num_vfs / 32;
2721                 IXGBE_WRITE_REG(hw, IXGBE_VFRE(0), 0);
2722                 IXGBE_WRITE_REG(hw, IXGBE_VFRE(1), 0);
2723                 IXGBE_WRITE_REG(hw, IXGBE_VFTE(0), 0);
2724                 IXGBE_WRITE_REG(hw, IXGBE_VFTE(1), 0);
2725                 /* Enable only the PF's pool for Tx/Rx */
2726                 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
2727                 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
2728                 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
2729                 ixgbe_set_vmolr(hw, adapter->num_vfs, true);
2730         }
2731
2732         /* Program MRQC for the distribution of queues */
2733         mrqc = ixgbe_setup_mrqc(adapter);
2734
2735         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
2736                 /* Fill out redirection table */
2737                 for (i = 0, j = 0; i < 128; i++, j++) {
2738                         if (j == adapter->ring_feature[RING_F_RSS].indices)
2739                                 j = 0;
2740                         /* reta = 4-byte sliding window of
2741                          * 0x00..(indices-1)(indices-1)00..etc. */
2742                         reta = (reta << 8) | (j * 0x11);
2743                         if ((i & 3) == 3)
2744                                 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2745                 }
2746
2747                 /* Fill out hash function seeds */
2748                 for (i = 0; i < 10; i++)
2749                         IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2750
2751                 if (hw->mac.type == ixgbe_mac_82598EB)
2752                         mrqc |= IXGBE_MRQC_RSSEN;
2753                     /* Perform hash on these packet types */
2754                 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2755                       | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2756                       | IXGBE_MRQC_RSS_FIELD_IPV4_UDP
2757                       | IXGBE_MRQC_RSS_FIELD_IPV6
2758                       | IXGBE_MRQC_RSS_FIELD_IPV6_TCP
2759                       | IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
2760         }
2761         IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2762
2763         if (adapter->num_vfs) {
2764                 u32 reg;
2765
2766                 /* Map PF MAC address in RAR Entry 0 to first pool
2767                  * following VFs */
2768                 hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
2769
2770                 /* Set up VF register offsets for selected VT Mode, i.e.
2771                  * 64 VFs for SR-IOV */
2772                 reg = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
2773                 reg |= IXGBE_GCR_EXT_SRIOV;
2774                 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, reg);
2775         }
2776
2777         rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2778
2779         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED ||
2780             adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED) {
2781                 /* Disable indicating checksum in descriptor, enables
2782                  * RSS hash */
2783                 rxcsum |= IXGBE_RXCSUM_PCSD;
2784         }
2785         if (!(rxcsum & IXGBE_RXCSUM_PCSD)) {
2786                 /* Enable IPv4 payload checksum for UDP fragments
2787                  * if PCSD is not set */
2788                 rxcsum |= IXGBE_RXCSUM_IPPCSE;
2789         }
2790
2791         IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2792
2793         if (hw->mac.type == ixgbe_mac_82599EB) {
2794                 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2795                 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
2796                 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
2797                 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2798         }
2799
2800         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
2801                 /* Enable 82599 HW-RSC */
2802                 for (i = 0; i < adapter->num_rx_queues; i++)
2803                         ixgbe_configure_rscctl(adapter, i);
2804
2805                 /* Disable RSC for ACK packets */
2806                 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
2807                    (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
2808         }
2809 }
2810
2811 static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
2812 {
2813         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2814         struct ixgbe_hw *hw = &adapter->hw;
2815         int pool_ndx = adapter->num_vfs;
2816
2817         /* add VID to filter table */
2818         hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
2819 }
2820
2821 static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
2822 {
2823         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2824         struct ixgbe_hw *hw = &adapter->hw;
2825         int pool_ndx = adapter->num_vfs;
2826
2827         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2828                 ixgbe_irq_disable(adapter);
2829
2830         vlan_group_set_device(adapter->vlgrp, vid, NULL);
2831
2832         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2833                 ixgbe_irq_enable(adapter);
2834
2835         /* remove VID from filter table */
2836         hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
2837 }
2838
2839 /**
2840  * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
2841  * @adapter: driver data
2842  */
2843 static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
2844 {
2845         struct ixgbe_hw *hw = &adapter->hw;
2846         u32 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2847         int i, j;
2848
2849         switch (hw->mac.type) {
2850         case ixgbe_mac_82598EB:
2851                 vlnctrl &= ~(IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE);
2852                 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2853                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2854                 break;
2855         case ixgbe_mac_82599EB:
2856                 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
2857                 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2858                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2859                 for (i = 0; i < adapter->num_rx_queues; i++) {
2860                         j = adapter->rx_ring[i]->reg_idx;
2861                         vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2862                         vlnctrl &= ~IXGBE_RXDCTL_VME;
2863                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
2864                 }
2865                 break;
2866         default:
2867                 break;
2868         }
2869 }
2870
2871 /**
2872  * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
2873  * @adapter: driver data
2874  */
2875 static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
2876 {
2877         struct ixgbe_hw *hw = &adapter->hw;
2878         u32 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2879         int i, j;
2880
2881         switch (hw->mac.type) {
2882         case ixgbe_mac_82598EB:
2883                 vlnctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2884                 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2885                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2886                 break;
2887         case ixgbe_mac_82599EB:
2888                 vlnctrl |= IXGBE_VLNCTRL_VFE;
2889                 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2890                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2891                 for (i = 0; i < adapter->num_rx_queues; i++) {
2892                         j = adapter->rx_ring[i]->reg_idx;
2893                         vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2894                         vlnctrl |= IXGBE_RXDCTL_VME;
2895                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
2896                 }
2897                 break;
2898         default:
2899                 break;
2900         }
2901 }
2902
2903 static void ixgbe_vlan_rx_register(struct net_device *netdev,
2904                                    struct vlan_group *grp)
2905 {
2906         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2907
2908         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2909                 ixgbe_irq_disable(adapter);
2910         adapter->vlgrp = grp;
2911
2912         /*
2913          * For a DCB driver, always enable VLAN tag stripping so we can
2914          * still receive traffic from a DCB-enabled host even if we're
2915          * not in DCB mode.
2916          */
2917         ixgbe_vlan_filter_enable(adapter);
2918
2919         ixgbe_vlan_rx_add_vid(netdev, 0);
2920
2921         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2922                 ixgbe_irq_enable(adapter);
2923 }
2924
2925 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
2926 {
2927         ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp);
2928
2929         if (adapter->vlgrp) {
2930                 u16 vid;
2931                 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
2932                         if (!vlan_group_get_device(adapter->vlgrp, vid))
2933                                 continue;
2934                         ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
2935                 }
2936         }
2937 }
2938
2939 /**
2940  * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
2941  * @netdev: network interface device structure
2942  *
2943  * The set_rx_method entry point is called whenever the unicast/multicast
2944  * address list or the network interface flags are updated.  This routine is
2945  * responsible for configuring the hardware for proper unicast, multicast and
2946  * promiscuous mode.
2947  **/
2948 void ixgbe_set_rx_mode(struct net_device *netdev)
2949 {
2950         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2951         struct ixgbe_hw *hw = &adapter->hw;
2952         u32 fctrl;
2953
2954         /* Check for Promiscuous and All Multicast modes */
2955
2956         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2957
2958         if (netdev->flags & IFF_PROMISC) {
2959                 hw->addr_ctrl.user_set_promisc = true;
2960                 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2961                 /* don't hardware filter vlans in promisc mode */
2962                 ixgbe_vlan_filter_disable(adapter);
2963         } else {
2964                 if (netdev->flags & IFF_ALLMULTI) {
2965                         fctrl |= IXGBE_FCTRL_MPE;
2966                         fctrl &= ~IXGBE_FCTRL_UPE;
2967                 } else if (!hw->addr_ctrl.uc_set_promisc) {
2968                         fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2969                 }
2970                 ixgbe_vlan_filter_enable(adapter);
2971                 hw->addr_ctrl.user_set_promisc = false;
2972         }
2973
2974         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2975
2976         /* reprogram secondary unicast list */
2977         hw->mac.ops.update_uc_addr_list(hw, netdev);
2978
2979         /* reprogram multicast list */
2980         hw->mac.ops.update_mc_addr_list(hw, netdev);
2981
2982         if (adapter->num_vfs)
2983                 ixgbe_restore_vf_multicasts(adapter);
2984 }
2985
2986 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
2987 {
2988         int q_idx;
2989         struct ixgbe_q_vector *q_vector;
2990         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2991
2992         /* legacy and MSI only use one vector */
2993         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2994                 q_vectors = 1;
2995
2996         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
2997                 struct napi_struct *napi;
2998                 q_vector = adapter->q_vector[q_idx];
2999                 napi = &q_vector->napi;
3000                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3001                         if (!q_vector->rxr_count || !q_vector->txr_count) {
3002                                 if (q_vector->txr_count == 1)
3003                                         napi->poll = &ixgbe_clean_txonly;
3004                                 else if (q_vector->rxr_count == 1)
3005                                         napi->poll = &ixgbe_clean_rxonly;
3006                         }
3007                 }
3008
3009                 napi_enable(napi);
3010         }
3011 }
3012
3013 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3014 {
3015         int q_idx;
3016         struct ixgbe_q_vector *q_vector;
3017         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3018
3019         /* legacy and MSI only use one vector */
3020         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3021                 q_vectors = 1;
3022
3023         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3024                 q_vector = adapter->q_vector[q_idx];
3025                 napi_disable(&q_vector->napi);
3026         }
3027 }
3028
3029 #ifdef CONFIG_IXGBE_DCB
3030 /*
3031  * ixgbe_configure_dcb - Configure DCB hardware
3032  * @adapter: ixgbe adapter struct
3033  *
3034  * This is called by the driver on open to configure the DCB hardware.
3035  * This is also called by the gennetlink interface when reconfiguring
3036  * the DCB state.
3037  */
3038 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3039 {
3040         struct ixgbe_hw *hw = &adapter->hw;
3041         u32 txdctl;
3042         int i, j;
3043
3044         ixgbe_dcb_check_config(&adapter->dcb_cfg);
3045         ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_TX_CONFIG);
3046         ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_RX_CONFIG);
3047
3048         /* reconfigure the hardware */
3049         ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg);
3050
3051         for (i = 0; i < adapter->num_tx_queues; i++) {
3052                 j = adapter->tx_ring[i]->reg_idx;
3053                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3054                 /* PThresh workaround for Tx hang with DFP enabled. */
3055                 txdctl |= 32;
3056                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
3057         }
3058         /* Enable VLAN tag insert/strip */
3059         ixgbe_vlan_filter_enable(adapter);
3060
3061         hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
3062 }
3063
3064 #endif
3065 static void ixgbe_configure(struct ixgbe_adapter *adapter)
3066 {
3067         struct net_device *netdev = adapter->netdev;
3068         struct ixgbe_hw *hw = &adapter->hw;
3069         int i;
3070
3071         ixgbe_set_rx_mode(netdev);
3072
3073         ixgbe_restore_vlan(adapter);
3074 #ifdef CONFIG_IXGBE_DCB
3075         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3076                 if (hw->mac.type == ixgbe_mac_82598EB)
3077                         netif_set_gso_max_size(netdev, 32768);
3078                 else
3079                         netif_set_gso_max_size(netdev, 65536);
3080                 ixgbe_configure_dcb(adapter);
3081         } else {
3082                 netif_set_gso_max_size(netdev, 65536);
3083         }
3084 #else
3085         netif_set_gso_max_size(netdev, 65536);
3086 #endif
3087
3088 #ifdef IXGBE_FCOE
3089         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
3090                 ixgbe_configure_fcoe(adapter);
3091
3092 #endif /* IXGBE_FCOE */
3093         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3094                 for (i = 0; i < adapter->num_tx_queues; i++)
3095                         adapter->tx_ring[i]->atr_sample_rate =
3096                                                        adapter->atr_sample_rate;
3097                 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
3098         } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3099                 ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc);
3100         }
3101
3102         ixgbe_configure_tx(adapter);
3103         ixgbe_configure_rx(adapter);
3104         for (i = 0; i < adapter->num_rx_queues; i++)
3105                 ixgbe_alloc_rx_buffers(adapter, adapter->rx_ring[i],
3106                                        (adapter->rx_ring[i]->count - 1));
3107 }
3108
3109 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3110 {
3111         switch (hw->phy.type) {
3112         case ixgbe_phy_sfp_avago:
3113         case ixgbe_phy_sfp_ftl:
3114         case ixgbe_phy_sfp_intel:
3115         case ixgbe_phy_sfp_unknown:
3116         case ixgbe_phy_tw_tyco:
3117         case ixgbe_phy_tw_unknown:
3118                 return true;
3119         default:
3120                 return false;
3121         }
3122 }
3123
3124 /**
3125  * ixgbe_sfp_link_config - set up SFP+ link
3126  * @adapter: pointer to private adapter struct
3127  **/
3128 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3129 {
3130         struct ixgbe_hw *hw = &adapter->hw;
3131
3132                 if (hw->phy.multispeed_fiber) {
3133                         /*
3134                          * In multispeed fiber setups, the device may not have
3135                          * had a physical connection when the driver loaded.
3136                          * If that's the case, the initial link configuration
3137                          * couldn't get the MAC into 10G or 1G mode, so we'll
3138                          * never have a link status change interrupt fire.
3139                          * We need to try and force an autonegotiation
3140                          * session, then bring up link.
3141                          */
3142                         hw->mac.ops.setup_sfp(hw);
3143                         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
3144                                 schedule_work(&adapter->multispeed_fiber_task);
3145                 } else {
3146                         /*
3147                          * Direct Attach Cu and non-multispeed fiber modules
3148                          * still need to be configured properly prior to
3149                          * attempting link.
3150                          */
3151                         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
3152                                 schedule_work(&adapter->sfp_config_module_task);
3153                 }
3154 }
3155
3156 /**
3157  * ixgbe_non_sfp_link_config - set up non-SFP+ link
3158  * @hw: pointer to private hardware struct
3159  *
3160  * Returns 0 on success, negative on failure
3161  **/
3162 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
3163 {
3164         u32 autoneg;
3165         bool negotiation, link_up = false;
3166         u32 ret = IXGBE_ERR_LINK_SETUP;
3167
3168         if (hw->mac.ops.check_link)
3169                 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3170
3171         if (ret)
3172                 goto link_cfg_out;
3173
3174         if (hw->mac.ops.get_link_capabilities)
3175                 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
3176         if (ret)
3177                 goto link_cfg_out;
3178
3179         if (hw->mac.ops.setup_link)
3180                 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
3181 link_cfg_out:
3182         return ret;
3183 }
3184
3185 #define IXGBE_MAX_RX_DESC_POLL 10
3186 static inline void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
3187                                               int rxr)
3188 {
3189         int j = adapter->rx_ring[rxr]->reg_idx;
3190         int k;
3191
3192         for (k = 0; k < IXGBE_MAX_RX_DESC_POLL; k++) {
3193                 if (IXGBE_READ_REG(&adapter->hw,
3194                                    IXGBE_RXDCTL(j)) & IXGBE_RXDCTL_ENABLE)
3195                         break;
3196                 else
3197                         msleep(1);
3198         }
3199         if (k >= IXGBE_MAX_RX_DESC_POLL) {
3200                 DPRINTK(DRV, ERR, "RXDCTL.ENABLE on Rx queue %d "
3201                         "not set within the polling period\n", rxr);
3202         }
3203         ixgbe_release_rx_desc(&adapter->hw, adapter->rx_ring[rxr],
3204                               (adapter->rx_ring[rxr]->count - 1));
3205 }
3206
3207 static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
3208 {
3209         struct net_device *netdev = adapter->netdev;
3210         struct ixgbe_hw *hw = &adapter->hw;
3211         int i, j = 0;
3212         int num_rx_rings = adapter->num_rx_queues;
3213         int err;
3214         int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3215         u32 txdctl, rxdctl, mhadd;
3216         u32 dmatxctl;
3217         u32 gpie;
3218         u32 ctrl_ext;
3219
3220         ixgbe_get_hw_control(adapter);
3221
3222         if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) ||
3223             (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) {
3224                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3225                         gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME |
3226                                 IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD);
3227                 } else {
3228                         /* MSI only */
3229                         gpie = 0;
3230                 }
3231                 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3232                         gpie &= ~IXGBE_GPIE_VTMODE_MASK;
3233                         gpie |= IXGBE_GPIE_VTMODE_64;
3234                 }
3235                 /* XXX: to interrupt immediately for EICS writes, enable this */
3236                 /* gpie |= IXGBE_GPIE_EIMEN; */
3237                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3238         }
3239
3240         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3241                 /*
3242                  * use EIAM to auto-mask when MSI-X interrupt is asserted
3243                  * this saves a register write for every interrupt
3244                  */
3245                 switch (hw->mac.type) {
3246                 case ixgbe_mac_82598EB:
3247                         IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3248                         break;
3249                 default:
3250                 case ixgbe_mac_82599EB:
3251                         IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3252                         IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3253                         break;
3254                 }
3255         } else {
3256                 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3257                  * specifically only auto mask tx and rx interrupts */
3258                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3259         }
3260
3261         /* Enable fan failure interrupt if media type is copper */
3262         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3263                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
3264                 gpie |= IXGBE_SDP1_GPIEN;
3265                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3266         }
3267
3268         if (hw->mac.type == ixgbe_mac_82599EB) {
3269                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
3270                 gpie |= IXGBE_SDP1_GPIEN;
3271                 gpie |= IXGBE_SDP2_GPIEN;
3272                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3273         }
3274
3275 #ifdef IXGBE_FCOE
3276         /* adjust max frame to be able to do baby jumbo for FCoE */
3277         if ((netdev->features & NETIF_F_FCOE_MTU) &&
3278             (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3279                 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3280
3281 #endif /* IXGBE_FCOE */
3282         mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3283         if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3284                 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3285                 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3286
3287                 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3288         }
3289
3290         for (i = 0; i < adapter->num_tx_queues; i++) {
3291                 j = adapter->tx_ring[i]->reg_idx;
3292                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3293                 if (adapter->rx_itr_setting == 0) {
3294                         /* cannot set wthresh when itr==0 */
3295                         txdctl &= ~0x007F0000;
3296                 } else {
3297                         /* enable WTHRESH=8 descriptors, to encourage burst writeback */
3298                         txdctl |= (8 << 16);
3299                 }
3300                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
3301         }
3302
3303         if (hw->mac.type == ixgbe_mac_82599EB) {
3304                 /* DMATXCTL.EN must be set after all Tx queue config is done */
3305                 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
3306                 dmatxctl |= IXGBE_DMATXCTL_TE;
3307                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
3308         }
3309         for (i = 0; i < adapter->num_tx_queues; i++) {
3310                 j = adapter->tx_ring[i]->reg_idx;
3311                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3312                 txdctl |= IXGBE_TXDCTL_ENABLE;
3313                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
3314                 if (hw->mac.type == ixgbe_mac_82599EB) {
3315                         int wait_loop = 10;
3316                         /* poll for Tx Enable ready */
3317                         do {
3318                                 msleep(1);
3319                                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3320                         } while (--wait_loop &&
3321                                  !(txdctl & IXGBE_TXDCTL_ENABLE));
3322                         if (!wait_loop)
3323                                 DPRINTK(DRV, ERR, "Could not enable "
3324                                         "Tx Queue %d\n", j);
3325                 }
3326         }
3327
3328         for (i = 0; i < num_rx_rings; i++) {
3329                 j = adapter->rx_ring[i]->reg_idx;
3330                 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3331                 /* enable PTHRESH=32 descriptors (half the internal cache)
3332                  * and HTHRESH=0 descriptors (to minimize latency on fetch),
3333                  * this also removes a pesky rx_no_buffer_count increment */
3334                 rxdctl |= 0x0020;
3335                 rxdctl |= IXGBE_RXDCTL_ENABLE;
3336                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl);
3337                 if (hw->mac.type == ixgbe_mac_82599EB)
3338                         ixgbe_rx_desc_queue_enable(adapter, i);
3339         }
3340         /* enable all receives */
3341         rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3342         if (hw->mac.type == ixgbe_mac_82598EB)
3343                 rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN);
3344         else
3345                 rxdctl |= IXGBE_RXCTRL_RXEN;
3346         hw->mac.ops.enable_rx_dma(hw, rxdctl);
3347
3348         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3349                 ixgbe_configure_msix(adapter);
3350         else
3351                 ixgbe_configure_msi_and_legacy(adapter);
3352
3353         /* enable the optics */
3354         if (hw->phy.multispeed_fiber)
3355                 hw->mac.ops.enable_tx_laser(hw);
3356
3357         clear_bit(__IXGBE_DOWN, &adapter->state);
3358         ixgbe_napi_enable_all(adapter);
3359
3360         /* clear any pending interrupts, may auto mask */
3361         IXGBE_READ_REG(hw, IXGBE_EICR);
3362
3363         ixgbe_irq_enable(adapter);
3364
3365         /*
3366          * If this adapter has a fan, check to see if we had a failure
3367          * before we enabled the interrupt.
3368          */
3369         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3370                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3371                 if (esdp & IXGBE_ESDP_SDP1)
3372                         DPRINTK(DRV, CRIT,
3373                                 "Fan has stopped, replace the adapter\n");
3374         }
3375
3376         /*
3377          * For hot-pluggable SFP+ devices, a new SFP+ module may have
3378          * arrived before interrupts were enabled but after probe.  Such
3379          * devices wouldn't have their type identified yet. We need to
3380          * kick off the SFP+ module setup first, then try to bring up link.
3381          * If we're not hot-pluggable SFP+, we just need to configure link
3382          * and bring it up.
3383          */
3384         if (hw->phy.type == ixgbe_phy_unknown) {
3385                 err = hw->phy.ops.identify(hw);
3386                 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
3387                         /*
3388                          * Take the device down and schedule the sfp tasklet
3389                          * which will unregister_netdev and log it.
3390                          */
3391                         ixgbe_down(adapter);
3392                         schedule_work(&adapter->sfp_config_module_task);
3393                         return err;
3394                 }
3395         }
3396
3397         if (ixgbe_is_sfp(hw)) {
3398                 ixgbe_sfp_link_config(adapter);
3399         } else {
3400                 err = ixgbe_non_sfp_link_config(hw);
3401                 if (err)
3402                         DPRINTK(PROBE, ERR, "link_config FAILED %d\n", err);
3403         }
3404
3405         for (i = 0; i < adapter->num_tx_queues; i++)
3406                 set_bit(__IXGBE_FDIR_INIT_DONE,
3407                         &(adapter->tx_ring[i]->reinit_state));
3408
3409         /* enable transmits */
3410         netif_tx_start_all_queues(netdev);
3411
3412         /* bring the link up in the watchdog, this could race with our first
3413          * link up interrupt but shouldn't be a problem */
3414         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3415         adapter->link_check_timeout = jiffies;
3416         mod_timer(&adapter->watchdog_timer, jiffies);
3417
3418         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3419         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3420         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
3421         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3422
3423         return 0;
3424 }
3425
3426 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
3427 {
3428         WARN_ON(in_interrupt());
3429         while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
3430                 msleep(1);
3431         ixgbe_down(adapter);
3432         /*
3433          * If SR-IOV enabled then wait a bit before bringing the adapter
3434          * back up to give the VFs time to respond to the reset.  The
3435          * two second wait is based upon the watchdog timer cycle in
3436          * the VF driver.
3437          */
3438         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3439                 msleep(2000);
3440         ixgbe_up(adapter);
3441         clear_bit(__IXGBE_RESETTING, &adapter->state);
3442 }
3443
3444 int ixgbe_up(struct ixgbe_adapter *adapter)
3445 {
3446         /* hardware has been reset, we need to reload some things */
3447         ixgbe_configure(adapter);
3448
3449         return ixgbe_up_complete(adapter);
3450 }
3451
3452 void ixgbe_reset(struct ixgbe_adapter *adapter)
3453 {
3454         struct ixgbe_hw *hw = &adapter->hw;
3455         int err;
3456
3457         err = hw->mac.ops.init_hw(hw);
3458         switch (err) {
3459         case 0:
3460         case IXGBE_ERR_SFP_NOT_PRESENT:
3461                 break;
3462         case IXGBE_ERR_MASTER_REQUESTS_PENDING:
3463                 dev_err(&adapter->pdev->dev, "master disable timed out\n");
3464                 break;
3465         case IXGBE_ERR_EEPROM_VERSION:
3466                 /* We are running on a pre-production device, log a warning */
3467                 dev_warn(&adapter->pdev->dev, "This device is a pre-production "
3468                          "adapter/LOM.  Please be aware there may be issues "
3469                          "associated with your hardware.  If you are "
3470                          "experiencing problems please contact your Intel or "
3471                          "hardware representative who provided you with this "
3472                          "hardware.\n");
3473                 break;
3474         default:
3475                 dev_err(&adapter->pdev->dev, "Hardware Error: %d\n", err);
3476         }
3477
3478         /* reprogram the RAR[0] in case user changed it. */
3479         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
3480                             IXGBE_RAH_AV);
3481 }
3482
3483 /**
3484  * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
3485  * @adapter: board private structure
3486  * @rx_ring: ring to free buffers from
3487  **/
3488 static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
3489                                 struct ixgbe_ring *rx_ring)
3490 {
3491         struct pci_dev *pdev = adapter->pdev;
3492         unsigned long size;
3493         unsigned int i;
3494
3495         /* Free all the Rx ring sk_buffs */
3496
3497         for (i = 0; i < rx_ring->count; i++) {
3498                 struct ixgbe_rx_buffer *rx_buffer_info;
3499
3500                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
3501                 if (rx_buffer_info->dma) {
3502                         dma_unmap_single(&pdev->dev, rx_buffer_info->dma,
3503                                          rx_ring->rx_buf_len,
3504                                          DMA_FROM_DEVICE);
3505                         rx_buffer_info->dma = 0;
3506                 }
3507                 if (rx_buffer_info->skb) {
3508                         struct sk_buff *skb = rx_buffer_info->skb;
3509                         rx_buffer_info->skb = NULL;
3510                         do {
3511                                 struct sk_buff *this = skb;
3512                                 if (IXGBE_RSC_CB(this)->delay_unmap) {
3513                                         dma_unmap_single(&pdev->dev,
3514                                                          IXGBE_RSC_CB(this)->dma,
3515                                                          rx_ring->rx_buf_len,
3516                                                          DMA_FROM_DEVICE);
3517                                         IXGBE_RSC_CB(this)->dma = 0;
3518                                         IXGBE_RSC_CB(skb)->delay_unmap = false;
3519                                 }
3520                                 skb = skb->prev;
3521                                 dev_kfree_skb(this);
3522                         } while (skb);
3523                 }
3524                 if (!rx_buffer_info->page)
3525                         continue;
3526                 if (rx_buffer_info->page_dma) {
3527                         dma_unmap_page(&pdev->dev, rx_buffer_info->page_dma,
3528                                        PAGE_SIZE / 2, DMA_FROM_DEVICE);
3529                         rx_buffer_info->page_dma = 0;
3530                 }
3531                 put_page(rx_buffer_info->page);
3532                 rx_buffer_info->page = NULL;
3533                 rx_buffer_info->page_offset = 0;
3534         }
3535
3536         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
3537         memset(rx_ring->rx_buffer_info, 0, size);
3538
3539         /* Zero out the descriptor ring */
3540         memset(rx_ring->desc, 0, rx_ring->size);
3541
3542         rx_ring->next_to_clean = 0;
3543         rx_ring->next_to_use = 0;
3544
3545         if (rx_ring->head)
3546                 writel(0, adapter->hw.hw_addr + rx_ring->head);
3547         if (rx_ring->tail)
3548                 writel(0, adapter->hw.hw_addr + rx_ring->tail);
3549 }
3550
3551 /**
3552  * ixgbe_clean_tx_ring - Free Tx Buffers
3553  * @adapter: board private structure
3554  * @tx_ring: ring to be cleaned
3555  **/
3556 static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
3557                                 struct ixgbe_ring *tx_ring)
3558 {
3559         struct ixgbe_tx_buffer *tx_buffer_info;
3560         unsigned long size;
3561         unsigned int i;
3562
3563         /* Free all the Tx ring sk_buffs */
3564
3565         for (i = 0; i < tx_ring->count; i++) {
3566                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3567                 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
3568         }
3569
3570         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3571         memset(tx_ring->tx_buffer_info, 0, size);
3572
3573         /* Zero out the descriptor ring */
3574         memset(tx_ring->desc, 0, tx_ring->size);
3575
3576         tx_ring->next_to_use = 0;
3577         tx_ring->next_to_clean = 0;
3578
3579         if (tx_ring->head)
3580                 writel(0, adapter->hw.hw_addr + tx_ring->head);
3581         if (tx_ring->tail)
3582                 writel(0, adapter->hw.hw_addr + tx_ring->tail);
3583 }
3584
3585 /**
3586  * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
3587  * @adapter: board private structure
3588  **/
3589 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
3590 {
3591         int i;
3592
3593         for (i = 0; i < adapter->num_rx_queues; i++)
3594                 ixgbe_clean_rx_ring(adapter, adapter->rx_ring[i]);
3595 }
3596
3597 /**
3598  * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
3599  * @adapter: board private structure
3600  **/
3601 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
3602 {
3603         int i;
3604
3605         for (i = 0; i < adapter->num_tx_queues; i++)
3606                 ixgbe_clean_tx_ring(adapter, adapter->tx_ring[i]);
3607 }
3608
3609 void ixgbe_down(struct ixgbe_adapter *adapter)
3610 {
3611         struct net_device *netdev = adapter->netdev;
3612         struct ixgbe_hw *hw = &adapter->hw;
3613         u32 rxctrl;
3614         u32 txdctl;
3615         int i, j;
3616
3617         /* signal that we are down to the interrupt handler */
3618         set_bit(__IXGBE_DOWN, &adapter->state);
3619
3620         /* power down the optics */
3621         if (hw->phy.multispeed_fiber)
3622                 hw->mac.ops.disable_tx_laser(hw);
3623
3624         /* disable receive for all VFs and wait one second */
3625         if (adapter->num_vfs) {
3626                 /* ping all the active vfs to let them know we are going down */
3627                 ixgbe_ping_all_vfs(adapter);
3628
3629                 /* Disable all VFTE/VFRE TX/RX */
3630                 ixgbe_disable_tx_rx(adapter);
3631
3632                 /* Mark all the VFs as inactive */
3633                 for (i = 0 ; i < adapter->num_vfs; i++)
3634                         adapter->vfinfo[i].clear_to_send = 0;
3635         }
3636
3637         /* disable receives */
3638         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3639         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3640
3641         IXGBE_WRITE_FLUSH(hw);
3642         msleep(10);
3643
3644         netif_tx_stop_all_queues(netdev);
3645
3646         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
3647         del_timer_sync(&adapter->sfp_timer);
3648         del_timer_sync(&adapter->watchdog_timer);
3649         cancel_work_sync(&adapter->watchdog_task);
3650
3651         netif_carrier_off(netdev);
3652         netif_tx_disable(netdev);
3653
3654         ixgbe_irq_disable(adapter);
3655
3656         ixgbe_napi_disable_all(adapter);
3657
3658         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3659             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
3660                 cancel_work_sync(&adapter->fdir_reinit_task);
3661
3662         /* disable transmits in the hardware now that interrupts are off */
3663         for (i = 0; i < adapter->num_tx_queues; i++) {
3664                 j = adapter->tx_ring[i]->reg_idx;
3665                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3666                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j),
3667                                 (txdctl & ~IXGBE_TXDCTL_ENABLE));
3668         }
3669         /* Disable the Tx DMA engine on 82599 */
3670         if (hw->mac.type == ixgbe_mac_82599EB)
3671                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
3672                                 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
3673                                  ~IXGBE_DMATXCTL_TE));
3674
3675         /* clear n-tuple filters that are cached */
3676         ethtool_ntuple_flush(netdev);
3677
3678         if (!pci_channel_offline(adapter->pdev))
3679                 ixgbe_reset(adapter);
3680         ixgbe_clean_all_tx_rings(adapter);
3681         ixgbe_clean_all_rx_rings(adapter);
3682
3683 #ifdef CONFIG_IXGBE_DCA
3684         /* since we reset the hardware DCA settings were cleared */
3685         ixgbe_setup_dca(adapter);
3686 #endif
3687 }
3688
3689 /**
3690  * ixgbe_poll - NAPI Rx polling callback
3691  * @napi: structure for representing this polling device
3692  * @budget: how many packets driver is allowed to clean
3693  *
3694  * This function is used for legacy and MSI, NAPI mode
3695  **/
3696 static int ixgbe_poll(struct napi_struct *napi, int budget)
3697 {
3698         struct ixgbe_q_vector *q_vector =
3699                                 container_of(napi, struct ixgbe_q_vector, napi);
3700         struct ixgbe_adapter *adapter = q_vector->adapter;
3701         int tx_clean_complete, work_done = 0;
3702
3703 #ifdef CONFIG_IXGBE_DCA
3704         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
3705                 ixgbe_update_tx_dca(adapter, adapter->tx_ring[0]);
3706                 ixgbe_update_rx_dca(adapter, adapter->rx_ring[0]);
3707         }
3708 #endif
3709
3710         tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring[0]);
3711         ixgbe_clean_rx_irq(q_vector, adapter->rx_ring[0], &work_done, budget);
3712
3713         if (!tx_clean_complete)
3714                 work_done = budget;
3715
3716         /* If budget not fully consumed, exit the polling mode */
3717         if (work_done < budget) {
3718                 napi_complete(napi);
3719                 if (adapter->rx_itr_setting & 1)
3720                         ixgbe_set_itr(adapter);
3721                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
3722                         ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
3723         }
3724         return work_done;
3725 }
3726
3727 /**
3728  * ixgbe_tx_timeout - Respond to a Tx Hang
3729  * @netdev: network interface device structure
3730  **/
3731 static void ixgbe_tx_timeout(struct net_device *netdev)
3732 {
3733         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3734
3735         /* Do the reset outside of interrupt context */
3736         schedule_work(&adapter->reset_task);
3737 }
3738
3739 static void ixgbe_reset_task(struct work_struct *work)
3740 {
3741         struct ixgbe_adapter *adapter;
3742         adapter = container_of(work, struct ixgbe_adapter, reset_task);
3743
3744         /* If we're already down or resetting, just bail */
3745         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
3746             test_bit(__IXGBE_RESETTING, &adapter->state))
3747                 return;
3748
3749         adapter->tx_timeout_count++;
3750
3751         ixgbe_dump(adapter);
3752         netdev_err(adapter->netdev, "Reset adapter\n");
3753         ixgbe_reinit_locked(adapter);
3754 }
3755
3756 #ifdef CONFIG_IXGBE_DCB
3757 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
3758 {
3759         bool ret = false;
3760         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB];
3761
3762         if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
3763                 return ret;
3764
3765         f->mask = 0x7 << 3;
3766         adapter->num_rx_queues = f->indices;
3767         adapter->num_tx_queues = f->indices;
3768         ret = true;
3769
3770         return ret;
3771 }
3772 #endif
3773
3774 /**
3775  * ixgbe_set_rss_queues: Allocate queues for RSS
3776  * @adapter: board private structure to initialize
3777  *
3778  * This is our "base" multiqueue mode.  RSS (Receive Side Scaling) will try
3779  * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
3780  *
3781  **/
3782 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
3783 {
3784         bool ret = false;
3785         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
3786
3787         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3788                 f->mask = 0xF;
3789                 adapter->num_rx_queues = f->indices;
3790                 adapter->num_tx_queues = f->indices;
3791                 ret = true;
3792         } else {
3793                 ret = false;
3794         }
3795
3796         return ret;
3797 }
3798
3799 /**
3800  * ixgbe_set_fdir_queues: Allocate queues for Flow Director
3801  * @adapter: board private structure to initialize
3802  *
3803  * Flow Director is an advanced Rx filter, attempting to get Rx flows back
3804  * to the original CPU that initiated the Tx session.  This runs in addition
3805  * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
3806  * Rx load across CPUs using RSS.
3807  *
3808  **/
3809 static bool inline ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
3810 {
3811         bool ret = false;
3812         struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
3813
3814         f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
3815         f_fdir->mask = 0;
3816
3817         /* Flow Director must have RSS enabled */
3818         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
3819             ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3820              (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) {
3821                 adapter->num_tx_queues = f_fdir->indices;
3822                 adapter->num_rx_queues = f_fdir->indices;
3823                 ret = true;
3824         } else {
3825                 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
3826                 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
3827         }
3828         return ret;
3829 }
3830
3831 #ifdef IXGBE_FCOE
3832 /**
3833  * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
3834  * @adapter: board private structure to initialize
3835  *
3836  * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
3837  * The ring feature mask is not used as a mask for FCoE, as it can take any 8
3838  * rx queues out of the max number of rx queues, instead, it is used as the
3839  * index of the first rx queue used by FCoE.
3840  *
3841  **/
3842 static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
3843 {
3844         bool ret = false;
3845         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
3846
3847         f->indices = min((int)num_online_cpus(), f->indices);
3848         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
3849                 adapter->num_rx_queues = 1;
3850                 adapter->num_tx_queues = 1;
3851 #ifdef CONFIG_IXGBE_DCB
3852                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3853                         DPRINTK(PROBE, INFO, "FCoE enabled with DCB\n");
3854                         ixgbe_set_dcb_queues(adapter);
3855                 }
3856 #endif
3857                 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3858                         DPRINTK(PROBE, INFO, "FCoE enabled with RSS\n");
3859                         if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3860                             (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
3861                                 ixgbe_set_fdir_queues(adapter);
3862                         else
3863                                 ixgbe_set_rss_queues(adapter);
3864                 }
3865                 /* adding FCoE rx rings to the end */
3866                 f->mask = adapter->num_rx_queues;
3867                 adapter->num_rx_queues += f->indices;
3868                 adapter->num_tx_queues += f->indices;
3869
3870                 ret = true;
3871         }
3872
3873         return ret;
3874 }
3875
3876 #endif /* IXGBE_FCOE */
3877 /**
3878  * ixgbe_set_sriov_queues: Allocate queues for IOV use
3879  * @adapter: board private structure to initialize
3880  *
3881  * IOV doesn't actually use anything, so just NAK the
3882  * request for now and let the other queue routines
3883  * figure out what to do.
3884  */
3885 static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
3886 {
3887         return false;
3888 }
3889
3890 /*
3891  * ixgbe_set_num_queues: Allocate queues for device, feature dependant
3892  * @adapter: board private structure to initialize
3893  *
3894  * This is the top level queue allocation routine.  The order here is very
3895  * important, starting with the "most" number of features turned on at once,
3896  * and ending with the smallest set of features.  This way large combinations
3897  * can be allocated if they're turned on, and smaller combinations are the
3898  * fallthrough conditions.
3899  *
3900  **/
3901 static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
3902 {
3903         /* Start with base case */
3904         adapter->num_rx_queues = 1;
3905         adapter->num_tx_queues = 1;
3906         adapter->num_rx_pools = adapter->num_rx_queues;
3907         adapter->num_rx_queues_per_pool = 1;
3908
3909         if (ixgbe_set_sriov_queues(adapter))
3910                 return;
3911
3912 #ifdef IXGBE_FCOE
3913         if (ixgbe_set_fcoe_queues(adapter))
3914                 goto done;
3915
3916 #endif /* IXGBE_FCOE */
3917 #ifdef CONFIG_IXGBE_DCB
3918         if (ixgbe_set_dcb_queues(adapter))
3919                 goto done;
3920
3921 #endif
3922         if (ixgbe_set_fdir_queues(adapter))
3923                 goto done;
3924
3925         if (ixgbe_set_rss_queues(adapter))
3926                 goto done;
3927
3928         /* fallback to base case */
3929         adapter->num_rx_queues = 1;
3930         adapter->num_tx_queues = 1;
3931
3932 done:
3933         /* Notify the stack of the (possibly) reduced Tx Queue count. */
3934         adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
3935 }
3936
3937 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
3938                                        int vectors)
3939 {
3940         int err, vector_threshold;
3941
3942         /* We'll want at least 3 (vector_threshold):
3943          * 1) TxQ[0] Cleanup
3944          * 2) RxQ[0] Cleanup
3945          * 3) Other (Link Status Change, etc.)
3946          * 4) TCP Timer (optional)
3947          */
3948         vector_threshold = MIN_MSIX_COUNT;
3949
3950         /* The more we get, the more we will assign to Tx/Rx Cleanup
3951          * for the separate queues...where Rx Cleanup >= Tx Cleanup.
3952          * Right now, we simply care about how many we'll get; we'll
3953          * set them up later while requesting irq's.
3954          */
3955         while (vectors >= vector_threshold) {
3956                 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
3957                                       vectors);
3958                 if (!err) /* Success in acquiring all requested vectors. */
3959                         break;
3960                 else if (err < 0)
3961                         vectors = 0; /* Nasty failure, quit now */
3962                 else /* err == number of vectors we should try again with */
3963                         vectors = err;
3964         }
3965
3966         if (vectors < vector_threshold) {
3967                 /* Can't allocate enough MSI-X interrupts?  Oh well.
3968                  * This just means we'll go with either a single MSI
3969                  * vector or fall back to legacy interrupts.
3970                  */
3971                 DPRINTK(HW, DEBUG, "Unable to allocate MSI-X interrupts\n");
3972                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
3973                 kfree(adapter->msix_entries);
3974                 adapter->msix_entries = NULL;
3975         } else {
3976                 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
3977                 /*
3978                  * Adjust for only the vectors we'll use, which is minimum
3979                  * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
3980                  * vectors we were allocated.
3981                  */
3982                 adapter->num_msix_vectors = min(vectors,
3983                                    adapter->max_msix_q_vectors + NON_Q_VECTORS);
3984         }
3985 }
3986
3987 /**
3988  * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
3989  * @adapter: board private structure to initialize
3990  *
3991  * Cache the descriptor ring offsets for RSS to the assigned rings.
3992  *
3993  **/
3994 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
3995 {
3996         int i;
3997         bool ret = false;
3998
3999         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4000                 for (i = 0; i < adapter->num_rx_queues; i++)
4001                         adapter->rx_ring[i]->reg_idx = i;
4002                 for (i = 0; i < adapter->num_tx_queues; i++)
4003                         adapter->tx_ring[i]->reg_idx = i;
4004                 ret = true;
4005         } else {
4006                 ret = false;
4007         }
4008
4009         return ret;
4010 }
4011
4012 #ifdef CONFIG_IXGBE_DCB
4013 /**
4014  * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4015  * @adapter: board private structure to initialize
4016  *
4017  * Cache the descriptor ring offsets for DCB to the assigned rings.
4018  *
4019  **/
4020 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
4021 {
4022         int i;
4023         bool ret = false;
4024         int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
4025
4026         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4027                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
4028                         /* the number of queues is assumed to be symmetric */
4029                         for (i = 0; i < dcb_i; i++) {
4030                                 adapter->rx_ring[i]->reg_idx = i << 3;
4031                                 adapter->tx_ring[i]->reg_idx = i << 2;
4032                         }
4033                         ret = true;
4034                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
4035                         if (dcb_i == 8) {
4036                                 /*
4037                                  * Tx TC0 starts at: descriptor queue 0
4038                                  * Tx TC1 starts at: descriptor queue 32
4039                                  * Tx TC2 starts at: descriptor queue 64
4040                                  * Tx TC3 starts at: descriptor queue 80
4041                                  * Tx TC4 starts at: descriptor queue 96
4042                                  * Tx TC5 starts at: descriptor queue 104
4043                                  * Tx TC6 starts at: descriptor queue 112
4044                                  * Tx TC7 starts at: descriptor queue 120
4045                                  *
4046                                  * Rx TC0-TC7 are offset by 16 queues each
4047                                  */
4048                                 for (i = 0; i < 3; i++) {
4049                                         adapter->tx_ring[i]->reg_idx = i << 5;
4050                                         adapter->rx_ring[i]->reg_idx = i << 4;
4051                                 }
4052                                 for ( ; i < 5; i++) {
4053                                         adapter->tx_ring[i]->reg_idx =
4054                                                                  ((i + 2) << 4);
4055                                         adapter->rx_ring[i]->reg_idx = i << 4;
4056                                 }
4057                                 for ( ; i < dcb_i; i++) {
4058                                         adapter->tx_ring[i]->reg_idx =
4059                                                                  ((i + 8) << 3);
4060                                         adapter->rx_ring[i]->reg_idx = i << 4;
4061                                 }
4062
4063                                 ret = true;
4064                         } else if (dcb_i == 4) {
4065                                 /*
4066                                  * Tx TC0 starts at: descriptor queue 0
4067                                  * Tx TC1 starts at: descriptor queue 64
4068                                  * Tx TC2 starts at: descriptor queue 96
4069                                  * Tx TC3 starts at: descriptor queue 112
4070                                  *
4071                                  * Rx TC0-TC3 are offset by 32 queues each
4072                                  */
4073                                 adapter->tx_ring[0]->reg_idx = 0;
4074                                 adapter->tx_ring[1]->reg_idx = 64;
4075                                 adapter->tx_ring[2]->reg_idx = 96;
4076                                 adapter->tx_ring[3]->reg_idx = 112;
4077                                 for (i = 0 ; i < dcb_i; i++)
4078                                         adapter->rx_ring[i]->reg_idx = i << 5;
4079
4080                                 ret = true;
4081                         } else {
4082                                 ret = false;
4083                         }
4084                 } else {
4085                         ret = false;
4086                 }
4087         } else {
4088                 ret = false;
4089         }
4090
4091         return ret;
4092 }
4093 #endif
4094
4095 /**
4096  * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
4097  * @adapter: board private structure to initialize
4098  *
4099  * Cache the descriptor ring offsets for Flow Director to the assigned rings.
4100  *
4101  **/
4102 static bool inline ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
4103 {
4104         int i;
4105         bool ret = false;
4106
4107         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
4108             ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4109              (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) {
4110                 for (i = 0; i < adapter->num_rx_queues; i++)
4111                         adapter->rx_ring[i]->reg_idx = i;
4112                 for (i = 0; i < adapter->num_tx_queues; i++)
4113                         adapter->tx_ring[i]->reg_idx = i;
4114                 ret = true;
4115         }
4116
4117         return ret;
4118 }
4119
4120 #ifdef IXGBE_FCOE
4121 /**
4122  * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
4123  * @adapter: board private structure to initialize
4124  *
4125  * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
4126  *
4127  */
4128 static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
4129 {
4130         int i, fcoe_rx_i = 0, fcoe_tx_i = 0;
4131         bool ret = false;
4132         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4133
4134         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
4135 #ifdef CONFIG_IXGBE_DCB
4136                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4137                         struct ixgbe_fcoe *fcoe = &adapter->fcoe;
4138
4139                         ixgbe_cache_ring_dcb(adapter);
4140                         /* find out queues in TC for FCoE */
4141                         fcoe_rx_i = adapter->rx_ring[fcoe->tc]->reg_idx + 1;
4142                         fcoe_tx_i = adapter->tx_ring[fcoe->tc]->reg_idx + 1;
4143                         /*
4144                          * In 82599, the number of Tx queues for each traffic
4145                          * class for both 8-TC and 4-TC modes are:
4146                          * TCs  : TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7
4147                          * 8 TCs:  32  32  16  16   8   8   8   8
4148                          * 4 TCs:  64  64  32  32
4149                          * We have max 8 queues for FCoE, where 8 the is
4150                          * FCoE redirection table size. If TC for FCoE is
4151                          * less than or equal to TC3, we have enough queues
4152                          * to add max of 8 queues for FCoE, so we start FCoE
4153                          * tx descriptor from the next one, i.e., reg_idx + 1.
4154                          * If TC for FCoE is above TC3, implying 8 TC mode,
4155                          * and we need 8 for FCoE, we have to take all queues
4156                          * in that traffic class for FCoE.
4157                          */
4158                         if ((f->indices == IXGBE_FCRETA_SIZE) && (fcoe->tc > 3))
4159                                 fcoe_tx_i--;
4160                 }
4161 #endif /* CONFIG_IXGBE_DCB */
4162                 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4163                         if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4164                             (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
4165                                 ixgbe_cache_ring_fdir(adapter);
4166                         else
4167                                 ixgbe_cache_ring_rss(adapter);
4168
4169                         fcoe_rx_i = f->mask;
4170                         fcoe_tx_i = f->mask;
4171                 }
4172                 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
4173                         adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
4174                         adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
4175                 }
4176                 ret = true;
4177         }
4178         return ret;
4179 }
4180
4181 #endif /* IXGBE_FCOE */
4182 /**
4183  * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
4184  * @adapter: board private structure to initialize
4185  *
4186  * SR-IOV doesn't use any descriptor rings but changes the default if
4187  * no other mapping is used.
4188  *
4189  */
4190 static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
4191 {
4192         adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2;
4193         adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2;
4194         if (adapter->num_vfs)
4195                 return true;
4196         else
4197                 return false;
4198 }
4199
4200 /**
4201  * ixgbe_cache_ring_register - Descriptor ring to register mapping
4202  * @adapter: board private structure to initialize
4203  *
4204  * Once we know the feature-set enabled for the device, we'll cache
4205  * the register offset the descriptor ring is assigned to.
4206  *
4207  * Note, the order the various feature calls is important.  It must start with
4208  * the "most" features enabled at the same time, then trickle down to the
4209  * least amount of features turned on at once.
4210  **/
4211 static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
4212 {
4213         /* start with default case */
4214         adapter->rx_ring[0]->reg_idx = 0;
4215         adapter->tx_ring[0]->reg_idx = 0;
4216
4217         if (ixgbe_cache_ring_sriov(adapter))
4218                 return;
4219
4220 #ifdef IXGBE_FCOE
4221         if (ixgbe_cache_ring_fcoe(adapter))
4222                 return;
4223
4224 #endif /* IXGBE_FCOE */
4225 #ifdef CONFIG_IXGBE_DCB
4226         if (ixgbe_cache_ring_dcb(adapter))
4227                 return;
4228
4229 #endif
4230         if (ixgbe_cache_ring_fdir(adapter))
4231                 return;
4232
4233         if (ixgbe_cache_ring_rss(adapter))
4234                 return;
4235 }
4236
4237 /**
4238  * ixgbe_alloc_queues - Allocate memory for all rings
4239  * @adapter: board private structure to initialize
4240  *
4241  * We allocate one ring per queue at run-time since we don't know the
4242  * number of queues at compile-time.  The polling_netdev array is
4243  * intended for Multiqueue, but should work fine with a single queue.
4244  **/
4245 static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
4246 {
4247         int i;
4248         int orig_node = adapter->node;
4249
4250         for (i = 0; i < adapter->num_tx_queues; i++) {
4251                 struct ixgbe_ring *ring = adapter->tx_ring[i];
4252                 if (orig_node == -1) {
4253                         int cur_node = next_online_node(adapter->node);
4254                         if (cur_node == MAX_NUMNODES)
4255                                 cur_node = first_online_node;
4256                         adapter->node = cur_node;
4257                 }
4258                 ring = kzalloc_node(sizeof(struct ixgbe_ring), GFP_KERNEL,
4259                                     adapter->node);
4260                 if (!ring)
4261                         ring = kzalloc(sizeof(struct ixgbe_ring), GFP_KERNEL);
4262                 if (!ring)
4263                         goto err_tx_ring_allocation;
4264                 ring->count = adapter->tx_ring_count;
4265                 ring->queue_index = i;
4266                 ring->numa_node = adapter->node;
4267
4268                 adapter->tx_ring[i] = ring;
4269         }
4270
4271         /* Restore the adapter's original node */
4272         adapter->node = orig_node;
4273
4274         for (i = 0; i < adapter->num_rx_queues; i++) {
4275                 struct ixgbe_ring *ring = adapter->rx_ring[i];
4276                 if (orig_node == -1) {
4277                         int cur_node = next_online_node(adapter->node);
4278                         if (cur_node == MAX_NUMNODES)
4279                                 cur_node = first_online_node;
4280                         adapter->node = cur_node;
4281                 }
4282                 ring = kzalloc_node(sizeof(struct ixgbe_ring), GFP_KERNEL,
4283                                     adapter->node);
4284                 if (!ring)
4285                         ring = kzalloc(sizeof(struct ixgbe_ring), GFP_KERNEL);
4286                 if (!ring)
4287                         goto err_rx_ring_allocation;
4288                 ring->count = adapter->rx_ring_count;
4289                 ring->queue_index = i;
4290                 ring->numa_node = adapter->node;
4291
4292                 adapter->rx_ring[i] = ring;
4293         }
4294
4295         /* Restore the adapter's original node */
4296         adapter->node = orig_node;
4297
4298         ixgbe_cache_ring_register(adapter);
4299
4300         return 0;
4301
4302 err_rx_ring_allocation:
4303         for (i = 0; i < adapter->num_tx_queues; i++)
4304                 kfree(adapter->tx_ring[i]);
4305 err_tx_ring_allocation:
4306         return -ENOMEM;
4307 }
4308
4309 /**
4310  * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
4311  * @adapter: board private structure to initialize
4312  *
4313  * Attempt to configure the interrupts using the best available
4314  * capabilities of the hardware and the kernel.
4315  **/
4316 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
4317 {
4318         struct ixgbe_hw *hw = &adapter->hw;
4319         int err = 0;
4320         int vector, v_budget;
4321
4322         /*
4323          * It's easy to be greedy for MSI-X vectors, but it really
4324          * doesn't do us much good if we have a lot more vectors
4325          * than CPU's.  So let's be conservative and only ask for
4326          * (roughly) the same number of vectors as there are CPU's.
4327          */
4328         v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
4329                        (int)num_online_cpus()) + NON_Q_VECTORS;
4330
4331         /*
4332          * At the same time, hardware can only support a maximum of
4333          * hw.mac->max_msix_vectors vectors.  With features
4334          * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
4335          * descriptor queues supported by our device.  Thus, we cap it off in
4336          * those rare cases where the cpu count also exceeds our vector limit.
4337          */
4338         v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
4339
4340         /* A failure in MSI-X entry allocation isn't fatal, but it does
4341          * mean we disable MSI-X capabilities of the adapter. */
4342         adapter->msix_entries = kcalloc(v_budget,
4343                                         sizeof(struct msix_entry), GFP_KERNEL);
4344         if (adapter->msix_entries) {
4345                 for (vector = 0; vector < v_budget; vector++)
4346                         adapter->msix_entries[vector].entry = vector;
4347
4348                 ixgbe_acquire_msix_vectors(adapter, v_budget);
4349
4350                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4351                         goto out;
4352         }
4353
4354         adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
4355         adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
4356         adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4357         adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4358         adapter->atr_sample_rate = 0;
4359         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4360                 ixgbe_disable_sriov(adapter);
4361
4362         ixgbe_set_num_queues(adapter);
4363
4364         err = pci_enable_msi(adapter->pdev);
4365         if (!err) {
4366                 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
4367         } else {
4368                 DPRINTK(HW, DEBUG, "Unable to allocate MSI interrupt, "
4369                         "falling back to legacy.  Error: %d\n", err);
4370                 /* reset err */
4371                 err = 0;
4372         }
4373
4374 out:
4375         return err;
4376 }
4377
4378 /**
4379  * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4380  * @adapter: board private structure to initialize
4381  *
4382  * We allocate one q_vector per queue interrupt.  If allocation fails we
4383  * return -ENOMEM.
4384  **/
4385 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
4386 {
4387         int q_idx, num_q_vectors;
4388         struct ixgbe_q_vector *q_vector;
4389         int napi_vectors;
4390         int (*poll)(struct napi_struct *, int);
4391
4392         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4393                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4394                 napi_vectors = adapter->num_rx_queues;
4395                 poll = &ixgbe_clean_rxtx_many;
4396         } else {
4397                 num_q_vectors = 1;
4398                 napi_vectors = 1;
4399                 poll = &ixgbe_poll;
4400         }
4401
4402         for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4403                 q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector),
4404                                         GFP_KERNEL, adapter->node);
4405                 if (!q_vector)
4406                         q_vector = kzalloc(sizeof(struct ixgbe_q_vector),
4407                                            GFP_KERNEL);
4408                 if (!q_vector)
4409                         goto err_out;
4410                 q_vector->adapter = adapter;
4411                 if (q_vector->txr_count && !q_vector->rxr_count)
4412                         q_vector->eitr = adapter->tx_eitr_param;
4413                 else
4414                         q_vector->eitr = adapter->rx_eitr_param;
4415                 q_vector->v_idx = q_idx;
4416                 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
4417                 adapter->q_vector[q_idx] = q_vector;
4418         }
4419
4420         return 0;
4421
4422 err_out:
4423         while (q_idx) {
4424                 q_idx--;
4425                 q_vector = adapter->q_vector[q_idx];
4426                 netif_napi_del(&q_vector->napi);
4427                 kfree(q_vector);
4428                 adapter->q_vector[q_idx] = NULL;
4429         }
4430         return -ENOMEM;
4431 }
4432
4433 /**
4434  * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
4435  * @adapter: board private structure to initialize
4436  *
4437  * This function frees the memory allocated to the q_vectors.  In addition if
4438  * NAPI is enabled it will delete any references to the NAPI struct prior
4439  * to freeing the q_vector.
4440  **/
4441 static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
4442 {
4443         int q_idx, num_q_vectors;
4444
4445         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4446                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4447         else
4448                 num_q_vectors = 1;
4449
4450         for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4451                 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
4452                 adapter->q_vector[q_idx] = NULL;
4453                 netif_napi_del(&q_vector->napi);
4454                 kfree(q_vector);
4455         }
4456 }
4457
4458 static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
4459 {
4460         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4461                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4462                 pci_disable_msix(adapter->pdev);
4463                 kfree(adapter->msix_entries);
4464                 adapter->msix_entries = NULL;
4465         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
4466                 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
4467                 pci_disable_msi(adapter->pdev);
4468         }
4469         return;
4470 }
4471
4472 /**
4473  * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
4474  * @adapter: board private structure to initialize
4475  *
4476  * We determine which interrupt scheme to use based on...
4477  * - Kernel support (MSI, MSI-X)
4478  *   - which can be user-defined (via MODULE_PARAM)
4479  * - Hardware queue count (num_*_queues)
4480  *   - defined by miscellaneous hardware support/features (RSS, etc.)
4481  **/
4482 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
4483 {
4484         int err;
4485
4486         /* Number of supported queues */
4487         ixgbe_set_num_queues(adapter);
4488
4489         err = ixgbe_set_interrupt_capability(adapter);
4490         if (err) {
4491                 DPRINTK(PROBE, ERR, "Unable to setup interrupt capabilities\n");
4492                 goto err_set_interrupt;
4493         }
4494
4495         err = ixgbe_alloc_q_vectors(adapter);
4496         if (err) {
4497                 DPRINTK(PROBE, ERR, "Unable to allocate memory for queue "
4498                         "vectors\n");
4499                 goto err_alloc_q_vectors;
4500         }
4501
4502         err = ixgbe_alloc_queues(adapter);
4503         if (err) {
4504                 DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n");
4505                 goto err_alloc_queues;
4506         }
4507
4508         DPRINTK(DRV, INFO, "Multiqueue %s: Rx Queue count = %u, "
4509                 "Tx Queue count = %u\n",
4510                 (adapter->num_rx_queues > 1) ? "Enabled" :
4511                 "Disabled", adapter->num_rx_queues, adapter->num_tx_queues);
4512
4513         set_bit(__IXGBE_DOWN, &adapter->state);
4514
4515         return 0;
4516
4517 err_alloc_queues:
4518         ixgbe_free_q_vectors(adapter);
4519 err_alloc_q_vectors:
4520         ixgbe_reset_interrupt_capability(adapter);
4521 err_set_interrupt:
4522         return err;
4523 }
4524
4525 /**
4526  * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
4527  * @adapter: board private structure to clear interrupt scheme on
4528  *
4529  * We go through and clear interrupt specific resources and reset the structure
4530  * to pre-load conditions
4531  **/
4532 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
4533 {
4534         int i;
4535
4536         for (i = 0; i < adapter->num_tx_queues; i++) {
4537                 kfree(adapter->tx_ring[i]);
4538                 adapter->tx_ring[i] = NULL;
4539         }
4540         for (i = 0; i < adapter->num_rx_queues; i++) {
4541                 kfree(adapter->rx_ring[i]);
4542                 adapter->rx_ring[i] = NULL;
4543         }
4544
4545         ixgbe_free_q_vectors(adapter);
4546         ixgbe_reset_interrupt_capability(adapter);
4547 }
4548
4549 /**
4550  * ixgbe_sfp_timer - worker thread to find a missing module
4551  * @data: pointer to our adapter struct
4552  **/
4553 static void ixgbe_sfp_timer(unsigned long data)
4554 {
4555         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
4556
4557         /*
4558          * Do the sfp_timer outside of interrupt context due to the
4559          * delays that sfp+ detection requires
4560          */
4561         schedule_work(&adapter->sfp_task);
4562 }
4563
4564 /**
4565  * ixgbe_sfp_task - worker thread to find a missing module
4566  * @work: pointer to work_struct containing our data
4567  **/
4568 static void ixgbe_sfp_task(struct work_struct *work)
4569 {
4570         struct ixgbe_adapter *adapter = container_of(work,
4571                                                      struct ixgbe_adapter,
4572                                                      sfp_task);
4573         struct ixgbe_hw *hw = &adapter->hw;
4574
4575         if ((hw->phy.type == ixgbe_phy_nl) &&
4576             (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
4577                 s32 ret = hw->phy.ops.identify_sfp(hw);
4578                 if (ret == IXGBE_ERR_SFP_NOT_PRESENT)
4579                         goto reschedule;
4580                 ret = hw->phy.ops.reset(hw);
4581                 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
4582                         dev_err(&adapter->pdev->dev, "failed to initialize "
4583                                 "because an unsupported SFP+ module type "
4584                                 "was detected.\n"
4585                                 "Reload the driver after installing a "
4586                                 "supported module.\n");
4587                         unregister_netdev(adapter->netdev);
4588                 } else {
4589                         DPRINTK(PROBE, INFO, "detected SFP+: %d\n",
4590                                 hw->phy.sfp_type);
4591                 }
4592                 /* don't need this routine any more */
4593                 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
4594         }
4595         return;
4596 reschedule:
4597         if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
4598                 mod_timer(&adapter->sfp_timer,
4599                           round_jiffies(jiffies + (2 * HZ)));
4600 }
4601
4602 /**
4603  * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4604  * @adapter: board private structure to initialize
4605  *
4606  * ixgbe_sw_init initializes the Adapter private data structure.
4607  * Fields are initialized based on PCI device information and
4608  * OS network device settings (MTU size).
4609  **/
4610 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
4611 {
4612         struct ixgbe_hw *hw = &adapter->hw;
4613         struct pci_dev *pdev = adapter->pdev;
4614         struct net_device *dev = adapter->netdev;
4615         unsigned int rss;
4616 #ifdef CONFIG_IXGBE_DCB
4617         int j;
4618         struct tc_configuration *tc;
4619 #endif
4620
4621         /* PCI config space info */
4622
4623         hw->vendor_id = pdev->vendor;
4624         hw->device_id = pdev->device;
4625         hw->revision_id = pdev->revision;
4626         hw->subsystem_vendor_id = pdev->subsystem_vendor;
4627         hw->subsystem_device_id = pdev->subsystem_device;
4628
4629         /* Set capability flags */
4630         rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
4631         adapter->ring_feature[RING_F_RSS].indices = rss;
4632         adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
4633         adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
4634         if (hw->mac.type == ixgbe_mac_82598EB) {
4635                 if (hw->device_id == IXGBE_DEV_ID_82598AT)
4636                         adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
4637                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
4638         } else if (hw->mac.type == ixgbe_mac_82599EB) {
4639                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
4640                 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
4641                 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
4642                 if (dev->features & NETIF_F_NTUPLE) {
4643                         /* Flow Director perfect filter enabled */
4644                         adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4645                         adapter->atr_sample_rate = 0;
4646                         spin_lock_init(&adapter->fdir_perfect_lock);
4647                 } else {
4648                         /* Flow Director hash filters enabled */
4649                         adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
4650                         adapter->atr_sample_rate = 20;
4651                 }
4652                 adapter->ring_feature[RING_F_FDIR].indices =
4653                                                          IXGBE_MAX_FDIR_INDICES;
4654                 adapter->fdir_pballoc = 0;
4655 #ifdef IXGBE_FCOE
4656                 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
4657                 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
4658                 adapter->ring_feature[RING_F_FCOE].indices = 0;
4659 #ifdef CONFIG_IXGBE_DCB
4660                 /* Default traffic class to use for FCoE */
4661                 adapter->fcoe.tc = IXGBE_FCOE_DEFTC;
4662 #endif
4663 #endif /* IXGBE_FCOE */
4664         }
4665
4666 #ifdef CONFIG_IXGBE_DCB
4667         /* Configure DCB traffic classes */
4668         for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
4669                 tc = &adapter->dcb_cfg.tc_config[j];
4670                 tc->path[DCB_TX_CONFIG].bwg_id = 0;
4671                 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
4672                 tc->path[DCB_RX_CONFIG].bwg_id = 0;
4673                 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
4674                 tc->dcb_pfc = pfc_disabled;
4675         }
4676         adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
4677         adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
4678         adapter->dcb_cfg.rx_pba_cfg = pba_equal;
4679         adapter->dcb_cfg.pfc_mode_enable = false;
4680         adapter->dcb_cfg.round_robin_enable = false;
4681         adapter->dcb_set_bitmap = 0x00;
4682         ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
4683                            adapter->ring_feature[RING_F_DCB].indices);
4684
4685 #endif
4686
4687         /* default flow control settings */
4688         hw->fc.requested_mode = ixgbe_fc_full;
4689         hw->fc.current_mode = ixgbe_fc_full;    /* init for ethtool output */
4690 #ifdef CONFIG_DCB
4691         adapter->last_lfc_mode = hw->fc.current_mode;
4692 #endif
4693         hw->fc.high_water = IXGBE_DEFAULT_FCRTH;
4694         hw->fc.low_water = IXGBE_DEFAULT_FCRTL;
4695         hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
4696         hw->fc.send_xon = true;
4697         hw->fc.disable_fc_autoneg = false;
4698
4699         /* enable itr by default in dynamic mode */
4700         adapter->rx_itr_setting = 1;
4701         adapter->rx_eitr_param = 20000;
4702         adapter->tx_itr_setting = 1;
4703         adapter->tx_eitr_param = 10000;
4704
4705         /* set defaults for eitr in MegaBytes */
4706         adapter->eitr_low = 10;
4707         adapter->eitr_high = 20;
4708
4709         /* set default ring sizes */
4710         adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
4711         adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
4712
4713         /* initialize eeprom parameters */
4714         if (ixgbe_init_eeprom_params_generic(hw)) {
4715                 dev_err(&pdev->dev, "EEPROM initialization failed\n");
4716                 return -EIO;
4717         }
4718
4719         /* enable rx csum by default */
4720         adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
4721
4722         /* get assigned NUMA node */
4723         adapter->node = dev_to_node(&pdev->dev);
4724
4725         set_bit(__IXGBE_DOWN, &adapter->state);
4726
4727         return 0;
4728 }
4729
4730 /**
4731  * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
4732  * @adapter: board private structure
4733  * @tx_ring:    tx descriptor ring (for a specific queue) to setup
4734  *
4735  * Return 0 on success, negative on failure
4736  **/
4737 int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
4738                              struct ixgbe_ring *tx_ring)
4739 {
4740         struct pci_dev *pdev = adapter->pdev;
4741         int size;
4742
4743         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4744         tx_ring->tx_buffer_info = vmalloc_node(size, tx_ring->numa_node);
4745         if (!tx_ring->tx_buffer_info)
4746                 tx_ring->tx_buffer_info = vmalloc(size);
4747         if (!tx_ring->tx_buffer_info)
4748                 goto err;
4749         memset(tx_ring->tx_buffer_info, 0, size);
4750
4751         /* round up to nearest 4K */
4752         tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
4753         tx_ring->size = ALIGN(tx_ring->size, 4096);
4754
4755         tx_ring->desc = dma_alloc_coherent(&pdev->dev, tx_ring->size,
4756                                            &tx_ring->dma, GFP_KERNEL);
4757         if (!tx_ring->desc)
4758                 goto err;
4759
4760         tx_ring->next_to_use = 0;
4761         tx_ring->next_to_clean = 0;
4762         tx_ring->work_limit = tx_ring->count;
4763         return 0;
4764
4765 err:
4766         vfree(tx_ring->tx_buffer_info);
4767         tx_ring->tx_buffer_info = NULL;
4768         DPRINTK(PROBE, ERR, "Unable to allocate memory for the transmit "
4769                             "descriptor ring\n");
4770         return -ENOMEM;
4771 }
4772
4773 /**
4774  * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
4775  * @adapter: board private structure
4776  *
4777  * If this function returns with an error, then it's possible one or
4778  * more of the rings is populated (while the rest are not).  It is the
4779  * callers duty to clean those orphaned rings.
4780  *
4781  * Return 0 on success, negative on failure
4782  **/
4783 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
4784 {
4785         int i, err = 0;
4786
4787         for (i = 0; i < adapter->num_tx_queues; i++) {
4788                 err = ixgbe_setup_tx_resources(adapter, adapter->tx_ring[i]);
4789                 if (!err)
4790                         continue;
4791                 DPRINTK(PROBE, ERR, "Allocation for Tx Queue %u failed\n", i);
4792                 break;
4793         }
4794
4795         return err;
4796 }
4797
4798 /**
4799  * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
4800  * @adapter: board private structure
4801  * @rx_ring:    rx descriptor ring (for a specific queue) to setup
4802  *
4803  * Returns 0 on success, negative on failure
4804  **/
4805 int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
4806                              struct ixgbe_ring *rx_ring)
4807 {
4808         struct pci_dev *pdev = adapter->pdev;
4809         int size;
4810
4811         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4812         rx_ring->rx_buffer_info = vmalloc_node(size, adapter->node);
4813         if (!rx_ring->rx_buffer_info)
4814                 rx_ring->rx_buffer_info = vmalloc(size);
4815         if (!rx_ring->rx_buffer_info) {
4816                 DPRINTK(PROBE, ERR,
4817                         "vmalloc allocation failed for the rx desc ring\n");
4818                 goto alloc_failed;
4819         }
4820         memset(rx_ring->rx_buffer_info, 0, size);
4821
4822         /* Round up to nearest 4K */
4823         rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
4824         rx_ring->size = ALIGN(rx_ring->size, 4096);
4825
4826         rx_ring->desc = dma_alloc_coherent(&pdev->dev, rx_ring->size,
4827                                            &rx_ring->dma, GFP_KERNEL);
4828
4829         if (!rx_ring->desc) {
4830                 DPRINTK(PROBE, ERR,
4831                         "Memory allocation failed for the rx desc ring\n");
4832                 vfree(rx_ring->rx_buffer_info);
4833                 goto alloc_failed;
4834         }
4835
4836         rx_ring->next_to_clean = 0;
4837         rx_ring->next_to_use = 0;
4838
4839         return 0;
4840
4841 alloc_failed:
4842         return -ENOMEM;
4843 }
4844
4845 /**
4846  * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
4847  * @adapter: board private structure
4848  *
4849  * If this function returns with an error, then it's possible one or
4850  * more of the rings is populated (while the rest are not).  It is the
4851  * callers duty to clean those orphaned rings.
4852  *
4853  * Return 0 on success, negative on failure
4854  **/
4855
4856 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
4857 {
4858         int i, err = 0;
4859
4860         for (i = 0; i < adapter->num_rx_queues; i++) {
4861                 err = ixgbe_setup_rx_resources(adapter, adapter->rx_ring[i]);
4862                 if (!err)
4863                         continue;
4864                 DPRINTK(PROBE, ERR, "Allocation for Rx Queue %u failed\n", i);
4865                 break;
4866         }
4867
4868         return err;
4869 }
4870
4871 /**
4872  * ixgbe_free_tx_resources - Free Tx Resources per Queue
4873  * @adapter: board private structure
4874  * @tx_ring: Tx descriptor ring for a specific queue
4875  *
4876  * Free all transmit software resources
4877  **/
4878 void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter,
4879                              struct ixgbe_ring *tx_ring)
4880 {
4881         struct pci_dev *pdev = adapter->pdev;
4882
4883         ixgbe_clean_tx_ring(adapter, tx_ring);
4884
4885         vfree(tx_ring->tx_buffer_info);
4886         tx_ring->tx_buffer_info = NULL;
4887
4888         dma_free_coherent(&pdev->dev, tx_ring->size, tx_ring->desc,
4889                           tx_ring->dma);
4890
4891         tx_ring->desc = NULL;
4892 }
4893
4894 /**
4895  * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
4896  * @adapter: board private structure
4897  *
4898  * Free all transmit software resources
4899  **/
4900 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
4901 {
4902         int i;
4903
4904         for (i = 0; i < adapter->num_tx_queues; i++)
4905                 if (adapter->tx_ring[i]->desc)
4906                         ixgbe_free_tx_resources(adapter, adapter->tx_ring[i]);
4907 }
4908
4909 /**
4910  * ixgbe_free_rx_resources - Free Rx Resources
4911  * @adapter: board private structure
4912  * @rx_ring: ring to clean the resources from
4913  *
4914  * Free all receive software resources
4915  **/
4916 void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
4917                              struct ixgbe_ring *rx_ring)
4918 {
4919         struct pci_dev *pdev = adapter->pdev;
4920
4921         ixgbe_clean_rx_ring(adapter, rx_ring);
4922
4923         vfree(rx_ring->rx_buffer_info);
4924         rx_ring->rx_buffer_info = NULL;
4925
4926         dma_free_coherent(&pdev->dev, rx_ring->size, rx_ring->desc,
4927                           rx_ring->dma);
4928
4929         rx_ring->desc = NULL;
4930 }
4931
4932 /**
4933  * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
4934  * @adapter: board private structure
4935  *
4936  * Free all receive software resources
4937  **/
4938 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
4939 {
4940         int i;
4941
4942         for (i = 0; i < adapter->num_rx_queues; i++)
4943                 if (adapter->rx_ring[i]->desc)
4944                         ixgbe_free_rx_resources(adapter, adapter->rx_ring[i]);
4945 }
4946
4947 /**
4948  * ixgbe_change_mtu - Change the Maximum Transfer Unit
4949  * @netdev: network interface device structure
4950  * @new_mtu: new value for maximum frame size
4951  *
4952  * Returns 0 on success, negative on failure
4953  **/
4954 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
4955 {
4956         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4957         int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
4958
4959         /* MTU < 68 is an error and causes problems on some kernels */
4960         if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
4961                 return -EINVAL;
4962
4963         DPRINTK(PROBE, INFO, "changing MTU from %d to %d\n",
4964                 netdev->mtu, new_mtu);
4965         /* must set new MTU before calling down or up */
4966         netdev->mtu = new_mtu;
4967
4968         if (netif_running(netdev))
4969                 ixgbe_reinit_locked(adapter);
4970
4971         return 0;
4972 }
4973
4974 /**
4975  * ixgbe_open - Called when a network interface is made active
4976  * @netdev: network interface device structure
4977  *
4978  * Returns 0 on success, negative value on failure
4979  *
4980  * The open entry point is called when a network interface is made
4981  * active by the system (IFF_UP).  At this point all resources needed
4982  * for transmit and receive operations are allocated, the interrupt
4983  * handler is registered with the OS, the watchdog timer is started,
4984  * and the stack is notified that the interface is ready.
4985  **/
4986 static int ixgbe_open(struct net_device *netdev)
4987 {
4988         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4989         int err;
4990
4991         /* disallow open during test */
4992         if (test_bit(__IXGBE_TESTING, &adapter->state))
4993                 return -EBUSY;
4994
4995         netif_carrier_off(netdev);
4996
4997         /* allocate transmit descriptors */
4998         err = ixgbe_setup_all_tx_resources(adapter);
4999         if (err)
5000                 goto err_setup_tx;
5001
5002         /* allocate receive descriptors */
5003         err = ixgbe_setup_all_rx_resources(adapter);
5004         if (err)
5005                 goto err_setup_rx;
5006
5007         ixgbe_configure(adapter);
5008
5009         err = ixgbe_request_irq(adapter);
5010         if (err)
5011                 goto err_req_irq;
5012
5013         err = ixgbe_up_complete(adapter);
5014         if (err)
5015                 goto err_up;
5016
5017         netif_tx_start_all_queues(netdev);
5018
5019         return 0;
5020
5021 err_up:
5022         ixgbe_release_hw_control(adapter);
5023         ixgbe_free_irq(adapter);
5024 err_req_irq:
5025 err_setup_rx:
5026         ixgbe_free_all_rx_resources(adapter);
5027 err_setup_tx:
5028         ixgbe_free_all_tx_resources(adapter);
5029         ixgbe_reset(adapter);
5030
5031         return err;
5032 }
5033
5034 /**
5035  * ixgbe_close - Disables a network interface
5036  * @netdev: network interface device structure
5037  *
5038  * Returns 0, this is not allowed to fail
5039  *
5040  * The close entry point is called when an interface is de-activated
5041  * by the OS.  The hardware is still under the drivers control, but
5042  * needs to be disabled.  A global MAC reset is issued to stop the
5043  * hardware, and all transmit and receive resources are freed.
5044  **/
5045 static int ixgbe_close(struct net_device *netdev)
5046 {
5047         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5048
5049         ixgbe_down(adapter);
5050         ixgbe_free_irq(adapter);
5051
5052         ixgbe_free_all_tx_resources(adapter);
5053         ixgbe_free_all_rx_resources(adapter);
5054
5055         ixgbe_release_hw_control(adapter);
5056
5057         return 0;
5058 }
5059
5060 #ifdef CONFIG_PM
5061 static int ixgbe_resume(struct pci_dev *pdev)
5062 {
5063         struct net_device *netdev = pci_get_drvdata(pdev);
5064         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5065         u32 err;
5066
5067         pci_set_power_state(pdev, PCI_D0);
5068         pci_restore_state(pdev);
5069         /*
5070          * pci_restore_state clears dev->state_saved so call
5071          * pci_save_state to restore it.
5072          */
5073         pci_save_state(pdev);
5074
5075         err = pci_enable_device_mem(pdev);
5076         if (err) {
5077                 printk(KERN_ERR "ixgbe: Cannot enable PCI device from "
5078                                 "suspend\n");
5079                 return err;
5080         }
5081         pci_set_master(pdev);
5082
5083         pci_wake_from_d3(pdev, false);
5084
5085         err = ixgbe_init_interrupt_scheme(adapter);
5086         if (err) {
5087                 printk(KERN_ERR "ixgbe: Cannot initialize interrupts for "
5088                                 "device\n");
5089                 return err;
5090         }
5091
5092         ixgbe_reset(adapter);
5093
5094         IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5095
5096         if (netif_running(netdev)) {
5097                 err = ixgbe_open(adapter->netdev);
5098                 if (err)
5099                         return err;
5100         }
5101
5102         netif_device_attach(netdev);
5103
5104         return 0;
5105 }
5106 #endif /* CONFIG_PM */
5107
5108 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
5109 {
5110         struct net_device *netdev = pci_get_drvdata(pdev);
5111         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5112         struct ixgbe_hw *hw = &adapter->hw;
5113         u32 ctrl, fctrl;
5114         u32 wufc = adapter->wol;
5115 #ifdef CONFIG_PM
5116         int retval = 0;
5117 #endif
5118
5119         netif_device_detach(netdev);
5120
5121         if (netif_running(netdev)) {
5122                 ixgbe_down(adapter);
5123                 ixgbe_free_irq(adapter);
5124                 ixgbe_free_all_tx_resources(adapter);
5125                 ixgbe_free_all_rx_resources(adapter);
5126         }
5127         ixgbe_clear_interrupt_scheme(adapter);
5128
5129 #ifdef CONFIG_PM
5130         retval = pci_save_state(pdev);
5131         if (retval)
5132                 return retval;
5133
5134 #endif
5135         if (wufc) {
5136                 ixgbe_set_rx_mode(netdev);
5137
5138                 /* turn on all-multi mode if wake on multicast is enabled */
5139                 if (wufc & IXGBE_WUFC_MC) {
5140                         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5141                         fctrl |= IXGBE_FCTRL_MPE;
5142                         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5143                 }
5144
5145                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5146                 ctrl |= IXGBE_CTRL_GIO_DIS;
5147                 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5148
5149                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5150         } else {
5151                 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5152                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5153         }
5154
5155         if (wufc && hw->mac.type == ixgbe_mac_82599EB)
5156                 pci_wake_from_d3(pdev, true);
5157         else
5158                 pci_wake_from_d3(pdev, false);
5159
5160         *enable_wake = !!wufc;
5161
5162         ixgbe_release_hw_control(adapter);
5163
5164         pci_disable_device(pdev);
5165
5166         return 0;
5167 }
5168
5169 #ifdef CONFIG_PM
5170 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5171 {
5172         int retval;
5173         bool wake;
5174
5175         retval = __ixgbe_shutdown(pdev, &wake);
5176         if (retval)
5177                 return retval;
5178
5179         if (wake) {
5180                 pci_prepare_to_sleep(pdev);
5181         } else {
5182                 pci_wake_from_d3(pdev, false);
5183                 pci_set_power_state(pdev, PCI_D3hot);
5184         }
5185
5186         return 0;
5187 }
5188 #endif /* CONFIG_PM */
5189
5190 static void ixgbe_shutdown(struct pci_dev *pdev)
5191 {
5192         bool wake;
5193
5194         __ixgbe_shutdown(pdev, &wake);
5195
5196         if (system_state == SYSTEM_POWER_OFF) {
5197                 pci_wake_from_d3(pdev, wake);
5198                 pci_set_power_state(pdev, PCI_D3hot);
5199         }
5200 }
5201
5202 /**
5203  * ixgbe_update_stats - Update the board statistics counters.
5204  * @adapter: board private structure
5205  **/
5206 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5207 {
5208         struct net_device *netdev = adapter->netdev;
5209         struct ixgbe_hw *hw = &adapter->hw;
5210         u64 total_mpc = 0;
5211         u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5212         u64 non_eop_descs = 0, restart_queue = 0;
5213
5214         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
5215                 u64 rsc_count = 0;
5216                 u64 rsc_flush = 0;
5217                 for (i = 0; i < 16; i++)
5218                         adapter->hw_rx_no_dma_resources +=
5219                                              IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
5220                 for (i = 0; i < adapter->num_rx_queues; i++) {
5221                         rsc_count += adapter->rx_ring[i]->rsc_count;
5222                         rsc_flush += adapter->rx_ring[i]->rsc_flush;
5223                 }
5224                 adapter->rsc_total_count = rsc_count;
5225                 adapter->rsc_total_flush = rsc_flush;
5226         }
5227
5228         /* gather some stats to the adapter struct that are per queue */
5229         for (i = 0; i < adapter->num_tx_queues; i++)
5230                 restart_queue += adapter->tx_ring[i]->restart_queue;
5231         adapter->restart_queue = restart_queue;
5232
5233         for (i = 0; i < adapter->num_rx_queues; i++)
5234                 non_eop_descs += adapter->rx_ring[i]->non_eop_descs;
5235         adapter->non_eop_descs = non_eop_descs;
5236
5237         adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
5238         for (i = 0; i < 8; i++) {
5239                 /* for packet buffers not used, the register should read 0 */
5240                 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5241                 missed_rx += mpc;
5242                 adapter->stats.mpc[i] += mpc;
5243                 total_mpc += adapter->stats.mpc[i];
5244                 if (hw->mac.type == ixgbe_mac_82598EB)
5245                         adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5246                 adapter->stats.qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5247                 adapter->stats.qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5248                 adapter->stats.qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5249                 adapter->stats.qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
5250                 if (hw->mac.type == ixgbe_mac_82599EB) {
5251                         adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
5252                                                             IXGBE_PXONRXCNT(i));
5253                         adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
5254                                                            IXGBE_PXOFFRXCNT(i));
5255                         adapter->stats.qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
5256                 } else {
5257                         adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
5258                                                               IXGBE_PXONRXC(i));
5259                         adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
5260                                                              IXGBE_PXOFFRXC(i));
5261                 }
5262                 adapter->stats.pxontxc[i] += IXGBE_READ_REG(hw,
5263                                                             IXGBE_PXONTXC(i));
5264                 adapter->stats.pxofftxc[i] += IXGBE_READ_REG(hw,
5265                                                              IXGBE_PXOFFTXC(i));
5266         }
5267         adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
5268         /* work around hardware counting issue */
5269         adapter->stats.gprc -= missed_rx;
5270
5271         /* 82598 hardware only has a 32 bit counter in the high register */
5272         if (hw->mac.type == ixgbe_mac_82599EB) {
5273                 u64 tmp;
5274                 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
5275                 tmp = IXGBE_READ_REG(hw, IXGBE_GORCH) & 0xF; /* 4 high bits of GORC */
5276                 adapter->stats.gorc += (tmp << 32);
5277                 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
5278                 tmp = IXGBE_READ_REG(hw, IXGBE_GOTCH) & 0xF; /* 4 high bits of GOTC */
5279                 adapter->stats.gotc += (tmp << 32);
5280                 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORL);
5281                 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
5282                 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
5283                 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
5284                 adapter->stats.fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5285                 adapter->stats.fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
5286 #ifdef IXGBE_FCOE
5287                 adapter->stats.fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5288                 adapter->stats.fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5289                 adapter->stats.fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5290                 adapter->stats.fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5291                 adapter->stats.fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5292                 adapter->stats.fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
5293 #endif /* IXGBE_FCOE */
5294         } else {
5295                 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
5296                 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
5297                 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5298                 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5299                 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5300         }
5301         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
5302         adapter->stats.bprc += bprc;
5303         adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
5304         if (hw->mac.type == ixgbe_mac_82598EB)
5305                 adapter->stats.mprc -= bprc;
5306         adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5307         adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5308         adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5309         adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5310         adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5311         adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5312         adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5313         adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
5314         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
5315         adapter->stats.lxontxc += lxon;
5316         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
5317         adapter->stats.lxofftxc += lxoff;
5318         adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5319         adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5320         adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
5321         /*
5322          * 82598 errata - tx of flow control packets is included in tx counters
5323          */
5324         xon_off_tot = lxon + lxoff;
5325         adapter->stats.gptc -= xon_off_tot;
5326         adapter->stats.mptc -= xon_off_tot;
5327         adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5328         adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5329         adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5330         adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5331         adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5332         adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5333         adapter->stats.ptc64 -= xon_off_tot;
5334         adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5335         adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5336         adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5337         adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5338         adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5339         adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
5340
5341         /* Fill out the OS statistics structure */
5342         netdev->stats.multicast = adapter->stats.mprc;
5343
5344         /* Rx Errors */
5345         netdev->stats.rx_errors = adapter->stats.crcerrs +
5346                                        adapter->stats.rlec;
5347         netdev->stats.rx_dropped = 0;
5348         netdev->stats.rx_length_errors = adapter->stats.rlec;
5349         netdev->stats.rx_crc_errors = adapter->stats.crcerrs;
5350         netdev->stats.rx_missed_errors = total_mpc;
5351 }
5352
5353 /**
5354  * ixgbe_watchdog - Timer Call-back
5355  * @data: pointer to adapter cast into an unsigned long
5356  **/
5357 static void ixgbe_watchdog(unsigned long data)
5358 {
5359         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
5360         struct ixgbe_hw *hw = &adapter->hw;
5361         u64 eics = 0;
5362         int i;
5363
5364         /*
5365          *  Do the watchdog outside of interrupt context due to the lovely
5366          * delays that some of the newer hardware requires
5367          */
5368
5369         if (test_bit(__IXGBE_DOWN, &adapter->state))
5370                 goto watchdog_short_circuit;
5371
5372         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5373                 /*
5374                  * for legacy and MSI interrupts don't set any bits
5375                  * that are enabled for EIAM, because this operation
5376                  * would set *both* EIMS and EICS for any bit in EIAM
5377                  */
5378                 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5379                         (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
5380                 goto watchdog_reschedule;
5381         }
5382
5383         /* get one bit for every active tx/rx interrupt vector */
5384         for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
5385                 struct ixgbe_q_vector *qv = adapter->q_vector[i];
5386                 if (qv->rxr_count || qv->txr_count)
5387                         eics |= ((u64)1 << i);
5388         }
5389
5390         /* Cause software interrupt to ensure rx rings are cleaned */
5391         ixgbe_irq_rearm_queues(adapter, eics);
5392
5393 watchdog_reschedule:
5394         /* Reset the timer */
5395         mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ));
5396
5397 watchdog_short_circuit:
5398         schedule_work(&adapter->watchdog_task);
5399 }
5400
5401 /**
5402  * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
5403  * @work: pointer to work_struct containing our data
5404  **/
5405 static void ixgbe_multispeed_fiber_task(struct work_struct *work)
5406 {
5407         struct ixgbe_adapter *adapter = container_of(work,
5408                                                      struct ixgbe_adapter,
5409                                                      multispeed_fiber_task);
5410         struct ixgbe_hw *hw = &adapter->hw;
5411         u32 autoneg;
5412         bool negotiation;
5413
5414         adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
5415         autoneg = hw->phy.autoneg_advertised;
5416         if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
5417                 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
5418         hw->mac.autotry_restart = false;
5419         if (hw->mac.ops.setup_link)
5420                 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
5421         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5422         adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
5423 }
5424
5425 /**
5426  * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
5427  * @work: pointer to work_struct containing our data
5428  **/
5429 static void ixgbe_sfp_config_module_task(struct work_struct *work)
5430 {
5431         struct ixgbe_adapter *adapter = container_of(work,
5432                                                      struct ixgbe_adapter,
5433                                                      sfp_config_module_task);
5434         struct ixgbe_hw *hw = &adapter->hw;
5435         u32 err;
5436
5437         adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
5438
5439         /* Time for electrical oscillations to settle down */
5440         msleep(100);
5441         err = hw->phy.ops.identify_sfp(hw);
5442
5443         if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
5444                 dev_err(&adapter->pdev->dev, "failed to initialize because "
5445                         "an unsupported SFP+ module type was detected.\n"
5446                         "Reload the driver after installing a supported "
5447                         "module.\n");
5448                 unregister_netdev(adapter->netdev);
5449                 return;
5450         }
5451         hw->mac.ops.setup_sfp(hw);
5452
5453         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
5454                 /* This will also work for DA Twinax connections */
5455                 schedule_work(&adapter->multispeed_fiber_task);
5456         adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
5457 }
5458
5459 /**
5460  * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table
5461  * @work: pointer to work_struct containing our data
5462  **/
5463 static void ixgbe_fdir_reinit_task(struct work_struct *work)
5464 {
5465         struct ixgbe_adapter *adapter = container_of(work,
5466                                                      struct ixgbe_adapter,
5467                                                      fdir_reinit_task);
5468         struct ixgbe_hw *hw = &adapter->hw;
5469         int i;
5470
5471         if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5472                 for (i = 0; i < adapter->num_tx_queues; i++)
5473                         set_bit(__IXGBE_FDIR_INIT_DONE,
5474                                 &(adapter->tx_ring[i]->reinit_state));
5475         } else {
5476                 DPRINTK(PROBE, ERR, "failed to finish FDIR re-initialization, "
5477                         "ignored adding FDIR ATR filters\n");
5478         }
5479         /* Done FDIR Re-initialization, enable transmits */
5480         netif_tx_start_all_queues(adapter->netdev);
5481 }
5482
5483 static DEFINE_MUTEX(ixgbe_watchdog_lock);
5484
5485 /**
5486  * ixgbe_watchdog_task - worker thread to bring link up
5487  * @work: pointer to work_struct containing our data
5488  **/
5489 static void ixgbe_watchdog_task(struct work_struct *work)
5490 {
5491         struct ixgbe_adapter *adapter = container_of(work,
5492                                                      struct ixgbe_adapter,
5493                                                      watchdog_task);
5494         struct net_device *netdev = adapter->netdev;
5495         struct ixgbe_hw *hw = &adapter->hw;
5496         u32 link_speed;
5497         bool link_up;
5498         int i;
5499         struct ixgbe_ring *tx_ring;
5500         int some_tx_pending = 0;
5501
5502         mutex_lock(&ixgbe_watchdog_lock);
5503
5504         link_up = adapter->link_up;
5505         link_speed = adapter->link_speed;
5506
5507         if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
5508                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
5509                 if (link_up) {
5510 #ifdef CONFIG_DCB
5511                         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5512                                 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
5513                                         hw->mac.ops.fc_enable(hw, i);
5514                         } else {
5515                                 hw->mac.ops.fc_enable(hw, 0);
5516                         }
5517 #else
5518                         hw->mac.ops.fc_enable(hw, 0);
5519 #endif
5520                 }
5521
5522                 if (link_up ||
5523                     time_after(jiffies, (adapter->link_check_timeout +
5524                                          IXGBE_TRY_LINK_TIMEOUT))) {
5525                         adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5526                         IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
5527                 }
5528                 adapter->link_up = link_up;
5529                 adapter->link_speed = link_speed;
5530         }
5531
5532         if (link_up) {
5533                 if (!netif_carrier_ok(netdev)) {
5534                         bool flow_rx, flow_tx;
5535
5536                         if (hw->mac.type == ixgbe_mac_82599EB) {
5537                                 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5538                                 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
5539                                 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5540                                 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
5541                         } else {
5542                                 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5543                                 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
5544                                 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5545                                 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
5546                         }
5547
5548                         printk(KERN_INFO "ixgbe: %s NIC Link is Up %s, "
5549                                "Flow Control: %s\n",
5550                                netdev->name,
5551                                (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
5552                                 "10 Gbps" :
5553                                 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5554                                  "1 Gbps" : "unknown speed")),
5555                                ((flow_rx && flow_tx) ? "RX/TX" :
5556                                 (flow_rx ? "RX" :
5557                                 (flow_tx ? "TX" : "None"))));
5558
5559                         netif_carrier_on(netdev);
5560                 } else {
5561                         /* Force detection of hung controller */
5562                         adapter->detect_tx_hung = true;
5563                 }
5564         } else {
5565                 adapter->link_up = false;
5566                 adapter->link_speed = 0;
5567                 if (netif_carrier_ok(netdev)) {
5568                         printk(KERN_INFO "ixgbe: %s NIC Link is Down\n",
5569                                netdev->name);
5570                         netif_carrier_off(netdev);
5571                 }
5572         }
5573
5574         if (!netif_carrier_ok(netdev)) {
5575                 for (i = 0; i < adapter->num_tx_queues; i++) {
5576                         tx_ring = adapter->tx_ring[i];
5577                         if (tx_ring->next_to_use != tx_ring->next_to_clean) {
5578                                 some_tx_pending = 1;
5579                                 break;
5580                         }
5581                 }
5582
5583                 if (some_tx_pending) {
5584                         /* We've lost link, so the controller stops DMA,
5585                          * but we've got queued Tx work that's never going
5586                          * to get done, so reset controller to flush Tx.
5587                          * (Do the reset outside of interrupt context).
5588                          */
5589                          schedule_work(&adapter->reset_task);
5590                 }
5591         }
5592
5593         ixgbe_update_stats(adapter);
5594         mutex_unlock(&ixgbe_watchdog_lock);
5595 }
5596
5597 static int ixgbe_tso(struct ixgbe_adapter *adapter,
5598                      struct ixgbe_ring *tx_ring, struct sk_buff *skb,
5599                      u32 tx_flags, u8 *hdr_len)
5600 {
5601         struct ixgbe_adv_tx_context_desc *context_desc;
5602         unsigned int i;
5603         int err;
5604         struct ixgbe_tx_buffer *tx_buffer_info;
5605         u32 vlan_macip_lens = 0, type_tucmd_mlhl;
5606         u32 mss_l4len_idx, l4len;
5607
5608         if (skb_is_gso(skb)) {
5609                 if (skb_header_cloned(skb)) {
5610                         err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
5611                         if (err)
5612                                 return err;
5613                 }
5614                 l4len = tcp_hdrlen(skb);
5615                 *hdr_len += l4len;
5616
5617                 if (skb->protocol == htons(ETH_P_IP)) {
5618                         struct iphdr *iph = ip_hdr(skb);
5619                         iph->tot_len = 0;
5620                         iph->check = 0;
5621                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5622                                                                  iph->daddr, 0,
5623                                                                  IPPROTO_TCP,
5624                                                                  0);
5625                 } else if (skb_is_gso_v6(skb)) {
5626                         ipv6_hdr(skb)->payload_len = 0;
5627                         tcp_hdr(skb)->check =
5628                             ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
5629                                              &ipv6_hdr(skb)->daddr,
5630                                              0, IPPROTO_TCP, 0);
5631                 }
5632
5633                 i = tx_ring->next_to_use;
5634
5635                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5636                 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
5637
5638                 /* VLAN MACLEN IPLEN */
5639                 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5640                         vlan_macip_lens |=
5641                             (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
5642                 vlan_macip_lens |= ((skb_network_offset(skb)) <<
5643                                     IXGBE_ADVTXD_MACLEN_SHIFT);
5644                 *hdr_len += skb_network_offset(skb);
5645                 vlan_macip_lens |=
5646                     (skb_transport_header(skb) - skb_network_header(skb));
5647                 *hdr_len +=
5648                     (skb_transport_header(skb) - skb_network_header(skb));
5649                 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
5650                 context_desc->seqnum_seed = 0;
5651
5652                 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
5653                 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
5654                                    IXGBE_ADVTXD_DTYP_CTXT);
5655
5656                 if (skb->protocol == htons(ETH_P_IP))
5657                         type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
5658                 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
5659                 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
5660
5661                 /* MSS L4LEN IDX */
5662                 mss_l4len_idx =
5663                     (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
5664                 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
5665                 /* use index 1 for TSO */
5666                 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
5667                 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
5668
5669                 tx_buffer_info->time_stamp = jiffies;
5670                 tx_buffer_info->next_to_watch = i;
5671
5672                 i++;
5673                 if (i == tx_ring->count)
5674                         i = 0;
5675                 tx_ring->next_to_use = i;
5676
5677                 return true;
5678         }
5679         return false;
5680 }
5681
5682 static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
5683                           struct ixgbe_ring *tx_ring,
5684                           struct sk_buff *skb, u32 tx_flags)
5685 {
5686         struct ixgbe_adv_tx_context_desc *context_desc;
5687         unsigned int i;
5688         struct ixgbe_tx_buffer *tx_buffer_info;
5689         u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
5690
5691         if (skb->ip_summed == CHECKSUM_PARTIAL ||
5692             (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
5693                 i = tx_ring->next_to_use;
5694                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5695                 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
5696
5697                 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5698                         vlan_macip_lens |=
5699                             (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
5700                 vlan_macip_lens |= (skb_network_offset(skb) <<
5701                                     IXGBE_ADVTXD_MACLEN_SHIFT);
5702                 if (skb->ip_summed == CHECKSUM_PARTIAL)
5703                         vlan_macip_lens |= (skb_transport_header(skb) -
5704                                             skb_network_header(skb));
5705
5706                 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
5707                 context_desc->seqnum_seed = 0;
5708
5709                 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
5710                                     IXGBE_ADVTXD_DTYP_CTXT);
5711
5712                 if (skb->ip_summed == CHECKSUM_PARTIAL) {
5713                         __be16 protocol;
5714
5715                         if (skb->protocol == cpu_to_be16(ETH_P_8021Q)) {
5716                                 const struct vlan_ethhdr *vhdr =
5717                                         (const struct vlan_ethhdr *)skb->data;
5718
5719                                 protocol = vhdr->h_vlan_encapsulated_proto;
5720                         } else {
5721                                 protocol = skb->protocol;
5722                         }
5723
5724                         switch (protocol) {
5725                         case cpu_to_be16(ETH_P_IP):
5726                                 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
5727                                 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
5728                                         type_tucmd_mlhl |=
5729                                                 IXGBE_ADVTXD_TUCMD_L4T_TCP;
5730                                 else if (ip_hdr(skb)->protocol == IPPROTO_SCTP)
5731                                         type_tucmd_mlhl |=
5732                                                 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
5733                                 break;
5734                         case cpu_to_be16(ETH_P_IPV6):
5735                                 /* XXX what about other V6 headers?? */
5736                                 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
5737                                         type_tucmd_mlhl |=
5738                                                 IXGBE_ADVTXD_TUCMD_L4T_TCP;
5739                                 else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP)
5740                                         type_tucmd_mlhl |=
5741                                                 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
5742                                 break;
5743                         default:
5744                                 if (unlikely(net_ratelimit())) {
5745                                         DPRINTK(PROBE, WARNING,
5746                                          "partial checksum but proto=%x!\n",
5747                                          skb->protocol);
5748                                 }
5749                                 break;
5750                         }
5751                 }
5752
5753                 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
5754                 /* use index zero for tx checksum offload */
5755                 context_desc->mss_l4len_idx = 0;
5756
5757                 tx_buffer_info->time_stamp = jiffies;
5758                 tx_buffer_info->next_to_watch = i;
5759
5760                 i++;
5761                 if (i == tx_ring->count)
5762                         i = 0;
5763                 tx_ring->next_to_use = i;
5764
5765                 return true;
5766         }
5767
5768         return false;
5769 }
5770
5771 static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
5772                         struct ixgbe_ring *tx_ring,
5773                         struct sk_buff *skb, u32 tx_flags,
5774                         unsigned int first)
5775 {
5776         struct pci_dev *pdev = adapter->pdev;
5777         struct ixgbe_tx_buffer *tx_buffer_info;
5778         unsigned int len;
5779         unsigned int total = skb->len;
5780         unsigned int offset = 0, size, count = 0, i;
5781         unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
5782         unsigned int f;
5783
5784         i = tx_ring->next_to_use;
5785
5786         if (tx_flags & IXGBE_TX_FLAGS_FCOE)
5787                 /* excluding fcoe_crc_eof for FCoE */
5788                 total -= sizeof(struct fcoe_crc_eof);
5789
5790         len = min(skb_headlen(skb), total);
5791         while (len) {
5792                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5793                 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
5794
5795                 tx_buffer_info->length = size;
5796                 tx_buffer_info->mapped_as_page = false;
5797                 tx_buffer_info->dma = dma_map_single(&pdev->dev,
5798                                                      skb->data + offset,
5799                                                      size, DMA_TO_DEVICE);
5800                 if (dma_mapping_error(&pdev->dev, tx_buffer_info->dma))
5801                         goto dma_error;
5802                 tx_buffer_info->time_stamp = jiffies;
5803                 tx_buffer_info->next_to_watch = i;
5804
5805                 len -= size;
5806                 total -= size;
5807                 offset += size;
5808                 count++;
5809
5810                 if (len) {
5811                         i++;
5812                         if (i == tx_ring->count)
5813                                 i = 0;
5814                 }
5815         }
5816
5817         for (f = 0; f < nr_frags; f++) {
5818                 struct skb_frag_struct *frag;
5819
5820                 frag = &skb_shinfo(skb)->frags[f];
5821                 len = min((unsigned int)frag->size, total);
5822                 offset = frag->page_offset;
5823
5824                 while (len) {
5825                         i++;
5826                         if (i == tx_ring->count)
5827                                 i = 0;
5828
5829                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
5830                         size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
5831
5832                         tx_buffer_info->length = size;
5833                         tx_buffer_info->dma = dma_map_page(&adapter->pdev->dev,
5834                                                            frag->page,
5835                                                            offset, size,
5836                                                            DMA_TO_DEVICE);
5837                         tx_buffer_info->mapped_as_page = true;
5838                         if (dma_mapping_error(&pdev->dev, tx_buffer_info->dma))
5839                                 goto dma_error;
5840                         tx_buffer_info->time_stamp = jiffies;
5841                         tx_buffer_info->next_to_watch = i;
5842
5843                         len -= size;
5844                         total -= size;
5845                         offset += size;
5846                         count++;
5847                 }
5848                 if (total == 0)
5849                         break;
5850         }
5851
5852         tx_ring->tx_buffer_info[i].skb = skb;
5853         tx_ring->tx_buffer_info[first].next_to_watch = i;
5854
5855         return count;
5856
5857 dma_error:
5858         dev_err(&pdev->dev, "TX DMA map failed\n");
5859
5860         /* clear timestamp and dma mappings for failed tx_buffer_info map */
5861         tx_buffer_info->dma = 0;
5862         tx_buffer_info->time_stamp = 0;
5863         tx_buffer_info->next_to_watch = 0;
5864         if (count)
5865                 count--;
5866
5867         /* clear timestamp and dma mappings for remaining portion of packet */
5868         while (count--) {
5869                 if (i==0)
5870                         i += tx_ring->count;
5871                 i--;
5872                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5873                 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
5874         }
5875
5876         return 0;
5877 }
5878
5879 static void ixgbe_tx_queue(struct ixgbe_adapter *adapter,
5880                            struct ixgbe_ring *tx_ring,
5881                            int tx_flags, int count, u32 paylen, u8 hdr_len)
5882 {
5883         union ixgbe_adv_tx_desc *tx_desc = NULL;
5884         struct ixgbe_tx_buffer *tx_buffer_info;
5885         u32 olinfo_status = 0, cmd_type_len = 0;
5886         unsigned int i;
5887         u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
5888
5889         cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
5890
5891         cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
5892
5893         if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5894                 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
5895
5896         if (tx_flags & IXGBE_TX_FLAGS_TSO) {
5897                 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
5898
5899                 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
5900                                  IXGBE_ADVTXD_POPTS_SHIFT;
5901
5902                 /* use index 1 context for tso */
5903                 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
5904                 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
5905                         olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
5906                                          IXGBE_ADVTXD_POPTS_SHIFT;
5907
5908         } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
5909                 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
5910                                  IXGBE_ADVTXD_POPTS_SHIFT;
5911
5912         if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
5913                 olinfo_status |= IXGBE_ADVTXD_CC;
5914                 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
5915                 if (tx_flags & IXGBE_TX_FLAGS_FSO)
5916                         cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
5917         }
5918
5919         olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
5920
5921         i = tx_ring->next_to_use;
5922         while (count--) {
5923                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5924                 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
5925                 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
5926                 tx_desc->read.cmd_type_len =
5927                         cpu_to_le32(cmd_type_len | tx_buffer_info->length);
5928                 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
5929                 i++;
5930                 if (i == tx_ring->count)
5931                         i = 0;
5932         }
5933
5934         tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
5935
5936         /*
5937          * Force memory writes to complete before letting h/w
5938          * know there are new descriptors to fetch.  (Only
5939          * applicable for weak-ordered memory model archs,
5940          * such as IA-64).
5941          */
5942         wmb();
5943
5944         tx_ring->next_to_use = i;
5945         writel(i, adapter->hw.hw_addr + tx_ring->tail);
5946 }
5947
5948 static void ixgbe_atr(struct ixgbe_adapter *adapter, struct sk_buff *skb,
5949                       int queue, u32 tx_flags)
5950 {
5951         /* Right now, we support IPv4 only */
5952         struct ixgbe_atr_input atr_input;
5953         struct tcphdr *th;
5954         struct iphdr *iph = ip_hdr(skb);
5955         struct ethhdr *eth = (struct ethhdr *)skb->data;
5956         u16 vlan_id, src_port, dst_port, flex_bytes;
5957         u32 src_ipv4_addr, dst_ipv4_addr;
5958         u8 l4type = 0;
5959
5960         /* check if we're UDP or TCP */
5961         if (iph->protocol == IPPROTO_TCP) {
5962                 th = tcp_hdr(skb);
5963                 src_port = th->source;
5964                 dst_port = th->dest;
5965                 l4type |= IXGBE_ATR_L4TYPE_TCP;
5966                 /* l4type IPv4 type is 0, no need to assign */
5967         } else {
5968                 /* Unsupported L4 header, just bail here */
5969                 return;
5970         }
5971
5972         memset(&atr_input, 0, sizeof(struct ixgbe_atr_input));
5973
5974         vlan_id = (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK) >>
5975                    IXGBE_TX_FLAGS_VLAN_SHIFT;
5976         src_ipv4_addr = iph->saddr;
5977         dst_ipv4_addr = iph->daddr;
5978         flex_bytes = eth->h_proto;
5979
5980         ixgbe_atr_set_vlan_id_82599(&atr_input, vlan_id);
5981         ixgbe_atr_set_src_port_82599(&atr_input, dst_port);
5982         ixgbe_atr_set_dst_port_82599(&atr_input, src_port);
5983         ixgbe_atr_set_flex_byte_82599(&atr_input, flex_bytes);
5984         ixgbe_atr_set_l4type_82599(&atr_input, l4type);
5985         /* src and dst are inverted, think how the receiver sees them */
5986         ixgbe_atr_set_src_ipv4_82599(&atr_input, dst_ipv4_addr);
5987         ixgbe_atr_set_dst_ipv4_82599(&atr_input, src_ipv4_addr);
5988
5989         /* This assumes the Rx queue and Tx queue are bound to the same CPU */
5990         ixgbe_fdir_add_signature_filter_82599(&adapter->hw, &atr_input, queue);
5991 }
5992
5993 static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
5994                                  struct ixgbe_ring *tx_ring, int size)
5995 {
5996         netif_stop_subqueue(netdev, tx_ring->queue_index);
5997         /* Herbert's original patch had:
5998          *  smp_mb__after_netif_stop_queue();
5999          * but since that doesn't exist yet, just open code it. */
6000         smp_mb();
6001
6002         /* We need to check again in a case another CPU has just
6003          * made room available. */
6004         if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
6005                 return -EBUSY;
6006
6007         /* A reprieve! - use start_queue because it doesn't call schedule */
6008         netif_start_subqueue(netdev, tx_ring->queue_index);
6009         ++tx_ring->restart_queue;
6010         return 0;
6011 }
6012
6013 static int ixgbe_maybe_stop_tx(struct net_device *netdev,
6014                               struct ixgbe_ring *tx_ring, int size)
6015 {
6016         if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
6017                 return 0;
6018         return __ixgbe_maybe_stop_tx(netdev, tx_ring, size);
6019 }
6020
6021 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6022 {
6023         struct ixgbe_adapter *adapter = netdev_priv(dev);
6024         int txq = smp_processor_id();
6025
6026         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6027                 while (unlikely(txq >= dev->real_num_tx_queues))
6028                         txq -= dev->real_num_tx_queues;
6029                 return txq;
6030         }
6031
6032 #ifdef IXGBE_FCOE
6033         if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
6034             ((skb->protocol == htons(ETH_P_FCOE)) ||
6035              (skb->protocol == htons(ETH_P_FIP)))) {
6036                 txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
6037                 txq += adapter->ring_feature[RING_F_FCOE].mask;
6038                 return txq;
6039         }
6040 #endif
6041         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6042                 if (skb->priority == TC_PRIO_CONTROL)
6043                         txq = adapter->ring_feature[RING_F_DCB].indices-1;
6044                 else
6045                         txq = (skb->vlan_tci & IXGBE_TX_FLAGS_VLAN_PRIO_MASK)
6046                                >> 13;
6047                 return txq;
6048         }
6049
6050         return skb_tx_hash(dev, skb);
6051 }
6052
6053 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
6054                                     struct net_device *netdev)
6055 {
6056         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6057         struct ixgbe_ring *tx_ring;
6058         struct netdev_queue *txq;
6059         unsigned int first;
6060         unsigned int tx_flags = 0;
6061         u8 hdr_len = 0;
6062         int tso;
6063         int count = 0;
6064         unsigned int f;
6065
6066         if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
6067                 tx_flags |= vlan_tx_tag_get(skb);
6068                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6069                         tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
6070                         tx_flags |= ((skb->queue_mapping & 0x7) << 13);
6071                 }
6072                 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6073                 tx_flags |= IXGBE_TX_FLAGS_VLAN;
6074         } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6075                 tx_flags |= ((skb->queue_mapping & 0x7) << 13);
6076                 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6077                 tx_flags |= IXGBE_TX_FLAGS_VLAN;
6078         }
6079
6080         tx_ring = adapter->tx_ring[skb->queue_mapping];
6081
6082 #ifdef IXGBE_FCOE
6083         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
6084 #ifdef CONFIG_IXGBE_DCB
6085                 /* for FCoE with DCB, we force the priority to what
6086                  * was specified by the switch */
6087                 if ((skb->protocol == htons(ETH_P_FCOE)) ||
6088                     (skb->protocol == htons(ETH_P_FIP))) {
6089                         tx_flags &= ~(IXGBE_TX_FLAGS_VLAN_PRIO_MASK
6090                                       << IXGBE_TX_FLAGS_VLAN_SHIFT);
6091                         tx_flags |= ((adapter->fcoe.up << 13)
6092                                      << IXGBE_TX_FLAGS_VLAN_SHIFT);
6093                 }
6094 #endif
6095                 /* flag for FCoE offloads */
6096                 if (skb->protocol == htons(ETH_P_FCOE))
6097                         tx_flags |= IXGBE_TX_FLAGS_FCOE;
6098         }
6099 #endif
6100
6101         /* four things can cause us to need a context descriptor */
6102         if (skb_is_gso(skb) ||
6103             (skb->ip_summed == CHECKSUM_PARTIAL) ||
6104             (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
6105             (tx_flags & IXGBE_TX_FLAGS_FCOE))
6106                 count++;
6107
6108         count += TXD_USE_COUNT(skb_headlen(skb));
6109         for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6110                 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6111
6112         if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) {
6113                 adapter->tx_busy++;
6114                 return NETDEV_TX_BUSY;
6115         }
6116
6117         first = tx_ring->next_to_use;
6118         if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6119 #ifdef IXGBE_FCOE
6120                 /* setup tx offload for FCoE */
6121                 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
6122                 if (tso < 0) {
6123                         dev_kfree_skb_any(skb);
6124                         return NETDEV_TX_OK;
6125                 }
6126                 if (tso)
6127                         tx_flags |= IXGBE_TX_FLAGS_FSO;
6128 #endif /* IXGBE_FCOE */
6129         } else {
6130                 if (skb->protocol == htons(ETH_P_IP))
6131                         tx_flags |= IXGBE_TX_FLAGS_IPV4;
6132                 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len);
6133                 if (tso < 0) {
6134                         dev_kfree_skb_any(skb);
6135                         return NETDEV_TX_OK;
6136                 }
6137
6138                 if (tso)
6139                         tx_flags |= IXGBE_TX_FLAGS_TSO;
6140                 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) &&
6141                          (skb->ip_summed == CHECKSUM_PARTIAL))
6142                         tx_flags |= IXGBE_TX_FLAGS_CSUM;
6143         }
6144
6145         count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first);
6146         if (count) {
6147                 /* add the ATR filter if ATR is on */
6148                 if (tx_ring->atr_sample_rate) {
6149                         ++tx_ring->atr_count;
6150                         if ((tx_ring->atr_count >= tx_ring->atr_sample_rate) &&
6151                              test_bit(__IXGBE_FDIR_INIT_DONE,
6152                                       &tx_ring->reinit_state)) {
6153                                 ixgbe_atr(adapter, skb, tx_ring->queue_index,
6154                                           tx_flags);
6155                                 tx_ring->atr_count = 0;
6156                         }
6157                 }
6158                 txq = netdev_get_tx_queue(netdev, tx_ring->queue_index);
6159                 txq->tx_bytes += skb->len;
6160                 txq->tx_packets++;
6161                 ixgbe_tx_queue(adapter, tx_ring, tx_flags, count, skb->len,
6162                                hdr_len);
6163                 ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
6164
6165         } else {
6166                 dev_kfree_skb_any(skb);
6167                 tx_ring->tx_buffer_info[first].time_stamp = 0;
6168                 tx_ring->next_to_use = first;
6169         }
6170
6171         return NETDEV_TX_OK;
6172 }
6173
6174 /**
6175  * ixgbe_set_mac - Change the Ethernet Address of the NIC
6176  * @netdev: network interface device structure
6177  * @p: pointer to an address structure
6178  *
6179  * Returns 0 on success, negative on failure
6180  **/
6181 static int ixgbe_set_mac(struct net_device *netdev, void *p)
6182 {
6183         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6184         struct ixgbe_hw *hw = &adapter->hw;
6185         struct sockaddr *addr = p;
6186
6187         if (!is_valid_ether_addr(addr->sa_data))
6188                 return -EADDRNOTAVAIL;
6189
6190         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
6191         memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
6192
6193         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
6194                             IXGBE_RAH_AV);
6195
6196         return 0;
6197 }
6198
6199 static int
6200 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6201 {
6202         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6203         struct ixgbe_hw *hw = &adapter->hw;
6204         u16 value;
6205         int rc;
6206
6207         if (prtad != hw->phy.mdio.prtad)
6208                 return -EINVAL;
6209         rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6210         if (!rc)
6211                 rc = value;
6212         return rc;
6213 }
6214
6215 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6216                             u16 addr, u16 value)
6217 {
6218         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6219         struct ixgbe_hw *hw = &adapter->hw;
6220
6221         if (prtad != hw->phy.mdio.prtad)
6222                 return -EINVAL;
6223         return hw->phy.ops.write_reg(hw, addr, devad, value);
6224 }
6225
6226 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6227 {
6228         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6229
6230         return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6231 }
6232
6233 /**
6234  * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
6235  * netdev->dev_addrs
6236  * @netdev: network interface device structure
6237  *
6238  * Returns non-zero on failure
6239  **/
6240 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6241 {
6242         int err = 0;
6243         struct ixgbe_adapter *adapter = netdev_priv(dev);
6244         struct ixgbe_mac_info *mac = &adapter->hw.mac;
6245
6246         if (is_valid_ether_addr(mac->san_addr)) {
6247                 rtnl_lock();
6248                 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6249                 rtnl_unlock();
6250         }
6251         return err;
6252 }
6253
6254 /**
6255  * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
6256  * netdev->dev_addrs
6257  * @netdev: network interface device structure
6258  *
6259  * Returns non-zero on failure
6260  **/
6261 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6262 {
6263         int err = 0;
6264         struct ixgbe_adapter *adapter = netdev_priv(dev);
6265         struct ixgbe_mac_info *mac = &adapter->hw.mac;
6266
6267         if (is_valid_ether_addr(mac->san_addr)) {
6268                 rtnl_lock();
6269                 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6270                 rtnl_unlock();
6271         }
6272         return err;
6273 }
6274
6275 #ifdef CONFIG_NET_POLL_CONTROLLER
6276 /*
6277  * Polling 'interrupt' - used by things like netconsole to send skbs
6278  * without having to re-enable interrupts. It's not called while
6279  * the interrupt routine is executing.
6280  */
6281 static void ixgbe_netpoll(struct net_device *netdev)
6282 {
6283         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6284         int i;
6285
6286         /* if interface is down do nothing */
6287         if (test_bit(__IXGBE_DOWN, &adapter->state))
6288                 return;
6289
6290         adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
6291         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
6292                 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
6293                 for (i = 0; i < num_q_vectors; i++) {
6294                         struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
6295                         ixgbe_msix_clean_many(0, q_vector);
6296                 }
6297         } else {
6298                 ixgbe_intr(adapter->pdev->irq, netdev);
6299         }
6300         adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
6301 }
6302 #endif
6303
6304 static const struct net_device_ops ixgbe_netdev_ops = {
6305         .ndo_open               = ixgbe_open,
6306         .ndo_stop               = ixgbe_close,
6307         .ndo_start_xmit         = ixgbe_xmit_frame,
6308         .ndo_select_queue       = ixgbe_select_queue,
6309         .ndo_set_rx_mode        = ixgbe_set_rx_mode,
6310         .ndo_set_multicast_list = ixgbe_set_rx_mode,
6311         .ndo_validate_addr      = eth_validate_addr,
6312         .ndo_set_mac_address    = ixgbe_set_mac,
6313         .ndo_change_mtu         = ixgbe_change_mtu,
6314         .ndo_tx_timeout         = ixgbe_tx_timeout,
6315         .ndo_vlan_rx_register   = ixgbe_vlan_rx_register,
6316         .ndo_vlan_rx_add_vid    = ixgbe_vlan_rx_add_vid,
6317         .ndo_vlan_rx_kill_vid   = ixgbe_vlan_rx_kill_vid,
6318         .ndo_do_ioctl           = ixgbe_ioctl,
6319         .ndo_set_vf_mac         = ixgbe_ndo_set_vf_mac,
6320         .ndo_set_vf_vlan        = ixgbe_ndo_set_vf_vlan,
6321         .ndo_set_vf_tx_rate     = ixgbe_ndo_set_vf_bw,
6322         .ndo_get_vf_config      = ixgbe_ndo_get_vf_config,
6323 #ifdef CONFIG_NET_POLL_CONTROLLER
6324         .ndo_poll_controller    = ixgbe_netpoll,
6325 #endif
6326 #ifdef IXGBE_FCOE
6327         .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
6328         .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
6329         .ndo_fcoe_enable = ixgbe_fcoe_enable,
6330         .ndo_fcoe_disable = ixgbe_fcoe_disable,
6331         .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
6332 #endif /* IXGBE_FCOE */
6333 };
6334
6335 static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
6336                            const struct ixgbe_info *ii)
6337 {
6338 #ifdef CONFIG_PCI_IOV
6339         struct ixgbe_hw *hw = &adapter->hw;
6340         int err;
6341
6342         if (hw->mac.type != ixgbe_mac_82599EB || !max_vfs)
6343                 return;
6344
6345         /* The 82599 supports up to 64 VFs per physical function
6346          * but this implementation limits allocation to 63 so that
6347          * basic networking resources are still available to the
6348          * physical function
6349          */
6350         adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
6351         adapter->flags |= IXGBE_FLAG_SRIOV_ENABLED;
6352         err = pci_enable_sriov(adapter->pdev, adapter->num_vfs);
6353         if (err) {
6354                 DPRINTK(PROBE, ERR,
6355                         "Failed to enable PCI sriov: %d\n", err);
6356                 goto err_novfs;
6357         }
6358         /* If call to enable VFs succeeded then allocate memory
6359          * for per VF control structures.
6360          */
6361         adapter->vfinfo =
6362                 kcalloc(adapter->num_vfs,
6363                         sizeof(struct vf_data_storage), GFP_KERNEL);
6364         if (adapter->vfinfo) {
6365                 /* Now that we're sure SR-IOV is enabled
6366                  * and memory allocated set up the mailbox parameters
6367                  */
6368                 ixgbe_init_mbx_params_pf(hw);
6369                 memcpy(&hw->mbx.ops, ii->mbx_ops,
6370                        sizeof(hw->mbx.ops));
6371
6372                 /* Disable RSC when in SR-IOV mode */
6373                 adapter->flags2 &= ~(IXGBE_FLAG2_RSC_CAPABLE |
6374                                      IXGBE_FLAG2_RSC_ENABLED);
6375                 return;
6376         }
6377
6378         /* Oh oh */
6379         DPRINTK(PROBE, ERR,
6380                 "Unable to allocate memory for VF "
6381                 "Data Storage - SRIOV disabled\n");
6382         pci_disable_sriov(adapter->pdev);
6383
6384 err_novfs:
6385         adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
6386         adapter->num_vfs = 0;
6387 #endif /* CONFIG_PCI_IOV */
6388 }
6389
6390 /**
6391  * ixgbe_probe - Device Initialization Routine
6392  * @pdev: PCI device information struct
6393  * @ent: entry in ixgbe_pci_tbl
6394  *
6395  * Returns 0 on success, negative on failure
6396  *
6397  * ixgbe_probe initializes an adapter identified by a pci_dev structure.
6398  * The OS initialization, configuring of the adapter private structure,
6399  * and a hardware reset occur.
6400  **/
6401 static int __devinit ixgbe_probe(struct pci_dev *pdev,
6402                                  const struct pci_device_id *ent)
6403 {
6404         struct net_device *netdev;
6405         struct ixgbe_adapter *adapter = NULL;
6406         struct ixgbe_hw *hw;
6407         const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
6408         static int cards_found;
6409         int i, err, pci_using_dac;
6410         unsigned int indices = num_possible_cpus();
6411 #ifdef IXGBE_FCOE
6412         u16 device_caps;
6413 #endif
6414         u32 part_num, eec;
6415
6416         err = pci_enable_device_mem(pdev);
6417         if (err)
6418                 return err;
6419
6420         if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
6421             !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
6422                 pci_using_dac = 1;
6423         } else {
6424                 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
6425                 if (err) {
6426                         err = dma_set_coherent_mask(&pdev->dev,
6427                                                     DMA_BIT_MASK(32));
6428                         if (err) {
6429                                 dev_err(&pdev->dev, "No usable DMA "
6430                                         "configuration, aborting\n");
6431                                 goto err_dma;
6432                         }
6433                 }
6434                 pci_using_dac = 0;
6435         }
6436
6437         err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
6438                                            IORESOURCE_MEM), ixgbe_driver_name);
6439         if (err) {
6440                 dev_err(&pdev->dev,
6441                         "pci_request_selected_regions failed 0x%x\n", err);
6442                 goto err_pci_reg;
6443         }
6444
6445         pci_enable_pcie_error_reporting(pdev);
6446
6447         pci_set_master(pdev);
6448         pci_save_state(pdev);
6449
6450         if (ii->mac == ixgbe_mac_82598EB)
6451                 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
6452         else
6453                 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
6454
6455         indices = max_t(unsigned int, indices, IXGBE_MAX_DCB_INDICES);
6456 #ifdef IXGBE_FCOE
6457         indices += min_t(unsigned int, num_possible_cpus(),
6458                          IXGBE_MAX_FCOE_INDICES);
6459 #endif
6460         netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
6461         if (!netdev) {
6462                 err = -ENOMEM;
6463                 goto err_alloc_etherdev;
6464         }
6465
6466         SET_NETDEV_DEV(netdev, &pdev->dev);
6467
6468         pci_set_drvdata(pdev, netdev);
6469         adapter = netdev_priv(netdev);
6470
6471         adapter->netdev = netdev;
6472         adapter->pdev = pdev;
6473         hw = &adapter->hw;
6474         hw->back = adapter;
6475         adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
6476
6477         hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
6478                               pci_resource_len(pdev, 0));
6479         if (!hw->hw_addr) {
6480                 err = -EIO;
6481                 goto err_ioremap;
6482         }
6483
6484         for (i = 1; i <= 5; i++) {
6485                 if (pci_resource_len(pdev, i) == 0)
6486                         continue;
6487         }
6488
6489         netdev->netdev_ops = &ixgbe_netdev_ops;
6490         ixgbe_set_ethtool_ops(netdev);
6491         netdev->watchdog_timeo = 5 * HZ;
6492         strcpy(netdev->name, pci_name(pdev));
6493
6494         adapter->bd_number = cards_found;
6495
6496         /* Setup hw api */
6497         memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
6498         hw->mac.type  = ii->mac;
6499
6500         /* EEPROM */
6501         memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
6502         eec = IXGBE_READ_REG(hw, IXGBE_EEC);
6503         /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
6504         if (!(eec & (1 << 8)))
6505                 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
6506
6507         /* PHY */
6508         memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
6509         hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6510         /* ixgbe_identify_phy_generic will set prtad and mmds properly */
6511         hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
6512         hw->phy.mdio.mmds = 0;
6513         hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
6514         hw->phy.mdio.dev = netdev;
6515         hw->phy.mdio.mdio_read = ixgbe_mdio_read;
6516         hw->phy.mdio.mdio_write = ixgbe_mdio_write;
6517
6518         /* set up this timer and work struct before calling get_invariants
6519          * which might start the timer
6520          */
6521         init_timer(&adapter->sfp_timer);
6522         adapter->sfp_timer.function = &ixgbe_sfp_timer;
6523         adapter->sfp_timer.data = (unsigned long) adapter;
6524
6525         INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
6526
6527         /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
6528         INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
6529
6530         /* a new SFP+ module arrival, called from GPI SDP2 context */
6531         INIT_WORK(&adapter->sfp_config_module_task,
6532                   ixgbe_sfp_config_module_task);
6533
6534         ii->get_invariants(hw);
6535
6536         /* setup the private structure */
6537         err = ixgbe_sw_init(adapter);
6538         if (err)
6539                 goto err_sw_init;
6540
6541         /* Make it possible the adapter to be woken up via WOL */
6542         if (adapter->hw.mac.type == ixgbe_mac_82599EB)
6543                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6544
6545         /*
6546          * If there is a fan on this device and it has failed log the
6547          * failure.
6548          */
6549         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
6550                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
6551                 if (esdp & IXGBE_ESDP_SDP1)
6552                         DPRINTK(PROBE, CRIT,
6553                                 "Fan has stopped, replace the adapter\n");
6554         }
6555
6556         /* reset_hw fills in the perm_addr as well */
6557         err = hw->mac.ops.reset_hw(hw);
6558         if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
6559             hw->mac.type == ixgbe_mac_82598EB) {
6560                 /*
6561                  * Start a kernel thread to watch for a module to arrive.
6562                  * Only do this for 82598, since 82599 will generate
6563                  * interrupts on module arrival.
6564                  */
6565                 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
6566                 mod_timer(&adapter->sfp_timer,
6567                           round_jiffies(jiffies + (2 * HZ)));
6568                 err = 0;
6569         } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
6570                 dev_err(&adapter->pdev->dev, "failed to initialize because "
6571                         "an unsupported SFP+ module type was detected.\n"
6572                         "Reload the driver after installing a supported "
6573                         "module.\n");
6574                 goto err_sw_init;
6575         } else if (err) {
6576                 dev_err(&adapter->pdev->dev, "HW Init failed: %d\n", err);
6577                 goto err_sw_init;
6578         }
6579
6580         ixgbe_probe_vf(adapter, ii);
6581
6582         netdev->features = NETIF_F_SG |
6583                            NETIF_F_IP_CSUM |
6584                            NETIF_F_HW_VLAN_TX |
6585                            NETIF_F_HW_VLAN_RX |
6586                            NETIF_F_HW_VLAN_FILTER;
6587
6588         netdev->features |= NETIF_F_IPV6_CSUM;
6589         netdev->features |= NETIF_F_TSO;
6590         netdev->features |= NETIF_F_TSO6;
6591         netdev->features |= NETIF_F_GRO;
6592
6593         if (adapter->hw.mac.type == ixgbe_mac_82599EB)
6594                 netdev->features |= NETIF_F_SCTP_CSUM;
6595
6596         netdev->vlan_features |= NETIF_F_TSO;
6597         netdev->vlan_features |= NETIF_F_TSO6;
6598         netdev->vlan_features |= NETIF_F_IP_CSUM;
6599         netdev->vlan_features |= NETIF_F_IPV6_CSUM;
6600         netdev->vlan_features |= NETIF_F_SG;
6601
6602         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6603                 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
6604                                     IXGBE_FLAG_DCB_ENABLED);
6605         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
6606                 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
6607
6608 #ifdef CONFIG_IXGBE_DCB
6609         netdev->dcbnl_ops = &dcbnl_ops;
6610 #endif
6611
6612 #ifdef IXGBE_FCOE
6613         if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
6614                 if (hw->mac.ops.get_device_caps) {
6615                         hw->mac.ops.get_device_caps(hw, &device_caps);
6616                         if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
6617                                 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
6618                 }
6619         }
6620 #endif /* IXGBE_FCOE */
6621         if (pci_using_dac)
6622                 netdev->features |= NETIF_F_HIGHDMA;
6623
6624         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
6625                 netdev->features |= NETIF_F_LRO;
6626
6627         /* make sure the EEPROM is good */
6628         if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
6629                 dev_err(&pdev->dev, "The EEPROM Checksum Is Not Valid\n");
6630                 err = -EIO;
6631                 goto err_eeprom;
6632         }
6633
6634         memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
6635         memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
6636
6637         if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
6638                 dev_err(&pdev->dev, "invalid MAC address\n");
6639                 err = -EIO;
6640                 goto err_eeprom;
6641         }
6642
6643         /* power down the optics */
6644         if (hw->phy.multispeed_fiber)
6645                 hw->mac.ops.disable_tx_laser(hw);
6646
6647         init_timer(&adapter->watchdog_timer);
6648         adapter->watchdog_timer.function = &ixgbe_watchdog;
6649         adapter->watchdog_timer.data = (unsigned long)adapter;
6650
6651         INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
6652         INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
6653
6654         err = ixgbe_init_interrupt_scheme(adapter);
6655         if (err)
6656                 goto err_sw_init;
6657
6658         switch (pdev->device) {
6659         case IXGBE_DEV_ID_82599_KX4:
6660                 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
6661                                 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
6662                 break;
6663         default:
6664                 adapter->wol = 0;
6665                 break;
6666         }
6667         device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
6668
6669         /* pick up the PCI bus settings for reporting later */
6670         hw->mac.ops.get_bus_info(hw);
6671
6672         /* print bus type/speed/width info */
6673         dev_info(&pdev->dev, "(PCI Express:%s:%s) %pM\n",
6674                 ((hw->bus.speed == ixgbe_bus_speed_5000) ? "5.0Gb/s":
6675                  (hw->bus.speed == ixgbe_bus_speed_2500) ? "2.5Gb/s":"Unknown"),
6676                 ((hw->bus.width == ixgbe_bus_width_pcie_x8) ? "Width x8" :
6677                  (hw->bus.width == ixgbe_bus_width_pcie_x4) ? "Width x4" :
6678                  (hw->bus.width == ixgbe_bus_width_pcie_x1) ? "Width x1" :
6679                  "Unknown"),
6680                 netdev->dev_addr);
6681         ixgbe_read_pba_num_generic(hw, &part_num);
6682         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
6683                 dev_info(&pdev->dev, "MAC: %d, PHY: %d, SFP+: %d, PBA No: %06x-%03x\n",
6684                          hw->mac.type, hw->phy.type, hw->phy.sfp_type,
6685                          (part_num >> 8), (part_num & 0xff));
6686         else
6687                 dev_info(&pdev->dev, "MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
6688                          hw->mac.type, hw->phy.type,
6689                          (part_num >> 8), (part_num & 0xff));
6690
6691         if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
6692                 dev_warn(&pdev->dev, "PCI-Express bandwidth available for "
6693                          "this card is not sufficient for optimal "
6694                          "performance.\n");
6695                 dev_warn(&pdev->dev, "For optimal performance a x8 "
6696                          "PCI-Express slot is required.\n");
6697         }
6698
6699         /* save off EEPROM version number */
6700         hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
6701
6702         /* reset the hardware with the new settings */
6703         err = hw->mac.ops.start_hw(hw);
6704
6705         if (err == IXGBE_ERR_EEPROM_VERSION) {
6706                 /* We are running on a pre-production device, log a warning */
6707                 dev_warn(&pdev->dev, "This device is a pre-production "
6708                          "adapter/LOM.  Please be aware there may be issues "
6709                          "associated with your hardware.  If you are "
6710                          "experiencing problems please contact your Intel or "
6711                          "hardware representative who provided you with this "
6712                          "hardware.\n");
6713         }
6714         strcpy(netdev->name, "eth%d");
6715         err = register_netdev(netdev);
6716         if (err)
6717                 goto err_register;
6718
6719         /* carrier off reporting is important to ethtool even BEFORE open */
6720         netif_carrier_off(netdev);
6721
6722         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
6723             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
6724                 INIT_WORK(&adapter->fdir_reinit_task, ixgbe_fdir_reinit_task);
6725
6726 #ifdef CONFIG_IXGBE_DCA
6727         if (dca_add_requester(&pdev->dev) == 0) {
6728                 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
6729                 ixgbe_setup_dca(adapter);
6730         }
6731 #endif
6732         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
6733                 DPRINTK(PROBE, INFO, "IOV is enabled with %d VFs\n",
6734                         adapter->num_vfs);
6735                 for (i = 0; i < adapter->num_vfs; i++)
6736                         ixgbe_vf_configuration(pdev, (i | 0x10000000));
6737         }
6738
6739         /* add san mac addr to netdev */
6740         ixgbe_add_sanmac_netdev(netdev);
6741
6742         dev_info(&pdev->dev, "Intel(R) 10 Gigabit Network Connection\n");
6743         cards_found++;
6744         return 0;
6745
6746 err_register:
6747         ixgbe_release_hw_control(adapter);
6748         ixgbe_clear_interrupt_scheme(adapter);
6749 err_sw_init:
6750 err_eeprom:
6751         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6752                 ixgbe_disable_sriov(adapter);
6753         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
6754         del_timer_sync(&adapter->sfp_timer);
6755         cancel_work_sync(&adapter->sfp_task);
6756         cancel_work_sync(&adapter->multispeed_fiber_task);
6757         cancel_work_sync(&adapter->sfp_config_module_task);
6758         iounmap(hw->hw_addr);
6759 err_ioremap:
6760         free_netdev(netdev);
6761 err_alloc_etherdev:
6762         pci_release_selected_regions(pdev, pci_select_bars(pdev,
6763                                      IORESOURCE_MEM));
6764 err_pci_reg:
6765 err_dma:
6766         pci_disable_device(pdev);
6767         return err;
6768 }
6769
6770 /**
6771  * ixgbe_remove - Device Removal Routine
6772  * @pdev: PCI device information struct
6773  *
6774  * ixgbe_remove is called by the PCI subsystem to alert the driver
6775  * that it should release a PCI device.  The could be caused by a
6776  * Hot-Plug event, or because the driver is going to be removed from
6777  * memory.
6778  **/
6779 static void __devexit ixgbe_remove(struct pci_dev *pdev)
6780 {
6781         struct net_device *netdev = pci_get_drvdata(pdev);
6782         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6783
6784         set_bit(__IXGBE_DOWN, &adapter->state);
6785         /* clear the module not found bit to make sure the worker won't
6786          * reschedule
6787          */
6788         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
6789         del_timer_sync(&adapter->watchdog_timer);
6790
6791         del_timer_sync(&adapter->sfp_timer);
6792         cancel_work_sync(&adapter->watchdog_task);
6793         cancel_work_sync(&adapter->sfp_task);
6794         cancel_work_sync(&adapter->multispeed_fiber_task);
6795         cancel_work_sync(&adapter->sfp_config_module_task);
6796         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
6797             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
6798                 cancel_work_sync(&adapter->fdir_reinit_task);
6799         flush_scheduled_work();
6800
6801 #ifdef CONFIG_IXGBE_DCA
6802         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
6803                 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
6804                 dca_remove_requester(&pdev->dev);
6805                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
6806         }
6807
6808 #endif
6809 #ifdef IXGBE_FCOE
6810         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
6811                 ixgbe_cleanup_fcoe(adapter);
6812
6813 #endif /* IXGBE_FCOE */
6814
6815         /* remove the added san mac */
6816         ixgbe_del_sanmac_netdev(netdev);
6817
6818         if (netdev->reg_state == NETREG_REGISTERED)
6819                 unregister_netdev(netdev);
6820
6821         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6822                 ixgbe_disable_sriov(adapter);
6823
6824         ixgbe_clear_interrupt_scheme(adapter);
6825
6826         ixgbe_release_hw_control(adapter);
6827
6828         iounmap(adapter->hw.hw_addr);
6829         pci_release_selected_regions(pdev, pci_select_bars(pdev,
6830                                      IORESOURCE_MEM));
6831
6832         DPRINTK(PROBE, INFO, "complete\n");
6833
6834         free_netdev(netdev);
6835
6836         pci_disable_pcie_error_reporting(pdev);
6837
6838         pci_disable_device(pdev);
6839 }
6840
6841 /**
6842  * ixgbe_io_error_detected - called when PCI error is detected
6843  * @pdev: Pointer to PCI device
6844  * @state: The current pci connection state
6845  *
6846  * This function is called after a PCI bus error affecting
6847  * this device has been detected.
6848  */
6849 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
6850                                                 pci_channel_state_t state)
6851 {
6852         struct net_device *netdev = pci_get_drvdata(pdev);
6853         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6854
6855         netif_device_detach(netdev);
6856
6857         if (state == pci_channel_io_perm_failure)
6858                 return PCI_ERS_RESULT_DISCONNECT;
6859
6860         if (netif_running(netdev))
6861                 ixgbe_down(adapter);
6862         pci_disable_device(pdev);
6863
6864         /* Request a slot reset. */
6865         return PCI_ERS_RESULT_NEED_RESET;
6866 }
6867
6868 /**
6869  * ixgbe_io_slot_reset - called after the pci bus has been reset.
6870  * @pdev: Pointer to PCI device
6871  *
6872  * Restart the card from scratch, as if from a cold-boot.
6873  */
6874 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
6875 {
6876         struct net_device *netdev = pci_get_drvdata(pdev);
6877         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6878         pci_ers_result_t result;
6879         int err;
6880
6881         if (pci_enable_device_mem(pdev)) {
6882                 DPRINTK(PROBE, ERR,
6883                         "Cannot re-enable PCI device after reset.\n");
6884                 result = PCI_ERS_RESULT_DISCONNECT;
6885         } else {
6886                 pci_set_master(pdev);
6887                 pci_restore_state(pdev);
6888                 pci_save_state(pdev);
6889
6890                 pci_wake_from_d3(pdev, false);
6891
6892                 ixgbe_reset(adapter);
6893                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6894                 result = PCI_ERS_RESULT_RECOVERED;
6895         }
6896
6897         err = pci_cleanup_aer_uncorrect_error_status(pdev);
6898         if (err) {
6899                 dev_err(&pdev->dev,
6900                   "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", err);
6901                 /* non-fatal, continue */
6902         }
6903
6904         return result;
6905 }
6906
6907 /**
6908  * ixgbe_io_resume - called when traffic can start flowing again.
6909  * @pdev: Pointer to PCI device
6910  *
6911  * This callback is called when the error recovery driver tells us that
6912  * its OK to resume normal operation.
6913  */
6914 static void ixgbe_io_resume(struct pci_dev *pdev)
6915 {
6916         struct net_device *netdev = pci_get_drvdata(pdev);
6917         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6918
6919         if (netif_running(netdev)) {
6920                 if (ixgbe_up(adapter)) {
6921                         DPRINTK(PROBE, INFO, "ixgbe_up failed after reset\n");
6922                         return;
6923                 }
6924         }
6925
6926         netif_device_attach(netdev);
6927 }
6928
6929 static struct pci_error_handlers ixgbe_err_handler = {
6930         .error_detected = ixgbe_io_error_detected,
6931         .slot_reset = ixgbe_io_slot_reset,
6932         .resume = ixgbe_io_resume,
6933 };
6934
6935 static struct pci_driver ixgbe_driver = {
6936         .name     = ixgbe_driver_name,
6937         .id_table = ixgbe_pci_tbl,
6938         .probe    = ixgbe_probe,
6939         .remove   = __devexit_p(ixgbe_remove),
6940 #ifdef CONFIG_PM
6941         .suspend  = ixgbe_suspend,
6942         .resume   = ixgbe_resume,
6943 #endif
6944         .shutdown = ixgbe_shutdown,
6945         .err_handler = &ixgbe_err_handler
6946 };
6947
6948 /**
6949  * ixgbe_init_module - Driver Registration Routine
6950  *
6951  * ixgbe_init_module is the first routine called when the driver is
6952  * loaded. All it does is register with the PCI subsystem.
6953  **/
6954 static int __init ixgbe_init_module(void)
6955 {
6956         int ret;
6957         printk(KERN_INFO "%s: %s - version %s\n", ixgbe_driver_name,
6958                ixgbe_driver_string, ixgbe_driver_version);
6959
6960         printk(KERN_INFO "%s: %s\n", ixgbe_driver_name, ixgbe_copyright);
6961
6962 #ifdef CONFIG_IXGBE_DCA
6963         dca_register_notify(&dca_notifier);
6964 #endif
6965
6966         ret = pci_register_driver(&ixgbe_driver);
6967         return ret;
6968 }
6969
6970 module_init(ixgbe_init_module);
6971
6972 /**
6973  * ixgbe_exit_module - Driver Exit Cleanup Routine
6974  *
6975  * ixgbe_exit_module is called just before the driver is removed
6976  * from memory.
6977  **/
6978 static void __exit ixgbe_exit_module(void)
6979 {
6980 #ifdef CONFIG_IXGBE_DCA
6981         dca_unregister_notify(&dca_notifier);
6982 #endif
6983         pci_unregister_driver(&ixgbe_driver);
6984 }
6985
6986 #ifdef CONFIG_IXGBE_DCA
6987 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
6988                             void *p)
6989 {
6990         int ret_val;
6991
6992         ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
6993                                          __ixgbe_notify_dca);
6994
6995         return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
6996 }
6997
6998 #endif /* CONFIG_IXGBE_DCA */
6999 #ifdef DEBUG
7000 /**
7001  * ixgbe_get_hw_dev_name - return device name string
7002  * used by hardware layer to print debugging information
7003  **/
7004 char *ixgbe_get_hw_dev_name(struct ixgbe_hw *hw)
7005 {
7006         struct ixgbe_adapter *adapter = hw->back;
7007         return adapter->netdev->name;
7008 }
7009
7010 #endif
7011 module_exit(ixgbe_exit_module);
7012
7013 /* ixgbe_main.c */