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   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2010 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #include <linux/types.h>
  29 #include <linux/module.h>
  30 #include <linux/pci.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/vmalloc.h>
  33 #include <linux/string.h>
  34 #include <linux/in.h>
  35 #include <linux/ip.h>
  36 #include <linux/tcp.h>
  37 #include <linux/pkt_sched.h>
  38 #include <linux/ipv6.h>
  39 #include <linux/slab.h>
  40 #include <net/checksum.h>
  41 #include <net/ip6_checksum.h>
  42 #include <linux/ethtool.h>
  43 #include <linux/if_vlan.h>
  44 #include <scsi/fc/fc_fcoe.h>
  45
  46 #include "ixgbe.h"
  47 #include "ixgbe_common.h"
  48 #include "ixgbe_dcb_82599.h"
  49 #include "ixgbe_sriov.h"
  50
  51 char ixgbe_driver_name[] = "ixgbe";
  52 static const char ixgbe_driver_string[] =
  53                               "Intel(R) 10 Gigabit PCI Express Network Driver";
  54
  55 #define DRV_VERSION "2.0.62-k2"
  56 const char ixgbe_driver_version[] = DRV_VERSION;
  57 static char ixgbe_copyright[] = "Copyright (c) 1999-2010 Intel Corporation.";
  58
  59 static const struct ixgbe_info *ixgbe_info_tbl[] = {
  60         [board_82598] = &ixgbe_82598_info,
  61         [board_82599] = &ixgbe_82599_info,
  62 };
  63
  64 /* ixgbe_pci_tbl - PCI Device ID Table
  65  *
  66  * Wildcard entries (PCI_ANY_ID) should come last
  67  * Last entry must be all 0s
  68  *
  69  * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
  70  *   Class, Class Mask, private data (not used) }
  71  */
  72 static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
  73         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
  74          board_82598 },
  75         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
  76          board_82598 },
  77         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
  78          board_82598 },
  79         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
  80          board_82598 },
  81         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
  82          board_82598 },
  83         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
  84          board_82598 },
  85         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
  86          board_82598 },
  87         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
  88          board_82598 },
  89         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
  90          board_82598 },
  91         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
  92          board_82598 },
  93         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
  94          board_82598 },
  95         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
  96          board_82598 },
  97         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
  98          board_82599 },
  99         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
 100          board_82599 },
 101         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR),
 102          board_82599 },
 103         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
 104          board_82599 },
 105         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM),
 106          board_82599 },
 107         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ),
 108          board_82599 },
 109         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
 110          board_82599 },
 111         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE),
 112          board_82599 },
 113
 114         /* required last entry */
 115         {0, }
 116 };
 117 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
 118
 119 #ifdef CONFIG_IXGBE_DCA
 120 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
 121                             void *p);
 122 static struct notifier_block dca_notifier = {
 123         .notifier_call = ixgbe_notify_dca,
 124         .next          = NULL,
 125         .priority      = 0
 126 };
 127 #endif
 128
 129 #ifdef CONFIG_PCI_IOV
 130 static unsigned int max_vfs;
 131 module_param(max_vfs, uint, 0);
 132 MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate "
 133                  "per physical function");
 134 #endif /* CONFIG_PCI_IOV */
 135
 136 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
 137 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
 138 MODULE_LICENSE("GPL");
 139 MODULE_VERSION(DRV_VERSION);
 140
 141 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
 142
 143 static inline void ixgbe_disable_sriov(struct ixgbe_adapter *adapter)
 144 {
 145         struct ixgbe_hw *hw = &adapter->hw;
 146         u32 gcr;
 147         u32 gpie;
 148         u32 vmdctl;
 149
 150 #ifdef CONFIG_PCI_IOV
 151         /* disable iov and allow time for transactions to clear */
 152         pci_disable_sriov(adapter->pdev);
 153 #endif
 154
 155         /* turn off device IOV mode */
 156         gcr = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
 157         gcr &= ~(IXGBE_GCR_EXT_SRIOV);
 158         IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr);
 159         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
 160         gpie &= ~IXGBE_GPIE_VTMODE_MASK;
 161         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
 162
 163         /* set default pool back to 0 */
 164         vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
 165         vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
 166         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
 167
 168         /* take a breather then clean up driver data */
 169         msleep(100);
 170         if (adapter->vfinfo)
 171                 kfree(adapter->vfinfo);
 172         adapter->vfinfo = NULL;
 173
 174         adapter->num_vfs = 0;
 175         adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
 176 }
 177
 178 struct ixgbe_reg_info {
 179         u32 ofs;
 180         char *name;
 181 };
 182
 183 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
 184
 185         /* General Registers */
 186         {IXGBE_CTRL, "CTRL"},
 187         {IXGBE_STATUS, "STATUS"},
 188         {IXGBE_CTRL_EXT, "CTRL_EXT"},
 189
 190         /* Interrupt Registers */
 191         {IXGBE_EICR, "EICR"},
 192
 193         /* RX Registers */
 194         {IXGBE_SRRCTL(0), "SRRCTL"},
 195         {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
 196         {IXGBE_RDLEN(0), "RDLEN"},
 197         {IXGBE_RDH(0), "RDH"},
 198         {IXGBE_RDT(0), "RDT"},
 199         {IXGBE_RXDCTL(0), "RXDCTL"},
 200         {IXGBE_RDBAL(0), "RDBAL"},
 201         {IXGBE_RDBAH(0), "RDBAH"},
 202
 203         /* TX Registers */
 204         {IXGBE_TDBAL(0), "TDBAL"},
 205         {IXGBE_TDBAH(0), "TDBAH"},
 206         {IXGBE_TDLEN(0), "TDLEN"},
 207         {IXGBE_TDH(0), "TDH"},
 208         {IXGBE_TDT(0), "TDT"},
 209         {IXGBE_TXDCTL(0), "TXDCTL"},
 210
 211         /* List Terminator */
 212         {}
 213 };
 214
 215
 216 /*
 217  * ixgbe_regdump - register printout routine
 218  */
 219 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
 220 {
 221         int i = 0, j = 0;
 222         char rname[16];
 223         u32 regs[64];
 224
 225         switch (reginfo->ofs) {
 226         case IXGBE_SRRCTL(0):
 227                 for (i = 0; i < 64; i++)
 228                         regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
 229                 break;
 230         case IXGBE_DCA_RXCTRL(0):
 231                 for (i = 0; i < 64; i++)
 232                         regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
 233                 break;
 234         case IXGBE_RDLEN(0):
 235                 for (i = 0; i < 64; i++)
 236                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
 237                 break;
 238         case IXGBE_RDH(0):
 239                 for (i = 0; i < 64; i++)
 240                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
 241                 break;
 242         case IXGBE_RDT(0):
 243                 for (i = 0; i < 64; i++)
 244                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
 245                 break;
 246         case IXGBE_RXDCTL(0):
 247                 for (i = 0; i < 64; i++)
 248                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
 249                 break;
 250         case IXGBE_RDBAL(0):
 251                 for (i = 0; i < 64; i++)
 252                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
 253                 break;
 254         case IXGBE_RDBAH(0):
 255                 for (i = 0; i < 64; i++)
 256                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
 257                 break;
 258         case IXGBE_TDBAL(0):
 259                 for (i = 0; i < 64; i++)
 260                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
 261                 break;
 262         case IXGBE_TDBAH(0):
 263                 for (i = 0; i < 64; i++)
 264                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
 265                 break;
 266         case IXGBE_TDLEN(0):
 267                 for (i = 0; i < 64; i++)
 268                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
 269                 break;
 270         case IXGBE_TDH(0):
 271                 for (i = 0; i < 64; i++)
 272                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
 273                 break;
 274         case IXGBE_TDT(0):
 275                 for (i = 0; i < 64; i++)
 276                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
 277                 break;
 278         case IXGBE_TXDCTL(0):
 279                 for (i = 0; i < 64; i++)
 280                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
 281                 break;
 282         default:
 283                 printk(KERN_INFO "%-15s %08x\n", reginfo->name,
 284                         IXGBE_READ_REG(hw, reginfo->ofs));
 285                 return;
 286         }
 287
 288         for (i = 0; i < 8; i++) {
 289                 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
 290                 printk(KERN_ERR "%-15s ", rname);
 291                 for (j = 0; j < 8; j++)
 292                         printk(KERN_CONT "%08x ", regs[i*8+j]);
 293                 printk(KERN_CONT "\n");
 294         }
 295
 296 }
 297
 298 /*
 299  * ixgbe_dump - Print registers, tx-rings and rx-rings
 300  */
 301 static void ixgbe_dump(struct ixgbe_adapter *adapter)
 302 {
 303         struct net_device *netdev = adapter->netdev;
 304         struct ixgbe_hw *hw = &adapter->hw;
 305         struct ixgbe_reg_info *reginfo;
 306         int n = 0;
 307         struct ixgbe_ring *tx_ring;
 308         struct ixgbe_tx_buffer *tx_buffer_info;
 309         union ixgbe_adv_tx_desc *tx_desc;
 310         struct my_u0 { u64 a; u64 b; } *u0;
 311         struct ixgbe_ring *rx_ring;
 312         union ixgbe_adv_rx_desc *rx_desc;
 313         struct ixgbe_rx_buffer *rx_buffer_info;
 314         u32 staterr;
 315         int i = 0;
 316
 317         if (!netif_msg_hw(adapter))
 318                 return;
 319
 320         /* Print netdevice Info */
 321         if (netdev) {
 322                 dev_info(&adapter->pdev->dev, "Net device Info\n");
 323                 printk(KERN_INFO "Device Name     state            "
 324                         "trans_start      last_rx\n");
 325                 printk(KERN_INFO "%-15s %016lX %016lX %016lX\n",
 326                 netdev->name,
 327                 netdev->state,
 328                 netdev->trans_start,
 329                 netdev->last_rx);
 330         }
 331
 332         /* Print Registers */
 333         dev_info(&adapter->pdev->dev, "Register Dump\n");
 334         printk(KERN_INFO " Register Name   Value\n");
 335         for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
 336              reginfo->name; reginfo++) {
 337                 ixgbe_regdump(hw, reginfo);
 338         }
 339
 340         /* Print TX Ring Summary */
 341         if (!netdev || !netif_running(netdev))
 342                 goto exit;
 343
 344         dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
 345         printk(KERN_INFO "Queue [NTU] [NTC] [bi(ntc)->dma  ] "
 346                 "leng ntw timestamp\n");
 347         for (n = 0; n < adapter->num_tx_queues; n++) {
 348                 tx_ring = adapter->tx_ring[n];
 349                 tx_buffer_info =
 350                         &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
 351                 printk(KERN_INFO " %5d %5X %5X %016llX %04X %3X %016llX\n",
 352                            n, tx_ring->next_to_use, tx_ring->next_to_clean,
 353                            (u64)tx_buffer_info->dma,
 354                            tx_buffer_info->length,
 355                            tx_buffer_info->next_to_watch,
 356                            (u64)tx_buffer_info->time_stamp);
 357         }
 358
 359         /* Print TX Rings */
 360         if (!netif_msg_tx_done(adapter))
 361                 goto rx_ring_summary;
 362
 363         dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
 364
 365         /* Transmit Descriptor Formats
 366          *
 367          * Advanced Transmit Descriptor
 368          *   +--------------------------------------------------------------+
 369          * 0 |         Buffer Address [63:0]                                |
 370          *   +--------------------------------------------------------------+
 371          * 8 |  PAYLEN  | PORTS  | IDX | STA | DCMD  |DTYP |  RSV |  DTALEN |
 372          *   +--------------------------------------------------------------+
 373          *   63       46 45    40 39 36 35 32 31   24 23 20 19              0
 374          */
 375
 376         for (n = 0; n < adapter->num_tx_queues; n++) {
 377                 tx_ring = adapter->tx_ring[n];
 378                 printk(KERN_INFO "------------------------------------\n");
 379                 printk(KERN_INFO "TX QUEUE INDEX = %d\n", tx_ring->queue_index);
 380                 printk(KERN_INFO "------------------------------------\n");
 381                 printk(KERN_INFO "T [desc]     [address 63:0  ] "
 382                         "[PlPOIdStDDt Ln] [bi->dma       ] "
 383                         "leng  ntw timestamp        bi->skb\n");
 384
 385                 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
 386                         tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
 387                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
 388                         u0 = (struct my_u0 *)tx_desc;
 389                         printk(KERN_INFO "T [0x%03X]    %016llX %016llX %016llX"
 390                                 " %04X  %3X %016llX %p", i,
 391                                 le64_to_cpu(u0->a),
 392                                 le64_to_cpu(u0->b),
 393                                 (u64)tx_buffer_info->dma,
 394                                 tx_buffer_info->length,
 395                                 tx_buffer_info->next_to_watch,
 396                                 (u64)tx_buffer_info->time_stamp,
 397                                 tx_buffer_info->skb);
 398                         if (i == tx_ring->next_to_use &&
 399                                 i == tx_ring->next_to_clean)
 400                                 printk(KERN_CONT " NTC/U\n");
 401                         else if (i == tx_ring->next_to_use)
 402                                 printk(KERN_CONT " NTU\n");
 403                         else if (i == tx_ring->next_to_clean)
 404                                 printk(KERN_CONT " NTC\n");
 405                         else
 406                                 printk(KERN_CONT "\n");
 407
 408                         if (netif_msg_pktdata(adapter) &&
 409                                 tx_buffer_info->dma != 0)
 410                                 print_hex_dump(KERN_INFO, "",
 411                                         DUMP_PREFIX_ADDRESS, 16, 1,
 412                                         phys_to_virt(tx_buffer_info->dma),
 413                                         tx_buffer_info->length, true);
 414                 }
 415         }
 416
 417         /* Print RX Rings Summary */
 418 rx_ring_summary:
 419         dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
 420         printk(KERN_INFO "Queue [NTU] [NTC]\n");
 421         for (n = 0; n < adapter->num_rx_queues; n++) {
 422                 rx_ring = adapter->rx_ring[n];
 423                 printk(KERN_INFO "%5d %5X %5X\n", n,
 424                            rx_ring->next_to_use, rx_ring->next_to_clean);
 425         }
 426
 427         /* Print RX Rings */
 428         if (!netif_msg_rx_status(adapter))
 429                 goto exit;
 430
 431         dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
 432
 433         /* Advanced Receive Descriptor (Read) Format
 434          *    63                                           1        0
 435          *    +-----------------------------------------------------+
 436          *  0 |       Packet Buffer Address [63:1]           |A0/NSE|
 437          *    +----------------------------------------------+------+
 438          *  8 |       Header Buffer Address [63:1]           |  DD  |
 439          *    +-----------------------------------------------------+
 440          *
 441          *
 442          * Advanced Receive Descriptor (Write-Back) Format
 443          *
 444          *   63       48 47    32 31  30      21 20 16 15   4 3     0
 445          *   +------------------------------------------------------+
 446          * 0 | Packet     IP     |SPH| HDR_LEN   | RSV|Packet|  RSS |
 447          *   | Checksum   Ident  |   |           |    | Type | Type |
 448          *   +------------------------------------------------------+
 449          * 8 | VLAN Tag | Length | Extended Error | Extended Status |
 450          *   +------------------------------------------------------+
 451          *   63       48 47    32 31            20 19               0
 452          */
 453         for (n = 0; n < adapter->num_rx_queues; n++) {
 454                 rx_ring = adapter->rx_ring[n];
 455                 printk(KERN_INFO "------------------------------------\n");
 456                 printk(KERN_INFO "RX QUEUE INDEX = %d\n", rx_ring->queue_index);
 457                 printk(KERN_INFO "------------------------------------\n");
 458                 printk(KERN_INFO "R  [desc]      [ PktBuf     A0] "
 459                         "[  HeadBuf   DD] [bi->dma       ] [bi->skb] "
 460                         "<-- Adv Rx Read format\n");
 461                 printk(KERN_INFO "RWB[desc]      [PcsmIpSHl PtRs] "
 462                         "[vl er S cks ln] ---------------- [bi->skb] "
 463                         "<-- Adv Rx Write-Back format\n");
 464
 465                 for (i = 0; i < rx_ring->count; i++) {
 466                         rx_buffer_info = &rx_ring->rx_buffer_info[i];
 467                         rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
 468                         u0 = (struct my_u0 *)rx_desc;
 469                         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
 470                         if (staterr & IXGBE_RXD_STAT_DD) {
 471                                 /* Descriptor Done */
 472                                 printk(KERN_INFO "RWB[0x%03X]     %016llX "
 473                                         "%016llX ---------------- %p", i,
 474                                         le64_to_cpu(u0->a),
 475                                         le64_to_cpu(u0->b),
 476                                         rx_buffer_info->skb);
 477                         } else {
 478                                 printk(KERN_INFO "R  [0x%03X]     %016llX "
 479                                         "%016llX %016llX %p", i,
 480                                         le64_to_cpu(u0->a),
 481                                         le64_to_cpu(u0->b),
 482                                         (u64)rx_buffer_info->dma,
 483                                         rx_buffer_info->skb);
 484
 485                                 if (netif_msg_pktdata(adapter)) {
 486                                         print_hex_dump(KERN_INFO, "",
 487                                            DUMP_PREFIX_ADDRESS, 16, 1,
 488                                            phys_to_virt(rx_buffer_info->dma),
 489                                            rx_ring->rx_buf_len, true);
 490
 491                                         if (rx_ring->rx_buf_len
 492                                                 < IXGBE_RXBUFFER_2048)
 493                                                 print_hex_dump(KERN_INFO, "",
 494                                                   DUMP_PREFIX_ADDRESS, 16, 1,
 495                                                   phys_to_virt(
 496                                                     rx_buffer_info->page_dma +
 497                                                     rx_buffer_info->page_offset
 498                                                   ),
 499                                                   PAGE_SIZE/2, true);
 500                                 }
 501                         }
 502
 503                         if (i == rx_ring->next_to_use)
 504                                 printk(KERN_CONT " NTU\n");
 505                         else if (i == rx_ring->next_to_clean)
 506                                 printk(KERN_CONT " NTC\n");
 507                         else
 508                                 printk(KERN_CONT "\n");
 509
 510                 }
 511         }
 512
 513 exit:
 514         return;
 515 }
 516
 517 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
 518 {
 519         u32 ctrl_ext;
 520
 521         /* Let firmware take over control of h/w */
 522         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 523         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 524                         ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
 525 }
 526
 527 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
 528 {
 529         u32 ctrl_ext;
 530
 531         /* Let firmware know the driver has taken over */
 532         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 533         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 534                         ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
 535 }
 536
 537 /*
 538  * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
 539  * @adapter: pointer to adapter struct
 540  * @direction: 0 for Rx, 1 for Tx, -1 for other causes
 541  * @queue: queue to map the corresponding interrupt to
 542  * @msix_vector: the vector to map to the corresponding queue
 543  *
 544  */
 545 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
 546                            u8 queue, u8 msix_vector)
 547 {
 548         u32 ivar, index;
 549         struct ixgbe_hw *hw = &adapter->hw;
 550         switch (hw->mac.type) {
 551         case ixgbe_mac_82598EB:
 552                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 553                 if (direction == -1)
 554                         direction = 0;
 555                 index = (((direction * 64) + queue) >> 2) & 0x1F;
 556                 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
 557                 ivar &= ~(0xFF << (8 * (queue & 0x3)));
 558                 ivar |= (msix_vector << (8 * (queue & 0x3)));
 559                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
 560                 break;
 561         case ixgbe_mac_82599EB:
 562                 if (direction == -1) {
 563                         /* other causes */
 564                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 565                         index = ((queue & 1) * 8);
 566                         ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
 567                         ivar &= ~(0xFF << index);
 568                         ivar |= (msix_vector << index);
 569                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
 570                         break;
 571                 } else {
 572                         /* tx or rx causes */
 573                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 574                         index = ((16 * (queue & 1)) + (8 * direction));
 575                         ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
 576                         ivar &= ~(0xFF << index);
 577                         ivar |= (msix_vector << index);
 578                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
 579                         break;
 580                 }
 581         default:
 582                 break;
 583         }
 584 }
 585
 586 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
 587                                           u64 qmask)
 588 {
 589         u32 mask;
 590
 591         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 592                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
 593                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
 594         } else {
 595                 mask = (qmask & 0xFFFFFFFF);
 596                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
 597                 mask = (qmask >> 32);
 598                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
 599         }
 600 }
 601
 602 static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
 603                                              struct ixgbe_tx_buffer
 604                                              *tx_buffer_info)
 605 {
 606         if (tx_buffer_info->dma) {
 607                 if (tx_buffer_info->mapped_as_page)
 608                         dma_unmap_page(&adapter->pdev->dev,
 609                                        tx_buffer_info->dma,
 610                                        tx_buffer_info->length,
 611                                        DMA_TO_DEVICE);
 612                 else
 613                         dma_unmap_single(&adapter->pdev->dev,
 614                                          tx_buffer_info->dma,
 615                                          tx_buffer_info->length,
 616                                          DMA_TO_DEVICE);
 617                 tx_buffer_info->dma = 0;
 618         }
 619         if (tx_buffer_info->skb) {
 620                 dev_kfree_skb_any(tx_buffer_info->skb);
 621                 tx_buffer_info->skb = NULL;
 622         }
 623         tx_buffer_info->time_stamp = 0;
 624         /* tx_buffer_info must be completely set up in the transmit path */
 625 }
 626
 627 /**
 628  * ixgbe_tx_is_paused - check if the tx ring is paused
 629  * @adapter: the ixgbe adapter
 630  * @tx_ring: the corresponding tx_ring
 631  *
 632  * If not in DCB mode, checks TFCS.TXOFF, otherwise, find out the
 633  * corresponding TC of this tx_ring when checking TFCS.
 634  *
 635  * Returns : true if paused
 636  */
 637 static inline bool ixgbe_tx_is_paused(struct ixgbe_adapter *adapter,
 638                                       struct ixgbe_ring *tx_ring)
 639 {
 640         u32 txoff = IXGBE_TFCS_TXOFF;
 641
 642 #ifdef CONFIG_IXGBE_DCB
 643         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
 644                 int tc;
 645                 int reg_idx = tx_ring->reg_idx;
 646                 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
 647
 648                 switch (adapter->hw.mac.type) {
 649                 case ixgbe_mac_82598EB:
 650                         tc = reg_idx >> 2;
 651                         txoff = IXGBE_TFCS_TXOFF0;
 652                         break;
 653                 case ixgbe_mac_82599EB:
 654                         tc = 0;
 655                         txoff = IXGBE_TFCS_TXOFF;
 656                         if (dcb_i == 8) {
 657                                 /* TC0, TC1 */
 658                                 tc = reg_idx >> 5;
 659                                 if (tc == 2) /* TC2, TC3 */
 660                                         tc += (reg_idx - 64) >> 4;
 661                                 else if (tc == 3) /* TC4, TC5, TC6, TC7 */
 662                                         tc += 1 + ((reg_idx - 96) >> 3);
 663                         } else if (dcb_i == 4) {
 664                                 /* TC0, TC1 */
 665                                 tc = reg_idx >> 6;
 666                                 if (tc == 1) {
 667                                         tc += (reg_idx - 64) >> 5;
 668                                         if (tc == 2) /* TC2, TC3 */
 669                                                 tc += (reg_idx - 96) >> 4;
 670                                 }
 671                         }
 672                         break;
 673                 default:
 674                         tc = 0;
 675                 }
 676                 txoff <<= tc;
 677         }
 678 #endif
 679         return IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & txoff;
 680 }
 681
 682 static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
 683                                        struct ixgbe_ring *tx_ring,
 684                                        unsigned int eop)
 685 {
 686         struct ixgbe_hw *hw = &adapter->hw;
 687
 688         /* Detect a transmit hang in hardware, this serializes the
 689          * check with the clearing of time_stamp and movement of eop */
 690         adapter->detect_tx_hung = false;
 691         if (tx_ring->tx_buffer_info[eop].time_stamp &&
 692             time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
 693             !ixgbe_tx_is_paused(adapter, tx_ring)) {
 694                 /* detected Tx unit hang */
 695                 union ixgbe_adv_tx_desc *tx_desc;
 696                 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
 697                 DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
 698                         "  Tx Queue             <%d>\n"
 699                         "  TDH, TDT             <%x>, <%x>\n"
 700                         "  next_to_use          <%x>\n"
 701                         "  next_to_clean        <%x>\n"
 702                         "tx_buffer_info[next_to_clean]\n"
 703                         "  time_stamp           <%lx>\n"
 704                         "  jiffies              <%lx>\n",
 705                         tx_ring->queue_index,
 706                         IXGBE_READ_REG(hw, tx_ring->head),
 707                         IXGBE_READ_REG(hw, tx_ring->tail),
 708                         tx_ring->next_to_use, eop,
 709                         tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
 710                 return true;
 711         }
 712
 713         return false;
 714 }
 715
 716 #define IXGBE_MAX_TXD_PWR       14
 717 #define IXGBE_MAX_DATA_PER_TXD  (1 << IXGBE_MAX_TXD_PWR)
 718
 719 /* Tx Descriptors needed, worst case */
 720 #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
 721                          (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
 722 #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
 723         MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
 724
 725 static void ixgbe_tx_timeout(struct net_device *netdev);
 726
 727 /**
 728  * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
 729  * @q_vector: structure containing interrupt and ring information
 730  * @tx_ring: tx ring to clean
 731  **/
 732 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
 733                                struct ixgbe_ring *tx_ring)
 734 {
 735         struct ixgbe_adapter *adapter = q_vector->adapter;
 736         struct net_device *netdev = adapter->netdev;
 737         union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
 738         struct ixgbe_tx_buffer *tx_buffer_info;
 739         unsigned int i, eop, count = 0;
 740         unsigned int total_bytes = 0, total_packets = 0;
 741
 742         i = tx_ring->next_to_clean;
 743         eop = tx_ring->tx_buffer_info[i].next_to_watch;
 744         eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
 745
 746         while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
 747                (count < tx_ring->work_limit)) {
 748                 bool cleaned = false;
 749                 for ( ; !cleaned; count++) {
 750                         struct sk_buff *skb;
 751                         tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
 752                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
 753                         cleaned = (i == eop);
 754                         skb = tx_buffer_info->skb;
 755
 756                         if (cleaned && skb) {
 757                                 unsigned int segs, bytecount;
 758                                 unsigned int hlen = skb_headlen(skb);
 759
 760                                 /* gso_segs is currently only valid for tcp */
 761                                 segs = skb_shinfo(skb)->gso_segs ?: 1;
 762 #ifdef IXGBE_FCOE
 763                                 /* adjust for FCoE Sequence Offload */
 764                                 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
 765                                     && (skb->protocol == htons(ETH_P_FCOE)) &&
 766                                     skb_is_gso(skb)) {
 767                                         hlen = skb_transport_offset(skb) +
 768                                                 sizeof(struct fc_frame_header) +
 769                                                 sizeof(struct fcoe_crc_eof);
 770                                         segs = DIV_ROUND_UP(skb->len - hlen,
 771                                                 skb_shinfo(skb)->gso_size);
 772                                 }
 773 #endif /* IXGBE_FCOE */
 774                                 /* multiply data chunks by size of headers */
 775                                 bytecount = ((segs - 1) * hlen) + skb->len;
 776                                 total_packets += segs;
 777                                 total_bytes += bytecount;
 778                         }
 779
 780                         ixgbe_unmap_and_free_tx_resource(adapter,
 781                                                          tx_buffer_info);
 782
 783                         tx_desc->wb.status = 0;
 784
 785                         i++;
 786                         if (i == tx_ring->count)
 787                                 i = 0;
 788                 }
 789
 790                 eop = tx_ring->tx_buffer_info[i].next_to_watch;
 791                 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
 792         }
 793
 794         tx_ring->next_to_clean = i;
 795
 796 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
 797         if (unlikely(count && netif_carrier_ok(netdev) &&
 798                      (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
 799                 /* Make sure that anybody stopping the queue after this
 800                  * sees the new next_to_clean.
 801                  */
 802                 smp_mb();
 803                 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
 804                     !test_bit(__IXGBE_DOWN, &adapter->state)) {
 805                         netif_wake_subqueue(netdev, tx_ring->queue_index);
 806                         ++tx_ring->restart_queue;
 807                 }
 808         }
 809
 810         if (adapter->detect_tx_hung) {
 811                 if (ixgbe_check_tx_hang(adapter, tx_ring, i)) {
 812                         /* schedule immediate reset if we believe we hung */
 813                         DPRINTK(PROBE, INFO,
 814                                 "tx hang %d detected, resetting adapter\n",
 815                                 adapter->tx_timeout_count + 1);
 816                         ixgbe_tx_timeout(adapter->netdev);
 817                 }
 818         }
 819
 820         /* re-arm the interrupt */
 821         if (count >= tx_ring->work_limit)
 822                 ixgbe_irq_rearm_queues(adapter, ((u64)1 << q_vector->v_idx));
 823
 824         tx_ring->total_bytes += total_bytes;
 825         tx_ring->total_packets += total_packets;
 826         tx_ring->stats.packets += total_packets;
 827         tx_ring->stats.bytes += total_bytes;
 828         return (count < tx_ring->work_limit);
 829 }
 830
 831 #ifdef CONFIG_IXGBE_DCA
 832 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
 833                                 struct ixgbe_ring *rx_ring)
 834 {
 835         u32 rxctrl;
 836         int cpu = get_cpu();
 837         int q = rx_ring->reg_idx;
 838
 839         if (rx_ring->cpu != cpu) {
 840                 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
 841                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 842                         rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
 843                         rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 844                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
 845                         rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
 846                         rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
 847                                    IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
 848                 }
 849                 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
 850                 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
 851                 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
 852                 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
 853                             IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
 854                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
 855                 rx_ring->cpu = cpu;
 856         }
 857         put_cpu();
 858 }
 859
 860 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
 861                                 struct ixgbe_ring *tx_ring)
 862 {
 863         u32 txctrl;
 864         int cpu = get_cpu();
 865         int q = tx_ring->reg_idx;
 866         struct ixgbe_hw *hw = &adapter->hw;
 867
 868         if (tx_ring->cpu != cpu) {
 869                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 870                         txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(q));
 871                         txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
 872                         txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 873                         txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
 874                         IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(q), txctrl);
 875                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
 876                         txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(q));
 877                         txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
 878                         txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
 879                                   IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
 880                         txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
 881                         IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(q), txctrl);
 882                 }
 883                 tx_ring->cpu = cpu;
 884         }
 885         put_cpu();
 886 }
 887
 888 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
 889 {
 890         int i;
 891
 892         if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
 893                 return;
 894
 895         /* always use CB2 mode, difference is masked in the CB driver */
 896         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
 897
 898         for (i = 0; i < adapter->num_tx_queues; i++) {
 899                 adapter->tx_ring[i]->cpu = -1;
 900                 ixgbe_update_tx_dca(adapter, adapter->tx_ring[i]);
 901         }
 902         for (i = 0; i < adapter->num_rx_queues; i++) {
 903                 adapter->rx_ring[i]->cpu = -1;
 904                 ixgbe_update_rx_dca(adapter, adapter->rx_ring[i]);
 905         }
 906 }
 907
 908 static int __ixgbe_notify_dca(struct device *dev, void *data)
 909 {
 910         struct net_device *netdev = dev_get_drvdata(dev);
 911         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 912         unsigned long event = *(unsigned long *)data;
 913
 914         switch (event) {
 915         case DCA_PROVIDER_ADD:
 916                 /* if we're already enabled, don't do it again */
 917                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
 918                         break;
 919                 if (dca_add_requester(dev) == 0) {
 920                         adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
 921                         ixgbe_setup_dca(adapter);
 922                         break;
 923                 }
 924                 /* Fall Through since DCA is disabled. */
 925         case DCA_PROVIDER_REMOVE:
 926                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
 927                         dca_remove_requester(dev);
 928                         adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
 929                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
 930                 }
 931                 break;
 932         }
 933
 934         return 0;
 935 }
 936
 937 #endif /* CONFIG_IXGBE_DCA */
 938 /**
 939  * ixgbe_receive_skb - Send a completed packet up the stack
 940  * @adapter: board private structure
 941  * @skb: packet to send up
 942  * @status: hardware indication of status of receive
 943  * @rx_ring: rx descriptor ring (for a specific queue) to setup
 944  * @rx_desc: rx descriptor
 945  **/
 946 static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
 947                               struct sk_buff *skb, u8 status,
 948                               struct ixgbe_ring *ring,
 949                               union ixgbe_adv_rx_desc *rx_desc)
 950 {
 951         struct ixgbe_adapter *adapter = q_vector->adapter;
 952         struct napi_struct *napi = &q_vector->napi;
 953         bool is_vlan = (status & IXGBE_RXD_STAT_VP);
 954         u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
 955
 956         skb_record_rx_queue(skb, ring->queue_index);
 957         if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) {
 958                 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
 959                         vlan_gro_receive(napi, adapter->vlgrp, tag, skb);
 960                 else
 961                         napi_gro_receive(napi, skb);
 962         } else {
 963                 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
 964                         vlan_hwaccel_rx(skb, adapter->vlgrp, tag);
 965                 else
 966                         netif_rx(skb);
 967         }
 968 }
 969
 970 /**
 971  * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
 972  * @adapter: address of board private structure
 973  * @status_err: hardware indication of status of receive
 974  * @skb: skb currently being received and modified
 975  **/
 976 static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
 977                                      union ixgbe_adv_rx_desc *rx_desc,
 978                                      struct sk_buff *skb)
 979 {
 980         u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error);
 981
 982         skb->ip_summed = CHECKSUM_NONE;
 983
 984         /* Rx csum disabled */
 985         if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
 986                 return;
 987
 988         /* if IP and error */
 989         if ((status_err & IXGBE_RXD_STAT_IPCS) &&
 990             (status_err & IXGBE_RXDADV_ERR_IPE)) {
 991                 adapter->hw_csum_rx_error++;
 992                 return;
 993         }
 994
 995         if (!(status_err & IXGBE_RXD_STAT_L4CS))
 996                 return;
 997
 998         if (status_err & IXGBE_RXDADV_ERR_TCPE) {
 999                 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1000
1001                 /*
1002                  * 82599 errata, UDP frames with a 0 checksum can be marked as
1003                  * checksum errors.
1004                  */
1005                 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
1006                     (adapter->hw.mac.type == ixgbe_mac_82599EB))
1007                         return;
1008
1009                 adapter->hw_csum_rx_error++;
1010                 return;
1011         }
1012
1013         /* It must be a TCP or UDP packet with a valid checksum */
1014         skb->ip_summed = CHECKSUM_UNNECESSARY;
1015 }
1016
1017 static inline void ixgbe_release_rx_desc(struct ixgbe_hw *hw,
1018                                          struct ixgbe_ring *rx_ring, u32 val)
1019 {
1020         /*
1021          * Force memory writes to complete before letting h/w
1022          * know there are new descriptors to fetch.  (Only
1023          * applicable for weak-ordered memory model archs,
1024          * such as IA-64).
1025          */
1026         wmb();
1027         IXGBE_WRITE_REG(hw, IXGBE_RDT(rx_ring->reg_idx), val);
1028 }
1029
1030 /**
1031  * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
1032  * @adapter: address of board private structure
1033  **/
1034 static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
1035                                    struct ixgbe_ring *rx_ring,
1036                                    int cleaned_count)
1037 {
1038         struct pci_dev *pdev = adapter->pdev;
1039         union ixgbe_adv_rx_desc *rx_desc;
1040         struct ixgbe_rx_buffer *bi;
1041         unsigned int i;
1042
1043         i = rx_ring->next_to_use;
1044         bi = &rx_ring->rx_buffer_info[i];
1045
1046         while (cleaned_count--) {
1047                 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
1048
1049                 if (!bi->page_dma &&
1050                     (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)) {
1051                         if (!bi->page) {
1052                                 bi->page = alloc_page(GFP_ATOMIC);
1053                                 if (!bi->page) {
1054                                         adapter->alloc_rx_page_failed++;
1055                                         goto no_buffers;
1056                                 }
1057                                 bi->page_offset = 0;
1058                         } else {
1059                                 /* use a half page if we're re-using */
1060                                 bi->page_offset ^= (PAGE_SIZE / 2);
1061                         }
1062
1063                         bi->page_dma = dma_map_page(&pdev->dev, bi->page,
1064                                                     bi->page_offset,
1065                                                     (PAGE_SIZE / 2),
1066                                                     DMA_FROM_DEVICE);
1067                 }
1068
1069                 if (!bi->skb) {
1070                         struct sk_buff *skb;
1071                         /* netdev_alloc_skb reserves 32 bytes up front!! */
1072                         uint bufsz = rx_ring->rx_buf_len + SMP_CACHE_BYTES;
1073                         skb = netdev_alloc_skb(adapter->netdev, bufsz);
1074
1075                         if (!skb) {
1076                                 adapter->alloc_rx_buff_failed++;
1077                                 goto no_buffers;
1078                         }
1079
1080                         /* advance the data pointer to the next cache line */
1081                         skb_reserve(skb, (PTR_ALIGN(skb->data, SMP_CACHE_BYTES)
1082                                           - skb->data));
1083
1084                         bi->skb = skb;
1085                         bi->dma = dma_map_single(&pdev->dev, skb->data,
1086                                                  rx_ring->rx_buf_len,
1087                                                  DMA_FROM_DEVICE);
1088                 }
1089                 /* Refresh the desc even if buffer_addrs didn't change because
1090                  * each write-back erases this info. */
1091                 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
1092                         rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
1093                         rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
1094                 } else {
1095                         rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
1096                 }
1097
1098                 i++;
1099                 if (i == rx_ring->count)
1100                         i = 0;
1101                 bi = &rx_ring->rx_buffer_info[i];
1102         }
1103
1104 no_buffers:
1105         if (rx_ring->next_to_use != i) {
1106                 rx_ring->next_to_use = i;
1107                 if (i-- == 0)
1108                         i = (rx_ring->count - 1);
1109
1110                 ixgbe_release_rx_desc(&adapter->hw, rx_ring, i);
1111         }
1112 }
1113
1114 static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
1115 {
1116         return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
1117 }
1118
1119 static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
1120 {
1121         return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1122 }
1123
1124 static inline u32 ixgbe_get_rsc_count(union ixgbe_adv_rx_desc *rx_desc)
1125 {
1126         return (le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
1127                 IXGBE_RXDADV_RSCCNT_MASK) >>
1128                 IXGBE_RXDADV_RSCCNT_SHIFT;
1129 }
1130
1131 /**
1132  * ixgbe_transform_rsc_queue - change rsc queue into a full packet
1133  * @skb: pointer to the last skb in the rsc queue
1134  * @count: pointer to number of packets coalesced in this context
1135  *
1136  * This function changes a queue full of hw rsc buffers into a completed
1137  * packet.  It uses the ->prev pointers to find the first packet and then
1138  * turns it into the frag list owner.
1139  **/
1140 static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb,
1141                                                         u64 *count)
1142 {
1143         unsigned int frag_list_size = 0;
1144
1145         while (skb->prev) {
1146                 struct sk_buff *prev = skb->prev;
1147                 frag_list_size += skb->len;
1148                 skb->prev = NULL;
1149                 skb = prev;
1150                 *count += 1;
1151         }
1152
1153         skb_shinfo(skb)->frag_list = skb->next;
1154         skb->next = NULL;
1155         skb->len += frag_list_size;
1156         skb->data_len += frag_list_size;
1157         skb->truesize += frag_list_size;
1158         return skb;
1159 }
1160
1161 struct ixgbe_rsc_cb {
1162         dma_addr_t dma;
1163 };
1164
1165 #define IXGBE_RSC_CB(skb) ((struct ixgbe_rsc_cb *)(skb)->cb)
1166
1167 static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
1168                                struct ixgbe_ring *rx_ring,
1169                                int *work_done, int work_to_do)
1170 {
1171         struct ixgbe_adapter *adapter = q_vector->adapter;
1172         struct net_device *netdev = adapter->netdev;
1173         struct pci_dev *pdev = adapter->pdev;
1174         union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
1175         struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
1176         struct sk_buff *skb;
1177         unsigned int i, rsc_count = 0;
1178         u32 len, staterr;
1179         u16 hdr_info;
1180         bool cleaned = false;
1181         int cleaned_count = 0;
1182         unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1183 #ifdef IXGBE_FCOE
1184         int ddp_bytes = 0;
1185 #endif /* IXGBE_FCOE */
1186
1187         i = rx_ring->next_to_clean;
1188         rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
1189         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1190         rx_buffer_info = &rx_ring->rx_buffer_info[i];
1191
1192         while (staterr & IXGBE_RXD_STAT_DD) {
1193                 u32 upper_len = 0;
1194                 if (*work_done >= work_to_do)
1195                         break;
1196                 (*work_done)++;
1197
1198                 rmb(); /* read descriptor and rx_buffer_info after status DD */
1199                 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
1200                         hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
1201                         len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
1202                                IXGBE_RXDADV_HDRBUFLEN_SHIFT;
1203                         if (len > IXGBE_RX_HDR_SIZE)
1204                                 len = IXGBE_RX_HDR_SIZE;
1205                         upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1206                 } else {
1207                         len = le16_to_cpu(rx_desc->wb.upper.length);
1208                 }
1209
1210                 cleaned = true;
1211                 skb = rx_buffer_info->skb;
1212                 prefetch(skb->data);
1213                 rx_buffer_info->skb = NULL;
1214
1215                 if (rx_buffer_info->dma) {
1216                         if ((adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
1217                             (!(staterr & IXGBE_RXD_STAT_EOP)) &&
1218                                  (!(skb->prev)))
1219                                 /*
1220                                  * When HWRSC is enabled, delay unmapping
1221                                  * of the first packet. It carries the
1222                                  * header information, HW may still
1223                                  * access the header after the writeback.
1224                                  * Only unmap it when EOP is reached
1225                                  */
1226                                 IXGBE_RSC_CB(skb)->dma = rx_buffer_info->dma;
1227                         else
1228                                 dma_unmap_single(&pdev->dev,
1229                                                  rx_buffer_info->dma,
1230                                                  rx_ring->rx_buf_len,
1231                                                  DMA_FROM_DEVICE);
1232                         rx_buffer_info->dma = 0;
1233                         skb_put(skb, len);
1234                 }
1235
1236                 if (upper_len) {
1237                         dma_unmap_page(&pdev->dev, rx_buffer_info->page_dma,
1238                                        PAGE_SIZE / 2, DMA_FROM_DEVICE);
1239                         rx_buffer_info->page_dma = 0;
1240                         skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
1241                                            rx_buffer_info->page,
1242                                            rx_buffer_info->page_offset,
1243                                            upper_len);
1244
1245                         if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
1246                             (page_count(rx_buffer_info->page) != 1))
1247                                 rx_buffer_info->page = NULL;
1248                         else
1249                                 get_page(rx_buffer_info->page);
1250
1251                         skb->len += upper_len;
1252                         skb->data_len += upper_len;
1253                         skb->truesize += upper_len;
1254                 }
1255
1256                 i++;
1257                 if (i == rx_ring->count)
1258                         i = 0;
1259
1260                 next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i);
1261                 prefetch(next_rxd);
1262                 cleaned_count++;
1263
1264                 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
1265                         rsc_count = ixgbe_get_rsc_count(rx_desc);
1266
1267                 if (rsc_count) {
1268                         u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
1269                                      IXGBE_RXDADV_NEXTP_SHIFT;
1270                         next_buffer = &rx_ring->rx_buffer_info[nextp];
1271                 } else {
1272                         next_buffer = &rx_ring->rx_buffer_info[i];
1273                 }
1274
1275                 if (staterr & IXGBE_RXD_STAT_EOP) {
1276                         if (skb->prev)
1277                                 skb = ixgbe_transform_rsc_queue(skb, &(rx_ring->rsc_count));
1278                         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
1279                                 if (IXGBE_RSC_CB(skb)->dma) {
1280                                         dma_unmap_single(&pdev->dev,
1281                                                          IXGBE_RSC_CB(skb)->dma,
1282                                                          rx_ring->rx_buf_len,
1283                                                          DMA_FROM_DEVICE);
1284                                         IXGBE_RSC_CB(skb)->dma = 0;
1285                                 }
1286                                 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)
1287                                         rx_ring->rsc_count += skb_shinfo(skb)->nr_frags;
1288                                 else
1289                                         rx_ring->rsc_count++;
1290                                 rx_ring->rsc_flush++;
1291                         }
1292                         rx_ring->stats.packets++;
1293                         rx_ring->stats.bytes += skb->len;
1294                 } else {
1295                         if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
1296                                 rx_buffer_info->skb = next_buffer->skb;
1297                                 rx_buffer_info->dma = next_buffer->dma;
1298                                 next_buffer->skb = skb;
1299                                 next_buffer->dma = 0;
1300                         } else {
1301                                 skb->next = next_buffer->skb;
1302                                 skb->next->prev = skb;
1303                         }
1304                         rx_ring->non_eop_descs++;
1305                         goto next_desc;
1306                 }
1307
1308                 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
1309                         dev_kfree_skb_irq(skb);
1310                         goto next_desc;
1311                 }
1312
1313                 ixgbe_rx_checksum(adapter, rx_desc, skb);
1314
1315                 /* probably a little skewed due to removing CRC */
1316                 total_rx_bytes += skb->len;
1317                 total_rx_packets++;
1318
1319                 skb->protocol = eth_type_trans(skb, adapter->netdev);
1320 #ifdef IXGBE_FCOE
1321                 /* if ddp, not passing to ULD unless for FCP_RSP or error */
1322                 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
1323                         ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
1324                         if (!ddp_bytes)
1325                                 goto next_desc;
1326                 }
1327 #endif /* IXGBE_FCOE */
1328                 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
1329
1330 next_desc:
1331                 rx_desc->wb.upper.status_error = 0;
1332
1333                 /* return some buffers to hardware, one at a time is too slow */
1334                 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
1335                         ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
1336                         cleaned_count = 0;
1337                 }
1338
1339                 /* use prefetched values */
1340                 rx_desc = next_rxd;
1341                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
1342
1343                 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1344         }
1345
1346         rx_ring->next_to_clean = i;
1347         cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
1348
1349         if (cleaned_count)
1350                 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
1351
1352 #ifdef IXGBE_FCOE
1353         /* include DDPed FCoE data */
1354         if (ddp_bytes > 0) {
1355                 unsigned int mss;
1356
1357                 mss = adapter->netdev->mtu - sizeof(struct fcoe_hdr) -
1358                         sizeof(struct fc_frame_header) -
1359                         sizeof(struct fcoe_crc_eof);
1360                 if (mss > 512)
1361                         mss &= ~511;
1362                 total_rx_bytes += ddp_bytes;
1363                 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1364         }
1365 #endif /* IXGBE_FCOE */
1366
1367         rx_ring->total_packets += total_rx_packets;
1368         rx_ring->total_bytes += total_rx_bytes;
1369         netdev->stats.rx_bytes += total_rx_bytes;
1370         netdev->stats.rx_packets += total_rx_packets;
1371
1372         return cleaned;
1373 }
1374
1375 static int ixgbe_clean_rxonly(struct napi_struct *, int);
1376 /**
1377  * ixgbe_configure_msix - Configure MSI-X hardware
1378  * @adapter: board private structure
1379  *
1380  * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1381  * interrupts.
1382  **/
1383 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1384 {
1385         struct ixgbe_q_vector *q_vector;
1386         int i, j, q_vectors, v_idx, r_idx;
1387         u32 mask;
1388
1389         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1390
1391         /*
1392          * Populate the IVAR table and set the ITR values to the
1393          * corresponding register.
1394          */
1395         for (v_idx = 0; v_idx < q_vectors; v_idx++) {
1396                 q_vector = adapter->q_vector[v_idx];
1397                 /* XXX for_each_set_bit(...) */
1398                 r_idx = find_first_bit(q_vector->rxr_idx,
1399                                        adapter->num_rx_queues);
1400
1401                 for (i = 0; i < q_vector->rxr_count; i++) {
1402                         j = adapter->rx_ring[r_idx]->reg_idx;
1403                         ixgbe_set_ivar(adapter, 0, j, v_idx);
1404                         r_idx = find_next_bit(q_vector->rxr_idx,
1405                                               adapter->num_rx_queues,
1406                                               r_idx + 1);
1407                 }
1408                 r_idx = find_first_bit(q_vector->txr_idx,
1409                                        adapter->num_tx_queues);
1410
1411                 for (i = 0; i < q_vector->txr_count; i++) {
1412                         j = adapter->tx_ring[r_idx]->reg_idx;
1413                         ixgbe_set_ivar(adapter, 1, j, v_idx);
1414                         r_idx = find_next_bit(q_vector->txr_idx,
1415                                               adapter->num_tx_queues,
1416                                               r_idx + 1);
1417                 }
1418
1419                 if (q_vector->txr_count && !q_vector->rxr_count)
1420                         /* tx only */
1421                         q_vector->eitr = adapter->tx_eitr_param;
1422                 else if (q_vector->rxr_count)
1423                         /* rx or mixed */
1424                         q_vector->eitr = adapter->rx_eitr_param;
1425
1426                 ixgbe_write_eitr(q_vector);
1427         }
1428
1429         if (adapter->hw.mac.type == ixgbe_mac_82598EB)
1430                 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
1431                                v_idx);
1432         else if (adapter->hw.mac.type == ixgbe_mac_82599EB)
1433                 ixgbe_set_ivar(adapter, -1, 1, v_idx);
1434         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1435
1436         /* set up to autoclear timer, and the vectors */
1437         mask = IXGBE_EIMS_ENABLE_MASK;
1438         if (adapter->num_vfs)
1439                 mask &= ~(IXGBE_EIMS_OTHER |
1440                           IXGBE_EIMS_MAILBOX |
1441                           IXGBE_EIMS_LSC);
1442         else
1443                 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
1444         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
1445 }
1446
1447 enum latency_range {
1448         lowest_latency = 0,
1449         low_latency = 1,
1450         bulk_latency = 2,
1451         latency_invalid = 255
1452 };
1453
1454 /**
1455  * ixgbe_update_itr - update the dynamic ITR value based on statistics
1456  * @adapter: pointer to adapter
1457  * @eitr: eitr setting (ints per sec) to give last timeslice
1458  * @itr_setting: current throttle rate in ints/second
1459  * @packets: the number of packets during this measurement interval
1460  * @bytes: the number of bytes during this measurement interval
1461  *
1462  *      Stores a new ITR value based on packets and byte
1463  *      counts during the last interrupt.  The advantage of per interrupt
1464  *      computation is faster updates and more accurate ITR for the current
1465  *      traffic pattern.  Constants in this function were computed
1466  *      based on theoretical maximum wire speed and thresholds were set based
1467  *      on testing data as well as attempting to minimize response time
1468  *      while increasing bulk throughput.
1469  *      this functionality is controlled by the InterruptThrottleRate module
1470  *      parameter (see ixgbe_param.c)
1471  **/
1472 static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
1473                            u32 eitr, u8 itr_setting,
1474                            int packets, int bytes)
1475 {
1476         unsigned int retval = itr_setting;
1477         u32 timepassed_us;
1478         u64 bytes_perint;
1479
1480         if (packets == 0)
1481                 goto update_itr_done;
1482
1483
1484         /* simple throttlerate management
1485          *    0-20MB/s lowest (100000 ints/s)
1486          *   20-100MB/s low   (20000 ints/s)
1487          *  100-1249MB/s bulk (8000 ints/s)
1488          */
1489         /* what was last interrupt timeslice? */
1490         timepassed_us = 1000000/eitr;
1491         bytes_perint = bytes / timepassed_us; /* bytes/usec */
1492
1493         switch (itr_setting) {
1494         case lowest_latency:
1495                 if (bytes_perint > adapter->eitr_low)
1496                         retval = low_latency;
1497                 break;
1498         case low_latency:
1499                 if (bytes_perint > adapter->eitr_high)
1500                         retval = bulk_latency;
1501                 else if (bytes_perint <= adapter->eitr_low)
1502                         retval = lowest_latency;
1503                 break;
1504         case bulk_latency:
1505                 if (bytes_perint <= adapter->eitr_high)
1506                         retval = low_latency;
1507                 break;
1508         }
1509
1510 update_itr_done:
1511         return retval;
1512 }
1513
1514 /**
1515  * ixgbe_write_eitr - write EITR register in hardware specific way
1516  * @q_vector: structure containing interrupt and ring information
1517  *
1518  * This function is made to be called by ethtool and by the driver
1519  * when it needs to update EITR registers at runtime.  Hardware
1520  * specific quirks/differences are taken care of here.
1521  */
1522 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
1523 {
1524         struct ixgbe_adapter *adapter = q_vector->adapter;
1525         struct ixgbe_hw *hw = &adapter->hw;
1526         int v_idx = q_vector->v_idx;
1527         u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1528
1529         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1530                 /* must write high and low 16 bits to reset counter */
1531                 itr_reg |= (itr_reg << 16);
1532         } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1533                 /*
1534                  * 82599 can support a value of zero, so allow it for
1535                  * max interrupt rate, but there is an errata where it can
1536                  * not be zero with RSC
1537                  */
1538                 if (itr_reg == 8 &&
1539                     !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
1540                         itr_reg = 0;
1541
1542                 /*
1543                  * set the WDIS bit to not clear the timer bits and cause an
1544                  * immediate assertion of the interrupt
1545                  */
1546                 itr_reg |= IXGBE_EITR_CNT_WDIS;
1547         }
1548         IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1549 }
1550
1551 static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
1552 {
1553         struct ixgbe_adapter *adapter = q_vector->adapter;
1554         u32 new_itr;
1555         u8 current_itr, ret_itr;
1556         int i, r_idx;
1557         struct ixgbe_ring *rx_ring, *tx_ring;
1558
1559         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1560         for (i = 0; i < q_vector->txr_count; i++) {
1561                 tx_ring = adapter->tx_ring[r_idx];
1562                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1563                                            q_vector->tx_itr,
1564                                            tx_ring->total_packets,
1565                                            tx_ring->total_bytes);
1566                 /* if the result for this queue would decrease interrupt
1567                  * rate for this vector then use that result */
1568                 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
1569                                     q_vector->tx_itr - 1 : ret_itr);
1570                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1571                                       r_idx + 1);
1572         }
1573
1574         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1575         for (i = 0; i < q_vector->rxr_count; i++) {
1576                 rx_ring = adapter->rx_ring[r_idx];
1577                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1578                                            q_vector->rx_itr,
1579                                            rx_ring->total_packets,
1580                                            rx_ring->total_bytes);
1581                 /* if the result for this queue would decrease interrupt
1582                  * rate for this vector then use that result */
1583                 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
1584                                     q_vector->rx_itr - 1 : ret_itr);
1585                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1586                                       r_idx + 1);
1587         }
1588
1589         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1590
1591         switch (current_itr) {
1592         /* counts and packets in update_itr are dependent on these numbers */
1593         case lowest_latency:
1594                 new_itr = 100000;
1595                 break;
1596         case low_latency:
1597                 new_itr = 20000; /* aka hwitr = ~200 */
1598                 break;
1599         case bulk_latency:
1600         default:
1601                 new_itr = 8000;
1602                 break;
1603         }
1604
1605         if (new_itr != q_vector->eitr) {
1606                 /* do an exponential smoothing */
1607                 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1608
1609                 /* save the algorithm value here, not the smoothed one */
1610                 q_vector->eitr = new_itr;
1611
1612                 ixgbe_write_eitr(q_vector);
1613         }
1614
1615         return;
1616 }
1617
1618 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1619 {
1620         struct ixgbe_hw *hw = &adapter->hw;
1621
1622         if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1623             (eicr & IXGBE_EICR_GPI_SDP1)) {
1624                 DPRINTK(PROBE, CRIT, "Fan has stopped, replace the adapter\n");
1625                 /* write to clear the interrupt */
1626                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1627         }
1628 }
1629
1630 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1631 {
1632         struct ixgbe_hw *hw = &adapter->hw;
1633
1634         if (eicr & IXGBE_EICR_GPI_SDP1) {
1635                 /* Clear the interrupt */
1636                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1637                 schedule_work(&adapter->multispeed_fiber_task);
1638         } else if (eicr & IXGBE_EICR_GPI_SDP2) {
1639                 /* Clear the interrupt */
1640                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1641                 schedule_work(&adapter->sfp_config_module_task);
1642         } else {
1643                 /* Interrupt isn't for us... */
1644                 return;
1645         }
1646 }
1647
1648 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1649 {
1650         struct ixgbe_hw *hw = &adapter->hw;
1651
1652         adapter->lsc_int++;
1653         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1654         adapter->link_check_timeout = jiffies;
1655         if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1656                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1657                 IXGBE_WRITE_FLUSH(hw);
1658                 schedule_work(&adapter->watchdog_task);
1659         }
1660 }
1661
1662 static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1663 {
1664         struct net_device *netdev = data;
1665         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1666         struct ixgbe_hw *hw = &adapter->hw;
1667         u32 eicr;
1668
1669         /*
1670          * Workaround for Silicon errata.  Use clear-by-write instead
1671          * of clear-by-read.  Reading with EICS will return the
1672          * interrupt causes without clearing, which later be done
1673          * with the write to EICR.
1674          */
1675         eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1676         IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
1677
1678         if (eicr & IXGBE_EICR_LSC)
1679                 ixgbe_check_lsc(adapter);
1680
1681         if (eicr & IXGBE_EICR_MAILBOX)
1682                 ixgbe_msg_task(adapter);
1683
1684         if (hw->mac.type == ixgbe_mac_82598EB)
1685                 ixgbe_check_fan_failure(adapter, eicr);
1686
1687         if (hw->mac.type == ixgbe_mac_82599EB) {
1688                 ixgbe_check_sfp_event(adapter, eicr);
1689
1690                 /* Handle Flow Director Full threshold interrupt */
1691                 if (eicr & IXGBE_EICR_FLOW_DIR) {
1692                         int i;
1693                         IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR);
1694                         /* Disable transmits before FDIR Re-initialization */
1695                         netif_tx_stop_all_queues(netdev);
1696                         for (i = 0; i < adapter->num_tx_queues; i++) {
1697                                 struct ixgbe_ring *tx_ring =
1698                                                             adapter->tx_ring[i];
1699                                 if (test_and_clear_bit(__IXGBE_FDIR_INIT_DONE,
1700                                                        &tx_ring->reinit_state))
1701                                         schedule_work(&adapter->fdir_reinit_task);
1702                         }
1703                 }
1704         }
1705         if (!test_bit(__IXGBE_DOWN, &adapter->state))
1706                 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
1707
1708         return IRQ_HANDLED;
1709 }
1710
1711 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1712                                            u64 qmask)
1713 {
1714         u32 mask;
1715
1716         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1717                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1718                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1719         } else {
1720                 mask = (qmask & 0xFFFFFFFF);
1721                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(0), mask);
1722                 mask = (qmask >> 32);
1723                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1), mask);
1724         }
1725         /* skip the flush */
1726 }
1727
1728 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
1729                                             u64 qmask)
1730 {
1731         u32 mask;
1732
1733         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1734                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1735                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, mask);
1736         } else {
1737                 mask = (qmask & 0xFFFFFFFF);
1738                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), mask);
1739                 mask = (qmask >> 32);
1740                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), mask);
1741         }
1742         /* skip the flush */
1743 }
1744
1745 static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1746 {
1747         struct ixgbe_q_vector *q_vector = data;
1748         struct ixgbe_adapter  *adapter = q_vector->adapter;
1749         struct ixgbe_ring     *tx_ring;
1750         int i, r_idx;
1751
1752         if (!q_vector->txr_count)
1753                 return IRQ_HANDLED;
1754
1755         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1756         for (i = 0; i < q_vector->txr_count; i++) {
1757                 tx_ring = adapter->tx_ring[r_idx];
1758                 tx_ring->total_bytes = 0;
1759                 tx_ring->total_packets = 0;
1760                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1761                                       r_idx + 1);
1762         }
1763
1764         /* EIAM disabled interrupts (on this vector) for us */
1765         napi_schedule(&q_vector->napi);
1766
1767         return IRQ_HANDLED;
1768 }
1769
1770 /**
1771  * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1772  * @irq: unused
1773  * @data: pointer to our q_vector struct for this interrupt vector
1774  **/
1775 static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
1776 {
1777         struct ixgbe_q_vector *q_vector = data;
1778         struct ixgbe_adapter  *adapter = q_vector->adapter;
1779         struct ixgbe_ring  *rx_ring;
1780         int r_idx;
1781         int i;
1782
1783         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1784         for (i = 0;  i < q_vector->rxr_count; i++) {
1785                 rx_ring = adapter->rx_ring[r_idx];
1786                 rx_ring->total_bytes = 0;
1787                 rx_ring->total_packets = 0;
1788                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1789                                       r_idx + 1);
1790         }
1791
1792         if (!q_vector->rxr_count)
1793                 return IRQ_HANDLED;
1794
1795         /* disable interrupts on this vector only */
1796         /* EIAM disabled interrupts (on this vector) for us */
1797         napi_schedule(&q_vector->napi);
1798
1799         return IRQ_HANDLED;
1800 }
1801
1802 static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1803 {
1804         struct ixgbe_q_vector *q_vector = data;
1805         struct ixgbe_adapter  *adapter = q_vector->adapter;
1806         struct ixgbe_ring  *ring;
1807         int r_idx;
1808         int i;
1809
1810         if (!q_vector->txr_count && !q_vector->rxr_count)
1811                 return IRQ_HANDLED;
1812
1813         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1814         for (i = 0; i < q_vector->txr_count; i++) {
1815                 ring = adapter->tx_ring[r_idx];
1816                 ring->total_bytes = 0;
1817                 ring->total_packets = 0;
1818                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1819                                       r_idx + 1);
1820         }
1821
1822         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1823         for (i = 0; i < q_vector->rxr_count; i++) {
1824                 ring = adapter->rx_ring[r_idx];
1825                 ring->total_bytes = 0;
1826                 ring->total_packets = 0;
1827                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1828                                       r_idx + 1);
1829         }
1830
1831         /* EIAM disabled interrupts (on this vector) for us */
1832         napi_schedule(&q_vector->napi);
1833
1834         return IRQ_HANDLED;
1835 }
1836
1837 /**
1838  * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1839  * @napi: napi struct with our devices info in it
1840  * @budget: amount of work driver is allowed to do this pass, in packets
1841  *
1842  * This function is optimized for cleaning one queue only on a single
1843  * q_vector!!!
1844  **/
1845 static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1846 {
1847         struct ixgbe_q_vector *q_vector =
1848                                container_of(napi, struct ixgbe_q_vector, napi);
1849         struct ixgbe_adapter *adapter = q_vector->adapter;
1850         struct ixgbe_ring *rx_ring = NULL;
1851         int work_done = 0;
1852         long r_idx;
1853
1854         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1855         rx_ring = adapter->rx_ring[r_idx];
1856 #ifdef CONFIG_IXGBE_DCA
1857         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1858                 ixgbe_update_rx_dca(adapter, rx_ring);
1859 #endif
1860
1861         ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
1862
1863         /* If all Rx work done, exit the polling mode */
1864         if (work_done < budget) {
1865                 napi_complete(napi);
1866                 if (adapter->rx_itr_setting & 1)
1867                         ixgbe_set_itr_msix(q_vector);
1868                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1869                         ixgbe_irq_enable_queues(adapter,
1870                                                 ((u64)1 << q_vector->v_idx));
1871         }
1872
1873         return work_done;
1874 }
1875
1876 /**
1877  * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
1878  * @napi: napi struct with our devices info in it
1879  * @budget: amount of work driver is allowed to do this pass, in packets
1880  *
1881  * This function will clean more than one rx queue associated with a
1882  * q_vector.
1883  **/
1884 static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
1885 {
1886         struct ixgbe_q_vector *q_vector =
1887                                container_of(napi, struct ixgbe_q_vector, napi);
1888         struct ixgbe_adapter *adapter = q_vector->adapter;
1889         struct ixgbe_ring *ring = NULL;
1890         int work_done = 0, i;
1891         long r_idx;
1892         bool tx_clean_complete = true;
1893
1894         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1895         for (i = 0; i < q_vector->txr_count; i++) {
1896                 ring = adapter->tx_ring[r_idx];
1897 #ifdef CONFIG_IXGBE_DCA
1898                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1899                         ixgbe_update_tx_dca(adapter, ring);
1900 #endif
1901                 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
1902                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1903                                       r_idx + 1);
1904         }
1905
1906         /* attempt to distribute budget to each queue fairly, but don't allow
1907          * the budget to go below 1 because we'll exit polling */
1908         budget /= (q_vector->rxr_count ?: 1);
1909         budget = max(budget, 1);
1910         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1911         for (i = 0; i < q_vector->rxr_count; i++) {
1912                 ring = adapter->rx_ring[r_idx];
1913 #ifdef CONFIG_IXGBE_DCA
1914                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1915                         ixgbe_update_rx_dca(adapter, ring);
1916 #endif
1917                 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
1918                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1919                                       r_idx + 1);
1920         }
1921
1922         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1923         ring = adapter->rx_ring[r_idx];
1924         /* If all Rx work done, exit the polling mode */
1925         if (work_done < budget) {
1926                 napi_complete(napi);
1927                 if (adapter->rx_itr_setting & 1)
1928                         ixgbe_set_itr_msix(q_vector);
1929                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1930                         ixgbe_irq_enable_queues(adapter,
1931                                                 ((u64)1 << q_vector->v_idx));
1932                 return 0;
1933         }
1934
1935         return work_done;
1936 }
1937
1938 /**
1939  * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
1940  * @napi: napi struct with our devices info in it
1941  * @budget: amount of work driver is allowed to do this pass, in packets
1942  *
1943  * This function is optimized for cleaning one queue only on a single
1944  * q_vector!!!
1945  **/
1946 static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
1947 {
1948         struct ixgbe_q_vector *q_vector =
1949                                container_of(napi, struct ixgbe_q_vector, napi);
1950         struct ixgbe_adapter *adapter = q_vector->adapter;
1951         struct ixgbe_ring *tx_ring = NULL;
1952         int work_done = 0;
1953         long r_idx;
1954
1955         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1956         tx_ring = adapter->tx_ring[r_idx];
1957 #ifdef CONFIG_IXGBE_DCA
1958         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1959                 ixgbe_update_tx_dca(adapter, tx_ring);
1960 #endif
1961
1962         if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
1963                 work_done = budget;
1964
1965         /* If all Tx work done, exit the polling mode */
1966         if (work_done < budget) {
1967                 napi_complete(napi);
1968                 if (adapter->tx_itr_setting & 1)
1969                         ixgbe_set_itr_msix(q_vector);
1970                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1971                         ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
1972         }
1973
1974         return work_done;
1975 }
1976
1977 static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
1978                                      int r_idx)
1979 {
1980         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1981
1982         set_bit(r_idx, q_vector->rxr_idx);
1983         q_vector->rxr_count++;
1984 }
1985
1986 static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
1987                                      int t_idx)
1988 {
1989         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1990
1991         set_bit(t_idx, q_vector->txr_idx);
1992         q_vector->txr_count++;
1993 }
1994
1995 /**
1996  * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
1997  * @adapter: board private structure to initialize
1998  * @vectors: allotted vector count for descriptor rings
1999  *
2000  * This function maps descriptor rings to the queue-specific vectors
2001  * we were allotted through the MSI-X enabling code.  Ideally, we'd have
2002  * one vector per ring/queue, but on a constrained vector budget, we
2003  * group the rings as "efficiently" as possible.  You would add new
2004  * mapping configurations in here.
2005  **/
2006 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
2007                                       int vectors)
2008 {
2009         int v_start = 0;
2010         int rxr_idx = 0, txr_idx = 0;
2011         int rxr_remaining = adapter->num_rx_queues;
2012         int txr_remaining = adapter->num_tx_queues;
2013         int i, j;
2014         int rqpv, tqpv;
2015         int err = 0;
2016
2017         /* No mapping required if MSI-X is disabled. */
2018         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2019                 goto out;
2020
2021         /*
2022          * The ideal configuration...
2023          * We have enough vectors to map one per queue.
2024          */
2025         if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
2026                 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
2027                         map_vector_to_rxq(adapter, v_start, rxr_idx);
2028
2029                 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
2030                         map_vector_to_txq(adapter, v_start, txr_idx);
2031
2032                 goto out;
2033         }
2034
2035         /*
2036          * If we don't have enough vectors for a 1-to-1
2037          * mapping, we'll have to group them so there are
2038          * multiple queues per vector.
2039          */
2040         /* Re-adjusting *qpv takes care of the remainder. */
2041         for (i = v_start; i < vectors; i++) {
2042                 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
2043                 for (j = 0; j < rqpv; j++) {
2044                         map_vector_to_rxq(adapter, i, rxr_idx);
2045                         rxr_idx++;
2046                         rxr_remaining--;
2047                 }
2048         }
2049         for (i = v_start; i < vectors; i++) {
2050                 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
2051                 for (j = 0; j < tqpv; j++) {
2052                         map_vector_to_txq(adapter, i, txr_idx);
2053                         txr_idx++;
2054                         txr_remaining--;
2055                 }
2056         }
2057
2058 out:
2059         return err;
2060 }
2061
2062 /**
2063  * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2064  * @adapter: board private structure
2065  *
2066  * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2067  * interrupts from the kernel.
2068  **/
2069 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2070 {
2071         struct net_device *netdev = adapter->netdev;
2072         irqreturn_t (*handler)(int, void *);
2073         int i, vector, q_vectors, err;
2074         int ri=0, ti=0;
2075
2076         /* Decrement for Other and TCP Timer vectors */
2077         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2078
2079         /* Map the Tx/Rx rings to the vectors we were allotted. */
2080         err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
2081         if (err)
2082                 goto out;
2083
2084 #define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
2085                          (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
2086                          &ixgbe_msix_clean_many)
2087         for (vector = 0; vector < q_vectors; vector++) {
2088                 handler = SET_HANDLER(adapter->q_vector[vector]);
2089
2090                 if(handler == &ixgbe_msix_clean_rx) {
2091                         sprintf(adapter->name[vector], "%s-%s-%d",
2092                                 netdev->name, "rx", ri++);
2093                 }
2094                 else if(handler == &ixgbe_msix_clean_tx) {
2095                         sprintf(adapter->name[vector], "%s-%s-%d",
2096                                 netdev->name, "tx", ti++);
2097                 }
2098                 else
2099                         sprintf(adapter->name[vector], "%s-%s-%d",
2100                                 netdev->name, "TxRx", vector);
2101
2102                 err = request_irq(adapter->msix_entries[vector].vector,
2103                                   handler, 0, adapter->name[vector],
2104                                   adapter->q_vector[vector]);
2105                 if (err) {
2106                         DPRINTK(PROBE, ERR,
2107                                 "request_irq failed for MSIX interrupt "
2108                                 "Error: %d\n", err);
2109                         goto free_queue_irqs;
2110                 }
2111         }
2112
2113         sprintf(adapter->name[vector], "%s:lsc", netdev->name);
2114         err = request_irq(adapter->msix_entries[vector].vector,
2115                           ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
2116         if (err) {
2117                 DPRINTK(PROBE, ERR,
2118                         "request_irq for msix_lsc failed: %d\n", err);
2119                 goto free_queue_irqs;
2120         }
2121
2122         return 0;
2123
2124 free_queue_irqs:
2125         for (i = vector - 1; i >= 0; i--)
2126                 free_irq(adapter->msix_entries[--vector].vector,
2127                          adapter->q_vector[i]);
2128         adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2129         pci_disable_msix(adapter->pdev);
2130         kfree(adapter->msix_entries);
2131         adapter->msix_entries = NULL;
2132 out:
2133         return err;
2134 }
2135
2136 static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
2137 {
2138         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2139         u8 current_itr;
2140         u32 new_itr = q_vector->eitr;
2141         struct ixgbe_ring *rx_ring = adapter->rx_ring[0];
2142         struct ixgbe_ring *tx_ring = adapter->tx_ring[0];
2143
2144         q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
2145                                             q_vector->tx_itr,
2146                                             tx_ring->total_packets,
2147                                             tx_ring->total_bytes);
2148         q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
2149                                             q_vector->rx_itr,
2150                                             rx_ring->total_packets,
2151                                             rx_ring->total_bytes);
2152
2153         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
2154
2155         switch (current_itr) {
2156         /* counts and packets in update_itr are dependent on these numbers */
2157         case lowest_latency:
2158                 new_itr = 100000;
2159                 break;
2160         case low_latency:
2161                 new_itr = 20000; /* aka hwitr = ~200 */
2162                 break;
2163         case bulk_latency:
2164                 new_itr = 8000;
2165                 break;
2166         default:
2167                 break;
2168         }
2169
2170         if (new_itr != q_vector->eitr) {
2171                 /* do an exponential smoothing */
2172                 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
2173
2174                 /* save the algorithm value here, not the smoothed one */
2175                 q_vector->eitr = new_itr;
2176
2177                 ixgbe_write_eitr(q_vector);
2178         }
2179
2180         return;
2181 }
2182
2183 /**
2184  * ixgbe_irq_enable - Enable default interrupt generation settings
2185  * @adapter: board private structure
2186  **/
2187 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter)
2188 {
2189         u32 mask;
2190
2191         mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
2192         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2193                 mask |= IXGBE_EIMS_GPI_SDP1;
2194         if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2195                 mask |= IXGBE_EIMS_ECC;
2196                 mask |= IXGBE_EIMS_GPI_SDP1;
2197                 mask |= IXGBE_EIMS_GPI_SDP2;
2198                 if (adapter->num_vfs)
2199                         mask |= IXGBE_EIMS_MAILBOX;
2200         }
2201         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
2202             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
2203                 mask |= IXGBE_EIMS_FLOW_DIR;
2204
2205         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2206         ixgbe_irq_enable_queues(adapter, ~0);
2207         IXGBE_WRITE_FLUSH(&adapter->hw);
2208
2209         if (adapter->num_vfs > 32) {
2210                 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2211                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2212         }
2213 }
2214
2215 /**
2216  * ixgbe_intr - legacy mode Interrupt Handler
2217  * @irq: interrupt number
2218  * @data: pointer to a network interface device structure
2219  **/
2220 static irqreturn_t ixgbe_intr(int irq, void *data)
2221 {
2222         struct net_device *netdev = data;
2223         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2224         struct ixgbe_hw *hw = &adapter->hw;
2225         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2226         u32 eicr;
2227
2228         /*
2229          * Workaround for silicon errata.  Mask the interrupts
2230          * before the read of EICR.
2231          */
2232         IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2233
2234         /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2235          * therefore no explict interrupt disable is necessary */
2236         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2237         if (!eicr) {
2238                 /* shared interrupt alert!
2239                  * make sure interrupts are enabled because the read will
2240                  * have disabled interrupts due to EIAM */
2241                 ixgbe_irq_enable(adapter);
2242                 return IRQ_NONE;        /* Not our interrupt */
2243         }
2244
2245         if (eicr & IXGBE_EICR_LSC)
2246                 ixgbe_check_lsc(adapter);
2247
2248         if (hw->mac.type == ixgbe_mac_82599EB)
2249                 ixgbe_check_sfp_event(adapter, eicr);
2250
2251         ixgbe_check_fan_failure(adapter, eicr);
2252
2253         if (napi_schedule_prep(&(q_vector->napi))) {
2254                 adapter->tx_ring[0]->total_packets = 0;
2255                 adapter->tx_ring[0]->total_bytes = 0;
2256                 adapter->rx_ring[0]->total_packets = 0;
2257                 adapter->rx_ring[0]->total_bytes = 0;
2258                 /* would disable interrupts here but EIAM disabled it */
2259                 __napi_schedule(&(q_vector->napi));
2260         }
2261
2262         return IRQ_HANDLED;
2263 }
2264
2265 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
2266 {
2267         int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2268
2269         for (i = 0; i < q_vectors; i++) {
2270                 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
2271                 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
2272                 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
2273                 q_vector->rxr_count = 0;
2274                 q_vector->txr_count = 0;
2275         }
2276 }
2277
2278 /**
2279  * ixgbe_request_irq - initialize interrupts
2280  * @adapter: board private structure
2281  *
2282  * Attempts to configure interrupts using the best available
2283  * capabilities of the hardware and kernel.
2284  **/
2285 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
2286 {
2287         struct net_device *netdev = adapter->netdev;
2288         int err;
2289
2290         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2291                 err = ixgbe_request_msix_irqs(adapter);
2292         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
2293                 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
2294                                   netdev->name, netdev);
2295         } else {
2296                 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
2297                                   netdev->name, netdev);
2298         }
2299
2300         if (err)
2301                 DPRINTK(PROBE, ERR, "request_irq failed, Error %d\n", err);
2302
2303         return err;
2304 }
2305
2306 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2307 {
2308         struct net_device *netdev = adapter->netdev;
2309
2310         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2311                 int i, q_vectors;
2312
2313                 q_vectors = adapter->num_msix_vectors;
2314
2315                 i = q_vectors - 1;
2316                 free_irq(adapter->msix_entries[i].vector, netdev);
2317
2318                 i--;
2319                 for (; i >= 0; i--) {
2320                         free_irq(adapter->msix_entries[i].vector,
2321                                  adapter->q_vector[i]);
2322                 }
2323
2324                 ixgbe_reset_q_vectors(adapter);
2325         } else {
2326                 free_irq(adapter->pdev->irq, netdev);
2327         }
2328 }
2329
2330 /**
2331  * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2332  * @adapter: board private structure
2333  **/
2334 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2335 {
2336         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2337                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
2338         } else {
2339                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2340                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
2341                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
2342                 if (adapter->num_vfs > 32)
2343                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
2344         }
2345         IXGBE_WRITE_FLUSH(&adapter->hw);
2346         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2347                 int i;
2348                 for (i = 0; i < adapter->num_msix_vectors; i++)
2349                         synchronize_irq(adapter->msix_entries[i].vector);
2350         } else {
2351                 synchronize_irq(adapter->pdev->irq);
2352         }
2353 }
2354
2355 /**
2356  * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2357  *
2358  **/
2359 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2360 {
2361         struct ixgbe_hw *hw = &adapter->hw;
2362
2363         IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
2364                         EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
2365
2366         ixgbe_set_ivar(adapter, 0, 0, 0);
2367         ixgbe_set_ivar(adapter, 1, 0, 0);
2368
2369         map_vector_to_rxq(adapter, 0, 0);
2370         map_vector_to_txq(adapter, 0, 0);
2371
2372         DPRINTK(HW, INFO, "Legacy interrupt IVAR setup done\n");
2373 }
2374
2375 /**
2376  * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
2377  * @adapter: board private structure
2378  *
2379  * Configure the Tx unit of the MAC after a reset.
2380  **/
2381 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2382 {
2383         u64 tdba;
2384         struct ixgbe_hw *hw = &adapter->hw;
2385         u32 i, j, tdlen, txctrl;
2386
2387         /* Setup the HW Tx Head and Tail descriptor pointers */
2388         for (i = 0; i < adapter->num_tx_queues; i++) {
2389                 struct ixgbe_ring *ring = adapter->tx_ring[i];
2390                 j = ring->reg_idx;
2391                 tdba = ring->dma;
2392                 tdlen = ring->count * sizeof(union ixgbe_adv_tx_desc);
2393                 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j),
2394                                 (tdba & DMA_BIT_MASK(32)));
2395                 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32));
2396                 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), tdlen);
2397                 IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0);
2398                 IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0);
2399                 adapter->tx_ring[i]->head = IXGBE_TDH(j);
2400                 adapter->tx_ring[i]->tail = IXGBE_TDT(j);
2401                 /*
2402                  * Disable Tx Head Writeback RO bit, since this hoses
2403                  * bookkeeping if things aren't delivered in order.
2404                  */
2405                 switch (hw->mac.type) {
2406                 case ixgbe_mac_82598EB:
2407                         txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j));
2408                         break;
2409                 case ixgbe_mac_82599EB:
2410                 default:
2411                         txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(j));
2412                         break;
2413                 }
2414                 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
2415                 switch (hw->mac.type) {
2416                 case ixgbe_mac_82598EB:
2417                         IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl);
2418                         break;
2419                 case ixgbe_mac_82599EB:
2420                 default:
2421                         IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(j), txctrl);
2422                         break;
2423                 }
2424         }
2425
2426         if (hw->mac.type == ixgbe_mac_82599EB) {
2427                 u32 rttdcs;
2428                 u32 mask;
2429
2430                 /* disable the arbiter while setting MTQC */
2431                 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2432                 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2433                 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2434
2435                 /* set transmit pool layout */
2436                 mask = (IXGBE_FLAG_SRIOV_ENABLED | IXGBE_FLAG_DCB_ENABLED);
2437                 switch (adapter->flags & mask) {
2438
2439                 case (IXGBE_FLAG_SRIOV_ENABLED):
2440                         IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2441                                         (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2442                         break;
2443
2444                 case (IXGBE_FLAG_DCB_ENABLED):
2445                         /* We enable 8 traffic classes, DCB only */
2446                         IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2447                                       (IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ));
2448                         break;
2449
2450                 default:
2451                         IXGBE_WRITE_REG(hw, IXGBE_MTQC, IXGBE_MTQC_64Q_1PB);
2452                         break;
2453                 }
2454
2455                 /* re-eable the arbiter */
2456                 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2457                 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2458         }
2459 }
2460
2461 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
2462
2463 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
2464                                    struct ixgbe_ring *rx_ring)
2465 {
2466         u32 srrctl;
2467         int index;
2468         struct ixgbe_ring_feature *feature = adapter->ring_feature;
2469
2470         index = rx_ring->reg_idx;
2471         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2472                 unsigned long mask;
2473                 mask = (unsigned long) feature[RING_F_RSS].mask;
2474                 index = index & mask;
2475         }
2476         srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
2477
2478         srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2479         srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
2480
2481         srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2482                   IXGBE_SRRCTL_BSIZEHDR_MASK;
2483
2484         if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
2485 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2486                 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2487 #else
2488                 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2489 #endif
2490                 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2491         } else {
2492                 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2493                           IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2494                 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
2495         }
2496
2497         IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
2498 }
2499
2500 static u32 ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
2501 {
2502         u32 mrqc = 0;
2503         int mask;
2504
2505         if (!(adapter->hw.mac.type == ixgbe_mac_82599EB))
2506                 return mrqc;
2507
2508         mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2509 #ifdef CONFIG_IXGBE_DCB
2510                                  | IXGBE_FLAG_DCB_ENABLED
2511 #endif
2512                                  | IXGBE_FLAG_SRIOV_ENABLED
2513                                 );
2514
2515         switch (mask) {
2516         case (IXGBE_FLAG_RSS_ENABLED):
2517                 mrqc = IXGBE_MRQC_RSSEN;
2518                 break;
2519         case (IXGBE_FLAG_SRIOV_ENABLED):
2520                 mrqc = IXGBE_MRQC_VMDQEN;
2521                 break;
2522 #ifdef CONFIG_IXGBE_DCB
2523         case (IXGBE_FLAG_DCB_ENABLED):
2524                 mrqc = IXGBE_MRQC_RT8TCEN;
2525                 break;
2526 #endif /* CONFIG_IXGBE_DCB */
2527         default:
2528                 break;
2529         }
2530
2531         return mrqc;
2532 }
2533
2534 /**
2535  * ixgbe_configure_rscctl - enable RSC for the indicated ring
2536  * @adapter:    address of board private structure
2537  * @index:      index of ring to set
2538  **/
2539 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter, int index)
2540 {
2541         struct ixgbe_ring *rx_ring;
2542         struct ixgbe_hw *hw = &adapter->hw;
2543         int j;
2544         u32 rscctrl;
2545         int rx_buf_len;
2546
2547         rx_ring = adapter->rx_ring[index];
2548         j = rx_ring->reg_idx;
2549         rx_buf_len = rx_ring->rx_buf_len;
2550         rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(j));
2551         rscctrl |= IXGBE_RSCCTL_RSCEN;
2552         /*
2553          * we must limit the number of descriptors so that the
2554          * total size of max desc * buf_len is not greater
2555          * than 65535
2556          */
2557         if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
2558 #if (MAX_SKB_FRAGS > 16)
2559                 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2560 #elif (MAX_SKB_FRAGS > 8)
2561                 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2562 #elif (MAX_SKB_FRAGS > 4)
2563                 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2564 #else
2565                 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2566 #endif
2567         } else {
2568                 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2569                         rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2570                 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2571                         rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2572                 else
2573                         rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2574         }
2575         IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(j), rscctrl);
2576 }
2577
2578 /**
2579  * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
2580  * @adapter: board private structure
2581  *
2582  * Configure the Rx unit of the MAC after a reset.
2583  **/
2584 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
2585 {
2586         u64 rdba;
2587         struct ixgbe_hw *hw = &adapter->hw;
2588         struct ixgbe_ring *rx_ring;
2589         struct net_device *netdev = adapter->netdev;
2590         int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2591         int i, j;
2592         u32 rdlen, rxctrl, rxcsum;
2593         static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2594                           0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2595                           0x6A3E67EA, 0x14364D17, 0x3BED200D};
2596         u32 fctrl, hlreg0;
2597         u32 reta = 0, mrqc = 0;
2598         u32 rdrxctl;
2599         int rx_buf_len;
2600
2601         /* Decide whether to use packet split mode or not */
2602         /* Do not use packet split if we're in SR-IOV Mode */
2603         if (!adapter->num_vfs)
2604                 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
2605
2606         /* Set the RX buffer length according to the mode */
2607         if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
2608                 rx_buf_len = IXGBE_RX_HDR_SIZE;
2609                 if (hw->mac.type == ixgbe_mac_82599EB) {
2610                         /* PSRTYPE must be initialized in 82599 */
2611                         u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
2612                                       IXGBE_PSRTYPE_UDPHDR |
2613                                       IXGBE_PSRTYPE_IPV4HDR |
2614                                       IXGBE_PSRTYPE_IPV6HDR |
2615                                       IXGBE_PSRTYPE_L2HDR;
2616                         IXGBE_WRITE_REG(hw,
2617                                         IXGBE_PSRTYPE(adapter->num_vfs),
2618                                         psrtype);
2619                 }
2620         } else {
2621                 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
2622                     (netdev->mtu <= ETH_DATA_LEN))
2623                         rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
2624                 else
2625                         rx_buf_len = ALIGN(max_frame, 1024);
2626         }
2627
2628         fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
2629         fctrl |= IXGBE_FCTRL_BAM;
2630         fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
2631         fctrl |= IXGBE_FCTRL_PMCF;
2632         IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, fctrl);
2633
2634         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2635         if (adapter->netdev->mtu <= ETH_DATA_LEN)
2636                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
2637         else
2638                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2639 #ifdef IXGBE_FCOE
2640         if (netdev->features & NETIF_F_FCOE_MTU)
2641                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2642 #endif
2643         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2644
2645         rdlen = adapter->rx_ring[0]->count * sizeof(union ixgbe_adv_rx_desc);
2646         /* disable receives while setting up the descriptors */
2647         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2648         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
2649
2650         /*
2651          * Setup the HW Rx Head and Tail Descriptor Pointers and
2652          * the Base and Length of the Rx Descriptor Ring
2653          */
2654         for (i = 0; i < adapter->num_rx_queues; i++) {
2655                 rx_ring = adapter->rx_ring[i];
2656                 rdba = rx_ring->dma;
2657                 j = rx_ring->reg_idx;
2658                 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j), (rdba & DMA_BIT_MASK(32)));
2659                 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32));
2660                 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j), rdlen);
2661                 IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0);
2662                 IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0);
2663                 rx_ring->head = IXGBE_RDH(j);
2664                 rx_ring->tail = IXGBE_RDT(j);
2665                 rx_ring->rx_buf_len = rx_buf_len;
2666
2667                 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
2668                         rx_ring->flags |= IXGBE_RING_RX_PS_ENABLED;
2669                 else
2670                         rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
2671
2672 #ifdef IXGBE_FCOE
2673                 if (netdev->features & NETIF_F_FCOE_MTU) {
2674                         struct ixgbe_ring_feature *f;
2675                         f = &adapter->ring_feature[RING_F_FCOE];
2676                         if ((i >= f->mask) && (i < f->mask + f->indices)) {
2677                                 rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
2678                                 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
2679                                         rx_ring->rx_buf_len =
2680                                                 IXGBE_FCOE_JUMBO_FRAME_SIZE;
2681                         }
2682                 }
2683
2684 #endif /* IXGBE_FCOE */
2685                 ixgbe_configure_srrctl(adapter, rx_ring);
2686         }
2687
2688         if (hw->mac.type == ixgbe_mac_82598EB) {
2689                 /*
2690                  * For VMDq support of different descriptor types or
2691                  * buffer sizes through the use of multiple SRRCTL
2692                  * registers, RDRXCTL.MVMEN must be set to 1
2693                  *
2694                  * also, the manual doesn't mention it clearly but DCA hints
2695                  * will only use queue 0's tags unless this bit is set.  Side
2696                  * effects of setting this bit are only that SRRCTL must be
2697                  * fully programmed [0..15]
2698                  */
2699                 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2700                 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
2701                 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2702         }
2703
2704         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
2705                 u32 vt_reg_bits;
2706                 u32 reg_offset, vf_shift;
2707                 u32 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2708                 vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN
2709                         | IXGBE_VT_CTL_REPLEN;
2710                 vt_reg_bits |= (adapter->num_vfs <<
2711                                 IXGBE_VT_CTL_POOL_SHIFT);
2712                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
2713                 IXGBE_WRITE_REG(hw, IXGBE_MRQC, 0);
2714
2715                 vf_shift = adapter->num_vfs % 32;
2716                 reg_offset = adapter->num_vfs / 32;
2717                 IXGBE_WRITE_REG(hw, IXGBE_VFRE(0), 0);
2718                 IXGBE_WRITE_REG(hw, IXGBE_VFRE(1), 0);
2719                 IXGBE_WRITE_REG(hw, IXGBE_VFTE(0), 0);
2720                 IXGBE_WRITE_REG(hw, IXGBE_VFTE(1), 0);
2721                 /* Enable only the PF's pool for Tx/Rx */
2722                 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
2723                 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
2724                 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
2725                 ixgbe_set_vmolr(hw, adapter->num_vfs, true);
2726         }
2727
2728         /* Program MRQC for the distribution of queues */
2729         mrqc = ixgbe_setup_mrqc(adapter);
2730
2731         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
2732                 /* Fill out redirection table */
2733                 for (i = 0, j = 0; i < 128; i++, j++) {
2734                         if (j == adapter->ring_feature[RING_F_RSS].indices)
2735                                 j = 0;
2736                         /* reta = 4-byte sliding window of
2737                          * 0x00..(indices-1)(indices-1)00..etc. */
2738                         reta = (reta << 8) | (j * 0x11);
2739                         if ((i & 3) == 3)
2740                                 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2741                 }
2742
2743                 /* Fill out hash function seeds */
2744                 for (i = 0; i < 10; i++)
2745                         IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2746
2747                 if (hw->mac.type == ixgbe_mac_82598EB)
2748                         mrqc |= IXGBE_MRQC_RSSEN;
2749                     /* Perform hash on these packet types */
2750                 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2751                       | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2752                       | IXGBE_MRQC_RSS_FIELD_IPV4_UDP
2753                       | IXGBE_MRQC_RSS_FIELD_IPV6
2754                       | IXGBE_MRQC_RSS_FIELD_IPV6_TCP
2755                       | IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
2756         }
2757         IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2758
2759         if (adapter->num_vfs) {
2760                 u32 reg;
2761
2762                 /* Map PF MAC address in RAR Entry 0 to first pool
2763                  * following VFs */
2764                 hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
2765
2766                 /* Set up VF register offsets for selected VT Mode, i.e.
2767                  * 64 VFs for SR-IOV */
2768                 reg = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
2769                 reg |= IXGBE_GCR_EXT_SRIOV;
2770                 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, reg);
2771         }
2772
2773         rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2774
2775         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED ||
2776             adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED) {
2777                 /* Disable indicating checksum in descriptor, enables
2778                  * RSS hash */
2779                 rxcsum |= IXGBE_RXCSUM_PCSD;
2780         }
2781         if (!(rxcsum & IXGBE_RXCSUM_PCSD)) {
2782                 /* Enable IPv4 payload checksum for UDP fragments
2783                  * if PCSD is not set */
2784                 rxcsum |= IXGBE_RXCSUM_IPPCSE;
2785         }
2786
2787         IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2788
2789         if (hw->mac.type == ixgbe_mac_82599EB) {
2790                 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2791                 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
2792                 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
2793                 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2794         }
2795
2796         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
2797                 /* Enable 82599 HW-RSC */
2798                 for (i = 0; i < adapter->num_rx_queues; i++)
2799                         ixgbe_configure_rscctl(adapter, i);
2800
2801                 /* Disable RSC for ACK packets */
2802                 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
2803                    (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
2804         }
2805 }
2806
2807 static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
2808 {
2809         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2810         struct ixgbe_hw *hw = &adapter->hw;
2811         int pool_ndx = adapter->num_vfs;
2812
2813         /* add VID to filter table */
2814         hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
2815 }
2816
2817 static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
2818 {
2819         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2820         struct ixgbe_hw *hw = &adapter->hw;
2821         int pool_ndx = adapter->num_vfs;
2822
2823         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2824                 ixgbe_irq_disable(adapter);
2825
2826         vlan_group_set_device(adapter->vlgrp, vid, NULL);
2827
2828         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2829                 ixgbe_irq_enable(adapter);
2830
2831         /* remove VID from filter table */
2832         hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
2833 }
2834
2835 /**
2836  * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
2837  * @adapter: driver data
2838  */
2839 static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
2840 {
2841         struct ixgbe_hw *hw = &adapter->hw;
2842         u32 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2843         int i, j;
2844
2845         switch (hw->mac.type) {
2846         case ixgbe_mac_82598EB:
2847                 vlnctrl &= ~(IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE);
2848                 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2849                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2850                 break;
2851         case ixgbe_mac_82599EB:
2852                 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
2853                 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2854                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2855                 for (i = 0; i < adapter->num_rx_queues; i++) {
2856                         j = adapter->rx_ring[i]->reg_idx;
2857                         vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2858                         vlnctrl &= ~IXGBE_RXDCTL_VME;
2859                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
2860                 }
2861                 break;
2862         default:
2863                 break;
2864         }
2865 }
2866
2867 /**
2868  * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
2869  * @adapter: driver data
2870  */
2871 static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
2872 {
2873         struct ixgbe_hw *hw = &adapter->hw;
2874         u32 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2875         int i, j;
2876
2877         switch (hw->mac.type) {
2878         case ixgbe_mac_82598EB:
2879                 vlnctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2880                 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2881                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2882                 break;
2883         case ixgbe_mac_82599EB:
2884                 vlnctrl |= IXGBE_VLNCTRL_VFE;
2885                 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2886                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2887                 for (i = 0; i < adapter->num_rx_queues; i++) {
2888                         j = adapter->rx_ring[i]->reg_idx;
2889                         vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2890                         vlnctrl |= IXGBE_RXDCTL_VME;
2891                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
2892                 }
2893                 break;
2894         default:
2895                 break;
2896         }
2897 }
2898
2899 static void ixgbe_vlan_rx_register(struct net_device *netdev,
2900                                    struct vlan_group *grp)
2901 {
2902         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2903
2904         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2905                 ixgbe_irq_disable(adapter);
2906         adapter->vlgrp = grp;
2907
2908         /*
2909          * For a DCB driver, always enable VLAN tag stripping so we can
2910          * still receive traffic from a DCB-enabled host even if we're
2911          * not in DCB mode.
2912          */
2913         ixgbe_vlan_filter_enable(adapter);
2914
2915         ixgbe_vlan_rx_add_vid(netdev, 0);
2916
2917         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2918                 ixgbe_irq_enable(adapter);
2919 }
2920
2921 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
2922 {
2923         ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp);
2924
2925         if (adapter->vlgrp) {
2926                 u16 vid;
2927                 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
2928                         if (!vlan_group_get_device(adapter->vlgrp, vid))
2929                                 continue;
2930                         ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
2931                 }
2932         }
2933 }
2934
2935 /**
2936  * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
2937  * @netdev: network interface device structure
2938  *
2939  * The set_rx_method entry point is called whenever the unicast/multicast
2940  * address list or the network interface flags are updated.  This routine is
2941  * responsible for configuring the hardware for proper unicast, multicast and
2942  * promiscuous mode.
2943  **/
2944 void ixgbe_set_rx_mode(struct net_device *netdev)
2945 {
2946         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2947         struct ixgbe_hw *hw = &adapter->hw;
2948         u32 fctrl;
2949
2950         /* Check for Promiscuous and All Multicast modes */
2951
2952         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2953
2954         if (netdev->flags & IFF_PROMISC) {
2955                 hw->addr_ctrl.user_set_promisc = true;
2956                 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2957                 /* don't hardware filter vlans in promisc mode */
2958                 ixgbe_vlan_filter_disable(adapter);
2959         } else {
2960                 if (netdev->flags & IFF_ALLMULTI) {
2961                         fctrl |= IXGBE_FCTRL_MPE;
2962                         fctrl &= ~IXGBE_FCTRL_UPE;
2963                 } else if (!hw->addr_ctrl.uc_set_promisc) {
2964                         fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2965                 }
2966                 ixgbe_vlan_filter_enable(adapter);
2967                 hw->addr_ctrl.user_set_promisc = false;
2968         }
2969
2970         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2971
2972         /* reprogram secondary unicast list */
2973         hw->mac.ops.update_uc_addr_list(hw, netdev);
2974
2975         /* reprogram multicast list */
2976         hw->mac.ops.update_mc_addr_list(hw, netdev);
2977
2978         if (adapter->num_vfs)
2979                 ixgbe_restore_vf_multicasts(adapter);
2980 }
2981
2982 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
2983 {
2984         int q_idx;
2985         struct ixgbe_q_vector *q_vector;
2986         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2987
2988         /* legacy and MSI only use one vector */
2989         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2990                 q_vectors = 1;
2991
2992         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
2993                 struct napi_struct *napi;
2994                 q_vector = adapter->q_vector[q_idx];
2995                 napi = &q_vector->napi;
2996                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2997                         if (!q_vector->rxr_count || !q_vector->txr_count) {
2998                                 if (q_vector->txr_count == 1)
2999                                         napi->poll = &ixgbe_clean_txonly;
3000                                 else if (q_vector->rxr_count == 1)
3001                                         napi->poll = &ixgbe_clean_rxonly;
3002                         }
3003                 }
3004
3005                 napi_enable(napi);
3006         }
3007 }
3008
3009 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3010 {
3011         int q_idx;
3012         struct ixgbe_q_vector *q_vector;
3013         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3014
3015         /* legacy and MSI only use one vector */
3016         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3017                 q_vectors = 1;
3018
3019         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3020                 q_vector = adapter->q_vector[q_idx];
3021                 napi_disable(&q_vector->napi);
3022         }
3023 }
3024
3025 #ifdef CONFIG_IXGBE_DCB
3026 /*
3027  * ixgbe_configure_dcb - Configure DCB hardware
3028  * @adapter: ixgbe adapter struct
3029  *
3030  * This is called by the driver on open to configure the DCB hardware.
3031  * This is also called by the gennetlink interface when reconfiguring
3032  * the DCB state.
3033  */
3034 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3035 {
3036         struct ixgbe_hw *hw = &adapter->hw;
3037         u32 txdctl;
3038         int i, j;
3039
3040         ixgbe_dcb_check_config(&adapter->dcb_cfg);
3041         ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_TX_CONFIG);
3042         ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_RX_CONFIG);
3043
3044         /* reconfigure the hardware */
3045         ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg);
3046
3047         for (i = 0; i < adapter->num_tx_queues; i++) {
3048                 j = adapter->tx_ring[i]->reg_idx;
3049                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3050                 /* PThresh workaround for Tx hang with DFP enabled. */
3051                 txdctl |= 32;
3052                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
3053         }
3054         /* Enable VLAN tag insert/strip */
3055         ixgbe_vlan_filter_enable(adapter);
3056
3057         hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
3058 }
3059
3060 #endif
3061 static void ixgbe_configure(struct ixgbe_adapter *adapter)
3062 {
3063         struct net_device *netdev = adapter->netdev;
3064         struct ixgbe_hw *hw = &adapter->hw;
3065         int i;
3066
3067         ixgbe_set_rx_mode(netdev);
3068
3069         ixgbe_restore_vlan(adapter);
3070 #ifdef CONFIG_IXGBE_DCB
3071         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3072                 if (hw->mac.type == ixgbe_mac_82598EB)
3073                         netif_set_gso_max_size(netdev, 32768);
3074                 else
3075                         netif_set_gso_max_size(netdev, 65536);
3076                 ixgbe_configure_dcb(adapter);
3077         } else {
3078                 netif_set_gso_max_size(netdev, 65536);
3079         }
3080 #else
3081         netif_set_gso_max_size(netdev, 65536);
3082 #endif
3083
3084 #ifdef IXGBE_FCOE
3085         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
3086                 ixgbe_configure_fcoe(adapter);
3087
3088 #endif /* IXGBE_FCOE */
3089         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3090                 for (i = 0; i < adapter->num_tx_queues; i++)
3091                         adapter->tx_ring[i]->atr_sample_rate =
3092                                                        adapter->atr_sample_rate;
3093                 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
3094         } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3095                 ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc);
3096         }
3097
3098         ixgbe_configure_tx(adapter);
3099         ixgbe_configure_rx(adapter);
3100         for (i = 0; i < adapter->num_rx_queues; i++)
3101                 ixgbe_alloc_rx_buffers(adapter, adapter->rx_ring[i],
3102                                        (adapter->rx_ring[i]->count - 1));
3103 }
3104
3105 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3106 {
3107         switch (hw->phy.type) {
3108         case ixgbe_phy_sfp_avago:
3109         case ixgbe_phy_sfp_ftl:
3110         case ixgbe_phy_sfp_intel:
3111         case ixgbe_phy_sfp_unknown:
3112         case ixgbe_phy_tw_tyco:
3113         case ixgbe_phy_tw_unknown:
3114                 return true;
3115         default:
3116                 return false;
3117         }
3118 }
3119
3120 /**
3121  * ixgbe_sfp_link_config - set up SFP+ link
3122  * @adapter: pointer to private adapter struct
3123  **/
3124 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3125 {
3126         struct ixgbe_hw *hw = &adapter->hw;
3127
3128                 if (hw->phy.multispeed_fiber) {
3129                         /*
3130                          * In multispeed fiber setups, the device may not have
3131                          * had a physical connection when the driver loaded.
3132                          * If that's the case, the initial link configuration
3133                          * couldn't get the MAC into 10G or 1G mode, so we'll
3134                          * never have a link status change interrupt fire.
3135                          * We need to try and force an autonegotiation
3136                          * session, then bring up link.
3137                          */
3138                         hw->mac.ops.setup_sfp(hw);
3139                         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
3140                                 schedule_work(&adapter->multispeed_fiber_task);
3141                 } else {
3142                         /*
3143                          * Direct Attach Cu and non-multispeed fiber modules
3144                          * still need to be configured properly prior to
3145                          * attempting link.
3146                          */
3147                         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
3148                                 schedule_work(&adapter->sfp_config_module_task);
3149                 }
3150 }
3151
3152 /**
3153  * ixgbe_non_sfp_link_config - set up non-SFP+ link
3154  * @hw: pointer to private hardware struct
3155  *
3156  * Returns 0 on success, negative on failure
3157  **/
3158 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
3159 {
3160         u32 autoneg;
3161         bool negotiation, link_up = false;
3162         u32 ret = IXGBE_ERR_LINK_SETUP;
3163
3164         if (hw->mac.ops.check_link)
3165                 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3166
3167         if (ret)
3168                 goto link_cfg_out;
3169
3170         if (hw->mac.ops.get_link_capabilities)
3171                 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
3172         if (ret)
3173                 goto link_cfg_out;
3174
3175         if (hw->mac.ops.setup_link)
3176                 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
3177 link_cfg_out:
3178         return ret;
3179 }
3180
3181 #define IXGBE_MAX_RX_DESC_POLL 10
3182 static inline void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
3183                                               int rxr)
3184 {
3185         int j = adapter->rx_ring[rxr]->reg_idx;
3186         int k;
3187
3188         for (k = 0; k < IXGBE_MAX_RX_DESC_POLL; k++) {
3189                 if (IXGBE_READ_REG(&adapter->hw,
3190                                    IXGBE_RXDCTL(j)) & IXGBE_RXDCTL_ENABLE)
3191                         break;
3192                 else
3193                         msleep(1);
3194         }
3195         if (k >= IXGBE_MAX_RX_DESC_POLL) {
3196                 DPRINTK(DRV, ERR, "RXDCTL.ENABLE on Rx queue %d "
3197                         "not set within the polling period\n", rxr);
3198         }
3199         ixgbe_release_rx_desc(&adapter->hw, adapter->rx_ring[rxr],
3200                               (adapter->rx_ring[rxr]->count - 1));
3201 }
3202
3203 static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
3204 {
3205         struct net_device *netdev = adapter->netdev;
3206         struct ixgbe_hw *hw = &adapter->hw;
3207         int i, j = 0;
3208         int num_rx_rings = adapter->num_rx_queues;
3209         int err;
3210         int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3211         u32 txdctl, rxdctl, mhadd;
3212         u32 dmatxctl;
3213         u32 gpie;
3214         u32 ctrl_ext;
3215
3216         ixgbe_get_hw_control(adapter);
3217
3218         if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) ||
3219             (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) {
3220                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3221                         gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME |
3222                                 IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD);
3223                 } else {
3224                         /* MSI only */
3225                         gpie = 0;
3226                 }
3227                 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3228                         gpie &= ~IXGBE_GPIE_VTMODE_MASK;
3229                         gpie |= IXGBE_GPIE_VTMODE_64;
3230                 }
3231                 /* XXX: to interrupt immediately for EICS writes, enable this */
3232                 /* gpie |= IXGBE_GPIE_EIMEN; */
3233                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3234         }
3235
3236         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3237                 /*
3238                  * use EIAM to auto-mask when MSI-X interrupt is asserted
3239                  * this saves a register write for every interrupt
3240                  */
3241                 switch (hw->mac.type) {
3242                 case ixgbe_mac_82598EB:
3243                         IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3244                         break;
3245                 default:
3246                 case ixgbe_mac_82599EB:
3247                         IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3248                         IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3249                         break;
3250                 }
3251         } else {
3252                 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3253                  * specifically only auto mask tx and rx interrupts */
3254                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3255         }
3256
3257         /* Enable fan failure interrupt if media type is copper */
3258         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3259                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
3260                 gpie |= IXGBE_SDP1_GPIEN;
3261                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3262         }
3263
3264         if (hw->mac.type == ixgbe_mac_82599EB) {
3265                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
3266                 gpie |= IXGBE_SDP1_GPIEN;
3267                 gpie |= IXGBE_SDP2_GPIEN;
3268                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3269         }
3270
3271 #ifdef IXGBE_FCOE
3272         /* adjust max frame to be able to do baby jumbo for FCoE */
3273         if ((netdev->features & NETIF_F_FCOE_MTU) &&
3274             (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3275                 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3276
3277 #endif /* IXGBE_FCOE */
3278         mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3279         if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3280                 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3281                 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3282
3283                 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3284         }
3285
3286         for (i = 0; i < adapter->num_tx_queues; i++) {
3287                 j = adapter->tx_ring[i]->reg_idx;
3288                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3289                 if (adapter->rx_itr_setting == 0) {
3290                         /* cannot set wthresh when itr==0 */
3291                         txdctl &= ~0x007F0000;
3292                 } else {
3293                         /* enable WTHRESH=8 descriptors, to encourage burst writeback */
3294                         txdctl |= (8 << 16);
3295                 }
3296                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
3297         }
3298
3299         if (hw->mac.type == ixgbe_mac_82599EB) {
3300                 /* DMATXCTL.EN must be set after all Tx queue config is done */
3301                 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
3302                 dmatxctl |= IXGBE_DMATXCTL_TE;
3303                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
3304         }
3305         for (i = 0; i < adapter->num_tx_queues; i++) {
3306                 j = adapter->tx_ring[i]->reg_idx;
3307                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3308                 txdctl |= IXGBE_TXDCTL_ENABLE;
3309                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
3310                 if (hw->mac.type == ixgbe_mac_82599EB) {
3311                         int wait_loop = 10;
3312                         /* poll for Tx Enable ready */
3313                         do {
3314                                 msleep(1);
3315                                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3316                         } while (--wait_loop &&
3317                                  !(txdctl & IXGBE_TXDCTL_ENABLE));
3318                         if (!wait_loop)
3319                                 DPRINTK(DRV, ERR, "Could not enable "
3320                                         "Tx Queue %d\n", j);
3321                 }
3322         }
3323
3324         for (i = 0; i < num_rx_rings; i++) {
3325                 j = adapter->rx_ring[i]->reg_idx;
3326                 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3327                 /* enable PTHRESH=32 descriptors (half the internal cache)
3328                  * and HTHRESH=0 descriptors (to minimize latency on fetch),
3329                  * this also removes a pesky rx_no_buffer_count increment */
3330                 rxdctl |= 0x0020;
3331                 rxdctl |= IXGBE_RXDCTL_ENABLE;
3332                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl);
3333                 if (hw->mac.type == ixgbe_mac_82599EB)
3334                         ixgbe_rx_desc_queue_enable(adapter, i);
3335         }
3336         /* enable all receives */
3337         rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3338         if (hw->mac.type == ixgbe_mac_82598EB)
3339                 rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN);
3340         else
3341                 rxdctl |= IXGBE_RXCTRL_RXEN;
3342         hw->mac.ops.enable_rx_dma(hw, rxdctl);
3343
3344         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3345                 ixgbe_configure_msix(adapter);
3346         else
3347                 ixgbe_configure_msi_and_legacy(adapter);
3348
3349         /* enable the optics */
3350         if (hw->phy.multispeed_fiber)
3351                 hw->mac.ops.enable_tx_laser(hw);
3352
3353         clear_bit(__IXGBE_DOWN, &adapter->state);
3354         ixgbe_napi_enable_all(adapter);
3355
3356         /* clear any pending interrupts, may auto mask */
3357         IXGBE_READ_REG(hw, IXGBE_EICR);
3358
3359         ixgbe_irq_enable(adapter);
3360
3361         /*
3362          * If this adapter has a fan, check to see if we had a failure
3363          * before we enabled the interrupt.
3364          */
3365         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3366                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3367                 if (esdp & IXGBE_ESDP_SDP1)
3368                         DPRINTK(DRV, CRIT,
3369                                 "Fan has stopped, replace the adapter\n");
3370         }
3371
3372         /*
3373          * For hot-pluggable SFP+ devices, a new SFP+ module may have
3374          * arrived before interrupts were enabled but after probe.  Such
3375          * devices wouldn't have their type identified yet. We need to
3376          * kick off the SFP+ module setup first, then try to bring up link.
3377          * If we're not hot-pluggable SFP+, we just need to configure link
3378          * and bring it up.
3379          */
3380         if (hw->phy.type == ixgbe_phy_unknown) {
3381                 err = hw->phy.ops.identify(hw);
3382                 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
3383                         /*
3384                          * Take the device down and schedule the sfp tasklet
3385                          * which will unregister_netdev and log it.
3386                          */
3387                         ixgbe_down(adapter);
3388                         schedule_work(&adapter->sfp_config_module_task);
3389                         return err;
3390                 }
3391         }
3392
3393         if (ixgbe_is_sfp(hw)) {
3394                 ixgbe_sfp_link_config(adapter);
3395         } else {
3396                 err = ixgbe_non_sfp_link_config(hw);
3397                 if (err)
3398                         DPRINTK(PROBE, ERR, "link_config FAILED %d\n", err);
3399         }
3400
3401         for (i = 0; i < adapter->num_tx_queues; i++)
3402                 set_bit(__IXGBE_FDIR_INIT_DONE,
3403                         &(adapter->tx_ring[i]->reinit_state));
3404
3405         /* enable transmits */
3406         netif_tx_start_all_queues(netdev);
3407
3408         /* bring the link up in the watchdog, this could race with our first
3409          * link up interrupt but shouldn't be a problem */
3410         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3411         adapter->link_check_timeout = jiffies;
3412         mod_timer(&adapter->watchdog_timer, jiffies);
3413
3414         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3415         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3416         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
3417         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3418
3419         return 0;
3420 }
3421
3422 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
3423 {
3424         WARN_ON(in_interrupt());
3425         while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
3426                 msleep(1);
3427         ixgbe_down(adapter);
3428         /*
3429          * If SR-IOV enabled then wait a bit before bringing the adapter
3430          * back up to give the VFs time to respond to the reset.  The
3431          * two second wait is based upon the watchdog timer cycle in
3432          * the VF driver.
3433          */
3434         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3435                 msleep(2000);
3436         ixgbe_up(adapter);
3437         clear_bit(__IXGBE_RESETTING, &adapter->state);
3438 }
3439
3440 int ixgbe_up(struct ixgbe_adapter *adapter)
3441 {
3442         /* hardware has been reset, we need to reload some things */
3443         ixgbe_configure(adapter);
3444
3445         return ixgbe_up_complete(adapter);
3446 }
3447
3448 void ixgbe_reset(struct ixgbe_adapter *adapter)
3449 {
3450         struct ixgbe_hw *hw = &adapter->hw;
3451         int err;
3452
3453         err = hw->mac.ops.init_hw(hw);
3454         switch (err) {
3455         case 0:
3456         case IXGBE_ERR_SFP_NOT_PRESENT:
3457                 break;
3458         case IXGBE_ERR_MASTER_REQUESTS_PENDING:
3459                 dev_err(&adapter->pdev->dev, "master disable timed out\n");
3460                 break;
3461         case IXGBE_ERR_EEPROM_VERSION:
3462                 /* We are running on a pre-production device, log a warning */
3463                 dev_warn(&adapter->pdev->dev, "This device is a pre-production "
3464                          "adapter/LOM.  Please be aware there may be issues "
3465                          "associated with your hardware.  If you are "
3466                          "experiencing problems please contact your Intel or "
3467                          "hardware representative who provided you with this "
3468                          "hardware.\n");
3469                 break;
3470         default:
3471                 dev_err(&adapter->pdev->dev, "Hardware Error: %d\n", err);
3472         }
3473
3474         /* reprogram the RAR[0] in case user changed it. */
3475         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
3476                             IXGBE_RAH_AV);
3477 }
3478
3479 /**
3480  * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
3481  * @adapter: board private structure
3482  * @rx_ring: ring to free buffers from
3483  **/
3484 static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
3485                                 struct ixgbe_ring *rx_ring)
3486 {
3487         struct pci_dev *pdev = adapter->pdev;
3488         unsigned long size;
3489         unsigned int i;
3490
3491         /* Free all the Rx ring sk_buffs */
3492
3493         for (i = 0; i < rx_ring->count; i++) {
3494                 struct ixgbe_rx_buffer *rx_buffer_info;
3495
3496                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
3497                 if (rx_buffer_info->dma) {
3498                         dma_unmap_single(&pdev->dev, rx_buffer_info->dma,
3499                                          rx_ring->rx_buf_len,
3500                                          DMA_FROM_DEVICE);
3501                         rx_buffer_info->dma = 0;
3502                 }
3503                 if (rx_buffer_info->skb) {
3504                         struct sk_buff *skb = rx_buffer_info->skb;
3505                         rx_buffer_info->skb = NULL;
3506                         do {
3507                                 struct sk_buff *this = skb;
3508                                 if (IXGBE_RSC_CB(this)->dma) {
3509                                         dma_unmap_single(&pdev->dev,
3510                                                          IXGBE_RSC_CB(this)->dma,
3511                                                          rx_ring->rx_buf_len,
3512                                                          DMA_FROM_DEVICE);
3513                                         IXGBE_RSC_CB(this)->dma = 0;
3514                                 }
3515                                 skb = skb->prev;
3516                                 dev_kfree_skb(this);
3517                         } while (skb);
3518                 }
3519                 if (!rx_buffer_info->page)
3520                         continue;
3521                 if (rx_buffer_info->page_dma) {
3522                         dma_unmap_page(&pdev->dev, rx_buffer_info->page_dma,
3523                                        PAGE_SIZE / 2, DMA_FROM_DEVICE);
3524                         rx_buffer_info->page_dma = 0;
3525                 }
3526                 put_page(rx_buffer_info->page);
3527                 rx_buffer_info->page = NULL;
3528                 rx_buffer_info->page_offset = 0;
3529         }
3530
3531         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
3532         memset(rx_ring->rx_buffer_info, 0, size);
3533
3534         /* Zero out the descriptor ring */
3535         memset(rx_ring->desc, 0, rx_ring->size);
3536
3537         rx_ring->next_to_clean = 0;
3538         rx_ring->next_to_use = 0;
3539
3540         if (rx_ring->head)
3541                 writel(0, adapter->hw.hw_addr + rx_ring->head);
3542         if (rx_ring->tail)
3543                 writel(0, adapter->hw.hw_addr + rx_ring->tail);
3544 }
3545
3546 /**
3547  * ixgbe_clean_tx_ring - Free Tx Buffers
3548  * @adapter: board private structure
3549  * @tx_ring: ring to be cleaned
3550  **/
3551 static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
3552                                 struct ixgbe_ring *tx_ring)
3553 {
3554         struct ixgbe_tx_buffer *tx_buffer_info;
3555         unsigned long size;
3556         unsigned int i;
3557
3558         /* Free all the Tx ring sk_buffs */
3559
3560         for (i = 0; i < tx_ring->count; i++) {
3561                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3562                 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
3563         }
3564
3565         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3566         memset(tx_ring->tx_buffer_info, 0, size);
3567
3568         /* Zero out the descriptor ring */
3569         memset(tx_ring->desc, 0, tx_ring->size);
3570
3571         tx_ring->next_to_use = 0;
3572         tx_ring->next_to_clean = 0;
3573
3574         if (tx_ring->head)
3575                 writel(0, adapter->hw.hw_addr + tx_ring->head);
3576         if (tx_ring->tail)
3577                 writel(0, adapter->hw.hw_addr + tx_ring->tail);
3578 }
3579
3580 /**
3581  * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
3582  * @adapter: board private structure
3583  **/
3584 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
3585 {
3586         int i;
3587
3588         for (i = 0; i < adapter->num_rx_queues; i++)
3589                 ixgbe_clean_rx_ring(adapter, adapter->rx_ring[i]);
3590 }
3591
3592 /**
3593  * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
3594  * @adapter: board private structure
3595  **/
3596 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
3597 {
3598         int i;
3599
3600         for (i = 0; i < adapter->num_tx_queues; i++)
3601                 ixgbe_clean_tx_ring(adapter, adapter->tx_ring[i]);
3602 }
3603
3604 void ixgbe_down(struct ixgbe_adapter *adapter)
3605 {
3606         struct net_device *netdev = adapter->netdev;
3607         struct ixgbe_hw *hw = &adapter->hw;
3608         u32 rxctrl;
3609         u32 txdctl;
3610         int i, j;
3611
3612         /* signal that we are down to the interrupt handler */
3613         set_bit(__IXGBE_DOWN, &adapter->state);
3614
3615         /* power down the optics */
3616         if (hw->phy.multispeed_fiber)
3617                 hw->mac.ops.disable_tx_laser(hw);
3618
3619         /* disable receive for all VFs and wait one second */
3620         if (adapter->num_vfs) {
3621                 /* ping all the active vfs to let them know we are going down */
3622                 ixgbe_ping_all_vfs(adapter);
3623
3624                 /* Disable all VFTE/VFRE TX/RX */
3625                 ixgbe_disable_tx_rx(adapter);
3626
3627                 /* Mark all the VFs as inactive */
3628                 for (i = 0 ; i < adapter->num_vfs; i++)
3629                         adapter->vfinfo[i].clear_to_send = 0;
3630         }
3631
3632         /* disable receives */
3633         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3634         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3635
3636         IXGBE_WRITE_FLUSH(hw);
3637         msleep(10);
3638
3639         netif_tx_stop_all_queues(netdev);
3640
3641         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
3642         del_timer_sync(&adapter->sfp_timer);
3643         del_timer_sync(&adapter->watchdog_timer);
3644         cancel_work_sync(&adapter->watchdog_task);
3645
3646         netif_carrier_off(netdev);
3647         netif_tx_disable(netdev);
3648
3649         ixgbe_irq_disable(adapter);
3650
3651         ixgbe_napi_disable_all(adapter);
3652
3653         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3654             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
3655                 cancel_work_sync(&adapter->fdir_reinit_task);
3656
3657         /* disable transmits in the hardware now that interrupts are off */
3658         for (i = 0; i < adapter->num_tx_queues; i++) {
3659                 j = adapter->tx_ring[i]->reg_idx;
3660                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3661                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j),
3662                                 (txdctl & ~IXGBE_TXDCTL_ENABLE));
3663         }
3664         /* Disable the Tx DMA engine on 82599 */
3665         if (hw->mac.type == ixgbe_mac_82599EB)
3666                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
3667                                 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
3668                                  ~IXGBE_DMATXCTL_TE));
3669
3670         /* clear n-tuple filters that are cached */
3671         ethtool_ntuple_flush(netdev);
3672
3673         if (!pci_channel_offline(adapter->pdev))
3674                 ixgbe_reset(adapter);
3675         ixgbe_clean_all_tx_rings(adapter);
3676         ixgbe_clean_all_rx_rings(adapter);
3677
3678 #ifdef CONFIG_IXGBE_DCA
3679         /* since we reset the hardware DCA settings were cleared */
3680         ixgbe_setup_dca(adapter);
3681 #endif
3682 }
3683
3684 /**
3685  * ixgbe_poll - NAPI Rx polling callback
3686  * @napi: structure for representing this polling device
3687  * @budget: how many packets driver is allowed to clean
3688  *
3689  * This function is used for legacy and MSI, NAPI mode
3690  **/
3691 static int ixgbe_poll(struct napi_struct *napi, int budget)
3692 {
3693         struct ixgbe_q_vector *q_vector =
3694                                 container_of(napi, struct ixgbe_q_vector, napi);
3695         struct ixgbe_adapter *adapter = q_vector->adapter;
3696         int tx_clean_complete, work_done = 0;
3697
3698 #ifdef CONFIG_IXGBE_DCA
3699         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
3700                 ixgbe_update_tx_dca(adapter, adapter->tx_ring[0]);
3701                 ixgbe_update_rx_dca(adapter, adapter->rx_ring[0]);
3702         }
3703 #endif
3704
3705         tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring[0]);
3706         ixgbe_clean_rx_irq(q_vector, adapter->rx_ring[0], &work_done, budget);
3707
3708         if (!tx_clean_complete)
3709                 work_done = budget;
3710
3711         /* If budget not fully consumed, exit the polling mode */
3712         if (work_done < budget) {
3713                 napi_complete(napi);
3714                 if (adapter->rx_itr_setting & 1)
3715                         ixgbe_set_itr(adapter);
3716                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
3717                         ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
3718         }
3719         return work_done;
3720 }
3721
3722 /**
3723  * ixgbe_tx_timeout - Respond to a Tx Hang
3724  * @netdev: network interface device structure
3725  **/
3726 static void ixgbe_tx_timeout(struct net_device *netdev)
3727 {
3728         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3729
3730         /* Do the reset outside of interrupt context */
3731         schedule_work(&adapter->reset_task);
3732 }
3733
3734 static void ixgbe_reset_task(struct work_struct *work)
3735 {
3736         struct ixgbe_adapter *adapter;
3737         adapter = container_of(work, struct ixgbe_adapter, reset_task);
3738
3739         /* If we're already down or resetting, just bail */
3740         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
3741             test_bit(__IXGBE_RESETTING, &adapter->state))
3742                 return;
3743
3744         adapter->tx_timeout_count++;
3745
3746         ixgbe_dump(adapter);
3747         netdev_err(adapter->netdev, "Reset adapter\n");
3748         ixgbe_reinit_locked(adapter);
3749 }
3750
3751 #ifdef CONFIG_IXGBE_DCB
3752 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
3753 {
3754         bool ret = false;
3755         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB];
3756
3757         if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
3758                 return ret;
3759
3760         f->mask = 0x7 << 3;
3761         adapter->num_rx_queues = f->indices;
3762         adapter->num_tx_queues = f->indices;
3763         ret = true;
3764
3765         return ret;
3766 }
3767 #endif
3768
3769 /**
3770  * ixgbe_set_rss_queues: Allocate queues for RSS
3771  * @adapter: board private structure to initialize
3772  *
3773  * This is our "base" multiqueue mode.  RSS (Receive Side Scaling) will try
3774  * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
3775  *
3776  **/
3777 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
3778 {
3779         bool ret = false;
3780         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
3781
3782         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3783                 f->mask = 0xF;
3784                 adapter->num_rx_queues = f->indices;
3785                 adapter->num_tx_queues = f->indices;
3786                 ret = true;
3787         } else {
3788                 ret = false;
3789         }
3790
3791         return ret;
3792 }
3793
3794 /**
3795  * ixgbe_set_fdir_queues: Allocate queues for Flow Director
3796  * @adapter: board private structure to initialize
3797  *
3798  * Flow Director is an advanced Rx filter, attempting to get Rx flows back
3799  * to the original CPU that initiated the Tx session.  This runs in addition
3800  * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
3801  * Rx load across CPUs using RSS.
3802  *
3803  **/
3804 static bool inline ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
3805 {
3806         bool ret = false;
3807         struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
3808
3809         f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
3810         f_fdir->mask = 0;
3811
3812         /* Flow Director must have RSS enabled */
3813         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
3814             ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3815              (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) {
3816                 adapter->num_tx_queues = f_fdir->indices;
3817                 adapter->num_rx_queues = f_fdir->indices;
3818                 ret = true;
3819         } else {
3820                 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
3821                 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
3822         }
3823         return ret;
3824 }
3825
3826 #ifdef IXGBE_FCOE
3827 /**
3828  * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
3829  * @adapter: board private structure to initialize
3830  *
3831  * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
3832  * The ring feature mask is not used as a mask for FCoE, as it can take any 8
3833  * rx queues out of the max number of rx queues, instead, it is used as the
3834  * index of the first rx queue used by FCoE.
3835  *
3836  **/
3837 static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
3838 {
3839         bool ret = false;
3840         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
3841
3842         f->indices = min((int)num_online_cpus(), f->indices);
3843         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
3844                 adapter->num_rx_queues = 1;
3845                 adapter->num_tx_queues = 1;
3846 #ifdef CONFIG_IXGBE_DCB
3847                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3848                         DPRINTK(PROBE, INFO, "FCoE enabled with DCB\n");
3849                         ixgbe_set_dcb_queues(adapter);
3850                 }
3851 #endif
3852                 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3853                         DPRINTK(PROBE, INFO, "FCoE enabled with RSS\n");
3854                         if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3855                             (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
3856                                 ixgbe_set_fdir_queues(adapter);
3857                         else
3858                                 ixgbe_set_rss_queues(adapter);
3859                 }
3860                 /* adding FCoE rx rings to the end */
3861                 f->mask = adapter->num_rx_queues;
3862                 adapter->num_rx_queues += f->indices;
3863                 adapter->num_tx_queues += f->indices;
3864
3865                 ret = true;
3866         }
3867
3868         return ret;
3869 }
3870
3871 #endif /* IXGBE_FCOE */
3872 /**
3873  * ixgbe_set_sriov_queues: Allocate queues for IOV use
3874  * @adapter: board private structure to initialize
3875  *
3876  * IOV doesn't actually use anything, so just NAK the
3877  * request for now and let the other queue routines
3878  * figure out what to do.
3879  */
3880 static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
3881 {
3882         return false;
3883 }
3884
3885 /*
3886  * ixgbe_set_num_queues: Allocate queues for device, feature dependant
3887  * @adapter: board private structure to initialize
3888  *
3889  * This is the top level queue allocation routine.  The order here is very
3890  * important, starting with the "most" number of features turned on at once,
3891  * and ending with the smallest set of features.  This way large combinations
3892  * can be allocated if they're turned on, and smaller combinations are the
3893  * fallthrough conditions.
3894  *
3895  **/
3896 static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
3897 {
3898         /* Start with base case */
3899         adapter->num_rx_queues = 1;
3900         adapter->num_tx_queues = 1;
3901         adapter->num_rx_pools = adapter->num_rx_queues;
3902         adapter->num_rx_queues_per_pool = 1;
3903
3904         if (ixgbe_set_sriov_queues(adapter))
3905                 return;
3906
3907 #ifdef IXGBE_FCOE
3908         if (ixgbe_set_fcoe_queues(adapter))
3909                 goto done;
3910
3911 #endif /* IXGBE_FCOE */
3912 #ifdef CONFIG_IXGBE_DCB
3913         if (ixgbe_set_dcb_queues(adapter))
3914                 goto done;
3915
3916 #endif
3917         if (ixgbe_set_fdir_queues(adapter))
3918                 goto done;
3919
3920         if (ixgbe_set_rss_queues(adapter))
3921                 goto done;
3922
3923         /* fallback to base case */
3924         adapter->num_rx_queues = 1;
3925         adapter->num_tx_queues = 1;
3926
3927 done:
3928         /* Notify the stack of the (possibly) reduced Tx Queue count. */
3929         adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
3930 }
3931
3932 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
3933                                        int vectors)
3934 {
3935         int err, vector_threshold;
3936
3937         /* We'll want at least 3 (vector_threshold):
3938          * 1) TxQ[0] Cleanup
3939          * 2) RxQ[0] Cleanup
3940          * 3) Other (Link Status Change, etc.)
3941          * 4) TCP Timer (optional)
3942          */
3943         vector_threshold = MIN_MSIX_COUNT;
3944
3945         /* The more we get, the more we will assign to Tx/Rx Cleanup
3946          * for the separate queues...where Rx Cleanup >= Tx Cleanup.
3947          * Right now, we simply care about how many we'll get; we'll
3948          * set them up later while requesting irq's.
3949          */
3950         while (vectors >= vector_threshold) {
3951                 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
3952                                       vectors);
3953                 if (!err) /* Success in acquiring all requested vectors. */
3954                         break;
3955                 else if (err < 0)
3956                         vectors = 0; /* Nasty failure, quit now */
3957                 else /* err == number of vectors we should try again with */
3958                         vectors = err;
3959         }
3960
3961         if (vectors < vector_threshold) {
3962                 /* Can't allocate enough MSI-X interrupts?  Oh well.
3963                  * This just means we'll go with either a single MSI
3964                  * vector or fall back to legacy interrupts.
3965                  */
3966                 DPRINTK(HW, DEBUG, "Unable to allocate MSI-X interrupts\n");
3967                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
3968                 kfree(adapter->msix_entries);
3969                 adapter->msix_entries = NULL;
3970         } else {
3971                 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
3972                 /*
3973                  * Adjust for only the vectors we'll use, which is minimum
3974                  * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
3975                  * vectors we were allocated.
3976                  */
3977                 adapter->num_msix_vectors = min(vectors,
3978                                    adapter->max_msix_q_vectors + NON_Q_VECTORS);
3979         }
3980 }
3981
3982 /**
3983  * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
3984  * @adapter: board private structure to initialize
3985  *
3986  * Cache the descriptor ring offsets for RSS to the assigned rings.
3987  *
3988  **/
3989 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
3990 {
3991         int i;
3992         bool ret = false;
3993
3994         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3995                 for (i = 0; i < adapter->num_rx_queues; i++)
3996                         adapter->rx_ring[i]->reg_idx = i;
3997                 for (i = 0; i < adapter->num_tx_queues; i++)
3998                         adapter->tx_ring[i]->reg_idx = i;
3999                 ret = true;
4000         } else {
4001                 ret = false;
4002         }
4003
4004         return ret;
4005 }
4006
4007 #ifdef CONFIG_IXGBE_DCB
4008 /**
4009  * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4010  * @adapter: board private structure to initialize
4011  *
4012  * Cache the descriptor ring offsets for DCB to the assigned rings.
4013  *
4014  **/
4015 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
4016 {
4017         int i;
4018         bool ret = false;
4019         int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
4020
4021         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4022                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
4023                         /* the number of queues is assumed to be symmetric */
4024                         for (i = 0; i < dcb_i; i++) {
4025                                 adapter->rx_ring[i]->reg_idx = i << 3;
4026                                 adapter->tx_ring[i]->reg_idx = i << 2;
4027                         }
4028                         ret = true;
4029                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
4030                         if (dcb_i == 8) {
4031                                 /*
4032                                  * Tx TC0 starts at: descriptor queue 0
4033                                  * Tx TC1 starts at: descriptor queue 32
4034                                  * Tx TC2 starts at: descriptor queue 64
4035                                  * Tx TC3 starts at: descriptor queue 80
4036                                  * Tx TC4 starts at: descriptor queue 96
4037                                  * Tx TC5 starts at: descriptor queue 104
4038                                  * Tx TC6 starts at: descriptor queue 112
4039                                  * Tx TC7 starts at: descriptor queue 120
4040                                  *
4041                                  * Rx TC0-TC7 are offset by 16 queues each
4042                                  */
4043                                 for (i = 0; i < 3; i++) {
4044                                         adapter->tx_ring[i]->reg_idx = i << 5;
4045                                         adapter->rx_ring[i]->reg_idx = i << 4;
4046                                 }
4047                                 for ( ; i < 5; i++) {
4048                                         adapter->tx_ring[i]->reg_idx =
4049                                                                  ((i + 2) << 4);
4050                                         adapter->rx_ring[i]->reg_idx = i << 4;
4051                                 }
4052                                 for ( ; i < dcb_i; i++) {
4053                                         adapter->tx_ring[i]->reg_idx =
4054                                                                  ((i + 8) << 3);
4055                                         adapter->rx_ring[i]->reg_idx = i << 4;
4056                                 }
4057
4058                                 ret = true;
4059                         } else if (dcb_i == 4) {
4060                                 /*
4061                                  * Tx TC0 starts at: descriptor queue 0
4062                                  * Tx TC1 starts at: descriptor queue 64
4063                                  * Tx TC2 starts at: descriptor queue 96
4064                                  * Tx TC3 starts at: descriptor queue 112
4065                                  *
4066                                  * Rx TC0-TC3 are offset by 32 queues each
4067                                  */
4068                                 adapter->tx_ring[0]->reg_idx = 0;
4069                                 adapter->tx_ring[1]->reg_idx = 64;
4070                                 adapter->tx_ring[2]->reg_idx = 96;
4071                                 adapter->tx_ring[3]->reg_idx = 112;
4072                                 for (i = 0 ; i < dcb_i; i++)
4073                                         adapter->rx_ring[i]->reg_idx = i << 5;
4074
4075                                 ret = true;
4076                         } else {
4077                                 ret = false;
4078                         }
4079                 } else {
4080                         ret = false;
4081                 }
4082         } else {
4083                 ret = false;
4084         }
4085
4086         return ret;
4087 }
4088 #endif
4089
4090 /**
4091  * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
4092  * @adapter: board private structure to initialize
4093  *
4094  * Cache the descriptor ring offsets for Flow Director to the assigned rings.
4095  *
4096  **/
4097 static bool inline ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
4098 {
4099         int i;
4100         bool ret = false;
4101
4102         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
4103             ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4104              (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) {
4105                 for (i = 0; i < adapter->num_rx_queues; i++)
4106                         adapter->rx_ring[i]->reg_idx = i;
4107                 for (i = 0; i < adapter->num_tx_queues; i++)
4108                         adapter->tx_ring[i]->reg_idx = i;
4109                 ret = true;
4110         }
4111
4112         return ret;
4113 }
4114
4115 #ifdef IXGBE_FCOE
4116 /**
4117  * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
4118  * @adapter: board private structure to initialize
4119  *
4120  * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
4121  *
4122  */
4123 static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
4124 {
4125         int i, fcoe_rx_i = 0, fcoe_tx_i = 0;
4126         bool ret = false;
4127         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4128
4129         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
4130 #ifdef CONFIG_IXGBE_DCB
4131                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4132                         struct ixgbe_fcoe *fcoe = &adapter->fcoe;
4133
4134                         ixgbe_cache_ring_dcb(adapter);
4135                         /* find out queues in TC for FCoE */
4136                         fcoe_rx_i = adapter->rx_ring[fcoe->tc]->reg_idx + 1;
4137                         fcoe_tx_i = adapter->tx_ring[fcoe->tc]->reg_idx + 1;
4138                         /*
4139                          * In 82599, the number of Tx queues for each traffic
4140                          * class for both 8-TC and 4-TC modes are:
4141                          * TCs  : TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7
4142                          * 8 TCs:  32  32  16  16   8   8   8   8
4143                          * 4 TCs:  64  64  32  32
4144                          * We have max 8 queues for FCoE, where 8 the is
4145                          * FCoE redirection table size. If TC for FCoE is
4146                          * less than or equal to TC3, we have enough queues
4147                          * to add max of 8 queues for FCoE, so we start FCoE
4148                          * tx descriptor from the next one, i.e., reg_idx + 1.
4149                          * If TC for FCoE is above TC3, implying 8 TC mode,
4150                          * and we need 8 for FCoE, we have to take all queues
4151                          * in that traffic class for FCoE.
4152                          */
4153                         if ((f->indices == IXGBE_FCRETA_SIZE) && (fcoe->tc > 3))
4154                                 fcoe_tx_i--;
4155                 }
4156 #endif /* CONFIG_IXGBE_DCB */
4157                 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4158                         if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4159                             (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
4160                                 ixgbe_cache_ring_fdir(adapter);
4161                         else
4162                                 ixgbe_cache_ring_rss(adapter);
4163
4164                         fcoe_rx_i = f->mask;
4165                         fcoe_tx_i = f->mask;
4166                 }
4167                 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
4168                         adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
4169                         adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
4170                 }
4171                 ret = true;
4172         }
4173         return ret;
4174 }
4175
4176 #endif /* IXGBE_FCOE */
4177 /**
4178  * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
4179  * @adapter: board private structure to initialize
4180  *
4181  * SR-IOV doesn't use any descriptor rings but changes the default if
4182  * no other mapping is used.
4183  *
4184  */
4185 static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
4186 {
4187         adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2;
4188         adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2;
4189         if (adapter->num_vfs)
4190                 return true;
4191         else
4192                 return false;
4193 }
4194
4195 /**
4196  * ixgbe_cache_ring_register - Descriptor ring to register mapping
4197  * @adapter: board private structure to initialize
4198  *
4199  * Once we know the feature-set enabled for the device, we'll cache
4200  * the register offset the descriptor ring is assigned to.
4201  *
4202  * Note, the order the various feature calls is important.  It must start with
4203  * the "most" features enabled at the same time, then trickle down to the
4204  * least amount of features turned on at once.
4205  **/
4206 static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
4207 {
4208         /* start with default case */
4209         adapter->rx_ring[0]->reg_idx = 0;
4210         adapter->tx_ring[0]->reg_idx = 0;
4211
4212         if (ixgbe_cache_ring_sriov(adapter))
4213                 return;
4214
4215 #ifdef IXGBE_FCOE
4216         if (ixgbe_cache_ring_fcoe(adapter))
4217                 return;
4218
4219 #endif /* IXGBE_FCOE */
4220 #ifdef CONFIG_IXGBE_DCB
4221         if (ixgbe_cache_ring_dcb(adapter))
4222                 return;
4223
4224 #endif
4225         if (ixgbe_cache_ring_fdir(adapter))
4226                 return;
4227
4228         if (ixgbe_cache_ring_rss(adapter))
4229                 return;
4230 }
4231
4232 /**
4233  * ixgbe_alloc_queues - Allocate memory for all rings
4234  * @adapter: board private structure to initialize
4235  *
4236  * We allocate one ring per queue at run-time since we don't know the
4237  * number of queues at compile-time.  The polling_netdev array is
4238  * intended for Multiqueue, but should work fine with a single queue.
4239  **/
4240 static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
4241 {
4242         int i;
4243         int orig_node = adapter->node;
4244
4245         for (i = 0; i < adapter->num_tx_queues; i++) {
4246                 struct ixgbe_ring *ring = adapter->tx_ring[i];
4247                 if (orig_node == -1) {
4248                         int cur_node = next_online_node(adapter->node);
4249                         if (cur_node == MAX_NUMNODES)
4250                                 cur_node = first_online_node;
4251                         adapter->node = cur_node;
4252                 }
4253                 ring = kzalloc_node(sizeof(struct ixgbe_ring), GFP_KERNEL,
4254                                     adapter->node);
4255                 if (!ring)
4256                         ring = kzalloc(sizeof(struct ixgbe_ring), GFP_KERNEL);
4257                 if (!ring)
4258                         goto err_tx_ring_allocation;
4259                 ring->count = adapter->tx_ring_count;
4260                 ring->queue_index = i;
4261                 ring->numa_node = adapter->node;
4262
4263                 adapter->tx_ring[i] = ring;
4264         }
4265
4266         /* Restore the adapter's original node */
4267         adapter->node = orig_node;
4268
4269         for (i = 0; i < adapter->num_rx_queues; i++) {
4270                 struct ixgbe_ring *ring = adapter->rx_ring[i];
4271                 if (orig_node == -1) {
4272                         int cur_node = next_online_node(adapter->node);
4273                         if (cur_node == MAX_NUMNODES)
4274                                 cur_node = first_online_node;
4275                         adapter->node = cur_node;
4276                 }
4277                 ring = kzalloc_node(sizeof(struct ixgbe_ring), GFP_KERNEL,
4278                                     adapter->node);
4279                 if (!ring)
4280                         ring = kzalloc(sizeof(struct ixgbe_ring), GFP_KERNEL);
4281                 if (!ring)
4282                         goto err_rx_ring_allocation;
4283                 ring->count = adapter->rx_ring_count;
4284                 ring->queue_index = i;
4285                 ring->numa_node = adapter->node;
4286
4287                 adapter->rx_ring[i] = ring;
4288         }
4289
4290         /* Restore the adapter's original node */
4291         adapter->node = orig_node;
4292
4293         ixgbe_cache_ring_register(adapter);
4294
4295         return 0;
4296
4297 err_rx_ring_allocation:
4298         for (i = 0; i < adapter->num_tx_queues; i++)
4299                 kfree(adapter->tx_ring[i]);
4300 err_tx_ring_allocation:
4301         return -ENOMEM;
4302 }
4303
4304 /**
4305  * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
4306  * @adapter: board private structure to initialize
4307  *
4308  * Attempt to configure the interrupts using the best available
4309  * capabilities of the hardware and the kernel.
4310  **/
4311 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
4312 {
4313         struct ixgbe_hw *hw = &adapter->hw;
4314         int err = 0;
4315         int vector, v_budget;
4316
4317         /*
4318          * It's easy to be greedy for MSI-X vectors, but it really
4319          * doesn't do us much good if we have a lot more vectors
4320          * than CPU's.  So let's be conservative and only ask for
4321          * (roughly) the same number of vectors as there are CPU's.
4322          */
4323         v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
4324                        (int)num_online_cpus()) + NON_Q_VECTORS;
4325
4326         /*
4327          * At the same time, hardware can only support a maximum of
4328          * hw.mac->max_msix_vectors vectors.  With features
4329          * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
4330          * descriptor queues supported by our device.  Thus, we cap it off in
4331          * those rare cases where the cpu count also exceeds our vector limit.
4332          */
4333         v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
4334
4335         /* A failure in MSI-X entry allocation isn't fatal, but it does
4336          * mean we disable MSI-X capabilities of the adapter. */
4337         adapter->msix_entries = kcalloc(v_budget,
4338                                         sizeof(struct msix_entry), GFP_KERNEL);
4339         if (adapter->msix_entries) {
4340                 for (vector = 0; vector < v_budget; vector++)
4341                         adapter->msix_entries[vector].entry = vector;
4342
4343                 ixgbe_acquire_msix_vectors(adapter, v_budget);
4344
4345                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4346                         goto out;
4347         }
4348
4349         adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
4350         adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
4351         adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4352         adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4353         adapter->atr_sample_rate = 0;
4354         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4355                 ixgbe_disable_sriov(adapter);
4356
4357         ixgbe_set_num_queues(adapter);
4358
4359         err = pci_enable_msi(adapter->pdev);
4360         if (!err) {
4361                 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
4362         } else {
4363                 DPRINTK(HW, DEBUG, "Unable to allocate MSI interrupt, "
4364                         "falling back to legacy.  Error: %d\n", err);
4365                 /* reset err */
4366                 err = 0;
4367         }
4368
4369 out:
4370         return err;
4371 }
4372
4373 /**
4374  * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4375  * @adapter: board private structure to initialize
4376  *
4377  * We allocate one q_vector per queue interrupt.  If allocation fails we
4378  * return -ENOMEM.
4379  **/
4380 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
4381 {
4382         int q_idx, num_q_vectors;
4383         struct ixgbe_q_vector *q_vector;
4384         int napi_vectors;
4385         int (*poll)(struct napi_struct *, int);
4386
4387         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4388                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4389                 napi_vectors = adapter->num_rx_queues;
4390                 poll = &ixgbe_clean_rxtx_many;
4391         } else {
4392                 num_q_vectors = 1;
4393                 napi_vectors = 1;
4394                 poll = &ixgbe_poll;
4395         }
4396
4397         for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4398                 q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector),
4399                                         GFP_KERNEL, adapter->node);
4400                 if (!q_vector)
4401                         q_vector = kzalloc(sizeof(struct ixgbe_q_vector),
4402                                            GFP_KERNEL);
4403                 if (!q_vector)
4404                         goto err_out;
4405                 q_vector->adapter = adapter;
4406                 if (q_vector->txr_count && !q_vector->rxr_count)
4407                         q_vector->eitr = adapter->tx_eitr_param;
4408                 else
4409                         q_vector->eitr = adapter->rx_eitr_param;
4410                 q_vector->v_idx = q_idx;
4411                 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
4412                 adapter->q_vector[q_idx] = q_vector;
4413         }
4414
4415         return 0;
4416
4417 err_out:
4418         while (q_idx) {
4419                 q_idx--;
4420                 q_vector = adapter->q_vector[q_idx];
4421                 netif_napi_del(&q_vector->napi);
4422                 kfree(q_vector);
4423                 adapter->q_vector[q_idx] = NULL;
4424         }
4425         return -ENOMEM;
4426 }
4427
4428 /**
4429  * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
4430  * @adapter: board private structure to initialize
4431  *
4432  * This function frees the memory allocated to the q_vectors.  In addition if
4433  * NAPI is enabled it will delete any references to the NAPI struct prior
4434  * to freeing the q_vector.
4435  **/
4436 static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
4437 {
4438         int q_idx, num_q_vectors;
4439
4440         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4441                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4442         else
4443                 num_q_vectors = 1;
4444
4445         for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4446                 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
4447                 adapter->q_vector[q_idx] = NULL;
4448                 netif_napi_del(&q_vector->napi);
4449                 kfree(q_vector);
4450         }
4451 }
4452
4453 static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
4454 {
4455         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4456                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4457                 pci_disable_msix(adapter->pdev);
4458                 kfree(adapter->msix_entries);
4459                 adapter->msix_entries = NULL;
4460         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
4461                 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
4462                 pci_disable_msi(adapter->pdev);
4463         }
4464         return;
4465 }
4466
4467 /**
4468  * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
4469  * @adapter: board private structure to initialize
4470  *
4471  * We determine which interrupt scheme to use based on...
4472  * - Kernel support (MSI, MSI-X)
4473  *   - which can be user-defined (via MODULE_PARAM)
4474  * - Hardware queue count (num_*_queues)
4475  *   - defined by miscellaneous hardware support/features (RSS, etc.)
4476  **/
4477 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
4478 {
4479         int err;
4480
4481         /* Number of supported queues */
4482         ixgbe_set_num_queues(adapter);
4483
4484         err = ixgbe_set_interrupt_capability(adapter);
4485         if (err) {
4486                 DPRINTK(PROBE, ERR, "Unable to setup interrupt capabilities\n");
4487                 goto err_set_interrupt;
4488         }
4489
4490         err = ixgbe_alloc_q_vectors(adapter);
4491         if (err) {
4492                 DPRINTK(PROBE, ERR, "Unable to allocate memory for queue "
4493                         "vectors\n");
4494                 goto err_alloc_q_vectors;
4495         }
4496
4497         err = ixgbe_alloc_queues(adapter);
4498         if (err) {
4499                 DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n");
4500                 goto err_alloc_queues;
4501         }
4502
4503         DPRINTK(DRV, INFO, "Multiqueue %s: Rx Queue count = %u, "
4504                 "Tx Queue count = %u\n",
4505                 (adapter->num_rx_queues > 1) ? "Enabled" :
4506                 "Disabled", adapter->num_rx_queues, adapter->num_tx_queues);
4507
4508         set_bit(__IXGBE_DOWN, &adapter->state);
4509
4510         return 0;
4511
4512 err_alloc_queues:
4513         ixgbe_free_q_vectors(adapter);
4514 err_alloc_q_vectors:
4515         ixgbe_reset_interrupt_capability(adapter);
4516 err_set_interrupt:
4517         return err;
4518 }
4519
4520 /**
4521  * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
4522  * @adapter: board private structure to clear interrupt scheme on
4523  *
4524  * We go through and clear interrupt specific resources and reset the structure
4525  * to pre-load conditions
4526  **/
4527 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
4528 {
4529         int i;
4530
4531         for (i = 0; i < adapter->num_tx_queues; i++) {
4532                 kfree(adapter->tx_ring[i]);
4533                 adapter->tx_ring[i] = NULL;
4534         }
4535         for (i = 0; i < adapter->num_rx_queues; i++) {
4536                 kfree(adapter->rx_ring[i]);
4537                 adapter->rx_ring[i] = NULL;
4538         }
4539
4540         ixgbe_free_q_vectors(adapter);
4541         ixgbe_reset_interrupt_capability(adapter);
4542 }
4543
4544 /**
4545  * ixgbe_sfp_timer - worker thread to find a missing module
4546  * @data: pointer to our adapter struct
4547  **/
4548 static void ixgbe_sfp_timer(unsigned long data)
4549 {
4550         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
4551
4552         /*
4553          * Do the sfp_timer outside of interrupt context due to the
4554          * delays that sfp+ detection requires
4555          */
4556         schedule_work(&adapter->sfp_task);
4557 }
4558
4559 /**
4560  * ixgbe_sfp_task - worker thread to find a missing module
4561  * @work: pointer to work_struct containing our data
4562  **/
4563 static void ixgbe_sfp_task(struct work_struct *work)
4564 {
4565         struct ixgbe_adapter *adapter = container_of(work,
4566                                                      struct ixgbe_adapter,
4567                                                      sfp_task);
4568         struct ixgbe_hw *hw = &adapter->hw;
4569
4570         if ((hw->phy.type == ixgbe_phy_nl) &&
4571             (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
4572                 s32 ret = hw->phy.ops.identify_sfp(hw);
4573                 if (ret == IXGBE_ERR_SFP_NOT_PRESENT)
4574                         goto reschedule;
4575                 ret = hw->phy.ops.reset(hw);
4576                 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
4577                         dev_err(&adapter->pdev->dev, "failed to initialize "
4578                                 "because an unsupported SFP+ module type "
4579                                 "was detected.\n"
4580                                 "Reload the driver after installing a "
4581                                 "supported module.\n");
4582                         unregister_netdev(adapter->netdev);
4583                 } else {
4584                         DPRINTK(PROBE, INFO, "detected SFP+: %d\n",
4585                                 hw->phy.sfp_type);
4586                 }
4587                 /* don't need this routine any more */
4588                 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
4589         }
4590         return;
4591 reschedule:
4592         if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
4593                 mod_timer(&adapter->sfp_timer,
4594                           round_jiffies(jiffies + (2 * HZ)));
4595 }
4596
4597 /**
4598  * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4599  * @adapter: board private structure to initialize
4600  *
4601  * ixgbe_sw_init initializes the Adapter private data structure.
4602  * Fields are initialized based on PCI device information and
4603  * OS network device settings (MTU size).
4604  **/
4605 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
4606 {
4607         struct ixgbe_hw *hw = &adapter->hw;
4608         struct pci_dev *pdev = adapter->pdev;
4609         struct net_device *dev = adapter->netdev;
4610         unsigned int rss;
4611 #ifdef CONFIG_IXGBE_DCB
4612         int j;
4613         struct tc_configuration *tc;
4614 #endif
4615
4616         /* PCI config space info */
4617
4618         hw->vendor_id = pdev->vendor;
4619         hw->device_id = pdev->device;
4620         hw->revision_id = pdev->revision;
4621         hw->subsystem_vendor_id = pdev->subsystem_vendor;
4622         hw->subsystem_device_id = pdev->subsystem_device;
4623
4624         /* Set capability flags */
4625         rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
4626         adapter->ring_feature[RING_F_RSS].indices = rss;
4627         adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
4628         adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
4629         if (hw->mac.type == ixgbe_mac_82598EB) {
4630                 if (hw->device_id == IXGBE_DEV_ID_82598AT)
4631                         adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
4632                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
4633         } else if (hw->mac.type == ixgbe_mac_82599EB) {
4634                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
4635                 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
4636                 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
4637                 if (dev->features & NETIF_F_NTUPLE) {
4638                         /* Flow Director perfect filter enabled */
4639                         adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4640                         adapter->atr_sample_rate = 0;
4641                         spin_lock_init(&adapter->fdir_perfect_lock);
4642                 } else {
4643                         /* Flow Director hash filters enabled */
4644                         adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
4645                         adapter->atr_sample_rate = 20;
4646                 }
4647                 adapter->ring_feature[RING_F_FDIR].indices =
4648                                                          IXGBE_MAX_FDIR_INDICES;
4649                 adapter->fdir_pballoc = 0;
4650 #ifdef IXGBE_FCOE
4651                 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
4652                 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
4653                 adapter->ring_feature[RING_F_FCOE].indices = 0;
4654 #ifdef CONFIG_IXGBE_DCB
4655                 /* Default traffic class to use for FCoE */
4656                 adapter->fcoe.tc = IXGBE_FCOE_DEFTC;
4657 #endif
4658 #endif /* IXGBE_FCOE */
4659         }
4660
4661 #ifdef CONFIG_IXGBE_DCB
4662         /* Configure DCB traffic classes */
4663         for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
4664                 tc = &adapter->dcb_cfg.tc_config[j];
4665                 tc->path[DCB_TX_CONFIG].bwg_id = 0;
4666                 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
4667                 tc->path[DCB_RX_CONFIG].bwg_id = 0;
4668                 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
4669                 tc->dcb_pfc = pfc_disabled;
4670         }
4671         adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
4672         adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
4673         adapter->dcb_cfg.rx_pba_cfg = pba_equal;
4674         adapter->dcb_cfg.pfc_mode_enable = false;
4675         adapter->dcb_cfg.round_robin_enable = false;
4676         adapter->dcb_set_bitmap = 0x00;
4677         ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
4678                            adapter->ring_feature[RING_F_DCB].indices);
4679
4680 #endif
4681
4682         /* default flow control settings */
4683         hw->fc.requested_mode = ixgbe_fc_full;
4684         hw->fc.current_mode = ixgbe_fc_full;    /* init for ethtool output */
4685 #ifdef CONFIG_DCB
4686         adapter->last_lfc_mode = hw->fc.current_mode;
4687 #endif
4688         hw->fc.high_water = IXGBE_DEFAULT_FCRTH;
4689         hw->fc.low_water = IXGBE_DEFAULT_FCRTL;
4690         hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
4691         hw->fc.send_xon = true;
4692         hw->fc.disable_fc_autoneg = false;
4693
4694         /* enable itr by default in dynamic mode */
4695         adapter->rx_itr_setting = 1;
4696         adapter->rx_eitr_param = 20000;
4697         adapter->tx_itr_setting = 1;
4698         adapter->tx_eitr_param = 10000;
4699
4700         /* set defaults for eitr in MegaBytes */
4701         adapter->eitr_low = 10;
4702         adapter->eitr_high = 20;
4703
4704         /* set default ring sizes */
4705         adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
4706         adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
4707
4708         /* initialize eeprom parameters */
4709         if (ixgbe_init_eeprom_params_generic(hw)) {
4710                 dev_err(&pdev->dev, "EEPROM initialization failed\n");
4711                 return -EIO;
4712         }
4713
4714         /* enable rx csum by default */
4715         adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
4716
4717         /* get assigned NUMA node */
4718         adapter->node = dev_to_node(&pdev->dev);
4719
4720         set_bit(__IXGBE_DOWN, &adapter->state);
4721
4722         return 0;
4723 }
4724
4725 /**
4726  * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
4727  * @adapter: board private structure
4728  * @tx_ring:    tx descriptor ring (for a specific queue) to setup
4729  *
4730  * Return 0 on success, negative on failure
4731  **/
4732 int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
4733                              struct ixgbe_ring *tx_ring)
4734 {
4735         struct pci_dev *pdev = adapter->pdev;
4736         int size;
4737
4738         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4739         tx_ring->tx_buffer_info = vmalloc_node(size, tx_ring->numa_node);
4740         if (!tx_ring->tx_buffer_info)
4741                 tx_ring->tx_buffer_info = vmalloc(size);
4742         if (!tx_ring->tx_buffer_info)
4743                 goto err;
4744         memset(tx_ring->tx_buffer_info, 0, size);
4745
4746         /* round up to nearest 4K */
4747         tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
4748         tx_ring->size = ALIGN(tx_ring->size, 4096);
4749
4750         tx_ring->desc = dma_alloc_coherent(&pdev->dev, tx_ring->size,
4751                                            &tx_ring->dma, GFP_KERNEL);
4752         if (!tx_ring->desc)
4753                 goto err;
4754
4755         tx_ring->next_to_use = 0;
4756         tx_ring->next_to_clean = 0;
4757         tx_ring->work_limit = tx_ring->count;
4758         return 0;
4759
4760 err:
4761         vfree(tx_ring->tx_buffer_info);
4762         tx_ring->tx_buffer_info = NULL;
4763         DPRINTK(PROBE, ERR, "Unable to allocate memory for the transmit "
4764                             "descriptor ring\n");
4765         return -ENOMEM;
4766 }
4767
4768 /**
4769  * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
4770  * @adapter: board private structure
4771  *
4772  * If this function returns with an error, then it's possible one or
4773  * more of the rings is populated (while the rest are not).  It is the
4774  * callers duty to clean those orphaned rings.
4775  *
4776  * Return 0 on success, negative on failure
4777  **/
4778 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
4779 {
4780         int i, err = 0;
4781
4782         for (i = 0; i < adapter->num_tx_queues; i++) {
4783                 err = ixgbe_setup_tx_resources(adapter, adapter->tx_ring[i]);
4784                 if (!err)
4785                         continue;
4786                 DPRINTK(PROBE, ERR, "Allocation for Tx Queue %u failed\n", i);
4787                 break;
4788         }
4789
4790         return err;
4791 }
4792
4793 /**
4794  * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
4795  * @adapter: board private structure
4796  * @rx_ring:    rx descriptor ring (for a specific queue) to setup
4797  *
4798  * Returns 0 on success, negative on failure
4799  **/
4800 int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
4801                              struct ixgbe_ring *rx_ring)
4802 {
4803         struct pci_dev *pdev = adapter->pdev;
4804         int size;
4805
4806         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4807         rx_ring->rx_buffer_info = vmalloc_node(size, adapter->node);
4808         if (!rx_ring->rx_buffer_info)
4809                 rx_ring->rx_buffer_info = vmalloc(size);
4810         if (!rx_ring->rx_buffer_info) {
4811                 DPRINTK(PROBE, ERR,
4812                         "vmalloc allocation failed for the rx desc ring\n");
4813                 goto alloc_failed;
4814         }
4815         memset(rx_ring->rx_buffer_info, 0, size);
4816
4817         /* Round up to nearest 4K */
4818         rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
4819         rx_ring->size = ALIGN(rx_ring->size, 4096);
4820
4821         rx_ring->desc = dma_alloc_coherent(&pdev->dev, rx_ring->size,
4822                                            &rx_ring->dma, GFP_KERNEL);
4823
4824         if (!rx_ring->desc) {
4825                 DPRINTK(PROBE, ERR,
4826                         "Memory allocation failed for the rx desc ring\n");
4827                 vfree(rx_ring->rx_buffer_info);
4828                 goto alloc_failed;
4829         }
4830
4831         rx_ring->next_to_clean = 0;
4832         rx_ring->next_to_use = 0;
4833
4834         return 0;
4835
4836 alloc_failed:
4837         return -ENOMEM;
4838 }
4839
4840 /**
4841  * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
4842  * @adapter: board private structure
4843  *
4844  * If this function returns with an error, then it's possible one or
4845  * more of the rings is populated (while the rest are not).  It is the
4846  * callers duty to clean those orphaned rings.
4847  *
4848  * Return 0 on success, negative on failure
4849  **/
4850
4851 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
4852 {
4853         int i, err = 0;
4854
4855         for (i = 0; i < adapter->num_rx_queues; i++) {
4856                 err = ixgbe_setup_rx_resources(adapter, adapter->rx_ring[i]);
4857                 if (!err)
4858                         continue;
4859                 DPRINTK(PROBE, ERR, "Allocation for Rx Queue %u failed\n", i);
4860                 break;
4861         }
4862
4863         return err;
4864 }
4865
4866 /**
4867  * ixgbe_free_tx_resources - Free Tx Resources per Queue
4868  * @adapter: board private structure
4869  * @tx_ring: Tx descriptor ring for a specific queue
4870  *
4871  * Free all transmit software resources
4872  **/
4873 void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter,
4874                              struct ixgbe_ring *tx_ring)
4875 {
4876         struct pci_dev *pdev = adapter->pdev;
4877
4878         ixgbe_clean_tx_ring(adapter, tx_ring);
4879
4880         vfree(tx_ring->tx_buffer_info);
4881         tx_ring->tx_buffer_info = NULL;
4882
4883         dma_free_coherent(&pdev->dev, tx_ring->size, tx_ring->desc,
4884                           tx_ring->dma);
4885
4886         tx_ring->desc = NULL;
4887 }
4888
4889 /**
4890  * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
4891  * @adapter: board private structure
4892  *
4893  * Free all transmit software resources
4894  **/
4895 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
4896 {
4897         int i;
4898
4899         for (i = 0; i < adapter->num_tx_queues; i++)
4900                 if (adapter->tx_ring[i]->desc)
4901                         ixgbe_free_tx_resources(adapter, adapter->tx_ring[i]);
4902 }
4903
4904 /**
4905  * ixgbe_free_rx_resources - Free Rx Resources
4906  * @adapter: board private structure
4907  * @rx_ring: ring to clean the resources from
4908  *
4909  * Free all receive software resources
4910  **/
4911 void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
4912                              struct ixgbe_ring *rx_ring)
4913 {
4914         struct pci_dev *pdev = adapter->pdev;
4915
4916         ixgbe_clean_rx_ring(adapter, rx_ring);
4917
4918         vfree(rx_ring->rx_buffer_info);
4919         rx_ring->rx_buffer_info = NULL;
4920
4921         dma_free_coherent(&pdev->dev, rx_ring->size, rx_ring->desc,
4922                           rx_ring->dma);
4923
4924         rx_ring->desc = NULL;
4925 }
4926
4927 /**
4928  * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
4929  * @adapter: board private structure
4930  *
4931  * Free all receive software resources
4932  **/
4933 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
4934 {
4935         int i;
4936
4937         for (i = 0; i < adapter->num_rx_queues; i++)
4938                 if (adapter->rx_ring[i]->desc)
4939                         ixgbe_free_rx_resources(adapter, adapter->rx_ring[i]);
4940 }
4941
4942 /**
4943  * ixgbe_change_mtu - Change the Maximum Transfer Unit
4944  * @netdev: network interface device structure
4945  * @new_mtu: new value for maximum frame size
4946  *
4947  * Returns 0 on success, negative on failure
4948  **/
4949 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
4950 {
4951         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4952         int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
4953
4954         /* MTU < 68 is an error and causes problems on some kernels */
4955         if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
4956                 return -EINVAL;
4957
4958         DPRINTK(PROBE, INFO, "changing MTU from %d to %d\n",
4959                 netdev->mtu, new_mtu);
4960         /* must set new MTU before calling down or up */
4961         netdev->mtu = new_mtu;
4962
4963         if (netif_running(netdev))
4964                 ixgbe_reinit_locked(adapter);
4965
4966         return 0;
4967 }
4968
4969 /**
4970  * ixgbe_open - Called when a network interface is made active
4971  * @netdev: network interface device structure
4972  *
4973  * Returns 0 on success, negative value on failure
4974  *
4975  * The open entry point is called when a network interface is made
4976  * active by the system (IFF_UP).  At this point all resources needed
4977  * for transmit and receive operations are allocated, the interrupt
4978  * handler is registered with the OS, the watchdog timer is started,
4979  * and the stack is notified that the interface is ready.
4980  **/
4981 static int ixgbe_open(struct net_device *netdev)
4982 {
4983         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4984         int err;
4985
4986         /* disallow open during test */
4987         if (test_bit(__IXGBE_TESTING, &adapter->state))
4988                 return -EBUSY;
4989
4990         netif_carrier_off(netdev);
4991
4992         /* allocate transmit descriptors */
4993         err = ixgbe_setup_all_tx_resources(adapter);
4994         if (err)
4995                 goto err_setup_tx;
4996
4997         /* allocate receive descriptors */
4998         err = ixgbe_setup_all_rx_resources(adapter);
4999         if (err)
5000                 goto err_setup_rx;
5001
5002         ixgbe_configure(adapter);
5003
5004         err = ixgbe_request_irq(adapter);
5005         if (err)
5006                 goto err_req_irq;
5007
5008         err = ixgbe_up_complete(adapter);
5009         if (err)
5010                 goto err_up;
5011
5012         netif_tx_start_all_queues(netdev);
5013
5014         return 0;
5015
5016 err_up:
5017         ixgbe_release_hw_control(adapter);
5018         ixgbe_free_irq(adapter);
5019 err_req_irq:
5020 err_setup_rx:
5021         ixgbe_free_all_rx_resources(adapter);
5022 err_setup_tx:
5023         ixgbe_free_all_tx_resources(adapter);
5024         ixgbe_reset(adapter);
5025
5026         return err;
5027 }
5028
5029 /**
5030  * ixgbe_close - Disables a network interface
5031  * @netdev: network interface device structure
5032  *
5033  * Returns 0, this is not allowed to fail
5034  *
5035  * The close entry point is called when an interface is de-activated
5036  * by the OS.  The hardware is still under the drivers control, but
5037  * needs to be disabled.  A global MAC reset is issued to stop the
5038  * hardware, and all transmit and receive resources are freed.
5039  **/
5040 static int ixgbe_close(struct net_device *netdev)
5041 {
5042         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5043
5044         ixgbe_down(adapter);
5045         ixgbe_free_irq(adapter);
5046
5047         ixgbe_free_all_tx_resources(adapter);
5048         ixgbe_free_all_rx_resources(adapter);
5049
5050         ixgbe_release_hw_control(adapter);
5051
5052         return 0;
5053 }
5054
5055 #ifdef CONFIG_PM
5056 static int ixgbe_resume(struct pci_dev *pdev)
5057 {
5058         struct net_device *netdev = pci_get_drvdata(pdev);
5059         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5060         u32 err;
5061
5062         pci_set_power_state(pdev, PCI_D0);
5063         pci_restore_state(pdev);
5064         /*
5065          * pci_restore_state clears dev->state_saved so call
5066          * pci_save_state to restore it.
5067          */
5068         pci_save_state(pdev);
5069
5070         err = pci_enable_device_mem(pdev);
5071         if (err) {
5072                 printk(KERN_ERR "ixgbe: Cannot enable PCI device from "
5073                                 "suspend\n");
5074                 return err;
5075         }
5076         pci_set_master(pdev);
5077
5078         pci_wake_from_d3(pdev, false);
5079
5080         err = ixgbe_init_interrupt_scheme(adapter);
5081         if (err) {
5082                 printk(KERN_ERR "ixgbe: Cannot initialize interrupts for "
5083                                 "device\n");
5084                 return err;
5085         }
5086
5087         ixgbe_reset(adapter);
5088
5089         IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5090
5091         if (netif_running(netdev)) {
5092                 err = ixgbe_open(adapter->netdev);
5093                 if (err)
5094                         return err;
5095         }
5096
5097         netif_device_attach(netdev);
5098
5099         return 0;
5100 }
5101 #endif /* CONFIG_PM */
5102
5103 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
5104 {
5105         struct net_device *netdev = pci_get_drvdata(pdev);
5106         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5107         struct ixgbe_hw *hw = &adapter->hw;
5108         u32 ctrl, fctrl;
5109         u32 wufc = adapter->wol;
5110 #ifdef CONFIG_PM
5111         int retval = 0;
5112 #endif
5113
5114         netif_device_detach(netdev);
5115
5116         if (netif_running(netdev)) {
5117                 ixgbe_down(adapter);
5118                 ixgbe_free_irq(adapter);
5119                 ixgbe_free_all_tx_resources(adapter);
5120                 ixgbe_free_all_rx_resources(adapter);
5121         }
5122         ixgbe_clear_interrupt_scheme(adapter);
5123
5124 #ifdef CONFIG_PM
5125         retval = pci_save_state(pdev);
5126         if (retval)
5127                 return retval;
5128
5129 #endif
5130         if (wufc) {
5131                 ixgbe_set_rx_mode(netdev);
5132
5133                 /* turn on all-multi mode if wake on multicast is enabled */
5134                 if (wufc & IXGBE_WUFC_MC) {
5135                         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5136                         fctrl |= IXGBE_FCTRL_MPE;
5137                         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5138                 }
5139
5140                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5141                 ctrl |= IXGBE_CTRL_GIO_DIS;
5142                 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5143
5144                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5145         } else {
5146                 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5147                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5148         }
5149
5150         if (wufc && hw->mac.type == ixgbe_mac_82599EB)
5151                 pci_wake_from_d3(pdev, true);
5152         else
5153                 pci_wake_from_d3(pdev, false);
5154
5155         *enable_wake = !!wufc;
5156
5157         ixgbe_release_hw_control(adapter);
5158
5159         pci_disable_device(pdev);
5160
5161         return 0;
5162 }
5163
5164 #ifdef CONFIG_PM
5165 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5166 {
5167         int retval;
5168         bool wake;
5169
5170         retval = __ixgbe_shutdown(pdev, &wake);
5171         if (retval)
5172                 return retval;
5173
5174         if (wake) {
5175                 pci_prepare_to_sleep(pdev);
5176         } else {
5177                 pci_wake_from_d3(pdev, false);
5178                 pci_set_power_state(pdev, PCI_D3hot);
5179         }
5180
5181         return 0;
5182 }
5183 #endif /* CONFIG_PM */
5184
5185 static void ixgbe_shutdown(struct pci_dev *pdev)
5186 {
5187         bool wake;
5188
5189         __ixgbe_shutdown(pdev, &wake);
5190
5191         if (system_state == SYSTEM_POWER_OFF) {
5192                 pci_wake_from_d3(pdev, wake);
5193                 pci_set_power_state(pdev, PCI_D3hot);
5194         }
5195 }
5196
5197 /**
5198  * ixgbe_update_stats - Update the board statistics counters.
5199  * @adapter: board private structure
5200  **/
5201 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5202 {
5203         struct net_device *netdev = adapter->netdev;
5204         struct ixgbe_hw *hw = &adapter->hw;
5205         u64 total_mpc = 0;
5206         u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5207         u64 non_eop_descs = 0, restart_queue = 0;
5208
5209         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
5210                 u64 rsc_count = 0;
5211                 u64 rsc_flush = 0;
5212                 for (i = 0; i < 16; i++)
5213                         adapter->hw_rx_no_dma_resources +=
5214                                              IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
5215                 for (i = 0; i < adapter->num_rx_queues; i++) {
5216                         rsc_count += adapter->rx_ring[i]->rsc_count;
5217                         rsc_flush += adapter->rx_ring[i]->rsc_flush;
5218                 }
5219                 adapter->rsc_total_count = rsc_count;
5220                 adapter->rsc_total_flush = rsc_flush;
5221         }
5222
5223         /* gather some stats to the adapter struct that are per queue */
5224         for (i = 0; i < adapter->num_tx_queues; i++)
5225                 restart_queue += adapter->tx_ring[i]->restart_queue;
5226         adapter->restart_queue = restart_queue;
5227
5228         for (i = 0; i < adapter->num_rx_queues; i++)
5229                 non_eop_descs += adapter->rx_ring[i]->non_eop_descs;
5230         adapter->non_eop_descs = non_eop_descs;
5231
5232         adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
5233         for (i = 0; i < 8; i++) {
5234                 /* for packet buffers not used, the register should read 0 */
5235                 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5236                 missed_rx += mpc;
5237                 adapter->stats.mpc[i] += mpc;
5238                 total_mpc += adapter->stats.mpc[i];
5239                 if (hw->mac.type == ixgbe_mac_82598EB)
5240                         adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5241                 adapter->stats.qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5242                 adapter->stats.qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5243                 adapter->stats.qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5244                 adapter->stats.qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
5245                 if (hw->mac.type == ixgbe_mac_82599EB) {
5246                         adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
5247                                                             IXGBE_PXONRXCNT(i));
5248                         adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
5249                                                            IXGBE_PXOFFRXCNT(i));
5250                         adapter->stats.qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
5251                 } else {
5252                         adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
5253                                                               IXGBE_PXONRXC(i));
5254                         adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
5255                                                              IXGBE_PXOFFRXC(i));
5256                 }
5257                 adapter->stats.pxontxc[i] += IXGBE_READ_REG(hw,
5258                                                             IXGBE_PXONTXC(i));
5259                 adapter->stats.pxofftxc[i] += IXGBE_READ_REG(hw,
5260                                                              IXGBE_PXOFFTXC(i));
5261         }
5262         adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
5263         /* work around hardware counting issue */
5264         adapter->stats.gprc -= missed_rx;
5265
5266         /* 82598 hardware only has a 32 bit counter in the high register */
5267         if (hw->mac.type == ixgbe_mac_82599EB) {
5268                 u64 tmp;
5269                 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
5270                 tmp = IXGBE_READ_REG(hw, IXGBE_GORCH) & 0xF; /* 4 high bits of GORC */
5271                 adapter->stats.gorc += (tmp << 32);
5272                 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
5273                 tmp = IXGBE_READ_REG(hw, IXGBE_GOTCH) & 0xF; /* 4 high bits of GOTC */
5274                 adapter->stats.gotc += (tmp << 32);
5275                 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORL);
5276                 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
5277                 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
5278                 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
5279                 adapter->stats.fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5280                 adapter->stats.fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
5281 #ifdef IXGBE_FCOE
5282                 adapter->stats.fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5283                 adapter->stats.fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5284                 adapter->stats.fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5285                 adapter->stats.fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5286                 adapter->stats.fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5287                 adapter->stats.fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
5288 #endif /* IXGBE_FCOE */
5289         } else {
5290                 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
5291                 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
5292                 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5293                 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5294                 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5295         }
5296         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
5297         adapter->stats.bprc += bprc;
5298         adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
5299         if (hw->mac.type == ixgbe_mac_82598EB)
5300                 adapter->stats.mprc -= bprc;
5301         adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5302         adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5303         adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5304         adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5305         adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5306         adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5307         adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5308         adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
5309         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
5310         adapter->stats.lxontxc += lxon;
5311         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
5312         adapter->stats.lxofftxc += lxoff;
5313         adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5314         adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5315         adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
5316         /*
5317          * 82598 errata - tx of flow control packets is included in tx counters
5318          */
5319         xon_off_tot = lxon + lxoff;
5320         adapter->stats.gptc -= xon_off_tot;
5321         adapter->stats.mptc -= xon_off_tot;
5322         adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5323         adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5324         adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5325         adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5326         adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5327         adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5328         adapter->stats.ptc64 -= xon_off_tot;
5329         adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5330         adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5331         adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5332         adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5333         adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5334         adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
5335
5336         /* Fill out the OS statistics structure */
5337         netdev->stats.multicast = adapter->stats.mprc;
5338
5339         /* Rx Errors */
5340         netdev->stats.rx_errors = adapter->stats.crcerrs +
5341                                        adapter->stats.rlec;
5342         netdev->stats.rx_dropped = 0;
5343         netdev->stats.rx_length_errors = adapter->stats.rlec;
5344         netdev->stats.rx_crc_errors = adapter->stats.crcerrs;
5345         netdev->stats.rx_missed_errors = total_mpc;
5346 }
5347
5348 /**
5349  * ixgbe_watchdog - Timer Call-back
5350  * @data: pointer to adapter cast into an unsigned long
5351  **/
5352 static void ixgbe_watchdog(unsigned long data)
5353 {
5354         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
5355         struct ixgbe_hw *hw = &adapter->hw;
5356         u64 eics = 0;
5357         int i;
5358
5359         /*
5360          *  Do the watchdog outside of interrupt context due to the lovely
5361          * delays that some of the newer hardware requires
5362          */
5363
5364         if (test_bit(__IXGBE_DOWN, &adapter->state))
5365                 goto watchdog_short_circuit;
5366
5367         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5368                 /*
5369                  * for legacy and MSI interrupts don't set any bits
5370                  * that are enabled for EIAM, because this operation
5371                  * would set *both* EIMS and EICS for any bit in EIAM
5372                  */
5373                 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5374                         (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
5375                 goto watchdog_reschedule;
5376         }
5377
5378         /* get one bit for every active tx/rx interrupt vector */
5379         for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
5380                 struct ixgbe_q_vector *qv = adapter->q_vector[i];
5381                 if (qv->rxr_count || qv->txr_count)
5382                         eics |= ((u64)1 << i);
5383         }
5384
5385         /* Cause software interrupt to ensure rx rings are cleaned */
5386         ixgbe_irq_rearm_queues(adapter, eics);
5387
5388 watchdog_reschedule:
5389         /* Reset the timer */
5390         mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ));
5391
5392 watchdog_short_circuit:
5393         schedule_work(&adapter->watchdog_task);
5394 }
5395
5396 /**
5397  * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
5398  * @work: pointer to work_struct containing our data
5399  **/
5400 static void ixgbe_multispeed_fiber_task(struct work_struct *work)
5401 {
5402         struct ixgbe_adapter *adapter = container_of(work,
5403                                                      struct ixgbe_adapter,
5404                                                      multispeed_fiber_task);
5405         struct ixgbe_hw *hw = &adapter->hw;
5406         u32 autoneg;
5407         bool negotiation;
5408
5409         adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
5410         autoneg = hw->phy.autoneg_advertised;
5411         if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
5412                 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
5413         hw->mac.autotry_restart = false;
5414         if (hw->mac.ops.setup_link)
5415                 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
5416         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5417         adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
5418 }
5419
5420 /**
5421  * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
5422  * @work: pointer to work_struct containing our data
5423  **/
5424 static void ixgbe_sfp_config_module_task(struct work_struct *work)
5425 {
5426         struct ixgbe_adapter *adapter = container_of(work,
5427                                                      struct ixgbe_adapter,
5428                                                      sfp_config_module_task);
5429         struct ixgbe_hw *hw = &adapter->hw;
5430         u32 err;
5431
5432         adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
5433
5434         /* Time for electrical oscillations to settle down */
5435         msleep(100);
5436         err = hw->phy.ops.identify_sfp(hw);
5437
5438         if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
5439                 dev_err(&adapter->pdev->dev, "failed to initialize because "
5440                         "an unsupported SFP+ module type was detected.\n"
5441                         "Reload the driver after installing a supported "
5442                         "module.\n");
5443                 unregister_netdev(adapter->netdev);
5444                 return;
5445         }
5446         hw->mac.ops.setup_sfp(hw);
5447
5448         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
5449                 /* This will also work for DA Twinax connections */
5450                 schedule_work(&adapter->multispeed_fiber_task);
5451         adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
5452 }
5453
5454 /**
5455  * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table
5456  * @work: pointer to work_struct containing our data
5457  **/
5458 static void ixgbe_fdir_reinit_task(struct work_struct *work)
5459 {
5460         struct ixgbe_adapter *adapter = container_of(work,
5461                                                      struct ixgbe_adapter,
5462                                                      fdir_reinit_task);
5463         struct ixgbe_hw *hw = &adapter->hw;
5464         int i;
5465
5466         if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5467                 for (i = 0; i < adapter->num_tx_queues; i++)
5468                         set_bit(__IXGBE_FDIR_INIT_DONE,
5469                                 &(adapter->tx_ring[i]->reinit_state));
5470         } else {
5471                 DPRINTK(PROBE, ERR, "failed to finish FDIR re-initialization, "
5472                         "ignored adding FDIR ATR filters\n");
5473         }
5474         /* Done FDIR Re-initialization, enable transmits */
5475         netif_tx_start_all_queues(adapter->netdev);
5476 }
5477
5478 static DEFINE_MUTEX(ixgbe_watchdog_lock);
5479
5480 /**
5481  * ixgbe_watchdog_task - worker thread to bring link up
5482  * @work: pointer to work_struct containing our data
5483  **/
5484 static void ixgbe_watchdog_task(struct work_struct *work)
5485 {
5486         struct ixgbe_adapter *adapter = container_of(work,
5487                                                      struct ixgbe_adapter,
5488                                                      watchdog_task);
5489         struct net_device *netdev = adapter->netdev;
5490         struct ixgbe_hw *hw = &adapter->hw;
5491         u32 link_speed;
5492         bool link_up;
5493         int i;
5494         struct ixgbe_ring *tx_ring;
5495         int some_tx_pending = 0;
5496
5497         mutex_lock(&ixgbe_watchdog_lock);
5498
5499         link_up = adapter->link_up;
5500         link_speed = adapter->link_speed;
5501
5502         if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
5503                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
5504                 if (link_up) {
5505 #ifdef CONFIG_DCB
5506                         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5507                                 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
5508                                         hw->mac.ops.fc_enable(hw, i);
5509                         } else {
5510                                 hw->mac.ops.fc_enable(hw, 0);
5511                         }
5512 #else
5513                         hw->mac.ops.fc_enable(hw, 0);
5514 #endif
5515                 }
5516
5517                 if (link_up ||
5518                     time_after(jiffies, (adapter->link_check_timeout +
5519                                          IXGBE_TRY_LINK_TIMEOUT))) {
5520                         adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5521                         IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
5522                 }
5523                 adapter->link_up = link_up;
5524                 adapter->link_speed = link_speed;
5525         }
5526
5527         if (link_up) {
5528                 if (!netif_carrier_ok(netdev)) {
5529                         bool flow_rx, flow_tx;
5530
5531                         if (hw->mac.type == ixgbe_mac_82599EB) {
5532                                 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5533                                 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
5534                                 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5535                                 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
5536                         } else {
5537                                 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5538                                 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
5539                                 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5540                                 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
5541                         }
5542
5543                         printk(KERN_INFO "ixgbe: %s NIC Link is Up %s, "
5544                                "Flow Control: %s\n",
5545                                netdev->name,
5546                                (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
5547                                 "10 Gbps" :
5548                                 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5549                                  "1 Gbps" : "unknown speed")),
5550                                ((flow_rx && flow_tx) ? "RX/TX" :
5551                                 (flow_rx ? "RX" :
5552                                 (flow_tx ? "TX" : "None"))));
5553
5554                         netif_carrier_on(netdev);
5555                 } else {
5556                         /* Force detection of hung controller */
5557                         adapter->detect_tx_hung = true;
5558                 }
5559         } else {
5560                 adapter->link_up = false;
5561                 adapter->link_speed = 0;
5562                 if (netif_carrier_ok(netdev)) {
5563                         printk(KERN_INFO "ixgbe: %s NIC Link is Down\n",
5564                                netdev->name);
5565                         netif_carrier_off(netdev);
5566                 }
5567         }
5568
5569         if (!netif_carrier_ok(netdev)) {
5570                 for (i = 0; i < adapter->num_tx_queues; i++) {
5571                         tx_ring = adapter->tx_ring[i];
5572                         if (tx_ring->next_to_use != tx_ring->next_to_clean) {
5573                                 some_tx_pending = 1;
5574                                 break;
5575                         }
5576                 }
5577
5578                 if (some_tx_pending) {
5579                         /* We've lost link, so the controller stops DMA,
5580                          * but we've got queued Tx work that's never going
5581                          * to get done, so reset controller to flush Tx.
5582                          * (Do the reset outside of interrupt context).
5583                          */
5584                          schedule_work(&adapter->reset_task);
5585                 }
5586         }
5587
5588         ixgbe_update_stats(adapter);
5589         mutex_unlock(&ixgbe_watchdog_lock);
5590 }
5591
5592 static int ixgbe_tso(struct ixgbe_adapter *adapter,
5593                      struct ixgbe_ring *tx_ring, struct sk_buff *skb,
5594                      u32 tx_flags, u8 *hdr_len)
5595 {
5596         struct ixgbe_adv_tx_context_desc *context_desc;
5597         unsigned int i;
5598         int err;
5599         struct ixgbe_tx_buffer *tx_buffer_info;
5600         u32 vlan_macip_lens = 0, type_tucmd_mlhl;
5601         u32 mss_l4len_idx, l4len;
5602
5603         if (skb_is_gso(skb)) {
5604                 if (skb_header_cloned(skb)) {
5605                         err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
5606                         if (err)
5607                                 return err;
5608                 }
5609                 l4len = tcp_hdrlen(skb);
5610                 *hdr_len += l4len;
5611
5612                 if (skb->protocol == htons(ETH_P_IP)) {
5613                         struct iphdr *iph = ip_hdr(skb);
5614                         iph->tot_len = 0;
5615                         iph->check = 0;
5616                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5617                                                                  iph->daddr, 0,
5618                                                                  IPPROTO_TCP,
5619                                                                  0);
5620                 } else if (skb_is_gso_v6(skb)) {
5621                         ipv6_hdr(skb)->payload_len = 0;
5622                         tcp_hdr(skb)->check =
5623                             ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
5624                                              &ipv6_hdr(skb)->daddr,
5625                                              0, IPPROTO_TCP, 0);
5626                 }
5627
5628                 i = tx_ring->next_to_use;
5629
5630                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5631                 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
5632
5633                 /* VLAN MACLEN IPLEN */
5634                 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5635                         vlan_macip_lens |=
5636                             (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
5637                 vlan_macip_lens |= ((skb_network_offset(skb)) <<
5638                                     IXGBE_ADVTXD_MACLEN_SHIFT);
5639                 *hdr_len += skb_network_offset(skb);
5640                 vlan_macip_lens |=
5641                     (skb_transport_header(skb) - skb_network_header(skb));
5642                 *hdr_len +=
5643                     (skb_transport_header(skb) - skb_network_header(skb));
5644                 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
5645                 context_desc->seqnum_seed = 0;
5646
5647                 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
5648                 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
5649                                    IXGBE_ADVTXD_DTYP_CTXT);
5650
5651                 if (skb->protocol == htons(ETH_P_IP))
5652                         type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
5653                 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
5654                 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
5655
5656                 /* MSS L4LEN IDX */
5657                 mss_l4len_idx =
5658                     (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
5659                 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
5660                 /* use index 1 for TSO */
5661                 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
5662                 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
5663
5664                 tx_buffer_info->time_stamp = jiffies;
5665                 tx_buffer_info->next_to_watch = i;
5666
5667                 i++;
5668                 if (i == tx_ring->count)
5669                         i = 0;
5670                 tx_ring->next_to_use = i;
5671
5672                 return true;
5673         }
5674         return false;
5675 }
5676
5677 static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
5678                           struct ixgbe_ring *tx_ring,
5679                           struct sk_buff *skb, u32 tx_flags)
5680 {
5681         struct ixgbe_adv_tx_context_desc *context_desc;
5682         unsigned int i;
5683         struct ixgbe_tx_buffer *tx_buffer_info;
5684         u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
5685
5686         if (skb->ip_summed == CHECKSUM_PARTIAL ||
5687             (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
5688                 i = tx_ring->next_to_use;
5689                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5690                 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
5691
5692                 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5693                         vlan_macip_lens |=
5694                             (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
5695                 vlan_macip_lens |= (skb_network_offset(skb) <<
5696                                     IXGBE_ADVTXD_MACLEN_SHIFT);
5697                 if (skb->ip_summed == CHECKSUM_PARTIAL)
5698                         vlan_macip_lens |= (skb_transport_header(skb) -
5699                                             skb_network_header(skb));
5700
5701                 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
5702                 context_desc->seqnum_seed = 0;
5703
5704                 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
5705                                     IXGBE_ADVTXD_DTYP_CTXT);
5706
5707                 if (skb->ip_summed == CHECKSUM_PARTIAL) {
5708                         __be16 protocol;
5709
5710                         if (skb->protocol == cpu_to_be16(ETH_P_8021Q)) {
5711                                 const struct vlan_ethhdr *vhdr =
5712                                         (const struct vlan_ethhdr *)skb->data;
5713
5714                                 protocol = vhdr->h_vlan_encapsulated_proto;
5715                         } else {
5716                                 protocol = skb->protocol;
5717                         }
5718
5719                         switch (protocol) {
5720                         case cpu_to_be16(ETH_P_IP):
5721                                 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
5722                                 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
5723                                         type_tucmd_mlhl |=
5724                                                 IXGBE_ADVTXD_TUCMD_L4T_TCP;
5725                                 else if (ip_hdr(skb)->protocol == IPPROTO_SCTP)
5726                                         type_tucmd_mlhl |=
5727                                                 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
5728                                 break;
5729                         case cpu_to_be16(ETH_P_IPV6):
5730                                 /* XXX what about other V6 headers?? */
5731                                 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
5732                                         type_tucmd_mlhl |=
5733                                                 IXGBE_ADVTXD_TUCMD_L4T_TCP;
5734                                 else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP)
5735                                         type_tucmd_mlhl |=
5736                                                 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
5737                                 break;
5738                         default:
5739                                 if (unlikely(net_ratelimit())) {
5740                                         DPRINTK(PROBE, WARNING,
5741                                          "partial checksum but proto=%x!\n",
5742                                          skb->protocol);
5743                                 }
5744                                 break;
5745                         }
5746                 }
5747
5748                 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
5749                 /* use index zero for tx checksum offload */
5750                 context_desc->mss_l4len_idx = 0;
5751
5752                 tx_buffer_info->time_stamp = jiffies;
5753                 tx_buffer_info->next_to_watch = i;
5754
5755                 i++;
5756                 if (i == tx_ring->count)
5757                         i = 0;
5758                 tx_ring->next_to_use = i;
5759
5760                 return true;
5761         }
5762
5763         return false;
5764 }
5765
5766 static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
5767                         struct ixgbe_ring *tx_ring,
5768                         struct sk_buff *skb, u32 tx_flags,
5769                         unsigned int first)
5770 {
5771         struct pci_dev *pdev = adapter->pdev;
5772         struct ixgbe_tx_buffer *tx_buffer_info;
5773         unsigned int len;
5774         unsigned int total = skb->len;
5775         unsigned int offset = 0, size, count = 0, i;
5776         unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
5777         unsigned int f;
5778
5779         i = tx_ring->next_to_use;
5780
5781         if (tx_flags & IXGBE_TX_FLAGS_FCOE)
5782                 /* excluding fcoe_crc_eof for FCoE */
5783                 total -= sizeof(struct fcoe_crc_eof);
5784
5785         len = min(skb_headlen(skb), total);
5786         while (len) {
5787                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5788                 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
5789
5790                 tx_buffer_info->length = size;
5791                 tx_buffer_info->mapped_as_page = false;
5792                 tx_buffer_info->dma = dma_map_single(&pdev->dev,
5793                                                      skb->data + offset,
5794                                                      size, DMA_TO_DEVICE);
5795                 if (dma_mapping_error(&pdev->dev, tx_buffer_info->dma))
5796                         goto dma_error;
5797                 tx_buffer_info->time_stamp = jiffies;
5798                 tx_buffer_info->next_to_watch = i;
5799
5800                 len -= size;
5801                 total -= size;
5802                 offset += size;
5803                 count++;
5804
5805                 if (len) {
5806                         i++;
5807                         if (i == tx_ring->count)
5808                                 i = 0;
5809                 }
5810         }
5811
5812         for (f = 0; f < nr_frags; f++) {
5813                 struct skb_frag_struct *frag;
5814
5815                 frag = &skb_shinfo(skb)->frags[f];
5816                 len = min((unsigned int)frag->size, total);
5817                 offset = frag->page_offset;
5818
5819                 while (len) {
5820                         i++;
5821                         if (i == tx_ring->count)
5822                                 i = 0;
5823
5824                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
5825                         size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
5826
5827                         tx_buffer_info->length = size;
5828                         tx_buffer_info->dma = dma_map_page(&adapter->pdev->dev,
5829                                                            frag->page,
5830                                                            offset, size,
5831                                                            DMA_TO_DEVICE);
5832                         tx_buffer_info->mapped_as_page = true;
5833                         if (dma_mapping_error(&pdev->dev, tx_buffer_info->dma))
5834                                 goto dma_error;
5835                         tx_buffer_info->time_stamp = jiffies;
5836                         tx_buffer_info->next_to_watch = i;
5837
5838                         len -= size;
5839                         total -= size;
5840                         offset += size;
5841                         count++;
5842                 }
5843                 if (total == 0)
5844                         break;
5845         }
5846
5847         tx_ring->tx_buffer_info[i].skb = skb;
5848         tx_ring->tx_buffer_info[first].next_to_watch = i;
5849
5850         return count;
5851
5852 dma_error:
5853         dev_err(&pdev->dev, "TX DMA map failed\n");
5854
5855         /* clear timestamp and dma mappings for failed tx_buffer_info map */
5856         tx_buffer_info->dma = 0;
5857         tx_buffer_info->time_stamp = 0;
5858         tx_buffer_info->next_to_watch = 0;
5859         if (count)
5860                 count--;
5861
5862         /* clear timestamp and dma mappings for remaining portion of packet */
5863         while (count--) {
5864                 if (i==0)
5865                         i += tx_ring->count;
5866                 i--;
5867                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5868                 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
5869         }
5870
5871         return 0;
5872 }
5873
5874 static void ixgbe_tx_queue(struct ixgbe_adapter *adapter,
5875                            struct ixgbe_ring *tx_ring,
5876                            int tx_flags, int count, u32 paylen, u8 hdr_len)
5877 {
5878         union ixgbe_adv_tx_desc *tx_desc = NULL;
5879         struct ixgbe_tx_buffer *tx_buffer_info;
5880         u32 olinfo_status = 0, cmd_type_len = 0;
5881         unsigned int i;
5882         u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
5883
5884         cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
5885
5886         cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
5887
5888         if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5889                 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
5890
5891         if (tx_flags & IXGBE_TX_FLAGS_TSO) {
5892                 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
5893
5894                 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
5895                                  IXGBE_ADVTXD_POPTS_SHIFT;
5896
5897                 /* use index 1 context for tso */
5898                 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
5899                 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
5900                         olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
5901                                          IXGBE_ADVTXD_POPTS_SHIFT;
5902
5903         } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
5904                 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
5905                                  IXGBE_ADVTXD_POPTS_SHIFT;
5906
5907         if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
5908                 olinfo_status |= IXGBE_ADVTXD_CC;
5909                 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
5910                 if (tx_flags & IXGBE_TX_FLAGS_FSO)
5911                         cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
5912         }
5913
5914         olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
5915
5916         i = tx_ring->next_to_use;
5917         while (count--) {
5918                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5919                 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
5920                 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
5921                 tx_desc->read.cmd_type_len =
5922                         cpu_to_le32(cmd_type_len | tx_buffer_info->length);
5923                 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
5924                 i++;
5925                 if (i == tx_ring->count)
5926                         i = 0;
5927         }
5928
5929         tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
5930
5931         /*
5932          * Force memory writes to complete before letting h/w
5933          * know there are new descriptors to fetch.  (Only
5934          * applicable for weak-ordered memory model archs,
5935          * such as IA-64).
5936          */
5937         wmb();
5938
5939         tx_ring->next_to_use = i;
5940         writel(i, adapter->hw.hw_addr + tx_ring->tail);
5941 }
5942
5943 static void ixgbe_atr(struct ixgbe_adapter *adapter, struct sk_buff *skb,
5944                       int queue, u32 tx_flags)
5945 {
5946         /* Right now, we support IPv4 only */
5947         struct ixgbe_atr_input atr_input;
5948         struct tcphdr *th;
5949         struct iphdr *iph = ip_hdr(skb);
5950         struct ethhdr *eth = (struct ethhdr *)skb->data;
5951         u16 vlan_id, src_port, dst_port, flex_bytes;
5952         u32 src_ipv4_addr, dst_ipv4_addr;
5953         u8 l4type = 0;
5954
5955         /* check if we're UDP or TCP */
5956         if (iph->protocol == IPPROTO_TCP) {
5957                 th = tcp_hdr(skb);
5958                 src_port = th->source;
5959                 dst_port = th->dest;
5960                 l4type |= IXGBE_ATR_L4TYPE_TCP;
5961                 /* l4type IPv4 type is 0, no need to assign */
5962         } else {
5963                 /* Unsupported L4 header, just bail here */
5964                 return;
5965         }
5966
5967         memset(&atr_input, 0, sizeof(struct ixgbe_atr_input));
5968
5969         vlan_id = (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK) >>
5970                    IXGBE_TX_FLAGS_VLAN_SHIFT;
5971         src_ipv4_addr = iph->saddr;
5972         dst_ipv4_addr = iph->daddr;
5973         flex_bytes = eth->h_proto;
5974
5975         ixgbe_atr_set_vlan_id_82599(&atr_input, vlan_id);
5976         ixgbe_atr_set_src_port_82599(&atr_input, dst_port);
5977         ixgbe_atr_set_dst_port_82599(&atr_input, src_port);
5978         ixgbe_atr_set_flex_byte_82599(&atr_input, flex_bytes);
5979         ixgbe_atr_set_l4type_82599(&atr_input, l4type);
5980         /* src and dst are inverted, think how the receiver sees them */
5981         ixgbe_atr_set_src_ipv4_82599(&atr_input, dst_ipv4_addr);
5982         ixgbe_atr_set_dst_ipv4_82599(&atr_input, src_ipv4_addr);
5983
5984         /* This assumes the Rx queue and Tx queue are bound to the same CPU */
5985         ixgbe_fdir_add_signature_filter_82599(&adapter->hw, &atr_input, queue);
5986 }
5987
5988 static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
5989                                  struct ixgbe_ring *tx_ring, int size)
5990 {
5991         netif_stop_subqueue(netdev, tx_ring->queue_index);
5992         /* Herbert's original patch had:
5993          *  smp_mb__after_netif_stop_queue();
5994          * but since that doesn't exist yet, just open code it. */
5995         smp_mb();
5996
5997         /* We need to check again in a case another CPU has just
5998          * made room available. */
5999         if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
6000                 return -EBUSY;
6001
6002         /* A reprieve! - use start_queue because it doesn't call schedule */
6003         netif_start_subqueue(netdev, tx_ring->queue_index);
6004         ++tx_ring->restart_queue;
6005         return 0;
6006 }
6007
6008 static int ixgbe_maybe_stop_tx(struct net_device *netdev,
6009                               struct ixgbe_ring *tx_ring, int size)
6010 {
6011         if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
6012                 return 0;
6013         return __ixgbe_maybe_stop_tx(netdev, tx_ring, size);
6014 }
6015
6016 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6017 {
6018         struct ixgbe_adapter *adapter = netdev_priv(dev);
6019         int txq = smp_processor_id();
6020
6021         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6022                 while (unlikely(txq >= dev->real_num_tx_queues))
6023                         txq -= dev->real_num_tx_queues;
6024                 return txq;
6025         }
6026
6027 #ifdef IXGBE_FCOE
6028         if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
6029             ((skb->protocol == htons(ETH_P_FCOE)) ||
6030              (skb->protocol == htons(ETH_P_FIP)))) {
6031                 txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
6032                 txq += adapter->ring_feature[RING_F_FCOE].mask;
6033                 return txq;
6034         }
6035 #endif
6036         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6037                 if (skb->priority == TC_PRIO_CONTROL)
6038                         txq = adapter->ring_feature[RING_F_DCB].indices-1;
6039                 else
6040                         txq = (skb->vlan_tci & IXGBE_TX_FLAGS_VLAN_PRIO_MASK)
6041                                >> 13;
6042                 return txq;
6043         }
6044
6045         return skb_tx_hash(dev, skb);
6046 }
6047
6048 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
6049                                     struct net_device *netdev)
6050 {
6051         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6052         struct ixgbe_ring *tx_ring;
6053         struct netdev_queue *txq;
6054         unsigned int first;
6055         unsigned int tx_flags = 0;
6056         u8 hdr_len = 0;
6057         int tso;
6058         int count = 0;
6059         unsigned int f;
6060
6061         if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
6062                 tx_flags |= vlan_tx_tag_get(skb);
6063                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6064                         tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
6065                         tx_flags |= ((skb->queue_mapping & 0x7) << 13);
6066                 }
6067                 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6068                 tx_flags |= IXGBE_TX_FLAGS_VLAN;
6069         } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6070                 tx_flags |= ((skb->queue_mapping & 0x7) << 13);
6071                 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6072                 tx_flags |= IXGBE_TX_FLAGS_VLAN;
6073         }
6074
6075         tx_ring = adapter->tx_ring[skb->queue_mapping];
6076
6077 #ifdef IXGBE_FCOE
6078         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
6079 #ifdef CONFIG_IXGBE_DCB
6080                 /* for FCoE with DCB, we force the priority to what
6081                  * was specified by the switch */
6082                 if ((skb->protocol == htons(ETH_P_FCOE)) ||
6083                     (skb->protocol == htons(ETH_P_FIP))) {
6084                         tx_flags &= ~(IXGBE_TX_FLAGS_VLAN_PRIO_MASK
6085                                       << IXGBE_TX_FLAGS_VLAN_SHIFT);
6086                         tx_flags |= ((adapter->fcoe.up << 13)
6087                                      << IXGBE_TX_FLAGS_VLAN_SHIFT);
6088                 }
6089 #endif
6090                 /* flag for FCoE offloads */
6091                 if (skb->protocol == htons(ETH_P_FCOE))
6092                         tx_flags |= IXGBE_TX_FLAGS_FCOE;
6093         }
6094 #endif
6095
6096         /* four things can cause us to need a context descriptor */
6097         if (skb_is_gso(skb) ||
6098             (skb->ip_summed == CHECKSUM_PARTIAL) ||
6099             (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
6100             (tx_flags & IXGBE_TX_FLAGS_FCOE))
6101                 count++;
6102
6103         count += TXD_USE_COUNT(skb_headlen(skb));
6104         for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6105                 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6106
6107         if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) {
6108                 adapter->tx_busy++;
6109                 return NETDEV_TX_BUSY;
6110         }
6111
6112         first = tx_ring->next_to_use;
6113         if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6114 #ifdef IXGBE_FCOE
6115                 /* setup tx offload for FCoE */
6116                 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
6117                 if (tso < 0) {
6118                         dev_kfree_skb_any(skb);
6119                         return NETDEV_TX_OK;
6120                 }
6121                 if (tso)
6122                         tx_flags |= IXGBE_TX_FLAGS_FSO;
6123 #endif /* IXGBE_FCOE */
6124         } else {
6125                 if (skb->protocol == htons(ETH_P_IP))
6126                         tx_flags |= IXGBE_TX_FLAGS_IPV4;
6127                 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len);
6128                 if (tso < 0) {
6129                         dev_kfree_skb_any(skb);
6130                         return NETDEV_TX_OK;
6131                 }
6132
6133                 if (tso)
6134                         tx_flags |= IXGBE_TX_FLAGS_TSO;
6135                 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) &&
6136                          (skb->ip_summed == CHECKSUM_PARTIAL))
6137                         tx_flags |= IXGBE_TX_FLAGS_CSUM;
6138         }
6139
6140         count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first);
6141         if (count) {
6142                 /* add the ATR filter if ATR is on */
6143                 if (tx_ring->atr_sample_rate) {
6144                         ++tx_ring->atr_count;
6145                         if ((tx_ring->atr_count >= tx_ring->atr_sample_rate) &&
6146                              test_bit(__IXGBE_FDIR_INIT_DONE,
6147                                       &tx_ring->reinit_state)) {
6148                                 ixgbe_atr(adapter, skb, tx_ring->queue_index,
6149                                           tx_flags);
6150                                 tx_ring->atr_count = 0;
6151                         }
6152                 }
6153                 txq = netdev_get_tx_queue(netdev, tx_ring->queue_index);
6154                 txq->tx_bytes += skb->len;
6155                 txq->tx_packets++;
6156                 ixgbe_tx_queue(adapter, tx_ring, tx_flags, count, skb->len,
6157                                hdr_len);
6158                 ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
6159
6160         } else {
6161                 dev_kfree_skb_any(skb);
6162                 tx_ring->tx_buffer_info[first].time_stamp = 0;
6163                 tx_ring->next_to_use = first;
6164         }
6165
6166         return NETDEV_TX_OK;
6167 }
6168
6169 /**
6170  * ixgbe_set_mac - Change the Ethernet Address of the NIC
6171  * @netdev: network interface device structure
6172  * @p: pointer to an address structure
6173  *
6174  * Returns 0 on success, negative on failure
6175  **/
6176 static int ixgbe_set_mac(struct net_device *netdev, void *p)
6177 {
6178         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6179         struct ixgbe_hw *hw = &adapter->hw;
6180         struct sockaddr *addr = p;
6181
6182         if (!is_valid_ether_addr(addr->sa_data))
6183                 return -EADDRNOTAVAIL;
6184
6185         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
6186         memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
6187
6188         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
6189                             IXGBE_RAH_AV);
6190
6191         return 0;
6192 }
6193
6194 static int
6195 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6196 {
6197         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6198         struct ixgbe_hw *hw = &adapter->hw;
6199         u16 value;
6200         int rc;
6201
6202         if (prtad != hw->phy.mdio.prtad)
6203                 return -EINVAL;
6204         rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6205         if (!rc)
6206                 rc = value;
6207         return rc;
6208 }
6209
6210 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6211                             u16 addr, u16 value)
6212 {
6213         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6214         struct ixgbe_hw *hw = &adapter->hw;
6215
6216         if (prtad != hw->phy.mdio.prtad)
6217                 return -EINVAL;
6218         return hw->phy.ops.write_reg(hw, addr, devad, value);
6219 }
6220
6221 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6222 {
6223         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6224
6225         return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6226 }
6227
6228 /**
6229  * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
6230  * netdev->dev_addrs
6231  * @netdev: network interface device structure
6232  *
6233  * Returns non-zero on failure
6234  **/
6235 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6236 {
6237         int err = 0;
6238         struct ixgbe_adapter *adapter = netdev_priv(dev);
6239         struct ixgbe_mac_info *mac = &adapter->hw.mac;
6240
6241         if (is_valid_ether_addr(mac->san_addr)) {
6242                 rtnl_lock();
6243                 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6244                 rtnl_unlock();
6245         }
6246         return err;
6247 }
6248
6249 /**
6250  * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
6251  * netdev->dev_addrs
6252  * @netdev: network interface device structure
6253  *
6254  * Returns non-zero on failure
6255  **/
6256 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6257 {
6258         int err = 0;
6259         struct ixgbe_adapter *adapter = netdev_priv(dev);
6260         struct ixgbe_mac_info *mac = &adapter->hw.mac;
6261
6262         if (is_valid_ether_addr(mac->san_addr)) {
6263                 rtnl_lock();
6264                 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6265                 rtnl_unlock();
6266         }
6267         return err;
6268 }
6269
6270 #ifdef CONFIG_NET_POLL_CONTROLLER
6271 /*
6272  * Polling 'interrupt' - used by things like netconsole to send skbs
6273  * without having to re-enable interrupts. It's not called while
6274  * the interrupt routine is executing.
6275  */
6276 static void ixgbe_netpoll(struct net_device *netdev)
6277 {
6278         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6279         int i;
6280
6281         /* if interface is down do nothing */
6282         if (test_bit(__IXGBE_DOWN, &adapter->state))
6283                 return;
6284
6285         adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
6286         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
6287                 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
6288                 for (i = 0; i < num_q_vectors; i++) {
6289                         struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
6290                         ixgbe_msix_clean_many(0, q_vector);
6291                 }
6292         } else {
6293                 ixgbe_intr(adapter->pdev->irq, netdev);
6294         }
6295         adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
6296 }
6297 #endif
6298
6299 static const struct net_device_ops ixgbe_netdev_ops = {
6300         .ndo_open               = ixgbe_open,
6301         .ndo_stop               = ixgbe_close,
6302         .ndo_start_xmit         = ixgbe_xmit_frame,
6303         .ndo_select_queue       = ixgbe_select_queue,
6304         .ndo_set_rx_mode        = ixgbe_set_rx_mode,
6305         .ndo_set_multicast_list = ixgbe_set_rx_mode,
6306         .ndo_validate_addr      = eth_validate_addr,
6307         .ndo_set_mac_address    = ixgbe_set_mac,
6308         .ndo_change_mtu         = ixgbe_change_mtu,
6309         .ndo_tx_timeout         = ixgbe_tx_timeout,
6310         .ndo_vlan_rx_register   = ixgbe_vlan_rx_register,
6311         .ndo_vlan_rx_add_vid    = ixgbe_vlan_rx_add_vid,
6312         .ndo_vlan_rx_kill_vid   = ixgbe_vlan_rx_kill_vid,
6313         .ndo_do_ioctl           = ixgbe_ioctl,
6314         .ndo_set_vf_mac         = ixgbe_ndo_set_vf_mac,
6315         .ndo_set_vf_vlan        = ixgbe_ndo_set_vf_vlan,
6316         .ndo_set_vf_tx_rate     = ixgbe_ndo_set_vf_bw,
6317         .ndo_get_vf_config      = ixgbe_ndo_get_vf_config,
6318 #ifdef CONFIG_NET_POLL_CONTROLLER
6319         .ndo_poll_controller    = ixgbe_netpoll,
6320 #endif
6321 #ifdef IXGBE_FCOE
6322         .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
6323         .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
6324         .ndo_fcoe_enable = ixgbe_fcoe_enable,
6325         .ndo_fcoe_disable = ixgbe_fcoe_disable,
6326         .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
6327 #endif /* IXGBE_FCOE */
6328 };
6329
6330 static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
6331                            const struct ixgbe_info *ii)
6332 {
6333 #ifdef CONFIG_PCI_IOV
6334         struct ixgbe_hw *hw = &adapter->hw;
6335         int err;
6336
6337         if (hw->mac.type != ixgbe_mac_82599EB || !max_vfs)
6338                 return;
6339
6340         /* The 82599 supports up to 64 VFs per physical function
6341          * but this implementation limits allocation to 63 so that
6342          * basic networking resources are still available to the
6343          * physical function
6344          */
6345         adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
6346         adapter->flags |= IXGBE_FLAG_SRIOV_ENABLED;
6347         err = pci_enable_sriov(adapter->pdev, adapter->num_vfs);
6348         if (err) {
6349                 DPRINTK(PROBE, ERR,
6350                         "Failed to enable PCI sriov: %d\n", err);
6351                 goto err_novfs;
6352         }
6353         /* If call to enable VFs succeeded then allocate memory
6354          * for per VF control structures.
6355          */
6356         adapter->vfinfo =
6357                 kcalloc(adapter->num_vfs,
6358                         sizeof(struct vf_data_storage), GFP_KERNEL);
6359         if (adapter->vfinfo) {
6360                 /* Now that we're sure SR-IOV is enabled
6361                  * and memory allocated set up the mailbox parameters
6362                  */
6363                 ixgbe_init_mbx_params_pf(hw);
6364                 memcpy(&hw->mbx.ops, ii->mbx_ops,
6365                        sizeof(hw->mbx.ops));
6366
6367                 /* Disable RSC when in SR-IOV mode */
6368                 adapter->flags2 &= ~(IXGBE_FLAG2_RSC_CAPABLE |
6369                                      IXGBE_FLAG2_RSC_ENABLED);
6370                 return;
6371         }
6372
6373         /* Oh oh */
6374         DPRINTK(PROBE, ERR,
6375                 "Unable to allocate memory for VF "
6376                 "Data Storage - SRIOV disabled\n");
6377         pci_disable_sriov(adapter->pdev);
6378
6379 err_novfs:
6380         adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
6381         adapter->num_vfs = 0;
6382 #endif /* CONFIG_PCI_IOV */
6383 }
6384
6385 /**
6386  * ixgbe_probe - Device Initialization Routine
6387  * @pdev: PCI device information struct
6388  * @ent: entry in ixgbe_pci_tbl
6389  *
6390  * Returns 0 on success, negative on failure
6391  *
6392  * ixgbe_probe initializes an adapter identified by a pci_dev structure.
6393  * The OS initialization, configuring of the adapter private structure,
6394  * and a hardware reset occur.
6395  **/
6396 static int __devinit ixgbe_probe(struct pci_dev *pdev,
6397                                  const struct pci_device_id *ent)
6398 {
6399         struct net_device *netdev;
6400         struct ixgbe_adapter *adapter = NULL;
6401         struct ixgbe_hw *hw;
6402         const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
6403         static int cards_found;
6404         int i, err, pci_using_dac;
6405         unsigned int indices = num_possible_cpus();
6406 #ifdef IXGBE_FCOE
6407         u16 device_caps;
6408 #endif
6409         u32 part_num, eec;
6410
6411         err = pci_enable_device_mem(pdev);
6412         if (err)
6413                 return err;
6414
6415         if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
6416             !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
6417                 pci_using_dac = 1;
6418         } else {
6419                 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
6420                 if (err) {
6421                         err = dma_set_coherent_mask(&pdev->dev,
6422                                                     DMA_BIT_MASK(32));
6423                         if (err) {
6424                                 dev_err(&pdev->dev, "No usable DMA "
6425                                         "configuration, aborting\n");
6426                                 goto err_dma;
6427                         }
6428                 }
6429                 pci_using_dac = 0;
6430         }
6431
6432         err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
6433                                            IORESOURCE_MEM), ixgbe_driver_name);
6434         if (err) {
6435                 dev_err(&pdev->dev,
6436                         "pci_request_selected_regions failed 0x%x\n", err);
6437                 goto err_pci_reg;
6438         }
6439
6440         pci_enable_pcie_error_reporting(pdev);
6441
6442         pci_set_master(pdev);
6443         pci_save_state(pdev);
6444
6445         if (ii->mac == ixgbe_mac_82598EB)
6446                 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
6447         else
6448                 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
6449
6450         indices = max_t(unsigned int, indices, IXGBE_MAX_DCB_INDICES);
6451 #ifdef IXGBE_FCOE
6452         indices += min_t(unsigned int, num_possible_cpus(),
6453                          IXGBE_MAX_FCOE_INDICES);
6454 #endif
6455         netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
6456         if (!netdev) {
6457                 err = -ENOMEM;
6458                 goto err_alloc_etherdev;
6459         }
6460
6461         SET_NETDEV_DEV(netdev, &pdev->dev);
6462
6463         pci_set_drvdata(pdev, netdev);
6464         adapter = netdev_priv(netdev);
6465
6466         adapter->netdev = netdev;
6467         adapter->pdev = pdev;
6468         hw = &adapter->hw;
6469         hw->back = adapter;
6470         adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
6471
6472         hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
6473                               pci_resource_len(pdev, 0));
6474         if (!hw->hw_addr) {
6475                 err = -EIO;
6476                 goto err_ioremap;
6477         }
6478
6479         for (i = 1; i <= 5; i++) {
6480                 if (pci_resource_len(pdev, i) == 0)
6481                         continue;
6482         }
6483
6484         netdev->netdev_ops = &ixgbe_netdev_ops;
6485         ixgbe_set_ethtool_ops(netdev);
6486         netdev->watchdog_timeo = 5 * HZ;
6487         strcpy(netdev->name, pci_name(pdev));
6488
6489         adapter->bd_number = cards_found;
6490
6491         /* Setup hw api */
6492         memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
6493         hw->mac.type  = ii->mac;
6494
6495         /* EEPROM */
6496         memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
6497         eec = IXGBE_READ_REG(hw, IXGBE_EEC);
6498         /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
6499         if (!(eec & (1 << 8)))
6500                 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
6501
6502         /* PHY */
6503         memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
6504         hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6505         /* ixgbe_identify_phy_generic will set prtad and mmds properly */
6506         hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
6507         hw->phy.mdio.mmds = 0;
6508         hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
6509         hw->phy.mdio.dev = netdev;
6510         hw->phy.mdio.mdio_read = ixgbe_mdio_read;
6511         hw->phy.mdio.mdio_write = ixgbe_mdio_write;
6512
6513         /* set up this timer and work struct before calling get_invariants
6514          * which might start the timer
6515          */
6516         init_timer(&adapter->sfp_timer);
6517         adapter->sfp_timer.function = &ixgbe_sfp_timer;
6518         adapter->sfp_timer.data = (unsigned long) adapter;
6519
6520         INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
6521
6522         /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
6523         INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
6524
6525         /* a new SFP+ module arrival, called from GPI SDP2 context */
6526         INIT_WORK(&adapter->sfp_config_module_task,
6527                   ixgbe_sfp_config_module_task);
6528
6529         ii->get_invariants(hw);
6530
6531         /* setup the private structure */
6532         err = ixgbe_sw_init(adapter);
6533         if (err)
6534                 goto err_sw_init;
6535
6536         /* Make it possible the adapter to be woken up via WOL */
6537         if (adapter->hw.mac.type == ixgbe_mac_82599EB)
6538                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6539
6540         /*
6541          * If there is a fan on this device and it has failed log the
6542          * failure.
6543          */
6544         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
6545                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
6546                 if (esdp & IXGBE_ESDP_SDP1)
6547                         DPRINTK(PROBE, CRIT,
6548                                 "Fan has stopped, replace the adapter\n");
6549         }
6550
6551         /* reset_hw fills in the perm_addr as well */
6552         err = hw->mac.ops.reset_hw(hw);
6553         if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
6554             hw->mac.type == ixgbe_mac_82598EB) {
6555                 /*
6556                  * Start a kernel thread to watch for a module to arrive.
6557                  * Only do this for 82598, since 82599 will generate
6558                  * interrupts on module arrival.
6559                  */
6560                 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
6561                 mod_timer(&adapter->sfp_timer,
6562                           round_jiffies(jiffies + (2 * HZ)));
6563                 err = 0;
6564         } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
6565                 dev_err(&adapter->pdev->dev, "failed to initialize because "
6566                         "an unsupported SFP+ module type was detected.\n"
6567                         "Reload the driver after installing a supported "
6568                         "module.\n");
6569                 goto err_sw_init;
6570         } else if (err) {
6571                 dev_err(&adapter->pdev->dev, "HW Init failed: %d\n", err);
6572                 goto err_sw_init;
6573         }
6574
6575         ixgbe_probe_vf(adapter, ii);
6576
6577         netdev->features = NETIF_F_SG |
6578                            NETIF_F_IP_CSUM |
6579                            NETIF_F_HW_VLAN_TX |
6580                            NETIF_F_HW_VLAN_RX |
6581                            NETIF_F_HW_VLAN_FILTER;
6582
6583         netdev->features |= NETIF_F_IPV6_CSUM;
6584         netdev->features |= NETIF_F_TSO;
6585         netdev->features |= NETIF_F_TSO6;
6586         netdev->features |= NETIF_F_GRO;
6587
6588         if (adapter->hw.mac.type == ixgbe_mac_82599EB)
6589                 netdev->features |= NETIF_F_SCTP_CSUM;
6590
6591         netdev->vlan_features |= NETIF_F_TSO;
6592         netdev->vlan_features |= NETIF_F_TSO6;
6593         netdev->vlan_features |= NETIF_F_IP_CSUM;
6594         netdev->vlan_features |= NETIF_F_IPV6_CSUM;
6595         netdev->vlan_features |= NETIF_F_SG;
6596
6597         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6598                 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
6599                                     IXGBE_FLAG_DCB_ENABLED);
6600         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
6601                 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
6602
6603 #ifdef CONFIG_IXGBE_DCB
6604         netdev->dcbnl_ops = &dcbnl_ops;
6605 #endif
6606
6607 #ifdef IXGBE_FCOE
6608         if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
6609                 if (hw->mac.ops.get_device_caps) {
6610                         hw->mac.ops.get_device_caps(hw, &device_caps);
6611                         if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
6612                                 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
6613                 }
6614         }
6615 #endif /* IXGBE_FCOE */
6616         if (pci_using_dac)
6617                 netdev->features |= NETIF_F_HIGHDMA;
6618
6619         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
6620                 netdev->features |= NETIF_F_LRO;
6621
6622         /* make sure the EEPROM is good */
6623         if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
6624                 dev_err(&pdev->dev, "The EEPROM Checksum Is Not Valid\n");
6625                 err = -EIO;
6626                 goto err_eeprom;
6627         }
6628
6629         memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
6630         memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
6631
6632         if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
6633                 dev_err(&pdev->dev, "invalid MAC address\n");
6634                 err = -EIO;
6635                 goto err_eeprom;
6636         }
6637
6638         /* power down the optics */
6639         if (hw->phy.multispeed_fiber)
6640                 hw->mac.ops.disable_tx_laser(hw);
6641
6642         init_timer(&adapter->watchdog_timer);
6643         adapter->watchdog_timer.function = &ixgbe_watchdog;
6644         adapter->watchdog_timer.data = (unsigned long)adapter;
6645
6646         INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
6647         INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
6648
6649         err = ixgbe_init_interrupt_scheme(adapter);
6650         if (err)
6651                 goto err_sw_init;
6652
6653         switch (pdev->device) {
6654         case IXGBE_DEV_ID_82599_KX4:
6655                 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
6656                                 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
6657                 break;
6658         default:
6659                 adapter->wol = 0;
6660                 break;
6661         }
6662         device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
6663
6664         /* pick up the PCI bus settings for reporting later */
6665         hw->mac.ops.get_bus_info(hw);
6666
6667         /* print bus type/speed/width info */
6668         dev_info(&pdev->dev, "(PCI Express:%s:%s) %pM\n",
6669                 ((hw->bus.speed == ixgbe_bus_speed_5000) ? "5.0Gb/s":
6670                  (hw->bus.speed == ixgbe_bus_speed_2500) ? "2.5Gb/s":"Unknown"),
6671                 ((hw->bus.width == ixgbe_bus_width_pcie_x8) ? "Width x8" :
6672                  (hw->bus.width == ixgbe_bus_width_pcie_x4) ? "Width x4" :
6673                  (hw->bus.width == ixgbe_bus_width_pcie_x1) ? "Width x1" :
6674                  "Unknown"),
6675                 netdev->dev_addr);
6676         ixgbe_read_pba_num_generic(hw, &part_num);
6677         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
6678                 dev_info(&pdev->dev, "MAC: %d, PHY: %d, SFP+: %d, PBA No: %06x-%03x\n",
6679                          hw->mac.type, hw->phy.type, hw->phy.sfp_type,
6680                          (part_num >> 8), (part_num & 0xff));
6681         else
6682                 dev_info(&pdev->dev, "MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
6683                          hw->mac.type, hw->phy.type,
6684                          (part_num >> 8), (part_num & 0xff));
6685
6686         if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
6687                 dev_warn(&pdev->dev, "PCI-Express bandwidth available for "
6688                          "this card is not sufficient for optimal "
6689                          "performance.\n");
6690                 dev_warn(&pdev->dev, "For optimal performance a x8 "
6691                          "PCI-Express slot is required.\n");
6692         }
6693
6694         /* save off EEPROM version number */
6695         hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
6696
6697         /* reset the hardware with the new settings */
6698         err = hw->mac.ops.start_hw(hw);
6699
6700         if (err == IXGBE_ERR_EEPROM_VERSION) {
6701                 /* We are running on a pre-production device, log a warning */
6702                 dev_warn(&pdev->dev, "This device is a pre-production "
6703                          "adapter/LOM.  Please be aware there may be issues "
6704                          "associated with your hardware.  If you are "
6705                          "experiencing problems please contact your Intel or "
6706                          "hardware representative who provided you with this "
6707                          "hardware.\n");
6708         }
6709         strcpy(netdev->name, "eth%d");
6710         err = register_netdev(netdev);
6711         if (err)
6712                 goto err_register;
6713
6714         /* carrier off reporting is important to ethtool even BEFORE open */
6715         netif_carrier_off(netdev);
6716
6717         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
6718             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
6719                 INIT_WORK(&adapter->fdir_reinit_task, ixgbe_fdir_reinit_task);
6720
6721 #ifdef CONFIG_IXGBE_DCA
6722         if (dca_add_requester(&pdev->dev) == 0) {
6723                 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
6724                 ixgbe_setup_dca(adapter);
6725         }
6726 #endif
6727         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
6728                 DPRINTK(PROBE, INFO, "IOV is enabled with %d VFs\n",
6729                         adapter->num_vfs);
6730                 for (i = 0; i < adapter->num_vfs; i++)
6731                         ixgbe_vf_configuration(pdev, (i | 0x10000000));
6732         }
6733
6734         /* add san mac addr to netdev */
6735         ixgbe_add_sanmac_netdev(netdev);
6736
6737         dev_info(&pdev->dev, "Intel(R) 10 Gigabit Network Connection\n");
6738         cards_found++;
6739         return 0;
6740
6741 err_register:
6742         ixgbe_release_hw_control(adapter);
6743         ixgbe_clear_interrupt_scheme(adapter);
6744 err_sw_init:
6745 err_eeprom:
6746         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6747                 ixgbe_disable_sriov(adapter);
6748         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
6749         del_timer_sync(&adapter->sfp_timer);
6750         cancel_work_sync(&adapter->sfp_task);
6751         cancel_work_sync(&adapter->multispeed_fiber_task);
6752         cancel_work_sync(&adapter->sfp_config_module_task);
6753         iounmap(hw->hw_addr);
6754 err_ioremap:
6755         free_netdev(netdev);
6756 err_alloc_etherdev:
6757         pci_release_selected_regions(pdev, pci_select_bars(pdev,
6758                                      IORESOURCE_MEM));
6759 err_pci_reg:
6760 err_dma:
6761         pci_disable_device(pdev);
6762         return err;
6763 }
6764
6765 /**
6766  * ixgbe_remove - Device Removal Routine
6767  * @pdev: PCI device information struct
6768  *
6769  * ixgbe_remove is called by the PCI subsystem to alert the driver
6770  * that it should release a PCI device.  The could be caused by a
6771  * Hot-Plug event, or because the driver is going to be removed from
6772  * memory.
6773  **/
6774 static void __devexit ixgbe_remove(struct pci_dev *pdev)
6775 {
6776         struct net_device *netdev = pci_get_drvdata(pdev);
6777         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6778
6779         set_bit(__IXGBE_DOWN, &adapter->state);
6780         /* clear the module not found bit to make sure the worker won't
6781          * reschedule
6782          */
6783         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
6784         del_timer_sync(&adapter->watchdog_timer);
6785
6786         del_timer_sync(&adapter->sfp_timer);
6787         cancel_work_sync(&adapter->watchdog_task);
6788         cancel_work_sync(&adapter->sfp_task);
6789         cancel_work_sync(&adapter->multispeed_fiber_task);
6790         cancel_work_sync(&adapter->sfp_config_module_task);
6791         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
6792             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
6793                 cancel_work_sync(&adapter->fdir_reinit_task);
6794         flush_scheduled_work();
6795
6796 #ifdef CONFIG_IXGBE_DCA
6797         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
6798                 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
6799                 dca_remove_requester(&pdev->dev);
6800                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
6801         }
6802
6803 #endif
6804 #ifdef IXGBE_FCOE
6805         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
6806                 ixgbe_cleanup_fcoe(adapter);
6807
6808 #endif /* IXGBE_FCOE */
6809
6810         /* remove the added san mac */
6811         ixgbe_del_sanmac_netdev(netdev);
6812
6813         if (netdev->reg_state == NETREG_REGISTERED)
6814                 unregister_netdev(netdev);
6815
6816         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6817                 ixgbe_disable_sriov(adapter);
6818
6819         ixgbe_clear_interrupt_scheme(adapter);
6820
6821         ixgbe_release_hw_control(adapter);
6822
6823         iounmap(adapter->hw.hw_addr);
6824         pci_release_selected_regions(pdev, pci_select_bars(pdev,
6825                                      IORESOURCE_MEM));
6826
6827         DPRINTK(PROBE, INFO, "complete\n");
6828
6829         free_netdev(netdev);
6830
6831         pci_disable_pcie_error_reporting(pdev);
6832
6833         pci_disable_device(pdev);
6834 }
6835
6836 /**
6837  * ixgbe_io_error_detected - called when PCI error is detected
6838  * @pdev: Pointer to PCI device
6839  * @state: The current pci connection state
6840  *
6841  * This function is called after a PCI bus error affecting
6842  * this device has been detected.
6843  */
6844 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
6845                                                 pci_channel_state_t state)
6846 {
6847         struct net_device *netdev = pci_get_drvdata(pdev);
6848         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6849
6850         netif_device_detach(netdev);
6851
6852         if (state == pci_channel_io_perm_failure)
6853                 return PCI_ERS_RESULT_DISCONNECT;
6854
6855         if (netif_running(netdev))
6856                 ixgbe_down(adapter);
6857         pci_disable_device(pdev);
6858
6859         /* Request a slot reset. */
6860         return PCI_ERS_RESULT_NEED_RESET;
6861 }
6862
6863 /**
6864  * ixgbe_io_slot_reset - called after the pci bus has been reset.
6865  * @pdev: Pointer to PCI device
6866  *
6867  * Restart the card from scratch, as if from a cold-boot.
6868  */
6869 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
6870 {
6871         struct net_device *netdev = pci_get_drvdata(pdev);
6872         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6873         pci_ers_result_t result;
6874         int err;
6875
6876         if (pci_enable_device_mem(pdev)) {
6877                 DPRINTK(PROBE, ERR,
6878                         "Cannot re-enable PCI device after reset.\n");
6879                 result = PCI_ERS_RESULT_DISCONNECT;
6880         } else {
6881                 pci_set_master(pdev);
6882                 pci_restore_state(pdev);
6883                 pci_save_state(pdev);
6884
6885                 pci_wake_from_d3(pdev, false);
6886
6887                 ixgbe_reset(adapter);
6888                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6889                 result = PCI_ERS_RESULT_RECOVERED;
6890         }
6891
6892         err = pci_cleanup_aer_uncorrect_error_status(pdev);
6893         if (err) {
6894                 dev_err(&pdev->dev,
6895                   "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", err);
6896                 /* non-fatal, continue */
6897         }
6898
6899         return result;
6900 }
6901
6902 /**
6903  * ixgbe_io_resume - called when traffic can start flowing again.
6904  * @pdev: Pointer to PCI device
6905  *
6906  * This callback is called when the error recovery driver tells us that
6907  * its OK to resume normal operation.
6908  */
6909 static void ixgbe_io_resume(struct pci_dev *pdev)
6910 {
6911         struct net_device *netdev = pci_get_drvdata(pdev);
6912         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6913
6914         if (netif_running(netdev)) {
6915                 if (ixgbe_up(adapter)) {
6916                         DPRINTK(PROBE, INFO, "ixgbe_up failed after reset\n");
6917                         return;
6918                 }
6919         }
6920
6921         netif_device_attach(netdev);
6922 }
6923
6924 static struct pci_error_handlers ixgbe_err_handler = {
6925         .error_detected = ixgbe_io_error_detected,
6926         .slot_reset = ixgbe_io_slot_reset,
6927         .resume = ixgbe_io_resume,
6928 };
6929
6930 static struct pci_driver ixgbe_driver = {
6931         .name     = ixgbe_driver_name,
6932         .id_table = ixgbe_pci_tbl,
6933         .probe    = ixgbe_probe,
6934         .remove   = __devexit_p(ixgbe_remove),
6935 #ifdef CONFIG_PM
6936         .suspend  = ixgbe_suspend,
6937         .resume   = ixgbe_resume,
6938 #endif
6939         .shutdown = ixgbe_shutdown,
6940         .err_handler = &ixgbe_err_handler
6941 };
6942
6943 /**
6944  * ixgbe_init_module - Driver Registration Routine
6945  *
6946  * ixgbe_init_module is the first routine called when the driver is
6947  * loaded. All it does is register with the PCI subsystem.
6948  **/
6949 static int __init ixgbe_init_module(void)
6950 {
6951         int ret;
6952         printk(KERN_INFO "%s: %s - version %s\n", ixgbe_driver_name,
6953                ixgbe_driver_string, ixgbe_driver_version);
6954
6955         printk(KERN_INFO "%s: %s\n", ixgbe_driver_name, ixgbe_copyright);
6956
6957 #ifdef CONFIG_IXGBE_DCA
6958         dca_register_notify(&dca_notifier);
6959 #endif
6960
6961         ret = pci_register_driver(&ixgbe_driver);
6962         return ret;
6963 }
6964
6965 module_init(ixgbe_init_module);
6966
6967 /**
6968  * ixgbe_exit_module - Driver Exit Cleanup Routine
6969  *
6970  * ixgbe_exit_module is called just before the driver is removed
6971  * from memory.
6972  **/
6973 static void __exit ixgbe_exit_module(void)
6974 {
6975 #ifdef CONFIG_IXGBE_DCA
6976         dca_unregister_notify(&dca_notifier);
6977 #endif
6978         pci_unregister_driver(&ixgbe_driver);
6979 }
6980
6981 #ifdef CONFIG_IXGBE_DCA
6982 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
6983                             void *p)
6984 {
6985         int ret_val;
6986
6987         ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
6988                                          __ixgbe_notify_dca);
6989
6990         return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
6991 }
6992
6993 #endif /* CONFIG_IXGBE_DCA */
6994 #ifdef DEBUG
6995 /**
6996  * ixgbe_get_hw_dev_name - return device name string
6997  * used by hardware layer to print debugging information
6998  **/
6999 char *ixgbe_get_hw_dev_name(struct ixgbe_hw *hw)
7000 {
7001         struct ixgbe_adapter *adapter = hw->back;
7002         return adapter->netdev->name;
7003 }
7004
7005 #endif
7006 module_exit(ixgbe_exit_module);
7007
7008 /* ixgbe_main.c */