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   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2009 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 /* ethtool support for ixgbe */
  29
  30 #include <linux/types.h>
  31 #include <linux/module.h>
  32 #include <linux/pci.h>
  33 #include <linux/netdevice.h>
  34 #include <linux/ethtool.h>
  35 #include <linux/vmalloc.h>
  36 #include <linux/uaccess.h>
  37
  38 #include "ixgbe.h"
  39
  40
  41 #define IXGBE_ALL_RAR_ENTRIES 16
  42
  43 enum {NETDEV_STATS, IXGBE_STATS};
  44
  45 struct ixgbe_stats {
  46         char stat_string[ETH_GSTRING_LEN];
  47         int type;
  48         int sizeof_stat;
  49         int stat_offset;
  50 };
  51
  52 #define IXGBE_STAT(m)           IXGBE_STATS, \
  53                                 sizeof(((struct ixgbe_adapter *)0)->m), \
  54                                 offsetof(struct ixgbe_adapter, m)
  55 #define IXGBE_NETDEV_STAT(m)    NETDEV_STATS, \
  56                                 sizeof(((struct net_device *)0)->m), \
  57                                 offsetof(struct net_device, m)
  58
  59 static struct ixgbe_stats ixgbe_gstrings_stats[] = {
  60         {"rx_packets", IXGBE_NETDEV_STAT(stats.rx_packets)},
  61         {"tx_packets", IXGBE_NETDEV_STAT(stats.tx_packets)},
  62         {"rx_bytes", IXGBE_NETDEV_STAT(stats.rx_bytes)},
  63         {"tx_bytes", IXGBE_NETDEV_STAT(stats.tx_bytes)},
  64         {"rx_pkts_nic", IXGBE_STAT(stats.gprc)},
  65         {"tx_pkts_nic", IXGBE_STAT(stats.gptc)},
  66         {"rx_bytes_nic", IXGBE_STAT(stats.gorc)},
  67         {"tx_bytes_nic", IXGBE_STAT(stats.gotc)},
  68         {"lsc_int", IXGBE_STAT(lsc_int)},
  69         {"tx_busy", IXGBE_STAT(tx_busy)},
  70         {"non_eop_descs", IXGBE_STAT(non_eop_descs)},
  71         {"rx_errors", IXGBE_NETDEV_STAT(stats.rx_errors)},
  72         {"tx_errors", IXGBE_NETDEV_STAT(stats.tx_errors)},
  73         {"rx_dropped", IXGBE_NETDEV_STAT(stats.rx_dropped)},
  74         {"tx_dropped", IXGBE_NETDEV_STAT(stats.tx_dropped)},
  75         {"multicast", IXGBE_NETDEV_STAT(stats.multicast)},
  76         {"broadcast", IXGBE_STAT(stats.bprc)},
  77         {"rx_no_buffer_count", IXGBE_STAT(stats.rnbc[0]) },
  78         {"collisions", IXGBE_NETDEV_STAT(stats.collisions)},
  79         {"rx_over_errors", IXGBE_NETDEV_STAT(stats.rx_over_errors)},
  80         {"rx_crc_errors", IXGBE_NETDEV_STAT(stats.rx_crc_errors)},
  81         {"rx_frame_errors", IXGBE_NETDEV_STAT(stats.rx_frame_errors)},
  82         {"hw_rsc_aggregated", IXGBE_STAT(rsc_total_count)},
  83         {"hw_rsc_flushed", IXGBE_STAT(rsc_total_flush)},
  84         {"fdir_match", IXGBE_STAT(stats.fdirmatch)},
  85         {"fdir_miss", IXGBE_STAT(stats.fdirmiss)},
  86         {"rx_fifo_errors", IXGBE_NETDEV_STAT(stats.rx_fifo_errors)},
  87         {"rx_missed_errors", IXGBE_NETDEV_STAT(stats.rx_missed_errors)},
  88         {"tx_aborted_errors", IXGBE_NETDEV_STAT(stats.tx_aborted_errors)},
  89         {"tx_carrier_errors", IXGBE_NETDEV_STAT(stats.tx_carrier_errors)},
  90         {"tx_fifo_errors", IXGBE_NETDEV_STAT(stats.tx_fifo_errors)},
  91         {"tx_heartbeat_errors", IXGBE_NETDEV_STAT(stats.tx_heartbeat_errors)},
  92         {"tx_timeout_count", IXGBE_STAT(tx_timeout_count)},
  93         {"tx_restart_queue", IXGBE_STAT(restart_queue)},
  94         {"rx_long_length_errors", IXGBE_STAT(stats.roc)},
  95         {"rx_short_length_errors", IXGBE_STAT(stats.ruc)},
  96         {"tx_tcp4_seg_ctxt", IXGBE_STAT(hw_tso_ctxt)},
  97         {"tx_tcp6_seg_ctxt", IXGBE_STAT(hw_tso6_ctxt)},
  98         {"tx_flow_control_xon", IXGBE_STAT(stats.lxontxc)},
  99         {"rx_flow_control_xon", IXGBE_STAT(stats.lxonrxc)},
 100         {"tx_flow_control_xoff", IXGBE_STAT(stats.lxofftxc)},
 101         {"rx_flow_control_xoff", IXGBE_STAT(stats.lxoffrxc)},
 102         {"rx_csum_offload_good", IXGBE_STAT(hw_csum_rx_good)},
 103         {"rx_csum_offload_errors", IXGBE_STAT(hw_csum_rx_error)},
 104         {"tx_csum_offload_ctxt", IXGBE_STAT(hw_csum_tx_good)},
 105         {"rx_header_split", IXGBE_STAT(rx_hdr_split)},
 106         {"alloc_rx_page_failed", IXGBE_STAT(alloc_rx_page_failed)},
 107         {"alloc_rx_buff_failed", IXGBE_STAT(alloc_rx_buff_failed)},
 108         {"rx_no_dma_resources", IXGBE_STAT(hw_rx_no_dma_resources)},
 109 #ifdef IXGBE_FCOE
 110         {"fcoe_bad_fccrc", IXGBE_STAT(stats.fccrc)},
 111         {"rx_fcoe_dropped", IXGBE_STAT(stats.fcoerpdc)},
 112         {"rx_fcoe_packets", IXGBE_STAT(stats.fcoeprc)},
 113         {"rx_fcoe_dwords", IXGBE_STAT(stats.fcoedwrc)},
 114         {"tx_fcoe_packets", IXGBE_STAT(stats.fcoeptc)},
 115         {"tx_fcoe_dwords", IXGBE_STAT(stats.fcoedwtc)},
 116 #endif /* IXGBE_FCOE */
 117 };
 118
 119 #define IXGBE_QUEUE_STATS_LEN \
 120         ((((struct ixgbe_adapter *)netdev_priv(netdev))->num_tx_queues + \
 121         ((struct ixgbe_adapter *)netdev_priv(netdev))->num_rx_queues) * \
 122         (sizeof(struct ixgbe_queue_stats) / sizeof(u64)))
 123 #define IXGBE_GLOBAL_STATS_LEN ARRAY_SIZE(ixgbe_gstrings_stats)
 124 #define IXGBE_PB_STATS_LEN ( \
 125                  (((struct ixgbe_adapter *)netdev_priv(netdev))->flags & \
 126                  IXGBE_FLAG_DCB_ENABLED) ? \
 127                  (sizeof(((struct ixgbe_adapter *)0)->stats.pxonrxc) + \
 128                   sizeof(((struct ixgbe_adapter *)0)->stats.pxontxc) + \
 129                   sizeof(((struct ixgbe_adapter *)0)->stats.pxoffrxc) + \
 130                   sizeof(((struct ixgbe_adapter *)0)->stats.pxofftxc)) \
 131                   / sizeof(u64) : 0)
 132 #define IXGBE_STATS_LEN (IXGBE_GLOBAL_STATS_LEN + \
 133                          IXGBE_PB_STATS_LEN + \
 134                          IXGBE_QUEUE_STATS_LEN)
 135
 136 static const char ixgbe_gstrings_test[][ETH_GSTRING_LEN] = {
 137         "Register test  (offline)", "Eeprom test    (offline)",
 138         "Interrupt test (offline)", "Loopback test  (offline)",
 139         "Link test   (on/offline)"
 140 };
 141 #define IXGBE_TEST_LEN sizeof(ixgbe_gstrings_test) / ETH_GSTRING_LEN
 142
 143 static int ixgbe_get_settings(struct net_device *netdev,
 144                               struct ethtool_cmd *ecmd)
 145 {
 146         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 147         struct ixgbe_hw *hw = &adapter->hw;
 148         u32 link_speed = 0;
 149         bool link_up;
 150
 151         ecmd->supported = SUPPORTED_10000baseT_Full;
 152         ecmd->autoneg = AUTONEG_ENABLE;
 153         ecmd->transceiver = XCVR_EXTERNAL;
 154         if ((hw->phy.media_type == ixgbe_media_type_copper) ||
 155             (hw->phy.multispeed_fiber)) {
 156                 ecmd->supported |= (SUPPORTED_1000baseT_Full |
 157                                     SUPPORTED_Autoneg);
 158
 159                 ecmd->advertising = ADVERTISED_Autoneg;
 160                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
 161                         ecmd->advertising |= ADVERTISED_10000baseT_Full;
 162                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
 163                         ecmd->advertising |= ADVERTISED_1000baseT_Full;
 164                 /*
 165                  * It's possible that phy.autoneg_advertised may not be
 166                  * set yet.  If so display what the default would be -
 167                  * both 1G and 10G supported.
 168                  */
 169                 if (!(ecmd->advertising & (ADVERTISED_1000baseT_Full |
 170                                            ADVERTISED_10000baseT_Full)))
 171                         ecmd->advertising |= (ADVERTISED_10000baseT_Full |
 172                                               ADVERTISED_1000baseT_Full);
 173
 174                 if (hw->phy.media_type == ixgbe_media_type_copper) {
 175                         ecmd->supported |= SUPPORTED_TP;
 176                         ecmd->advertising |= ADVERTISED_TP;
 177                         ecmd->port = PORT_TP;
 178                 } else {
 179                         ecmd->supported |= SUPPORTED_FIBRE;
 180                         ecmd->advertising |= ADVERTISED_FIBRE;
 181                         ecmd->port = PORT_FIBRE;
 182                 }
 183         } else if (hw->phy.media_type == ixgbe_media_type_backplane) {
 184                 /* Set as FIBRE until SERDES defined in kernel */
 185                 if (hw->device_id == IXGBE_DEV_ID_82598_BX) {
 186                         ecmd->supported = (SUPPORTED_1000baseT_Full |
 187                                            SUPPORTED_FIBRE);
 188                         ecmd->advertising = (ADVERTISED_1000baseT_Full |
 189                                              ADVERTISED_FIBRE);
 190                         ecmd->port = PORT_FIBRE;
 191                         ecmd->autoneg = AUTONEG_DISABLE;
 192                 } else {
 193                         ecmd->supported |= (SUPPORTED_1000baseT_Full |
 194                                             SUPPORTED_FIBRE);
 195                         ecmd->advertising = (ADVERTISED_10000baseT_Full |
 196                                              ADVERTISED_1000baseT_Full |
 197                                              ADVERTISED_FIBRE);
 198                         ecmd->port = PORT_FIBRE;
 199                 }
 200         } else {
 201                 ecmd->supported |= SUPPORTED_FIBRE;
 202                 ecmd->advertising = (ADVERTISED_10000baseT_Full |
 203                                      ADVERTISED_FIBRE);
 204                 ecmd->port = PORT_FIBRE;
 205                 ecmd->autoneg = AUTONEG_DISABLE;
 206         }
 207
 208         /* Get PHY type */
 209         switch (adapter->hw.phy.type) {
 210         case ixgbe_phy_tn:
 211         case ixgbe_phy_cu_unknown:
 212                 /* Copper 10G-BASET */
 213                 ecmd->port = PORT_TP;
 214                 break;
 215         case ixgbe_phy_qt:
 216                 ecmd->port = PORT_FIBRE;
 217                 break;
 218         case ixgbe_phy_nl:
 219         case ixgbe_phy_tw_tyco:
 220         case ixgbe_phy_tw_unknown:
 221         case ixgbe_phy_sfp_ftl:
 222         case ixgbe_phy_sfp_avago:
 223         case ixgbe_phy_sfp_intel:
 224         case ixgbe_phy_sfp_unknown:
 225                 switch (adapter->hw.phy.sfp_type) {
 226                 /* SFP+ devices, further checking needed */
 227                 case ixgbe_sfp_type_da_cu:
 228                 case ixgbe_sfp_type_da_cu_core0:
 229                 case ixgbe_sfp_type_da_cu_core1:
 230                         ecmd->port = PORT_DA;
 231                         break;
 232                 case ixgbe_sfp_type_sr:
 233                 case ixgbe_sfp_type_lr:
 234                 case ixgbe_sfp_type_srlr_core0:
 235                 case ixgbe_sfp_type_srlr_core1:
 236                         ecmd->port = PORT_FIBRE;
 237                         break;
 238                 case ixgbe_sfp_type_not_present:
 239                         ecmd->port = PORT_NONE;
 240                         break;
 241                 case ixgbe_sfp_type_unknown:
 242                 default:
 243                         ecmd->port = PORT_OTHER;
 244                         break;
 245                 }
 246                 break;
 247         case ixgbe_phy_xaui:
 248                 ecmd->port = PORT_NONE;
 249                 break;
 250         case ixgbe_phy_unknown:
 251         case ixgbe_phy_generic:
 252         case ixgbe_phy_sfp_unsupported:
 253         default:
 254                 ecmd->port = PORT_OTHER;
 255                 break;
 256         }
 257
 258         hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
 259         if (link_up) {
 260                 ecmd->speed = (link_speed == IXGBE_LINK_SPEED_10GB_FULL) ?
 261                                SPEED_10000 : SPEED_1000;
 262                 ecmd->duplex = DUPLEX_FULL;
 263         } else {
 264                 ecmd->speed = -1;
 265                 ecmd->duplex = -1;
 266         }
 267
 268         return 0;
 269 }
 270
 271 static int ixgbe_set_settings(struct net_device *netdev,
 272                               struct ethtool_cmd *ecmd)
 273 {
 274         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 275         struct ixgbe_hw *hw = &adapter->hw;
 276         u32 advertised, old;
 277         s32 err = 0;
 278
 279         if ((hw->phy.media_type == ixgbe_media_type_copper) ||
 280             (hw->phy.multispeed_fiber)) {
 281                 /* 10000/copper and 1000/copper must autoneg
 282                  * this function does not support any duplex forcing, but can
 283                  * limit the advertising of the adapter to only 10000 or 1000 */
 284                 if (ecmd->autoneg == AUTONEG_DISABLE)
 285                         return -EINVAL;
 286
 287                 old = hw->phy.autoneg_advertised;
 288                 advertised = 0;
 289                 if (ecmd->advertising & ADVERTISED_10000baseT_Full)
 290                         advertised |= IXGBE_LINK_SPEED_10GB_FULL;
 291
 292                 if (ecmd->advertising & ADVERTISED_1000baseT_Full)
 293                         advertised |= IXGBE_LINK_SPEED_1GB_FULL;
 294
 295                 if (old == advertised)
 296                         return err;
 297                 /* this sets the link speed and restarts auto-neg */
 298                 hw->mac.autotry_restart = true;
 299                 err = hw->mac.ops.setup_link(hw, advertised, true, true);
 300                 if (err) {
 301                         DPRINTK(PROBE, INFO,
 302                                 "setup link failed with code %d\n", err);
 303                         hw->mac.ops.setup_link(hw, old, true, true);
 304                 }
 305         } else {
 306                 /* in this case we currently only support 10Gb/FULL */
 307                 if ((ecmd->autoneg == AUTONEG_ENABLE) ||
 308                     (ecmd->advertising != ADVERTISED_10000baseT_Full) ||
 309                     (ecmd->speed + ecmd->duplex != SPEED_10000 + DUPLEX_FULL))
 310                         return -EINVAL;
 311         }
 312
 313         return err;
 314 }
 315
 316 static void ixgbe_get_pauseparam(struct net_device *netdev,
 317                                  struct ethtool_pauseparam *pause)
 318 {
 319         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 320         struct ixgbe_hw *hw = &adapter->hw;
 321
 322         /*
 323          * Flow Control Autoneg isn't on if
 324          *  - we didn't ask for it OR
 325          *  - it failed, we know this by tx & rx being off
 326          */
 327         if (hw->fc.disable_fc_autoneg ||
 328             (hw->fc.current_mode == ixgbe_fc_none))
 329                 pause->autoneg = 0;
 330         else
 331                 pause->autoneg = 1;
 332
 333 #ifdef CONFIG_DCB
 334         if (hw->fc.current_mode == ixgbe_fc_pfc) {
 335                 pause->rx_pause = 0;
 336                 pause->tx_pause = 0;
 337         }
 338
 339 #endif
 340         if (hw->fc.current_mode == ixgbe_fc_rx_pause) {
 341                 pause->rx_pause = 1;
 342         } else if (hw->fc.current_mode == ixgbe_fc_tx_pause) {
 343                 pause->tx_pause = 1;
 344         } else if (hw->fc.current_mode == ixgbe_fc_full) {
 345                 pause->rx_pause = 1;
 346                 pause->tx_pause = 1;
 347         }
 348 }
 349
 350 static int ixgbe_set_pauseparam(struct net_device *netdev,
 351                                 struct ethtool_pauseparam *pause)
 352 {
 353         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 354         struct ixgbe_hw *hw = &adapter->hw;
 355         struct ixgbe_fc_info fc;
 356
 357 #ifdef CONFIG_DCB
 358         if (adapter->dcb_cfg.pfc_mode_enable ||
 359                 ((hw->mac.type == ixgbe_mac_82598EB) &&
 360                 (adapter->flags & IXGBE_FLAG_DCB_ENABLED)))
 361                 return -EINVAL;
 362
 363 #endif
 364
 365         fc = hw->fc;
 366
 367         if (pause->autoneg != AUTONEG_ENABLE)
 368                 fc.disable_fc_autoneg = true;
 369         else
 370                 fc.disable_fc_autoneg = false;
 371
 372         if (pause->rx_pause && pause->tx_pause)
 373                 fc.requested_mode = ixgbe_fc_full;
 374         else if (pause->rx_pause && !pause->tx_pause)
 375                 fc.requested_mode = ixgbe_fc_rx_pause;
 376         else if (!pause->rx_pause && pause->tx_pause)
 377                 fc.requested_mode = ixgbe_fc_tx_pause;
 378         else if (!pause->rx_pause && !pause->tx_pause)
 379                 fc.requested_mode = ixgbe_fc_none;
 380         else
 381                 return -EINVAL;
 382
 383 #ifdef CONFIG_DCB
 384         adapter->last_lfc_mode = fc.requested_mode;
 385 #endif
 386
 387         /* if the thing changed then we'll update and use new autoneg */
 388         if (memcmp(&fc, &hw->fc, sizeof(struct ixgbe_fc_info))) {
 389                 hw->fc = fc;
 390                 if (netif_running(netdev))
 391                         ixgbe_reinit_locked(adapter);
 392                 else
 393                         ixgbe_reset(adapter);
 394         }
 395
 396         return 0;
 397 }
 398
 399 static u32 ixgbe_get_rx_csum(struct net_device *netdev)
 400 {
 401         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 402         return (adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED);
 403 }
 404
 405 static int ixgbe_set_rx_csum(struct net_device *netdev, u32 data)
 406 {
 407         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 408         if (data)
 409                 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
 410         else
 411                 adapter->flags &= ~IXGBE_FLAG_RX_CSUM_ENABLED;
 412
 413         if (netif_running(netdev))
 414                 ixgbe_reinit_locked(adapter);
 415         else
 416                 ixgbe_reset(adapter);
 417
 418         return 0;
 419 }
 420
 421 static u32 ixgbe_get_tx_csum(struct net_device *netdev)
 422 {
 423         return (netdev->features & NETIF_F_IP_CSUM) != 0;
 424 }
 425
 426 static int ixgbe_set_tx_csum(struct net_device *netdev, u32 data)
 427 {
 428         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 429
 430         if (data) {
 431                 netdev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
 432                 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
 433                         netdev->features |= NETIF_F_SCTP_CSUM;
 434         } else {
 435                 netdev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
 436                 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
 437                         netdev->features &= ~NETIF_F_SCTP_CSUM;
 438         }
 439
 440         return 0;
 441 }
 442
 443 static int ixgbe_set_tso(struct net_device *netdev, u32 data)
 444 {
 445         if (data) {
 446                 netdev->features |= NETIF_F_TSO;
 447                 netdev->features |= NETIF_F_TSO6;
 448         } else {
 449                 netif_tx_stop_all_queues(netdev);
 450                 netdev->features &= ~NETIF_F_TSO;
 451                 netdev->features &= ~NETIF_F_TSO6;
 452                 netif_tx_start_all_queues(netdev);
 453         }
 454         return 0;
 455 }
 456
 457 static u32 ixgbe_get_msglevel(struct net_device *netdev)
 458 {
 459         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 460         return adapter->msg_enable;
 461 }
 462
 463 static void ixgbe_set_msglevel(struct net_device *netdev, u32 data)
 464 {
 465         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 466         adapter->msg_enable = data;
 467 }
 468
 469 static int ixgbe_get_regs_len(struct net_device *netdev)
 470 {
 471 #define IXGBE_REGS_LEN  1128
 472         return IXGBE_REGS_LEN * sizeof(u32);
 473 }
 474
 475 #define IXGBE_GET_STAT(_A_, _R_) _A_->stats._R_
 476
 477 static void ixgbe_get_regs(struct net_device *netdev,
 478                            struct ethtool_regs *regs, void *p)
 479 {
 480         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 481         struct ixgbe_hw *hw = &adapter->hw;
 482         u32 *regs_buff = p;
 483         u8 i;
 484
 485         memset(p, 0, IXGBE_REGS_LEN * sizeof(u32));
 486
 487         regs->version = (1 << 24) | hw->revision_id << 16 | hw->device_id;
 488
 489         /* General Registers */
 490         regs_buff[0] = IXGBE_READ_REG(hw, IXGBE_CTRL);
 491         regs_buff[1] = IXGBE_READ_REG(hw, IXGBE_STATUS);
 492         regs_buff[2] = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 493         regs_buff[3] = IXGBE_READ_REG(hw, IXGBE_ESDP);
 494         regs_buff[4] = IXGBE_READ_REG(hw, IXGBE_EODSDP);
 495         regs_buff[5] = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
 496         regs_buff[6] = IXGBE_READ_REG(hw, IXGBE_FRTIMER);
 497         regs_buff[7] = IXGBE_READ_REG(hw, IXGBE_TCPTIMER);
 498
 499         /* NVM Register */
 500         regs_buff[8] = IXGBE_READ_REG(hw, IXGBE_EEC);
 501         regs_buff[9] = IXGBE_READ_REG(hw, IXGBE_EERD);
 502         regs_buff[10] = IXGBE_READ_REG(hw, IXGBE_FLA);
 503         regs_buff[11] = IXGBE_READ_REG(hw, IXGBE_EEMNGCTL);
 504         regs_buff[12] = IXGBE_READ_REG(hw, IXGBE_EEMNGDATA);
 505         regs_buff[13] = IXGBE_READ_REG(hw, IXGBE_FLMNGCTL);
 506         regs_buff[14] = IXGBE_READ_REG(hw, IXGBE_FLMNGDATA);
 507         regs_buff[15] = IXGBE_READ_REG(hw, IXGBE_FLMNGCNT);
 508         regs_buff[16] = IXGBE_READ_REG(hw, IXGBE_FLOP);
 509         regs_buff[17] = IXGBE_READ_REG(hw, IXGBE_GRC);
 510
 511         /* Interrupt */
 512         /* don't read EICR because it can clear interrupt causes, instead
 513          * read EICS which is a shadow but doesn't clear EICR */
 514         regs_buff[18] = IXGBE_READ_REG(hw, IXGBE_EICS);
 515         regs_buff[19] = IXGBE_READ_REG(hw, IXGBE_EICS);
 516         regs_buff[20] = IXGBE_READ_REG(hw, IXGBE_EIMS);
 517         regs_buff[21] = IXGBE_READ_REG(hw, IXGBE_EIMC);
 518         regs_buff[22] = IXGBE_READ_REG(hw, IXGBE_EIAC);
 519         regs_buff[23] = IXGBE_READ_REG(hw, IXGBE_EIAM);
 520         regs_buff[24] = IXGBE_READ_REG(hw, IXGBE_EITR(0));
 521         regs_buff[25] = IXGBE_READ_REG(hw, IXGBE_IVAR(0));
 522         regs_buff[26] = IXGBE_READ_REG(hw, IXGBE_MSIXT);
 523         regs_buff[27] = IXGBE_READ_REG(hw, IXGBE_MSIXPBA);
 524         regs_buff[28] = IXGBE_READ_REG(hw, IXGBE_PBACL(0));
 525         regs_buff[29] = IXGBE_READ_REG(hw, IXGBE_GPIE);
 526
 527         /* Flow Control */
 528         regs_buff[30] = IXGBE_READ_REG(hw, IXGBE_PFCTOP);
 529         regs_buff[31] = IXGBE_READ_REG(hw, IXGBE_FCTTV(0));
 530         regs_buff[32] = IXGBE_READ_REG(hw, IXGBE_FCTTV(1));
 531         regs_buff[33] = IXGBE_READ_REG(hw, IXGBE_FCTTV(2));
 532         regs_buff[34] = IXGBE_READ_REG(hw, IXGBE_FCTTV(3));
 533         for (i = 0; i < 8; i++)
 534                 regs_buff[35 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTL(i));
 535         for (i = 0; i < 8; i++)
 536                 regs_buff[43 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTH(i));
 537         regs_buff[51] = IXGBE_READ_REG(hw, IXGBE_FCRTV);
 538         regs_buff[52] = IXGBE_READ_REG(hw, IXGBE_TFCS);
 539
 540         /* Receive DMA */
 541         for (i = 0; i < 64; i++)
 542                 regs_buff[53 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
 543         for (i = 0; i < 64; i++)
 544                 regs_buff[117 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
 545         for (i = 0; i < 64; i++)
 546                 regs_buff[181 + i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
 547         for (i = 0; i < 64; i++)
 548                 regs_buff[245 + i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
 549         for (i = 0; i < 64; i++)
 550                 regs_buff[309 + i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
 551         for (i = 0; i < 64; i++)
 552                 regs_buff[373 + i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
 553         for (i = 0; i < 16; i++)
 554                 regs_buff[437 + i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
 555         for (i = 0; i < 16; i++)
 556                 regs_buff[453 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
 557         regs_buff[469] = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
 558         for (i = 0; i < 8; i++)
 559                 regs_buff[470 + i] = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
 560         regs_buff[478] = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
 561         regs_buff[479] = IXGBE_READ_REG(hw, IXGBE_DROPEN);
 562
 563         /* Receive */
 564         regs_buff[480] = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
 565         regs_buff[481] = IXGBE_READ_REG(hw, IXGBE_RFCTL);
 566         for (i = 0; i < 16; i++)
 567                 regs_buff[482 + i] = IXGBE_READ_REG(hw, IXGBE_RAL(i));
 568         for (i = 0; i < 16; i++)
 569                 regs_buff[498 + i] = IXGBE_READ_REG(hw, IXGBE_RAH(i));
 570         regs_buff[514] = IXGBE_READ_REG(hw, IXGBE_PSRTYPE(0));
 571         regs_buff[515] = IXGBE_READ_REG(hw, IXGBE_FCTRL);
 572         regs_buff[516] = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
 573         regs_buff[517] = IXGBE_READ_REG(hw, IXGBE_MCSTCTRL);
 574         regs_buff[518] = IXGBE_READ_REG(hw, IXGBE_MRQC);
 575         regs_buff[519] = IXGBE_READ_REG(hw, IXGBE_VMD_CTL);
 576         for (i = 0; i < 8; i++)
 577                 regs_buff[520 + i] = IXGBE_READ_REG(hw, IXGBE_IMIR(i));
 578         for (i = 0; i < 8; i++)
 579                 regs_buff[528 + i] = IXGBE_READ_REG(hw, IXGBE_IMIREXT(i));
 580         regs_buff[536] = IXGBE_READ_REG(hw, IXGBE_IMIRVP);
 581
 582         /* Transmit */
 583         for (i = 0; i < 32; i++)
 584                 regs_buff[537 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
 585         for (i = 0; i < 32; i++)
 586                 regs_buff[569 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
 587         for (i = 0; i < 32; i++)
 588                 regs_buff[601 + i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
 589         for (i = 0; i < 32; i++)
 590                 regs_buff[633 + i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
 591         for (i = 0; i < 32; i++)
 592                 regs_buff[665 + i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
 593         for (i = 0; i < 32; i++)
 594                 regs_buff[697 + i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
 595         for (i = 0; i < 32; i++)
 596                 regs_buff[729 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAL(i));
 597         for (i = 0; i < 32; i++)
 598                 regs_buff[761 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAH(i));
 599         regs_buff[793] = IXGBE_READ_REG(hw, IXGBE_DTXCTL);
 600         for (i = 0; i < 16; i++)
 601                 regs_buff[794 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i));
 602         regs_buff[810] = IXGBE_READ_REG(hw, IXGBE_TIPG);
 603         for (i = 0; i < 8; i++)
 604                 regs_buff[811 + i] = IXGBE_READ_REG(hw, IXGBE_TXPBSIZE(i));
 605         regs_buff[819] = IXGBE_READ_REG(hw, IXGBE_MNGTXMAP);
 606
 607         /* Wake Up */
 608         regs_buff[820] = IXGBE_READ_REG(hw, IXGBE_WUC);
 609         regs_buff[821] = IXGBE_READ_REG(hw, IXGBE_WUFC);
 610         regs_buff[822] = IXGBE_READ_REG(hw, IXGBE_WUS);
 611         regs_buff[823] = IXGBE_READ_REG(hw, IXGBE_IPAV);
 612         regs_buff[824] = IXGBE_READ_REG(hw, IXGBE_IP4AT);
 613         regs_buff[825] = IXGBE_READ_REG(hw, IXGBE_IP6AT);
 614         regs_buff[826] = IXGBE_READ_REG(hw, IXGBE_WUPL);
 615         regs_buff[827] = IXGBE_READ_REG(hw, IXGBE_WUPM);
 616         regs_buff[828] = IXGBE_READ_REG(hw, IXGBE_FHFT(0));
 617
 618         regs_buff[829] = IXGBE_READ_REG(hw, IXGBE_RMCS);
 619         regs_buff[830] = IXGBE_READ_REG(hw, IXGBE_DPMCS);
 620         regs_buff[831] = IXGBE_READ_REG(hw, IXGBE_PDPMCS);
 621         regs_buff[832] = IXGBE_READ_REG(hw, IXGBE_RUPPBMR);
 622         for (i = 0; i < 8; i++)
 623                 regs_buff[833 + i] = IXGBE_READ_REG(hw, IXGBE_RT2CR(i));
 624         for (i = 0; i < 8; i++)
 625                 regs_buff[841 + i] = IXGBE_READ_REG(hw, IXGBE_RT2SR(i));
 626         for (i = 0; i < 8; i++)
 627                 regs_buff[849 + i] = IXGBE_READ_REG(hw, IXGBE_TDTQ2TCCR(i));
 628         for (i = 0; i < 8; i++)
 629                 regs_buff[857 + i] = IXGBE_READ_REG(hw, IXGBE_TDTQ2TCSR(i));
 630         for (i = 0; i < 8; i++)
 631                 regs_buff[865 + i] = IXGBE_READ_REG(hw, IXGBE_TDPT2TCCR(i));
 632         for (i = 0; i < 8; i++)
 633                 regs_buff[873 + i] = IXGBE_READ_REG(hw, IXGBE_TDPT2TCSR(i));
 634
 635         /* Statistics */
 636         regs_buff[881] = IXGBE_GET_STAT(adapter, crcerrs);
 637         regs_buff[882] = IXGBE_GET_STAT(adapter, illerrc);
 638         regs_buff[883] = IXGBE_GET_STAT(adapter, errbc);
 639         regs_buff[884] = IXGBE_GET_STAT(adapter, mspdc);
 640         for (i = 0; i < 8; i++)
 641                 regs_buff[885 + i] = IXGBE_GET_STAT(adapter, mpc[i]);
 642         regs_buff[893] = IXGBE_GET_STAT(adapter, mlfc);
 643         regs_buff[894] = IXGBE_GET_STAT(adapter, mrfc);
 644         regs_buff[895] = IXGBE_GET_STAT(adapter, rlec);
 645         regs_buff[896] = IXGBE_GET_STAT(adapter, lxontxc);
 646         regs_buff[897] = IXGBE_GET_STAT(adapter, lxonrxc);
 647         regs_buff[898] = IXGBE_GET_STAT(adapter, lxofftxc);
 648         regs_buff[899] = IXGBE_GET_STAT(adapter, lxoffrxc);
 649         for (i = 0; i < 8; i++)
 650                 regs_buff[900 + i] = IXGBE_GET_STAT(adapter, pxontxc[i]);
 651         for (i = 0; i < 8; i++)
 652                 regs_buff[908 + i] = IXGBE_GET_STAT(adapter, pxonrxc[i]);
 653         for (i = 0; i < 8; i++)
 654                 regs_buff[916 + i] = IXGBE_GET_STAT(adapter, pxofftxc[i]);
 655         for (i = 0; i < 8; i++)
 656                 regs_buff[924 + i] = IXGBE_GET_STAT(adapter, pxoffrxc[i]);
 657         regs_buff[932] = IXGBE_GET_STAT(adapter, prc64);
 658         regs_buff[933] = IXGBE_GET_STAT(adapter, prc127);
 659         regs_buff[934] = IXGBE_GET_STAT(adapter, prc255);
 660         regs_buff[935] = IXGBE_GET_STAT(adapter, prc511);
 661         regs_buff[936] = IXGBE_GET_STAT(adapter, prc1023);
 662         regs_buff[937] = IXGBE_GET_STAT(adapter, prc1522);
 663         regs_buff[938] = IXGBE_GET_STAT(adapter, gprc);
 664         regs_buff[939] = IXGBE_GET_STAT(adapter, bprc);
 665         regs_buff[940] = IXGBE_GET_STAT(adapter, mprc);
 666         regs_buff[941] = IXGBE_GET_STAT(adapter, gptc);
 667         regs_buff[942] = IXGBE_GET_STAT(adapter, gorc);
 668         regs_buff[944] = IXGBE_GET_STAT(adapter, gotc);
 669         for (i = 0; i < 8; i++)
 670                 regs_buff[946 + i] = IXGBE_GET_STAT(adapter, rnbc[i]);
 671         regs_buff[954] = IXGBE_GET_STAT(adapter, ruc);
 672         regs_buff[955] = IXGBE_GET_STAT(adapter, rfc);
 673         regs_buff[956] = IXGBE_GET_STAT(adapter, roc);
 674         regs_buff[957] = IXGBE_GET_STAT(adapter, rjc);
 675         regs_buff[958] = IXGBE_GET_STAT(adapter, mngprc);
 676         regs_buff[959] = IXGBE_GET_STAT(adapter, mngpdc);
 677         regs_buff[960] = IXGBE_GET_STAT(adapter, mngptc);
 678         regs_buff[961] = IXGBE_GET_STAT(adapter, tor);
 679         regs_buff[963] = IXGBE_GET_STAT(adapter, tpr);
 680         regs_buff[964] = IXGBE_GET_STAT(adapter, tpt);
 681         regs_buff[965] = IXGBE_GET_STAT(adapter, ptc64);
 682         regs_buff[966] = IXGBE_GET_STAT(adapter, ptc127);
 683         regs_buff[967] = IXGBE_GET_STAT(adapter, ptc255);
 684         regs_buff[968] = IXGBE_GET_STAT(adapter, ptc511);
 685         regs_buff[969] = IXGBE_GET_STAT(adapter, ptc1023);
 686         regs_buff[970] = IXGBE_GET_STAT(adapter, ptc1522);
 687         regs_buff[971] = IXGBE_GET_STAT(adapter, mptc);
 688         regs_buff[972] = IXGBE_GET_STAT(adapter, bptc);
 689         regs_buff[973] = IXGBE_GET_STAT(adapter, xec);
 690         for (i = 0; i < 16; i++)
 691                 regs_buff[974 + i] = IXGBE_GET_STAT(adapter, qprc[i]);
 692         for (i = 0; i < 16; i++)
 693                 regs_buff[990 + i] = IXGBE_GET_STAT(adapter, qptc[i]);
 694         for (i = 0; i < 16; i++)
 695                 regs_buff[1006 + i] = IXGBE_GET_STAT(adapter, qbrc[i]);
 696         for (i = 0; i < 16; i++)
 697                 regs_buff[1022 + i] = IXGBE_GET_STAT(adapter, qbtc[i]);
 698
 699         /* MAC */
 700         regs_buff[1038] = IXGBE_READ_REG(hw, IXGBE_PCS1GCFIG);
 701         regs_buff[1039] = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
 702         regs_buff[1040] = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
 703         regs_buff[1041] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG0);
 704         regs_buff[1042] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG1);
 705         regs_buff[1043] = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
 706         regs_buff[1044] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
 707         regs_buff[1045] = IXGBE_READ_REG(hw, IXGBE_PCS1GANNP);
 708         regs_buff[1046] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLPNP);
 709         regs_buff[1047] = IXGBE_READ_REG(hw, IXGBE_HLREG0);
 710         regs_buff[1048] = IXGBE_READ_REG(hw, IXGBE_HLREG1);
 711         regs_buff[1049] = IXGBE_READ_REG(hw, IXGBE_PAP);
 712         regs_buff[1050] = IXGBE_READ_REG(hw, IXGBE_MACA);
 713         regs_buff[1051] = IXGBE_READ_REG(hw, IXGBE_APAE);
 714         regs_buff[1052] = IXGBE_READ_REG(hw, IXGBE_ARD);
 715         regs_buff[1053] = IXGBE_READ_REG(hw, IXGBE_AIS);
 716         regs_buff[1054] = IXGBE_READ_REG(hw, IXGBE_MSCA);
 717         regs_buff[1055] = IXGBE_READ_REG(hw, IXGBE_MSRWD);
 718         regs_buff[1056] = IXGBE_READ_REG(hw, IXGBE_MLADD);
 719         regs_buff[1057] = IXGBE_READ_REG(hw, IXGBE_MHADD);
 720         regs_buff[1058] = IXGBE_READ_REG(hw, IXGBE_TREG);
 721         regs_buff[1059] = IXGBE_READ_REG(hw, IXGBE_PCSS1);
 722         regs_buff[1060] = IXGBE_READ_REG(hw, IXGBE_PCSS2);
 723         regs_buff[1061] = IXGBE_READ_REG(hw, IXGBE_XPCSS);
 724         regs_buff[1062] = IXGBE_READ_REG(hw, IXGBE_SERDESC);
 725         regs_buff[1063] = IXGBE_READ_REG(hw, IXGBE_MACS);
 726         regs_buff[1064] = IXGBE_READ_REG(hw, IXGBE_AUTOC);
 727         regs_buff[1065] = IXGBE_READ_REG(hw, IXGBE_LINKS);
 728         regs_buff[1066] = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
 729         regs_buff[1067] = IXGBE_READ_REG(hw, IXGBE_AUTOC3);
 730         regs_buff[1068] = IXGBE_READ_REG(hw, IXGBE_ANLP1);
 731         regs_buff[1069] = IXGBE_READ_REG(hw, IXGBE_ANLP2);
 732         regs_buff[1070] = IXGBE_READ_REG(hw, IXGBE_ATLASCTL);
 733
 734         /* Diagnostic */
 735         regs_buff[1071] = IXGBE_READ_REG(hw, IXGBE_RDSTATCTL);
 736         for (i = 0; i < 8; i++)
 737                 regs_buff[1072 + i] = IXGBE_READ_REG(hw, IXGBE_RDSTAT(i));
 738         regs_buff[1080] = IXGBE_READ_REG(hw, IXGBE_RDHMPN);
 739         for (i = 0; i < 4; i++)
 740                 regs_buff[1081 + i] = IXGBE_READ_REG(hw, IXGBE_RIC_DW(i));
 741         regs_buff[1085] = IXGBE_READ_REG(hw, IXGBE_RDPROBE);
 742         regs_buff[1086] = IXGBE_READ_REG(hw, IXGBE_TDSTATCTL);
 743         for (i = 0; i < 8; i++)
 744                 regs_buff[1087 + i] = IXGBE_READ_REG(hw, IXGBE_TDSTAT(i));
 745         regs_buff[1095] = IXGBE_READ_REG(hw, IXGBE_TDHMPN);
 746         for (i = 0; i < 4; i++)
 747                 regs_buff[1096 + i] = IXGBE_READ_REG(hw, IXGBE_TIC_DW(i));
 748         regs_buff[1100] = IXGBE_READ_REG(hw, IXGBE_TDPROBE);
 749         regs_buff[1101] = IXGBE_READ_REG(hw, IXGBE_TXBUFCTRL);
 750         regs_buff[1102] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA0);
 751         regs_buff[1103] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA1);
 752         regs_buff[1104] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA2);
 753         regs_buff[1105] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA3);
 754         regs_buff[1106] = IXGBE_READ_REG(hw, IXGBE_RXBUFCTRL);
 755         regs_buff[1107] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA0);
 756         regs_buff[1108] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA1);
 757         regs_buff[1109] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA2);
 758         regs_buff[1110] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA3);
 759         for (i = 0; i < 8; i++)
 760                 regs_buff[1111 + i] = IXGBE_READ_REG(hw, IXGBE_PCIE_DIAG(i));
 761         regs_buff[1119] = IXGBE_READ_REG(hw, IXGBE_RFVAL);
 762         regs_buff[1120] = IXGBE_READ_REG(hw, IXGBE_MDFTC1);
 763         regs_buff[1121] = IXGBE_READ_REG(hw, IXGBE_MDFTC2);
 764         regs_buff[1122] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO1);
 765         regs_buff[1123] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO2);
 766         regs_buff[1124] = IXGBE_READ_REG(hw, IXGBE_MDFTS);
 767         regs_buff[1125] = IXGBE_READ_REG(hw, IXGBE_PCIEECCCTL);
 768         regs_buff[1126] = IXGBE_READ_REG(hw, IXGBE_PBTXECC);
 769         regs_buff[1127] = IXGBE_READ_REG(hw, IXGBE_PBRXECC);
 770 }
 771
 772 static int ixgbe_get_eeprom_len(struct net_device *netdev)
 773 {
 774         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 775         return adapter->hw.eeprom.word_size * 2;
 776 }
 777
 778 static int ixgbe_get_eeprom(struct net_device *netdev,
 779                             struct ethtool_eeprom *eeprom, u8 *bytes)
 780 {
 781         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 782         struct ixgbe_hw *hw = &adapter->hw;
 783         u16 *eeprom_buff;
 784         int first_word, last_word, eeprom_len;
 785         int ret_val = 0;
 786         u16 i;
 787
 788         if (eeprom->len == 0)
 789                 return -EINVAL;
 790
 791         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
 792
 793         first_word = eeprom->offset >> 1;
 794         last_word = (eeprom->offset + eeprom->len - 1) >> 1;
 795         eeprom_len = last_word - first_word + 1;
 796
 797         eeprom_buff = kmalloc(sizeof(u16) * eeprom_len, GFP_KERNEL);
 798         if (!eeprom_buff)
 799                 return -ENOMEM;
 800
 801         for (i = 0; i < eeprom_len; i++) {
 802                 if ((ret_val = hw->eeprom.ops.read(hw, first_word + i,
 803                     &eeprom_buff[i])))
 804                         break;
 805         }
 806
 807         /* Device's eeprom is always little-endian, word addressable */
 808         for (i = 0; i < eeprom_len; i++)
 809                 le16_to_cpus(&eeprom_buff[i]);
 810
 811         memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1), eeprom->len);
 812         kfree(eeprom_buff);
 813
 814         return ret_val;
 815 }
 816
 817 static void ixgbe_get_drvinfo(struct net_device *netdev,
 818                               struct ethtool_drvinfo *drvinfo)
 819 {
 820         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 821         char firmware_version[32];
 822
 823         strncpy(drvinfo->driver, ixgbe_driver_name, 32);
 824         strncpy(drvinfo->version, ixgbe_driver_version, 32);
 825
 826         sprintf(firmware_version, "%d.%d-%d",
 827                 (adapter->eeprom_version & 0xF000) >> 12,
 828                 (adapter->eeprom_version & 0x0FF0) >> 4,
 829                 adapter->eeprom_version & 0x000F);
 830
 831         strncpy(drvinfo->fw_version, firmware_version, 32);
 832         strncpy(drvinfo->bus_info, pci_name(adapter->pdev), 32);
 833         drvinfo->n_stats = IXGBE_STATS_LEN;
 834         drvinfo->testinfo_len = IXGBE_TEST_LEN;
 835         drvinfo->regdump_len = ixgbe_get_regs_len(netdev);
 836 }
 837
 838 static void ixgbe_get_ringparam(struct net_device *netdev,
 839                                 struct ethtool_ringparam *ring)
 840 {
 841         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 842         struct ixgbe_ring *tx_ring = adapter->tx_ring;
 843         struct ixgbe_ring *rx_ring = adapter->rx_ring;
 844
 845         ring->rx_max_pending = IXGBE_MAX_RXD;
 846         ring->tx_max_pending = IXGBE_MAX_TXD;
 847         ring->rx_mini_max_pending = 0;
 848         ring->rx_jumbo_max_pending = 0;
 849         ring->rx_pending = rx_ring->count;
 850         ring->tx_pending = tx_ring->count;
 851         ring->rx_mini_pending = 0;
 852         ring->rx_jumbo_pending = 0;
 853 }
 854
 855 static int ixgbe_set_ringparam(struct net_device *netdev,
 856                                struct ethtool_ringparam *ring)
 857 {
 858         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 859         struct ixgbe_ring *temp_tx_ring, *temp_rx_ring;
 860         int i, err = 0;
 861         u32 new_rx_count, new_tx_count;
 862         bool need_update = false;
 863
 864         if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
 865                 return -EINVAL;
 866
 867         new_rx_count = max(ring->rx_pending, (u32)IXGBE_MIN_RXD);
 868         new_rx_count = min(new_rx_count, (u32)IXGBE_MAX_RXD);
 869         new_rx_count = ALIGN(new_rx_count, IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE);
 870
 871         new_tx_count = max(ring->tx_pending, (u32)IXGBE_MIN_TXD);
 872         new_tx_count = min(new_tx_count, (u32)IXGBE_MAX_TXD);
 873         new_tx_count = ALIGN(new_tx_count, IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE);
 874
 875         if ((new_tx_count == adapter->tx_ring->count) &&
 876             (new_rx_count == adapter->rx_ring->count)) {
 877                 /* nothing to do */
 878                 return 0;
 879         }
 880
 881         while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
 882                 msleep(1);
 883
 884         if (!netif_running(adapter->netdev)) {
 885                 for (i = 0; i < adapter->num_tx_queues; i++)
 886                         adapter->tx_ring[i].count = new_tx_count;
 887                 for (i = 0; i < adapter->num_rx_queues; i++)
 888                         adapter->rx_ring[i].count = new_rx_count;
 889                 adapter->tx_ring_count = new_tx_count;
 890                 adapter->rx_ring_count = new_rx_count;
 891                 goto err_setup;
 892         }
 893
 894         temp_tx_ring = kcalloc(adapter->num_tx_queues,
 895                                sizeof(struct ixgbe_ring), GFP_KERNEL);
 896         if (!temp_tx_ring) {
 897                 err = -ENOMEM;
 898                 goto err_setup;
 899         }
 900
 901         if (new_tx_count != adapter->tx_ring_count) {
 902                 memcpy(temp_tx_ring, adapter->tx_ring,
 903                        adapter->num_tx_queues * sizeof(struct ixgbe_ring));
 904                 for (i = 0; i < adapter->num_tx_queues; i++) {
 905                         temp_tx_ring[i].count = new_tx_count;
 906                         err = ixgbe_setup_tx_resources(adapter,
 907                                                        &temp_tx_ring[i]);
 908                         if (err) {
 909                                 while (i) {
 910                                         i--;
 911                                         ixgbe_free_tx_resources(adapter,
 912                                                                 &temp_tx_ring[i]);
 913                                 }
 914                                 goto err_setup;
 915                         }
 916                 }
 917                 need_update = true;
 918         }
 919
 920         temp_rx_ring = kcalloc(adapter->num_rx_queues,
 921                                sizeof(struct ixgbe_ring), GFP_KERNEL);
 922         if ((!temp_rx_ring) && (need_update)) {
 923                 for (i = 0; i < adapter->num_tx_queues; i++)
 924                         ixgbe_free_tx_resources(adapter, &temp_tx_ring[i]);
 925                 kfree(temp_tx_ring);
 926                 err = -ENOMEM;
 927                 goto err_setup;
 928         }
 929
 930         if (new_rx_count != adapter->rx_ring_count) {
 931                 memcpy(temp_rx_ring, adapter->rx_ring,
 932                        adapter->num_rx_queues * sizeof(struct ixgbe_ring));
 933                 for (i = 0; i < adapter->num_rx_queues; i++) {
 934                         temp_rx_ring[i].count = new_rx_count;
 935                         err = ixgbe_setup_rx_resources(adapter,
 936                                                        &temp_rx_ring[i]);
 937                         if (err) {
 938                                 while (i) {
 939                                         i--;
 940                                         ixgbe_free_rx_resources(adapter,
 941                                                               &temp_rx_ring[i]);
 942                                 }
 943                                 goto err_setup;
 944                         }
 945                 }
 946                 need_update = true;
 947         }
 948
 949         /* if rings need to be updated, here's the place to do it in one shot */
 950         if (need_update) {
 951                 ixgbe_down(adapter);
 952
 953                 /* tx */
 954                 if (new_tx_count != adapter->tx_ring_count) {
 955                         kfree(adapter->tx_ring);
 956                         adapter->tx_ring = temp_tx_ring;
 957                         temp_tx_ring = NULL;
 958                         adapter->tx_ring_count = new_tx_count;
 959                 }
 960
 961                 /* rx */
 962                 if (new_rx_count != adapter->rx_ring_count) {
 963                         kfree(adapter->rx_ring);
 964                         adapter->rx_ring = temp_rx_ring;
 965                         temp_rx_ring = NULL;
 966                         adapter->rx_ring_count = new_rx_count;
 967                 }
 968                 ixgbe_up(adapter);
 969         }
 970 err_setup:
 971         clear_bit(__IXGBE_RESETTING, &adapter->state);
 972         return err;
 973 }
 974
 975 static int ixgbe_get_sset_count(struct net_device *netdev, int sset)
 976 {
 977         switch (sset) {
 978         case ETH_SS_TEST:
 979                 return IXGBE_TEST_LEN;
 980         case ETH_SS_STATS:
 981                 return IXGBE_STATS_LEN;
 982         default:
 983                 return -EOPNOTSUPP;
 984         }
 985 }
 986
 987 static void ixgbe_get_ethtool_stats(struct net_device *netdev,
 988                                     struct ethtool_stats *stats, u64 *data)
 989 {
 990         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 991         u64 *queue_stat;
 992         int stat_count = sizeof(struct ixgbe_queue_stats) / sizeof(u64);
 993         int j, k;
 994         int i;
 995         char *p = NULL;
 996
 997         ixgbe_update_stats(adapter);
 998         for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) {
 999                 switch (ixgbe_gstrings_stats[i].type) {
1000                 case NETDEV_STATS:
1001                         p = (char *) netdev +
1002                                         ixgbe_gstrings_stats[i].stat_offset;
1003                         break;
1004                 case IXGBE_STATS:
1005                         p = (char *) adapter +
1006                                         ixgbe_gstrings_stats[i].stat_offset;
1007                         break;
1008                 }
1009
1010                 data[i] = (ixgbe_gstrings_stats[i].sizeof_stat ==
1011                            sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
1012         }
1013         for (j = 0; j < adapter->num_tx_queues; j++) {
1014                 queue_stat = (u64 *)&adapter->tx_ring[j].stats;
1015                 for (k = 0; k < stat_count; k++)
1016                         data[i + k] = queue_stat[k];
1017                 i += k;
1018         }
1019         for (j = 0; j < adapter->num_rx_queues; j++) {
1020                 queue_stat = (u64 *)&adapter->rx_ring[j].stats;
1021                 for (k = 0; k < stat_count; k++)
1022                         data[i + k] = queue_stat[k];
1023                 i += k;
1024         }
1025         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
1026                 for (j = 0; j < MAX_TX_PACKET_BUFFERS; j++) {
1027                         data[i++] = adapter->stats.pxontxc[j];
1028                         data[i++] = adapter->stats.pxofftxc[j];
1029                 }
1030                 for (j = 0; j < MAX_RX_PACKET_BUFFERS; j++) {
1031                         data[i++] = adapter->stats.pxonrxc[j];
1032                         data[i++] = adapter->stats.pxoffrxc[j];
1033                 }
1034         }
1035 }
1036
1037 static void ixgbe_get_strings(struct net_device *netdev, u32 stringset,
1038                               u8 *data)
1039 {
1040         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1041         char *p = (char *)data;
1042         int i;
1043
1044         switch (stringset) {
1045         case ETH_SS_TEST:
1046                 memcpy(data, *ixgbe_gstrings_test,
1047                        IXGBE_TEST_LEN * ETH_GSTRING_LEN);
1048                 break;
1049         case ETH_SS_STATS:
1050                 for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) {
1051                         memcpy(p, ixgbe_gstrings_stats[i].stat_string,
1052                                ETH_GSTRING_LEN);
1053                         p += ETH_GSTRING_LEN;
1054                 }
1055                 for (i = 0; i < adapter->num_tx_queues; i++) {
1056                         sprintf(p, "tx_queue_%u_packets", i);
1057                         p += ETH_GSTRING_LEN;
1058                         sprintf(p, "tx_queue_%u_bytes", i);
1059                         p += ETH_GSTRING_LEN;
1060                 }
1061                 for (i = 0; i < adapter->num_rx_queues; i++) {
1062                         sprintf(p, "rx_queue_%u_packets", i);
1063                         p += ETH_GSTRING_LEN;
1064                         sprintf(p, "rx_queue_%u_bytes", i);
1065                         p += ETH_GSTRING_LEN;
1066                 }
1067                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
1068                         for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
1069                                 sprintf(p, "tx_pb_%u_pxon", i);
1070                                 p += ETH_GSTRING_LEN;
1071                                 sprintf(p, "tx_pb_%u_pxoff", i);
1072                                 p += ETH_GSTRING_LEN;
1073                         }
1074                         for (i = 0; i < MAX_RX_PACKET_BUFFERS; i++) {
1075                                 sprintf(p, "rx_pb_%u_pxon", i);
1076                                 p += ETH_GSTRING_LEN;
1077                                 sprintf(p, "rx_pb_%u_pxoff", i);
1078                                 p += ETH_GSTRING_LEN;
1079                         }
1080                 }
1081                 /* BUG_ON(p - data != IXGBE_STATS_LEN * ETH_GSTRING_LEN); */
1082                 break;
1083         }
1084 }
1085
1086 static int ixgbe_link_test(struct ixgbe_adapter *adapter, u64 *data)
1087 {
1088         struct ixgbe_hw *hw = &adapter->hw;
1089         bool link_up;
1090         u32 link_speed = 0;
1091         *data = 0;
1092
1093         hw->mac.ops.check_link(hw, &link_speed, &link_up, true);
1094         if (link_up)
1095                 return *data;
1096         else
1097                 *data = 1;
1098         return *data;
1099 }
1100
1101 /* ethtool register test data */
1102 struct ixgbe_reg_test {
1103         u16 reg;
1104         u8  array_len;
1105         u8  test_type;
1106         u32 mask;
1107         u32 write;
1108 };
1109
1110 /* In the hardware, registers are laid out either singly, in arrays
1111  * spaced 0x40 bytes apart, or in contiguous tables.  We assume
1112  * most tests take place on arrays or single registers (handled
1113  * as a single-element array) and special-case the tables.
1114  * Table tests are always pattern tests.
1115  *
1116  * We also make provision for some required setup steps by specifying
1117  * registers to be written without any read-back testing.
1118  */
1119
1120 #define PATTERN_TEST    1
1121 #define SET_READ_TEST   2
1122 #define WRITE_NO_TEST   3
1123 #define TABLE32_TEST    4
1124 #define TABLE64_TEST_LO 5
1125 #define TABLE64_TEST_HI 6
1126
1127 /* default 82599 register test */
1128 static struct ixgbe_reg_test reg_test_82599[] = {
1129         { IXGBE_FCRTL_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1130         { IXGBE_FCRTH_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1131         { IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1132         { IXGBE_VLNCTRL, 1, PATTERN_TEST, 0x00000000, 0x00000000 },
1133         { IXGBE_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFF80 },
1134         { IXGBE_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1135         { IXGBE_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1136         { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE },
1137         { IXGBE_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1138         { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 },
1139         { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1140         { IXGBE_FCTTV(0), 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1141         { IXGBE_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1142         { IXGBE_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1143         { IXGBE_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFF80 },
1144         { IXGBE_RXCTRL, 1, SET_READ_TEST, 0x00000001, 0x00000001 },
1145         { IXGBE_RAL(0), 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1146         { IXGBE_RAL(0), 16, TABLE64_TEST_HI, 0x8001FFFF, 0x800CFFFF },
1147         { IXGBE_MTA(0), 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1148         { 0, 0, 0, 0 }
1149 };
1150
1151 /* default 82598 register test */
1152 static struct ixgbe_reg_test reg_test_82598[] = {
1153         { IXGBE_FCRTL(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1154         { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1155         { IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1156         { IXGBE_VLNCTRL, 1, PATTERN_TEST, 0x00000000, 0x00000000 },
1157         { IXGBE_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1158         { IXGBE_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1159         { IXGBE_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1160         /* Enable all four RX queues before testing. */
1161         { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE },
1162         /* RDH is read-only for 82598, only test RDT. */
1163         { IXGBE_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1164         { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 },
1165         { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1166         { IXGBE_FCTTV(0), 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1167         { IXGBE_TIPG, 1, PATTERN_TEST, 0x000000FF, 0x000000FF },
1168         { IXGBE_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1169         { IXGBE_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1170         { IXGBE_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1171         { IXGBE_RXCTRL, 1, SET_READ_TEST, 0x00000003, 0x00000003 },
1172         { IXGBE_DTXCTL, 1, SET_READ_TEST, 0x00000005, 0x00000005 },
1173         { IXGBE_RAL(0), 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1174         { IXGBE_RAL(0), 16, TABLE64_TEST_HI, 0x800CFFFF, 0x800CFFFF },
1175         { IXGBE_MTA(0), 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1176         { 0, 0, 0, 0 }
1177 };
1178
1179 #define REG_PATTERN_TEST(R, M, W)                                             \
1180 {                                                                             \
1181         u32 pat, val, before;                                                 \
1182         const u32 _test[] = {0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF}; \
1183         for (pat = 0; pat < ARRAY_SIZE(_test); pat++) {                       \
1184                 before = readl(adapter->hw.hw_addr + R);                      \
1185                 writel((_test[pat] & W), (adapter->hw.hw_addr + R));          \
1186                 val = readl(adapter->hw.hw_addr + R);                         \
1187                 if (val != (_test[pat] & W & M)) {                            \
1188                         DPRINTK(DRV, ERR, "pattern test reg %04X failed: got "\
1189                                           "0x%08X expected 0x%08X\n",         \
1190                                 R, val, (_test[pat] & W & M));                \
1191                         *data = R;                                            \
1192                         writel(before, adapter->hw.hw_addr + R);              \
1193                         return 1;                                             \
1194                 }                                                             \
1195                 writel(before, adapter->hw.hw_addr + R);                      \
1196         }                                                                     \
1197 }
1198
1199 #define REG_SET_AND_CHECK(R, M, W)                                            \
1200 {                                                                             \
1201         u32 val, before;                                                      \
1202         before = readl(adapter->hw.hw_addr + R);                              \
1203         writel((W & M), (adapter->hw.hw_addr + R));                           \
1204         val = readl(adapter->hw.hw_addr + R);                                 \
1205         if ((W & M) != (val & M)) {                                           \
1206                 DPRINTK(DRV, ERR, "set/check reg %04X test failed: got 0x%08X "\
1207                                  "expected 0x%08X\n", R, (val & M), (W & M)); \
1208                 *data = R;                                                    \
1209                 writel(before, (adapter->hw.hw_addr + R));                    \
1210                 return 1;                                                     \
1211         }                                                                     \
1212         writel(before, (adapter->hw.hw_addr + R));                            \
1213 }
1214
1215 static int ixgbe_reg_test(struct ixgbe_adapter *adapter, u64 *data)
1216 {
1217         struct ixgbe_reg_test *test;
1218         u32 value, before, after;
1219         u32 i, toggle;
1220
1221         if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1222                 toggle = 0x7FFFF30F;
1223                 test = reg_test_82599;
1224         } else {
1225                 toggle = 0x7FFFF3FF;
1226                 test = reg_test_82598;
1227         }
1228
1229         /*
1230          * Because the status register is such a special case,
1231          * we handle it separately from the rest of the register
1232          * tests.  Some bits are read-only, some toggle, and some
1233          * are writeable on newer MACs.
1234          */
1235         before = IXGBE_READ_REG(&adapter->hw, IXGBE_STATUS);
1236         value = (IXGBE_READ_REG(&adapter->hw, IXGBE_STATUS) & toggle);
1237         IXGBE_WRITE_REG(&adapter->hw, IXGBE_STATUS, toggle);
1238         after = IXGBE_READ_REG(&adapter->hw, IXGBE_STATUS) & toggle;
1239         if (value != after) {
1240                 DPRINTK(DRV, ERR, "failed STATUS register test got: "
1241                         "0x%08X expected: 0x%08X\n", after, value);
1242                 *data = 1;
1243                 return 1;
1244         }
1245         /* restore previous status */
1246         IXGBE_WRITE_REG(&adapter->hw, IXGBE_STATUS, before);
1247
1248         /*
1249          * Perform the remainder of the register test, looping through
1250          * the test table until we either fail or reach the null entry.
1251          */
1252         while (test->reg) {
1253                 for (i = 0; i < test->array_len; i++) {
1254                         switch (test->test_type) {
1255                         case PATTERN_TEST:
1256                                 REG_PATTERN_TEST(test->reg + (i * 0x40),
1257                                                 test->mask,
1258                                                 test->write);
1259                                 break;
1260                         case SET_READ_TEST:
1261                                 REG_SET_AND_CHECK(test->reg + (i * 0x40),
1262                                                 test->mask,
1263                                                 test->write);
1264                                 break;
1265                         case WRITE_NO_TEST:
1266                                 writel(test->write,
1267                                        (adapter->hw.hw_addr + test->reg)
1268                                        + (i * 0x40));
1269                                 break;
1270                         case TABLE32_TEST:
1271                                 REG_PATTERN_TEST(test->reg + (i * 4),
1272                                                 test->mask,
1273                                                 test->write);
1274                                 break;
1275                         case TABLE64_TEST_LO:
1276                                 REG_PATTERN_TEST(test->reg + (i * 8),
1277                                                 test->mask,
1278                                                 test->write);
1279                                 break;
1280                         case TABLE64_TEST_HI:
1281                                 REG_PATTERN_TEST((test->reg + 4) + (i * 8),
1282                                                 test->mask,
1283                                                 test->write);
1284                                 break;
1285                         }
1286                 }
1287                 test++;
1288         }
1289
1290         *data = 0;
1291         return 0;
1292 }
1293
1294 static int ixgbe_eeprom_test(struct ixgbe_adapter *adapter, u64 *data)
1295 {
1296         struct ixgbe_hw *hw = &adapter->hw;
1297         if (hw->eeprom.ops.validate_checksum(hw, NULL))
1298                 *data = 1;
1299         else
1300                 *data = 0;
1301         return *data;
1302 }
1303
1304 static irqreturn_t ixgbe_test_intr(int irq, void *data)
1305 {
1306         struct net_device *netdev = (struct net_device *) data;
1307         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1308
1309         adapter->test_icr |= IXGBE_READ_REG(&adapter->hw, IXGBE_EICR);
1310
1311         return IRQ_HANDLED;
1312 }
1313
1314 static int ixgbe_intr_test(struct ixgbe_adapter *adapter, u64 *data)
1315 {
1316         struct net_device *netdev = adapter->netdev;
1317         u32 mask, i = 0, shared_int = true;
1318         u32 irq = adapter->pdev->irq;
1319
1320         *data = 0;
1321
1322         /* Hook up test interrupt handler just for this test */
1323         if (adapter->msix_entries) {
1324                 /* NOTE: we don't test MSI-X interrupts here, yet */
1325                 return 0;
1326         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1327                 shared_int = false;
1328                 if (request_irq(irq, ixgbe_test_intr, 0, netdev->name,
1329                                 netdev)) {
1330                         *data = 1;
1331                         return -1;
1332                 }
1333         } else if (!request_irq(irq, ixgbe_test_intr, IRQF_PROBE_SHARED,
1334                                 netdev->name, netdev)) {
1335                 shared_int = false;
1336         } else if (request_irq(irq, ixgbe_test_intr, IRQF_SHARED,
1337                                netdev->name, netdev)) {
1338                 *data = 1;
1339                 return -1;
1340         }
1341         DPRINTK(HW, INFO, "testing %s interrupt\n",
1342                 (shared_int ? "shared" : "unshared"));
1343
1344         /* Disable all the interrupts */
1345         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF);
1346         msleep(10);
1347
1348         /* Test each interrupt */
1349         for (; i < 10; i++) {
1350                 /* Interrupt to test */
1351                 mask = 1 << i;
1352
1353                 if (!shared_int) {
1354                         /*
1355                          * Disable the interrupts to be reported in
1356                          * the cause register and then force the same
1357                          * interrupt and see if one gets posted.  If
1358                          * an interrupt was posted to the bus, the
1359                          * test failed.
1360                          */
1361                         adapter->test_icr = 0;
1362                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC,
1363                                         ~mask & 0x00007FFF);
1364                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
1365                                         ~mask & 0x00007FFF);
1366                         msleep(10);
1367
1368                         if (adapter->test_icr & mask) {
1369                                 *data = 3;
1370                                 break;
1371                         }
1372                 }
1373
1374                 /*
1375                  * Enable the interrupt to be reported in the cause
1376                  * register and then force the same interrupt and see
1377                  * if one gets posted.  If an interrupt was not posted
1378                  * to the bus, the test failed.
1379                  */
1380                 adapter->test_icr = 0;
1381                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1382                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
1383                 msleep(10);
1384
1385                 if (!(adapter->test_icr &mask)) {
1386                         *data = 4;
1387                         break;
1388                 }
1389
1390                 if (!shared_int) {
1391                         /*
1392                          * Disable the other interrupts to be reported in
1393                          * the cause register and then force the other
1394                          * interrupts and see if any get posted.  If
1395                          * an interrupt was posted to the bus, the
1396                          * test failed.
1397                          */
1398                         adapter->test_icr = 0;
1399                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC,
1400                                         ~mask & 0x00007FFF);
1401                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
1402                                         ~mask & 0x00007FFF);
1403                         msleep(10);
1404
1405                         if (adapter->test_icr) {
1406                                 *data = 5;
1407                                 break;
1408                         }
1409                 }
1410         }
1411
1412         /* Disable all the interrupts */
1413         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF);
1414         msleep(10);
1415
1416         /* Unhook test interrupt handler */
1417         free_irq(irq, netdev);
1418
1419         return *data;
1420 }
1421
1422 static void ixgbe_free_desc_rings(struct ixgbe_adapter *adapter)
1423 {
1424         struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
1425         struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
1426         struct ixgbe_hw *hw = &adapter->hw;
1427         struct pci_dev *pdev = adapter->pdev;
1428         u32 reg_ctl;
1429         int i;
1430
1431         /* shut down the DMA engines now so they can be reinitialized later */
1432
1433         /* first Rx */
1434         reg_ctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1435         reg_ctl &= ~IXGBE_RXCTRL_RXEN;
1436         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg_ctl);
1437         reg_ctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(0));
1438         reg_ctl &= ~IXGBE_RXDCTL_ENABLE;
1439         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(0), reg_ctl);
1440
1441         /* now Tx */
1442         reg_ctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(0));
1443         reg_ctl &= ~IXGBE_TXDCTL_ENABLE;
1444         IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(0), reg_ctl);
1445         if (hw->mac.type == ixgbe_mac_82599EB) {
1446                 reg_ctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1447                 reg_ctl &= ~IXGBE_DMATXCTL_TE;
1448                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg_ctl);
1449         }
1450
1451         ixgbe_reset(adapter);
1452
1453         if (tx_ring->desc && tx_ring->tx_buffer_info) {
1454                 for (i = 0; i < tx_ring->count; i++) {
1455                         struct ixgbe_tx_buffer *buf =
1456                                         &(tx_ring->tx_buffer_info[i]);
1457                         if (buf->dma)
1458                                 pci_unmap_single(pdev, buf->dma, buf->length,
1459                                                  PCI_DMA_TODEVICE);
1460                         if (buf->skb)
1461                                 dev_kfree_skb(buf->skb);
1462                 }
1463         }
1464
1465         if (rx_ring->desc && rx_ring->rx_buffer_info) {
1466                 for (i = 0; i < rx_ring->count; i++) {
1467                         struct ixgbe_rx_buffer *buf =
1468                                         &(rx_ring->rx_buffer_info[i]);
1469                         if (buf->dma)
1470                                 pci_unmap_single(pdev, buf->dma,
1471                                                  IXGBE_RXBUFFER_2048,
1472                                                  PCI_DMA_FROMDEVICE);
1473                         if (buf->skb)
1474                                 dev_kfree_skb(buf->skb);
1475                 }
1476         }
1477
1478         if (tx_ring->desc) {
1479                 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc,
1480                                     tx_ring->dma);
1481                 tx_ring->desc = NULL;
1482         }
1483         if (rx_ring->desc) {
1484                 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc,
1485                                     rx_ring->dma);
1486                 rx_ring->desc = NULL;
1487         }
1488
1489         kfree(tx_ring->tx_buffer_info);
1490         tx_ring->tx_buffer_info = NULL;
1491         kfree(rx_ring->rx_buffer_info);
1492         rx_ring->rx_buffer_info = NULL;
1493
1494         return;
1495 }
1496
1497 static int ixgbe_setup_desc_rings(struct ixgbe_adapter *adapter)
1498 {
1499         struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
1500         struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
1501         struct pci_dev *pdev = adapter->pdev;
1502         u32 rctl, reg_data;
1503         int i, ret_val;
1504
1505         /* Setup Tx descriptor ring and Tx buffers */
1506
1507         if (!tx_ring->count)
1508                 tx_ring->count = IXGBE_DEFAULT_TXD;
1509
1510         tx_ring->tx_buffer_info = kcalloc(tx_ring->count,
1511                                           sizeof(struct ixgbe_tx_buffer),
1512                                           GFP_KERNEL);
1513         if (!(tx_ring->tx_buffer_info)) {
1514                 ret_val = 1;
1515                 goto err_nomem;
1516         }
1517
1518         tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
1519         tx_ring->size = ALIGN(tx_ring->size, 4096);
1520         if (!(tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
1521                                                    &tx_ring->dma))) {
1522                 ret_val = 2;
1523                 goto err_nomem;
1524         }
1525         tx_ring->next_to_use = tx_ring->next_to_clean = 0;
1526
1527         IXGBE_WRITE_REG(&adapter->hw, IXGBE_TDBAL(0),
1528                         ((u64) tx_ring->dma & 0x00000000FFFFFFFF));
1529         IXGBE_WRITE_REG(&adapter->hw, IXGBE_TDBAH(0),
1530                         ((u64) tx_ring->dma >> 32));
1531         IXGBE_WRITE_REG(&adapter->hw, IXGBE_TDLEN(0),
1532                         tx_ring->count * sizeof(union ixgbe_adv_tx_desc));
1533         IXGBE_WRITE_REG(&adapter->hw, IXGBE_TDH(0), 0);
1534         IXGBE_WRITE_REG(&adapter->hw, IXGBE_TDT(0), 0);
1535
1536         reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0);
1537         reg_data |= IXGBE_HLREG0_TXPADEN;
1538         IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data);
1539
1540         if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1541                 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_DMATXCTL);
1542                 reg_data |= IXGBE_DMATXCTL_TE;
1543                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DMATXCTL, reg_data);
1544         }
1545         reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_TXDCTL(0));
1546         reg_data |= IXGBE_TXDCTL_ENABLE;
1547         IXGBE_WRITE_REG(&adapter->hw, IXGBE_TXDCTL(0), reg_data);
1548
1549         for (i = 0; i < tx_ring->count; i++) {
1550                 union ixgbe_adv_tx_desc *desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
1551                 struct sk_buff *skb;
1552                 unsigned int size = 1024;
1553
1554                 skb = alloc_skb(size, GFP_KERNEL);
1555                 if (!skb) {
1556                         ret_val = 3;
1557                         goto err_nomem;
1558                 }
1559                 skb_put(skb, size);
1560                 tx_ring->tx_buffer_info[i].skb = skb;
1561                 tx_ring->tx_buffer_info[i].length = skb->len;
1562                 tx_ring->tx_buffer_info[i].dma =
1563                         pci_map_single(pdev, skb->data, skb->len,
1564                                        PCI_DMA_TODEVICE);
1565                 desc->read.buffer_addr =
1566                                     cpu_to_le64(tx_ring->tx_buffer_info[i].dma);
1567                 desc->read.cmd_type_len = cpu_to_le32(skb->len);
1568                 desc->read.cmd_type_len |= cpu_to_le32(IXGBE_TXD_CMD_EOP |
1569                                                        IXGBE_TXD_CMD_IFCS |
1570                                                        IXGBE_TXD_CMD_RS);
1571                 desc->read.olinfo_status = 0;
1572                 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
1573                         desc->read.olinfo_status |=
1574                                         (skb->len << IXGBE_ADVTXD_PAYLEN_SHIFT);
1575
1576         }
1577
1578         /* Setup Rx Descriptor ring and Rx buffers */
1579
1580         if (!rx_ring->count)
1581                 rx_ring->count = IXGBE_DEFAULT_RXD;
1582
1583         rx_ring->rx_buffer_info = kcalloc(rx_ring->count,
1584                                           sizeof(struct ixgbe_rx_buffer),
1585                                           GFP_KERNEL);
1586         if (!(rx_ring->rx_buffer_info)) {
1587                 ret_val = 4;
1588                 goto err_nomem;
1589         }
1590
1591         rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
1592         rx_ring->size = ALIGN(rx_ring->size, 4096);
1593         if (!(rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size,
1594                                                    &rx_ring->dma))) {
1595                 ret_val = 5;
1596                 goto err_nomem;
1597         }
1598         rx_ring->next_to_use = rx_ring->next_to_clean = 0;
1599
1600         rctl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXCTRL);
1601         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXCTRL, rctl & ~IXGBE_RXCTRL_RXEN);
1602         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDBAL(0),
1603                         ((u64)rx_ring->dma & 0xFFFFFFFF));
1604         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDBAH(0),
1605                         ((u64) rx_ring->dma >> 32));
1606         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDLEN(0), rx_ring->size);
1607         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDH(0), 0);
1608         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDT(0), 0);
1609
1610         reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
1611         reg_data |= IXGBE_FCTRL_BAM | IXGBE_FCTRL_SBP | IXGBE_FCTRL_MPE;
1612         IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, reg_data);
1613
1614         reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0);
1615         reg_data &= ~IXGBE_HLREG0_LPBK;
1616         IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data);
1617
1618         reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_RDRXCTL);
1619 #define IXGBE_RDRXCTL_RDMTS_MASK    0x00000003 /* Receive Descriptor Minimum
1620                                                   Threshold Size mask */
1621         reg_data &= ~IXGBE_RDRXCTL_RDMTS_MASK;
1622         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDRXCTL, reg_data);
1623
1624         reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_MCSTCTRL);
1625 #define IXGBE_MCSTCTRL_MO_MASK      0x00000003 /* Multicast Offset mask */
1626         reg_data &= ~IXGBE_MCSTCTRL_MO_MASK;
1627         reg_data |= adapter->hw.mac.mc_filter_type;
1628         IXGBE_WRITE_REG(&adapter->hw, IXGBE_MCSTCTRL, reg_data);
1629
1630         reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_RXDCTL(0));
1631         reg_data |= IXGBE_RXDCTL_ENABLE;
1632         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXDCTL(0), reg_data);
1633         if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1634                 int j = adapter->rx_ring[0].reg_idx;
1635                 u32 k;
1636                 for (k = 0; k < 10; k++) {
1637                         if (IXGBE_READ_REG(&adapter->hw,
1638                                            IXGBE_RXDCTL(j)) & IXGBE_RXDCTL_ENABLE)
1639                                 break;
1640                         else
1641                                 msleep(1);
1642                 }
1643         }
1644
1645         rctl |= IXGBE_RXCTRL_RXEN | IXGBE_RXCTRL_DMBYPS;
1646         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXCTRL, rctl);
1647
1648         for (i = 0; i < rx_ring->count; i++) {
1649                 union ixgbe_adv_rx_desc *rx_desc =
1650                                                  IXGBE_RX_DESC_ADV(*rx_ring, i);
1651                 struct sk_buff *skb;
1652
1653                 skb = alloc_skb(IXGBE_RXBUFFER_2048 + NET_IP_ALIGN, GFP_KERNEL);
1654                 if (!skb) {
1655                         ret_val = 6;
1656                         goto err_nomem;
1657                 }
1658                 skb_reserve(skb, NET_IP_ALIGN);
1659                 rx_ring->rx_buffer_info[i].skb = skb;
1660                 rx_ring->rx_buffer_info[i].dma =
1661                         pci_map_single(pdev, skb->data, IXGBE_RXBUFFER_2048,
1662                                        PCI_DMA_FROMDEVICE);
1663                 rx_desc->read.pkt_addr =
1664                                 cpu_to_le64(rx_ring->rx_buffer_info[i].dma);
1665                 memset(skb->data, 0x00, skb->len);
1666         }
1667
1668         return 0;
1669
1670 err_nomem:
1671         ixgbe_free_desc_rings(adapter);
1672         return ret_val;
1673 }
1674
1675 static int ixgbe_setup_loopback_test(struct ixgbe_adapter *adapter)
1676 {
1677         struct ixgbe_hw *hw = &adapter->hw;
1678         u32 reg_data;
1679
1680         /* right now we only support MAC loopback in the driver */
1681
1682         /* Setup MAC loopback */
1683         reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0);
1684         reg_data |= IXGBE_HLREG0_LPBK;
1685         IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data);
1686
1687         reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_AUTOC);
1688         reg_data &= ~IXGBE_AUTOC_LMS_MASK;
1689         reg_data |= IXGBE_AUTOC_LMS_10G_LINK_NO_AN | IXGBE_AUTOC_FLU;
1690         IXGBE_WRITE_REG(&adapter->hw, IXGBE_AUTOC, reg_data);
1691
1692         /* Disable Atlas Tx lanes; re-enabled in reset path */
1693         if (hw->mac.type == ixgbe_mac_82598EB) {
1694                 u8 atlas;
1695
1696                 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &atlas);
1697                 atlas |= IXGBE_ATLAS_PDN_TX_REG_EN;
1698                 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, atlas);
1699
1700                 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, &atlas);
1701                 atlas |= IXGBE_ATLAS_PDN_TX_10G_QL_ALL;
1702                 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, atlas);
1703
1704                 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, &atlas);
1705                 atlas |= IXGBE_ATLAS_PDN_TX_1G_QL_ALL;
1706                 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, atlas);
1707
1708                 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, &atlas);
1709                 atlas |= IXGBE_ATLAS_PDN_TX_AN_QL_ALL;
1710                 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, atlas);
1711         }
1712
1713         return 0;
1714 }
1715
1716 static void ixgbe_loopback_cleanup(struct ixgbe_adapter *adapter)
1717 {
1718         u32 reg_data;
1719
1720         reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0);
1721         reg_data &= ~IXGBE_HLREG0_LPBK;
1722         IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data);
1723 }
1724
1725 static void ixgbe_create_lbtest_frame(struct sk_buff *skb,
1726                                       unsigned int frame_size)
1727 {
1728         memset(skb->data, 0xFF, frame_size);
1729         frame_size &= ~1;
1730         memset(&skb->data[frame_size / 2], 0xAA, frame_size / 2 - 1);
1731         memset(&skb->data[frame_size / 2 + 10], 0xBE, 1);
1732         memset(&skb->data[frame_size / 2 + 12], 0xAF, 1);
1733 }
1734
1735 static int ixgbe_check_lbtest_frame(struct sk_buff *skb,
1736                                     unsigned int frame_size)
1737 {
1738         frame_size &= ~1;
1739         if (*(skb->data + 3) == 0xFF) {
1740                 if ((*(skb->data + frame_size / 2 + 10) == 0xBE) &&
1741                     (*(skb->data + frame_size / 2 + 12) == 0xAF)) {
1742                         return 0;
1743                 }
1744         }
1745         return 13;
1746 }
1747
1748 static int ixgbe_run_loopback_test(struct ixgbe_adapter *adapter)
1749 {
1750         struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
1751         struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
1752         struct pci_dev *pdev = adapter->pdev;
1753         int i, j, k, l, lc, good_cnt, ret_val = 0;
1754         unsigned long time;
1755
1756         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDT(0), rx_ring->count - 1);
1757
1758         /*
1759          * Calculate the loop count based on the largest descriptor ring
1760          * The idea is to wrap the largest ring a number of times using 64
1761          * send/receive pairs during each loop
1762          */
1763
1764         if (rx_ring->count <= tx_ring->count)
1765                 lc = ((tx_ring->count / 64) * 2) + 1;
1766         else
1767                 lc = ((rx_ring->count / 64) * 2) + 1;
1768
1769         k = l = 0;
1770         for (j = 0; j <= lc; j++) {
1771                 for (i = 0; i < 64; i++) {
1772                         ixgbe_create_lbtest_frame(
1773                                         tx_ring->tx_buffer_info[k].skb,
1774                                         1024);
1775                         pci_dma_sync_single_for_device(pdev,
1776                                 tx_ring->tx_buffer_info[k].dma,
1777                                 tx_ring->tx_buffer_info[k].length,
1778                                 PCI_DMA_TODEVICE);
1779                         if (unlikely(++k == tx_ring->count))
1780                                 k = 0;
1781                 }
1782                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_TDT(0), k);
1783                 msleep(200);
1784                 /* set the start time for the receive */
1785                 time = jiffies;
1786                 good_cnt = 0;
1787                 do {
1788                         /* receive the sent packets */
1789                         pci_dma_sync_single_for_cpu(pdev,
1790                                         rx_ring->rx_buffer_info[l].dma,
1791                                         IXGBE_RXBUFFER_2048,
1792                                         PCI_DMA_FROMDEVICE);
1793                         ret_val = ixgbe_check_lbtest_frame(
1794                                         rx_ring->rx_buffer_info[l].skb, 1024);
1795                         if (!ret_val)
1796                                 good_cnt++;
1797                         if (++l == rx_ring->count)
1798                                 l = 0;
1799                         /*
1800                          * time + 20 msecs (200 msecs on 2.4) is more than
1801                          * enough time to complete the receives, if it's
1802                          * exceeded, break and error off
1803                          */
1804                 } while (good_cnt < 64 && jiffies < (time + 20));
1805                 if (good_cnt != 64) {
1806                         /* ret_val is the same as mis-compare */
1807                         ret_val = 13;
1808                         break;
1809                 }
1810                 if (jiffies >= (time + 20)) {
1811                         /* Error code for time out error */
1812                         ret_val = 14;
1813                         break;
1814                 }
1815         }
1816
1817         return ret_val;
1818 }
1819
1820 static int ixgbe_loopback_test(struct ixgbe_adapter *adapter, u64 *data)
1821 {
1822         *data = ixgbe_setup_desc_rings(adapter);
1823         if (*data)
1824                 goto out;
1825         *data = ixgbe_setup_loopback_test(adapter);
1826         if (*data)
1827                 goto err_loopback;
1828         *data = ixgbe_run_loopback_test(adapter);
1829         ixgbe_loopback_cleanup(adapter);
1830
1831 err_loopback:
1832         ixgbe_free_desc_rings(adapter);
1833 out:
1834         return *data;
1835 }
1836
1837 static void ixgbe_diag_test(struct net_device *netdev,
1838                             struct ethtool_test *eth_test, u64 *data)
1839 {
1840         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1841         bool if_running = netif_running(netdev);
1842
1843         set_bit(__IXGBE_TESTING, &adapter->state);
1844         if (eth_test->flags == ETH_TEST_FL_OFFLINE) {
1845                 /* Offline tests */
1846
1847                 DPRINTK(HW, INFO, "offline testing starting\n");
1848
1849                 /* Link test performed before hardware reset so autoneg doesn't
1850                  * interfere with test result */
1851                 if (ixgbe_link_test(adapter, &data[4]))
1852                         eth_test->flags |= ETH_TEST_FL_FAILED;
1853
1854                 if (if_running)
1855                         /* indicate we're in test mode */
1856                         dev_close(netdev);
1857                 else
1858                         ixgbe_reset(adapter);
1859
1860                 DPRINTK(HW, INFO, "register testing starting\n");
1861                 if (ixgbe_reg_test(adapter, &data[0]))
1862                         eth_test->flags |= ETH_TEST_FL_FAILED;
1863
1864                 ixgbe_reset(adapter);
1865                 DPRINTK(HW, INFO, "eeprom testing starting\n");
1866                 if (ixgbe_eeprom_test(adapter, &data[1]))
1867                         eth_test->flags |= ETH_TEST_FL_FAILED;
1868
1869                 ixgbe_reset(adapter);
1870                 DPRINTK(HW, INFO, "interrupt testing starting\n");
1871                 if (ixgbe_intr_test(adapter, &data[2]))
1872                         eth_test->flags |= ETH_TEST_FL_FAILED;
1873
1874                 ixgbe_reset(adapter);
1875                 DPRINTK(HW, INFO, "loopback testing starting\n");
1876                 if (ixgbe_loopback_test(adapter, &data[3]))
1877                         eth_test->flags |= ETH_TEST_FL_FAILED;
1878
1879                 ixgbe_reset(adapter);
1880
1881                 clear_bit(__IXGBE_TESTING, &adapter->state);
1882                 if (if_running)
1883                         dev_open(netdev);
1884         } else {
1885                 DPRINTK(HW, INFO, "online testing starting\n");
1886                 /* Online tests */
1887                 if (ixgbe_link_test(adapter, &data[4]))
1888                         eth_test->flags |= ETH_TEST_FL_FAILED;
1889
1890                 /* Online tests aren't run; pass by default */
1891                 data[0] = 0;
1892                 data[1] = 0;
1893                 data[2] = 0;
1894                 data[3] = 0;
1895
1896                 clear_bit(__IXGBE_TESTING, &adapter->state);
1897         }
1898         msleep_interruptible(4 * 1000);
1899 }
1900
1901 static int ixgbe_wol_exclusion(struct ixgbe_adapter *adapter,
1902                                struct ethtool_wolinfo *wol)
1903 {
1904         struct ixgbe_hw *hw = &adapter->hw;
1905         int retval = 1;
1906
1907         switch(hw->device_id) {
1908         case IXGBE_DEV_ID_82599_KX4:
1909                 retval = 0;
1910                 break;
1911         default:
1912                 wol->supported = 0;
1913         }
1914
1915         return retval;
1916 }
1917
1918 static void ixgbe_get_wol(struct net_device *netdev,
1919                           struct ethtool_wolinfo *wol)
1920 {
1921         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1922
1923         wol->supported = WAKE_UCAST | WAKE_MCAST |
1924                          WAKE_BCAST | WAKE_MAGIC;
1925         wol->wolopts = 0;
1926
1927         if (ixgbe_wol_exclusion(adapter, wol) ||
1928             !device_can_wakeup(&adapter->pdev->dev))
1929                 return;
1930
1931         if (adapter->wol & IXGBE_WUFC_EX)
1932                 wol->wolopts |= WAKE_UCAST;
1933         if (adapter->wol & IXGBE_WUFC_MC)
1934                 wol->wolopts |= WAKE_MCAST;
1935         if (adapter->wol & IXGBE_WUFC_BC)
1936                 wol->wolopts |= WAKE_BCAST;
1937         if (adapter->wol & IXGBE_WUFC_MAG)
1938                 wol->wolopts |= WAKE_MAGIC;
1939
1940         return;
1941 }
1942
1943 static int ixgbe_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1944 {
1945         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1946
1947         if (wol->wolopts & (WAKE_PHY | WAKE_ARP | WAKE_MAGICSECURE))
1948                 return -EOPNOTSUPP;
1949
1950         if (ixgbe_wol_exclusion(adapter, wol))
1951                 return wol->wolopts ? -EOPNOTSUPP : 0;
1952
1953         adapter->wol = 0;
1954
1955         if (wol->wolopts & WAKE_UCAST)
1956                 adapter->wol |= IXGBE_WUFC_EX;
1957         if (wol->wolopts & WAKE_MCAST)
1958                 adapter->wol |= IXGBE_WUFC_MC;
1959         if (wol->wolopts & WAKE_BCAST)
1960                 adapter->wol |= IXGBE_WUFC_BC;
1961         if (wol->wolopts & WAKE_MAGIC)
1962                 adapter->wol |= IXGBE_WUFC_MAG;
1963
1964         device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
1965
1966         return 0;
1967 }
1968
1969 static int ixgbe_nway_reset(struct net_device *netdev)
1970 {
1971         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1972
1973         if (netif_running(netdev))
1974                 ixgbe_reinit_locked(adapter);
1975
1976         return 0;
1977 }
1978
1979 static int ixgbe_phys_id(struct net_device *netdev, u32 data)
1980 {
1981         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1982         struct ixgbe_hw *hw = &adapter->hw;
1983         u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
1984         u32 i;
1985
1986         if (!data || data > 300)
1987                 data = 300;
1988
1989         for (i = 0; i < (data * 1000); i += 400) {
1990                 hw->mac.ops.led_on(hw, IXGBE_LED_ON);
1991                 msleep_interruptible(200);
1992                 hw->mac.ops.led_off(hw, IXGBE_LED_ON);
1993                 msleep_interruptible(200);
1994         }
1995
1996         /* Restore LED settings */
1997         IXGBE_WRITE_REG(&adapter->hw, IXGBE_LEDCTL, led_reg);
1998
1999         return 0;
2000 }
2001
2002 static int ixgbe_get_coalesce(struct net_device *netdev,
2003                               struct ethtool_coalesce *ec)
2004 {
2005         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2006
2007         ec->tx_max_coalesced_frames_irq = adapter->tx_ring[0].work_limit;
2008
2009         /* only valid if in constant ITR mode */
2010         switch (adapter->rx_itr_setting) {
2011         case 0:
2012                 /* throttling disabled */
2013                 ec->rx_coalesce_usecs = 0;
2014                 break;
2015         case 1:
2016                 /* dynamic ITR mode */
2017                 ec->rx_coalesce_usecs = 1;
2018                 break;
2019         default:
2020                 /* fixed interrupt rate mode */
2021                 ec->rx_coalesce_usecs = 1000000/adapter->rx_eitr_param;
2022                 break;
2023         }
2024
2025         /* if in mixed tx/rx queues per vector mode, report only rx settings */
2026         if (adapter->q_vector[0]->txr_count && adapter->q_vector[0]->rxr_count)
2027                 return 0;
2028
2029         /* only valid if in constant ITR mode */
2030         switch (adapter->tx_itr_setting) {
2031         case 0:
2032                 /* throttling disabled */
2033                 ec->tx_coalesce_usecs = 0;
2034                 break;
2035         case 1:
2036                 /* dynamic ITR mode */
2037                 ec->tx_coalesce_usecs = 1;
2038                 break;
2039         default:
2040                 ec->tx_coalesce_usecs = 1000000/adapter->tx_eitr_param;
2041                 break;
2042         }
2043
2044         return 0;
2045 }
2046
2047 static int ixgbe_set_coalesce(struct net_device *netdev,
2048                               struct ethtool_coalesce *ec)
2049 {
2050         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2051         struct ixgbe_q_vector *q_vector;
2052         int i;
2053
2054         /* don't accept tx specific changes if we've got mixed RxTx vectors */
2055         if (adapter->q_vector[0]->txr_count && adapter->q_vector[0]->rxr_count
2056            && ec->tx_coalesce_usecs)
2057                 return -EINVAL;
2058
2059         if (ec->tx_max_coalesced_frames_irq)
2060                 adapter->tx_ring[0].work_limit = ec->tx_max_coalesced_frames_irq;
2061
2062         if (ec->rx_coalesce_usecs > 1) {
2063                 /* check the limits */
2064                 if ((1000000/ec->rx_coalesce_usecs > IXGBE_MAX_INT_RATE) ||
2065                     (1000000/ec->rx_coalesce_usecs < IXGBE_MIN_INT_RATE))
2066                         return -EINVAL;
2067
2068                 /* store the value in ints/second */
2069                 adapter->rx_eitr_param = 1000000/ec->rx_coalesce_usecs;
2070
2071                 /* static value of interrupt rate */
2072                 adapter->rx_itr_setting = adapter->rx_eitr_param;
2073                 /* clear the lower bit as its used for dynamic state */
2074                 adapter->rx_itr_setting &= ~1;
2075         } else if (ec->rx_coalesce_usecs == 1) {
2076                 /* 1 means dynamic mode */
2077                 adapter->rx_eitr_param = 20000;
2078                 adapter->rx_itr_setting = 1;
2079         } else {
2080                 /*
2081                  * any other value means disable eitr, which is best
2082                  * served by setting the interrupt rate very high
2083                  */
2084                 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
2085                         adapter->rx_eitr_param = IXGBE_MAX_RSC_INT_RATE;
2086                 else
2087                         adapter->rx_eitr_param = IXGBE_MAX_INT_RATE;
2088                 adapter->rx_itr_setting = 0;
2089         }
2090
2091         if (ec->tx_coalesce_usecs > 1) {
2092                 /* check the limits */
2093                 if ((1000000/ec->tx_coalesce_usecs > IXGBE_MAX_INT_RATE) ||
2094                     (1000000/ec->tx_coalesce_usecs < IXGBE_MIN_INT_RATE))
2095                         return -EINVAL;
2096
2097                 /* store the value in ints/second */
2098                 adapter->tx_eitr_param = 1000000/ec->tx_coalesce_usecs;
2099
2100                 /* static value of interrupt rate */
2101                 adapter->tx_itr_setting = adapter->tx_eitr_param;
2102
2103                 /* clear the lower bit as its used for dynamic state */
2104                 adapter->tx_itr_setting &= ~1;
2105         } else if (ec->tx_coalesce_usecs == 1) {
2106                 /* 1 means dynamic mode */
2107                 adapter->tx_eitr_param = 10000;
2108                 adapter->tx_itr_setting = 1;
2109         } else {
2110                 adapter->tx_eitr_param = IXGBE_MAX_INT_RATE;
2111                 adapter->tx_itr_setting = 0;
2112         }
2113
2114         /* MSI/MSIx Interrupt Mode */
2115         if (adapter->flags &
2116             (IXGBE_FLAG_MSIX_ENABLED | IXGBE_FLAG_MSI_ENABLED)) {
2117                 int num_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2118                 for (i = 0; i < num_vectors; i++) {
2119                         q_vector = adapter->q_vector[i];
2120                         if (q_vector->txr_count && !q_vector->rxr_count)
2121                                 /* tx only */
2122                                 q_vector->eitr = adapter->tx_eitr_param;
2123                         else
2124                                 /* rx only or mixed */
2125                                 q_vector->eitr = adapter->rx_eitr_param;
2126                         ixgbe_write_eitr(q_vector);
2127                 }
2128         /* Legacy Interrupt Mode */
2129         } else {
2130                 q_vector = adapter->q_vector[0];
2131                 q_vector->eitr = adapter->rx_eitr_param;
2132                 ixgbe_write_eitr(q_vector);
2133         }
2134
2135         return 0;
2136 }
2137
2138 static int ixgbe_set_flags(struct net_device *netdev, u32 data)
2139 {
2140         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2141
2142         ethtool_op_set_flags(netdev, data);
2143
2144         if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE))
2145                 return 0;
2146
2147         /* if state changes we need to update adapter->flags and reset */
2148         if ((!!(data & ETH_FLAG_LRO)) !=
2149             (!!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))) {
2150                 adapter->flags2 ^= IXGBE_FLAG2_RSC_ENABLED;
2151                 if (netif_running(netdev))
2152                         ixgbe_reinit_locked(adapter);
2153                 else
2154                         ixgbe_reset(adapter);
2155         }
2156         return 0;
2157
2158 }
2159
2160 static const struct ethtool_ops ixgbe_ethtool_ops = {
2161         .get_settings           = ixgbe_get_settings,
2162         .set_settings           = ixgbe_set_settings,
2163         .get_drvinfo            = ixgbe_get_drvinfo,
2164         .get_regs_len           = ixgbe_get_regs_len,
2165         .get_regs               = ixgbe_get_regs,
2166         .get_wol                = ixgbe_get_wol,
2167         .set_wol                = ixgbe_set_wol,
2168         .nway_reset             = ixgbe_nway_reset,
2169         .get_link               = ethtool_op_get_link,
2170         .get_eeprom_len         = ixgbe_get_eeprom_len,
2171         .get_eeprom             = ixgbe_get_eeprom,
2172         .get_ringparam          = ixgbe_get_ringparam,
2173         .set_ringparam          = ixgbe_set_ringparam,
2174         .get_pauseparam         = ixgbe_get_pauseparam,
2175         .set_pauseparam         = ixgbe_set_pauseparam,
2176         .get_rx_csum            = ixgbe_get_rx_csum,
2177         .set_rx_csum            = ixgbe_set_rx_csum,
2178         .get_tx_csum            = ixgbe_get_tx_csum,
2179         .set_tx_csum            = ixgbe_set_tx_csum,
2180         .get_sg                 = ethtool_op_get_sg,
2181         .set_sg                 = ethtool_op_set_sg,
2182         .get_msglevel           = ixgbe_get_msglevel,
2183         .set_msglevel           = ixgbe_set_msglevel,
2184         .get_tso                = ethtool_op_get_tso,
2185         .set_tso                = ixgbe_set_tso,
2186         .self_test              = ixgbe_diag_test,
2187         .get_strings            = ixgbe_get_strings,
2188         .phys_id                = ixgbe_phys_id,
2189         .get_sset_count         = ixgbe_get_sset_count,
2190         .get_ethtool_stats      = ixgbe_get_ethtool_stats,
2191         .get_coalesce           = ixgbe_get_coalesce,
2192         .set_coalesce           = ixgbe_set_coalesce,
2193         .get_flags              = ethtool_op_get_flags,
2194         .set_flags              = ixgbe_set_flags,
2195 };
2196
2197 void ixgbe_set_ethtool_ops(struct net_device *netdev)
2198 {
2199         SET_ETHTOOL_OPS(netdev, &ixgbe_ethtool_ops);
2200 }