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   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2010 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 /* ethtool support for ixgbe */
  29
  30 #include <linux/types.h>
  31 #include <linux/module.h>
  32 #include <linux/pci.h>
  33 #include <linux/netdevice.h>
  34 #include <linux/ethtool.h>
  35 #include <linux/vmalloc.h>
  36 #include <linux/uaccess.h>
  37
  38 #include "ixgbe.h"
  39
  40
  41 #define IXGBE_ALL_RAR_ENTRIES 16
  42
  43 enum {NETDEV_STATS, IXGBE_STATS};
  44
  45 struct ixgbe_stats {
  46         char stat_string[ETH_GSTRING_LEN];
  47         int type;
  48         int sizeof_stat;
  49         int stat_offset;
  50 };
  51
  52 #define IXGBE_STAT(m)           IXGBE_STATS, \
  53                                 sizeof(((struct ixgbe_adapter *)0)->m), \
  54                                 offsetof(struct ixgbe_adapter, m)
  55 #define IXGBE_NETDEV_STAT(m)    NETDEV_STATS, \
  56                                 sizeof(((struct net_device *)0)->m), \
  57                                 offsetof(struct net_device, m)
  58
  59 static struct ixgbe_stats ixgbe_gstrings_stats[] = {
  60         {"rx_packets", IXGBE_NETDEV_STAT(stats.rx_packets)},
  61         {"tx_packets", IXGBE_NETDEV_STAT(stats.tx_packets)},
  62         {"rx_bytes", IXGBE_NETDEV_STAT(stats.rx_bytes)},
  63         {"tx_bytes", IXGBE_NETDEV_STAT(stats.tx_bytes)},
  64         {"rx_pkts_nic", IXGBE_STAT(stats.gprc)},
  65         {"tx_pkts_nic", IXGBE_STAT(stats.gptc)},
  66         {"rx_bytes_nic", IXGBE_STAT(stats.gorc)},
  67         {"tx_bytes_nic", IXGBE_STAT(stats.gotc)},
  68         {"lsc_int", IXGBE_STAT(lsc_int)},
  69         {"tx_busy", IXGBE_STAT(tx_busy)},
  70         {"non_eop_descs", IXGBE_STAT(non_eop_descs)},
  71         {"rx_errors", IXGBE_NETDEV_STAT(stats.rx_errors)},
  72         {"tx_errors", IXGBE_NETDEV_STAT(stats.tx_errors)},
  73         {"rx_dropped", IXGBE_NETDEV_STAT(stats.rx_dropped)},
  74         {"tx_dropped", IXGBE_NETDEV_STAT(stats.tx_dropped)},
  75         {"multicast", IXGBE_NETDEV_STAT(stats.multicast)},
  76         {"broadcast", IXGBE_STAT(stats.bprc)},
  77         {"rx_no_buffer_count", IXGBE_STAT(stats.rnbc[0]) },
  78         {"collisions", IXGBE_NETDEV_STAT(stats.collisions)},
  79         {"rx_over_errors", IXGBE_NETDEV_STAT(stats.rx_over_errors)},
  80         {"rx_crc_errors", IXGBE_NETDEV_STAT(stats.rx_crc_errors)},
  81         {"rx_frame_errors", IXGBE_NETDEV_STAT(stats.rx_frame_errors)},
  82         {"hw_rsc_aggregated", IXGBE_STAT(rsc_total_count)},
  83         {"hw_rsc_flushed", IXGBE_STAT(rsc_total_flush)},
  84         {"fdir_match", IXGBE_STAT(stats.fdirmatch)},
  85         {"fdir_miss", IXGBE_STAT(stats.fdirmiss)},
  86         {"rx_fifo_errors", IXGBE_NETDEV_STAT(stats.rx_fifo_errors)},
  87         {"rx_missed_errors", IXGBE_NETDEV_STAT(stats.rx_missed_errors)},
  88         {"tx_aborted_errors", IXGBE_NETDEV_STAT(stats.tx_aborted_errors)},
  89         {"tx_carrier_errors", IXGBE_NETDEV_STAT(stats.tx_carrier_errors)},
  90         {"tx_fifo_errors", IXGBE_NETDEV_STAT(stats.tx_fifo_errors)},
  91         {"tx_heartbeat_errors", IXGBE_NETDEV_STAT(stats.tx_heartbeat_errors)},
  92         {"tx_timeout_count", IXGBE_STAT(tx_timeout_count)},
  93         {"tx_restart_queue", IXGBE_STAT(restart_queue)},
  94         {"rx_long_length_errors", IXGBE_STAT(stats.roc)},
  95         {"rx_short_length_errors", IXGBE_STAT(stats.ruc)},
  96         {"tx_flow_control_xon", IXGBE_STAT(stats.lxontxc)},
  97         {"rx_flow_control_xon", IXGBE_STAT(stats.lxonrxc)},
  98         {"tx_flow_control_xoff", IXGBE_STAT(stats.lxofftxc)},
  99         {"rx_flow_control_xoff", IXGBE_STAT(stats.lxoffrxc)},
 100         {"rx_csum_offload_errors", IXGBE_STAT(hw_csum_rx_error)},
 101         {"alloc_rx_page_failed", IXGBE_STAT(alloc_rx_page_failed)},
 102         {"alloc_rx_buff_failed", IXGBE_STAT(alloc_rx_buff_failed)},
 103         {"rx_no_dma_resources", IXGBE_STAT(hw_rx_no_dma_resources)},
 104 #ifdef IXGBE_FCOE
 105         {"fcoe_bad_fccrc", IXGBE_STAT(stats.fccrc)},
 106         {"rx_fcoe_dropped", IXGBE_STAT(stats.fcoerpdc)},
 107         {"rx_fcoe_packets", IXGBE_STAT(stats.fcoeprc)},
 108         {"rx_fcoe_dwords", IXGBE_STAT(stats.fcoedwrc)},
 109         {"tx_fcoe_packets", IXGBE_STAT(stats.fcoeptc)},
 110         {"tx_fcoe_dwords", IXGBE_STAT(stats.fcoedwtc)},
 111 #endif /* IXGBE_FCOE */
 112 };
 113
 114 #define IXGBE_QUEUE_STATS_LEN \
 115         ((((struct ixgbe_adapter *)netdev_priv(netdev))->num_tx_queues + \
 116         ((struct ixgbe_adapter *)netdev_priv(netdev))->num_rx_queues) * \
 117         (sizeof(struct ixgbe_queue_stats) / sizeof(u64)))
 118 #define IXGBE_GLOBAL_STATS_LEN ARRAY_SIZE(ixgbe_gstrings_stats)
 119 #define IXGBE_PB_STATS_LEN ( \
 120                  (((struct ixgbe_adapter *)netdev_priv(netdev))->flags & \
 121                  IXGBE_FLAG_DCB_ENABLED) ? \
 122                  (sizeof(((struct ixgbe_adapter *)0)->stats.pxonrxc) + \
 123                   sizeof(((struct ixgbe_adapter *)0)->stats.pxontxc) + \
 124                   sizeof(((struct ixgbe_adapter *)0)->stats.pxoffrxc) + \
 125                   sizeof(((struct ixgbe_adapter *)0)->stats.pxofftxc)) \
 126                   / sizeof(u64) : 0)
 127 #define IXGBE_STATS_LEN (IXGBE_GLOBAL_STATS_LEN + \
 128                          IXGBE_PB_STATS_LEN + \
 129                          IXGBE_QUEUE_STATS_LEN)
 130
 131 static const char ixgbe_gstrings_test[][ETH_GSTRING_LEN] = {
 132         "Register test  (offline)", "Eeprom test    (offline)",
 133         "Interrupt test (offline)", "Loopback test  (offline)",
 134         "Link test   (on/offline)"
 135 };
 136 #define IXGBE_TEST_LEN sizeof(ixgbe_gstrings_test) / ETH_GSTRING_LEN
 137
 138 static int ixgbe_get_settings(struct net_device *netdev,
 139                               struct ethtool_cmd *ecmd)
 140 {
 141         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 142         struct ixgbe_hw *hw = &adapter->hw;
 143         u32 link_speed = 0;
 144         bool link_up;
 145
 146         ecmd->supported = SUPPORTED_10000baseT_Full;
 147         ecmd->autoneg = AUTONEG_ENABLE;
 148         ecmd->transceiver = XCVR_EXTERNAL;
 149         if ((hw->phy.media_type == ixgbe_media_type_copper) ||
 150             (hw->phy.multispeed_fiber)) {
 151                 ecmd->supported |= (SUPPORTED_1000baseT_Full |
 152                                     SUPPORTED_Autoneg);
 153
 154                 ecmd->advertising = ADVERTISED_Autoneg;
 155                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
 156                         ecmd->advertising |= ADVERTISED_10000baseT_Full;
 157                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
 158                         ecmd->advertising |= ADVERTISED_1000baseT_Full;
 159                 /*
 160                  * It's possible that phy.autoneg_advertised may not be
 161                  * set yet.  If so display what the default would be -
 162                  * both 1G and 10G supported.
 163                  */
 164                 if (!(ecmd->advertising & (ADVERTISED_1000baseT_Full |
 165                                            ADVERTISED_10000baseT_Full)))
 166                         ecmd->advertising |= (ADVERTISED_10000baseT_Full |
 167                                               ADVERTISED_1000baseT_Full);
 168
 169                 if (hw->phy.media_type == ixgbe_media_type_copper) {
 170                         ecmd->supported |= SUPPORTED_TP;
 171                         ecmd->advertising |= ADVERTISED_TP;
 172                         ecmd->port = PORT_TP;
 173                 } else {
 174                         ecmd->supported |= SUPPORTED_FIBRE;
 175                         ecmd->advertising |= ADVERTISED_FIBRE;
 176                         ecmd->port = PORT_FIBRE;
 177                 }
 178         } else if (hw->phy.media_type == ixgbe_media_type_backplane) {
 179                 /* Set as FIBRE until SERDES defined in kernel */
 180                 if (hw->device_id == IXGBE_DEV_ID_82598_BX) {
 181                         ecmd->supported = (SUPPORTED_1000baseT_Full |
 182                                            SUPPORTED_FIBRE);
 183                         ecmd->advertising = (ADVERTISED_1000baseT_Full |
 184                                              ADVERTISED_FIBRE);
 185                         ecmd->port = PORT_FIBRE;
 186                         ecmd->autoneg = AUTONEG_DISABLE;
 187                 } else {
 188                         ecmd->supported |= (SUPPORTED_1000baseT_Full |
 189                                             SUPPORTED_FIBRE);
 190                         ecmd->advertising = (ADVERTISED_10000baseT_Full |
 191                                              ADVERTISED_1000baseT_Full |
 192                                              ADVERTISED_FIBRE);
 193                         ecmd->port = PORT_FIBRE;
 194                 }
 195         } else {
 196                 ecmd->supported |= SUPPORTED_FIBRE;
 197                 ecmd->advertising = (ADVERTISED_10000baseT_Full |
 198                                      ADVERTISED_FIBRE);
 199                 ecmd->port = PORT_FIBRE;
 200                 ecmd->autoneg = AUTONEG_DISABLE;
 201         }
 202
 203         /* Get PHY type */
 204         switch (adapter->hw.phy.type) {
 205         case ixgbe_phy_tn:
 206         case ixgbe_phy_cu_unknown:
 207                 /* Copper 10G-BASET */
 208                 ecmd->port = PORT_TP;
 209                 break;
 210         case ixgbe_phy_qt:
 211                 ecmd->port = PORT_FIBRE;
 212                 break;
 213         case ixgbe_phy_nl:
 214         case ixgbe_phy_tw_tyco:
 215         case ixgbe_phy_tw_unknown:
 216         case ixgbe_phy_sfp_ftl:
 217         case ixgbe_phy_sfp_avago:
 218         case ixgbe_phy_sfp_intel:
 219         case ixgbe_phy_sfp_unknown:
 220                 switch (adapter->hw.phy.sfp_type) {
 221                 /* SFP+ devices, further checking needed */
 222                 case ixgbe_sfp_type_da_cu:
 223                 case ixgbe_sfp_type_da_cu_core0:
 224                 case ixgbe_sfp_type_da_cu_core1:
 225                         ecmd->port = PORT_DA;
 226                         break;
 227                 case ixgbe_sfp_type_sr:
 228                 case ixgbe_sfp_type_lr:
 229                 case ixgbe_sfp_type_srlr_core0:
 230                 case ixgbe_sfp_type_srlr_core1:
 231                         ecmd->port = PORT_FIBRE;
 232                         break;
 233                 case ixgbe_sfp_type_not_present:
 234                         ecmd->port = PORT_NONE;
 235                         break;
 236                 case ixgbe_sfp_type_unknown:
 237                 default:
 238                         ecmd->port = PORT_OTHER;
 239                         break;
 240                 }
 241                 break;
 242         case ixgbe_phy_xaui:
 243                 ecmd->port = PORT_NONE;
 244                 break;
 245         case ixgbe_phy_unknown:
 246         case ixgbe_phy_generic:
 247         case ixgbe_phy_sfp_unsupported:
 248         default:
 249                 ecmd->port = PORT_OTHER;
 250                 break;
 251         }
 252
 253         hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
 254         if (link_up) {
 255                 ecmd->speed = (link_speed == IXGBE_LINK_SPEED_10GB_FULL) ?
 256                                SPEED_10000 : SPEED_1000;
 257                 ecmd->duplex = DUPLEX_FULL;
 258         } else {
 259                 ecmd->speed = -1;
 260                 ecmd->duplex = -1;
 261         }
 262
 263         return 0;
 264 }
 265
 266 static int ixgbe_set_settings(struct net_device *netdev,
 267                               struct ethtool_cmd *ecmd)
 268 {
 269         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 270         struct ixgbe_hw *hw = &adapter->hw;
 271         u32 advertised, old;
 272         s32 err = 0;
 273
 274         if ((hw->phy.media_type == ixgbe_media_type_copper) ||
 275             (hw->phy.multispeed_fiber)) {
 276                 /* 10000/copper and 1000/copper must autoneg
 277                  * this function does not support any duplex forcing, but can
 278                  * limit the advertising of the adapter to only 10000 or 1000 */
 279                 if (ecmd->autoneg == AUTONEG_DISABLE)
 280                         return -EINVAL;
 281
 282                 old = hw->phy.autoneg_advertised;
 283                 advertised = 0;
 284                 if (ecmd->advertising & ADVERTISED_10000baseT_Full)
 285                         advertised |= IXGBE_LINK_SPEED_10GB_FULL;
 286
 287                 if (ecmd->advertising & ADVERTISED_1000baseT_Full)
 288                         advertised |= IXGBE_LINK_SPEED_1GB_FULL;
 289
 290                 if (old == advertised)
 291                         return err;
 292                 /* this sets the link speed and restarts auto-neg */
 293                 hw->mac.autotry_restart = true;
 294                 err = hw->mac.ops.setup_link(hw, advertised, true, true);
 295                 if (err) {
 296                         DPRINTK(PROBE, INFO,
 297                                 "setup link failed with code %d\n", err);
 298                         hw->mac.ops.setup_link(hw, old, true, true);
 299                 }
 300         } else {
 301                 /* in this case we currently only support 10Gb/FULL */
 302                 if ((ecmd->autoneg == AUTONEG_ENABLE) ||
 303                     (ecmd->advertising != ADVERTISED_10000baseT_Full) ||
 304                     (ecmd->speed + ecmd->duplex != SPEED_10000 + DUPLEX_FULL))
 305                         return -EINVAL;
 306         }
 307
 308         return err;
 309 }
 310
 311 static void ixgbe_get_pauseparam(struct net_device *netdev,
 312                                  struct ethtool_pauseparam *pause)
 313 {
 314         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 315         struct ixgbe_hw *hw = &adapter->hw;
 316
 317         /*
 318          * Flow Control Autoneg isn't on if
 319          *  - we didn't ask for it OR
 320          *  - it failed, we know this by tx & rx being off
 321          */
 322         if (hw->fc.disable_fc_autoneg ||
 323             (hw->fc.current_mode == ixgbe_fc_none))
 324                 pause->autoneg = 0;
 325         else
 326                 pause->autoneg = 1;
 327
 328 #ifdef CONFIG_DCB
 329         if (hw->fc.current_mode == ixgbe_fc_pfc) {
 330                 pause->rx_pause = 0;
 331                 pause->tx_pause = 0;
 332         }
 333
 334 #endif
 335         if (hw->fc.current_mode == ixgbe_fc_rx_pause) {
 336                 pause->rx_pause = 1;
 337         } else if (hw->fc.current_mode == ixgbe_fc_tx_pause) {
 338                 pause->tx_pause = 1;
 339         } else if (hw->fc.current_mode == ixgbe_fc_full) {
 340                 pause->rx_pause = 1;
 341                 pause->tx_pause = 1;
 342         }
 343 }
 344
 345 static int ixgbe_set_pauseparam(struct net_device *netdev,
 346                                 struct ethtool_pauseparam *pause)
 347 {
 348         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 349         struct ixgbe_hw *hw = &adapter->hw;
 350         struct ixgbe_fc_info fc;
 351
 352 #ifdef CONFIG_DCB
 353         if (adapter->dcb_cfg.pfc_mode_enable ||
 354                 ((hw->mac.type == ixgbe_mac_82598EB) &&
 355                 (adapter->flags & IXGBE_FLAG_DCB_ENABLED)))
 356                 return -EINVAL;
 357
 358 #endif
 359
 360         fc = hw->fc;
 361
 362         if (pause->autoneg != AUTONEG_ENABLE)
 363                 fc.disable_fc_autoneg = true;
 364         else
 365                 fc.disable_fc_autoneg = false;
 366
 367         if (pause->rx_pause && pause->tx_pause)
 368                 fc.requested_mode = ixgbe_fc_full;
 369         else if (pause->rx_pause && !pause->tx_pause)
 370                 fc.requested_mode = ixgbe_fc_rx_pause;
 371         else if (!pause->rx_pause && pause->tx_pause)
 372                 fc.requested_mode = ixgbe_fc_tx_pause;
 373         else if (!pause->rx_pause && !pause->tx_pause)
 374                 fc.requested_mode = ixgbe_fc_none;
 375         else
 376                 return -EINVAL;
 377
 378 #ifdef CONFIG_DCB
 379         adapter->last_lfc_mode = fc.requested_mode;
 380 #endif
 381
 382         /* if the thing changed then we'll update and use new autoneg */
 383         if (memcmp(&fc, &hw->fc, sizeof(struct ixgbe_fc_info))) {
 384                 hw->fc = fc;
 385                 if (netif_running(netdev))
 386                         ixgbe_reinit_locked(adapter);
 387                 else
 388                         ixgbe_reset(adapter);
 389         }
 390
 391         return 0;
 392 }
 393
 394 static u32 ixgbe_get_rx_csum(struct net_device *netdev)
 395 {
 396         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 397         return (adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED);
 398 }
 399
 400 static int ixgbe_set_rx_csum(struct net_device *netdev, u32 data)
 401 {
 402         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 403         if (data)
 404                 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
 405         else
 406                 adapter->flags &= ~IXGBE_FLAG_RX_CSUM_ENABLED;
 407
 408         if (netif_running(netdev))
 409                 ixgbe_reinit_locked(adapter);
 410         else
 411                 ixgbe_reset(adapter);
 412
 413         return 0;
 414 }
 415
 416 static u32 ixgbe_get_tx_csum(struct net_device *netdev)
 417 {
 418         return (netdev->features & NETIF_F_IP_CSUM) != 0;
 419 }
 420
 421 static int ixgbe_set_tx_csum(struct net_device *netdev, u32 data)
 422 {
 423         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 424
 425         if (data) {
 426                 netdev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
 427                 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
 428                         netdev->features |= NETIF_F_SCTP_CSUM;
 429         } else {
 430                 netdev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
 431                 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
 432                         netdev->features &= ~NETIF_F_SCTP_CSUM;
 433         }
 434
 435         return 0;
 436 }
 437
 438 static int ixgbe_set_tso(struct net_device *netdev, u32 data)
 439 {
 440         if (data) {
 441                 netdev->features |= NETIF_F_TSO;
 442                 netdev->features |= NETIF_F_TSO6;
 443         } else {
 444                 netif_tx_stop_all_queues(netdev);
 445                 netdev->features &= ~NETIF_F_TSO;
 446                 netdev->features &= ~NETIF_F_TSO6;
 447                 netif_tx_start_all_queues(netdev);
 448         }
 449         return 0;
 450 }
 451
 452 static u32 ixgbe_get_msglevel(struct net_device *netdev)
 453 {
 454         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 455         return adapter->msg_enable;
 456 }
 457
 458 static void ixgbe_set_msglevel(struct net_device *netdev, u32 data)
 459 {
 460         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 461         adapter->msg_enable = data;
 462 }
 463
 464 static int ixgbe_get_regs_len(struct net_device *netdev)
 465 {
 466 #define IXGBE_REGS_LEN  1128
 467         return IXGBE_REGS_LEN * sizeof(u32);
 468 }
 469
 470 #define IXGBE_GET_STAT(_A_, _R_) _A_->stats._R_
 471
 472 static void ixgbe_get_regs(struct net_device *netdev,
 473                            struct ethtool_regs *regs, void *p)
 474 {
 475         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 476         struct ixgbe_hw *hw = &adapter->hw;
 477         u32 *regs_buff = p;
 478         u8 i;
 479
 480         memset(p, 0, IXGBE_REGS_LEN * sizeof(u32));
 481
 482         regs->version = (1 << 24) | hw->revision_id << 16 | hw->device_id;
 483
 484         /* General Registers */
 485         regs_buff[0] = IXGBE_READ_REG(hw, IXGBE_CTRL);
 486         regs_buff[1] = IXGBE_READ_REG(hw, IXGBE_STATUS);
 487         regs_buff[2] = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 488         regs_buff[3] = IXGBE_READ_REG(hw, IXGBE_ESDP);
 489         regs_buff[4] = IXGBE_READ_REG(hw, IXGBE_EODSDP);
 490         regs_buff[5] = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
 491         regs_buff[6] = IXGBE_READ_REG(hw, IXGBE_FRTIMER);
 492         regs_buff[7] = IXGBE_READ_REG(hw, IXGBE_TCPTIMER);
 493
 494         /* NVM Register */
 495         regs_buff[8] = IXGBE_READ_REG(hw, IXGBE_EEC);
 496         regs_buff[9] = IXGBE_READ_REG(hw, IXGBE_EERD);
 497         regs_buff[10] = IXGBE_READ_REG(hw, IXGBE_FLA);
 498         regs_buff[11] = IXGBE_READ_REG(hw, IXGBE_EEMNGCTL);
 499         regs_buff[12] = IXGBE_READ_REG(hw, IXGBE_EEMNGDATA);
 500         regs_buff[13] = IXGBE_READ_REG(hw, IXGBE_FLMNGCTL);
 501         regs_buff[14] = IXGBE_READ_REG(hw, IXGBE_FLMNGDATA);
 502         regs_buff[15] = IXGBE_READ_REG(hw, IXGBE_FLMNGCNT);
 503         regs_buff[16] = IXGBE_READ_REG(hw, IXGBE_FLOP);
 504         regs_buff[17] = IXGBE_READ_REG(hw, IXGBE_GRC);
 505
 506         /* Interrupt */
 507         /* don't read EICR because it can clear interrupt causes, instead
 508          * read EICS which is a shadow but doesn't clear EICR */
 509         regs_buff[18] = IXGBE_READ_REG(hw, IXGBE_EICS);
 510         regs_buff[19] = IXGBE_READ_REG(hw, IXGBE_EICS);
 511         regs_buff[20] = IXGBE_READ_REG(hw, IXGBE_EIMS);
 512         regs_buff[21] = IXGBE_READ_REG(hw, IXGBE_EIMC);
 513         regs_buff[22] = IXGBE_READ_REG(hw, IXGBE_EIAC);
 514         regs_buff[23] = IXGBE_READ_REG(hw, IXGBE_EIAM);
 515         regs_buff[24] = IXGBE_READ_REG(hw, IXGBE_EITR(0));
 516         regs_buff[25] = IXGBE_READ_REG(hw, IXGBE_IVAR(0));
 517         regs_buff[26] = IXGBE_READ_REG(hw, IXGBE_MSIXT);
 518         regs_buff[27] = IXGBE_READ_REG(hw, IXGBE_MSIXPBA);
 519         regs_buff[28] = IXGBE_READ_REG(hw, IXGBE_PBACL(0));
 520         regs_buff[29] = IXGBE_READ_REG(hw, IXGBE_GPIE);
 521
 522         /* Flow Control */
 523         regs_buff[30] = IXGBE_READ_REG(hw, IXGBE_PFCTOP);
 524         regs_buff[31] = IXGBE_READ_REG(hw, IXGBE_FCTTV(0));
 525         regs_buff[32] = IXGBE_READ_REG(hw, IXGBE_FCTTV(1));
 526         regs_buff[33] = IXGBE_READ_REG(hw, IXGBE_FCTTV(2));
 527         regs_buff[34] = IXGBE_READ_REG(hw, IXGBE_FCTTV(3));
 528         for (i = 0; i < 8; i++)
 529                 regs_buff[35 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTL(i));
 530         for (i = 0; i < 8; i++)
 531                 regs_buff[43 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTH(i));
 532         regs_buff[51] = IXGBE_READ_REG(hw, IXGBE_FCRTV);
 533         regs_buff[52] = IXGBE_READ_REG(hw, IXGBE_TFCS);
 534
 535         /* Receive DMA */
 536         for (i = 0; i < 64; i++)
 537                 regs_buff[53 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
 538         for (i = 0; i < 64; i++)
 539                 regs_buff[117 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
 540         for (i = 0; i < 64; i++)
 541                 regs_buff[181 + i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
 542         for (i = 0; i < 64; i++)
 543                 regs_buff[245 + i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
 544         for (i = 0; i < 64; i++)
 545                 regs_buff[309 + i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
 546         for (i = 0; i < 64; i++)
 547                 regs_buff[373 + i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
 548         for (i = 0; i < 16; i++)
 549                 regs_buff[437 + i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
 550         for (i = 0; i < 16; i++)
 551                 regs_buff[453 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
 552         regs_buff[469] = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
 553         for (i = 0; i < 8; i++)
 554                 regs_buff[470 + i] = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
 555         regs_buff[478] = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
 556         regs_buff[479] = IXGBE_READ_REG(hw, IXGBE_DROPEN);
 557
 558         /* Receive */
 559         regs_buff[480] = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
 560         regs_buff[481] = IXGBE_READ_REG(hw, IXGBE_RFCTL);
 561         for (i = 0; i < 16; i++)
 562                 regs_buff[482 + i] = IXGBE_READ_REG(hw, IXGBE_RAL(i));
 563         for (i = 0; i < 16; i++)
 564                 regs_buff[498 + i] = IXGBE_READ_REG(hw, IXGBE_RAH(i));
 565         regs_buff[514] = IXGBE_READ_REG(hw, IXGBE_PSRTYPE(0));
 566         regs_buff[515] = IXGBE_READ_REG(hw, IXGBE_FCTRL);
 567         regs_buff[516] = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
 568         regs_buff[517] = IXGBE_READ_REG(hw, IXGBE_MCSTCTRL);
 569         regs_buff[518] = IXGBE_READ_REG(hw, IXGBE_MRQC);
 570         regs_buff[519] = IXGBE_READ_REG(hw, IXGBE_VMD_CTL);
 571         for (i = 0; i < 8; i++)
 572                 regs_buff[520 + i] = IXGBE_READ_REG(hw, IXGBE_IMIR(i));
 573         for (i = 0; i < 8; i++)
 574                 regs_buff[528 + i] = IXGBE_READ_REG(hw, IXGBE_IMIREXT(i));
 575         regs_buff[536] = IXGBE_READ_REG(hw, IXGBE_IMIRVP);
 576
 577         /* Transmit */
 578         for (i = 0; i < 32; i++)
 579                 regs_buff[537 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
 580         for (i = 0; i < 32; i++)
 581                 regs_buff[569 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
 582         for (i = 0; i < 32; i++)
 583                 regs_buff[601 + i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
 584         for (i = 0; i < 32; i++)
 585                 regs_buff[633 + i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
 586         for (i = 0; i < 32; i++)
 587                 regs_buff[665 + i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
 588         for (i = 0; i < 32; i++)
 589                 regs_buff[697 + i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
 590         for (i = 0; i < 32; i++)
 591                 regs_buff[729 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAL(i));
 592         for (i = 0; i < 32; i++)
 593                 regs_buff[761 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAH(i));
 594         regs_buff[793] = IXGBE_READ_REG(hw, IXGBE_DTXCTL);
 595         for (i = 0; i < 16; i++)
 596                 regs_buff[794 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i));
 597         regs_buff[810] = IXGBE_READ_REG(hw, IXGBE_TIPG);
 598         for (i = 0; i < 8; i++)
 599                 regs_buff[811 + i] = IXGBE_READ_REG(hw, IXGBE_TXPBSIZE(i));
 600         regs_buff[819] = IXGBE_READ_REG(hw, IXGBE_MNGTXMAP);
 601
 602         /* Wake Up */
 603         regs_buff[820] = IXGBE_READ_REG(hw, IXGBE_WUC);
 604         regs_buff[821] = IXGBE_READ_REG(hw, IXGBE_WUFC);
 605         regs_buff[822] = IXGBE_READ_REG(hw, IXGBE_WUS);
 606         regs_buff[823] = IXGBE_READ_REG(hw, IXGBE_IPAV);
 607         regs_buff[824] = IXGBE_READ_REG(hw, IXGBE_IP4AT);
 608         regs_buff[825] = IXGBE_READ_REG(hw, IXGBE_IP6AT);
 609         regs_buff[826] = IXGBE_READ_REG(hw, IXGBE_WUPL);
 610         regs_buff[827] = IXGBE_READ_REG(hw, IXGBE_WUPM);
 611         regs_buff[828] = IXGBE_READ_REG(hw, IXGBE_FHFT(0));
 612
 613         regs_buff[829] = IXGBE_READ_REG(hw, IXGBE_RMCS);
 614         regs_buff[830] = IXGBE_READ_REG(hw, IXGBE_DPMCS);
 615         regs_buff[831] = IXGBE_READ_REG(hw, IXGBE_PDPMCS);
 616         regs_buff[832] = IXGBE_READ_REG(hw, IXGBE_RUPPBMR);
 617         for (i = 0; i < 8; i++)
 618                 regs_buff[833 + i] = IXGBE_READ_REG(hw, IXGBE_RT2CR(i));
 619         for (i = 0; i < 8; i++)
 620                 regs_buff[841 + i] = IXGBE_READ_REG(hw, IXGBE_RT2SR(i));
 621         for (i = 0; i < 8; i++)
 622                 regs_buff[849 + i] = IXGBE_READ_REG(hw, IXGBE_TDTQ2TCCR(i));
 623         for (i = 0; i < 8; i++)
 624                 regs_buff[857 + i] = IXGBE_READ_REG(hw, IXGBE_TDTQ2TCSR(i));
 625         for (i = 0; i < 8; i++)
 626                 regs_buff[865 + i] = IXGBE_READ_REG(hw, IXGBE_TDPT2TCCR(i));
 627         for (i = 0; i < 8; i++)
 628                 regs_buff[873 + i] = IXGBE_READ_REG(hw, IXGBE_TDPT2TCSR(i));
 629
 630         /* Statistics */
 631         regs_buff[881] = IXGBE_GET_STAT(adapter, crcerrs);
 632         regs_buff[882] = IXGBE_GET_STAT(adapter, illerrc);
 633         regs_buff[883] = IXGBE_GET_STAT(adapter, errbc);
 634         regs_buff[884] = IXGBE_GET_STAT(adapter, mspdc);
 635         for (i = 0; i < 8; i++)
 636                 regs_buff[885 + i] = IXGBE_GET_STAT(adapter, mpc[i]);
 637         regs_buff[893] = IXGBE_GET_STAT(adapter, mlfc);
 638         regs_buff[894] = IXGBE_GET_STAT(adapter, mrfc);
 639         regs_buff[895] = IXGBE_GET_STAT(adapter, rlec);
 640         regs_buff[896] = IXGBE_GET_STAT(adapter, lxontxc);
 641         regs_buff[897] = IXGBE_GET_STAT(adapter, lxonrxc);
 642         regs_buff[898] = IXGBE_GET_STAT(adapter, lxofftxc);
 643         regs_buff[899] = IXGBE_GET_STAT(adapter, lxoffrxc);
 644         for (i = 0; i < 8; i++)
 645                 regs_buff[900 + i] = IXGBE_GET_STAT(adapter, pxontxc[i]);
 646         for (i = 0; i < 8; i++)
 647                 regs_buff[908 + i] = IXGBE_GET_STAT(adapter, pxonrxc[i]);
 648         for (i = 0; i < 8; i++)
 649                 regs_buff[916 + i] = IXGBE_GET_STAT(adapter, pxofftxc[i]);
 650         for (i = 0; i < 8; i++)
 651                 regs_buff[924 + i] = IXGBE_GET_STAT(adapter, pxoffrxc[i]);
 652         regs_buff[932] = IXGBE_GET_STAT(adapter, prc64);
 653         regs_buff[933] = IXGBE_GET_STAT(adapter, prc127);
 654         regs_buff[934] = IXGBE_GET_STAT(adapter, prc255);
 655         regs_buff[935] = IXGBE_GET_STAT(adapter, prc511);
 656         regs_buff[936] = IXGBE_GET_STAT(adapter, prc1023);
 657         regs_buff[937] = IXGBE_GET_STAT(adapter, prc1522);
 658         regs_buff[938] = IXGBE_GET_STAT(adapter, gprc);
 659         regs_buff[939] = IXGBE_GET_STAT(adapter, bprc);
 660         regs_buff[940] = IXGBE_GET_STAT(adapter, mprc);
 661         regs_buff[941] = IXGBE_GET_STAT(adapter, gptc);
 662         regs_buff[942] = IXGBE_GET_STAT(adapter, gorc);
 663         regs_buff[944] = IXGBE_GET_STAT(adapter, gotc);
 664         for (i = 0; i < 8; i++)
 665                 regs_buff[946 + i] = IXGBE_GET_STAT(adapter, rnbc[i]);
 666         regs_buff[954] = IXGBE_GET_STAT(adapter, ruc);
 667         regs_buff[955] = IXGBE_GET_STAT(adapter, rfc);
 668         regs_buff[956] = IXGBE_GET_STAT(adapter, roc);
 669         regs_buff[957] = IXGBE_GET_STAT(adapter, rjc);
 670         regs_buff[958] = IXGBE_GET_STAT(adapter, mngprc);
 671         regs_buff[959] = IXGBE_GET_STAT(adapter, mngpdc);
 672         regs_buff[960] = IXGBE_GET_STAT(adapter, mngptc);
 673         regs_buff[961] = IXGBE_GET_STAT(adapter, tor);
 674         regs_buff[963] = IXGBE_GET_STAT(adapter, tpr);
 675         regs_buff[964] = IXGBE_GET_STAT(adapter, tpt);
 676         regs_buff[965] = IXGBE_GET_STAT(adapter, ptc64);
 677         regs_buff[966] = IXGBE_GET_STAT(adapter, ptc127);
 678         regs_buff[967] = IXGBE_GET_STAT(adapter, ptc255);
 679         regs_buff[968] = IXGBE_GET_STAT(adapter, ptc511);
 680         regs_buff[969] = IXGBE_GET_STAT(adapter, ptc1023);
 681         regs_buff[970] = IXGBE_GET_STAT(adapter, ptc1522);
 682         regs_buff[971] = IXGBE_GET_STAT(adapter, mptc);
 683         regs_buff[972] = IXGBE_GET_STAT(adapter, bptc);
 684         regs_buff[973] = IXGBE_GET_STAT(adapter, xec);
 685         for (i = 0; i < 16; i++)
 686                 regs_buff[974 + i] = IXGBE_GET_STAT(adapter, qprc[i]);
 687         for (i = 0; i < 16; i++)
 688                 regs_buff[990 + i] = IXGBE_GET_STAT(adapter, qptc[i]);
 689         for (i = 0; i < 16; i++)
 690                 regs_buff[1006 + i] = IXGBE_GET_STAT(adapter, qbrc[i]);
 691         for (i = 0; i < 16; i++)
 692                 regs_buff[1022 + i] = IXGBE_GET_STAT(adapter, qbtc[i]);
 693
 694         /* MAC */
 695         regs_buff[1038] = IXGBE_READ_REG(hw, IXGBE_PCS1GCFIG);
 696         regs_buff[1039] = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
 697         regs_buff[1040] = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
 698         regs_buff[1041] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG0);
 699         regs_buff[1042] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG1);
 700         regs_buff[1043] = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
 701         regs_buff[1044] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
 702         regs_buff[1045] = IXGBE_READ_REG(hw, IXGBE_PCS1GANNP);
 703         regs_buff[1046] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLPNP);
 704         regs_buff[1047] = IXGBE_READ_REG(hw, IXGBE_HLREG0);
 705         regs_buff[1048] = IXGBE_READ_REG(hw, IXGBE_HLREG1);
 706         regs_buff[1049] = IXGBE_READ_REG(hw, IXGBE_PAP);
 707         regs_buff[1050] = IXGBE_READ_REG(hw, IXGBE_MACA);
 708         regs_buff[1051] = IXGBE_READ_REG(hw, IXGBE_APAE);
 709         regs_buff[1052] = IXGBE_READ_REG(hw, IXGBE_ARD);
 710         regs_buff[1053] = IXGBE_READ_REG(hw, IXGBE_AIS);
 711         regs_buff[1054] = IXGBE_READ_REG(hw, IXGBE_MSCA);
 712         regs_buff[1055] = IXGBE_READ_REG(hw, IXGBE_MSRWD);
 713         regs_buff[1056] = IXGBE_READ_REG(hw, IXGBE_MLADD);
 714         regs_buff[1057] = IXGBE_READ_REG(hw, IXGBE_MHADD);
 715         regs_buff[1058] = IXGBE_READ_REG(hw, IXGBE_TREG);
 716         regs_buff[1059] = IXGBE_READ_REG(hw, IXGBE_PCSS1);
 717         regs_buff[1060] = IXGBE_READ_REG(hw, IXGBE_PCSS2);
 718         regs_buff[1061] = IXGBE_READ_REG(hw, IXGBE_XPCSS);
 719         regs_buff[1062] = IXGBE_READ_REG(hw, IXGBE_SERDESC);
 720         regs_buff[1063] = IXGBE_READ_REG(hw, IXGBE_MACS);
 721         regs_buff[1064] = IXGBE_READ_REG(hw, IXGBE_AUTOC);
 722         regs_buff[1065] = IXGBE_READ_REG(hw, IXGBE_LINKS);
 723         regs_buff[1066] = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
 724         regs_buff[1067] = IXGBE_READ_REG(hw, IXGBE_AUTOC3);
 725         regs_buff[1068] = IXGBE_READ_REG(hw, IXGBE_ANLP1);
 726         regs_buff[1069] = IXGBE_READ_REG(hw, IXGBE_ANLP2);
 727         regs_buff[1070] = IXGBE_READ_REG(hw, IXGBE_ATLASCTL);
 728
 729         /* Diagnostic */
 730         regs_buff[1071] = IXGBE_READ_REG(hw, IXGBE_RDSTATCTL);
 731         for (i = 0; i < 8; i++)
 732                 regs_buff[1072 + i] = IXGBE_READ_REG(hw, IXGBE_RDSTAT(i));
 733         regs_buff[1080] = IXGBE_READ_REG(hw, IXGBE_RDHMPN);
 734         for (i = 0; i < 4; i++)
 735                 regs_buff[1081 + i] = IXGBE_READ_REG(hw, IXGBE_RIC_DW(i));
 736         regs_buff[1085] = IXGBE_READ_REG(hw, IXGBE_RDPROBE);
 737         regs_buff[1086] = IXGBE_READ_REG(hw, IXGBE_TDSTATCTL);
 738         for (i = 0; i < 8; i++)
 739                 regs_buff[1087 + i] = IXGBE_READ_REG(hw, IXGBE_TDSTAT(i));
 740         regs_buff[1095] = IXGBE_READ_REG(hw, IXGBE_TDHMPN);
 741         for (i = 0; i < 4; i++)
 742                 regs_buff[1096 + i] = IXGBE_READ_REG(hw, IXGBE_TIC_DW(i));
 743         regs_buff[1100] = IXGBE_READ_REG(hw, IXGBE_TDPROBE);
 744         regs_buff[1101] = IXGBE_READ_REG(hw, IXGBE_TXBUFCTRL);
 745         regs_buff[1102] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA0);
 746         regs_buff[1103] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA1);
 747         regs_buff[1104] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA2);
 748         regs_buff[1105] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA3);
 749         regs_buff[1106] = IXGBE_READ_REG(hw, IXGBE_RXBUFCTRL);
 750         regs_buff[1107] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA0);
 751         regs_buff[1108] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA1);
 752         regs_buff[1109] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA2);
 753         regs_buff[1110] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA3);
 754         for (i = 0; i < 8; i++)
 755                 regs_buff[1111 + i] = IXGBE_READ_REG(hw, IXGBE_PCIE_DIAG(i));
 756         regs_buff[1119] = IXGBE_READ_REG(hw, IXGBE_RFVAL);
 757         regs_buff[1120] = IXGBE_READ_REG(hw, IXGBE_MDFTC1);
 758         regs_buff[1121] = IXGBE_READ_REG(hw, IXGBE_MDFTC2);
 759         regs_buff[1122] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO1);
 760         regs_buff[1123] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO2);
 761         regs_buff[1124] = IXGBE_READ_REG(hw, IXGBE_MDFTS);
 762         regs_buff[1125] = IXGBE_READ_REG(hw, IXGBE_PCIEECCCTL);
 763         regs_buff[1126] = IXGBE_READ_REG(hw, IXGBE_PBTXECC);
 764         regs_buff[1127] = IXGBE_READ_REG(hw, IXGBE_PBRXECC);
 765 }
 766
 767 static int ixgbe_get_eeprom_len(struct net_device *netdev)
 768 {
 769         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 770         return adapter->hw.eeprom.word_size * 2;
 771 }
 772
 773 static int ixgbe_get_eeprom(struct net_device *netdev,
 774                             struct ethtool_eeprom *eeprom, u8 *bytes)
 775 {
 776         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 777         struct ixgbe_hw *hw = &adapter->hw;
 778         u16 *eeprom_buff;
 779         int first_word, last_word, eeprom_len;
 780         int ret_val = 0;
 781         u16 i;
 782
 783         if (eeprom->len == 0)
 784                 return -EINVAL;
 785
 786         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
 787
 788         first_word = eeprom->offset >> 1;
 789         last_word = (eeprom->offset + eeprom->len - 1) >> 1;
 790         eeprom_len = last_word - first_word + 1;
 791
 792         eeprom_buff = kmalloc(sizeof(u16) * eeprom_len, GFP_KERNEL);
 793         if (!eeprom_buff)
 794                 return -ENOMEM;
 795
 796         for (i = 0; i < eeprom_len; i++) {
 797                 if ((ret_val = hw->eeprom.ops.read(hw, first_word + i,
 798                     &eeprom_buff[i])))
 799                         break;
 800         }
 801
 802         /* Device's eeprom is always little-endian, word addressable */
 803         for (i = 0; i < eeprom_len; i++)
 804                 le16_to_cpus(&eeprom_buff[i]);
 805
 806         memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1), eeprom->len);
 807         kfree(eeprom_buff);
 808
 809         return ret_val;
 810 }
 811
 812 static void ixgbe_get_drvinfo(struct net_device *netdev,
 813                               struct ethtool_drvinfo *drvinfo)
 814 {
 815         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 816         char firmware_version[32];
 817
 818         strncpy(drvinfo->driver, ixgbe_driver_name, 32);
 819         strncpy(drvinfo->version, ixgbe_driver_version, 32);
 820
 821         sprintf(firmware_version, "%d.%d-%d",
 822                 (adapter->eeprom_version & 0xF000) >> 12,
 823                 (adapter->eeprom_version & 0x0FF0) >> 4,
 824                 adapter->eeprom_version & 0x000F);
 825
 826         strncpy(drvinfo->fw_version, firmware_version, 32);
 827         strncpy(drvinfo->bus_info, pci_name(adapter->pdev), 32);
 828         drvinfo->n_stats = IXGBE_STATS_LEN;
 829         drvinfo->testinfo_len = IXGBE_TEST_LEN;
 830         drvinfo->regdump_len = ixgbe_get_regs_len(netdev);
 831 }
 832
 833 static void ixgbe_get_ringparam(struct net_device *netdev,
 834                                 struct ethtool_ringparam *ring)
 835 {
 836         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 837         struct ixgbe_ring *tx_ring = adapter->tx_ring;
 838         struct ixgbe_ring *rx_ring = adapter->rx_ring;
 839
 840         ring->rx_max_pending = IXGBE_MAX_RXD;
 841         ring->tx_max_pending = IXGBE_MAX_TXD;
 842         ring->rx_mini_max_pending = 0;
 843         ring->rx_jumbo_max_pending = 0;
 844         ring->rx_pending = rx_ring->count;
 845         ring->tx_pending = tx_ring->count;
 846         ring->rx_mini_pending = 0;
 847         ring->rx_jumbo_pending = 0;
 848 }
 849
 850 static int ixgbe_set_ringparam(struct net_device *netdev,
 851                                struct ethtool_ringparam *ring)
 852 {
 853         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 854         struct ixgbe_ring *temp_tx_ring, *temp_rx_ring;
 855         int i, err = 0;
 856         u32 new_rx_count, new_tx_count;
 857         bool need_update = false;
 858
 859         if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
 860                 return -EINVAL;
 861
 862         new_rx_count = max(ring->rx_pending, (u32)IXGBE_MIN_RXD);
 863         new_rx_count = min(new_rx_count, (u32)IXGBE_MAX_RXD);
 864         new_rx_count = ALIGN(new_rx_count, IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE);
 865
 866         new_tx_count = max(ring->tx_pending, (u32)IXGBE_MIN_TXD);
 867         new_tx_count = min(new_tx_count, (u32)IXGBE_MAX_TXD);
 868         new_tx_count = ALIGN(new_tx_count, IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE);
 869
 870         if ((new_tx_count == adapter->tx_ring->count) &&
 871             (new_rx_count == adapter->rx_ring->count)) {
 872                 /* nothing to do */
 873                 return 0;
 874         }
 875
 876         while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
 877                 msleep(1);
 878
 879         if (!netif_running(adapter->netdev)) {
 880                 for (i = 0; i < adapter->num_tx_queues; i++)
 881                         adapter->tx_ring[i].count = new_tx_count;
 882                 for (i = 0; i < adapter->num_rx_queues; i++)
 883                         adapter->rx_ring[i].count = new_rx_count;
 884                 adapter->tx_ring_count = new_tx_count;
 885                 adapter->rx_ring_count = new_rx_count;
 886                 goto err_setup;
 887         }
 888
 889         temp_tx_ring = kcalloc(adapter->num_tx_queues,
 890                                sizeof(struct ixgbe_ring), GFP_KERNEL);
 891         if (!temp_tx_ring) {
 892                 err = -ENOMEM;
 893                 goto err_setup;
 894         }
 895
 896         if (new_tx_count != adapter->tx_ring_count) {
 897                 memcpy(temp_tx_ring, adapter->tx_ring,
 898                        adapter->num_tx_queues * sizeof(struct ixgbe_ring));
 899                 for (i = 0; i < adapter->num_tx_queues; i++) {
 900                         temp_tx_ring[i].count = new_tx_count;
 901                         err = ixgbe_setup_tx_resources(adapter,
 902                                                        &temp_tx_ring[i]);
 903                         if (err) {
 904                                 while (i) {
 905                                         i--;
 906                                         ixgbe_free_tx_resources(adapter,
 907                                                                 &temp_tx_ring[i]);
 908                                 }
 909                                 goto err_setup;
 910                         }
 911                 }
 912                 need_update = true;
 913         }
 914
 915         temp_rx_ring = kcalloc(adapter->num_rx_queues,
 916                                sizeof(struct ixgbe_ring), GFP_KERNEL);
 917         if ((!temp_rx_ring) && (need_update)) {
 918                 for (i = 0; i < adapter->num_tx_queues; i++)
 919                         ixgbe_free_tx_resources(adapter, &temp_tx_ring[i]);
 920                 kfree(temp_tx_ring);
 921                 err = -ENOMEM;
 922                 goto err_setup;
 923         }
 924
 925         if (new_rx_count != adapter->rx_ring_count) {
 926                 memcpy(temp_rx_ring, adapter->rx_ring,
 927                        adapter->num_rx_queues * sizeof(struct ixgbe_ring));
 928                 for (i = 0; i < adapter->num_rx_queues; i++) {
 929                         temp_rx_ring[i].count = new_rx_count;
 930                         err = ixgbe_setup_rx_resources(adapter,
 931                                                        &temp_rx_ring[i]);
 932                         if (err) {
 933                                 while (i) {
 934                                         i--;
 935                                         ixgbe_free_rx_resources(adapter,
 936                                                               &temp_rx_ring[i]);
 937                                 }
 938                                 goto err_setup;
 939                         }
 940                 }
 941                 need_update = true;
 942         }
 943
 944         /* if rings need to be updated, here's the place to do it in one shot */
 945         if (need_update) {
 946                 ixgbe_down(adapter);
 947
 948                 /* tx */
 949                 if (new_tx_count != adapter->tx_ring_count) {
 950                         kfree(adapter->tx_ring);
 951                         adapter->tx_ring = temp_tx_ring;
 952                         temp_tx_ring = NULL;
 953                         adapter->tx_ring_count = new_tx_count;
 954                 }
 955
 956                 /* rx */
 957                 if (new_rx_count != adapter->rx_ring_count) {
 958                         kfree(adapter->rx_ring);
 959                         adapter->rx_ring = temp_rx_ring;
 960                         temp_rx_ring = NULL;
 961                         adapter->rx_ring_count = new_rx_count;
 962                 }
 963                 ixgbe_up(adapter);
 964         }
 965 err_setup:
 966         clear_bit(__IXGBE_RESETTING, &adapter->state);
 967         return err;
 968 }
 969
 970 static int ixgbe_get_sset_count(struct net_device *netdev, int sset)
 971 {
 972         switch (sset) {
 973         case ETH_SS_TEST:
 974                 return IXGBE_TEST_LEN;
 975         case ETH_SS_STATS:
 976                 return IXGBE_STATS_LEN;
 977         default:
 978                 return -EOPNOTSUPP;
 979         }
 980 }
 981
 982 static void ixgbe_get_ethtool_stats(struct net_device *netdev,
 983                                     struct ethtool_stats *stats, u64 *data)
 984 {
 985         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 986         u64 *queue_stat;
 987         int stat_count = sizeof(struct ixgbe_queue_stats) / sizeof(u64);
 988         int j, k;
 989         int i;
 990         char *p = NULL;
 991
 992         ixgbe_update_stats(adapter);
 993         dev_get_stats(netdev);
 994         for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) {
 995                 switch (ixgbe_gstrings_stats[i].type) {
 996                 case NETDEV_STATS:
 997                         p = (char *) netdev +
 998                                         ixgbe_gstrings_stats[i].stat_offset;
 999                         break;
1000                 case IXGBE_STATS:
1001                         p = (char *) adapter +
1002                                         ixgbe_gstrings_stats[i].stat_offset;
1003                         break;
1004                 }
1005
1006                 data[i] = (ixgbe_gstrings_stats[i].sizeof_stat ==
1007                            sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
1008         }
1009         for (j = 0; j < adapter->num_tx_queues; j++) {
1010                 queue_stat = (u64 *)&adapter->tx_ring[j].stats;
1011                 for (k = 0; k < stat_count; k++)
1012                         data[i + k] = queue_stat[k];
1013                 i += k;
1014         }
1015         for (j = 0; j < adapter->num_rx_queues; j++) {
1016                 queue_stat = (u64 *)&adapter->rx_ring[j].stats;
1017                 for (k = 0; k < stat_count; k++)
1018                         data[i + k] = queue_stat[k];
1019                 i += k;
1020         }
1021         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
1022                 for (j = 0; j < MAX_TX_PACKET_BUFFERS; j++) {
1023                         data[i++] = adapter->stats.pxontxc[j];
1024                         data[i++] = adapter->stats.pxofftxc[j];
1025                 }
1026                 for (j = 0; j < MAX_RX_PACKET_BUFFERS; j++) {
1027                         data[i++] = adapter->stats.pxonrxc[j];
1028                         data[i++] = adapter->stats.pxoffrxc[j];
1029                 }
1030         }
1031 }
1032
1033 static void ixgbe_get_strings(struct net_device *netdev, u32 stringset,
1034                               u8 *data)
1035 {
1036         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1037         char *p = (char *)data;
1038         int i;
1039
1040         switch (stringset) {
1041         case ETH_SS_TEST:
1042                 memcpy(data, *ixgbe_gstrings_test,
1043                        IXGBE_TEST_LEN * ETH_GSTRING_LEN);
1044                 break;
1045         case ETH_SS_STATS:
1046                 for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) {
1047                         memcpy(p, ixgbe_gstrings_stats[i].stat_string,
1048                                ETH_GSTRING_LEN);
1049                         p += ETH_GSTRING_LEN;
1050                 }
1051                 for (i = 0; i < adapter->num_tx_queues; i++) {
1052                         sprintf(p, "tx_queue_%u_packets", i);
1053                         p += ETH_GSTRING_LEN;
1054                         sprintf(p, "tx_queue_%u_bytes", i);
1055                         p += ETH_GSTRING_LEN;
1056                 }
1057                 for (i = 0; i < adapter->num_rx_queues; i++) {
1058                         sprintf(p, "rx_queue_%u_packets", i);
1059                         p += ETH_GSTRING_LEN;
1060                         sprintf(p, "rx_queue_%u_bytes", i);
1061                         p += ETH_GSTRING_LEN;
1062                 }
1063                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
1064                         for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
1065                                 sprintf(p, "tx_pb_%u_pxon", i);
1066                                 p += ETH_GSTRING_LEN;
1067                                 sprintf(p, "tx_pb_%u_pxoff", i);
1068                                 p += ETH_GSTRING_LEN;
1069                         }
1070                         for (i = 0; i < MAX_RX_PACKET_BUFFERS; i++) {
1071                                 sprintf(p, "rx_pb_%u_pxon", i);
1072                                 p += ETH_GSTRING_LEN;
1073                                 sprintf(p, "rx_pb_%u_pxoff", i);
1074                                 p += ETH_GSTRING_LEN;
1075                         }
1076                 }
1077                 /* BUG_ON(p - data != IXGBE_STATS_LEN * ETH_GSTRING_LEN); */
1078                 break;
1079         }
1080 }
1081
1082 static int ixgbe_link_test(struct ixgbe_adapter *adapter, u64 *data)
1083 {
1084         struct ixgbe_hw *hw = &adapter->hw;
1085         bool link_up;
1086         u32 link_speed = 0;
1087         *data = 0;
1088
1089         hw->mac.ops.check_link(hw, &link_speed, &link_up, true);
1090         if (link_up)
1091                 return *data;
1092         else
1093                 *data = 1;
1094         return *data;
1095 }
1096
1097 /* ethtool register test data */
1098 struct ixgbe_reg_test {
1099         u16 reg;
1100         u8  array_len;
1101         u8  test_type;
1102         u32 mask;
1103         u32 write;
1104 };
1105
1106 /* In the hardware, registers are laid out either singly, in arrays
1107  * spaced 0x40 bytes apart, or in contiguous tables.  We assume
1108  * most tests take place on arrays or single registers (handled
1109  * as a single-element array) and special-case the tables.
1110  * Table tests are always pattern tests.
1111  *
1112  * We also make provision for some required setup steps by specifying
1113  * registers to be written without any read-back testing.
1114  */
1115
1116 #define PATTERN_TEST    1
1117 #define SET_READ_TEST   2
1118 #define WRITE_NO_TEST   3
1119 #define TABLE32_TEST    4
1120 #define TABLE64_TEST_LO 5
1121 #define TABLE64_TEST_HI 6
1122
1123 /* default 82599 register test */
1124 static struct ixgbe_reg_test reg_test_82599[] = {
1125         { IXGBE_FCRTL_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1126         { IXGBE_FCRTH_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1127         { IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1128         { IXGBE_VLNCTRL, 1, PATTERN_TEST, 0x00000000, 0x00000000 },
1129         { IXGBE_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFF80 },
1130         { IXGBE_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1131         { IXGBE_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1132         { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE },
1133         { IXGBE_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1134         { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 },
1135         { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1136         { IXGBE_FCTTV(0), 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1137         { IXGBE_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1138         { IXGBE_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1139         { IXGBE_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFF80 },
1140         { IXGBE_RXCTRL, 1, SET_READ_TEST, 0x00000001, 0x00000001 },
1141         { IXGBE_RAL(0), 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1142         { IXGBE_RAL(0), 16, TABLE64_TEST_HI, 0x8001FFFF, 0x800CFFFF },
1143         { IXGBE_MTA(0), 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1144         { 0, 0, 0, 0 }
1145 };
1146
1147 /* default 82598 register test */
1148 static struct ixgbe_reg_test reg_test_82598[] = {
1149         { IXGBE_FCRTL(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1150         { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1151         { IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1152         { IXGBE_VLNCTRL, 1, PATTERN_TEST, 0x00000000, 0x00000000 },
1153         { IXGBE_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1154         { IXGBE_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1155         { IXGBE_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1156         /* Enable all four RX queues before testing. */
1157         { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE },
1158         /* RDH is read-only for 82598, only test RDT. */
1159         { IXGBE_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1160         { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 },
1161         { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1162         { IXGBE_FCTTV(0), 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1163         { IXGBE_TIPG, 1, PATTERN_TEST, 0x000000FF, 0x000000FF },
1164         { IXGBE_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1165         { IXGBE_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1166         { IXGBE_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1167         { IXGBE_RXCTRL, 1, SET_READ_TEST, 0x00000003, 0x00000003 },
1168         { IXGBE_DTXCTL, 1, SET_READ_TEST, 0x00000005, 0x00000005 },
1169         { IXGBE_RAL(0), 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1170         { IXGBE_RAL(0), 16, TABLE64_TEST_HI, 0x800CFFFF, 0x800CFFFF },
1171         { IXGBE_MTA(0), 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1172         { 0, 0, 0, 0 }
1173 };
1174
1175 #define REG_PATTERN_TEST(R, M, W)                                             \
1176 {                                                                             \
1177         u32 pat, val, before;                                                 \
1178         const u32 _test[] = {0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF}; \
1179         for (pat = 0; pat < ARRAY_SIZE(_test); pat++) {                       \
1180                 before = readl(adapter->hw.hw_addr + R);                      \
1181                 writel((_test[pat] & W), (adapter->hw.hw_addr + R));          \
1182                 val = readl(adapter->hw.hw_addr + R);                         \
1183                 if (val != (_test[pat] & W & M)) {                            \
1184                         DPRINTK(DRV, ERR, "pattern test reg %04X failed: got "\
1185                                           "0x%08X expected 0x%08X\n",         \
1186                                 R, val, (_test[pat] & W & M));                \
1187                         *data = R;                                            \
1188                         writel(before, adapter->hw.hw_addr + R);              \
1189                         return 1;                                             \
1190                 }                                                             \
1191                 writel(before, adapter->hw.hw_addr + R);                      \
1192         }                                                                     \
1193 }
1194
1195 #define REG_SET_AND_CHECK(R, M, W)                                            \
1196 {                                                                             \
1197         u32 val, before;                                                      \
1198         before = readl(adapter->hw.hw_addr + R);                              \
1199         writel((W & M), (adapter->hw.hw_addr + R));                           \
1200         val = readl(adapter->hw.hw_addr + R);                                 \
1201         if ((W & M) != (val & M)) {                                           \
1202                 DPRINTK(DRV, ERR, "set/check reg %04X test failed: got 0x%08X "\
1203                                  "expected 0x%08X\n", R, (val & M), (W & M)); \
1204                 *data = R;                                                    \
1205                 writel(before, (adapter->hw.hw_addr + R));                    \
1206                 return 1;                                                     \
1207         }                                                                     \
1208         writel(before, (adapter->hw.hw_addr + R));                            \
1209 }
1210
1211 static int ixgbe_reg_test(struct ixgbe_adapter *adapter, u64 *data)
1212 {
1213         struct ixgbe_reg_test *test;
1214         u32 value, before, after;
1215         u32 i, toggle;
1216
1217         if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1218                 toggle = 0x7FFFF30F;
1219                 test = reg_test_82599;
1220         } else {
1221                 toggle = 0x7FFFF3FF;
1222                 test = reg_test_82598;
1223         }
1224
1225         /*
1226          * Because the status register is such a special case,
1227          * we handle it separately from the rest of the register
1228          * tests.  Some bits are read-only, some toggle, and some
1229          * are writeable on newer MACs.
1230          */
1231         before = IXGBE_READ_REG(&adapter->hw, IXGBE_STATUS);
1232         value = (IXGBE_READ_REG(&adapter->hw, IXGBE_STATUS) & toggle);
1233         IXGBE_WRITE_REG(&adapter->hw, IXGBE_STATUS, toggle);
1234         after = IXGBE_READ_REG(&adapter->hw, IXGBE_STATUS) & toggle;
1235         if (value != after) {
1236                 DPRINTK(DRV, ERR, "failed STATUS register test got: "
1237                         "0x%08X expected: 0x%08X\n", after, value);
1238                 *data = 1;
1239                 return 1;
1240         }
1241         /* restore previous status */
1242         IXGBE_WRITE_REG(&adapter->hw, IXGBE_STATUS, before);
1243
1244         /*
1245          * Perform the remainder of the register test, looping through
1246          * the test table until we either fail or reach the null entry.
1247          */
1248         while (test->reg) {
1249                 for (i = 0; i < test->array_len; i++) {
1250                         switch (test->test_type) {
1251                         case PATTERN_TEST:
1252                                 REG_PATTERN_TEST(test->reg + (i * 0x40),
1253                                                 test->mask,
1254                                                 test->write);
1255                                 break;
1256                         case SET_READ_TEST:
1257                                 REG_SET_AND_CHECK(test->reg + (i * 0x40),
1258                                                 test->mask,
1259                                                 test->write);
1260                                 break;
1261                         case WRITE_NO_TEST:
1262                                 writel(test->write,
1263                                        (adapter->hw.hw_addr + test->reg)
1264                                        + (i * 0x40));
1265                                 break;
1266                         case TABLE32_TEST:
1267                                 REG_PATTERN_TEST(test->reg + (i * 4),
1268                                                 test->mask,
1269                                                 test->write);
1270                                 break;
1271                         case TABLE64_TEST_LO:
1272                                 REG_PATTERN_TEST(test->reg + (i * 8),
1273                                                 test->mask,
1274                                                 test->write);
1275                                 break;
1276                         case TABLE64_TEST_HI:
1277                                 REG_PATTERN_TEST((test->reg + 4) + (i * 8),
1278                                                 test->mask,
1279                                                 test->write);
1280                                 break;
1281                         }
1282                 }
1283                 test++;
1284         }
1285
1286         *data = 0;
1287         return 0;
1288 }
1289
1290 static int ixgbe_eeprom_test(struct ixgbe_adapter *adapter, u64 *data)
1291 {
1292         struct ixgbe_hw *hw = &adapter->hw;
1293         if (hw->eeprom.ops.validate_checksum(hw, NULL))
1294                 *data = 1;
1295         else
1296                 *data = 0;
1297         return *data;
1298 }
1299
1300 static irqreturn_t ixgbe_test_intr(int irq, void *data)
1301 {
1302         struct net_device *netdev = (struct net_device *) data;
1303         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1304
1305         adapter->test_icr |= IXGBE_READ_REG(&adapter->hw, IXGBE_EICR);
1306
1307         return IRQ_HANDLED;
1308 }
1309
1310 static int ixgbe_intr_test(struct ixgbe_adapter *adapter, u64 *data)
1311 {
1312         struct net_device *netdev = adapter->netdev;
1313         u32 mask, i = 0, shared_int = true;
1314         u32 irq = adapter->pdev->irq;
1315
1316         *data = 0;
1317
1318         /* Hook up test interrupt handler just for this test */
1319         if (adapter->msix_entries) {
1320                 /* NOTE: we don't test MSI-X interrupts here, yet */
1321                 return 0;
1322         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1323                 shared_int = false;
1324                 if (request_irq(irq, ixgbe_test_intr, 0, netdev->name,
1325                                 netdev)) {
1326                         *data = 1;
1327                         return -1;
1328                 }
1329         } else if (!request_irq(irq, ixgbe_test_intr, IRQF_PROBE_SHARED,
1330                                 netdev->name, netdev)) {
1331                 shared_int = false;
1332         } else if (request_irq(irq, ixgbe_test_intr, IRQF_SHARED,
1333                                netdev->name, netdev)) {
1334                 *data = 1;
1335                 return -1;
1336         }
1337         DPRINTK(HW, INFO, "testing %s interrupt\n",
1338                 (shared_int ? "shared" : "unshared"));
1339
1340         /* Disable all the interrupts */
1341         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF);
1342         msleep(10);
1343
1344         /* Test each interrupt */
1345         for (; i < 10; i++) {
1346                 /* Interrupt to test */
1347                 mask = 1 << i;
1348
1349                 if (!shared_int) {
1350                         /*
1351                          * Disable the interrupts to be reported in
1352                          * the cause register and then force the same
1353                          * interrupt and see if one gets posted.  If
1354                          * an interrupt was posted to the bus, the
1355                          * test failed.
1356                          */
1357                         adapter->test_icr = 0;
1358                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC,
1359                                         ~mask & 0x00007FFF);
1360                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
1361                                         ~mask & 0x00007FFF);
1362                         msleep(10);
1363
1364                         if (adapter->test_icr & mask) {
1365                                 *data = 3;
1366                                 break;
1367                         }
1368                 }
1369
1370                 /*
1371                  * Enable the interrupt to be reported in the cause
1372                  * register and then force the same interrupt and see
1373                  * if one gets posted.  If an interrupt was not posted
1374                  * to the bus, the test failed.
1375                  */
1376                 adapter->test_icr = 0;
1377                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1378                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
1379                 msleep(10);
1380
1381                 if (!(adapter->test_icr &mask)) {
1382                         *data = 4;
1383                         break;
1384                 }
1385
1386                 if (!shared_int) {
1387                         /*
1388                          * Disable the other interrupts to be reported in
1389                          * the cause register and then force the other
1390                          * interrupts and see if any get posted.  If
1391                          * an interrupt was posted to the bus, the
1392                          * test failed.
1393                          */
1394                         adapter->test_icr = 0;
1395                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC,
1396                                         ~mask & 0x00007FFF);
1397                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
1398                                         ~mask & 0x00007FFF);
1399                         msleep(10);
1400
1401                         if (adapter->test_icr) {
1402                                 *data = 5;
1403                                 break;
1404                         }
1405                 }
1406         }
1407
1408         /* Disable all the interrupts */
1409         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF);
1410         msleep(10);
1411
1412         /* Unhook test interrupt handler */
1413         free_irq(irq, netdev);
1414
1415         return *data;
1416 }
1417
1418 static void ixgbe_free_desc_rings(struct ixgbe_adapter *adapter)
1419 {
1420         struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
1421         struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
1422         struct ixgbe_hw *hw = &adapter->hw;
1423         struct pci_dev *pdev = adapter->pdev;
1424         u32 reg_ctl;
1425         int i;
1426
1427         /* shut down the DMA engines now so they can be reinitialized later */
1428
1429         /* first Rx */
1430         reg_ctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1431         reg_ctl &= ~IXGBE_RXCTRL_RXEN;
1432         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg_ctl);
1433         reg_ctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(0));
1434         reg_ctl &= ~IXGBE_RXDCTL_ENABLE;
1435         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(0), reg_ctl);
1436
1437         /* now Tx */
1438         reg_ctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(0));
1439         reg_ctl &= ~IXGBE_TXDCTL_ENABLE;
1440         IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(0), reg_ctl);
1441         if (hw->mac.type == ixgbe_mac_82599EB) {
1442                 reg_ctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1443                 reg_ctl &= ~IXGBE_DMATXCTL_TE;
1444                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg_ctl);
1445         }
1446
1447         ixgbe_reset(adapter);
1448
1449         if (tx_ring->desc && tx_ring->tx_buffer_info) {
1450                 for (i = 0; i < tx_ring->count; i++) {
1451                         struct ixgbe_tx_buffer *buf =
1452                                         &(tx_ring->tx_buffer_info[i]);
1453                         if (buf->dma)
1454                                 pci_unmap_single(pdev, buf->dma, buf->length,
1455                                                  PCI_DMA_TODEVICE);
1456                         if (buf->skb)
1457                                 dev_kfree_skb(buf->skb);
1458                 }
1459         }
1460
1461         if (rx_ring->desc && rx_ring->rx_buffer_info) {
1462                 for (i = 0; i < rx_ring->count; i++) {
1463                         struct ixgbe_rx_buffer *buf =
1464                                         &(rx_ring->rx_buffer_info[i]);
1465                         if (buf->dma)
1466                                 pci_unmap_single(pdev, buf->dma,
1467                                                  IXGBE_RXBUFFER_2048,
1468                                                  PCI_DMA_FROMDEVICE);
1469                         if (buf->skb)
1470                                 dev_kfree_skb(buf->skb);
1471                 }
1472         }
1473
1474         if (tx_ring->desc) {
1475                 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc,
1476                                     tx_ring->dma);
1477                 tx_ring->desc = NULL;
1478         }
1479         if (rx_ring->desc) {
1480                 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc,
1481                                     rx_ring->dma);
1482                 rx_ring->desc = NULL;
1483         }
1484
1485         kfree(tx_ring->tx_buffer_info);
1486         tx_ring->tx_buffer_info = NULL;
1487         kfree(rx_ring->rx_buffer_info);
1488         rx_ring->rx_buffer_info = NULL;
1489
1490         return;
1491 }
1492
1493 static int ixgbe_setup_desc_rings(struct ixgbe_adapter *adapter)
1494 {
1495         struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
1496         struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
1497         struct pci_dev *pdev = adapter->pdev;
1498         u32 rctl, reg_data;
1499         int i, ret_val;
1500
1501         /* Setup Tx descriptor ring and Tx buffers */
1502
1503         if (!tx_ring->count)
1504                 tx_ring->count = IXGBE_DEFAULT_TXD;
1505
1506         tx_ring->tx_buffer_info = kcalloc(tx_ring->count,
1507                                           sizeof(struct ixgbe_tx_buffer),
1508                                           GFP_KERNEL);
1509         if (!(tx_ring->tx_buffer_info)) {
1510                 ret_val = 1;
1511                 goto err_nomem;
1512         }
1513
1514         tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
1515         tx_ring->size = ALIGN(tx_ring->size, 4096);
1516         if (!(tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
1517                                                    &tx_ring->dma))) {
1518                 ret_val = 2;
1519                 goto err_nomem;
1520         }
1521         tx_ring->next_to_use = tx_ring->next_to_clean = 0;
1522
1523         IXGBE_WRITE_REG(&adapter->hw, IXGBE_TDBAL(0),
1524                         ((u64) tx_ring->dma & 0x00000000FFFFFFFF));
1525         IXGBE_WRITE_REG(&adapter->hw, IXGBE_TDBAH(0),
1526                         ((u64) tx_ring->dma >> 32));
1527         IXGBE_WRITE_REG(&adapter->hw, IXGBE_TDLEN(0),
1528                         tx_ring->count * sizeof(union ixgbe_adv_tx_desc));
1529         IXGBE_WRITE_REG(&adapter->hw, IXGBE_TDH(0), 0);
1530         IXGBE_WRITE_REG(&adapter->hw, IXGBE_TDT(0), 0);
1531
1532         reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0);
1533         reg_data |= IXGBE_HLREG0_TXPADEN;
1534         IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data);
1535
1536         if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1537                 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_DMATXCTL);
1538                 reg_data |= IXGBE_DMATXCTL_TE;
1539                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DMATXCTL, reg_data);
1540         }
1541         reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_TXDCTL(0));
1542         reg_data |= IXGBE_TXDCTL_ENABLE;
1543         IXGBE_WRITE_REG(&adapter->hw, IXGBE_TXDCTL(0), reg_data);
1544
1545         for (i = 0; i < tx_ring->count; i++) {
1546                 union ixgbe_adv_tx_desc *desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
1547                 struct sk_buff *skb;
1548                 unsigned int size = 1024;
1549
1550                 skb = alloc_skb(size, GFP_KERNEL);
1551                 if (!skb) {
1552                         ret_val = 3;
1553                         goto err_nomem;
1554                 }
1555                 skb_put(skb, size);
1556                 tx_ring->tx_buffer_info[i].skb = skb;
1557                 tx_ring->tx_buffer_info[i].length = skb->len;
1558                 tx_ring->tx_buffer_info[i].dma =
1559                         pci_map_single(pdev, skb->data, skb->len,
1560                                        PCI_DMA_TODEVICE);
1561                 desc->read.buffer_addr =
1562                                     cpu_to_le64(tx_ring->tx_buffer_info[i].dma);
1563                 desc->read.cmd_type_len = cpu_to_le32(skb->len);
1564                 desc->read.cmd_type_len |= cpu_to_le32(IXGBE_TXD_CMD_EOP |
1565                                                        IXGBE_TXD_CMD_IFCS |
1566                                                        IXGBE_TXD_CMD_RS);
1567                 desc->read.olinfo_status = 0;
1568                 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
1569                         desc->read.olinfo_status |=
1570                                         (skb->len << IXGBE_ADVTXD_PAYLEN_SHIFT);
1571
1572         }
1573
1574         /* Setup Rx Descriptor ring and Rx buffers */
1575
1576         if (!rx_ring->count)
1577                 rx_ring->count = IXGBE_DEFAULT_RXD;
1578
1579         rx_ring->rx_buffer_info = kcalloc(rx_ring->count,
1580                                           sizeof(struct ixgbe_rx_buffer),
1581                                           GFP_KERNEL);
1582         if (!(rx_ring->rx_buffer_info)) {
1583                 ret_val = 4;
1584                 goto err_nomem;
1585         }
1586
1587         rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
1588         rx_ring->size = ALIGN(rx_ring->size, 4096);
1589         if (!(rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size,
1590                                                    &rx_ring->dma))) {
1591                 ret_val = 5;
1592                 goto err_nomem;
1593         }
1594         rx_ring->next_to_use = rx_ring->next_to_clean = 0;
1595
1596         rctl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXCTRL);
1597         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXCTRL, rctl & ~IXGBE_RXCTRL_RXEN);
1598         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDBAL(0),
1599                         ((u64)rx_ring->dma & 0xFFFFFFFF));
1600         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDBAH(0),
1601                         ((u64) rx_ring->dma >> 32));
1602         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDLEN(0), rx_ring->size);
1603         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDH(0), 0);
1604         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDT(0), 0);
1605
1606         reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
1607         reg_data |= IXGBE_FCTRL_BAM | IXGBE_FCTRL_SBP | IXGBE_FCTRL_MPE;
1608         IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, reg_data);
1609
1610         reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0);
1611         reg_data &= ~IXGBE_HLREG0_LPBK;
1612         IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data);
1613
1614         reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_RDRXCTL);
1615 #define IXGBE_RDRXCTL_RDMTS_MASK    0x00000003 /* Receive Descriptor Minimum
1616                                                   Threshold Size mask */
1617         reg_data &= ~IXGBE_RDRXCTL_RDMTS_MASK;
1618         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDRXCTL, reg_data);
1619
1620         reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_MCSTCTRL);
1621 #define IXGBE_MCSTCTRL_MO_MASK      0x00000003 /* Multicast Offset mask */
1622         reg_data &= ~IXGBE_MCSTCTRL_MO_MASK;
1623         reg_data |= adapter->hw.mac.mc_filter_type;
1624         IXGBE_WRITE_REG(&adapter->hw, IXGBE_MCSTCTRL, reg_data);
1625
1626         reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_RXDCTL(0));
1627         reg_data |= IXGBE_RXDCTL_ENABLE;
1628         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXDCTL(0), reg_data);
1629         if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1630                 int j = adapter->rx_ring[0].reg_idx;
1631                 u32 k;
1632                 for (k = 0; k < 10; k++) {
1633                         if (IXGBE_READ_REG(&adapter->hw,
1634                                            IXGBE_RXDCTL(j)) & IXGBE_RXDCTL_ENABLE)
1635                                 break;
1636                         else
1637                                 msleep(1);
1638                 }
1639         }
1640
1641         rctl |= IXGBE_RXCTRL_RXEN | IXGBE_RXCTRL_DMBYPS;
1642         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXCTRL, rctl);
1643
1644         for (i = 0; i < rx_ring->count; i++) {
1645                 union ixgbe_adv_rx_desc *rx_desc =
1646                                                  IXGBE_RX_DESC_ADV(*rx_ring, i);
1647                 struct sk_buff *skb;
1648
1649                 skb = alloc_skb(IXGBE_RXBUFFER_2048 + NET_IP_ALIGN, GFP_KERNEL);
1650                 if (!skb) {
1651                         ret_val = 6;
1652                         goto err_nomem;
1653                 }
1654                 skb_reserve(skb, NET_IP_ALIGN);
1655                 rx_ring->rx_buffer_info[i].skb = skb;
1656                 rx_ring->rx_buffer_info[i].dma =
1657                         pci_map_single(pdev, skb->data, IXGBE_RXBUFFER_2048,
1658                                        PCI_DMA_FROMDEVICE);
1659                 rx_desc->read.pkt_addr =
1660                                 cpu_to_le64(rx_ring->rx_buffer_info[i].dma);
1661                 memset(skb->data, 0x00, skb->len);
1662         }
1663
1664         return 0;
1665
1666 err_nomem:
1667         ixgbe_free_desc_rings(adapter);
1668         return ret_val;
1669 }
1670
1671 static int ixgbe_setup_loopback_test(struct ixgbe_adapter *adapter)
1672 {
1673         struct ixgbe_hw *hw = &adapter->hw;
1674         u32 reg_data;
1675
1676         /* right now we only support MAC loopback in the driver */
1677
1678         /* Setup MAC loopback */
1679         reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0);
1680         reg_data |= IXGBE_HLREG0_LPBK;
1681         IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data);
1682
1683         reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_AUTOC);
1684         reg_data &= ~IXGBE_AUTOC_LMS_MASK;
1685         reg_data |= IXGBE_AUTOC_LMS_10G_LINK_NO_AN | IXGBE_AUTOC_FLU;
1686         IXGBE_WRITE_REG(&adapter->hw, IXGBE_AUTOC, reg_data);
1687
1688         /* Disable Atlas Tx lanes; re-enabled in reset path */
1689         if (hw->mac.type == ixgbe_mac_82598EB) {
1690                 u8 atlas;
1691
1692                 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &atlas);
1693                 atlas |= IXGBE_ATLAS_PDN_TX_REG_EN;
1694                 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, atlas);
1695
1696                 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, &atlas);
1697                 atlas |= IXGBE_ATLAS_PDN_TX_10G_QL_ALL;
1698                 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, atlas);
1699
1700                 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, &atlas);
1701                 atlas |= IXGBE_ATLAS_PDN_TX_1G_QL_ALL;
1702                 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, atlas);
1703
1704                 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, &atlas);
1705                 atlas |= IXGBE_ATLAS_PDN_TX_AN_QL_ALL;
1706                 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, atlas);
1707         }
1708
1709         return 0;
1710 }
1711
1712 static void ixgbe_loopback_cleanup(struct ixgbe_adapter *adapter)
1713 {
1714         u32 reg_data;
1715
1716         reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0);
1717         reg_data &= ~IXGBE_HLREG0_LPBK;
1718         IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data);
1719 }
1720
1721 static void ixgbe_create_lbtest_frame(struct sk_buff *skb,
1722                                       unsigned int frame_size)
1723 {
1724         memset(skb->data, 0xFF, frame_size);
1725         frame_size &= ~1;
1726         memset(&skb->data[frame_size / 2], 0xAA, frame_size / 2 - 1);
1727         memset(&skb->data[frame_size / 2 + 10], 0xBE, 1);
1728         memset(&skb->data[frame_size / 2 + 12], 0xAF, 1);
1729 }
1730
1731 static int ixgbe_check_lbtest_frame(struct sk_buff *skb,
1732                                     unsigned int frame_size)
1733 {
1734         frame_size &= ~1;
1735         if (*(skb->data + 3) == 0xFF) {
1736                 if ((*(skb->data + frame_size / 2 + 10) == 0xBE) &&
1737                     (*(skb->data + frame_size / 2 + 12) == 0xAF)) {
1738                         return 0;
1739                 }
1740         }
1741         return 13;
1742 }
1743
1744 static int ixgbe_run_loopback_test(struct ixgbe_adapter *adapter)
1745 {
1746         struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
1747         struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
1748         struct pci_dev *pdev = adapter->pdev;
1749         int i, j, k, l, lc, good_cnt, ret_val = 0;
1750         unsigned long time;
1751
1752         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDT(0), rx_ring->count - 1);
1753
1754         /*
1755          * Calculate the loop count based on the largest descriptor ring
1756          * The idea is to wrap the largest ring a number of times using 64
1757          * send/receive pairs during each loop
1758          */
1759
1760         if (rx_ring->count <= tx_ring->count)
1761                 lc = ((tx_ring->count / 64) * 2) + 1;
1762         else
1763                 lc = ((rx_ring->count / 64) * 2) + 1;
1764
1765         k = l = 0;
1766         for (j = 0; j <= lc; j++) {
1767                 for (i = 0; i < 64; i++) {
1768                         ixgbe_create_lbtest_frame(
1769                                         tx_ring->tx_buffer_info[k].skb,
1770                                         1024);
1771                         pci_dma_sync_single_for_device(pdev,
1772                                 tx_ring->tx_buffer_info[k].dma,
1773                                 tx_ring->tx_buffer_info[k].length,
1774                                 PCI_DMA_TODEVICE);
1775                         if (unlikely(++k == tx_ring->count))
1776                                 k = 0;
1777                 }
1778                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_TDT(0), k);
1779                 msleep(200);
1780                 /* set the start time for the receive */
1781                 time = jiffies;
1782                 good_cnt = 0;
1783                 do {
1784                         /* receive the sent packets */
1785                         pci_dma_sync_single_for_cpu(pdev,
1786                                         rx_ring->rx_buffer_info[l].dma,
1787                                         IXGBE_RXBUFFER_2048,
1788                                         PCI_DMA_FROMDEVICE);
1789                         ret_val = ixgbe_check_lbtest_frame(
1790                                         rx_ring->rx_buffer_info[l].skb, 1024);
1791                         if (!ret_val)
1792                                 good_cnt++;
1793                         if (++l == rx_ring->count)
1794                                 l = 0;
1795                         /*
1796                          * time + 20 msecs (200 msecs on 2.4) is more than
1797                          * enough time to complete the receives, if it's
1798                          * exceeded, break and error off
1799                          */
1800                 } while (good_cnt < 64 && jiffies < (time + 20));
1801                 if (good_cnt != 64) {
1802                         /* ret_val is the same as mis-compare */
1803                         ret_val = 13;
1804                         break;
1805                 }
1806                 if (jiffies >= (time + 20)) {
1807                         /* Error code for time out error */
1808                         ret_val = 14;
1809                         break;
1810                 }
1811         }
1812
1813         return ret_val;
1814 }
1815
1816 static int ixgbe_loopback_test(struct ixgbe_adapter *adapter, u64 *data)
1817 {
1818         *data = ixgbe_setup_desc_rings(adapter);
1819         if (*data)
1820                 goto out;
1821         *data = ixgbe_setup_loopback_test(adapter);
1822         if (*data)
1823                 goto err_loopback;
1824         *data = ixgbe_run_loopback_test(adapter);
1825         ixgbe_loopback_cleanup(adapter);
1826
1827 err_loopback:
1828         ixgbe_free_desc_rings(adapter);
1829 out:
1830         return *data;
1831 }
1832
1833 static void ixgbe_diag_test(struct net_device *netdev,
1834                             struct ethtool_test *eth_test, u64 *data)
1835 {
1836         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1837         bool if_running = netif_running(netdev);
1838
1839         set_bit(__IXGBE_TESTING, &adapter->state);
1840         if (eth_test->flags == ETH_TEST_FL_OFFLINE) {
1841                 /* Offline tests */
1842
1843                 DPRINTK(HW, INFO, "offline testing starting\n");
1844
1845                 /* Link test performed before hardware reset so autoneg doesn't
1846                  * interfere with test result */
1847                 if (ixgbe_link_test(adapter, &data[4]))
1848                         eth_test->flags |= ETH_TEST_FL_FAILED;
1849
1850                 if (if_running)
1851                         /* indicate we're in test mode */
1852                         dev_close(netdev);
1853                 else
1854                         ixgbe_reset(adapter);
1855
1856                 DPRINTK(HW, INFO, "register testing starting\n");
1857                 if (ixgbe_reg_test(adapter, &data[0]))
1858                         eth_test->flags |= ETH_TEST_FL_FAILED;
1859
1860                 ixgbe_reset(adapter);
1861                 DPRINTK(HW, INFO, "eeprom testing starting\n");
1862                 if (ixgbe_eeprom_test(adapter, &data[1]))
1863                         eth_test->flags |= ETH_TEST_FL_FAILED;
1864
1865                 ixgbe_reset(adapter);
1866                 DPRINTK(HW, INFO, "interrupt testing starting\n");
1867                 if (ixgbe_intr_test(adapter, &data[2]))
1868                         eth_test->flags |= ETH_TEST_FL_FAILED;
1869
1870                 /* If SRIOV or VMDq is enabled then skip MAC
1871                  * loopback diagnostic. */
1872                 if (adapter->flags & (IXGBE_FLAG_SRIOV_ENABLED |
1873                                       IXGBE_FLAG_VMDQ_ENABLED)) {
1874                         DPRINTK(HW, INFO, "Skip MAC loopback diagnostic in VT "
1875                                 "mode\n");
1876                         data[3] = 0;
1877                         goto skip_loopback;
1878                 }
1879
1880                 ixgbe_reset(adapter);
1881                 DPRINTK(HW, INFO, "loopback testing starting\n");
1882                 if (ixgbe_loopback_test(adapter, &data[3]))
1883                         eth_test->flags |= ETH_TEST_FL_FAILED;
1884
1885 skip_loopback:
1886                 ixgbe_reset(adapter);
1887
1888                 clear_bit(__IXGBE_TESTING, &adapter->state);
1889                 if (if_running)
1890                         dev_open(netdev);
1891         } else {
1892                 DPRINTK(HW, INFO, "online testing starting\n");
1893                 /* Online tests */
1894                 if (ixgbe_link_test(adapter, &data[4]))
1895                         eth_test->flags |= ETH_TEST_FL_FAILED;
1896
1897                 /* Online tests aren't run; pass by default */
1898                 data[0] = 0;
1899                 data[1] = 0;
1900                 data[2] = 0;
1901                 data[3] = 0;
1902
1903                 clear_bit(__IXGBE_TESTING, &adapter->state);
1904         }
1905         msleep_interruptible(4 * 1000);
1906 }
1907
1908 static int ixgbe_wol_exclusion(struct ixgbe_adapter *adapter,
1909                                struct ethtool_wolinfo *wol)
1910 {
1911         struct ixgbe_hw *hw = &adapter->hw;
1912         int retval = 1;
1913
1914         switch(hw->device_id) {
1915         case IXGBE_DEV_ID_82599_KX4:
1916                 retval = 0;
1917                 break;
1918         default:
1919                 wol->supported = 0;
1920         }
1921
1922         return retval;
1923 }
1924
1925 static void ixgbe_get_wol(struct net_device *netdev,
1926                           struct ethtool_wolinfo *wol)
1927 {
1928         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1929
1930         wol->supported = WAKE_UCAST | WAKE_MCAST |
1931                          WAKE_BCAST | WAKE_MAGIC;
1932         wol->wolopts = 0;
1933
1934         if (ixgbe_wol_exclusion(adapter, wol) ||
1935             !device_can_wakeup(&adapter->pdev->dev))
1936                 return;
1937
1938         if (adapter->wol & IXGBE_WUFC_EX)
1939                 wol->wolopts |= WAKE_UCAST;
1940         if (adapter->wol & IXGBE_WUFC_MC)
1941                 wol->wolopts |= WAKE_MCAST;
1942         if (adapter->wol & IXGBE_WUFC_BC)
1943                 wol->wolopts |= WAKE_BCAST;
1944         if (adapter->wol & IXGBE_WUFC_MAG)
1945                 wol->wolopts |= WAKE_MAGIC;
1946
1947         return;
1948 }
1949
1950 static int ixgbe_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1951 {
1952         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1953
1954         if (wol->wolopts & (WAKE_PHY | WAKE_ARP | WAKE_MAGICSECURE))
1955                 return -EOPNOTSUPP;
1956
1957         if (ixgbe_wol_exclusion(adapter, wol))
1958                 return wol->wolopts ? -EOPNOTSUPP : 0;
1959
1960         adapter->wol = 0;
1961
1962         if (wol->wolopts & WAKE_UCAST)
1963                 adapter->wol |= IXGBE_WUFC_EX;
1964         if (wol->wolopts & WAKE_MCAST)
1965                 adapter->wol |= IXGBE_WUFC_MC;
1966         if (wol->wolopts & WAKE_BCAST)
1967                 adapter->wol |= IXGBE_WUFC_BC;
1968         if (wol->wolopts & WAKE_MAGIC)
1969                 adapter->wol |= IXGBE_WUFC_MAG;
1970
1971         device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
1972
1973         return 0;
1974 }
1975
1976 static int ixgbe_nway_reset(struct net_device *netdev)
1977 {
1978         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1979
1980         if (netif_running(netdev))
1981                 ixgbe_reinit_locked(adapter);
1982
1983         return 0;
1984 }
1985
1986 static int ixgbe_phys_id(struct net_device *netdev, u32 data)
1987 {
1988         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1989         struct ixgbe_hw *hw = &adapter->hw;
1990         u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
1991         u32 i;
1992
1993         if (!data || data > 300)
1994                 data = 300;
1995
1996         for (i = 0; i < (data * 1000); i += 400) {
1997                 hw->mac.ops.led_on(hw, IXGBE_LED_ON);
1998                 msleep_interruptible(200);
1999                 hw->mac.ops.led_off(hw, IXGBE_LED_ON);
2000                 msleep_interruptible(200);
2001         }
2002
2003         /* Restore LED settings */
2004         IXGBE_WRITE_REG(&adapter->hw, IXGBE_LEDCTL, led_reg);
2005
2006         return 0;
2007 }
2008
2009 static int ixgbe_get_coalesce(struct net_device *netdev,
2010                               struct ethtool_coalesce *ec)
2011 {
2012         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2013
2014         ec->tx_max_coalesced_frames_irq = adapter->tx_ring[0].work_limit;
2015
2016         /* only valid if in constant ITR mode */
2017         switch (adapter->rx_itr_setting) {
2018         case 0:
2019                 /* throttling disabled */
2020                 ec->rx_coalesce_usecs = 0;
2021                 break;
2022         case 1:
2023                 /* dynamic ITR mode */
2024                 ec->rx_coalesce_usecs = 1;
2025                 break;
2026         default:
2027                 /* fixed interrupt rate mode */
2028                 ec->rx_coalesce_usecs = 1000000/adapter->rx_eitr_param;
2029                 break;
2030         }
2031
2032         /* if in mixed tx/rx queues per vector mode, report only rx settings */
2033         if (adapter->q_vector[0]->txr_count && adapter->q_vector[0]->rxr_count)
2034                 return 0;
2035
2036         /* only valid if in constant ITR mode */
2037         switch (adapter->tx_itr_setting) {
2038         case 0:
2039                 /* throttling disabled */
2040                 ec->tx_coalesce_usecs = 0;
2041                 break;
2042         case 1:
2043                 /* dynamic ITR mode */
2044                 ec->tx_coalesce_usecs = 1;
2045                 break;
2046         default:
2047                 ec->tx_coalesce_usecs = 1000000/adapter->tx_eitr_param;
2048                 break;
2049         }
2050
2051         return 0;
2052 }
2053
2054 static int ixgbe_set_coalesce(struct net_device *netdev,
2055                               struct ethtool_coalesce *ec)
2056 {
2057         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2058         struct ixgbe_q_vector *q_vector;
2059         int i;
2060
2061         /* don't accept tx specific changes if we've got mixed RxTx vectors */
2062         if (adapter->q_vector[0]->txr_count && adapter->q_vector[0]->rxr_count
2063            && ec->tx_coalesce_usecs)
2064                 return -EINVAL;
2065
2066         if (ec->tx_max_coalesced_frames_irq)
2067                 adapter->tx_ring[0].work_limit = ec->tx_max_coalesced_frames_irq;
2068
2069         if (ec->rx_coalesce_usecs > 1) {
2070                 /* check the limits */
2071                 if ((1000000/ec->rx_coalesce_usecs > IXGBE_MAX_INT_RATE) ||
2072                     (1000000/ec->rx_coalesce_usecs < IXGBE_MIN_INT_RATE))
2073                         return -EINVAL;
2074
2075                 /* store the value in ints/second */
2076                 adapter->rx_eitr_param = 1000000/ec->rx_coalesce_usecs;
2077
2078                 /* static value of interrupt rate */
2079                 adapter->rx_itr_setting = adapter->rx_eitr_param;
2080                 /* clear the lower bit as its used for dynamic state */
2081                 adapter->rx_itr_setting &= ~1;
2082         } else if (ec->rx_coalesce_usecs == 1) {
2083                 /* 1 means dynamic mode */
2084                 adapter->rx_eitr_param = 20000;
2085                 adapter->rx_itr_setting = 1;
2086         } else {
2087                 /*
2088                  * any other value means disable eitr, which is best
2089                  * served by setting the interrupt rate very high
2090                  */
2091                 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
2092                         adapter->rx_eitr_param = IXGBE_MAX_RSC_INT_RATE;
2093                 else
2094                         adapter->rx_eitr_param = IXGBE_MAX_INT_RATE;
2095                 adapter->rx_itr_setting = 0;
2096         }
2097
2098         if (ec->tx_coalesce_usecs > 1) {
2099                 /* check the limits */
2100                 if ((1000000/ec->tx_coalesce_usecs > IXGBE_MAX_INT_RATE) ||
2101                     (1000000/ec->tx_coalesce_usecs < IXGBE_MIN_INT_RATE))
2102                         return -EINVAL;
2103
2104                 /* store the value in ints/second */
2105                 adapter->tx_eitr_param = 1000000/ec->tx_coalesce_usecs;
2106
2107                 /* static value of interrupt rate */
2108                 adapter->tx_itr_setting = adapter->tx_eitr_param;
2109
2110                 /* clear the lower bit as its used for dynamic state */
2111                 adapter->tx_itr_setting &= ~1;
2112         } else if (ec->tx_coalesce_usecs == 1) {
2113                 /* 1 means dynamic mode */
2114                 adapter->tx_eitr_param = 10000;
2115                 adapter->tx_itr_setting = 1;
2116         } else {
2117                 adapter->tx_eitr_param = IXGBE_MAX_INT_RATE;
2118                 adapter->tx_itr_setting = 0;
2119         }
2120
2121         /* MSI/MSIx Interrupt Mode */
2122         if (adapter->flags &
2123             (IXGBE_FLAG_MSIX_ENABLED | IXGBE_FLAG_MSI_ENABLED)) {
2124                 int num_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2125                 for (i = 0; i < num_vectors; i++) {
2126                         q_vector = adapter->q_vector[i];
2127                         if (q_vector->txr_count && !q_vector->rxr_count)
2128                                 /* tx only */
2129                                 q_vector->eitr = adapter->tx_eitr_param;
2130                         else
2131                                 /* rx only or mixed */
2132                                 q_vector->eitr = adapter->rx_eitr_param;
2133                         ixgbe_write_eitr(q_vector);
2134                 }
2135         /* Legacy Interrupt Mode */
2136         } else {
2137                 q_vector = adapter->q_vector[0];
2138                 q_vector->eitr = adapter->rx_eitr_param;
2139                 ixgbe_write_eitr(q_vector);
2140         }
2141
2142         return 0;
2143 }
2144
2145 static int ixgbe_set_flags(struct net_device *netdev, u32 data)
2146 {
2147         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2148
2149         ethtool_op_set_flags(netdev, data);
2150
2151         if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE))
2152                 return 0;
2153
2154         /* if state changes we need to update adapter->flags and reset */
2155         if ((!!(data & ETH_FLAG_LRO)) !=
2156             (!!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))) {
2157                 adapter->flags2 ^= IXGBE_FLAG2_RSC_ENABLED;
2158                 if (netif_running(netdev))
2159                         ixgbe_reinit_locked(adapter);
2160                 else
2161                         ixgbe_reset(adapter);
2162         }
2163         return 0;
2164
2165 }
2166
2167 static const struct ethtool_ops ixgbe_ethtool_ops = {
2168         .get_settings           = ixgbe_get_settings,
2169         .set_settings           = ixgbe_set_settings,
2170         .get_drvinfo            = ixgbe_get_drvinfo,
2171         .get_regs_len           = ixgbe_get_regs_len,
2172         .get_regs               = ixgbe_get_regs,
2173         .get_wol                = ixgbe_get_wol,
2174         .set_wol                = ixgbe_set_wol,
2175         .nway_reset             = ixgbe_nway_reset,
2176         .get_link               = ethtool_op_get_link,
2177         .get_eeprom_len         = ixgbe_get_eeprom_len,
2178         .get_eeprom             = ixgbe_get_eeprom,
2179         .get_ringparam          = ixgbe_get_ringparam,
2180         .set_ringparam          = ixgbe_set_ringparam,
2181         .get_pauseparam         = ixgbe_get_pauseparam,
2182         .set_pauseparam         = ixgbe_set_pauseparam,
2183         .get_rx_csum            = ixgbe_get_rx_csum,
2184         .set_rx_csum            = ixgbe_set_rx_csum,
2185         .get_tx_csum            = ixgbe_get_tx_csum,
2186         .set_tx_csum            = ixgbe_set_tx_csum,
2187         .get_sg                 = ethtool_op_get_sg,
2188         .set_sg                 = ethtool_op_set_sg,
2189         .get_msglevel           = ixgbe_get_msglevel,
2190         .set_msglevel           = ixgbe_set_msglevel,
2191         .get_tso                = ethtool_op_get_tso,
2192         .set_tso                = ixgbe_set_tso,
2193         .self_test              = ixgbe_diag_test,
2194         .get_strings            = ixgbe_get_strings,
2195         .phys_id                = ixgbe_phys_id,
2196         .get_sset_count         = ixgbe_get_sset_count,
2197         .get_ethtool_stats      = ixgbe_get_ethtool_stats,
2198         .get_coalesce           = ixgbe_get_coalesce,
2199         .set_coalesce           = ixgbe_set_coalesce,
2200         .get_flags              = ethtool_op_get_flags,
2201         .set_flags              = ixgbe_set_flags,
2202 };
2203
2204 void ixgbe_set_ethtool_ops(struct net_device *netdev)
2205 {
2206         SET_ETHTOOL_OPS(netdev, &ixgbe_ethtool_ops);
2207 }