1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2010 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
31 #include <linux/types.h>
32 #include <linux/pci.h>
33 #include <linux/netdevice.h>
34 #include <linux/aer.h>
36 #include "ixgbe_type.h"
37 #include "ixgbe_common.h"
38 #include "ixgbe_dcb.h"
39 #if defined(CONFIG_FCOE) || defined(CONFIG_FCOE_MODULE)
41 #include "ixgbe_fcoe.h"
42 #endif /* CONFIG_FCOE or CONFIG_FCOE_MODULE */
43 #ifdef CONFIG_IXGBE_DCA
44 #include <linux/dca.h>
48 #define DPRINTK(nlevel, klevel, fmt, args...) \
49 ((void)((NETIF_MSG_##nlevel & adapter->msg_enable) && \
50 printk(KERN_##klevel PFX "%s: %s: " fmt, adapter->netdev->name, \
53 /* TX/RX descriptor defines */
54 #define IXGBE_DEFAULT_TXD 512
55 #define IXGBE_MAX_TXD 4096
56 #define IXGBE_MIN_TXD 64
58 #define IXGBE_DEFAULT_RXD 512
59 #define IXGBE_MAX_RXD 4096
60 #define IXGBE_MIN_RXD 64
63 #define IXGBE_DEFAULT_FCRTL 0x10000
64 #define IXGBE_MIN_FCRTL 0x40
65 #define IXGBE_MAX_FCRTL 0x7FF80
66 #define IXGBE_DEFAULT_FCRTH 0x20000
67 #define IXGBE_MIN_FCRTH 0x600
68 #define IXGBE_MAX_FCRTH 0x7FFF0
69 #define IXGBE_DEFAULT_FCPAUSE 0xFFFF
70 #define IXGBE_MIN_FCPAUSE 0
71 #define IXGBE_MAX_FCPAUSE 0xFFFF
73 /* Supported Rx Buffer Sizes */
74 #define IXGBE_RXBUFFER_64 64 /* Used for packet split */
75 #define IXGBE_RXBUFFER_128 128 /* Used for packet split */
76 #define IXGBE_RXBUFFER_256 256 /* Used for packet split */
77 #define IXGBE_RXBUFFER_2048 2048
78 #define IXGBE_RXBUFFER_4096 4096
79 #define IXGBE_RXBUFFER_8192 8192
80 #define IXGBE_MAX_RXBUFFER 16384 /* largest size for a single descriptor */
82 #define IXGBE_RX_HDR_SIZE IXGBE_RXBUFFER_256
84 #define MAXIMUM_ETHERNET_VLAN_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN)
86 /* How many Rx Buffers do we bundle into one write to the hardware ? */
87 #define IXGBE_RX_BUFFER_WRITE 16 /* Must be power of 2 */
89 #define IXGBE_TX_FLAGS_CSUM (u32)(1)
90 #define IXGBE_TX_FLAGS_VLAN (u32)(1 << 1)
91 #define IXGBE_TX_FLAGS_TSO (u32)(1 << 2)
92 #define IXGBE_TX_FLAGS_IPV4 (u32)(1 << 3)
93 #define IXGBE_TX_FLAGS_FCOE (u32)(1 << 4)
94 #define IXGBE_TX_FLAGS_FSO (u32)(1 << 5)
95 #define IXGBE_TX_FLAGS_VLAN_MASK 0xffff0000
96 #define IXGBE_TX_FLAGS_VLAN_PRIO_MASK 0x0000e000
97 #define IXGBE_TX_FLAGS_VLAN_SHIFT 16
99 #define IXGBE_MAX_RSC_INT_RATE 162760
101 #define IXGBE_MAX_VF_MC_ENTRIES 30
102 #define IXGBE_MAX_VF_FUNCTIONS 64
103 #define IXGBE_MAX_VFTA_ENTRIES 128
104 #define MAX_EMULATION_MAC_ADDRS 16
105 #define VMDQ_P(p) ((p) + adapter->num_vfs)
107 #define IXGBE_SUBDEV_ID_82598AF_MEZZ 0x0049
108 #define IXGBE_SUBDEV_ID_82598AF_MENLO_Q_MEZZ 0x004a
109 #define IXGBE_SUBDEV_ID_82598AF_MENLO_E_MEZZ 0x004b
111 struct vf_data_storage {
112 unsigned char vf_mac_addresses[ETH_ALEN];
113 u16 vf_mc_hashes[IXGBE_MAX_VF_MC_ENTRIES];
114 u16 num_vf_mc_hashes;
115 u16 default_vf_vlan_id;
121 /* wrapper around a pointer to a socket buffer,
122 * so a DMA handle can be stored along with the buffer */
123 struct ixgbe_tx_buffer {
126 unsigned long time_stamp;
132 struct ixgbe_rx_buffer {
137 unsigned int page_offset;
140 struct ixgbe_queue_stats {
146 void *desc; /* descriptor ring memory */
148 struct ixgbe_tx_buffer *tx_buffer_info;
149 struct ixgbe_rx_buffer *rx_buffer_info;
153 u16 count; /* amount of descriptors */
158 u8 queue_index; /* needed for multiqueue queue management */
160 #define IXGBE_RING_RX_PS_ENABLED (u8)(1)
161 u8 flags; /* per ring feature flags */
165 unsigned int total_bytes;
166 unsigned int total_packets;
168 #ifdef CONFIG_IXGBE_DCA
169 /* cpu for tx queue */
173 u16 work_limit; /* max work per interrupt */
174 u16 reg_idx; /* holds the special value that gets
175 * the hardware register offset
176 * associated with this ring, which is
177 * different for DCB and RSS modes
180 struct ixgbe_queue_stats stats;
181 unsigned long reinit_state;
183 u64 rsc_count; /* stat for coalesced packets */
184 u64 rsc_flush; /* stats for flushed packets */
185 u32 restart_queue; /* track tx queue restarts */
186 u32 non_eop_descs; /* track hardware descriptor chaining */
188 unsigned int size; /* length in bytes */
189 dma_addr_t dma; /* phys. address of descriptor ring */
190 } ____cacheline_internodealigned_in_smp;
192 enum ixgbe_ring_f_enum {
195 RING_F_VMDQ, /* SR-IOV uses the same ring feature */
200 #endif /* IXGBE_FCOE */
202 RING_F_ARRAY_SIZE /* must be last in enum set */
205 #define IXGBE_MAX_DCB_INDICES 8
206 #define IXGBE_MAX_RSS_INDICES 16
207 #define IXGBE_MAX_VMDQ_INDICES 64
208 #define IXGBE_MAX_FDIR_INDICES 64
210 #define IXGBE_MAX_FCOE_INDICES 8
211 #define MAX_RX_QUEUES (IXGBE_MAX_FDIR_INDICES + IXGBE_MAX_FCOE_INDICES)
212 #define MAX_TX_QUEUES (IXGBE_MAX_FDIR_INDICES + IXGBE_MAX_FCOE_INDICES)
214 #define MAX_RX_QUEUES IXGBE_MAX_FDIR_INDICES
215 #define MAX_TX_QUEUES IXGBE_MAX_FDIR_INDICES
216 #endif /* IXGBE_FCOE */
217 struct ixgbe_ring_feature {
220 } ____cacheline_internodealigned_in_smp;
223 #define MAX_RX_PACKET_BUFFERS ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) \
225 #define MAX_TX_PACKET_BUFFERS MAX_RX_PACKET_BUFFERS
227 /* MAX_MSIX_Q_VECTORS of these are allocated,
228 * but we only use one per queue-specific vector.
230 struct ixgbe_q_vector {
231 struct ixgbe_adapter *adapter;
232 unsigned int v_idx; /* index of q_vector within array, also used for
233 * finding the bit in EICR and friends that
234 * represents the vector for this ring */
235 struct napi_struct napi;
236 DECLARE_BITMAP(rxr_idx, MAX_RX_QUEUES); /* Rx ring indices */
237 DECLARE_BITMAP(txr_idx, MAX_TX_QUEUES); /* Tx ring indices */
238 u8 rxr_count; /* Rx ring count assigned to this vector */
239 u8 txr_count; /* Tx ring count assigned to this vector */
245 /* Helper macros to switch between ints/sec and what the register uses.
246 * And yes, it's the same math going both ways. The lowest value
247 * supported by all of the ixgbe hardware is 8.
249 #define EITR_INTS_PER_SEC_TO_REG(_eitr) \
250 ((_eitr) ? (1000000000 / ((_eitr) * 256)) : 8)
251 #define EITR_REG_TO_INTS_PER_SEC EITR_INTS_PER_SEC_TO_REG
253 #define IXGBE_DESC_UNUSED(R) \
254 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
255 (R)->next_to_clean - (R)->next_to_use - 1)
257 #define IXGBE_RX_DESC_ADV(R, i) \
258 (&(((union ixgbe_adv_rx_desc *)((R).desc))[i]))
259 #define IXGBE_TX_DESC_ADV(R, i) \
260 (&(((union ixgbe_adv_tx_desc *)((R).desc))[i]))
261 #define IXGBE_TX_CTXTDESC_ADV(R, i) \
262 (&(((struct ixgbe_adv_tx_context_desc *)((R).desc))[i]))
264 #define IXGBE_MAX_JUMBO_FRAME_SIZE 16128
266 /* Use 3K as the baby jumbo frame size for FCoE */
267 #define IXGBE_FCOE_JUMBO_FRAME_SIZE 3072
268 #endif /* IXGBE_FCOE */
270 #define OTHER_VECTOR 1
271 #define NON_Q_VECTORS (OTHER_VECTOR)
273 #define MAX_MSIX_VECTORS_82599 64
274 #define MAX_MSIX_Q_VECTORS_82599 64
275 #define MAX_MSIX_VECTORS_82598 18
276 #define MAX_MSIX_Q_VECTORS_82598 16
278 #define MAX_MSIX_Q_VECTORS MAX_MSIX_Q_VECTORS_82599
279 #define MAX_MSIX_COUNT MAX_MSIX_VECTORS_82599
281 #define MIN_MSIX_Q_VECTORS 2
282 #define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS)
284 /* board specific private data structure */
285 struct ixgbe_adapter {
286 struct timer_list watchdog_timer;
287 struct vlan_group *vlgrp;
289 struct work_struct reset_task;
290 struct ixgbe_q_vector *q_vector[MAX_MSIX_Q_VECTORS];
291 char name[MAX_MSIX_COUNT][IFNAMSIZ + 9];
292 struct ixgbe_dcb_config dcb_cfg;
293 struct ixgbe_dcb_config temp_dcb_cfg;
295 enum ixgbe_fc_mode last_lfc_mode;
297 /* Interrupt Throttle Rate */
304 struct ixgbe_ring *tx_ring[MAX_TX_QUEUES] ____cacheline_aligned_in_smp;
306 u32 tx_timeout_count;
313 struct ixgbe_ring *rx_ring[MAX_RX_QUEUES] ____cacheline_aligned_in_smp;
315 int num_rx_pools; /* == num_rx_queues in 82598 */
316 int num_rx_queues_per_pool; /* 1 if 82598, can be many if 82599 */
317 u64 hw_csum_rx_error;
318 u64 hw_rx_no_dma_resources;
320 int num_msix_vectors;
321 int max_msix_q_vectors; /* true count of q_vectors for device */
322 struct ixgbe_ring_feature ring_feature[RING_F_ARRAY_SIZE];
323 struct msix_entry *msix_entries;
325 u32 alloc_rx_page_failed;
326 u32 alloc_rx_buff_failed;
328 /* Some features need tri-state capability,
329 * thus the additional *_CAPABLE flags.
332 #define IXGBE_FLAG_RX_CSUM_ENABLED (u32)(1)
333 #define IXGBE_FLAG_MSI_CAPABLE (u32)(1 << 1)
334 #define IXGBE_FLAG_MSI_ENABLED (u32)(1 << 2)
335 #define IXGBE_FLAG_MSIX_CAPABLE (u32)(1 << 3)
336 #define IXGBE_FLAG_MSIX_ENABLED (u32)(1 << 4)
337 #define IXGBE_FLAG_RX_1BUF_CAPABLE (u32)(1 << 6)
338 #define IXGBE_FLAG_RX_PS_CAPABLE (u32)(1 << 7)
339 #define IXGBE_FLAG_RX_PS_ENABLED (u32)(1 << 8)
340 #define IXGBE_FLAG_IN_NETPOLL (u32)(1 << 9)
341 #define IXGBE_FLAG_DCA_ENABLED (u32)(1 << 10)
342 #define IXGBE_FLAG_DCA_CAPABLE (u32)(1 << 11)
343 #define IXGBE_FLAG_IMIR_ENABLED (u32)(1 << 12)
344 #define IXGBE_FLAG_MQ_CAPABLE (u32)(1 << 13)
345 #define IXGBE_FLAG_DCB_ENABLED (u32)(1 << 14)
346 #define IXGBE_FLAG_RSS_ENABLED (u32)(1 << 16)
347 #define IXGBE_FLAG_RSS_CAPABLE (u32)(1 << 17)
348 #define IXGBE_FLAG_VMDQ_CAPABLE (u32)(1 << 18)
349 #define IXGBE_FLAG_VMDQ_ENABLED (u32)(1 << 19)
350 #define IXGBE_FLAG_FAN_FAIL_CAPABLE (u32)(1 << 20)
351 #define IXGBE_FLAG_NEED_LINK_UPDATE (u32)(1 << 22)
352 #define IXGBE_FLAG_IN_SFP_LINK_TASK (u32)(1 << 23)
353 #define IXGBE_FLAG_IN_SFP_MOD_TASK (u32)(1 << 24)
354 #define IXGBE_FLAG_FDIR_HASH_CAPABLE (u32)(1 << 25)
355 #define IXGBE_FLAG_FDIR_PERFECT_CAPABLE (u32)(1 << 26)
356 #define IXGBE_FLAG_FCOE_CAPABLE (u32)(1 << 27)
357 #define IXGBE_FLAG_FCOE_ENABLED (u32)(1 << 28)
358 #define IXGBE_FLAG_SRIOV_CAPABLE (u32)(1 << 29)
359 #define IXGBE_FLAG_SRIOV_ENABLED (u32)(1 << 30)
362 #define IXGBE_FLAG2_RSC_CAPABLE (u32)(1)
363 #define IXGBE_FLAG2_RSC_ENABLED (u32)(1 << 1)
364 /* default to trying for four seconds */
365 #define IXGBE_TRY_LINK_TIMEOUT (4 * HZ)
367 /* OS defined structs */
368 struct net_device *netdev;
369 struct pci_dev *pdev;
372 struct ixgbe_ring test_tx_ring;
373 struct ixgbe_ring test_rx_ring;
375 /* structs defined in ixgbe_hw.h */
378 struct ixgbe_hw_stats stats;
380 /* Interrupt Throttle Rate */
386 unsigned int tx_ring_count;
387 unsigned int rx_ring_count;
391 unsigned long link_check_timeout;
393 struct work_struct watchdog_task;
394 struct work_struct sfp_task;
395 struct timer_list sfp_timer;
396 struct work_struct multispeed_fiber_task;
397 struct work_struct sfp_config_module_task;
400 spinlock_t fdir_perfect_lock;
401 struct work_struct fdir_reinit_task;
403 struct ixgbe_fcoe fcoe;
404 #endif /* IXGBE_FCOE */
413 DECLARE_BITMAP(active_vfs, IXGBE_MAX_VF_FUNCTIONS);
414 unsigned int num_vfs;
415 struct vf_data_storage *vfinfo;
422 __IXGBE_FDIR_INIT_DONE,
423 __IXGBE_SFP_MODULE_NOT_FOUND
431 extern struct ixgbe_info ixgbe_82598_info;
432 extern struct ixgbe_info ixgbe_82599_info;
433 #ifdef CONFIG_IXGBE_DCB
434 extern const struct dcbnl_rtnl_ops dcbnl_ops;
435 extern int ixgbe_copy_dcb_cfg(struct ixgbe_dcb_config *src_dcb_cfg,
436 struct ixgbe_dcb_config *dst_dcb_cfg,
440 extern char ixgbe_driver_name[];
441 extern const char ixgbe_driver_version[];
443 extern int ixgbe_up(struct ixgbe_adapter *adapter);
444 extern void ixgbe_down(struct ixgbe_adapter *adapter);
445 extern void ixgbe_reinit_locked(struct ixgbe_adapter *adapter);
446 extern void ixgbe_reset(struct ixgbe_adapter *adapter);
447 extern void ixgbe_set_ethtool_ops(struct net_device *netdev);
448 extern int ixgbe_setup_rx_resources(struct ixgbe_adapter *, struct ixgbe_ring *);
449 extern int ixgbe_setup_tx_resources(struct ixgbe_adapter *, struct ixgbe_ring *);
450 extern void ixgbe_free_rx_resources(struct ixgbe_adapter *, struct ixgbe_ring *);
451 extern void ixgbe_free_tx_resources(struct ixgbe_adapter *, struct ixgbe_ring *);
452 extern void ixgbe_update_stats(struct ixgbe_adapter *adapter);
453 extern int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter);
454 extern void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter);
455 extern void ixgbe_write_eitr(struct ixgbe_q_vector *);
456 extern int ethtool_ioctl(struct ifreq *ifr);
457 extern s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw);
458 extern s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 pballoc);
459 extern s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 pballoc);
460 extern s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
461 struct ixgbe_atr_input *input,
463 extern s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
464 struct ixgbe_atr_input *input,
465 struct ixgbe_atr_input_masks *input_masks,
466 u16 soft_id, u8 queue);
467 extern s32 ixgbe_atr_set_vlan_id_82599(struct ixgbe_atr_input *input,
469 extern s32 ixgbe_atr_set_src_ipv4_82599(struct ixgbe_atr_input *input,
471 extern s32 ixgbe_atr_set_dst_ipv4_82599(struct ixgbe_atr_input *input,
473 extern s32 ixgbe_atr_set_src_port_82599(struct ixgbe_atr_input *input,
475 extern s32 ixgbe_atr_set_dst_port_82599(struct ixgbe_atr_input *input,
477 extern s32 ixgbe_atr_set_flex_byte_82599(struct ixgbe_atr_input *input,
479 extern s32 ixgbe_atr_set_l4type_82599(struct ixgbe_atr_input *input,
481 extern void ixgbe_set_rx_mode(struct net_device *netdev);
483 extern void ixgbe_configure_fcoe(struct ixgbe_adapter *adapter);
484 extern int ixgbe_fso(struct ixgbe_adapter *adapter,
485 struct ixgbe_ring *tx_ring, struct sk_buff *skb,
486 u32 tx_flags, u8 *hdr_len);
487 extern void ixgbe_cleanup_fcoe(struct ixgbe_adapter *adapter);
488 extern int ixgbe_fcoe_ddp(struct ixgbe_adapter *adapter,
489 union ixgbe_adv_rx_desc *rx_desc,
490 struct sk_buff *skb);
491 extern int ixgbe_fcoe_ddp_get(struct net_device *netdev, u16 xid,
492 struct scatterlist *sgl, unsigned int sgc);
493 extern int ixgbe_fcoe_ddp_put(struct net_device *netdev, u16 xid);
494 extern int ixgbe_fcoe_enable(struct net_device *netdev);
495 extern int ixgbe_fcoe_disable(struct net_device *netdev);
496 #ifdef CONFIG_IXGBE_DCB
497 extern u8 ixgbe_fcoe_getapp(struct ixgbe_adapter *adapter);
498 extern u8 ixgbe_fcoe_setapp(struct ixgbe_adapter *adapter, u8 up);
499 #endif /* CONFIG_IXGBE_DCB */
500 extern int ixgbe_fcoe_get_wwn(struct net_device *netdev, u64 *wwn, int type);
501 #endif /* IXGBE_FCOE */
503 #endif /* _IXGBE_H_ */