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   1 /*******************************************************************************
   2
   3   Intel(R) Gigabit Ethernet Linux driver
   4   Copyright(c) 2007-2009 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 /* ethtool support for igb */
  29
  30 #include <linux/vmalloc.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/pci.h>
  33 #include <linux/delay.h>
  34 #include <linux/interrupt.h>
  35 #include <linux/if_ether.h>
  36 #include <linux/ethtool.h>
  37
  38 #include "igb.h"
  39
  40 struct igb_stats {
  41         char stat_string[ETH_GSTRING_LEN];
  42         int sizeof_stat;
  43         int stat_offset;
  44 };
  45
  46 #define IGB_STAT(m) FIELD_SIZEOF(struct igb_adapter, m), \
  47                       offsetof(struct igb_adapter, m)
  48 static const struct igb_stats igb_gstrings_stats[] = {
  49         { "rx_packets", IGB_STAT(stats.gprc) },
  50         { "tx_packets", IGB_STAT(stats.gptc) },
  51         { "rx_bytes", IGB_STAT(stats.gorc) },
  52         { "tx_bytes", IGB_STAT(stats.gotc) },
  53         { "rx_broadcast", IGB_STAT(stats.bprc) },
  54         { "tx_broadcast", IGB_STAT(stats.bptc) },
  55         { "rx_multicast", IGB_STAT(stats.mprc) },
  56         { "tx_multicast", IGB_STAT(stats.mptc) },
  57         { "rx_errors", IGB_STAT(net_stats.rx_errors) },
  58         { "tx_errors", IGB_STAT(net_stats.tx_errors) },
  59         { "tx_dropped", IGB_STAT(net_stats.tx_dropped) },
  60         { "multicast", IGB_STAT(stats.mprc) },
  61         { "collisions", IGB_STAT(stats.colc) },
  62         { "rx_length_errors", IGB_STAT(net_stats.rx_length_errors) },
  63         { "rx_over_errors", IGB_STAT(net_stats.rx_over_errors) },
  64         { "rx_crc_errors", IGB_STAT(stats.crcerrs) },
  65         { "rx_frame_errors", IGB_STAT(net_stats.rx_frame_errors) },
  66         { "rx_no_buffer_count", IGB_STAT(stats.rnbc) },
  67         { "rx_queue_drop_packet_count", IGB_STAT(net_stats.rx_fifo_errors) },
  68         { "rx_missed_errors", IGB_STAT(stats.mpc) },
  69         { "tx_aborted_errors", IGB_STAT(stats.ecol) },
  70         { "tx_carrier_errors", IGB_STAT(stats.tncrs) },
  71         { "tx_fifo_errors", IGB_STAT(net_stats.tx_fifo_errors) },
  72         { "tx_heartbeat_errors", IGB_STAT(net_stats.tx_heartbeat_errors) },
  73         { "tx_window_errors", IGB_STAT(stats.latecol) },
  74         { "tx_abort_late_coll", IGB_STAT(stats.latecol) },
  75         { "tx_deferred_ok", IGB_STAT(stats.dc) },
  76         { "tx_single_coll_ok", IGB_STAT(stats.scc) },
  77         { "tx_multi_coll_ok", IGB_STAT(stats.mcc) },
  78         { "tx_timeout_count", IGB_STAT(tx_timeout_count) },
  79         { "tx_restart_queue", IGB_STAT(restart_queue) },
  80         { "rx_long_length_errors", IGB_STAT(stats.roc) },
  81         { "rx_short_length_errors", IGB_STAT(stats.ruc) },
  82         { "rx_align_errors", IGB_STAT(stats.algnerrc) },
  83         { "tx_tcp_seg_good", IGB_STAT(stats.tsctc) },
  84         { "tx_tcp_seg_failed", IGB_STAT(stats.tsctfc) },
  85         { "rx_flow_control_xon", IGB_STAT(stats.xonrxc) },
  86         { "rx_flow_control_xoff", IGB_STAT(stats.xoffrxc) },
  87         { "tx_flow_control_xon", IGB_STAT(stats.xontxc) },
  88         { "tx_flow_control_xoff", IGB_STAT(stats.xofftxc) },
  89         { "rx_long_byte_count", IGB_STAT(stats.gorc) },
  90         { "rx_csum_offload_good", IGB_STAT(hw_csum_good) },
  91         { "rx_csum_offload_errors", IGB_STAT(hw_csum_err) },
  92         { "tx_dma_out_of_sync", IGB_STAT(stats.doosync) },
  93         { "alloc_rx_buff_failed", IGB_STAT(alloc_rx_buff_failed) },
  94         { "tx_smbus", IGB_STAT(stats.mgptc) },
  95         { "rx_smbus", IGB_STAT(stats.mgprc) },
  96         { "dropped_smbus", IGB_STAT(stats.mgpdc) },
  97 };
  98
  99 #define IGB_QUEUE_STATS_LEN \
 100         (((((struct igb_adapter *)netdev_priv(netdev))->num_rx_queues)* \
 101           (sizeof(struct igb_rx_queue_stats) / sizeof(u64))) + \
 102          ((((struct igb_adapter *)netdev_priv(netdev))->num_tx_queues) * \
 103           (sizeof(struct igb_tx_queue_stats) / sizeof(u64))))
 104 #define IGB_GLOBAL_STATS_LEN    \
 105         sizeof(igb_gstrings_stats) / sizeof(struct igb_stats)
 106 #define IGB_STATS_LEN (IGB_GLOBAL_STATS_LEN + IGB_QUEUE_STATS_LEN)
 107 static const char igb_gstrings_test[][ETH_GSTRING_LEN] = {
 108         "Register test  (offline)", "Eeprom test    (offline)",
 109         "Interrupt test (offline)", "Loopback test  (offline)",
 110         "Link test   (on/offline)"
 111 };
 112 #define IGB_TEST_LEN sizeof(igb_gstrings_test) / ETH_GSTRING_LEN
 113
 114 static int igb_get_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
 115 {
 116         struct igb_adapter *adapter = netdev_priv(netdev);
 117         struct e1000_hw *hw = &adapter->hw;
 118
 119         if (hw->phy.media_type == e1000_media_type_copper) {
 120
 121                 ecmd->supported = (SUPPORTED_10baseT_Half |
 122                                    SUPPORTED_10baseT_Full |
 123                                    SUPPORTED_100baseT_Half |
 124                                    SUPPORTED_100baseT_Full |
 125                                    SUPPORTED_1000baseT_Full|
 126                                    SUPPORTED_Autoneg |
 127                                    SUPPORTED_TP);
 128                 ecmd->advertising = ADVERTISED_TP;
 129
 130                 if (hw->mac.autoneg == 1) {
 131                         ecmd->advertising |= ADVERTISED_Autoneg;
 132                         /* the e1000 autoneg seems to match ethtool nicely */
 133                         ecmd->advertising |= hw->phy.autoneg_advertised;
 134                 }
 135
 136                 ecmd->port = PORT_TP;
 137                 ecmd->phy_address = hw->phy.addr;
 138         } else {
 139                 ecmd->supported   = (SUPPORTED_1000baseT_Full |
 140                                      SUPPORTED_FIBRE |
 141                                      SUPPORTED_Autoneg);
 142
 143                 ecmd->advertising = (ADVERTISED_1000baseT_Full |
 144                                      ADVERTISED_FIBRE |
 145                                      ADVERTISED_Autoneg);
 146
 147                 ecmd->port = PORT_FIBRE;
 148         }
 149
 150         ecmd->transceiver = XCVR_INTERNAL;
 151
 152         if (rd32(E1000_STATUS) & E1000_STATUS_LU) {
 153
 154                 adapter->hw.mac.ops.get_speed_and_duplex(hw,
 155                                         &adapter->link_speed,
 156                                         &adapter->link_duplex);
 157                 ecmd->speed = adapter->link_speed;
 158
 159                 /* unfortunately FULL_DUPLEX != DUPLEX_FULL
 160                  *          and HALF_DUPLEX != DUPLEX_HALF */
 161
 162                 if (adapter->link_duplex == FULL_DUPLEX)
 163                         ecmd->duplex = DUPLEX_FULL;
 164                 else
 165                         ecmd->duplex = DUPLEX_HALF;
 166         } else {
 167                 ecmd->speed = -1;
 168                 ecmd->duplex = -1;
 169         }
 170
 171         ecmd->autoneg = hw->mac.autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE;
 172         return 0;
 173 }
 174
 175 static int igb_set_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
 176 {
 177         struct igb_adapter *adapter = netdev_priv(netdev);
 178         struct e1000_hw *hw = &adapter->hw;
 179
 180         /* When SoL/IDER sessions are active, autoneg/speed/duplex
 181          * cannot be changed */
 182         if (igb_check_reset_block(hw)) {
 183                 dev_err(&adapter->pdev->dev, "Cannot change link "
 184                         "characteristics when SoL/IDER is active.\n");
 185                 return -EINVAL;
 186         }
 187
 188         while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
 189                 msleep(1);
 190
 191         if (ecmd->autoneg == AUTONEG_ENABLE) {
 192                 hw->mac.autoneg = 1;
 193                 hw->phy.autoneg_advertised = ecmd->advertising |
 194                                              ADVERTISED_TP |
 195                                              ADVERTISED_Autoneg;
 196                 ecmd->advertising = hw->phy.autoneg_advertised;
 197         } else {
 198                 if (igb_set_spd_dplx(adapter, ecmd->speed + ecmd->duplex)) {
 199                         clear_bit(__IGB_RESETTING, &adapter->state);
 200                         return -EINVAL;
 201                 }
 202         }
 203
 204         /* reset the link */
 205         if (netif_running(adapter->netdev)) {
 206                 igb_down(adapter);
 207                 igb_up(adapter);
 208         } else
 209                 igb_reset(adapter);
 210
 211         clear_bit(__IGB_RESETTING, &adapter->state);
 212         return 0;
 213 }
 214
 215 static void igb_get_pauseparam(struct net_device *netdev,
 216                                struct ethtool_pauseparam *pause)
 217 {
 218         struct igb_adapter *adapter = netdev_priv(netdev);
 219         struct e1000_hw *hw = &adapter->hw;
 220
 221         pause->autoneg =
 222                 (adapter->fc_autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE);
 223
 224         if (hw->fc.type == e1000_fc_rx_pause)
 225                 pause->rx_pause = 1;
 226         else if (hw->fc.type == e1000_fc_tx_pause)
 227                 pause->tx_pause = 1;
 228         else if (hw->fc.type == e1000_fc_full) {
 229                 pause->rx_pause = 1;
 230                 pause->tx_pause = 1;
 231         }
 232 }
 233
 234 static int igb_set_pauseparam(struct net_device *netdev,
 235                               struct ethtool_pauseparam *pause)
 236 {
 237         struct igb_adapter *adapter = netdev_priv(netdev);
 238         struct e1000_hw *hw = &adapter->hw;
 239         int retval = 0;
 240
 241         adapter->fc_autoneg = pause->autoneg;
 242
 243         while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
 244                 msleep(1);
 245
 246         if (pause->rx_pause && pause->tx_pause)
 247                 hw->fc.type = e1000_fc_full;
 248         else if (pause->rx_pause && !pause->tx_pause)
 249                 hw->fc.type = e1000_fc_rx_pause;
 250         else if (!pause->rx_pause && pause->tx_pause)
 251                 hw->fc.type = e1000_fc_tx_pause;
 252         else if (!pause->rx_pause && !pause->tx_pause)
 253                 hw->fc.type = e1000_fc_none;
 254
 255         hw->fc.original_type = hw->fc.type;
 256
 257         if (adapter->fc_autoneg == AUTONEG_ENABLE) {
 258                 if (netif_running(adapter->netdev)) {
 259                         igb_down(adapter);
 260                         igb_up(adapter);
 261                 } else
 262                         igb_reset(adapter);
 263         } else
 264                 retval = ((hw->phy.media_type == e1000_media_type_copper) ?
 265                           igb_force_mac_fc(hw) : igb_setup_link(hw));
 266
 267         clear_bit(__IGB_RESETTING, &adapter->state);
 268         return retval;
 269 }
 270
 271 static u32 igb_get_rx_csum(struct net_device *netdev)
 272 {
 273         struct igb_adapter *adapter = netdev_priv(netdev);
 274         return !(adapter->flags & IGB_FLAG_RX_CSUM_DISABLED);
 275 }
 276
 277 static int igb_set_rx_csum(struct net_device *netdev, u32 data)
 278 {
 279         struct igb_adapter *adapter = netdev_priv(netdev);
 280
 281         if (data)
 282                 adapter->flags &= ~IGB_FLAG_RX_CSUM_DISABLED;
 283         else
 284                 adapter->flags |= IGB_FLAG_RX_CSUM_DISABLED;
 285
 286         return 0;
 287 }
 288
 289 static u32 igb_get_tx_csum(struct net_device *netdev)
 290 {
 291         return (netdev->features & NETIF_F_IP_CSUM) != 0;
 292 }
 293
 294 static int igb_set_tx_csum(struct net_device *netdev, u32 data)
 295 {
 296         struct igb_adapter *adapter = netdev_priv(netdev);
 297
 298         if (data) {
 299                 netdev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
 300                 if (adapter->hw.mac.type == e1000_82576)
 301                         netdev->features |= NETIF_F_SCTP_CSUM;
 302         } else {
 303                 netdev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
 304                                       NETIF_F_SCTP_CSUM);
 305         }
 306
 307         return 0;
 308 }
 309
 310 static int igb_set_tso(struct net_device *netdev, u32 data)
 311 {
 312         struct igb_adapter *adapter = netdev_priv(netdev);
 313
 314         if (data) {
 315                 netdev->features |= NETIF_F_TSO;
 316                 netdev->features |= NETIF_F_TSO6;
 317         } else {
 318                 netdev->features &= ~NETIF_F_TSO;
 319                 netdev->features &= ~NETIF_F_TSO6;
 320         }
 321
 322         dev_info(&adapter->pdev->dev, "TSO is %s\n",
 323                  data ? "Enabled" : "Disabled");
 324         return 0;
 325 }
 326
 327 static u32 igb_get_msglevel(struct net_device *netdev)
 328 {
 329         struct igb_adapter *adapter = netdev_priv(netdev);
 330         return adapter->msg_enable;
 331 }
 332
 333 static void igb_set_msglevel(struct net_device *netdev, u32 data)
 334 {
 335         struct igb_adapter *adapter = netdev_priv(netdev);
 336         adapter->msg_enable = data;
 337 }
 338
 339 static int igb_get_regs_len(struct net_device *netdev)
 340 {
 341 #define IGB_REGS_LEN 551
 342         return IGB_REGS_LEN * sizeof(u32);
 343 }
 344
 345 static void igb_get_regs(struct net_device *netdev,
 346                          struct ethtool_regs *regs, void *p)
 347 {
 348         struct igb_adapter *adapter = netdev_priv(netdev);
 349         struct e1000_hw *hw = &adapter->hw;
 350         u32 *regs_buff = p;
 351         u8 i;
 352
 353         memset(p, 0, IGB_REGS_LEN * sizeof(u32));
 354
 355         regs->version = (1 << 24) | (hw->revision_id << 16) | hw->device_id;
 356
 357         /* General Registers */
 358         regs_buff[0] = rd32(E1000_CTRL);
 359         regs_buff[1] = rd32(E1000_STATUS);
 360         regs_buff[2] = rd32(E1000_CTRL_EXT);
 361         regs_buff[3] = rd32(E1000_MDIC);
 362         regs_buff[4] = rd32(E1000_SCTL);
 363         regs_buff[5] = rd32(E1000_CONNSW);
 364         regs_buff[6] = rd32(E1000_VET);
 365         regs_buff[7] = rd32(E1000_LEDCTL);
 366         regs_buff[8] = rd32(E1000_PBA);
 367         regs_buff[9] = rd32(E1000_PBS);
 368         regs_buff[10] = rd32(E1000_FRTIMER);
 369         regs_buff[11] = rd32(E1000_TCPTIMER);
 370
 371         /* NVM Register */
 372         regs_buff[12] = rd32(E1000_EECD);
 373
 374         /* Interrupt */
 375         /* Reading EICS for EICR because they read the
 376          * same but EICS does not clear on read */
 377         regs_buff[13] = rd32(E1000_EICS);
 378         regs_buff[14] = rd32(E1000_EICS);
 379         regs_buff[15] = rd32(E1000_EIMS);
 380         regs_buff[16] = rd32(E1000_EIMC);
 381         regs_buff[17] = rd32(E1000_EIAC);
 382         regs_buff[18] = rd32(E1000_EIAM);
 383         /* Reading ICS for ICR because they read the
 384          * same but ICS does not clear on read */
 385         regs_buff[19] = rd32(E1000_ICS);
 386         regs_buff[20] = rd32(E1000_ICS);
 387         regs_buff[21] = rd32(E1000_IMS);
 388         regs_buff[22] = rd32(E1000_IMC);
 389         regs_buff[23] = rd32(E1000_IAC);
 390         regs_buff[24] = rd32(E1000_IAM);
 391         regs_buff[25] = rd32(E1000_IMIRVP);
 392
 393         /* Flow Control */
 394         regs_buff[26] = rd32(E1000_FCAL);
 395         regs_buff[27] = rd32(E1000_FCAH);
 396         regs_buff[28] = rd32(E1000_FCTTV);
 397         regs_buff[29] = rd32(E1000_FCRTL);
 398         regs_buff[30] = rd32(E1000_FCRTH);
 399         regs_buff[31] = rd32(E1000_FCRTV);
 400
 401         /* Receive */
 402         regs_buff[32] = rd32(E1000_RCTL);
 403         regs_buff[33] = rd32(E1000_RXCSUM);
 404         regs_buff[34] = rd32(E1000_RLPML);
 405         regs_buff[35] = rd32(E1000_RFCTL);
 406         regs_buff[36] = rd32(E1000_MRQC);
 407         regs_buff[37] = rd32(E1000_VT_CTL);
 408
 409         /* Transmit */
 410         regs_buff[38] = rd32(E1000_TCTL);
 411         regs_buff[39] = rd32(E1000_TCTL_EXT);
 412         regs_buff[40] = rd32(E1000_TIPG);
 413         regs_buff[41] = rd32(E1000_DTXCTL);
 414
 415         /* Wake Up */
 416         regs_buff[42] = rd32(E1000_WUC);
 417         regs_buff[43] = rd32(E1000_WUFC);
 418         regs_buff[44] = rd32(E1000_WUS);
 419         regs_buff[45] = rd32(E1000_IPAV);
 420         regs_buff[46] = rd32(E1000_WUPL);
 421
 422         /* MAC */
 423         regs_buff[47] = rd32(E1000_PCS_CFG0);
 424         regs_buff[48] = rd32(E1000_PCS_LCTL);
 425         regs_buff[49] = rd32(E1000_PCS_LSTAT);
 426         regs_buff[50] = rd32(E1000_PCS_ANADV);
 427         regs_buff[51] = rd32(E1000_PCS_LPAB);
 428         regs_buff[52] = rd32(E1000_PCS_NPTX);
 429         regs_buff[53] = rd32(E1000_PCS_LPABNP);
 430
 431         /* Statistics */
 432         regs_buff[54] = adapter->stats.crcerrs;
 433         regs_buff[55] = adapter->stats.algnerrc;
 434         regs_buff[56] = adapter->stats.symerrs;
 435         regs_buff[57] = adapter->stats.rxerrc;
 436         regs_buff[58] = adapter->stats.mpc;
 437         regs_buff[59] = adapter->stats.scc;
 438         regs_buff[60] = adapter->stats.ecol;
 439         regs_buff[61] = adapter->stats.mcc;
 440         regs_buff[62] = adapter->stats.latecol;
 441         regs_buff[63] = adapter->stats.colc;
 442         regs_buff[64] = adapter->stats.dc;
 443         regs_buff[65] = adapter->stats.tncrs;
 444         regs_buff[66] = adapter->stats.sec;
 445         regs_buff[67] = adapter->stats.htdpmc;
 446         regs_buff[68] = adapter->stats.rlec;
 447         regs_buff[69] = adapter->stats.xonrxc;
 448         regs_buff[70] = adapter->stats.xontxc;
 449         regs_buff[71] = adapter->stats.xoffrxc;
 450         regs_buff[72] = adapter->stats.xofftxc;
 451         regs_buff[73] = adapter->stats.fcruc;
 452         regs_buff[74] = adapter->stats.prc64;
 453         regs_buff[75] = adapter->stats.prc127;
 454         regs_buff[76] = adapter->stats.prc255;
 455         regs_buff[77] = adapter->stats.prc511;
 456         regs_buff[78] = adapter->stats.prc1023;
 457         regs_buff[79] = adapter->stats.prc1522;
 458         regs_buff[80] = adapter->stats.gprc;
 459         regs_buff[81] = adapter->stats.bprc;
 460         regs_buff[82] = adapter->stats.mprc;
 461         regs_buff[83] = adapter->stats.gptc;
 462         regs_buff[84] = adapter->stats.gorc;
 463         regs_buff[86] = adapter->stats.gotc;
 464         regs_buff[88] = adapter->stats.rnbc;
 465         regs_buff[89] = adapter->stats.ruc;
 466         regs_buff[90] = adapter->stats.rfc;
 467         regs_buff[91] = adapter->stats.roc;
 468         regs_buff[92] = adapter->stats.rjc;
 469         regs_buff[93] = adapter->stats.mgprc;
 470         regs_buff[94] = adapter->stats.mgpdc;
 471         regs_buff[95] = adapter->stats.mgptc;
 472         regs_buff[96] = adapter->stats.tor;
 473         regs_buff[98] = adapter->stats.tot;
 474         regs_buff[100] = adapter->stats.tpr;
 475         regs_buff[101] = adapter->stats.tpt;
 476         regs_buff[102] = adapter->stats.ptc64;
 477         regs_buff[103] = adapter->stats.ptc127;
 478         regs_buff[104] = adapter->stats.ptc255;
 479         regs_buff[105] = adapter->stats.ptc511;
 480         regs_buff[106] = adapter->stats.ptc1023;
 481         regs_buff[107] = adapter->stats.ptc1522;
 482         regs_buff[108] = adapter->stats.mptc;
 483         regs_buff[109] = adapter->stats.bptc;
 484         regs_buff[110] = adapter->stats.tsctc;
 485         regs_buff[111] = adapter->stats.iac;
 486         regs_buff[112] = adapter->stats.rpthc;
 487         regs_buff[113] = adapter->stats.hgptc;
 488         regs_buff[114] = adapter->stats.hgorc;
 489         regs_buff[116] = adapter->stats.hgotc;
 490         regs_buff[118] = adapter->stats.lenerrs;
 491         regs_buff[119] = adapter->stats.scvpc;
 492         regs_buff[120] = adapter->stats.hrmpc;
 493
 494         /* These should probably be added to e1000_regs.h instead */
 495         #define E1000_PSRTYPE_REG(_i) (0x05480 + ((_i) * 4))
 496         #define E1000_IP4AT_REG(_i)   (0x05840 + ((_i) * 8))
 497         #define E1000_IP6AT_REG(_i)   (0x05880 + ((_i) * 4))
 498         #define E1000_WUPM_REG(_i)    (0x05A00 + ((_i) * 4))
 499         #define E1000_FFMT_REG(_i)    (0x09000 + ((_i) * 8))
 500         #define E1000_FFVT_REG(_i)    (0x09800 + ((_i) * 8))
 501         #define E1000_FFLT_REG(_i)    (0x05F00 + ((_i) * 8))
 502
 503         for (i = 0; i < 4; i++)
 504                 regs_buff[121 + i] = rd32(E1000_SRRCTL(i));
 505         for (i = 0; i < 4; i++)
 506                 regs_buff[125 + i] = rd32(E1000_PSRTYPE_REG(i));
 507         for (i = 0; i < 4; i++)
 508                 regs_buff[129 + i] = rd32(E1000_RDBAL(i));
 509         for (i = 0; i < 4; i++)
 510                 regs_buff[133 + i] = rd32(E1000_RDBAH(i));
 511         for (i = 0; i < 4; i++)
 512                 regs_buff[137 + i] = rd32(E1000_RDLEN(i));
 513         for (i = 0; i < 4; i++)
 514                 regs_buff[141 + i] = rd32(E1000_RDH(i));
 515         for (i = 0; i < 4; i++)
 516                 regs_buff[145 + i] = rd32(E1000_RDT(i));
 517         for (i = 0; i < 4; i++)
 518                 regs_buff[149 + i] = rd32(E1000_RXDCTL(i));
 519
 520         for (i = 0; i < 10; i++)
 521                 regs_buff[153 + i] = rd32(E1000_EITR(i));
 522         for (i = 0; i < 8; i++)
 523                 regs_buff[163 + i] = rd32(E1000_IMIR(i));
 524         for (i = 0; i < 8; i++)
 525                 regs_buff[171 + i] = rd32(E1000_IMIREXT(i));
 526         for (i = 0; i < 16; i++)
 527                 regs_buff[179 + i] = rd32(E1000_RAL(i));
 528         for (i = 0; i < 16; i++)
 529                 regs_buff[195 + i] = rd32(E1000_RAH(i));
 530
 531         for (i = 0; i < 4; i++)
 532                 regs_buff[211 + i] = rd32(E1000_TDBAL(i));
 533         for (i = 0; i < 4; i++)
 534                 regs_buff[215 + i] = rd32(E1000_TDBAH(i));
 535         for (i = 0; i < 4; i++)
 536                 regs_buff[219 + i] = rd32(E1000_TDLEN(i));
 537         for (i = 0; i < 4; i++)
 538                 regs_buff[223 + i] = rd32(E1000_TDH(i));
 539         for (i = 0; i < 4; i++)
 540                 regs_buff[227 + i] = rd32(E1000_TDT(i));
 541         for (i = 0; i < 4; i++)
 542                 regs_buff[231 + i] = rd32(E1000_TXDCTL(i));
 543         for (i = 0; i < 4; i++)
 544                 regs_buff[235 + i] = rd32(E1000_TDWBAL(i));
 545         for (i = 0; i < 4; i++)
 546                 regs_buff[239 + i] = rd32(E1000_TDWBAH(i));
 547         for (i = 0; i < 4; i++)
 548                 regs_buff[243 + i] = rd32(E1000_DCA_TXCTRL(i));
 549
 550         for (i = 0; i < 4; i++)
 551                 regs_buff[247 + i] = rd32(E1000_IP4AT_REG(i));
 552         for (i = 0; i < 4; i++)
 553                 regs_buff[251 + i] = rd32(E1000_IP6AT_REG(i));
 554         for (i = 0; i < 32; i++)
 555                 regs_buff[255 + i] = rd32(E1000_WUPM_REG(i));
 556         for (i = 0; i < 128; i++)
 557                 regs_buff[287 + i] = rd32(E1000_FFMT_REG(i));
 558         for (i = 0; i < 128; i++)
 559                 regs_buff[415 + i] = rd32(E1000_FFVT_REG(i));
 560         for (i = 0; i < 4; i++)
 561                 regs_buff[543 + i] = rd32(E1000_FFLT_REG(i));
 562
 563         regs_buff[547] = rd32(E1000_TDFH);
 564         regs_buff[548] = rd32(E1000_TDFT);
 565         regs_buff[549] = rd32(E1000_TDFHS);
 566         regs_buff[550] = rd32(E1000_TDFPC);
 567
 568 }
 569
 570 static int igb_get_eeprom_len(struct net_device *netdev)
 571 {
 572         struct igb_adapter *adapter = netdev_priv(netdev);
 573         return adapter->hw.nvm.word_size * 2;
 574 }
 575
 576 static int igb_get_eeprom(struct net_device *netdev,
 577                           struct ethtool_eeprom *eeprom, u8 *bytes)
 578 {
 579         struct igb_adapter *adapter = netdev_priv(netdev);
 580         struct e1000_hw *hw = &adapter->hw;
 581         u16 *eeprom_buff;
 582         int first_word, last_word;
 583         int ret_val = 0;
 584         u16 i;
 585
 586         if (eeprom->len == 0)
 587                 return -EINVAL;
 588
 589         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
 590
 591         first_word = eeprom->offset >> 1;
 592         last_word = (eeprom->offset + eeprom->len - 1) >> 1;
 593
 594         eeprom_buff = kmalloc(sizeof(u16) *
 595                         (last_word - first_word + 1), GFP_KERNEL);
 596         if (!eeprom_buff)
 597                 return -ENOMEM;
 598
 599         if (hw->nvm.type == e1000_nvm_eeprom_spi)
 600                 ret_val = hw->nvm.ops.read(hw, first_word,
 601                                             last_word - first_word + 1,
 602                                             eeprom_buff);
 603         else {
 604                 for (i = 0; i < last_word - first_word + 1; i++) {
 605                         ret_val = hw->nvm.ops.read(hw, first_word + i, 1,
 606                                                     &eeprom_buff[i]);
 607                         if (ret_val)
 608                                 break;
 609                 }
 610         }
 611
 612         /* Device's eeprom is always little-endian, word addressable */
 613         for (i = 0; i < last_word - first_word + 1; i++)
 614                 le16_to_cpus(&eeprom_buff[i]);
 615
 616         memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1),
 617                         eeprom->len);
 618         kfree(eeprom_buff);
 619
 620         return ret_val;
 621 }
 622
 623 static int igb_set_eeprom(struct net_device *netdev,
 624                           struct ethtool_eeprom *eeprom, u8 *bytes)
 625 {
 626         struct igb_adapter *adapter = netdev_priv(netdev);
 627         struct e1000_hw *hw = &adapter->hw;
 628         u16 *eeprom_buff;
 629         void *ptr;
 630         int max_len, first_word, last_word, ret_val = 0;
 631         u16 i;
 632
 633         if (eeprom->len == 0)
 634                 return -EOPNOTSUPP;
 635
 636         if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16)))
 637                 return -EFAULT;
 638
 639         max_len = hw->nvm.word_size * 2;
 640
 641         first_word = eeprom->offset >> 1;
 642         last_word = (eeprom->offset + eeprom->len - 1) >> 1;
 643         eeprom_buff = kmalloc(max_len, GFP_KERNEL);
 644         if (!eeprom_buff)
 645                 return -ENOMEM;
 646
 647         ptr = (void *)eeprom_buff;
 648
 649         if (eeprom->offset & 1) {
 650                 /* need read/modify/write of first changed EEPROM word */
 651                 /* only the second byte of the word is being modified */
 652                 ret_val = hw->nvm.ops.read(hw, first_word, 1,
 653                                             &eeprom_buff[0]);
 654                 ptr++;
 655         }
 656         if (((eeprom->offset + eeprom->len) & 1) && (ret_val == 0)) {
 657                 /* need read/modify/write of last changed EEPROM word */
 658                 /* only the first byte of the word is being modified */
 659                 ret_val = hw->nvm.ops.read(hw, last_word, 1,
 660                                    &eeprom_buff[last_word - first_word]);
 661         }
 662
 663         /* Device's eeprom is always little-endian, word addressable */
 664         for (i = 0; i < last_word - first_word + 1; i++)
 665                 le16_to_cpus(&eeprom_buff[i]);
 666
 667         memcpy(ptr, bytes, eeprom->len);
 668
 669         for (i = 0; i < last_word - first_word + 1; i++)
 670                 eeprom_buff[i] = cpu_to_le16(eeprom_buff[i]);
 671
 672         ret_val = hw->nvm.ops.write(hw, first_word,
 673                                      last_word - first_word + 1, eeprom_buff);
 674
 675         /* Update the checksum over the first part of the EEPROM if needed
 676          * and flush shadow RAM for 82573 controllers */
 677         if ((ret_val == 0) && ((first_word <= NVM_CHECKSUM_REG)))
 678                 igb_update_nvm_checksum(hw);
 679
 680         kfree(eeprom_buff);
 681         return ret_val;
 682 }
 683
 684 static void igb_get_drvinfo(struct net_device *netdev,
 685                             struct ethtool_drvinfo *drvinfo)
 686 {
 687         struct igb_adapter *adapter = netdev_priv(netdev);
 688         char firmware_version[32];
 689         u16 eeprom_data;
 690
 691         strncpy(drvinfo->driver,  igb_driver_name, 32);
 692         strncpy(drvinfo->version, igb_driver_version, 32);
 693
 694         /* EEPROM image version # is reported as firmware version # for
 695          * 82575 controllers */
 696         adapter->hw.nvm.ops.read(&adapter->hw, 5, 1, &eeprom_data);
 697         sprintf(firmware_version, "%d.%d-%d",
 698                 (eeprom_data & 0xF000) >> 12,
 699                 (eeprom_data & 0x0FF0) >> 4,
 700                 eeprom_data & 0x000F);
 701
 702         strncpy(drvinfo->fw_version, firmware_version, 32);
 703         strncpy(drvinfo->bus_info, pci_name(adapter->pdev), 32);
 704         drvinfo->n_stats = IGB_STATS_LEN;
 705         drvinfo->testinfo_len = IGB_TEST_LEN;
 706         drvinfo->regdump_len = igb_get_regs_len(netdev);
 707         drvinfo->eedump_len = igb_get_eeprom_len(netdev);
 708 }
 709
 710 static void igb_get_ringparam(struct net_device *netdev,
 711                               struct ethtool_ringparam *ring)
 712 {
 713         struct igb_adapter *adapter = netdev_priv(netdev);
 714
 715         ring->rx_max_pending = IGB_MAX_RXD;
 716         ring->tx_max_pending = IGB_MAX_TXD;
 717         ring->rx_mini_max_pending = 0;
 718         ring->rx_jumbo_max_pending = 0;
 719         ring->rx_pending = adapter->rx_ring_count;
 720         ring->tx_pending = adapter->tx_ring_count;
 721         ring->rx_mini_pending = 0;
 722         ring->rx_jumbo_pending = 0;
 723 }
 724
 725 static int igb_set_ringparam(struct net_device *netdev,
 726                              struct ethtool_ringparam *ring)
 727 {
 728         struct igb_adapter *adapter = netdev_priv(netdev);
 729         struct igb_ring *temp_ring;
 730         int i, err;
 731         u32 new_rx_count, new_tx_count;
 732
 733         if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
 734                 return -EINVAL;
 735
 736         new_rx_count = max(ring->rx_pending, (u32)IGB_MIN_RXD);
 737         new_rx_count = min(new_rx_count, (u32)IGB_MAX_RXD);
 738         new_rx_count = ALIGN(new_rx_count, REQ_RX_DESCRIPTOR_MULTIPLE);
 739
 740         new_tx_count = max(ring->tx_pending, (u32)IGB_MIN_TXD);
 741         new_tx_count = min(new_tx_count, (u32)IGB_MAX_TXD);
 742         new_tx_count = ALIGN(new_tx_count, REQ_TX_DESCRIPTOR_MULTIPLE);
 743
 744         if ((new_tx_count == adapter->tx_ring_count) &&
 745             (new_rx_count == adapter->rx_ring_count)) {
 746                 /* nothing to do */
 747                 return 0;
 748         }
 749
 750         if (adapter->num_tx_queues > adapter->num_rx_queues)
 751                 temp_ring = vmalloc(adapter->num_tx_queues * sizeof(struct igb_ring));
 752         else
 753                 temp_ring = vmalloc(adapter->num_rx_queues * sizeof(struct igb_ring));
 754         if (!temp_ring)
 755                 return -ENOMEM;
 756
 757         while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
 758                 msleep(1);
 759
 760         if (netif_running(adapter->netdev))
 761                 igb_down(adapter);
 762
 763         /*
 764          * We can't just free everything and then setup again,
 765          * because the ISRs in MSI-X mode get passed pointers
 766          * to the tx and rx ring structs.
 767          */
 768         if (new_tx_count != adapter->tx_ring_count) {
 769                 memcpy(temp_ring, adapter->tx_ring,
 770                        adapter->num_tx_queues * sizeof(struct igb_ring));
 771
 772                 for (i = 0; i < adapter->num_tx_queues; i++) {
 773                         temp_ring[i].count = new_tx_count;
 774                         err = igb_setup_tx_resources(adapter, &temp_ring[i]);
 775                         if (err) {
 776                                 while (i) {
 777                                         i--;
 778                                         igb_free_tx_resources(&temp_ring[i]);
 779                                 }
 780                                 goto err_setup;
 781                         }
 782                 }
 783
 784                 for (i = 0; i < adapter->num_tx_queues; i++)
 785                         igb_free_tx_resources(&adapter->tx_ring[i]);
 786
 787                 memcpy(adapter->tx_ring, temp_ring,
 788                        adapter->num_tx_queues * sizeof(struct igb_ring));
 789
 790                 adapter->tx_ring_count = new_tx_count;
 791         }
 792
 793         if (new_rx_count != adapter->rx_ring->count) {
 794                 memcpy(temp_ring, adapter->rx_ring,
 795                        adapter->num_rx_queues * sizeof(struct igb_ring));
 796
 797                 for (i = 0; i < adapter->num_rx_queues; i++) {
 798                         temp_ring[i].count = new_rx_count;
 799                         err = igb_setup_rx_resources(adapter, &temp_ring[i]);
 800                         if (err) {
 801                                 while (i) {
 802                                         i--;
 803                                         igb_free_rx_resources(&temp_ring[i]);
 804                                 }
 805                                 goto err_setup;
 806                         }
 807
 808                 }
 809
 810                 for (i = 0; i < adapter->num_rx_queues; i++)
 811                         igb_free_rx_resources(&adapter->rx_ring[i]);
 812
 813                 memcpy(adapter->rx_ring, temp_ring,
 814                        adapter->num_rx_queues * sizeof(struct igb_ring));
 815
 816                 adapter->rx_ring_count = new_rx_count;
 817         }
 818
 819         err = 0;
 820 err_setup:
 821         if (netif_running(adapter->netdev))
 822                 igb_up(adapter);
 823
 824         clear_bit(__IGB_RESETTING, &adapter->state);
 825         vfree(temp_ring);
 826         return err;
 827 }
 828
 829 /* ethtool register test data */
 830 struct igb_reg_test {
 831         u16 reg;
 832         u16 reg_offset;
 833         u16 array_len;
 834         u16 test_type;
 835         u32 mask;
 836         u32 write;
 837 };
 838
 839 /* In the hardware, registers are laid out either singly, in arrays
 840  * spaced 0x100 bytes apart, or in contiguous tables.  We assume
 841  * most tests take place on arrays or single registers (handled
 842  * as a single-element array) and special-case the tables.
 843  * Table tests are always pattern tests.
 844  *
 845  * We also make provision for some required setup steps by specifying
 846  * registers to be written without any read-back testing.
 847  */
 848
 849 #define PATTERN_TEST    1
 850 #define SET_READ_TEST   2
 851 #define WRITE_NO_TEST   3
 852 #define TABLE32_TEST    4
 853 #define TABLE64_TEST_LO 5
 854 #define TABLE64_TEST_HI 6
 855
 856 /* 82576 reg test */
 857 static struct igb_reg_test reg_test_82576[] = {
 858         { E1000_FCAL,      0x100, 1,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 859         { E1000_FCAH,      0x100, 1,  PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
 860         { E1000_FCT,       0x100, 1,  PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
 861         { E1000_VET,       0x100, 1,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 862         { E1000_RDBAL(0),  0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
 863         { E1000_RDBAH(0),  0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 864         { E1000_RDLEN(0),  0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
 865         { E1000_RDBAL(4),  0x40, 12, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
 866         { E1000_RDBAH(4),  0x40, 12, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 867         { E1000_RDLEN(4),  0x40, 12, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
 868         /* Enable all RX queues before testing. */
 869         { E1000_RXDCTL(0), 0x100, 4,  WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE },
 870         { E1000_RXDCTL(4), 0x40, 12,  WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE },
 871         /* RDH is read-only for 82576, only test RDT. */
 872         { E1000_RDT(0),    0x100, 4,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
 873         { E1000_RDT(4),    0x40, 12,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
 874         { E1000_RXDCTL(0), 0x100, 4,  WRITE_NO_TEST, 0, 0 },
 875         { E1000_RXDCTL(4), 0x40, 12,  WRITE_NO_TEST, 0, 0 },
 876         { E1000_FCRTH,     0x100, 1,  PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
 877         { E1000_FCTTV,     0x100, 1,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
 878         { E1000_TIPG,      0x100, 1,  PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
 879         { E1000_TDBAL(0),  0x100, 4,  PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
 880         { E1000_TDBAH(0),  0x100, 4,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 881         { E1000_TDLEN(0),  0x100, 4,  PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
 882         { E1000_TDBAL(4),  0x40, 12,  PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
 883         { E1000_TDBAH(4),  0x40, 12,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 884         { E1000_TDLEN(4),  0x40, 12,  PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
 885         { E1000_RCTL,      0x100, 1,  SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
 886         { E1000_RCTL,      0x100, 1,  SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
 887         { E1000_RCTL,      0x100, 1,  SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
 888         { E1000_TCTL,      0x100, 1,  SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
 889         { E1000_RA,        0, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
 890         { E1000_RA,        0, 16, TABLE64_TEST_HI, 0x83FFFFFF, 0xFFFFFFFF },
 891         { E1000_RA2,       0, 8, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
 892         { E1000_RA2,       0, 8, TABLE64_TEST_HI, 0x83FFFFFF, 0xFFFFFFFF },
 893         { E1000_MTA,       0, 128,TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 894         { 0, 0, 0, 0 }
 895 };
 896
 897 /* 82575 register test */
 898 static struct igb_reg_test reg_test_82575[] = {
 899         { E1000_FCAL,      0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 900         { E1000_FCAH,      0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
 901         { E1000_FCT,       0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
 902         { E1000_VET,       0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 903         { E1000_RDBAL(0),  0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
 904         { E1000_RDBAH(0),  0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 905         { E1000_RDLEN(0),  0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
 906         /* Enable all four RX queues before testing. */
 907         { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE },
 908         /* RDH is read-only for 82575, only test RDT. */
 909         { E1000_RDT(0),    0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
 910         { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 0 },
 911         { E1000_FCRTH,     0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
 912         { E1000_FCTTV,     0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
 913         { E1000_TIPG,      0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
 914         { E1000_TDBAL(0),  0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
 915         { E1000_TDBAH(0),  0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 916         { E1000_TDLEN(0),  0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
 917         { E1000_RCTL,      0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
 918         { E1000_RCTL,      0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0x003FFFFB },
 919         { E1000_RCTL,      0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0xFFFFFFFF },
 920         { E1000_TCTL,      0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
 921         { E1000_TXCW,      0x100, 1, PATTERN_TEST, 0xC000FFFF, 0x0000FFFF },
 922         { E1000_RA,        0, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
 923         { E1000_RA,        0, 16, TABLE64_TEST_HI, 0x800FFFFF, 0xFFFFFFFF },
 924         { E1000_MTA,       0, 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 925         { 0, 0, 0, 0 }
 926 };
 927
 928 static bool reg_pattern_test(struct igb_adapter *adapter, u64 *data,
 929                              int reg, u32 mask, u32 write)
 930 {
 931         struct e1000_hw *hw = &adapter->hw;
 932         u32 pat, val;
 933         u32 _test[] =
 934                 {0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF};
 935         for (pat = 0; pat < ARRAY_SIZE(_test); pat++) {
 936                 wr32(reg, (_test[pat] & write));
 937                 val = rd32(reg);
 938                 if (val != (_test[pat] & write & mask)) {
 939                         dev_err(&adapter->pdev->dev, "pattern test reg %04X "
 940                                 "failed: got 0x%08X expected 0x%08X\n",
 941                                 reg, val, (_test[pat] & write & mask));
 942                         *data = reg;
 943                         return 1;
 944                 }
 945         }
 946         return 0;
 947 }
 948
 949 static bool reg_set_and_check(struct igb_adapter *adapter, u64 *data,
 950                               int reg, u32 mask, u32 write)
 951 {
 952         struct e1000_hw *hw = &adapter->hw;
 953         u32 val;
 954         wr32(reg, write & mask);
 955         val = rd32(reg);
 956         if ((write & mask) != (val & mask)) {
 957                 dev_err(&adapter->pdev->dev, "set/check reg %04X test failed:"
 958                         " got 0x%08X expected 0x%08X\n", reg,
 959                         (val & mask), (write & mask));
 960                 *data = reg;
 961                 return 1;
 962         }
 963         return 0;
 964 }
 965
 966 #define REG_PATTERN_TEST(reg, mask, write) \
 967         do { \
 968                 if (reg_pattern_test(adapter, data, reg, mask, write)) \
 969                         return 1; \
 970         } while (0)
 971
 972 #define REG_SET_AND_CHECK(reg, mask, write) \
 973         do { \
 974                 if (reg_set_and_check(adapter, data, reg, mask, write)) \
 975                         return 1; \
 976         } while (0)
 977
 978 static int igb_reg_test(struct igb_adapter *adapter, u64 *data)
 979 {
 980         struct e1000_hw *hw = &adapter->hw;
 981         struct igb_reg_test *test;
 982         u32 value, before, after;
 983         u32 i, toggle;
 984
 985         toggle = 0x7FFFF3FF;
 986
 987         switch (adapter->hw.mac.type) {
 988         case e1000_82576:
 989                 test = reg_test_82576;
 990                 break;
 991         default:
 992                 test = reg_test_82575;
 993                 break;
 994         }
 995
 996         /* Because the status register is such a special case,
 997          * we handle it separately from the rest of the register
 998          * tests.  Some bits are read-only, some toggle, and some
 999          * are writable on newer MACs.
1000          */
1001         before = rd32(E1000_STATUS);
1002         value = (rd32(E1000_STATUS) & toggle);
1003         wr32(E1000_STATUS, toggle);
1004         after = rd32(E1000_STATUS) & toggle;
1005         if (value != after) {
1006                 dev_err(&adapter->pdev->dev, "failed STATUS register test "
1007                         "got: 0x%08X expected: 0x%08X\n", after, value);
1008                 *data = 1;
1009                 return 1;
1010         }
1011         /* restore previous status */
1012         wr32(E1000_STATUS, before);
1013
1014         /* Perform the remainder of the register test, looping through
1015          * the test table until we either fail or reach the null entry.
1016          */
1017         while (test->reg) {
1018                 for (i = 0; i < test->array_len; i++) {
1019                         switch (test->test_type) {
1020                         case PATTERN_TEST:
1021                                 REG_PATTERN_TEST(test->reg +
1022                                                 (i * test->reg_offset),
1023                                                 test->mask,
1024                                                 test->write);
1025                                 break;
1026                         case SET_READ_TEST:
1027                                 REG_SET_AND_CHECK(test->reg +
1028                                                 (i * test->reg_offset),
1029                                                 test->mask,
1030                                                 test->write);
1031                                 break;
1032                         case WRITE_NO_TEST:
1033                                 writel(test->write,
1034                                     (adapter->hw.hw_addr + test->reg)
1035                                         + (i * test->reg_offset));
1036                                 break;
1037                         case TABLE32_TEST:
1038                                 REG_PATTERN_TEST(test->reg + (i * 4),
1039                                                 test->mask,
1040                                                 test->write);
1041                                 break;
1042                         case TABLE64_TEST_LO:
1043                                 REG_PATTERN_TEST(test->reg + (i * 8),
1044                                                 test->mask,
1045                                                 test->write);
1046                                 break;
1047                         case TABLE64_TEST_HI:
1048                                 REG_PATTERN_TEST((test->reg + 4) + (i * 8),
1049                                                 test->mask,
1050                                                 test->write);
1051                                 break;
1052                         }
1053                 }
1054                 test++;
1055         }
1056
1057         *data = 0;
1058         return 0;
1059 }
1060
1061 static int igb_eeprom_test(struct igb_adapter *adapter, u64 *data)
1062 {
1063         u16 temp;
1064         u16 checksum = 0;
1065         u16 i;
1066
1067         *data = 0;
1068         /* Read and add up the contents of the EEPROM */
1069         for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) {
1070                 if ((adapter->hw.nvm.ops.read(&adapter->hw, i, 1, &temp))
1071                     < 0) {
1072                         *data = 1;
1073                         break;
1074                 }
1075                 checksum += temp;
1076         }
1077
1078         /* If Checksum is not Correct return error else test passed */
1079         if ((checksum != (u16) NVM_SUM) && !(*data))
1080                 *data = 2;
1081
1082         return *data;
1083 }
1084
1085 static irqreturn_t igb_test_intr(int irq, void *data)
1086 {
1087         struct net_device *netdev = (struct net_device *) data;
1088         struct igb_adapter *adapter = netdev_priv(netdev);
1089         struct e1000_hw *hw = &adapter->hw;
1090
1091         adapter->test_icr |= rd32(E1000_ICR);
1092
1093         return IRQ_HANDLED;
1094 }
1095
1096 static int igb_intr_test(struct igb_adapter *adapter, u64 *data)
1097 {
1098         struct e1000_hw *hw = &adapter->hw;
1099         struct net_device *netdev = adapter->netdev;
1100         u32 mask, ics_mask, i = 0, shared_int = true;
1101         u32 irq = adapter->pdev->irq;
1102
1103         *data = 0;
1104
1105         /* Hook up test interrupt handler just for this test */
1106         if (adapter->msix_entries)
1107                 /* NOTE: we don't test MSI-X interrupts here, yet */
1108                 return 0;
1109
1110         if (adapter->flags & IGB_FLAG_HAS_MSI) {
1111                 shared_int = false;
1112                 if (request_irq(irq, &igb_test_intr, 0, netdev->name, netdev)) {
1113                         *data = 1;
1114                         return -1;
1115                 }
1116         } else if (!request_irq(irq, &igb_test_intr, IRQF_PROBE_SHARED,
1117                                 netdev->name, netdev)) {
1118                 shared_int = false;
1119         } else if (request_irq(irq, &igb_test_intr, IRQF_SHARED,
1120                  netdev->name, netdev)) {
1121                 *data = 1;
1122                 return -1;
1123         }
1124         dev_info(&adapter->pdev->dev, "testing %s interrupt\n",
1125                 (shared_int ? "shared" : "unshared"));
1126         /* Disable all the interrupts */
1127         wr32(E1000_IMC, 0xFFFFFFFF);
1128         msleep(10);
1129
1130         /* Define all writable bits for ICS */
1131         switch(hw->mac.type) {
1132         case e1000_82575:
1133                 ics_mask = 0x37F47EDD;
1134                 break;
1135         case e1000_82576:
1136                 ics_mask = 0x77D4FBFD;
1137                 break;
1138         default:
1139                 ics_mask = 0x7FFFFFFF;
1140                 break;
1141         }
1142
1143         /* Test each interrupt */
1144         for (; i < 31; i++) {
1145                 /* Interrupt to test */
1146                 mask = 1 << i;
1147
1148                 if (!(mask & ics_mask))
1149                         continue;
1150
1151                 if (!shared_int) {
1152                         /* Disable the interrupt to be reported in
1153                          * the cause register and then force the same
1154                          * interrupt and see if one gets posted.  If
1155                          * an interrupt was posted to the bus, the
1156                          * test failed.
1157                          */
1158                         adapter->test_icr = 0;
1159
1160                         /* Flush any pending interrupts */
1161                         wr32(E1000_ICR, ~0);
1162
1163                         wr32(E1000_IMC, mask);
1164                         wr32(E1000_ICS, mask);
1165                         msleep(10);
1166
1167                         if (adapter->test_icr & mask) {
1168                                 *data = 3;
1169                                 break;
1170                         }
1171                 }
1172
1173                 /* Enable the interrupt to be reported in
1174                  * the cause register and then force the same
1175                  * interrupt and see if one gets posted.  If
1176                  * an interrupt was not posted to the bus, the
1177                  * test failed.
1178                  */
1179                 adapter->test_icr = 0;
1180
1181                 /* Flush any pending interrupts */
1182                 wr32(E1000_ICR, ~0);
1183
1184                 wr32(E1000_IMS, mask);
1185                 wr32(E1000_ICS, mask);
1186                 msleep(10);
1187
1188                 if (!(adapter->test_icr & mask)) {
1189                         *data = 4;
1190                         break;
1191                 }
1192
1193                 if (!shared_int) {
1194                         /* Disable the other interrupts to be reported in
1195                          * the cause register and then force the other
1196                          * interrupts and see if any get posted.  If
1197                          * an interrupt was posted to the bus, the
1198                          * test failed.
1199                          */
1200                         adapter->test_icr = 0;
1201
1202                         /* Flush any pending interrupts */
1203                         wr32(E1000_ICR, ~0);
1204
1205                         wr32(E1000_IMC, ~mask);
1206                         wr32(E1000_ICS, ~mask);
1207                         msleep(10);
1208
1209                         if (adapter->test_icr & mask) {
1210                                 *data = 5;
1211                                 break;
1212                         }
1213                 }
1214         }
1215
1216         /* Disable all the interrupts */
1217         wr32(E1000_IMC, ~0);
1218         msleep(10);
1219
1220         /* Unhook test interrupt handler */
1221         free_irq(irq, netdev);
1222
1223         return *data;
1224 }
1225
1226 static void igb_free_desc_rings(struct igb_adapter *adapter)
1227 {
1228         struct igb_ring *tx_ring = &adapter->test_tx_ring;
1229         struct igb_ring *rx_ring = &adapter->test_rx_ring;
1230         struct pci_dev *pdev = adapter->pdev;
1231         int i;
1232
1233         if (tx_ring->desc && tx_ring->buffer_info) {
1234                 for (i = 0; i < tx_ring->count; i++) {
1235                         struct igb_buffer *buf = &(tx_ring->buffer_info[i]);
1236                         if (buf->dma)
1237                                 pci_unmap_single(pdev, buf->dma, buf->length,
1238                                                  PCI_DMA_TODEVICE);
1239                         if (buf->skb)
1240                                 dev_kfree_skb(buf->skb);
1241                 }
1242         }
1243
1244         if (rx_ring->desc && rx_ring->buffer_info) {
1245                 for (i = 0; i < rx_ring->count; i++) {
1246                         struct igb_buffer *buf = &(rx_ring->buffer_info[i]);
1247                         if (buf->dma)
1248                                 pci_unmap_single(pdev, buf->dma,
1249                                                  IGB_RXBUFFER_2048,
1250                                                  PCI_DMA_FROMDEVICE);
1251                         if (buf->skb)
1252                                 dev_kfree_skb(buf->skb);
1253                 }
1254         }
1255
1256         if (tx_ring->desc) {
1257                 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc,
1258                                     tx_ring->dma);
1259                 tx_ring->desc = NULL;
1260         }
1261         if (rx_ring->desc) {
1262                 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc,
1263                                     rx_ring->dma);
1264                 rx_ring->desc = NULL;
1265         }
1266
1267         kfree(tx_ring->buffer_info);
1268         tx_ring->buffer_info = NULL;
1269         kfree(rx_ring->buffer_info);
1270         rx_ring->buffer_info = NULL;
1271
1272         return;
1273 }
1274
1275 static int igb_setup_desc_rings(struct igb_adapter *adapter)
1276 {
1277         struct e1000_hw *hw = &adapter->hw;
1278         struct igb_ring *tx_ring = &adapter->test_tx_ring;
1279         struct igb_ring *rx_ring = &adapter->test_rx_ring;
1280         struct pci_dev *pdev = adapter->pdev;
1281         struct igb_buffer *buffer_info;
1282         u32 rctl;
1283         int i, ret_val;
1284
1285         /* Setup Tx descriptor ring and Tx buffers */
1286
1287         if (!tx_ring->count)
1288                 tx_ring->count = IGB_DEFAULT_TXD;
1289
1290         tx_ring->buffer_info = kcalloc(tx_ring->count,
1291                                        sizeof(struct igb_buffer),
1292                                        GFP_KERNEL);
1293         if (!tx_ring->buffer_info) {
1294                 ret_val = 1;
1295                 goto err_nomem;
1296         }
1297
1298         tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
1299         tx_ring->size = ALIGN(tx_ring->size, 4096);
1300         tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
1301                                              &tx_ring->dma);
1302         if (!tx_ring->desc) {
1303                 ret_val = 2;
1304                 goto err_nomem;
1305         }
1306         tx_ring->next_to_use = tx_ring->next_to_clean = 0;
1307
1308         wr32(E1000_TDBAL(0),
1309                         ((u64) tx_ring->dma & 0x00000000FFFFFFFF));
1310         wr32(E1000_TDBAH(0), ((u64) tx_ring->dma >> 32));
1311         wr32(E1000_TDLEN(0),
1312                         tx_ring->count * sizeof(union e1000_adv_tx_desc));
1313         wr32(E1000_TDH(0), 0);
1314         wr32(E1000_TDT(0), 0);
1315         wr32(E1000_TCTL,
1316                         E1000_TCTL_PSP | E1000_TCTL_EN |
1317                         E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT |
1318                         E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT);
1319
1320         for (i = 0; i < tx_ring->count; i++) {
1321                 union e1000_adv_tx_desc *tx_desc;
1322                 struct sk_buff *skb;
1323                 unsigned int size = 1024;
1324
1325                 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
1326                 skb = alloc_skb(size, GFP_KERNEL);
1327                 if (!skb) {
1328                         ret_val = 3;
1329                         goto err_nomem;
1330                 }
1331                 skb_put(skb, size);
1332                 buffer_info = &tx_ring->buffer_info[i];
1333                 buffer_info->skb = skb;
1334                 buffer_info->length = skb->len;
1335                 buffer_info->dma = pci_map_single(pdev, skb->data, skb->len,
1336                                                   PCI_DMA_TODEVICE);
1337                 tx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
1338                 tx_desc->read.olinfo_status = cpu_to_le32(skb->len) <<
1339                                               E1000_ADVTXD_PAYLEN_SHIFT;
1340                 tx_desc->read.cmd_type_len = cpu_to_le32(skb->len);
1341                 tx_desc->read.cmd_type_len |= cpu_to_le32(E1000_TXD_CMD_EOP |
1342                                                           E1000_TXD_CMD_IFCS |
1343                                                           E1000_TXD_CMD_RS |
1344                                                           E1000_ADVTXD_DTYP_DATA |
1345                                                           E1000_ADVTXD_DCMD_DEXT);
1346         }
1347
1348         /* Setup Rx descriptor ring and Rx buffers */
1349
1350         if (!rx_ring->count)
1351                 rx_ring->count = IGB_DEFAULT_RXD;
1352
1353         rx_ring->buffer_info = kcalloc(rx_ring->count,
1354                                        sizeof(struct igb_buffer),
1355                                        GFP_KERNEL);
1356         if (!rx_ring->buffer_info) {
1357                 ret_val = 4;
1358                 goto err_nomem;
1359         }
1360
1361         rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc);
1362         rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size,
1363                                              &rx_ring->dma);
1364         if (!rx_ring->desc) {
1365                 ret_val = 5;
1366                 goto err_nomem;
1367         }
1368         rx_ring->next_to_use = rx_ring->next_to_clean = 0;
1369
1370         rctl = rd32(E1000_RCTL);
1371         wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1372         wr32(E1000_RDBAL(0),
1373                         ((u64) rx_ring->dma & 0xFFFFFFFF));
1374         wr32(E1000_RDBAH(0),
1375                         ((u64) rx_ring->dma >> 32));
1376         wr32(E1000_RDLEN(0), rx_ring->size);
1377         wr32(E1000_RDH(0), 0);
1378         wr32(E1000_RDT(0), 0);
1379         rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
1380         rctl = E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
1381                 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
1382         wr32(E1000_RCTL, rctl);
1383         wr32(E1000_SRRCTL(0), E1000_SRRCTL_DESCTYPE_ADV_ONEBUF);
1384
1385         for (i = 0; i < rx_ring->count; i++) {
1386                 union e1000_adv_rx_desc *rx_desc;
1387                 struct sk_buff *skb;
1388
1389                 buffer_info = &rx_ring->buffer_info[i];
1390                 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
1391                 skb = alloc_skb(IGB_RXBUFFER_2048 + NET_IP_ALIGN,
1392                                 GFP_KERNEL);
1393                 if (!skb) {
1394                         ret_val = 6;
1395                         goto err_nomem;
1396                 }
1397                 skb_reserve(skb, NET_IP_ALIGN);
1398                 buffer_info->skb = skb;
1399                 buffer_info->dma = pci_map_single(pdev, skb->data,
1400                                                   IGB_RXBUFFER_2048,
1401                                                   PCI_DMA_FROMDEVICE);
1402                 rx_desc->read.pkt_addr = cpu_to_le64(buffer_info->dma);
1403                 memset(skb->data, 0x00, skb->len);
1404         }
1405
1406         return 0;
1407
1408 err_nomem:
1409         igb_free_desc_rings(adapter);
1410         return ret_val;
1411 }
1412
1413 static void igb_phy_disable_receiver(struct igb_adapter *adapter)
1414 {
1415         struct e1000_hw *hw = &adapter->hw;
1416
1417         /* Write out to PHY registers 29 and 30 to disable the Receiver. */
1418         igb_write_phy_reg(hw, 29, 0x001F);
1419         igb_write_phy_reg(hw, 30, 0x8FFC);
1420         igb_write_phy_reg(hw, 29, 0x001A);
1421         igb_write_phy_reg(hw, 30, 0x8FF0);
1422 }
1423
1424 static int igb_integrated_phy_loopback(struct igb_adapter *adapter)
1425 {
1426         struct e1000_hw *hw = &adapter->hw;
1427         u32 ctrl_reg = 0;
1428
1429         hw->mac.autoneg = false;
1430
1431         if (hw->phy.type == e1000_phy_m88) {
1432                 /* Auto-MDI/MDIX Off */
1433                 igb_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 0x0808);
1434                 /* reset to update Auto-MDI/MDIX */
1435                 igb_write_phy_reg(hw, PHY_CONTROL, 0x9140);
1436                 /* autoneg off */
1437                 igb_write_phy_reg(hw, PHY_CONTROL, 0x8140);
1438         }
1439
1440         ctrl_reg = rd32(E1000_CTRL);
1441
1442         /* force 1000, set loopback */
1443         igb_write_phy_reg(hw, PHY_CONTROL, 0x4140);
1444
1445         /* Now set up the MAC to the same speed/duplex as the PHY. */
1446         ctrl_reg = rd32(E1000_CTRL);
1447         ctrl_reg &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */
1448         ctrl_reg |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */
1449                      E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */
1450                      E1000_CTRL_SPD_1000 |/* Force Speed to 1000 */
1451                      E1000_CTRL_FD |     /* Force Duplex to FULL */
1452                      E1000_CTRL_SLU);    /* Set link up enable bit */
1453
1454         if (hw->phy.type == e1000_phy_m88)
1455                 ctrl_reg |= E1000_CTRL_ILOS; /* Invert Loss of Signal */
1456
1457         wr32(E1000_CTRL, ctrl_reg);
1458
1459         /* Disable the receiver on the PHY so when a cable is plugged in, the
1460          * PHY does not begin to autoneg when a cable is reconnected to the NIC.
1461          */
1462         if (hw->phy.type == e1000_phy_m88)
1463                 igb_phy_disable_receiver(adapter);
1464
1465         udelay(500);
1466
1467         return 0;
1468 }
1469
1470 static int igb_set_phy_loopback(struct igb_adapter *adapter)
1471 {
1472         return igb_integrated_phy_loopback(adapter);
1473 }
1474
1475 static int igb_setup_loopback_test(struct igb_adapter *adapter)
1476 {
1477         struct e1000_hw *hw = &adapter->hw;
1478         u32 reg;
1479
1480         if (hw->phy.media_type == e1000_media_type_internal_serdes) {
1481                 reg = rd32(E1000_RCTL);
1482                 reg |= E1000_RCTL_LBM_TCVR;
1483                 wr32(E1000_RCTL, reg);
1484
1485                 wr32(E1000_SCTL, E1000_ENABLE_SERDES_LOOPBACK);
1486
1487                 reg = rd32(E1000_CTRL);
1488                 reg &= ~(E1000_CTRL_RFCE |
1489                          E1000_CTRL_TFCE |
1490                          E1000_CTRL_LRST);
1491                 reg |= E1000_CTRL_SLU |
1492                        E1000_CTRL_FD;
1493                 wr32(E1000_CTRL, reg);
1494
1495                 /* Unset switch control to serdes energy detect */
1496                 reg = rd32(E1000_CONNSW);
1497                 reg &= ~E1000_CONNSW_ENRGSRC;
1498                 wr32(E1000_CONNSW, reg);
1499
1500                 /* Set PCS register for forced speed */
1501                 reg = rd32(E1000_PCS_LCTL);
1502                 reg &= ~E1000_PCS_LCTL_AN_ENABLE;     /* Disable Autoneg*/
1503                 reg |= E1000_PCS_LCTL_FLV_LINK_UP |   /* Force link up */
1504                        E1000_PCS_LCTL_FSV_1000 |      /* Force 1000    */
1505                        E1000_PCS_LCTL_FDV_FULL |      /* SerDes Full duplex */
1506                        E1000_PCS_LCTL_FSD |           /* Force Speed */
1507                        E1000_PCS_LCTL_FORCE_LINK;     /* Force Link */
1508                 wr32(E1000_PCS_LCTL, reg);
1509
1510                 return 0;
1511         } else if (hw->phy.media_type == e1000_media_type_copper) {
1512                 return igb_set_phy_loopback(adapter);
1513         }
1514
1515         return 7;
1516 }
1517
1518 static void igb_loopback_cleanup(struct igb_adapter *adapter)
1519 {
1520         struct e1000_hw *hw = &adapter->hw;
1521         u32 rctl;
1522         u16 phy_reg;
1523
1524         rctl = rd32(E1000_RCTL);
1525         rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
1526         wr32(E1000_RCTL, rctl);
1527
1528         hw->mac.autoneg = true;
1529         igb_read_phy_reg(hw, PHY_CONTROL, &phy_reg);
1530         if (phy_reg & MII_CR_LOOPBACK) {
1531                 phy_reg &= ~MII_CR_LOOPBACK;
1532                 igb_write_phy_reg(hw, PHY_CONTROL, phy_reg);
1533                 igb_phy_sw_reset(hw);
1534         }
1535 }
1536
1537 static void igb_create_lbtest_frame(struct sk_buff *skb,
1538                                     unsigned int frame_size)
1539 {
1540         memset(skb->data, 0xFF, frame_size);
1541         frame_size &= ~1;
1542         memset(&skb->data[frame_size / 2], 0xAA, frame_size / 2 - 1);
1543         memset(&skb->data[frame_size / 2 + 10], 0xBE, 1);
1544         memset(&skb->data[frame_size / 2 + 12], 0xAF, 1);
1545 }
1546
1547 static int igb_check_lbtest_frame(struct sk_buff *skb, unsigned int frame_size)
1548 {
1549         frame_size &= ~1;
1550         if (*(skb->data + 3) == 0xFF)
1551                 if ((*(skb->data + frame_size / 2 + 10) == 0xBE) &&
1552                    (*(skb->data + frame_size / 2 + 12) == 0xAF))
1553                         return 0;
1554         return 13;
1555 }
1556
1557 static int igb_run_loopback_test(struct igb_adapter *adapter)
1558 {
1559         struct e1000_hw *hw = &adapter->hw;
1560         struct igb_ring *tx_ring = &adapter->test_tx_ring;
1561         struct igb_ring *rx_ring = &adapter->test_rx_ring;
1562         struct pci_dev *pdev = adapter->pdev;
1563         int i, j, k, l, lc, good_cnt;
1564         int ret_val = 0;
1565         unsigned long time;
1566
1567         wr32(E1000_RDT(0), rx_ring->count - 1);
1568
1569         /* Calculate the loop count based on the largest descriptor ring
1570          * The idea is to wrap the largest ring a number of times using 64
1571          * send/receive pairs during each loop
1572          */
1573
1574         if (rx_ring->count <= tx_ring->count)
1575                 lc = ((tx_ring->count / 64) * 2) + 1;
1576         else
1577                 lc = ((rx_ring->count / 64) * 2) + 1;
1578
1579         k = l = 0;
1580         for (j = 0; j <= lc; j++) { /* loop count loop */
1581                 for (i = 0; i < 64; i++) { /* send the packets */
1582                         igb_create_lbtest_frame(tx_ring->buffer_info[k].skb,
1583                                                 1024);
1584                         pci_dma_sync_single_for_device(pdev,
1585                                 tx_ring->buffer_info[k].dma,
1586                                 tx_ring->buffer_info[k].length,
1587                                 PCI_DMA_TODEVICE);
1588                         k++;
1589                         if (k == tx_ring->count)
1590                                 k = 0;
1591                 }
1592                 wr32(E1000_TDT(0), k);
1593                 msleep(200);
1594                 time = jiffies; /* set the start time for the receive */
1595                 good_cnt = 0;
1596                 do { /* receive the sent packets */
1597                         pci_dma_sync_single_for_cpu(pdev,
1598                                         rx_ring->buffer_info[l].dma,
1599                                         IGB_RXBUFFER_2048,
1600                                         PCI_DMA_FROMDEVICE);
1601
1602                         ret_val = igb_check_lbtest_frame(
1603                                              rx_ring->buffer_info[l].skb, 1024);
1604                         if (!ret_val)
1605                                 good_cnt++;
1606                         l++;
1607                         if (l == rx_ring->count)
1608                                 l = 0;
1609                         /* time + 20 msecs (200 msecs on 2.4) is more than
1610                          * enough time to complete the receives, if it's
1611                          * exceeded, break and error off
1612                          */
1613                 } while (good_cnt < 64 && jiffies < (time + 20));
1614                 if (good_cnt != 64) {
1615                         ret_val = 13; /* ret_val is the same as mis-compare */
1616                         break;
1617                 }
1618                 if (jiffies >= (time + 20)) {
1619                         ret_val = 14; /* error code for time out error */
1620                         break;
1621                 }
1622         } /* end loop count loop */
1623         return ret_val;
1624 }
1625
1626 static int igb_loopback_test(struct igb_adapter *adapter, u64 *data)
1627 {
1628         /* PHY loopback cannot be performed if SoL/IDER
1629          * sessions are active */
1630         if (igb_check_reset_block(&adapter->hw)) {
1631                 dev_err(&adapter->pdev->dev,
1632                         "Cannot do PHY loopback test "
1633                         "when SoL/IDER is active.\n");
1634                 *data = 0;
1635                 goto out;
1636         }
1637         *data = igb_setup_desc_rings(adapter);
1638         if (*data)
1639                 goto out;
1640         *data = igb_setup_loopback_test(adapter);
1641         if (*data)
1642                 goto err_loopback;
1643         *data = igb_run_loopback_test(adapter);
1644         igb_loopback_cleanup(adapter);
1645
1646 err_loopback:
1647         igb_free_desc_rings(adapter);
1648 out:
1649         return *data;
1650 }
1651
1652 static int igb_link_test(struct igb_adapter *adapter, u64 *data)
1653 {
1654         struct e1000_hw *hw = &adapter->hw;
1655         *data = 0;
1656         if (hw->phy.media_type == e1000_media_type_internal_serdes) {
1657                 int i = 0;
1658                 hw->mac.serdes_has_link = false;
1659
1660                 /* On some blade server designs, link establishment
1661                  * could take as long as 2-3 minutes */
1662                 do {
1663                         hw->mac.ops.check_for_link(&adapter->hw);
1664                         if (hw->mac.serdes_has_link)
1665                                 return *data;
1666                         msleep(20);
1667                 } while (i++ < 3750);
1668
1669                 *data = 1;
1670         } else {
1671                 hw->mac.ops.check_for_link(&adapter->hw);
1672                 if (hw->mac.autoneg)
1673                         msleep(4000);
1674
1675                 if (!(rd32(E1000_STATUS) &
1676                       E1000_STATUS_LU))
1677                         *data = 1;
1678         }
1679         return *data;
1680 }
1681
1682 static void igb_diag_test(struct net_device *netdev,
1683                           struct ethtool_test *eth_test, u64 *data)
1684 {
1685         struct igb_adapter *adapter = netdev_priv(netdev);
1686         u16 autoneg_advertised;
1687         u8 forced_speed_duplex, autoneg;
1688         bool if_running = netif_running(netdev);
1689
1690         set_bit(__IGB_TESTING, &adapter->state);
1691         if (eth_test->flags == ETH_TEST_FL_OFFLINE) {
1692                 /* Offline tests */
1693
1694                 /* save speed, duplex, autoneg settings */
1695                 autoneg_advertised = adapter->hw.phy.autoneg_advertised;
1696                 forced_speed_duplex = adapter->hw.mac.forced_speed_duplex;
1697                 autoneg = adapter->hw.mac.autoneg;
1698
1699                 dev_info(&adapter->pdev->dev, "offline testing starting\n");
1700
1701                 /* Link test performed before hardware reset so autoneg doesn't
1702                  * interfere with test result */
1703                 if (igb_link_test(adapter, &data[4]))
1704                         eth_test->flags |= ETH_TEST_FL_FAILED;
1705
1706                 if (if_running)
1707                         /* indicate we're in test mode */
1708                         dev_close(netdev);
1709                 else
1710                         igb_reset(adapter);
1711
1712                 if (igb_reg_test(adapter, &data[0]))
1713                         eth_test->flags |= ETH_TEST_FL_FAILED;
1714
1715                 igb_reset(adapter);
1716                 if (igb_eeprom_test(adapter, &data[1]))
1717                         eth_test->flags |= ETH_TEST_FL_FAILED;
1718
1719                 igb_reset(adapter);
1720                 if (igb_intr_test(adapter, &data[2]))
1721                         eth_test->flags |= ETH_TEST_FL_FAILED;
1722
1723                 igb_reset(adapter);
1724                 if (igb_loopback_test(adapter, &data[3]))
1725                         eth_test->flags |= ETH_TEST_FL_FAILED;
1726
1727                 /* restore speed, duplex, autoneg settings */
1728                 adapter->hw.phy.autoneg_advertised = autoneg_advertised;
1729                 adapter->hw.mac.forced_speed_duplex = forced_speed_duplex;
1730                 adapter->hw.mac.autoneg = autoneg;
1731
1732                 /* force this routine to wait until autoneg complete/timeout */
1733                 adapter->hw.phy.autoneg_wait_to_complete = true;
1734                 igb_reset(adapter);
1735                 adapter->hw.phy.autoneg_wait_to_complete = false;
1736
1737                 clear_bit(__IGB_TESTING, &adapter->state);
1738                 if (if_running)
1739                         dev_open(netdev);
1740         } else {
1741                 dev_info(&adapter->pdev->dev, "online testing starting\n");
1742                 /* Online tests */
1743                 if (igb_link_test(adapter, &data[4]))
1744                         eth_test->flags |= ETH_TEST_FL_FAILED;
1745
1746                 /* Online tests aren't run; pass by default */
1747                 data[0] = 0;
1748                 data[1] = 0;
1749                 data[2] = 0;
1750                 data[3] = 0;
1751
1752                 clear_bit(__IGB_TESTING, &adapter->state);
1753         }
1754         msleep_interruptible(4 * 1000);
1755 }
1756
1757 static int igb_wol_exclusion(struct igb_adapter *adapter,
1758                              struct ethtool_wolinfo *wol)
1759 {
1760         struct e1000_hw *hw = &adapter->hw;
1761         int retval = 1; /* fail by default */
1762
1763         switch (hw->device_id) {
1764         case E1000_DEV_ID_82575GB_QUAD_COPPER:
1765                 /* WoL not supported */
1766                 wol->supported = 0;
1767                 break;
1768         case E1000_DEV_ID_82575EB_FIBER_SERDES:
1769         case E1000_DEV_ID_82576_FIBER:
1770         case E1000_DEV_ID_82576_SERDES:
1771                 /* Wake events not supported on port B */
1772                 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1) {
1773                         wol->supported = 0;
1774                         break;
1775                 }
1776                 /* return success for non excluded adapter ports */
1777                 retval = 0;
1778                 break;
1779         case E1000_DEV_ID_82576_QUAD_COPPER:
1780                 /* quad port adapters only support WoL on port A */
1781                 if (!(adapter->flags & IGB_FLAG_QUAD_PORT_A)) {
1782                         wol->supported = 0;
1783                         break;
1784                 }
1785                 /* return success for non excluded adapter ports */
1786                 retval = 0;
1787                 break;
1788         default:
1789                 /* dual port cards only support WoL on port A from now on
1790                  * unless it was enabled in the eeprom for port B
1791                  * so exclude FUNC_1 ports from having WoL enabled */
1792                 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1 &&
1793                     !adapter->eeprom_wol) {
1794                         wol->supported = 0;
1795                         break;
1796                 }
1797
1798                 retval = 0;
1799         }
1800
1801         return retval;
1802 }
1803
1804 static void igb_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1805 {
1806         struct igb_adapter *adapter = netdev_priv(netdev);
1807
1808         wol->supported = WAKE_UCAST | WAKE_MCAST |
1809                          WAKE_BCAST | WAKE_MAGIC;
1810         wol->wolopts = 0;
1811
1812         /* this function will set ->supported = 0 and return 1 if wol is not
1813          * supported by this hardware */
1814         if (igb_wol_exclusion(adapter, wol) ||
1815             !device_can_wakeup(&adapter->pdev->dev))
1816                 return;
1817
1818         /* apply any specific unsupported masks here */
1819         switch (adapter->hw.device_id) {
1820         default:
1821                 break;
1822         }
1823
1824         if (adapter->wol & E1000_WUFC_EX)
1825                 wol->wolopts |= WAKE_UCAST;
1826         if (adapter->wol & E1000_WUFC_MC)
1827                 wol->wolopts |= WAKE_MCAST;
1828         if (adapter->wol & E1000_WUFC_BC)
1829                 wol->wolopts |= WAKE_BCAST;
1830         if (adapter->wol & E1000_WUFC_MAG)
1831                 wol->wolopts |= WAKE_MAGIC;
1832
1833         return;
1834 }
1835
1836 static int igb_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1837 {
1838         struct igb_adapter *adapter = netdev_priv(netdev);
1839
1840         if (wol->wolopts & (WAKE_PHY | WAKE_ARP | WAKE_MAGICSECURE))
1841                 return -EOPNOTSUPP;
1842
1843         if (igb_wol_exclusion(adapter, wol) ||
1844             !device_can_wakeup(&adapter->pdev->dev))
1845                 return wol->wolopts ? -EOPNOTSUPP : 0;
1846
1847         /* these settings will always override what we currently have */
1848         adapter->wol = 0;
1849
1850         if (wol->wolopts & WAKE_UCAST)
1851                 adapter->wol |= E1000_WUFC_EX;
1852         if (wol->wolopts & WAKE_MCAST)
1853                 adapter->wol |= E1000_WUFC_MC;
1854         if (wol->wolopts & WAKE_BCAST)
1855                 adapter->wol |= E1000_WUFC_BC;
1856         if (wol->wolopts & WAKE_MAGIC)
1857                 adapter->wol |= E1000_WUFC_MAG;
1858
1859         device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
1860
1861         return 0;
1862 }
1863
1864 /* bit defines for adapter->led_status */
1865 #define IGB_LED_ON              0
1866
1867 static int igb_phys_id(struct net_device *netdev, u32 data)
1868 {
1869         struct igb_adapter *adapter = netdev_priv(netdev);
1870         struct e1000_hw *hw = &adapter->hw;
1871
1872         if (!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
1873                 data = (u32)(MAX_SCHEDULE_TIMEOUT / HZ);
1874
1875         igb_blink_led(hw);
1876         msleep_interruptible(data * 1000);
1877
1878         igb_led_off(hw);
1879         clear_bit(IGB_LED_ON, &adapter->led_status);
1880         igb_cleanup_led(hw);
1881
1882         return 0;
1883 }
1884
1885 static int igb_set_coalesce(struct net_device *netdev,
1886                             struct ethtool_coalesce *ec)
1887 {
1888         struct igb_adapter *adapter = netdev_priv(netdev);
1889         struct e1000_hw *hw = &adapter->hw;
1890         int i;
1891
1892         if ((ec->rx_coalesce_usecs > IGB_MAX_ITR_USECS) ||
1893             ((ec->rx_coalesce_usecs > 3) &&
1894              (ec->rx_coalesce_usecs < IGB_MIN_ITR_USECS)) ||
1895             (ec->rx_coalesce_usecs == 2))
1896                 return -EINVAL;
1897
1898         /* convert to rate of irq's per second */
1899         if (ec->rx_coalesce_usecs && ec->rx_coalesce_usecs <= 3) {
1900                 adapter->itr_setting = ec->rx_coalesce_usecs;
1901                 adapter->itr = IGB_START_ITR;
1902         } else {
1903                 adapter->itr_setting = ec->rx_coalesce_usecs << 2;
1904                 adapter->itr = adapter->itr_setting;
1905         }
1906
1907         for (i = 0; i < adapter->num_rx_queues; i++)
1908                 wr32(adapter->rx_ring[i].itr_register, adapter->itr);
1909
1910         return 0;
1911 }
1912
1913 static int igb_get_coalesce(struct net_device *netdev,
1914                             struct ethtool_coalesce *ec)
1915 {
1916         struct igb_adapter *adapter = netdev_priv(netdev);
1917
1918         if (adapter->itr_setting <= 3)
1919                 ec->rx_coalesce_usecs = adapter->itr_setting;
1920         else
1921                 ec->rx_coalesce_usecs = adapter->itr_setting >> 2;
1922
1923         return 0;
1924 }
1925
1926
1927 static int igb_nway_reset(struct net_device *netdev)
1928 {
1929         struct igb_adapter *adapter = netdev_priv(netdev);
1930         if (netif_running(netdev))
1931                 igb_reinit_locked(adapter);
1932         return 0;
1933 }
1934
1935 static int igb_get_sset_count(struct net_device *netdev, int sset)
1936 {
1937         switch (sset) {
1938         case ETH_SS_STATS:
1939                 return IGB_STATS_LEN;
1940         case ETH_SS_TEST:
1941                 return IGB_TEST_LEN;
1942         default:
1943                 return -ENOTSUPP;
1944         }
1945 }
1946
1947 static void igb_get_ethtool_stats(struct net_device *netdev,
1948                                   struct ethtool_stats *stats, u64 *data)
1949 {
1950         struct igb_adapter *adapter = netdev_priv(netdev);
1951         u64 *queue_stat;
1952         int stat_count_tx = sizeof(struct igb_tx_queue_stats) / sizeof(u64);
1953         int stat_count_rx = sizeof(struct igb_rx_queue_stats) / sizeof(u64);
1954         int j;
1955         int i;
1956
1957         igb_update_stats(adapter);
1958         for (i = 0; i < IGB_GLOBAL_STATS_LEN; i++) {
1959                 char *p = (char *)adapter+igb_gstrings_stats[i].stat_offset;
1960                 data[i] = (igb_gstrings_stats[i].sizeof_stat ==
1961                         sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
1962         }
1963         for (j = 0; j < adapter->num_tx_queues; j++) {
1964                 int k;
1965                 queue_stat = (u64 *)&adapter->tx_ring[j].tx_stats;
1966                 for (k = 0; k < stat_count_tx; k++)
1967                         data[i + k] = queue_stat[k];
1968                 i += k;
1969         }
1970         for (j = 0; j < adapter->num_rx_queues; j++) {
1971                 int k;
1972                 queue_stat = (u64 *)&adapter->rx_ring[j].rx_stats;
1973                 for (k = 0; k < stat_count_rx; k++)
1974                         data[i + k] = queue_stat[k];
1975                 i += k;
1976         }
1977 }
1978
1979 static void igb_get_strings(struct net_device *netdev, u32 stringset, u8 *data)
1980 {
1981         struct igb_adapter *adapter = netdev_priv(netdev);
1982         u8 *p = data;
1983         int i;
1984
1985         switch (stringset) {
1986         case ETH_SS_TEST:
1987                 memcpy(data, *igb_gstrings_test,
1988                         IGB_TEST_LEN*ETH_GSTRING_LEN);
1989                 break;
1990         case ETH_SS_STATS:
1991                 for (i = 0; i < IGB_GLOBAL_STATS_LEN; i++) {
1992                         memcpy(p, igb_gstrings_stats[i].stat_string,
1993                                ETH_GSTRING_LEN);
1994                         p += ETH_GSTRING_LEN;
1995                 }
1996                 for (i = 0; i < adapter->num_tx_queues; i++) {
1997                         sprintf(p, "tx_queue_%u_packets", i);
1998                         p += ETH_GSTRING_LEN;
1999                         sprintf(p, "tx_queue_%u_bytes", i);
2000                         p += ETH_GSTRING_LEN;
2001                 }
2002                 for (i = 0; i < adapter->num_rx_queues; i++) {
2003                         sprintf(p, "rx_queue_%u_packets", i);
2004                         p += ETH_GSTRING_LEN;
2005                         sprintf(p, "rx_queue_%u_bytes", i);
2006                         p += ETH_GSTRING_LEN;
2007                         sprintf(p, "rx_queue_%u_drops", i);
2008                         p += ETH_GSTRING_LEN;
2009                 }
2010 /*              BUG_ON(p - data != IGB_STATS_LEN * ETH_GSTRING_LEN); */
2011                 break;
2012         }
2013 }
2014
2015 static struct ethtool_ops igb_ethtool_ops = {
2016         .get_settings           = igb_get_settings,
2017         .set_settings           = igb_set_settings,
2018         .get_drvinfo            = igb_get_drvinfo,
2019         .get_regs_len           = igb_get_regs_len,
2020         .get_regs               = igb_get_regs,
2021         .get_wol                = igb_get_wol,
2022         .set_wol                = igb_set_wol,
2023         .get_msglevel           = igb_get_msglevel,
2024         .set_msglevel           = igb_set_msglevel,
2025         .nway_reset             = igb_nway_reset,
2026         .get_link               = ethtool_op_get_link,
2027         .get_eeprom_len         = igb_get_eeprom_len,
2028         .get_eeprom             = igb_get_eeprom,
2029         .set_eeprom             = igb_set_eeprom,
2030         .get_ringparam          = igb_get_ringparam,
2031         .set_ringparam          = igb_set_ringparam,
2032         .get_pauseparam         = igb_get_pauseparam,
2033         .set_pauseparam         = igb_set_pauseparam,
2034         .get_rx_csum            = igb_get_rx_csum,
2035         .set_rx_csum            = igb_set_rx_csum,
2036         .get_tx_csum            = igb_get_tx_csum,
2037         .set_tx_csum            = igb_set_tx_csum,
2038         .get_sg                 = ethtool_op_get_sg,
2039         .set_sg                 = ethtool_op_set_sg,
2040         .get_tso                = ethtool_op_get_tso,
2041         .set_tso                = igb_set_tso,
2042         .self_test              = igb_diag_test,
2043         .get_strings            = igb_get_strings,
2044         .phys_id                = igb_phys_id,
2045         .get_sset_count         = igb_get_sset_count,
2046         .get_ethtool_stats      = igb_get_ethtool_stats,
2047         .get_coalesce           = igb_get_coalesce,
2048         .set_coalesce           = igb_set_coalesce,
2049 };
2050
2051 void igb_set_ethtool_ops(struct net_device *netdev)
2052 {
2053         SET_ETHTOOL_OPS(netdev, &igb_ethtool_ops);
2054 }