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   1 /*******************************************************************************
   2
   3   Intel(R) Gigabit Ethernet Linux driver
   4   Copyright(c) 2007 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 /* ethtool support for igb */
  29
  30 #include <linux/vmalloc.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/pci.h>
  33 #include <linux/delay.h>
  34 #include <linux/interrupt.h>
  35 #include <linux/if_ether.h>
  36 #include <linux/ethtool.h>
  37
  38 #include "igb.h"
  39
  40 struct igb_stats {
  41         char stat_string[ETH_GSTRING_LEN];
  42         int sizeof_stat;
  43         int stat_offset;
  44 };
  45
  46 #define IGB_STAT(m) FIELD_SIZEOF(struct igb_adapter, m), \
  47                       offsetof(struct igb_adapter, m)
  48 static const struct igb_stats igb_gstrings_stats[] = {
  49         { "rx_packets", IGB_STAT(stats.gprc) },
  50         { "tx_packets", IGB_STAT(stats.gptc) },
  51         { "rx_bytes", IGB_STAT(stats.gorc) },
  52         { "tx_bytes", IGB_STAT(stats.gotc) },
  53         { "rx_broadcast", IGB_STAT(stats.bprc) },
  54         { "tx_broadcast", IGB_STAT(stats.bptc) },
  55         { "rx_multicast", IGB_STAT(stats.mprc) },
  56         { "tx_multicast", IGB_STAT(stats.mptc) },
  57         { "rx_errors", IGB_STAT(net_stats.rx_errors) },
  58         { "tx_errors", IGB_STAT(net_stats.tx_errors) },
  59         { "tx_dropped", IGB_STAT(net_stats.tx_dropped) },
  60         { "multicast", IGB_STAT(stats.mprc) },
  61         { "collisions", IGB_STAT(stats.colc) },
  62         { "rx_length_errors", IGB_STAT(net_stats.rx_length_errors) },
  63         { "rx_over_errors", IGB_STAT(net_stats.rx_over_errors) },
  64         { "rx_crc_errors", IGB_STAT(stats.crcerrs) },
  65         { "rx_frame_errors", IGB_STAT(net_stats.rx_frame_errors) },
  66         { "rx_no_buffer_count", IGB_STAT(stats.rnbc) },
  67         { "rx_missed_errors", IGB_STAT(stats.mpc) },
  68         { "tx_aborted_errors", IGB_STAT(stats.ecol) },
  69         { "tx_carrier_errors", IGB_STAT(stats.tncrs) },
  70         { "tx_fifo_errors", IGB_STAT(net_stats.tx_fifo_errors) },
  71         { "tx_heartbeat_errors", IGB_STAT(net_stats.tx_heartbeat_errors) },
  72         { "tx_window_errors", IGB_STAT(stats.latecol) },
  73         { "tx_abort_late_coll", IGB_STAT(stats.latecol) },
  74         { "tx_deferred_ok", IGB_STAT(stats.dc) },
  75         { "tx_single_coll_ok", IGB_STAT(stats.scc) },
  76         { "tx_multi_coll_ok", IGB_STAT(stats.mcc) },
  77         { "tx_timeout_count", IGB_STAT(tx_timeout_count) },
  78         { "tx_restart_queue", IGB_STAT(restart_queue) },
  79         { "rx_long_length_errors", IGB_STAT(stats.roc) },
  80         { "rx_short_length_errors", IGB_STAT(stats.ruc) },
  81         { "rx_align_errors", IGB_STAT(stats.algnerrc) },
  82         { "tx_tcp_seg_good", IGB_STAT(stats.tsctc) },
  83         { "tx_tcp_seg_failed", IGB_STAT(stats.tsctfc) },
  84         { "rx_flow_control_xon", IGB_STAT(stats.xonrxc) },
  85         { "rx_flow_control_xoff", IGB_STAT(stats.xoffrxc) },
  86         { "tx_flow_control_xon", IGB_STAT(stats.xontxc) },
  87         { "tx_flow_control_xoff", IGB_STAT(stats.xofftxc) },
  88         { "rx_long_byte_count", IGB_STAT(stats.gorc) },
  89         { "rx_csum_offload_good", IGB_STAT(hw_csum_good) },
  90         { "rx_csum_offload_errors", IGB_STAT(hw_csum_err) },
  91         { "rx_header_split", IGB_STAT(rx_hdr_split) },
  92         { "alloc_rx_buff_failed", IGB_STAT(alloc_rx_buff_failed) },
  93         { "tx_smbus", IGB_STAT(stats.mgptc) },
  94         { "rx_smbus", IGB_STAT(stats.mgprc) },
  95         { "dropped_smbus", IGB_STAT(stats.mgpdc) },
  96 #ifdef CONFIG_IGB_LRO
  97         { "lro_aggregated", IGB_STAT(lro_aggregated) },
  98         { "lro_flushed", IGB_STAT(lro_flushed) },
  99         { "lro_no_desc", IGB_STAT(lro_no_desc) },
 100 #endif
 101 };
 102
 103 #define IGB_QUEUE_STATS_LEN \
 104         ((((struct igb_adapter *)netdev_priv(netdev))->num_rx_queues + \
 105          ((struct igb_adapter *)netdev_priv(netdev))->num_tx_queues) * \
 106         (sizeof(struct igb_queue_stats) / sizeof(u64)))
 107 #define IGB_GLOBAL_STATS_LEN    \
 108         sizeof(igb_gstrings_stats) / sizeof(struct igb_stats)
 109 #define IGB_STATS_LEN (IGB_GLOBAL_STATS_LEN + IGB_QUEUE_STATS_LEN)
 110 static const char igb_gstrings_test[][ETH_GSTRING_LEN] = {
 111         "Register test  (offline)", "Eeprom test    (offline)",
 112         "Interrupt test (offline)", "Loopback test  (offline)",
 113         "Link test   (on/offline)"
 114 };
 115 #define IGB_TEST_LEN sizeof(igb_gstrings_test) / ETH_GSTRING_LEN
 116
 117 static int igb_get_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
 118 {
 119         struct igb_adapter *adapter = netdev_priv(netdev);
 120         struct e1000_hw *hw = &adapter->hw;
 121
 122         if (hw->phy.media_type == e1000_media_type_copper) {
 123
 124                 ecmd->supported = (SUPPORTED_10baseT_Half |
 125                                    SUPPORTED_10baseT_Full |
 126                                    SUPPORTED_100baseT_Half |
 127                                    SUPPORTED_100baseT_Full |
 128                                    SUPPORTED_1000baseT_Full|
 129                                    SUPPORTED_Autoneg |
 130                                    SUPPORTED_TP);
 131                 ecmd->advertising = ADVERTISED_TP;
 132
 133                 if (hw->mac.autoneg == 1) {
 134                         ecmd->advertising |= ADVERTISED_Autoneg;
 135                         /* the e1000 autoneg seems to match ethtool nicely */
 136                         ecmd->advertising |= hw->phy.autoneg_advertised;
 137                 }
 138
 139                 ecmd->port = PORT_TP;
 140                 ecmd->phy_address = hw->phy.addr;
 141         } else {
 142                 ecmd->supported   = (SUPPORTED_1000baseT_Full |
 143                                      SUPPORTED_FIBRE |
 144                                      SUPPORTED_Autoneg);
 145
 146                 ecmd->advertising = (ADVERTISED_1000baseT_Full |
 147                                      ADVERTISED_FIBRE |
 148                                      ADVERTISED_Autoneg);
 149
 150                 ecmd->port = PORT_FIBRE;
 151         }
 152
 153         ecmd->transceiver = XCVR_INTERNAL;
 154
 155         if (rd32(E1000_STATUS) & E1000_STATUS_LU) {
 156
 157                 adapter->hw.mac.ops.get_speed_and_duplex(hw,
 158                                         &adapter->link_speed,
 159                                         &adapter->link_duplex);
 160                 ecmd->speed = adapter->link_speed;
 161
 162                 /* unfortunately FULL_DUPLEX != DUPLEX_FULL
 163                  *          and HALF_DUPLEX != DUPLEX_HALF */
 164
 165                 if (adapter->link_duplex == FULL_DUPLEX)
 166                         ecmd->duplex = DUPLEX_FULL;
 167                 else
 168                         ecmd->duplex = DUPLEX_HALF;
 169         } else {
 170                 ecmd->speed = -1;
 171                 ecmd->duplex = -1;
 172         }
 173
 174         ecmd->autoneg = ((hw->phy.media_type == e1000_media_type_fiber) ||
 175                          hw->mac.autoneg) ? AUTONEG_ENABLE : AUTONEG_DISABLE;
 176         return 0;
 177 }
 178
 179 static int igb_set_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
 180 {
 181         struct igb_adapter *adapter = netdev_priv(netdev);
 182         struct e1000_hw *hw = &adapter->hw;
 183
 184         /* When SoL/IDER sessions are active, autoneg/speed/duplex
 185          * cannot be changed */
 186         if (igb_check_reset_block(hw)) {
 187                 dev_err(&adapter->pdev->dev, "Cannot change link "
 188                         "characteristics when SoL/IDER is active.\n");
 189                 return -EINVAL;
 190         }
 191
 192         while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
 193                 msleep(1);
 194
 195         if (ecmd->autoneg == AUTONEG_ENABLE) {
 196                 hw->mac.autoneg = 1;
 197                 if (hw->phy.media_type == e1000_media_type_fiber)
 198                         hw->phy.autoneg_advertised = ADVERTISED_1000baseT_Full |
 199                                                      ADVERTISED_FIBRE |
 200                                                      ADVERTISED_Autoneg;
 201                 else
 202                         hw->phy.autoneg_advertised = ecmd->advertising |
 203                                                      ADVERTISED_TP |
 204                                                      ADVERTISED_Autoneg;
 205                 ecmd->advertising = hw->phy.autoneg_advertised;
 206         } else
 207                 if (igb_set_spd_dplx(adapter, ecmd->speed + ecmd->duplex)) {
 208                         clear_bit(__IGB_RESETTING, &adapter->state);
 209                         return -EINVAL;
 210                 }
 211
 212         /* reset the link */
 213
 214         if (netif_running(adapter->netdev)) {
 215                 igb_down(adapter);
 216                 igb_up(adapter);
 217         } else
 218                 igb_reset(adapter);
 219
 220         clear_bit(__IGB_RESETTING, &adapter->state);
 221         return 0;
 222 }
 223
 224 static void igb_get_pauseparam(struct net_device *netdev,
 225                                struct ethtool_pauseparam *pause)
 226 {
 227         struct igb_adapter *adapter = netdev_priv(netdev);
 228         struct e1000_hw *hw = &adapter->hw;
 229
 230         pause->autoneg =
 231                 (adapter->fc_autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE);
 232
 233         if (hw->fc.type == e1000_fc_rx_pause)
 234                 pause->rx_pause = 1;
 235         else if (hw->fc.type == e1000_fc_tx_pause)
 236                 pause->tx_pause = 1;
 237         else if (hw->fc.type == e1000_fc_full) {
 238                 pause->rx_pause = 1;
 239                 pause->tx_pause = 1;
 240         }
 241 }
 242
 243 static int igb_set_pauseparam(struct net_device *netdev,
 244                               struct ethtool_pauseparam *pause)
 245 {
 246         struct igb_adapter *adapter = netdev_priv(netdev);
 247         struct e1000_hw *hw = &adapter->hw;
 248         int retval = 0;
 249
 250         adapter->fc_autoneg = pause->autoneg;
 251
 252         while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
 253                 msleep(1);
 254
 255         if (pause->rx_pause && pause->tx_pause)
 256                 hw->fc.type = e1000_fc_full;
 257         else if (pause->rx_pause && !pause->tx_pause)
 258                 hw->fc.type = e1000_fc_rx_pause;
 259         else if (!pause->rx_pause && pause->tx_pause)
 260                 hw->fc.type = e1000_fc_tx_pause;
 261         else if (!pause->rx_pause && !pause->tx_pause)
 262                 hw->fc.type = e1000_fc_none;
 263
 264         hw->fc.original_type = hw->fc.type;
 265
 266         if (adapter->fc_autoneg == AUTONEG_ENABLE) {
 267                 if (netif_running(adapter->netdev)) {
 268                         igb_down(adapter);
 269                         igb_up(adapter);
 270                 } else
 271                         igb_reset(adapter);
 272         } else
 273                 retval = ((hw->phy.media_type == e1000_media_type_fiber) ?
 274                           igb_setup_link(hw) : igb_force_mac_fc(hw));
 275
 276         clear_bit(__IGB_RESETTING, &adapter->state);
 277         return retval;
 278 }
 279
 280 static u32 igb_get_rx_csum(struct net_device *netdev)
 281 {
 282         struct igb_adapter *adapter = netdev_priv(netdev);
 283         return adapter->rx_csum;
 284 }
 285
 286 static int igb_set_rx_csum(struct net_device *netdev, u32 data)
 287 {
 288         struct igb_adapter *adapter = netdev_priv(netdev);
 289         adapter->rx_csum = data;
 290
 291         return 0;
 292 }
 293
 294 static u32 igb_get_tx_csum(struct net_device *netdev)
 295 {
 296         return (netdev->features & NETIF_F_HW_CSUM) != 0;
 297 }
 298
 299 static int igb_set_tx_csum(struct net_device *netdev, u32 data)
 300 {
 301         if (data)
 302                 netdev->features |= NETIF_F_HW_CSUM;
 303         else
 304                 netdev->features &= ~NETIF_F_HW_CSUM;
 305
 306         return 0;
 307 }
 308
 309 static int igb_set_tso(struct net_device *netdev, u32 data)
 310 {
 311         struct igb_adapter *adapter = netdev_priv(netdev);
 312
 313         if (data)
 314                 netdev->features |= NETIF_F_TSO;
 315         else
 316                 netdev->features &= ~NETIF_F_TSO;
 317
 318         if (data)
 319                 netdev->features |= NETIF_F_TSO6;
 320         else
 321                 netdev->features &= ~NETIF_F_TSO6;
 322
 323         dev_info(&adapter->pdev->dev, "TSO is %s\n",
 324                  data ? "Enabled" : "Disabled");
 325         return 0;
 326 }
 327
 328 static u32 igb_get_msglevel(struct net_device *netdev)
 329 {
 330         struct igb_adapter *adapter = netdev_priv(netdev);
 331         return adapter->msg_enable;
 332 }
 333
 334 static void igb_set_msglevel(struct net_device *netdev, u32 data)
 335 {
 336         struct igb_adapter *adapter = netdev_priv(netdev);
 337         adapter->msg_enable = data;
 338 }
 339
 340 static int igb_get_regs_len(struct net_device *netdev)
 341 {
 342 #define IGB_REGS_LEN 551
 343         return IGB_REGS_LEN * sizeof(u32);
 344 }
 345
 346 static void igb_get_regs(struct net_device *netdev,
 347                          struct ethtool_regs *regs, void *p)
 348 {
 349         struct igb_adapter *adapter = netdev_priv(netdev);
 350         struct e1000_hw *hw = &adapter->hw;
 351         u32 *regs_buff = p;
 352         u8 i;
 353
 354         memset(p, 0, IGB_REGS_LEN * sizeof(u32));
 355
 356         regs->version = (1 << 24) | (hw->revision_id << 16) | hw->device_id;
 357
 358         /* General Registers */
 359         regs_buff[0] = rd32(E1000_CTRL);
 360         regs_buff[1] = rd32(E1000_STATUS);
 361         regs_buff[2] = rd32(E1000_CTRL_EXT);
 362         regs_buff[3] = rd32(E1000_MDIC);
 363         regs_buff[4] = rd32(E1000_SCTL);
 364         regs_buff[5] = rd32(E1000_CONNSW);
 365         regs_buff[6] = rd32(E1000_VET);
 366         regs_buff[7] = rd32(E1000_LEDCTL);
 367         regs_buff[8] = rd32(E1000_PBA);
 368         regs_buff[9] = rd32(E1000_PBS);
 369         regs_buff[10] = rd32(E1000_FRTIMER);
 370         regs_buff[11] = rd32(E1000_TCPTIMER);
 371
 372         /* NVM Register */
 373         regs_buff[12] = rd32(E1000_EECD);
 374
 375         /* Interrupt */
 376         /* Reading EICS for EICR because they read the
 377          * same but EICS does not clear on read */
 378         regs_buff[13] = rd32(E1000_EICS);
 379         regs_buff[14] = rd32(E1000_EICS);
 380         regs_buff[15] = rd32(E1000_EIMS);
 381         regs_buff[16] = rd32(E1000_EIMC);
 382         regs_buff[17] = rd32(E1000_EIAC);
 383         regs_buff[18] = rd32(E1000_EIAM);
 384         /* Reading ICS for ICR because they read the
 385          * same but ICS does not clear on read */
 386         regs_buff[19] = rd32(E1000_ICS);
 387         regs_buff[20] = rd32(E1000_ICS);
 388         regs_buff[21] = rd32(E1000_IMS);
 389         regs_buff[22] = rd32(E1000_IMC);
 390         regs_buff[23] = rd32(E1000_IAC);
 391         regs_buff[24] = rd32(E1000_IAM);
 392         regs_buff[25] = rd32(E1000_IMIRVP);
 393
 394         /* Flow Control */
 395         regs_buff[26] = rd32(E1000_FCAL);
 396         regs_buff[27] = rd32(E1000_FCAH);
 397         regs_buff[28] = rd32(E1000_FCTTV);
 398         regs_buff[29] = rd32(E1000_FCRTL);
 399         regs_buff[30] = rd32(E1000_FCRTH);
 400         regs_buff[31] = rd32(E1000_FCRTV);
 401
 402         /* Receive */
 403         regs_buff[32] = rd32(E1000_RCTL);
 404         regs_buff[33] = rd32(E1000_RXCSUM);
 405         regs_buff[34] = rd32(E1000_RLPML);
 406         regs_buff[35] = rd32(E1000_RFCTL);
 407         regs_buff[36] = rd32(E1000_MRQC);
 408         regs_buff[37] = rd32(E1000_VMD_CTL);
 409
 410         /* Transmit */
 411         regs_buff[38] = rd32(E1000_TCTL);
 412         regs_buff[39] = rd32(E1000_TCTL_EXT);
 413         regs_buff[40] = rd32(E1000_TIPG);
 414         regs_buff[41] = rd32(E1000_DTXCTL);
 415
 416         /* Wake Up */
 417         regs_buff[42] = rd32(E1000_WUC);
 418         regs_buff[43] = rd32(E1000_WUFC);
 419         regs_buff[44] = rd32(E1000_WUS);
 420         regs_buff[45] = rd32(E1000_IPAV);
 421         regs_buff[46] = rd32(E1000_WUPL);
 422
 423         /* MAC */
 424         regs_buff[47] = rd32(E1000_PCS_CFG0);
 425         regs_buff[48] = rd32(E1000_PCS_LCTL);
 426         regs_buff[49] = rd32(E1000_PCS_LSTAT);
 427         regs_buff[50] = rd32(E1000_PCS_ANADV);
 428         regs_buff[51] = rd32(E1000_PCS_LPAB);
 429         regs_buff[52] = rd32(E1000_PCS_NPTX);
 430         regs_buff[53] = rd32(E1000_PCS_LPABNP);
 431
 432         /* Statistics */
 433         regs_buff[54] = adapter->stats.crcerrs;
 434         regs_buff[55] = adapter->stats.algnerrc;
 435         regs_buff[56] = adapter->stats.symerrs;
 436         regs_buff[57] = adapter->stats.rxerrc;
 437         regs_buff[58] = adapter->stats.mpc;
 438         regs_buff[59] = adapter->stats.scc;
 439         regs_buff[60] = adapter->stats.ecol;
 440         regs_buff[61] = adapter->stats.mcc;
 441         regs_buff[62] = adapter->stats.latecol;
 442         regs_buff[63] = adapter->stats.colc;
 443         regs_buff[64] = adapter->stats.dc;
 444         regs_buff[65] = adapter->stats.tncrs;
 445         regs_buff[66] = adapter->stats.sec;
 446         regs_buff[67] = adapter->stats.htdpmc;
 447         regs_buff[68] = adapter->stats.rlec;
 448         regs_buff[69] = adapter->stats.xonrxc;
 449         regs_buff[70] = adapter->stats.xontxc;
 450         regs_buff[71] = adapter->stats.xoffrxc;
 451         regs_buff[72] = adapter->stats.xofftxc;
 452         regs_buff[73] = adapter->stats.fcruc;
 453         regs_buff[74] = adapter->stats.prc64;
 454         regs_buff[75] = adapter->stats.prc127;
 455         regs_buff[76] = adapter->stats.prc255;
 456         regs_buff[77] = adapter->stats.prc511;
 457         regs_buff[78] = adapter->stats.prc1023;
 458         regs_buff[79] = adapter->stats.prc1522;
 459         regs_buff[80] = adapter->stats.gprc;
 460         regs_buff[81] = adapter->stats.bprc;
 461         regs_buff[82] = adapter->stats.mprc;
 462         regs_buff[83] = adapter->stats.gptc;
 463         regs_buff[84] = adapter->stats.gorc;
 464         regs_buff[86] = adapter->stats.gotc;
 465         regs_buff[88] = adapter->stats.rnbc;
 466         regs_buff[89] = adapter->stats.ruc;
 467         regs_buff[90] = adapter->stats.rfc;
 468         regs_buff[91] = adapter->stats.roc;
 469         regs_buff[92] = adapter->stats.rjc;
 470         regs_buff[93] = adapter->stats.mgprc;
 471         regs_buff[94] = adapter->stats.mgpdc;
 472         regs_buff[95] = adapter->stats.mgptc;
 473         regs_buff[96] = adapter->stats.tor;
 474         regs_buff[98] = adapter->stats.tot;
 475         regs_buff[100] = adapter->stats.tpr;
 476         regs_buff[101] = adapter->stats.tpt;
 477         regs_buff[102] = adapter->stats.ptc64;
 478         regs_buff[103] = adapter->stats.ptc127;
 479         regs_buff[104] = adapter->stats.ptc255;
 480         regs_buff[105] = adapter->stats.ptc511;
 481         regs_buff[106] = adapter->stats.ptc1023;
 482         regs_buff[107] = adapter->stats.ptc1522;
 483         regs_buff[108] = adapter->stats.mptc;
 484         regs_buff[109] = adapter->stats.bptc;
 485         regs_buff[110] = adapter->stats.tsctc;
 486         regs_buff[111] = adapter->stats.iac;
 487         regs_buff[112] = adapter->stats.rpthc;
 488         regs_buff[113] = adapter->stats.hgptc;
 489         regs_buff[114] = adapter->stats.hgorc;
 490         regs_buff[116] = adapter->stats.hgotc;
 491         regs_buff[118] = adapter->stats.lenerrs;
 492         regs_buff[119] = adapter->stats.scvpc;
 493         regs_buff[120] = adapter->stats.hrmpc;
 494
 495         /* These should probably be added to e1000_regs.h instead */
 496         #define E1000_PSRTYPE_REG(_i) (0x05480 + ((_i) * 4))
 497         #define E1000_RAL(_i)         (0x05400 + ((_i) * 8))
 498         #define E1000_RAH(_i)         (0x05404 + ((_i) * 8))
 499         #define E1000_IP4AT_REG(_i)   (0x05840 + ((_i) * 8))
 500         #define E1000_IP6AT_REG(_i)   (0x05880 + ((_i) * 4))
 501         #define E1000_WUPM_REG(_i)    (0x05A00 + ((_i) * 4))
 502         #define E1000_FFMT_REG(_i)    (0x09000 + ((_i) * 8))
 503         #define E1000_FFVT_REG(_i)    (0x09800 + ((_i) * 8))
 504         #define E1000_FFLT_REG(_i)    (0x05F00 + ((_i) * 8))
 505
 506         for (i = 0; i < 4; i++)
 507                 regs_buff[121 + i] = rd32(E1000_SRRCTL(i));
 508         for (i = 0; i < 4; i++)
 509                 regs_buff[125 + i] = rd32(E1000_PSRTYPE_REG(i));
 510         for (i = 0; i < 4; i++)
 511                 regs_buff[129 + i] = rd32(E1000_RDBAL(i));
 512         for (i = 0; i < 4; i++)
 513                 regs_buff[133 + i] = rd32(E1000_RDBAH(i));
 514         for (i = 0; i < 4; i++)
 515                 regs_buff[137 + i] = rd32(E1000_RDLEN(i));
 516         for (i = 0; i < 4; i++)
 517                 regs_buff[141 + i] = rd32(E1000_RDH(i));
 518         for (i = 0; i < 4; i++)
 519                 regs_buff[145 + i] = rd32(E1000_RDT(i));
 520         for (i = 0; i < 4; i++)
 521                 regs_buff[149 + i] = rd32(E1000_RXDCTL(i));
 522
 523         for (i = 0; i < 10; i++)
 524                 regs_buff[153 + i] = rd32(E1000_EITR(i));
 525         for (i = 0; i < 8; i++)
 526                 regs_buff[163 + i] = rd32(E1000_IMIR(i));
 527         for (i = 0; i < 8; i++)
 528                 regs_buff[171 + i] = rd32(E1000_IMIREXT(i));
 529         for (i = 0; i < 16; i++)
 530                 regs_buff[179 + i] = rd32(E1000_RAL(i));
 531         for (i = 0; i < 16; i++)
 532                 regs_buff[195 + i] = rd32(E1000_RAH(i));
 533
 534         for (i = 0; i < 4; i++)
 535                 regs_buff[211 + i] = rd32(E1000_TDBAL(i));
 536         for (i = 0; i < 4; i++)
 537                 regs_buff[215 + i] = rd32(E1000_TDBAH(i));
 538         for (i = 0; i < 4; i++)
 539                 regs_buff[219 + i] = rd32(E1000_TDLEN(i));
 540         for (i = 0; i < 4; i++)
 541                 regs_buff[223 + i] = rd32(E1000_TDH(i));
 542         for (i = 0; i < 4; i++)
 543                 regs_buff[227 + i] = rd32(E1000_TDT(i));
 544         for (i = 0; i < 4; i++)
 545                 regs_buff[231 + i] = rd32(E1000_TXDCTL(i));
 546         for (i = 0; i < 4; i++)
 547                 regs_buff[235 + i] = rd32(E1000_TDWBAL(i));
 548         for (i = 0; i < 4; i++)
 549                 regs_buff[239 + i] = rd32(E1000_TDWBAH(i));
 550         for (i = 0; i < 4; i++)
 551                 regs_buff[243 + i] = rd32(E1000_DCA_TXCTRL(i));
 552
 553         for (i = 0; i < 4; i++)
 554                 regs_buff[247 + i] = rd32(E1000_IP4AT_REG(i));
 555         for (i = 0; i < 4; i++)
 556                 regs_buff[251 + i] = rd32(E1000_IP6AT_REG(i));
 557         for (i = 0; i < 32; i++)
 558                 regs_buff[255 + i] = rd32(E1000_WUPM_REG(i));
 559         for (i = 0; i < 128; i++)
 560                 regs_buff[287 + i] = rd32(E1000_FFMT_REG(i));
 561         for (i = 0; i < 128; i++)
 562                 regs_buff[415 + i] = rd32(E1000_FFVT_REG(i));
 563         for (i = 0; i < 4; i++)
 564                 regs_buff[543 + i] = rd32(E1000_FFLT_REG(i));
 565
 566         regs_buff[547] = rd32(E1000_TDFH);
 567         regs_buff[548] = rd32(E1000_TDFT);
 568         regs_buff[549] = rd32(E1000_TDFHS);
 569         regs_buff[550] = rd32(E1000_TDFPC);
 570
 571 }
 572
 573 static int igb_get_eeprom_len(struct net_device *netdev)
 574 {
 575         struct igb_adapter *adapter = netdev_priv(netdev);
 576         return adapter->hw.nvm.word_size * 2;
 577 }
 578
 579 static int igb_get_eeprom(struct net_device *netdev,
 580                           struct ethtool_eeprom *eeprom, u8 *bytes)
 581 {
 582         struct igb_adapter *adapter = netdev_priv(netdev);
 583         struct e1000_hw *hw = &adapter->hw;
 584         u16 *eeprom_buff;
 585         int first_word, last_word;
 586         int ret_val = 0;
 587         u16 i;
 588
 589         if (eeprom->len == 0)
 590                 return -EINVAL;
 591
 592         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
 593
 594         first_word = eeprom->offset >> 1;
 595         last_word = (eeprom->offset + eeprom->len - 1) >> 1;
 596
 597         eeprom_buff = kmalloc(sizeof(u16) *
 598                         (last_word - first_word + 1), GFP_KERNEL);
 599         if (!eeprom_buff)
 600                 return -ENOMEM;
 601
 602         if (hw->nvm.type == e1000_nvm_eeprom_spi)
 603                 ret_val = hw->nvm.ops.read_nvm(hw, first_word,
 604                                             last_word - first_word + 1,
 605                                             eeprom_buff);
 606         else {
 607                 for (i = 0; i < last_word - first_word + 1; i++) {
 608                         ret_val = hw->nvm.ops.read_nvm(hw, first_word + i, 1,
 609                                                     &eeprom_buff[i]);
 610                         if (ret_val)
 611                                 break;
 612                 }
 613         }
 614
 615         /* Device's eeprom is always little-endian, word addressable */
 616         for (i = 0; i < last_word - first_word + 1; i++)
 617                 le16_to_cpus(&eeprom_buff[i]);
 618
 619         memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1),
 620                         eeprom->len);
 621         kfree(eeprom_buff);
 622
 623         return ret_val;
 624 }
 625
 626 static int igb_set_eeprom(struct net_device *netdev,
 627                           struct ethtool_eeprom *eeprom, u8 *bytes)
 628 {
 629         struct igb_adapter *adapter = netdev_priv(netdev);
 630         struct e1000_hw *hw = &adapter->hw;
 631         u16 *eeprom_buff;
 632         void *ptr;
 633         int max_len, first_word, last_word, ret_val = 0;
 634         u16 i;
 635
 636         if (eeprom->len == 0)
 637                 return -EOPNOTSUPP;
 638
 639         if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16)))
 640                 return -EFAULT;
 641
 642         max_len = hw->nvm.word_size * 2;
 643
 644         first_word = eeprom->offset >> 1;
 645         last_word = (eeprom->offset + eeprom->len - 1) >> 1;
 646         eeprom_buff = kmalloc(max_len, GFP_KERNEL);
 647         if (!eeprom_buff)
 648                 return -ENOMEM;
 649
 650         ptr = (void *)eeprom_buff;
 651
 652         if (eeprom->offset & 1) {
 653                 /* need read/modify/write of first changed EEPROM word */
 654                 /* only the second byte of the word is being modified */
 655                 ret_val = hw->nvm.ops.read_nvm(hw, first_word, 1,
 656                                             &eeprom_buff[0]);
 657                 ptr++;
 658         }
 659         if (((eeprom->offset + eeprom->len) & 1) && (ret_val == 0)) {
 660                 /* need read/modify/write of last changed EEPROM word */
 661                 /* only the first byte of the word is being modified */
 662                 ret_val = hw->nvm.ops.read_nvm(hw, last_word, 1,
 663                                    &eeprom_buff[last_word - first_word]);
 664         }
 665
 666         /* Device's eeprom is always little-endian, word addressable */
 667         for (i = 0; i < last_word - first_word + 1; i++)
 668                 le16_to_cpus(&eeprom_buff[i]);
 669
 670         memcpy(ptr, bytes, eeprom->len);
 671
 672         for (i = 0; i < last_word - first_word + 1; i++)
 673                 eeprom_buff[i] = cpu_to_le16(eeprom_buff[i]);
 674
 675         ret_val = hw->nvm.ops.write_nvm(hw, first_word,
 676                                      last_word - first_word + 1, eeprom_buff);
 677
 678         /* Update the checksum over the first part of the EEPROM if needed
 679          * and flush shadow RAM for 82573 controllers */
 680         if ((ret_val == 0) && ((first_word <= NVM_CHECKSUM_REG)))
 681                 igb_update_nvm_checksum(hw);
 682
 683         kfree(eeprom_buff);
 684         return ret_val;
 685 }
 686
 687 static void igb_get_drvinfo(struct net_device *netdev,
 688                             struct ethtool_drvinfo *drvinfo)
 689 {
 690         struct igb_adapter *adapter = netdev_priv(netdev);
 691         char firmware_version[32];
 692         u16 eeprom_data;
 693
 694         strncpy(drvinfo->driver,  igb_driver_name, 32);
 695         strncpy(drvinfo->version, igb_driver_version, 32);
 696
 697         /* EEPROM image version # is reported as firmware version # for
 698          * 82575 controllers */
 699         adapter->hw.nvm.ops.read_nvm(&adapter->hw, 5, 1, &eeprom_data);
 700         sprintf(firmware_version, "%d.%d-%d",
 701                 (eeprom_data & 0xF000) >> 12,
 702                 (eeprom_data & 0x0FF0) >> 4,
 703                 eeprom_data & 0x000F);
 704
 705         strncpy(drvinfo->fw_version, firmware_version, 32);
 706         strncpy(drvinfo->bus_info, pci_name(adapter->pdev), 32);
 707         drvinfo->n_stats = IGB_STATS_LEN;
 708         drvinfo->testinfo_len = IGB_TEST_LEN;
 709         drvinfo->regdump_len = igb_get_regs_len(netdev);
 710         drvinfo->eedump_len = igb_get_eeprom_len(netdev);
 711 }
 712
 713 static void igb_get_ringparam(struct net_device *netdev,
 714                               struct ethtool_ringparam *ring)
 715 {
 716         struct igb_adapter *adapter = netdev_priv(netdev);
 717
 718         ring->rx_max_pending = IGB_MAX_RXD;
 719         ring->tx_max_pending = IGB_MAX_TXD;
 720         ring->rx_mini_max_pending = 0;
 721         ring->rx_jumbo_max_pending = 0;
 722         ring->rx_pending = adapter->rx_ring_count;
 723         ring->tx_pending = adapter->tx_ring_count;
 724         ring->rx_mini_pending = 0;
 725         ring->rx_jumbo_pending = 0;
 726 }
 727
 728 static int igb_set_ringparam(struct net_device *netdev,
 729                              struct ethtool_ringparam *ring)
 730 {
 731         struct igb_adapter *adapter = netdev_priv(netdev);
 732         struct igb_ring *temp_ring;
 733         int i, err;
 734         u32 new_rx_count, new_tx_count;
 735
 736         if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
 737                 return -EINVAL;
 738
 739         new_rx_count = max(ring->rx_pending, (u32)IGB_MIN_RXD);
 740         new_rx_count = min(new_rx_count, (u32)IGB_MAX_RXD);
 741         new_rx_count = ALIGN(new_rx_count, REQ_RX_DESCRIPTOR_MULTIPLE);
 742
 743         new_tx_count = max(ring->tx_pending, (u32)IGB_MIN_TXD);
 744         new_tx_count = min(new_tx_count, (u32)IGB_MAX_TXD);
 745         new_tx_count = ALIGN(new_tx_count, REQ_TX_DESCRIPTOR_MULTIPLE);
 746
 747         if ((new_tx_count == adapter->tx_ring_count) &&
 748             (new_rx_count == adapter->rx_ring_count)) {
 749                 /* nothing to do */
 750                 return 0;
 751         }
 752
 753         if (adapter->num_tx_queues > adapter->num_rx_queues)
 754                 temp_ring = vmalloc(adapter->num_tx_queues * sizeof(struct igb_ring));
 755         else
 756                 temp_ring = vmalloc(adapter->num_rx_queues * sizeof(struct igb_ring));
 757         if (!temp_ring)
 758                 return -ENOMEM;
 759
 760         while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
 761                 msleep(1);
 762
 763         if (netif_running(adapter->netdev))
 764                 igb_down(adapter);
 765
 766         /*
 767          * We can't just free everything and then setup again,
 768          * because the ISRs in MSI-X mode get passed pointers
 769          * to the tx and rx ring structs.
 770          */
 771         if (new_tx_count != adapter->tx_ring_count) {
 772                 memcpy(temp_ring, adapter->tx_ring,
 773                        adapter->num_tx_queues * sizeof(struct igb_ring));
 774
 775                 for (i = 0; i < adapter->num_tx_queues; i++) {
 776                         temp_ring[i].count = new_tx_count;
 777                         err = igb_setup_tx_resources(adapter, &temp_ring[i]);
 778                         if (err) {
 779                                 while (i) {
 780                                         i--;
 781                                         igb_free_tx_resources(&temp_ring[i]);
 782                                 }
 783                                 goto err_setup;
 784                         }
 785                 }
 786
 787                 for (i = 0; i < adapter->num_tx_queues; i++)
 788                         igb_free_tx_resources(&adapter->tx_ring[i]);
 789
 790                 memcpy(adapter->tx_ring, temp_ring,
 791                        adapter->num_tx_queues * sizeof(struct igb_ring));
 792
 793                 adapter->tx_ring_count = new_tx_count;
 794         }
 795
 796         if (new_rx_count != adapter->rx_ring->count) {
 797                 memcpy(temp_ring, adapter->rx_ring,
 798                        adapter->num_rx_queues * sizeof(struct igb_ring));
 799
 800                 for (i = 0; i < adapter->num_rx_queues; i++) {
 801                         temp_ring[i].count = new_rx_count;
 802                         err = igb_setup_rx_resources(adapter, &temp_ring[i]);
 803                         if (err) {
 804                                 while (i) {
 805                                         i--;
 806                                         igb_free_rx_resources(&temp_ring[i]);
 807                                 }
 808                                 goto err_setup;
 809                         }
 810
 811                 }
 812
 813                 for (i = 0; i < adapter->num_rx_queues; i++)
 814                         igb_free_rx_resources(&adapter->rx_ring[i]);
 815
 816                 memcpy(adapter->rx_ring, temp_ring,
 817                        adapter->num_rx_queues * sizeof(struct igb_ring));
 818
 819                 adapter->rx_ring_count = new_rx_count;
 820         }
 821
 822         err = 0;
 823 err_setup:
 824         if (netif_running(adapter->netdev))
 825                 igb_up(adapter);
 826
 827         clear_bit(__IGB_RESETTING, &adapter->state);
 828         vfree(temp_ring);
 829         return err;
 830 }
 831
 832 /* ethtool register test data */
 833 struct igb_reg_test {
 834         u16 reg;
 835         u16 reg_offset;
 836         u16 array_len;
 837         u16 test_type;
 838         u32 mask;
 839         u32 write;
 840 };
 841
 842 /* In the hardware, registers are laid out either singly, in arrays
 843  * spaced 0x100 bytes apart, or in contiguous tables.  We assume
 844  * most tests take place on arrays or single registers (handled
 845  * as a single-element array) and special-case the tables.
 846  * Table tests are always pattern tests.
 847  *
 848  * We also make provision for some required setup steps by specifying
 849  * registers to be written without any read-back testing.
 850  */
 851
 852 #define PATTERN_TEST    1
 853 #define SET_READ_TEST   2
 854 #define WRITE_NO_TEST   3
 855 #define TABLE32_TEST    4
 856 #define TABLE64_TEST_LO 5
 857 #define TABLE64_TEST_HI 6
 858
 859 /* 82576 reg test */
 860 static struct igb_reg_test reg_test_82576[] = {
 861         { E1000_FCAL,      0x100, 1,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 862         { E1000_FCAH,      0x100, 1,  PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
 863         { E1000_FCT,       0x100, 1,  PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
 864         { E1000_VET,       0x100, 1,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 865         { E1000_RDBAL(0),  0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
 866         { E1000_RDBAH(0),  0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 867         { E1000_RDLEN(0),  0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
 868         { E1000_RDBAL(4),  0x40,  8, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
 869         { E1000_RDBAH(4),  0x40,  8, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 870         { E1000_RDLEN(4),  0x40,  8, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
 871         /* Enable all four RX queues before testing. */
 872         { E1000_RXDCTL(0), 0x100, 1,  WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE },
 873         /* RDH is read-only for 82576, only test RDT. */
 874         { E1000_RDT(0),    0x100, 4,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
 875         { E1000_RXDCTL(0), 0x100, 4,  WRITE_NO_TEST, 0, 0 },
 876         { E1000_FCRTH,     0x100, 1,  PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
 877         { E1000_FCTTV,     0x100, 1,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
 878         { E1000_TIPG,      0x100, 1,  PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
 879         { E1000_TDBAL(0),  0x100, 4,  PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
 880         { E1000_TDBAH(0),  0x100, 4,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 881         { E1000_TDLEN(0),  0x100, 4,  PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
 882         { E1000_TDBAL(4),  0x40, 8,  PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
 883         { E1000_TDBAH(4),  0x40, 8,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 884         { E1000_TDLEN(4),  0x40, 8,  PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
 885         { E1000_RCTL,      0x100, 1,  SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
 886         { E1000_RCTL,      0x100, 1,  SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
 887         { E1000_RCTL,      0x100, 1,  SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
 888         { E1000_TCTL,      0x100, 1,  SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
 889         { E1000_RA,        0, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
 890         { E1000_RA,        0, 16, TABLE64_TEST_HI, 0x83FFFFFF, 0xFFFFFFFF },
 891         { E1000_RA2,       0, 8, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
 892         { E1000_RA2,       0, 8, TABLE64_TEST_HI, 0x83FFFFFF, 0xFFFFFFFF },
 893         { E1000_MTA,       0, 128,TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 894         { 0, 0, 0, 0 }
 895 };
 896
 897 /* 82575 register test */
 898 static struct igb_reg_test reg_test_82575[] = {
 899         { E1000_FCAL,      0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 900         { E1000_FCAH,      0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
 901         { E1000_FCT,       0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
 902         { E1000_VET,       0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 903         { E1000_RDBAL(0),  0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
 904         { E1000_RDBAH(0),  0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 905         { E1000_RDLEN(0),  0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
 906         /* Enable all four RX queues before testing. */
 907         { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE },
 908         /* RDH is read-only for 82575, only test RDT. */
 909         { E1000_RDT(0),    0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
 910         { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 0 },
 911         { E1000_FCRTH,     0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
 912         { E1000_FCTTV,     0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
 913         { E1000_TIPG,      0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
 914         { E1000_TDBAL(0),  0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
 915         { E1000_TDBAH(0),  0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 916         { E1000_TDLEN(0),  0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
 917         { E1000_RCTL,      0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
 918         { E1000_RCTL,      0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0x003FFFFB },
 919         { E1000_RCTL,      0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0xFFFFFFFF },
 920         { E1000_TCTL,      0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
 921         { E1000_TXCW,      0x100, 1, PATTERN_TEST, 0xC000FFFF, 0x0000FFFF },
 922         { E1000_RA,        0, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
 923         { E1000_RA,        0, 16, TABLE64_TEST_HI, 0x800FFFFF, 0xFFFFFFFF },
 924         { E1000_MTA,       0, 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 925         { 0, 0, 0, 0 }
 926 };
 927
 928 static bool reg_pattern_test(struct igb_adapter *adapter, u64 *data,
 929                              int reg, u32 mask, u32 write)
 930 {
 931         u32 pat, val;
 932         u32 _test[] =
 933                 {0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF};
 934         for (pat = 0; pat < ARRAY_SIZE(_test); pat++) {
 935                 writel((_test[pat] & write), (adapter->hw.hw_addr + reg));
 936                 val = readl(adapter->hw.hw_addr + reg);
 937                 if (val != (_test[pat] & write & mask)) {
 938                         dev_err(&adapter->pdev->dev, "pattern test reg %04X "
 939                                 "failed: got 0x%08X expected 0x%08X\n",
 940                                 reg, val, (_test[pat] & write & mask));
 941                         *data = reg;
 942                         return 1;
 943                 }
 944         }
 945         return 0;
 946 }
 947
 948 static bool reg_set_and_check(struct igb_adapter *adapter, u64 *data,
 949                               int reg, u32 mask, u32 write)
 950 {
 951         u32 val;
 952         writel((write & mask), (adapter->hw.hw_addr + reg));
 953         val = readl(adapter->hw.hw_addr + reg);
 954         if ((write & mask) != (val & mask)) {
 955                 dev_err(&adapter->pdev->dev, "set/check reg %04X test failed:"
 956                         " got 0x%08X expected 0x%08X\n", reg,
 957                         (val & mask), (write & mask));
 958                 *data = reg;
 959                 return 1;
 960         }
 961         return 0;
 962 }
 963
 964 #define REG_PATTERN_TEST(reg, mask, write) \
 965         do { \
 966                 if (reg_pattern_test(adapter, data, reg, mask, write)) \
 967                         return 1; \
 968         } while (0)
 969
 970 #define REG_SET_AND_CHECK(reg, mask, write) \
 971         do { \
 972                 if (reg_set_and_check(adapter, data, reg, mask, write)) \
 973                         return 1; \
 974         } while (0)
 975
 976 static int igb_reg_test(struct igb_adapter *adapter, u64 *data)
 977 {
 978         struct e1000_hw *hw = &adapter->hw;
 979         struct igb_reg_test *test;
 980         u32 value, before, after;
 981         u32 i, toggle;
 982
 983         toggle = 0x7FFFF3FF;
 984
 985         switch (adapter->hw.mac.type) {
 986         case e1000_82576:
 987                 test = reg_test_82576;
 988                 break;
 989         default:
 990                 test = reg_test_82575;
 991                 break;
 992         }
 993
 994         /* Because the status register is such a special case,
 995          * we handle it separately from the rest of the register
 996          * tests.  Some bits are read-only, some toggle, and some
 997          * are writable on newer MACs.
 998          */
 999         before = rd32(E1000_STATUS);
1000         value = (rd32(E1000_STATUS) & toggle);
1001         wr32(E1000_STATUS, toggle);
1002         after = rd32(E1000_STATUS) & toggle;
1003         if (value != after) {
1004                 dev_err(&adapter->pdev->dev, "failed STATUS register test "
1005                         "got: 0x%08X expected: 0x%08X\n", after, value);
1006                 *data = 1;
1007                 return 1;
1008         }
1009         /* restore previous status */
1010         wr32(E1000_STATUS, before);
1011
1012         /* Perform the remainder of the register test, looping through
1013          * the test table until we either fail or reach the null entry.
1014          */
1015         while (test->reg) {
1016                 for (i = 0; i < test->array_len; i++) {
1017                         switch (test->test_type) {
1018                         case PATTERN_TEST:
1019                                 REG_PATTERN_TEST(test->reg + (i * test->reg_offset),
1020                                                 test->mask,
1021                                                 test->write);
1022                                 break;
1023                         case SET_READ_TEST:
1024                                 REG_SET_AND_CHECK(test->reg + (i * test->reg_offset),
1025                                                 test->mask,
1026                                                 test->write);
1027                                 break;
1028                         case WRITE_NO_TEST:
1029                                 writel(test->write,
1030                                     (adapter->hw.hw_addr + test->reg)
1031                                         + (i * test->reg_offset));
1032                                 break;
1033                         case TABLE32_TEST:
1034                                 REG_PATTERN_TEST(test->reg + (i * 4),
1035                                                 test->mask,
1036                                                 test->write);
1037                                 break;
1038                         case TABLE64_TEST_LO:
1039                                 REG_PATTERN_TEST(test->reg + (i * 8),
1040                                                 test->mask,
1041                                                 test->write);
1042                                 break;
1043                         case TABLE64_TEST_HI:
1044                                 REG_PATTERN_TEST((test->reg + 4) + (i * 8),
1045                                                 test->mask,
1046                                                 test->write);
1047                                 break;
1048                         }
1049                 }
1050                 test++;
1051         }
1052
1053         *data = 0;
1054         return 0;
1055 }
1056
1057 static int igb_eeprom_test(struct igb_adapter *adapter, u64 *data)
1058 {
1059         u16 temp;
1060         u16 checksum = 0;
1061         u16 i;
1062
1063         *data = 0;
1064         /* Read and add up the contents of the EEPROM */
1065         for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) {
1066                 if ((adapter->hw.nvm.ops.read_nvm(&adapter->hw, i, 1, &temp))
1067                     < 0) {
1068                         *data = 1;
1069                         break;
1070                 }
1071                 checksum += temp;
1072         }
1073
1074         /* If Checksum is not Correct return error else test passed */
1075         if ((checksum != (u16) NVM_SUM) && !(*data))
1076                 *data = 2;
1077
1078         return *data;
1079 }
1080
1081 static irqreturn_t igb_test_intr(int irq, void *data)
1082 {
1083         struct net_device *netdev = (struct net_device *) data;
1084         struct igb_adapter *adapter = netdev_priv(netdev);
1085         struct e1000_hw *hw = &adapter->hw;
1086
1087         adapter->test_icr |= rd32(E1000_ICR);
1088
1089         return IRQ_HANDLED;
1090 }
1091
1092 static int igb_intr_test(struct igb_adapter *adapter, u64 *data)
1093 {
1094         struct e1000_hw *hw = &adapter->hw;
1095         struct net_device *netdev = adapter->netdev;
1096         u32 mask, i = 0, shared_int = true;
1097         u32 irq = adapter->pdev->irq;
1098
1099         *data = 0;
1100
1101         /* Hook up test interrupt handler just for this test */
1102         if (adapter->msix_entries) {
1103                 /* NOTE: we don't test MSI-X interrupts here, yet */
1104                 return 0;
1105         } else if (adapter->flags & IGB_FLAG_HAS_MSI) {
1106                 shared_int = false;
1107                 if (request_irq(irq, &igb_test_intr, 0, netdev->name, netdev)) {
1108                         *data = 1;
1109                         return -1;
1110                 }
1111         } else if (!request_irq(irq, &igb_test_intr, IRQF_PROBE_SHARED,
1112                                 netdev->name, netdev)) {
1113                 shared_int = false;
1114         } else if (request_irq(irq, &igb_test_intr, IRQF_SHARED,
1115                  netdev->name, netdev)) {
1116                 *data = 1;
1117                 return -1;
1118         }
1119         dev_info(&adapter->pdev->dev, "testing %s interrupt\n",
1120                 (shared_int ? "shared" : "unshared"));
1121
1122         /* Disable all the interrupts */
1123         wr32(E1000_IMC, 0xFFFFFFFF);
1124         msleep(10);
1125
1126         /* Test each interrupt */
1127         for (; i < 10; i++) {
1128                 /* Interrupt to test */
1129                 mask = 1 << i;
1130
1131                 if (!shared_int) {
1132                         /* Disable the interrupt to be reported in
1133                          * the cause register and then force the same
1134                          * interrupt and see if one gets posted.  If
1135                          * an interrupt was posted to the bus, the
1136                          * test failed.
1137                          */
1138                         adapter->test_icr = 0;
1139                         wr32(E1000_IMC, ~mask & 0x00007FFF);
1140                         wr32(E1000_ICS, ~mask & 0x00007FFF);
1141                         msleep(10);
1142
1143                         if (adapter->test_icr & mask) {
1144                                 *data = 3;
1145                                 break;
1146                         }
1147                 }
1148
1149                 /* Enable the interrupt to be reported in
1150                  * the cause register and then force the same
1151                  * interrupt and see if one gets posted.  If
1152                  * an interrupt was not posted to the bus, the
1153                  * test failed.
1154                  */
1155                 adapter->test_icr = 0;
1156                 wr32(E1000_IMS, mask);
1157                 wr32(E1000_ICS, mask);
1158                 msleep(10);
1159
1160                 if (!(adapter->test_icr & mask)) {
1161                         *data = 4;
1162                         break;
1163                 }
1164
1165                 if (!shared_int) {
1166                         /* Disable the other interrupts to be reported in
1167                          * the cause register and then force the other
1168                          * interrupts and see if any get posted.  If
1169                          * an interrupt was posted to the bus, the
1170                          * test failed.
1171                          */
1172                         adapter->test_icr = 0;
1173                         wr32(E1000_IMC, ~mask & 0x00007FFF);
1174                         wr32(E1000_ICS, ~mask & 0x00007FFF);
1175                         msleep(10);
1176
1177                         if (adapter->test_icr) {
1178                                 *data = 5;
1179                                 break;
1180                         }
1181                 }
1182         }
1183
1184         /* Disable all the interrupts */
1185         wr32(E1000_IMC, 0xFFFFFFFF);
1186         msleep(10);
1187
1188         /* Unhook test interrupt handler */
1189         free_irq(irq, netdev);
1190
1191         return *data;
1192 }
1193
1194 static void igb_free_desc_rings(struct igb_adapter *adapter)
1195 {
1196         struct igb_ring *tx_ring = &adapter->test_tx_ring;
1197         struct igb_ring *rx_ring = &adapter->test_rx_ring;
1198         struct pci_dev *pdev = adapter->pdev;
1199         int i;
1200
1201         if (tx_ring->desc && tx_ring->buffer_info) {
1202                 for (i = 0; i < tx_ring->count; i++) {
1203                         struct igb_buffer *buf = &(tx_ring->buffer_info[i]);
1204                         if (buf->dma)
1205                                 pci_unmap_single(pdev, buf->dma, buf->length,
1206                                                  PCI_DMA_TODEVICE);
1207                         if (buf->skb)
1208                                 dev_kfree_skb(buf->skb);
1209                 }
1210         }
1211
1212         if (rx_ring->desc && rx_ring->buffer_info) {
1213                 for (i = 0; i < rx_ring->count; i++) {
1214                         struct igb_buffer *buf = &(rx_ring->buffer_info[i]);
1215                         if (buf->dma)
1216                                 pci_unmap_single(pdev, buf->dma,
1217                                                  IGB_RXBUFFER_2048,
1218                                                  PCI_DMA_FROMDEVICE);
1219                         if (buf->skb)
1220                                 dev_kfree_skb(buf->skb);
1221                 }
1222         }
1223
1224         if (tx_ring->desc) {
1225                 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc,
1226                                     tx_ring->dma);
1227                 tx_ring->desc = NULL;
1228         }
1229         if (rx_ring->desc) {
1230                 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc,
1231                                     rx_ring->dma);
1232                 rx_ring->desc = NULL;
1233         }
1234
1235         kfree(tx_ring->buffer_info);
1236         tx_ring->buffer_info = NULL;
1237         kfree(rx_ring->buffer_info);
1238         rx_ring->buffer_info = NULL;
1239
1240         return;
1241 }
1242
1243 static int igb_setup_desc_rings(struct igb_adapter *adapter)
1244 {
1245         struct e1000_hw *hw = &adapter->hw;
1246         struct igb_ring *tx_ring = &adapter->test_tx_ring;
1247         struct igb_ring *rx_ring = &adapter->test_rx_ring;
1248         struct pci_dev *pdev = adapter->pdev;
1249         u32 rctl;
1250         int i, ret_val;
1251
1252         /* Setup Tx descriptor ring and Tx buffers */
1253
1254         if (!tx_ring->count)
1255                 tx_ring->count = IGB_DEFAULT_TXD;
1256
1257         tx_ring->buffer_info = kcalloc(tx_ring->count,
1258                                        sizeof(struct igb_buffer),
1259                                        GFP_KERNEL);
1260         if (!tx_ring->buffer_info) {
1261                 ret_val = 1;
1262                 goto err_nomem;
1263         }
1264
1265         tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc);
1266         tx_ring->size = ALIGN(tx_ring->size, 4096);
1267         tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
1268                                              &tx_ring->dma);
1269         if (!tx_ring->desc) {
1270                 ret_val = 2;
1271                 goto err_nomem;
1272         }
1273         tx_ring->next_to_use = tx_ring->next_to_clean = 0;
1274
1275         wr32(E1000_TDBAL(0),
1276                         ((u64) tx_ring->dma & 0x00000000FFFFFFFF));
1277         wr32(E1000_TDBAH(0), ((u64) tx_ring->dma >> 32));
1278         wr32(E1000_TDLEN(0),
1279                         tx_ring->count * sizeof(struct e1000_tx_desc));
1280         wr32(E1000_TDH(0), 0);
1281         wr32(E1000_TDT(0), 0);
1282         wr32(E1000_TCTL,
1283                         E1000_TCTL_PSP | E1000_TCTL_EN |
1284                         E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT |
1285                         E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT);
1286
1287         for (i = 0; i < tx_ring->count; i++) {
1288                 struct e1000_tx_desc *tx_desc = E1000_TX_DESC(*tx_ring, i);
1289                 struct sk_buff *skb;
1290                 unsigned int size = 1024;
1291
1292                 skb = alloc_skb(size, GFP_KERNEL);
1293                 if (!skb) {
1294                         ret_val = 3;
1295                         goto err_nomem;
1296                 }
1297                 skb_put(skb, size);
1298                 tx_ring->buffer_info[i].skb = skb;
1299                 tx_ring->buffer_info[i].length = skb->len;
1300                 tx_ring->buffer_info[i].dma =
1301                         pci_map_single(pdev, skb->data, skb->len,
1302                                        PCI_DMA_TODEVICE);
1303                 tx_desc->buffer_addr = cpu_to_le64(tx_ring->buffer_info[i].dma);
1304                 tx_desc->lower.data = cpu_to_le32(skb->len);
1305                 tx_desc->lower.data |= cpu_to_le32(E1000_TXD_CMD_EOP |
1306                                                    E1000_TXD_CMD_IFCS |
1307                                                    E1000_TXD_CMD_RS);
1308                 tx_desc->upper.data = 0;
1309         }
1310
1311         /* Setup Rx descriptor ring and Rx buffers */
1312
1313         if (!rx_ring->count)
1314                 rx_ring->count = IGB_DEFAULT_RXD;
1315
1316         rx_ring->buffer_info = kcalloc(rx_ring->count,
1317                                        sizeof(struct igb_buffer),
1318                                        GFP_KERNEL);
1319         if (!rx_ring->buffer_info) {
1320                 ret_val = 4;
1321                 goto err_nomem;
1322         }
1323
1324         rx_ring->size = rx_ring->count * sizeof(struct e1000_rx_desc);
1325         rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size,
1326                                              &rx_ring->dma);
1327         if (!rx_ring->desc) {
1328                 ret_val = 5;
1329                 goto err_nomem;
1330         }
1331         rx_ring->next_to_use = rx_ring->next_to_clean = 0;
1332
1333         rctl = rd32(E1000_RCTL);
1334         wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1335         wr32(E1000_RDBAL(0),
1336                         ((u64) rx_ring->dma & 0xFFFFFFFF));
1337         wr32(E1000_RDBAH(0),
1338                         ((u64) rx_ring->dma >> 32));
1339         wr32(E1000_RDLEN(0), rx_ring->size);
1340         wr32(E1000_RDH(0), 0);
1341         wr32(E1000_RDT(0), 0);
1342         rctl = E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_SZ_2048 |
1343                 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
1344                 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
1345         wr32(E1000_RCTL, rctl);
1346         wr32(E1000_SRRCTL(0), 0);
1347
1348         for (i = 0; i < rx_ring->count; i++) {
1349                 struct e1000_rx_desc *rx_desc = E1000_RX_DESC(*rx_ring, i);
1350                 struct sk_buff *skb;
1351
1352                 skb = alloc_skb(IGB_RXBUFFER_2048 + NET_IP_ALIGN,
1353                                 GFP_KERNEL);
1354                 if (!skb) {
1355                         ret_val = 6;
1356                         goto err_nomem;
1357                 }
1358                 skb_reserve(skb, NET_IP_ALIGN);
1359                 rx_ring->buffer_info[i].skb = skb;
1360                 rx_ring->buffer_info[i].dma =
1361                         pci_map_single(pdev, skb->data, IGB_RXBUFFER_2048,
1362                                        PCI_DMA_FROMDEVICE);
1363                 rx_desc->buffer_addr = cpu_to_le64(rx_ring->buffer_info[i].dma);
1364                 memset(skb->data, 0x00, skb->len);
1365         }
1366
1367         return 0;
1368
1369 err_nomem:
1370         igb_free_desc_rings(adapter);
1371         return ret_val;
1372 }
1373
1374 static void igb_phy_disable_receiver(struct igb_adapter *adapter)
1375 {
1376         struct e1000_hw *hw = &adapter->hw;
1377
1378         /* Write out to PHY registers 29 and 30 to disable the Receiver. */
1379         igb_write_phy_reg(hw, 29, 0x001F);
1380         igb_write_phy_reg(hw, 30, 0x8FFC);
1381         igb_write_phy_reg(hw, 29, 0x001A);
1382         igb_write_phy_reg(hw, 30, 0x8FF0);
1383 }
1384
1385 static int igb_integrated_phy_loopback(struct igb_adapter *adapter)
1386 {
1387         struct e1000_hw *hw = &adapter->hw;
1388         u32 ctrl_reg = 0;
1389         u32 stat_reg = 0;
1390
1391         hw->mac.autoneg = false;
1392
1393         if (hw->phy.type == e1000_phy_m88) {
1394                 /* Auto-MDI/MDIX Off */
1395                 igb_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 0x0808);
1396                 /* reset to update Auto-MDI/MDIX */
1397                 igb_write_phy_reg(hw, PHY_CONTROL, 0x9140);
1398                 /* autoneg off */
1399                 igb_write_phy_reg(hw, PHY_CONTROL, 0x8140);
1400         }
1401
1402         ctrl_reg = rd32(E1000_CTRL);
1403
1404         /* force 1000, set loopback */
1405         igb_write_phy_reg(hw, PHY_CONTROL, 0x4140);
1406
1407         /* Now set up the MAC to the same speed/duplex as the PHY. */
1408         ctrl_reg = rd32(E1000_CTRL);
1409         ctrl_reg &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */
1410         ctrl_reg |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */
1411                      E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */
1412                      E1000_CTRL_SPD_1000 |/* Force Speed to 1000 */
1413                      E1000_CTRL_FD);     /* Force Duplex to FULL */
1414
1415         if (hw->phy.media_type == e1000_media_type_copper &&
1416             hw->phy.type == e1000_phy_m88)
1417                 ctrl_reg |= E1000_CTRL_ILOS; /* Invert Loss of Signal */
1418         else {
1419                 /* Set the ILOS bit on the fiber Nic if half duplex link is
1420                  * detected. */
1421                 stat_reg = rd32(E1000_STATUS);
1422                 if ((stat_reg & E1000_STATUS_FD) == 0)
1423                         ctrl_reg |= (E1000_CTRL_ILOS | E1000_CTRL_SLU);
1424         }
1425
1426         wr32(E1000_CTRL, ctrl_reg);
1427
1428         /* Disable the receiver on the PHY so when a cable is plugged in, the
1429          * PHY does not begin to autoneg when a cable is reconnected to the NIC.
1430          */
1431         if (hw->phy.type == e1000_phy_m88)
1432                 igb_phy_disable_receiver(adapter);
1433
1434         udelay(500);
1435
1436         return 0;
1437 }
1438
1439 static int igb_set_phy_loopback(struct igb_adapter *adapter)
1440 {
1441         return igb_integrated_phy_loopback(adapter);
1442 }
1443
1444 static int igb_setup_loopback_test(struct igb_adapter *adapter)
1445 {
1446         struct e1000_hw *hw = &adapter->hw;
1447         u32 reg;
1448
1449         if (hw->phy.media_type == e1000_media_type_fiber ||
1450             hw->phy.media_type == e1000_media_type_internal_serdes) {
1451                 reg = rd32(E1000_RCTL);
1452                 reg |= E1000_RCTL_LBM_TCVR;
1453                 wr32(E1000_RCTL, reg);
1454
1455                 wr32(E1000_SCTL, E1000_ENABLE_SERDES_LOOPBACK);
1456
1457                 reg = rd32(E1000_CTRL);
1458                 reg &= ~(E1000_CTRL_RFCE |
1459                          E1000_CTRL_TFCE |
1460                          E1000_CTRL_LRST);
1461                 reg |= E1000_CTRL_SLU |
1462                        E1000_CTRL_FD;
1463                 wr32(E1000_CTRL, reg);
1464
1465                 /* Unset switch control to serdes energy detect */
1466                 reg = rd32(E1000_CONNSW);
1467                 reg &= ~E1000_CONNSW_ENRGSRC;
1468                 wr32(E1000_CONNSW, reg);
1469
1470                 /* Set PCS register for forced speed */
1471                 reg = rd32(E1000_PCS_LCTL);
1472                 reg &= ~E1000_PCS_LCTL_AN_ENABLE;     /* Disable Autoneg*/
1473                 reg |= E1000_PCS_LCTL_FLV_LINK_UP |   /* Force link up */
1474                        E1000_PCS_LCTL_FSV_1000 |      /* Force 1000    */
1475                        E1000_PCS_LCTL_FDV_FULL |      /* SerDes Full duplex */
1476                        E1000_PCS_LCTL_FSD |           /* Force Speed */
1477                        E1000_PCS_LCTL_FORCE_LINK;     /* Force Link */
1478                 wr32(E1000_PCS_LCTL, reg);
1479
1480                 return 0;
1481         } else if (hw->phy.media_type == e1000_media_type_copper) {
1482                 return igb_set_phy_loopback(adapter);
1483         }
1484
1485         return 7;
1486 }
1487
1488 static void igb_loopback_cleanup(struct igb_adapter *adapter)
1489 {
1490         struct e1000_hw *hw = &adapter->hw;
1491         u32 rctl;
1492         u16 phy_reg;
1493
1494         rctl = rd32(E1000_RCTL);
1495         rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
1496         wr32(E1000_RCTL, rctl);
1497
1498         hw->mac.autoneg = true;
1499         igb_read_phy_reg(hw, PHY_CONTROL, &phy_reg);
1500         if (phy_reg & MII_CR_LOOPBACK) {
1501                 phy_reg &= ~MII_CR_LOOPBACK;
1502                 igb_write_phy_reg(hw, PHY_CONTROL, phy_reg);
1503                 igb_phy_sw_reset(hw);
1504         }
1505 }
1506
1507 static void igb_create_lbtest_frame(struct sk_buff *skb,
1508                                     unsigned int frame_size)
1509 {
1510         memset(skb->data, 0xFF, frame_size);
1511         frame_size &= ~1;
1512         memset(&skb->data[frame_size / 2], 0xAA, frame_size / 2 - 1);
1513         memset(&skb->data[frame_size / 2 + 10], 0xBE, 1);
1514         memset(&skb->data[frame_size / 2 + 12], 0xAF, 1);
1515 }
1516
1517 static int igb_check_lbtest_frame(struct sk_buff *skb, unsigned int frame_size)
1518 {
1519         frame_size &= ~1;
1520         if (*(skb->data + 3) == 0xFF)
1521                 if ((*(skb->data + frame_size / 2 + 10) == 0xBE) &&
1522                    (*(skb->data + frame_size / 2 + 12) == 0xAF))
1523                         return 0;
1524         return 13;
1525 }
1526
1527 static int igb_run_loopback_test(struct igb_adapter *adapter)
1528 {
1529         struct e1000_hw *hw = &adapter->hw;
1530         struct igb_ring *tx_ring = &adapter->test_tx_ring;
1531         struct igb_ring *rx_ring = &adapter->test_rx_ring;
1532         struct pci_dev *pdev = adapter->pdev;
1533         int i, j, k, l, lc, good_cnt;
1534         int ret_val = 0;
1535         unsigned long time;
1536
1537         wr32(E1000_RDT(0), rx_ring->count - 1);
1538
1539         /* Calculate the loop count based on the largest descriptor ring
1540          * The idea is to wrap the largest ring a number of times using 64
1541          * send/receive pairs during each loop
1542          */
1543
1544         if (rx_ring->count <= tx_ring->count)
1545                 lc = ((tx_ring->count / 64) * 2) + 1;
1546         else
1547                 lc = ((rx_ring->count / 64) * 2) + 1;
1548
1549         k = l = 0;
1550         for (j = 0; j <= lc; j++) { /* loop count loop */
1551                 for (i = 0; i < 64; i++) { /* send the packets */
1552                         igb_create_lbtest_frame(tx_ring->buffer_info[k].skb,
1553                                                 1024);
1554                         pci_dma_sync_single_for_device(pdev,
1555                                 tx_ring->buffer_info[k].dma,
1556                                 tx_ring->buffer_info[k].length,
1557                                 PCI_DMA_TODEVICE);
1558                         k++;
1559                         if (k == tx_ring->count)
1560                                 k = 0;
1561                 }
1562                 wr32(E1000_TDT(0), k);
1563                 msleep(200);
1564                 time = jiffies; /* set the start time for the receive */
1565                 good_cnt = 0;
1566                 do { /* receive the sent packets */
1567                         pci_dma_sync_single_for_cpu(pdev,
1568                                         rx_ring->buffer_info[l].dma,
1569                                         IGB_RXBUFFER_2048,
1570                                         PCI_DMA_FROMDEVICE);
1571
1572                         ret_val = igb_check_lbtest_frame(
1573                                              rx_ring->buffer_info[l].skb, 1024);
1574                         if (!ret_val)
1575                                 good_cnt++;
1576                         l++;
1577                         if (l == rx_ring->count)
1578                                 l = 0;
1579                         /* time + 20 msecs (200 msecs on 2.4) is more than
1580                          * enough time to complete the receives, if it's
1581                          * exceeded, break and error off
1582                          */
1583                 } while (good_cnt < 64 && jiffies < (time + 20));
1584                 if (good_cnt != 64) {
1585                         ret_val = 13; /* ret_val is the same as mis-compare */
1586                         break;
1587                 }
1588                 if (jiffies >= (time + 20)) {
1589                         ret_val = 14; /* error code for time out error */
1590                         break;
1591                 }
1592         } /* end loop count loop */
1593         return ret_val;
1594 }
1595
1596 static int igb_loopback_test(struct igb_adapter *adapter, u64 *data)
1597 {
1598         /* PHY loopback cannot be performed if SoL/IDER
1599          * sessions are active */
1600         if (igb_check_reset_block(&adapter->hw)) {
1601                 dev_err(&adapter->pdev->dev,
1602                         "Cannot do PHY loopback test "
1603                         "when SoL/IDER is active.\n");
1604                 *data = 0;
1605                 goto out;
1606         }
1607         *data = igb_setup_desc_rings(adapter);
1608         if (*data)
1609                 goto out;
1610         *data = igb_setup_loopback_test(adapter);
1611         if (*data)
1612                 goto err_loopback;
1613         *data = igb_run_loopback_test(adapter);
1614         igb_loopback_cleanup(adapter);
1615
1616 err_loopback:
1617         igb_free_desc_rings(adapter);
1618 out:
1619         return *data;
1620 }
1621
1622 static int igb_link_test(struct igb_adapter *adapter, u64 *data)
1623 {
1624         struct e1000_hw *hw = &adapter->hw;
1625         *data = 0;
1626         if (hw->phy.media_type == e1000_media_type_internal_serdes) {
1627                 int i = 0;
1628                 hw->mac.serdes_has_link = false;
1629
1630                 /* On some blade server designs, link establishment
1631                  * could take as long as 2-3 minutes */
1632                 do {
1633                         hw->mac.ops.check_for_link(&adapter->hw);
1634                         if (hw->mac.serdes_has_link)
1635                                 return *data;
1636                         msleep(20);
1637                 } while (i++ < 3750);
1638
1639                 *data = 1;
1640         } else {
1641                 hw->mac.ops.check_for_link(&adapter->hw);
1642                 if (hw->mac.autoneg)
1643                         msleep(4000);
1644
1645                 if (!(rd32(E1000_STATUS) &
1646                       E1000_STATUS_LU))
1647                         *data = 1;
1648         }
1649         return *data;
1650 }
1651
1652 static void igb_diag_test(struct net_device *netdev,
1653                           struct ethtool_test *eth_test, u64 *data)
1654 {
1655         struct igb_adapter *adapter = netdev_priv(netdev);
1656         u16 autoneg_advertised;
1657         u8 forced_speed_duplex, autoneg;
1658         bool if_running = netif_running(netdev);
1659
1660         set_bit(__IGB_TESTING, &adapter->state);
1661         if (eth_test->flags == ETH_TEST_FL_OFFLINE) {
1662                 /* Offline tests */
1663
1664                 /* save speed, duplex, autoneg settings */
1665                 autoneg_advertised = adapter->hw.phy.autoneg_advertised;
1666                 forced_speed_duplex = adapter->hw.mac.forced_speed_duplex;
1667                 autoneg = adapter->hw.mac.autoneg;
1668
1669                 dev_info(&adapter->pdev->dev, "offline testing starting\n");
1670
1671                 /* Link test performed before hardware reset so autoneg doesn't
1672                  * interfere with test result */
1673                 if (igb_link_test(adapter, &data[4]))
1674                         eth_test->flags |= ETH_TEST_FL_FAILED;
1675
1676                 if (if_running)
1677                         /* indicate we're in test mode */
1678                         dev_close(netdev);
1679                 else
1680                         igb_reset(adapter);
1681
1682                 if (igb_reg_test(adapter, &data[0]))
1683                         eth_test->flags |= ETH_TEST_FL_FAILED;
1684
1685                 igb_reset(adapter);
1686                 if (igb_eeprom_test(adapter, &data[1]))
1687                         eth_test->flags |= ETH_TEST_FL_FAILED;
1688
1689                 igb_reset(adapter);
1690                 if (igb_intr_test(adapter, &data[2]))
1691                         eth_test->flags |= ETH_TEST_FL_FAILED;
1692
1693                 igb_reset(adapter);
1694                 if (igb_loopback_test(adapter, &data[3]))
1695                         eth_test->flags |= ETH_TEST_FL_FAILED;
1696
1697                 /* restore speed, duplex, autoneg settings */
1698                 adapter->hw.phy.autoneg_advertised = autoneg_advertised;
1699                 adapter->hw.mac.forced_speed_duplex = forced_speed_duplex;
1700                 adapter->hw.mac.autoneg = autoneg;
1701
1702                 /* force this routine to wait until autoneg complete/timeout */
1703                 adapter->hw.phy.autoneg_wait_to_complete = true;
1704                 igb_reset(adapter);
1705                 adapter->hw.phy.autoneg_wait_to_complete = false;
1706
1707                 clear_bit(__IGB_TESTING, &adapter->state);
1708                 if (if_running)
1709                         dev_open(netdev);
1710         } else {
1711                 dev_info(&adapter->pdev->dev, "online testing starting\n");
1712                 /* Online tests */
1713                 if (igb_link_test(adapter, &data[4]))
1714                         eth_test->flags |= ETH_TEST_FL_FAILED;
1715
1716                 /* Online tests aren't run; pass by default */
1717                 data[0] = 0;
1718                 data[1] = 0;
1719                 data[2] = 0;
1720                 data[3] = 0;
1721
1722                 clear_bit(__IGB_TESTING, &adapter->state);
1723         }
1724         msleep_interruptible(4 * 1000);
1725 }
1726
1727 static int igb_wol_exclusion(struct igb_adapter *adapter,
1728                              struct ethtool_wolinfo *wol)
1729 {
1730         struct e1000_hw *hw = &adapter->hw;
1731         int retval = 1; /* fail by default */
1732
1733         switch (hw->device_id) {
1734         case E1000_DEV_ID_82575GB_QUAD_COPPER:
1735                 /* WoL not supported */
1736                 wol->supported = 0;
1737                 break;
1738         case E1000_DEV_ID_82575EB_FIBER_SERDES:
1739         case E1000_DEV_ID_82576_FIBER:
1740         case E1000_DEV_ID_82576_SERDES:
1741                 /* Wake events not supported on port B */
1742                 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1) {
1743                         wol->supported = 0;
1744                         break;
1745                 }
1746                 /* return success for non excluded adapter ports */
1747                 retval = 0;
1748                 break;
1749         default:
1750                 /* dual port cards only support WoL on port A from now on
1751                  * unless it was enabled in the eeprom for port B
1752                  * so exclude FUNC_1 ports from having WoL enabled */
1753                 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1 &&
1754                     !adapter->eeprom_wol) {
1755                         wol->supported = 0;
1756                         break;
1757                 }
1758
1759                 retval = 0;
1760         }
1761
1762         return retval;
1763 }
1764
1765 static void igb_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1766 {
1767         struct igb_adapter *adapter = netdev_priv(netdev);
1768
1769         wol->supported = WAKE_UCAST | WAKE_MCAST |
1770                          WAKE_BCAST | WAKE_MAGIC;
1771         wol->wolopts = 0;
1772
1773         /* this function will set ->supported = 0 and return 1 if wol is not
1774          * supported by this hardware */
1775         if (igb_wol_exclusion(adapter, wol) ||
1776             !device_can_wakeup(&adapter->pdev->dev))
1777                 return;
1778
1779         /* apply any specific unsupported masks here */
1780         switch (adapter->hw.device_id) {
1781         default:
1782                 break;
1783         }
1784
1785         if (adapter->wol & E1000_WUFC_EX)
1786                 wol->wolopts |= WAKE_UCAST;
1787         if (adapter->wol & E1000_WUFC_MC)
1788                 wol->wolopts |= WAKE_MCAST;
1789         if (adapter->wol & E1000_WUFC_BC)
1790                 wol->wolopts |= WAKE_BCAST;
1791         if (adapter->wol & E1000_WUFC_MAG)
1792                 wol->wolopts |= WAKE_MAGIC;
1793
1794         return;
1795 }
1796
1797 static int igb_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1798 {
1799         struct igb_adapter *adapter = netdev_priv(netdev);
1800         struct e1000_hw *hw = &adapter->hw;
1801
1802         if (wol->wolopts & (WAKE_PHY | WAKE_ARP | WAKE_MAGICSECURE))
1803                 return -EOPNOTSUPP;
1804
1805         if (igb_wol_exclusion(adapter, wol) ||
1806             !device_can_wakeup(&adapter->pdev->dev))
1807                 return wol->wolopts ? -EOPNOTSUPP : 0;
1808
1809         switch (hw->device_id) {
1810         default:
1811                 break;
1812         }
1813
1814         /* these settings will always override what we currently have */
1815         adapter->wol = 0;
1816
1817         if (wol->wolopts & WAKE_UCAST)
1818                 adapter->wol |= E1000_WUFC_EX;
1819         if (wol->wolopts & WAKE_MCAST)
1820                 adapter->wol |= E1000_WUFC_MC;
1821         if (wol->wolopts & WAKE_BCAST)
1822                 adapter->wol |= E1000_WUFC_BC;
1823         if (wol->wolopts & WAKE_MAGIC)
1824                 adapter->wol |= E1000_WUFC_MAG;
1825
1826         device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
1827
1828         return 0;
1829 }
1830
1831 /* toggle LED 4 times per second = 2 "blinks" per second */
1832 #define IGB_ID_INTERVAL         (HZ/4)
1833
1834 /* bit defines for adapter->led_status */
1835 #define IGB_LED_ON              0
1836
1837 static int igb_phys_id(struct net_device *netdev, u32 data)
1838 {
1839         struct igb_adapter *adapter = netdev_priv(netdev);
1840         struct e1000_hw *hw = &adapter->hw;
1841
1842         if (!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
1843                 data = (u32)(MAX_SCHEDULE_TIMEOUT / HZ);
1844
1845         igb_blink_led(hw);
1846         msleep_interruptible(data * 1000);
1847
1848         igb_led_off(hw);
1849         clear_bit(IGB_LED_ON, &adapter->led_status);
1850         igb_cleanup_led(hw);
1851
1852         return 0;
1853 }
1854
1855 static int igb_set_coalesce(struct net_device *netdev,
1856                             struct ethtool_coalesce *ec)
1857 {
1858         struct igb_adapter *adapter = netdev_priv(netdev);
1859         struct e1000_hw *hw = &adapter->hw;
1860         int i;
1861
1862         if ((ec->rx_coalesce_usecs > IGB_MAX_ITR_USECS) ||
1863             ((ec->rx_coalesce_usecs > 3) &&
1864              (ec->rx_coalesce_usecs < IGB_MIN_ITR_USECS)) ||
1865             (ec->rx_coalesce_usecs == 2))
1866                 return -EINVAL;
1867
1868         /* convert to rate of irq's per second */
1869         if (ec->rx_coalesce_usecs && ec->rx_coalesce_usecs <= 3) {
1870                 adapter->itr_setting = ec->rx_coalesce_usecs;
1871                 adapter->itr = IGB_START_ITR;
1872         } else {
1873                 adapter->itr_setting = ec->rx_coalesce_usecs << 2;
1874                 adapter->itr = adapter->itr_setting;
1875         }
1876
1877         for (i = 0; i < adapter->num_rx_queues; i++)
1878                 wr32(adapter->rx_ring[i].itr_register, adapter->itr);
1879
1880         return 0;
1881 }
1882
1883 static int igb_get_coalesce(struct net_device *netdev,
1884                             struct ethtool_coalesce *ec)
1885 {
1886         struct igb_adapter *adapter = netdev_priv(netdev);
1887
1888         if (adapter->itr_setting <= 3)
1889                 ec->rx_coalesce_usecs = adapter->itr_setting;
1890         else
1891                 ec->rx_coalesce_usecs = adapter->itr_setting >> 2;
1892
1893         return 0;
1894 }
1895
1896
1897 static int igb_nway_reset(struct net_device *netdev)
1898 {
1899         struct igb_adapter *adapter = netdev_priv(netdev);
1900         if (netif_running(netdev))
1901                 igb_reinit_locked(adapter);
1902         return 0;
1903 }
1904
1905 static int igb_get_sset_count(struct net_device *netdev, int sset)
1906 {
1907         switch (sset) {
1908         case ETH_SS_STATS:
1909                 return IGB_STATS_LEN;
1910         case ETH_SS_TEST:
1911                 return IGB_TEST_LEN;
1912         default:
1913                 return -ENOTSUPP;
1914         }
1915 }
1916
1917 static void igb_get_ethtool_stats(struct net_device *netdev,
1918                                   struct ethtool_stats *stats, u64 *data)
1919 {
1920         struct igb_adapter *adapter = netdev_priv(netdev);
1921         u64 *queue_stat;
1922         int stat_count = sizeof(struct igb_queue_stats) / sizeof(u64);
1923         int j;
1924         int i;
1925 #ifdef CONFIG_IGB_LRO
1926         int aggregated = 0, flushed = 0, no_desc = 0;
1927
1928         for (i = 0; i < adapter->num_rx_queues; i++) {
1929                 aggregated += adapter->rx_ring[i].lro_mgr.stats.aggregated;
1930                 flushed += adapter->rx_ring[i].lro_mgr.stats.flushed;
1931                 no_desc += adapter->rx_ring[i].lro_mgr.stats.no_desc;
1932         }
1933         adapter->lro_aggregated = aggregated;
1934         adapter->lro_flushed = flushed;
1935         adapter->lro_no_desc = no_desc;
1936 #endif
1937
1938         igb_update_stats(adapter);
1939         for (i = 0; i < IGB_GLOBAL_STATS_LEN; i++) {
1940                 char *p = (char *)adapter+igb_gstrings_stats[i].stat_offset;
1941                 data[i] = (igb_gstrings_stats[i].sizeof_stat ==
1942                         sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
1943         }
1944         for (j = 0; j < adapter->num_tx_queues; j++) {
1945                 int k;
1946                 queue_stat = (u64 *)&adapter->tx_ring[j].tx_stats;
1947                 for (k = 0; k < stat_count; k++)
1948                         data[i + k] = queue_stat[k];
1949                 i += k;
1950         }
1951         for (j = 0; j < adapter->num_rx_queues; j++) {
1952                 int k;
1953                 queue_stat = (u64 *)&adapter->rx_ring[j].rx_stats;
1954                 for (k = 0; k < stat_count; k++)
1955                         data[i + k] = queue_stat[k];
1956                 i += k;
1957         }
1958 }
1959
1960 static void igb_get_strings(struct net_device *netdev, u32 stringset, u8 *data)
1961 {
1962         struct igb_adapter *adapter = netdev_priv(netdev);
1963         u8 *p = data;
1964         int i;
1965
1966         switch (stringset) {
1967         case ETH_SS_TEST:
1968                 memcpy(data, *igb_gstrings_test,
1969                         IGB_TEST_LEN*ETH_GSTRING_LEN);
1970                 break;
1971         case ETH_SS_STATS:
1972                 for (i = 0; i < IGB_GLOBAL_STATS_LEN; i++) {
1973                         memcpy(p, igb_gstrings_stats[i].stat_string,
1974                                ETH_GSTRING_LEN);
1975                         p += ETH_GSTRING_LEN;
1976                 }
1977                 for (i = 0; i < adapter->num_tx_queues; i++) {
1978                         sprintf(p, "tx_queue_%u_packets", i);
1979                         p += ETH_GSTRING_LEN;
1980                         sprintf(p, "tx_queue_%u_bytes", i);
1981                         p += ETH_GSTRING_LEN;
1982                 }
1983                 for (i = 0; i < adapter->num_rx_queues; i++) {
1984                         sprintf(p, "rx_queue_%u_packets", i);
1985                         p += ETH_GSTRING_LEN;
1986                         sprintf(p, "rx_queue_%u_bytes", i);
1987                         p += ETH_GSTRING_LEN;
1988                 }
1989 /*              BUG_ON(p - data != IGB_STATS_LEN * ETH_GSTRING_LEN); */
1990                 break;
1991         }
1992 }
1993
1994 static struct ethtool_ops igb_ethtool_ops = {
1995         .get_settings           = igb_get_settings,
1996         .set_settings           = igb_set_settings,
1997         .get_drvinfo            = igb_get_drvinfo,
1998         .get_regs_len           = igb_get_regs_len,
1999         .get_regs               = igb_get_regs,
2000         .get_wol                = igb_get_wol,
2001         .set_wol                = igb_set_wol,
2002         .get_msglevel           = igb_get_msglevel,
2003         .set_msglevel           = igb_set_msglevel,
2004         .nway_reset             = igb_nway_reset,
2005         .get_link               = ethtool_op_get_link,
2006         .get_eeprom_len         = igb_get_eeprom_len,
2007         .get_eeprom             = igb_get_eeprom,
2008         .set_eeprom             = igb_set_eeprom,
2009         .get_ringparam          = igb_get_ringparam,
2010         .set_ringparam          = igb_set_ringparam,
2011         .get_pauseparam         = igb_get_pauseparam,
2012         .set_pauseparam         = igb_set_pauseparam,
2013         .get_rx_csum            = igb_get_rx_csum,
2014         .set_rx_csum            = igb_set_rx_csum,
2015         .get_tx_csum            = igb_get_tx_csum,
2016         .set_tx_csum            = igb_set_tx_csum,
2017         .get_sg                 = ethtool_op_get_sg,
2018         .set_sg                 = ethtool_op_set_sg,
2019         .get_tso                = ethtool_op_get_tso,
2020         .set_tso                = igb_set_tso,
2021         .self_test              = igb_diag_test,
2022         .get_strings            = igb_get_strings,
2023         .phys_id                = igb_phys_id,
2024         .get_sset_count         = igb_get_sset_count,
2025         .get_ethtool_stats      = igb_get_ethtool_stats,
2026         .get_coalesce           = igb_get_coalesce,
2027         .set_coalesce           = igb_set_coalesce,
2028 };
2029
2030 void igb_set_ethtool_ops(struct net_device *netdev)
2031 {
2032         SET_ETHTOOL_OPS(netdev, &igb_ethtool_ops);
2033 }