1 /*******************************************************************************
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2009 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
32 e1000_mng_mode_none = 0,
36 e1000_mng_mode_host_if_only
39 #define E1000_FACTPS_MNGCG 0x20000000
41 /* Intel(R) Active Management Technology signature */
42 #define E1000_IAMT_SIGNATURE 0x544D4149
45 * e1000e_get_bus_info_pcie - Get PCIe bus information
46 * @hw: pointer to the HW structure
48 * Determines and stores the system bus information for a particular
49 * network interface. The following bus information is determined and stored:
50 * bus speed, bus width, type (PCIe), and PCIe function.
52 s32 e1000e_get_bus_info_pcie(struct e1000_hw *hw)
54 struct e1000_bus_info *bus = &hw->bus;
55 struct e1000_adapter *adapter = hw->adapter;
57 u16 pcie_link_status, pci_header_type, cap_offset;
59 cap_offset = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP);
61 bus->width = e1000_bus_width_unknown;
63 pci_read_config_word(adapter->pdev,
64 cap_offset + PCIE_LINK_STATUS,
66 bus->width = (enum e1000_bus_width)((pcie_link_status &
67 PCIE_LINK_WIDTH_MASK) >>
68 PCIE_LINK_WIDTH_SHIFT);
71 pci_read_config_word(adapter->pdev, PCI_HEADER_TYPE_REGISTER,
73 if (pci_header_type & PCI_HEADER_TYPE_MULTIFUNC) {
74 status = er32(STATUS);
75 bus->func = (status & E1000_STATUS_FUNC_MASK)
76 >> E1000_STATUS_FUNC_SHIFT;
85 * e1000_clear_vfta_generic - Clear VLAN filter table
86 * @hw: pointer to the HW structure
88 * Clears the register array which contains the VLAN filter table by
89 * setting all the values to 0.
91 void e1000_clear_vfta_generic(struct e1000_hw *hw)
95 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
96 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0);
102 * e1000_write_vfta_generic - Write value to VLAN filter table
103 * @hw: pointer to the HW structure
104 * @offset: register offset in VLAN filter table
105 * @value: register value written to VLAN filter table
107 * Writes value at the given offset in the register array which stores
108 * the VLAN filter table.
110 void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value)
112 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value);
117 * e1000e_init_rx_addrs - Initialize receive address's
118 * @hw: pointer to the HW structure
119 * @rar_count: receive address registers
121 * Setups the receive address registers by setting the base receive address
122 * register to the devices MAC address and clearing all the other receive
123 * address registers to 0.
125 void e1000e_init_rx_addrs(struct e1000_hw *hw, u16 rar_count)
128 u8 mac_addr[ETH_ALEN] = {0};
130 /* Setup the receive address */
131 e_dbg("Programming MAC Address into RAR[0]\n");
133 e1000e_rar_set(hw, hw->mac.addr, 0);
135 /* Zero out the other (rar_entry_count - 1) receive addresses */
136 e_dbg("Clearing RAR[1-%u]\n", rar_count-1);
137 for (i = 1; i < rar_count; i++)
138 e1000e_rar_set(hw, mac_addr, i);
142 * e1000_check_alt_mac_addr_generic - Check for alternate MAC addr
143 * @hw: pointer to the HW structure
145 * Checks the nvm for an alternate MAC address. An alternate MAC address
146 * can be setup by pre-boot software and must be treated like a permanent
147 * address and must override the actual permanent MAC address. If an
148 * alternate MAC address is found it is programmed into RAR0, replacing
149 * the permanent address that was installed into RAR0 by the Si on reset.
150 * This function will return SUCCESS unless it encounters an error while
151 * reading the EEPROM.
153 s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw)
157 u16 offset, nvm_alt_mac_addr_offset, nvm_data;
158 u8 alt_mac_addr[ETH_ALEN];
160 ret_val = e1000_read_nvm(hw, NVM_ALT_MAC_ADDR_PTR, 1,
161 &nvm_alt_mac_addr_offset);
163 e_dbg("NVM Read Error\n");
167 if (nvm_alt_mac_addr_offset == 0xFFFF) {
168 /* There is no Alternate MAC Address */
172 if (hw->bus.func == E1000_FUNC_1)
173 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN1;
174 for (i = 0; i < ETH_ALEN; i += 2) {
175 offset = nvm_alt_mac_addr_offset + (i >> 1);
176 ret_val = e1000_read_nvm(hw, offset, 1, &nvm_data);
178 e_dbg("NVM Read Error\n");
182 alt_mac_addr[i] = (u8)(nvm_data & 0xFF);
183 alt_mac_addr[i + 1] = (u8)(nvm_data >> 8);
186 /* if multicast bit is set, the alternate address will not be used */
187 if (alt_mac_addr[0] & 0x01) {
188 e_dbg("Ignoring Alternate Mac Address with MC bit set\n");
193 * We have a valid alternate MAC address, and we want to treat it the
194 * same as the normal permanent MAC address stored by the HW into the
195 * RAR. Do this by mapping this address into RAR0.
197 e1000e_rar_set(hw, alt_mac_addr, 0);
204 * e1000e_rar_set - Set receive address register
205 * @hw: pointer to the HW structure
206 * @addr: pointer to the receive address
207 * @index: receive address array register
209 * Sets the receive address array register at index to the address passed
212 void e1000e_rar_set(struct e1000_hw *hw, u8 *addr, u32 index)
214 u32 rar_low, rar_high;
217 * HW expects these in little endian so we reverse the byte order
218 * from network order (big endian) to little endian
220 rar_low = ((u32) addr[0] |
221 ((u32) addr[1] << 8) |
222 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
224 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
226 /* If MAC address zero, no need to set the AV bit */
227 if (rar_low || rar_high)
228 rar_high |= E1000_RAH_AV;
231 * Some bridges will combine consecutive 32-bit writes into
232 * a single burst write, which will malfunction on some parts.
233 * The flushes avoid this.
235 ew32(RAL(index), rar_low);
237 ew32(RAH(index), rar_high);
242 * e1000_hash_mc_addr - Generate a multicast hash value
243 * @hw: pointer to the HW structure
244 * @mc_addr: pointer to a multicast address
246 * Generates a multicast address hash value which is used to determine
247 * the multicast filter table array address and new table value. See
248 * e1000_mta_set_generic()
250 static u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr)
252 u32 hash_value, hash_mask;
255 /* Register count multiplied by bits per register */
256 hash_mask = (hw->mac.mta_reg_count * 32) - 1;
259 * For a mc_filter_type of 0, bit_shift is the number of left-shifts
260 * where 0xFF would still fall within the hash mask.
262 while (hash_mask >> bit_shift != 0xFF)
266 * The portion of the address that is used for the hash table
267 * is determined by the mc_filter_type setting.
268 * The algorithm is such that there is a total of 8 bits of shifting.
269 * The bit_shift for a mc_filter_type of 0 represents the number of
270 * left-shifts where the MSB of mc_addr[5] would still fall within
271 * the hash_mask. Case 0 does this exactly. Since there are a total
272 * of 8 bits of shifting, then mc_addr[4] will shift right the
273 * remaining number of bits. Thus 8 - bit_shift. The rest of the
274 * cases are a variation of this algorithm...essentially raising the
275 * number of bits to shift mc_addr[5] left, while still keeping the
276 * 8-bit shifting total.
278 * For example, given the following Destination MAC Address and an
279 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask),
280 * we can see that the bit_shift for case 0 is 4. These are the hash
281 * values resulting from each mc_filter_type...
282 * [0] [1] [2] [3] [4] [5]
286 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563
287 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6
288 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163
289 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634
291 switch (hw->mac.mc_filter_type) {
306 hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) |
307 (((u16) mc_addr[5]) << bit_shift)));
313 * e1000e_update_mc_addr_list_generic - Update Multicast addresses
314 * @hw: pointer to the HW structure
315 * @mc_addr_list: array of multicast addresses to program
316 * @mc_addr_count: number of multicast addresses to program
317 * @rar_used_count: the first RAR register free to program
318 * @rar_count: total number of supported Receive Address Registers
320 * Updates the Receive Address Registers and Multicast Table Array.
321 * The caller must have a packed mc_addr_list of multicast addresses.
322 * The parameter rar_count will usually be hw->mac.rar_entry_count
323 * unless there are workarounds that change this.
325 void e1000e_update_mc_addr_list_generic(struct e1000_hw *hw,
326 u8 *mc_addr_list, u32 mc_addr_count,
327 u32 rar_used_count, u32 rar_count)
330 u32 *mcarray = kzalloc(hw->mac.mta_reg_count * sizeof(u32), GFP_ATOMIC);
333 printk(KERN_ERR "multicast array memory allocation failed\n");
338 * Load the first set of multicast addresses into the exact
339 * filters (RAR). If there are not enough to fill the RAR
340 * array, clear the filters.
342 for (i = rar_used_count; i < rar_count; i++) {
344 e1000e_rar_set(hw, mc_addr_list, i);
346 mc_addr_list += ETH_ALEN;
348 E1000_WRITE_REG_ARRAY(hw, E1000_RA, i << 1, 0);
350 E1000_WRITE_REG_ARRAY(hw, E1000_RA, (i << 1) + 1, 0);
355 /* Load any remaining multicast addresses into the hash table. */
356 for (; mc_addr_count > 0; mc_addr_count--) {
357 u32 hash_value, hash_reg, hash_bit, mta;
358 hash_value = e1000_hash_mc_addr(hw, mc_addr_list);
359 e_dbg("Hash value = 0x%03X\n", hash_value);
360 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1);
361 hash_bit = hash_value & 0x1F;
362 mta = (1 << hash_bit);
363 mcarray[hash_reg] |= mta;
364 mc_addr_list += ETH_ALEN;
367 /* write the hash table completely */
368 for (i = 0; i < hw->mac.mta_reg_count; i++)
369 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, mcarray[i]);
376 * e1000e_clear_hw_cntrs_base - Clear base hardware counters
377 * @hw: pointer to the HW structure
379 * Clears the base hardware counters by reading the counter registers.
381 void e1000e_clear_hw_cntrs_base(struct e1000_hw *hw)
423 * e1000e_check_for_copper_link - Check for link (Copper)
424 * @hw: pointer to the HW structure
426 * Checks to see of the link status of the hardware has changed. If a
427 * change in link status has been detected, then we read the PHY registers
428 * to get the current speed/duplex if link exists.
430 s32 e1000e_check_for_copper_link(struct e1000_hw *hw)
432 struct e1000_mac_info *mac = &hw->mac;
437 * We only want to go out to the PHY registers to see if Auto-Neg
438 * has completed and/or if our link status has changed. The
439 * get_link_status flag is set upon receiving a Link Status
440 * Change or Rx Sequence Error interrupt.
442 if (!mac->get_link_status)
446 * First we want to see if the MII Status Register reports
447 * link. If so, then we want to get the current speed/duplex
450 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
455 return ret_val; /* No link detected */
457 mac->get_link_status = false;
460 * Check if there was DownShift, must be checked
461 * immediately after link-up
463 e1000e_check_downshift(hw);
466 * If we are forcing speed/duplex, then we simply return since
467 * we have already determined whether we have link or not.
470 ret_val = -E1000_ERR_CONFIG;
475 * Auto-Neg is enabled. Auto Speed Detection takes care
476 * of MAC speed/duplex configuration. So we only need to
477 * configure Collision Distance in the MAC.
479 e1000e_config_collision_dist(hw);
482 * Configure Flow Control now that Auto-Neg has completed.
483 * First, we need to restore the desired flow control
484 * settings because we may have had to re-autoneg with a
485 * different link partner.
487 ret_val = e1000e_config_fc_after_link_up(hw);
489 e_dbg("Error configuring flow control\n");
496 * e1000e_check_for_fiber_link - Check for link (Fiber)
497 * @hw: pointer to the HW structure
499 * Checks for link up on the hardware. If link is not up and we have
500 * a signal, then we need to force link up.
502 s32 e1000e_check_for_fiber_link(struct e1000_hw *hw)
504 struct e1000_mac_info *mac = &hw->mac;
511 status = er32(STATUS);
515 * If we don't have link (auto-negotiation failed or link partner
516 * cannot auto-negotiate), the cable is plugged in (we have signal),
517 * and our link partner is not trying to auto-negotiate with us (we
518 * are receiving idles or data), we need to force link up. We also
519 * need to give auto-negotiation time to complete, in case the cable
520 * was just plugged in. The autoneg_failed flag does this.
522 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
523 if ((ctrl & E1000_CTRL_SWDPIN1) && (!(status & E1000_STATUS_LU)) &&
524 (!(rxcw & E1000_RXCW_C))) {
525 if (mac->autoneg_failed == 0) {
526 mac->autoneg_failed = 1;
529 e_dbg("NOT RXing /C/, disable AutoNeg and force link.\n");
531 /* Disable auto-negotiation in the TXCW register */
532 ew32(TXCW, (mac->txcw & ~E1000_TXCW_ANE));
534 /* Force link-up and also force full-duplex. */
536 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
539 /* Configure Flow Control after forcing link up. */
540 ret_val = e1000e_config_fc_after_link_up(hw);
542 e_dbg("Error configuring flow control\n");
545 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
547 * If we are forcing link and we are receiving /C/ ordered
548 * sets, re-enable auto-negotiation in the TXCW register
549 * and disable forced link in the Device Control register
550 * in an attempt to auto-negotiate with our link partner.
552 e_dbg("RXing /C/, enable AutoNeg and stop forcing link.\n");
553 ew32(TXCW, mac->txcw);
554 ew32(CTRL, (ctrl & ~E1000_CTRL_SLU));
556 mac->serdes_has_link = true;
563 * e1000e_check_for_serdes_link - Check for link (Serdes)
564 * @hw: pointer to the HW structure
566 * Checks for link up on the hardware. If link is not up and we have
567 * a signal, then we need to force link up.
569 s32 e1000e_check_for_serdes_link(struct e1000_hw *hw)
571 struct e1000_mac_info *mac = &hw->mac;
578 status = er32(STATUS);
582 * If we don't have link (auto-negotiation failed or link partner
583 * cannot auto-negotiate), and our link partner is not trying to
584 * auto-negotiate with us (we are receiving idles or data),
585 * we need to force link up. We also need to give auto-negotiation
588 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
589 if ((!(status & E1000_STATUS_LU)) && (!(rxcw & E1000_RXCW_C))) {
590 if (mac->autoneg_failed == 0) {
591 mac->autoneg_failed = 1;
594 e_dbg("NOT RXing /C/, disable AutoNeg and force link.\n");
596 /* Disable auto-negotiation in the TXCW register */
597 ew32(TXCW, (mac->txcw & ~E1000_TXCW_ANE));
599 /* Force link-up and also force full-duplex. */
601 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
604 /* Configure Flow Control after forcing link up. */
605 ret_val = e1000e_config_fc_after_link_up(hw);
607 e_dbg("Error configuring flow control\n");
610 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
612 * If we are forcing link and we are receiving /C/ ordered
613 * sets, re-enable auto-negotiation in the TXCW register
614 * and disable forced link in the Device Control register
615 * in an attempt to auto-negotiate with our link partner.
617 e_dbg("RXing /C/, enable AutoNeg and stop forcing link.\n");
618 ew32(TXCW, mac->txcw);
619 ew32(CTRL, (ctrl & ~E1000_CTRL_SLU));
621 mac->serdes_has_link = true;
622 } else if (!(E1000_TXCW_ANE & er32(TXCW))) {
624 * If we force link for non-auto-negotiation switch, check
625 * link status based on MAC synchronization for internal
628 /* SYNCH bit and IV bit are sticky. */
631 if (rxcw & E1000_RXCW_SYNCH) {
632 if (!(rxcw & E1000_RXCW_IV)) {
633 mac->serdes_has_link = true;
634 e_dbg("SERDES: Link up - forced.\n");
637 mac->serdes_has_link = false;
638 e_dbg("SERDES: Link down - force failed.\n");
642 if (E1000_TXCW_ANE & er32(TXCW)) {
643 status = er32(STATUS);
644 if (status & E1000_STATUS_LU) {
645 /* SYNCH bit and IV bit are sticky, so reread rxcw. */
648 if (rxcw & E1000_RXCW_SYNCH) {
649 if (!(rxcw & E1000_RXCW_IV)) {
650 mac->serdes_has_link = true;
651 e_dbg("SERDES: Link up - autoneg "
652 "completed sucessfully.\n");
654 mac->serdes_has_link = false;
655 e_dbg("SERDES: Link down - invalid"
656 "codewords detected in autoneg.\n");
659 mac->serdes_has_link = false;
660 e_dbg("SERDES: Link down - no sync.\n");
663 mac->serdes_has_link = false;
664 e_dbg("SERDES: Link down - autoneg failed\n");
672 * e1000_set_default_fc_generic - Set flow control default values
673 * @hw: pointer to the HW structure
675 * Read the EEPROM for the default values for flow control and store the
678 static s32 e1000_set_default_fc_generic(struct e1000_hw *hw)
684 * Read and store word 0x0F of the EEPROM. This word contains bits
685 * that determine the hardware's default PAUSE (flow control) mode,
686 * a bit that determines whether the HW defaults to enabling or
687 * disabling auto-negotiation, and the direction of the
688 * SW defined pins. If there is no SW over-ride of the flow
689 * control setting, then the variable hw->fc will
690 * be initialized based on a value in the EEPROM.
692 ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &nvm_data);
695 e_dbg("NVM Read Error\n");
699 if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 0)
700 hw->fc.requested_mode = e1000_fc_none;
701 else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) ==
703 hw->fc.requested_mode = e1000_fc_tx_pause;
705 hw->fc.requested_mode = e1000_fc_full;
711 * e1000e_setup_link - Setup flow control and link settings
712 * @hw: pointer to the HW structure
714 * Determines which flow control settings to use, then configures flow
715 * control. Calls the appropriate media-specific link configuration
716 * function. Assuming the adapter has a valid link partner, a valid link
717 * should be established. Assumes the hardware has previously been reset
718 * and the transmitter and receiver are not enabled.
720 s32 e1000e_setup_link(struct e1000_hw *hw)
722 struct e1000_mac_info *mac = &hw->mac;
726 * In the case of the phy reset being blocked, we already have a link.
727 * We do not need to set it up again.
729 if (e1000_check_reset_block(hw))
733 * If requested flow control is set to default, set flow control
734 * based on the EEPROM flow control settings.
736 if (hw->fc.requested_mode == e1000_fc_default) {
737 ret_val = e1000_set_default_fc_generic(hw);
743 * Save off the requested flow control mode for use later. Depending
744 * on the link partner's capabilities, we may or may not use this mode.
746 hw->fc.current_mode = hw->fc.requested_mode;
748 e_dbg("After fix-ups FlowControl is now = %x\n",
749 hw->fc.current_mode);
751 /* Call the necessary media_type subroutine to configure the link. */
752 ret_val = mac->ops.setup_physical_interface(hw);
757 * Initialize the flow control address, type, and PAUSE timer
758 * registers to their default values. This is done even if flow
759 * control is disabled, because it does not hurt anything to
760 * initialize these registers.
762 e_dbg("Initializing the Flow Control address, type and timer regs\n");
763 ew32(FCT, FLOW_CONTROL_TYPE);
764 ew32(FCAH, FLOW_CONTROL_ADDRESS_HIGH);
765 ew32(FCAL, FLOW_CONTROL_ADDRESS_LOW);
767 ew32(FCTTV, hw->fc.pause_time);
769 return e1000e_set_fc_watermarks(hw);
773 * e1000_commit_fc_settings_generic - Configure flow control
774 * @hw: pointer to the HW structure
776 * Write the flow control settings to the Transmit Config Word Register (TXCW)
777 * base on the flow control settings in e1000_mac_info.
779 static s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw)
781 struct e1000_mac_info *mac = &hw->mac;
785 * Check for a software override of the flow control settings, and
786 * setup the device accordingly. If auto-negotiation is enabled, then
787 * software will have to set the "PAUSE" bits to the correct value in
788 * the Transmit Config Word Register (TXCW) and re-start auto-
789 * negotiation. However, if auto-negotiation is disabled, then
790 * software will have to manually configure the two flow control enable
791 * bits in the CTRL register.
793 * The possible values of the "fc" parameter are:
794 * 0: Flow control is completely disabled
795 * 1: Rx flow control is enabled (we can receive pause frames,
796 * but not send pause frames).
797 * 2: Tx flow control is enabled (we can send pause frames but we
798 * do not support receiving pause frames).
799 * 3: Both Rx and Tx flow control (symmetric) are enabled.
801 switch (hw->fc.current_mode) {
803 /* Flow control completely disabled by a software over-ride. */
804 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
806 case e1000_fc_rx_pause:
808 * Rx Flow control is enabled and Tx Flow control is disabled
809 * by a software over-ride. Since there really isn't a way to
810 * advertise that we are capable of Rx Pause ONLY, we will
811 * advertise that we support both symmetric and asymmetric Rx
812 * PAUSE. Later, we will disable the adapter's ability to send
815 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
817 case e1000_fc_tx_pause:
819 * Tx Flow control is enabled, and Rx Flow control is disabled,
820 * by a software over-ride.
822 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
826 * Flow control (both Rx and Tx) is enabled by a software
829 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
832 e_dbg("Flow control param set incorrectly\n");
833 return -E1000_ERR_CONFIG;
844 * e1000_poll_fiber_serdes_link_generic - Poll for link up
845 * @hw: pointer to the HW structure
847 * Polls for link up by reading the status register, if link fails to come
848 * up with auto-negotiation, then the link is forced if a signal is detected.
850 static s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw)
852 struct e1000_mac_info *mac = &hw->mac;
857 * If we have a signal (the cable is plugged in, or assumed true for
858 * serdes media) then poll for a "Link-Up" indication in the Device
859 * Status Register. Time-out if a link isn't seen in 500 milliseconds
860 * seconds (Auto-negotiation should complete in less than 500
861 * milliseconds even if the other end is doing it in SW).
863 for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) {
865 status = er32(STATUS);
866 if (status & E1000_STATUS_LU)
869 if (i == FIBER_LINK_UP_LIMIT) {
870 e_dbg("Never got a valid link from auto-neg!!!\n");
871 mac->autoneg_failed = 1;
873 * AutoNeg failed to achieve a link, so we'll call
874 * mac->check_for_link. This routine will force the
875 * link up if we detect a signal. This will allow us to
876 * communicate with non-autonegotiating link partners.
878 ret_val = mac->ops.check_for_link(hw);
880 e_dbg("Error while checking for link\n");
883 mac->autoneg_failed = 0;
885 mac->autoneg_failed = 0;
886 e_dbg("Valid Link Found\n");
893 * e1000e_setup_fiber_serdes_link - Setup link for fiber/serdes
894 * @hw: pointer to the HW structure
896 * Configures collision distance and flow control for fiber and serdes
897 * links. Upon successful setup, poll for link.
899 s32 e1000e_setup_fiber_serdes_link(struct e1000_hw *hw)
906 /* Take the link out of reset */
907 ctrl &= ~E1000_CTRL_LRST;
909 e1000e_config_collision_dist(hw);
911 ret_val = e1000_commit_fc_settings_generic(hw);
916 * Since auto-negotiation is enabled, take the link out of reset (the
917 * link will be in reset, because we previously reset the chip). This
918 * will restart auto-negotiation. If auto-negotiation is successful
919 * then the link-up status bit will be set and the flow control enable
920 * bits (RFCE and TFCE) will be set according to their negotiated value.
922 e_dbg("Auto-negotiation enabled\n");
929 * For these adapters, the SW definable pin 1 is set when the optics
930 * detect a signal. If we have a signal, then poll for a "Link-Up"
933 if (hw->phy.media_type == e1000_media_type_internal_serdes ||
934 (er32(CTRL) & E1000_CTRL_SWDPIN1)) {
935 ret_val = e1000_poll_fiber_serdes_link_generic(hw);
937 e_dbg("No signal detected\n");
944 * e1000e_config_collision_dist - Configure collision distance
945 * @hw: pointer to the HW structure
947 * Configures the collision distance to the default value and is used
948 * during link setup. Currently no func pointer exists and all
949 * implementations are handled in the generic version of this function.
951 void e1000e_config_collision_dist(struct e1000_hw *hw)
957 tctl &= ~E1000_TCTL_COLD;
958 tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT;
965 * e1000e_set_fc_watermarks - Set flow control high/low watermarks
966 * @hw: pointer to the HW structure
968 * Sets the flow control high/low threshold (watermark) registers. If
969 * flow control XON frame transmission is enabled, then set XON frame
970 * transmission as well.
972 s32 e1000e_set_fc_watermarks(struct e1000_hw *hw)
974 u32 fcrtl = 0, fcrth = 0;
977 * Set the flow control receive threshold registers. Normally,
978 * these registers will be set to a default threshold that may be
979 * adjusted later by the driver's runtime code. However, if the
980 * ability to transmit pause frames is not enabled, then these
981 * registers will be set to 0.
983 if (hw->fc.current_mode & e1000_fc_tx_pause) {
985 * We need to set up the Receive Threshold high and low water
986 * marks as well as (optionally) enabling the transmission of
989 fcrtl = hw->fc.low_water;
990 fcrtl |= E1000_FCRTL_XONE;
991 fcrth = hw->fc.high_water;
1000 * e1000e_force_mac_fc - Force the MAC's flow control settings
1001 * @hw: pointer to the HW structure
1003 * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the
1004 * device control register to reflect the adapter settings. TFCE and RFCE
1005 * need to be explicitly set by software when a copper PHY is used because
1006 * autonegotiation is managed by the PHY rather than the MAC. Software must
1007 * also configure these bits when link is forced on a fiber connection.
1009 s32 e1000e_force_mac_fc(struct e1000_hw *hw)
1016 * Because we didn't get link via the internal auto-negotiation
1017 * mechanism (we either forced link or we got link via PHY
1018 * auto-neg), we have to manually enable/disable transmit an
1019 * receive flow control.
1021 * The "Case" statement below enables/disable flow control
1022 * according to the "hw->fc.current_mode" parameter.
1024 * The possible values of the "fc" parameter are:
1025 * 0: Flow control is completely disabled
1026 * 1: Rx flow control is enabled (we can receive pause
1027 * frames but not send pause frames).
1028 * 2: Tx flow control is enabled (we can send pause frames
1029 * frames but we do not receive pause frames).
1030 * 3: Both Rx and Tx flow control (symmetric) is enabled.
1031 * other: No other values should be possible at this point.
1033 e_dbg("hw->fc.current_mode = %u\n", hw->fc.current_mode);
1035 switch (hw->fc.current_mode) {
1037 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
1039 case e1000_fc_rx_pause:
1040 ctrl &= (~E1000_CTRL_TFCE);
1041 ctrl |= E1000_CTRL_RFCE;
1043 case e1000_fc_tx_pause:
1044 ctrl &= (~E1000_CTRL_RFCE);
1045 ctrl |= E1000_CTRL_TFCE;
1048 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
1051 e_dbg("Flow control param set incorrectly\n");
1052 return -E1000_ERR_CONFIG;
1061 * e1000e_config_fc_after_link_up - Configures flow control after link
1062 * @hw: pointer to the HW structure
1064 * Checks the status of auto-negotiation after link up to ensure that the
1065 * speed and duplex were not forced. If the link needed to be forced, then
1066 * flow control needs to be forced also. If auto-negotiation is enabled
1067 * and did not fail, then we configure flow control based on our link
1070 s32 e1000e_config_fc_after_link_up(struct e1000_hw *hw)
1072 struct e1000_mac_info *mac = &hw->mac;
1074 u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg;
1078 * Check for the case where we have fiber media and auto-neg failed
1079 * so we had to force link. In this case, we need to force the
1080 * configuration of the MAC to match the "fc" parameter.
1082 if (mac->autoneg_failed) {
1083 if (hw->phy.media_type == e1000_media_type_fiber ||
1084 hw->phy.media_type == e1000_media_type_internal_serdes)
1085 ret_val = e1000e_force_mac_fc(hw);
1087 if (hw->phy.media_type == e1000_media_type_copper)
1088 ret_val = e1000e_force_mac_fc(hw);
1092 e_dbg("Error forcing flow control settings\n");
1097 * Check for the case where we have copper media and auto-neg is
1098 * enabled. In this case, we need to check and see if Auto-Neg
1099 * has completed, and if so, how the PHY and link partner has
1100 * flow control configured.
1102 if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) {
1104 * Read the MII Status Register and check to see if AutoNeg
1105 * has completed. We read this twice because this reg has
1106 * some "sticky" (latched) bits.
1108 ret_val = e1e_rphy(hw, PHY_STATUS, &mii_status_reg);
1111 ret_val = e1e_rphy(hw, PHY_STATUS, &mii_status_reg);
1115 if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) {
1116 e_dbg("Copper PHY and Auto Neg "
1117 "has not completed.\n");
1122 * The AutoNeg process has completed, so we now need to
1123 * read both the Auto Negotiation Advertisement
1124 * Register (Address 4) and the Auto_Negotiation Base
1125 * Page Ability Register (Address 5) to determine how
1126 * flow control was negotiated.
1128 ret_val = e1e_rphy(hw, PHY_AUTONEG_ADV, &mii_nway_adv_reg);
1131 ret_val = e1e_rphy(hw, PHY_LP_ABILITY, &mii_nway_lp_ability_reg);
1136 * Two bits in the Auto Negotiation Advertisement Register
1137 * (Address 4) and two bits in the Auto Negotiation Base
1138 * Page Ability Register (Address 5) determine flow control
1139 * for both the PHY and the link partner. The following
1140 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
1141 * 1999, describes these PAUSE resolution bits and how flow
1142 * control is determined based upon these settings.
1143 * NOTE: DC = Don't Care
1145 * LOCAL DEVICE | LINK PARTNER
1146 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
1147 *-------|---------|-------|---------|--------------------
1148 * 0 | 0 | DC | DC | e1000_fc_none
1149 * 0 | 1 | 0 | DC | e1000_fc_none
1150 * 0 | 1 | 1 | 0 | e1000_fc_none
1151 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1152 * 1 | 0 | 0 | DC | e1000_fc_none
1153 * 1 | DC | 1 | DC | e1000_fc_full
1154 * 1 | 1 | 0 | 0 | e1000_fc_none
1155 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1157 * Are both PAUSE bits set to 1? If so, this implies
1158 * Symmetric Flow Control is enabled at both ends. The
1159 * ASM_DIR bits are irrelevant per the spec.
1161 * For Symmetric Flow Control:
1163 * LOCAL DEVICE | LINK PARTNER
1164 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1165 *-------|---------|-------|---------|--------------------
1166 * 1 | DC | 1 | DC | E1000_fc_full
1169 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1170 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
1172 * Now we need to check if the user selected Rx ONLY
1173 * of pause frames. In this case, we had to advertise
1174 * FULL flow control because we could not advertise Rx
1175 * ONLY. Hence, we must now check to see if we need to
1176 * turn OFF the TRANSMISSION of PAUSE frames.
1178 if (hw->fc.requested_mode == e1000_fc_full) {
1179 hw->fc.current_mode = e1000_fc_full;
1180 e_dbg("Flow Control = FULL.\r\n");
1182 hw->fc.current_mode = e1000_fc_rx_pause;
1183 e_dbg("Flow Control = "
1184 "RX PAUSE frames only.\r\n");
1188 * For receiving PAUSE frames ONLY.
1190 * LOCAL DEVICE | LINK PARTNER
1191 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1192 *-------|---------|-------|---------|--------------------
1193 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1195 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1196 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1197 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1198 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1199 hw->fc.current_mode = e1000_fc_tx_pause;
1200 e_dbg("Flow Control = Tx PAUSE frames only.\r\n");
1203 * For transmitting PAUSE frames ONLY.
1205 * LOCAL DEVICE | LINK PARTNER
1206 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1207 *-------|---------|-------|---------|--------------------
1208 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1210 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1211 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1212 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1213 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1214 hw->fc.current_mode = e1000_fc_rx_pause;
1215 e_dbg("Flow Control = Rx PAUSE frames only.\r\n");
1218 * Per the IEEE spec, at this point flow control
1219 * should be disabled.
1221 hw->fc.current_mode = e1000_fc_none;
1222 e_dbg("Flow Control = NONE.\r\n");
1226 * Now we need to do one last check... If we auto-
1227 * negotiated to HALF DUPLEX, flow control should not be
1228 * enabled per IEEE 802.3 spec.
1230 ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex);
1232 e_dbg("Error getting link speed and duplex\n");
1236 if (duplex == HALF_DUPLEX)
1237 hw->fc.current_mode = e1000_fc_none;
1240 * Now we call a subroutine to actually force the MAC
1241 * controller to use the correct flow control settings.
1243 ret_val = e1000e_force_mac_fc(hw);
1245 e_dbg("Error forcing flow control settings\n");
1254 * e1000e_get_speed_and_duplex_copper - Retrieve current speed/duplex
1255 * @hw: pointer to the HW structure
1256 * @speed: stores the current speed
1257 * @duplex: stores the current duplex
1259 * Read the status register for the current speed/duplex and store the current
1260 * speed and duplex for copper connections.
1262 s32 e1000e_get_speed_and_duplex_copper(struct e1000_hw *hw, u16 *speed, u16 *duplex)
1266 status = er32(STATUS);
1267 if (status & E1000_STATUS_SPEED_1000) {
1268 *speed = SPEED_1000;
1269 e_dbg("1000 Mbs, ");
1270 } else if (status & E1000_STATUS_SPEED_100) {
1278 if (status & E1000_STATUS_FD) {
1279 *duplex = FULL_DUPLEX;
1280 e_dbg("Full Duplex\n");
1282 *duplex = HALF_DUPLEX;
1283 e_dbg("Half Duplex\n");
1290 * e1000e_get_speed_and_duplex_fiber_serdes - Retrieve current speed/duplex
1291 * @hw: pointer to the HW structure
1292 * @speed: stores the current speed
1293 * @duplex: stores the current duplex
1295 * Sets the speed and duplex to gigabit full duplex (the only possible option)
1296 * for fiber/serdes links.
1298 s32 e1000e_get_speed_and_duplex_fiber_serdes(struct e1000_hw *hw, u16 *speed, u16 *duplex)
1300 *speed = SPEED_1000;
1301 *duplex = FULL_DUPLEX;
1307 * e1000e_get_hw_semaphore - Acquire hardware semaphore
1308 * @hw: pointer to the HW structure
1310 * Acquire the HW semaphore to access the PHY or NVM
1312 s32 e1000e_get_hw_semaphore(struct e1000_hw *hw)
1315 s32 timeout = hw->nvm.word_size + 1;
1318 /* Get the SW semaphore */
1319 while (i < timeout) {
1321 if (!(swsm & E1000_SWSM_SMBI))
1329 e_dbg("Driver can't access device - SMBI bit is set.\n");
1330 return -E1000_ERR_NVM;
1333 /* Get the FW semaphore. */
1334 for (i = 0; i < timeout; i++) {
1336 ew32(SWSM, swsm | E1000_SWSM_SWESMBI);
1338 /* Semaphore acquired if bit latched */
1339 if (er32(SWSM) & E1000_SWSM_SWESMBI)
1346 /* Release semaphores */
1347 e1000e_put_hw_semaphore(hw);
1348 e_dbg("Driver can't access the NVM\n");
1349 return -E1000_ERR_NVM;
1356 * e1000e_put_hw_semaphore - Release hardware semaphore
1357 * @hw: pointer to the HW structure
1359 * Release hardware semaphore used to access the PHY or NVM
1361 void e1000e_put_hw_semaphore(struct e1000_hw *hw)
1366 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
1371 * e1000e_get_auto_rd_done - Check for auto read completion
1372 * @hw: pointer to the HW structure
1374 * Check EEPROM for Auto Read done bit.
1376 s32 e1000e_get_auto_rd_done(struct e1000_hw *hw)
1380 while (i < AUTO_READ_DONE_TIMEOUT) {
1381 if (er32(EECD) & E1000_EECD_AUTO_RD)
1387 if (i == AUTO_READ_DONE_TIMEOUT) {
1388 e_dbg("Auto read by HW from NVM has not completed.\n");
1389 return -E1000_ERR_RESET;
1396 * e1000e_valid_led_default - Verify a valid default LED config
1397 * @hw: pointer to the HW structure
1398 * @data: pointer to the NVM (EEPROM)
1400 * Read the EEPROM for the current default LED configuration. If the
1401 * LED configuration is not valid, set to a valid LED configuration.
1403 s32 e1000e_valid_led_default(struct e1000_hw *hw, u16 *data)
1407 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
1409 e_dbg("NVM Read Error\n");
1413 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
1414 *data = ID_LED_DEFAULT;
1420 * e1000e_id_led_init -
1421 * @hw: pointer to the HW structure
1424 s32 e1000e_id_led_init(struct e1000_hw *hw)
1426 struct e1000_mac_info *mac = &hw->mac;
1428 const u32 ledctl_mask = 0x000000FF;
1429 const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON;
1430 const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
1432 const u16 led_mask = 0x0F;
1434 ret_val = hw->nvm.ops.valid_led_default(hw, &data);
1438 mac->ledctl_default = er32(LEDCTL);
1439 mac->ledctl_mode1 = mac->ledctl_default;
1440 mac->ledctl_mode2 = mac->ledctl_default;
1442 for (i = 0; i < 4; i++) {
1443 temp = (data >> (i << 2)) & led_mask;
1445 case ID_LED_ON1_DEF2:
1446 case ID_LED_ON1_ON2:
1447 case ID_LED_ON1_OFF2:
1448 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
1449 mac->ledctl_mode1 |= ledctl_on << (i << 3);
1451 case ID_LED_OFF1_DEF2:
1452 case ID_LED_OFF1_ON2:
1453 case ID_LED_OFF1_OFF2:
1454 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
1455 mac->ledctl_mode1 |= ledctl_off << (i << 3);
1462 case ID_LED_DEF1_ON2:
1463 case ID_LED_ON1_ON2:
1464 case ID_LED_OFF1_ON2:
1465 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
1466 mac->ledctl_mode2 |= ledctl_on << (i << 3);
1468 case ID_LED_DEF1_OFF2:
1469 case ID_LED_ON1_OFF2:
1470 case ID_LED_OFF1_OFF2:
1471 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
1472 mac->ledctl_mode2 |= ledctl_off << (i << 3);
1484 * e1000e_setup_led_generic - Configures SW controllable LED
1485 * @hw: pointer to the HW structure
1487 * This prepares the SW controllable LED for use and saves the current state
1488 * of the LED so it can be later restored.
1490 s32 e1000e_setup_led_generic(struct e1000_hw *hw)
1494 if (hw->mac.ops.setup_led != e1000e_setup_led_generic) {
1495 return -E1000_ERR_CONFIG;
1498 if (hw->phy.media_type == e1000_media_type_fiber) {
1499 ledctl = er32(LEDCTL);
1500 hw->mac.ledctl_default = ledctl;
1502 ledctl &= ~(E1000_LEDCTL_LED0_IVRT |
1503 E1000_LEDCTL_LED0_BLINK |
1504 E1000_LEDCTL_LED0_MODE_MASK);
1505 ledctl |= (E1000_LEDCTL_MODE_LED_OFF <<
1506 E1000_LEDCTL_LED0_MODE_SHIFT);
1507 ew32(LEDCTL, ledctl);
1508 } else if (hw->phy.media_type == e1000_media_type_copper) {
1509 ew32(LEDCTL, hw->mac.ledctl_mode1);
1516 * e1000e_cleanup_led_generic - Set LED config to default operation
1517 * @hw: pointer to the HW structure
1519 * Remove the current LED configuration and set the LED configuration
1520 * to the default value, saved from the EEPROM.
1522 s32 e1000e_cleanup_led_generic(struct e1000_hw *hw)
1524 ew32(LEDCTL, hw->mac.ledctl_default);
1529 * e1000e_blink_led - Blink LED
1530 * @hw: pointer to the HW structure
1532 * Blink the LEDs which are set to be on.
1534 s32 e1000e_blink_led(struct e1000_hw *hw)
1536 u32 ledctl_blink = 0;
1539 if (hw->phy.media_type == e1000_media_type_fiber) {
1540 /* always blink LED0 for PCI-E fiber */
1541 ledctl_blink = E1000_LEDCTL_LED0_BLINK |
1542 (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT);
1545 * set the blink bit for each LED that's "on" (0x0E)
1548 ledctl_blink = hw->mac.ledctl_mode2;
1549 for (i = 0; i < 4; i++)
1550 if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) ==
1551 E1000_LEDCTL_MODE_LED_ON)
1552 ledctl_blink |= (E1000_LEDCTL_LED0_BLINK <<
1556 ew32(LEDCTL, ledctl_blink);
1562 * e1000e_led_on_generic - Turn LED on
1563 * @hw: pointer to the HW structure
1567 s32 e1000e_led_on_generic(struct e1000_hw *hw)
1571 switch (hw->phy.media_type) {
1572 case e1000_media_type_fiber:
1574 ctrl &= ~E1000_CTRL_SWDPIN0;
1575 ctrl |= E1000_CTRL_SWDPIO0;
1578 case e1000_media_type_copper:
1579 ew32(LEDCTL, hw->mac.ledctl_mode2);
1589 * e1000e_led_off_generic - Turn LED off
1590 * @hw: pointer to the HW structure
1594 s32 e1000e_led_off_generic(struct e1000_hw *hw)
1598 switch (hw->phy.media_type) {
1599 case e1000_media_type_fiber:
1601 ctrl |= E1000_CTRL_SWDPIN0;
1602 ctrl |= E1000_CTRL_SWDPIO0;
1605 case e1000_media_type_copper:
1606 ew32(LEDCTL, hw->mac.ledctl_mode1);
1616 * e1000e_set_pcie_no_snoop - Set PCI-express capabilities
1617 * @hw: pointer to the HW structure
1618 * @no_snoop: bitmap of snoop events
1620 * Set the PCI-express register to snoop for events enabled in 'no_snoop'.
1622 void e1000e_set_pcie_no_snoop(struct e1000_hw *hw, u32 no_snoop)
1628 gcr &= ~(PCIE_NO_SNOOP_ALL);
1635 * e1000e_disable_pcie_master - Disables PCI-express master access
1636 * @hw: pointer to the HW structure
1638 * Returns 0 if successful, else returns -10
1639 * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused
1640 * the master requests to be disabled.
1642 * Disables PCI-Express master access and verifies there are no pending
1645 s32 e1000e_disable_pcie_master(struct e1000_hw *hw)
1648 s32 timeout = MASTER_DISABLE_TIMEOUT;
1651 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE;
1655 if (!(er32(STATUS) &
1656 E1000_STATUS_GIO_MASTER_ENABLE))
1663 e_dbg("Master requests are pending.\n");
1664 return -E1000_ERR_MASTER_REQUESTS_PENDING;
1671 * e1000e_reset_adaptive - Reset Adaptive Interframe Spacing
1672 * @hw: pointer to the HW structure
1674 * Reset the Adaptive Interframe Spacing throttle to default values.
1676 void e1000e_reset_adaptive(struct e1000_hw *hw)
1678 struct e1000_mac_info *mac = &hw->mac;
1680 if (!mac->adaptive_ifs) {
1681 e_dbg("Not in Adaptive IFS mode!\n");
1685 mac->current_ifs_val = 0;
1686 mac->ifs_min_val = IFS_MIN;
1687 mac->ifs_max_val = IFS_MAX;
1688 mac->ifs_step_size = IFS_STEP;
1689 mac->ifs_ratio = IFS_RATIO;
1691 mac->in_ifs_mode = false;
1698 * e1000e_update_adaptive - Update Adaptive Interframe Spacing
1699 * @hw: pointer to the HW structure
1701 * Update the Adaptive Interframe Spacing Throttle value based on the
1702 * time between transmitted packets and time between collisions.
1704 void e1000e_update_adaptive(struct e1000_hw *hw)
1706 struct e1000_mac_info *mac = &hw->mac;
1708 if (!mac->adaptive_ifs) {
1709 e_dbg("Not in Adaptive IFS mode!\n");
1713 if ((mac->collision_delta * mac->ifs_ratio) > mac->tx_packet_delta) {
1714 if (mac->tx_packet_delta > MIN_NUM_XMITS) {
1715 mac->in_ifs_mode = true;
1716 if (mac->current_ifs_val < mac->ifs_max_val) {
1717 if (!mac->current_ifs_val)
1718 mac->current_ifs_val = mac->ifs_min_val;
1720 mac->current_ifs_val +=
1722 ew32(AIT, mac->current_ifs_val);
1726 if (mac->in_ifs_mode &&
1727 (mac->tx_packet_delta <= MIN_NUM_XMITS)) {
1728 mac->current_ifs_val = 0;
1729 mac->in_ifs_mode = false;
1738 * e1000_raise_eec_clk - Raise EEPROM clock
1739 * @hw: pointer to the HW structure
1740 * @eecd: pointer to the EEPROM
1742 * Enable/Raise the EEPROM clock bit.
1744 static void e1000_raise_eec_clk(struct e1000_hw *hw, u32 *eecd)
1746 *eecd = *eecd | E1000_EECD_SK;
1749 udelay(hw->nvm.delay_usec);
1753 * e1000_lower_eec_clk - Lower EEPROM clock
1754 * @hw: pointer to the HW structure
1755 * @eecd: pointer to the EEPROM
1757 * Clear/Lower the EEPROM clock bit.
1759 static void e1000_lower_eec_clk(struct e1000_hw *hw, u32 *eecd)
1761 *eecd = *eecd & ~E1000_EECD_SK;
1764 udelay(hw->nvm.delay_usec);
1768 * e1000_shift_out_eec_bits - Shift data bits our to the EEPROM
1769 * @hw: pointer to the HW structure
1770 * @data: data to send to the EEPROM
1771 * @count: number of bits to shift out
1773 * We need to shift 'count' bits out to the EEPROM. So, the value in the
1774 * "data" parameter will be shifted out to the EEPROM one bit at a time.
1775 * In order to do this, "data" must be broken down into bits.
1777 static void e1000_shift_out_eec_bits(struct e1000_hw *hw, u16 data, u16 count)
1779 struct e1000_nvm_info *nvm = &hw->nvm;
1780 u32 eecd = er32(EECD);
1783 mask = 0x01 << (count - 1);
1784 if (nvm->type == e1000_nvm_eeprom_spi)
1785 eecd |= E1000_EECD_DO;
1788 eecd &= ~E1000_EECD_DI;
1791 eecd |= E1000_EECD_DI;
1796 udelay(nvm->delay_usec);
1798 e1000_raise_eec_clk(hw, &eecd);
1799 e1000_lower_eec_clk(hw, &eecd);
1804 eecd &= ~E1000_EECD_DI;
1809 * e1000_shift_in_eec_bits - Shift data bits in from the EEPROM
1810 * @hw: pointer to the HW structure
1811 * @count: number of bits to shift in
1813 * In order to read a register from the EEPROM, we need to shift 'count' bits
1814 * in from the EEPROM. Bits are "shifted in" by raising the clock input to
1815 * the EEPROM (setting the SK bit), and then reading the value of the data out
1816 * "DO" bit. During this "shifting in" process the data in "DI" bit should
1819 static u16 e1000_shift_in_eec_bits(struct e1000_hw *hw, u16 count)
1827 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
1830 for (i = 0; i < count; i++) {
1832 e1000_raise_eec_clk(hw, &eecd);
1836 eecd &= ~E1000_EECD_DI;
1837 if (eecd & E1000_EECD_DO)
1840 e1000_lower_eec_clk(hw, &eecd);
1847 * e1000e_poll_eerd_eewr_done - Poll for EEPROM read/write completion
1848 * @hw: pointer to the HW structure
1849 * @ee_reg: EEPROM flag for polling
1851 * Polls the EEPROM status bit for either read or write completion based
1852 * upon the value of 'ee_reg'.
1854 s32 e1000e_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg)
1856 u32 attempts = 100000;
1859 for (i = 0; i < attempts; i++) {
1860 if (ee_reg == E1000_NVM_POLL_READ)
1865 if (reg & E1000_NVM_RW_REG_DONE)
1871 return -E1000_ERR_NVM;
1875 * e1000e_acquire_nvm - Generic request for access to EEPROM
1876 * @hw: pointer to the HW structure
1878 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
1879 * Return successful if access grant bit set, else clear the request for
1880 * EEPROM access and return -E1000_ERR_NVM (-1).
1882 s32 e1000e_acquire_nvm(struct e1000_hw *hw)
1884 u32 eecd = er32(EECD);
1885 s32 timeout = E1000_NVM_GRANT_ATTEMPTS;
1887 ew32(EECD, eecd | E1000_EECD_REQ);
1891 if (eecd & E1000_EECD_GNT)
1899 eecd &= ~E1000_EECD_REQ;
1901 e_dbg("Could not acquire NVM grant\n");
1902 return -E1000_ERR_NVM;
1909 * e1000_standby_nvm - Return EEPROM to standby state
1910 * @hw: pointer to the HW structure
1912 * Return the EEPROM to a standby state.
1914 static void e1000_standby_nvm(struct e1000_hw *hw)
1916 struct e1000_nvm_info *nvm = &hw->nvm;
1917 u32 eecd = er32(EECD);
1919 if (nvm->type == e1000_nvm_eeprom_spi) {
1920 /* Toggle CS to flush commands */
1921 eecd |= E1000_EECD_CS;
1924 udelay(nvm->delay_usec);
1925 eecd &= ~E1000_EECD_CS;
1928 udelay(nvm->delay_usec);
1933 * e1000_stop_nvm - Terminate EEPROM command
1934 * @hw: pointer to the HW structure
1936 * Terminates the current command by inverting the EEPROM's chip select pin.
1938 static void e1000_stop_nvm(struct e1000_hw *hw)
1943 if (hw->nvm.type == e1000_nvm_eeprom_spi) {
1945 eecd |= E1000_EECD_CS;
1946 e1000_lower_eec_clk(hw, &eecd);
1951 * e1000e_release_nvm - Release exclusive access to EEPROM
1952 * @hw: pointer to the HW structure
1954 * Stop any current commands to the EEPROM and clear the EEPROM request bit.
1956 void e1000e_release_nvm(struct e1000_hw *hw)
1963 eecd &= ~E1000_EECD_REQ;
1968 * e1000_ready_nvm_eeprom - Prepares EEPROM for read/write
1969 * @hw: pointer to the HW structure
1971 * Setups the EEPROM for reading and writing.
1973 static s32 e1000_ready_nvm_eeprom(struct e1000_hw *hw)
1975 struct e1000_nvm_info *nvm = &hw->nvm;
1976 u32 eecd = er32(EECD);
1980 if (nvm->type == e1000_nvm_eeprom_spi) {
1981 /* Clear SK and CS */
1982 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
1985 timeout = NVM_MAX_RETRY_SPI;
1988 * Read "Status Register" repeatedly until the LSB is cleared.
1989 * The EEPROM will signal that the command has been completed
1990 * by clearing bit 0 of the internal status register. If it's
1991 * not cleared within 'timeout', then error out.
1994 e1000_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI,
1995 hw->nvm.opcode_bits);
1996 spi_stat_reg = (u8)e1000_shift_in_eec_bits(hw, 8);
1997 if (!(spi_stat_reg & NVM_STATUS_RDY_SPI))
2001 e1000_standby_nvm(hw);
2006 e_dbg("SPI NVM Status error\n");
2007 return -E1000_ERR_NVM;
2015 * e1000e_read_nvm_eerd - Reads EEPROM using EERD register
2016 * @hw: pointer to the HW structure
2017 * @offset: offset of word in the EEPROM to read
2018 * @words: number of words to read
2019 * @data: word read from the EEPROM
2021 * Reads a 16 bit word from the EEPROM using the EERD register.
2023 s32 e1000e_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
2025 struct e1000_nvm_info *nvm = &hw->nvm;
2030 * A check for invalid values: offset too large, too many words,
2031 * too many words for the offset, and not enough words.
2033 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
2035 e_dbg("nvm parameter(s) out of bounds\n");
2036 return -E1000_ERR_NVM;
2039 for (i = 0; i < words; i++) {
2040 eerd = ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) +
2041 E1000_NVM_RW_REG_START;
2044 ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_READ);
2048 data[i] = (er32(EERD) >> E1000_NVM_RW_REG_DATA);
2055 * e1000e_write_nvm_spi - Write to EEPROM using SPI
2056 * @hw: pointer to the HW structure
2057 * @offset: offset within the EEPROM to be written to
2058 * @words: number of words to write
2059 * @data: 16 bit word(s) to be written to the EEPROM
2061 * Writes data to EEPROM at offset using SPI interface.
2063 * If e1000e_update_nvm_checksum is not called after this function , the
2064 * EEPROM will most likely contain an invalid checksum.
2066 s32 e1000e_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
2068 struct e1000_nvm_info *nvm = &hw->nvm;
2073 * A check for invalid values: offset too large, too many words,
2074 * and not enough words.
2076 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
2078 e_dbg("nvm parameter(s) out of bounds\n");
2079 return -E1000_ERR_NVM;
2082 ret_val = nvm->ops.acquire(hw);
2088 while (widx < words) {
2089 u8 write_opcode = NVM_WRITE_OPCODE_SPI;
2091 ret_val = e1000_ready_nvm_eeprom(hw);
2093 nvm->ops.release(hw);
2097 e1000_standby_nvm(hw);
2099 /* Send the WRITE ENABLE command (8 bit opcode) */
2100 e1000_shift_out_eec_bits(hw, NVM_WREN_OPCODE_SPI,
2103 e1000_standby_nvm(hw);
2106 * Some SPI eeproms use the 8th address bit embedded in the
2109 if ((nvm->address_bits == 8) && (offset >= 128))
2110 write_opcode |= NVM_A8_OPCODE_SPI;
2112 /* Send the Write command (8-bit opcode + addr) */
2113 e1000_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits);
2114 e1000_shift_out_eec_bits(hw, (u16)((offset + widx) * 2),
2117 /* Loop to allow for up to whole page write of eeprom */
2118 while (widx < words) {
2119 u16 word_out = data[widx];
2120 word_out = (word_out >> 8) | (word_out << 8);
2121 e1000_shift_out_eec_bits(hw, word_out, 16);
2124 if ((((offset + widx) * 2) % nvm->page_size) == 0) {
2125 e1000_standby_nvm(hw);
2132 nvm->ops.release(hw);
2137 * e1000_read_mac_addr_generic - Read device MAC address
2138 * @hw: pointer to the HW structure
2140 * Reads the device MAC address from the EEPROM and stores the value.
2141 * Since devices with two ports use the same EEPROM, we increment the
2142 * last bit in the MAC address for the second port.
2144 s32 e1000_read_mac_addr_generic(struct e1000_hw *hw)
2150 rar_high = er32(RAH(0));
2151 rar_low = er32(RAL(0));
2153 for (i = 0; i < E1000_RAL_MAC_ADDR_LEN; i++)
2154 hw->mac.perm_addr[i] = (u8)(rar_low >> (i*8));
2156 for (i = 0; i < E1000_RAH_MAC_ADDR_LEN; i++)
2157 hw->mac.perm_addr[i+4] = (u8)(rar_high >> (i*8));
2159 for (i = 0; i < ETH_ALEN; i++)
2160 hw->mac.addr[i] = hw->mac.perm_addr[i];
2166 * e1000e_validate_nvm_checksum_generic - Validate EEPROM checksum
2167 * @hw: pointer to the HW structure
2169 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
2170 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
2172 s32 e1000e_validate_nvm_checksum_generic(struct e1000_hw *hw)
2178 for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) {
2179 ret_val = e1000_read_nvm(hw, i, 1, &nvm_data);
2181 e_dbg("NVM Read Error\n");
2184 checksum += nvm_data;
2187 if (checksum != (u16) NVM_SUM) {
2188 e_dbg("NVM Checksum Invalid\n");
2189 return -E1000_ERR_NVM;
2196 * e1000e_update_nvm_checksum_generic - Update EEPROM checksum
2197 * @hw: pointer to the HW structure
2199 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
2200 * up to the checksum. Then calculates the EEPROM checksum and writes the
2201 * value to the EEPROM.
2203 s32 e1000e_update_nvm_checksum_generic(struct e1000_hw *hw)
2209 for (i = 0; i < NVM_CHECKSUM_REG; i++) {
2210 ret_val = e1000_read_nvm(hw, i, 1, &nvm_data);
2212 e_dbg("NVM Read Error while updating checksum.\n");
2215 checksum += nvm_data;
2217 checksum = (u16) NVM_SUM - checksum;
2218 ret_val = e1000_write_nvm(hw, NVM_CHECKSUM_REG, 1, &checksum);
2220 e_dbg("NVM Write Error while updating checksum.\n");
2226 * e1000e_reload_nvm - Reloads EEPROM
2227 * @hw: pointer to the HW structure
2229 * Reloads the EEPROM by setting the "Reinitialize from EEPROM" bit in the
2230 * extended control register.
2232 void e1000e_reload_nvm(struct e1000_hw *hw)
2237 ctrl_ext = er32(CTRL_EXT);
2238 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
2239 ew32(CTRL_EXT, ctrl_ext);
2244 * e1000_calculate_checksum - Calculate checksum for buffer
2245 * @buffer: pointer to EEPROM
2246 * @length: size of EEPROM to calculate a checksum for
2248 * Calculates the checksum for some buffer on a specified length. The
2249 * checksum calculated is returned.
2251 static u8 e1000_calculate_checksum(u8 *buffer, u32 length)
2259 for (i = 0; i < length; i++)
2262 return (u8) (0 - sum);
2266 * e1000_mng_enable_host_if - Checks host interface is enabled
2267 * @hw: pointer to the HW structure
2269 * Returns E1000_success upon success, else E1000_ERR_HOST_INTERFACE_COMMAND
2271 * This function checks whether the HOST IF is enabled for command operation
2272 * and also checks whether the previous command is completed. It busy waits
2273 * in case of previous command is not completed.
2275 static s32 e1000_mng_enable_host_if(struct e1000_hw *hw)
2280 /* Check that the host interface is enabled. */
2282 if ((hicr & E1000_HICR_EN) == 0) {
2283 e_dbg("E1000_HOST_EN bit disabled.\n");
2284 return -E1000_ERR_HOST_INTERFACE_COMMAND;
2286 /* check the previous command is completed */
2287 for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) {
2289 if (!(hicr & E1000_HICR_C))
2294 if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) {
2295 e_dbg("Previous command timeout failed .\n");
2296 return -E1000_ERR_HOST_INTERFACE_COMMAND;
2303 * e1000e_check_mng_mode_generic - check management mode
2304 * @hw: pointer to the HW structure
2306 * Reads the firmware semaphore register and returns true (>0) if
2307 * manageability is enabled, else false (0).
2309 bool e1000e_check_mng_mode_generic(struct e1000_hw *hw)
2311 u32 fwsm = er32(FWSM);
2313 return (fwsm & E1000_FWSM_MODE_MASK) ==
2314 (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT);
2318 * e1000e_enable_tx_pkt_filtering - Enable packet filtering on Tx
2319 * @hw: pointer to the HW structure
2321 * Enables packet filtering on transmit packets if manageability is enabled
2322 * and host interface is enabled.
2324 bool e1000e_enable_tx_pkt_filtering(struct e1000_hw *hw)
2326 struct e1000_host_mng_dhcp_cookie *hdr = &hw->mng_cookie;
2327 u32 *buffer = (u32 *)&hw->mng_cookie;
2329 s32 ret_val, hdr_csum, csum;
2332 hw->mac.tx_pkt_filtering = true;
2334 /* No manageability, no filtering */
2335 if (!e1000e_check_mng_mode(hw)) {
2336 hw->mac.tx_pkt_filtering = false;
2341 * If we can't read from the host interface for whatever
2342 * reason, disable filtering.
2344 ret_val = e1000_mng_enable_host_if(hw);
2346 hw->mac.tx_pkt_filtering = false;
2350 /* Read in the header. Length and offset are in dwords. */
2351 len = E1000_MNG_DHCP_COOKIE_LENGTH >> 2;
2352 offset = E1000_MNG_DHCP_COOKIE_OFFSET >> 2;
2353 for (i = 0; i < len; i++)
2354 *(buffer + i) = E1000_READ_REG_ARRAY(hw, E1000_HOST_IF, offset + i);
2355 hdr_csum = hdr->checksum;
2357 csum = e1000_calculate_checksum((u8 *)hdr,
2358 E1000_MNG_DHCP_COOKIE_LENGTH);
2360 * If either the checksums or signature don't match, then
2361 * the cookie area isn't considered valid, in which case we
2362 * take the safe route of assuming Tx filtering is enabled.
2364 if ((hdr_csum != csum) || (hdr->signature != E1000_IAMT_SIGNATURE)) {
2365 hw->mac.tx_pkt_filtering = true;
2369 /* Cookie area is valid, make the final check for filtering. */
2370 if (!(hdr->status & E1000_MNG_DHCP_COOKIE_STATUS_PARSING)) {
2371 hw->mac.tx_pkt_filtering = false;
2376 return hw->mac.tx_pkt_filtering;
2380 * e1000_mng_write_cmd_header - Writes manageability command header
2381 * @hw: pointer to the HW structure
2382 * @hdr: pointer to the host interface command header
2384 * Writes the command header after does the checksum calculation.
2386 static s32 e1000_mng_write_cmd_header(struct e1000_hw *hw,
2387 struct e1000_host_mng_command_header *hdr)
2389 u16 i, length = sizeof(struct e1000_host_mng_command_header);
2391 /* Write the whole command header structure with new checksum. */
2393 hdr->checksum = e1000_calculate_checksum((u8 *)hdr, length);
2396 /* Write the relevant command block into the ram area. */
2397 for (i = 0; i < length; i++) {
2398 E1000_WRITE_REG_ARRAY(hw, E1000_HOST_IF, i,
2399 *((u32 *) hdr + i));
2407 * e1000_mng_host_if_write - Write to the manageability host interface
2408 * @hw: pointer to the HW structure
2409 * @buffer: pointer to the host interface buffer
2410 * @length: size of the buffer
2411 * @offset: location in the buffer to write to
2412 * @sum: sum of the data (not checksum)
2414 * This function writes the buffer content at the offset given on the host if.
2415 * It also does alignment considerations to do the writes in most efficient
2416 * way. Also fills up the sum of the buffer in *buffer parameter.
2418 static s32 e1000_mng_host_if_write(struct e1000_hw *hw, u8 *buffer,
2419 u16 length, u16 offset, u8 *sum)
2422 u8 *bufptr = buffer;
2424 u16 remaining, i, j, prev_bytes;
2426 /* sum = only sum of the data and it is not checksum */
2428 if (length == 0 || offset + length > E1000_HI_MAX_MNG_DATA_LENGTH)
2429 return -E1000_ERR_PARAM;
2432 prev_bytes = offset & 0x3;
2436 data = E1000_READ_REG_ARRAY(hw, E1000_HOST_IF, offset);
2437 for (j = prev_bytes; j < sizeof(u32); j++) {
2438 *(tmp + j) = *bufptr++;
2441 E1000_WRITE_REG_ARRAY(hw, E1000_HOST_IF, offset, data);
2442 length -= j - prev_bytes;
2446 remaining = length & 0x3;
2447 length -= remaining;
2449 /* Calculate length in DWORDs */
2453 * The device driver writes the relevant command block into the
2456 for (i = 0; i < length; i++) {
2457 for (j = 0; j < sizeof(u32); j++) {
2458 *(tmp + j) = *bufptr++;
2462 E1000_WRITE_REG_ARRAY(hw, E1000_HOST_IF, offset + i, data);
2465 for (j = 0; j < sizeof(u32); j++) {
2467 *(tmp + j) = *bufptr++;
2473 E1000_WRITE_REG_ARRAY(hw, E1000_HOST_IF, offset + i, data);
2480 * e1000e_mng_write_dhcp_info - Writes DHCP info to host interface
2481 * @hw: pointer to the HW structure
2482 * @buffer: pointer to the host interface
2483 * @length: size of the buffer
2485 * Writes the DHCP information to the host interface.
2487 s32 e1000e_mng_write_dhcp_info(struct e1000_hw *hw, u8 *buffer, u16 length)
2489 struct e1000_host_mng_command_header hdr;
2493 hdr.command_id = E1000_MNG_DHCP_TX_PAYLOAD_CMD;
2494 hdr.command_length = length;
2499 /* Enable the host interface */
2500 ret_val = e1000_mng_enable_host_if(hw);
2504 /* Populate the host interface with the contents of "buffer". */
2505 ret_val = e1000_mng_host_if_write(hw, buffer, length,
2506 sizeof(hdr), &(hdr.checksum));
2510 /* Write the manageability command header */
2511 ret_val = e1000_mng_write_cmd_header(hw, &hdr);
2515 /* Tell the ARC a new command is pending. */
2517 ew32(HICR, hicr | E1000_HICR_C);
2523 * e1000e_enable_mng_pass_thru - Enable processing of ARP's
2524 * @hw: pointer to the HW structure
2526 * Verifies the hardware needs to allow ARPs to be processed by the host.
2528 bool e1000e_enable_mng_pass_thru(struct e1000_hw *hw)
2532 bool ret_val = false;
2536 if (!(manc & E1000_MANC_RCV_TCO_EN) ||
2537 !(manc & E1000_MANC_EN_MAC_ADDR_FILTER))
2540 if (hw->mac.arc_subsystem_valid) {
2542 factps = er32(FACTPS);
2544 if (!(factps & E1000_FACTPS_MNGCG) &&
2545 ((fwsm & E1000_FWSM_MODE_MASK) ==
2546 (e1000_mng_mode_pt << E1000_FWSM_MODE_SHIFT))) {
2551 if ((manc & E1000_MANC_SMBUS_EN) &&
2552 !(manc & E1000_MANC_ASF_EN)) {
2561 s32 e1000e_read_pba_num(struct e1000_hw *hw, u32 *pba_num)
2566 ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
2568 e_dbg("NVM Read Error\n");
2571 *pba_num = (u32)(nvm_data << 16);
2573 ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_1, 1, &nvm_data);
2575 e_dbg("NVM Read Error\n");
2578 *pba_num |= nvm_data;