1 /*******************************************************************************
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2009 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
32 e1000_mng_mode_none = 0,
36 e1000_mng_mode_host_if_only
39 #define E1000_FACTPS_MNGCG 0x20000000
41 /* Intel(R) Active Management Technology signature */
42 #define E1000_IAMT_SIGNATURE 0x544D4149
45 * e1000e_get_bus_info_pcie - Get PCIe bus information
46 * @hw: pointer to the HW structure
48 * Determines and stores the system bus information for a particular
49 * network interface. The following bus information is determined and stored:
50 * bus speed, bus width, type (PCIe), and PCIe function.
52 s32 e1000e_get_bus_info_pcie(struct e1000_hw *hw)
54 struct e1000_bus_info *bus = &hw->bus;
55 struct e1000_adapter *adapter = hw->adapter;
57 u16 pcie_link_status, pci_header_type, cap_offset;
59 cap_offset = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP);
61 bus->width = e1000_bus_width_unknown;
63 pci_read_config_word(adapter->pdev,
64 cap_offset + PCIE_LINK_STATUS,
66 bus->width = (enum e1000_bus_width)((pcie_link_status &
67 PCIE_LINK_WIDTH_MASK) >>
68 PCIE_LINK_WIDTH_SHIFT);
71 pci_read_config_word(adapter->pdev, PCI_HEADER_TYPE_REGISTER,
73 if (pci_header_type & PCI_HEADER_TYPE_MULTIFUNC) {
74 status = er32(STATUS);
75 bus->func = (status & E1000_STATUS_FUNC_MASK)
76 >> E1000_STATUS_FUNC_SHIFT;
85 * e1000_clear_vfta_generic - Clear VLAN filter table
86 * @hw: pointer to the HW structure
88 * Clears the register array which contains the VLAN filter table by
89 * setting all the values to 0.
91 void e1000_clear_vfta_generic(struct e1000_hw *hw)
95 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
96 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0);
102 * e1000_write_vfta_generic - Write value to VLAN filter table
103 * @hw: pointer to the HW structure
104 * @offset: register offset in VLAN filter table
105 * @value: register value written to VLAN filter table
107 * Writes value at the given offset in the register array which stores
108 * the VLAN filter table.
110 void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value)
112 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value);
117 * e1000e_init_rx_addrs - Initialize receive address's
118 * @hw: pointer to the HW structure
119 * @rar_count: receive address registers
121 * Setups the receive address registers by setting the base receive address
122 * register to the devices MAC address and clearing all the other receive
123 * address registers to 0.
125 void e1000e_init_rx_addrs(struct e1000_hw *hw, u16 rar_count)
129 /* Setup the receive address */
130 e_dbg("Programming MAC Address into RAR[0]\n");
132 e1000e_rar_set(hw, hw->mac.addr, 0);
134 /* Zero out the other (rar_entry_count - 1) receive addresses */
135 e_dbg("Clearing RAR[1-%u]\n", rar_count-1);
136 for (i = 1; i < rar_count; i++) {
137 E1000_WRITE_REG_ARRAY(hw, E1000_RA, (i << 1), 0);
139 E1000_WRITE_REG_ARRAY(hw, E1000_RA, ((i << 1) + 1), 0);
145 * e1000e_rar_set - Set receive address register
146 * @hw: pointer to the HW structure
147 * @addr: pointer to the receive address
148 * @index: receive address array register
150 * Sets the receive address array register at index to the address passed
153 void e1000e_rar_set(struct e1000_hw *hw, u8 *addr, u32 index)
155 u32 rar_low, rar_high;
158 * HW expects these in little endian so we reverse the byte order
159 * from network order (big endian) to little endian
161 rar_low = ((u32) addr[0] |
162 ((u32) addr[1] << 8) |
163 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
165 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
167 rar_high |= E1000_RAH_AV;
169 E1000_WRITE_REG_ARRAY(hw, E1000_RA, (index << 1), rar_low);
170 E1000_WRITE_REG_ARRAY(hw, E1000_RA, ((index << 1) + 1), rar_high);
174 * e1000_hash_mc_addr - Generate a multicast hash value
175 * @hw: pointer to the HW structure
176 * @mc_addr: pointer to a multicast address
178 * Generates a multicast address hash value which is used to determine
179 * the multicast filter table array address and new table value. See
180 * e1000_mta_set_generic()
182 static u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr)
184 u32 hash_value, hash_mask;
187 /* Register count multiplied by bits per register */
188 hash_mask = (hw->mac.mta_reg_count * 32) - 1;
191 * For a mc_filter_type of 0, bit_shift is the number of left-shifts
192 * where 0xFF would still fall within the hash mask.
194 while (hash_mask >> bit_shift != 0xFF)
198 * The portion of the address that is used for the hash table
199 * is determined by the mc_filter_type setting.
200 * The algorithm is such that there is a total of 8 bits of shifting.
201 * The bit_shift for a mc_filter_type of 0 represents the number of
202 * left-shifts where the MSB of mc_addr[5] would still fall within
203 * the hash_mask. Case 0 does this exactly. Since there are a total
204 * of 8 bits of shifting, then mc_addr[4] will shift right the
205 * remaining number of bits. Thus 8 - bit_shift. The rest of the
206 * cases are a variation of this algorithm...essentially raising the
207 * number of bits to shift mc_addr[5] left, while still keeping the
208 * 8-bit shifting total.
210 * For example, given the following Destination MAC Address and an
211 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask),
212 * we can see that the bit_shift for case 0 is 4. These are the hash
213 * values resulting from each mc_filter_type...
214 * [0] [1] [2] [3] [4] [5]
218 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563
219 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6
220 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163
221 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634
223 switch (hw->mac.mc_filter_type) {
238 hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) |
239 (((u16) mc_addr[5]) << bit_shift)));
245 * e1000e_update_mc_addr_list_generic - Update Multicast addresses
246 * @hw: pointer to the HW structure
247 * @mc_addr_list: array of multicast addresses to program
248 * @mc_addr_count: number of multicast addresses to program
249 * @rar_used_count: the first RAR register free to program
250 * @rar_count: total number of supported Receive Address Registers
252 * Updates the Receive Address Registers and Multicast Table Array.
253 * The caller must have a packed mc_addr_list of multicast addresses.
254 * The parameter rar_count will usually be hw->mac.rar_entry_count
255 * unless there are workarounds that change this.
257 void e1000e_update_mc_addr_list_generic(struct e1000_hw *hw,
258 u8 *mc_addr_list, u32 mc_addr_count,
259 u32 rar_used_count, u32 rar_count)
262 u32 *mcarray = kzalloc(hw->mac.mta_reg_count * sizeof(u32), GFP_ATOMIC);
265 printk(KERN_ERR "multicast array memory allocation failed\n");
270 * Load the first set of multicast addresses into the exact
271 * filters (RAR). If there are not enough to fill the RAR
272 * array, clear the filters.
274 for (i = rar_used_count; i < rar_count; i++) {
276 e1000e_rar_set(hw, mc_addr_list, i);
278 mc_addr_list += ETH_ALEN;
280 E1000_WRITE_REG_ARRAY(hw, E1000_RA, i << 1, 0);
282 E1000_WRITE_REG_ARRAY(hw, E1000_RA, (i << 1) + 1, 0);
287 /* Load any remaining multicast addresses into the hash table. */
288 for (; mc_addr_count > 0; mc_addr_count--) {
289 u32 hash_value, hash_reg, hash_bit, mta;
290 hash_value = e1000_hash_mc_addr(hw, mc_addr_list);
291 e_dbg("Hash value = 0x%03X\n", hash_value);
292 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1);
293 hash_bit = hash_value & 0x1F;
294 mta = (1 << hash_bit);
295 mcarray[hash_reg] |= mta;
296 mc_addr_list += ETH_ALEN;
299 /* write the hash table completely */
300 for (i = 0; i < hw->mac.mta_reg_count; i++)
301 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, mcarray[i]);
308 * e1000e_clear_hw_cntrs_base - Clear base hardware counters
309 * @hw: pointer to the HW structure
311 * Clears the base hardware counters by reading the counter registers.
313 void e1000e_clear_hw_cntrs_base(struct e1000_hw *hw)
355 * e1000e_check_for_copper_link - Check for link (Copper)
356 * @hw: pointer to the HW structure
358 * Checks to see of the link status of the hardware has changed. If a
359 * change in link status has been detected, then we read the PHY registers
360 * to get the current speed/duplex if link exists.
362 s32 e1000e_check_for_copper_link(struct e1000_hw *hw)
364 struct e1000_mac_info *mac = &hw->mac;
369 * We only want to go out to the PHY registers to see if Auto-Neg
370 * has completed and/or if our link status has changed. The
371 * get_link_status flag is set upon receiving a Link Status
372 * Change or Rx Sequence Error interrupt.
374 if (!mac->get_link_status)
378 * First we want to see if the MII Status Register reports
379 * link. If so, then we want to get the current speed/duplex
382 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
387 return ret_val; /* No link detected */
389 mac->get_link_status = false;
392 * Check if there was DownShift, must be checked
393 * immediately after link-up
395 e1000e_check_downshift(hw);
398 * If we are forcing speed/duplex, then we simply return since
399 * we have already determined whether we have link or not.
402 ret_val = -E1000_ERR_CONFIG;
407 * Auto-Neg is enabled. Auto Speed Detection takes care
408 * of MAC speed/duplex configuration. So we only need to
409 * configure Collision Distance in the MAC.
411 e1000e_config_collision_dist(hw);
414 * Configure Flow Control now that Auto-Neg has completed.
415 * First, we need to restore the desired flow control
416 * settings because we may have had to re-autoneg with a
417 * different link partner.
419 ret_val = e1000e_config_fc_after_link_up(hw);
421 e_dbg("Error configuring flow control\n");
428 * e1000e_check_for_fiber_link - Check for link (Fiber)
429 * @hw: pointer to the HW structure
431 * Checks for link up on the hardware. If link is not up and we have
432 * a signal, then we need to force link up.
434 s32 e1000e_check_for_fiber_link(struct e1000_hw *hw)
436 struct e1000_mac_info *mac = &hw->mac;
443 status = er32(STATUS);
447 * If we don't have link (auto-negotiation failed or link partner
448 * cannot auto-negotiate), the cable is plugged in (we have signal),
449 * and our link partner is not trying to auto-negotiate with us (we
450 * are receiving idles or data), we need to force link up. We also
451 * need to give auto-negotiation time to complete, in case the cable
452 * was just plugged in. The autoneg_failed flag does this.
454 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
455 if ((ctrl & E1000_CTRL_SWDPIN1) && (!(status & E1000_STATUS_LU)) &&
456 (!(rxcw & E1000_RXCW_C))) {
457 if (mac->autoneg_failed == 0) {
458 mac->autoneg_failed = 1;
461 e_dbg("NOT RXing /C/, disable AutoNeg and force link.\n");
463 /* Disable auto-negotiation in the TXCW register */
464 ew32(TXCW, (mac->txcw & ~E1000_TXCW_ANE));
466 /* Force link-up and also force full-duplex. */
468 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
471 /* Configure Flow Control after forcing link up. */
472 ret_val = e1000e_config_fc_after_link_up(hw);
474 e_dbg("Error configuring flow control\n");
477 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
479 * If we are forcing link and we are receiving /C/ ordered
480 * sets, re-enable auto-negotiation in the TXCW register
481 * and disable forced link in the Device Control register
482 * in an attempt to auto-negotiate with our link partner.
484 e_dbg("RXing /C/, enable AutoNeg and stop forcing link.\n");
485 ew32(TXCW, mac->txcw);
486 ew32(CTRL, (ctrl & ~E1000_CTRL_SLU));
488 mac->serdes_has_link = true;
495 * e1000e_check_for_serdes_link - Check for link (Serdes)
496 * @hw: pointer to the HW structure
498 * Checks for link up on the hardware. If link is not up and we have
499 * a signal, then we need to force link up.
501 s32 e1000e_check_for_serdes_link(struct e1000_hw *hw)
503 struct e1000_mac_info *mac = &hw->mac;
510 status = er32(STATUS);
514 * If we don't have link (auto-negotiation failed or link partner
515 * cannot auto-negotiate), and our link partner is not trying to
516 * auto-negotiate with us (we are receiving idles or data),
517 * we need to force link up. We also need to give auto-negotiation
520 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
521 if ((!(status & E1000_STATUS_LU)) && (!(rxcw & E1000_RXCW_C))) {
522 if (mac->autoneg_failed == 0) {
523 mac->autoneg_failed = 1;
526 e_dbg("NOT RXing /C/, disable AutoNeg and force link.\n");
528 /* Disable auto-negotiation in the TXCW register */
529 ew32(TXCW, (mac->txcw & ~E1000_TXCW_ANE));
531 /* Force link-up and also force full-duplex. */
533 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
536 /* Configure Flow Control after forcing link up. */
537 ret_val = e1000e_config_fc_after_link_up(hw);
539 e_dbg("Error configuring flow control\n");
542 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
544 * If we are forcing link and we are receiving /C/ ordered
545 * sets, re-enable auto-negotiation in the TXCW register
546 * and disable forced link in the Device Control register
547 * in an attempt to auto-negotiate with our link partner.
549 e_dbg("RXing /C/, enable AutoNeg and stop forcing link.\n");
550 ew32(TXCW, mac->txcw);
551 ew32(CTRL, (ctrl & ~E1000_CTRL_SLU));
553 mac->serdes_has_link = true;
554 } else if (!(E1000_TXCW_ANE & er32(TXCW))) {
556 * If we force link for non-auto-negotiation switch, check
557 * link status based on MAC synchronization for internal
560 /* SYNCH bit and IV bit are sticky. */
563 if (rxcw & E1000_RXCW_SYNCH) {
564 if (!(rxcw & E1000_RXCW_IV)) {
565 mac->serdes_has_link = true;
566 e_dbg("SERDES: Link up - forced.\n");
569 mac->serdes_has_link = false;
570 e_dbg("SERDES: Link down - force failed.\n");
574 if (E1000_TXCW_ANE & er32(TXCW)) {
575 status = er32(STATUS);
576 if (status & E1000_STATUS_LU) {
577 /* SYNCH bit and IV bit are sticky, so reread rxcw. */
580 if (rxcw & E1000_RXCW_SYNCH) {
581 if (!(rxcw & E1000_RXCW_IV)) {
582 mac->serdes_has_link = true;
583 e_dbg("SERDES: Link up - autoneg "
584 "completed sucessfully.\n");
586 mac->serdes_has_link = false;
587 e_dbg("SERDES: Link down - invalid"
588 "codewords detected in autoneg.\n");
591 mac->serdes_has_link = false;
592 e_dbg("SERDES: Link down - no sync.\n");
595 mac->serdes_has_link = false;
596 e_dbg("SERDES: Link down - autoneg failed\n");
604 * e1000_set_default_fc_generic - Set flow control default values
605 * @hw: pointer to the HW structure
607 * Read the EEPROM for the default values for flow control and store the
610 static s32 e1000_set_default_fc_generic(struct e1000_hw *hw)
616 * Read and store word 0x0F of the EEPROM. This word contains bits
617 * that determine the hardware's default PAUSE (flow control) mode,
618 * a bit that determines whether the HW defaults to enabling or
619 * disabling auto-negotiation, and the direction of the
620 * SW defined pins. If there is no SW over-ride of the flow
621 * control setting, then the variable hw->fc will
622 * be initialized based on a value in the EEPROM.
624 ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &nvm_data);
627 e_dbg("NVM Read Error\n");
631 if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 0)
632 hw->fc.requested_mode = e1000_fc_none;
633 else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) ==
635 hw->fc.requested_mode = e1000_fc_tx_pause;
637 hw->fc.requested_mode = e1000_fc_full;
643 * e1000e_setup_link - Setup flow control and link settings
644 * @hw: pointer to the HW structure
646 * Determines which flow control settings to use, then configures flow
647 * control. Calls the appropriate media-specific link configuration
648 * function. Assuming the adapter has a valid link partner, a valid link
649 * should be established. Assumes the hardware has previously been reset
650 * and the transmitter and receiver are not enabled.
652 s32 e1000e_setup_link(struct e1000_hw *hw)
654 struct e1000_mac_info *mac = &hw->mac;
658 * In the case of the phy reset being blocked, we already have a link.
659 * We do not need to set it up again.
661 if (e1000_check_reset_block(hw))
665 * If requested flow control is set to default, set flow control
666 * based on the EEPROM flow control settings.
668 if (hw->fc.requested_mode == e1000_fc_default) {
669 ret_val = e1000_set_default_fc_generic(hw);
675 * Save off the requested flow control mode for use later. Depending
676 * on the link partner's capabilities, we may or may not use this mode.
678 hw->fc.current_mode = hw->fc.requested_mode;
680 e_dbg("After fix-ups FlowControl is now = %x\n",
681 hw->fc.current_mode);
683 /* Call the necessary media_type subroutine to configure the link. */
684 ret_val = mac->ops.setup_physical_interface(hw);
689 * Initialize the flow control address, type, and PAUSE timer
690 * registers to their default values. This is done even if flow
691 * control is disabled, because it does not hurt anything to
692 * initialize these registers.
694 e_dbg("Initializing the Flow Control address, type and timer regs\n");
695 ew32(FCT, FLOW_CONTROL_TYPE);
696 ew32(FCAH, FLOW_CONTROL_ADDRESS_HIGH);
697 ew32(FCAL, FLOW_CONTROL_ADDRESS_LOW);
699 ew32(FCTTV, hw->fc.pause_time);
701 return e1000e_set_fc_watermarks(hw);
705 * e1000_commit_fc_settings_generic - Configure flow control
706 * @hw: pointer to the HW structure
708 * Write the flow control settings to the Transmit Config Word Register (TXCW)
709 * base on the flow control settings in e1000_mac_info.
711 static s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw)
713 struct e1000_mac_info *mac = &hw->mac;
717 * Check for a software override of the flow control settings, and
718 * setup the device accordingly. If auto-negotiation is enabled, then
719 * software will have to set the "PAUSE" bits to the correct value in
720 * the Transmit Config Word Register (TXCW) and re-start auto-
721 * negotiation. However, if auto-negotiation is disabled, then
722 * software will have to manually configure the two flow control enable
723 * bits in the CTRL register.
725 * The possible values of the "fc" parameter are:
726 * 0: Flow control is completely disabled
727 * 1: Rx flow control is enabled (we can receive pause frames,
728 * but not send pause frames).
729 * 2: Tx flow control is enabled (we can send pause frames but we
730 * do not support receiving pause frames).
731 * 3: Both Rx and Tx flow control (symmetric) are enabled.
733 switch (hw->fc.current_mode) {
735 /* Flow control completely disabled by a software over-ride. */
736 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
738 case e1000_fc_rx_pause:
740 * Rx Flow control is enabled and Tx Flow control is disabled
741 * by a software over-ride. Since there really isn't a way to
742 * advertise that we are capable of Rx Pause ONLY, we will
743 * advertise that we support both symmetric and asymmetric Rx
744 * PAUSE. Later, we will disable the adapter's ability to send
747 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
749 case e1000_fc_tx_pause:
751 * Tx Flow control is enabled, and Rx Flow control is disabled,
752 * by a software over-ride.
754 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
758 * Flow control (both Rx and Tx) is enabled by a software
761 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
764 e_dbg("Flow control param set incorrectly\n");
765 return -E1000_ERR_CONFIG;
776 * e1000_poll_fiber_serdes_link_generic - Poll for link up
777 * @hw: pointer to the HW structure
779 * Polls for link up by reading the status register, if link fails to come
780 * up with auto-negotiation, then the link is forced if a signal is detected.
782 static s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw)
784 struct e1000_mac_info *mac = &hw->mac;
789 * If we have a signal (the cable is plugged in, or assumed true for
790 * serdes media) then poll for a "Link-Up" indication in the Device
791 * Status Register. Time-out if a link isn't seen in 500 milliseconds
792 * seconds (Auto-negotiation should complete in less than 500
793 * milliseconds even if the other end is doing it in SW).
795 for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) {
797 status = er32(STATUS);
798 if (status & E1000_STATUS_LU)
801 if (i == FIBER_LINK_UP_LIMIT) {
802 e_dbg("Never got a valid link from auto-neg!!!\n");
803 mac->autoneg_failed = 1;
805 * AutoNeg failed to achieve a link, so we'll call
806 * mac->check_for_link. This routine will force the
807 * link up if we detect a signal. This will allow us to
808 * communicate with non-autonegotiating link partners.
810 ret_val = mac->ops.check_for_link(hw);
812 e_dbg("Error while checking for link\n");
815 mac->autoneg_failed = 0;
817 mac->autoneg_failed = 0;
818 e_dbg("Valid Link Found\n");
825 * e1000e_setup_fiber_serdes_link - Setup link for fiber/serdes
826 * @hw: pointer to the HW structure
828 * Configures collision distance and flow control for fiber and serdes
829 * links. Upon successful setup, poll for link.
831 s32 e1000e_setup_fiber_serdes_link(struct e1000_hw *hw)
838 /* Take the link out of reset */
839 ctrl &= ~E1000_CTRL_LRST;
841 e1000e_config_collision_dist(hw);
843 ret_val = e1000_commit_fc_settings_generic(hw);
848 * Since auto-negotiation is enabled, take the link out of reset (the
849 * link will be in reset, because we previously reset the chip). This
850 * will restart auto-negotiation. If auto-negotiation is successful
851 * then the link-up status bit will be set and the flow control enable
852 * bits (RFCE and TFCE) will be set according to their negotiated value.
854 e_dbg("Auto-negotiation enabled\n");
861 * For these adapters, the SW definable pin 1 is set when the optics
862 * detect a signal. If we have a signal, then poll for a "Link-Up"
865 if (hw->phy.media_type == e1000_media_type_internal_serdes ||
866 (er32(CTRL) & E1000_CTRL_SWDPIN1)) {
867 ret_val = e1000_poll_fiber_serdes_link_generic(hw);
869 e_dbg("No signal detected\n");
876 * e1000e_config_collision_dist - Configure collision distance
877 * @hw: pointer to the HW structure
879 * Configures the collision distance to the default value and is used
880 * during link setup. Currently no func pointer exists and all
881 * implementations are handled in the generic version of this function.
883 void e1000e_config_collision_dist(struct e1000_hw *hw)
889 tctl &= ~E1000_TCTL_COLD;
890 tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT;
897 * e1000e_set_fc_watermarks - Set flow control high/low watermarks
898 * @hw: pointer to the HW structure
900 * Sets the flow control high/low threshold (watermark) registers. If
901 * flow control XON frame transmission is enabled, then set XON frame
902 * transmission as well.
904 s32 e1000e_set_fc_watermarks(struct e1000_hw *hw)
906 u32 fcrtl = 0, fcrth = 0;
909 * Set the flow control receive threshold registers. Normally,
910 * these registers will be set to a default threshold that may be
911 * adjusted later by the driver's runtime code. However, if the
912 * ability to transmit pause frames is not enabled, then these
913 * registers will be set to 0.
915 if (hw->fc.current_mode & e1000_fc_tx_pause) {
917 * We need to set up the Receive Threshold high and low water
918 * marks as well as (optionally) enabling the transmission of
921 fcrtl = hw->fc.low_water;
922 fcrtl |= E1000_FCRTL_XONE;
923 fcrth = hw->fc.high_water;
932 * e1000e_force_mac_fc - Force the MAC's flow control settings
933 * @hw: pointer to the HW structure
935 * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the
936 * device control register to reflect the adapter settings. TFCE and RFCE
937 * need to be explicitly set by software when a copper PHY is used because
938 * autonegotiation is managed by the PHY rather than the MAC. Software must
939 * also configure these bits when link is forced on a fiber connection.
941 s32 e1000e_force_mac_fc(struct e1000_hw *hw)
948 * Because we didn't get link via the internal auto-negotiation
949 * mechanism (we either forced link or we got link via PHY
950 * auto-neg), we have to manually enable/disable transmit an
951 * receive flow control.
953 * The "Case" statement below enables/disable flow control
954 * according to the "hw->fc.current_mode" parameter.
956 * The possible values of the "fc" parameter are:
957 * 0: Flow control is completely disabled
958 * 1: Rx flow control is enabled (we can receive pause
959 * frames but not send pause frames).
960 * 2: Tx flow control is enabled (we can send pause frames
961 * frames but we do not receive pause frames).
962 * 3: Both Rx and Tx flow control (symmetric) is enabled.
963 * other: No other values should be possible at this point.
965 e_dbg("hw->fc.current_mode = %u\n", hw->fc.current_mode);
967 switch (hw->fc.current_mode) {
969 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
971 case e1000_fc_rx_pause:
972 ctrl &= (~E1000_CTRL_TFCE);
973 ctrl |= E1000_CTRL_RFCE;
975 case e1000_fc_tx_pause:
976 ctrl &= (~E1000_CTRL_RFCE);
977 ctrl |= E1000_CTRL_TFCE;
980 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
983 e_dbg("Flow control param set incorrectly\n");
984 return -E1000_ERR_CONFIG;
993 * e1000e_config_fc_after_link_up - Configures flow control after link
994 * @hw: pointer to the HW structure
996 * Checks the status of auto-negotiation after link up to ensure that the
997 * speed and duplex were not forced. If the link needed to be forced, then
998 * flow control needs to be forced also. If auto-negotiation is enabled
999 * and did not fail, then we configure flow control based on our link
1002 s32 e1000e_config_fc_after_link_up(struct e1000_hw *hw)
1004 struct e1000_mac_info *mac = &hw->mac;
1006 u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg;
1010 * Check for the case where we have fiber media and auto-neg failed
1011 * so we had to force link. In this case, we need to force the
1012 * configuration of the MAC to match the "fc" parameter.
1014 if (mac->autoneg_failed) {
1015 if (hw->phy.media_type == e1000_media_type_fiber ||
1016 hw->phy.media_type == e1000_media_type_internal_serdes)
1017 ret_val = e1000e_force_mac_fc(hw);
1019 if (hw->phy.media_type == e1000_media_type_copper)
1020 ret_val = e1000e_force_mac_fc(hw);
1024 e_dbg("Error forcing flow control settings\n");
1029 * Check for the case where we have copper media and auto-neg is
1030 * enabled. In this case, we need to check and see if Auto-Neg
1031 * has completed, and if so, how the PHY and link partner has
1032 * flow control configured.
1034 if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) {
1036 * Read the MII Status Register and check to see if AutoNeg
1037 * has completed. We read this twice because this reg has
1038 * some "sticky" (latched) bits.
1040 ret_val = e1e_rphy(hw, PHY_STATUS, &mii_status_reg);
1043 ret_val = e1e_rphy(hw, PHY_STATUS, &mii_status_reg);
1047 if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) {
1048 e_dbg("Copper PHY and Auto Neg "
1049 "has not completed.\n");
1054 * The AutoNeg process has completed, so we now need to
1055 * read both the Auto Negotiation Advertisement
1056 * Register (Address 4) and the Auto_Negotiation Base
1057 * Page Ability Register (Address 5) to determine how
1058 * flow control was negotiated.
1060 ret_val = e1e_rphy(hw, PHY_AUTONEG_ADV, &mii_nway_adv_reg);
1063 ret_val = e1e_rphy(hw, PHY_LP_ABILITY, &mii_nway_lp_ability_reg);
1068 * Two bits in the Auto Negotiation Advertisement Register
1069 * (Address 4) and two bits in the Auto Negotiation Base
1070 * Page Ability Register (Address 5) determine flow control
1071 * for both the PHY and the link partner. The following
1072 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
1073 * 1999, describes these PAUSE resolution bits and how flow
1074 * control is determined based upon these settings.
1075 * NOTE: DC = Don't Care
1077 * LOCAL DEVICE | LINK PARTNER
1078 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
1079 *-------|---------|-------|---------|--------------------
1080 * 0 | 0 | DC | DC | e1000_fc_none
1081 * 0 | 1 | 0 | DC | e1000_fc_none
1082 * 0 | 1 | 1 | 0 | e1000_fc_none
1083 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1084 * 1 | 0 | 0 | DC | e1000_fc_none
1085 * 1 | DC | 1 | DC | e1000_fc_full
1086 * 1 | 1 | 0 | 0 | e1000_fc_none
1087 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1089 * Are both PAUSE bits set to 1? If so, this implies
1090 * Symmetric Flow Control is enabled at both ends. The
1091 * ASM_DIR bits are irrelevant per the spec.
1093 * For Symmetric Flow Control:
1095 * LOCAL DEVICE | LINK PARTNER
1096 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1097 *-------|---------|-------|---------|--------------------
1098 * 1 | DC | 1 | DC | E1000_fc_full
1101 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1102 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
1104 * Now we need to check if the user selected Rx ONLY
1105 * of pause frames. In this case, we had to advertise
1106 * FULL flow control because we could not advertise Rx
1107 * ONLY. Hence, we must now check to see if we need to
1108 * turn OFF the TRANSMISSION of PAUSE frames.
1110 if (hw->fc.requested_mode == e1000_fc_full) {
1111 hw->fc.current_mode = e1000_fc_full;
1112 e_dbg("Flow Control = FULL.\r\n");
1114 hw->fc.current_mode = e1000_fc_rx_pause;
1115 e_dbg("Flow Control = "
1116 "RX PAUSE frames only.\r\n");
1120 * For receiving PAUSE frames ONLY.
1122 * LOCAL DEVICE | LINK PARTNER
1123 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1124 *-------|---------|-------|---------|--------------------
1125 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1127 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1128 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1129 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1130 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1131 hw->fc.current_mode = e1000_fc_tx_pause;
1132 e_dbg("Flow Control = Tx PAUSE frames only.\r\n");
1135 * For transmitting PAUSE frames ONLY.
1137 * LOCAL DEVICE | LINK PARTNER
1138 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1139 *-------|---------|-------|---------|--------------------
1140 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1142 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1143 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1144 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1145 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1146 hw->fc.current_mode = e1000_fc_rx_pause;
1147 e_dbg("Flow Control = Rx PAUSE frames only.\r\n");
1150 * Per the IEEE spec, at this point flow control
1151 * should be disabled.
1153 hw->fc.current_mode = e1000_fc_none;
1154 e_dbg("Flow Control = NONE.\r\n");
1158 * Now we need to do one last check... If we auto-
1159 * negotiated to HALF DUPLEX, flow control should not be
1160 * enabled per IEEE 802.3 spec.
1162 ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex);
1164 e_dbg("Error getting link speed and duplex\n");
1168 if (duplex == HALF_DUPLEX)
1169 hw->fc.current_mode = e1000_fc_none;
1172 * Now we call a subroutine to actually force the MAC
1173 * controller to use the correct flow control settings.
1175 ret_val = e1000e_force_mac_fc(hw);
1177 e_dbg("Error forcing flow control settings\n");
1186 * e1000e_get_speed_and_duplex_copper - Retrieve current speed/duplex
1187 * @hw: pointer to the HW structure
1188 * @speed: stores the current speed
1189 * @duplex: stores the current duplex
1191 * Read the status register for the current speed/duplex and store the current
1192 * speed and duplex for copper connections.
1194 s32 e1000e_get_speed_and_duplex_copper(struct e1000_hw *hw, u16 *speed, u16 *duplex)
1198 status = er32(STATUS);
1199 if (status & E1000_STATUS_SPEED_1000) {
1200 *speed = SPEED_1000;
1201 e_dbg("1000 Mbs, ");
1202 } else if (status & E1000_STATUS_SPEED_100) {
1210 if (status & E1000_STATUS_FD) {
1211 *duplex = FULL_DUPLEX;
1212 e_dbg("Full Duplex\n");
1214 *duplex = HALF_DUPLEX;
1215 e_dbg("Half Duplex\n");
1222 * e1000e_get_speed_and_duplex_fiber_serdes - Retrieve current speed/duplex
1223 * @hw: pointer to the HW structure
1224 * @speed: stores the current speed
1225 * @duplex: stores the current duplex
1227 * Sets the speed and duplex to gigabit full duplex (the only possible option)
1228 * for fiber/serdes links.
1230 s32 e1000e_get_speed_and_duplex_fiber_serdes(struct e1000_hw *hw, u16 *speed, u16 *duplex)
1232 *speed = SPEED_1000;
1233 *duplex = FULL_DUPLEX;
1239 * e1000e_get_hw_semaphore - Acquire hardware semaphore
1240 * @hw: pointer to the HW structure
1242 * Acquire the HW semaphore to access the PHY or NVM
1244 s32 e1000e_get_hw_semaphore(struct e1000_hw *hw)
1247 s32 timeout = hw->nvm.word_size + 1;
1250 /* Get the SW semaphore */
1251 while (i < timeout) {
1253 if (!(swsm & E1000_SWSM_SMBI))
1261 e_dbg("Driver can't access device - SMBI bit is set.\n");
1262 return -E1000_ERR_NVM;
1265 /* Get the FW semaphore. */
1266 for (i = 0; i < timeout; i++) {
1268 ew32(SWSM, swsm | E1000_SWSM_SWESMBI);
1270 /* Semaphore acquired if bit latched */
1271 if (er32(SWSM) & E1000_SWSM_SWESMBI)
1278 /* Release semaphores */
1279 e1000e_put_hw_semaphore(hw);
1280 e_dbg("Driver can't access the NVM\n");
1281 return -E1000_ERR_NVM;
1288 * e1000e_put_hw_semaphore - Release hardware semaphore
1289 * @hw: pointer to the HW structure
1291 * Release hardware semaphore used to access the PHY or NVM
1293 void e1000e_put_hw_semaphore(struct e1000_hw *hw)
1298 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
1303 * e1000e_get_auto_rd_done - Check for auto read completion
1304 * @hw: pointer to the HW structure
1306 * Check EEPROM for Auto Read done bit.
1308 s32 e1000e_get_auto_rd_done(struct e1000_hw *hw)
1312 while (i < AUTO_READ_DONE_TIMEOUT) {
1313 if (er32(EECD) & E1000_EECD_AUTO_RD)
1319 if (i == AUTO_READ_DONE_TIMEOUT) {
1320 e_dbg("Auto read by HW from NVM has not completed.\n");
1321 return -E1000_ERR_RESET;
1328 * e1000e_valid_led_default - Verify a valid default LED config
1329 * @hw: pointer to the HW structure
1330 * @data: pointer to the NVM (EEPROM)
1332 * Read the EEPROM for the current default LED configuration. If the
1333 * LED configuration is not valid, set to a valid LED configuration.
1335 s32 e1000e_valid_led_default(struct e1000_hw *hw, u16 *data)
1339 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
1341 e_dbg("NVM Read Error\n");
1345 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
1346 *data = ID_LED_DEFAULT;
1352 * e1000e_id_led_init -
1353 * @hw: pointer to the HW structure
1356 s32 e1000e_id_led_init(struct e1000_hw *hw)
1358 struct e1000_mac_info *mac = &hw->mac;
1360 const u32 ledctl_mask = 0x000000FF;
1361 const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON;
1362 const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
1364 const u16 led_mask = 0x0F;
1366 ret_val = hw->nvm.ops.valid_led_default(hw, &data);
1370 mac->ledctl_default = er32(LEDCTL);
1371 mac->ledctl_mode1 = mac->ledctl_default;
1372 mac->ledctl_mode2 = mac->ledctl_default;
1374 for (i = 0; i < 4; i++) {
1375 temp = (data >> (i << 2)) & led_mask;
1377 case ID_LED_ON1_DEF2:
1378 case ID_LED_ON1_ON2:
1379 case ID_LED_ON1_OFF2:
1380 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
1381 mac->ledctl_mode1 |= ledctl_on << (i << 3);
1383 case ID_LED_OFF1_DEF2:
1384 case ID_LED_OFF1_ON2:
1385 case ID_LED_OFF1_OFF2:
1386 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
1387 mac->ledctl_mode1 |= ledctl_off << (i << 3);
1394 case ID_LED_DEF1_ON2:
1395 case ID_LED_ON1_ON2:
1396 case ID_LED_OFF1_ON2:
1397 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
1398 mac->ledctl_mode2 |= ledctl_on << (i << 3);
1400 case ID_LED_DEF1_OFF2:
1401 case ID_LED_ON1_OFF2:
1402 case ID_LED_OFF1_OFF2:
1403 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
1404 mac->ledctl_mode2 |= ledctl_off << (i << 3);
1416 * e1000e_setup_led_generic - Configures SW controllable LED
1417 * @hw: pointer to the HW structure
1419 * This prepares the SW controllable LED for use and saves the current state
1420 * of the LED so it can be later restored.
1422 s32 e1000e_setup_led_generic(struct e1000_hw *hw)
1426 if (hw->mac.ops.setup_led != e1000e_setup_led_generic) {
1427 return -E1000_ERR_CONFIG;
1430 if (hw->phy.media_type == e1000_media_type_fiber) {
1431 ledctl = er32(LEDCTL);
1432 hw->mac.ledctl_default = ledctl;
1434 ledctl &= ~(E1000_LEDCTL_LED0_IVRT |
1435 E1000_LEDCTL_LED0_BLINK |
1436 E1000_LEDCTL_LED0_MODE_MASK);
1437 ledctl |= (E1000_LEDCTL_MODE_LED_OFF <<
1438 E1000_LEDCTL_LED0_MODE_SHIFT);
1439 ew32(LEDCTL, ledctl);
1440 } else if (hw->phy.media_type == e1000_media_type_copper) {
1441 ew32(LEDCTL, hw->mac.ledctl_mode1);
1448 * e1000e_cleanup_led_generic - Set LED config to default operation
1449 * @hw: pointer to the HW structure
1451 * Remove the current LED configuration and set the LED configuration
1452 * to the default value, saved from the EEPROM.
1454 s32 e1000e_cleanup_led_generic(struct e1000_hw *hw)
1456 ew32(LEDCTL, hw->mac.ledctl_default);
1461 * e1000e_blink_led - Blink LED
1462 * @hw: pointer to the HW structure
1464 * Blink the LEDs which are set to be on.
1466 s32 e1000e_blink_led(struct e1000_hw *hw)
1468 u32 ledctl_blink = 0;
1471 if (hw->phy.media_type == e1000_media_type_fiber) {
1472 /* always blink LED0 for PCI-E fiber */
1473 ledctl_blink = E1000_LEDCTL_LED0_BLINK |
1474 (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT);
1477 * set the blink bit for each LED that's "on" (0x0E)
1480 ledctl_blink = hw->mac.ledctl_mode2;
1481 for (i = 0; i < 4; i++)
1482 if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) ==
1483 E1000_LEDCTL_MODE_LED_ON)
1484 ledctl_blink |= (E1000_LEDCTL_LED0_BLINK <<
1488 ew32(LEDCTL, ledctl_blink);
1494 * e1000e_led_on_generic - Turn LED on
1495 * @hw: pointer to the HW structure
1499 s32 e1000e_led_on_generic(struct e1000_hw *hw)
1503 switch (hw->phy.media_type) {
1504 case e1000_media_type_fiber:
1506 ctrl &= ~E1000_CTRL_SWDPIN0;
1507 ctrl |= E1000_CTRL_SWDPIO0;
1510 case e1000_media_type_copper:
1511 ew32(LEDCTL, hw->mac.ledctl_mode2);
1521 * e1000e_led_off_generic - Turn LED off
1522 * @hw: pointer to the HW structure
1526 s32 e1000e_led_off_generic(struct e1000_hw *hw)
1530 switch (hw->phy.media_type) {
1531 case e1000_media_type_fiber:
1533 ctrl |= E1000_CTRL_SWDPIN0;
1534 ctrl |= E1000_CTRL_SWDPIO0;
1537 case e1000_media_type_copper:
1538 ew32(LEDCTL, hw->mac.ledctl_mode1);
1548 * e1000e_set_pcie_no_snoop - Set PCI-express capabilities
1549 * @hw: pointer to the HW structure
1550 * @no_snoop: bitmap of snoop events
1552 * Set the PCI-express register to snoop for events enabled in 'no_snoop'.
1554 void e1000e_set_pcie_no_snoop(struct e1000_hw *hw, u32 no_snoop)
1560 gcr &= ~(PCIE_NO_SNOOP_ALL);
1567 * e1000e_disable_pcie_master - Disables PCI-express master access
1568 * @hw: pointer to the HW structure
1570 * Returns 0 if successful, else returns -10
1571 * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused
1572 * the master requests to be disabled.
1574 * Disables PCI-Express master access and verifies there are no pending
1577 s32 e1000e_disable_pcie_master(struct e1000_hw *hw)
1580 s32 timeout = MASTER_DISABLE_TIMEOUT;
1583 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE;
1587 if (!(er32(STATUS) &
1588 E1000_STATUS_GIO_MASTER_ENABLE))
1595 e_dbg("Master requests are pending.\n");
1596 return -E1000_ERR_MASTER_REQUESTS_PENDING;
1603 * e1000e_reset_adaptive - Reset Adaptive Interframe Spacing
1604 * @hw: pointer to the HW structure
1606 * Reset the Adaptive Interframe Spacing throttle to default values.
1608 void e1000e_reset_adaptive(struct e1000_hw *hw)
1610 struct e1000_mac_info *mac = &hw->mac;
1612 mac->current_ifs_val = 0;
1613 mac->ifs_min_val = IFS_MIN;
1614 mac->ifs_max_val = IFS_MAX;
1615 mac->ifs_step_size = IFS_STEP;
1616 mac->ifs_ratio = IFS_RATIO;
1618 mac->in_ifs_mode = false;
1623 * e1000e_update_adaptive - Update Adaptive Interframe Spacing
1624 * @hw: pointer to the HW structure
1626 * Update the Adaptive Interframe Spacing Throttle value based on the
1627 * time between transmitted packets and time between collisions.
1629 void e1000e_update_adaptive(struct e1000_hw *hw)
1631 struct e1000_mac_info *mac = &hw->mac;
1633 if ((mac->collision_delta * mac->ifs_ratio) > mac->tx_packet_delta) {
1634 if (mac->tx_packet_delta > MIN_NUM_XMITS) {
1635 mac->in_ifs_mode = true;
1636 if (mac->current_ifs_val < mac->ifs_max_val) {
1637 if (!mac->current_ifs_val)
1638 mac->current_ifs_val = mac->ifs_min_val;
1640 mac->current_ifs_val +=
1642 ew32(AIT, mac->current_ifs_val);
1646 if (mac->in_ifs_mode &&
1647 (mac->tx_packet_delta <= MIN_NUM_XMITS)) {
1648 mac->current_ifs_val = 0;
1649 mac->in_ifs_mode = false;
1656 * e1000_raise_eec_clk - Raise EEPROM clock
1657 * @hw: pointer to the HW structure
1658 * @eecd: pointer to the EEPROM
1660 * Enable/Raise the EEPROM clock bit.
1662 static void e1000_raise_eec_clk(struct e1000_hw *hw, u32 *eecd)
1664 *eecd = *eecd | E1000_EECD_SK;
1667 udelay(hw->nvm.delay_usec);
1671 * e1000_lower_eec_clk - Lower EEPROM clock
1672 * @hw: pointer to the HW structure
1673 * @eecd: pointer to the EEPROM
1675 * Clear/Lower the EEPROM clock bit.
1677 static void e1000_lower_eec_clk(struct e1000_hw *hw, u32 *eecd)
1679 *eecd = *eecd & ~E1000_EECD_SK;
1682 udelay(hw->nvm.delay_usec);
1686 * e1000_shift_out_eec_bits - Shift data bits our to the EEPROM
1687 * @hw: pointer to the HW structure
1688 * @data: data to send to the EEPROM
1689 * @count: number of bits to shift out
1691 * We need to shift 'count' bits out to the EEPROM. So, the value in the
1692 * "data" parameter will be shifted out to the EEPROM one bit at a time.
1693 * In order to do this, "data" must be broken down into bits.
1695 static void e1000_shift_out_eec_bits(struct e1000_hw *hw, u16 data, u16 count)
1697 struct e1000_nvm_info *nvm = &hw->nvm;
1698 u32 eecd = er32(EECD);
1701 mask = 0x01 << (count - 1);
1702 if (nvm->type == e1000_nvm_eeprom_spi)
1703 eecd |= E1000_EECD_DO;
1706 eecd &= ~E1000_EECD_DI;
1709 eecd |= E1000_EECD_DI;
1714 udelay(nvm->delay_usec);
1716 e1000_raise_eec_clk(hw, &eecd);
1717 e1000_lower_eec_clk(hw, &eecd);
1722 eecd &= ~E1000_EECD_DI;
1727 * e1000_shift_in_eec_bits - Shift data bits in from the EEPROM
1728 * @hw: pointer to the HW structure
1729 * @count: number of bits to shift in
1731 * In order to read a register from the EEPROM, we need to shift 'count' bits
1732 * in from the EEPROM. Bits are "shifted in" by raising the clock input to
1733 * the EEPROM (setting the SK bit), and then reading the value of the data out
1734 * "DO" bit. During this "shifting in" process the data in "DI" bit should
1737 static u16 e1000_shift_in_eec_bits(struct e1000_hw *hw, u16 count)
1745 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
1748 for (i = 0; i < count; i++) {
1750 e1000_raise_eec_clk(hw, &eecd);
1754 eecd &= ~E1000_EECD_DI;
1755 if (eecd & E1000_EECD_DO)
1758 e1000_lower_eec_clk(hw, &eecd);
1765 * e1000e_poll_eerd_eewr_done - Poll for EEPROM read/write completion
1766 * @hw: pointer to the HW structure
1767 * @ee_reg: EEPROM flag for polling
1769 * Polls the EEPROM status bit for either read or write completion based
1770 * upon the value of 'ee_reg'.
1772 s32 e1000e_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg)
1774 u32 attempts = 100000;
1777 for (i = 0; i < attempts; i++) {
1778 if (ee_reg == E1000_NVM_POLL_READ)
1783 if (reg & E1000_NVM_RW_REG_DONE)
1789 return -E1000_ERR_NVM;
1793 * e1000e_acquire_nvm - Generic request for access to EEPROM
1794 * @hw: pointer to the HW structure
1796 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
1797 * Return successful if access grant bit set, else clear the request for
1798 * EEPROM access and return -E1000_ERR_NVM (-1).
1800 s32 e1000e_acquire_nvm(struct e1000_hw *hw)
1802 u32 eecd = er32(EECD);
1803 s32 timeout = E1000_NVM_GRANT_ATTEMPTS;
1805 ew32(EECD, eecd | E1000_EECD_REQ);
1809 if (eecd & E1000_EECD_GNT)
1817 eecd &= ~E1000_EECD_REQ;
1819 e_dbg("Could not acquire NVM grant\n");
1820 return -E1000_ERR_NVM;
1827 * e1000_standby_nvm - Return EEPROM to standby state
1828 * @hw: pointer to the HW structure
1830 * Return the EEPROM to a standby state.
1832 static void e1000_standby_nvm(struct e1000_hw *hw)
1834 struct e1000_nvm_info *nvm = &hw->nvm;
1835 u32 eecd = er32(EECD);
1837 if (nvm->type == e1000_nvm_eeprom_spi) {
1838 /* Toggle CS to flush commands */
1839 eecd |= E1000_EECD_CS;
1842 udelay(nvm->delay_usec);
1843 eecd &= ~E1000_EECD_CS;
1846 udelay(nvm->delay_usec);
1851 * e1000_stop_nvm - Terminate EEPROM command
1852 * @hw: pointer to the HW structure
1854 * Terminates the current command by inverting the EEPROM's chip select pin.
1856 static void e1000_stop_nvm(struct e1000_hw *hw)
1861 if (hw->nvm.type == e1000_nvm_eeprom_spi) {
1863 eecd |= E1000_EECD_CS;
1864 e1000_lower_eec_clk(hw, &eecd);
1869 * e1000e_release_nvm - Release exclusive access to EEPROM
1870 * @hw: pointer to the HW structure
1872 * Stop any current commands to the EEPROM and clear the EEPROM request bit.
1874 void e1000e_release_nvm(struct e1000_hw *hw)
1881 eecd &= ~E1000_EECD_REQ;
1886 * e1000_ready_nvm_eeprom - Prepares EEPROM for read/write
1887 * @hw: pointer to the HW structure
1889 * Setups the EEPROM for reading and writing.
1891 static s32 e1000_ready_nvm_eeprom(struct e1000_hw *hw)
1893 struct e1000_nvm_info *nvm = &hw->nvm;
1894 u32 eecd = er32(EECD);
1898 if (nvm->type == e1000_nvm_eeprom_spi) {
1899 /* Clear SK and CS */
1900 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
1903 timeout = NVM_MAX_RETRY_SPI;
1906 * Read "Status Register" repeatedly until the LSB is cleared.
1907 * The EEPROM will signal that the command has been completed
1908 * by clearing bit 0 of the internal status register. If it's
1909 * not cleared within 'timeout', then error out.
1912 e1000_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI,
1913 hw->nvm.opcode_bits);
1914 spi_stat_reg = (u8)e1000_shift_in_eec_bits(hw, 8);
1915 if (!(spi_stat_reg & NVM_STATUS_RDY_SPI))
1919 e1000_standby_nvm(hw);
1924 e_dbg("SPI NVM Status error\n");
1925 return -E1000_ERR_NVM;
1933 * e1000e_read_nvm_eerd - Reads EEPROM using EERD register
1934 * @hw: pointer to the HW structure
1935 * @offset: offset of word in the EEPROM to read
1936 * @words: number of words to read
1937 * @data: word read from the EEPROM
1939 * Reads a 16 bit word from the EEPROM using the EERD register.
1941 s32 e1000e_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
1943 struct e1000_nvm_info *nvm = &hw->nvm;
1948 * A check for invalid values: offset too large, too many words,
1949 * too many words for the offset, and not enough words.
1951 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
1953 e_dbg("nvm parameter(s) out of bounds\n");
1954 return -E1000_ERR_NVM;
1957 for (i = 0; i < words; i++) {
1958 eerd = ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) +
1959 E1000_NVM_RW_REG_START;
1962 ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_READ);
1966 data[i] = (er32(EERD) >> E1000_NVM_RW_REG_DATA);
1973 * e1000e_write_nvm_spi - Write to EEPROM using SPI
1974 * @hw: pointer to the HW structure
1975 * @offset: offset within the EEPROM to be written to
1976 * @words: number of words to write
1977 * @data: 16 bit word(s) to be written to the EEPROM
1979 * Writes data to EEPROM at offset using SPI interface.
1981 * If e1000e_update_nvm_checksum is not called after this function , the
1982 * EEPROM will most likely contain an invalid checksum.
1984 s32 e1000e_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
1986 struct e1000_nvm_info *nvm = &hw->nvm;
1991 * A check for invalid values: offset too large, too many words,
1992 * and not enough words.
1994 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
1996 e_dbg("nvm parameter(s) out of bounds\n");
1997 return -E1000_ERR_NVM;
2000 ret_val = nvm->ops.acquire(hw);
2006 while (widx < words) {
2007 u8 write_opcode = NVM_WRITE_OPCODE_SPI;
2009 ret_val = e1000_ready_nvm_eeprom(hw);
2011 nvm->ops.release(hw);
2015 e1000_standby_nvm(hw);
2017 /* Send the WRITE ENABLE command (8 bit opcode) */
2018 e1000_shift_out_eec_bits(hw, NVM_WREN_OPCODE_SPI,
2021 e1000_standby_nvm(hw);
2024 * Some SPI eeproms use the 8th address bit embedded in the
2027 if ((nvm->address_bits == 8) && (offset >= 128))
2028 write_opcode |= NVM_A8_OPCODE_SPI;
2030 /* Send the Write command (8-bit opcode + addr) */
2031 e1000_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits);
2032 e1000_shift_out_eec_bits(hw, (u16)((offset + widx) * 2),
2035 /* Loop to allow for up to whole page write of eeprom */
2036 while (widx < words) {
2037 u16 word_out = data[widx];
2038 word_out = (word_out >> 8) | (word_out << 8);
2039 e1000_shift_out_eec_bits(hw, word_out, 16);
2042 if ((((offset + widx) * 2) % nvm->page_size) == 0) {
2043 e1000_standby_nvm(hw);
2050 nvm->ops.release(hw);
2055 * e1000e_read_mac_addr - Read device MAC address
2056 * @hw: pointer to the HW structure
2058 * Reads the device MAC address from the EEPROM and stores the value.
2059 * Since devices with two ports use the same EEPROM, we increment the
2060 * last bit in the MAC address for the second port.
2062 s32 e1000e_read_mac_addr(struct e1000_hw *hw)
2065 u16 offset, nvm_data, i;
2066 u16 mac_addr_offset = 0;
2068 if (hw->mac.type == e1000_82571) {
2069 /* Check for an alternate MAC address. An alternate MAC
2070 * address can be setup by pre-boot software and must be
2071 * treated like a permanent address and must override the
2072 * actual permanent MAC address.*/
2073 ret_val = e1000_read_nvm(hw, NVM_ALT_MAC_ADDR_PTR, 1,
2076 e_dbg("NVM Read Error\n");
2079 if (mac_addr_offset == 0xFFFF)
2080 mac_addr_offset = 0;
2082 if (mac_addr_offset) {
2083 if (hw->bus.func == E1000_FUNC_1)
2084 mac_addr_offset += ETH_ALEN/sizeof(u16);
2086 /* make sure we have a valid mac address here
2087 * before using it */
2088 ret_val = e1000_read_nvm(hw, mac_addr_offset, 1,
2091 e_dbg("NVM Read Error\n");
2094 if (nvm_data & 0x0001)
2095 mac_addr_offset = 0;
2098 if (mac_addr_offset)
2099 hw->dev_spec.e82571.alt_mac_addr_is_present = 1;
2102 for (i = 0; i < ETH_ALEN; i += 2) {
2103 offset = mac_addr_offset + (i >> 1);
2104 ret_val = e1000_read_nvm(hw, offset, 1, &nvm_data);
2106 e_dbg("NVM Read Error\n");
2109 hw->mac.perm_addr[i] = (u8)(nvm_data & 0xFF);
2110 hw->mac.perm_addr[i+1] = (u8)(nvm_data >> 8);
2113 /* Flip last bit of mac address if we're on second port */
2114 if (!mac_addr_offset && hw->bus.func == E1000_FUNC_1)
2115 hw->mac.perm_addr[5] ^= 1;
2117 for (i = 0; i < ETH_ALEN; i++)
2118 hw->mac.addr[i] = hw->mac.perm_addr[i];
2124 * e1000e_validate_nvm_checksum_generic - Validate EEPROM checksum
2125 * @hw: pointer to the HW structure
2127 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
2128 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
2130 s32 e1000e_validate_nvm_checksum_generic(struct e1000_hw *hw)
2136 for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) {
2137 ret_val = e1000_read_nvm(hw, i, 1, &nvm_data);
2139 e_dbg("NVM Read Error\n");
2142 checksum += nvm_data;
2145 if (checksum != (u16) NVM_SUM) {
2146 e_dbg("NVM Checksum Invalid\n");
2147 return -E1000_ERR_NVM;
2154 * e1000e_update_nvm_checksum_generic - Update EEPROM checksum
2155 * @hw: pointer to the HW structure
2157 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
2158 * up to the checksum. Then calculates the EEPROM checksum and writes the
2159 * value to the EEPROM.
2161 s32 e1000e_update_nvm_checksum_generic(struct e1000_hw *hw)
2167 for (i = 0; i < NVM_CHECKSUM_REG; i++) {
2168 ret_val = e1000_read_nvm(hw, i, 1, &nvm_data);
2170 e_dbg("NVM Read Error while updating checksum.\n");
2173 checksum += nvm_data;
2175 checksum = (u16) NVM_SUM - checksum;
2176 ret_val = e1000_write_nvm(hw, NVM_CHECKSUM_REG, 1, &checksum);
2178 e_dbg("NVM Write Error while updating checksum.\n");
2184 * e1000e_reload_nvm - Reloads EEPROM
2185 * @hw: pointer to the HW structure
2187 * Reloads the EEPROM by setting the "Reinitialize from EEPROM" bit in the
2188 * extended control register.
2190 void e1000e_reload_nvm(struct e1000_hw *hw)
2195 ctrl_ext = er32(CTRL_EXT);
2196 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
2197 ew32(CTRL_EXT, ctrl_ext);
2202 * e1000_calculate_checksum - Calculate checksum for buffer
2203 * @buffer: pointer to EEPROM
2204 * @length: size of EEPROM to calculate a checksum for
2206 * Calculates the checksum for some buffer on a specified length. The
2207 * checksum calculated is returned.
2209 static u8 e1000_calculate_checksum(u8 *buffer, u32 length)
2217 for (i = 0; i < length; i++)
2220 return (u8) (0 - sum);
2224 * e1000_mng_enable_host_if - Checks host interface is enabled
2225 * @hw: pointer to the HW structure
2227 * Returns E1000_success upon success, else E1000_ERR_HOST_INTERFACE_COMMAND
2229 * This function checks whether the HOST IF is enabled for command operation
2230 * and also checks whether the previous command is completed. It busy waits
2231 * in case of previous command is not completed.
2233 static s32 e1000_mng_enable_host_if(struct e1000_hw *hw)
2238 /* Check that the host interface is enabled. */
2240 if ((hicr & E1000_HICR_EN) == 0) {
2241 e_dbg("E1000_HOST_EN bit disabled.\n");
2242 return -E1000_ERR_HOST_INTERFACE_COMMAND;
2244 /* check the previous command is completed */
2245 for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) {
2247 if (!(hicr & E1000_HICR_C))
2252 if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) {
2253 e_dbg("Previous command timeout failed .\n");
2254 return -E1000_ERR_HOST_INTERFACE_COMMAND;
2261 * e1000e_check_mng_mode_generic - check management mode
2262 * @hw: pointer to the HW structure
2264 * Reads the firmware semaphore register and returns true (>0) if
2265 * manageability is enabled, else false (0).
2267 bool e1000e_check_mng_mode_generic(struct e1000_hw *hw)
2269 u32 fwsm = er32(FWSM);
2271 return (fwsm & E1000_FWSM_MODE_MASK) ==
2272 (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT);
2276 * e1000e_enable_tx_pkt_filtering - Enable packet filtering on Tx
2277 * @hw: pointer to the HW structure
2279 * Enables packet filtering on transmit packets if manageability is enabled
2280 * and host interface is enabled.
2282 bool e1000e_enable_tx_pkt_filtering(struct e1000_hw *hw)
2284 struct e1000_host_mng_dhcp_cookie *hdr = &hw->mng_cookie;
2285 u32 *buffer = (u32 *)&hw->mng_cookie;
2287 s32 ret_val, hdr_csum, csum;
2290 /* No manageability, no filtering */
2291 if (!e1000e_check_mng_mode(hw)) {
2292 hw->mac.tx_pkt_filtering = false;
2297 * If we can't read from the host interface for whatever
2298 * reason, disable filtering.
2300 ret_val = e1000_mng_enable_host_if(hw);
2302 hw->mac.tx_pkt_filtering = false;
2306 /* Read in the header. Length and offset are in dwords. */
2307 len = E1000_MNG_DHCP_COOKIE_LENGTH >> 2;
2308 offset = E1000_MNG_DHCP_COOKIE_OFFSET >> 2;
2309 for (i = 0; i < len; i++)
2310 *(buffer + i) = E1000_READ_REG_ARRAY(hw, E1000_HOST_IF, offset + i);
2311 hdr_csum = hdr->checksum;
2313 csum = e1000_calculate_checksum((u8 *)hdr,
2314 E1000_MNG_DHCP_COOKIE_LENGTH);
2316 * If either the checksums or signature don't match, then
2317 * the cookie area isn't considered valid, in which case we
2318 * take the safe route of assuming Tx filtering is enabled.
2320 if ((hdr_csum != csum) || (hdr->signature != E1000_IAMT_SIGNATURE)) {
2321 hw->mac.tx_pkt_filtering = true;
2325 /* Cookie area is valid, make the final check for filtering. */
2326 if (!(hdr->status & E1000_MNG_DHCP_COOKIE_STATUS_PARSING)) {
2327 hw->mac.tx_pkt_filtering = false;
2331 hw->mac.tx_pkt_filtering = true;
2336 * e1000_mng_write_cmd_header - Writes manageability command header
2337 * @hw: pointer to the HW structure
2338 * @hdr: pointer to the host interface command header
2340 * Writes the command header after does the checksum calculation.
2342 static s32 e1000_mng_write_cmd_header(struct e1000_hw *hw,
2343 struct e1000_host_mng_command_header *hdr)
2345 u16 i, length = sizeof(struct e1000_host_mng_command_header);
2347 /* Write the whole command header structure with new checksum. */
2349 hdr->checksum = e1000_calculate_checksum((u8 *)hdr, length);
2352 /* Write the relevant command block into the ram area. */
2353 for (i = 0; i < length; i++) {
2354 E1000_WRITE_REG_ARRAY(hw, E1000_HOST_IF, i,
2355 *((u32 *) hdr + i));
2363 * e1000_mng_host_if_write - Write to the manageability host interface
2364 * @hw: pointer to the HW structure
2365 * @buffer: pointer to the host interface buffer
2366 * @length: size of the buffer
2367 * @offset: location in the buffer to write to
2368 * @sum: sum of the data (not checksum)
2370 * This function writes the buffer content at the offset given on the host if.
2371 * It also does alignment considerations to do the writes in most efficient
2372 * way. Also fills up the sum of the buffer in *buffer parameter.
2374 static s32 e1000_mng_host_if_write(struct e1000_hw *hw, u8 *buffer,
2375 u16 length, u16 offset, u8 *sum)
2378 u8 *bufptr = buffer;
2380 u16 remaining, i, j, prev_bytes;
2382 /* sum = only sum of the data and it is not checksum */
2384 if (length == 0 || offset + length > E1000_HI_MAX_MNG_DATA_LENGTH)
2385 return -E1000_ERR_PARAM;
2388 prev_bytes = offset & 0x3;
2392 data = E1000_READ_REG_ARRAY(hw, E1000_HOST_IF, offset);
2393 for (j = prev_bytes; j < sizeof(u32); j++) {
2394 *(tmp + j) = *bufptr++;
2397 E1000_WRITE_REG_ARRAY(hw, E1000_HOST_IF, offset, data);
2398 length -= j - prev_bytes;
2402 remaining = length & 0x3;
2403 length -= remaining;
2405 /* Calculate length in DWORDs */
2409 * The device driver writes the relevant command block into the
2412 for (i = 0; i < length; i++) {
2413 for (j = 0; j < sizeof(u32); j++) {
2414 *(tmp + j) = *bufptr++;
2418 E1000_WRITE_REG_ARRAY(hw, E1000_HOST_IF, offset + i, data);
2421 for (j = 0; j < sizeof(u32); j++) {
2423 *(tmp + j) = *bufptr++;
2429 E1000_WRITE_REG_ARRAY(hw, E1000_HOST_IF, offset + i, data);
2436 * e1000e_mng_write_dhcp_info - Writes DHCP info to host interface
2437 * @hw: pointer to the HW structure
2438 * @buffer: pointer to the host interface
2439 * @length: size of the buffer
2441 * Writes the DHCP information to the host interface.
2443 s32 e1000e_mng_write_dhcp_info(struct e1000_hw *hw, u8 *buffer, u16 length)
2445 struct e1000_host_mng_command_header hdr;
2449 hdr.command_id = E1000_MNG_DHCP_TX_PAYLOAD_CMD;
2450 hdr.command_length = length;
2455 /* Enable the host interface */
2456 ret_val = e1000_mng_enable_host_if(hw);
2460 /* Populate the host interface with the contents of "buffer". */
2461 ret_val = e1000_mng_host_if_write(hw, buffer, length,
2462 sizeof(hdr), &(hdr.checksum));
2466 /* Write the manageability command header */
2467 ret_val = e1000_mng_write_cmd_header(hw, &hdr);
2471 /* Tell the ARC a new command is pending. */
2473 ew32(HICR, hicr | E1000_HICR_C);
2479 * e1000e_enable_mng_pass_thru - Enable processing of ARP's
2480 * @hw: pointer to the HW structure
2482 * Verifies the hardware needs to allow ARPs to be processed by the host.
2484 bool e1000e_enable_mng_pass_thru(struct e1000_hw *hw)
2488 bool ret_val = false;
2492 if (!(manc & E1000_MANC_RCV_TCO_EN) ||
2493 !(manc & E1000_MANC_EN_MAC_ADDR_FILTER))
2496 if (hw->mac.arc_subsystem_valid) {
2498 factps = er32(FACTPS);
2500 if (!(factps & E1000_FACTPS_MNGCG) &&
2501 ((fwsm & E1000_FWSM_MODE_MASK) ==
2502 (e1000_mng_mode_pt << E1000_FWSM_MODE_SHIFT))) {
2507 if ((manc & E1000_MANC_SMBUS_EN) &&
2508 !(manc & E1000_MANC_ASF_EN)) {
2517 s32 e1000e_read_pba_num(struct e1000_hw *hw, u32 *pba_num)
2522 ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
2524 e_dbg("NVM Read Error\n");
2527 *pba_num = (u32)(nvm_data << 16);
2529 ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_1, 1, &nvm_data);
2531 e_dbg("NVM Read Error\n");
2534 *pba_num |= nvm_data;