1 /*******************************************************************************
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2009 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
30 * 82562G 10/100 Network Connection
31 * 82562G-2 10/100 Network Connection
32 * 82562GT 10/100 Network Connection
33 * 82562GT-2 10/100 Network Connection
34 * 82562V 10/100 Network Connection
35 * 82562V-2 10/100 Network Connection
36 * 82566DC-2 Gigabit Network Connection
37 * 82566DC Gigabit Network Connection
38 * 82566DM-2 Gigabit Network Connection
39 * 82566DM Gigabit Network Connection
40 * 82566MC Gigabit Network Connection
41 * 82566MM Gigabit Network Connection
42 * 82567LM Gigabit Network Connection
43 * 82567LF Gigabit Network Connection
44 * 82567V Gigabit Network Connection
45 * 82567LM-2 Gigabit Network Connection
46 * 82567LF-2 Gigabit Network Connection
47 * 82567V-2 Gigabit Network Connection
48 * 82567LF-3 Gigabit Network Connection
49 * 82567LM-3 Gigabit Network Connection
50 * 82567LM-4 Gigabit Network Connection
51 * 82577LM Gigabit Network Connection
52 * 82577LC Gigabit Network Connection
53 * 82578DM Gigabit Network Connection
54 * 82578DC Gigabit Network Connection
59 #define ICH_FLASH_GFPREG 0x0000
60 #define ICH_FLASH_HSFSTS 0x0004
61 #define ICH_FLASH_HSFCTL 0x0006
62 #define ICH_FLASH_FADDR 0x0008
63 #define ICH_FLASH_FDATA0 0x0010
64 #define ICH_FLASH_PR0 0x0074
66 #define ICH_FLASH_READ_COMMAND_TIMEOUT 500
67 #define ICH_FLASH_WRITE_COMMAND_TIMEOUT 500
68 #define ICH_FLASH_ERASE_COMMAND_TIMEOUT 3000000
69 #define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF
70 #define ICH_FLASH_CYCLE_REPEAT_COUNT 10
72 #define ICH_CYCLE_READ 0
73 #define ICH_CYCLE_WRITE 2
74 #define ICH_CYCLE_ERASE 3
76 #define FLASH_GFPREG_BASE_MASK 0x1FFF
77 #define FLASH_SECTOR_ADDR_SHIFT 12
79 #define ICH_FLASH_SEG_SIZE_256 256
80 #define ICH_FLASH_SEG_SIZE_4K 4096
81 #define ICH_FLASH_SEG_SIZE_8K 8192
82 #define ICH_FLASH_SEG_SIZE_64K 65536
85 #define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */
87 #define E1000_ICH_MNG_IAMT_MODE 0x2
89 #define ID_LED_DEFAULT_ICH8LAN ((ID_LED_DEF1_DEF2 << 12) | \
90 (ID_LED_DEF1_OFF2 << 8) | \
91 (ID_LED_DEF1_ON2 << 4) | \
94 #define E1000_ICH_NVM_SIG_WORD 0x13
95 #define E1000_ICH_NVM_SIG_MASK 0xC000
96 #define E1000_ICH_NVM_VALID_SIG_MASK 0xC0
97 #define E1000_ICH_NVM_SIG_VALUE 0x80
99 #define E1000_ICH8_LAN_INIT_TIMEOUT 1500
101 #define E1000_FEXTNVM_SW_CONFIG 1
102 #define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M :/ */
104 #define PCIE_ICH8_SNOOP_ALL PCIE_NO_SNOOP_ALL
106 #define E1000_ICH_RAR_ENTRIES 7
108 #define PHY_PAGE_SHIFT 5
109 #define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
110 ((reg) & MAX_PHY_REG_ADDRESS))
111 #define IGP3_KMRN_DIAG PHY_REG(770, 19) /* KMRN Diagnostic */
112 #define IGP3_VR_CTRL PHY_REG(776, 18) /* Voltage Regulator Control */
114 #define IGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002
115 #define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300
116 #define IGP3_VR_CTRL_MODE_SHUTDOWN 0x0200
118 #define HV_LED_CONFIG PHY_REG(768, 30) /* LED Configuration */
120 #define SW_FLAG_TIMEOUT 1000 /* SW Semaphore flag timeout in milliseconds */
122 /* SMBus Address Phy Register */
123 #define HV_SMB_ADDR PHY_REG(768, 26)
124 #define HV_SMB_ADDR_PEC_EN 0x0200
125 #define HV_SMB_ADDR_VALID 0x0080
127 /* Strapping Option Register - RO */
128 #define E1000_STRAP 0x0000C
129 #define E1000_STRAP_SMBUS_ADDRESS_MASK 0x00FE0000
130 #define E1000_STRAP_SMBUS_ADDRESS_SHIFT 17
132 /* OEM Bits Phy Register */
133 #define HV_OEM_BITS PHY_REG(768, 25)
134 #define HV_OEM_BITS_LPLU 0x0004 /* Low Power Link Up */
135 #define HV_OEM_BITS_GBE_DIS 0x0040 /* Gigabit Disable */
136 #define HV_OEM_BITS_RESTART_AN 0x0400 /* Restart Auto-negotiation */
138 #define E1000_NVM_K1_CONFIG 0x1B /* NVM K1 Config Word */
139 #define E1000_NVM_K1_ENABLE 0x1 /* NVM Enable K1 bit */
141 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
142 /* Offset 04h HSFSTS */
143 union ich8_hws_flash_status {
145 u16 flcdone :1; /* bit 0 Flash Cycle Done */
146 u16 flcerr :1; /* bit 1 Flash Cycle Error */
147 u16 dael :1; /* bit 2 Direct Access error Log */
148 u16 berasesz :2; /* bit 4:3 Sector Erase Size */
149 u16 flcinprog :1; /* bit 5 flash cycle in Progress */
150 u16 reserved1 :2; /* bit 13:6 Reserved */
151 u16 reserved2 :6; /* bit 13:6 Reserved */
152 u16 fldesvalid :1; /* bit 14 Flash Descriptor Valid */
153 u16 flockdn :1; /* bit 15 Flash Config Lock-Down */
158 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
159 /* Offset 06h FLCTL */
160 union ich8_hws_flash_ctrl {
161 struct ich8_hsflctl {
162 u16 flcgo :1; /* 0 Flash Cycle Go */
163 u16 flcycle :2; /* 2:1 Flash Cycle */
164 u16 reserved :5; /* 7:3 Reserved */
165 u16 fldbcount :2; /* 9:8 Flash Data Byte Count */
166 u16 flockdn :6; /* 15:10 Reserved */
171 /* ICH Flash Region Access Permissions */
172 union ich8_hws_flash_regacc {
174 u32 grra :8; /* 0:7 GbE region Read Access */
175 u32 grwa :8; /* 8:15 GbE region Write Access */
176 u32 gmrag :8; /* 23:16 GbE Master Read Access Grant */
177 u32 gmwag :8; /* 31:24 GbE Master Write Access Grant */
182 /* ICH Flash Protected Region */
183 union ich8_flash_protected_range {
185 u32 base:13; /* 0:12 Protected Range Base */
186 u32 reserved1:2; /* 13:14 Reserved */
187 u32 rpe:1; /* 15 Read Protection Enable */
188 u32 limit:13; /* 16:28 Protected Range Limit */
189 u32 reserved2:2; /* 29:30 Reserved */
190 u32 wpe:1; /* 31 Write Protection Enable */
195 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);
196 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
197 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
198 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
199 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
200 u32 offset, u8 byte);
201 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
203 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
205 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
207 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
208 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
209 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
210 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
211 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
212 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
213 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
214 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
215 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
216 static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
217 static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
218 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
219 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
220 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw);
221 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
223 static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
225 return readw(hw->flash_address + reg);
228 static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)
230 return readl(hw->flash_address + reg);
233 static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)
235 writew(val, hw->flash_address + reg);
238 static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)
240 writel(val, hw->flash_address + reg);
243 #define er16flash(reg) __er16flash(hw, (reg))
244 #define er32flash(reg) __er32flash(hw, (reg))
245 #define ew16flash(reg,val) __ew16flash(hw, (reg), (val))
246 #define ew32flash(reg,val) __ew32flash(hw, (reg), (val))
249 * e1000_init_phy_params_pchlan - Initialize PHY function pointers
250 * @hw: pointer to the HW structure
252 * Initialize family-specific PHY parameters and function pointers.
254 static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
256 struct e1000_phy_info *phy = &hw->phy;
260 phy->reset_delay_us = 100;
262 phy->ops.read_reg = e1000_read_phy_reg_hv;
263 phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked;
264 phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan;
265 phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan;
266 phy->ops.write_reg = e1000_write_phy_reg_hv;
267 phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked;
268 phy->ops.power_up = e1000_power_up_phy_copper;
269 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
270 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
272 phy->id = e1000_phy_unknown;
273 e1000e_get_phy_id(hw);
274 phy->type = e1000e_get_phy_type_from_id(phy->id);
277 case e1000_phy_82577:
278 phy->ops.check_polarity = e1000_check_polarity_82577;
279 phy->ops.force_speed_duplex =
280 e1000_phy_force_speed_duplex_82577;
281 phy->ops.get_cable_length = e1000_get_cable_length_82577;
282 phy->ops.get_info = e1000_get_phy_info_82577;
283 phy->ops.commit = e1000e_phy_sw_reset;
284 case e1000_phy_82578:
285 phy->ops.check_polarity = e1000_check_polarity_m88;
286 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
287 phy->ops.get_cable_length = e1000e_get_cable_length_m88;
288 phy->ops.get_info = e1000e_get_phy_info_m88;
291 ret_val = -E1000_ERR_PHY;
299 * e1000_init_phy_params_ich8lan - Initialize PHY function pointers
300 * @hw: pointer to the HW structure
302 * Initialize family-specific PHY parameters and function pointers.
304 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
306 struct e1000_phy_info *phy = &hw->phy;
311 phy->reset_delay_us = 100;
313 phy->ops.power_up = e1000_power_up_phy_copper;
314 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
317 * We may need to do this twice - once for IGP and if that fails,
318 * we'll set BM func pointers and try again
320 ret_val = e1000e_determine_phy_address(hw);
322 phy->ops.write_reg = e1000e_write_phy_reg_bm;
323 phy->ops.read_reg = e1000e_read_phy_reg_bm;
324 ret_val = e1000e_determine_phy_address(hw);
326 e_dbg("Cannot determine PHY addr. Erroring out\n");
332 while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&
335 ret_val = e1000e_get_phy_id(hw);
342 case IGP03E1000_E_PHY_ID:
343 phy->type = e1000_phy_igp_3;
344 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
345 phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked;
346 phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked;
347 phy->ops.get_info = e1000e_get_phy_info_igp;
348 phy->ops.check_polarity = e1000_check_polarity_igp;
349 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_igp;
352 case IFE_PLUS_E_PHY_ID:
354 phy->type = e1000_phy_ife;
355 phy->autoneg_mask = E1000_ALL_NOT_GIG;
356 phy->ops.get_info = e1000_get_phy_info_ife;
357 phy->ops.check_polarity = e1000_check_polarity_ife;
358 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
360 case BME1000_E_PHY_ID:
361 phy->type = e1000_phy_bm;
362 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
363 phy->ops.read_reg = e1000e_read_phy_reg_bm;
364 phy->ops.write_reg = e1000e_write_phy_reg_bm;
365 phy->ops.commit = e1000e_phy_sw_reset;
366 phy->ops.get_info = e1000e_get_phy_info_m88;
367 phy->ops.check_polarity = e1000_check_polarity_m88;
368 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
371 return -E1000_ERR_PHY;
379 * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
380 * @hw: pointer to the HW structure
382 * Initialize family-specific NVM parameters and function
385 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
387 struct e1000_nvm_info *nvm = &hw->nvm;
388 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
389 u32 gfpreg, sector_base_addr, sector_end_addr;
392 /* Can't read flash registers if the register set isn't mapped. */
393 if (!hw->flash_address) {
394 e_dbg("ERROR: Flash registers not mapped\n");
395 return -E1000_ERR_CONFIG;
398 nvm->type = e1000_nvm_flash_sw;
400 gfpreg = er32flash(ICH_FLASH_GFPREG);
403 * sector_X_addr is a "sector"-aligned address (4096 bytes)
404 * Add 1 to sector_end_addr since this sector is included in
407 sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
408 sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
410 /* flash_base_addr is byte-aligned */
411 nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
414 * find total size of the NVM, then cut in half since the total
415 * size represents two separate NVM banks.
417 nvm->flash_bank_size = (sector_end_addr - sector_base_addr)
418 << FLASH_SECTOR_ADDR_SHIFT;
419 nvm->flash_bank_size /= 2;
420 /* Adjust to word count */
421 nvm->flash_bank_size /= sizeof(u16);
423 nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS;
425 /* Clear shadow ram */
426 for (i = 0; i < nvm->word_size; i++) {
427 dev_spec->shadow_ram[i].modified = false;
428 dev_spec->shadow_ram[i].value = 0xFFFF;
435 * e1000_init_mac_params_ich8lan - Initialize MAC function pointers
436 * @hw: pointer to the HW structure
438 * Initialize family-specific MAC parameters and function
441 static s32 e1000_init_mac_params_ich8lan(struct e1000_adapter *adapter)
443 struct e1000_hw *hw = &adapter->hw;
444 struct e1000_mac_info *mac = &hw->mac;
446 /* Set media type function pointer */
447 hw->phy.media_type = e1000_media_type_copper;
449 /* Set mta register count */
450 mac->mta_reg_count = 32;
451 /* Set rar entry count */
452 mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
453 if (mac->type == e1000_ich8lan)
454 mac->rar_entry_count--;
455 /* Set if manageability features are enabled. */
456 mac->arc_subsystem_valid = true;
457 /* Adaptive IFS supported */
458 mac->adaptive_ifs = true;
466 mac->ops.id_led_init = e1000e_id_led_init;
468 mac->ops.setup_led = e1000e_setup_led_generic;
470 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
471 /* turn on/off LED */
472 mac->ops.led_on = e1000_led_on_ich8lan;
473 mac->ops.led_off = e1000_led_off_ich8lan;
477 mac->ops.id_led_init = e1000_id_led_init_pchlan;
479 mac->ops.setup_led = e1000_setup_led_pchlan;
481 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
482 /* turn on/off LED */
483 mac->ops.led_on = e1000_led_on_pchlan;
484 mac->ops.led_off = e1000_led_off_pchlan;
490 /* Enable PCS Lock-loss workaround for ICH8 */
491 if (mac->type == e1000_ich8lan)
492 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
498 * e1000_check_for_copper_link_ich8lan - Check for link (Copper)
499 * @hw: pointer to the HW structure
501 * Checks to see of the link status of the hardware has changed. If a
502 * change in link status has been detected, then we read the PHY registers
503 * to get the current speed/duplex if link exists.
505 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
507 struct e1000_mac_info *mac = &hw->mac;
512 * We only want to go out to the PHY registers to see if Auto-Neg
513 * has completed and/or if our link status has changed. The
514 * get_link_status flag is set upon receiving a Link Status
515 * Change or Rx Sequence Error interrupt.
517 if (!mac->get_link_status) {
523 * First we want to see if the MII Status Register reports
524 * link. If so, then we want to get the current speed/duplex
527 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
531 if (hw->mac.type == e1000_pchlan) {
532 ret_val = e1000_k1_gig_workaround_hv(hw, link);
538 goto out; /* No link detected */
540 mac->get_link_status = false;
542 if (hw->phy.type == e1000_phy_82578) {
543 ret_val = e1000_link_stall_workaround_hv(hw);
549 * Check if there was DownShift, must be checked
550 * immediately after link-up
552 e1000e_check_downshift(hw);
555 * If we are forcing speed/duplex, then we simply return since
556 * we have already determined whether we have link or not.
559 ret_val = -E1000_ERR_CONFIG;
564 * Auto-Neg is enabled. Auto Speed Detection takes care
565 * of MAC speed/duplex configuration. So we only need to
566 * configure Collision Distance in the MAC.
568 e1000e_config_collision_dist(hw);
571 * Configure Flow Control now that Auto-Neg has completed.
572 * First, we need to restore the desired flow control
573 * settings because we may have had to re-autoneg with a
574 * different link partner.
576 ret_val = e1000e_config_fc_after_link_up(hw);
578 e_dbg("Error configuring flow control\n");
584 static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)
586 struct e1000_hw *hw = &adapter->hw;
589 rc = e1000_init_mac_params_ich8lan(adapter);
593 rc = e1000_init_nvm_params_ich8lan(hw);
597 if (hw->mac.type == e1000_pchlan)
598 rc = e1000_init_phy_params_pchlan(hw);
600 rc = e1000_init_phy_params_ich8lan(hw);
604 if (adapter->hw.phy.type == e1000_phy_ife) {
605 adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES;
606 adapter->max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN;
609 if ((adapter->hw.mac.type == e1000_ich8lan) &&
610 (adapter->hw.phy.type == e1000_phy_igp_3))
611 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP;
616 static DEFINE_MUTEX(nvm_mutex);
619 * e1000_acquire_nvm_ich8lan - Acquire NVM mutex
620 * @hw: pointer to the HW structure
622 * Acquires the mutex for performing NVM operations.
624 static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw)
626 mutex_lock(&nvm_mutex);
632 * e1000_release_nvm_ich8lan - Release NVM mutex
633 * @hw: pointer to the HW structure
635 * Releases the mutex used while performing NVM operations.
637 static void e1000_release_nvm_ich8lan(struct e1000_hw *hw)
639 mutex_unlock(&nvm_mutex);
644 static DEFINE_MUTEX(swflag_mutex);
647 * e1000_acquire_swflag_ich8lan - Acquire software control flag
648 * @hw: pointer to the HW structure
650 * Acquires the software control flag for performing PHY and select
653 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
655 u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
658 mutex_lock(&swflag_mutex);
661 extcnf_ctrl = er32(EXTCNF_CTRL);
662 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
670 e_dbg("SW/FW/HW has locked the resource for too long.\n");
671 ret_val = -E1000_ERR_CONFIG;
675 timeout = SW_FLAG_TIMEOUT;
677 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
678 ew32(EXTCNF_CTRL, extcnf_ctrl);
681 extcnf_ctrl = er32(EXTCNF_CTRL);
682 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
690 e_dbg("Failed to acquire the semaphore.\n");
691 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
692 ew32(EXTCNF_CTRL, extcnf_ctrl);
693 ret_val = -E1000_ERR_CONFIG;
699 mutex_unlock(&swflag_mutex);
705 * e1000_release_swflag_ich8lan - Release software control flag
706 * @hw: pointer to the HW structure
708 * Releases the software control flag for performing PHY and select
711 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
715 extcnf_ctrl = er32(EXTCNF_CTRL);
716 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
717 ew32(EXTCNF_CTRL, extcnf_ctrl);
719 mutex_unlock(&swflag_mutex);
725 * e1000_check_mng_mode_ich8lan - Checks management mode
726 * @hw: pointer to the HW structure
728 * This checks if the adapter has manageability enabled.
729 * This is a function pointer entry point only called by read/write
730 * routines for the PHY and NVM parts.
732 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
738 return (fwsm & E1000_FWSM_MODE_MASK) ==
739 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT);
743 * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
744 * @hw: pointer to the HW structure
746 * Checks if firmware is blocking the reset of the PHY.
747 * This is a function pointer entry point only called by
750 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
756 return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? 0 : E1000_BLK_PHY_RESET;
760 * e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
761 * @hw: pointer to the HW structure
763 * SW should configure the LCD from the NVM extended configuration region
764 * as a workaround for certain parts.
766 static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
768 struct e1000_phy_info *phy = &hw->phy;
769 u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
771 u16 word_addr, reg_data, reg_addr, phy_page = 0;
773 ret_val = hw->phy.ops.acquire(hw);
778 * Initialize the PHY from the NVM on ICH platforms. This
779 * is needed due to an issue where the NVM configuration is
780 * not properly autoloaded after power transitions.
781 * Therefore, after each PHY reset, we will load the
782 * configuration data out of the NVM manually.
784 if ((hw->mac.type == e1000_ich8lan && phy->type == e1000_phy_igp_3) ||
785 (hw->mac.type == e1000_pchlan)) {
786 struct e1000_adapter *adapter = hw->adapter;
788 /* Check if SW needs to configure the PHY */
789 if ((adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_M_AMT) ||
790 (adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_M) ||
791 (hw->mac.type == e1000_pchlan))
792 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
794 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
796 data = er32(FEXTNVM);
797 if (!(data & sw_cfg_mask))
800 /* Wait for basic configuration completes before proceeding */
801 e1000_lan_init_done_ich8lan(hw);
804 * Make sure HW does not configure LCD from PHY
805 * extended configuration before SW configuration
807 data = er32(EXTCNF_CTRL);
808 if (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE)
811 cnf_size = er32(EXTCNF_SIZE);
812 cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
813 cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
817 cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
818 cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
820 if (!(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE) &&
821 (hw->mac.type == e1000_pchlan)) {
823 * HW configures the SMBus address and LEDs when the
824 * OEM and LCD Write Enable bits are set in the NVM.
825 * When both NVM bits are cleared, SW will configure
829 data &= E1000_STRAP_SMBUS_ADDRESS_MASK;
830 reg_data = data >> E1000_STRAP_SMBUS_ADDRESS_SHIFT;
831 reg_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
832 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR,
838 ret_val = e1000_write_phy_reg_hv_locked(hw,
844 /* Configure LCD from extended configuration region. */
846 /* cnf_base_addr is in DWORD */
847 word_addr = (u16)(cnf_base_addr << 1);
849 for (i = 0; i < cnf_size; i++) {
850 ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1,
855 ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1),
860 /* Save off the PHY page for future writes. */
861 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
866 reg_addr &= PHY_REG_MASK;
867 reg_addr |= phy_page;
869 ret_val = phy->ops.write_reg_locked(hw,
878 hw->phy.ops.release(hw);
883 * e1000_k1_gig_workaround_hv - K1 Si workaround
884 * @hw: pointer to the HW structure
885 * @link: link up bool flag
887 * If K1 is enabled for 1Gbps, the MAC might stall when transitioning
888 * from a lower speed. This workaround disables K1 whenever link is at 1Gig
889 * If link is down, the function will restore the default K1 setting located
892 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
896 bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
898 if (hw->mac.type != e1000_pchlan)
901 /* Wrap the whole flow with the sw flag */
902 ret_val = hw->phy.ops.acquire(hw);
906 /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
908 if (hw->phy.type == e1000_phy_82578) {
909 ret_val = hw->phy.ops.read_reg_locked(hw, BM_CS_STATUS,
914 status_reg &= BM_CS_STATUS_LINK_UP |
915 BM_CS_STATUS_RESOLVED |
916 BM_CS_STATUS_SPEED_MASK;
918 if (status_reg == (BM_CS_STATUS_LINK_UP |
919 BM_CS_STATUS_RESOLVED |
920 BM_CS_STATUS_SPEED_1000))
924 if (hw->phy.type == e1000_phy_82577) {
925 ret_val = hw->phy.ops.read_reg_locked(hw, HV_M_STATUS,
930 status_reg &= HV_M_STATUS_LINK_UP |
931 HV_M_STATUS_AUTONEG_COMPLETE |
932 HV_M_STATUS_SPEED_MASK;
934 if (status_reg == (HV_M_STATUS_LINK_UP |
935 HV_M_STATUS_AUTONEG_COMPLETE |
936 HV_M_STATUS_SPEED_1000))
940 /* Link stall fix for link up */
941 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
947 /* Link stall fix for link down */
948 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
954 ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
957 hw->phy.ops.release(hw);
963 * e1000_configure_k1_ich8lan - Configure K1 power state
964 * @hw: pointer to the HW structure
965 * @enable: K1 state to configure
967 * Configure the K1 power state based on the provided parameter.
968 * Assumes semaphore already acquired.
970 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
972 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
980 ret_val = e1000e_read_kmrn_reg_locked(hw,
981 E1000_KMRNCTRLSTA_K1_CONFIG,
987 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
989 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
991 ret_val = e1000e_write_kmrn_reg_locked(hw,
992 E1000_KMRNCTRLSTA_K1_CONFIG,
998 ctrl_ext = er32(CTRL_EXT);
999 ctrl_reg = er32(CTRL);
1001 reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1002 reg |= E1000_CTRL_FRCSPD;
1005 ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
1007 ew32(CTRL, ctrl_reg);
1008 ew32(CTRL_EXT, ctrl_ext);
1016 * e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
1017 * @hw: pointer to the HW structure
1018 * @d0_state: boolean if entering d0 or d3 device state
1020 * SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
1021 * collectively called OEM bits. The OEM Write Enable bit and SW Config bit
1022 * in NVM determines whether HW should configure LPLU and Gbe Disable.
1024 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
1030 if (hw->mac.type != e1000_pchlan)
1033 ret_val = hw->phy.ops.acquire(hw);
1037 mac_reg = er32(EXTCNF_CTRL);
1038 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
1041 mac_reg = er32(FEXTNVM);
1042 if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
1045 mac_reg = er32(PHY_CTRL);
1047 ret_val = hw->phy.ops.read_reg_locked(hw, HV_OEM_BITS, &oem_reg);
1051 oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
1054 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
1055 oem_reg |= HV_OEM_BITS_GBE_DIS;
1057 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
1058 oem_reg |= HV_OEM_BITS_LPLU;
1060 if (mac_reg & E1000_PHY_CTRL_NOND0A_GBE_DISABLE)
1061 oem_reg |= HV_OEM_BITS_GBE_DIS;
1063 if (mac_reg & E1000_PHY_CTRL_NOND0A_LPLU)
1064 oem_reg |= HV_OEM_BITS_LPLU;
1066 /* Restart auto-neg to activate the bits */
1067 if (!e1000_check_reset_block(hw))
1068 oem_reg |= HV_OEM_BITS_RESTART_AN;
1069 ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg);
1072 hw->phy.ops.release(hw);
1079 * e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
1080 * done after every PHY reset.
1082 static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
1086 if (hw->mac.type != e1000_pchlan)
1089 if (((hw->phy.type == e1000_phy_82577) &&
1090 ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
1091 ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
1092 /* Disable generation of early preamble */
1093 ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431);
1097 /* Preamble tuning for SSC */
1098 ret_val = e1e_wphy(hw, PHY_REG(770, 16), 0xA204);
1103 if (hw->phy.type == e1000_phy_82578) {
1105 * Return registers to default by doing a soft reset then
1106 * writing 0x3140 to the control register.
1108 if (hw->phy.revision < 2) {
1109 e1000e_phy_sw_reset(hw);
1110 ret_val = e1e_wphy(hw, PHY_CONTROL, 0x3140);
1115 ret_val = hw->phy.ops.acquire(hw);
1120 ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
1123 hw->phy.ops.release(hw);
1126 * Configure the K1 Si workaround during phy reset assuming there is
1127 * link so that it disables K1 if link is in 1Gbps.
1129 ret_val = e1000_k1_gig_workaround_hv(hw, true);
1136 * e1000_lan_init_done_ich8lan - Check for PHY config completion
1137 * @hw: pointer to the HW structure
1139 * Check the appropriate indication the MAC has finished configuring the
1140 * PHY after a software reset.
1142 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
1144 u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
1146 /* Wait for basic configuration completes before proceeding */
1148 data = er32(STATUS);
1149 data &= E1000_STATUS_LAN_INIT_DONE;
1151 } while ((!data) && --loop);
1154 * If basic configuration is incomplete before the above loop
1155 * count reaches 0, loading the configuration from NVM will
1156 * leave the PHY in a bad state possibly resulting in no link.
1159 e_dbg("LAN_INIT_DONE not set, increase timeout\n");
1161 /* Clear the Init Done bit for the next init event */
1162 data = er32(STATUS);
1163 data &= ~E1000_STATUS_LAN_INIT_DONE;
1168 * e1000_phy_hw_reset_ich8lan - Performs a PHY reset
1169 * @hw: pointer to the HW structure
1172 * This is a function pointer entry point called by drivers
1173 * or other shared routines.
1175 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
1180 ret_val = e1000e_phy_hw_reset_generic(hw);
1184 /* Allow time for h/w to get to a quiescent state after reset */
1187 if (hw->mac.type == e1000_pchlan) {
1188 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
1193 /* Dummy read to clear the phy wakeup bit after lcd reset */
1194 if (hw->mac.type == e1000_pchlan)
1195 e1e_rphy(hw, BM_WUC, ®);
1197 /* Configure the LCD with the extended configuration region in NVM */
1198 ret_val = e1000_sw_lcd_config_ich8lan(hw);
1202 /* Configure the LCD with the OEM bits in NVM */
1203 if (hw->mac.type == e1000_pchlan)
1204 ret_val = e1000_oem_bits_config_ich8lan(hw, true);
1211 * e1000_set_lplu_state_pchlan - Set Low Power Link Up state
1212 * @hw: pointer to the HW structure
1213 * @active: true to enable LPLU, false to disable
1215 * Sets the LPLU state according to the active flag. For PCH, if OEM write
1216 * bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
1217 * the phy speed. This function will manually set the LPLU bit and restart
1218 * auto-neg as hw would do. D3 and D0 LPLU will call the same function
1219 * since it configures the same bit.
1221 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
1226 ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg);
1231 oem_reg |= HV_OEM_BITS_LPLU;
1233 oem_reg &= ~HV_OEM_BITS_LPLU;
1235 oem_reg |= HV_OEM_BITS_RESTART_AN;
1236 ret_val = e1e_wphy(hw, HV_OEM_BITS, oem_reg);
1243 * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
1244 * @hw: pointer to the HW structure
1245 * @active: true to enable LPLU, false to disable
1247 * Sets the LPLU D0 state according to the active flag. When
1248 * activating LPLU this function also disables smart speed
1249 * and vice versa. LPLU will not be activated unless the
1250 * device autonegotiation advertisement meets standards of
1251 * either 10 or 10/100 or 10/100/1000 at all duplexes.
1252 * This is a function pointer entry point only called by
1253 * PHY setup routines.
1255 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
1257 struct e1000_phy_info *phy = &hw->phy;
1262 if (phy->type == e1000_phy_ife)
1265 phy_ctrl = er32(PHY_CTRL);
1268 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
1269 ew32(PHY_CTRL, phy_ctrl);
1271 if (phy->type != e1000_phy_igp_3)
1275 * Call gig speed drop workaround on LPLU before accessing
1278 if (hw->mac.type == e1000_ich8lan)
1279 e1000e_gig_downshift_workaround_ich8lan(hw);
1281 /* When LPLU is enabled, we should disable SmartSpeed */
1282 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1283 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1284 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
1288 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
1289 ew32(PHY_CTRL, phy_ctrl);
1291 if (phy->type != e1000_phy_igp_3)
1295 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
1296 * during Dx states where the power conservation is most
1297 * important. During driver activity we should enable
1298 * SmartSpeed, so performance is maintained.
1300 if (phy->smart_speed == e1000_smart_speed_on) {
1301 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1306 data |= IGP01E1000_PSCFR_SMART_SPEED;
1307 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1311 } else if (phy->smart_speed == e1000_smart_speed_off) {
1312 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1317 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1318 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1329 * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
1330 * @hw: pointer to the HW structure
1331 * @active: true to enable LPLU, false to disable
1333 * Sets the LPLU D3 state according to the active flag. When
1334 * activating LPLU this function also disables smart speed
1335 * and vice versa. LPLU will not be activated unless the
1336 * device autonegotiation advertisement meets standards of
1337 * either 10 or 10/100 or 10/100/1000 at all duplexes.
1338 * This is a function pointer entry point only called by
1339 * PHY setup routines.
1341 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
1343 struct e1000_phy_info *phy = &hw->phy;
1348 phy_ctrl = er32(PHY_CTRL);
1351 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
1352 ew32(PHY_CTRL, phy_ctrl);
1354 if (phy->type != e1000_phy_igp_3)
1358 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
1359 * during Dx states where the power conservation is most
1360 * important. During driver activity we should enable
1361 * SmartSpeed, so performance is maintained.
1363 if (phy->smart_speed == e1000_smart_speed_on) {
1364 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1369 data |= IGP01E1000_PSCFR_SMART_SPEED;
1370 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1374 } else if (phy->smart_speed == e1000_smart_speed_off) {
1375 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1380 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1381 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1386 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1387 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1388 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1389 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
1390 ew32(PHY_CTRL, phy_ctrl);
1392 if (phy->type != e1000_phy_igp_3)
1396 * Call gig speed drop workaround on LPLU before accessing
1399 if (hw->mac.type == e1000_ich8lan)
1400 e1000e_gig_downshift_workaround_ich8lan(hw);
1402 /* When LPLU is enabled, we should disable SmartSpeed */
1403 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1407 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1408 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
1415 * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
1416 * @hw: pointer to the HW structure
1417 * @bank: pointer to the variable that returns the active bank
1419 * Reads signature byte from the NVM using the flash access registers.
1420 * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
1422 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
1425 struct e1000_nvm_info *nvm = &hw->nvm;
1426 u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
1427 u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
1431 switch (hw->mac.type) {
1435 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
1436 E1000_EECD_SEC1VAL_VALID_MASK) {
1437 if (eecd & E1000_EECD_SEC1VAL)
1444 e_dbg("Unable to determine valid NVM bank via EEC - "
1445 "reading flash signature\n");
1448 /* set bank to 0 in case flash read fails */
1452 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
1456 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
1457 E1000_ICH_NVM_SIG_VALUE) {
1463 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
1468 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
1469 E1000_ICH_NVM_SIG_VALUE) {
1474 e_dbg("ERROR: No valid NVM bank present\n");
1475 return -E1000_ERR_NVM;
1482 * e1000_read_nvm_ich8lan - Read word(s) from the NVM
1483 * @hw: pointer to the HW structure
1484 * @offset: The offset (in bytes) of the word(s) to read.
1485 * @words: Size of data to read in words
1486 * @data: Pointer to the word(s) to read at offset.
1488 * Reads a word(s) from the NVM using the flash access registers.
1490 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
1493 struct e1000_nvm_info *nvm = &hw->nvm;
1494 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1500 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
1502 e_dbg("nvm parameter(s) out of bounds\n");
1503 ret_val = -E1000_ERR_NVM;
1507 nvm->ops.acquire(hw);
1509 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
1511 e_dbg("Could not detect valid bank, assuming bank 0\n");
1515 act_offset = (bank) ? nvm->flash_bank_size : 0;
1516 act_offset += offset;
1519 for (i = 0; i < words; i++) {
1520 if ((dev_spec->shadow_ram) &&
1521 (dev_spec->shadow_ram[offset+i].modified)) {
1522 data[i] = dev_spec->shadow_ram[offset+i].value;
1524 ret_val = e1000_read_flash_word_ich8lan(hw,
1533 nvm->ops.release(hw);
1537 e_dbg("NVM read error: %d\n", ret_val);
1543 * e1000_flash_cycle_init_ich8lan - Initialize flash
1544 * @hw: pointer to the HW structure
1546 * This function does initial flash setup so that a new read/write/erase cycle
1549 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
1551 union ich8_hws_flash_status hsfsts;
1552 s32 ret_val = -E1000_ERR_NVM;
1555 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1557 /* Check if the flash descriptor is valid */
1558 if (hsfsts.hsf_status.fldesvalid == 0) {
1559 e_dbg("Flash descriptor invalid. "
1560 "SW Sequencing must be used.");
1561 return -E1000_ERR_NVM;
1564 /* Clear FCERR and DAEL in hw status by writing 1 */
1565 hsfsts.hsf_status.flcerr = 1;
1566 hsfsts.hsf_status.dael = 1;
1568 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
1571 * Either we should have a hardware SPI cycle in progress
1572 * bit to check against, in order to start a new cycle or
1573 * FDONE bit should be changed in the hardware so that it
1574 * is 1 after hardware reset, which can then be used as an
1575 * indication whether a cycle is in progress or has been
1579 if (hsfsts.hsf_status.flcinprog == 0) {
1581 * There is no cycle running at present,
1582 * so we can start a cycle.
1583 * Begin by setting Flash Cycle Done.
1585 hsfsts.hsf_status.flcdone = 1;
1586 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
1590 * Otherwise poll for sometime so the current
1591 * cycle has a chance to end before giving up.
1593 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
1594 hsfsts.regval = __er16flash(hw, ICH_FLASH_HSFSTS);
1595 if (hsfsts.hsf_status.flcinprog == 0) {
1603 * Successful in waiting for previous cycle to timeout,
1604 * now set the Flash Cycle Done.
1606 hsfsts.hsf_status.flcdone = 1;
1607 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
1609 e_dbg("Flash controller busy, cannot get access");
1617 * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
1618 * @hw: pointer to the HW structure
1619 * @timeout: maximum time to wait for completion
1621 * This function starts a flash cycle and waits for its completion.
1623 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
1625 union ich8_hws_flash_ctrl hsflctl;
1626 union ich8_hws_flash_status hsfsts;
1627 s32 ret_val = -E1000_ERR_NVM;
1630 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
1631 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
1632 hsflctl.hsf_ctrl.flcgo = 1;
1633 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
1635 /* wait till FDONE bit is set to 1 */
1637 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1638 if (hsfsts.hsf_status.flcdone == 1)
1641 } while (i++ < timeout);
1643 if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0)
1650 * e1000_read_flash_word_ich8lan - Read word from flash
1651 * @hw: pointer to the HW structure
1652 * @offset: offset to data location
1653 * @data: pointer to the location for storing the data
1655 * Reads the flash word at offset into data. Offset is converted
1656 * to bytes before read.
1658 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
1661 /* Must convert offset into bytes. */
1664 return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
1668 * e1000_read_flash_byte_ich8lan - Read byte from flash
1669 * @hw: pointer to the HW structure
1670 * @offset: The offset of the byte to read.
1671 * @data: Pointer to a byte to store the value read.
1673 * Reads a single byte from the NVM using the flash access registers.
1675 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
1681 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
1691 * e1000_read_flash_data_ich8lan - Read byte or word from NVM
1692 * @hw: pointer to the HW structure
1693 * @offset: The offset (in bytes) of the byte or word to read.
1694 * @size: Size of data to read, 1=byte 2=word
1695 * @data: Pointer to the word to store the value read.
1697 * Reads a byte or word from the NVM using the flash access registers.
1699 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
1702 union ich8_hws_flash_status hsfsts;
1703 union ich8_hws_flash_ctrl hsflctl;
1704 u32 flash_linear_addr;
1706 s32 ret_val = -E1000_ERR_NVM;
1709 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
1710 return -E1000_ERR_NVM;
1712 flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
1713 hw->nvm.flash_base_addr;
1718 ret_val = e1000_flash_cycle_init_ich8lan(hw);
1722 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
1723 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
1724 hsflctl.hsf_ctrl.fldbcount = size - 1;
1725 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
1726 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
1728 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
1730 ret_val = e1000_flash_cycle_ich8lan(hw,
1731 ICH_FLASH_READ_COMMAND_TIMEOUT);
1734 * Check if FCERR is set to 1, if set to 1, clear it
1735 * and try the whole sequence a few more times, else
1736 * read in (shift in) the Flash Data0, the order is
1737 * least significant byte first msb to lsb
1740 flash_data = er32flash(ICH_FLASH_FDATA0);
1742 *data = (u8)(flash_data & 0x000000FF);
1743 } else if (size == 2) {
1744 *data = (u16)(flash_data & 0x0000FFFF);
1749 * If we've gotten here, then things are probably
1750 * completely hosed, but if the error condition is
1751 * detected, it won't hurt to give it another try...
1752 * ICH_FLASH_CYCLE_REPEAT_COUNT times.
1754 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1755 if (hsfsts.hsf_status.flcerr == 1) {
1756 /* Repeat for some time before giving up. */
1758 } else if (hsfsts.hsf_status.flcdone == 0) {
1759 e_dbg("Timeout error - flash cycle "
1760 "did not complete.");
1764 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
1770 * e1000_write_nvm_ich8lan - Write word(s) to the NVM
1771 * @hw: pointer to the HW structure
1772 * @offset: The offset (in bytes) of the word(s) to write.
1773 * @words: Size of data to write in words
1774 * @data: Pointer to the word(s) to write at offset.
1776 * Writes a byte or word to the NVM using the flash access registers.
1778 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
1781 struct e1000_nvm_info *nvm = &hw->nvm;
1782 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1785 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
1787 e_dbg("nvm parameter(s) out of bounds\n");
1788 return -E1000_ERR_NVM;
1791 nvm->ops.acquire(hw);
1793 for (i = 0; i < words; i++) {
1794 dev_spec->shadow_ram[offset+i].modified = true;
1795 dev_spec->shadow_ram[offset+i].value = data[i];
1798 nvm->ops.release(hw);
1804 * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
1805 * @hw: pointer to the HW structure
1807 * The NVM checksum is updated by calling the generic update_nvm_checksum,
1808 * which writes the checksum to the shadow ram. The changes in the shadow
1809 * ram are then committed to the EEPROM by processing each bank at a time
1810 * checking for the modified bit and writing only the pending changes.
1811 * After a successful commit, the shadow ram is cleared and is ready for
1814 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
1816 struct e1000_nvm_info *nvm = &hw->nvm;
1817 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1818 u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
1822 ret_val = e1000e_update_nvm_checksum_generic(hw);
1826 if (nvm->type != e1000_nvm_flash_sw)
1829 nvm->ops.acquire(hw);
1832 * We're writing to the opposite bank so if we're on bank 1,
1833 * write to bank 0 etc. We also need to erase the segment that
1834 * is going to be written
1836 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
1838 e_dbg("Could not detect valid bank, assuming bank 0\n");
1843 new_bank_offset = nvm->flash_bank_size;
1844 old_bank_offset = 0;
1845 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
1847 nvm->ops.release(hw);
1851 old_bank_offset = nvm->flash_bank_size;
1852 new_bank_offset = 0;
1853 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
1855 nvm->ops.release(hw);
1860 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
1862 * Determine whether to write the value stored
1863 * in the other NVM bank or a modified value stored
1866 if (dev_spec->shadow_ram[i].modified) {
1867 data = dev_spec->shadow_ram[i].value;
1869 ret_val = e1000_read_flash_word_ich8lan(hw, i +
1877 * If the word is 0x13, then make sure the signature bits
1878 * (15:14) are 11b until the commit has completed.
1879 * This will allow us to write 10b which indicates the
1880 * signature is valid. We want to do this after the write
1881 * has completed so that we don't mark the segment valid
1882 * while the write is still in progress
1884 if (i == E1000_ICH_NVM_SIG_WORD)
1885 data |= E1000_ICH_NVM_SIG_MASK;
1887 /* Convert offset to bytes. */
1888 act_offset = (i + new_bank_offset) << 1;
1891 /* Write the bytes to the new bank. */
1892 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
1899 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
1907 * Don't bother writing the segment valid bits if sector
1908 * programming failed.
1911 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
1912 e_dbg("Flash commit failed.\n");
1913 nvm->ops.release(hw);
1918 * Finally validate the new segment by setting bit 15:14
1919 * to 10b in word 0x13 , this can be done without an
1920 * erase as well since these bits are 11 to start with
1921 * and we need to change bit 14 to 0b
1923 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
1924 ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
1926 nvm->ops.release(hw);
1930 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
1934 nvm->ops.release(hw);
1939 * And invalidate the previously valid segment by setting
1940 * its signature word (0x13) high_byte to 0b. This can be
1941 * done without an erase because flash erase sets all bits
1942 * to 1's. We can write 1's to 0's without an erase
1944 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
1945 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
1947 nvm->ops.release(hw);
1951 /* Great! Everything worked, we can now clear the cached entries. */
1952 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
1953 dev_spec->shadow_ram[i].modified = false;
1954 dev_spec->shadow_ram[i].value = 0xFFFF;
1957 nvm->ops.release(hw);
1960 * Reload the EEPROM, or else modifications will not appear
1961 * until after the next adapter reset.
1963 e1000e_reload_nvm(hw);
1968 e_dbg("NVM update error: %d\n", ret_val);
1974 * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
1975 * @hw: pointer to the HW structure
1977 * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
1978 * If the bit is 0, that the EEPROM had been modified, but the checksum was not
1979 * calculated, in which case we need to calculate the checksum and set bit 6.
1981 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
1987 * Read 0x19 and check bit 6. If this bit is 0, the checksum
1988 * needs to be fixed. This bit is an indication that the NVM
1989 * was prepared by OEM software and did not calculate the
1990 * checksum...a likely scenario.
1992 ret_val = e1000_read_nvm(hw, 0x19, 1, &data);
1996 if ((data & 0x40) == 0) {
1998 ret_val = e1000_write_nvm(hw, 0x19, 1, &data);
2001 ret_val = e1000e_update_nvm_checksum(hw);
2006 return e1000e_validate_nvm_checksum_generic(hw);
2010 * e1000e_write_protect_nvm_ich8lan - Make the NVM read-only
2011 * @hw: pointer to the HW structure
2013 * To prevent malicious write/erase of the NVM, set it to be read-only
2014 * so that the hardware ignores all write/erase cycles of the NVM via
2015 * the flash control registers. The shadow-ram copy of the NVM will
2016 * still be updated, however any updates to this copy will not stick
2017 * across driver reloads.
2019 void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw)
2021 struct e1000_nvm_info *nvm = &hw->nvm;
2022 union ich8_flash_protected_range pr0;
2023 union ich8_hws_flash_status hsfsts;
2026 nvm->ops.acquire(hw);
2028 gfpreg = er32flash(ICH_FLASH_GFPREG);
2030 /* Write-protect GbE Sector of NVM */
2031 pr0.regval = er32flash(ICH_FLASH_PR0);
2032 pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK;
2033 pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK);
2034 pr0.range.wpe = true;
2035 ew32flash(ICH_FLASH_PR0, pr0.regval);
2038 * Lock down a subset of GbE Flash Control Registers, e.g.
2039 * PR0 to prevent the write-protection from being lifted.
2040 * Once FLOCKDN is set, the registers protected by it cannot
2041 * be written until FLOCKDN is cleared by a hardware reset.
2043 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2044 hsfsts.hsf_status.flockdn = true;
2045 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2047 nvm->ops.release(hw);
2051 * e1000_write_flash_data_ich8lan - Writes bytes to the NVM
2052 * @hw: pointer to the HW structure
2053 * @offset: The offset (in bytes) of the byte/word to read.
2054 * @size: Size of data to read, 1=byte 2=word
2055 * @data: The byte(s) to write to the NVM.
2057 * Writes one/two bytes to the NVM using the flash access registers.
2059 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
2062 union ich8_hws_flash_status hsfsts;
2063 union ich8_hws_flash_ctrl hsflctl;
2064 u32 flash_linear_addr;
2069 if (size < 1 || size > 2 || data > size * 0xff ||
2070 offset > ICH_FLASH_LINEAR_ADDR_MASK)
2071 return -E1000_ERR_NVM;
2073 flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
2074 hw->nvm.flash_base_addr;
2079 ret_val = e1000_flash_cycle_init_ich8lan(hw);
2083 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2084 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
2085 hsflctl.hsf_ctrl.fldbcount = size -1;
2086 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
2087 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2089 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2092 flash_data = (u32)data & 0x00FF;
2094 flash_data = (u32)data;
2096 ew32flash(ICH_FLASH_FDATA0, flash_data);
2099 * check if FCERR is set to 1 , if set to 1, clear it
2100 * and try the whole sequence a few more times else done
2102 ret_val = e1000_flash_cycle_ich8lan(hw,
2103 ICH_FLASH_WRITE_COMMAND_TIMEOUT);
2108 * If we're here, then things are most likely
2109 * completely hosed, but if the error condition
2110 * is detected, it won't hurt to give it another
2111 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
2113 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2114 if (hsfsts.hsf_status.flcerr == 1)
2115 /* Repeat for some time before giving up. */
2117 if (hsfsts.hsf_status.flcdone == 0) {
2118 e_dbg("Timeout error - flash cycle "
2119 "did not complete.");
2122 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
2128 * e1000_write_flash_byte_ich8lan - Write a single byte to NVM
2129 * @hw: pointer to the HW structure
2130 * @offset: The index of the byte to read.
2131 * @data: The byte to write to the NVM.
2133 * Writes a single byte to the NVM using the flash access registers.
2135 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
2138 u16 word = (u16)data;
2140 return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
2144 * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
2145 * @hw: pointer to the HW structure
2146 * @offset: The offset of the byte to write.
2147 * @byte: The byte to write to the NVM.
2149 * Writes a single byte to the NVM using the flash access registers.
2150 * Goes through a retry algorithm before giving up.
2152 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
2153 u32 offset, u8 byte)
2156 u16 program_retries;
2158 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
2162 for (program_retries = 0; program_retries < 100; program_retries++) {
2163 e_dbg("Retrying Byte %2.2X at offset %u\n", byte, offset);
2165 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
2169 if (program_retries == 100)
2170 return -E1000_ERR_NVM;
2176 * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
2177 * @hw: pointer to the HW structure
2178 * @bank: 0 for first bank, 1 for second bank, etc.
2180 * Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
2181 * bank N is 4096 * N + flash_reg_addr.
2183 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
2185 struct e1000_nvm_info *nvm = &hw->nvm;
2186 union ich8_hws_flash_status hsfsts;
2187 union ich8_hws_flash_ctrl hsflctl;
2188 u32 flash_linear_addr;
2189 /* bank size is in 16bit words - adjust to bytes */
2190 u32 flash_bank_size = nvm->flash_bank_size * 2;
2193 s32 j, iteration, sector_size;
2195 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2198 * Determine HW Sector size: Read BERASE bits of hw flash status
2200 * 00: The Hw sector is 256 bytes, hence we need to erase 16
2201 * consecutive sectors. The start index for the nth Hw sector
2202 * can be calculated as = bank * 4096 + n * 256
2203 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
2204 * The start index for the nth Hw sector can be calculated
2206 * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
2207 * (ich9 only, otherwise error condition)
2208 * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
2210 switch (hsfsts.hsf_status.berasesz) {
2212 /* Hw sector size 256 */
2213 sector_size = ICH_FLASH_SEG_SIZE_256;
2214 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
2217 sector_size = ICH_FLASH_SEG_SIZE_4K;
2221 sector_size = ICH_FLASH_SEG_SIZE_8K;
2225 sector_size = ICH_FLASH_SEG_SIZE_64K;
2229 return -E1000_ERR_NVM;
2232 /* Start with the base address, then add the sector offset. */
2233 flash_linear_addr = hw->nvm.flash_base_addr;
2234 flash_linear_addr += (bank) ? flash_bank_size : 0;
2236 for (j = 0; j < iteration ; j++) {
2239 ret_val = e1000_flash_cycle_init_ich8lan(hw);
2244 * Write a value 11 (block Erase) in Flash
2245 * Cycle field in hw flash control
2247 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2248 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
2249 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2252 * Write the last 24 bits of an index within the
2253 * block into Flash Linear address field in Flash
2256 flash_linear_addr += (j * sector_size);
2257 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2259 ret_val = e1000_flash_cycle_ich8lan(hw,
2260 ICH_FLASH_ERASE_COMMAND_TIMEOUT);
2265 * Check if FCERR is set to 1. If 1,
2266 * clear it and try the whole sequence
2267 * a few more times else Done
2269 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2270 if (hsfsts.hsf_status.flcerr == 1)
2271 /* repeat for some time before giving up */
2273 else if (hsfsts.hsf_status.flcdone == 0)
2275 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
2282 * e1000_valid_led_default_ich8lan - Set the default LED settings
2283 * @hw: pointer to the HW structure
2284 * @data: Pointer to the LED settings
2286 * Reads the LED default settings from the NVM to data. If the NVM LED
2287 * settings is all 0's or F's, set the LED default to a valid LED default
2290 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
2294 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
2296 e_dbg("NVM Read Error\n");
2300 if (*data == ID_LED_RESERVED_0000 ||
2301 *data == ID_LED_RESERVED_FFFF)
2302 *data = ID_LED_DEFAULT_ICH8LAN;
2308 * e1000_id_led_init_pchlan - store LED configurations
2309 * @hw: pointer to the HW structure
2311 * PCH does not control LEDs via the LEDCTL register, rather it uses
2312 * the PHY LED configuration register.
2314 * PCH also does not have an "always on" or "always off" mode which
2315 * complicates the ID feature. Instead of using the "on" mode to indicate
2316 * in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init()),
2317 * use "link_up" mode. The LEDs will still ID on request if there is no
2318 * link based on logic in e1000_led_[on|off]_pchlan().
2320 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
2322 struct e1000_mac_info *mac = &hw->mac;
2324 const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
2325 const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
2326 u16 data, i, temp, shift;
2328 /* Get default ID LED modes */
2329 ret_val = hw->nvm.ops.valid_led_default(hw, &data);
2333 mac->ledctl_default = er32(LEDCTL);
2334 mac->ledctl_mode1 = mac->ledctl_default;
2335 mac->ledctl_mode2 = mac->ledctl_default;
2337 for (i = 0; i < 4; i++) {
2338 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
2341 case ID_LED_ON1_DEF2:
2342 case ID_LED_ON1_ON2:
2343 case ID_LED_ON1_OFF2:
2344 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
2345 mac->ledctl_mode1 |= (ledctl_on << shift);
2347 case ID_LED_OFF1_DEF2:
2348 case ID_LED_OFF1_ON2:
2349 case ID_LED_OFF1_OFF2:
2350 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
2351 mac->ledctl_mode1 |= (ledctl_off << shift);
2358 case ID_LED_DEF1_ON2:
2359 case ID_LED_ON1_ON2:
2360 case ID_LED_OFF1_ON2:
2361 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
2362 mac->ledctl_mode2 |= (ledctl_on << shift);
2364 case ID_LED_DEF1_OFF2:
2365 case ID_LED_ON1_OFF2:
2366 case ID_LED_OFF1_OFF2:
2367 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
2368 mac->ledctl_mode2 |= (ledctl_off << shift);
2381 * e1000_get_bus_info_ich8lan - Get/Set the bus type and width
2382 * @hw: pointer to the HW structure
2384 * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
2385 * register, so the the bus width is hard coded.
2387 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
2389 struct e1000_bus_info *bus = &hw->bus;
2392 ret_val = e1000e_get_bus_info_pcie(hw);
2395 * ICH devices are "PCI Express"-ish. They have
2396 * a configuration space, but do not contain
2397 * PCI Express Capability registers, so bus width
2398 * must be hardcoded.
2400 if (bus->width == e1000_bus_width_unknown)
2401 bus->width = e1000_bus_width_pcie_x1;
2407 * e1000_reset_hw_ich8lan - Reset the hardware
2408 * @hw: pointer to the HW structure
2410 * Does a full reset of the hardware which includes a reset of the PHY and
2413 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
2415 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2421 * Prevent the PCI-E bus from sticking if there is no TLP connection
2422 * on the last TLP read/write transaction when MAC is reset.
2424 ret_val = e1000e_disable_pcie_master(hw);
2426 e_dbg("PCI-E Master disable polling has failed.\n");
2429 e_dbg("Masking off all interrupts\n");
2430 ew32(IMC, 0xffffffff);
2433 * Disable the Transmit and Receive units. Then delay to allow
2434 * any pending transactions to complete before we hit the MAC
2435 * with the global reset.
2438 ew32(TCTL, E1000_TCTL_PSP);
2443 /* Workaround for ICH8 bit corruption issue in FIFO memory */
2444 if (hw->mac.type == e1000_ich8lan) {
2445 /* Set Tx and Rx buffer allocation to 8k apiece. */
2446 ew32(PBA, E1000_PBA_8K);
2447 /* Set Packet Buffer Size to 16k. */
2448 ew32(PBS, E1000_PBS_16K);
2451 if (hw->mac.type == e1000_pchlan) {
2452 /* Save the NVM K1 bit setting*/
2453 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, ®);
2457 if (reg & E1000_NVM_K1_ENABLE)
2458 dev_spec->nvm_k1_enabled = true;
2460 dev_spec->nvm_k1_enabled = false;
2465 if (!e1000_check_reset_block(hw)) {
2466 /* Clear PHY Reset Asserted bit */
2467 if (hw->mac.type >= e1000_pchlan) {
2468 u32 status = er32(STATUS);
2469 ew32(STATUS, status & ~E1000_STATUS_PHYRA);
2473 * PHY HW reset requires MAC CORE reset at the same
2474 * time to make sure the interface between MAC and the
2475 * external PHY is reset.
2477 ctrl |= E1000_CTRL_PHY_RST;
2479 ret_val = e1000_acquire_swflag_ich8lan(hw);
2480 e_dbg("Issuing a global reset to ich8lan\n");
2481 ew32(CTRL, (ctrl | E1000_CTRL_RST));
2485 e1000_release_swflag_ich8lan(hw);
2487 if (ctrl & E1000_CTRL_PHY_RST)
2488 ret_val = hw->phy.ops.get_cfg_done(hw);
2490 if (hw->mac.type >= e1000_ich10lan) {
2491 e1000_lan_init_done_ich8lan(hw);
2493 ret_val = e1000e_get_auto_rd_done(hw);
2496 * When auto config read does not complete, do not
2497 * return with an error. This can happen in situations
2498 * where there is no eeprom and prevents getting link.
2500 e_dbg("Auto Read Done did not complete\n");
2503 /* Dummy read to clear the phy wakeup bit after lcd reset */
2504 if (hw->mac.type == e1000_pchlan)
2505 e1e_rphy(hw, BM_WUC, ®);
2507 ret_val = e1000_sw_lcd_config_ich8lan(hw);
2511 if (hw->mac.type == e1000_pchlan) {
2512 ret_val = e1000_oem_bits_config_ich8lan(hw, true);
2517 * For PCH, this write will make sure that any noise
2518 * will be detected as a CRC error and be dropped rather than show up
2519 * as a bad packet to the DMA engine.
2521 if (hw->mac.type == e1000_pchlan)
2522 ew32(CRC_OFFSET, 0x65656565);
2524 ew32(IMC, 0xffffffff);
2527 kab = er32(KABGTXD);
2528 kab |= E1000_KABGTXD_BGSQLBIAS;
2531 if (hw->mac.type == e1000_pchlan)
2532 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
2539 * e1000_init_hw_ich8lan - Initialize the hardware
2540 * @hw: pointer to the HW structure
2542 * Prepares the hardware for transmit and receive by doing the following:
2543 * - initialize hardware bits
2544 * - initialize LED identification
2545 * - setup receive address registers
2546 * - setup flow control
2547 * - setup transmit descriptors
2548 * - clear statistics
2550 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
2552 struct e1000_mac_info *mac = &hw->mac;
2553 u32 ctrl_ext, txdctl, snoop;
2557 e1000_initialize_hw_bits_ich8lan(hw);
2559 /* Initialize identification LED */
2560 ret_val = mac->ops.id_led_init(hw);
2562 e_dbg("Error initializing identification LED\n");
2563 /* This is not fatal and we should not stop init due to this */
2565 /* Setup the receive address. */
2566 e1000e_init_rx_addrs(hw, mac->rar_entry_count);
2568 /* Zero out the Multicast HASH table */
2569 e_dbg("Zeroing the MTA\n");
2570 for (i = 0; i < mac->mta_reg_count; i++)
2571 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
2574 * The 82578 Rx buffer will stall if wakeup is enabled in host and
2575 * the ME. Reading the BM_WUC register will clear the host wakeup bit.
2576 * Reset the phy after disabling host wakeup to reset the Rx buffer.
2578 if (hw->phy.type == e1000_phy_82578) {
2579 hw->phy.ops.read_reg(hw, BM_WUC, &i);
2580 ret_val = e1000_phy_hw_reset_ich8lan(hw);
2585 /* Setup link and flow control */
2586 ret_val = e1000_setup_link_ich8lan(hw);
2588 /* Set the transmit descriptor write-back policy for both queues */
2589 txdctl = er32(TXDCTL(0));
2590 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
2591 E1000_TXDCTL_FULL_TX_DESC_WB;
2592 txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
2593 E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
2594 ew32(TXDCTL(0), txdctl);
2595 txdctl = er32(TXDCTL(1));
2596 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
2597 E1000_TXDCTL_FULL_TX_DESC_WB;
2598 txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
2599 E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
2600 ew32(TXDCTL(1), txdctl);
2603 * ICH8 has opposite polarity of no_snoop bits.
2604 * By default, we should use snoop behavior.
2606 if (mac->type == e1000_ich8lan)
2607 snoop = PCIE_ICH8_SNOOP_ALL;
2609 snoop = (u32) ~(PCIE_NO_SNOOP_ALL);
2610 e1000e_set_pcie_no_snoop(hw, snoop);
2612 ctrl_ext = er32(CTRL_EXT);
2613 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
2614 ew32(CTRL_EXT, ctrl_ext);
2617 * Clear all of the statistics registers (clear on read). It is
2618 * important that we do this after we have tried to establish link
2619 * because the symbol error count will increment wildly if there
2622 e1000_clear_hw_cntrs_ich8lan(hw);
2627 * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
2628 * @hw: pointer to the HW structure
2630 * Sets/Clears required hardware bits necessary for correctly setting up the
2631 * hardware for transmit and receive.
2633 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
2637 /* Extended Device Control */
2638 reg = er32(CTRL_EXT);
2640 /* Enable PHY low-power state when MAC is at D3 w/o WoL */
2641 if (hw->mac.type >= e1000_pchlan)
2642 reg |= E1000_CTRL_EXT_PHYPDEN;
2643 ew32(CTRL_EXT, reg);
2645 /* Transmit Descriptor Control 0 */
2646 reg = er32(TXDCTL(0));
2648 ew32(TXDCTL(0), reg);
2650 /* Transmit Descriptor Control 1 */
2651 reg = er32(TXDCTL(1));
2653 ew32(TXDCTL(1), reg);
2655 /* Transmit Arbitration Control 0 */
2656 reg = er32(TARC(0));
2657 if (hw->mac.type == e1000_ich8lan)
2658 reg |= (1 << 28) | (1 << 29);
2659 reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
2662 /* Transmit Arbitration Control 1 */
2663 reg = er32(TARC(1));
2664 if (er32(TCTL) & E1000_TCTL_MULR)
2668 reg |= (1 << 24) | (1 << 26) | (1 << 30);
2672 if (hw->mac.type == e1000_ich8lan) {
2680 * e1000_setup_link_ich8lan - Setup flow control and link settings
2681 * @hw: pointer to the HW structure
2683 * Determines which flow control settings to use, then configures flow
2684 * control. Calls the appropriate media-specific link configuration
2685 * function. Assuming the adapter has a valid link partner, a valid link
2686 * should be established. Assumes the hardware has previously been reset
2687 * and the transmitter and receiver are not enabled.
2689 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
2693 if (e1000_check_reset_block(hw))
2697 * ICH parts do not have a word in the NVM to determine
2698 * the default flow control setting, so we explicitly
2701 if (hw->fc.requested_mode == e1000_fc_default) {
2702 /* Workaround h/w hang when Tx flow control enabled */
2703 if (hw->mac.type == e1000_pchlan)
2704 hw->fc.requested_mode = e1000_fc_rx_pause;
2706 hw->fc.requested_mode = e1000_fc_full;
2710 * Save off the requested flow control mode for use later. Depending
2711 * on the link partner's capabilities, we may or may not use this mode.
2713 hw->fc.current_mode = hw->fc.requested_mode;
2715 e_dbg("After fix-ups FlowControl is now = %x\n",
2716 hw->fc.current_mode);
2718 /* Continue to configure the copper link. */
2719 ret_val = e1000_setup_copper_link_ich8lan(hw);
2723 ew32(FCTTV, hw->fc.pause_time);
2724 if ((hw->phy.type == e1000_phy_82578) ||
2725 (hw->phy.type == e1000_phy_82577)) {
2726 ret_val = hw->phy.ops.write_reg(hw,
2727 PHY_REG(BM_PORT_CTRL_PAGE, 27),
2733 return e1000e_set_fc_watermarks(hw);
2737 * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
2738 * @hw: pointer to the HW structure
2740 * Configures the kumeran interface to the PHY to wait the appropriate time
2741 * when polling the PHY, then call the generic setup_copper_link to finish
2742 * configuring the copper link.
2744 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
2751 ctrl |= E1000_CTRL_SLU;
2752 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2756 * Set the mac to wait the maximum time between each iteration
2757 * and increase the max iterations when polling the phy;
2758 * this fixes erroneous timeouts at 10Mbps.
2760 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_TIMEOUTS, 0xFFFF);
2763 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
2768 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
2773 switch (hw->phy.type) {
2774 case e1000_phy_igp_3:
2775 ret_val = e1000e_copper_link_setup_igp(hw);
2780 case e1000_phy_82578:
2781 ret_val = e1000e_copper_link_setup_m88(hw);
2785 case e1000_phy_82577:
2786 ret_val = e1000_copper_link_setup_82577(hw);
2791 ret_val = hw->phy.ops.read_reg(hw, IFE_PHY_MDIX_CONTROL,
2796 reg_data &= ~IFE_PMC_AUTO_MDIX;
2798 switch (hw->phy.mdix) {
2800 reg_data &= ~IFE_PMC_FORCE_MDIX;
2803 reg_data |= IFE_PMC_FORCE_MDIX;
2807 reg_data |= IFE_PMC_AUTO_MDIX;
2810 ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_MDIX_CONTROL,
2818 return e1000e_setup_copper_link(hw);
2822 * e1000_get_link_up_info_ich8lan - Get current link speed and duplex
2823 * @hw: pointer to the HW structure
2824 * @speed: pointer to store current link speed
2825 * @duplex: pointer to store the current link duplex
2827 * Calls the generic get_speed_and_duplex to retrieve the current link
2828 * information and then calls the Kumeran lock loss workaround for links at
2831 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
2836 ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
2840 if ((hw->mac.type == e1000_ich8lan) &&
2841 (hw->phy.type == e1000_phy_igp_3) &&
2842 (*speed == SPEED_1000)) {
2843 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
2850 * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
2851 * @hw: pointer to the HW structure
2853 * Work-around for 82566 Kumeran PCS lock loss:
2854 * On link status change (i.e. PCI reset, speed change) and link is up and
2856 * 0) if workaround is optionally disabled do nothing
2857 * 1) wait 1ms for Kumeran link to come up
2858 * 2) check Kumeran Diagnostic register PCS lock loss bit
2859 * 3) if not set the link is locked (all is good), otherwise...
2861 * 5) repeat up to 10 times
2862 * Note: this is only called for IGP3 copper when speed is 1gb.
2864 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
2866 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2872 if (!dev_spec->kmrn_lock_loss_workaround_enabled)
2876 * Make sure link is up before proceeding. If not just return.
2877 * Attempting this while link is negotiating fouled up link
2880 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
2884 for (i = 0; i < 10; i++) {
2885 /* read once to clear */
2886 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
2889 /* and again to get new status */
2890 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
2894 /* check for PCS lock */
2895 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
2898 /* Issue PHY reset */
2899 e1000_phy_hw_reset(hw);
2902 /* Disable GigE link negotiation */
2903 phy_ctrl = er32(PHY_CTRL);
2904 phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
2905 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
2906 ew32(PHY_CTRL, phy_ctrl);
2909 * Call gig speed drop workaround on Gig disable before accessing
2912 e1000e_gig_downshift_workaround_ich8lan(hw);
2914 /* unable to acquire PCS lock */
2915 return -E1000_ERR_PHY;
2919 * e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
2920 * @hw: pointer to the HW structure
2921 * @state: boolean value used to set the current Kumeran workaround state
2923 * If ICH8, set the current Kumeran workaround state (enabled - true
2924 * /disabled - false).
2926 void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
2929 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2931 if (hw->mac.type != e1000_ich8lan) {
2932 e_dbg("Workaround applies to ICH8 only.\n");
2936 dev_spec->kmrn_lock_loss_workaround_enabled = state;
2940 * e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
2941 * @hw: pointer to the HW structure
2943 * Workaround for 82566 power-down on D3 entry:
2944 * 1) disable gigabit link
2945 * 2) write VR power-down enable
2947 * Continue if successful, else issue LCD reset and repeat
2949 void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
2955 if (hw->phy.type != e1000_phy_igp_3)
2958 /* Try the workaround twice (if needed) */
2961 reg = er32(PHY_CTRL);
2962 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
2963 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
2964 ew32(PHY_CTRL, reg);
2967 * Call gig speed drop workaround on Gig disable before
2968 * accessing any PHY registers
2970 if (hw->mac.type == e1000_ich8lan)
2971 e1000e_gig_downshift_workaround_ich8lan(hw);
2973 /* Write VR power-down enable */
2974 e1e_rphy(hw, IGP3_VR_CTRL, &data);
2975 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
2976 e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN);
2978 /* Read it back and test */
2979 e1e_rphy(hw, IGP3_VR_CTRL, &data);
2980 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
2981 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
2984 /* Issue PHY reset and repeat at most one more time */
2986 ew32(CTRL, reg | E1000_CTRL_PHY_RST);
2992 * e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
2993 * @hw: pointer to the HW structure
2995 * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
2996 * LPLU, Gig disable, MDIC PHY reset):
2997 * 1) Set Kumeran Near-end loopback
2998 * 2) Clear Kumeran Near-end loopback
2999 * Should only be called for ICH8[m] devices with IGP_3 Phy.
3001 void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
3006 if ((hw->mac.type != e1000_ich8lan) ||
3007 (hw->phy.type != e1000_phy_igp_3))
3010 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3014 reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
3015 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3019 reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
3020 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3025 * e1000e_disable_gig_wol_ich8lan - disable gig during WoL
3026 * @hw: pointer to the HW structure
3028 * During S0 to Sx transition, it is possible the link remains at gig
3029 * instead of negotiating to a lower speed. Before going to Sx, set
3030 * 'LPLU Enabled' and 'Gig Disable' to force link speed negotiation
3033 * Should only be called for applicable parts.
3035 void e1000e_disable_gig_wol_ich8lan(struct e1000_hw *hw)
3039 switch (hw->mac.type) {
3042 case e1000_ich10lan:
3044 phy_ctrl = er32(PHY_CTRL);
3045 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU |
3046 E1000_PHY_CTRL_GBE_DISABLE;
3047 ew32(PHY_CTRL, phy_ctrl);
3049 if (hw->mac.type == e1000_pchlan)
3050 e1000_phy_hw_reset_ich8lan(hw);
3059 * e1000_cleanup_led_ich8lan - Restore the default LED operation
3060 * @hw: pointer to the HW structure
3062 * Return the LED back to the default configuration.
3064 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
3066 if (hw->phy.type == e1000_phy_ife)
3067 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
3069 ew32(LEDCTL, hw->mac.ledctl_default);
3074 * e1000_led_on_ich8lan - Turn LEDs on
3075 * @hw: pointer to the HW structure
3079 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
3081 if (hw->phy.type == e1000_phy_ife)
3082 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
3083 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
3085 ew32(LEDCTL, hw->mac.ledctl_mode2);
3090 * e1000_led_off_ich8lan - Turn LEDs off
3091 * @hw: pointer to the HW structure
3093 * Turn off the LEDs.
3095 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
3097 if (hw->phy.type == e1000_phy_ife)
3098 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
3099 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
3101 ew32(LEDCTL, hw->mac.ledctl_mode1);
3106 * e1000_setup_led_pchlan - Configures SW controllable LED
3107 * @hw: pointer to the HW structure
3109 * This prepares the SW controllable LED for use.
3111 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
3113 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
3114 (u16)hw->mac.ledctl_mode1);
3118 * e1000_cleanup_led_pchlan - Restore the default LED operation
3119 * @hw: pointer to the HW structure
3121 * Return the LED back to the default configuration.
3123 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
3125 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
3126 (u16)hw->mac.ledctl_default);
3130 * e1000_led_on_pchlan - Turn LEDs on
3131 * @hw: pointer to the HW structure
3135 static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
3137 u16 data = (u16)hw->mac.ledctl_mode2;
3141 * If no link, then turn LED on by setting the invert bit
3142 * for each LED that's mode is "link_up" in ledctl_mode2.
3144 if (!(er32(STATUS) & E1000_STATUS_LU)) {
3145 for (i = 0; i < 3; i++) {
3146 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
3147 if ((led & E1000_PHY_LED0_MODE_MASK) !=
3148 E1000_LEDCTL_MODE_LINK_UP)
3150 if (led & E1000_PHY_LED0_IVRT)
3151 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
3153 data |= (E1000_PHY_LED0_IVRT << (i * 5));
3157 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
3161 * e1000_led_off_pchlan - Turn LEDs off
3162 * @hw: pointer to the HW structure
3164 * Turn off the LEDs.
3166 static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
3168 u16 data = (u16)hw->mac.ledctl_mode1;
3172 * If no link, then turn LED off by clearing the invert bit
3173 * for each LED that's mode is "link_up" in ledctl_mode1.
3175 if (!(er32(STATUS) & E1000_STATUS_LU)) {
3176 for (i = 0; i < 3; i++) {
3177 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
3178 if ((led & E1000_PHY_LED0_MODE_MASK) !=
3179 E1000_LEDCTL_MODE_LINK_UP)
3181 if (led & E1000_PHY_LED0_IVRT)
3182 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
3184 data |= (E1000_PHY_LED0_IVRT << (i * 5));
3188 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
3192 * e1000_get_cfg_done_ich8lan - Read config done bit
3193 * @hw: pointer to the HW structure
3195 * Read the management control register for the config done bit for
3196 * completion status. NOTE: silicon which is EEPROM-less will fail trying
3197 * to read the config done bit, so an error is *ONLY* logged and returns
3198 * 0. If we were to return with error, EEPROM-less silicon
3199 * would not be able to be reset or change link.
3201 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
3205 if (hw->mac.type >= e1000_pchlan) {
3206 u32 status = er32(STATUS);
3208 if (status & E1000_STATUS_PHYRA)
3209 ew32(STATUS, status & ~E1000_STATUS_PHYRA);
3211 e_dbg("PHY Reset Asserted not set - needs delay\n");
3214 e1000e_get_cfg_done(hw);
3216 /* If EEPROM is not marked present, init the IGP 3 PHY manually */
3217 if ((hw->mac.type != e1000_ich10lan) &&
3218 (hw->mac.type != e1000_pchlan)) {
3219 if (((er32(EECD) & E1000_EECD_PRES) == 0) &&
3220 (hw->phy.type == e1000_phy_igp_3)) {
3221 e1000e_phy_init_script_igp3(hw);
3224 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
3225 /* Maybe we should do a basic PHY config */
3226 e_dbg("EEPROM not present\n");
3227 return -E1000_ERR_CONFIG;
3235 * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
3236 * @hw: pointer to the HW structure
3238 * In the case of a PHY power down to save power, or to turn off link during a
3239 * driver unload, or wake on lan is not enabled, remove the link.
3241 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
3243 /* If the management interface is not enabled, then power down */
3244 if (!(hw->mac.ops.check_mng_mode(hw) ||
3245 hw->phy.ops.check_reset_block(hw)))
3246 e1000_power_down_phy_copper(hw);
3252 * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
3253 * @hw: pointer to the HW structure
3255 * Clears hardware counters specific to the silicon family and calls
3256 * clear_hw_cntrs_generic to clear all general purpose counters.
3258 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
3262 e1000e_clear_hw_cntrs_base(hw);
3278 /* Clear PHY statistics registers */
3279 if ((hw->phy.type == e1000_phy_82578) ||
3280 (hw->phy.type == e1000_phy_82577)) {
3281 hw->phy.ops.read_reg(hw, HV_SCC_UPPER, &phy_data);
3282 hw->phy.ops.read_reg(hw, HV_SCC_LOWER, &phy_data);
3283 hw->phy.ops.read_reg(hw, HV_ECOL_UPPER, &phy_data);
3284 hw->phy.ops.read_reg(hw, HV_ECOL_LOWER, &phy_data);
3285 hw->phy.ops.read_reg(hw, HV_MCC_UPPER, &phy_data);
3286 hw->phy.ops.read_reg(hw, HV_MCC_LOWER, &phy_data);
3287 hw->phy.ops.read_reg(hw, HV_LATECOL_UPPER, &phy_data);
3288 hw->phy.ops.read_reg(hw, HV_LATECOL_LOWER, &phy_data);
3289 hw->phy.ops.read_reg(hw, HV_COLC_UPPER, &phy_data);
3290 hw->phy.ops.read_reg(hw, HV_COLC_LOWER, &phy_data);
3291 hw->phy.ops.read_reg(hw, HV_DC_UPPER, &phy_data);
3292 hw->phy.ops.read_reg(hw, HV_DC_LOWER, &phy_data);
3293 hw->phy.ops.read_reg(hw, HV_TNCRS_UPPER, &phy_data);
3294 hw->phy.ops.read_reg(hw, HV_TNCRS_LOWER, &phy_data);
3298 static struct e1000_mac_operations ich8_mac_ops = {
3299 .id_led_init = e1000e_id_led_init,
3300 .check_mng_mode = e1000_check_mng_mode_ich8lan,
3301 .check_for_link = e1000_check_for_copper_link_ich8lan,
3302 /* cleanup_led dependent on mac type */
3303 .clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan,
3304 .get_bus_info = e1000_get_bus_info_ich8lan,
3305 .get_link_up_info = e1000_get_link_up_info_ich8lan,
3306 /* led_on dependent on mac type */
3307 /* led_off dependent on mac type */
3308 .update_mc_addr_list = e1000e_update_mc_addr_list_generic,
3309 .reset_hw = e1000_reset_hw_ich8lan,
3310 .init_hw = e1000_init_hw_ich8lan,
3311 .setup_link = e1000_setup_link_ich8lan,
3312 .setup_physical_interface= e1000_setup_copper_link_ich8lan,
3313 /* id_led_init dependent on mac type */
3316 static struct e1000_phy_operations ich8_phy_ops = {
3317 .acquire = e1000_acquire_swflag_ich8lan,
3318 .check_reset_block = e1000_check_reset_block_ich8lan,
3320 .get_cfg_done = e1000_get_cfg_done_ich8lan,
3321 .get_cable_length = e1000e_get_cable_length_igp_2,
3322 .read_reg = e1000e_read_phy_reg_igp,
3323 .release = e1000_release_swflag_ich8lan,
3324 .reset = e1000_phy_hw_reset_ich8lan,
3325 .set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan,
3326 .set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan,
3327 .write_reg = e1000e_write_phy_reg_igp,
3330 static struct e1000_nvm_operations ich8_nvm_ops = {
3331 .acquire = e1000_acquire_nvm_ich8lan,
3332 .read = e1000_read_nvm_ich8lan,
3333 .release = e1000_release_nvm_ich8lan,
3334 .update = e1000_update_nvm_checksum_ich8lan,
3335 .valid_led_default = e1000_valid_led_default_ich8lan,
3336 .validate = e1000_validate_nvm_checksum_ich8lan,
3337 .write = e1000_write_nvm_ich8lan,
3340 struct e1000_info e1000_ich8_info = {
3341 .mac = e1000_ich8lan,
3342 .flags = FLAG_HAS_WOL
3344 | FLAG_RX_CSUM_ENABLED
3345 | FLAG_HAS_CTRLEXT_ON_LOAD
3350 .max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN,
3351 .get_variants = e1000_get_variants_ich8lan,
3352 .mac_ops = &ich8_mac_ops,
3353 .phy_ops = &ich8_phy_ops,
3354 .nvm_ops = &ich8_nvm_ops,
3357 struct e1000_info e1000_ich9_info = {
3358 .mac = e1000_ich9lan,
3359 .flags = FLAG_HAS_JUMBO_FRAMES
3362 | FLAG_RX_CSUM_ENABLED
3363 | FLAG_HAS_CTRLEXT_ON_LOAD
3369 .max_hw_frame_size = DEFAULT_JUMBO,
3370 .get_variants = e1000_get_variants_ich8lan,
3371 .mac_ops = &ich8_mac_ops,
3372 .phy_ops = &ich8_phy_ops,
3373 .nvm_ops = &ich8_nvm_ops,
3376 struct e1000_info e1000_ich10_info = {
3377 .mac = e1000_ich10lan,
3378 .flags = FLAG_HAS_JUMBO_FRAMES
3381 | FLAG_RX_CSUM_ENABLED
3382 | FLAG_HAS_CTRLEXT_ON_LOAD
3388 .max_hw_frame_size = DEFAULT_JUMBO,
3389 .get_variants = e1000_get_variants_ich8lan,
3390 .mac_ops = &ich8_mac_ops,
3391 .phy_ops = &ich8_phy_ops,
3392 .nvm_ops = &ich8_nvm_ops,
3395 struct e1000_info e1000_pch_info = {
3396 .mac = e1000_pchlan,
3397 .flags = FLAG_IS_ICH
3399 | FLAG_RX_CSUM_ENABLED
3400 | FLAG_HAS_CTRLEXT_ON_LOAD
3403 | FLAG_HAS_JUMBO_FRAMES
3404 | FLAG_DISABLE_FC_PAUSE_TIME /* errata */
3407 .max_hw_frame_size = 4096,
3408 .get_variants = e1000_get_variants_ich8lan,
3409 .mac_ops = &ich8_mac_ops,
3410 .phy_ops = &ich8_phy_ops,
3411 .nvm_ops = &ich8_nvm_ops,