SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/net/bcm63xx_enet.c

   1 /*
   2  * Driver for BCM963xx builtin Ethernet mac
   3  *
   4  * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  19  */
  20 #include <linux/init.h>
  21 #include <linux/module.h>
  22 #include <linux/clk.h>
  23 #include <linux/etherdevice.h>
  24 #include <linux/delay.h>
  25 #include <linux/ethtool.h>
  26 #include <linux/crc32.h>
  27 #include <linux/err.h>
  28 #include <linux/dma-mapping.h>
  29 #include <linux/platform_device.h>
  30 #include <linux/if_vlan.h>
  31
  32 #include <bcm63xx_dev_enet.h>
  33 #include "bcm63xx_enet.h"
  34
  35 static char bcm_enet_driver_name[] = "bcm63xx_enet";
  36 static char bcm_enet_driver_version[] = "1.0";
  37
  38 static int copybreak __read_mostly = 128;
  39 module_param(copybreak, int, 0);
  40 MODULE_PARM_DESC(copybreak, "Receive copy threshold");
  41
  42 /* io memory shared between all devices */
  43 static void __iomem *bcm_enet_shared_base;
  44
  45 /*
  46  * io helpers to access mac registers
  47  */
  48 static inline u32 enet_readl(struct bcm_enet_priv *priv, u32 off)
  49 {
  50         return bcm_readl(priv->base + off);
  51 }
  52
  53 static inline void enet_writel(struct bcm_enet_priv *priv,
  54                                u32 val, u32 off)
  55 {
  56         bcm_writel(val, priv->base + off);
  57 }
  58
  59 /*
  60  * io helpers to access shared registers
  61  */
  62 static inline u32 enet_dma_readl(struct bcm_enet_priv *priv, u32 off)
  63 {
  64         return bcm_readl(bcm_enet_shared_base + off);
  65 }
  66
  67 static inline void enet_dma_writel(struct bcm_enet_priv *priv,
  68                                        u32 val, u32 off)
  69 {
  70         bcm_writel(val, bcm_enet_shared_base + off);
  71 }
  72
  73 /*
  74  * write given data into mii register and wait for transfer to end
  75  * with timeout (average measured transfer time is 25us)
  76  */
  77 static int do_mdio_op(struct bcm_enet_priv *priv, unsigned int data)
  78 {
  79         int limit;
  80
  81         /* make sure mii interrupt status is cleared */
  82         enet_writel(priv, ENET_IR_MII, ENET_IR_REG);
  83
  84         enet_writel(priv, data, ENET_MIIDATA_REG);
  85         wmb();
  86
  87         /* busy wait on mii interrupt bit, with timeout */
  88         limit = 1000;
  89         do {
  90                 if (enet_readl(priv, ENET_IR_REG) & ENET_IR_MII)
  91                         break;
  92                 udelay(1);
  93         } while (limit-- > 0);
  94
  95         return (limit < 0) ? 1 : 0;
  96 }
  97
  98 /*
  99  * MII internal read callback
 100  */
 101 static int bcm_enet_mdio_read(struct bcm_enet_priv *priv, int mii_id,
 102                               int regnum)
 103 {
 104         u32 tmp, val;
 105
 106         tmp = regnum << ENET_MIIDATA_REG_SHIFT;
 107         tmp |= 0x2 << ENET_MIIDATA_TA_SHIFT;
 108         tmp |= mii_id << ENET_MIIDATA_PHYID_SHIFT;
 109         tmp |= ENET_MIIDATA_OP_READ_MASK;
 110
 111         if (do_mdio_op(priv, tmp))
 112                 return -1;
 113
 114         val = enet_readl(priv, ENET_MIIDATA_REG);
 115         val &= 0xffff;
 116         return val;
 117 }
 118
 119 /*
 120  * MII internal write callback
 121  */
 122 static int bcm_enet_mdio_write(struct bcm_enet_priv *priv, int mii_id,
 123                                int regnum, u16 value)
 124 {
 125         u32 tmp;
 126
 127         tmp = (value & 0xffff) << ENET_MIIDATA_DATA_SHIFT;
 128         tmp |= 0x2 << ENET_MIIDATA_TA_SHIFT;
 129         tmp |= regnum << ENET_MIIDATA_REG_SHIFT;
 130         tmp |= mii_id << ENET_MIIDATA_PHYID_SHIFT;
 131         tmp |= ENET_MIIDATA_OP_WRITE_MASK;
 132
 133         (void)do_mdio_op(priv, tmp);
 134         return 0;
 135 }
 136
 137 /*
 138  * MII read callback from phylib
 139  */
 140 static int bcm_enet_mdio_read_phylib(struct mii_bus *bus, int mii_id,
 141                                      int regnum)
 142 {
 143         return bcm_enet_mdio_read(bus->priv, mii_id, regnum);
 144 }
 145
 146 /*
 147  * MII write callback from phylib
 148  */
 149 static int bcm_enet_mdio_write_phylib(struct mii_bus *bus, int mii_id,
 150                                       int regnum, u16 value)
 151 {
 152         return bcm_enet_mdio_write(bus->priv, mii_id, regnum, value);
 153 }
 154
 155 /*
 156  * MII read callback from mii core
 157  */
 158 static int bcm_enet_mdio_read_mii(struct net_device *dev, int mii_id,
 159                                   int regnum)
 160 {
 161         return bcm_enet_mdio_read(netdev_priv(dev), mii_id, regnum);
 162 }
 163
 164 /*
 165  * MII write callback from mii core
 166  */
 167 static void bcm_enet_mdio_write_mii(struct net_device *dev, int mii_id,
 168                                     int regnum, int value)
 169 {
 170         bcm_enet_mdio_write(netdev_priv(dev), mii_id, regnum, value);
 171 }
 172
 173 /*
 174  * refill rx queue
 175  */
 176 static int bcm_enet_refill_rx(struct net_device *dev)
 177 {
 178         struct bcm_enet_priv *priv;
 179
 180         priv = netdev_priv(dev);
 181
 182         while (priv->rx_desc_count < priv->rx_ring_size) {
 183                 struct bcm_enet_desc *desc;
 184                 struct sk_buff *skb;
 185                 dma_addr_t p;
 186                 int desc_idx;
 187                 u32 len_stat;
 188
 189                 desc_idx = priv->rx_dirty_desc;
 190                 desc = &priv->rx_desc_cpu[desc_idx];
 191
 192                 if (!priv->rx_skb[desc_idx]) {
 193                         skb = netdev_alloc_skb(dev, priv->rx_skb_size);
 194                         if (!skb)
 195                                 break;
 196                         priv->rx_skb[desc_idx] = skb;
 197
 198                         p = dma_map_single(&priv->pdev->dev, skb->data,
 199                                            priv->rx_skb_size,
 200                                            DMA_FROM_DEVICE);
 201                         desc->address = p;
 202                 }
 203
 204                 len_stat = priv->rx_skb_size << DMADESC_LENGTH_SHIFT;
 205                 len_stat |= DMADESC_OWNER_MASK;
 206                 if (priv->rx_dirty_desc == priv->rx_ring_size - 1) {
 207                         len_stat |= DMADESC_WRAP_MASK;
 208                         priv->rx_dirty_desc = 0;
 209                 } else {
 210                         priv->rx_dirty_desc++;
 211                 }
 212                 wmb();
 213                 desc->len_stat = len_stat;
 214
 215                 priv->rx_desc_count++;
 216
 217                 /* tell dma engine we allocated one buffer */
 218                 enet_dma_writel(priv, 1, ENETDMA_BUFALLOC_REG(priv->rx_chan));
 219         }
 220
 221         /* If rx ring is still empty, set a timer to try allocating
 222          * again at a later time. */
 223         if (priv->rx_desc_count == 0 && netif_running(dev)) {
 224                 dev_warn(&priv->pdev->dev, "unable to refill rx ring\n");
 225                 priv->rx_timeout.expires = jiffies + HZ;
 226                 add_timer(&priv->rx_timeout);
 227         }
 228
 229         return 0;
 230 }
 231
 232 /*
 233  * timer callback to defer refill rx queue in case we're OOM
 234  */
 235 static void bcm_enet_refill_rx_timer(unsigned long data)
 236 {
 237         struct net_device *dev;
 238         struct bcm_enet_priv *priv;
 239
 240         dev = (struct net_device *)data;
 241         priv = netdev_priv(dev);
 242
 243         spin_lock(&priv->rx_lock);
 244         bcm_enet_refill_rx((struct net_device *)data);
 245         spin_unlock(&priv->rx_lock);
 246 }
 247
 248 /*
 249  * extract packet from rx queue
 250  */
 251 static int bcm_enet_receive_queue(struct net_device *dev, int budget)
 252 {
 253         struct bcm_enet_priv *priv;
 254         struct device *kdev;
 255         int processed;
 256
 257         priv = netdev_priv(dev);
 258         kdev = &priv->pdev->dev;
 259         processed = 0;
 260
 261         /* don't scan ring further than number of refilled
 262          * descriptor */
 263         if (budget > priv->rx_desc_count)
 264                 budget = priv->rx_desc_count;
 265
 266         do {
 267                 struct bcm_enet_desc *desc;
 268                 struct sk_buff *skb;
 269                 int desc_idx;
 270                 u32 len_stat;
 271                 unsigned int len;
 272
 273                 desc_idx = priv->rx_curr_desc;
 274                 desc = &priv->rx_desc_cpu[desc_idx];
 275
 276                 /* make sure we actually read the descriptor status at
 277                  * each loop */
 278                 rmb();
 279
 280                 len_stat = desc->len_stat;
 281
 282                 /* break if dma ownership belongs to hw */
 283                 if (len_stat & DMADESC_OWNER_MASK)
 284                         break;
 285
 286                 processed++;
 287                 priv->rx_curr_desc++;
 288                 if (priv->rx_curr_desc == priv->rx_ring_size)
 289                         priv->rx_curr_desc = 0;
 290                 priv->rx_desc_count--;
 291
 292                 /* if the packet does not have start of packet _and_
 293                  * end of packet flag set, then just recycle it */
 294                 if ((len_stat & DMADESC_ESOP_MASK) != DMADESC_ESOP_MASK) {
 295                         priv->stats.rx_dropped++;
 296                         continue;
 297                 }
 298
 299                 /* recycle packet if it's marked as bad */
 300                 if (unlikely(len_stat & DMADESC_ERR_MASK)) {
 301                         priv->stats.rx_errors++;
 302
 303                         if (len_stat & DMADESC_OVSIZE_MASK)
 304                                 priv->stats.rx_length_errors++;
 305                         if (len_stat & DMADESC_CRC_MASK)
 306                                 priv->stats.rx_crc_errors++;
 307                         if (len_stat & DMADESC_UNDER_MASK)
 308                                 priv->stats.rx_frame_errors++;
 309                         if (len_stat & DMADESC_OV_MASK)
 310                                 priv->stats.rx_fifo_errors++;
 311                         continue;
 312                 }
 313
 314                 /* valid packet */
 315                 skb = priv->rx_skb[desc_idx];
 316                 len = (len_stat & DMADESC_LENGTH_MASK) >> DMADESC_LENGTH_SHIFT;
 317                 /* don't include FCS */
 318                 len -= 4;
 319
 320                 if (len < copybreak) {
 321                         struct sk_buff *nskb;
 322
 323                         nskb = netdev_alloc_skb_ip_align(dev, len);
 324                         if (!nskb) {
 325                                 /* forget packet, just rearm desc */
 326                                 priv->stats.rx_dropped++;
 327                                 continue;
 328                         }
 329
 330                         dma_sync_single_for_cpu(kdev, desc->address,
 331                                                 len, DMA_FROM_DEVICE);
 332                         memcpy(nskb->data, skb->data, len);
 333                         dma_sync_single_for_device(kdev, desc->address,
 334                                                    len, DMA_FROM_DEVICE);
 335                         skb = nskb;
 336                 } else {
 337                         dma_unmap_single(&priv->pdev->dev, desc->address,
 338                                          priv->rx_skb_size, DMA_FROM_DEVICE);
 339                         priv->rx_skb[desc_idx] = NULL;
 340                 }
 341
 342                 skb_put(skb, len);
 343                 skb->dev = dev;
 344                 skb->protocol = eth_type_trans(skb, dev);
 345                 priv->stats.rx_packets++;
 346                 priv->stats.rx_bytes += len;
 347                 dev->last_rx = jiffies;
 348                 netif_receive_skb(skb);
 349
 350         } while (--budget > 0);
 351
 352         if (processed || !priv->rx_desc_count) {
 353                 bcm_enet_refill_rx(dev);
 354
 355                 /* kick rx dma */
 356                 enet_dma_writel(priv, ENETDMA_CHANCFG_EN_MASK,
 357                                 ENETDMA_CHANCFG_REG(priv->rx_chan));
 358         }
 359
 360         return processed;
 361 }
 362
 363
 364 /*
 365  * try to or force reclaim of transmitted buffers
 366  */
 367 static int bcm_enet_tx_reclaim(struct net_device *dev, int force)
 368 {
 369         struct bcm_enet_priv *priv;
 370         int released;
 371
 372         priv = netdev_priv(dev);
 373         released = 0;
 374
 375         while (priv->tx_desc_count < priv->tx_ring_size) {
 376                 struct bcm_enet_desc *desc;
 377                 struct sk_buff *skb;
 378
 379                 /* We run in a bh and fight against start_xmit, which
 380                  * is called with bh disabled  */
 381                 spin_lock(&priv->tx_lock);
 382
 383                 desc = &priv->tx_desc_cpu[priv->tx_dirty_desc];
 384
 385                 if (!force && (desc->len_stat & DMADESC_OWNER_MASK)) {
 386                         spin_unlock(&priv->tx_lock);
 387                         break;
 388                 }
 389
 390                 /* ensure other field of the descriptor were not read
 391                  * before we checked ownership */
 392                 rmb();
 393
 394                 skb = priv->tx_skb[priv->tx_dirty_desc];
 395                 priv->tx_skb[priv->tx_dirty_desc] = NULL;
 396                 dma_unmap_single(&priv->pdev->dev, desc->address, skb->len,
 397                                  DMA_TO_DEVICE);
 398
 399                 priv->tx_dirty_desc++;
 400                 if (priv->tx_dirty_desc == priv->tx_ring_size)
 401                         priv->tx_dirty_desc = 0;
 402                 priv->tx_desc_count++;
 403
 404                 spin_unlock(&priv->tx_lock);
 405
 406                 if (desc->len_stat & DMADESC_UNDER_MASK)
 407                         priv->stats.tx_errors++;
 408
 409                 dev_kfree_skb(skb);
 410                 released++;
 411         }
 412
 413         if (netif_queue_stopped(dev) && released)
 414                 netif_wake_queue(dev);
 415
 416         return released;
 417 }
 418
 419 /*
 420  * poll func, called by network core
 421  */
 422 static int bcm_enet_poll(struct napi_struct *napi, int budget)
 423 {
 424         struct bcm_enet_priv *priv;
 425         struct net_device *dev;
 426         int tx_work_done, rx_work_done;
 427
 428         priv = container_of(napi, struct bcm_enet_priv, napi);
 429         dev = priv->net_dev;
 430
 431         /* ack interrupts */
 432         enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
 433                         ENETDMA_IR_REG(priv->rx_chan));
 434         enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
 435                         ENETDMA_IR_REG(priv->tx_chan));
 436
 437         /* reclaim sent skb */
 438         tx_work_done = bcm_enet_tx_reclaim(dev, 0);
 439
 440         spin_lock(&priv->rx_lock);
 441         rx_work_done = bcm_enet_receive_queue(dev, budget);
 442         spin_unlock(&priv->rx_lock);
 443
 444         if (rx_work_done >= budget || tx_work_done > 0) {
 445                 /* rx/tx queue is not yet empty/clean */
 446                 return rx_work_done;
 447         }
 448
 449         /* no more packet in rx/tx queue, remove device from poll
 450          * queue */
 451         napi_complete(napi);
 452
 453         /* restore rx/tx interrupt */
 454         enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
 455                         ENETDMA_IRMASK_REG(priv->rx_chan));
 456         enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
 457                         ENETDMA_IRMASK_REG(priv->tx_chan));
 458
 459         return rx_work_done;
 460 }
 461
 462 /*
 463  * mac interrupt handler
 464  */
 465 static irqreturn_t bcm_enet_isr_mac(int irq, void *dev_id)
 466 {
 467         struct net_device *dev;
 468         struct bcm_enet_priv *priv;
 469         u32 stat;
 470
 471         dev = dev_id;
 472         priv = netdev_priv(dev);
 473
 474         stat = enet_readl(priv, ENET_IR_REG);
 475         if (!(stat & ENET_IR_MIB))
 476                 return IRQ_NONE;
 477
 478         /* clear & mask interrupt */
 479         enet_writel(priv, ENET_IR_MIB, ENET_IR_REG);
 480         enet_writel(priv, 0, ENET_IRMASK_REG);
 481
 482         /* read mib registers in workqueue */
 483         schedule_work(&priv->mib_update_task);
 484
 485         return IRQ_HANDLED;
 486 }
 487
 488 /*
 489  * rx/tx dma interrupt handler
 490  */
 491 static irqreturn_t bcm_enet_isr_dma(int irq, void *dev_id)
 492 {
 493         struct net_device *dev;
 494         struct bcm_enet_priv *priv;
 495
 496         dev = dev_id;
 497         priv = netdev_priv(dev);
 498
 499         /* mask rx/tx interrupts */
 500         enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->rx_chan));
 501         enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->tx_chan));
 502
 503         napi_schedule(&priv->napi);
 504
 505         return IRQ_HANDLED;
 506 }
 507
 508 /*
 509  * tx request callback
 510  */
 511 static int bcm_enet_start_xmit(struct sk_buff *skb, struct net_device *dev)
 512 {
 513         struct bcm_enet_priv *priv;
 514         struct bcm_enet_desc *desc;
 515         u32 len_stat;
 516         int ret;
 517
 518         priv = netdev_priv(dev);
 519
 520         /* lock against tx reclaim */
 521         spin_lock(&priv->tx_lock);
 522
 523         /* make sure  the tx hw queue  is not full,  should not happen
 524          * since we stop queue before it's the case */
 525         if (unlikely(!priv->tx_desc_count)) {
 526                 netif_stop_queue(dev);
 527                 dev_err(&priv->pdev->dev, "xmit called with no tx desc "
 528                         "available?\n");
 529                 ret = NETDEV_TX_BUSY;
 530                 goto out_unlock;
 531         }
 532
 533         /* point to the next available desc */
 534         desc = &priv->tx_desc_cpu[priv->tx_curr_desc];
 535         priv->tx_skb[priv->tx_curr_desc] = skb;
 536
 537         /* fill descriptor */
 538         desc->address = dma_map_single(&priv->pdev->dev, skb->data, skb->len,
 539                                        DMA_TO_DEVICE);
 540
 541         len_stat = (skb->len << DMADESC_LENGTH_SHIFT) & DMADESC_LENGTH_MASK;
 542         len_stat |= DMADESC_ESOP_MASK |
 543                 DMADESC_APPEND_CRC |
 544                 DMADESC_OWNER_MASK;
 545
 546         priv->tx_curr_desc++;
 547         if (priv->tx_curr_desc == priv->tx_ring_size) {
 548                 priv->tx_curr_desc = 0;
 549                 len_stat |= DMADESC_WRAP_MASK;
 550         }
 551         priv->tx_desc_count--;
 552
 553         /* dma might be already polling, make sure we update desc
 554          * fields in correct order */
 555         wmb();
 556         desc->len_stat = len_stat;
 557         wmb();
 558
 559         /* kick tx dma */
 560         enet_dma_writel(priv, ENETDMA_CHANCFG_EN_MASK,
 561                         ENETDMA_CHANCFG_REG(priv->tx_chan));
 562
 563         /* stop queue if no more desc available */
 564         if (!priv->tx_desc_count)
 565                 netif_stop_queue(dev);
 566
 567         priv->stats.tx_bytes += skb->len;
 568         priv->stats.tx_packets++;
 569         dev->trans_start = jiffies;
 570         ret = NETDEV_TX_OK;
 571
 572 out_unlock:
 573         spin_unlock(&priv->tx_lock);
 574         return ret;
 575 }
 576
 577 /*
 578  * Change the interface's mac address.
 579  */
 580 static int bcm_enet_set_mac_address(struct net_device *dev, void *p)
 581 {
 582         struct bcm_enet_priv *priv;
 583         struct sockaddr *addr = p;
 584         u32 val;
 585
 586         priv = netdev_priv(dev);
 587         memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
 588
 589         /* use perfect match register 0 to store my mac address */
 590         val = (dev->dev_addr[2] << 24) | (dev->dev_addr[3] << 16) |
 591                 (dev->dev_addr[4] << 8) | dev->dev_addr[5];
 592         enet_writel(priv, val, ENET_PML_REG(0));
 593
 594         val = (dev->dev_addr[0] << 8 | dev->dev_addr[1]);
 595         val |= ENET_PMH_DATAVALID_MASK;
 596         enet_writel(priv, val, ENET_PMH_REG(0));
 597
 598         return 0;
 599 }
 600
 601 /*
 602  * Change rx mode (promiscous/allmulti) and update multicast list
 603  */
 604 static void bcm_enet_set_multicast_list(struct net_device *dev)
 605 {
 606         struct bcm_enet_priv *priv;
 607         struct dev_mc_list *mc_list;
 608         u32 val;
 609         int i;
 610
 611         priv = netdev_priv(dev);
 612
 613         val = enet_readl(priv, ENET_RXCFG_REG);
 614
 615         if (dev->flags & IFF_PROMISC)
 616                 val |= ENET_RXCFG_PROMISC_MASK;
 617         else
 618                 val &= ~ENET_RXCFG_PROMISC_MASK;
 619
 620         /* only 3 perfect match registers left, first one is used for
 621          * own mac address */
 622         if ((dev->flags & IFF_ALLMULTI) || dev->mc_count > 3)
 623                 val |= ENET_RXCFG_ALLMCAST_MASK;
 624         else
 625                 val &= ~ENET_RXCFG_ALLMCAST_MASK;
 626
 627         /* no need to set perfect match registers if we catch all
 628          * multicast */
 629         if (val & ENET_RXCFG_ALLMCAST_MASK) {
 630                 enet_writel(priv, val, ENET_RXCFG_REG);
 631                 return;
 632         }
 633
 634         for (i = 0, mc_list = dev->mc_list;
 635              (mc_list != NULL) && (i < dev->mc_count) && (i < 3);
 636              i++, mc_list = mc_list->next) {
 637                 u8 *dmi_addr;
 638                 u32 tmp;
 639
 640                 /* filter non ethernet address */
 641                 if (mc_list->dmi_addrlen != 6)
 642                         continue;
 643
 644                 /* update perfect match registers */
 645                 dmi_addr = mc_list->dmi_addr;
 646                 tmp = (dmi_addr[2] << 24) | (dmi_addr[3] << 16) |
 647                         (dmi_addr[4] << 8) | dmi_addr[5];
 648                 enet_writel(priv, tmp, ENET_PML_REG(i + 1));
 649
 650                 tmp = (dmi_addr[0] << 8 | dmi_addr[1]);
 651                 tmp |= ENET_PMH_DATAVALID_MASK;
 652                 enet_writel(priv, tmp, ENET_PMH_REG(i + 1));
 653         }
 654
 655         for (; i < 3; i++) {
 656                 enet_writel(priv, 0, ENET_PML_REG(i + 1));
 657                 enet_writel(priv, 0, ENET_PMH_REG(i + 1));
 658         }
 659
 660         enet_writel(priv, val, ENET_RXCFG_REG);
 661 }
 662
 663 /*
 664  * set mac duplex parameters
 665  */
 666 static void bcm_enet_set_duplex(struct bcm_enet_priv *priv, int fullduplex)
 667 {
 668         u32 val;
 669
 670         val = enet_readl(priv, ENET_TXCTL_REG);
 671         if (fullduplex)
 672                 val |= ENET_TXCTL_FD_MASK;
 673         else
 674                 val &= ~ENET_TXCTL_FD_MASK;
 675         enet_writel(priv, val, ENET_TXCTL_REG);
 676 }
 677
 678 /*
 679  * set mac flow control parameters
 680  */
 681 static void bcm_enet_set_flow(struct bcm_enet_priv *priv, int rx_en, int tx_en)
 682 {
 683         u32 val;
 684
 685         /* rx flow control (pause frame handling) */
 686         val = enet_readl(priv, ENET_RXCFG_REG);
 687         if (rx_en)
 688                 val |= ENET_RXCFG_ENFLOW_MASK;
 689         else
 690                 val &= ~ENET_RXCFG_ENFLOW_MASK;
 691         enet_writel(priv, val, ENET_RXCFG_REG);
 692
 693         /* tx flow control (pause frame generation) */
 694         val = enet_dma_readl(priv, ENETDMA_CFG_REG);
 695         if (tx_en)
 696                 val |= ENETDMA_CFG_FLOWCH_MASK(priv->rx_chan);
 697         else
 698                 val &= ~ENETDMA_CFG_FLOWCH_MASK(priv->rx_chan);
 699         enet_dma_writel(priv, val, ENETDMA_CFG_REG);
 700 }
 701
 702 /*
 703  * link changed callback (from phylib)
 704  */
 705 static void bcm_enet_adjust_phy_link(struct net_device *dev)
 706 {
 707         struct bcm_enet_priv *priv;
 708         struct phy_device *phydev;
 709         int status_changed;
 710
 711         priv = netdev_priv(dev);
 712         phydev = priv->phydev;
 713         status_changed = 0;
 714
 715         if (priv->old_link != phydev->link) {
 716                 status_changed = 1;
 717                 priv->old_link = phydev->link;
 718         }
 719
 720         /* reflect duplex change in mac configuration */
 721         if (phydev->link && phydev->duplex != priv->old_duplex) {
 722                 bcm_enet_set_duplex(priv,
 723                                     (phydev->duplex == DUPLEX_FULL) ? 1 : 0);
 724                 status_changed = 1;
 725                 priv->old_duplex = phydev->duplex;
 726         }
 727
 728         /* enable flow control if remote advertise it (trust phylib to
 729          * check that duplex is full */
 730         if (phydev->link && phydev->pause != priv->old_pause) {
 731                 int rx_pause_en, tx_pause_en;
 732
 733                 if (phydev->pause) {
 734                         /* pause was advertised by lpa and us */
 735                         rx_pause_en = 1;
 736                         tx_pause_en = 1;
 737                 } else if (!priv->pause_auto) {
 738                         /* pause setting overrided by user */
 739                         rx_pause_en = priv->pause_rx;
 740                         tx_pause_en = priv->pause_tx;
 741                 } else {
 742                         rx_pause_en = 0;
 743                         tx_pause_en = 0;
 744                 }
 745
 746                 bcm_enet_set_flow(priv, rx_pause_en, tx_pause_en);
 747                 status_changed = 1;
 748                 priv->old_pause = phydev->pause;
 749         }
 750
 751         if (status_changed) {
 752                 pr_info("%s: link %s", dev->name, phydev->link ?
 753                         "UP" : "DOWN");
 754                 if (phydev->link)
 755                         pr_cont(" - %d/%s - flow control %s", phydev->speed,
 756                                DUPLEX_FULL == phydev->duplex ? "full" : "half",
 757                                phydev->pause == 1 ? "rx&tx" : "off");
 758
 759                 pr_cont("\n");
 760         }
 761 }
 762
 763 /*
 764  * link changed callback (if phylib is not used)
 765  */
 766 static void bcm_enet_adjust_link(struct net_device *dev)
 767 {
 768         struct bcm_enet_priv *priv;
 769
 770         priv = netdev_priv(dev);
 771         bcm_enet_set_duplex(priv, priv->force_duplex_full);
 772         bcm_enet_set_flow(priv, priv->pause_rx, priv->pause_tx);
 773         netif_carrier_on(dev);
 774
 775         pr_info("%s: link forced UP - %d/%s - flow control %s/%s\n",
 776                 dev->name,
 777                 priv->force_speed_100 ? 100 : 10,
 778                 priv->force_duplex_full ? "full" : "half",
 779                 priv->pause_rx ? "rx" : "off",
 780                 priv->pause_tx ? "tx" : "off");
 781 }
 782
 783 /*
 784  * open callback, allocate dma rings & buffers and start rx operation
 785  */
 786 static int bcm_enet_open(struct net_device *dev)
 787 {
 788         struct bcm_enet_priv *priv;
 789         struct sockaddr addr;
 790         struct device *kdev;
 791         struct phy_device *phydev;
 792         int i, ret;
 793         unsigned int size;
 794         char phy_id[MII_BUS_ID_SIZE + 3];
 795         void *p;
 796         u32 val;
 797
 798         priv = netdev_priv(dev);
 799         kdev = &priv->pdev->dev;
 800
 801         if (priv->has_phy) {
 802                 /* connect to PHY */
 803                 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
 804                          priv->mac_id ? "1" : "0", priv->phy_id);
 805
 806                 phydev = phy_connect(dev, phy_id, &bcm_enet_adjust_phy_link, 0,
 807                                      PHY_INTERFACE_MODE_MII);
 808
 809                 if (IS_ERR(phydev)) {
 810                         dev_err(kdev, "could not attach to PHY\n");
 811                         return PTR_ERR(phydev);
 812                 }
 813
 814                 /* mask with MAC supported features */
 815                 phydev->supported &= (SUPPORTED_10baseT_Half |
 816                                       SUPPORTED_10baseT_Full |
 817                                       SUPPORTED_100baseT_Half |
 818                                       SUPPORTED_100baseT_Full |
 819                                       SUPPORTED_Autoneg |
 820                                       SUPPORTED_Pause |
 821                                       SUPPORTED_MII);
 822                 phydev->advertising = phydev->supported;
 823
 824                 if (priv->pause_auto && priv->pause_rx && priv->pause_tx)
 825                         phydev->advertising |= SUPPORTED_Pause;
 826                 else
 827                         phydev->advertising &= ~SUPPORTED_Pause;
 828
 829                 dev_info(kdev, "attached PHY at address %d [%s]\n",
 830                          phydev->addr, phydev->drv->name);
 831
 832                 priv->old_link = 0;
 833                 priv->old_duplex = -1;
 834                 priv->old_pause = -1;
 835                 priv->phydev = phydev;
 836         }
 837
 838         /* mask all interrupts and request them */
 839         enet_writel(priv, 0, ENET_IRMASK_REG);
 840         enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->rx_chan));
 841         enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->tx_chan));
 842
 843         ret = request_irq(dev->irq, bcm_enet_isr_mac, 0, dev->name, dev);
 844         if (ret)
 845                 goto out_phy_disconnect;
 846
 847         ret = request_irq(priv->irq_rx, bcm_enet_isr_dma,
 848                           IRQF_SAMPLE_RANDOM | IRQF_DISABLED, dev->name, dev);
 849         if (ret)
 850                 goto out_freeirq;
 851
 852         ret = request_irq(priv->irq_tx, bcm_enet_isr_dma,
 853                           IRQF_DISABLED, dev->name, dev);
 854         if (ret)
 855                 goto out_freeirq_rx;
 856
 857         /* initialize perfect match registers */
 858         for (i = 0; i < 4; i++) {
 859                 enet_writel(priv, 0, ENET_PML_REG(i));
 860                 enet_writel(priv, 0, ENET_PMH_REG(i));
 861         }
 862
 863         /* write device mac address */
 864         memcpy(addr.sa_data, dev->dev_addr, ETH_ALEN);
 865         bcm_enet_set_mac_address(dev, &addr);
 866
 867         /* allocate rx dma ring */
 868         size = priv->rx_ring_size * sizeof(struct bcm_enet_desc);
 869         p = dma_alloc_coherent(kdev, size, &priv->rx_desc_dma, GFP_KERNEL);
 870         if (!p) {
 871                 dev_err(kdev, "cannot allocate rx ring %u\n", size);
 872                 ret = -ENOMEM;
 873                 goto out_freeirq_tx;
 874         }
 875
 876         memset(p, 0, size);
 877         priv->rx_desc_alloc_size = size;
 878         priv->rx_desc_cpu = p;
 879
 880         /* allocate tx dma ring */
 881         size = priv->tx_ring_size * sizeof(struct bcm_enet_desc);
 882         p = dma_alloc_coherent(kdev, size, &priv->tx_desc_dma, GFP_KERNEL);
 883         if (!p) {
 884                 dev_err(kdev, "cannot allocate tx ring\n");
 885                 ret = -ENOMEM;
 886                 goto out_free_rx_ring;
 887         }
 888
 889         memset(p, 0, size);
 890         priv->tx_desc_alloc_size = size;
 891         priv->tx_desc_cpu = p;
 892
 893         priv->tx_skb = kzalloc(sizeof(struct sk_buff *) * priv->tx_ring_size,
 894                                GFP_KERNEL);
 895         if (!priv->tx_skb) {
 896                 dev_err(kdev, "cannot allocate rx skb queue\n");
 897                 ret = -ENOMEM;
 898                 goto out_free_tx_ring;
 899         }
 900
 901         priv->tx_desc_count = priv->tx_ring_size;
 902         priv->tx_dirty_desc = 0;
 903         priv->tx_curr_desc = 0;
 904         spin_lock_init(&priv->tx_lock);
 905
 906         /* init & fill rx ring with skbs */
 907         priv->rx_skb = kzalloc(sizeof(struct sk_buff *) * priv->rx_ring_size,
 908                                GFP_KERNEL);
 909         if (!priv->rx_skb) {
 910                 dev_err(kdev, "cannot allocate rx skb queue\n");
 911                 ret = -ENOMEM;
 912                 goto out_free_tx_skb;
 913         }
 914
 915         priv->rx_desc_count = 0;
 916         priv->rx_dirty_desc = 0;
 917         priv->rx_curr_desc = 0;
 918
 919         /* initialize flow control buffer allocation */
 920         enet_dma_writel(priv, ENETDMA_BUFALLOC_FORCE_MASK | 0,
 921                         ENETDMA_BUFALLOC_REG(priv->rx_chan));
 922
 923         if (bcm_enet_refill_rx(dev)) {
 924                 dev_err(kdev, "cannot allocate rx skb queue\n");
 925                 ret = -ENOMEM;
 926                 goto out;
 927         }
 928
 929         /* write rx & tx ring addresses */
 930         enet_dma_writel(priv, priv->rx_desc_dma,
 931                         ENETDMA_RSTART_REG(priv->rx_chan));
 932         enet_dma_writel(priv, priv->tx_desc_dma,
 933                         ENETDMA_RSTART_REG(priv->tx_chan));
 934
 935         /* clear remaining state ram for rx & tx channel */
 936         enet_dma_writel(priv, 0, ENETDMA_SRAM2_REG(priv->rx_chan));
 937         enet_dma_writel(priv, 0, ENETDMA_SRAM2_REG(priv->tx_chan));
 938         enet_dma_writel(priv, 0, ENETDMA_SRAM3_REG(priv->rx_chan));
 939         enet_dma_writel(priv, 0, ENETDMA_SRAM3_REG(priv->tx_chan));
 940         enet_dma_writel(priv, 0, ENETDMA_SRAM4_REG(priv->rx_chan));
 941         enet_dma_writel(priv, 0, ENETDMA_SRAM4_REG(priv->tx_chan));
 942
 943         /* set max rx/tx length */
 944         enet_writel(priv, priv->hw_mtu, ENET_RXMAXLEN_REG);
 945         enet_writel(priv, priv->hw_mtu, ENET_TXMAXLEN_REG);
 946
 947         /* set dma maximum burst len */
 948         enet_dma_writel(priv, BCMENET_DMA_MAXBURST,
 949                         ENETDMA_MAXBURST_REG(priv->rx_chan));
 950         enet_dma_writel(priv, BCMENET_DMA_MAXBURST,
 951                         ENETDMA_MAXBURST_REG(priv->tx_chan));
 952
 953         /* set correct transmit fifo watermark */
 954         enet_writel(priv, BCMENET_TX_FIFO_TRESH, ENET_TXWMARK_REG);
 955
 956         /* set flow control low/high threshold to 1/3 / 2/3 */
 957         val = priv->rx_ring_size / 3;
 958         enet_dma_writel(priv, val, ENETDMA_FLOWCL_REG(priv->rx_chan));
 959         val = (priv->rx_ring_size * 2) / 3;
 960         enet_dma_writel(priv, val, ENETDMA_FLOWCH_REG(priv->rx_chan));
 961
 962         /* all set, enable mac and interrupts, start dma engine and
 963          * kick rx dma channel */
 964         wmb();
 965         enet_writel(priv, ENET_CTL_ENABLE_MASK, ENET_CTL_REG);
 966         enet_dma_writel(priv, ENETDMA_CFG_EN_MASK, ENETDMA_CFG_REG);
 967         enet_dma_writel(priv, ENETDMA_CHANCFG_EN_MASK,
 968                         ENETDMA_CHANCFG_REG(priv->rx_chan));
 969
 970         /* watch "mib counters about to overflow" interrupt */
 971         enet_writel(priv, ENET_IR_MIB, ENET_IR_REG);
 972         enet_writel(priv, ENET_IR_MIB, ENET_IRMASK_REG);
 973
 974         /* watch "packet transferred" interrupt in rx and tx */
 975         enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
 976                         ENETDMA_IR_REG(priv->rx_chan));
 977         enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
 978                         ENETDMA_IR_REG(priv->tx_chan));
 979
 980         /* make sure we enable napi before rx interrupt  */
 981         napi_enable(&priv->napi);
 982
 983         enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
 984                         ENETDMA_IRMASK_REG(priv->rx_chan));
 985         enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
 986                         ENETDMA_IRMASK_REG(priv->tx_chan));
 987
 988         if (priv->has_phy)
 989                 phy_start(priv->phydev);
 990         else
 991                 bcm_enet_adjust_link(dev);
 992
 993         netif_start_queue(dev);
 994         return 0;
 995
 996 out:
 997         for (i = 0; i < priv->rx_ring_size; i++) {
 998                 struct bcm_enet_desc *desc;
 999
1000                 if (!priv->rx_skb[i])
1001                         continue;
1002
1003                 desc = &priv->rx_desc_cpu[i];
1004                 dma_unmap_single(kdev, desc->address, priv->rx_skb_size,
1005                                  DMA_FROM_DEVICE);
1006                 kfree_skb(priv->rx_skb[i]);
1007         }
1008         kfree(priv->rx_skb);
1009
1010 out_free_tx_skb:
1011         kfree(priv->tx_skb);
1012
1013 out_free_tx_ring:
1014         dma_free_coherent(kdev, priv->tx_desc_alloc_size,
1015                           priv->tx_desc_cpu, priv->tx_desc_dma);
1016
1017 out_free_rx_ring:
1018         dma_free_coherent(kdev, priv->rx_desc_alloc_size,
1019                           priv->rx_desc_cpu, priv->rx_desc_dma);
1020
1021 out_freeirq_tx:
1022         free_irq(priv->irq_tx, dev);
1023
1024 out_freeirq_rx:
1025         free_irq(priv->irq_rx, dev);
1026
1027 out_freeirq:
1028         free_irq(dev->irq, dev);
1029
1030 out_phy_disconnect:
1031         phy_disconnect(priv->phydev);
1032
1033         return ret;
1034 }
1035
1036 /*
1037  * disable mac
1038  */
1039 static void bcm_enet_disable_mac(struct bcm_enet_priv *priv)
1040 {
1041         int limit;
1042         u32 val;
1043
1044         val = enet_readl(priv, ENET_CTL_REG);
1045         val |= ENET_CTL_DISABLE_MASK;
1046         enet_writel(priv, val, ENET_CTL_REG);
1047
1048         limit = 1000;
1049         do {
1050                 u32 val;
1051
1052                 val = enet_readl(priv, ENET_CTL_REG);
1053                 if (!(val & ENET_CTL_DISABLE_MASK))
1054                         break;
1055                 udelay(1);
1056         } while (limit--);
1057 }
1058
1059 /*
1060  * disable dma in given channel
1061  */
1062 static void bcm_enet_disable_dma(struct bcm_enet_priv *priv, int chan)
1063 {
1064         int limit;
1065
1066         enet_dma_writel(priv, 0, ENETDMA_CHANCFG_REG(chan));
1067
1068         limit = 1000;
1069         do {
1070                 u32 val;
1071
1072                 val = enet_dma_readl(priv, ENETDMA_CHANCFG_REG(chan));
1073                 if (!(val & ENETDMA_CHANCFG_EN_MASK))
1074                         break;
1075                 udelay(1);
1076         } while (limit--);
1077 }
1078
1079 /*
1080  * stop callback
1081  */
1082 static int bcm_enet_stop(struct net_device *dev)
1083 {
1084         struct bcm_enet_priv *priv;
1085         struct device *kdev;
1086         int i;
1087
1088         priv = netdev_priv(dev);
1089         kdev = &priv->pdev->dev;
1090
1091         netif_stop_queue(dev);
1092         napi_disable(&priv->napi);
1093         if (priv->has_phy)
1094                 phy_stop(priv->phydev);
1095         del_timer_sync(&priv->rx_timeout);
1096
1097         /* mask all interrupts */
1098         enet_writel(priv, 0, ENET_IRMASK_REG);
1099         enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->rx_chan));
1100         enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->tx_chan));
1101
1102         /* make sure no mib update is scheduled */
1103         flush_scheduled_work();
1104
1105         /* disable dma & mac */
1106         bcm_enet_disable_dma(priv, priv->tx_chan);
1107         bcm_enet_disable_dma(priv, priv->rx_chan);
1108         bcm_enet_disable_mac(priv);
1109
1110         /* force reclaim of all tx buffers */
1111         bcm_enet_tx_reclaim(dev, 1);
1112
1113         /* free the rx skb ring */
1114         for (i = 0; i < priv->rx_ring_size; i++) {
1115                 struct bcm_enet_desc *desc;
1116
1117                 if (!priv->rx_skb[i])
1118                         continue;
1119
1120                 desc = &priv->rx_desc_cpu[i];
1121                 dma_unmap_single(kdev, desc->address, priv->rx_skb_size,
1122                                  DMA_FROM_DEVICE);
1123                 kfree_skb(priv->rx_skb[i]);
1124         }
1125
1126         /* free remaining allocated memory */
1127         kfree(priv->rx_skb);
1128         kfree(priv->tx_skb);
1129         dma_free_coherent(kdev, priv->rx_desc_alloc_size,
1130                           priv->rx_desc_cpu, priv->rx_desc_dma);
1131         dma_free_coherent(kdev, priv->tx_desc_alloc_size,
1132                           priv->tx_desc_cpu, priv->tx_desc_dma);
1133         free_irq(priv->irq_tx, dev);
1134         free_irq(priv->irq_rx, dev);
1135         free_irq(dev->irq, dev);
1136
1137         /* release phy */
1138         if (priv->has_phy) {
1139                 phy_disconnect(priv->phydev);
1140                 priv->phydev = NULL;
1141         }
1142
1143         return 0;
1144 }
1145
1146 /*
1147  * core request to return device rx/tx stats
1148  */
1149 static struct net_device_stats *bcm_enet_get_stats(struct net_device *dev)
1150 {
1151         struct bcm_enet_priv *priv;
1152
1153         priv = netdev_priv(dev);
1154         return &priv->stats;
1155 }
1156
1157 /*
1158  * ethtool callbacks
1159  */
1160 struct bcm_enet_stats {
1161         char stat_string[ETH_GSTRING_LEN];
1162         int sizeof_stat;
1163         int stat_offset;
1164         int mib_reg;
1165 };
1166
1167 #define GEN_STAT(m) sizeof(((struct bcm_enet_priv *)0)->m),             \
1168                      offsetof(struct bcm_enet_priv, m)
1169
1170 static const struct bcm_enet_stats bcm_enet_gstrings_stats[] = {
1171         { "rx_packets", GEN_STAT(stats.rx_packets), -1 },
1172         { "tx_packets", GEN_STAT(stats.tx_packets), -1 },
1173         { "rx_bytes", GEN_STAT(stats.rx_bytes), -1 },
1174         { "tx_bytes", GEN_STAT(stats.tx_bytes), -1 },
1175         { "rx_errors", GEN_STAT(stats.rx_errors), -1 },
1176         { "tx_errors", GEN_STAT(stats.tx_errors), -1 },
1177         { "rx_dropped", GEN_STAT(stats.rx_dropped), -1 },
1178         { "tx_dropped", GEN_STAT(stats.tx_dropped), -1 },
1179
1180         { "rx_good_octets", GEN_STAT(mib.rx_gd_octets), ETH_MIB_RX_GD_OCTETS},
1181         { "rx_good_pkts", GEN_STAT(mib.rx_gd_pkts), ETH_MIB_RX_GD_PKTS },
1182         { "rx_broadcast", GEN_STAT(mib.rx_brdcast), ETH_MIB_RX_BRDCAST },
1183         { "rx_multicast", GEN_STAT(mib.rx_mult), ETH_MIB_RX_MULT },
1184         { "rx_64_octets", GEN_STAT(mib.rx_64), ETH_MIB_RX_64 },
1185         { "rx_65_127_oct", GEN_STAT(mib.rx_65_127), ETH_MIB_RX_65_127 },
1186         { "rx_128_255_oct", GEN_STAT(mib.rx_128_255), ETH_MIB_RX_128_255 },
1187         { "rx_256_511_oct", GEN_STAT(mib.rx_256_511), ETH_MIB_RX_256_511 },
1188         { "rx_512_1023_oct", GEN_STAT(mib.rx_512_1023), ETH_MIB_RX_512_1023 },
1189         { "rx_1024_max_oct", GEN_STAT(mib.rx_1024_max), ETH_MIB_RX_1024_MAX },
1190         { "rx_jabber", GEN_STAT(mib.rx_jab), ETH_MIB_RX_JAB },
1191         { "rx_oversize", GEN_STAT(mib.rx_ovr), ETH_MIB_RX_OVR },
1192         { "rx_fragment", GEN_STAT(mib.rx_frag), ETH_MIB_RX_FRAG },
1193         { "rx_dropped", GEN_STAT(mib.rx_drop), ETH_MIB_RX_DROP },
1194         { "rx_crc_align", GEN_STAT(mib.rx_crc_align), ETH_MIB_RX_CRC_ALIGN },
1195         { "rx_undersize", GEN_STAT(mib.rx_und), ETH_MIB_RX_UND },
1196         { "rx_crc", GEN_STAT(mib.rx_crc), ETH_MIB_RX_CRC },
1197         { "rx_align", GEN_STAT(mib.rx_align), ETH_MIB_RX_ALIGN },
1198         { "rx_symbol_error", GEN_STAT(mib.rx_sym), ETH_MIB_RX_SYM },
1199         { "rx_pause", GEN_STAT(mib.rx_pause), ETH_MIB_RX_PAUSE },
1200         { "rx_control", GEN_STAT(mib.rx_cntrl), ETH_MIB_RX_CNTRL },
1201
1202         { "tx_good_octets", GEN_STAT(mib.tx_gd_octets), ETH_MIB_TX_GD_OCTETS },
1203         { "tx_good_pkts", GEN_STAT(mib.tx_gd_pkts), ETH_MIB_TX_GD_PKTS },
1204         { "tx_broadcast", GEN_STAT(mib.tx_brdcast), ETH_MIB_TX_BRDCAST },
1205         { "tx_multicast", GEN_STAT(mib.tx_mult), ETH_MIB_TX_MULT },
1206         { "tx_64_oct", GEN_STAT(mib.tx_64), ETH_MIB_TX_64 },
1207         { "tx_65_127_oct", GEN_STAT(mib.tx_65_127), ETH_MIB_TX_65_127 },
1208         { "tx_128_255_oct", GEN_STAT(mib.tx_128_255), ETH_MIB_TX_128_255 },
1209         { "tx_256_511_oct", GEN_STAT(mib.tx_256_511), ETH_MIB_TX_256_511 },
1210         { "tx_512_1023_oct", GEN_STAT(mib.tx_512_1023), ETH_MIB_TX_512_1023},
1211         { "tx_1024_max_oct", GEN_STAT(mib.tx_1024_max), ETH_MIB_TX_1024_MAX },
1212         { "tx_jabber", GEN_STAT(mib.tx_jab), ETH_MIB_TX_JAB },
1213         { "tx_oversize", GEN_STAT(mib.tx_ovr), ETH_MIB_TX_OVR },
1214         { "tx_fragment", GEN_STAT(mib.tx_frag), ETH_MIB_TX_FRAG },
1215         { "tx_underrun", GEN_STAT(mib.tx_underrun), ETH_MIB_TX_UNDERRUN },
1216         { "tx_collisions", GEN_STAT(mib.tx_col), ETH_MIB_TX_COL },
1217         { "tx_single_collision", GEN_STAT(mib.tx_1_col), ETH_MIB_TX_1_COL },
1218         { "tx_multiple_collision", GEN_STAT(mib.tx_m_col), ETH_MIB_TX_M_COL },
1219         { "tx_excess_collision", GEN_STAT(mib.tx_ex_col), ETH_MIB_TX_EX_COL },
1220         { "tx_late_collision", GEN_STAT(mib.tx_late), ETH_MIB_TX_LATE },
1221         { "tx_deferred", GEN_STAT(mib.tx_def), ETH_MIB_TX_DEF },
1222         { "tx_carrier_sense", GEN_STAT(mib.tx_crs), ETH_MIB_TX_CRS },
1223         { "tx_pause", GEN_STAT(mib.tx_pause), ETH_MIB_TX_PAUSE },
1224
1225 };
1226
1227 #define BCM_ENET_STATS_LEN      \
1228         (sizeof(bcm_enet_gstrings_stats) / sizeof(struct bcm_enet_stats))
1229
1230 static const u32 unused_mib_regs[] = {
1231         ETH_MIB_TX_ALL_OCTETS,
1232         ETH_MIB_TX_ALL_PKTS,
1233         ETH_MIB_RX_ALL_OCTETS,
1234         ETH_MIB_RX_ALL_PKTS,
1235 };
1236
1237
1238 static void bcm_enet_get_drvinfo(struct net_device *netdev,
1239                                  struct ethtool_drvinfo *drvinfo)
1240 {
1241         strncpy(drvinfo->driver, bcm_enet_driver_name, 32);
1242         strncpy(drvinfo->version, bcm_enet_driver_version, 32);
1243         strncpy(drvinfo->fw_version, "N/A", 32);
1244         strncpy(drvinfo->bus_info, "bcm63xx", 32);
1245         drvinfo->n_stats = BCM_ENET_STATS_LEN;
1246 }
1247
1248 static int bcm_enet_get_sset_count(struct net_device *netdev,
1249                                         int string_set)
1250 {
1251         switch (string_set) {
1252         case ETH_SS_STATS:
1253                 return BCM_ENET_STATS_LEN;
1254         default:
1255                 return -EINVAL;
1256         }
1257 }
1258
1259 static void bcm_enet_get_strings(struct net_device *netdev,
1260                                  u32 stringset, u8 *data)
1261 {
1262         int i;
1263
1264         switch (stringset) {
1265         case ETH_SS_STATS:
1266                 for (i = 0; i < BCM_ENET_STATS_LEN; i++) {
1267                         memcpy(data + i * ETH_GSTRING_LEN,
1268                                bcm_enet_gstrings_stats[i].stat_string,
1269                                ETH_GSTRING_LEN);
1270                 }
1271                 break;
1272         }
1273 }
1274
1275 static void update_mib_counters(struct bcm_enet_priv *priv)
1276 {
1277         int i;
1278
1279         for (i = 0; i < BCM_ENET_STATS_LEN; i++) {
1280                 const struct bcm_enet_stats *s;
1281                 u32 val;
1282                 char *p;
1283
1284                 s = &bcm_enet_gstrings_stats[i];
1285                 if (s->mib_reg == -1)
1286                         continue;
1287
1288                 val = enet_readl(priv, ENET_MIB_REG(s->mib_reg));
1289                 p = (char *)priv + s->stat_offset;
1290
1291                 if (s->sizeof_stat == sizeof(u64))
1292                         *(u64 *)p += val;
1293                 else
1294                         *(u32 *)p += val;
1295         }
1296
1297         /* also empty unused mib counters to make sure mib counter
1298          * overflow interrupt is cleared */
1299         for (i = 0; i < ARRAY_SIZE(unused_mib_regs); i++)
1300                 (void)enet_readl(priv, ENET_MIB_REG(unused_mib_regs[i]));
1301 }
1302
1303 static void bcm_enet_update_mib_counters_defer(struct work_struct *t)
1304 {
1305         struct bcm_enet_priv *priv;
1306
1307         priv = container_of(t, struct bcm_enet_priv, mib_update_task);
1308         mutex_lock(&priv->mib_update_lock);
1309         update_mib_counters(priv);
1310         mutex_unlock(&priv->mib_update_lock);
1311
1312         /* reenable mib interrupt */
1313         if (netif_running(priv->net_dev))
1314                 enet_writel(priv, ENET_IR_MIB, ENET_IRMASK_REG);
1315 }
1316
1317 static void bcm_enet_get_ethtool_stats(struct net_device *netdev,
1318                                        struct ethtool_stats *stats,
1319                                        u64 *data)
1320 {
1321         struct bcm_enet_priv *priv;
1322         int i;
1323
1324         priv = netdev_priv(netdev);
1325
1326         mutex_lock(&priv->mib_update_lock);
1327         update_mib_counters(priv);
1328
1329         for (i = 0; i < BCM_ENET_STATS_LEN; i++) {
1330                 const struct bcm_enet_stats *s;
1331                 char *p;
1332
1333                 s = &bcm_enet_gstrings_stats[i];
1334                 p = (char *)priv + s->stat_offset;
1335                 data[i] = (s->sizeof_stat == sizeof(u64)) ?
1336                         *(u64 *)p : *(u32 *)p;
1337         }
1338         mutex_unlock(&priv->mib_update_lock);
1339 }
1340
1341 static int bcm_enet_get_settings(struct net_device *dev,
1342                                  struct ethtool_cmd *cmd)
1343 {
1344         struct bcm_enet_priv *priv;
1345
1346         priv = netdev_priv(dev);
1347
1348         cmd->maxrxpkt = 0;
1349         cmd->maxtxpkt = 0;
1350
1351         if (priv->has_phy) {
1352                 if (!priv->phydev)
1353                         return -ENODEV;
1354                 return phy_ethtool_gset(priv->phydev, cmd);
1355         } else {
1356                 cmd->autoneg = 0;
1357                 cmd->speed = (priv->force_speed_100) ? SPEED_100 : SPEED_10;
1358                 cmd->duplex = (priv->force_duplex_full) ?
1359                         DUPLEX_FULL : DUPLEX_HALF;
1360                 cmd->supported = ADVERTISED_10baseT_Half  |
1361                         ADVERTISED_10baseT_Full |
1362                         ADVERTISED_100baseT_Half |
1363                         ADVERTISED_100baseT_Full;
1364                 cmd->advertising = 0;
1365                 cmd->port = PORT_MII;
1366                 cmd->transceiver = XCVR_EXTERNAL;
1367         }
1368         return 0;
1369 }
1370
1371 static int bcm_enet_set_settings(struct net_device *dev,
1372                                  struct ethtool_cmd *cmd)
1373 {
1374         struct bcm_enet_priv *priv;
1375
1376         priv = netdev_priv(dev);
1377         if (priv->has_phy) {
1378                 if (!priv->phydev)
1379                         return -ENODEV;
1380                 return phy_ethtool_sset(priv->phydev, cmd);
1381         } else {
1382
1383                 if (cmd->autoneg ||
1384                     (cmd->speed != SPEED_100 && cmd->speed != SPEED_10) ||
1385                     cmd->port != PORT_MII)
1386                         return -EINVAL;
1387
1388                 priv->force_speed_100 = (cmd->speed == SPEED_100) ? 1 : 0;
1389                 priv->force_duplex_full = (cmd->duplex == DUPLEX_FULL) ? 1 : 0;
1390
1391                 if (netif_running(dev))
1392                         bcm_enet_adjust_link(dev);
1393                 return 0;
1394         }
1395 }
1396
1397 static void bcm_enet_get_ringparam(struct net_device *dev,
1398                                    struct ethtool_ringparam *ering)
1399 {
1400         struct bcm_enet_priv *priv;
1401
1402         priv = netdev_priv(dev);
1403
1404         /* rx/tx ring is actually only limited by memory */
1405         ering->rx_max_pending = 8192;
1406         ering->tx_max_pending = 8192;
1407         ering->rx_mini_max_pending = 0;
1408         ering->rx_jumbo_max_pending = 0;
1409         ering->rx_pending = priv->rx_ring_size;
1410         ering->tx_pending = priv->tx_ring_size;
1411 }
1412
1413 static int bcm_enet_set_ringparam(struct net_device *dev,
1414                                   struct ethtool_ringparam *ering)
1415 {
1416         struct bcm_enet_priv *priv;
1417         int was_running;
1418
1419         priv = netdev_priv(dev);
1420
1421         was_running = 0;
1422         if (netif_running(dev)) {
1423                 bcm_enet_stop(dev);
1424                 was_running = 1;
1425         }
1426
1427         priv->rx_ring_size = ering->rx_pending;
1428         priv->tx_ring_size = ering->tx_pending;
1429
1430         if (was_running) {
1431                 int err;
1432
1433                 err = bcm_enet_open(dev);
1434                 if (err)
1435                         dev_close(dev);
1436                 else
1437                         bcm_enet_set_multicast_list(dev);
1438         }
1439         return 0;
1440 }
1441
1442 static void bcm_enet_get_pauseparam(struct net_device *dev,
1443                                     struct ethtool_pauseparam *ecmd)
1444 {
1445         struct bcm_enet_priv *priv;
1446
1447         priv = netdev_priv(dev);
1448         ecmd->autoneg = priv->pause_auto;
1449         ecmd->rx_pause = priv->pause_rx;
1450         ecmd->tx_pause = priv->pause_tx;
1451 }
1452
1453 static int bcm_enet_set_pauseparam(struct net_device *dev,
1454                                    struct ethtool_pauseparam *ecmd)
1455 {
1456         struct bcm_enet_priv *priv;
1457
1458         priv = netdev_priv(dev);
1459
1460         if (priv->has_phy) {
1461                 if (ecmd->autoneg && (ecmd->rx_pause != ecmd->tx_pause)) {
1462                         /* asymetric pause mode not supported,
1463                          * actually possible but integrated PHY has RO
1464                          * asym_pause bit */
1465                         return -EINVAL;
1466                 }
1467         } else {
1468                 /* no pause autoneg on direct mii connection */
1469                 if (ecmd->autoneg)
1470                         return -EINVAL;
1471         }
1472
1473         priv->pause_auto = ecmd->autoneg;
1474         priv->pause_rx = ecmd->rx_pause;
1475         priv->pause_tx = ecmd->tx_pause;
1476
1477         return 0;
1478 }
1479
1480 static struct ethtool_ops bcm_enet_ethtool_ops = {
1481         .get_strings            = bcm_enet_get_strings,
1482         .get_sset_count         = bcm_enet_get_sset_count,
1483         .get_ethtool_stats      = bcm_enet_get_ethtool_stats,
1484         .get_settings           = bcm_enet_get_settings,
1485         .set_settings           = bcm_enet_set_settings,
1486         .get_drvinfo            = bcm_enet_get_drvinfo,
1487         .get_link               = ethtool_op_get_link,
1488         .get_ringparam          = bcm_enet_get_ringparam,
1489         .set_ringparam          = bcm_enet_set_ringparam,
1490         .get_pauseparam         = bcm_enet_get_pauseparam,
1491         .set_pauseparam         = bcm_enet_set_pauseparam,
1492 };
1493
1494 static int bcm_enet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1495 {
1496         struct bcm_enet_priv *priv;
1497
1498         priv = netdev_priv(dev);
1499         if (priv->has_phy) {
1500                 if (!priv->phydev)
1501                         return -ENODEV;
1502                 return phy_mii_ioctl(priv->phydev, if_mii(rq), cmd);
1503         } else {
1504                 struct mii_if_info mii;
1505
1506                 mii.dev = dev;
1507                 mii.mdio_read = bcm_enet_mdio_read_mii;
1508                 mii.mdio_write = bcm_enet_mdio_write_mii;
1509                 mii.phy_id = 0;
1510                 mii.phy_id_mask = 0x3f;
1511                 mii.reg_num_mask = 0x1f;
1512                 return generic_mii_ioctl(&mii, if_mii(rq), cmd, NULL);
1513         }
1514 }
1515
1516 /*
1517  * calculate actual hardware mtu
1518  */
1519 static int compute_hw_mtu(struct bcm_enet_priv *priv, int mtu)
1520 {
1521         int actual_mtu;
1522
1523         actual_mtu = mtu;
1524
1525         /* add ethernet header + vlan tag size */
1526         actual_mtu += VLAN_ETH_HLEN;
1527
1528         if (actual_mtu < 64 || actual_mtu > BCMENET_MAX_MTU)
1529                 return -EINVAL;
1530
1531         /*
1532          * setup maximum size before we get overflow mark in
1533          * descriptor, note that this will not prevent reception of
1534          * big frames, they will be split into multiple buffers
1535          * anyway
1536          */
1537         priv->hw_mtu = actual_mtu;
1538
1539         /*
1540          * align rx buffer size to dma burst len, account FCS since
1541          * it's appended
1542          */
1543         priv->rx_skb_size = ALIGN(actual_mtu + ETH_FCS_LEN,
1544                                   BCMENET_DMA_MAXBURST * 4);
1545         return 0;
1546 }
1547
1548 /*
1549  * adjust mtu, can't be called while device is running
1550  */
1551 static int bcm_enet_change_mtu(struct net_device *dev, int new_mtu)
1552 {
1553         int ret;
1554
1555         if (netif_running(dev))
1556                 return -EBUSY;
1557
1558         ret = compute_hw_mtu(netdev_priv(dev), new_mtu);
1559         if (ret)
1560                 return ret;
1561         dev->mtu = new_mtu;
1562         return 0;
1563 }
1564
1565 /*
1566  * preinit hardware to allow mii operation while device is down
1567  */
1568 static void bcm_enet_hw_preinit(struct bcm_enet_priv *priv)
1569 {
1570         u32 val;
1571         int limit;
1572
1573         /* make sure mac is disabled */
1574         bcm_enet_disable_mac(priv);
1575
1576         /* soft reset mac */
1577         val = ENET_CTL_SRESET_MASK;
1578         enet_writel(priv, val, ENET_CTL_REG);
1579         wmb();
1580
1581         limit = 1000;
1582         do {
1583                 val = enet_readl(priv, ENET_CTL_REG);
1584                 if (!(val & ENET_CTL_SRESET_MASK))
1585                         break;
1586                 udelay(1);
1587         } while (limit--);
1588
1589         /* select correct mii interface */
1590         val = enet_readl(priv, ENET_CTL_REG);
1591         if (priv->use_external_mii)
1592                 val |= ENET_CTL_EPHYSEL_MASK;
1593         else
1594                 val &= ~ENET_CTL_EPHYSEL_MASK;
1595         enet_writel(priv, val, ENET_CTL_REG);
1596
1597         /* turn on mdc clock */
1598         enet_writel(priv, (0x1f << ENET_MIISC_MDCFREQDIV_SHIFT) |
1599                     ENET_MIISC_PREAMBLEEN_MASK, ENET_MIISC_REG);
1600
1601         /* set mib counters to self-clear when read */
1602         val = enet_readl(priv, ENET_MIBCTL_REG);
1603         val |= ENET_MIBCTL_RDCLEAR_MASK;
1604         enet_writel(priv, val, ENET_MIBCTL_REG);
1605 }
1606
1607 static const struct net_device_ops bcm_enet_ops = {
1608         .ndo_open               = bcm_enet_open,
1609         .ndo_stop               = bcm_enet_stop,
1610         .ndo_start_xmit         = bcm_enet_start_xmit,
1611         .ndo_get_stats          = bcm_enet_get_stats,
1612         .ndo_set_mac_address    = bcm_enet_set_mac_address,
1613         .ndo_set_multicast_list = bcm_enet_set_multicast_list,
1614         .ndo_do_ioctl           = bcm_enet_ioctl,
1615         .ndo_change_mtu         = bcm_enet_change_mtu,
1616 #ifdef CONFIG_NET_POLL_CONTROLLER
1617         .ndo_poll_controller = bcm_enet_netpoll,
1618 #endif
1619 };
1620
1621 /*
1622  * allocate netdevice, request register memory and register device.
1623  */
1624 static int __devinit bcm_enet_probe(struct platform_device *pdev)
1625 {
1626         struct bcm_enet_priv *priv;
1627         struct net_device *dev;
1628         struct bcm63xx_enet_platform_data *pd;
1629         struct resource *res_mem, *res_irq, *res_irq_rx, *res_irq_tx;
1630         struct mii_bus *bus;
1631         const char *clk_name;
1632         unsigned int iomem_size;
1633         int i, ret;
1634
1635         /* stop if shared driver failed, assume driver->probe will be
1636          * called in the same order we register devices (correct ?) */
1637         if (!bcm_enet_shared_base)
1638                 return -ENODEV;
1639
1640         res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1641         res_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1642         res_irq_rx = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
1643         res_irq_tx = platform_get_resource(pdev, IORESOURCE_IRQ, 2);
1644         if (!res_mem || !res_irq || !res_irq_rx || !res_irq_tx)
1645                 return -ENODEV;
1646
1647         ret = 0;
1648         dev = alloc_etherdev(sizeof(*priv));
1649         if (!dev)
1650                 return -ENOMEM;
1651         priv = netdev_priv(dev);
1652         memset(priv, 0, sizeof(*priv));
1653
1654         ret = compute_hw_mtu(priv, dev->mtu);
1655         if (ret)
1656                 goto out;
1657
1658         iomem_size = res_mem->end - res_mem->start + 1;
1659         if (!request_mem_region(res_mem->start, iomem_size, "bcm63xx_enet")) {
1660                 ret = -EBUSY;
1661                 goto out;
1662         }
1663
1664         priv->base = ioremap(res_mem->start, iomem_size);
1665         if (priv->base == NULL) {
1666                 ret = -ENOMEM;
1667                 goto out_release_mem;
1668         }
1669         dev->irq = priv->irq = res_irq->start;
1670         priv->irq_rx = res_irq_rx->start;
1671         priv->irq_tx = res_irq_tx->start;
1672         priv->mac_id = pdev->id;
1673
1674         /* get rx & tx dma channel id for this mac */
1675         if (priv->mac_id == 0) {
1676                 priv->rx_chan = 0;
1677                 priv->tx_chan = 1;
1678                 clk_name = "enet0";
1679         } else {
1680                 priv->rx_chan = 2;
1681                 priv->tx_chan = 3;
1682                 clk_name = "enet1";
1683         }
1684
1685         priv->mac_clk = clk_get(&pdev->dev, clk_name);
1686         if (IS_ERR(priv->mac_clk)) {
1687                 ret = PTR_ERR(priv->mac_clk);
1688                 goto out_unmap;
1689         }
1690         clk_enable(priv->mac_clk);
1691
1692         /* initialize default and fetch platform data */
1693         priv->rx_ring_size = BCMENET_DEF_RX_DESC;
1694         priv->tx_ring_size = BCMENET_DEF_TX_DESC;
1695
1696         pd = pdev->dev.platform_data;
1697         if (pd) {
1698                 memcpy(dev->dev_addr, pd->mac_addr, ETH_ALEN);
1699                 priv->has_phy = pd->has_phy;
1700                 priv->phy_id = pd->phy_id;
1701                 priv->has_phy_interrupt = pd->has_phy_interrupt;
1702                 priv->phy_interrupt = pd->phy_interrupt;
1703                 priv->use_external_mii = !pd->use_internal_phy;
1704                 priv->pause_auto = pd->pause_auto;
1705                 priv->pause_rx = pd->pause_rx;
1706                 priv->pause_tx = pd->pause_tx;
1707                 priv->force_duplex_full = pd->force_duplex_full;
1708                 priv->force_speed_100 = pd->force_speed_100;
1709         }
1710
1711         if (priv->mac_id == 0 && priv->has_phy && !priv->use_external_mii) {
1712                 /* using internal PHY, enable clock */
1713                 priv->phy_clk = clk_get(&pdev->dev, "ephy");
1714                 if (IS_ERR(priv->phy_clk)) {
1715                         ret = PTR_ERR(priv->phy_clk);
1716                         priv->phy_clk = NULL;
1717                         goto out_put_clk_mac;
1718                 }
1719                 clk_enable(priv->phy_clk);
1720         }
1721
1722         /* do minimal hardware init to be able to probe mii bus */
1723         bcm_enet_hw_preinit(priv);
1724
1725         /* MII bus registration */
1726         if (priv->has_phy) {
1727
1728                 priv->mii_bus = mdiobus_alloc();
1729                 if (!priv->mii_bus) {
1730                         ret = -ENOMEM;
1731                         goto out_uninit_hw;
1732                 }
1733
1734                 bus = priv->mii_bus;
1735                 bus->name = "bcm63xx_enet MII bus";
1736                 bus->parent = &pdev->dev;
1737                 bus->priv = priv;
1738                 bus->read = bcm_enet_mdio_read_phylib;
1739                 bus->write = bcm_enet_mdio_write_phylib;
1740                 sprintf(bus->id, "%d", priv->mac_id);
1741
1742                 /* only probe bus where we think the PHY is, because
1743                  * the mdio read operation return 0 instead of 0xffff
1744                  * if a slave is not present on hw */
1745                 bus->phy_mask = ~(1 << priv->phy_id);
1746
1747                 bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
1748                 if (!bus->irq) {
1749                         ret = -ENOMEM;
1750                         goto out_free_mdio;
1751                 }
1752
1753                 if (priv->has_phy_interrupt)
1754                         bus->irq[priv->phy_id] = priv->phy_interrupt;
1755                 else
1756                         bus->irq[priv->phy_id] = PHY_POLL;
1757
1758                 ret = mdiobus_register(bus);
1759                 if (ret) {
1760                         dev_err(&pdev->dev, "unable to register mdio bus\n");
1761                         goto out_free_mdio;
1762                 }
1763         } else {
1764
1765                 /* run platform code to initialize PHY device */
1766                 if (pd->mii_config &&
1767                     pd->mii_config(dev, 1, bcm_enet_mdio_read_mii,
1768                                    bcm_enet_mdio_write_mii)) {
1769                         dev_err(&pdev->dev, "unable to configure mdio bus\n");
1770                         goto out_uninit_hw;
1771                 }
1772         }
1773
1774         spin_lock_init(&priv->rx_lock);
1775
1776         /* init rx timeout (used for oom) */
1777         init_timer(&priv->rx_timeout);
1778         priv->rx_timeout.function = bcm_enet_refill_rx_timer;
1779         priv->rx_timeout.data = (unsigned long)dev;
1780
1781         /* init the mib update lock&work */
1782         mutex_init(&priv->mib_update_lock);
1783         INIT_WORK(&priv->mib_update_task, bcm_enet_update_mib_counters_defer);
1784
1785         /* zero mib counters */
1786         for (i = 0; i < ENET_MIB_REG_COUNT; i++)
1787                 enet_writel(priv, 0, ENET_MIB_REG(i));
1788
1789         /* register netdevice */
1790         dev->netdev_ops = &bcm_enet_ops;
1791         netif_napi_add(dev, &priv->napi, bcm_enet_poll, 16);
1792
1793         SET_ETHTOOL_OPS(dev, &bcm_enet_ethtool_ops);
1794         SET_NETDEV_DEV(dev, &pdev->dev);
1795
1796         ret = register_netdev(dev);
1797         if (ret)
1798                 goto out_unregister_mdio;
1799
1800         netif_carrier_off(dev);
1801         platform_set_drvdata(pdev, dev);
1802         priv->pdev = pdev;
1803         priv->net_dev = dev;
1804
1805         return 0;
1806
1807 out_unregister_mdio:
1808         if (priv->mii_bus) {
1809                 mdiobus_unregister(priv->mii_bus);
1810                 kfree(priv->mii_bus->irq);
1811         }
1812
1813 out_free_mdio:
1814         if (priv->mii_bus)
1815                 mdiobus_free(priv->mii_bus);
1816
1817 out_uninit_hw:
1818         /* turn off mdc clock */
1819         enet_writel(priv, 0, ENET_MIISC_REG);
1820         if (priv->phy_clk) {
1821                 clk_disable(priv->phy_clk);
1822                 clk_put(priv->phy_clk);
1823         }
1824
1825 out_put_clk_mac:
1826         clk_disable(priv->mac_clk);
1827         clk_put(priv->mac_clk);
1828
1829 out_unmap:
1830         iounmap(priv->base);
1831
1832 out_release_mem:
1833         release_mem_region(res_mem->start, iomem_size);
1834 out:
1835         free_netdev(dev);
1836         return ret;
1837 }
1838
1839
1840 /*
1841  * exit func, stops hardware and unregisters netdevice
1842  */
1843 static int __devexit bcm_enet_remove(struct platform_device *pdev)
1844 {
1845         struct bcm_enet_priv *priv;
1846         struct net_device *dev;
1847         struct resource *res;
1848
1849         /* stop netdevice */
1850         dev = platform_get_drvdata(pdev);
1851         priv = netdev_priv(dev);
1852         unregister_netdev(dev);
1853
1854         /* turn off mdc clock */
1855         enet_writel(priv, 0, ENET_MIISC_REG);
1856
1857         if (priv->has_phy) {
1858                 mdiobus_unregister(priv->mii_bus);
1859                 kfree(priv->mii_bus->irq);
1860                 mdiobus_free(priv->mii_bus);
1861         } else {
1862                 struct bcm63xx_enet_platform_data *pd;
1863
1864                 pd = pdev->dev.platform_data;
1865                 if (pd && pd->mii_config)
1866                         pd->mii_config(dev, 0, bcm_enet_mdio_read_mii,
1867                                        bcm_enet_mdio_write_mii);
1868         }
1869
1870         /* release device resources */
1871         iounmap(priv->base);
1872         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1873         release_mem_region(res->start, res->end - res->start + 1);
1874
1875         /* disable hw block clocks */
1876         if (priv->phy_clk) {
1877                 clk_disable(priv->phy_clk);
1878                 clk_put(priv->phy_clk);
1879         }
1880         clk_disable(priv->mac_clk);
1881         clk_put(priv->mac_clk);
1882
1883         platform_set_drvdata(pdev, NULL);
1884         free_netdev(dev);
1885         return 0;
1886 }
1887
1888 struct platform_driver bcm63xx_enet_driver = {
1889         .probe  = bcm_enet_probe,
1890         .remove = __devexit_p(bcm_enet_remove),
1891         .driver = {
1892                 .name   = "bcm63xx_enet",
1893                 .owner  = THIS_MODULE,
1894         },
1895 };
1896
1897 /*
1898  * reserve & remap memory space shared between all macs
1899  */
1900 static int __devinit bcm_enet_shared_probe(struct platform_device *pdev)
1901 {
1902         struct resource *res;
1903         unsigned int iomem_size;
1904
1905         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1906         if (!res)
1907                 return -ENODEV;
1908
1909         iomem_size = res->end - res->start + 1;
1910         if (!request_mem_region(res->start, iomem_size, "bcm63xx_enet_dma"))
1911                 return -EBUSY;
1912
1913         bcm_enet_shared_base = ioremap(res->start, iomem_size);
1914         if (!bcm_enet_shared_base) {
1915                 release_mem_region(res->start, iomem_size);
1916                 return -ENOMEM;
1917         }
1918         return 0;
1919 }
1920
1921 static int __devexit bcm_enet_shared_remove(struct platform_device *pdev)
1922 {
1923         struct resource *res;
1924
1925         iounmap(bcm_enet_shared_base);
1926         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1927         release_mem_region(res->start, res->end - res->start + 1);
1928         return 0;
1929 }
1930
1931 /*
1932  * this "shared" driver is needed because both macs share a single
1933  * address space
1934  */
1935 struct platform_driver bcm63xx_enet_shared_driver = {
1936         .probe  = bcm_enet_shared_probe,
1937         .remove = __devexit_p(bcm_enet_shared_remove),
1938         .driver = {
1939                 .name   = "bcm63xx_enet_shared",
1940                 .owner  = THIS_MODULE,
1941         },
1942 };
1943
1944 /*
1945  * entry point
1946  */
1947 static int __init bcm_enet_init(void)
1948 {
1949         int ret;
1950
1951         ret = platform_driver_register(&bcm63xx_enet_shared_driver);
1952         if (ret)
1953                 return ret;
1954
1955         ret = platform_driver_register(&bcm63xx_enet_driver);
1956         if (ret)
1957                 platform_driver_unregister(&bcm63xx_enet_shared_driver);
1958
1959         return ret;
1960 }
1961
1962 static void __exit bcm_enet_exit(void)
1963 {
1964         platform_driver_unregister(&bcm63xx_enet_driver);
1965         platform_driver_unregister(&bcm63xx_enet_shared_driver);
1966 }
1967
1968
1969 module_init(bcm_enet_init);
1970 module_exit(bcm_enet_exit);
1971
1972 MODULE_DESCRIPTION("BCM63xx internal ethernet mac driver");
1973 MODULE_AUTHOR("Maxime Bizon <mbizon@freebox.fr>");
1974 MODULE_LICENSE("GPL");