1 /* 8139cp.c: A Linux PCI Ethernet driver for the RealTek 8139C+ chips. */
3 Copyright 2001-2004 Jeff Garzik <jgarzik@pobox.com>
5 Copyright (C) 2001, 2002 David S. Miller (davem@redhat.com) [tg3.c]
6 Copyright (C) 2000, 2001 David S. Miller (davem@redhat.com) [sungem.c]
7 Copyright 2001 Manfred Spraul [natsemi.c]
8 Copyright 1999-2001 by Donald Becker. [natsemi.c]
9 Written 1997-2001 by Donald Becker. [8139too.c]
10 Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>. [acenic.c]
12 This software may be used and distributed according to the terms of
13 the GNU General Public License (GPL), incorporated herein by reference.
14 Drivers based on or derived from this code fall under the GPL and must
15 retain the authorship, copyright and license notice. This file is not
16 a complete program and may only be used when the entire operating
17 system is licensed under the GPL.
19 See the file COPYING in this distribution for more information.
23 Wake-on-LAN support - Felipe Damasio <felipewd@terra.com.br>
24 PCI suspend/resume - Felipe Damasio <felipewd@terra.com.br>
25 LinkChg interrupt - Felipe Damasio <felipewd@terra.com.br>
28 * Test Tx checksumming thoroughly
29 * Implement dev->tx_timeout
32 * Complete reset on PciErr
33 * Consider Rx interrupt mitigation using TimerIntr
34 * Investigate using skb->priority with h/w VLAN priority
35 * Investigate using High Priority Tx Queue with skb->priority
36 * Adjust Rx FIFO threshold and Max Rx DMA burst on Rx FIFO error
37 * Adjust Tx FIFO threshold and Max Tx DMA burst on Tx FIFO error
38 * Implement Tx software interrupt mitigation via
40 * The real minimum of CP_MIN_MTU is 4 bytes. However,
41 for this to be supported, one must(?) turn on packet padding.
42 * Support external MII transceivers (patch available)
45 * TX checksumming is considered experimental. It is off by
46 default, use ethtool to turn it on.
50 #define DRV_NAME "8139cp"
51 #define DRV_VERSION "1.2"
52 #define DRV_RELDATE "Mar 22, 2004"
55 #include <linux/config.h>
56 #include <linux/module.h>
57 #include <linux/kernel.h>
58 #include <linux/compiler.h>
59 #include <linux/netdevice.h>
60 #include <linux/etherdevice.h>
61 #include <linux/init.h>
62 #include <linux/pci.h>
63 #include <linux/delay.h>
64 #include <linux/ethtool.h>
65 #include <linux/mii.h>
66 #include <linux/if_vlan.h>
67 #include <linux/crc32.h>
70 #include <linux/tcp.h>
71 #include <linux/udp.h>
72 #include <linux/cache.h>
75 #include <asm/uaccess.h>
77 /* VLAN tagging feature enable/disable */
78 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
79 #define CP_VLAN_TAG_USED 1
80 #define CP_VLAN_TX_TAG(tx_desc,vlan_tag_value) \
81 do { (tx_desc)->opts2 = (vlan_tag_value); } while (0)
83 #define CP_VLAN_TAG_USED 0
84 #define CP_VLAN_TX_TAG(tx_desc,vlan_tag_value) \
85 do { (tx_desc)->opts2 = 0; } while (0)
88 /* These identify the driver base version and may not be removed. */
89 static char version[] =
90 KERN_INFO DRV_NAME ": 10/100 PCI Ethernet driver v" DRV_VERSION " (" DRV_RELDATE ")\n";
92 MODULE_AUTHOR("Jeff Garzik <jgarzik@pobox.com>");
93 MODULE_DESCRIPTION("RealTek RTL-8139C+ series 10/100 PCI Ethernet driver");
94 MODULE_LICENSE("GPL");
96 static int debug = -1;
97 MODULE_PARM (debug, "i");
98 MODULE_PARM_DESC (debug, "8139cp: bitmapped message enable number");
100 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
101 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
102 static int multicast_filter_limit = 32;
103 MODULE_PARM (multicast_filter_limit, "i");
104 MODULE_PARM_DESC (multicast_filter_limit, "8139cp: maximum number of filtered multicast addresses");
106 #define PFX DRV_NAME ": "
110 #define TRUE (!FALSE)
113 #define CP_DEF_MSG_ENABLE (NETIF_MSG_DRV | \
116 #define CP_NUM_STATS 14 /* struct cp_dma_stats, plus one */
117 #define CP_STATS_SIZE 64 /* size in bytes of DMA stats block */
118 #define CP_REGS_SIZE (0xff + 1)
119 #define CP_REGS_VER 1 /* version 1 */
120 #define CP_RX_RING_SIZE 64
121 #define CP_TX_RING_SIZE 64
122 #define CP_RING_BYTES \
123 ((sizeof(struct cp_desc) * CP_RX_RING_SIZE) + \
124 (sizeof(struct cp_desc) * CP_TX_RING_SIZE) + \
126 #define NEXT_TX(N) (((N) + 1) & (CP_TX_RING_SIZE - 1))
127 #define NEXT_RX(N) (((N) + 1) & (CP_RX_RING_SIZE - 1))
128 #define TX_BUFFS_AVAIL(CP) \
129 (((CP)->tx_tail <= (CP)->tx_head) ? \
130 (CP)->tx_tail + (CP_TX_RING_SIZE - 1) - (CP)->tx_head : \
131 (CP)->tx_tail - (CP)->tx_head - 1)
133 #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
135 #define CP_INTERNAL_PHY 32
137 /* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024, 7==end of packet. */
138 #define RX_FIFO_THRESH 5 /* Rx buffer level before first PCI xfer. */
139 #define RX_DMA_BURST 4 /* Maximum PCI burst, '4' is 256 */
140 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
141 #define TX_EARLY_THRESH 256 /* Early Tx threshold, in bytes */
143 /* Time in jiffies before concluding the transmitter is hung. */
144 #define TX_TIMEOUT (6*HZ)
146 /* hardware minimum and maximum for a single frame's data payload */
147 #define CP_MIN_MTU 60 /* TODO: allow lower, but pad */
148 #define CP_MAX_MTU 4096
151 /* NIC register offsets */
152 MAC0 = 0x00, /* Ethernet hardware address. */
153 MAR0 = 0x08, /* Multicast filter. */
154 StatsAddr = 0x10, /* 64-bit start addr of 64-byte DMA stats blk */
155 TxRingAddr = 0x20, /* 64-bit start addr of Tx ring */
156 HiTxRingAddr = 0x28, /* 64-bit start addr of high priority Tx ring */
157 Cmd = 0x37, /* Command register */
158 IntrMask = 0x3C, /* Interrupt mask */
159 IntrStatus = 0x3E, /* Interrupt status */
160 TxConfig = 0x40, /* Tx configuration */
161 ChipVersion = 0x43, /* 8-bit chip version, inside TxConfig */
162 RxConfig = 0x44, /* Rx configuration */
163 RxMissed = 0x4C, /* 24 bits valid, write clears */
164 Cfg9346 = 0x50, /* EEPROM select/control; Cfg reg [un]lock */
165 Config1 = 0x52, /* Config1 */
166 Config3 = 0x59, /* Config3 */
167 Config4 = 0x5A, /* Config4 */
168 MultiIntr = 0x5C, /* Multiple interrupt select */
169 BasicModeCtrl = 0x62, /* MII BMCR */
170 BasicModeStatus = 0x64, /* MII BMSR */
171 NWayAdvert = 0x66, /* MII ADVERTISE */
172 NWayLPAR = 0x68, /* MII LPA */
173 NWayExpansion = 0x6A, /* MII Expansion */
174 Config5 = 0xD8, /* Config5 */
175 TxPoll = 0xD9, /* Tell chip to check Tx descriptors for work */
176 RxMaxSize = 0xDA, /* Max size of an Rx packet (8169 only) */
177 CpCmd = 0xE0, /* C+ Command register (C+ mode only) */
178 IntrMitigate = 0xE2, /* rx/tx interrupt mitigation control */
179 RxRingAddr = 0xE4, /* 64-bit start addr of Rx ring */
180 TxThresh = 0xEC, /* Early Tx threshold */
181 OldRxBufAddr = 0x30, /* DMA address of Rx ring buffer (C mode) */
182 OldTSD0 = 0x10, /* DMA address of first Tx desc (C mode) */
184 /* Tx and Rx status descriptors */
185 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
186 RingEnd = (1 << 30), /* End of descriptor ring */
187 FirstFrag = (1 << 29), /* First segment of a packet */
188 LastFrag = (1 << 28), /* Final segment of a packet */
189 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
190 MSSShift = 16, /* MSS value position */
191 MSSMask = 0xfff, /* MSS value: 11 bits */
192 TxError = (1 << 23), /* Tx error summary */
193 RxError = (1 << 20), /* Rx error summary */
194 IPCS = (1 << 18), /* Calculate IP checksum */
195 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
196 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
197 TxVlanTag = (1 << 17), /* Add VLAN tag */
198 RxVlanTagged = (1 << 16), /* Rx VLAN tag available */
199 IPFail = (1 << 15), /* IP checksum failed */
200 UDPFail = (1 << 14), /* UDP/IP checksum failed */
201 TCPFail = (1 << 13), /* TCP/IP checksum failed */
202 NormalTxPoll = (1 << 6), /* One or more normal Tx packets to send */
203 PID1 = (1 << 17), /* 2 protocol id bits: 0==non-IP, */
204 PID0 = (1 << 16), /* 1==UDP/IP, 2==TCP/IP, 3==IP */
208 TxFIFOUnder = (1 << 25), /* Tx FIFO underrun */
209 TxOWC = (1 << 22), /* Tx Out-of-window collision */
210 TxLinkFail = (1 << 21), /* Link failed during Tx of packet */
211 TxMaxCol = (1 << 20), /* Tx aborted due to excessive collisions */
212 TxColCntShift = 16, /* Shift, to get 4-bit Tx collision cnt */
213 TxColCntMask = 0x01 | 0x02 | 0x04 | 0x08, /* 4-bit collision count */
214 RxErrFrame = (1 << 27), /* Rx frame alignment error */
215 RxMcast = (1 << 26), /* Rx multicast packet rcv'd */
216 RxErrCRC = (1 << 18), /* Rx CRC error */
217 RxErrRunt = (1 << 19), /* Rx error, packet < 64 bytes */
218 RxErrLong = (1 << 21), /* Rx error, packet > 4096 bytes */
219 RxErrFIFO = (1 << 22), /* Rx error, FIFO overflowed, pkt bad */
221 /* StatsAddr register */
222 DumpStats = (1 << 3), /* Begin stats dump */
224 /* RxConfig register */
225 RxCfgFIFOShift = 13, /* Shift, to get Rx FIFO thresh value */
226 RxCfgDMAShift = 8, /* Shift, to get Rx Max DMA value */
227 AcceptErr = 0x20, /* Accept packets with CRC errors */
228 AcceptRunt = 0x10, /* Accept runt (<64 bytes) packets */
229 AcceptBroadcast = 0x08, /* Accept broadcast packets */
230 AcceptMulticast = 0x04, /* Accept multicast packets */
231 AcceptMyPhys = 0x02, /* Accept pkts with our MAC as dest */
232 AcceptAllPhys = 0x01, /* Accept all pkts w/ physical dest */
234 /* IntrMask / IntrStatus registers */
235 PciErr = (1 << 15), /* System error on the PCI bus */
236 TimerIntr = (1 << 14), /* Asserted when TCTR reaches TimerInt value */
237 LenChg = (1 << 13), /* Cable length change */
238 SWInt = (1 << 8), /* Software-requested interrupt */
239 TxEmpty = (1 << 7), /* No Tx descriptors available */
240 RxFIFOOvr = (1 << 6), /* Rx FIFO Overflow */
241 LinkChg = (1 << 5), /* Packet underrun, or link change */
242 RxEmpty = (1 << 4), /* No Rx descriptors available */
243 TxErr = (1 << 3), /* Tx error */
244 TxOK = (1 << 2), /* Tx packet sent */
245 RxErr = (1 << 1), /* Rx error */
246 RxOK = (1 << 0), /* Rx packet received */
247 IntrResvd = (1 << 10), /* reserved, according to RealTek engineers,
248 but hardware likes to raise it */
250 IntrAll = PciErr | TimerIntr | LenChg | SWInt | TxEmpty |
251 RxFIFOOvr | LinkChg | RxEmpty | TxErr | TxOK |
252 RxErr | RxOK | IntrResvd,
254 /* C mode command register */
255 CmdReset = (1 << 4), /* Enable to reset; self-clearing */
256 RxOn = (1 << 3), /* Rx mode enable */
257 TxOn = (1 << 2), /* Tx mode enable */
259 /* C+ mode command register */
260 RxVlanOn = (1 << 6), /* Rx VLAN de-tagging enable */
261 RxChkSum = (1 << 5), /* Rx checksum offload enable */
262 PCIDAC = (1 << 4), /* PCI Dual Address Cycle (64-bit PCI) */
263 PCIMulRW = (1 << 3), /* Enable PCI read/write multiple */
264 CpRxOn = (1 << 1), /* Rx mode enable */
265 CpTxOn = (1 << 0), /* Tx mode enable */
267 /* Cfg9436 EEPROM control register */
268 Cfg9346_Lock = 0x00, /* Lock ConfigX/MII register access */
269 Cfg9346_Unlock = 0xC0, /* Unlock ConfigX/MII register access */
271 /* TxConfig register */
272 IFG = (1 << 25) | (1 << 24), /* standard IEEE interframe gap */
273 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
275 /* Early Tx Threshold register */
276 TxThreshMask = 0x3f, /* Mask bits 5-0 */
277 TxThreshMax = 2048, /* Max early Tx threshold */
279 /* Config1 register */
280 DriverLoaded = (1 << 5), /* Software marker, driver is loaded */
281 LWACT = (1 << 4), /* LWAKE active mode */
282 PMEnable = (1 << 0), /* Enable various PM features of chip */
284 /* Config3 register */
285 PARMEnable = (1 << 6), /* Enable auto-loading of PHY parms */
286 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
287 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
289 /* Config4 register */
290 LWPTN = (1 << 1), /* LWAKE Pattern */
291 LWPME = (1 << 4), /* LANWAKE vs PMEB */
293 /* Config5 register */
294 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
295 MWF = (1 << 5), /* Accept Multicast wakeup frame */
296 UWF = (1 << 4), /* Accept Unicast wakeup frame */
297 LANWake = (1 << 1), /* Enable LANWake signal */
298 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
300 cp_norx_intr_mask = PciErr | LinkChg | TxOK | TxErr | TxEmpty,
301 cp_rx_intr_mask = RxOK | RxErr | RxEmpty | RxFIFOOvr,
302 cp_intr_mask = cp_rx_intr_mask | cp_norx_intr_mask,
305 static const unsigned int cp_rx_config =
306 (RX_FIFO_THRESH << RxCfgFIFOShift) |
307 (RX_DMA_BURST << RxCfgDMAShift);
321 struct cp_dma_stats {
335 } __attribute__((packed));
337 struct cp_extra_stats {
338 unsigned long rx_frags;
343 struct net_device *dev;
347 struct pci_dev *pdev;
351 struct net_device_stats net_stats;
352 struct cp_extra_stats cp_stats;
353 struct cp_dma_stats *nic_stats;
354 dma_addr_t nic_stats_dma;
356 unsigned rx_tail ____cacheline_aligned;
357 struct cp_desc *rx_ring;
358 struct ring_info rx_skb[CP_RX_RING_SIZE];
361 unsigned tx_head ____cacheline_aligned;
364 struct cp_desc *tx_ring;
365 struct ring_info tx_skb[CP_TX_RING_SIZE];
369 struct vlan_group *vlgrp;
372 unsigned int wol_enabled : 1; /* Is Wake-on-LAN enabled? */
374 struct mii_if_info mii_if;
377 #define cpr8(reg) readb(cp->regs + (reg))
378 #define cpr16(reg) readw(cp->regs + (reg))
379 #define cpr32(reg) readl(cp->regs + (reg))
380 #define cpw8(reg,val) writeb((val), cp->regs + (reg))
381 #define cpw16(reg,val) writew((val), cp->regs + (reg))
382 #define cpw32(reg,val) writel((val), cp->regs + (reg))
383 #define cpw8_f(reg,val) do { \
384 writeb((val), cp->regs + (reg)); \
385 readb(cp->regs + (reg)); \
387 #define cpw16_f(reg,val) do { \
388 writew((val), cp->regs + (reg)); \
389 readw(cp->regs + (reg)); \
391 #define cpw32_f(reg,val) do { \
392 writel((val), cp->regs + (reg)); \
393 readl(cp->regs + (reg)); \
397 static void __cp_set_rx_mode (struct net_device *dev);
398 static void cp_tx (struct cp_private *cp);
399 static void cp_clean_rings (struct cp_private *cp);
401 static struct pci_device_id cp_pci_tbl[] = {
402 { PCI_VENDOR_ID_REALTEK, PCI_DEVICE_ID_REALTEK_8139,
403 PCI_ANY_ID, PCI_ANY_ID, 0, 0, },
404 { PCI_VENDOR_ID_TTTECH, PCI_DEVICE_ID_TTTECH_MC322,
405 PCI_ANY_ID, PCI_ANY_ID, 0, 0, },
408 MODULE_DEVICE_TABLE(pci, cp_pci_tbl);
411 const char str[ETH_GSTRING_LEN];
412 } ethtool_stats_keys[] = {
431 static void cp_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
433 struct cp_private *cp = netdev_priv(dev);
436 spin_lock_irqsave(&cp->lock, flags);
438 cp->cpcmd |= RxVlanOn;
439 cpw16(CpCmd, cp->cpcmd);
440 spin_unlock_irqrestore(&cp->lock, flags);
443 static void cp_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
445 struct cp_private *cp = netdev_priv(dev);
448 spin_lock_irqsave(&cp->lock, flags);
449 cp->cpcmd &= ~RxVlanOn;
450 cpw16(CpCmd, cp->cpcmd);
452 cp->vlgrp->vlan_devices[vid] = NULL;
453 spin_unlock_irqrestore(&cp->lock, flags);
455 #endif /* CP_VLAN_TAG_USED */
457 static inline void cp_set_rxbufsize (struct cp_private *cp)
459 unsigned int mtu = cp->dev->mtu;
461 if (mtu > ETH_DATA_LEN)
462 /* MTU + ethernet header + FCS + optional VLAN tag */
463 cp->rx_buf_sz = mtu + ETH_HLEN + 8;
465 cp->rx_buf_sz = PKT_BUF_SZ;
468 static inline void cp_rx_skb (struct cp_private *cp, struct sk_buff *skb,
469 struct cp_desc *desc)
471 skb->protocol = eth_type_trans (skb, cp->dev);
473 cp->net_stats.rx_packets++;
474 cp->net_stats.rx_bytes += skb->len;
475 cp->dev->last_rx = jiffies;
478 if (cp->vlgrp && (desc->opts2 & RxVlanTagged)) {
479 vlan_hwaccel_receive_skb(skb, cp->vlgrp,
480 be16_to_cpu(desc->opts2 & 0xffff));
483 netif_receive_skb(skb);
486 static void cp_rx_err_acct (struct cp_private *cp, unsigned rx_tail,
489 if (netif_msg_rx_err (cp))
491 "%s: rx err, slot %d status 0x%x len %d\n",
492 cp->dev->name, rx_tail, status, len);
493 cp->net_stats.rx_errors++;
494 if (status & RxErrFrame)
495 cp->net_stats.rx_frame_errors++;
496 if (status & RxErrCRC)
497 cp->net_stats.rx_crc_errors++;
498 if ((status & RxErrRunt) || (status & RxErrLong))
499 cp->net_stats.rx_length_errors++;
500 if ((status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag))
501 cp->net_stats.rx_length_errors++;
502 if (status & RxErrFIFO)
503 cp->net_stats.rx_fifo_errors++;
506 static inline unsigned int cp_rx_csum_ok (u32 status)
508 unsigned int protocol = (status >> 16) & 0x3;
510 if (likely((protocol == RxProtoTCP) && (!(status & TCPFail))))
512 else if ((protocol == RxProtoUDP) && (!(status & UDPFail)))
514 else if ((protocol == RxProtoIP) && (!(status & IPFail)))
519 static int cp_rx_poll (struct net_device *dev, int *budget)
521 struct cp_private *cp = netdev_priv(dev);
522 unsigned rx_tail = cp->rx_tail;
523 unsigned rx_work = dev->quota;
528 cpw16(IntrStatus, cp_rx_intr_mask);
533 struct sk_buff *skb, *new_skb;
534 struct cp_desc *desc;
537 skb = cp->rx_skb[rx_tail].skb;
541 desc = &cp->rx_ring[rx_tail];
542 status = le32_to_cpu(desc->opts1);
543 if (status & DescOwn)
546 len = (status & 0x1fff) - 4;
547 mapping = cp->rx_skb[rx_tail].mapping;
549 if ((status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag)) {
550 /* we don't support incoming fragmented frames.
551 * instead, we attempt to ensure that the
552 * pre-allocated RX skbs are properly sized such
553 * that RX fragments are never encountered
555 cp_rx_err_acct(cp, rx_tail, status, len);
556 cp->net_stats.rx_dropped++;
557 cp->cp_stats.rx_frags++;
561 if (status & (RxError | RxErrFIFO)) {
562 cp_rx_err_acct(cp, rx_tail, status, len);
566 if (netif_msg_rx_status(cp))
567 printk(KERN_DEBUG "%s: rx slot %d status 0x%x len %d\n",
568 cp->dev->name, rx_tail, status, len);
570 buflen = cp->rx_buf_sz + RX_OFFSET;
571 new_skb = dev_alloc_skb (buflen);
573 cp->net_stats.rx_dropped++;
577 skb_reserve(new_skb, RX_OFFSET);
578 new_skb->dev = cp->dev;
580 pci_unmap_single(cp->pdev, mapping,
581 buflen, PCI_DMA_FROMDEVICE);
583 /* Handle checksum offloading for incoming packets. */
584 if (cp_rx_csum_ok(status))
585 skb->ip_summed = CHECKSUM_UNNECESSARY;
587 skb->ip_summed = CHECKSUM_NONE;
592 cp->rx_skb[rx_tail].mapping =
593 pci_map_single(cp->pdev, new_skb->tail,
594 buflen, PCI_DMA_FROMDEVICE);
595 cp->rx_skb[rx_tail].skb = new_skb;
597 cp_rx_skb(cp, skb, desc);
601 cp->rx_ring[rx_tail].opts2 = 0;
602 cp->rx_ring[rx_tail].addr = cpu_to_le64(mapping);
603 if (rx_tail == (CP_RX_RING_SIZE - 1))
604 desc->opts1 = cpu_to_le32(DescOwn | RingEnd |
607 desc->opts1 = cpu_to_le32(DescOwn | cp->rx_buf_sz);
608 rx_tail = NEXT_RX(rx_tail);
614 cp->rx_tail = rx_tail;
619 /* if we did not reach work limit, then we're done with
620 * this round of polling
623 if (cpr16(IntrStatus) & cp_rx_intr_mask)
627 cpw16_f(IntrMask, cp_intr_mask);
628 __netif_rx_complete(dev);
634 return 1; /* not done */
638 cp_interrupt (int irq, void *dev_instance, struct pt_regs *regs)
640 struct net_device *dev = dev_instance;
641 struct cp_private *cp;
644 if (unlikely(dev == NULL))
646 cp = netdev_priv(dev);
648 status = cpr16(IntrStatus);
649 if (!status || (status == 0xFFFF))
652 if (netif_msg_intr(cp))
653 printk(KERN_DEBUG "%s: intr, status %04x cmd %02x cpcmd %04x\n",
654 dev->name, status, cpr8(Cmd), cpr16(CpCmd));
656 cpw16(IntrStatus, status & ~cp_rx_intr_mask);
658 spin_lock(&cp->lock);
660 /* close possible race's with dev_close */
661 if (unlikely(!netif_running(dev))) {
663 spin_unlock(&cp->lock);
667 if (status & (RxOK | RxErr | RxEmpty | RxFIFOOvr))
668 if (netif_rx_schedule_prep(dev)) {
669 cpw16_f(IntrMask, cp_norx_intr_mask);
670 __netif_rx_schedule(dev);
673 if (status & (TxOK | TxErr | TxEmpty | SWInt))
675 if (status & LinkChg)
676 mii_check_media(&cp->mii_if, netif_msg_link(cp), FALSE);
678 spin_unlock(&cp->lock);
680 if (status & PciErr) {
683 pci_read_config_word(cp->pdev, PCI_STATUS, &pci_status);
684 pci_write_config_word(cp->pdev, PCI_STATUS, pci_status);
685 printk(KERN_ERR "%s: PCI bus error, status=%04x, PCI status=%04x\n",
686 dev->name, status, pci_status);
688 /* TODO: reset hardware */
694 static void cp_tx (struct cp_private *cp)
696 unsigned tx_head = cp->tx_head;
697 unsigned tx_tail = cp->tx_tail;
699 while (tx_tail != tx_head) {
704 status = le32_to_cpu(cp->tx_ring[tx_tail].opts1);
705 if (status & DescOwn)
708 skb = cp->tx_skb[tx_tail].skb;
712 pci_unmap_single(cp->pdev, cp->tx_skb[tx_tail].mapping,
713 cp->tx_skb[tx_tail].len, PCI_DMA_TODEVICE);
715 if (status & LastFrag) {
716 if (status & (TxError | TxFIFOUnder)) {
717 if (netif_msg_tx_err(cp))
718 printk(KERN_DEBUG "%s: tx err, status 0x%x\n",
719 cp->dev->name, status);
720 cp->net_stats.tx_errors++;
722 cp->net_stats.tx_window_errors++;
723 if (status & TxMaxCol)
724 cp->net_stats.tx_aborted_errors++;
725 if (status & TxLinkFail)
726 cp->net_stats.tx_carrier_errors++;
727 if (status & TxFIFOUnder)
728 cp->net_stats.tx_fifo_errors++;
730 cp->net_stats.collisions +=
731 ((status >> TxColCntShift) & TxColCntMask);
732 cp->net_stats.tx_packets++;
733 cp->net_stats.tx_bytes += skb->len;
734 if (netif_msg_tx_done(cp))
735 printk(KERN_DEBUG "%s: tx done, slot %d\n", cp->dev->name, tx_tail);
737 dev_kfree_skb_irq(skb);
740 cp->tx_skb[tx_tail].skb = NULL;
742 tx_tail = NEXT_TX(tx_tail);
745 cp->tx_tail = tx_tail;
747 if (TX_BUFFS_AVAIL(cp) > (MAX_SKB_FRAGS + 1))
748 netif_wake_queue(cp->dev);
751 static int cp_start_xmit (struct sk_buff *skb, struct net_device *dev)
753 struct cp_private *cp = netdev_priv(dev);
761 spin_lock_irq(&cp->lock);
763 /* This is a hard error, log it. */
764 if (TX_BUFFS_AVAIL(cp) <= (skb_shinfo(skb)->nr_frags + 1)) {
765 netif_stop_queue(dev);
766 spin_unlock_irq(&cp->lock);
767 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when queue awake!\n",
773 if (cp->vlgrp && vlan_tx_tag_present(skb))
774 vlan_tag = TxVlanTag | cpu_to_be16(vlan_tx_tag_get(skb));
778 eor = (entry == (CP_TX_RING_SIZE - 1)) ? RingEnd : 0;
779 if (dev->features & NETIF_F_TSO)
780 mss = skb_shinfo(skb)->tso_size;
782 if (skb_shinfo(skb)->nr_frags == 0) {
783 struct cp_desc *txd = &cp->tx_ring[entry];
788 mapping = pci_map_single(cp->pdev, skb->data, len, PCI_DMA_TODEVICE);
789 CP_VLAN_TX_TAG(txd, vlan_tag);
790 txd->addr = cpu_to_le64(mapping);
793 flags = eor | len | DescOwn | FirstFrag | LastFrag;
796 flags |= LargeSend | ((mss & MSSMask) << MSSShift);
797 else if (skb->ip_summed == CHECKSUM_HW) {
798 const struct iphdr *ip = skb->nh.iph;
799 if (ip->protocol == IPPROTO_TCP)
800 flags |= IPCS | TCPCS;
801 else if (ip->protocol == IPPROTO_UDP)
802 flags |= IPCS | UDPCS;
804 WARN_ON(1); /* we need a WARN() */
807 txd->opts1 = cpu_to_le32(flags);
810 cp->tx_skb[entry].skb = skb;
811 cp->tx_skb[entry].mapping = mapping;
812 cp->tx_skb[entry].len = len;
813 entry = NEXT_TX(entry);
816 u32 first_len, first_eor;
817 dma_addr_t first_mapping;
818 int frag, first_entry = entry;
819 const struct iphdr *ip = skb->nh.iph;
821 /* We must give this initial chunk to the device last.
822 * Otherwise we could race with the device.
825 first_len = skb_headlen(skb);
826 first_mapping = pci_map_single(cp->pdev, skb->data,
827 first_len, PCI_DMA_TODEVICE);
828 cp->tx_skb[entry].skb = skb;
829 cp->tx_skb[entry].mapping = first_mapping;
830 cp->tx_skb[entry].len = first_len;
831 entry = NEXT_TX(entry);
833 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
834 skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
839 len = this_frag->size;
840 mapping = pci_map_single(cp->pdev,
841 ((void *) page_address(this_frag->page) +
842 this_frag->page_offset),
843 len, PCI_DMA_TODEVICE);
844 eor = (entry == (CP_TX_RING_SIZE - 1)) ? RingEnd : 0;
846 ctrl = eor | len | DescOwn;
850 ((mss & MSSMask) << MSSShift);
851 else if (skb->ip_summed == CHECKSUM_HW) {
852 if (ip->protocol == IPPROTO_TCP)
853 ctrl |= IPCS | TCPCS;
854 else if (ip->protocol == IPPROTO_UDP)
855 ctrl |= IPCS | UDPCS;
860 if (frag == skb_shinfo(skb)->nr_frags - 1)
863 txd = &cp->tx_ring[entry];
864 CP_VLAN_TX_TAG(txd, vlan_tag);
865 txd->addr = cpu_to_le64(mapping);
868 txd->opts1 = cpu_to_le32(ctrl);
871 cp->tx_skb[entry].skb = skb;
872 cp->tx_skb[entry].mapping = mapping;
873 cp->tx_skb[entry].len = len;
874 entry = NEXT_TX(entry);
877 txd = &cp->tx_ring[first_entry];
878 CP_VLAN_TX_TAG(txd, vlan_tag);
879 txd->addr = cpu_to_le64(first_mapping);
882 if (skb->ip_summed == CHECKSUM_HW) {
883 if (ip->protocol == IPPROTO_TCP)
884 txd->opts1 = cpu_to_le32(first_eor | first_len |
885 FirstFrag | DescOwn |
887 else if (ip->protocol == IPPROTO_UDP)
888 txd->opts1 = cpu_to_le32(first_eor | first_len |
889 FirstFrag | DescOwn |
894 txd->opts1 = cpu_to_le32(first_eor | first_len |
895 FirstFrag | DescOwn);
899 if (netif_msg_tx_queued(cp))
900 printk(KERN_DEBUG "%s: tx queued, slot %d, skblen %d\n",
901 dev->name, entry, skb->len);
902 if (TX_BUFFS_AVAIL(cp) <= (MAX_SKB_FRAGS + 1))
903 netif_stop_queue(dev);
905 spin_unlock_irq(&cp->lock);
907 cpw8(TxPoll, NormalTxPoll);
908 dev->trans_start = jiffies;
913 /* Set or clear the multicast filter for this adaptor.
914 This routine is not state sensitive and need not be SMP locked. */
916 static void __cp_set_rx_mode (struct net_device *dev)
918 struct cp_private *cp = netdev_priv(dev);
919 u32 mc_filter[2]; /* Multicast hash filter */
923 /* Note: do not reorder, GCC is clever about common statements. */
924 if (dev->flags & IFF_PROMISC) {
925 /* Unconditionally log net taps. */
926 printk (KERN_NOTICE "%s: Promiscuous mode enabled.\n",
929 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
931 mc_filter[1] = mc_filter[0] = 0xffffffff;
932 } else if ((dev->mc_count > multicast_filter_limit)
933 || (dev->flags & IFF_ALLMULTI)) {
934 /* Too many to filter perfectly -- accept all multicasts. */
935 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
936 mc_filter[1] = mc_filter[0] = 0xffffffff;
938 struct dev_mc_list *mclist;
939 rx_mode = AcceptBroadcast | AcceptMyPhys;
940 mc_filter[1] = mc_filter[0] = 0;
941 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
942 i++, mclist = mclist->next) {
943 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
945 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
946 rx_mode |= AcceptMulticast;
950 /* We can safely update without stopping the chip. */
951 tmp = cp_rx_config | rx_mode;
952 if (cp->rx_config != tmp) {
953 cpw32_f (RxConfig, tmp);
956 cpw32_f (MAR0 + 0, mc_filter[0]);
957 cpw32_f (MAR0 + 4, mc_filter[1]);
960 static void cp_set_rx_mode (struct net_device *dev)
963 struct cp_private *cp = netdev_priv(dev);
965 spin_lock_irqsave (&cp->lock, flags);
966 __cp_set_rx_mode(dev);
967 spin_unlock_irqrestore (&cp->lock, flags);
970 static void __cp_get_stats(struct cp_private *cp)
972 /* only lower 24 bits valid; write any value to clear */
973 cp->net_stats.rx_missed_errors += (cpr32 (RxMissed) & 0xffffff);
977 static struct net_device_stats *cp_get_stats(struct net_device *dev)
979 struct cp_private *cp = netdev_priv(dev);
982 /* The chip only need report frame silently dropped. */
983 spin_lock_irqsave(&cp->lock, flags);
984 if (netif_running(dev) && netif_device_present(dev))
986 spin_unlock_irqrestore(&cp->lock, flags);
988 return &cp->net_stats;
991 static void cp_stop_hw (struct cp_private *cp)
993 cpw16(IntrStatus, ~(cpr16(IntrStatus)));
994 cpw16_f(IntrMask, 0);
997 cpw16_f(IntrStatus, ~(cpr16(IntrStatus)));
1000 cp->tx_head = cp->tx_tail = 0;
1003 static void cp_reset_hw (struct cp_private *cp)
1005 unsigned work = 1000;
1007 cpw8(Cmd, CmdReset);
1010 if (!(cpr8(Cmd) & CmdReset))
1013 set_current_state(TASK_UNINTERRUPTIBLE);
1014 schedule_timeout(10);
1017 printk(KERN_ERR "%s: hardware reset timeout\n", cp->dev->name);
1020 static inline void cp_start_hw (struct cp_private *cp)
1022 cpw16(CpCmd, cp->cpcmd);
1023 cpw8(Cmd, RxOn | TxOn);
1026 static void cp_init_hw (struct cp_private *cp)
1028 struct net_device *dev = cp->dev;
1029 dma_addr_t ring_dma;
1033 cpw8_f (Cfg9346, Cfg9346_Unlock);
1035 /* Restore our idea of the MAC address. */
1036 cpw32_f (MAC0 + 0, cpu_to_le32 (*(u32 *) (dev->dev_addr + 0)));
1037 cpw32_f (MAC0 + 4, cpu_to_le32 (*(u32 *) (dev->dev_addr + 4)));
1040 cpw8(TxThresh, 0x06); /* XXX convert magic num to a constant */
1042 __cp_set_rx_mode(dev);
1043 cpw32_f (TxConfig, IFG | (TX_DMA_BURST << TxDMAShift));
1045 cpw8(Config1, cpr8(Config1) | DriverLoaded | PMEnable);
1046 /* Disable Wake-on-LAN. Can be turned on with ETHTOOL_SWOL */
1047 cpw8(Config3, PARMEnable);
1048 cp->wol_enabled = 0;
1050 cpw8(Config5, cpr8(Config5) & PMEStatus);
1052 cpw32_f(HiTxRingAddr, 0);
1053 cpw32_f(HiTxRingAddr + 4, 0);
1055 ring_dma = cp->ring_dma;
1056 cpw32_f(RxRingAddr, ring_dma & 0xffffffff);
1057 cpw32_f(RxRingAddr + 4, (ring_dma >> 16) >> 16);
1059 ring_dma += sizeof(struct cp_desc) * CP_RX_RING_SIZE;
1060 cpw32_f(TxRingAddr, ring_dma & 0xffffffff);
1061 cpw32_f(TxRingAddr + 4, (ring_dma >> 16) >> 16);
1063 cpw16(MultiIntr, 0);
1065 cpw16_f(IntrMask, cp_intr_mask);
1067 cpw8_f(Cfg9346, Cfg9346_Lock);
1070 static int cp_refill_rx (struct cp_private *cp)
1074 for (i = 0; i < CP_RX_RING_SIZE; i++) {
1075 struct sk_buff *skb;
1077 skb = dev_alloc_skb(cp->rx_buf_sz + RX_OFFSET);
1082 skb_reserve(skb, RX_OFFSET);
1084 cp->rx_skb[i].mapping = pci_map_single(cp->pdev,
1085 skb->tail, cp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1086 cp->rx_skb[i].skb = skb;
1088 cp->rx_ring[i].opts2 = 0;
1089 cp->rx_ring[i].addr = cpu_to_le64(cp->rx_skb[i].mapping);
1090 if (i == (CP_RX_RING_SIZE - 1))
1091 cp->rx_ring[i].opts1 =
1092 cpu_to_le32(DescOwn | RingEnd | cp->rx_buf_sz);
1094 cp->rx_ring[i].opts1 =
1095 cpu_to_le32(DescOwn | cp->rx_buf_sz);
1105 static int cp_init_rings (struct cp_private *cp)
1107 memset(cp->tx_ring, 0, sizeof(struct cp_desc) * CP_TX_RING_SIZE);
1108 cp->tx_ring[CP_TX_RING_SIZE - 1].opts1 = cpu_to_le32(RingEnd);
1111 cp->tx_head = cp->tx_tail = 0;
1113 return cp_refill_rx (cp);
1116 static int cp_alloc_rings (struct cp_private *cp)
1120 mem = pci_alloc_consistent(cp->pdev, CP_RING_BYTES, &cp->ring_dma);
1125 cp->tx_ring = &cp->rx_ring[CP_RX_RING_SIZE];
1127 mem += (CP_RING_BYTES - CP_STATS_SIZE);
1128 cp->nic_stats = mem;
1129 cp->nic_stats_dma = cp->ring_dma + (CP_RING_BYTES - CP_STATS_SIZE);
1131 return cp_init_rings(cp);
1134 static void cp_clean_rings (struct cp_private *cp)
1138 for (i = 0; i < CP_RX_RING_SIZE; i++) {
1139 if (cp->rx_skb[i].skb) {
1140 pci_unmap_single(cp->pdev, cp->rx_skb[i].mapping,
1141 cp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1142 dev_kfree_skb(cp->rx_skb[i].skb);
1146 for (i = 0; i < CP_TX_RING_SIZE; i++) {
1147 if (cp->tx_skb[i].skb) {
1148 struct sk_buff *skb = cp->tx_skb[i].skb;
1150 pci_unmap_single(cp->pdev, cp->tx_skb[i].mapping,
1151 cp->tx_skb[i].len, PCI_DMA_TODEVICE);
1152 if (le32_to_cpu(cp->tx_ring[i].opts1) & LastFrag)
1154 cp->net_stats.tx_dropped++;
1158 memset(cp->rx_ring, 0, sizeof(struct cp_desc) * CP_RX_RING_SIZE);
1159 memset(cp->tx_ring, 0, sizeof(struct cp_desc) * CP_TX_RING_SIZE);
1161 memset(&cp->rx_skb, 0, sizeof(struct ring_info) * CP_RX_RING_SIZE);
1162 memset(&cp->tx_skb, 0, sizeof(struct ring_info) * CP_TX_RING_SIZE);
1165 static void cp_free_rings (struct cp_private *cp)
1168 pci_free_consistent(cp->pdev, CP_RING_BYTES, cp->rx_ring, cp->ring_dma);
1171 cp->nic_stats = NULL;
1174 static int cp_open (struct net_device *dev)
1176 struct cp_private *cp = netdev_priv(dev);
1179 if (netif_msg_ifup(cp))
1180 printk(KERN_DEBUG "%s: enabling interface\n", dev->name);
1182 rc = cp_alloc_rings(cp);
1188 rc = request_irq(dev->irq, cp_interrupt, SA_SHIRQ, dev->name, dev);
1192 netif_carrier_off(dev);
1193 mii_check_media(&cp->mii_if, netif_msg_link(cp), TRUE);
1194 netif_start_queue(dev);
1204 static int cp_close (struct net_device *dev)
1206 struct cp_private *cp = netdev_priv(dev);
1207 unsigned long flags;
1209 if (netif_msg_ifdown(cp))
1210 printk(KERN_DEBUG "%s: disabling interface\n", dev->name);
1212 spin_lock_irqsave(&cp->lock, flags);
1214 netif_stop_queue(dev);
1215 netif_carrier_off(dev);
1219 spin_unlock_irqrestore(&cp->lock, flags);
1221 synchronize_irq(dev->irq);
1222 free_irq(dev->irq, dev);
1229 static int cp_change_mtu(struct net_device *dev, int new_mtu)
1231 struct cp_private *cp = netdev_priv(dev);
1233 unsigned long flags;
1235 /* check for invalid MTU, according to hardware limits */
1236 if (new_mtu < CP_MIN_MTU || new_mtu > CP_MAX_MTU)
1239 /* if network interface not up, no need for complexity */
1240 if (!netif_running(dev)) {
1242 cp_set_rxbufsize(cp); /* set new rx buf size */
1246 spin_lock_irqsave(&cp->lock, flags);
1248 cp_stop_hw(cp); /* stop h/w and free rings */
1252 cp_set_rxbufsize(cp); /* set new rx buf size */
1254 rc = cp_init_rings(cp); /* realloc and restart h/w */
1257 spin_unlock_irqrestore(&cp->lock, flags);
1263 static char mii_2_8139_map[8] = {
1274 static int mdio_read(struct net_device *dev, int phy_id, int location)
1276 struct cp_private *cp = netdev_priv(dev);
1278 return location < 8 && mii_2_8139_map[location] ?
1279 readw(cp->regs + mii_2_8139_map[location]) : 0;
1283 static void mdio_write(struct net_device *dev, int phy_id, int location,
1286 struct cp_private *cp = netdev_priv(dev);
1288 if (location == 0) {
1289 cpw8(Cfg9346, Cfg9346_Unlock);
1290 cpw16(BasicModeCtrl, value);
1291 cpw8(Cfg9346, Cfg9346_Lock);
1292 } else if (location < 8 && mii_2_8139_map[location])
1293 cpw16(mii_2_8139_map[location], value);
1296 /* Set the ethtool Wake-on-LAN settings */
1297 static int netdev_set_wol (struct cp_private *cp,
1298 const struct ethtool_wolinfo *wol)
1302 options = cpr8 (Config3) & ~(LinkUp | MagicPacket);
1303 /* If WOL is being disabled, no need for complexity */
1305 if (wol->wolopts & WAKE_PHY) options |= LinkUp;
1306 if (wol->wolopts & WAKE_MAGIC) options |= MagicPacket;
1309 cpw8 (Cfg9346, Cfg9346_Unlock);
1310 cpw8 (Config3, options);
1311 cpw8 (Cfg9346, Cfg9346_Lock);
1313 options = 0; /* Paranoia setting */
1314 options = cpr8 (Config5) & ~(UWF | MWF | BWF);
1315 /* If WOL is being disabled, no need for complexity */
1317 if (wol->wolopts & WAKE_UCAST) options |= UWF;
1318 if (wol->wolopts & WAKE_BCAST) options |= BWF;
1319 if (wol->wolopts & WAKE_MCAST) options |= MWF;
1322 cpw8 (Config5, options);
1324 cp->wol_enabled = (wol->wolopts) ? 1 : 0;
1329 /* Get the ethtool Wake-on-LAN settings */
1330 static void netdev_get_wol (struct cp_private *cp,
1331 struct ethtool_wolinfo *wol)
1335 wol->wolopts = 0; /* Start from scratch */
1336 wol->supported = WAKE_PHY | WAKE_BCAST | WAKE_MAGIC |
1337 WAKE_MCAST | WAKE_UCAST;
1338 /* We don't need to go on if WOL is disabled */
1339 if (!cp->wol_enabled) return;
1341 options = cpr8 (Config3);
1342 if (options & LinkUp) wol->wolopts |= WAKE_PHY;
1343 if (options & MagicPacket) wol->wolopts |= WAKE_MAGIC;
1345 options = 0; /* Paranoia setting */
1346 options = cpr8 (Config5);
1347 if (options & UWF) wol->wolopts |= WAKE_UCAST;
1348 if (options & BWF) wol->wolopts |= WAKE_BCAST;
1349 if (options & MWF) wol->wolopts |= WAKE_MCAST;
1352 static void cp_get_drvinfo (struct net_device *dev, struct ethtool_drvinfo *info)
1354 struct cp_private *cp = netdev_priv(dev);
1356 strcpy (info->driver, DRV_NAME);
1357 strcpy (info->version, DRV_VERSION);
1358 strcpy (info->bus_info, pci_name(cp->pdev));
1361 static int cp_get_regs_len(struct net_device *dev)
1363 return CP_REGS_SIZE;
1366 static int cp_get_stats_count (struct net_device *dev)
1368 return CP_NUM_STATS;
1371 static int cp_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1373 struct cp_private *cp = netdev_priv(dev);
1375 unsigned long flags;
1377 spin_lock_irqsave(&cp->lock, flags);
1378 rc = mii_ethtool_gset(&cp->mii_if, cmd);
1379 spin_unlock_irqrestore(&cp->lock, flags);
1384 static int cp_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1386 struct cp_private *cp = netdev_priv(dev);
1388 unsigned long flags;
1390 spin_lock_irqsave(&cp->lock, flags);
1391 rc = mii_ethtool_sset(&cp->mii_if, cmd);
1392 spin_unlock_irqrestore(&cp->lock, flags);
1397 static int cp_nway_reset(struct net_device *dev)
1399 struct cp_private *cp = netdev_priv(dev);
1400 return mii_nway_restart(&cp->mii_if);
1403 static u32 cp_get_msglevel(struct net_device *dev)
1405 struct cp_private *cp = netdev_priv(dev);
1406 return cp->msg_enable;
1409 static void cp_set_msglevel(struct net_device *dev, u32 value)
1411 struct cp_private *cp = netdev_priv(dev);
1412 cp->msg_enable = value;
1415 static u32 cp_get_rx_csum(struct net_device *dev)
1417 struct cp_private *cp = netdev_priv(dev);
1418 return (cpr16(CpCmd) & RxChkSum) ? 1 : 0;
1421 static int cp_set_rx_csum(struct net_device *dev, u32 data)
1423 struct cp_private *cp = netdev_priv(dev);
1424 u16 cmd = cp->cpcmd, newcmd;
1431 newcmd &= ~RxChkSum;
1433 if (newcmd != cmd) {
1434 unsigned long flags;
1436 spin_lock_irqsave(&cp->lock, flags);
1438 cpw16_f(CpCmd, newcmd);
1439 spin_unlock_irqrestore(&cp->lock, flags);
1445 static void cp_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1448 struct cp_private *cp = netdev_priv(dev);
1449 unsigned long flags;
1451 if (regs->len < CP_REGS_SIZE)
1452 return /* -EINVAL */;
1454 regs->version = CP_REGS_VER;
1456 spin_lock_irqsave(&cp->lock, flags);
1457 memcpy_fromio(p, cp->regs, CP_REGS_SIZE);
1458 spin_unlock_irqrestore(&cp->lock, flags);
1461 static void cp_get_wol (struct net_device *dev, struct ethtool_wolinfo *wol)
1463 struct cp_private *cp = netdev_priv(dev);
1464 unsigned long flags;
1466 spin_lock_irqsave (&cp->lock, flags);
1467 netdev_get_wol (cp, wol);
1468 spin_unlock_irqrestore (&cp->lock, flags);
1471 static int cp_set_wol (struct net_device *dev, struct ethtool_wolinfo *wol)
1473 struct cp_private *cp = netdev_priv(dev);
1474 unsigned long flags;
1477 spin_lock_irqsave (&cp->lock, flags);
1478 rc = netdev_set_wol (cp, wol);
1479 spin_unlock_irqrestore (&cp->lock, flags);
1484 static void cp_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
1486 switch (stringset) {
1488 memcpy(buf, ðtool_stats_keys, sizeof(ethtool_stats_keys));
1496 static void cp_get_ethtool_stats (struct net_device *dev,
1497 struct ethtool_stats *estats, u64 *tmp_stats)
1499 struct cp_private *cp = netdev_priv(dev);
1500 unsigned int work = 100;
1503 /* begin NIC statistics dump */
1504 cpw32(StatsAddr + 4, (cp->nic_stats_dma >> 16) >> 16);
1505 cpw32(StatsAddr, (cp->nic_stats_dma & 0xffffffff) | DumpStats);
1508 while (work-- > 0) {
1509 if ((cpr32(StatsAddr) & DumpStats) == 0)
1514 if (cpr32(StatsAddr) & DumpStats)
1518 tmp_stats[i++] = le64_to_cpu(cp->nic_stats->tx_ok);
1519 tmp_stats[i++] = le64_to_cpu(cp->nic_stats->rx_ok);
1520 tmp_stats[i++] = le64_to_cpu(cp->nic_stats->tx_err);
1521 tmp_stats[i++] = le32_to_cpu(cp->nic_stats->rx_err);
1522 tmp_stats[i++] = le16_to_cpu(cp->nic_stats->rx_fifo);
1523 tmp_stats[i++] = le16_to_cpu(cp->nic_stats->frame_align);
1524 tmp_stats[i++] = le32_to_cpu(cp->nic_stats->tx_ok_1col);
1525 tmp_stats[i++] = le32_to_cpu(cp->nic_stats->tx_ok_mcol);
1526 tmp_stats[i++] = le64_to_cpu(cp->nic_stats->rx_ok_phys);
1527 tmp_stats[i++] = le64_to_cpu(cp->nic_stats->rx_ok_bcast);
1528 tmp_stats[i++] = le32_to_cpu(cp->nic_stats->rx_ok_mcast);
1529 tmp_stats[i++] = le16_to_cpu(cp->nic_stats->tx_abort);
1530 tmp_stats[i++] = le16_to_cpu(cp->nic_stats->tx_underrun);
1531 tmp_stats[i++] = cp->cp_stats.rx_frags;
1532 if (i != CP_NUM_STATS)
1536 static struct ethtool_ops cp_ethtool_ops = {
1537 .get_drvinfo = cp_get_drvinfo,
1538 .get_regs_len = cp_get_regs_len,
1539 .get_stats_count = cp_get_stats_count,
1540 .get_settings = cp_get_settings,
1541 .set_settings = cp_set_settings,
1542 .nway_reset = cp_nway_reset,
1543 .get_link = ethtool_op_get_link,
1544 .get_msglevel = cp_get_msglevel,
1545 .set_msglevel = cp_set_msglevel,
1546 .get_rx_csum = cp_get_rx_csum,
1547 .set_rx_csum = cp_set_rx_csum,
1548 .get_tx_csum = ethtool_op_get_tx_csum,
1549 .set_tx_csum = ethtool_op_set_tx_csum, /* local! */
1550 .get_sg = ethtool_op_get_sg,
1551 .set_sg = ethtool_op_set_sg,
1552 .get_tso = ethtool_op_get_tso,
1553 .set_tso = ethtool_op_set_tso,
1554 .get_regs = cp_get_regs,
1555 .get_wol = cp_get_wol,
1556 .set_wol = cp_set_wol,
1557 .get_strings = cp_get_strings,
1558 .get_ethtool_stats = cp_get_ethtool_stats,
1561 static int cp_ioctl (struct net_device *dev, struct ifreq *rq, int cmd)
1563 struct cp_private *cp = netdev_priv(dev);
1565 unsigned long flags;
1567 if (!netif_running(dev))
1570 spin_lock_irqsave(&cp->lock, flags);
1571 rc = generic_mii_ioctl(&cp->mii_if, if_mii(rq), cmd, NULL);
1572 spin_unlock_irqrestore(&cp->lock, flags);
1576 /* Serial EEPROM section. */
1578 /* EEPROM_Ctrl bits. */
1579 #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
1580 #define EE_CS 0x08 /* EEPROM chip select. */
1581 #define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */
1582 #define EE_WRITE_0 0x00
1583 #define EE_WRITE_1 0x02
1584 #define EE_DATA_READ 0x01 /* EEPROM chip data out. */
1585 #define EE_ENB (0x80 | EE_CS)
1587 /* Delay between EEPROM clock transitions.
1588 No extra delay is needed with 33Mhz PCI, but 66Mhz may change this.
1591 #define eeprom_delay() readl(ee_addr)
1593 /* The EEPROM commands include the alway-set leading bit. */
1594 #define EE_WRITE_CMD (5)
1595 #define EE_READ_CMD (6)
1596 #define EE_ERASE_CMD (7)
1598 static int read_eeprom (void __iomem *ioaddr, int location, int addr_len)
1601 unsigned retval = 0;
1602 void __iomem *ee_addr = ioaddr + Cfg9346;
1603 int read_cmd = location | (EE_READ_CMD << addr_len);
1605 writeb (EE_ENB & ~EE_CS, ee_addr);
1606 writeb (EE_ENB, ee_addr);
1609 /* Shift the read command bits out. */
1610 for (i = 4 + addr_len; i >= 0; i--) {
1611 int dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
1612 writeb (EE_ENB | dataval, ee_addr);
1614 writeb (EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
1617 writeb (EE_ENB, ee_addr);
1620 for (i = 16; i > 0; i--) {
1621 writeb (EE_ENB | EE_SHIFT_CLK, ee_addr);
1624 (retval << 1) | ((readb (ee_addr) & EE_DATA_READ) ? 1 :
1626 writeb (EE_ENB, ee_addr);
1630 /* Terminate the EEPROM access. */
1631 writeb (~EE_CS, ee_addr);
1637 /* Put the board into D3cold state and wait for WakeUp signal */
1638 static void cp_set_d3_state (struct cp_private *cp)
1640 pci_enable_wake (cp->pdev, 0, 1); /* Enable PME# generation */
1641 pci_set_power_state (cp->pdev, PCI_D3hot);
1644 static int cp_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1646 struct net_device *dev;
1647 struct cp_private *cp;
1651 unsigned int addr_len, i, pci_using_dac;
1655 static int version_printed;
1656 if (version_printed++ == 0)
1657 printk("%s", version);
1660 pci_read_config_byte(pdev, PCI_REVISION_ID, &pci_rev);
1662 if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&
1663 pdev->device == PCI_DEVICE_ID_REALTEK_8139 && pci_rev < 0x20) {
1664 printk(KERN_ERR PFX "pci dev %s (id %04x:%04x rev %02x) is not an 8139C+ compatible chip\n",
1665 pci_name(pdev), pdev->vendor, pdev->device, pci_rev);
1666 printk(KERN_ERR PFX "Try the \"8139too\" driver instead.\n");
1670 dev = alloc_etherdev(sizeof(struct cp_private));
1673 SET_MODULE_OWNER(dev);
1674 SET_NETDEV_DEV(dev, &pdev->dev);
1676 cp = netdev_priv(dev);
1679 cp->msg_enable = (debug < 0 ? CP_DEF_MSG_ENABLE : debug);
1680 spin_lock_init (&cp->lock);
1681 cp->mii_if.dev = dev;
1682 cp->mii_if.mdio_read = mdio_read;
1683 cp->mii_if.mdio_write = mdio_write;
1684 cp->mii_if.phy_id = CP_INTERNAL_PHY;
1685 cp->mii_if.phy_id_mask = 0x1f;
1686 cp->mii_if.reg_num_mask = 0x1f;
1687 cp_set_rxbufsize(cp);
1689 rc = pci_enable_device(pdev);
1693 rc = pci_set_mwi(pdev);
1695 goto err_out_disable;
1697 rc = pci_request_regions(pdev, DRV_NAME);
1701 pciaddr = pci_resource_start(pdev, 1);
1704 printk(KERN_ERR PFX "no MMIO resource for pci dev %s\n",
1708 if (pci_resource_len(pdev, 1) < CP_REGS_SIZE) {
1710 printk(KERN_ERR PFX "MMIO resource (%lx) too small on pci dev %s\n",
1711 pci_resource_len(pdev, 1), pci_name(pdev));
1715 /* Configure DMA attributes. */
1716 if ((sizeof(dma_addr_t) > 4) &&
1717 !pci_set_consistent_dma_mask(pdev, 0xffffffffffffffffULL) &&
1718 !pci_set_dma_mask(pdev, 0xffffffffffffffffULL)) {
1723 rc = pci_set_dma_mask(pdev, 0xffffffffULL);
1725 printk(KERN_ERR PFX "No usable DMA configuration, "
1729 rc = pci_set_consistent_dma_mask(pdev, 0xffffffffULL);
1731 printk(KERN_ERR PFX "No usable consistent DMA configuration, "
1737 cp->cpcmd = (pci_using_dac ? PCIDAC : 0) |
1738 PCIMulRW | RxChkSum | CpRxOn | CpTxOn;
1740 regs = ioremap(pciaddr, CP_REGS_SIZE);
1743 printk(KERN_ERR PFX "Cannot map PCI MMIO (%lx@%lx) on pci dev %s\n",
1744 pci_resource_len(pdev, 1), pciaddr, pci_name(pdev));
1747 dev->base_addr = (unsigned long) regs;
1752 /* read MAC address from EEPROM */
1753 addr_len = read_eeprom (regs, 0, 8) == 0x8129 ? 8 : 6;
1754 for (i = 0; i < 3; i++)
1755 ((u16 *) (dev->dev_addr))[i] =
1756 le16_to_cpu (read_eeprom (regs, i + 7, addr_len));
1758 dev->open = cp_open;
1759 dev->stop = cp_close;
1760 dev->set_multicast_list = cp_set_rx_mode;
1761 dev->hard_start_xmit = cp_start_xmit;
1762 dev->get_stats = cp_get_stats;
1763 dev->do_ioctl = cp_ioctl;
1764 dev->poll = cp_rx_poll;
1765 dev->weight = 16; /* arbitrary? from NAPI_HOWTO.txt. */
1767 dev->change_mtu = cp_change_mtu;
1769 dev->ethtool_ops = &cp_ethtool_ops;
1771 dev->tx_timeout = cp_tx_timeout;
1772 dev->watchdog_timeo = TX_TIMEOUT;
1775 #if CP_VLAN_TAG_USED
1776 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1777 dev->vlan_rx_register = cp_vlan_rx_register;
1778 dev->vlan_rx_kill_vid = cp_vlan_rx_kill_vid;
1782 dev->features |= NETIF_F_HIGHDMA;
1784 #if 0 /* disabled by default until verified */
1785 dev->features |= NETIF_F_TSO;
1788 dev->irq = pdev->irq;
1790 rc = register_netdev(dev);
1794 printk (KERN_INFO "%s: RTL-8139C+ at 0x%lx, "
1795 "%02x:%02x:%02x:%02x:%02x:%02x, "
1799 dev->dev_addr[0], dev->dev_addr[1],
1800 dev->dev_addr[2], dev->dev_addr[3],
1801 dev->dev_addr[4], dev->dev_addr[5],
1804 pci_set_drvdata(pdev, dev);
1806 /* enable busmastering and memory-write-invalidate */
1807 pci_set_master(pdev);
1809 if (cp->wol_enabled) cp_set_d3_state (cp);
1816 pci_release_regions(pdev);
1818 pci_clear_mwi(pdev);
1820 pci_disable_device(pdev);
1826 static void cp_remove_one (struct pci_dev *pdev)
1828 struct net_device *dev = pci_get_drvdata(pdev);
1829 struct cp_private *cp = netdev_priv(dev);
1833 unregister_netdev(dev);
1835 if (cp->wol_enabled) pci_set_power_state (pdev, PCI_D0);
1836 pci_release_regions(pdev);
1837 pci_clear_mwi(pdev);
1838 pci_disable_device(pdev);
1839 pci_set_drvdata(pdev, NULL);
1844 static int cp_suspend (struct pci_dev *pdev, pm_message_t state)
1846 struct net_device *dev;
1847 struct cp_private *cp;
1848 unsigned long flags;
1850 dev = pci_get_drvdata (pdev);
1851 cp = netdev_priv(dev);
1853 if (!dev || !netif_running (dev)) return 0;
1855 netif_device_detach (dev);
1856 netif_stop_queue (dev);
1858 spin_lock_irqsave (&cp->lock, flags);
1860 /* Disable Rx and Tx */
1861 cpw16 (IntrMask, 0);
1862 cpw8 (Cmd, cpr8 (Cmd) & (~RxOn | ~TxOn));
1864 spin_unlock_irqrestore (&cp->lock, flags);
1866 if (cp->pdev && cp->wol_enabled) {
1867 pci_save_state (cp->pdev);
1868 cp_set_d3_state (cp);
1874 static int cp_resume (struct pci_dev *pdev)
1876 struct net_device *dev;
1877 struct cp_private *cp;
1879 dev = pci_get_drvdata (pdev);
1880 cp = netdev_priv(dev);
1882 netif_device_attach (dev);
1884 if (cp->pdev && cp->wol_enabled) {
1885 pci_set_power_state (cp->pdev, PCI_D0);
1886 pci_restore_state (cp->pdev);
1890 netif_start_queue (dev);
1894 #endif /* CONFIG_PM */
1896 static struct pci_driver cp_driver = {
1898 .id_table = cp_pci_tbl,
1899 .probe = cp_init_one,
1900 .remove = cp_remove_one,
1902 .resume = cp_resume,
1903 .suspend = cp_suspend,
1907 static int __init cp_init (void)
1910 printk("%s", version);
1912 return pci_module_init (&cp_driver);
1915 static void __exit cp_exit (void)
1917 pci_unregister_driver (&cp_driver);
1920 module_init(cp_init);
1921 module_exit(cp_exit);