2 * linux/drivers/mmc/sdhci.c - Secure Digital Host Controller Interface driver
4 * Copyright (C) 2005-2007 Pierre Ossman, All Rights Reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
12 #include <linux/delay.h>
13 #include <linux/highmem.h>
14 #include <linux/pci.h>
15 #include <linux/dma-mapping.h>
17 #include <linux/mmc/host.h>
19 #include <asm/scatterlist.h>
23 #define DRIVER_NAME "sdhci"
25 #define DBG(f, x...) \
26 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
28 static unsigned int debug_nodma = 0;
29 static unsigned int debug_forcedma = 0;
30 static unsigned int debug_quirks = 0;
32 #define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1<<0)
33 #define SDHCI_QUIRK_FORCE_DMA (1<<1)
34 /* Controller doesn't like some resets when there is no card inserted. */
35 #define SDHCI_QUIRK_NO_CARD_NO_RESET (1<<2)
36 #define SDHCI_QUIRK_SINGLE_POWER_WRITE (1<<3)
38 static const struct pci_device_id pci_ids[] __devinitdata = {
40 .vendor = PCI_VENDOR_ID_RICOH,
41 .device = PCI_DEVICE_ID_RICOH_R5C822,
42 .subvendor = PCI_VENDOR_ID_IBM,
43 .subdevice = PCI_ANY_ID,
44 .driver_data = SDHCI_QUIRK_CLOCK_BEFORE_RESET |
45 SDHCI_QUIRK_FORCE_DMA,
49 .vendor = PCI_VENDOR_ID_RICOH,
50 .device = PCI_DEVICE_ID_RICOH_R5C822,
51 .subvendor = PCI_ANY_ID,
52 .subdevice = PCI_ANY_ID,
53 .driver_data = SDHCI_QUIRK_FORCE_DMA |
54 SDHCI_QUIRK_NO_CARD_NO_RESET,
58 .vendor = PCI_VENDOR_ID_TI,
59 .device = PCI_DEVICE_ID_TI_XX21_XX11_SD,
60 .subvendor = PCI_ANY_ID,
61 .subdevice = PCI_ANY_ID,
62 .driver_data = SDHCI_QUIRK_FORCE_DMA,
66 .vendor = PCI_VENDOR_ID_ENE,
67 .device = PCI_DEVICE_ID_ENE_CB712_SD,
68 .subvendor = PCI_ANY_ID,
69 .subdevice = PCI_ANY_ID,
70 .driver_data = SDHCI_QUIRK_SINGLE_POWER_WRITE,
74 .vendor = PCI_VENDOR_ID_ENE,
75 .device = PCI_DEVICE_ID_ENE_CB712_SD_2,
76 .subvendor = PCI_ANY_ID,
77 .subdevice = PCI_ANY_ID,
78 .driver_data = SDHCI_QUIRK_SINGLE_POWER_WRITE,
81 { /* Generic SD host controller */
82 PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00)
85 { /* end: all zeroes */ },
88 MODULE_DEVICE_TABLE(pci, pci_ids);
90 static void sdhci_prepare_data(struct sdhci_host *, struct mmc_data *);
91 static void sdhci_finish_data(struct sdhci_host *);
93 static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
94 static void sdhci_finish_command(struct sdhci_host *);
96 static void sdhci_dumpregs(struct sdhci_host *host)
98 printk(KERN_DEBUG DRIVER_NAME ": ============== REGISTER DUMP ==============\n");
100 printk(KERN_DEBUG DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
101 readl(host->ioaddr + SDHCI_DMA_ADDRESS),
102 readw(host->ioaddr + SDHCI_HOST_VERSION));
103 printk(KERN_DEBUG DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
104 readw(host->ioaddr + SDHCI_BLOCK_SIZE),
105 readw(host->ioaddr + SDHCI_BLOCK_COUNT));
106 printk(KERN_DEBUG DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
107 readl(host->ioaddr + SDHCI_ARGUMENT),
108 readw(host->ioaddr + SDHCI_TRANSFER_MODE));
109 printk(KERN_DEBUG DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
110 readl(host->ioaddr + SDHCI_PRESENT_STATE),
111 readb(host->ioaddr + SDHCI_HOST_CONTROL));
112 printk(KERN_DEBUG DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
113 readb(host->ioaddr + SDHCI_POWER_CONTROL),
114 readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL));
115 printk(KERN_DEBUG DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
116 readb(host->ioaddr + SDHCI_WALK_UP_CONTROL),
117 readw(host->ioaddr + SDHCI_CLOCK_CONTROL));
118 printk(KERN_DEBUG DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
119 readb(host->ioaddr + SDHCI_TIMEOUT_CONTROL),
120 readl(host->ioaddr + SDHCI_INT_STATUS));
121 printk(KERN_DEBUG DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
122 readl(host->ioaddr + SDHCI_INT_ENABLE),
123 readl(host->ioaddr + SDHCI_SIGNAL_ENABLE));
124 printk(KERN_DEBUG DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
125 readw(host->ioaddr + SDHCI_ACMD12_ERR),
126 readw(host->ioaddr + SDHCI_SLOT_INT_STATUS));
127 printk(KERN_DEBUG DRIVER_NAME ": Caps: 0x%08x | Max curr: 0x%08x\n",
128 readl(host->ioaddr + SDHCI_CAPABILITIES),
129 readl(host->ioaddr + SDHCI_MAX_CURRENT));
131 printk(KERN_DEBUG DRIVER_NAME ": ===========================================\n");
134 /*****************************************************************************\
136 * Low level functions *
138 \*****************************************************************************/
140 static void sdhci_reset(struct sdhci_host *host, u8 mask)
142 unsigned long timeout;
144 if (host->chip->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
145 if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) &
150 writeb(mask, host->ioaddr + SDHCI_SOFTWARE_RESET);
152 if (mask & SDHCI_RESET_ALL)
155 /* Wait max 100 ms */
158 /* hw clears the bit when it's done */
159 while (readb(host->ioaddr + SDHCI_SOFTWARE_RESET) & mask) {
161 printk(KERN_ERR "%s: Reset 0x%x never completed.\n",
162 mmc_hostname(host->mmc), (int)mask);
163 sdhci_dumpregs(host);
171 static void sdhci_init(struct sdhci_host *host)
175 sdhci_reset(host, SDHCI_RESET_ALL);
177 intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
178 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
179 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
180 SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT |
181 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL |
182 SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE;
184 writel(intmask, host->ioaddr + SDHCI_INT_ENABLE);
185 writel(intmask, host->ioaddr + SDHCI_SIGNAL_ENABLE);
188 static void sdhci_activate_led(struct sdhci_host *host)
192 ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
193 ctrl |= SDHCI_CTRL_LED;
194 writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
197 static void sdhci_deactivate_led(struct sdhci_host *host)
201 ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
202 ctrl &= ~SDHCI_CTRL_LED;
203 writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
206 /*****************************************************************************\
210 \*****************************************************************************/
212 static inline char* sdhci_sg_to_buffer(struct sdhci_host* host)
214 return page_address(host->cur_sg->page) + host->cur_sg->offset;
217 static inline int sdhci_next_sg(struct sdhci_host* host)
220 * Skip to next SG entry.
228 if (host->num_sg > 0) {
230 host->remain = host->cur_sg->length;
236 static void sdhci_read_block_pio(struct sdhci_host *host)
238 int blksize, chunk_remain;
243 DBG("PIO reading\n");
245 blksize = host->data->blksz;
249 buffer = sdhci_sg_to_buffer(host) + host->offset;
252 if (chunk_remain == 0) {
253 data = readl(host->ioaddr + SDHCI_BUFFER);
254 chunk_remain = min(blksize, 4);
257 size = min(host->remain, chunk_remain);
259 chunk_remain -= size;
261 host->offset += size;
262 host->remain -= size;
265 *buffer = data & 0xFF;
271 if (host->remain == 0) {
272 if (sdhci_next_sg(host) == 0) {
273 BUG_ON(blksize != 0);
276 buffer = sdhci_sg_to_buffer(host);
281 static void sdhci_write_block_pio(struct sdhci_host *host)
283 int blksize, chunk_remain;
288 DBG("PIO writing\n");
290 blksize = host->data->blksz;
295 buffer = sdhci_sg_to_buffer(host) + host->offset;
298 size = min(host->remain, chunk_remain);
300 chunk_remain -= size;
302 host->offset += size;
303 host->remain -= size;
307 data |= (u32)*buffer << 24;
312 if (chunk_remain == 0) {
313 writel(data, host->ioaddr + SDHCI_BUFFER);
314 chunk_remain = min(blksize, 4);
317 if (host->remain == 0) {
318 if (sdhci_next_sg(host) == 0) {
319 BUG_ON(blksize != 0);
322 buffer = sdhci_sg_to_buffer(host);
327 static void sdhci_transfer_pio(struct sdhci_host *host)
333 if (host->num_sg == 0)
336 if (host->data->flags & MMC_DATA_READ)
337 mask = SDHCI_DATA_AVAILABLE;
339 mask = SDHCI_SPACE_AVAILABLE;
341 while (readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask) {
342 if (host->data->flags & MMC_DATA_READ)
343 sdhci_read_block_pio(host);
345 sdhci_write_block_pio(host);
347 if (host->num_sg == 0)
351 DBG("PIO transfer complete.\n");
354 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_data *data)
357 unsigned target_timeout, current_timeout;
364 DBG("blksz %04x blks %04x flags %08x\n",
365 data->blksz, data->blocks, data->flags);
366 DBG("tsac %d ms nsac %d clk\n",
367 data->timeout_ns / 1000000, data->timeout_clks);
370 BUG_ON(data->blksz * data->blocks > 524288);
371 BUG_ON(data->blksz > host->mmc->max_blk_size);
372 BUG_ON(data->blocks > 65535);
375 target_timeout = data->timeout_ns / 1000 +
376 data->timeout_clks / host->clock;
379 * Figure out needed cycles.
380 * We do this in steps in order to fit inside a 32 bit int.
381 * The first step is the minimum timeout, which will have a
382 * minimum resolution of 6 bits:
383 * (1) 2^13*1000 > 2^22,
384 * (2) host->timeout_clk < 2^16
389 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
390 while (current_timeout < target_timeout) {
392 current_timeout <<= 1;
398 printk(KERN_WARNING "%s: Too large timeout requested!\n",
399 mmc_hostname(host->mmc));
403 writeb(count, host->ioaddr + SDHCI_TIMEOUT_CONTROL);
405 if (host->flags & SDHCI_USE_DMA) {
408 count = pci_map_sg(host->chip->pdev, data->sg, data->sg_len,
409 (data->flags & MMC_DATA_READ)?PCI_DMA_FROMDEVICE:PCI_DMA_TODEVICE);
412 writel(sg_dma_address(data->sg), host->ioaddr + SDHCI_DMA_ADDRESS);
414 host->cur_sg = data->sg;
415 host->num_sg = data->sg_len;
418 host->remain = host->cur_sg->length;
421 /* We do not handle DMA boundaries, so set it to max (512 KiB) */
422 writew(SDHCI_MAKE_BLKSZ(7, data->blksz),
423 host->ioaddr + SDHCI_BLOCK_SIZE);
424 writew(data->blocks, host->ioaddr + SDHCI_BLOCK_COUNT);
427 static void sdhci_set_transfer_mode(struct sdhci_host *host,
428 struct mmc_data *data)
437 mode = SDHCI_TRNS_BLK_CNT_EN;
438 if (data->blocks > 1)
439 mode |= SDHCI_TRNS_MULTI;
440 if (data->flags & MMC_DATA_READ)
441 mode |= SDHCI_TRNS_READ;
442 if (host->flags & SDHCI_USE_DMA)
443 mode |= SDHCI_TRNS_DMA;
445 writew(mode, host->ioaddr + SDHCI_TRANSFER_MODE);
448 static void sdhci_finish_data(struct sdhci_host *host)
450 struct mmc_data *data;
458 if (host->flags & SDHCI_USE_DMA) {
459 pci_unmap_sg(host->chip->pdev, data->sg, data->sg_len,
460 (data->flags & MMC_DATA_READ)?PCI_DMA_FROMDEVICE:PCI_DMA_TODEVICE);
464 * Controller doesn't count down when in single block mode.
466 if ((data->blocks == 1) && (data->error == MMC_ERR_NONE))
469 blocks = readw(host->ioaddr + SDHCI_BLOCK_COUNT);
470 data->bytes_xfered = data->blksz * (data->blocks - blocks);
472 if ((data->error == MMC_ERR_NONE) && blocks) {
473 printk(KERN_ERR "%s: Controller signalled completion even "
474 "though there were blocks left.\n",
475 mmc_hostname(host->mmc));
476 data->error = MMC_ERR_FAILED;
479 DBG("Ending data transfer (%d bytes)\n", data->bytes_xfered);
483 * The controller needs a reset of internal state machines
484 * upon error conditions.
486 if (data->error != MMC_ERR_NONE) {
487 sdhci_reset(host, SDHCI_RESET_CMD);
488 sdhci_reset(host, SDHCI_RESET_DATA);
491 sdhci_send_command(host, data->stop);
493 tasklet_schedule(&host->finish_tasklet);
496 static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
500 unsigned long timeout;
504 DBG("Sending cmd (%x)\n", cmd->opcode);
509 mask = SDHCI_CMD_INHIBIT;
510 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
511 mask |= SDHCI_DATA_INHIBIT;
513 /* We shouldn't wait for data inihibit for stop commands, even
514 though they might use busy signaling */
515 if (host->mrq->data && (cmd == host->mrq->data->stop))
516 mask &= ~SDHCI_DATA_INHIBIT;
518 while (readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask) {
520 printk(KERN_ERR "%s: Controller never released "
521 "inhibit bit(s).\n", mmc_hostname(host->mmc));
522 sdhci_dumpregs(host);
523 cmd->error = MMC_ERR_FAILED;
524 tasklet_schedule(&host->finish_tasklet);
531 mod_timer(&host->timer, jiffies + 10 * HZ);
535 sdhci_prepare_data(host, cmd->data);
537 writel(cmd->arg, host->ioaddr + SDHCI_ARGUMENT);
539 sdhci_set_transfer_mode(host, cmd->data);
541 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
542 printk(KERN_ERR "%s: Unsupported response type!\n",
543 mmc_hostname(host->mmc));
544 cmd->error = MMC_ERR_INVALID;
545 tasklet_schedule(&host->finish_tasklet);
549 if (!(cmd->flags & MMC_RSP_PRESENT))
550 flags = SDHCI_CMD_RESP_NONE;
551 else if (cmd->flags & MMC_RSP_136)
552 flags = SDHCI_CMD_RESP_LONG;
553 else if (cmd->flags & MMC_RSP_BUSY)
554 flags = SDHCI_CMD_RESP_SHORT_BUSY;
556 flags = SDHCI_CMD_RESP_SHORT;
558 if (cmd->flags & MMC_RSP_CRC)
559 flags |= SDHCI_CMD_CRC;
560 if (cmd->flags & MMC_RSP_OPCODE)
561 flags |= SDHCI_CMD_INDEX;
563 flags |= SDHCI_CMD_DATA;
565 writew(SDHCI_MAKE_CMD(cmd->opcode, flags),
566 host->ioaddr + SDHCI_COMMAND);
569 static void sdhci_finish_command(struct sdhci_host *host)
573 BUG_ON(host->cmd == NULL);
575 if (host->cmd->flags & MMC_RSP_PRESENT) {
576 if (host->cmd->flags & MMC_RSP_136) {
577 /* CRC is stripped so we need to do some shifting. */
578 for (i = 0;i < 4;i++) {
579 host->cmd->resp[i] = readl(host->ioaddr +
580 SDHCI_RESPONSE + (3-i)*4) << 8;
582 host->cmd->resp[i] |=
584 SDHCI_RESPONSE + (3-i)*4-1);
587 host->cmd->resp[0] = readl(host->ioaddr + SDHCI_RESPONSE);
591 host->cmd->error = MMC_ERR_NONE;
593 DBG("Ending cmd (%x)\n", host->cmd->opcode);
596 host->data = host->cmd->data;
598 tasklet_schedule(&host->finish_tasklet);
603 static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
607 unsigned long timeout;
609 if (clock == host->clock)
612 writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL);
617 for (div = 1;div < 256;div *= 2) {
618 if ((host->max_clk / div) <= clock)
623 clk = div << SDHCI_DIVIDER_SHIFT;
624 clk |= SDHCI_CLOCK_INT_EN;
625 writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL);
629 while (!((clk = readw(host->ioaddr + SDHCI_CLOCK_CONTROL))
630 & SDHCI_CLOCK_INT_STABLE)) {
632 printk(KERN_ERR "%s: Internal clock never "
633 "stabilised.\n", mmc_hostname(host->mmc));
634 sdhci_dumpregs(host);
641 clk |= SDHCI_CLOCK_CARD_EN;
642 writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL);
648 static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
652 if (host->power == power)
655 if (power == (unsigned short)-1) {
656 writeb(0, host->ioaddr + SDHCI_POWER_CONTROL);
661 * Spec says that we should clear the power reg before setting
662 * a new value. Some controllers don't seem to like this though.
664 if (!(host->chip->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
665 writeb(0, host->ioaddr + SDHCI_POWER_CONTROL);
667 pwr = SDHCI_POWER_ON;
669 switch (1 << power) {
670 case MMC_VDD_165_195:
671 pwr |= SDHCI_POWER_180;
675 pwr |= SDHCI_POWER_300;
679 pwr |= SDHCI_POWER_330;
685 writeb(pwr, host->ioaddr + SDHCI_POWER_CONTROL);
691 /*****************************************************************************\
695 \*****************************************************************************/
697 static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
699 struct sdhci_host *host;
702 host = mmc_priv(mmc);
704 spin_lock_irqsave(&host->lock, flags);
706 WARN_ON(host->mrq != NULL);
708 sdhci_activate_led(host);
712 if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
713 host->mrq->cmd->error = MMC_ERR_TIMEOUT;
714 tasklet_schedule(&host->finish_tasklet);
716 sdhci_send_command(host, mrq->cmd);
719 spin_unlock_irqrestore(&host->lock, flags);
722 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
724 struct sdhci_host *host;
728 host = mmc_priv(mmc);
730 spin_lock_irqsave(&host->lock, flags);
733 * Reset the chip on each power off.
734 * Should clear out any weird states.
736 if (ios->power_mode == MMC_POWER_OFF) {
737 writel(0, host->ioaddr + SDHCI_SIGNAL_ENABLE);
741 sdhci_set_clock(host, ios->clock);
743 if (ios->power_mode == MMC_POWER_OFF)
744 sdhci_set_power(host, -1);
746 sdhci_set_power(host, ios->vdd);
748 ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
750 if (ios->bus_width == MMC_BUS_WIDTH_4)
751 ctrl |= SDHCI_CTRL_4BITBUS;
753 ctrl &= ~SDHCI_CTRL_4BITBUS;
755 if (ios->timing == MMC_TIMING_SD_HS)
756 ctrl |= SDHCI_CTRL_HISPD;
758 ctrl &= ~SDHCI_CTRL_HISPD;
760 writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
763 spin_unlock_irqrestore(&host->lock, flags);
766 static int sdhci_get_ro(struct mmc_host *mmc)
768 struct sdhci_host *host;
772 host = mmc_priv(mmc);
774 spin_lock_irqsave(&host->lock, flags);
776 present = readl(host->ioaddr + SDHCI_PRESENT_STATE);
778 spin_unlock_irqrestore(&host->lock, flags);
780 return !(present & SDHCI_WRITE_PROTECT);
783 static const struct mmc_host_ops sdhci_ops = {
784 .request = sdhci_request,
785 .set_ios = sdhci_set_ios,
786 .get_ro = sdhci_get_ro,
789 /*****************************************************************************\
793 \*****************************************************************************/
795 static void sdhci_tasklet_card(unsigned long param)
797 struct sdhci_host *host;
800 host = (struct sdhci_host*)param;
802 spin_lock_irqsave(&host->lock, flags);
804 if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
806 printk(KERN_ERR "%s: Card removed during transfer!\n",
807 mmc_hostname(host->mmc));
808 printk(KERN_ERR "%s: Resetting controller.\n",
809 mmc_hostname(host->mmc));
811 sdhci_reset(host, SDHCI_RESET_CMD);
812 sdhci_reset(host, SDHCI_RESET_DATA);
814 host->mrq->cmd->error = MMC_ERR_FAILED;
815 tasklet_schedule(&host->finish_tasklet);
819 spin_unlock_irqrestore(&host->lock, flags);
821 mmc_detect_change(host->mmc, msecs_to_jiffies(500));
824 static void sdhci_tasklet_finish(unsigned long param)
826 struct sdhci_host *host;
828 struct mmc_request *mrq;
830 host = (struct sdhci_host*)param;
832 spin_lock_irqsave(&host->lock, flags);
834 del_timer(&host->timer);
838 DBG("Ending request, cmd (%x)\n", mrq->cmd->opcode);
841 * The controller needs a reset of internal state machines
842 * upon error conditions.
844 if ((mrq->cmd->error != MMC_ERR_NONE) ||
845 (mrq->data && ((mrq->data->error != MMC_ERR_NONE) ||
846 (mrq->data->stop && (mrq->data->stop->error != MMC_ERR_NONE))))) {
848 /* Some controllers need this kick or reset won't work here */
849 if (host->chip->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) {
852 /* This is to force an update */
855 sdhci_set_clock(host, clock);
858 /* Spec says we should do both at the same time, but Ricoh
859 controllers do not like that. */
860 sdhci_reset(host, SDHCI_RESET_CMD);
861 sdhci_reset(host, SDHCI_RESET_DATA);
868 sdhci_deactivate_led(host);
871 spin_unlock_irqrestore(&host->lock, flags);
873 mmc_request_done(host->mmc, mrq);
876 static void sdhci_timeout_timer(unsigned long data)
878 struct sdhci_host *host;
881 host = (struct sdhci_host*)data;
883 spin_lock_irqsave(&host->lock, flags);
886 printk(KERN_ERR "%s: Timeout waiting for hardware "
887 "interrupt.\n", mmc_hostname(host->mmc));
888 sdhci_dumpregs(host);
891 host->data->error = MMC_ERR_TIMEOUT;
892 sdhci_finish_data(host);
895 host->cmd->error = MMC_ERR_TIMEOUT;
897 host->mrq->cmd->error = MMC_ERR_TIMEOUT;
899 tasklet_schedule(&host->finish_tasklet);
904 spin_unlock_irqrestore(&host->lock, flags);
907 /*****************************************************************************\
909 * Interrupt handling *
911 \*****************************************************************************/
913 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
915 BUG_ON(intmask == 0);
918 printk(KERN_ERR "%s: Got command interrupt even though no "
919 "command operation was in progress.\n",
920 mmc_hostname(host->mmc));
921 sdhci_dumpregs(host);
925 if (intmask & SDHCI_INT_TIMEOUT)
926 host->cmd->error = MMC_ERR_TIMEOUT;
927 else if (intmask & SDHCI_INT_CRC)
928 host->cmd->error = MMC_ERR_BADCRC;
929 else if (intmask & (SDHCI_INT_END_BIT | SDHCI_INT_INDEX))
930 host->cmd->error = MMC_ERR_FAILED;
932 if (host->cmd->error != MMC_ERR_NONE)
933 tasklet_schedule(&host->finish_tasklet);
934 else if (intmask & SDHCI_INT_RESPONSE)
935 sdhci_finish_command(host);
938 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
940 BUG_ON(intmask == 0);
944 * A data end interrupt is sent together with the response
945 * for the stop command.
947 if (intmask & SDHCI_INT_DATA_END)
950 printk(KERN_ERR "%s: Got data interrupt even though no "
951 "data operation was in progress.\n",
952 mmc_hostname(host->mmc));
953 sdhci_dumpregs(host);
958 if (intmask & SDHCI_INT_DATA_TIMEOUT)
959 host->data->error = MMC_ERR_TIMEOUT;
960 else if (intmask & SDHCI_INT_DATA_CRC)
961 host->data->error = MMC_ERR_BADCRC;
962 else if (intmask & SDHCI_INT_DATA_END_BIT)
963 host->data->error = MMC_ERR_FAILED;
965 if (host->data->error != MMC_ERR_NONE)
966 sdhci_finish_data(host);
968 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
969 sdhci_transfer_pio(host);
972 * We currently don't do anything fancy with DMA
973 * boundaries, but as we can't disable the feature
974 * we need to at least restart the transfer.
976 if (intmask & SDHCI_INT_DMA_END)
977 writel(readl(host->ioaddr + SDHCI_DMA_ADDRESS),
978 host->ioaddr + SDHCI_DMA_ADDRESS);
980 if (intmask & SDHCI_INT_DATA_END)
981 sdhci_finish_data(host);
985 static irqreturn_t sdhci_irq(int irq, void *dev_id)
988 struct sdhci_host* host = dev_id;
991 spin_lock(&host->lock);
993 intmask = readl(host->ioaddr + SDHCI_INT_STATUS);
995 if (!intmask || intmask == 0xffffffff) {
1000 DBG("*** %s got interrupt: 0x%08x\n", host->slot_descr, intmask);
1002 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
1003 writel(intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE),
1004 host->ioaddr + SDHCI_INT_STATUS);
1005 tasklet_schedule(&host->card_tasklet);
1008 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
1010 if (intmask & SDHCI_INT_CMD_MASK) {
1011 writel(intmask & SDHCI_INT_CMD_MASK,
1012 host->ioaddr + SDHCI_INT_STATUS);
1013 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
1016 if (intmask & SDHCI_INT_DATA_MASK) {
1017 writel(intmask & SDHCI_INT_DATA_MASK,
1018 host->ioaddr + SDHCI_INT_STATUS);
1019 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
1022 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
1024 intmask &= ~SDHCI_INT_ERROR;
1026 if (intmask & SDHCI_INT_BUS_POWER) {
1027 printk(KERN_ERR "%s: Card is consuming too much power!\n",
1028 mmc_hostname(host->mmc));
1029 writel(SDHCI_INT_BUS_POWER, host->ioaddr + SDHCI_INT_STATUS);
1032 intmask &= ~SDHCI_INT_BUS_POWER;
1035 printk(KERN_ERR "%s: Unexpected interrupt 0x%08x.\n",
1036 mmc_hostname(host->mmc), intmask);
1037 sdhci_dumpregs(host);
1039 writel(intmask, host->ioaddr + SDHCI_INT_STATUS);
1042 result = IRQ_HANDLED;
1046 spin_unlock(&host->lock);
1051 /*****************************************************************************\
1055 \*****************************************************************************/
1059 static int sdhci_suspend (struct pci_dev *pdev, pm_message_t state)
1061 struct sdhci_chip *chip;
1064 chip = pci_get_drvdata(pdev);
1068 DBG("Suspending...\n");
1070 for (i = 0;i < chip->num_slots;i++) {
1071 if (!chip->hosts[i])
1073 ret = mmc_suspend_host(chip->hosts[i]->mmc, state);
1075 for (i--;i >= 0;i--)
1076 mmc_resume_host(chip->hosts[i]->mmc);
1081 pci_save_state(pdev);
1082 pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
1084 for (i = 0;i < chip->num_slots;i++) {
1085 if (!chip->hosts[i])
1087 free_irq(chip->hosts[i]->irq, chip->hosts[i]);
1090 pci_disable_device(pdev);
1091 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1096 static int sdhci_resume (struct pci_dev *pdev)
1098 struct sdhci_chip *chip;
1101 chip = pci_get_drvdata(pdev);
1105 DBG("Resuming...\n");
1107 pci_set_power_state(pdev, PCI_D0);
1108 pci_restore_state(pdev);
1109 ret = pci_enable_device(pdev);
1113 for (i = 0;i < chip->num_slots;i++) {
1114 if (!chip->hosts[i])
1116 if (chip->hosts[i]->flags & SDHCI_USE_DMA)
1117 pci_set_master(pdev);
1118 ret = request_irq(chip->hosts[i]->irq, sdhci_irq,
1119 IRQF_SHARED, chip->hosts[i]->slot_descr,
1123 sdhci_init(chip->hosts[i]);
1125 ret = mmc_resume_host(chip->hosts[i]->mmc);
1133 #else /* CONFIG_PM */
1135 #define sdhci_suspend NULL
1136 #define sdhci_resume NULL
1138 #endif /* CONFIG_PM */
1140 /*****************************************************************************\
1142 * Device probing/removal *
1144 \*****************************************************************************/
1146 static int __devinit sdhci_probe_slot(struct pci_dev *pdev, int slot)
1149 unsigned int version;
1150 struct sdhci_chip *chip;
1151 struct mmc_host *mmc;
1152 struct sdhci_host *host;
1157 chip = pci_get_drvdata(pdev);
1160 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar);
1164 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK;
1166 if (first_bar > 5) {
1167 printk(KERN_ERR DRIVER_NAME ": Invalid first BAR. Aborting.\n");
1171 if (!(pci_resource_flags(pdev, first_bar + slot) & IORESOURCE_MEM)) {
1172 printk(KERN_ERR DRIVER_NAME ": BAR is not iomem. Aborting.\n");
1176 if (pci_resource_len(pdev, first_bar + slot) != 0x100) {
1177 printk(KERN_ERR DRIVER_NAME ": Invalid iomem size. "
1178 "You may experience problems.\n");
1181 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
1182 printk(KERN_ERR DRIVER_NAME ": Vendor specific interface. Aborting.\n");
1186 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) {
1187 printk(KERN_ERR DRIVER_NAME ": Unknown interface. Aborting.\n");
1191 mmc = mmc_alloc_host(sizeof(struct sdhci_host), &pdev->dev);
1195 host = mmc_priv(mmc);
1199 chip->hosts[slot] = host;
1201 host->bar = first_bar + slot;
1203 host->addr = pci_resource_start(pdev, host->bar);
1204 host->irq = pdev->irq;
1206 DBG("slot %d at 0x%08lx, irq %d\n", slot, host->addr, host->irq);
1208 snprintf(host->slot_descr, 20, "sdhci:slot%d", slot);
1210 ret = pci_request_region(pdev, host->bar, host->slot_descr);
1214 host->ioaddr = ioremap_nocache(host->addr,
1215 pci_resource_len(pdev, host->bar));
1216 if (!host->ioaddr) {
1221 sdhci_reset(host, SDHCI_RESET_ALL);
1223 version = readw(host->ioaddr + SDHCI_HOST_VERSION);
1224 version = (version & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT;
1226 printk(KERN_ERR "%s: Unknown controller version (%d). "
1227 "You may experience problems.\n", host->slot_descr,
1231 caps = readl(host->ioaddr + SDHCI_CAPABILITIES);
1234 DBG("DMA forced off\n");
1235 else if (debug_forcedma) {
1236 DBG("DMA forced on\n");
1237 host->flags |= SDHCI_USE_DMA;
1238 } else if (chip->quirks & SDHCI_QUIRK_FORCE_DMA)
1239 host->flags |= SDHCI_USE_DMA;
1240 else if ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA)
1241 DBG("Controller doesn't have DMA interface\n");
1242 else if (!(caps & SDHCI_CAN_DO_DMA))
1243 DBG("Controller doesn't have DMA capability\n");
1245 host->flags |= SDHCI_USE_DMA;
1247 if (host->flags & SDHCI_USE_DMA) {
1248 if (pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
1249 printk(KERN_WARNING "%s: No suitable DMA available. "
1250 "Falling back to PIO.\n", host->slot_descr);
1251 host->flags &= ~SDHCI_USE_DMA;
1255 if (host->flags & SDHCI_USE_DMA)
1256 pci_set_master(pdev);
1257 else /* XXX: Hack to get MMC layer to avoid highmem */
1261 (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
1262 if (host->max_clk == 0) {
1263 printk(KERN_ERR "%s: Hardware doesn't specify base clock "
1264 "frequency.\n", host->slot_descr);
1268 host->max_clk *= 1000000;
1271 (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
1272 if (host->timeout_clk == 0) {
1273 printk(KERN_ERR "%s: Hardware doesn't specify timeout clock "
1274 "frequency.\n", host->slot_descr);
1278 if (caps & SDHCI_TIMEOUT_CLK_UNIT)
1279 host->timeout_clk *= 1000;
1282 * Set host parameters.
1284 mmc->ops = &sdhci_ops;
1285 mmc->f_min = host->max_clk / 256;
1286 mmc->f_max = host->max_clk;
1287 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_MULTIWRITE | MMC_CAP_BYTEBLOCK;
1289 if (caps & SDHCI_CAN_DO_HISPD)
1290 mmc->caps |= MMC_CAP_SD_HIGHSPEED;
1293 if (caps & SDHCI_CAN_VDD_330)
1294 mmc->ocr_avail |= MMC_VDD_32_33|MMC_VDD_33_34;
1295 if (caps & SDHCI_CAN_VDD_300)
1296 mmc->ocr_avail |= MMC_VDD_29_30|MMC_VDD_30_31;
1297 if (caps & SDHCI_CAN_VDD_180)
1298 mmc->ocr_avail |= MMC_VDD_165_195;
1300 if (mmc->ocr_avail == 0) {
1301 printk(KERN_ERR "%s: Hardware doesn't report any "
1302 "support voltages.\n", host->slot_descr);
1307 spin_lock_init(&host->lock);
1310 * Maximum number of segments. Hardware cannot do scatter lists.
1312 if (host->flags & SDHCI_USE_DMA)
1313 mmc->max_hw_segs = 1;
1315 mmc->max_hw_segs = 16;
1316 mmc->max_phys_segs = 16;
1319 * Maximum number of sectors in one transfer. Limited by DMA boundary
1322 mmc->max_req_size = 524288;
1325 * Maximum segment size. Could be one segment with the maximum number
1328 mmc->max_seg_size = mmc->max_req_size;
1331 * Maximum block size. This varies from controller to controller and
1332 * is specified in the capabilities register.
1334 mmc->max_blk_size = (caps & SDHCI_MAX_BLOCK_MASK) >> SDHCI_MAX_BLOCK_SHIFT;
1335 if (mmc->max_blk_size >= 3) {
1336 printk(KERN_ERR "%s: Invalid maximum block size.\n",
1341 mmc->max_blk_size = 512 << mmc->max_blk_size;
1344 * Maximum block count.
1346 mmc->max_blk_count = 65535;
1351 tasklet_init(&host->card_tasklet,
1352 sdhci_tasklet_card, (unsigned long)host);
1353 tasklet_init(&host->finish_tasklet,
1354 sdhci_tasklet_finish, (unsigned long)host);
1356 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
1358 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
1359 host->slot_descr, host);
1365 #ifdef CONFIG_MMC_DEBUG
1366 sdhci_dumpregs(host);
1373 printk(KERN_INFO "%s: SDHCI at 0x%08lx irq %d %s\n", mmc_hostname(mmc),
1374 host->addr, host->irq,
1375 (host->flags & SDHCI_USE_DMA)?"DMA":"PIO");
1380 tasklet_kill(&host->card_tasklet);
1381 tasklet_kill(&host->finish_tasklet);
1383 iounmap(host->ioaddr);
1385 pci_release_region(pdev, host->bar);
1392 static void sdhci_remove_slot(struct pci_dev *pdev, int slot)
1394 struct sdhci_chip *chip;
1395 struct mmc_host *mmc;
1396 struct sdhci_host *host;
1398 chip = pci_get_drvdata(pdev);
1399 host = chip->hosts[slot];
1402 chip->hosts[slot] = NULL;
1404 mmc_remove_host(mmc);
1406 sdhci_reset(host, SDHCI_RESET_ALL);
1408 free_irq(host->irq, host);
1410 del_timer_sync(&host->timer);
1412 tasklet_kill(&host->card_tasklet);
1413 tasklet_kill(&host->finish_tasklet);
1415 iounmap(host->ioaddr);
1417 pci_release_region(pdev, host->bar);
1422 static int __devinit sdhci_probe(struct pci_dev *pdev,
1423 const struct pci_device_id *ent)
1427 struct sdhci_chip *chip;
1429 BUG_ON(pdev == NULL);
1430 BUG_ON(ent == NULL);
1432 pci_read_config_byte(pdev, PCI_CLASS_REVISION, &rev);
1434 printk(KERN_INFO DRIVER_NAME
1435 ": SDHCI controller found at %s [%04x:%04x] (rev %x)\n",
1436 pci_name(pdev), (int)pdev->vendor, (int)pdev->device,
1439 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots);
1443 slots = PCI_SLOT_INFO_SLOTS(slots) + 1;
1444 DBG("found %d slot(s)\n", slots);
1448 ret = pci_enable_device(pdev);
1452 chip = kzalloc(sizeof(struct sdhci_chip) +
1453 sizeof(struct sdhci_host*) * slots, GFP_KERNEL);
1460 chip->quirks = ent->driver_data;
1463 chip->quirks = debug_quirks;
1465 chip->num_slots = slots;
1466 pci_set_drvdata(pdev, chip);
1468 for (i = 0;i < slots;i++) {
1469 ret = sdhci_probe_slot(pdev, i);
1471 for (i--;i >= 0;i--)
1472 sdhci_remove_slot(pdev, i);
1480 pci_set_drvdata(pdev, NULL);
1484 pci_disable_device(pdev);
1488 static void __devexit sdhci_remove(struct pci_dev *pdev)
1491 struct sdhci_chip *chip;
1493 chip = pci_get_drvdata(pdev);
1496 for (i = 0;i < chip->num_slots;i++)
1497 sdhci_remove_slot(pdev, i);
1499 pci_set_drvdata(pdev, NULL);
1504 pci_disable_device(pdev);
1507 static struct pci_driver sdhci_driver = {
1508 .name = DRIVER_NAME,
1509 .id_table = pci_ids,
1510 .probe = sdhci_probe,
1511 .remove = __devexit_p(sdhci_remove),
1512 .suspend = sdhci_suspend,
1513 .resume = sdhci_resume,
1516 /*****************************************************************************\
1518 * Driver init/exit *
1520 \*****************************************************************************/
1522 static int __init sdhci_drv_init(void)
1524 printk(KERN_INFO DRIVER_NAME
1525 ": Secure Digital Host Controller Interface driver\n");
1526 printk(KERN_INFO DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
1528 return pci_register_driver(&sdhci_driver);
1531 static void __exit sdhci_drv_exit(void)
1535 pci_unregister_driver(&sdhci_driver);
1538 module_init(sdhci_drv_init);
1539 module_exit(sdhci_drv_exit);
1541 module_param(debug_nodma, uint, 0444);
1542 module_param(debug_forcedma, uint, 0444);
1543 module_param(debug_quirks, uint, 0444);
1545 MODULE_AUTHOR("Pierre Ossman <drzeus@drzeus.cx>");
1546 MODULE_DESCRIPTION("Secure Digital Host Controller Interface driver");
1547 MODULE_LICENSE("GPL");
1549 MODULE_PARM_DESC(debug_nodma, "Forcefully disable DMA transfers. (default 0)");
1550 MODULE_PARM_DESC(debug_forcedma, "Forcefully enable DMA transfers. (default 0)");
1551 MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");