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   1 /*
   2  *  linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
   3  *
   4  *  Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or (at
   9  * your option) any later version.
  10  *
  11  * Thanks to the following companies for their support:
  12  *
  13  *     - JMicron (hardware and technical support)
  14  */
  15
  16 #include <linux/delay.h>
  17 #include <linux/highmem.h>
  18 #include <linux/io.h>
  19 #include <linux/dma-mapping.h>
  20 #include <linux/slab.h>
  21 #include <linux/scatterlist.h>
  22
  23 #include <linux/leds.h>
  24
  25 #include <linux/mmc/host.h>
  26
  27 #include "sdhci.h"
  28
  29 #define DRIVER_NAME "sdhci"
  30
  31 #define DBG(f, x...) \
  32         pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
  33
  34 #if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
  35         defined(CONFIG_MMC_SDHCI_MODULE))
  36 #define SDHCI_USE_LEDS_CLASS
  37 #endif
  38
  39 static unsigned int debug_quirks = 0;
  40
  41 static void sdhci_prepare_data(struct sdhci_host *, struct mmc_data *);
  42 static void sdhci_finish_data(struct sdhci_host *);
  43
  44 static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
  45 static void sdhci_finish_command(struct sdhci_host *);
  46
  47 static void sdhci_dumpregs(struct sdhci_host *host)
  48 {
  49         printk(KERN_DEBUG DRIVER_NAME ": ============== REGISTER DUMP ==============\n");
  50
  51         printk(KERN_DEBUG DRIVER_NAME ": Sys addr: 0x%08x | Version:  0x%08x\n",
  52                 sdhci_readl(host, SDHCI_DMA_ADDRESS),
  53                 sdhci_readw(host, SDHCI_HOST_VERSION));
  54         printk(KERN_DEBUG DRIVER_NAME ": Blk size: 0x%08x | Blk cnt:  0x%08x\n",
  55                 sdhci_readw(host, SDHCI_BLOCK_SIZE),
  56                 sdhci_readw(host, SDHCI_BLOCK_COUNT));
  57         printk(KERN_DEBUG DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
  58                 sdhci_readl(host, SDHCI_ARGUMENT),
  59                 sdhci_readw(host, SDHCI_TRANSFER_MODE));
  60         printk(KERN_DEBUG DRIVER_NAME ": Present:  0x%08x | Host ctl: 0x%08x\n",
  61                 sdhci_readl(host, SDHCI_PRESENT_STATE),
  62                 sdhci_readb(host, SDHCI_HOST_CONTROL));
  63         printk(KERN_DEBUG DRIVER_NAME ": Power:    0x%08x | Blk gap:  0x%08x\n",
  64                 sdhci_readb(host, SDHCI_POWER_CONTROL),
  65                 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
  66         printk(KERN_DEBUG DRIVER_NAME ": Wake-up:  0x%08x | Clock:    0x%08x\n",
  67                 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
  68                 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
  69         printk(KERN_DEBUG DRIVER_NAME ": Timeout:  0x%08x | Int stat: 0x%08x\n",
  70                 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
  71                 sdhci_readl(host, SDHCI_INT_STATUS));
  72         printk(KERN_DEBUG DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
  73                 sdhci_readl(host, SDHCI_INT_ENABLE),
  74                 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
  75         printk(KERN_DEBUG DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
  76                 sdhci_readw(host, SDHCI_ACMD12_ERR),
  77                 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
  78         printk(KERN_DEBUG DRIVER_NAME ": Caps:     0x%08x | Max curr: 0x%08x\n",
  79                 sdhci_readl(host, SDHCI_CAPABILITIES),
  80                 sdhci_readl(host, SDHCI_MAX_CURRENT));
  81
  82         if (host->flags & SDHCI_USE_ADMA)
  83                 printk(KERN_DEBUG DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
  84                        readl(host->ioaddr + SDHCI_ADMA_ERROR),
  85                        readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
  86
  87         printk(KERN_DEBUG DRIVER_NAME ": ===========================================\n");
  88 }
  89
  90 /*****************************************************************************\
  91  *                                                                           *
  92  * Low level functions                                                       *
  93  *                                                                           *
  94 \*****************************************************************************/
  95
  96 static void sdhci_clear_set_irqs(struct sdhci_host *host, u32 clear, u32 set)
  97 {
  98         u32 ier;
  99
 100         ier = sdhci_readl(host, SDHCI_INT_ENABLE);
 101         ier &= ~clear;
 102         ier |= set;
 103         sdhci_writel(host, ier, SDHCI_INT_ENABLE);
 104         sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE);
 105 }
 106
 107 static void sdhci_unmask_irqs(struct sdhci_host *host, u32 irqs)
 108 {
 109         sdhci_clear_set_irqs(host, 0, irqs);
 110 }
 111
 112 static void sdhci_mask_irqs(struct sdhci_host *host, u32 irqs)
 113 {
 114         sdhci_clear_set_irqs(host, irqs, 0);
 115 }
 116
 117 static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
 118 {
 119         u32 irqs = SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT;
 120
 121         if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
 122                 return;
 123
 124         if (enable)
 125                 sdhci_unmask_irqs(host, irqs);
 126         else
 127                 sdhci_mask_irqs(host, irqs);
 128 }
 129
 130 static void sdhci_enable_card_detection(struct sdhci_host *host)
 131 {
 132         sdhci_set_card_detection(host, true);
 133 }
 134
 135 static void sdhci_disable_card_detection(struct sdhci_host *host)
 136 {
 137         sdhci_set_card_detection(host, false);
 138 }
 139
 140 static void sdhci_reset(struct sdhci_host *host, u8 mask)
 141 {
 142         unsigned long timeout;
 143         u32 uninitialized_var(ier);
 144
 145         if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
 146                 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
 147                         SDHCI_CARD_PRESENT))
 148                         return;
 149         }
 150
 151         if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
 152                 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
 153
 154         sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
 155
 156         if (mask & SDHCI_RESET_ALL)
 157                 host->clock = 0;
 158
 159         /* Wait max 100 ms */
 160         timeout = 100;
 161
 162         /* hw clears the bit when it's done */
 163         while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
 164                 if (timeout == 0) {
 165                         printk(KERN_ERR "%s: Reset 0x%x never completed.\n",
 166                                 mmc_hostname(host->mmc), (int)mask);
 167                         sdhci_dumpregs(host);
 168                         return;
 169                 }
 170                 timeout--;
 171                 mdelay(1);
 172         }
 173
 174         if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
 175                 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK, ier);
 176 }
 177
 178 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
 179
 180 static void sdhci_init(struct sdhci_host *host, int soft)
 181 {
 182         if (soft)
 183                 sdhci_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
 184         else
 185                 sdhci_reset(host, SDHCI_RESET_ALL);
 186
 187         sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK,
 188                 SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
 189                 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
 190                 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
 191                 SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE);
 192
 193         if (soft) {
 194                 /* force clock reconfiguration */
 195                 host->clock = 0;
 196                 sdhci_set_ios(host->mmc, &host->mmc->ios);
 197         }
 198 }
 199
 200 static void sdhci_reinit(struct sdhci_host *host)
 201 {
 202         sdhci_init(host, 0);
 203         sdhci_enable_card_detection(host);
 204 }
 205
 206 static void sdhci_activate_led(struct sdhci_host *host)
 207 {
 208         u8 ctrl;
 209
 210         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 211         ctrl |= SDHCI_CTRL_LED;
 212         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 213 }
 214
 215 static void sdhci_deactivate_led(struct sdhci_host *host)
 216 {
 217         u8 ctrl;
 218
 219         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 220         ctrl &= ~SDHCI_CTRL_LED;
 221         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 222 }
 223
 224 #ifdef SDHCI_USE_LEDS_CLASS
 225 static void sdhci_led_control(struct led_classdev *led,
 226         enum led_brightness brightness)
 227 {
 228         struct sdhci_host *host = container_of(led, struct sdhci_host, led);
 229         unsigned long flags;
 230
 231         spin_lock_irqsave(&host->lock, flags);
 232
 233         if (brightness == LED_OFF)
 234                 sdhci_deactivate_led(host);
 235         else
 236                 sdhci_activate_led(host);
 237
 238         spin_unlock_irqrestore(&host->lock, flags);
 239 }
 240 #endif
 241
 242 /*****************************************************************************\
 243  *                                                                           *
 244  * Core functions                                                            *
 245  *                                                                           *
 246 \*****************************************************************************/
 247
 248 static void sdhci_read_block_pio(struct sdhci_host *host)
 249 {
 250         unsigned long flags;
 251         size_t blksize, len, chunk;
 252         u32 uninitialized_var(scratch);
 253         u8 *buf;
 254
 255         DBG("PIO reading\n");
 256
 257         blksize = host->data->blksz;
 258         chunk = 0;
 259
 260         local_irq_save(flags);
 261
 262         while (blksize) {
 263                 if (!sg_miter_next(&host->sg_miter))
 264                         BUG();
 265
 266                 len = min(host->sg_miter.length, blksize);
 267
 268                 blksize -= len;
 269                 host->sg_miter.consumed = len;
 270
 271                 buf = host->sg_miter.addr;
 272
 273                 while (len) {
 274                         if (chunk == 0) {
 275                                 scratch = sdhci_readl(host, SDHCI_BUFFER);
 276                                 chunk = 4;
 277                         }
 278
 279                         *buf = scratch & 0xFF;
 280
 281                         buf++;
 282                         scratch >>= 8;
 283                         chunk--;
 284                         len--;
 285                 }
 286         }
 287
 288         sg_miter_stop(&host->sg_miter);
 289
 290         local_irq_restore(flags);
 291 }
 292
 293 static void sdhci_write_block_pio(struct sdhci_host *host)
 294 {
 295         unsigned long flags;
 296         size_t blksize, len, chunk;
 297         u32 scratch;
 298         u8 *buf;
 299
 300         DBG("PIO writing\n");
 301
 302         blksize = host->data->blksz;
 303         chunk = 0;
 304         scratch = 0;
 305
 306         local_irq_save(flags);
 307
 308         while (blksize) {
 309                 if (!sg_miter_next(&host->sg_miter))
 310                         BUG();
 311
 312                 len = min(host->sg_miter.length, blksize);
 313
 314                 blksize -= len;
 315                 host->sg_miter.consumed = len;
 316
 317                 buf = host->sg_miter.addr;
 318
 319                 while (len) {
 320                         scratch |= (u32)*buf << (chunk * 8);
 321
 322                         buf++;
 323                         chunk++;
 324                         len--;
 325
 326                         if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
 327                                 sdhci_writel(host, scratch, SDHCI_BUFFER);
 328                                 chunk = 0;
 329                                 scratch = 0;
 330                         }
 331                 }
 332         }
 333
 334         sg_miter_stop(&host->sg_miter);
 335
 336         local_irq_restore(flags);
 337 }
 338
 339 static void sdhci_transfer_pio(struct sdhci_host *host)
 340 {
 341         u32 mask;
 342
 343         BUG_ON(!host->data);
 344
 345         if (host->blocks == 0)
 346                 return;
 347
 348         if (host->data->flags & MMC_DATA_READ)
 349                 mask = SDHCI_DATA_AVAILABLE;
 350         else
 351                 mask = SDHCI_SPACE_AVAILABLE;
 352
 353         /*
 354          * Some controllers (JMicron JMB38x) mess up the buffer bits
 355          * for transfers < 4 bytes. As long as it is just one block,
 356          * we can ignore the bits.
 357          */
 358         if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
 359                 (host->data->blocks == 1))
 360                 mask = ~0;
 361
 362         while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
 363                 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
 364                         udelay(100);
 365
 366                 if (host->data->flags & MMC_DATA_READ)
 367                         sdhci_read_block_pio(host);
 368                 else
 369                         sdhci_write_block_pio(host);
 370
 371                 host->blocks--;
 372                 if (host->blocks == 0)
 373                         break;
 374         }
 375
 376         DBG("PIO transfer complete.\n");
 377 }
 378
 379 static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
 380 {
 381         local_irq_save(*flags);
 382         return kmap_atomic(sg_page(sg), KM_BIO_SRC_IRQ) + sg->offset;
 383 }
 384
 385 static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
 386 {
 387         kunmap_atomic(buffer, KM_BIO_SRC_IRQ);
 388         local_irq_restore(*flags);
 389 }
 390
 391 static void sdhci_set_adma_desc(u8 *desc, u32 addr, int len, unsigned cmd)
 392 {
 393         __le32 *dataddr = (__le32 __force *)(desc + 4);
 394         __le16 *cmdlen = (__le16 __force *)desc;
 395
 396         /* SDHCI specification says ADMA descriptors should be 4 byte
 397          * aligned, so using 16 or 32bit operations should be safe. */
 398
 399         cmdlen[0] = cpu_to_le16(cmd);
 400         cmdlen[1] = cpu_to_le16(len);
 401
 402         dataddr[0] = cpu_to_le32(addr);
 403 }
 404
 405 static int sdhci_adma_table_pre(struct sdhci_host *host,
 406         struct mmc_data *data)
 407 {
 408         int direction;
 409
 410         u8 *desc;
 411         u8 *align;
 412         dma_addr_t addr;
 413         dma_addr_t align_addr;
 414         int len, offset;
 415
 416         struct scatterlist *sg;
 417         int i;
 418         char *buffer;
 419         unsigned long flags;
 420
 421         /*
 422          * The spec does not specify endianness of descriptor table.
 423          * We currently guess that it is LE.
 424          */
 425
 426         if (data->flags & MMC_DATA_READ)
 427                 direction = DMA_FROM_DEVICE;
 428         else
 429                 direction = DMA_TO_DEVICE;
 430
 431         /*
 432          * The ADMA descriptor table is mapped further down as we
 433          * need to fill it with data first.
 434          */
 435
 436         host->align_addr = dma_map_single(mmc_dev(host->mmc),
 437                 host->align_buffer, 128 * 4, direction);
 438         if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
 439                 goto fail;
 440         BUG_ON(host->align_addr & 0x3);
 441
 442         host->sg_count = dma_map_sg(mmc_dev(host->mmc),
 443                 data->sg, data->sg_len, direction);
 444         if (host->sg_count == 0)
 445                 goto unmap_align;
 446
 447         desc = host->adma_desc;
 448         align = host->align_buffer;
 449
 450         align_addr = host->align_addr;
 451
 452         for_each_sg(data->sg, sg, host->sg_count, i) {
 453                 addr = sg_dma_address(sg);
 454                 len = sg_dma_len(sg);
 455
 456                 /*
 457                  * The SDHCI specification states that ADMA
 458                  * addresses must be 32-bit aligned. If they
 459                  * aren't, then we use a bounce buffer for
 460                  * the (up to three) bytes that screw up the
 461                  * alignment.
 462                  */
 463                 offset = (4 - (addr & 0x3)) & 0x3;
 464                 if (offset) {
 465                         if (data->flags & MMC_DATA_WRITE) {
 466                                 buffer = sdhci_kmap_atomic(sg, &flags);
 467                                 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
 468                                 memcpy(align, buffer, offset);
 469                                 sdhci_kunmap_atomic(buffer, &flags);
 470                         }
 471
 472                         /* tran, valid */
 473                         sdhci_set_adma_desc(desc, align_addr, offset, 0x21);
 474
 475                         BUG_ON(offset > 65536);
 476
 477                         align += 4;
 478                         align_addr += 4;
 479
 480                         desc += 8;
 481
 482                         addr += offset;
 483                         len -= offset;
 484                 }
 485
 486                 BUG_ON(len > 65536);
 487
 488                 /* tran, valid */
 489                 sdhci_set_adma_desc(desc, addr, len, 0x21);
 490                 desc += 8;
 491
 492                 /*
 493                  * If this triggers then we have a calculation bug
 494                  * somewhere. :/
 495                  */
 496                 WARN_ON((desc - host->adma_desc) > (128 * 2 + 1) * 4);
 497         }
 498
 499         /*
 500          * Add a terminating entry.
 501          */
 502
 503         /* nop, end, valid */
 504         sdhci_set_adma_desc(desc, 0, 0, 0x3);
 505
 506         /*
 507          * Resync align buffer as we might have changed it.
 508          */
 509         if (data->flags & MMC_DATA_WRITE) {
 510                 dma_sync_single_for_device(mmc_dev(host->mmc),
 511                         host->align_addr, 128 * 4, direction);
 512         }
 513
 514         host->adma_addr = dma_map_single(mmc_dev(host->mmc),
 515                 host->adma_desc, (128 * 2 + 1) * 4, DMA_TO_DEVICE);
 516         if (dma_mapping_error(mmc_dev(host->mmc), host->adma_addr))
 517                 goto unmap_entries;
 518         BUG_ON(host->adma_addr & 0x3);
 519
 520         return 0;
 521
 522 unmap_entries:
 523         dma_unmap_sg(mmc_dev(host->mmc), data->sg,
 524                 data->sg_len, direction);
 525 unmap_align:
 526         dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
 527                 128 * 4, direction);
 528 fail:
 529         return -EINVAL;
 530 }
 531
 532 static void sdhci_adma_table_post(struct sdhci_host *host,
 533         struct mmc_data *data)
 534 {
 535         int direction;
 536
 537         struct scatterlist *sg;
 538         int i, size;
 539         u8 *align;
 540         char *buffer;
 541         unsigned long flags;
 542
 543         if (data->flags & MMC_DATA_READ)
 544                 direction = DMA_FROM_DEVICE;
 545         else
 546                 direction = DMA_TO_DEVICE;
 547
 548         dma_unmap_single(mmc_dev(host->mmc), host->adma_addr,
 549                 (128 * 2 + 1) * 4, DMA_TO_DEVICE);
 550
 551         dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
 552                 128 * 4, direction);
 553
 554         if (data->flags & MMC_DATA_READ) {
 555                 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
 556                         data->sg_len, direction);
 557
 558                 align = host->align_buffer;
 559
 560                 for_each_sg(data->sg, sg, host->sg_count, i) {
 561                         if (sg_dma_address(sg) & 0x3) {
 562                                 size = 4 - (sg_dma_address(sg) & 0x3);
 563
 564                                 buffer = sdhci_kmap_atomic(sg, &flags);
 565                                 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
 566                                 memcpy(buffer, align, size);
 567                                 sdhci_kunmap_atomic(buffer, &flags);
 568
 569                                 align += 4;
 570                         }
 571                 }
 572         }
 573
 574         dma_unmap_sg(mmc_dev(host->mmc), data->sg,
 575                 data->sg_len, direction);
 576 }
 577
 578 static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_data *data)
 579 {
 580         u8 count;
 581         unsigned target_timeout, current_timeout;
 582
 583         /*
 584          * If the host controller provides us with an incorrect timeout
 585          * value, just skip the check and use 0xE.  The hardware may take
 586          * longer to time out, but that's much better than having a too-short
 587          * timeout value.
 588          */
 589         if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
 590                 return 0xE;
 591
 592         /* timeout in us */
 593         target_timeout = data->timeout_ns / 1000 +
 594                 data->timeout_clks / host->clock;
 595
 596         if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)
 597                 host->timeout_clk = host->clock / 1000;
 598
 599         /*
 600          * Figure out needed cycles.
 601          * We do this in steps in order to fit inside a 32 bit int.
 602          * The first step is the minimum timeout, which will have a
 603          * minimum resolution of 6 bits:
 604          * (1) 2^13*1000 > 2^22,
 605          * (2) host->timeout_clk < 2^16
 606          *     =>
 607          *     (1) / (2) > 2^6
 608          */
 609         count = 0;
 610         current_timeout = (1 << 13) * 1000 / host->timeout_clk;
 611         while (current_timeout < target_timeout) {
 612                 count++;
 613                 current_timeout <<= 1;
 614                 if (count >= 0xF)
 615                         break;
 616         }
 617
 618         if (count >= 0xF) {
 619                 printk(KERN_WARNING "%s: Too large timeout requested!\n",
 620                         mmc_hostname(host->mmc));
 621                 count = 0xE;
 622         }
 623
 624         return count;
 625 }
 626
 627 static void sdhci_set_transfer_irqs(struct sdhci_host *host)
 628 {
 629         u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
 630         u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
 631
 632         if (host->flags & SDHCI_REQ_USE_DMA)
 633                 sdhci_clear_set_irqs(host, pio_irqs, dma_irqs);
 634         else
 635                 sdhci_clear_set_irqs(host, dma_irqs, pio_irqs);
 636 }
 637
 638 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_data *data)
 639 {
 640         u8 count;
 641         u8 ctrl;
 642         int ret;
 643
 644         WARN_ON(host->data);
 645
 646         if (data == NULL)
 647                 return;
 648
 649         /* Sanity checks */
 650         BUG_ON(data->blksz * data->blocks > 524288);
 651         BUG_ON(data->blksz > host->mmc->max_blk_size);
 652         BUG_ON(data->blocks > 65535);
 653
 654         host->data = data;
 655         host->data_early = 0;
 656
 657         count = sdhci_calc_timeout(host, data);
 658         sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
 659
 660         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
 661                 host->flags |= SDHCI_REQ_USE_DMA;
 662
 663         /*
 664          * FIXME: This doesn't account for merging when mapping the
 665          * scatterlist.
 666          */
 667         if (host->flags & SDHCI_REQ_USE_DMA) {
 668                 int broken, i;
 669                 struct scatterlist *sg;
 670
 671                 broken = 0;
 672                 if (host->flags & SDHCI_USE_ADMA) {
 673                         if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
 674                                 broken = 1;
 675                 } else {
 676                         if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
 677                                 broken = 1;
 678                 }
 679
 680                 if (unlikely(broken)) {
 681                         for_each_sg(data->sg, sg, data->sg_len, i) {
 682                                 if (sg->length & 0x3) {
 683                                         DBG("Reverting to PIO because of "
 684                                                 "transfer size (%d)\n",
 685                                                 sg->length);
 686                                         host->flags &= ~SDHCI_REQ_USE_DMA;
 687                                         break;
 688                                 }
 689                         }
 690                 }
 691         }
 692
 693         /*
 694          * The assumption here being that alignment is the same after
 695          * translation to device address space.
 696          */
 697         if (host->flags & SDHCI_REQ_USE_DMA) {
 698                 int broken, i;
 699                 struct scatterlist *sg;
 700
 701                 broken = 0;
 702                 if (host->flags & SDHCI_USE_ADMA) {
 703                         /*
 704                          * As we use 3 byte chunks to work around
 705                          * alignment problems, we need to check this
 706                          * quirk.
 707                          */
 708                         if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
 709                                 broken = 1;
 710                 } else {
 711                         if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
 712                                 broken = 1;
 713                 }
 714
 715                 if (unlikely(broken)) {
 716                         for_each_sg(data->sg, sg, data->sg_len, i) {
 717                                 if (sg->offset & 0x3) {
 718                                         DBG("Reverting to PIO because of "
 719                                                 "bad alignment\n");
 720                                         host->flags &= ~SDHCI_REQ_USE_DMA;
 721                                         break;
 722                                 }
 723                         }
 724                 }
 725         }
 726
 727         if (host->flags & SDHCI_REQ_USE_DMA) {
 728                 if (host->flags & SDHCI_USE_ADMA) {
 729                         ret = sdhci_adma_table_pre(host, data);
 730                         if (ret) {
 731                                 /*
 732                                  * This only happens when someone fed
 733                                  * us an invalid request.
 734                                  */
 735                                 WARN_ON(1);
 736                                 host->flags &= ~SDHCI_REQ_USE_DMA;
 737                         } else {
 738                                 sdhci_writel(host, host->adma_addr,
 739                                         SDHCI_ADMA_ADDRESS);
 740                         }
 741                 } else {
 742                         int sg_cnt;
 743
 744                         sg_cnt = dma_map_sg(mmc_dev(host->mmc),
 745                                         data->sg, data->sg_len,
 746                                         (data->flags & MMC_DATA_READ) ?
 747                                                 DMA_FROM_DEVICE :
 748                                                 DMA_TO_DEVICE);
 749                         if (sg_cnt == 0) {
 750                                 /*
 751                                  * This only happens when someone fed
 752                                  * us an invalid request.
 753                                  */
 754                                 WARN_ON(1);
 755                                 host->flags &= ~SDHCI_REQ_USE_DMA;
 756                         } else {
 757                                 WARN_ON(sg_cnt != 1);
 758                                 sdhci_writel(host, sg_dma_address(data->sg),
 759                                         SDHCI_DMA_ADDRESS);
 760                         }
 761                 }
 762         }
 763
 764         /*
 765          * Always adjust the DMA selection as some controllers
 766          * (e.g. JMicron) can't do PIO properly when the selection
 767          * is ADMA.
 768          */
 769         if (host->version >= SDHCI_SPEC_200) {
 770                 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 771                 ctrl &= ~SDHCI_CTRL_DMA_MASK;
 772                 if ((host->flags & SDHCI_REQ_USE_DMA) &&
 773                         (host->flags & SDHCI_USE_ADMA))
 774                         ctrl |= SDHCI_CTRL_ADMA32;
 775                 else
 776                         ctrl |= SDHCI_CTRL_SDMA;
 777                 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 778         }
 779
 780         if (!(host->flags & SDHCI_REQ_USE_DMA)) {
 781                 int flags;
 782
 783                 flags = SG_MITER_ATOMIC;
 784                 if (host->data->flags & MMC_DATA_READ)
 785                         flags |= SG_MITER_TO_SG;
 786                 else
 787                         flags |= SG_MITER_FROM_SG;
 788                 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
 789                 host->blocks = data->blocks;
 790         }
 791
 792         sdhci_set_transfer_irqs(host);
 793
 794         /* We do not handle DMA boundaries, so set it to max (512 KiB) */
 795         sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, data->blksz), SDHCI_BLOCK_SIZE);
 796         sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
 797 }
 798
 799 static void sdhci_set_transfer_mode(struct sdhci_host *host,
 800         struct mmc_data *data)
 801 {
 802         u16 mode;
 803
 804         if (data == NULL)
 805                 return;
 806
 807         WARN_ON(!host->data);
 808
 809         mode = SDHCI_TRNS_BLK_CNT_EN;
 810         if (data->blocks > 1)
 811                 mode |= SDHCI_TRNS_MULTI;
 812         if (data->flags & MMC_DATA_READ)
 813                 mode |= SDHCI_TRNS_READ;
 814         if (host->flags & SDHCI_REQ_USE_DMA)
 815                 mode |= SDHCI_TRNS_DMA;
 816
 817         sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
 818 }
 819
 820 static void sdhci_finish_data(struct sdhci_host *host)
 821 {
 822         struct mmc_data *data;
 823
 824         BUG_ON(!host->data);
 825
 826         data = host->data;
 827         host->data = NULL;
 828
 829         if (host->flags & SDHCI_REQ_USE_DMA) {
 830                 if (host->flags & SDHCI_USE_ADMA)
 831                         sdhci_adma_table_post(host, data);
 832                 else {
 833                         dma_unmap_sg(mmc_dev(host->mmc), data->sg,
 834                                 data->sg_len, (data->flags & MMC_DATA_READ) ?
 835                                         DMA_FROM_DEVICE : DMA_TO_DEVICE);
 836                 }
 837         }
 838
 839         /*
 840          * The specification states that the block count register must
 841          * be updated, but it does not specify at what point in the
 842          * data flow. That makes the register entirely useless to read
 843          * back so we have to assume that nothing made it to the card
 844          * in the event of an error.
 845          */
 846         if (data->error)
 847                 data->bytes_xfered = 0;
 848         else
 849                 data->bytes_xfered = data->blksz * data->blocks;
 850
 851         if (data->stop) {
 852                 /*
 853                  * The controller needs a reset of internal state machines
 854                  * upon error conditions.
 855                  */
 856                 if (data->error) {
 857                         sdhci_reset(host, SDHCI_RESET_CMD);
 858                         sdhci_reset(host, SDHCI_RESET_DATA);
 859                 }
 860
 861                 sdhci_send_command(host, data->stop);
 862         } else
 863                 tasklet_schedule(&host->finish_tasklet);
 864 }
 865
 866 static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
 867 {
 868         int flags;
 869         u32 mask;
 870         unsigned long timeout;
 871
 872         WARN_ON(host->cmd);
 873
 874         /* Wait max 10 ms */
 875         timeout = 10;
 876
 877         mask = SDHCI_CMD_INHIBIT;
 878         if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
 879                 mask |= SDHCI_DATA_INHIBIT;
 880
 881         /* We shouldn't wait for data inihibit for stop commands, even
 882            though they might use busy signaling */
 883         if (host->mrq->data && (cmd == host->mrq->data->stop))
 884                 mask &= ~SDHCI_DATA_INHIBIT;
 885
 886         while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
 887                 if (timeout == 0) {
 888                         printk(KERN_ERR "%s: Controller never released "
 889                                 "inhibit bit(s).\n", mmc_hostname(host->mmc));
 890                         sdhci_dumpregs(host);
 891                         cmd->error = -EIO;
 892                         tasklet_schedule(&host->finish_tasklet);
 893                         return;
 894                 }
 895                 timeout--;
 896                 mdelay(1);
 897         }
 898
 899         mod_timer(&host->timer, jiffies + 10 * HZ);
 900
 901         host->cmd = cmd;
 902
 903         sdhci_prepare_data(host, cmd->data);
 904
 905         sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
 906
 907         sdhci_set_transfer_mode(host, cmd->data);
 908
 909         if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
 910                 printk(KERN_ERR "%s: Unsupported response type!\n",
 911                         mmc_hostname(host->mmc));
 912                 cmd->error = -EINVAL;
 913                 tasklet_schedule(&host->finish_tasklet);
 914                 return;
 915         }
 916
 917         if (!(cmd->flags & MMC_RSP_PRESENT))
 918                 flags = SDHCI_CMD_RESP_NONE;
 919         else if (cmd->flags & MMC_RSP_136)
 920                 flags = SDHCI_CMD_RESP_LONG;
 921         else if (cmd->flags & MMC_RSP_BUSY)
 922                 flags = SDHCI_CMD_RESP_SHORT_BUSY;
 923         else
 924                 flags = SDHCI_CMD_RESP_SHORT;
 925
 926         if (cmd->flags & MMC_RSP_CRC)
 927                 flags |= SDHCI_CMD_CRC;
 928         if (cmd->flags & MMC_RSP_OPCODE)
 929                 flags |= SDHCI_CMD_INDEX;
 930         if (cmd->data)
 931                 flags |= SDHCI_CMD_DATA;
 932
 933         sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
 934 }
 935
 936 static void sdhci_finish_command(struct sdhci_host *host)
 937 {
 938         int i;
 939
 940         BUG_ON(host->cmd == NULL);
 941
 942         if (host->cmd->flags & MMC_RSP_PRESENT) {
 943                 if (host->cmd->flags & MMC_RSP_136) {
 944                         /* CRC is stripped so we need to do some shifting. */
 945                         for (i = 0;i < 4;i++) {
 946                                 host->cmd->resp[i] = sdhci_readl(host,
 947                                         SDHCI_RESPONSE + (3-i)*4) << 8;
 948                                 if (i != 3)
 949                                         host->cmd->resp[i] |=
 950                                                 sdhci_readb(host,
 951                                                 SDHCI_RESPONSE + (3-i)*4-1);
 952                         }
 953                 } else {
 954                         host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
 955                 }
 956         }
 957
 958         host->cmd->error = 0;
 959
 960         if (host->data && host->data_early)
 961                 sdhci_finish_data(host);
 962
 963         if (!host->cmd->data)
 964                 tasklet_schedule(&host->finish_tasklet);
 965
 966         host->cmd = NULL;
 967 }
 968
 969 static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
 970 {
 971         int div;
 972         u16 clk;
 973         unsigned long timeout;
 974
 975         if (clock == host->clock)
 976                 return;
 977
 978         if (host->ops->set_clock) {
 979                 host->ops->set_clock(host, clock);
 980                 if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK)
 981                         return;
 982         }
 983
 984         sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
 985
 986         if (clock == 0)
 987                 goto out;
 988
 989         for (div = 1;div < 256;div *= 2) {
 990                 if ((host->max_clk / div) <= clock)
 991                         break;
 992         }
 993         div >>= 1;
 994
 995         clk = div << SDHCI_DIVIDER_SHIFT;
 996         clk |= SDHCI_CLOCK_INT_EN;
 997         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
 998
 999         /* Wait max 20 ms */
1000         timeout = 20;
1001         while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
1002                 & SDHCI_CLOCK_INT_STABLE)) {
1003                 if (timeout == 0) {
1004                         printk(KERN_ERR "%s: Internal clock never "
1005                                 "stabilised.\n", mmc_hostname(host->mmc));
1006                         sdhci_dumpregs(host);
1007                         return;
1008                 }
1009                 timeout--;
1010                 mdelay(1);
1011         }
1012
1013         clk |= SDHCI_CLOCK_CARD_EN;
1014         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1015
1016 out:
1017         host->clock = clock;
1018 }
1019
1020 static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
1021 {
1022         u8 pwr;
1023
1024         if (power == (unsigned short)-1)
1025                 pwr = 0;
1026         else {
1027                 switch (1 << power) {
1028                 case MMC_VDD_165_195:
1029                         pwr = SDHCI_POWER_180;
1030                         break;
1031                 case MMC_VDD_29_30:
1032                 case MMC_VDD_30_31:
1033                         pwr = SDHCI_POWER_300;
1034                         break;
1035                 case MMC_VDD_32_33:
1036                 case MMC_VDD_33_34:
1037                         pwr = SDHCI_POWER_330;
1038                         break;
1039                 default:
1040                         BUG();
1041                 }
1042         }
1043
1044         if (host->pwr == pwr)
1045                 return;
1046
1047         host->pwr = pwr;
1048
1049         if (pwr == 0) {
1050                 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1051                 return;
1052         }
1053
1054         /*
1055          * Spec says that we should clear the power reg before setting
1056          * a new value. Some controllers don't seem to like this though.
1057          */
1058         if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1059                 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1060
1061         /*
1062          * At least the Marvell CaFe chip gets confused if we set the voltage
1063          * and set turn on power at the same time, so set the voltage first.
1064          */
1065         if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1066                 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1067
1068         pwr |= SDHCI_POWER_ON;
1069
1070         sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1071
1072         /*
1073          * Some controllers need an extra 10ms delay of 10ms before they
1074          * can apply clock after applying power
1075          */
1076         if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1077                 mdelay(10);
1078 }
1079
1080 /*****************************************************************************\
1081  *                                                                           *
1082  * MMC callbacks                                                             *
1083  *                                                                           *
1084 \*****************************************************************************/
1085
1086 static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1087 {
1088         struct sdhci_host *host;
1089         bool present;
1090         unsigned long flags;
1091
1092         host = mmc_priv(mmc);
1093
1094         spin_lock_irqsave(&host->lock, flags);
1095
1096         WARN_ON(host->mrq != NULL);
1097
1098 #ifndef SDHCI_USE_LEDS_CLASS
1099         sdhci_activate_led(host);
1100 #endif
1101
1102         host->mrq = mrq;
1103
1104         /* If polling, assume that the card is always present. */
1105         if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1106                 present = true;
1107         else
1108                 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
1109                                 SDHCI_CARD_PRESENT;
1110
1111         if (!present || host->flags & SDHCI_DEVICE_DEAD) {
1112                 host->mrq->cmd->error = -ENOMEDIUM;
1113                 tasklet_schedule(&host->finish_tasklet);
1114         } else
1115                 sdhci_send_command(host, mrq->cmd);
1116
1117         mmiowb();
1118         spin_unlock_irqrestore(&host->lock, flags);
1119 }
1120
1121 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1122 {
1123         struct sdhci_host *host;
1124         unsigned long flags;
1125         u8 ctrl;
1126
1127         host = mmc_priv(mmc);
1128
1129         spin_lock_irqsave(&host->lock, flags);
1130
1131         if (host->flags & SDHCI_DEVICE_DEAD)
1132                 goto out;
1133
1134         /*
1135          * Reset the chip on each power off.
1136          * Should clear out any weird states.
1137          */
1138         if (ios->power_mode == MMC_POWER_OFF) {
1139                 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
1140                 sdhci_reinit(host);
1141         }
1142
1143         sdhci_set_clock(host, ios->clock);
1144
1145         if (ios->power_mode == MMC_POWER_OFF)
1146                 sdhci_set_power(host, -1);
1147         else
1148                 sdhci_set_power(host, ios->vdd);
1149
1150         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1151
1152         if (ios->bus_width == MMC_BUS_WIDTH_4)
1153                 ctrl |= SDHCI_CTRL_4BITBUS;
1154         else
1155                 ctrl &= ~SDHCI_CTRL_4BITBUS;
1156
1157         if (ios->timing == MMC_TIMING_SD_HS)
1158                 ctrl |= SDHCI_CTRL_HISPD;
1159         else
1160                 ctrl &= ~SDHCI_CTRL_HISPD;
1161
1162         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1163
1164         /*
1165          * Some (ENE) controllers go apeshit on some ios operation,
1166          * signalling timeout and CRC errors even on CMD0. Resetting
1167          * it on each ios seems to solve the problem.
1168          */
1169         if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
1170                 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1171
1172 out:
1173         mmiowb();
1174         spin_unlock_irqrestore(&host->lock, flags);
1175 }
1176
1177 static int sdhci_get_ro(struct mmc_host *mmc)
1178 {
1179         struct sdhci_host *host;
1180         unsigned long flags;
1181         int present;
1182
1183         host = mmc_priv(mmc);
1184
1185         spin_lock_irqsave(&host->lock, flags);
1186
1187         if (host->flags & SDHCI_DEVICE_DEAD)
1188                 present = 0;
1189         else
1190                 present = sdhci_readl(host, SDHCI_PRESENT_STATE);
1191
1192         spin_unlock_irqrestore(&host->lock, flags);
1193
1194         if (host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT)
1195                 return !!(present & SDHCI_WRITE_PROTECT);
1196         return !(present & SDHCI_WRITE_PROTECT);
1197 }
1198
1199 static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1200 {
1201         struct sdhci_host *host;
1202         unsigned long flags;
1203
1204         host = mmc_priv(mmc);
1205
1206         spin_lock_irqsave(&host->lock, flags);
1207
1208         if (host->flags & SDHCI_DEVICE_DEAD)
1209                 goto out;
1210
1211         if (enable)
1212                 sdhci_unmask_irqs(host, SDHCI_INT_CARD_INT);
1213         else
1214                 sdhci_mask_irqs(host, SDHCI_INT_CARD_INT);
1215 out:
1216         mmiowb();
1217
1218         spin_unlock_irqrestore(&host->lock, flags);
1219 }
1220
1221 static const struct mmc_host_ops sdhci_ops = {
1222         .request        = sdhci_request,
1223         .set_ios        = sdhci_set_ios,
1224         .get_ro         = sdhci_get_ro,
1225         .enable_sdio_irq = sdhci_enable_sdio_irq,
1226 };
1227
1228 /*****************************************************************************\
1229  *                                                                           *
1230  * Tasklets                                                                  *
1231  *                                                                           *
1232 \*****************************************************************************/
1233
1234 static void sdhci_tasklet_card(unsigned long param)
1235 {
1236         struct sdhci_host *host;
1237         unsigned long flags;
1238
1239         host = (struct sdhci_host*)param;
1240
1241         spin_lock_irqsave(&host->lock, flags);
1242
1243         if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
1244                 if (host->mrq) {
1245                         printk(KERN_ERR "%s: Card removed during transfer!\n",
1246                                 mmc_hostname(host->mmc));
1247                         printk(KERN_ERR "%s: Resetting controller.\n",
1248                                 mmc_hostname(host->mmc));
1249
1250                         sdhci_reset(host, SDHCI_RESET_CMD);
1251                         sdhci_reset(host, SDHCI_RESET_DATA);
1252
1253                         host->mrq->cmd->error = -ENOMEDIUM;
1254                         tasklet_schedule(&host->finish_tasklet);
1255                 }
1256         }
1257
1258         spin_unlock_irqrestore(&host->lock, flags);
1259
1260         mmc_detect_change(host->mmc, msecs_to_jiffies(200));
1261 }
1262
1263 static void sdhci_tasklet_finish(unsigned long param)
1264 {
1265         struct sdhci_host *host;
1266         unsigned long flags;
1267         struct mmc_request *mrq;
1268
1269         host = (struct sdhci_host*)param;
1270
1271         spin_lock_irqsave(&host->lock, flags);
1272
1273         del_timer(&host->timer);
1274
1275         mrq = host->mrq;
1276
1277         /*
1278          * The controller needs a reset of internal state machines
1279          * upon error conditions.
1280          */
1281         if (!(host->flags & SDHCI_DEVICE_DEAD) &&
1282                 (mrq->cmd->error ||
1283                  (mrq->data && (mrq->data->error ||
1284                   (mrq->data->stop && mrq->data->stop->error))) ||
1285                    (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
1286
1287                 /* Some controllers need this kick or reset won't work here */
1288                 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) {
1289                         unsigned int clock;
1290
1291                         /* This is to force an update */
1292                         clock = host->clock;
1293                         host->clock = 0;
1294                         sdhci_set_clock(host, clock);
1295                 }
1296
1297                 /* Spec says we should do both at the same time, but Ricoh
1298                    controllers do not like that. */
1299                 sdhci_reset(host, SDHCI_RESET_CMD);
1300                 sdhci_reset(host, SDHCI_RESET_DATA);
1301         }
1302
1303         host->mrq = NULL;
1304         host->cmd = NULL;
1305         host->data = NULL;
1306
1307 #ifndef SDHCI_USE_LEDS_CLASS
1308         sdhci_deactivate_led(host);
1309 #endif
1310
1311         mmiowb();
1312         spin_unlock_irqrestore(&host->lock, flags);
1313
1314         mmc_request_done(host->mmc, mrq);
1315 }
1316
1317 static void sdhci_timeout_timer(unsigned long data)
1318 {
1319         struct sdhci_host *host;
1320         unsigned long flags;
1321
1322         host = (struct sdhci_host*)data;
1323
1324         spin_lock_irqsave(&host->lock, flags);
1325
1326         if (host->mrq) {
1327                 printk(KERN_ERR "%s: Timeout waiting for hardware "
1328                         "interrupt.\n", mmc_hostname(host->mmc));
1329                 sdhci_dumpregs(host);
1330
1331                 if (host->data) {
1332                         host->data->error = -ETIMEDOUT;
1333                         sdhci_finish_data(host);
1334                 } else {
1335                         if (host->cmd)
1336                                 host->cmd->error = -ETIMEDOUT;
1337                         else
1338                                 host->mrq->cmd->error = -ETIMEDOUT;
1339
1340                         tasklet_schedule(&host->finish_tasklet);
1341                 }
1342         }
1343
1344         mmiowb();
1345         spin_unlock_irqrestore(&host->lock, flags);
1346 }
1347
1348 /*****************************************************************************\
1349  *                                                                           *
1350  * Interrupt handling                                                        *
1351  *                                                                           *
1352 \*****************************************************************************/
1353
1354 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
1355 {
1356         BUG_ON(intmask == 0);
1357
1358         if (!host->cmd) {
1359                 printk(KERN_ERR "%s: Got command interrupt 0x%08x even "
1360                         "though no command operation was in progress.\n",
1361                         mmc_hostname(host->mmc), (unsigned)intmask);
1362                 sdhci_dumpregs(host);
1363                 return;
1364         }
1365
1366         if (intmask & SDHCI_INT_TIMEOUT)
1367                 host->cmd->error = -ETIMEDOUT;
1368         else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
1369                         SDHCI_INT_INDEX))
1370                 host->cmd->error = -EILSEQ;
1371
1372         if (host->cmd->error) {
1373                 tasklet_schedule(&host->finish_tasklet);
1374                 return;
1375         }
1376
1377         /*
1378          * The host can send and interrupt when the busy state has
1379          * ended, allowing us to wait without wasting CPU cycles.
1380          * Unfortunately this is overloaded on the "data complete"
1381          * interrupt, so we need to take some care when handling
1382          * it.
1383          *
1384          * Note: The 1.0 specification is a bit ambiguous about this
1385          *       feature so there might be some problems with older
1386          *       controllers.
1387          */
1388         if (host->cmd->flags & MMC_RSP_BUSY) {
1389                 if (host->cmd->data)
1390                         DBG("Cannot wait for busy signal when also "
1391                                 "doing a data transfer");
1392                 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ))
1393                         return;
1394
1395                 /* The controller does not support the end-of-busy IRQ,
1396                  * fall through and take the SDHCI_INT_RESPONSE */
1397         }
1398
1399         if (intmask & SDHCI_INT_RESPONSE)
1400                 sdhci_finish_command(host);
1401 }
1402
1403 #ifdef DEBUG
1404 static void sdhci_show_adma_error(struct sdhci_host *host)
1405 {
1406         const char *name = mmc_hostname(host->mmc);
1407         u8 *desc = host->adma_desc;
1408         __le32 *dma;
1409         __le16 *len;
1410         u8 attr;
1411
1412         sdhci_dumpregs(host);
1413
1414         while (true) {
1415                 dma = (__le32 *)(desc + 4);
1416                 len = (__le16 *)(desc + 2);
1417                 attr = *desc;
1418
1419                 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
1420                     name, desc, le32_to_cpu(*dma), le16_to_cpu(*len), attr);
1421
1422                 desc += 8;
1423
1424                 if (attr & 2)
1425                         break;
1426         }
1427 }
1428 #else
1429 static void sdhci_show_adma_error(struct sdhci_host *host) { }
1430 #endif
1431
1432 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
1433 {
1434         BUG_ON(intmask == 0);
1435
1436         if (!host->data) {
1437                 /*
1438                  * The "data complete" interrupt is also used to
1439                  * indicate that a busy state has ended. See comment
1440                  * above in sdhci_cmd_irq().
1441                  */
1442                 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
1443                         if (intmask & SDHCI_INT_DATA_END) {
1444                                 sdhci_finish_command(host);
1445                                 return;
1446                         }
1447                 }
1448
1449                 printk(KERN_ERR "%s: Got data interrupt 0x%08x even "
1450                         "though no data operation was in progress.\n",
1451                         mmc_hostname(host->mmc), (unsigned)intmask);
1452                 sdhci_dumpregs(host);
1453
1454                 return;
1455         }
1456
1457         if (intmask & SDHCI_INT_DATA_TIMEOUT)
1458                 host->data->error = -ETIMEDOUT;
1459         else if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT))
1460                 host->data->error = -EILSEQ;
1461         else if (intmask & SDHCI_INT_ADMA_ERROR) {
1462                 printk(KERN_ERR "%s: ADMA error\n", mmc_hostname(host->mmc));
1463                 sdhci_show_adma_error(host);
1464                 host->data->error = -EIO;
1465         }
1466
1467         if (host->data->error)
1468                 sdhci_finish_data(host);
1469         else {
1470                 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
1471                         sdhci_transfer_pio(host);
1472
1473                 /*
1474                  * We currently don't do anything fancy with DMA
1475                  * boundaries, but as we can't disable the feature
1476                  * we need to at least restart the transfer.
1477                  */
1478                 if (intmask & SDHCI_INT_DMA_END)
1479                         sdhci_writel(host, sdhci_readl(host, SDHCI_DMA_ADDRESS),
1480                                 SDHCI_DMA_ADDRESS);
1481
1482                 if (intmask & SDHCI_INT_DATA_END) {
1483                         if (host->cmd) {
1484                                 /*
1485                                  * Data managed to finish before the
1486                                  * command completed. Make sure we do
1487                                  * things in the proper order.
1488                                  */
1489                                 host->data_early = 1;
1490                         } else {
1491                                 sdhci_finish_data(host);
1492                         }
1493                 }
1494         }
1495 }
1496
1497 static irqreturn_t sdhci_irq(int irq, void *dev_id)
1498 {
1499         irqreturn_t result;
1500         struct sdhci_host* host = dev_id;
1501         u32 intmask;
1502         int cardint = 0;
1503
1504         spin_lock(&host->lock);
1505
1506         intmask = sdhci_readl(host, SDHCI_INT_STATUS);
1507
1508         if (!intmask || intmask == 0xffffffff) {
1509                 result = IRQ_NONE;
1510                 goto out;
1511         }
1512
1513         DBG("*** %s got interrupt: 0x%08x\n",
1514                 mmc_hostname(host->mmc), intmask);
1515
1516         if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
1517                 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
1518                         SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
1519                 tasklet_schedule(&host->card_tasklet);
1520         }
1521
1522         intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
1523
1524         if (intmask & SDHCI_INT_CMD_MASK) {
1525                 sdhci_writel(host, intmask & SDHCI_INT_CMD_MASK,
1526                         SDHCI_INT_STATUS);
1527                 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
1528         }
1529
1530         if (intmask & SDHCI_INT_DATA_MASK) {
1531                 sdhci_writel(host, intmask & SDHCI_INT_DATA_MASK,
1532                         SDHCI_INT_STATUS);
1533                 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
1534         }
1535
1536         intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
1537
1538         intmask &= ~SDHCI_INT_ERROR;
1539
1540         if (intmask & SDHCI_INT_BUS_POWER) {
1541                 printk(KERN_ERR "%s: Card is consuming too much power!\n",
1542                         mmc_hostname(host->mmc));
1543                 sdhci_writel(host, SDHCI_INT_BUS_POWER, SDHCI_INT_STATUS);
1544         }
1545
1546         intmask &= ~SDHCI_INT_BUS_POWER;
1547
1548         if (intmask & SDHCI_INT_CARD_INT)
1549                 cardint = 1;
1550
1551         intmask &= ~SDHCI_INT_CARD_INT;
1552
1553         if (intmask) {
1554                 printk(KERN_ERR "%s: Unexpected interrupt 0x%08x.\n",
1555                         mmc_hostname(host->mmc), intmask);
1556                 sdhci_dumpregs(host);
1557
1558                 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
1559         }
1560
1561         result = IRQ_HANDLED;
1562
1563         mmiowb();
1564 out:
1565         spin_unlock(&host->lock);
1566
1567         /*
1568          * We have to delay this as it calls back into the driver.
1569          */
1570         if (cardint)
1571                 mmc_signal_sdio_irq(host->mmc);
1572
1573         return result;
1574 }
1575
1576 /*****************************************************************************\
1577  *                                                                           *
1578  * Suspend/resume                                                            *
1579  *                                                                           *
1580 \*****************************************************************************/
1581
1582 #ifdef CONFIG_PM
1583
1584 int sdhci_suspend_host(struct sdhci_host *host, pm_message_t state)
1585 {
1586         int ret;
1587
1588         sdhci_disable_card_detection(host);
1589
1590         ret = mmc_suspend_host(host->mmc, state);
1591         if (ret)
1592                 return ret;
1593
1594         free_irq(host->irq, host);
1595
1596         return 0;
1597 }
1598
1599 EXPORT_SYMBOL_GPL(sdhci_suspend_host);
1600
1601 int sdhci_resume_host(struct sdhci_host *host)
1602 {
1603         int ret;
1604
1605         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
1606                 if (host->ops->enable_dma)
1607                         host->ops->enable_dma(host);
1608         }
1609
1610         ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
1611                           mmc_hostname(host->mmc), host);
1612         if (ret)
1613                 return ret;
1614
1615         sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
1616         mmiowb();
1617
1618         ret = mmc_resume_host(host->mmc);
1619         sdhci_enable_card_detection(host);
1620
1621         return ret;
1622 }
1623
1624 EXPORT_SYMBOL_GPL(sdhci_resume_host);
1625
1626 #endif /* CONFIG_PM */
1627
1628 /*****************************************************************************\
1629  *                                                                           *
1630  * Device allocation/registration                                            *
1631  *                                                                           *
1632 \*****************************************************************************/
1633
1634 struct sdhci_host *sdhci_alloc_host(struct device *dev,
1635         size_t priv_size)
1636 {
1637         struct mmc_host *mmc;
1638         struct sdhci_host *host;
1639
1640         WARN_ON(dev == NULL);
1641
1642         mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
1643         if (!mmc)
1644                 return ERR_PTR(-ENOMEM);
1645
1646         host = mmc_priv(mmc);
1647         host->mmc = mmc;
1648
1649         return host;
1650 }
1651
1652 EXPORT_SYMBOL_GPL(sdhci_alloc_host);
1653
1654 int sdhci_add_host(struct sdhci_host *host)
1655 {
1656         struct mmc_host *mmc;
1657         unsigned int caps;
1658         int ret;
1659
1660         WARN_ON(host == NULL);
1661         if (host == NULL)
1662                 return -EINVAL;
1663
1664         mmc = host->mmc;
1665
1666         if (debug_quirks)
1667                 host->quirks = debug_quirks;
1668
1669         sdhci_reset(host, SDHCI_RESET_ALL);
1670
1671         host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
1672         host->version = (host->version & SDHCI_SPEC_VER_MASK)
1673                                 >> SDHCI_SPEC_VER_SHIFT;
1674         if (host->version > SDHCI_SPEC_200) {
1675                 printk(KERN_ERR "%s: Unknown controller version (%d). "
1676                         "You may experience problems.\n", mmc_hostname(mmc),
1677                         host->version);
1678         }
1679
1680         caps = sdhci_readl(host, SDHCI_CAPABILITIES);
1681
1682         if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
1683                 host->flags |= SDHCI_USE_SDMA;
1684         else if (!(caps & SDHCI_CAN_DO_SDMA))
1685                 DBG("Controller doesn't have SDMA capability\n");
1686         else
1687                 host->flags |= SDHCI_USE_SDMA;
1688
1689         if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
1690                 (host->flags & SDHCI_USE_SDMA)) {
1691                 DBG("Disabling DMA as it is marked broken\n");
1692                 host->flags &= ~SDHCI_USE_SDMA;
1693         }
1694
1695         if ((host->version >= SDHCI_SPEC_200) && (caps & SDHCI_CAN_DO_ADMA2))
1696                 host->flags |= SDHCI_USE_ADMA;
1697
1698         if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
1699                 (host->flags & SDHCI_USE_ADMA)) {
1700                 DBG("Disabling ADMA as it is marked broken\n");
1701                 host->flags &= ~SDHCI_USE_ADMA;
1702         }
1703
1704         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
1705                 if (host->ops->enable_dma) {
1706                         if (host->ops->enable_dma(host)) {
1707                                 printk(KERN_WARNING "%s: No suitable DMA "
1708                                         "available. Falling back to PIO.\n",
1709                                         mmc_hostname(mmc));
1710                                 host->flags &=
1711                                         ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
1712                         }
1713                 }
1714         }
1715
1716         if (host->flags & SDHCI_USE_ADMA) {
1717                 /*
1718                  * We need to allocate descriptors for all sg entries
1719                  * (128) and potentially one alignment transfer for
1720                  * each of those entries.
1721                  */
1722                 host->adma_desc = kmalloc((128 * 2 + 1) * 4, GFP_KERNEL);
1723                 host->align_buffer = kmalloc(128 * 4, GFP_KERNEL);
1724                 if (!host->adma_desc || !host->align_buffer) {
1725                         kfree(host->adma_desc);
1726                         kfree(host->align_buffer);
1727                         printk(KERN_WARNING "%s: Unable to allocate ADMA "
1728                                 "buffers. Falling back to standard DMA.\n",
1729                                 mmc_hostname(mmc));
1730                         host->flags &= ~SDHCI_USE_ADMA;
1731                 }
1732         }
1733
1734         /*
1735          * If we use DMA, then it's up to the caller to set the DMA
1736          * mask, but PIO does not need the hw shim so we set a new
1737          * mask here in that case.
1738          */
1739         if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
1740                 host->dma_mask = DMA_BIT_MASK(64);
1741                 mmc_dev(host->mmc)->dma_mask = &host->dma_mask;
1742         }
1743
1744         host->max_clk =
1745                 (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
1746         host->max_clk *= 1000000;
1747         if (host->max_clk == 0) {
1748                 if (!host->ops->get_max_clock) {
1749                         printk(KERN_ERR
1750                                "%s: Hardware doesn't specify base clock "
1751                                "frequency.\n", mmc_hostname(mmc));
1752                         return -ENODEV;
1753                 }
1754                 host->max_clk = host->ops->get_max_clock(host);
1755         }
1756
1757         host->timeout_clk =
1758                 (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
1759         if (host->timeout_clk == 0) {
1760                 if (host->ops->get_timeout_clock) {
1761                         host->timeout_clk = host->ops->get_timeout_clock(host);
1762                 } else if (!(host->quirks &
1763                                 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
1764                         printk(KERN_ERR
1765                                "%s: Hardware doesn't specify timeout clock "
1766                                "frequency.\n", mmc_hostname(mmc));
1767                         return -ENODEV;
1768                 }
1769         }
1770         if (caps & SDHCI_TIMEOUT_CLK_UNIT)
1771                 host->timeout_clk *= 1000;
1772
1773         /*
1774          * Set host parameters.
1775          */
1776         mmc->ops = &sdhci_ops;
1777         if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK &&
1778                         host->ops->set_clock && host->ops->get_min_clock)
1779                 mmc->f_min = host->ops->get_min_clock(host);
1780         else
1781                 mmc->f_min = host->max_clk / 256;
1782         mmc->f_max = host->max_clk;
1783         mmc->caps = MMC_CAP_SDIO_IRQ;
1784
1785         if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
1786                 mmc->caps |= MMC_CAP_4_BIT_DATA;
1787
1788         if (caps & SDHCI_CAN_DO_HISPD)
1789                 mmc->caps |= MMC_CAP_SD_HIGHSPEED;
1790
1791         if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1792                 mmc->caps |= MMC_CAP_NEEDS_POLL;
1793
1794         mmc->ocr_avail = 0;
1795         if (caps & SDHCI_CAN_VDD_330)
1796                 mmc->ocr_avail |= MMC_VDD_32_33|MMC_VDD_33_34;
1797         if (caps & SDHCI_CAN_VDD_300)
1798                 mmc->ocr_avail |= MMC_VDD_29_30|MMC_VDD_30_31;
1799         if (caps & SDHCI_CAN_VDD_180)
1800                 mmc->ocr_avail |= MMC_VDD_165_195;
1801
1802         if (mmc->ocr_avail == 0) {
1803                 printk(KERN_ERR "%s: Hardware doesn't report any "
1804                         "support voltages.\n", mmc_hostname(mmc));
1805                 return -ENODEV;
1806         }
1807
1808         spin_lock_init(&host->lock);
1809
1810         /*
1811          * Maximum number of segments. Depends on if the hardware
1812          * can do scatter/gather or not.
1813          */
1814         if (host->flags & SDHCI_USE_ADMA)
1815                 mmc->max_hw_segs = 128;
1816         else if (host->flags & SDHCI_USE_SDMA)
1817                 mmc->max_hw_segs = 1;
1818         else /* PIO */
1819                 mmc->max_hw_segs = 128;
1820         mmc->max_phys_segs = 128;
1821
1822         /*
1823          * Maximum number of sectors in one transfer. Limited by DMA boundary
1824          * size (512KiB).
1825          */
1826         mmc->max_req_size = 524288;
1827
1828         /*
1829          * Maximum segment size. Could be one segment with the maximum number
1830          * of bytes. When doing hardware scatter/gather, each entry cannot
1831          * be larger than 64 KiB though.
1832          */
1833         if (host->flags & SDHCI_USE_ADMA)
1834                 mmc->max_seg_size = 65536;
1835         else
1836                 mmc->max_seg_size = mmc->max_req_size;
1837
1838         /*
1839          * Maximum block size. This varies from controller to controller and
1840          * is specified in the capabilities register.
1841          */
1842         if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
1843                 mmc->max_blk_size = 2;
1844         } else {
1845                 mmc->max_blk_size = (caps & SDHCI_MAX_BLOCK_MASK) >>
1846                                 SDHCI_MAX_BLOCK_SHIFT;
1847                 if (mmc->max_blk_size >= 3) {
1848                         printk(KERN_WARNING "%s: Invalid maximum block size, "
1849                                 "assuming 512 bytes\n", mmc_hostname(mmc));
1850                         mmc->max_blk_size = 0;
1851                 }
1852         }
1853
1854         mmc->max_blk_size = 512 << mmc->max_blk_size;
1855
1856         /*
1857          * Maximum block count.
1858          */
1859         mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
1860
1861         /*
1862          * Init tasklets.
1863          */
1864         tasklet_init(&host->card_tasklet,
1865                 sdhci_tasklet_card, (unsigned long)host);
1866         tasklet_init(&host->finish_tasklet,
1867                 sdhci_tasklet_finish, (unsigned long)host);
1868
1869         setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
1870
1871         ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
1872                 mmc_hostname(mmc), host);
1873         if (ret)
1874                 goto untasklet;
1875
1876         sdhci_init(host, 0);
1877
1878 #ifdef CONFIG_MMC_DEBUG
1879         sdhci_dumpregs(host);
1880 #endif
1881
1882 #ifdef SDHCI_USE_LEDS_CLASS
1883         snprintf(host->led_name, sizeof(host->led_name),
1884                 "%s::", mmc_hostname(mmc));
1885         host->led.name = host->led_name;
1886         host->led.brightness = LED_OFF;
1887         host->led.default_trigger = mmc_hostname(mmc);
1888         host->led.brightness_set = sdhci_led_control;
1889
1890         ret = led_classdev_register(mmc_dev(mmc), &host->led);
1891         if (ret)
1892                 goto reset;
1893 #endif
1894
1895         mmiowb();
1896
1897         mmc_add_host(mmc);
1898
1899         printk(KERN_INFO "%s: SDHCI controller on %s [%s] using %s\n",
1900                 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
1901                 (host->flags & SDHCI_USE_ADMA) ? "ADMA" :
1902                 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
1903
1904         sdhci_enable_card_detection(host);
1905
1906         return 0;
1907
1908 #ifdef SDHCI_USE_LEDS_CLASS
1909 reset:
1910         sdhci_reset(host, SDHCI_RESET_ALL);
1911         free_irq(host->irq, host);
1912 #endif
1913 untasklet:
1914         tasklet_kill(&host->card_tasklet);
1915         tasklet_kill(&host->finish_tasklet);
1916
1917         return ret;
1918 }
1919
1920 EXPORT_SYMBOL_GPL(sdhci_add_host);
1921
1922 void sdhci_remove_host(struct sdhci_host *host, int dead)
1923 {
1924         unsigned long flags;
1925
1926         if (dead) {
1927                 spin_lock_irqsave(&host->lock, flags);
1928
1929                 host->flags |= SDHCI_DEVICE_DEAD;
1930
1931                 if (host->mrq) {
1932                         printk(KERN_ERR "%s: Controller removed during "
1933                                 " transfer!\n", mmc_hostname(host->mmc));
1934
1935                         host->mrq->cmd->error = -ENOMEDIUM;
1936                         tasklet_schedule(&host->finish_tasklet);
1937                 }
1938
1939                 spin_unlock_irqrestore(&host->lock, flags);
1940         }
1941
1942         sdhci_disable_card_detection(host);
1943
1944         mmc_remove_host(host->mmc);
1945
1946 #ifdef SDHCI_USE_LEDS_CLASS
1947         led_classdev_unregister(&host->led);
1948 #endif
1949
1950         if (!dead)
1951                 sdhci_reset(host, SDHCI_RESET_ALL);
1952
1953         free_irq(host->irq, host);
1954
1955         del_timer_sync(&host->timer);
1956
1957         tasklet_kill(&host->card_tasklet);
1958         tasklet_kill(&host->finish_tasklet);
1959
1960         kfree(host->adma_desc);
1961         kfree(host->align_buffer);
1962
1963         host->adma_desc = NULL;
1964         host->align_buffer = NULL;
1965 }
1966
1967 EXPORT_SYMBOL_GPL(sdhci_remove_host);
1968
1969 void sdhci_free_host(struct sdhci_host *host)
1970 {
1971         mmc_free_host(host->mmc);
1972 }
1973
1974 EXPORT_SYMBOL_GPL(sdhci_free_host);
1975
1976 /*****************************************************************************\
1977  *                                                                           *
1978  * Driver init/exit                                                          *
1979  *                                                                           *
1980 \*****************************************************************************/
1981
1982 static int __init sdhci_drv_init(void)
1983 {
1984         printk(KERN_INFO DRIVER_NAME
1985                 ": Secure Digital Host Controller Interface driver\n");
1986         printk(KERN_INFO DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
1987
1988         return 0;
1989 }
1990
1991 static void __exit sdhci_drv_exit(void)
1992 {
1993 }
1994
1995 module_init(sdhci_drv_init);
1996 module_exit(sdhci_drv_exit);
1997
1998 module_param(debug_quirks, uint, 0444);
1999
2000 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
2001 MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
2002 MODULE_LICENSE("GPL");
2003
2004 MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");